STM32G431xx HAL User Manual: STM32G4xx HAL Drivers

STM32G431xx HAL User Manual
  • Main Page
  • Modules
  • Data Structures
  • Files
  • Directories
STM32G4xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32G431xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Exported Variables

  • Data Structures
  • Files
  • Directories
Variables
HAL Exported Variables
HAL | HAL Exported Functions

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
uint32_t | uwTickFreq = HAL_TICK_FREQ_DEFAULT
__IO uint32_t | uwTick
uint32_t | uwTickPrio
uint32_t | uwTickFreq

Variable Documentation

__IO uint32_t uwTick

Definition at line 85 of file stm32g4xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

__IO uint32_t uwTick

Definition at line 85 of file stm32g4xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT

Definition at line 87 of file stm32g4xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickFreq

Definition at line 87 of file stm32g4xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS)

Definition at line 86 of file stm32g4xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

uint32_t uwTickPrio

Definition at line 86 of file stm32g4xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

HAL Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Detailed Description

HAL Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the Flash interface the NVIC allocation and initial time base
          clock configuration.
      (+) De-Initialize common part of the HAL.
      (+) Configure the time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-initializes common part of the HAL and stops the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 192 of file stm32g4xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g4xx_hal_msp.c.

Note:
HAL_Init() function is called at the beginning of program after reset and before the clock configuration.
In the default implementation the System Timer (Systick) is used as source of time base. The Systick configuration is based on HSI clock, as HSI is the clock used after a system Reset and the NVIC configuration is set to Priority group 4. Once done, time base tick starts incrementing: the tick variable counter is incremented each 1ms in the SysTick_Handler() interrupt handler.
Return values:
HAL status

Definition at line 148 of file stm32g4xx_hal.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 255 of file stm32g4xx_hal.c.

References HAL_NVIC_SetPriority(), HAL_SYSTICK_Config(), uwTickFreq, and uwTickPrio.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 232 of file stm32g4xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initialize the MSP.

Return values:
None

Definition at line 221 of file stm32g4xx_hal.c.

Referenced by HAL_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Returns tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspends Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier

Function Documentation

void HAL_Delay ( uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 400 of file stm32g4xx_hal.c.

References HAL_GetTick(), and uwTickFreq.

Referenced by HAL_DACEx_SelfCalibrate(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 470 of file stm32g4xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 452 of file stm32g4xx_hal.c.

References __STM32G4xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 461 of file stm32g4xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 333 of file stm32g4xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), FLASH_WaitForLastOperation(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_Reset(), FMAC_WaitOnStartUntilTimeout(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_CORDIC_Calculate(), HAL_CORDIC_CalculateZO(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DMA_PollForTransfer(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_FMAC_PollFilterData(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_PCDEx_BCD_VBUSDetect(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SYSCFG_EnableVREFBUF(), HAL_TIMEx_ReArmBreakInput(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_IsErrorOccurred(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), RTC_EnterInitMode(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

uint32_t HAL_GetTickFreq ( void )

Returns tick frequency.

Return values:
Tick frequency. Value of HAL_TickFreqTypeDef.

Definition at line 384 of file stm32g4xx_hal.c.

References uwTickFreq.

uint32_t HAL_GetTickPrio ( void )

This function returns a tick priority.

Return values:
tick priority

Definition at line 342 of file stm32g4xx_hal.c.

References uwTickPrio.

uint32_t HAL_GetUIDw0 ( void )

Return the first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 479 of file stm32g4xx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Return the second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 488 of file stm32g4xx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Return the third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 497 of file stm32g4xx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in SysTick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 322 of file stm32g4xx_hal.c.

References uwTick, and uwTickFreq.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 442 of file stm32g4xx_hal.c.

HAL_StatusTypeDef HAL_SetTickFreq ( uint32_t Freq )

Set new tick Freq.

Return values:
status

Definition at line 351 of file stm32g4xx_hal.c.

References assert_param, HAL_InitTick(), IS_TICKFREQ, uwTickFreq, and uwTickPrio.

void HAL_SuspendTick ( void )

Suspends Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 426 of file stm32g4xx_hal.c.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Debug functions

Functions
HAL Debug functions
HAL Exported Functions

HAL Debug functions. More...

Functions

void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

HAL Debug functions.

 ===============================================================================
                      ##### HAL Debug functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 535 of file stm32g4xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 571 of file stm32g4xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP0/STOP1/STOP2 modes.

Return values:
None

Definition at line 553 of file stm32g4xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 526 of file stm32g4xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 562 of file stm32g4xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP0/STOP1/STOP2 modes.

Return values:
None

Definition at line 544 of file stm32g4xx_hal.c.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL SYSCFG configuration functions

Functions
HAL SYSCFG configuration functions
HAL Exported Functions

HAL SYSCFG configuration functions. More...

Functions

void | HAL_SYSCFG_CCMSRAMErase (void)
Start a hardware CCMSRAM erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOSwitchVDD (void)
Enable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_DisableIOSwitchVDD (void)
Disable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_CCMSRAM_WriteProtectionEnable (uint32_t Page)
CCMSRAM page write protection enable.

Detailed Description

HAL SYSCFG configuration functions.

 ===============================================================================
                      ##### HAL SYSCFG configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a hardware CCMSRAM erase operation
      (+) Enable/Disable the Internal FLASH Bank Swapping
      (+) Configure the Voltage reference buffer
      (+) Enable/Disable the Voltage reference buffer
      (+) Enable/Disable the I/O analog switch voltage booster

Function Documentation

void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable ( uint32_t Page )

CCMSRAM page write protection enable.

Parameters:
Page,: This parameter is a long 32bit value and can be a value of CCM Write protection
Note:
write protection can only be disabled by a system reset
Return values:
None

Definition at line 776 of file stm32g4xx_hal.c.

References assert_param, and IS_SYSCFG_CCMSRAMWRP_PAGE.

void HAL_SYSCFG_CCMSRAMErase ( void )

Start a hardware CCMSRAM erase operation.

Note:
As long as CCMSRAM is not erased the CCMER bit will be set. This bit is automatically reset at the end of the CCMSRAM erase operation.
Return values:
None

Definition at line 604 of file stm32g4xx_hal.c.

void HAL_SYSCFG_DisableIOSwitchBooster ( void )

Disable the I/O analog switch voltage booster.

Return values:
None

Definition at line 745 of file stm32g4xx_hal.c.

void HAL_SYSCFG_DisableIOSwitchVDD ( void )

Disable the I/O analog switch voltage by VDD.

Return values:
None

Definition at line 765 of file stm32g4xx_hal.c.

void HAL_SYSCFG_DisableMemorySwappingBank ( void )

Disable the Internal FLASH Bank Swapping.

Note:
This function can be used only for STM32G4xx devices.
The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000)
Return values:
None

Definition at line 638 of file stm32g4xx_hal.c.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 724 of file stm32g4xx_hal.c.

void HAL_SYSCFG_EnableIOSwitchBooster ( void )

Enable the I/O analog switch voltage booster.

Return values:
None

Definition at line 735 of file stm32g4xx_hal.c.

void HAL_SYSCFG_EnableIOSwitchVDD ( void )

Enable the I/O analog switch voltage by VDD.

Return values:
None

Definition at line 755 of file stm32g4xx_hal.c.

void HAL_SYSCFG_EnableMemorySwappingBank ( void )

Enable the Internal FLASH Bank Swapping.

Note:
This function can be used only for STM32G4xx devices.
Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
Return values:
None

Definition at line 623 of file stm32g4xx_hal.c.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 698 of file stm32g4xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode,: specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
Return values:
None

Definition at line 672 of file stm32g4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Parameters:
TrimmingValue specifies trimming code for VREFBUF calibration This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
Return values:
None

Definition at line 686 of file stm32g4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling,: specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V. This requires VDDA equal to or higher than 3.15 V.
Return values:
None

Definition at line 656 of file stm32g4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Tick Frequency

Defines
Tick Frequency
HAL Exported Constants

Defines

#define | HAL_TICK_FREQ_10HZ 100U
#define | HAL_TICK_FREQ_100HZ 10U
#define | HAL_TICK_FREQ_1KHZ 1U
#define | HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ

Define Documentation

#define HAL_TICK_FREQ_100HZ 10U

Definition at line 50 of file stm32g4xx_hal.h.

#define HAL_TICK_FREQ_10HZ 100U

Definition at line 49 of file stm32g4xx_hal.h.

#define HAL_TICK_FREQ_1KHZ 1U

Definition at line 51 of file stm32g4xx_hal.h.

#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ

Definition at line 52 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Boot Mode

Defines
Boot Mode
SYSCFG Exported Constants

Defines

#define | SYSCFG_BOOT_MAINFLASH 0x00000000U
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
#define | SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)

Define Documentation

#define SYSCFG_BOOT_MAINFLASH 0x00000000U

Definition at line 65 of file stm32g4xx_hal.h.

#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)

Definition at line 72 of file stm32g4xx_hal.h.

#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0

Definition at line 66 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FPU Interrupts

Defines
FPU Interrupts
SYSCFG Exported Constants

Defines

#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Define Documentation

#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1

Floating Point Unit Divide-by-zero Interrupt

Definition at line 86 of file stm32g4xx_hal.h.

#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4

Floating Point Unit Input denormal Interrupt

Definition at line 89 of file stm32g4xx_hal.h.

#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0

Floating Point Unit Invalid operation Interrupt

Definition at line 85 of file stm32g4xx_hal.h.

#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Floating Point Unit Inexact Interrupt

Definition at line 90 of file stm32g4xx_hal.h.

#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3

Floating Point Unit Overflow Interrupt

Definition at line 88 of file stm32g4xx_hal.h.

#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2

Floating Point Unit Underflow Interrupt

Definition at line 87 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CCM Write protection

Defines
CCM Write protection
SYSCFG Exported Constants

Defines

#define | SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31

Define Documentation

#define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0

CCMSRAM Write protection page 0

Definition at line 99 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1

CCMSRAM Write protection page 1

Definition at line 100 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10

CCMSRAM Write protection page 10

Definition at line 109 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11

CCMSRAM Write protection page 11

Definition at line 110 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12

CCMSRAM Write protection page 12

Definition at line 111 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13

CCMSRAM Write protection page 13

Definition at line 112 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14

CCMSRAM Write protection page 14

Definition at line 113 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15

CCMSRAM Write protection page 15

Definition at line 114 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16

CCMSRAM Write protection page 16

Definition at line 115 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17

CCMSRAM Write protection page 17

Definition at line 116 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18

CCMSRAM Write protection page 18

Definition at line 117 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19

CCMSRAM Write protection page 19

Definition at line 118 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2

CCMSRAM Write protection page 2

Definition at line 101 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20

CCMSRAM Write protection page 20

Definition at line 119 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21

CCMSRAM Write protection page 21

Definition at line 120 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22

CCMSRAM Write protection page 22

Definition at line 121 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23

CCMSRAM Write protection page 23

Definition at line 122 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24

CCMSRAM Write protection page 24

Definition at line 123 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25

CCMSRAM Write protection page 25

Definition at line 124 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26

CCMSRAM Write protection page 26

Definition at line 125 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27

CCMSRAM Write protection page 27

Definition at line 126 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28

CCMSRAM Write protection page 28

Definition at line 127 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29

CCMSRAM Write protection page 29

Definition at line 128 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3

CCMSRAM Write protection page 3

Definition at line 102 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30

CCMSRAM Write protection page 30

Definition at line 129 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31

CCMSRAM Write protection page 31

Definition at line 130 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4

CCMSRAM Write protection page 4

Definition at line 103 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5

CCMSRAM Write protection page 5

Definition at line 104 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6

CCMSRAM Write protection page 6

Definition at line 105 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7

CCMSRAM Write protection page 7

Definition at line 106 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8

CCMSRAM Write protection page 8

Definition at line 107 of file stm32g4xx_hal.h.

#define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9

CCMSRAM Write protection page 9

Definition at line 108 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1

Define Documentation

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U

Voltage reference scale 0 (VREFBUF_OUT = 2.048V)

Definition at line 140 of file stm32g4xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0

Voltage reference scale 1 (VREFBUF_OUT = 2.5V)

Definition at line 141 of file stm32g4xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1

Voltage reference scale 2 (VREFBUF_OUT = 2.9V)

Definition at line 142 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

Define Documentation

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 151 of file stm32g4xx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 152 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Flags

Defines
Flags
SYSCFG Exported Constants

Defines

#define | SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY

Define Documentation

#define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY

CCMSRAM busy by erase operation

Definition at line 164 of file stm32g4xx_hal.h.

#define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF

SRAM parity error (first 32kB of SRAM1 + CCM SRAM)

Definition at line 163 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
SYSCFG Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Define Documentation

#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Fast-mode Plus driving capability on a specific GPIO.

Enable Fast-mode Plus on PB6

Definition at line 176 of file stm32g4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast-mode Plus on PB7

Definition at line 177 of file stm32g4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast-mode Plus on PB8

Definition at line 179 of file stm32g4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast-mode Plus on PB9

Definition at line 182 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU Exported Macros

Defines
DBGMCU Exported Macros
HAL

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Define Documentation

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

Definition at line 251 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

Definition at line 256 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

Definition at line 261 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

Definition at line 246 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

Definition at line 266 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

Definition at line 236 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

Definition at line 276 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

Definition at line 286 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

Definition at line 291 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Definition at line 296 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 206 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

Definition at line 211 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

Definition at line 216 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

Definition at line 226 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

Definition at line 231 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

Definition at line 281 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

Definition at line 241 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

Definition at line 252 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

Definition at line 257 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

Definition at line 262 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

Definition at line 247 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM1 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

Definition at line 267 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

Definition at line 237 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

Definition at line 277 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM15 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

Definition at line 287 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM16 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

Definition at line 292 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM17 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Definition at line 297 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

Definition at line 207 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

Definition at line 212 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

Definition at line 217 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

Definition at line 227 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

Definition at line 232 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM8 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

Definition at line 282 of file stm32g4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

Definition at line 242 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG Exported Macros

Defines
SYSCFG Exported Macros
HAL

Defines

#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
CCMSRAM page write protection enable macro.
#define | __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__)
#define | __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK()
CCMSRAM page write protection unlock prior to erase.
#define | __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
CCMSRAM erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Define Documentation

#define __HAL_SYSCFG_BREAK_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)

SYSCFG Break ECC lock.

Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 393 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)

SYSCFG Break Cortex-M4 Lockup lock.

Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 399 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)

SYSCFG Break PVD lock.

Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 405 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)

SYSCFG Break SRAM parity lock.

Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked by system reset.

Definition at line 411 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_CCMSRAM_ERASE ( ) SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)

CCMSRAM erase.

Note:
__SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase

Definition at line 376 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE ( __CCMSRAMWRP__ )
Value:
do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
                                                                     SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
                                                                   }while(0)

Definition at line 362 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE

CCMSRAM page write protection enable macro.

Parameters:
__CCMSRAMWRP__,: This parameter can be a value of CCM Write protection
Note:
write protection can only be disabled by a system reset
Return values:
None

Definition at line 361 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK ( )
Value:
do {SYSCFG->SKR = 0xCA;\
                                                  SYSCFG->SKR = 0x53;\
                                                }while(0)

CCMSRAM page write protection unlock prior to erase.

Note:
Writing a wrong key reactivates the write protection

Definition at line 369 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_CLEAR_FLAG ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)

Set the SPF bit to clear the SRAM Parity Error Flag.

Definition at line 425 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0)

Definition at line 438 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0)

Fast-mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__,: This parameter can be a value of :
  • SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
  • SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
  • SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
  • SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

Definition at line 434 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                               }while(0)

Definition at line 385 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                               }while(0)

Floating Point Unit interrupt enable/disable macros.

Parameters:
__INTERRUPT__,: This parameter can be a value of FPU Interrupts

Definition at line 381 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_GET_BOOT_MODE ( ) READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

Return the boot mode as configured by user.

Return values:
The boot mode as configured by user. The returned value can be one of the following values:
  • SYSCFG_BOOT_MAINFLASH
  • SYSCFG_BOOT_SYSTEMFLASH
  • SYSCFG_BOOT_FMC (*)
  • SYSCFG_BOOT_QUADSPI (*)
  • SYSCFG_BOOT_SRAM
Note:
(*) availability depends on devices

Definition at line 353 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_GET_FLAG ( __FLAG__ )
Value:
((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
                                                & (__FLAG__))!= 0U) ? 1U : 0U)

Check SYSCFG flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
  • SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 420 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

Main Flash memory mapped at 0x00000000.

Definition at line 320 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))

Embedded SRAM mapped at 0x00000000.

Definition at line 328 of file stm32g4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)

System Flash memory mapped at 0x00000000.

Definition at line 324 of file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG Private Macros

Defines
SYSCFG Private Macros
HAL

Defines

#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)

Define Documentation

#define IS_SYSCFG_BREAK_CONFIG ( __CONFIG__ )
Value:
(((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
                                            ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY)    || \
                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))

Definition at line 458 of file stm32g4xx_hal.h.

#define IS_SYSCFG_CCMSRAMWRP_PAGE ( __PAGE__ ) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))

Definition at line 466 of file stm32g4xx_hal.h.

Referenced by HAL_SYSCFG_CCMSRAM_WriteProtectionEnable().

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 481 of file stm32g4xx_hal.h.

#define IS_SYSCFG_FPU_INTERRUPT ( __INTERRUPT__ )
Value:
((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

Definition at line 451 of file stm32g4xx_hal.h.

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 474 of file stm32g4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 477 of file stm32g4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))

Definition at line 470 of file stm32g4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Private Macros

Defines
HAL Private Macros
HAL

Defines

#define IS_TICKFREQ(FREQ)

Define Documentation

#define IS_TICKFREQ ( FREQ )
Value:
(((FREQ) == HAL_TICK_FREQ_10HZ)  || \
                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
                           ((FREQ) == HAL_TICK_FREQ_1KHZ))

Definition at line 504 of file stm32g4xx_hal.h.

Referenced by HAL_SetTickFreq().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL

Modules | Defines
HAL
STM32G4xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Variables
HAL Exported Functions
HAL Exported Constants
DBGMCU Exported Macros
SYSCFG Exported Macros
SYSCFG Private Macros
HAL Private Macros

Defines

#define | __STM32G4xx_HAL_VERSION_MAIN (0x01U)
STM32G4xx HAL Driver version number V1.2.2.
#define | __STM32G4xx_HAL_VERSION_SUB1 (0x02U)
#define | __STM32G4xx_HAL_VERSION_SUB2 (0x03U)
#define | __STM32G4xx_HAL_VERSION_RC (0x00U)
#define | __STM32G4xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | FB_MODE_BitNumber ((uint8_t)0x8)
#define | FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
#define | SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
#define | CCMER_BitNumber ((uint8_t)0x0)
#define | SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))

Detailed Description

HAL module driver.

Define Documentation

#define __STM32G4xx_HAL_VERSION
Value:
((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
                                         |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
                                         |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\
                                         |(__STM32G4xx_HAL_VERSION_RC))

Definition at line 57 of file stm32g4xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32G4xx_HAL_VERSION_MAIN (0x01U)

STM32G4xx HAL Driver version number V1.2.2.

[31:24] main version

Definition at line 53 of file stm32g4xx_hal.c.

#define __STM32G4xx_HAL_VERSION_RC (0x00U)

[7:0] release candidate

Definition at line 56 of file stm32g4xx_hal.c.

#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U)

[23:16] sub1 version

Definition at line 54 of file stm32g4xx_hal.c.

#define __STM32G4xx_HAL_VERSION_SUB2 (0x03U)

[15:8] sub2 version

Definition at line 55 of file stm32g4xx_hal.c.

#define CCMER_BitNumber ((uint8_t)0x0)

Definition at line 77 of file stm32g4xx_hal.c.

#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))

Definition at line 72 of file stm32g4xx_hal.c.

#define FB_MODE_BitNumber ((uint8_t)0x8)

Definition at line 71 of file stm32g4xx_hal.c.

#define MEMRMP_OFFSET SYSCFG_OFFSET

Definition at line 70 of file stm32g4xx_hal.c.

#define SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))

Definition at line 78 of file stm32g4xx_hal.c.

#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18)

Definition at line 76 of file stm32g4xx_hal.c.

#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)

Definition at line 67 of file stm32g4xx_hal.c.

#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */

Definition at line 63 of file stm32g4xx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

Define Documentation

#define ADC_CFGR_FIELDS_1
Value:
(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
                           ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                           ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
                           ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)

ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going

Definition at line 317 of file stm32g4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)

ADC conversion completion time-out value

Definition at line 338 of file stm32g4xx_hal_adc.c.

Referenced by ADC_ConversionStop().

#define ADC_DISABLE_TIMEOUT (2UL)

ADC disable time-out value

Definition at line 328 of file stm32g4xx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT (2UL)

ADC enable time-out value

Definition at line 327 of file stm32g4xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL)

ADC stop time-out value

Definition at line 1444 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

Definition at line 1449 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

ADC Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Detailed Description

ADC Initialization and Configuration functions.

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
For devices with several ADCs: reset of ADC common registers is done only if all ADCs sharing the same common group are disabled. (function "HAL_ADC_MspDeInit()" is also called under the same conditions: all ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances). If this is not the case, reset of these common parameters reset is bypassed without error reporting: it can be the intended behavior in case of reset of a single ADC while the other ADCs sharing the same common group is still running.
By default, HAL_ADC_DeInit() set ADC in mode deep power-down: this saves more power by reducing leakage currents and is particularly interesting before entering MCU low-power modes.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 713 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CFGR_FIELDS, ADC_CLEAR_COMMON_CONTROL_REGISTER, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_IT_RDY, ADC_REGULAR_INJECTED_GROUP, ADC_SMPR1_FIELDS, assert_param, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, __ADC_HandleTypeDef::MspDeInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (refer to description of RCC configuration for ADC in header of this file).
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters related to common ADC registers (ADC clock mode) are set only if all ADCs are disabled. If this is not the case, these common parameters setting are bypassed without error reporting: it can be the intended behaviour in case of update of a parameter of ADC_InitTypeDef on the fly, without disabling the other ADCs.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 396 of file stm32g4xx_hal_adc.c.

References __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CFGR_AUTOWAIT, ADC_CFGR_CONTINUOUS, ADC_CFGR_DFSDM, ADC_CFGR_DISCONTINUOUS_NUM, ADC_CFGR_DMACONTREQ, ADC_CFGR_FIELDS_1, ADC_CFGR_FIELDS_2, ADC_CFGR_REG_DISCONTINUOUS, ADC_CLEAR_ERRORCODE, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SOFTWARE_START, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, ADC_InitTypeDef::GainCompensation, HAL_ADC_ConvCpltCallback(), HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_GAIN_COMPENSATION, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGOVERSAMPLING_MODE, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLINGMODE, IS_ADC_SCAN_MODE, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_DELAY_INTERNAL_REGUL_STAB_US, LL_ADC_DisableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsDeepPowerDownEnabled(), LL_ADC_IsEnabled(), LL_ADC_IsInternalRegulatorEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCommonClock(), __ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoWait, __ADC_HandleTypeDef::MspInitCallback, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::OversamplingStopReset, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::SamplingMode, ADC_InitTypeDef::ScanConvMode, __ADC_HandleTypeDef::State, and ADC_OversamplingTypeDef::TriggeredMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc ADC handle
Note:
All ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances).
Return values:
None

Definition at line 929 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 912 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_RegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID,
 |  | pADC_CallbackTypeDef | pCallback
 | ) |  |

Register a User ADC Callback To be used instead of the weak predefined callback.

Parameters:
hadc | Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 963 of file stm32g4xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_UnRegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Parameters:
hadc Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 1088 of file stm32g4xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_ErrorCallback(), HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspDeInit(), HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MspInit(), HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Input and Output operation functions

Functions
ADC Input and Output operation functions
ADC Exported Functions

ADC IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (const ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
HAL_StatusTypeDef | HAL_ADC_StartSampling (ADC_HandleTypeDef *hadc)
Start ADC conversion sampling phase of regular group.
HAL_StatusTypeDef | HAL_ADC_StopSampling (ADC_HandleTypeDef *hadc)
Stop ADC conversion sampling phase of regular group and start conversion.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

ADC IO operation functions.

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2662 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2677 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Note:
In case of error due to overrun when using ADC with DMA transfer (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  • Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  • If needed, restart a new ADC conversion using function "HAL_ADC_Start_DMA()" (this function is also clearing overrun flag)
Parameters:
hadc ADC handle
Return values:
None

Definition at line 2714 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADC_GetValue ( const ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc ADC handle
Return values:
ADC group regular conversion data

Definition at line 2230 of file stm32g4xx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2290 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_GetMultiDMATransfer(), LL_ADC_GetMultimode(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2692 of file stm32g4xx_hal_adc.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function, with an exception: if low power feature "LowPowerAutoWait" is enabled, flags are not cleared to not interfere with this feature until data register is read using function HAL_ADC_GetValue().
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence (ADC init parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1408 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultiDMATransfer(), LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series)
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series)
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series)
  • ADC_OVR_EVENT ADC Overrun event
  • ADC_JQOVF_EVENT ADC Injected context queue overflow event
Timeout | Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1594 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_JQOVF_EVENT, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled (when multimode feature is available): if ADC is Slave, ADC is enabled but conversion is not started, if ADC is master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1219 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
Parameters:
hadc | ADC handle
pData | Destination Buffer address.
Length | Number of data to be transferred from ADC peripheral to memory
Return values:
HAL status.

Definition at line 2003 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IS_INDEPENDENT, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_IT() must be called for ADC Slave first, then for ADC Master. For ADC Slave, ADC is enabled only (conversion is not started). For ADC Master, ADC is enabled and multimode conversion is started.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() does not enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must: 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1743 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_MULTI_DUAL_INJ_ALTERN, LL_ADC_MULTI_DUAL_INJ_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_StartSampling ( ADC_HandleTypeDef * hadc )

Start ADC conversion sampling phase of regular group.

Note:
: This function should only be called to start sampling when
  • ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling mode has been selected
  • ADC_SOFTWARE_START has been selected as trigger source
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2251 of file stm32g4xx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1354 of file stm32g4xx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on ADC group injected. If ADC group injected is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2145 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_DMA_STATE_BUSY, __ADC_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1950 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_StopSampling ( ADC_HandleTypeDef * hadc )

Stop ADC conversion sampling phase of regular group and start conversion.

Note:
: This function should only be called to stop sampling when
  • ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling mode has been selected
  • ADC_SOFTWARE_START has been selected as trigger source
  • after sampling has been started using HAL_ADC_StartSampling.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2273 of file stm32g4xx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | const ADC_AnalogWDGConfTypeDef * | pAnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
On this STM32 series, analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc | ADC handle
pAnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2998 of file stm32g4xx_hal_adc.c.

References __LL_ADC_ANALOGWD_CHANNEL_GROUP, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_ALL_INJEC, ADC_ANALOGWATCHDOG_ALL_REG, ADC_ANALOGWATCHDOG_ALL_REGINJEC, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_AWD23THRESHOLD_SHIFT_RESOLUTION, ADC_GET_RESOLUTION, ADC_RESOLUTION_12B, assert_param, ADC_AnalogWDGConfTypeDef::Channel, ADC_AnalogWDGConfTypeDef::FilteringConfig, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, ADC_AnalogWDGConfTypeDef::HighThreshold, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ, LL_ADC_AWD_ALL_CHANNELS_REG, LL_ADC_AWD_ALL_CHANNELS_REG_INJ, LL_ADC_AWD_DISABLE, LL_ADC_ClearFlag_AWD1(), LL_ADC_ClearFlag_AWD2(), LL_ADC_ClearFlag_AWD3(), LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_DisableIT_AWD1(), LL_ADC_DisableIT_AWD2(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD1(), LL_ADC_EnableIT_AWD2(), LL_ADC_EnableIT_AWD3(), LL_ADC_GROUP_INJECTED, LL_ADC_GROUP_REGULAR, LL_ADC_GROUP_REGULAR_INJECTED, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetAnalogWDMonitChannels(), ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_InitTypeDef::OversamplingMode, __ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | const ADC_ChannelConfTypeDef * | pConfig
 | ) |  |

Configure a channel to be assigned to ADC group regular.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into ADC group regular, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
pConfig | Structure of ADC channel assigned to ADC group regular.
Return values:
HAL status

Definition at line 2760 of file stm32g4xx_hal_adc.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CHANNEL_TEMPSENSOR_ADC1, ADC_CHANNEL_TEMPSENSOR_ADC5, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_GET_RESOLUTION, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_SAMPLETIME_3CYCLES_5, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_OFFSET_NUMBER, IS_ADC_OFFSET_SIGN, IS_ADC_RANGE, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_GetOffsetChannel(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_1, LL_ADC_OFFSET_2, LL_ADC_OFFSET_3, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE, LL_ADC_OFFSET_SATURATION_DISABLE, LL_ADC_OFFSET_SATURATION_ENABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SAMPLINGTIME_2CYCLES_5, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT, LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetOffset(), LL_ADC_SetOffsetSaturation(), LL_ADC_SetOffsetSign(), LL_ADC_SetOffsetState(), LL_ADC_SetSamplingTimeCommonConfig(), ADC_ChannelConfTypeDef::Offset, ADC_ChannelConfTypeDef::OffsetNumber, ADC_ChannelConfTypeDef::OffsetSaturation, ADC_ChannelConfTypeDef::OffsetSign, ADC_InitTypeDef::OversamplingMode, ADC_ChannelConfTypeDef::Rank, ADC_ChannelConfTypeDef::SamplingTime, ADC_ChannelConfTypeDef::SingleDiff, and __ADC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (const ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (const ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( const ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc ADC handle
Return values:
ADC error code (bitfield on 32 bits)

Definition at line 3273 of file stm32g4xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, and __ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( const ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Note:
ADC state machine is managed by bitfields, ADC status must be compared with states bits. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
Parameters:
hadc ADC handle
Return values:
ADC handle state (bitfield on 32 bits)

Definition at line 3259 of file stm32g4xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | ConversionGroup
 | ) |  |

Stop ADC conversion.

Parameters:
hadc ADC handle
ConversionGroup ADC group regular and/or injected. This parameter can be one of the following values:
  • ADC_REGULAR_GROUP ADC regular conversion type.
  • ADC_INJECTED_GROUP ADC injected conversion type.
  • ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
Return values:
HAL status.

Definition at line 3303 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_CONVERSION_TIME_MAX_CPU_CYCLES, ADC_FLAG_JEOS, ADC_INJECTED_GROUP, ADC_REGULAR_GROUP, ADC_REGULAR_INJECTED_GROUP, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CONVERSION_GROUP, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StopConversion(), LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StopConversion(), ADC_InitTypeDef::LowPowerAutoWait, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 3528 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_DISABLE_TIMEOUT, ADC_FLAG_EOSMP, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3590 of file stm32g4xx_hal_adc.c.

References ADC_FLAG_EOS, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCallback, HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsTriggerSourceSWStart(), __ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3686 of file stm32g4xx_hal_adc.c.

References __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3668 of file stm32g4xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvHalfCpltCallback, and HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 3435 of file stm32g4xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, ADC_ENABLE_TIMEOUT, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_Enable(), LL_ADC_GetCommonPathInternalCh(), LL_ADC_IsEnabled(), LL_ADC_PATH_INTERNAL_TEMPSENSOR, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Define Documentation

#define HAL_ADC_STATE_AWD1 (0x00010000UL)

Out-of-window occurrence of ADC analog watchdog 1

Definition at line 471 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 (0x00020000UL)

Out-of-window occurrence of ADC analog watchdog 2

Definition at line 472 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 (0x00040000UL)

Out-of-window occurrence of ADC analog watchdog 3

Definition at line 473 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)

ADC is busy due to an internal process (initialization, calibration, ...)

Definition at line 443 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)

Configuration error occurrence

Definition at line 449 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL)

DMA error occurrence

Definition at line 450 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)

Internal error occurrence

Definition at line 448 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL)

A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 463 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_INJ_EOC (0x00002000UL)

Conversion data available on group injected

Definition at line 467 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)

Injected queue overflow occurrence

Definition at line 468 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADCEx_EnableInjectedQueue().

#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 476 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_READY (0x00000001UL)

ADC peripheral ready for use

Definition at line 442 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_BUSY (0x00000100UL)

A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 453 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_EOC (0x00000200UL)

Conversion data available on group regular

Definition at line 457 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL)

Not available on this STM32 series: End Of Sampling flag raised

Definition at line 459 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR (0x00000400UL)

Overrun occurrence

Definition at line 458 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET (0x00000000UL)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " ADC not yet initialized or disabled

Definition at line 441 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_STATE_TIMEOUT (0x00000004UL)

TimeOut occurrence

Definition at line 445 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Types

Data Structures | Modules | Typedefs | Enumerations
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Modules

ADC States

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __ADC_HandleTypeDef ADC_HandleTypeDef

ADC handle Structure definition.

typedef void(* pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc)

HAL ADC Callback pointer definition.

pointer to a ADC callback function

Definition at line 541 of file stm32g4xx_hal_adc.h.

Enumeration Type Documentation

enum HAL_ADC_CallbackIDTypeDef

HAL ADC Callback ID enumeration definition.

Enumerator:
HAL_ADC_CONVERSION_COMPLETE_CB_ID

ADC conversion complete callback ID

HAL_ADC_CONVERSION_HALF_CB_ID

ADC conversion DMA half-transfer callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID

ADC analog watchdog 1 callback ID

HAL_ADC_ERROR_CB_ID

ADC error callback ID

HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID

ADC group injected conversion complete callback ID

HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID

ADC group injected context queue overflow callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID

ADC analog watchdog 2 callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID

ADC analog watchdog 3 callback ID

HAL_ADC_END_OF_SAMPLING_CB_ID

ADC end of sampling callback ID

HAL_ADC_MSPINIT_CB_ID

ADC Msp Init callback ID

HAL_ADC_MSPDEINIT_CB_ID

ADC Msp DeInit callback ID

Definition at line 523 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC group regular oversampling structure definition. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode
uint32_t | OversamplingStopReset

Detailed Description

ADC group regular oversampling structure definition.

Definition at line 49 of file stm32g4xx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::OversamplingStopReset

Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of Oversampling - Oversampling scope for ADC group regular

Definition at line 60 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of Oversampling - Ratio

Definition at line 51 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 54 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of Oversampling - Discontinuous mode

Definition at line 57 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC instance and ADC group regular. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | GainCompensation
uint32_t | ScanConvMode
uint32_t | EOCSelection
FunctionalState | LowPowerAutoWait
FunctionalState | ContinuousConvMode
uint32_t | NbrOfConversion
FunctionalState | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | SamplingMode
FunctionalState | DMAContinuousRequests
uint32_t | Overrun
FunctionalState | OversamplingMode
ADC_OversamplingTypeDef Oversampling

Detailed Description

Structure definition of ADC instance and ADC group regular.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode.
The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
  • For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 90 of file stm32g4xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of ADC common - Clock source. Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled.

Definition at line 92 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::ContinuousConvMode

Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 166 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_Init(), HAL_ADC_PollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::DataAlign

Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of ADC conversion data alignment

Definition at line 112 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::DiscontinuousConvMode

Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one.

Definition at line 189 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InitTypeDef::DMAContinuousRequests

Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.

Definition at line 219 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADCEx_MultiModeConfigChannel(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::EOCSelection

Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of ADC sequencer end of unitary conversion or sequence conversions.

Definition at line 140 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group regular trigger source. Caution: external trigger source is common to all ADC instances.

Definition at line 205 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Select the external event edge used to trigger ADC group regular conversion start If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC group regular trigger edge (when external trigger is selected)

Definition at line 212 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::GainCompensation

Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: DATA = DATA(raw) * (gain compensation coef) / 4096 "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa Gain step is 1/4096 = 0.000244 Gain range is 0.0000 to 3.999756 This parameter value can be 0 Gain compensation will be disabled and coefficient set to 0 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value Note: Gain compensation when enabled is applied to all channels.

Definition at line 116 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoWait

Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).

Definition at line 144 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specify the number of ranks that will be converted within the regular group sequencer. This parameter is dependent on ScanConvMode:

  • sequencer configured to fully configurable: Number of ranks in the scan sequence is configurable using this parameter. Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
  • sequencer configured to not fully configurable: Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 171 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 200 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of ADC group regular - Overrun behavior on conversion data. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear) Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 227 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled.

Definition at line 248 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::OversamplingMode

Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected

Definition at line 243 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configure the ADC resolution. This parameter can be a value of ADC instance - Resolution

Definition at line 109 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::SamplingMode

Select the sampling mode to be used for ADC group regular conversion. This parameter can be a value of ADC group regular sampling mode

Definition at line 216 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of ADC sequencer scan mode

Definition at line 128 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | SingleDiff
uint32_t | OffsetNumber
uint32_t | Offset
uint32_t | OffsetSign
FunctionalState | OffsetSaturation

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  • For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  • For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 267 of file stm32g4xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specify the channel to configure into ADC regular group. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 269 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Define the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 317 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetNumber

Select the offset number This parameter can be a value of ADC instance - Offset number Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 312 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

FunctionalState ADC_ChannelConfTypeDef::OffsetSaturation

Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 332 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetSign

Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of ADC Extended Offset Sign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 326 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specify the rank in the regular group sequencer. This parameter can be a value of ADC group regular - Sequencer ranks Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 275 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values.

Definition at line 281 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SingleDiff

Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically This parameter must be a value of Channel - Single or differential ending Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 294 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
FunctionalState | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold
uint32_t | FilteringConfig

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either:
  • For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
  • For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups.

Definition at line 349 of file stm32g4xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC instance - Channel number.

Definition at line 370 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::FilteringConfig

Specify whether filtering should be use and the number of samples to consider. Before setting flag or raising interrupt, analog watchdog can wait to have several consecutive out-of-window samples. This parameter allows to configure this number. This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. This parameter can be a value of ADC analog watchdog (AWD) filtering configuration.

Definition at line 407 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 383 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

FunctionalState ADC_AnalogWDGConfTypeDef::ITMode

Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 380 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 395 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. This parameter can be a value of ADC analog watchdog (AWD) mode.

Definition at line 358 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of Analog watchdog - ADC analog watchdog (AWD) number.

Definition at line 351 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_InjectionConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfigTypeDef Struct Reference
ADC Exported Types

ADC group injected contexts queue configuration. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

uint32_t | ContextQueue
uint32_t | ChannelCount

Detailed Description

ADC group injected contexts queue configuration.

Note:
Structure intended to be used only through structure "ADC_HandleTypeDef"

Definition at line 419 of file stm32g4xx_hal_adc.h.

Field Documentation

uint32_t ADC_InjectionConfigTypeDef::ChannelCount

Number of channels in the injected sequence

Definition at line 425 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfigTypeDef::ContextQueue

Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call

Definition at line 421 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32g4xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
ADC_InjectionConfigTypeDef InjectionConfig
void(* | ConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ConvHalfCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ErrorCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedQueueOverflowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow2Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow3Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | EndOfSamplingCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspInitCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspDeInitCallback )(struct __ADC_HandleTypeDef *hadc)

Detailed Description

ADC handle Structure definition.

Definition at line 487 of file stm32g4xx_hal_adc.h.

Field Documentation

void(* __ADC_HandleTypeDef::ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion complete callback

Definition at line 502 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion DMA half-transfer callback

Definition at line 503 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

DMA_HandleTypeDef* __ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 495 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

void(* __ADC_HandleTypeDef::EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc)

ADC end of sampling callback

Definition at line 513 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ErrorCallback)(struct __ADC_HandleTypeDef *hadc)

ADC error callback

Definition at line 506 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 498 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

ADC_InitTypeDef __ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 493 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), and HAL_ADCEx_MultiModeStart_DMA().

void(* __ADC_HandleTypeDef::InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected conversion complete callback

Definition at line 507 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected context queue overflow callback

Definition at line 509 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

ADC_InjectionConfigTypeDef __ADC_HandleTypeDef::InjectionConfig

ADC injected channel configuration build-up structure

Definition at line 499 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

ADC_TypeDef* __ADC_HandleTypeDef::Instance

Register base address

Definition at line 492 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_StartSampling(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_StopSampling(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void(* __ADC_HandleTypeDef::LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 2 callback

Definition at line 511 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 3 callback

Definition at line 512 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 1 callback

Definition at line 505 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

HAL_LockTypeDef __ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 496 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

void(* __ADC_HandleTypeDef::MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp DeInit callback

Definition at line 515 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::MspInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp Init callback

Definition at line 514 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 497 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Define Documentation

#define HAL_ADC_ERROR_DMA (0x04U)

DMA transfer error

Definition at line 563 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL (0x01U)

ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...)

Definition at line 560 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_Calibration_SetValue().

#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Invalid Callback error

Definition at line 566 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_ERROR_JQOVF (0x08U)

Injected context queue overflow error

Definition at line 564 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_ERROR_NONE (0x00U)

No error

Definition at line 559 of file stm32g4xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR (0x02U)

Overrun error

Definition at line 562 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)

ADC asynchronous clock without prescaler

Definition at line 582 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)

ADC asynchronous clock with prescaler division by 10

Definition at line 592 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)

ADC asynchronous clock with prescaler division by 12

Definition at line 594 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)

ADC asynchronous clock with prescaler division by 128

Definition at line 602 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)

ADC asynchronous clock with prescaler division by 16

Definition at line 596 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)

ADC asynchronous clock with prescaler division by 2

Definition at line 584 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

ADC asynchronous clock with prescaler division by 256

Definition at line 604 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)

ADC asynchronous clock with prescaler division by 32

Definition at line 598 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)

ADC asynchronous clock with prescaler division by 4

Definition at line 586 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)

ADC asynchronous clock with prescaler division by 6

Definition at line 588 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)

ADC asynchronous clock with prescaler division by 64

Definition at line 600 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)

ADC asynchronous clock with prescaler division by 8

Definition at line 590 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)

ADC synchronous clock from AHB clock without prescaler

Definition at line 576 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)

ADC synchronous clock from AHB clock with prescaler division by 2

Definition at line 578 of file stm32g4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)

ADC synchronous clock from AHB clock with prescaler division by 4

Definition at line 580 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

Define Documentation

#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)

ADC resolution 10 bits

Definition at line 614 of file stm32g4xx_hal_adc.h.

#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)

ADC resolution 12 bits

Definition at line 613 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

ADC resolution 6 bits

Definition at line 616 of file stm32g4xx_hal_adc.h.

#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)

ADC resolution 8 bits

Definition at line 615 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC conversion data alignment

Defines
ADC conversion data alignment
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

Define Documentation

#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)

Definition at line 626 of file stm32g4xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 624 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC sequencer scan mode

Defines
ADC sequencer scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)

Define Documentation

#define ADC_SCAN_DISABLE (0x00000000UL)

Scan mode disabled

Definition at line 635 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE (0x00000001UL)

Scan mode enabled

Definition at line 636 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular trigger source

Defines
ADC group regular trigger source
ADC Exported Constants

Defines

#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1)
#define | ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)
#define | ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)
#define | ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1)
#define | ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2)
#define | ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3)
#define | ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)
#define | ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)
#define | ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)
#define | ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)
#define | ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)
#define | ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)
#define | ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

ADC group regular conversion trigger from external peripheral: external interrupt line 11.

Definition at line 721 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)

ADC group regular conversion trigger from external peripheral: external interrupt line 2.

Definition at line 719 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event.

Definition at line 699 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event.

Definition at line 717 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event.

Definition at line 701 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event.

Definition at line 703 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event.

Definition at line 705 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event.

Definition at line 707 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event.

Definition at line 709 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event.

Definition at line 711 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event.

Definition at line 713 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event.

Definition at line 715 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)

ADC group regular conversion trigger from external peripheral: LPTIMER OUT event.

Definition at line 723 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO.

Definition at line 687 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare).

Definition at line 651 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare).

Definition at line 653 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare).

Definition at line 655 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO.

Definition at line 647 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2.

Definition at line 649 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1)

ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare).

Definition at line 693 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2)

ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare).

Definition at line 695 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3)

ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare).

Definition at line 697 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)

ADC group regular conversion trigger from external peripheral: TIM20 TRGO.

Definition at line 689 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM20 TRGO2.

Definition at line 691 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1)

ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare).

Definition at line 659 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare).

Definition at line 661 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3)

ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare).

Definition at line 663 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO.

Definition at line 657 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1)

ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare).

Definition at line 667 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)

ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare).

Definition at line 669 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO.

Definition at line 665 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1)

ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare).

Definition at line 673 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)

ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare).

Definition at line 675 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO.

Definition at line 671 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO.

Definition at line 677 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)

ADC group regular conversion trigger from external peripheral: TIM7 TRGO.

Definition at line 679 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1)

ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare).

Definition at line 685 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO.

Definition at line 681 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO2.

Definition at line 683 of file stm32g4xx_hal_adc.h.

#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)

ADC group regular conversion trigger software start

Definition at line 645 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular trigger edge (when external trigger is selected)

Defines
ADC group regular trigger edge (when external trigger is selected)
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)

ADC group regular conversion trigger polarity set to falling edge

Definition at line 736 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)

ADC group regular trigger disabled (SW start)

Definition at line 732 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 734 of file stm32g4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 738 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular sampling mode

Defines
ADC group regular sampling mode
ADC Exported Constants

Defines

#define | ADC_SAMPLING_MODE_NORMAL (0x00000000UL)
#define | ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)
#define | ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)

Define Documentation

#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)

ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see Channel - Sampling time)

Definition at line 749 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL)

ADC conversions sampling phase duration is defined using Channel - Sampling time

Definition at line 747 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)

ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion

Definition at line 753 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC sequencer end of unitary conversion or sequence conversions

Defines
ADC sequencer end of unitary conversion or sequence conversions
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

Define Documentation

#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

End of sequence conversions flag

Definition at line 765 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)

End of unitary conversion flag

Definition at line 764 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 775 of file stm32g4xx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)

ADC group regular behavior in case of overrun: data preserved

Definition at line 773 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

Define Documentation

#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)

ADC group regular sequencer rank 1

Definition at line 784 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)

ADC group regular sequencer rank 10

Definition at line 793 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)

ADC group regular sequencer rank 11

Definition at line 794 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)

ADC group regular sequencer rank 12

Definition at line 795 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)

ADC group regular sequencer rank 13

Definition at line 796 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)

ADC group regular sequencer rank 14

Definition at line 797 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)

ADC group regular sequencer rank 15

Definition at line 798 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

ADC group regular sequencer rank 16

Definition at line 799 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)

ADC group regular sequencer rank 2

Definition at line 785 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)

ADC group regular sequencer rank 3

Definition at line 786 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)

ADC group regular sequencer rank 4

Definition at line 787 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)

ADC group regular sequencer rank 5

Definition at line 788 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)

ADC group regular sequencer rank 6

Definition at line 789 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)

ADC group regular sequencer rank 7

Definition at line 790 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)

ADC group regular sequencer rank 8

Definition at line 791 of file stm32g4xx_hal_adc.h.

#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)

ADC group regular sequencer rank 9

Definition at line 792 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)
#define | ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)
#define | ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)
#define | ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)
#define | ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)
#define | ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5)

Define Documentation

#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)

Sampling time 12.5 ADC clock cycles

Definition at line 809 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)

Sampling time 247.5 ADC clock cycles

Definition at line 813 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)

Sampling time 24.5 ADC clock cycles

Definition at line 810 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)

Sampling time 2.5 ADC clock cycles

Definition at line 807 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5)

Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously.

Definition at line 815 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)

Sampling time 47.5 ADC clock cycles

Definition at line 811 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)

Sampling time 640.5 ADC clock cycles

Definition at line 814 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)

Sampling time 6.5 ADC clock cycles

Definition at line 808 of file stm32g4xx_hal_adc.h.

#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)

Sampling time 92.5 ADC clock cycles

Definition at line 812 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1)
#define | ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1)
#define | ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2)
#define | ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2)
#define | ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3)
#define | ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4)
#define | ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5)
#define | ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6)

Define Documentation

#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)

External channel (GPIO pin) ADCx_IN0

Definition at line 827 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)

External channel (GPIO pin) ADCx_IN1

Definition at line 828 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)

External channel (GPIO pin) ADCx_IN10

Definition at line 837 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)

External channel (GPIO pin) ADCx_IN11

Definition at line 838 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)

External channel (GPIO pin) ADCx_IN12

Definition at line 839 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)

External channel (GPIO pin) ADCx_IN13

Definition at line 840 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)

External channel (GPIO pin) ADCx_IN14

Definition at line 841 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)

External channel (GPIO pin) ADCx_IN15

Definition at line 842 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)

External channel (GPIO pin) ADCx_IN16

Definition at line 843 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)

External channel (GPIO pin) ADCx_IN17

Definition at line 844 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)

External channel (GPIO pin) ADCx_IN18

Definition at line 845 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)

External channel (GPIO pin) ADCx_IN2

Definition at line 829 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)

External channel (GPIO pin) ADCx_IN3

Definition at line 830 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)

External channel (GPIO pin) ADCx_IN4

Definition at line 831 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)

External channel (GPIO pin) ADCx_IN5

Definition at line 832 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)

External channel (GPIO pin) ADCx_IN6

Definition at line 833 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)

External channel (GPIO pin) ADCx_IN7

Definition at line 834 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)

External channel (GPIO pin) ADCx_IN8

Definition at line 835 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)

External channel (GPIO pin) ADCx_IN9

Definition at line 836 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1)

Internal channel Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance.

Definition at line 849 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5)

Internal channel Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility

Definition at line 851 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

Internal channel Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda. On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility

Definition at line 854 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1)

Internal channel OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance.

Definition at line 859 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2)

Internal channel OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance.

Definition at line 861 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2)

Internal channel OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance.

Definition at line 863 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3)

Internal channel OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability

Definition at line 865 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4)

Internal channel OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability

Definition at line 868 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5)

Internal channel OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability

Definition at line 871 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6)

Internal channel OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability

Definition at line 874 of file stm32g4xx_hal_adc.h.

#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)

Internal channel VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2.

Definition at line 846 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog watchdog - ADC analog watchdog (AWD) number

Defines
Analog watchdog - ADC analog watchdog (AWD) number
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)

ADC analog watchdog number 1

Definition at line 884 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)

ADC analog watchdog number 2

Definition at line 885 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

ADC analog watchdog number 3

Definition at line 886 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC analog watchdog (AWD) filtering configuration

Defines
ADC analog watchdog (AWD) filtering configuration
ADC Exported Constants

Defines

#define | ADC_AWD_FILTERING_NONE (0x00000000UL)
#define | ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1))
#define | ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2))
#define | ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1))
#define | ADC_AWD_FILTERING_8SAMPLES

Define Documentation

#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0))

ADC AWD 2 consecutives out-of-window samples to raise flag or interrupt

Definition at line 896 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1))

ADC AWD 3 consecutives out-of-window samples to raise flag or interrupt

Definition at line 898 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0))

ADC AWD 4 consecutives out-of-window samples to raise flag or interrupt

Definition at line 900 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2))

ADC AWD 5 consecutives out-of-window samples to raise flag or interrupt

Definition at line 902 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0))

ADC AWD 6 consecutives out-of-window samples to raise flag or interrupt

Definition at line 904 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1))

ADC AWD 7 consecutives out-of-window samples to raise flag or interrupt

Definition at line 906 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_8SAMPLES
Value:
((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
                                          | ADC_TR1_AWDFILT_0))

ADC AWD 8 consecutives out-of-window samples to raise flag or interrupt

Definition at line 908 of file stm32g4xx_hal_adc.h.

#define ADC_AWD_FILTERING_NONE (0x00000000UL)

ADC AWD no filtering, one out-of-window sample to raise flag or interrupt

Definition at line 894 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC analog watchdog (AWD) mode

Defines
ADC analog watchdog (AWD) mode
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)

ADC AWD applied to injected group all channels

Definition at line 928 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)

ADC AWD applied to regular group all channels

Definition at line 926 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

ADC AWD applied to regular and injected groups all channels

Definition at line 930 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL)

ADC AWD not selected

Definition at line 918 of file stm32g4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)

ADC AWD applied to an injected group single channel

Definition at line 921 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)

ADC AWD applied to a regular group single channel

Definition at line 919 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
Value:
(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
                                                 | ADC_CFGR_JAWD1EN)

ADC AWD applied to a regular and injected groups single channel

Definition at line 923 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

Define Documentation

#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)

ADC oversampling ratio 128

Definition at line 949 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)

ADC oversampling ratio 16

Definition at line 946 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
Note:
The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) ADC oversampling ratio 2

Definition at line 943 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

ADC oversampling ratio 256

Definition at line 950 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)

ADC oversampling ratio 32

Definition at line 947 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)

ADC oversampling ratio 4

Definition at line 944 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)

ADC oversampling ratio 64

Definition at line 948 of file stm32g4xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)

ADC oversampling ratio 8

Definition at line 945 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

Define Documentation

#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)

ADC oversampling right shift of 1 ranks

Definition at line 963 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)

ADC oversampling right shift of 2 ranks

Definition at line 964 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)

ADC oversampling right shift of 3 ranks

Definition at line 965 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)

ADC oversampling right shift of 4 ranks

Definition at line 966 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)

ADC oversampling right shift of 5 ranks

Definition at line 967 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)

ADC oversampling right shift of 6 ranks

Definition at line 968 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)

ADC oversampling right shift of 7 ranks

Definition at line 969 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

ADC oversampling right shift of 8 ranks

Definition at line 970 of file stm32g4xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
Note:
The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling conversion data) ADC oversampling no shift

Definition at line 962 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of OVS ratio needs a trigger)

Definition at line 980 of file stm32g4xx_hal_adc.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)

ADC oversampling discontinuous mode: continuous mode (all conversions of OVS ratio are done from 1 trigger)

Definition at line 978 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Oversampling scope for ADC group regular

Defines
Oversampling - Oversampling scope for ADC group regular
ADC Exported Constants

Defines

#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Define Documentation

#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)

Oversampling buffer maintained during injection sequence

Definition at line 989 of file stm32g4xx_hal_adc.h.

#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Oversampling buffer zeroed during injection sequence

Definition at line 991 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Event type

Defines
ADC Event type
ADC Exported Constants

Defines

#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

Define Documentation

#define ADC_AWD1_EVENT (ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog)

Definition at line 1005 of file stm32g4xx_hal_adc.h.

#define ADC_AWD2_EVENT (ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog)

Definition at line 1006 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT (ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog)

Definition at line 1007 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
Note:
Analog watchdog 1 is available on all stm32 series Analog watchdog 2 and 3 are not available on all series ADC End of Sampling event

Definition at line 1004 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

ADC Injected Context Queue Overflow event

Definition at line 1009 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT (ADC_FLAG_OVR)

ADC overrun event

Definition at line 1008 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC interrupts definition

Defines
ADC interrupts definition
ADC Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE

Define Documentation

#define ADC_IT_AWD1 ADC_IER_AWD1IE

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 1026 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2IE

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 1027 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3IE

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 1029 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOCIE

ADC End of regular conversion interrupt source

Definition at line 1021 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOS ADC_IER_EOSIE

ADC End of regular sequence of conversions interrupt source

Definition at line 1022 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC End of sampling interrupt source

Definition at line 1020 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_JEOC ADC_IER_JEOCIE

ADC End of injected conversion interrupt source

Definition at line 1024 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JEOS ADC_IER_JEOSIE

ADC End of injected sequence of conversions interrupt source

Definition at line 1025 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC Injected Context Queue Overflow interrupt source

Definition at line 1031 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVRIE

ADC overrun interrupt source

Definition at line 1023 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_RDY ADC_IER_ADRDYIE

ADC Ready interrupt source

Definition at line 1019 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC flags definition

Defines
ADC flags definition
ADC Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF

Define Documentation

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag (main analog watchdog)

Definition at line 1047 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag (additional analog watchdog)

Definition at line 1048 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag (additional analog watchdog)

Definition at line 1049 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 1042 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 1043 of file stm32g4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 1041 of file stm32g4xx_hal_adc.h.

Referenced by ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_JEOC ADC_ISR_JEOC

ADC End of Injected Conversion flag

Definition at line 1045 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JEOS ADC_ISR_JEOS

ADC End of Injected sequence of Conversions flag

Definition at line 1046 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC Injected Context Queue Overflow flag

Definition at line 1050 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 1044 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_RDY ADC_ISR_ADRDY

ADC Ready flag

Definition at line 1040 of file stm32g4xx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), and HAL_ADC_DeInit().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Constants

Modules | Defines
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC common - Clock source
ADC instance - Resolution
ADC conversion data alignment
ADC sequencer scan mode
ADC group regular trigger source
ADC group regular trigger edge (when external trigger is selected)
ADC group regular sampling mode
ADC sequencer end of unitary conversion or sequence conversions
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer ranks
Channel - Sampling time
ADC instance - Channel number
Analog watchdog - ADC analog watchdog (AWD) number
ADC analog watchdog (AWD) filtering configuration
ADC analog watchdog (AWD) mode
Oversampling - Ratio
Oversampling - Data shift
Oversampling - Discontinuous mode
Oversampling - Oversampling scope for ADC group regular
ADC Event type
ADC interrupts definition
ADC flags definition

Defines

#define ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 1013 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
Verify the ADC gain compensation.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 1081 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR register RES[1:0] field.

Parameters:
__HANDLE__ ADC handle
Return values:
Value of bitfield RES in CFGR register.

Definition at line 1073 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note:
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 1090 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__ )
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )

Verify the ADC clock setting.

Parameters:
__ADC_CLOCK__ programmed ADC clock.
Return values:
SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)

Definition at line 1124 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( __ALIGN__ )
Value:
(((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )

Verify the ADC converted data alignment.

Parameters:
__ALIGN__ programmed ADC converted data alignment.
Return values:
SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)

Definition at line 1163 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( __EOC_SELECTION__ )
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )

Verify the ADC regular conversions check for converted data availability.

Parameters:
__EOC_SELECTION__ converted data availability check.
Return values:
SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)

Definition at line 1378 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EXTTRIG | ( | __HANDLE__,
 |  | __REGTRIG__
 | ) |
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)          || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)        || \
                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )

Verify the ADC regular conversions external trigger.

Parameters:
__HANDLE__ | ADC handle
__REGTRIG__ | programmed ADC regular conversions external trigger.
Return values:
SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)

Definition at line 1309 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for regular group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 1186 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_GAIN_COMPENSATION ( __GAIN_COMPENSATION__ ) ((__GAIN_COMPENSATION__) <= 16393UL)

Verify the ADC gain compensation.

Parameters:
__GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
Return values:
SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)

Definition at line 1171 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_OVERRUN ( __OVR__ )
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )

Verify the ADC regular conversions overrun handling.

Parameters:
__OVR__ ADC regular conversions overrun handling.
Return values:
SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)

Definition at line 1386 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) | ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters:
__RESOLUTION__ | ADC resolution (12, 10, 8 or 6 bits).
__ADC_VALUE__ | value checked against the resolution.
Return values:
SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

Definition at line 1098 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters:
NUMBER number of scheduled regular conversions in discontinuous mode.
Return values:
SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

Definition at line 1116 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

Verify the length of the scheduled regular conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 1107 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

Verify the ADC regular channel setting.

Parameters:
__CHANNEL__ programmed ADC regular channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1409 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )

Verify the ADC resolution setting.

Parameters:
__RESOLUTION__ programmed ADC resolution.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 1145 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION_8_6_BITS ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )

Verify the ADC resolution setting when limited to 6 or 8 bits.

Parameters:
__RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 1155 of file stm32g4xx_hal_adc.h.

#define IS_ADC_SAMPLE_TIME ( __TIME__ )
Value:
(((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )

Verify the ADC conversions sampling time.

Parameters:
__TIME__ ADC conversions sampling time.
Return values:
SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)

Definition at line 1394 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLINGMODE ( __SAMPLINGMODE__ )
Value:
(((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL)          || \
                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB)            || \
                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)  )

Verify the ADC regular conversions external trigger.

Parameters:
__SAMPLINGMODE__ programmed ADC regular conversions external trigger.
Return values:
SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)

Definition at line 1369 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_SCAN_MODE ( __SCAN_MODE__ )
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
__SCAN_MODE__ programmed ADC scan mode.
Return values:
SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)

Definition at line 1178 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL ADC macro to manage HAL ADC handle, IT and flags.

Defines
HAL ADC macro to manage HAL ADC handle, IT and flags.
ADC Exported Macros

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear the specified ADC flag.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
None

Definition at line 1585 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1522 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1501 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Check whether the specified ADC flag is set or not.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
State of flag (TRUE or FALSE).

Definition at line 1563 of file stm32g4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
State of interruption (SET or RESET)

Definition at line 1542 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                                          \
    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
    (__HANDLE__)->MspInitCallback = NULL;                                      \
    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
  } while(0)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 1472 of file stm32g4xx_hal_adc.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL ADC helper macro

Defines
HAL ADC helper macro
ADC Exported Macros

Defines

#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __HAL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
                              (__ADC_DATA__),\
                              (__ADC_RESOLUTION__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 2015 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
                                   (__ADC_DATA__),\
                                   (__ADC_RESOLUTION__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 2039 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
                          (__TEMPSENSOR_ADC_DATA__),\
                          (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 series, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2121 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
                                     (__TEMPSENSOR_TYP_CALX_V__),\
                                     (__TEMPSENSOR_CALX_TEMP__),\
                                     (__VREFANALOG_VOLTAGE__),\
                                     (__TEMPSENSOR_ADC_DATA__),\
                                     (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32G4, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2176 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
                                 (__ADC_RESOLUTION__))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 series, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 2071 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (8)
  • ADC_CHANNEL_2 (8)
  • ADC_CHANNEL_3 (8)
  • ADC_CHANNEL_4 (8)
  • ADC_CHANNEL_5 (8)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (7)
  • ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • ADC_CHANNEL_VBAT (6)
  • ADC_CHANNEL_VOPAMP1 (1)
  • ADC_CHANNEL_VOPAMP2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • ADC_CHANNEL_VOPAMP4 (5)
  • ADC_CHANNEL_VOPAMP5 (5)
  • ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18

Definition at line 1862 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))

Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.

Note:
Example: __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (8)
  • ADC_CHANNEL_2 (8)
  • ADC_CHANNEL_3 (8)
  • ADC_CHANNEL_4 (8)
  • ADC_CHANNEL_5 (8)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (7)
  • ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • ADC_CHANNEL_VBAT (6)
  • ADC_CHANNEL_VOPAMP1 (1)
  • ADC_CHANNEL_VOPAMP2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • ADC_CHANNEL_VOPAMP4 (5)
  • ADC_CHANNEL_VOPAMP5 (5)
  • ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1652 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_COMMON_INSTANCE ( __ADCx__ ) __LL_ADC_COMMON_INSTANCE((__ADCx__))

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1935 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
                                 (__ADC_RESOLUTION_CURRENT__),\
                                 (__ADC_RESOLUTION_TARGET__))

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 1992 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))

Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.

Note:
Example: __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (8)
  • ADC_CHANNEL_2 (8)
  • ADC_CHANNEL_3 (8)
  • ADC_CHANNEL_4 (8)
  • ADC_CHANNEL_5 (8)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (7)
  • ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • ADC_CHANNEL_VBAT (6)
  • ADC_CHANNEL_VOPAMP1 (1)
  • ADC_CHANNEL_VOPAMP2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • ADC_CHANNEL_VOPAMP4 (5)
  • ADC_CHANNEL_VOPAMP5 (5)
  • ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
  • On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
    (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1711 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value

Definition at line 1971 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): ADC_CHANNEL_1, ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (8)
  • ADC_CHANNEL_2 (8)
  • ADC_CHANNEL_3 (8)
  • ADC_CHANNEL_4 (8)
  • ADC_CHANNEL_5 (8)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (7)
  • ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • ADC_CHANNEL_VBAT (6)
  • ADC_CHANNEL_VOPAMP1 (1)
  • ADC_CHANNEL_VOPAMP2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • ADC_CHANNEL_VOPAMP4 (5)
  • ADC_CHANNEL_VOPAMP5 (5)
  • ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1780 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_VREFINT (7)
  • ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • ADC_CHANNEL_VBAT (6)
  • ADC_CHANNEL_VOPAMP1 (1)
  • ADC_CHANNEL_VOPAMP2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • ADC_CHANNEL_VOPAMP4 (5)
  • ADC_CHANNEL_VOPAMP5 (5)
  • ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1904 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1955 of file stm32g4xx_hal_adc.h.

#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled: refer to function LL_ADC_SetMultiDMATransfer(). In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1921 of file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (318978UL)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT (318978UL)

ADC calibration time-out value (unit: CPU cycles)

Definition at line 72 of file stm32g4xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_JSQR_FIELDS
Value:
((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                               ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
                               ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))

ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled

Definition at line 53 of file stm32g4xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (const ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

      (+) Start conversion of ADC group injected.
      (+) Stop conversion of ADC group injected.
      (+) Poll for conversion complete on ADC group injected.
      (+) Get result of ADC group injected channel conversion.
      (+) Start conversion of ADC group injected and enable interruptions.
      (+) Stop conversion of ADC group injected and disable interruptions.

      (+) When multimode feature is available, start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue | ( | const ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Get the calibration factor.

Parameters:
hadc ADC handle.
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
Calibration value.

Definition at line 200 of file stm32g4xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, and LL_ADC_GetCalibrationFactor().

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result.

ADC must be enabled and no conversion is ongoing.

Parameters:
hadc | ADC handle
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
CalibrationFactor | Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 220 of file stm32g4xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCalibrationFactor(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Parameters:
hadc ADC handle
SingleDiff Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
HAL status

Definition at line 126 of file stm32g4xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_IsCalibrationOnGoing(), LL_ADC_StartCalibration(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1251 of file stm32g4xx_hal_adc_ex.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1186 of file stm32g4xx_hal_adc_ex.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADCEx_InjectedGetValue | ( | const ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 series). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc ADC handle
InjectedRank the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1 ADC group injected rank 1
  • ADC_INJECTED_RANK_2 ADC group injected rank 2
  • ADC_INJECTED_RANK_3 ADC group injected rank 3
  • ADC_INJECTED_RANK_4 ADC group injected rank 4
Return values:
ADC group injected conversion data

Definition at line 1151 of file stm32g4xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, __ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, JEOS or JEOC is checked and cleared depending on AUTDLY bit status.
Return values:
HAL status

Definition at line 481 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedQueueOverflowCallback ( ADC_HandleTypeDef * hadc )

Injected context queue overflow callback.

Note:
This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts).
Parameters:
hadc ADC handle
Return values:
None

Definition at line 1205 of file stm32g4xx_hal_adc_ex.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled when multimode feature is available: HAL_ADCEx_InjectedStart() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 277 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : JEOC (end of conversion) or JEOS (end of sequence)
Case of multimode enabled (when multimode feature is enabled): HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc ADC handle.
Return values:
HAL status.

Definition at line 622 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_MULTI_INSTANCE_MASTER, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_GetMultimode(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_MULTI_DUAL_REG_INTERL, LL_ADC_MULTI_DUAL_REG_SIMULT, LL_ADC_MULTI_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of multimode enabled (when multimode feature is available), HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 426 of file stm32g4xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Case of multimode enabled (when multimode feature is available): HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
In case of auto-injection mode, HAL_ADC_Stop() must be used.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 795 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_JQOVF, ADC_INJECTED_GROUP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1220 of file stm32g4xx_hal_adc_ex.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1235 of file stm32g4xx_hal_adc_ex.c.

References UNUSED.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADCEx_MultiModeGetValue ( const ADC_HandleTypeDef * hadc )

Return the last ADC Master and Slave regular conversions results when in multimode configuration.

Parameters:
hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
Return values:
The converted data values.

Definition at line 1104 of file stm32g4xx_hal_adc_ex.c.

References __LL_ADC_COMMON_INSTANCE, assert_param, __ADC_HandleTypeDef::Instance, and UNUSED.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start MultiMode conversion and transfer regular results through DMA.

Note:
Multimode must have been previously configured using HAL_ADCEx_MultiModeConfigChannel() function. Interruptions enabled in this function: overrun, DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
State field of Slave ADC handle is not updated in this configuration: user should not rely on it for information related to Slave regular conversions.
Parameters:
hadc | ADC handle of ADC master (handle of ADC slave must not be used)
pData | Destination Buffer address.
Length | Length of data to be transferred from ADC peripheral to memory (in bytes).
Return values:
HAL status

Definition at line 862 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, __HAL_ADC_RESET_HANDLE_STATE, __LL_ADC_COMMON_INSTANCE, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EXTTRIG_EDGE, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.

Note:
Multimode is kept enabled after this function. MultiMode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADC_Stop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 981 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_RESET_HANDLE_STATE, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Note:
Multimode is kept enabled after this function. Multimode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
HAL status

Definition at line 1474 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_RESET_HANDLE_STATE, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1268 of file stm32g4xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.

Note:
HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. For multimode (when multimode feature is available), HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1386 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1326 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Peripheral Control functions

Functions
ADC Extended Peripheral Control functions
ADC Extended Exported Functions

ADC Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

ADC Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode when multimode feature is available
      (+) Enable or Disable Injected Queue
      (+) Disable ADC voltage regulator
      (+) Enter ADC deep-power-down mode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue ( ADC_HandleTypeDef * hadc )

Disable Injected Queue.

Note:
This function sets CFGR register JQDIS bit in order to disable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2274 of file stm32g4xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_QUEUE_DISABLE, LL_ADC_INJ_SetQueueMode(), and LL_ADC_REG_IsConversionOngoing().

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2311 of file stm32g4xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue ( ADC_HandleTypeDef * hadc )

Enable Injected Queue.

Note:
This function resets CFGR register JQDIS bit in order to enable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2233 of file stm32g4xx_hal_adc_ex.c.

References assert_param, HAL_ADC_STATE_INJ_JQOVF, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode ( ADC_HandleTypeDef * hadc )

Enter ADC deep-power-down mode.

Note:
This mode is achieved in setting DEEPPWD bit and allows to save power in reducing leakage currents. It is particularly interesting before entering stop modes.
Setting DEEPPWD automatically clears ADVREGEN bit and disables the ADC voltage regulator. This means that this API encompasses HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal calibration is lost.
To exit the ADC deep-power-down mode, the user is expected to resort to HAL_ADC_Init() API as well as to relaunch a calibration with HAL_ADCEx_Calibration_Start() API or to re-apply a previously saved calibration factor.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 2348 of file stm32g4xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_EnableDeepPowerDown(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | const ADC_InjectionConfTypeDef * | pConfigInjected
 | ) |  |

Configure a channel to be assigned to ADC group injected.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_InjectionConfTypeDef".
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Caution: For Injected Context Queue use, a context must be fully defined before start of injected conversion. All channels are configured consecutively for the same ADC instance. Therefore, the number of calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter InjectedNbrOfConversion for each context.
  • Example 1: If 1 context is intended to be used (or if there is no use of the Injected Queue Context feature) and if the context contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel (i.e. 3 times) before starting a conversion. This function must not be called to configure a 4th injected channel: it would start a new context into context queue.
  • Example 2: If 2 contexts are intended to be used and each of them contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and for each context (3 channels x 2 contexts = 6 calls). Conversion can start once the 1st context is set, that is after the first three HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
Parameters:
hadc | ADC handle
pConfigInjected | Structure of ADC injected group and ADC channel for injected group.
Return values:
HAL status

Definition at line 1659 of file stm32g4xx_hal_adc_ex.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CFGR_INJECT_CONTEXT_QUEUE, ADC_CFGR_INJECT_DISCCONTINUOUS, ADC_CHANNEL_TEMPSENSOR_ADC1, ADC_CHANNEL_TEMPSENSOR_ADC5, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, ADC_GET_RESOLUTION, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_JSQR_FIELDS, ADC_JSQR_RK, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_SAMPLETIME_3CYCLES_5, ADC_SCAN_DISABLE, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjecOversampling, ADC_InjectionConfTypeDef::InjecOversamplingMode, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedOffsetNumber, ADC_InjectionConfTypeDef::InjectedOffsetSaturation, ADC_InjectionConfTypeDef::InjectedOffsetSign, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_InjectionConfTypeDef::InjectedSingleDiff, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_EXTTRIGINJEC_EDGE, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_OFFSET_NUMBER, IS_ADC_OFFSET_SIGN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_RANGE, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_GetOffsetChannel(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_1, LL_ADC_OFFSET_2, LL_ADC_OFFSET_3, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE, LL_ADC_OFFSET_SATURATION_DISABLE, LL_ADC_OFFSET_SATURATION_ENABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_SAMPLINGTIME_2CYCLES_5, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT, LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetOffset(), LL_ADC_SetOffsetSaturation(), LL_ADC_SetOffsetSign(), LL_ADC_SetOffsetState(), LL_ADC_SetSamplingTimeCommonConfig(), ADC_InjectionConfTypeDef::QueueInjectedContext, ADC_InjOversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | const ADC_MultiModeTypeDef * | pMultimode
 | ) |  |

Enable ADC multimode and configure multimode parameters.

Note:
Possibility to update parameters on the fly: This function initializes multimode parameters, following calls to this function can be used to reconfigure some parameters of structure "ADC_MultiModeTypeDef" on the fly, without resetting the ADCs. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_MultiModeTypeDef".
To move back configuration from multimode to single mode, ADC must be reset (using function HAL_ADC_Init() ).
Parameters:
hadc | Master ADC handle
pMultimode | Structure of ADC multimode configuration
Return values:
HAL status

Definition at line 2116 of file stm32g4xx_hal_adc_ex.c.

References __HAL_ADC_RESET_HANDLE_STATE, __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CCR_MULTI_DMACONTREQ, ADC_CLEAR_ERRORCODE, ADC_MODE_INDEPENDENT, ADC_MULTI_SLAVE, assert_param, ADC_MultiModeTypeDef::DMAAccessMode, ADC_InitTypeDef::DMAContinuousRequests, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_DMA_ACCESS_MULTIMODE, IS_ADC_MULTIMODE, IS_ADC_SAMPLING_DELAY, LL_ADC_REG_IsConversionOngoing(), ADC_MultiModeTypeDef::Mode, __ADC_HandleTypeDef::State, and ADC_MultiModeTypeDef::TwoSamplingDelay.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_InjOversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjOversamplingTypeDef Struct Reference
ADC Extended Exported Types

ADC Injected Conversion Oversampling structure definition. More...

#include <stm32g4xx_hal_adc_ex.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift

Detailed Description

ADC Injected Conversion Oversampling structure definition.

Definition at line 46 of file stm32g4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjOversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of Oversampling - Ratio

Definition at line 48 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjOversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 51 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...

#include <stm32g4xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedSingleDiff
uint32_t | InjectedOffsetNumber
uint32_t | InjectedOffset
uint32_t | InjectedOffsetSign
FunctionalState | InjectedOffsetSaturation
uint32_t | InjectedNbrOfConversion
FunctionalState | InjectedDiscontinuousConvMode
FunctionalState | AutoInjectedConv
FunctionalState | QueueInjectedContext
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge
FunctionalState | InjecOversamplingMode
ADC_InjOversamplingTypeDef InjecOversampling

Detailed Description

Structure definition of ADC group injected and ADC channel affected to ADC group injected.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
  • Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
  • For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
  • For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
  • For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 80 of file stm32g4xx_hal_adc_ex.h.

Field Documentation

FunctionalState ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 182 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group injected trigger source. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 220 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC group injected trigger edge (when external trigger is selected). If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 231 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

ADC_InjOversamplingTypeDef ADC_InjectionConfTypeDef::InjecOversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 245 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjecOversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 240 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Specifies the channel to configure into ADC group injected. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 82 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 166 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 156 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 132 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetNumber

Selects the offset number. This parameter can be a value of ADC instance - Offset number. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 127 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedOffsetSaturation

Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 149 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetSign

Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of ADC Extended Offset Sign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 142 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Specifies the rank in the ADC group injected sequencer. This parameter must be a value of ADC group injected - Sequencer ranks. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 88 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt, ...), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values.

Definition at line 95 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of Channel - Single or differential ending. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 108 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::QueueInjectedContext

Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

Definition at line 201 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC multimode. More...

#include <stm32g4xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DMAAccessMode
uint32_t | TwoSamplingDelay

Detailed Description

Structure definition of ADC multimode.

Note:
The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). Both Master and Slave ADCs must be disabled.

Definition at line 259 of file stm32g4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DMAAccessMode

Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). This parameter can be a value of Multimode - DMA transfer mode depending on ADC resolution.

Definition at line 264 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multimode. This parameter can be a value of Multimode - Mode.

Definition at line 261 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of Multimode - Delay between two sampling phases. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.

Definition at line 269 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_adc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected trigger source

Defines
ADC group injected trigger source
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)
#define | ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)
#define | ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)
#define | ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
#define | ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)

ADC group injected conversion trigger from external peripheral: external interrupt line 15.

Definition at line 365 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)

ADC group injected conversion trigger from external peripheral: external interrupt line 3.

Definition at line 363 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event.

Definition at line 343 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event.

Definition at line 361 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event.

Definition at line 345 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event.

Definition at line 347 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event.

Definition at line 349 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event.

Definition at line 351 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event.

Definition at line 353 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event.

Definition at line 355 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event.

Definition at line 357 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event.

Definition at line 359 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)

ADC group injected conversion trigger from external peripheral: LPTIMER OUT event.

Definition at line 367 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)

ADC group injected conversion trigger from external peripheral: TIM15 TRGO.

Definition at line 331 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare).

Definition at line 333 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)

ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare).

Definition at line 297 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare).

Definition at line 299 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO.

Definition at line 293 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2.

Definition at line 295 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)

ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare).

Definition at line 339 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)

ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare).

Definition at line 341 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)

ADC group injected conversion trigger from external peripheral: TIM20 TRGO.

Definition at line 335 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM20 TRGO2.

Definition at line 337 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare).

Definition at line 303 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO.

Definition at line 301 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)

ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare).

Definition at line 307 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)

ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare).

Definition at line 309 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)

ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare).

Definition at line 311 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)

ADC group injected conversion trigger from external peripheral: TIM3 TRGO.

Definition at line 305 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)

ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare).

Definition at line 315 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)

ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare).

Definition at line 317 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)

ADC group injected conversion trigger from external peripheral: TIM4 TRGO.

Definition at line 313 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)

ADC group injected conversion trigger from external peripheral: TIM6 TRGO.

Definition at line 319 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)

ADC group injected conversion trigger from external peripheral: TIM7 TRGO.

Definition at line 321 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)

ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare).

Definition at line 327 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare).

Definition at line 329 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO.

Definition at line 323 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO2.

Definition at line 325 of file stm32g4xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)

ADC group injected conversion trigger software start

Definition at line 291 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected trigger edge (when external trigger is selected)

Defines
ADC group injected trigger edge (when external trigger is selected)
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)

Injected conversions trigger polarity set to falling edge

Definition at line 380 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)

Injected conversions trigger disabled (SW start)

Definition at line 376 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)

Injected conversions trigger polarity set to rising edge

Definition at line 378 of file stm32g4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Injected conversions trigger polarity set to both rising and falling edges

Definition at line 382 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Extended Exported Constants

Defines

#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to differential

Definition at line 392 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)

ADC channel ending set to single ended

Definition at line 391 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)

Define Documentation

#define ADC_OFFSET_1 (LL_ADC_OFFSET_1)

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 402 of file stm32g4xx_hal_adc_ex.h.

#define ADC_OFFSET_2 (LL_ADC_OFFSET_2)

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 405 of file stm32g4xx_hal_adc_ex.h.

#define ADC_OFFSET_3 (LL_ADC_OFFSET_3)

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 408 of file stm32g4xx_hal_adc_ex.h.

#define ADC_OFFSET_4 (LL_ADC_OFFSET_4)

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 411 of file stm32g4xx_hal_adc_ex.h.

#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)

ADC offset disabled: no offset correction for the selected ADC channel

Definition at line 400 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Offset Sign

Defines
ADC Extended Offset Sign
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
#define | ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)

Define Documentation

#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)

Offset sign negative, offset is subtracted

Definition at line 421 of file stm32g4xx_hal_adc_ex.h.

#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)

Offset sign positive, offset is added

Definition at line 422 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

Define Documentation

#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)

ADC group injected sequencer rank 1

Definition at line 430 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)

ADC group injected sequencer rank 2

Definition at line 431 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)

ADC group injected sequencer rank 3

Definition at line 432 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

ADC group injected sequencer rank 4

Definition at line 433 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - DMA transfer mode depending on ADC resolution

Defines
Multimode - DMA transfer mode depending on ADC resolution
Multimode - Mode

Defines

#define | ADC_DMAACCESSMODE_DISABLED (0x00000000UL)
#define | ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1)
#define | ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA)

Define Documentation

#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1)

DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution

Definition at line 465 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA)

DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution

Definition at line 467 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL)

DMA multimode disabled: each ADC uses its own DMA channel

Definition at line 463 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - Delay between two sampling phases

Defines
Multimode - Delay between two sampling phases
Multimode - Mode

Defines

#define | ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)
#define | ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)
#define | ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)
#define | ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
#define | ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)
#define | ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)
#define | ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)

Define Documentation

#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)

ADC multimode delay between two sampling phases: 10 ADC clock cycles

Definition at line 494 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)

ADC multimode delay between two sampling phases: 11 ADC clock cycles

Definition at line 496 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)

ADC multimode delay between two sampling phases: 12 ADC clock cycles

Definition at line 498 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)

ADC multimode delay between two sampling phases: 1 ADC clock cycle

Definition at line 476 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)

ADC multimode delay between two sampling phases: 2 ADC clock cycles

Definition at line 478 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)

ADC multimode delay between two sampling phases: 3 ADC clock cycles

Definition at line 480 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)

ADC multimode delay between two sampling phases: 4 ADC clock cycles

Definition at line 482 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)

ADC multimode delay between two sampling phases: 5 ADC clock cycles

Definition at line 484 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)

ADC multimode delay between two sampling phases: 6 ADC clock cycles

Definition at line 486 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)

ADC multimode delay between two sampling phases: 7 ADC clock cycles

Definition at line 488 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)

ADC multimode delay between two sampling phases: 8 ADC clock cycles

Definition at line 490 of file stm32g4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)

ADC multimode delay between two sampling phases: 9 ADC clock cycles

Definition at line 492 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - Mode

Modules | Defines
Multimode - Mode
ADC Extended Exported Constants

Modules

Multimode - DMA transfer mode depending on ADC resolution
Multimode - Delay between two sampling phases

Defines

#define | ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
#define | ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
#define | ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
#define | ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
#define | ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)

Define Documentation

#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)

Definition at line 450 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)

ADC dual mode enabled: group injected simultaneous

Definition at line 448 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)

ADC dual mode enabled: Combined group regular interleaved

Definition at line 446 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Definition at line 457 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)

ADC dual mode enabled: group regular simultaneous

Definition at line 444 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 455 of file stm32g4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 453 of file stm32g4xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)

ADC dual mode disabled (ADC independent mode)

Definition at line 442 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

Define Documentation

#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)

ADC group injected (not available on all STM32 devices)

Definition at line 514 of file stm32g4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)

ADC group regular (available on all STM32 devices)

Definition at line 512 of file stm32g4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

ADC both groups regular and injected

Definition at line 516 of file stm32g4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADCx CFGR fields

Defines
ADCx CFGR fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS

Define Documentation

#define ADC_CFGR_FIELDS
Value:
(ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )

Definition at line 524 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADCx SMPR1 fields

Defines
ADCx SMPR1 fields
ADC Extended Exported Constants

Defines

#define ADC_SMPR1_FIELDS

Define Documentation

#define ADC_SMPR1_FIELDS
Value:
(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
                             ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)

Definition at line 538 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADCx CFGR sub fields

Defines
ADCx CFGR sub fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Define Documentation

#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Definition at line 557 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Exported Macros

Defines
ADC Extended Exported Macros
ADCEx

Defines

#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
Force ADC instance in multimode mode independent (multimode disable).

Define Documentation

#define ADC_FORCE_MODE_INDEPENDENT ( __HANDLE__ ) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)

Force ADC instance in multimode mode independent (multimode disable).

Note:
This macro must be used only in case of transition from multimode to mode independent and in case of unknown previous state, to ensure ADC configuration is in mode independent.
Standard way of multimode configuration change is done from HAL ADC handle of ADC master using function "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". Usage of this macro is not the Standard way of multimode configuration and can lead to have HAL ADC handles status misaligned. Usage of this macro must be limited to cases mentioned above.
Parameters:
__HANDLE__ ADC handle.
Return values:
None

Definition at line 587 of file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
Check whether or not ADC is independent.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__)
Set the selected injected Channel rank.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
Configure the ADC DMA continuous request.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)
Verify the ADC offset sign setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__)
Verify the ADC multimode DMA access setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__)
Verify the ADC analog watchdog filtering setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
Return the DFSDM configuration mode.

Define Documentation

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) | ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))

Shift the AWD1 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__ | ADC handle
__THRESHOLD__ | Value to be shifted
Return values:
None

Definition at line 737 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) |
Value:
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
   ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
   ((__THRESHOLD__) << 2UL)                                                                                 \
  )

Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 7. If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). If resolution 8 bits, no shift. If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
Parameters:
__HANDLE__ | ADC handle
__THRESHOLD__ | Value to be shifted
Return values:
None

Definition at line 751 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_BATTERY_VOLTAGE_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) != ADC2)

Verify the ADC instance connected to the battery voltage VBAT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 832 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CCR_MULTI_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)

Configure the ADC DMA continuous request for ADC multimode.

Parameters:
__DMACONTREQ_MODE__ DMA continuous request mode.
Return values:
None

Definition at line 707 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define ADC_CFGR_AUTOWAIT ( __AUTOWAIT__ ) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)

Configure the ADC auto delay mode.

Parameters:
__AUTOWAIT__ Auto delay bit enable or disable.
Return values:
None

Definition at line 685 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_CONTINUOUS ( __CONTINUOUS_MODE__ ) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)

Configure ADC continuous conversion mode.

Parameters:
__CONTINUOUS_MODE__ Continuous mode.
Return values:
None

Definition at line 692 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DFSDM ( __HANDLE__ ) (0x0UL)

Return the DFSDM configuration mode.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
DFSDM configuration mode

Definition at line 1473 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DISCONTINUOUS_NUM ( __NBR_DISCONTINUOUS_CONV__ ) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)

Configure the number of discontinuous conversions for regular group.

Parameters:
__NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
Return values:
None

Definition at line 677 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)

Configure the ADC DMA continuous request.

Parameters:
__DMACONTREQ_MODE__ DMA continuous request mode.
Return values:
None

Definition at line 699 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_INJECT_CONTEXT_QUEUE ( __INJECT_CONTEXT_QUEUE_MODE__ ) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)

Configure ADC injected context queue.

Parameters:
__INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
Return values:
None

Definition at line 653 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_INJECT_DISCCONTINUOUS ( __INJECT_DISCONTINUOUS_MODE__ ) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)

Configure ADC discontinuous conversion mode for injected group.

Parameters:
__INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
Return values:
None

Definition at line 661 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_REG_DISCONTINUOUS ( __REG_DISCONTINUOUS_MODE__ ) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)

Configure ADC discontinuous conversion mode for regular group.

Parameters:
__REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
Return values:
None

Definition at line 669 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CLEAR_COMMON_CONTROL_REGISTER ( __HANDLE__ )
Value:
CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
                                                                ADC_CCR_CKMODE    | \
                                                                ADC_CCR_PRESC     | \
                                                                ADC_CCR_VBATSEL   | \
                                                                ADC_CCR_VSENSESEL | \
                                                                ADC_CCR_VREFEN    | \
                                                                ADC_CCR_MDMA      | \
                                                                ADC_CCR_DMACFG    | \
                                                                ADC_CCR_DELAY     | \
                                                                ADC_CCR_DUAL)

Clear Common Control Register.

Parameters:
__HANDLE__ ADC handle.
Return values:
None

Definition at line 763 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

#define ADC_IS_INDEPENDENT ( __HANDLE__ ) (RESET)

Check whether or not ADC is independent.

Parameters:
__HANDLE__ ADC handle.
Note:
When multimode feature is not available, the macro always returns SET.
Return values:
SET (ADC is independent) or RESET (ADC is not).

Definition at line 635 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start_DMA().

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (software start) or RESET (external trigger).

Definition at line 609 of file stm32g4xx_hal_adc_ex.h.

#define ADC_JSQR_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) |
Value:
((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
   << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

Set the selected injected Channel rank.

Parameters:
__CHANNELNB__ | Channel number.
__RANKNB__ | Rank number.
Return values:
None

Definition at line 644 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_MULTI_SLAVE | ( | __HANDLE_MASTER__,
 |  | __HANDLE_SLAVE__
 | ) |
Value:
( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
    ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
    :                                                                    \
    ((__HANDLE_SLAVE__)->Instance = NULL)                                \
  )

Set handle instance of the ADC slave associated to the ADC master.

Parameters:
__HANDLE_MASTER__ | ADC master handle.
__HANDLE_SLAVE__ | ADC slave handle.
Note:
if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
Return values:
None

Definition at line 802 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_OFFSET_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __OFFSET__
 | ) | ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))

Shift the offset with respect to the selected ADC resolution.

Note:
Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__ | ADC handle
__OFFSET__ | Value to be shifted
Return values:
None

Definition at line 722 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_TEMPERATURE_SENSOR_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC1)

Verify the ADC instance connected to the temperature sensor.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 820 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_VREFINT_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) != ADC2)

Verify the ADC instance connected to the internal voltage reference VREFINT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 842 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE ( __FILTERING_MODE__ )
Value:
(((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)            || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)        || \
   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)           )

Verify the ADC analog watchdog filtering setting.

Parameters:
__FILTERING_MODE__ programmed ADC analog watchdog mode setting.
Return values:
SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)

Definition at line 1378 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( __WATCHDOG_MODE__ )
Value:
(((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)            || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)      || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)    || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)         || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)       || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      )

Verify the ADC analog watchdog mode setting.

Parameters:
__WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
Return values:
SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)

Definition at line 1365 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( __WATCHDOG__ )
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )

Verify the ADC analog watchdog setting.

Parameters:
__WATCHDOG__ programmed ADC analog watchdog setting.
Return values:
SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)

Definition at line 1356 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CALFACT ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) <= (0x7FU))

Calibration factor size verification (7 bits maximum).

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

Definition at line 857 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_1)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))

Verify the ADC channel setting.

Parameters:
__HANDLE__ | ADC handle.
__CHANNEL__ | programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 951 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( __CONVERSION__ )
Value:
(((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )

Verify the ADC conversion (regular or injected or both).

Parameters:
__CONVERSION__ ADC conversion group.
Return values:
SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)

Definition at line 1394 of file stm32g4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop().

#define IS_ADC_DFSDMCFG_MODE ( __HANDLE__ ) (SET)

Verify the DFSDM mode configuration.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports SET. For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

Definition at line 1463 of file stm32g4xx_hal_adc_ex.h.

#define IS_ADC_DIFF_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_13))) )

Verify the ADC channel setting in differential mode.

Parameters:
__HANDLE__ | ADC handle.
__CHANNEL__ | programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1073 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_DMA_ACCESS_MULTIMODE ( __MODE__ )
Value:
(((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )

Verify the ADC multimode DMA access setting.

Parameters:
__MODE__ programmed ADC multimode DMA access setting.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1328 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EVENT_TYPE ( __EVENT__ )
Value:
(((__EVENT__) == ADC_EOSMP_EVENT)  || \
                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )

Verify the ADC event type.

Parameters:
__EVENT__ ADC event.
Return values:
SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)

Definition at line 1403 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIGINJEC | ( | __HANDLE__,
 |  | __INJTRIG__
 | ) |
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)        || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)       || \
                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )

Verify the ADC injected conversions external trigger.

Parameters:
__HANDLE__ | ADC handle.
__INJTRIG__ | programmed ADC injected conversions external trigger.
Return values:
SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)

Definition at line 1243 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )

Verify the ADC edge trigger setting for injected group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 1303 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))

Verify the length of scheduled injected conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 850 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )

Verify the ADC injected channel setting.

Parameters:
__CHANNEL__ programmed ADC injected channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1122 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MULTIMODE ( __MODE__ )
Value:
(((__MODE__) == ADC_MODE_INDEPENDENT)               || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )

Verify the ADC multimode setting.

Parameters:
__MODE__ programmed ADC multimode setting.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1314 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_OFFSET_NUMBER ( __OFFSET_NUMBER__ )
Value:
(((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )

Verify the ADC offset management setting.

Parameters:
__OFFSET_NUMBER__ ADC offset management.
Return values:
SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)

Definition at line 1103 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OFFSET_SIGN ( __OFFSET_SIGN__ )
Value:
(((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
                                                 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )

Verify the ADC offset sign setting.

Parameters:
__OFFSET_SIGN__ ADC offset sign.
Return values:
SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)

Definition at line 1114 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OVERSAMPLING_RATIO ( __RATIO__ )
Value:
(((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))

Verify the ADC oversampling ratio.

Parameters:
__RATIO__ programmed ADC oversampling ratio.
Return values:
SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)

Definition at line 1415 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGOVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters:
__MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1452 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RIGHT_BIT_SHIFT ( __SHIFT__ )
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling shift.

Parameters:
__SHIFT__ programmed ADC oversampling shift.
Return values:
SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

Definition at line 1429 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( __DELAY__ )
Value:
(((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )

Verify the ADC multimode delay setting.

Parameters:
__DELAY__ programmed ADC multimode delay setting.
Return values:
SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)

Definition at line 1337 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_SINGLE_DIFFERENTIAL ( __SING_DIFF__ )
Value:
(((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )

Verify the ADC single-ended input or differential mode setting.

Parameters:
__SING_DIFF__ programmed channel setting.
Return values:
SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)

Definition at line 1095 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
__MODE__ programmed ADC oversampling triggered mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1444 of file stm32g4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 517 of file stm32g4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, __COMP_HandleTypeDef::MspDeInitCallback, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 224 of file stm32g4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_CLEAR_ERRORCODE, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TriggerCallback(), COMP_InitTypeDef::Hysteresis, __COMP_HandleTypeDef::Init, COMP_InitTypeDef::InputMinus, COMP_InitTypeDef::InputPlus, __COMP_HandleTypeDef::Instance, IS_COMP_BLANKINGSRC_INSTANCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_TRIGGERMODE, LL_EXTI_ClearFlag_0_31(), LL_EXTI_ClearFlag_32_63(), LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableFallingTrig_32_63(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_DisableRisingTrig_32_63(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableFallingTrig_32_63(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_EnableRisingTrig_32_63(), __COMP_HandleTypeDef::Lock, __COMP_HandleTypeDef::MspInitCallback, COMP_InitTypeDef::OutputPol, __COMP_HandleTypeDef::State, __COMP_HandleTypeDef::TriggerCallback, and COMP_InitTypeDef::TriggerMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 581 of file stm32g4xx_hal_comp.c.

References UNUSED.

Referenced by HAL_COMP_DeInit(), and HAL_COMP_UnRegisterCallback().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 566 of file stm32g4xx_hal_comp.c.

References UNUSED.

Referenced by HAL_COMP_Init(), and HAL_COMP_UnRegisterCallback().

HAL_StatusTypeDef HAL_COMP_RegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID,
 |  | pCOMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User COMP Callback To be used instead of the weak predefined callback.

Parameters:
hcomp | Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 605 of file stm32g4xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_UnRegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Parameters:
hcomp Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 688 of file stm32g4xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MspDeInit(), HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MspInit(), HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a comparator instance.
      (+) Stop a comparator instance.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ handler.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 872 of file stm32g4xx_hal_comp.c.

References COMP_GET_EXTI_LINE, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::Instance, LL_EXTI_ClearFlag_0_31(), LL_EXTI_ClearFlag_32_63(), LL_EXTI_IsActiveFlag_0_31(), LL_EXTI_IsActiveFlag_32_63(), and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 776 of file stm32g4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 830 of file stm32g4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (const COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( const COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

On this STM32 series, comparator 'value' is taken before polarity and blanking are applied, thus:

  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus
    Parameters:
    hcomp COMP handle
    Return values:
    Returns the selected comparator output level:
    • COMP_OUTPUT_LEVEL_LOW
    • COMP_OUTPUT_LEVEL_HIGH

Definition at line 1005 of file stm32g4xx_hal_comp.c.

References assert_param, COMP_OUTPUT_LEVEL_BITOFFSET_POS, and __COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Locking the comparator from reset state is possible if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 952 of file stm32g4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, HAL_COMP_STATE_BUSY_LOCKED, HAL_COMP_STATE_READY, HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_RESET, HAL_COMP_STATE_RESET_LOCKED, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator trigger callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 1019 of file stm32g4xx_hal_comp.c.

References UNUSED.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef | HAL_COMP_GetState (const COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (const COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_COMP_GetError ( const COMP_HandleTypeDef * hcomp )

Return the COMP error code.

Parameters:
hcomp COMP handle
Return values:
COMP error code

Definition at line 1073 of file stm32g4xx_hal_comp.c.

References assert_param, __COMP_HandleTypeDef::ErrorCode, and __COMP_HandleTypeDef::Instance.

HAL_COMP_StateTypeDef HAL_COMP_GetState ( const COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 1053 of file stm32g4xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Types

Data Structures | Defines | Typedefs | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Define Documentation

#define COMP_STATE_BITFIELD_LOCK (0x10U)

HAL COMP state machine: HAL COMP states definition.

Definition at line 74 of file stm32g4xx_hal_comp.h.

Typedef Documentation

typedef struct __COMP_HandleTypeDef COMP_HandleTypeDef

COMP Handle Structure definition.

typedef void(* pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp)

HAL COMP Callback pointer definition.

pointer to a COMP callback function

Definition at line 120 of file stm32g4xx_hal_comp.h.

Enumeration Type Documentation

enum HAL_COMP_CallbackIDTypeDef

HAL COMP Callback ID enumeration definition.

Enumerator:
HAL_COMP_TRIGGER_CB_ID

COMP trigger callback ID

HAL_COMP_MSPINIT_CB_ID

COMP Msp Init callback ID

HAL_COMP_MSPDEINIT_CB_ID

COMP Msp DeInit callback ID

Definition at line 110 of file stm32g4xx_hal_comp.h.

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 75 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32g4xx_hal_comp.h>

Data Fields

uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 48 of file stm32g4xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP blanking source

Definition at line 63 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 57 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 54 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 51 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP output Polarity

Definition at line 60 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 66 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_comp.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32g4xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TriggerCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspInitCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspDeInitCallback )(struct __COMP_HandleTypeDef *hcomp)

Detailed Description

COMP Handle Structure definition.

Definition at line 89 of file stm32g4xx_hal_comp.h.

Field Documentation

__IO uint32_t __COMP_HandleTypeDef::ErrorCode

COMP error code

Definition at line 98 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_GetError(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

COMP_InitTypeDef __COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 95 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* __COMP_HandleTypeDef::Instance

Register base address

Definition at line 94 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

HAL_LockTypeDef __COMP_HandleTypeDef::Lock

Locking object

Definition at line 96 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

void(* __COMP_HandleTypeDef::MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp DeInit callback

Definition at line 102 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::MspInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp Init callback

Definition at line 101 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

__IO HAL_COMP_StateTypeDef __COMP_HandleTypeDef::State

COMP communication state

Definition at line 97 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_RegisterCallback(), HAL_COMP_Start(), HAL_COMP_Stop(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::TriggerCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP trigger callback

Definition at line 100 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_comp.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Error Code

Defines
COMP Error Code
COMP Exported Constants

Defines

#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Define Documentation

#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Invalid Callback error

Definition at line 138 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

#define HAL_COMP_ERROR_NONE (0x00UL)

No error

Definition at line 136 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)

Define Documentation

#define COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 147 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)

Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 148 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 157 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 156 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 158 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 160 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 161 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 162 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 163 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 164 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 165 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 166 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 167 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 168 of file stm32g4xx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 159 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )
#define | COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_LOW COMP_HYSTERESIS_10MV
#define | COMP_HYSTERESIS_MEDIUM COMP_HYSTERESIS_40MV
#define | COMP_HYSTERESIS_HIGH COMP_HYSTERESIS_70MV

Define Documentation

#define COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)

Hysteresis level 10mV

Definition at line 177 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )

Hysteresis level 20mV

Definition at line 178 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level 30mV

Definition at line 179 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )

Hysteresis level 40mV

Definition at line 180 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)

Hysteresis level 50mV

Definition at line 181 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )

Hysteresis level 60mV

Definition at line 182 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level 70mV

Definition at line 183 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_HIGH COMP_HYSTERESIS_70MV

Hysteresis level high

Definition at line 186 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_LOW COMP_HYSTERESIS_10MV

Hysteresis level low

Definition at line 184 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM COMP_HYSTERESIS_40MV

Hysteresis level medium

Definition at line 185 of file stm32g4xx_hal_comp.h.

#define COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 176 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP output Polarity

Defines
COMP output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 195 of file stm32g4xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 194 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP blanking source

Defines
COMP blanking source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Define Documentation

#define COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 203 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM15 OC1 (Common to all COMP instances)

Definition at line 233 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 229 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 230 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 231 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 204 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 205 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 206 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 207 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 208 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 209 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 210 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM20 OC5 (Common to all COMP instances)

Definition at line 232 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 211 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 212 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 213 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 214 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 215 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 216 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 217 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 218 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 219 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 220 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 221 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM4 OC3 (Common to all COMP instances)

Definition at line 234 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 222 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 223 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 224 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 225 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 226 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 227 of file stm32g4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 228 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Definition at line 252 of file stm32g4xx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Definition at line 249 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 265 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 264 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 266 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 262 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 261 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 263 of file stm32g4xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE (0x00000000UL)

Comparator output triggering no External Interrupt Line

Definition at line 260 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 317 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 310 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 335 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 328 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
                                                      (__HANDLE__)->MspInitCallback = NULL;            \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 289 of file stm32g4xx_hal_comp.h.

#define COMP_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)

Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 303 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
Generate a software interrupt on the COMP3 EXTI line.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI flag.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP4 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP4 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
Generate a software interrupt on the COMP4 EXTI line.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line in event mode.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line in event mode.
#define | __HAL_COMP_COMP4_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
Check whether the COMP4 EXTI line flag is set.
#define | __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
Clear the COMP4 EXTI flag.

Define Documentation

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 426 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 414 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 366 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 396 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 354 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
                                                               } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 381 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 408 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 360 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 390 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 348 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
                                                              } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 372 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 402 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 420 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI flag.

Return values:
None

Definition at line 510 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 498 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 450 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 480 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 438 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
                                                               } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 465 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 492 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 444 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 474 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 432 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
                                                              } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 456 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 486 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 504 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)

Clear the COMP3 EXTI flag.

Return values:
None

Definition at line 594 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line in event mode.

Return values:
None

Definition at line 582 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line falling edge trigger.

Return values:
None

Definition at line 534 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line in interrupt mode.

Return values:
None

Definition at line 564 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line rising edge trigger.

Return values:
None

Definition at line 522 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                  LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                                  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                                } while(0)

Disable the COMP3 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 549 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line in event mode.

Return values:
None

Definition at line 576 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line falling edge trigger.

Return values:
None

Definition at line 528 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line in interrupt mode.

Return values:
None

Definition at line 558 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line rising edge trigger.

Return values:
None

Definition at line 516 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                  LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                                  LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                                } while(0)

Enable the COMP3 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 540 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)

Generate a software interrupt on the COMP3 EXTI line.

Return values:
None

Definition at line 570 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)

Check whether the COMP3 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 588 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)

Clear the COMP4 EXTI flag.

Return values:
None

Definition at line 678 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)

Disable the COMP4 EXTI line in event mode.

Return values:
None

Definition at line 666 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)

Disable the COMP4 EXTI line falling edge trigger.

Return values:
None

Definition at line 618 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)

Disable the COMP4 EXTI line in interrupt mode.

Return values:
None

Definition at line 648 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)

Disable the COMP4 EXTI line rising edge trigger.

Return values:
None

Definition at line 606 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                  LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
                                                                  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
                                                                } while(0)

Disable the COMP4 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 633 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)

Enable the COMP4 EXTI line in event mode.

Return values:
None

Definition at line 660 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)

Enable the COMP4 EXTI line falling edge trigger.

Return values:
None

Definition at line 612 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)

Enable the COMP4 EXTI line in interrupt mode.

Return values:
None

Definition at line 642 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)

Enable the COMP4 EXTI line rising edge trigger.

Return values:
None

Definition at line 600 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                  LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
                                                                  LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
                                                                } while(0)

Enable the COMP4 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 624 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)

Generate a software interrupt on the COMP4 EXTI line.

Return values:
None

Definition at line 654 of file stm32g4xx_hal_comp.h.

#define __HAL_COMP_COMP4_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)

Check whether the COMP4 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 672 of file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21)
#define | COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22)
#define | COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29)
#define | COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)

Define Documentation

#define COMP_EXTI_EVENT (0x00000002UL)

EXTI line event only (without interruption)

Definition at line 973 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING (0x00000020UL)

EXTI line event on falling edge

Definition at line 975 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT (0x00000001UL)

EXTI line event with interruption

Definition at line 972 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21)

EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet

Definition at line 956 of file stm32g4xx_hal_comp.h.

#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22)

EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet

Definition at line 957 of file stm32g4xx_hal_comp.h.

#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29)

EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet

Definition at line 958 of file stm32g4xx_hal_comp.h.

#define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30)

EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet

Definition at line 959 of file stm32g4xx_hal_comp.h.

#define COMP_EXTI_RISING (0x00000010UL)

EXTI line event on rising edge

Definition at line 974 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US (5UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Define Documentation

#define COMP_DELAY_STARTUP_US (5UL)

Delay for COMP startup time

Definition at line 180 of file stm32g4xx_hal_comp.c.

Referenced by HAL_COMP_Start().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 186 of file stm32g4xx_hal_comp.c.

Referenced by HAL_COMP_Init().

#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Definition at line 188 of file stm32g4xx_hal_comp.c.

Referenced by HAL_COMP_GetOutputLevel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP private macros to get EXTI line associated with comparators

Defines
COMP private macros to get EXTI line associated with comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
                                             :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
                                             :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
                                             : COMP_EXTI_LINE_COMP4)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__ specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 1006 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRC_INSTANCE | ( | __INSTANCE__,
 |  | __OUTPUT_BLANKING_SOURCE__
 | ) |
Value:
((((__INSTANCE__) == COMP1) &&                                               \
    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
   ||                                                                          \
   (((__INSTANCE__) == COMP2) &&                                               \
    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
   ||                                                                          \
   (((__INSTANCE__) == COMP3) &&                                               \
    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
   ||                                                                          \
   (((__INSTANCE__) == COMP4) &&                                               \
    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)             \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)              \
  )

Definition at line 1189 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_BLANKINGSRCE ( __OUTPUT_BLANKING_SOURCE__ )

Definition at line 1100 of file stm32g4xx_hal_comp.h.

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_10MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_20MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_30MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_40MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_50MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_60MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_70MV)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 1082 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  ||\
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  ||\
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  ||\
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     ||\
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         ||\
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         ||\
                                                                 (((__COMP_INSTANCE__) == COMP1)                        && \
                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))   \
                                                                 )                                                      || \
                                                                 (((__COMP_INSTANCE__) == COMP2)                        && \
                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  ||\
                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
                                                                 )                                                      || \
                                                                 (((__COMP_INSTANCE__) == COMP3)                        && \
                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))   \
                                                                 )                                                      || \
                                                                 (((__COMP_INSTANCE__) == COMP4)                        && \
                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
                                                                 ))

Definition at line 1057 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))

Definition at line 1018 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 1263 of file stm32g4xx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 1094 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 1255 of file stm32g4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Private Functions

Functions
CORDIC Private Functions
CORDIC

Functions

static void | CORDIC_WriteInDataIncrementPtr (const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
Write input data for CORDIC processing, and increment input buffer pointer.
static void | CORDIC_ReadOutDataIncrementPtr (const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
Read output data of CORDIC processing, and increment output buffer pointer.
static void | CORDIC_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CORDIC Input Data process complete callback.
static void | CORDIC_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CORDIC Output Data process complete callback.
static void | CORDIC_DMAError (DMA_HandleTypeDef *hdma)
DMA CORDIC communication error callback.

Function Documentation

static void CORDIC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CORDIC communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1316 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::ErrorCallback, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_DMA, HAL_CORDIC_ErrorCallback(), HAL_CORDIC_STATE_READY, and __CORDIC_HandleTypeDef::State.

Referenced by HAL_CORDIC_Calculate_DMA().

static void CORDIC_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CORDIC Input Data process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1256 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::CalculateCpltCallback, CORDIC_DMA_DIR_IN, CORDIC_DMA_DIR_NONE, CORDIC_DMA_WEN, __CORDIC_HandleTypeDef::DMADirection, HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_STATE_READY, __CORDIC_HandleTypeDef::Instance, and __CORDIC_HandleTypeDef::State.

Referenced by HAL_CORDIC_Calculate_DMA().

static void CORDIC_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CORDIC Output Data process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1288 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::CalculateCpltCallback, CORDIC_DMA_DIR_NONE, CORDIC_DMA_REN, __CORDIC_HandleTypeDef::DMADirection, HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_STATE_READY, __CORDIC_HandleTypeDef::Instance, and __CORDIC_HandleTypeDef::State.

Referenced by HAL_CORDIC_Calculate_DMA().

static void CORDIC_ReadOutDataIncrementPtr | ( | const CORDIC_HandleTypeDef * | hcordic,
 |  | int32_t ** | ppOutBuff
 | ) |  | [static]

Read output data of CORDIC processing, and increment output buffer pointer.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
ppOutBuff | Pointer to pointer to output buffer.
Return values:
none

Definition at line 1232 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::Instance.

Referenced by HAL_CORDIC_Calculate(), HAL_CORDIC_CalculateZO(), and HAL_CORDIC_IRQHandler().

static void CORDIC_WriteInDataIncrementPtr | ( | const CORDIC_HandleTypeDef * | hcordic,
 |  | const int32_t ** | ppInBuff
 | ) |  | [static]

Write input data for CORDIC processing, and increment input buffer pointer.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
ppInBuff | Pointer to pointer to input buffer.
Return values:
none

Definition at line 1206 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::Instance.

Referenced by HAL_CORDIC_Calculate(), HAL_CORDIC_CalculateZO(), and HAL_CORDIC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORDIC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CORDIC_Init (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_CORDIC_DeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC peripheral.
__weak void | HAL_CORDIC_MspInit (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC MSP.
__weak void | HAL_CORDIC_MspDeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC MSP.
HAL_StatusTypeDef | HAL_CORDIC_RegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void(*pCallback)(CORDIC_HandleTypeDef *_hcordic))
Register a CORDIC CallBack.
HAL_StatusTypeDef | HAL_CORDIC_UnRegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
Unregister a CORDIC CallBack.
HAL_StatusTypeDef | HAL_CORDIC_RegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CORDIC peripheral and the associated handle
      (+) DeInitialize the CORDIC peripheral
      (+) Initialize the CORDIC MSP (MCU Specific Package)
      (+) De-Initialize the CORDIC MSP

    [..]

Function Documentation

HAL_StatusTypeDef HAL_CORDIC_DeInit ( CORDIC_HandleTypeDef * hcordic )

DeInitialize the CORDIC peripheral.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure.
Return values:
HAL status

Definition at line 268 of file stm32g4xx_hal_cordic.c.

References assert_param, CORDIC_DMA_DIR_NONE, __CORDIC_HandleTypeDef::DMADirection, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_NONE, HAL_CORDIC_MspDeInit(), HAL_CORDIC_STATE_BUSY, HAL_CORDIC_STATE_RESET, __CORDIC_HandleTypeDef::Instance, __CORDIC_HandleTypeDef::Lock, __CORDIC_HandleTypeDef::MspDeInitCallback, __CORDIC_HandleTypeDef::NbCalcToGet, __CORDIC_HandleTypeDef::NbCalcToOrder, __CORDIC_HandleTypeDef::pInBuff, __CORDIC_HandleTypeDef::pOutBuff, and __CORDIC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CORDIC_Init ( CORDIC_HandleTypeDef * hcordic )

Initialize the CORDIC peripheral and the associated handle.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure.
Return values:
HAL status

Definition at line 201 of file stm32g4xx_hal_cordic.c.

References assert_param, __CORDIC_HandleTypeDef::CalculateCpltCallback, CORDIC_DMA_DIR_NONE, __CORDIC_HandleTypeDef::DMADirection, __CORDIC_HandleTypeDef::ErrorCallback, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_ERROR_NONE, HAL_CORDIC_ErrorCallback(), HAL_CORDIC_MspInit(), HAL_CORDIC_STATE_READY, HAL_CORDIC_STATE_RESET, __CORDIC_HandleTypeDef::Instance, __CORDIC_HandleTypeDef::Lock, __CORDIC_HandleTypeDef::MspInitCallback, __CORDIC_HandleTypeDef::NbCalcToGet, __CORDIC_HandleTypeDef::NbCalcToOrder, __CORDIC_HandleTypeDef::pInBuff, __CORDIC_HandleTypeDef::pOutBuff, and __CORDIC_HandleTypeDef::State.

void HAL_CORDIC_MspDeInit ( CORDIC_HandleTypeDef * hcordic )

DeInitialize the CORDIC MSP.

Parameters:
hcordic CORDIC handle
Return values:
None

Definition at line 340 of file stm32g4xx_hal_cordic.c.

References UNUSED.

Referenced by HAL_CORDIC_DeInit(), and HAL_CORDIC_UnRegisterCallback().

void HAL_CORDIC_MspInit ( CORDIC_HandleTypeDef * hcordic )

Initialize the CORDIC MSP.

Parameters:
hcordic CORDIC handle
Return values:
None

Definition at line 325 of file stm32g4xx_hal_cordic.c.

References UNUSED.

Referenced by HAL_CORDIC_Init(), and HAL_CORDIC_UnRegisterCallback().

HAL_StatusTypeDef HAL_CORDIC_RegisterCallback | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | HAL_CORDIC_CallbackIDTypeDef | CallbackID,
 |  | void(*)(CORDIC_HandleTypeDef *_hcordic) | pCallback
 | ) |  |

Register a CORDIC CallBack.

To be used instead of the weak predefined callback.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CORDIC_ERROR_CB_ID error Callback ID
  • HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
  • HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 365 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::CalculateCpltCallback, __CORDIC_HandleTypeDef::ErrorCallback, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_CALCULATE_CPLT_CB_ID, HAL_CORDIC_ERROR_CB_ID, HAL_CORDIC_ERROR_INVALID_CALLBACK, HAL_CORDIC_MSPDEINIT_CB_ID, HAL_CORDIC_MSPINIT_CB_ID, HAL_CORDIC_STATE_READY, HAL_CORDIC_STATE_RESET, __CORDIC_HandleTypeDef::MspDeInitCallback, __CORDIC_HandleTypeDef::MspInitCallback, and __CORDIC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CORDIC_RegisterCallback | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | HAL_CORDIC_CallbackIDTypeDef | CallbackID,
 |  | pCORDIC_CallbackTypeDef | pCallback
 | ) |  |
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | HAL_CORDIC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a CORDIC CallBack.

CORDIC callback is redirected to the weak predefined callback.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CORDIC_ERROR_CB_ID error Callback ID
  • HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
  • HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 456 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::CalculateCpltCallback, __CORDIC_HandleTypeDef::ErrorCallback, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_CALCULATE_CPLT_CB_ID, HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_ERROR_CB_ID, HAL_CORDIC_ERROR_INVALID_CALLBACK, HAL_CORDIC_ErrorCallback(), HAL_CORDIC_MspDeInit(), HAL_CORDIC_MSPDEINIT_CB_ID, HAL_CORDIC_MspInit(), HAL_CORDIC_MSPINIT_CB_ID, HAL_CORDIC_STATE_READY, HAL_CORDIC_STATE_RESET, __CORDIC_HandleTypeDef::MspDeInitCallback, __CORDIC_HandleTypeDef::MspInitCallback, and __CORDIC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORDIC Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_CORDIC_Configure (CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
Configure the CORDIC processing according to the specified parameters in the CORDIC_ConfigTypeDef structure.
HAL_StatusTypeDef | HAL_CORDIC_Calculate (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in polling mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_CalculateZO (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in Zero-Overhead mode (output data being read soon as input data are written), according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_IT (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
Carry out data of CORDIC processing in interrupt mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_DMA (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
Carry out input and/or output data of CORDIC processing in DMA mode, according to the existing CORDIC configuration.

Detailed Description

Control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the CORDIC peripheral: function, precision, scaling factor,
          number of input data and output data, size of input data and output data.
      (+) Calculate output data of CORDIC processing on input date, using the
          existing CORDIC configuration
    [..]  Four processing functions are available for calculation:
      (+) Polling mode
      (+) Polling mode, with Zero-Overhead register access
      (+) Interrupt mode
      (+) DMA mode

Function Documentation

HAL_StatusTypeDef HAL_CORDIC_Calculate | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | const int32_t * | pInBuff,
 |  | int32_t * | pOutBuff,
 |  | uint32_t | NbCalc,
 |  | uint32_t | Timeout
 | ) |  |

Carry out data of CORDIC processing in polling mode, according to the existing CORDIC configuration.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
pInBuff | Pointer to buffer containing input data for CORDIC processing.
pOutBuff | Pointer to buffer where output data of CORDIC processing will be stored.
NbCalc | Number of CORDIC calculation to process.
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 605 of file stm32g4xx_hal_cordic.c.

References CORDIC_ReadOutDataIncrementPtr(), CORDIC_WriteInDataIncrementPtr(), __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_NONE, HAL_CORDIC_ERROR_NOT_READY, HAL_CORDIC_ERROR_PARAM, HAL_CORDIC_ERROR_TIMEOUT, HAL_CORDIC_STATE_BUSY, HAL_CORDIC_STATE_READY, HAL_GetTick(), __CORDIC_HandleTypeDef::Instance, and __CORDIC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | const int32_t * | pInBuff,
 |  | int32_t * | pOutBuff,
 |  | uint32_t | NbCalc,
 |  | uint32_t | DMADirection
 | ) |  |

Carry out input and/or output data of CORDIC processing in DMA mode, according to the existing CORDIC configuration.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
pInBuff | Pointer to buffer containing input data for CORDIC processing.
pOutBuff | Pointer to buffer where output data of CORDIC processing will be stored.
NbCalc | Number of CORDIC calculation to process.
DMADirection Direction of DMA transfers. This parameter can be one of the following values:
  • CORDIC DMA direction CORDIC DMA direction
Note:
pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can be set to NULL value in this case.
pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the Peripheral.
Return values:
HAL status

Definition at line 884 of file stm32g4xx_hal_cordic.c.

References assert_param, CORDIC_DMA_DIR_IN, CORDIC_DMA_DIR_IN_OUT, CORDIC_DMA_DIR_OUT, CORDIC_DMA_REN, CORDIC_DMA_WEN, CORDIC_DMAError(), CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), __CORDIC_HandleTypeDef::DMADirection, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_DMA, HAL_CORDIC_ERROR_NONE, HAL_CORDIC_ERROR_NOT_READY, HAL_CORDIC_ERROR_PARAM, HAL_CORDIC_STATE_BUSY, HAL_CORDIC_STATE_READY, HAL_DMA_Start_IT(), __CORDIC_HandleTypeDef::hdmaIn, __CORDIC_HandleTypeDef::hdmaOut, __CORDIC_HandleTypeDef::Instance, IS_CORDIC_DMA_DIRECTION, __CORDIC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_CORDIC_Calculate_IT | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | const int32_t * | pInBuff,
 |  | int32_t * | pOutBuff,
 |  | uint32_t | NbCalc
 | ) |  |

Carry out data of CORDIC processing in interrupt mode, according to the existing CORDIC configuration.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
pInBuff | Pointer to buffer containing input data for CORDIC processing.
pOutBuff | Pointer to buffer where output data of CORDIC processing will be stored.
NbCalc | Number of CORDIC calculation to process.
Return values:
HAL status

Definition at line 792 of file stm32g4xx_hal_cordic.c.

References __HAL_CORDIC_ENABLE_IT, CORDIC_IT_IEN, __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_NONE, HAL_CORDIC_ERROR_NOT_READY, HAL_CORDIC_ERROR_PARAM, HAL_CORDIC_STATE_BUSY, HAL_CORDIC_STATE_READY, __CORDIC_HandleTypeDef::Instance, __CORDIC_HandleTypeDef::NbCalcToGet, __CORDIC_HandleTypeDef::NbCalcToOrder, __CORDIC_HandleTypeDef::pInBuff, __CORDIC_HandleTypeDef::pOutBuff, and __CORDIC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CORDIC_CalculateZO | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | const int32_t * | pInBuff,
 |  | int32_t * | pOutBuff,
 |  | uint32_t | NbCalc,
 |  | uint32_t | Timeout
 | ) |  |

Carry out data of CORDIC processing in Zero-Overhead mode (output data being read soon as input data are written), according to the existing CORDIC configuration.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module.
pInBuff | Pointer to buffer containing input data for CORDIC processing.
pOutBuff | Pointer to buffer where output data of CORDIC processing will be stored.
NbCalc | Number of CORDIC calculation to process.
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 699 of file stm32g4xx_hal_cordic.c.

References CORDIC_ReadOutDataIncrementPtr(), CORDIC_WriteInDataIncrementPtr(), __CORDIC_HandleTypeDef::ErrorCode, HAL_CORDIC_ERROR_NONE, HAL_CORDIC_ERROR_NOT_READY, HAL_CORDIC_ERROR_PARAM, HAL_CORDIC_ERROR_TIMEOUT, HAL_CORDIC_STATE_BUSY, HAL_CORDIC_STATE_READY, HAL_GetTick(), and __CORDIC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CORDIC_Configure | ( | CORDIC_HandleTypeDef * | hcordic,
 |  | const CORDIC_ConfigTypeDef * | sConfig
 | ) |  |

Configure the CORDIC processing according to the specified parameters in the CORDIC_ConfigTypeDef structure.

Parameters:
hcordic | pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
sConfig | pointer to a CORDIC_ConfigTypeDef structure that contains the CORDIC configuration information.
Return values:
HAL status

Definition at line 558 of file stm32g4xx_hal_cordic.c.

References assert_param, __CORDIC_HandleTypeDef::ErrorCode, CORDIC_ConfigTypeDef::Function, HAL_CORDIC_ERROR_NOT_READY, HAL_CORDIC_STATE_READY, CORDIC_ConfigTypeDef::InSize, __CORDIC_HandleTypeDef::Instance, IS_CORDIC_FUNCTION, IS_CORDIC_INSIZE, IS_CORDIC_NBREAD, IS_CORDIC_NBWRITE, IS_CORDIC_OUTSIZE, IS_CORDIC_PRECISION, IS_CORDIC_SCALE, CORDIC_ConfigTypeDef::NbRead, CORDIC_ConfigTypeDef::NbWrite, CORDIC_ConfigTypeDef::OutSize, CORDIC_ConfigTypeDef::Precision, CORDIC_ConfigTypeDef::Scale, and __CORDIC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Callback functions

Functions
Callback functions
CORDIC Exported Functions

Callback functions. More...

Functions

__weak void | HAL_CORDIC_ErrorCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC error callback.
__weak void | HAL_CORDIC_CalculateCpltCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC calculate complete callback.

Detailed Description

Callback functions.

  ==============================================================================
                      ##### Callback functions  #####
  ==============================================================================
    [..]  This section provides Interruption and DMA callback functions:
      (+) DMA or Interrupt calculate complete
      (+) DMA or Interrupt error

Function Documentation

void HAL_CORDIC_CalculateCpltCallback ( CORDIC_HandleTypeDef * hcordic )

CORDIC calculate complete callback.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
Return values:
None

Definition at line 1064 of file stm32g4xx_hal_cordic.c.

References UNUSED.

Referenced by CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), HAL_CORDIC_Init(), HAL_CORDIC_IRQHandler(), and HAL_CORDIC_UnRegisterCallback().

void HAL_CORDIC_ErrorCallback ( CORDIC_HandleTypeDef * hcordic )

CORDIC error callback.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
Return values:
None

Definition at line 1048 of file stm32g4xx_hal_cordic.c.

References UNUSED.

Referenced by CORDIC_DMAError(), HAL_CORDIC_Init(), and HAL_CORDIC_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRQ handler management

Functions
IRQ handler management
CORDIC Exported Functions

IRQ handler. More...

Functions

void HAL_CORDIC_IRQHandler (CORDIC_HandleTypeDef *hcordic)
Handle CORDIC interrupt request.

Detailed Description

IRQ handler.

  ==============================================================================
                ##### IRQ handler management #####
  ==============================================================================
[..]  This section provides IRQ handler function.

Function Documentation

void HAL_CORDIC_IRQHandler ( CORDIC_HandleTypeDef * hcordic )

Handle CORDIC interrupt request.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
Return values:
None

Definition at line 1097 of file stm32g4xx_hal_cordic.c.

References __HAL_CORDIC_DISABLE_IT, __HAL_CORDIC_GET_FLAG, __HAL_CORDIC_GET_IT_SOURCE, __CORDIC_HandleTypeDef::CalculateCpltCallback, CORDIC_FLAG_RRDY, CORDIC_IT_IEN, CORDIC_ReadOutDataIncrementPtr(), CORDIC_WriteInDataIncrementPtr(), HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_STATE_READY, __CORDIC_HandleTypeDef::NbCalcToGet, __CORDIC_HandleTypeDef::NbCalcToOrder, __CORDIC_HandleTypeDef::pInBuff, __CORDIC_HandleTypeDef::pOutBuff, and __CORDIC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CORDIC Exported Functions

Peripheral State functions. More...

Functions

HAL_CORDIC_StateTypeDef | HAL_CORDIC_GetState (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC handle state.
uint32_t | HAL_CORDIC_GetError (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC peripheral error.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_CORDIC_GetError ( const CORDIC_HandleTypeDef * hcordic )

Return the CORDIC peripheral error.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
Note:
The returned error is a bit-map combination of possible errors
Return values:
Error bit-map

Definition at line 1181 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::ErrorCode.

HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState ( const CORDIC_HandleTypeDef * hcordic )

Return the CORDIC handle state.

Parameters:
hcordic pointer to a CORDIC_HandleTypeDef structure that contains the configuration information for CORDIC module
Return values:
HAL state

Definition at line 1168 of file stm32g4xx_hal_cordic.c.

References __CORDIC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Types

Data Structures | Typedefs | Enumerations
CORDIC Exported Types
CORDIC

Data Structures

struct | __CORDIC_HandleTypeDef
CORDIC Handle Structure definition. More...
struct | CORDIC_ConfigTypeDef
CORDIC Config Structure definition. More...

Typedefs

typedef struct
__CORDIC_HandleTypeDef 		CORDIC_HandleTypeDef
CORDIC Handle Structure definition.
typedef void(* | pCORDIC_CallbackTypeDef )(CORDIC_HandleTypeDef *hcordic)
HAL CORDIC Callback pointer definition.

Enumerations

enum | HAL_CORDIC_StateTypeDef { HAL_CORDIC_STATE_RESET = 0x00U, HAL_CORDIC_STATE_READY = 0x01U, HAL_CORDIC_STATE_BUSY = 0x02U, HAL_CORDIC_STATE_ERROR = 0x03U }
CORDIC HAL State Structure definition. More...
enum | HAL_CORDIC_CallbackIDTypeDef { HAL_CORDIC_ERROR_CB_ID = 0x00U, HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, HAL_CORDIC_MSPINIT_CB_ID = 0x02U, HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U }
HAL CORDIC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __CORDIC_HandleTypeDef CORDIC_HandleTypeDef

CORDIC Handle Structure definition.

typedef void(* pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic)

HAL CORDIC Callback pointer definition.

pointer to a CORDIC callback function

Definition at line 144 of file stm32g4xx_hal_cordic.h.

Enumeration Type Documentation

enum HAL_CORDIC_CallbackIDTypeDef

HAL CORDIC Callback ID enumeration definition.

Enumerator:
HAL_CORDIC_ERROR_CB_ID

CORDIC error callback ID

HAL_CORDIC_CALCULATE_CPLT_CB_ID

CORDIC calculate complete callback ID

HAL_CORDIC_MSPINIT_CB_ID

CORDIC MspInit callback ID

HAL_CORDIC_MSPDEINIT_CB_ID

CORDIC MspDeInit callback ID

Definition at line 131 of file stm32g4xx_hal_cordic.h.

enum HAL_CORDIC_StateTypeDef

CORDIC HAL State Structure definition.

Enumerator:
HAL_CORDIC_STATE_RESET

CORDIC not yet initialized or disabled

HAL_CORDIC_STATE_READY

CORDIC initialized and ready for use

HAL_CORDIC_STATE_BUSY

CORDIC internal process is ongoing

HAL_CORDIC_STATE_ERROR

CORDIC error state

Definition at line 48 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __CORDIC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CORDIC_HandleTypeDef Struct Reference
CORDIC Exported Types

CORDIC Handle Structure definition. More...

#include <stm32g4xx_hal_cordic.h>

Data Fields

CORDIC_TypeDef * | Instance
const int32_t * | pInBuff
int32_t * | pOutBuff
uint32_t | NbCalcToOrder
uint32_t | NbCalcToGet
uint32_t | DMADirection
DMA_HandleTypeDef * hdmaIn
DMA_HandleTypeDef * hdmaOut
HAL_LockTypeDef | Lock
__IO HAL_CORDIC_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | ErrorCallback )(struct __CORDIC_HandleTypeDef *hcordic)
void(* | CalculateCpltCallback )(struct __CORDIC_HandleTypeDef *hcordic)
void(* | MspInitCallback )(struct __CORDIC_HandleTypeDef *hcordic)
void(* | MspDeInitCallback )(struct __CORDIC_HandleTypeDef *hcordic)

Detailed Description

CORDIC Handle Structure definition.

Definition at line 60 of file stm32g4xx_hal_cordic.h.

Field Documentation

void(* __CORDIC_HandleTypeDef::CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic)

CORDIC calculate complete callback

Definition at line 90 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), HAL_CORDIC_Init(), HAL_CORDIC_IRQHandler(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

uint32_t __CORDIC_HandleTypeDef::DMADirection

Direction of CORDIC DMA transfers

Definition at line 75 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_DeInit(), and HAL_CORDIC_Init().

void(* __CORDIC_HandleTypeDef::ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic)

CORDIC error callback

Definition at line 89 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAError(), HAL_CORDIC_Init(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

__IO uint32_t __CORDIC_HandleTypeDef::ErrorCode

CORDIC peripheral error code This parameter can be a value of CORDIC Error code

Definition at line 85 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAError(), HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), HAL_CORDIC_CalculateZO(), HAL_CORDIC_Configure(), HAL_CORDIC_DeInit(), HAL_CORDIC_GetError(), HAL_CORDIC_Init(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

DMA_HandleTypeDef* __CORDIC_HandleTypeDef::hdmaIn

CORDIC peripheral input data DMA handle parameters

Definition at line 77 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_DMA().

DMA_HandleTypeDef* __CORDIC_HandleTypeDef::hdmaOut

CORDIC peripheral output data DMA handle parameters

Definition at line 79 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_DMA().

CORDIC_TypeDef* __CORDIC_HandleTypeDef::Instance

Register base address

Definition at line 65 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), CORDIC_ReadOutDataIncrementPtr(), CORDIC_WriteInDataIncrementPtr(), HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), HAL_CORDIC_Configure(), HAL_CORDIC_DeInit(), and HAL_CORDIC_Init().

HAL_LockTypeDef __CORDIC_HandleTypeDef::Lock

CORDIC locking object

Definition at line 81 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_DeInit(), and HAL_CORDIC_Init().

void(* __CORDIC_HandleTypeDef::MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic)

CORDIC Msp DeInit callback

Definition at line 93 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_DeInit(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

void(* __CORDIC_HandleTypeDef::MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic)

CORDIC Msp Init callback

Definition at line 92 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Init(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

uint32_t __CORDIC_HandleTypeDef::NbCalcToGet

Remaining number of calculation result to get

Definition at line 73 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT(), HAL_CORDIC_DeInit(), HAL_CORDIC_Init(), and HAL_CORDIC_IRQHandler().

uint32_t __CORDIC_HandleTypeDef::NbCalcToOrder

Remaining number of calculation to order

Definition at line 71 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT(), HAL_CORDIC_DeInit(), HAL_CORDIC_Init(), and HAL_CORDIC_IRQHandler().

const int32_t* __CORDIC_HandleTypeDef::pInBuff

Pointer to CORDIC input data buffer

Definition at line 67 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT(), HAL_CORDIC_DeInit(), HAL_CORDIC_Init(), and HAL_CORDIC_IRQHandler().

int32_t* __CORDIC_HandleTypeDef::pOutBuff

Pointer to CORDIC output data buffer

Definition at line 69 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT(), HAL_CORDIC_DeInit(), HAL_CORDIC_Init(), and HAL_CORDIC_IRQHandler().

__IO HAL_CORDIC_StateTypeDef __CORDIC_HandleTypeDef::State

CORDIC state

Definition at line 83 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAError(), CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), HAL_CORDIC_CalculateZO(), HAL_CORDIC_Configure(), HAL_CORDIC_DeInit(), HAL_CORDIC_GetState(), HAL_CORDIC_Init(), HAL_CORDIC_IRQHandler(), HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_cordic.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CORDIC_ConfigTypeDef Struct Reference
CORDIC Exported Types

CORDIC Config Structure definition. More...

#include <stm32g4xx_hal_cordic.h>

Data Fields

uint32_t | Function
uint32_t | Scale
uint32_t | InSize
uint32_t | OutSize
uint32_t | NbWrite
uint32_t | NbRead
uint32_t | Precision

Detailed Description

CORDIC Config Structure definition.

Definition at line 102 of file stm32g4xx_hal_cordic.h.

Field Documentation

uint32_t CORDIC_ConfigTypeDef::Function

Function This parameter can be a value of CORDIC Function

Definition at line 104 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::InSize

Width of input data This parameter can be a value of CORDIC input data size

Definition at line 110 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::NbRead

Number of 32-bit read expected after one calculation This parameter can be a value of CORDIC Number of 32-bit read required after one calculation

Definition at line 119 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::NbWrite

Number of 32-bit write expected for one calculation This parameter can be a value of CORDIC Number of 32-bit write required for one calculation

Definition at line 116 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::OutSize

Width of output data This parameter can be a value of CORDIC Results Size

Definition at line 113 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::Precision

Number of cycles for calculation This parameter can be a value of CORDIC Precision in Cycles Number

Definition at line 122 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

uint32_t CORDIC_ConfigTypeDef::Scale

Scaling factor This parameter can be a value of CORDIC Scaling factor

Definition at line 107 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_cordic.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Error code

Defines
CORDIC Error code
CORDIC Exported Constants

Defines

#define | HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U)
#define | HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)

Define Documentation

#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U)

DMA error

Definition at line 165 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAError(), and HAL_CORDIC_Calculate_DMA().

#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)

Invalid Callback error

Definition at line 167 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_RegisterCallback(), and HAL_CORDIC_UnRegisterCallback().

#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 161 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), HAL_CORDIC_CalculateZO(), HAL_CORDIC_DeInit(), and HAL_CORDIC_Init().

#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U)

Peripheral not ready

Definition at line 163 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), HAL_CORDIC_CalculateZO(), and HAL_CORDIC_Configure().

#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U)

Wrong parameter error

Definition at line 162 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Calculate_IT(), and HAL_CORDIC_CalculateZO().

#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U)

Timeout error

Definition at line 164 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate(), and HAL_CORDIC_CalculateZO().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Function

Defines
CORDIC Function
CORDIC Exported Constants

Defines

#define | CORDIC_FUNCTION_COSINE (0x00000000U)
#define | CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))
#define | CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))
#define | CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))
#define | CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))
#define | CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))

Define Documentation

#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))

Arctangent

Definition at line 180 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_COSINE (0x00000000U)

Cosine

Definition at line 176 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))

Hyperbolic Arctangent

Definition at line 183 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))

Hyperbolic Cosine

Definition at line 181 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))

Hyperbolic Sine

Definition at line 182 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))

Modulus

Definition at line 179 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))

Natural Logarithm

Definition at line 184 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))

Phase

Definition at line 178 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))

Sine

Definition at line 177 of file stm32g4xx_hal_cordic.h.

#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))

Square Root

Definition at line 185 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Precision in Cycles Number

Defines
CORDIC Precision in Cycles Number
CORDIC Exported Constants

Defines

#define | CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define | CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_7CYCLES
#define | CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define | CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_11CYCLES
#define | CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define | CORDIC_PRECISION_13CYCLES
#define | CORDIC_PRECISION_14CYCLES
#define | CORDIC_PRECISION_15CYCLES

Define Documentation

#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))

Definition at line 204 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_11CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 205 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))

Definition at line 207 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_13CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))

Definition at line 208 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_14CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))

Definition at line 210 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_15CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
                                                |CORDIC_CSR_PRECISION_0))

Definition at line 212 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))

Definition at line 194 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))

Definition at line 195 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 196 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))

Definition at line 197 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))

Definition at line 198 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))

Definition at line 199 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_7CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_2\
                                                | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 200 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))

Definition at line 202 of file stm32g4xx_hal_cordic.h.

#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))

Definition at line 203 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Scaling factor

Defines
CORDIC Scaling factor
CORDIC Exported Constants

Defines

#define | CORDIC_SCALE_0 (0x00000000U)
#define | CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define | CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define | CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define | CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Define Documentation

#define CORDIC_SCALE_0 (0x00000000U)

Definition at line 224 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))

Definition at line 225 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))

Definition at line 226 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Definition at line 227 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))

Definition at line 228 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))

Definition at line 229 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))

Definition at line 230 of file stm32g4xx_hal_cordic.h.

#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Definition at line 231 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Interrupts Enable bit

Defines
CORDIC Interrupts Enable bit
CORDIC Exported Constants

Defines

#define CORDIC_IT_IEN CORDIC_CSR_IEN

Define Documentation

#define CORDIC_IT_IEN CORDIC_CSR_IEN

Result ready interrupt enable

Definition at line 239 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT(), and HAL_CORDIC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Read Request Enable bit

Defines
DMA Read Request Enable bit
CORDIC Exported Constants

Defines

#define CORDIC_DMA_REN CORDIC_CSR_DMAREN

Define Documentation

#define CORDIC_DMA_REN CORDIC_CSR_DMAREN

DMA Read requests enable

Definition at line 247 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAOutCplt(), and HAL_CORDIC_Calculate_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Write Request Enable bit

Defines
DMA Write Request Enable bit
CORDIC Exported Constants

Defines

#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN

Define Documentation

#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN

DMA Write channel enable

Definition at line 255 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), and HAL_CORDIC_Calculate_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Number of 32-bit write required for one calculation

Defines
CORDIC Number of 32-bit write required for one calculation
CORDIC Exported Constants

Defines

#define | CORDIC_NBWRITE_1 (0x00000000U)
#define | CORDIC_NBWRITE_2 CORDIC_CSR_NARGS

Define Documentation

#define CORDIC_NBWRITE_1 (0x00000000U)

One 32-bits write containing either only one 32-bit data input (Q1.31 format), or two 16-bit data input (Q1.15 format) packed in one 32 bits Data

Definition at line 263 of file stm32g4xx_hal_cordic.h.

#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS

Two 32-bit write containing two 32-bits data input (Q1.31 format)

Definition at line 267 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Number of 32-bit read required after one calculation

Defines
CORDIC Number of 32-bit read required after one calculation
CORDIC Exported Constants

Defines

#define | CORDIC_NBREAD_1 (0x00000000U)
#define | CORDIC_NBREAD_2 CORDIC_CSR_NRES

Define Documentation

#define CORDIC_NBREAD_1 (0x00000000U)

One 32-bits read containing either only one 32-bit data output (Q1.31 format), or two 16-bit data output (Q1.15 format) packed in one 32 bits Data

Definition at line 276 of file stm32g4xx_hal_cordic.h.

#define CORDIC_NBREAD_2 CORDIC_CSR_NRES

Two 32-bit Data containing two 32-bits data output (Q1.31 format)

Definition at line 280 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC input data size

Defines
CORDIC input data size
CORDIC Exported Constants

Defines

#define | CORDIC_INSIZE_32BITS (0x00000000U)
#define | CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE

Define Documentation

#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE

16 bits input data size (Q1.15 format)

Definition at line 290 of file stm32g4xx_hal_cordic.h.

#define CORDIC_INSIZE_32BITS (0x00000000U)

32 bits input data size (Q1.31 format)

Definition at line 289 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Results Size

Defines
CORDIC Results Size
CORDIC Exported Constants

Defines

#define | CORDIC_OUTSIZE_32BITS (0x00000000U)
#define | CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE

Define Documentation

#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE

16 bits output data size (Q1.15 format)

Definition at line 299 of file stm32g4xx_hal_cordic.h.

#define CORDIC_OUTSIZE_32BITS (0x00000000U)

32 bits output data size (Q1.31 format)

Definition at line 298 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC status flags

Defines
CORDIC status flags
CORDIC Exported Constants

Defines

#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY

Define Documentation

#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY

Result Ready Flag

Definition at line 307 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC DMA direction

Defines
CORDIC DMA direction
CORDIC Exported Constants

Defines

#define | CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U)
#define | CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U)
#define | CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U)
#define | CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U)

Define Documentation

#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U)

DMA direction : Input of CORDIC

Definition at line 316 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), and HAL_CORDIC_Calculate_DMA().

#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U)

DMA direction : Input and Output of CORDIC

Definition at line 318 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_DMA().

#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U)

DMA direction : none

Definition at line 315 of file stm32g4xx_hal_cordic.h.

Referenced by CORDIC_DMAInCplt(), CORDIC_DMAOutCplt(), HAL_CORDIC_DeInit(), and HAL_CORDIC_Init().

#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U)

DMA direction : Output of CORDIC

Definition at line 317 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Macros

Defines
CORDIC Exported Macros
CORDIC

Defines

#define | __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__)
Reset CORDIC handle state.
#define | __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
Enable the CORDIC interrupt when result is ready.
#define | __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
Disable the CORDIC interrupt.
#define | __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Check whether the specified CORDIC interrupt occurred or not.
#define | __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Clear specified CORDIC interrupt status.
#define | __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
Check whether the specified CORDIC status flag is set or not.
#define | __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
Clear specified CORDIC status flag.
#define | __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
Check whether the specified CORDIC interrupt is enabled or not.

Define Documentation

#define __HAL_CORDIC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* Dummy macro */

Clear specified CORDIC status flag.

Dummy macro as no flag can be cleared.

Parameters:
__HANDLE__ CORDIC handle.
__FLAG__ CORDIC flag to clear This parameter can be one of the following values:
  • CORDIC_FLAG_RRDY Result Ready Flag
Return values:
None

Definition at line 403 of file stm32g4xx_hal_cordic.h.

#define __HAL_CORDIC_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | /* Dummy macro */

Clear specified CORDIC interrupt status.

Dummy macro as no interrupt status flag.

Parameters:
__HANDLE__ | CORDIC handle.
__INTERRUPT__ | CORDIC interrupt to clear
Return values:
None

Definition at line 383 of file stm32g4xx_hal_cordic.h.

#define __HAL_CORDIC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))

Disable the CORDIC interrupt.

Parameters:
__HANDLE__ CORDIC handle.
__INTERRUPT__ CORDIC Interrupt. This parameter can be one of the following values:
  • CORDIC_IT_IEN Enable Interrupt
Return values:
None

Definition at line 366 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_IRQHandler().

#define __HAL_CORDIC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))

Enable the CORDIC interrupt when result is ready.

Parameters:
__HANDLE__ CORDIC handle.
__INTERRUPT__ CORDIC Interrupt. This parameter can be one of the following values:
  • CORDIC_IT_IEN Enable Interrupt
Return values:
None

Definition at line 355 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_IT().

#define __HAL_CORDIC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))

Check whether the specified CORDIC status flag is set or not.

Parameters:
__HANDLE__ CORDIC handle.
__FLAG__ CORDIC flag to check This parameter can be one of the following values:
  • CORDIC_FLAG_RRDY Result Ready Flag
Return values:
SET (flag is set) or RESET (flag is reset)

Definition at line 392 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_IRQHandler().

#define __HAL_CORDIC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | /* Dummy macro */

Check whether the specified CORDIC interrupt occurred or not.

Dummy macro as no interrupt status flag.

Parameters:
__HANDLE__ | CORDIC handle.
__INTERRUPT__ | CORDIC interrupt to check
Return values:
SET (interrupt occurred) or RESET (interrupt did not occurred)

Definition at line 375 of file stm32g4xx_hal_cordic.h.

#define __HAL_CORDIC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))

Check whether the specified CORDIC interrupt is enabled or not.

Parameters:
__HANDLE__ CORDIC handle.
__INTERRUPT__ CORDIC interrupt to check This parameter can be one of the following values:
  • CORDIC_IT_IEN Enable Interrupt
Return values:
FlagStatus

Definition at line 412 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_IRQHandler().

#define __HAL_CORDIC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                \
                                                        (__HANDLE__)->State = HAL_CORDIC_STATE_RESET;   \
                                                        (__HANDLE__)->MspInitCallback = NULL;           \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                      } while(0)

Reset CORDIC handle state.

Parameters:
__HANDLE__ CORDIC handle
Return values:
None

Definition at line 338 of file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Private Macros

Defines
CORDIC Private Macros
CORDIC

Defines

#define | IS_CORDIC_FUNCTION(__FUNCTION__)
Verify the CORDIC function.
#define | IS_CORDIC_PRECISION(__PRECISION__)
Verify the CORDIC precision.
#define | IS_CORDIC_SCALE(__SCALE__)
Verify the CORDIC scaling factor.
#define | IS_CORDIC_NBWRITE(__NBWRITE__)
Verify the CORDIC number of 32-bits write expected for one calculation.
#define | IS_CORDIC_NBREAD(__NBREAD__)
Verify the CORDIC number of 32-bits read expected after one calculation.
#define | IS_CORDIC_INSIZE(__INSIZE__)
Verify the CORDIC input data size for one calculation.
#define | IS_CORDIC_OUTSIZE(__OUTSIZE__)
Verify the CORDIC output data size for one calculation.
#define | IS_CORDIC_DMA_DIRECTION(__DMADIR__)
Verify the CORDIC DMA transfer Direction.

Define Documentation

#define IS_CORDIC_DMA_DIRECTION ( __DMADIR__ )
Value:
(((__DMADIR__) == CORDIC_DMA_DIR_IN)  || \
                                             ((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
                                             ((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))

Verify the CORDIC DMA transfer Direction.

Parameters:
__DMADIR__ DMA transfer direction.
Return values:
SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)

Definition at line 513 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Calculate_DMA().

#define IS_CORDIC_FUNCTION ( __FUNCTION__ )
Value:
(((__FUNCTION__) == CORDIC_FUNCTION_COSINE)       || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_SINE)         || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_PHASE)        || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS)      || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT)   || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE)      || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_HSINE)        || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT)  || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG)   || \
                                          ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))

Verify the CORDIC function.

Parameters:
__FUNCTION__ Name of the function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 429 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_INSIZE ( __INSIZE__ )
Value:
(((__INSIZE__) == CORDIC_INSIZE_32BITS)  || \
                                      ((__INSIZE__) == CORDIC_INSIZE_16BITS))

Verify the CORDIC input data size for one calculation.

Parameters:
__INSIZE__ input data size for one calculation.
Return values:
SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)

Definition at line 497 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_NBREAD ( __NBREAD__ )
Value:
(((__NBREAD__) == CORDIC_NBREAD_1)  || \
                                      ((__NBREAD__) == CORDIC_NBREAD_2))

Verify the CORDIC number of 32-bits read expected after one calculation.

Parameters:
__NBREAD__ Number of 32-bits read expected after one calculation.
Return values:
SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)

Definition at line 489 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_NBWRITE ( __NBWRITE__ )
Value:
(((__NBWRITE__) == CORDIC_NBWRITE_1)  || \
                                        ((__NBWRITE__) == CORDIC_NBWRITE_2))

Verify the CORDIC number of 32-bits write expected for one calculation.

Parameters:
__NBWRITE__ Number of 32-bits write expected for one calculation.
Return values:
SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)

Definition at line 481 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_OUTSIZE ( __OUTSIZE__ )
Value:
(((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS)  || \
                                        ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))

Verify the CORDIC output data size for one calculation.

Parameters:
__OUTSIZE__ output data size for one calculation.
Return values:
SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)

Definition at line 505 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_PRECISION ( __PRECISION__ )
Value:
(((__PRECISION__) == CORDIC_PRECISION_1CYCLE)   || \
                                            ((__PRECISION__) == CORDIC_PRECISION_2CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_3CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_4CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_5CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_6CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_7CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_8CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_9CYCLES)  || \
                                            ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
                                            ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
                                            ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
                                            ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
                                            ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
                                            ((__PRECISION__) == CORDIC_PRECISION_15CYCLES))

Verify the CORDIC precision.

Parameters:
__PRECISION__ CORDIC Precision in Cycles Number.
Return values:
SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)

Definition at line 446 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

#define IS_CORDIC_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == CORDIC_SCALE_0)  || \
                                    ((__SCALE__) == CORDIC_SCALE_1)  || \
                                    ((__SCALE__) == CORDIC_SCALE_2)  || \
                                    ((__SCALE__) == CORDIC_SCALE_3)  || \
                                    ((__SCALE__) == CORDIC_SCALE_4)  || \
                                    ((__SCALE__) == CORDIC_SCALE_5)  || \
                                    ((__SCALE__) == CORDIC_SCALE_6)  || \
                                    ((__SCALE__) == CORDIC_SCALE_7))

Verify the CORDIC scaling factor.

Parameters:
__SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
Return values:
SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)

Definition at line 467 of file stm32g4xx_hal_cordic.h.

Referenced by HAL_CORDIC_Configure().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32g4xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 48 of file stm32g4xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 61 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 54 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 63 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 50 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 69 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 67 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 65 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 52 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 55 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 57 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of CORTEX MPU TEX Levels

Definition at line 59 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 0x00000007U
#define | NVIC_PRIORITYGROUP_1 0x00000006U
#define | NVIC_PRIORITYGROUP_2 0x00000005U
#define | NVIC_PRIORITYGROUP_3 0x00000004U
#define | NVIC_PRIORITYGROUP_4 0x00000003U

Define Documentation

#define NVIC_PRIORITYGROUP_0 0x00000007U

0 bit for pre-emption priority, 4 bits for subpriority

Definition at line 90 of file stm32g4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 0x00000006U

1 bit for pre-emption priority, 3 bits for subpriority

Definition at line 92 of file stm32g4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 0x00000005U

2 bits for pre-emption priority, 2 bits for subpriority

Definition at line 94 of file stm32g4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 0x00000004U

3 bits for pre-emption priority, 1 bit for subpriority

Definition at line 96 of file stm32g4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 0x00000003U

4 bits for pre-emption priority, 0 bit for subpriority

Definition at line 98 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK 0x00000004U

Definition at line 108 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

Definition at line 107 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU HFNMI and PRIVILEGED Access control

Defines
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)

Definition at line 119 of file stm32g4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 121 of file stm32g4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U

Definition at line 118 of file stm32g4xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 120 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 130 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 129 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 139 of file stm32g4xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 138 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 148 of file stm32g4xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 147 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 156 of file stm32g4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 157 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 165 of file stm32g4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 166 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU TEX Levels

Defines
CORTEX MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_TEX_LEVEL4 ((uint8_t)0x04)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 174 of file stm32g4xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 175 of file stm32g4xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 176 of file stm32g4xx_hal_cortex.h.

#define MPU_TEX_LEVEL4 ((uint8_t)0x04)

Definition at line 177 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 187 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 197 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 207 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 194 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 204 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 210 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 190 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 200 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 188 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 198 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 208 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 211 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 191 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 201 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 185 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 195 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 205 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 212 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 192 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 202 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 189 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 199 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 209 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 186 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 196 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 206 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 193 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 203 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 223 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 220 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 224 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 225 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 221 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 222 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 233 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 234 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 235 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 236 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 237 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 238 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 239 of file stm32g4xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 240 of file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      SysTick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
None

Definition at line 223 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enable a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
None

Definition at line 207 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Set the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
PreemptPriority,: The pre-emption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 185 of file stm32g4xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 163 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiate a system reset request to reset the MCU.

Return values:
None

Definition at line 236 of file stm32g4xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 249 of file stm32g4xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initialize and configure the Region and the memory to be protected.

Parameters:
MPU_Init,: Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 461 of file stm32g4xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_MPU_Disable ( void )

Disable the MPU.

Return values:
None

Definition at line 445 of file stm32g4xx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enable the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged accessto the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 430 of file stm32g4xx_hal_cortex.c.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clear the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
None

Definition at line 353 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Get active interrupt (read the active register in NVIC and return the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 370 of file stm32g4xx_hal_cortex.c.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 337 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Get the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 304 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Get the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 277 of file stm32g4xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Set Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
Return values:
None

Definition at line 319 of file stm32g4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 411 of file stm32g4xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configure the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 384 of file stm32g4xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

Handle SYSTICK interrupt request.

Return values:
None

Definition at line 402 of file stm32g4xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 343 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 340 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 337 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 334 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 331 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 358 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 351 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 367 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FF)

Definition at line 396 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2)  || \
                                ((TYPE) == MPU_TEX_LEVEL4))

Definition at line 346 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) > SysTick_IRQn)

Definition at line 325 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 321 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 315 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 323 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 327 of file stm32g4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 483 of file stm32g4xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 432 of file stm32g4xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 179 of file stm32g4xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 103 of file stm32g4xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 238 of file stm32g4xx_hal_crc.c.

References UNUSED.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 223 of file stm32g4xx_hal_crc.c.

References UNUSED.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

       [..]  or

      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 287 of file stm32g4xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 339 of file stm32g4xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (const CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( const CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc CRC handle
Return values:
HAL state

Definition at line 406 of file stm32g4xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 46 of file stm32g4xx_hal_crc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32g4xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 58 of file stm32g4xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the peripheral and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 79 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 68 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 60 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal, representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 73 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 86 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 89 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 99 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_crc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32g4xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 109 of file stm32g4xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 113 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 119 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 111 of file stm32g4xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 115 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 117 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_crc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7U

X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1

Definition at line 144 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Initial CRC default value

Definition at line 152 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Disable default generating polynomial 0x04C11DB7

Definition at line 161 of file stm32g4xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Enable default generating polynomial 0x04C11DB7

Definition at line 160 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Disable initial CRC default value

Definition at line 170 of file stm32g4xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Enable initial CRC default value

Definition at line 169 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Polynomial sizes to configure the peripheral

Defines
Polynomial sizes to configure the peripheral
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Define Documentation

#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

Resort to a 16-bit long generating polynomial

Definition at line 179 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B 0x00000000U

Resort to a 32-bit long generating polynomial

Definition at line 178 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Resort to a 7-bit long generating polynomial

Definition at line 181 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

Resort to a 8-bit long generating polynomial

Definition at line 180 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U

Define Documentation

#define HAL_CRC_LENGTH_16B 16U

16-bit long CRC

Definition at line 190 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32U

32-bit long CRC

Definition at line 189 of file stm32g4xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7U

7-bit long CRC

Definition at line 192 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8U

8-bit long CRC

Definition at line 191 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U

Input data in byte format

Definition at line 205 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U

Input data in half-word format

Definition at line 206 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U

Undefined input data format

Definition at line 204 of file stm32g4xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Input data in word format

Definition at line 207 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 232 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the data stored in the Independent Data (ID) register.

Parameters:
__HANDLE__ CRC handle
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
Value of the ID register

Definition at line 257 of file stm32g4xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | CRC handle
__INIT__ | 32-bit initial value
Return values:
None

Definition at line 240 of file stm32g4xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__ CRC handle.
Return values:
None

Definition at line 225 of file stm32g4xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store data in the Independent Data (ID) register.

Parameters:
__HANDLE__ | CRC handle
__VALUE__ | Value to be stored in the ID register
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
None

Definition at line 249 of file stm32g4xx_hal_crc.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 279 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 274 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 271 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 268 of file stm32g4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Initialization/de-initialization functions

Functions
Extended Initialization/de-initialization functions
CRC Extended Exported Functions

Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc CRC handle
InputReverseMode Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
Return values:
HAL status

Definition at line 168 of file stm32g4xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc CRC handle
OutputReverseMode Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 194 of file stm32g4xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc CRC handle
Pol CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 89 of file stm32g4xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Data Inversion Modes

Defines
Input Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0

Byte-wise input data inversion

Definition at line 48 of file stm32g4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1

HalfWord-wise input data inversion

Definition at line 49 of file stm32g4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U

No input data inversion

Definition at line 47 of file stm32g4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Word-wise input data inversion

Definition at line 50 of file stm32g4xx_hal_crc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Data Inversion Modes

Defines
Output Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U

No output data inversion

Definition at line 58 of file stm32g4xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Bit-wise output data inversion

Definition at line 59 of file stm32g4xx_hal_crc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Extended Exported Macros

Defines
CRC Extended Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 85 of file stm32g4xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 78 of file stm32g4xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ | CRC handle
__POLYNOMIAL__ | 7, 8, 16 or 32-bit polynomial
Return values:
None

Definition at line 93 of file stm32g4xx_hal_crc_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Extended Private Macros

Defines
CRC Extended Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 104 of file stm32g4xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 109 of file stm32g4xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 466 of file stm32g4xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::MspDeInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 405 of file stm32g4xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_NONE, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::Lock, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 527 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 511 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.

Note:
The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1447 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.

Note:
The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1559 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 1011 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 1027 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 1059 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 1043 of file stm32g4xx_hal_dac.c.

References UNUSED.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 888 of file stm32g4xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_DISABLE_IT, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.

Note:
The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1447 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Alignment Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data | Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 967 of file stm32g4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 572 of file stm32g4xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, DAC_DELAY_STARTUP_US, DAC_TRIGGER_SOFTWARE, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
pData | The source Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 688 of file stm32g4xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DELAY_STARTUP_US, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 647 of file stm32g4xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 834 of file stm32g4xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.

Note:
The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1559 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_DAC_GetValue (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | const DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Note:
By calling this function, the high frequency interface mode (HFSEL bits) will be set. This parameter scope is the DAC instance. As the function is called for each channel, the DAC high frequency interface mode of
  • sConfig must be the same at each call. (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 1144 of file stm32g4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_CHIPCONNECT_EXTERNAL, DAC_CHIPCONNECT_INTERNAL, DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral, DAC_ChannelConfTypeDef::DAC_DMADoubleDataMode, DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ, DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ, DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC, DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE, DAC_ChannelConfTypeDef::DAC_HighFrequency, DAC_SampleAndHoldConfTypeDef::DAC_HoldTime, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_OUTPUTBUFFER_ENABLE, DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime, DAC_ChannelConfTypeDef::DAC_SampleAndHold, DAC_SAMPLEANDHOLD_ENABLE, DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig, DAC_SampleAndHoldConfTypeDef::DAC_SampleTime, DAC_ChannelConfTypeDef::DAC_SignedFormat, DAC_ChannelConfTypeDef::DAC_Trigger, DAC_ChannelConfTypeDef::DAC_Trigger2, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_TIMEOUT, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_TIMEOUT, HAL_GetTick(), HAL_RCC_GetHCLKFreq(), HFSEL_ENABLE_THRESHOLD_160MHZ, HFSEL_ENABLE_THRESHOLD_80MHZ, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_CHIP_CONNECTION, IS_DAC_HIGH_FREQUENCY_MODE, IS_DAC_HOLDTIME, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_REFRESHTIME, IS_DAC_SAMPLEANDHOLD, IS_DAC_SAMPLETIME, IS_DAC_TRIGGER, IS_DAC_TRIGGER2, IS_DAC_TRIMMING, IS_DAC_TRIMMINGVALUE, __DAC_HandleTypeDef::State, and TIMEOUT_DAC_CALIBCONFIG.

uint32_t HAL_DAC_GetValue | ( | const DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
The selected DAC channel data output value.

Definition at line 1101 of file stm32g4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (const DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (const DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( const DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 1403 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( const DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 1390 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Types

Data Structures | Typedefs | Enumerations
DAC Exported Types
DAC

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __DAC_HandleTypeDef DAC_HandleTypeDef

DAC handle Structure definition.

typedef void(* pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac)

HAL DAC Callback pointer definition.

Definition at line 183 of file stm32g4xx_hal_dac.h.

Enumeration Type Documentation

enum HAL_DAC_CallbackIDTypeDef

HAL DAC Callback ID enumeration definition.

Enumerator:
HAL_DAC_CH1_COMPLETE_CB_ID

DAC CH1 Complete Callback ID

HAL_DAC_CH1_HALF_COMPLETE_CB_ID

DAC CH1 half Complete Callback ID

HAL_DAC_CH1_ERROR_ID

DAC CH1 error Callback ID

HAL_DAC_CH1_UNDERRUN_CB_ID

DAC CH1 underrun Callback ID

HAL_DAC_CH2_COMPLETE_CB_ID

DAC CH2 Complete Callback ID

HAL_DAC_CH2_HALF_COMPLETE_CB_ID

DAC CH2 half Complete Callback ID

HAL_DAC_CH2_ERROR_ID

DAC CH2 error Callback ID

HAL_DAC_CH2_UNDERRUN_CB_ID

DAC CH2 underrun Callback ID

HAL_DAC_MSPINIT_CB_ID

DAC MspInit Callback ID

HAL_DAC_MSPDEINIT_CB_ID

DAC MspDeInit Callback ID

HAL_DAC_ALL_CB_ID

DAC All ID

Definition at line 163 of file stm32g4xx_hal_dac.h.

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 49 of file stm32g4xx_hal_dac.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32g4xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode
void(* | ConvCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | MspInitCallback )(struct __DAC_HandleTypeDef *hdac)
void(* | MspDeInitCallback )(struct __DAC_HandleTypeDef *hdac)

Detailed Description

DAC handle Structure definition.

Definition at line 63 of file stm32g4xx_hal_dac.h.

Field Documentation

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 81 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 86 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 82 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 87 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 74 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 76 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 84 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 89 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 83 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 88 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO uint32_t __DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 78 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start_DMA(), HAL_DAC_UnRegisterCallback(), and HAL_DACEx_DualStart_DMA().

DAC_TypeDef* __DAC_HandleTypeDef::Instance

Register base address

Definition at line 68 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SawtoothWaveDataReset(), HAL_DACEx_SawtoothWaveDataStep(), HAL_DACEx_SawtoothWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef __DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 72 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Init().

void(* __DAC_HandleTypeDef::MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 93 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::MspInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 92 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO HAL_DAC_StateTypeDef __DAC_HandleTypeDef::State

DAC communication state

Definition at line 70 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DAC_UnRegisterCallback(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SawtoothWaveDataReset(), HAL_DACEx_SawtoothWaveDataStep(), HAL_DACEx_SawtoothWaveGenerate(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dac.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC_SampleAndHoldConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_SampleAndHoldConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration sample and hold Channel structure definition. More...

#include <stm32g4xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleTime
uint32_t | DAC_HoldTime
uint32_t | DAC_RefreshTime

Detailed Description

DAC Configuration sample and hold Channel structure definition.

Definition at line 101 of file stm32g4xx_hal_dac.h.

Field Documentation

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_HoldTime

Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 107 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime

Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255

Definition at line 111 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_SampleTime

Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 103 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dac.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32g4xx_hal_dac.h>

Data Fields

uint32_t | DAC_HighFrequency
FunctionalState | DAC_DMADoubleDataMode
FunctionalState | DAC_SignedFormat
uint32_t | DAC_SampleAndHold
uint32_t | DAC_Trigger
uint32_t | DAC_Trigger2
uint32_t | DAC_OutputBuffer
uint32_t | DAC_ConnectOnChipPeripheral
uint32_t | DAC_UserTrimming
uint32_t | DAC_TrimmingValue
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 119 of file stm32g4xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral

Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of DAC ConnectOnChipPeripheral

Definition at line 146 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

FunctionalState DAC_ChannelConfTypeDef::DAC_DMADoubleDataMode

Specifies if DMA double data mode should be enabled or not for the selected channel. This parameter can be ENABLE or DISABLE

Definition at line 124 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_HighFrequency

Specifies the frequency interface mode This parameter can be a value of DAC high frequency interface mode

Definition at line 121 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer

Definition at line 143 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_SampleAndHold

Specifies whether the DAC mode. This parameter can be a value of DAC power mode

Definition at line 130 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

DAC_SampleAndHoldConfTypeDef DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig

Sample and Hold settings

Definition at line 156 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

FunctionalState DAC_ChannelConfTypeDef::DAC_SignedFormat

Specifies if signed format should be used or not for the selected channel. This parameter can be ENABLE or DISABLE

Definition at line 127 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection. Note: In case of sawtooth wave generation, this trigger corresponds to the reset trigger.

Definition at line 133 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger2

Specifies the external secondary trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection. Note: In case of sawtooth wave generation, this trigger corresponds to the step trigger.

Definition at line 138 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_TrimmingValue

Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 153 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

uint32_t DAC_ChannelConfTypeDef::DAC_UserTrimming

Specifies the trimming mode This parameter must be a value of DAC User Trimming DAC_UserTrimming is either factory or user trimming

Definition at line 149 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dac.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04U

DMA error

Definition at line 202 of file stm32g4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U

DAC channel1 DMA underrun error

Definition at line 200 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U

DAC channel2 DMA underrun error

Definition at line 201 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Invalid callback error

Definition at line 205 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

#define HAL_DAC_ERROR_NONE 0x00U

No error

Definition at line 199 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

#define HAL_DAC_ERROR_TIMEOUT 0x08U

Timeout error

Definition at line 203 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC trigger selection

Defines
DAC trigger selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE 0x00000000UL
#define | DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

Define Documentation

#define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger

Definition at line 224 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger

Definition at line 223 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 227 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 229 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 231 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 233 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 235 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 237 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 228 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 230 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 232 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 234 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 236 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 238 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 239 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability)

Definition at line 240 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 241 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_NONE 0x00000000UL

DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger

Definition at line 215 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)

DAC (all) conversion started by software trigger for DAC channel

Definition at line 216 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DACEx_DualStart().

#define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel

Definition at line 220 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel.

Definition at line 217 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)

DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 221 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)

DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel

Definition at line 226 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 222 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 225 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)

DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 219 of file stm32g4xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)

DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability.

Definition at line 218 of file stm32g4xx_hal_dac.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Definition at line 251 of file stm32g4xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U

Definition at line 250 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Channel selection

Defines
DAC Channel selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U

Define Documentation

#define DAC_CHANNEL_1 0x00000000U

Definition at line 260 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_SawtoothWaveDataReset(), HAL_DACEx_SawtoothWaveDataStep(), and HAL_DACEx_SawtoothWaveGenerate().

#define DAC_CHANNEL_2 0x00000010U

Definition at line 262 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), and HAL_DACEx_DualStop_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC data alignment

Defines
DAC data alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U

Define Documentation

#define DAC_ALIGN_12B_L 0x00000004U

Definition at line 272 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define DAC_ALIGN_12B_R 0x00000000U

Definition at line 271 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define DAC_ALIGN_8B_R 0x00000008U

Definition at line 273 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue(), and HAL_DACEx_DualStart_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define | DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)

Define Documentation

#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)

Definition at line 286 of file stm32g4xx_hal_dac.h.

#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)

Definition at line 288 of file stm32g4xx_hal_dac.h.

#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 282 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 284 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC IT definition

Defines
DAC IT definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 298 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 300 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart_DMA(), and HAL_DACEx_DualStop_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC ConnectOnChipPeripheral

Defines
DAC ConnectOnChipPeripheral
DAC Exported Constants

Defines

#define | DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define | DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define | DAC_CHIPCONNECT_BOTH (1UL << 2)

Define Documentation

#define DAC_CHIPCONNECT_BOTH (1UL << 2)

Definition at line 312 of file stm32g4xx_hal_dac.h.

#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)

Definition at line 310 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)

Definition at line 311 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC User Trimming

Defines
DAC User Trimming
DAC Exported Constants

Defines

#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)

Define Documentation

#define DAC_TRIMMING_FACTORY (0x00000000UL)

Factory trimming

Definition at line 321 of file stm32g4xx_hal_dac.h.

#define DAC_TRIMMING_USER (0x00000001UL)

User trimming

Definition at line 322 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC power mode

Defines
DAC power mode
DAC Exported Constants

Defines

#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Define Documentation

#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)

Definition at line 330 of file stm32g4xx_hal_dac.h.

#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Definition at line 331 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC high frequency interface mode

Defines
DAC high frequency interface mode
DAC Exported Constants

Defines

#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL

Define Documentation

#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)

High frequency interface mode compatible to AHB>160MHz enabled

Definition at line 341 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)

High frequency interface mode compatible to AHB>80MHz enabled

Definition at line 340 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL

High frequency interface mode automatic

Definition at line 342 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL

High frequency interface mode disabled

Definition at line 339 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 488 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Disable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle
__DAC_Channel__ | specifies the DAC channel.
Return values:
None

Definition at line 399 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStop(), and HAL_DACEx_DualStop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 446 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Stop_DMA(), and HAL_DACEx_DualStop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Enable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle.
__DAC_Channel__ | specifies the DAC channel
Return values:
None

Definition at line 391 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart(), and HAL_DACEx_DualStart_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 433 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
  • DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
  • DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 475 of file stm32g4xx_hal_dac.h.

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CR\
                                                             & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__ DAC handle
__INTERRUPT__ DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of interruption (SET or RESET)

Definition at line 459 of file stm32g4xx_hal_dac.h.

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
                                                     } while(0)

Reset DAC handle state.

Parameters:
__HANDLE__ specifies the DAC handle.
Return values:
None

Definition at line 377 of file stm32g4xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (0x00000008UL + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 406 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (0x00000014UL + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 413 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (0x00000020UL + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 420 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(DACX, CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 515 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), HAL_DACEx_DualSetValue(), and HAL_DACEx_DualStart_DMA().

#define IS_DAC_CHANNEL | ( | DACX,
 |  | CHANNEL
 | ) |
Value:
(((CHANNEL) == DAC_CHANNEL_1)     || \
   ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 510 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SawtoothWaveDataReset(), HAL_DACEx_SawtoothWaveDataStep(), HAL_DACEx_SawtoothWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0UL)

Definition at line 519 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 499 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_REFRESHTIME ( TIME ) ((TIME) <= 0x000000FFUL)

Definition at line 521 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DAC

Functions

void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1675 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1711 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1694 of file stm32g4xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, and HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
#define | HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
#define | HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */

Define Documentation

#define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */

Definition at line 368 of file stm32g4xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

#define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */

Definition at line 367 of file stm32g4xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Definition at line 366 of file stm32g4xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC

Modules | Defines
DAC
STM32G4xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Macros
DAC Private Functions
DAC Private Constants

Defines

#define DAC_DELAY_STARTUP_US (15UL)

Detailed Description

DAC driver modules.

Define Documentation

#define DAC_DELAY_STARTUP_US (15UL)

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 364 of file stm32g4xx_hal_dac.h.

Referenced by HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart(), and HAL_DACEx_DualStart_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
DACEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData)
Enable or disable the selected DAC channel sawtooth wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataReset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave reset.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataStep (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave step.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (const DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.

Detailed Description

Extended IO operation functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 796 of file stm32g4xx_hal_dac_ex.c.

References UNUSED.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 812 of file stm32g4xx_hal_dac_ex.c.

References UNUSED.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 844 of file stm32g4xx_hal_dac_ex.c.

References UNUSED.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_DualGetValue ( const DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 1081 of file stm32g4xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment | Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1 | Data for DAC Channel1 to be loaded in the selected data holding register.
Data2 | Data for DAC Channel2 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 754 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DACEx_DualStart ( DAC_HandleTypeDef * hdac )

Enables DAC and starts conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 131 of file stm32g4xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_DELAY_STARTUP_US, DAC_TRIGGER_SOFTWARE, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_DualStart_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The DAC channel that will request data from DMA. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData | The destination peripheral Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 232 of file stm32g4xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_DELAY_STARTUP_US, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DACEx_DualStop ( DAC_HandleTypeDef * hdac )

Disables DAC and stop conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 193 of file stm32g4xx_hal_dac_ex.c.

References __HAL_DAC_DISABLE, assert_param, DAC_CHANNEL_1, DAC_CHANNEL_2, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_DualStop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion both channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The DAC channel that requests data from DMA. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 360 of file stm32g4xx_hal_dac_ex.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 828 of file stm32g4xx_hal_dac_ex.c.

References UNUSED.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_GetTrimOffset | ( | const DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Trimming value : range: 0->31

Definition at line 1047 of file stm32g4xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Amplitude Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 503 of file stm32g4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Trig sawtooth wave reset.

Note:
This function allows to reset sawtooth wave in case of SW trigger has been configured for this usage.
Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 629 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Trig sawtooth wave step.

Note:
This function allows to generate step in sawtooth wave in case of SW trigger has been configured for this usage.
Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
HAL status

Definition at line 691 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity,
 |  | uint32_t | ResetData,
 |  | uint32_t | StepData
 | ) |  |

Enable or disable the selected DAC channel sawtooth wave generation.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Polarity polarity to be used for wave generation. This parameter can be one of the following values:
  • DAC_SAWTOOTH_POLARITY_DECREMENT
  • DAC_SAWTOOTH_POLARITY_INCREMENT
ResetData | Sawtooth wave reset value. Range is from 0 to DAC full range 4095 (0xFFF)
StepData | Sawtooth wave step value. 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa Step value step is 1/16 = 0.0625 Step value range is 0.0000 to 4095.9375 (0xFFF.F)
Note:
Sawtooth reset and step triggers are configured by calling HAL_DAC_ConfigChannel
Return values:
HAL status

Definition at line 559 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_RESET_DATA, IS_DAC_SAWTOOTH_POLARITY, IS_DAC_STEP_DATA, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 871 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_DELAY_TRIM_US, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 1002 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Amplitude Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 444 of file stm32g4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DACEx Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (const DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

uint32_t HAL_DACEx_DualGetValue ( const DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 1081 of file stm32g4xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

uint32_t HAL_DACEx_GetTrimOffset | ( | const DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Trimming value : range: 0->31

Definition at line 1047 of file stm32g4xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 871 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_DELAY_TRIM_US, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 1002 of file stm32g4xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx private functions

Functions
DACEx private functions
DACEx

Extended private functions. More...

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended private functions.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1114 of file stm32g4xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh2, HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1150 of file stm32g4xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1133 of file stm32g4xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, and HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart_DMA().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx lfsrunmask triangle amplitude

Defines
DACEx lfsrunmask triangle amplitude
DACEx Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 0x00000000UL

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 55 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 65 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 66 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 56 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 57 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 58 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 59 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 60 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 61 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 62 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 63 of file stm32g4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 64 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL

Select max triangle amplitude of 1

Definition at line 67 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 76 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 127

Definition at line 73 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 70 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 2047

Definition at line 77 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 74 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 68 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Select max triangle amplitude of 31

Definition at line 71 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 78 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )

Select max triangle amplitude of 511

Definition at line 75 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 72 of file stm32g4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Select max triangle amplitude of 7

Definition at line 69 of file stm32g4xx_hal_dac_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Sawtooth polarity mode

Defines
DAC Sawtooth polarity mode
DACEx Exported Constants

Defines

#define | DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL
#define | DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)

Define Documentation

#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL

Sawtooth wave generation, polarity is decrement

Definition at line 87 of file stm32g4xx_hal_dac_ex.h.

#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)

Sawtooth wave generation, polarity is increment

Definition at line 88 of file stm32g4xx_hal_dac_ex.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define | IS_DAC_TRIGGER(DACX, TRIGGER)
#define | IS_DAC_TRIGGER2(DACX, TRIGGER)
#define | IS_DAC_HIGH_FREQUENCY_MODE(MODE)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_SAWTOOTH_POLARITY(POLARITY)
#define | IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
#define | IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL)

Define Documentation

#define IS_DAC_CHIP_CONNECTION ( CONNECT )
Value:
(((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_BOTH))

Definition at line 221 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HIGH_FREQUENCY_MODE ( MODE )
Value:
(((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE)         || \
                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ)     || \
                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ)    || \
                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))

Definition at line 205 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HOLDTIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 212 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 228 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_NEWTRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 219 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SetUserTrimming().

#define IS_DAC_RESET_DATA ( DATA ) ((DATA) <= 0x00000FFFUL)

Definition at line 256 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SawtoothWaveGenerate().

#define IS_DAC_SAMPLEANDHOLD ( MODE )
Value:
(((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

Definition at line 214 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAMPLETIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 210 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAWTOOTH_POLARITY ( POLARITY )
Value:
(((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
                                            ((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))

Definition at line 253 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SawtoothWaveGenerate().

#define IS_DAC_STEP_DATA ( DATA ) ((DATA) <= 0x0000FFFFUL)

Definition at line 257 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SawtoothWaveGenerate().

#define IS_DAC_TRIGGER | ( | DACX,
 |  | TRIGGER
 | ) |
Value:
(((TRIGGER) == DAC_TRIGGER_NONE)           || \
   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)       || \
   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)        || \
   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)       || \
   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)        || \
   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)        || \
   ((TRIGGER) == DAC_TRIGGER_EXT_IT9)        || \
   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)        || \
   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)        || \
   (((DACX) == DAC3) ?                          \
    ((TRIGGER) == DAC_TRIGGER_T1_TRGO)          \
    : ((TRIGGER) == DAC_TRIGGER_T8_TRGO)        \
   )                                            \
  )

Definition at line 141 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER2 | ( | DACX,
 |  | TRIGGER
 | ) |
Value:
(((TRIGGER) == DAC_TRIGGER_NONE)            || \
   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)        || \
   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)         || \
   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)        || \
   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)         || \
   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)         || \
   ((TRIGGER) == DAC_TRIGGER_EXT_IT10)        || \
   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)         || \
   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)         || \
   (((DACX) == DAC3) ?                           \
    ((TRIGGER) == DAC_TRIGGER_T1_TRGO)           \
    :((TRIGGER) == DAC_TRIGGER_T8_TRGO)          \
   )                                             \
  )

Definition at line 189 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == DAC_TRIMMING_FACTORY) || \
                                   ((TRIMMING) == DAC_TRIMMING_USER))

Definition at line 225 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 217 of file stm32g4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx

Modules | Defines
DACEx
STM32G4xx_HAL_Driver

DAC Extended HAL module driver. More...

Modules

DACEx Exported Functions
DACEx private functions

Extended private functions.

DACEx Exported Constants

HAL State structures definition.

DACEx Private Macros

Defines

#define DAC_DELAY_TRIM_US (50UL)

Detailed Description

DAC Extended HAL module driver.

Define Documentation

#define DAC_DELAY_TRIM_US (50UL)

Delay for DAC minimum trimming time

Definition at line 94 of file stm32g4xx_hal_dac_ex.c.

Referenced by HAL_DACEx_SelfCalibrate().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.

Function Documentation

static void DMA_CalcDMAMUXChannelBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 1045 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXRequestGenBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX request generator params.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 1082 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and DMA_InitTypeDef::Request.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 1002 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 263 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_REQUEST_GENERATOR3, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 152 of file stm32g4xx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_MEMORY_TO_MEMORY, DMA_REQUEST_GENERATOR3, DMA_REQUEST_MEM2MEM, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_ALL_REQUEST, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, __DMA_HandleTypeDef::Lock, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, and __DMA_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 491 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStop_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 544 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_SAI_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handle DMA interrupt request.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 741 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel | Specifies the DMA level complete.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 611 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifier a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback | pointer to private callbacsk function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 835 of file stm32g4xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination (up to 256Kbytes-1)
Return values:
HAL status

Definition at line 378 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination (up to 256Kbytes-1)
Return values:
HAL status

Definition at line 421 of file stm32g4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_CORDIC_Calculate_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and UART_Start_Receive_DMA().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma | pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifier a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 886 of file stm32g4xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DMA Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 976 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Return the DMA hande state.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 964 of file stm32g4xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Referenced by I2C_ITError().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 100 of file stm32g4xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 90 of file stm32g4xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 79 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32g4xx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 46 of file stm32g4xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 51 of file stm32g4xx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 64 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 58 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 67 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init(), I2S_DMARxCplt(), I2S_DMATxCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 61 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 55 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 72 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified channel. This parameter can be a value of DMA request

Definition at line 48 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dma.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32g4xx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex
DMAMUX_Channel_TypeDef * | DMAmuxChannel
DMAMUX_ChannelStatus_TypeDef * | DMAmuxChannelStatus
uint32_t | DMAmuxChannelStatusMask
DMAMUX_RequestGen_TypeDef * | DMAmuxRequestGen
DMAMUX_RequestGenStatus_TypeDef * | DMAmuxRequestGenStatus
uint32_t | DMAmuxRequestGenStatusMask

Detailed Description

DMA handle Structure definition.

Definition at line 113 of file stm32g4xx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 137 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 135 of file stm32g4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMAMUX_Channel_TypeDef* __DMA_HandleTypeDef::DMAmuxChannel

Register base address

Definition at line 139 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxSync(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_ChannelStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxChannelStatus

DMAMUX Channels Status Base Address

Definition at line 141 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxChannelStatusMask

DMAMUX Channel Status Mask

Definition at line 143 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGen_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGen

DMAMUX request generator Base Address

Definition at line 145 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGenStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGenStatus

DMAMUX request generator Address

Definition at line 147 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask

DMAMUX request generator Status mask

Definition at line 149 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 133 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_DMAEx_MUX_IRQHandler().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 117 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), I2S_DMARxCplt(), I2S_DMATxCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 115 of file stm32g4xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_UART_IRQHandler(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 119 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 123 of file stm32g4xx_hal_dma.h.

Referenced by IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 121 of file stm32g4xx_hal_dma.h.

Referenced by HAL_ADC_Stop_DMA(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), and HAL_DMAEx_EnableMuxRequestGenerator().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 131 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_Start_Receive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 125 of file stm32g4xx_hal_dma.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_CORDIC_Calculate_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 129 of file stm32g4xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_CORDIC_Calculate_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MUX_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 127 of file stm32g4xx_hal_dma.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DACEx_DualStart_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dma.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U

Define Documentation

#define HAL_DMA_ERROR_NO_XFER 0x00000004U

Abort requested with no Xfer ongoing

Definition at line 167 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE 0x00000000U

No error

Definition at line 165 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

Not supported mode

Definition at line 169 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_REQGEN 0x00000400U

DMAMUX request generator overrun error

Definition at line 171 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_SYNC 0x00000200U

DMAMUX sync overrun error

Definition at line 170 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_TE 0x00000001U

Transfer error

Definition at line 166 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT 0x00000020U

Timeout error

Definition at line 168 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA request

Defines
DMA request
DMA Exported Constants

Defines

#define | DMA_REQUEST_MEM2MEM 0U
#define | DMA_REQUEST_GENERATOR0 1U
#define | DMA_REQUEST_GENERATOR1 2U
#define | DMA_REQUEST_GENERATOR2 3U
#define | DMA_REQUEST_GENERATOR3 4U
#define | DMA_REQUEST_ADC1 5U
#define | DMA_REQUEST_DAC1_CHANNEL1 6U
#define | DMA_REQUEST_DAC1_CHANNEL2 7U
#define | DMA_REQUEST_TIM6_UP 8U
#define | DMA_REQUEST_TIM7_UP 9U
#define | DMA_REQUEST_SPI1_RX 10U
#define | DMA_REQUEST_SPI1_TX 11U
#define | DMA_REQUEST_SPI2_RX 12U
#define | DMA_REQUEST_SPI2_TX 13U
#define | DMA_REQUEST_SPI3_RX 14U
#define | DMA_REQUEST_SPI3_TX 15U
#define | DMA_REQUEST_I2C1_RX 16U
#define | DMA_REQUEST_I2C1_TX 17U
#define | DMA_REQUEST_I2C2_RX 18U
#define | DMA_REQUEST_I2C2_TX 19U
#define | DMA_REQUEST_I2C3_RX 20U
#define | DMA_REQUEST_I2C3_TX 21U
#define | DMA_REQUEST_USART1_RX 24U
#define | DMA_REQUEST_USART1_TX 25U
#define | DMA_REQUEST_USART2_RX 26U
#define | DMA_REQUEST_USART2_TX 27U
#define | DMA_REQUEST_USART3_RX 28U
#define | DMA_REQUEST_USART3_TX 29U
#define | DMA_REQUEST_UART4_RX 30U
#define | DMA_REQUEST_UART4_TX 31U
#define | DMA_REQUEST_LPUART1_RX 34U
#define | DMA_REQUEST_LPUART1_TX 35U
#define | DMA_REQUEST_ADC2 36U
#define | DMA_REQUEST_TIM1_CH1 42U
#define | DMA_REQUEST_TIM1_CH2 43U
#define | DMA_REQUEST_TIM1_CH3 44U
#define | DMA_REQUEST_TIM1_CH4 45U
#define | DMA_REQUEST_TIM1_UP 46U
#define | DMA_REQUEST_TIM1_TRIG 47U
#define | DMA_REQUEST_TIM1_COM 48U
#define | DMA_REQUEST_TIM8_CH1 49U
#define | DMA_REQUEST_TIM8_CH2 50U
#define | DMA_REQUEST_TIM8_CH3 51U
#define | DMA_REQUEST_TIM8_CH4 52U
#define | DMA_REQUEST_TIM8_UP 53U
#define | DMA_REQUEST_TIM8_TRIG 54U
#define | DMA_REQUEST_TIM8_COM 55U
#define | DMA_REQUEST_TIM2_CH1 56U
#define | DMA_REQUEST_TIM2_CH2 57U
#define | DMA_REQUEST_TIM2_CH3 58U
#define | DMA_REQUEST_TIM2_CH4 59U
#define | DMA_REQUEST_TIM2_UP 60U
#define | DMA_REQUEST_TIM3_CH1 61U
#define | DMA_REQUEST_TIM3_CH2 62U
#define | DMA_REQUEST_TIM3_CH3 63U
#define | DMA_REQUEST_TIM3_CH4 64U
#define | DMA_REQUEST_TIM3_UP 65U
#define | DMA_REQUEST_TIM3_TRIG 66U
#define | DMA_REQUEST_TIM4_CH1 67U
#define | DMA_REQUEST_TIM4_CH2 68U
#define | DMA_REQUEST_TIM4_CH3 69U
#define | DMA_REQUEST_TIM4_CH4 70U
#define | DMA_REQUEST_TIM4_UP 71U
#define | DMA_REQUEST_TIM15_CH1 78U
#define | DMA_REQUEST_TIM15_UP 79U
#define | DMA_REQUEST_TIM15_TRIG 80U
#define | DMA_REQUEST_TIM15_COM 81U
#define | DMA_REQUEST_TIM16_CH1 82U
#define | DMA_REQUEST_TIM16_UP 83U
#define | DMA_REQUEST_TIM17_CH1 84U
#define | DMA_REQUEST_TIM17_UP 85U
#define | DMA_REQUEST_AES_IN 91U
#define | DMA_REQUEST_AES_OUT 92U
#define | DMA_REQUEST_DAC3_CHANNEL1 102U
#define | DMA_REQUEST_DAC3_CHANNEL2 103U
#define | DMA_REQUEST_SAI1_A 108U
#define | DMA_REQUEST_SAI1_B 109U
#define | DMA_REQUEST_FMAC_READ 110U
#define | DMA_REQUEST_FMAC_WRITE 111U
#define | DMA_REQUEST_CORDIC_READ 112U
#define | DMA_REQUEST_CORDIC_WRITE 113U
#define | DMA_REQUEST_UCPD1_RX 114U
#define | DMA_REQUEST_UCPD1_TX 115U

Define Documentation

#define DMA_REQUEST_ADC1 5U

Definition at line 186 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_ADC2 36U

Definition at line 229 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_AES_IN 91U

Definition at line 310 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_AES_OUT 92U

Definition at line 311 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_CORDIC_READ 112U

Definition at line 346 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_CORDIC_WRITE 113U

Definition at line 347 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CHANNEL1 6U

Definition at line 188 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CHANNEL2 7U

Definition at line 189 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_DAC3_CHANNEL1 102U

Definition at line 328 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_DAC3_CHANNEL2 103U

Definition at line 329 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_FMAC_READ 110U

Definition at line 343 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_FMAC_WRITE 111U

Definition at line 344 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR0 1U

Definition at line 181 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR1 2U

Definition at line 182 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR2 3U

Definition at line 183 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR3 4U

Definition at line 184 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

#define DMA_REQUEST_I2C1_RX 16U

Definition at line 201 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_I2C1_TX 17U

Definition at line 202 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_I2C2_RX 18U

Definition at line 203 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_I2C2_TX 19U

Definition at line 204 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_I2C3_RX 20U

Definition at line 205 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_I2C3_TX 21U

Definition at line 206 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_LPUART1_RX 34U

Definition at line 226 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_LPUART1_TX 35U

Definition at line 227 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_MEM2MEM 0U

memory to memory transfer

Definition at line 179 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_REQUEST_SAI1_A 108U

Definition at line 340 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SAI1_B 109U

Definition at line 341 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI1_RX 10U

Definition at line 194 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI1_TX 11U

Definition at line 195 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI2_RX 12U

Definition at line 196 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI2_TX 13U

Definition at line 197 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI3_RX 14U

Definition at line 198 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_SPI3_TX 15U

Definition at line 199 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM15_CH1 78U

Definition at line 292 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM15_COM 81U

Definition at line 295 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM15_TRIG 80U

Definition at line 294 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM15_UP 79U

Definition at line 293 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM16_CH1 82U

Definition at line 297 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM16_UP 83U

Definition at line 298 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM17_CH1 84U

Definition at line 299 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM17_UP 85U

Definition at line 300 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH1 42U

Definition at line 248 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH2 43U

Definition at line 249 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH3 44U

Definition at line 250 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH4 45U

Definition at line 251 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_COM 48U

Definition at line 254 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_TRIG 47U

Definition at line 253 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM1_UP 46U

Definition at line 252 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH1 56U

Definition at line 264 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH2 57U

Definition at line 265 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH3 58U

Definition at line 266 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH4 59U

Definition at line 267 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM2_UP 60U

Definition at line 268 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH1 61U

Definition at line 270 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH2 62U

Definition at line 271 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH3 63U

Definition at line 272 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH4 64U

Definition at line 273 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_TRIG 66U

Definition at line 275 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM3_UP 65U

Definition at line 274 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH1 67U

Definition at line 277 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH2 68U

Definition at line 278 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH3 69U

Definition at line 279 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH4 70U

Definition at line 280 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM4_UP 71U

Definition at line 281 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM6_UP 8U

Definition at line 191 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM7_UP 9U

Definition at line 192 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH1 49U

Definition at line 256 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH2 50U

Definition at line 257 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH3 51U

Definition at line 258 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_CH4 52U

Definition at line 259 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_COM 55U

Definition at line 262 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_TRIG 54U

Definition at line 261 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_TIM8_UP 53U

Definition at line 260 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_UART4_RX 30U

Definition at line 219 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_UART4_TX 31U

Definition at line 220 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_UCPD1_RX 114U

Definition at line 349 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_UCPD1_TX 115U

Definition at line 350 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART1_RX 24U

Definition at line 212 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART1_TX 25U

Definition at line 213 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART2_RX 26U

Definition at line 214 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART2_TX 27U

Definition at line 215 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART3_RX 28U

Definition at line 216 of file stm32g4xx_hal_dma.h.

#define DMA_REQUEST_USART3_TX 29U

Definition at line 217 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY 0x00000000U
#define | DMA_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 361 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 360 of file stm32g4xx_hal_dma.h.

Referenced by DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 359 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE DMA_CCR_PINC
#define | DMA_PINC_DISABLE 0x00000000U

Define Documentation

#define DMA_PINC_DISABLE 0x00000000U

Peripheral increment mode Disable

Definition at line 370 of file stm32g4xx_hal_dma.h.

#define DMA_PINC_ENABLE DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 369 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE DMA_CCR_MINC
#define | DMA_MINC_DISABLE 0x00000000U

Define Documentation

#define DMA_MINC_DISABLE 0x00000000U

Memory increment mode Disable

Definition at line 379 of file stm32g4xx_hal_dma.h.

#define DMA_MINC_ENABLE DMA_CCR_MINC

Memory increment mode Enable

Definition at line 378 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE 0x00000000U
#define | DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 387 of file stm32g4xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 388 of file stm32g4xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 389 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE 0x00000000U
#define | DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 397 of file stm32g4xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 398 of file stm32g4xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 399 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL 0x00000000U
#define | DMA_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define DMA_CIRCULAR DMA_CCR_CIRC

Circular mode

Definition at line 408 of file stm32g4xx_hal_dma.h.

Referenced by SAI_DMARxCplt(), and SAI_DMATxCplt().

#define DMA_NORMAL 0x00000000U

Normal mode

Definition at line 407 of file stm32g4xx_hal_dma.h.

Referenced by I2S_DMARxCplt(), I2S_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW 0x00000000U
#define | DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | DMA_PRIORITY_VERY_HIGH DMA_CCR_PL

Define Documentation

#define DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 418 of file stm32g4xx_hal_dma.h.

#define DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 416 of file stm32g4xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 417 of file stm32g4xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 419 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC DMA_CCR_TCIE
#define | DMA_IT_HT DMA_CCR_HTIE
#define | DMA_IT_TE DMA_CCR_TEIE

Define Documentation

#define DMA_IT_HT DMA_CCR_HTIE

Definition at line 429 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC DMA_CCR_TCIE

Definition at line 428 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE DMA_CCR_TEIE

Definition at line 430 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GL1 0x00000001U
#define | DMA_FLAG_TC1 0x00000002U
#define | DMA_FLAG_HT1 0x00000004U
#define | DMA_FLAG_TE1 0x00000008U
#define | DMA_FLAG_GL2 0x00000010U
#define | DMA_FLAG_TC2 0x00000020U
#define | DMA_FLAG_HT2 0x00000040U
#define | DMA_FLAG_TE2 0x00000080U
#define | DMA_FLAG_GL3 0x00000100U
#define | DMA_FLAG_TC3 0x00000200U
#define | DMA_FLAG_HT3 0x00000400U
#define | DMA_FLAG_TE3 0x00000800U
#define | DMA_FLAG_GL4 0x00001000U
#define | DMA_FLAG_TC4 0x00002000U
#define | DMA_FLAG_HT4 0x00004000U
#define | DMA_FLAG_TE4 0x00008000U
#define | DMA_FLAG_GL5 0x00010000U
#define | DMA_FLAG_TC5 0x00020000U
#define | DMA_FLAG_HT5 0x00040000U
#define | DMA_FLAG_TE5 0x00080000U
#define | DMA_FLAG_GL6 0x00100000U
#define | DMA_FLAG_TC6 0x00200000U
#define | DMA_FLAG_HT6 0x00400000U
#define | DMA_FLAG_TE6 0x00800000U

Define Documentation

#define DMA_FLAG_GL1 0x00000001U

Definition at line 438 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_GL2 0x00000010U

Definition at line 442 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_GL3 0x00000100U

Definition at line 446 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_GL4 0x00001000U

Definition at line 450 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_GL5 0x00010000U

Definition at line 454 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_GL6 0x00100000U

Definition at line 458 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_HT1 0x00000004U

Definition at line 440 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HT2 0x00000040U

Definition at line 444 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_HT3 0x00000400U

Definition at line 448 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_HT4 0x00004000U

Definition at line 452 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_HT5 0x00040000U

Definition at line 456 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_HT6 0x00400000U

Definition at line 460 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TC1 0x00000002U

Definition at line 439 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TC2 0x00000020U

Definition at line 443 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TC3 0x00000200U

Definition at line 447 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TC4 0x00002000U

Definition at line 451 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TC5 0x00020000U

Definition at line 455 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TC6 0x00200000U

Definition at line 459 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TE1 0x00000008U

Definition at line 441 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TE2 0x00000080U

Definition at line 445 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TE3 0x00000800U

Definition at line 449 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TE4 0x00008000U

Definition at line 453 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TE5 0x00080000U

Definition at line 457 of file stm32g4xx_hal_dma.h.

#define DMA_FLAG_TE6 0x00800000U

Definition at line 461 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
                                                    (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))

Clear the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx Transfer complete flag
  • DMA_FLAG_HTx Half transfer complete flag
  • DMA_FLAG_TEx Transfer error flag
  • DMA_FLAG_GLx Global interrupt flag Where x can be from 1 to 8 to select the DMA Channel x flag.
Return values:
None

Definition at line 695 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 505 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC Transfer complete interrupt mask
  • DMA_IT_HT Half transfer complete interrupt mask
  • DMA_IT_TE Transfer error interrupt mask
Return values:
None

Definition at line 721 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)

Enable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 498 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC Transfer complete interrupt mask
  • DMA_IT_HT Half transfer complete interrupt mask
  • DMA_IT_TE Transfer error interrupt mask
Return values:
None

Definition at line 709 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Start_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Return the number of remaining data units in the current DMA Channel transfer.

Parameters:
__HANDLE__ DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 740 of file stm32g4xx_hal_dma.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
                                                  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx Transfer complete flag
  • DMA_FLAG_HTx Half transfer complete flag
  • DMA_FLAG_TEx Transfer error flag
  • DMA_FLAG_GLx Global interrupt flag Where x can be from 1 to 8 to select the DMA Channel x flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 675 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
   DMA_ISR_GIF6)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 645 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
   DMA_FLAG_HT6)

Return the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 571 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Check whether the specified DMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC Transfer complete interrupt mask
  • DMA_IT_HT Half transfer complete interrupt mask
  • DMA_IT_TE Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 733 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
   DMA_FLAG_TC6)

Return the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 534 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
   DMA_FLAG_TE6)

Return the current DMA Channel transfer error flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 608 of file stm32g4xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 491 of file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define IS_DMA_ALL_REQUEST ( REQUEST ) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)

Definition at line 815 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))

Definition at line 807 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 803 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 821 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 812 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR))

Definition at line 825 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 817 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 809 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 828 of file stm32g4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx Extended features functions

Functions
DMAEx Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:

    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxRequestGeneratorConfigTypeDef * | pRequestGeneratorConfig
 | ) |  |

Configure the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator parameters.
Return values:
HAL status

Definition at line 141 of file stm32g4xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_REQUEST_GEN_POLARITY, IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER, IS_DMAMUX_REQUEST_GEN_SIGNAL_ID, HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity, HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber, HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxSyncConfigTypeDef * | pSyncConfig
 | ) |  |

Configure the DMAMUX synchronization parameters for a given DMA channel (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
Return values:
HAL status

Definition at line 95 of file stm32g4xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxChannel, HAL_DMA_MuxSyncConfigTypeDef::EventEnable, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_SYNC_EVENT, IS_DMAMUX_SYNC_POLARITY, IS_DMAMUX_SYNC_REQUEST_NUMBER, IS_DMAMUX_SYNC_SIGNAL_ID, IS_DMAMUX_SYNC_STATE, HAL_DMA_MuxSyncConfigTypeDef::RequestNumber, __DMA_HandleTypeDef::State, HAL_DMA_MuxSyncConfigTypeDef::SyncEnable, HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity, and HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID.

HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Disable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 209 of file stm32g4xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Enable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 181 of file stm32g4xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

void HAL_DMAEx_MUX_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMAMUX interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
None

Definition at line 237 of file stm32g4xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL_DMA_MuxSyncConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxSyncConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMA Synchro definition. More...

#include <stm32g4xx_hal_dma_ex.h>

Data Fields

uint32_t | SyncSignalID
uint32_t | SyncPolarity
FunctionalState | SyncEnable
FunctionalState | EventEnable
uint32_t | RequestNumber

Detailed Description

HAL DMA Synchro definition.

HAL DMAMUX Synchronization configuration structure definition

Definition at line 51 of file stm32g4xx_hal_dma_ex.h.

Field Documentation

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::EventEnable

Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE

Definition at line 63 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be authorized after a sync event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 66 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::SyncEnable

Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE

Definition at line 59 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity

Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of DMAMUX SyncPolarity selection

Definition at line 56 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID

Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of DMAMUX SyncSignalID selection

Definition at line 53 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dma_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX request generator parameters structure definition. More...

#include <stm32g4xx_hal_dma_ex.h>

Data Fields

uint32_t | SignalID
uint32_t | Polarity
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX request generator parameters structure definition.

Definition at line 76 of file stm32g4xx_hal_dma_ex.h.

Field Documentation

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity

Specifies the polarity of the signal on which the request is generated. This parameter can be a value of DMAMUX RequestGeneneratorPolarity selection

Definition at line 81 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be generated after a signal event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 84 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID

Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMAMUX SignalGeneratorID selection

Definition at line 78 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_dma_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX SyncSignalID selection

Defines
DMAMUX SyncSignalID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 0U
#define | HAL_DMAMUX1_SYNC_EXTI1 1U
#define | HAL_DMAMUX1_SYNC_EXTI2 2U
#define | HAL_DMAMUX1_SYNC_EXTI3 3U
#define | HAL_DMAMUX1_SYNC_EXTI4 4U
#define | HAL_DMAMUX1_SYNC_EXTI5 5U
#define | HAL_DMAMUX1_SYNC_EXTI6 6U
#define | HAL_DMAMUX1_SYNC_EXTI7 7U
#define | HAL_DMAMUX1_SYNC_EXTI8 8U
#define | HAL_DMAMUX1_SYNC_EXTI9 9U
#define | HAL_DMAMUX1_SYNC_EXTI10 10U
#define | HAL_DMAMUX1_SYNC_EXTI11 11U
#define | HAL_DMAMUX1_SYNC_EXTI12 12U
#define | HAL_DMAMUX1_SYNC_EXTI13 13U
#define | HAL_DMAMUX1_SYNC_EXTI14 14U
#define | HAL_DMAMUX1_SYNC_EXTI15 15U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U

Define Documentation

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U

Synchronization Signal is DMAMUX1 Channel0 Event

Definition at line 117 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U

Synchronization Signal is DMAMUX1 Channel1 Event

Definition at line 118 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U

Synchronization Signal is DMAMUX1 Channel2 Event

Definition at line 119 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U

Synchronization Signal is DMAMUX1 Channel3 Event

Definition at line 120 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI0 0U

Synchronization Signal is EXTI0 IT

Definition at line 101 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI1 1U

Synchronization Signal is EXTI1 IT

Definition at line 102 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI10 10U

Synchronization Signal is EXTI10 IT

Definition at line 111 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI11 11U

Synchronization Signal is EXTI11 IT

Definition at line 112 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI12 12U

Synchronization Signal is EXTI12 IT

Definition at line 113 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI13 13U

Synchronization Signal is EXTI13 IT

Definition at line 114 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI14 14U

Synchronization Signal is EXTI14 IT

Definition at line 115 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI15 15U

Synchronization Signal is EXTI15 IT

Definition at line 116 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI2 2U

Synchronization Signal is EXTI2 IT

Definition at line 103 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI3 3U

Synchronization Signal is EXTI3 IT

Definition at line 104 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI4 4U

Synchronization Signal is EXTI4 IT

Definition at line 105 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI5 5U

Synchronization Signal is EXTI5 IT

Definition at line 106 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI6 6U

Synchronization Signal is EXTI6 IT

Definition at line 107 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI7 7U

Synchronization Signal is EXTI7 IT

Definition at line 108 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI8 8U

Synchronization Signal is EXTI8 IT

Definition at line 109 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI9 9U

Synchronization Signal is EXTI9 IT

Definition at line 110 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U

Synchronization Signal is LPTIM1 OUT

Definition at line 121 of file stm32g4xx_hal_dma_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX SyncPolarity selection

Defines
DMAMUX SyncPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_SYNC_NO_EVENT 0U
#define | HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)
#define | HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)
#define | HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)

Define Documentation

#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)

synchronize with falling edge events

Definition at line 132 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_NO_EVENT 0U

block synchronization events

Definition at line 130 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)

synchronize with rising edge events

Definition at line 131 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)

synchronize with rising and falling edge events

Definition at line 133 of file stm32g4xx_hal_dma_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX SignalGeneratorID selection

Defines
DMAMUX SignalGeneratorID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_REQ_GEN_EXTI0 0U
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 1U
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 2U
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 3U
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 4U
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 5U
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 6U
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 7U
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 8U
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 9U
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 10U
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 11U
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 12U
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 13U
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 14U
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 15U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U

Define Documentation

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U

Request generator Signal is DMAMUX1 Channel0 Event

Definition at line 158 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U

Request generator Signal is DMAMUX1 Channel1 Event

Definition at line 159 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U

Request generator Signal is DMAMUX1 Channel2 Event

Definition at line 160 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U

Request generator Signal is DMAMUX1 Channel3 Event

Definition at line 161 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U

Request generator Signal is EXTI0 IT

Definition at line 142 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U

Request generator Signal is EXTI1 IT

Definition at line 143 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U

Request generator Signal is EXTI10 IT

Definition at line 152 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U

Request generator Signal is EXTI11 IT

Definition at line 153 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U

Request generator Signal is EXTI12 IT

Definition at line 154 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U

Request generator Signal is EXTI13 IT

Definition at line 155 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U

Request generator Signal is EXTI14 IT

Definition at line 156 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U

Request generator Signal is EXTI15 IT

Definition at line 157 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U

Request generator Signal is EXTI2 IT

Definition at line 144 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U

Request generator Signal is EXTI3 IT

Definition at line 145 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U

Request generator Signal is EXTI4 IT

Definition at line 146 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U

Request generator Signal is EXTI5 IT

Definition at line 147 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U

Request generator Signal is EXTI6 IT

Definition at line 148 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U

Request generator Signal is EXTI7 IT

Definition at line 149 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U

Request generator Signal is EXTI8 IT

Definition at line 150 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U

Request generator Signal is EXTI9 IT

Definition at line 151 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U

Request generator Signal is LPTIM1 OUT

Definition at line 162 of file stm32g4xx_hal_dma_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX RequestGeneneratorPolarity selection

Defines
DMAMUX RequestGeneneratorPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
#define | HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL

Define Documentation

#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1

generate request on falling edge events

Definition at line 173 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

block request generator events

Definition at line 171 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0

generate request on rising edge events

Definition at line 172 of file stm32g4xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL

generate request on rising and falling edge events

Definition at line 174 of file stm32g4xx_hal_dma_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx Private Macros

Defines
DMAEx Private Macros
DMAEx

DMAEx private macros. More...

Defines

#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Detailed Description

DMAEx private macros.

Define Documentation

#define IS_DMAMUX_REQUEST_GEN_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))

Definition at line 241 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 239 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)

Definition at line 237 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_SYNC_EVENT ( EVENT )
Value:
(((EVENT) == DISABLE)   || \
                                     ((EVENT) == ENABLE))

Definition at line 234 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

Definition at line 227 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 225 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)

Definition at line 223 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_STATE ( SYNC ) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))

Definition at line 232 of file stm32g4xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Private Constants

Defines
EXTI Private Constants
EXTI

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine. More...

Defines

#define | EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */
#define | EXTI_PROPERTY_SHIFT 24U
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_REG_SHIFT 16U
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001FU
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 44UL
EXTI Line number.

Detailed Description

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

Define Documentation

#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)

Definition at line 193 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */

Definition at line 112 of file stm32g4xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)

Definition at line 192 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

Definition at line 194 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_LINE_NB 44UL

EXTI Line number.

Definition at line 220 of file stm32g4xx_hal_exti.h.

#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)

EXTI Mask for interrupt & event mode.

Definition at line 210 of file stm32g4xx_hal_exti.h.

#define EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */

Definition at line 111 of file stm32g4xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_PIN_MASK 0x0000001FU

Definition at line 205 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)

Definition at line 196 of file stm32g4xx_hal_exti.h.

#define EXTI_PROPERTY_SHIFT 24U

EXTI Line property definition.

Definition at line 191 of file stm32g4xx_hal_exti.h.

#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)

Definition at line 202 of file stm32g4xx_hal_exti.h.

#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)

Definition at line 203 of file stm32g4xx_hal_exti.h.

#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)

Definition at line 204 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_REG_SHIFT 16U

EXTI Register and bit usage.

Definition at line 201 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)

Definition at line 195 of file stm32g4xx_hal_exti.h.

#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

EXTI Mask for trigger possibilities.

Definition at line 215 of file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Types

Data Structures | Enumerations
EXTI Exported Types
EXTI

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00UL }

Enumeration Type Documentation

enum EXTI_CallbackIDTypeDef
Enumerator:
HAL_EXTI_COMMON_CB_ID

Definition at line 44 of file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_HandleTypeDef Struct Reference
EXTI Exported Types

EXTI Handle structure definition. More...

#include <stm32g4xx_hal_exti.h>

Data Fields

uint32_t | Line
void(* | PendingCallback )(void)

Detailed Description

EXTI Handle structure definition.

Definition at line 53 of file stm32g4xx_hal_exti.h.

Field Documentation

uint32_t EXTI_HandleTypeDef::Line

Exti line number

Definition at line 55 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

void(* EXTI_HandleTypeDef::PendingCallback)(void)

Exti pending callback

Definition at line 56 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_IRQHandler(), and HAL_EXTI_RegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_exti.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_ConfigTypeDef Struct Reference
EXTI Exported Types

EXTI Configuration structure definition. More...

#include <stm32g4xx_hal_exti.h>

Data Fields

uint32_t | Line
uint32_t | Mode
uint32_t | Trigger
uint32_t | GPIOSel

Detailed Description

EXTI Configuration structure definition.

Definition at line 62 of file stm32g4xx_hal_exti.h.

Field Documentation

uint32_t EXTI_ConfigTypeDef::GPIOSel

The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of EXTI GPIOSel

Definition at line 70 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Line

The Exti line to be configured. This parameter can be a value of EXTI Line

Definition at line 64 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Mode

The Exit Mode to be configured for a core. This parameter can be a combination of EXTI Mode

Definition at line 66 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Trigger

The Exti Trigger to be configured. This parameter can be a value of EXTI Trigger

Definition at line 68 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_exti.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Line

Defines
EXTI Line
EXTI Exported Constants

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define | EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
#define | EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
#define | EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
#define | EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)

Define Documentation

#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)

Definition at line 87 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)

Definition at line 88 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)

Definition at line 97 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)

Definition at line 98 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)

Definition at line 99 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)

Definition at line 100 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)

Definition at line 101 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)

Definition at line 102 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)

Definition at line 103 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)

Definition at line 104 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)

Definition at line 105 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)

Definition at line 106 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)

Definition at line 89 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)

Definition at line 107 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)

Definition at line 108 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)

Definition at line 109 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)

Definition at line 110 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)

Definition at line 111 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)

Definition at line 112 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)

Definition at line 113 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)

Definition at line 114 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)

Definition at line 115 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)

Definition at line 116 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)

Definition at line 90 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)

Definition at line 117 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)

Definition at line 118 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)

Definition at line 119 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)

Definition at line 120 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)

Definition at line 121 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)

Definition at line 122 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)

Definition at line 123 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)

Definition at line 124 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)

Definition at line 125 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)

Definition at line 126 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)

Definition at line 91 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)

Definition at line 127 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)

Definition at line 128 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)

Definition at line 129 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)

Definition at line 130 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)

Definition at line 92 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)

Definition at line 93 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)

Definition at line 94 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)

Definition at line 95 of file stm32g4xx_hal_exti.h.

#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)

Definition at line 96 of file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Mode

Defines
EXTI Mode
EXTI Exported Constants

Defines

#define | EXTI_MODE_NONE 0x00000000U
#define | EXTI_MODE_INTERRUPT 0x00000001U
#define | EXTI_MODE_EVENT 0x00000002U

Define Documentation

#define EXTI_MODE_EVENT 0x00000002U

Definition at line 140 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_INTERRUPT 0x00000001U

Definition at line 139 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_NONE 0x00000000U

Definition at line 138 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Trigger

Defines
EXTI Trigger
EXTI Exported Constants

Defines

#define | EXTI_TRIGGER_NONE 0x00000000U
#define | EXTI_TRIGGER_RISING 0x00000001U
#define | EXTI_TRIGGER_FALLING 0x00000002U
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Define Documentation

#define EXTI_TRIGGER_FALLING 0x00000002U

Definition at line 150 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_NONE 0x00000000U

Definition at line 148 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

#define EXTI_TRIGGER_RISING 0x00000001U

Definition at line 149 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Definition at line 151 of file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI GPIOSel

Defines
EXTI GPIOSel
EXTI Exported Constants

Defines

#define | EXTI_GPIOA 0x00000000U
#define | EXTI_GPIOB 0x00000001U
#define | EXTI_GPIOC 0x00000002U
#define | EXTI_GPIOD 0x00000003U
#define | EXTI_GPIOE 0x00000004U
#define | EXTI_GPIOF 0x00000005U
#define | EXTI_GPIOG 0x00000006U

Define Documentation

#define EXTI_GPIOA 0x00000000U

Definition at line 160 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOB 0x00000001U

Definition at line 161 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOC 0x00000002U

Definition at line 162 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOD 0x00000003U

Definition at line 163 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOE 0x00000004U

Definition at line 164 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOF 0x00000005U

Definition at line 165 of file stm32g4xx_hal_exti.h.

#define EXTI_GPIOG 0x00000006U

Definition at line 166 of file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Macros

EXTI Exported Macros
EXTI
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_EXTI_LINE(__EXTI_LINE__)
#define | IS_EXTI_MODE(__EXTI_LINE__)
#define | IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define | IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
#define | IS_EXTI_PENDING_EDGE(__EDGE__)
#define | IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)

Define Documentation

#define IS_EXTI_CB ( __CB__ ) ((__CB__) == HAL_EXTI_COMMON_CB_ID)

Definition at line 258 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_RegisterCallback().

#define IS_EXTI_CONFIG_LINE ( __EXTI_LINE__ ) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)

Definition at line 242 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), and HAL_EXTI_GetPending().

#define IS_EXTI_GPIO_PIN ( __PIN__ ) ((__PIN__) < 16u)

Definition at line 252 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_GPIO_PORT ( __PORT__ )
Value:
(((__PORT__) == EXTI_GPIOA) || \
                                         ((__PORT__) == EXTI_GPIOB) || \
                                         ((__PORT__) == EXTI_GPIOC) || \
                                         ((__PORT__) == EXTI_GPIOD) || \
                                         ((__PORT__) == EXTI_GPIOE) || \
                                         ((__PORT__) == EXTI_GPIOF) || \
                                         ((__PORT__) == EXTI_GPIOG))

Definition at line 244 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_LINE ( __EXTI_LINE__ )
Value:
((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
                                              ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
                                               (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
                                               (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
                                              (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
                                               (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))

Definition at line 230 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_MODE ( __EXTI_LINE__ )
Value:
((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))

Definition at line 237 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_PENDING_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == EXTI_TRIGGER_RISING)   || \
                                          ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
                                          ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))

Definition at line 254 of file stm32g4xx_hal_exti.h.

#define IS_EXTI_TRIGGER ( __EXTI_LINE__ ) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)

Definition at line 240 of file stm32g4xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions

Functions
Configuration functions
EXTI Exported Functions

Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.

Detailed Description

Configuration functions.

 ===============================================================================
              ##### Configuration functions #####
 ===============================================================================

Function Documentation

HAL_StatusTypeDef HAL_EXTI_ClearConfigLine ( EXTI_HandleTypeDef * hexti )

Clear whole configuration of a dedicated Exti line.

Parameters:
hexti Exti handle.
Return values:
HAL Status.

Definition at line 364 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_GetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Get configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on structure to store Exti configuration.
Return values:
HAL Status.

Definition at line 268 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_NONE, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_NONE, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

HAL_StatusTypeDef HAL_EXTI_GetHandle | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | ExtiLine
 | ) |  |

Store line number as handle private field.

Parameters:
hexti | Exti handle.
ExtiLine | Exti line number. This parameter can be from 0 to EXTI_LINE_NB.
Return values:
HAL Status.

Definition at line 463 of file stm32g4xx_hal_exti.c.

References assert_param, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_RegisterCallback | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_CallbackIDTypeDef | CallbackID,
 |  | void(*)(void) | pPendingCbfn
 | ) |  |

Register callback for a dedicated Exti line.

Parameters:
hexti | Exti handle.
CallbackID User callback identifier. This parameter can be one of
  • EXTI_CallbackIDTypeDef values.
pPendingCbfn | function pointer to be stored as callback.
Return values:
HAL Status.

Definition at line 432 of file stm32g4xx_hal_exti.c.

References assert_param, HAL_EXTI_COMMON_CB_ID, IS_EXTI_CB, and EXTI_HandleTypeDef::PendingCallback.

HAL_StatusTypeDef HAL_EXTI_SetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Set configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on EXTI configuration to be set.
Return values:
HAL Status.

Definition at line 144 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_GPIO_PORT, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
EXTI Exported Functions

IO operation functions. More...

Functions

void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

IO operation functions.

EXTI IO functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_EXTI_ClearPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Clear interrupt pending bit of a dedicated line.

Parameters:
hexti | Exti handle.
Edge | unused
Return values:
None.

Definition at line 574 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, and UNUSED.

void HAL_EXTI_GenerateSWI ( EXTI_HandleTypeDef * hexti )

Generate a software interrupt for a dedicated line.

Parameters:
hexti Exti handle.
Return values:
None.

Definition at line 603 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

uint32_t HAL_EXTI_GetPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Get interrupt pending bit of a dedicated line.

Parameters:
hexti | Exti handle.
Edge | unused
Return values:
1 if interrupt is pending else 0.

Definition at line 539 of file stm32g4xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, and UNUSED.

void HAL_EXTI_IRQHandler ( EXTI_HandleTypeDef * hexti )

Handle EXTI interrupt request.

Parameters:
hexti Exti handle.
Return values:
none.

Definition at line 504 of file stm32g4xx_hal_exti.c.

References EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_HandleTypeDef::Line, and EXTI_HandleTypeDef::PendingCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FDCAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the FDCAN.
      (+) De-initialize the FDCAN.
      (+) Enter FDCAN peripheral in power down mode.
      (+) Exit power down mode.
      (+) Register callbacks.
      (+) Unregister callbacks.

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_DeInit ( FDCAN_HandleTypeDef * hfdcan )

Deinitializes the FDCAN peripheral registers to their default reset values.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 532 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_MspDeInit(), HAL_FDCAN_STATE_RESET, HAL_FDCAN_Stop(), __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::MspDeInitCallback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Enter FDCAN peripheral in sleep mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 608 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Exit power down mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 643 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Init ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 289 of file stm32g4xx_hal_fdcan.c.

References assert_param, FDCAN_InitTypeDef::AutoRetransmission, FDCAN_InitTypeDef::ClockDivider, FDCAN_InitTypeDef::DataPrescaler, FDCAN_InitTypeDef::DataSyncJumpWidth, FDCAN_InitTypeDef::DataTimeSeg1, FDCAN_InitTypeDef::DataTimeSeg2, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_CalcultateRamBlockAddresses(), FDCAN_FRAME_FD_BRS, FDCAN_MODE_BUS_MONITORING, FDCAN_MODE_INTERNAL_LOOPBACK, FDCAN_MODE_NORMAL, FDCAN_MODE_RESTRICTED_OPERATION, FDCAN_TIMEOUT_VALUE, FDCAN_InitTypeDef::FrameFormat, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspInit(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), HAL_GetTick(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_CKDIV, IS_FDCAN_DATA_PRESCALER, IS_FDCAN_DATA_SJW, IS_FDCAN_DATA_TSEG1, IS_FDCAN_DATA_TSEG2, IS_FDCAN_FRAME_FORMAT, IS_FDCAN_MAX_VALUE, IS_FDCAN_MODE, IS_FDCAN_NOMINAL_PRESCALER, IS_FDCAN_NOMINAL_SJW, IS_FDCAN_NOMINAL_TSEG1, IS_FDCAN_NOMINAL_TSEG2, IS_FDCAN_TX_FIFO_QUEUE_MODE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, __FDCAN_HandleTypeDef::Lock, FDCAN_InitTypeDef::Mode, __FDCAN_HandleTypeDef::MspInitCallback, FDCAN_InitTypeDef::NominalPrescaler, FDCAN_InitTypeDef::NominalSyncJumpWidth, FDCAN_InitTypeDef::NominalTimeSeg1, FDCAN_InitTypeDef::NominalTimeSeg2, FDCAN_InitTypeDef::ProtocolException, __FDCAN_HandleTypeDef::RxFifo0Callback, __FDCAN_HandleTypeDef::RxFifo1Callback, SRAMCAN_FLE_NBR, SRAMCAN_FLS_NBR, __FDCAN_HandleTypeDef::State, FDCAN_InitTypeDef::StdFiltersNbr, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, FDCAN_InitTypeDef::TransmitPause, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, __FDCAN_HandleTypeDef::TxEventFifoCallback, __FDCAN_HandleTypeDef::TxFifoEmptyCallback, and FDCAN_InitTypeDef::TxFifoQueueMode.

void HAL_FDCAN_MspDeInit ( FDCAN_HandleTypeDef * hfdcan )

DeInitializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 593 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_DeInit(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_MspInit ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 578 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), and HAL_FDCAN_UnRegisterCallback().

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | void(*)(FDCAN_HandleTypeDef *_hFDCAN) | pCallback
 | ) |  |

Register a FDCAN CallBack.

To be used instead of the weak predefined callback

Parameters:
hfdcan | pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 693 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | pFDCAN_CallbackTypeDef | pCallback
 | ) |  |
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_ErrorStatusCallbackTypeDef | pCallback
 | ) |  |

Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Error Status Callback function
Return values:
HAL status

Definition at line 1188 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo0CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 0 Callback function
Return values:
HAL status

Definition at line 942 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo1CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 1 Callback function
Return values:
HAL status

Definition at line 1003 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferAbortCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Abort Callback function
Return values:
HAL status

Definition at line 1126 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferCompleteCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Complete Callback function
Return values:
HAL status

Definition at line 1064 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxEventFifoCallbackTypeDef | pCallback
 | ) |  |

Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Event Fifo Callback function
Return values:
HAL status

Definition at line 881 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a FDCAN CallBack.

FDCAN callback is redirected to the weak predefined callback

Parameters:
hfdcan pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 796 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspDeInit(), HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MspInit(), HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1222 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 976 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1037 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1161 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferAbortCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1099 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferCompleteCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 915 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxEventFifoCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions

Functions
Configuration functions
FDCAN Exported Functions

FDCAN Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.

Detailed Description

FDCAN Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Mask
 | ) |  |

Configure the extended ID mask.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Mask | Extended ID Mask. This parameter must be a number between 0 and 0x1FFFFFFF.
Return values:
HAL status

Definition at line 1420 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | const FDCAN_FilterTypeDef * | sFilterConfig
 | ) |  |

Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sFilterConfig | pointer to an FDCAN_FilterTypeDef structure that contains the filter configuration information
Return values:
HAL status

Definition at line 1292 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_STANDARD_ID, FDCAN_FilterTypeDef::FilterConfig, FDCAN_FilterTypeDef::FilterID1, FDCAN_FilterTypeDef::FilterID2, FDCAN_FilterTypeDef::FilterIndex, FDCAN_FilterTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_FilterTypeDef::IdType, __FDCAN_HandleTypeDef::Init, IS_FDCAN_EXT_FILTER_TYPE, IS_FDCAN_FILTER_CFG, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_STD_FILTER_TYPE, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_FLE_SIZE, SRAMCAN_FLS_SIZE, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, __FDCAN_HandleTypeDef::State, and FDCAN_InitTypeDef::StdFiltersNbr.

HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NonMatchingStd,
 |  | uint32_t | NonMatchingExt,
 |  | uint32_t | RejectRemoteStd,
 |  | uint32_t | RejectRemoteExt
 | ) |  |

Configure the FDCAN global filter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NonMatchingStd Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
NonMatchingExt Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
Return values:
HAL status

Definition at line 1376 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_NON_MATCHING, IS_FDCAN_REJECT_REMOTE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | CounterStartValue
 | ) |  |

Configure the RAM watchdog.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
CounterStartValue | Start value of the Message RAM Watchdog Counter, This parameter must be a number between 0x00 and 0xFF, with the reset value of 0x00 the counter is disabled.
Return values:
HAL status

Definition at line 1494 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo,
 |  | uint32_t | OperationMode
 | ) |  |

Configure the Rx FIFO operation mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
OperationMode operation mode. This parameter can be a value of
  • FDCAN_Rx_FIFO_operation_mode.
Return values:
HAL status

Definition at line 1454 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RX_FIFO0, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, IS_FDCAN_RX_FIFO_MODE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeoutOperation,
 |  | uint32_t | TimeoutPeriod
 | ) |  |

Configure the timeout counter.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeoutOperation Timeout counter operation. This parameter can be a value of
  • FDCAN_Timeout_Operation.
TimeoutPeriod | Start value of the timeout down-counter. This parameter must be a number between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 1649 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TIMEOUT, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampPrescaler
 | ) |  |

Configure the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampPrescaler Timestamp Counter Prescaler. This parameter can be a value of
  • FDCAN_Timestamp_Prescaler.
Return values:
HAL status

Definition at line 1524 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP_PRESCALER, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TdcOffset,
 |  | uint32_t | TdcFilter
 | ) |  |

Configure the transmitter delay compensation.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TdcOffset | Transmitter Delay Compensation Offset. This parameter must be a number between 0x00 and 0x7F.
TdcFilter | Transmitter Delay Compensation Filter Window Length. This parameter must be a number between 0x00 and 0x7F.
Return values:
HAL status

Definition at line 1771 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Disable edge filtering during bus integration.

One dominant tq is required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1930 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Disable ISO 11898-1 protocol mode.

CAN FD frame format is according to Bosch CAN FD specification V1.0.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1878 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1705 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1582 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Disable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1826 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Enable edge filtering during bus integration.

Two consecutive dominant tq are required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1904 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Enable ISO 11898-1 protocol mode.

CAN FD frame format is according to ISO 11898-1 standard.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1852 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Enable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1680 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampOperation
 | ) |  |

Enable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampOperation Timestamp counter operation. This parameter can be a value of
  • FDCAN_Timestamp.
Return values:
HAL status

Definition at line 1554 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Enable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1801 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

uint16_t HAL_FDCAN_GetTimeoutCounter ( const FDCAN_HandleTypeDef * hfdcan )

Get the timeout counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Timeout counter value

Definition at line 1730 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint16_t HAL_FDCAN_GetTimestampCounter ( const FDCAN_HandleTypeDef * hfdcan )

Get the timestamp counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Timestamp counter value

Definition at line 1607 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timeout counter to its start value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1741 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_CONTINUOUS, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timestamp counter to zero.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1618 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMESTAMP_EXTERNAL, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Control functions

Functions
Control functions
FDCAN Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (const FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (const FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (const FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.

Detailed Description

Control functions.

  ==============================================================================
                          ##### Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_Start                         : Start the FDCAN module
      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
                                                    transmission request
      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx FIFO zone into the message RAM
      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
                                                    into the message RAM
      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
                                                    on the selected Tx buffer
      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Abort transmission request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 2185 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TX_LOCATION_LIST, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | const FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | const uint8_t * | pTxData
 | ) |  |

Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
Return values:
HAL status

Definition at line 2103 of file stm32g4xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_FULL, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Exit Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2615 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ErrorCountersTypeDef * | ErrorCounters
 | ) |  |

Get error counter values.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorCounters | pointer to an FDCAN_ErrorCountersTypeDef structure.
Return values:
HAL status

Definition at line 2503 of file stm32g4xx_hal_fdcan.c.

References FDCAN_ErrorCountersTypeDef::ErrorLogging, __FDCAN_HandleTypeDef::Instance, FDCAN_ErrorCountersTypeDef::RxErrorCnt, FDCAN_ErrorCountersTypeDef::RxErrorPassive, and FDCAN_ErrorCountersTypeDef::TxErrorCnt.

HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_HpMsgStatusTypeDef * | HpMsgStatus
 | ) |  |

Get high priority message status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
HpMsgStatus | pointer to an FDCAN_HpMsgStatusTypeDef structure.
Return values:
HAL status

Definition at line 2452 of file stm32g4xx_hal_fdcan.c.

References FDCAN_HpMsgStatusTypeDef::FilterIndex, FDCAN_HpMsgStatusTypeDef::FilterList, __FDCAN_HandleTypeDef::Instance, FDCAN_HpMsgStatusTypeDef::MessageIndex, and FDCAN_HpMsgStatusTypeDef::MessageStorage.

uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer ( const FDCAN_HandleTypeDef * hfdcan )

Get Tx buffer index of latest Tx FIFO/Queue request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Tx buffer index of last Tx FIFO/Queue request
  • Any value of
    • FDCAN_Tx_location if Tx request has been submitted.
  • 0 if no Tx FIFO/Queue request have been submitted.

Definition at line 2171 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::LatestTxFifoQRequest.

HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ProtocolStatusTypeDef * | ProtocolStatus
 | ) |  |

Get protocol status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ProtocolStatus | pointer to an FDCAN_ProtocolStatusTypeDef structure.
Return values:
HAL status

Definition at line 2471 of file stm32g4xx_hal_fdcan.c.

References FDCAN_ProtocolStatusTypeDef::Activity, FDCAN_ProtocolStatusTypeDef::BusOff, FDCAN_ProtocolStatusTypeDef::DataLastErrorCode, FDCAN_ProtocolStatusTypeDef::ErrorPassive, __FDCAN_HandleTypeDef::Instance, FDCAN_ProtocolStatusTypeDef::LastErrorCode, FDCAN_ProtocolStatusTypeDef::ProtocolException, FDCAN_ProtocolStatusTypeDef::RxBRSflag, FDCAN_ProtocolStatusTypeDef::RxESIflag, FDCAN_ProtocolStatusTypeDef::RxFDFflag, FDCAN_ProtocolStatusTypeDef::TDCvalue, and FDCAN_ProtocolStatusTypeDef::Warning.

uint32_t HAL_FDCAN_GetRxFifoFillLevel | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo
 | ) |  |

Return Rx FIFO fill level.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
Return values:
Rx FIFO fill level.

Definition at line 2554 of file stm32g4xx_hal_fdcan.c.

References assert_param, FDCAN_RX_FIFO0, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_RX_FIFO.

HAL_StatusTypeDef HAL_FDCAN_GetRxMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxLocation,
 |  | FDCAN_RxHeaderTypeDef * | pRxHeader,
 |  | uint8_t * | pRxData
 | ) |  |

Get an FDCAN frame from the Rx FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxLocation Location of the received message to be read. This parameter can be a value of
  • FDCAN_Rx_location.
pRxHeader | pointer to a FDCAN_RxHeaderTypeDef structure.
pRxData | pointer to a buffer where the payload of the Rx frame will be stored.
Return values:
HAL status

Definition at line 2217 of file stm32g4xx_hal_fdcan.c.

References assert_param, FDCAN_RxHeaderTypeDef::BitRateSwitch, FDCAN_RxHeaderTypeDef::DataLength, DLCtoBytes, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RxHeaderTypeDef::ErrorStateIndicator, FDCAN_ELEMENT_MASK_ANMF, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_FIDX, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_RX_FIFO0, FDCAN_RX_FIFO_OVERWRITE, FDCAN_STANDARD_ID, FDCAN_RxHeaderTypeDef::FDFormat, FDCAN_RxHeaderTypeDef::FilterIndex, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_RxHeaderTypeDef::Identifier, FDCAN_RxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_RxHeaderTypeDef::RxFrameType, FDCAN_RxHeaderTypeDef::RxTimestamp, SRAMCAN_RF0_SIZE, SRAMCAN_RF1_SIZE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetTxEvent | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxEventFifoTypeDef * | pTxEvent
 | ) |  |

Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxEvent | pointer to a FDCAN_TxEventFifoTypeDef structure.
Return values:
HAL status

Definition at line 2369 of file stm32g4xx_hal_fdcan.c.

References FDCAN_TxEventFifoTypeDef::BitRateSwitch, FDCAN_TxEventFifoTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxEventFifoTypeDef::ErrorStateIndicator, FDCAN_TxEventFifoTypeDef::EventType, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_ET, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_MM, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_STANDARD_ID, FDCAN_TxEventFifoTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_TxEventFifoTypeDef::Identifier, FDCAN_TxEventFifoTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, FDCAN_TxEventFifoTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_TEF_SIZE, __FDCAN_HandleTypeDef::State, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_TxEventFifoTypeDef::TxFrameType, and FDCAN_TxEventFifoTypeDef::TxTimestamp.

uint32_t HAL_FDCAN_GetTxFifoFreeLevel ( const FDCAN_HandleTypeDef * hfdcan )

Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Tx FIFO free level.

Definition at line 2581 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRestrictedOperationMode ( const FDCAN_HandleTypeDef * hfdcan )

Check if the FDCAN peripheral entered Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Status
  • 0 : Normal FDCAN operation.
  • 1 : Restricted Operation Mode active.

Definition at line 2599 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsTxBufferMessagePending | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxBufferIndex
 | ) |  |

Check if a transmission request is pending on the selected Tx buffer.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxBufferIndex Tx buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
Status
  • 0 : No pending transmission request on TxBufferIndex list.
  • 1 : Pending transmission request on TxBufferIndex.

Definition at line 2531 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_TX_LOCATION_LIST.

HAL_StatusTypeDef HAL_FDCAN_Start ( FDCAN_HandleTypeDef * hfdcan )

Start the FDCAN module.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1990 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Stop ( FDCAN_HandleTypeDef * hfdcan )

Stop the FDCAN module and enable access to configuration registers.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2021 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, and __FDCAN_HandleTypeDef::State.

Referenced by HAL_FDCAN_DeInit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupts management

Functions
Interrupts management
FDCAN Exported Functions

Interrupts management. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.

Detailed Description

Interrupts management.

  ==============================================================================
                       ##### Interrupts management #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveITs,
 |  | uint32_t | BufferIndexes
 | ) |  |

Enable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveITs indicates which interrupts will be enabled. This parameter can be any combination of
  • FDCAN_Interrupts.
BufferIndexes Tx Buffer Indexes. This parameter can be any combination of
  • FDCAN_Tx_location. This parameter is ignored if ActiveITs does not include one of the following:
    • FDCAN_IT_TX_COMPLETE
    • FDCAN_IT_TX_ABORT_COMPLETE
Return values:
HAL status

Definition at line 2712 of file stm32g4xx_hal_fdcan.c.

References __HAL_FDCAN_ENABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_GROUP_BIT_LINE_ERROR, FDCAN_IT_GROUP_MISC, FDCAN_IT_GROUP_PROTOCOL_ERROR, FDCAN_IT_GROUP_RX_FIFO0, FDCAN_IT_GROUP_RX_FIFO1, FDCAN_IT_GROUP_SMSG, FDCAN_IT_GROUP_TX_FIFO_ERROR, FDCAN_IT_LIST_BIT_LINE_ERROR, FDCAN_IT_LIST_MISC, FDCAN_IT_LIST_PROTOCOL_ERROR, FDCAN_IT_LIST_RX_FIFO0, FDCAN_IT_LIST_RX_FIFO1, FDCAN_IT_LIST_SMSG, FDCAN_IT_LIST_TX_FIFO_ERROR, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, IS_FDCAN_TX_LOCATION_LIST, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ITList indicates which interrupts group will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_Interrupts_Group.
InterruptLine Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 2667 of file stm32g4xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT_GROUP, IS_FDCAN_IT_LINE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveITs
 | ) |  |

Disable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveITs indicates which interrupts will be disabled. This parameter can be any combination of
  • FDCAN_Interrupts.
Return values:
HAL status

Definition at line 2805 of file stm32g4xx_hal_fdcan.c.

References __HAL_FDCAN_DISABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_GROUP_BIT_LINE_ERROR, FDCAN_IT_GROUP_MISC, FDCAN_IT_GROUP_PROTOCOL_ERROR, FDCAN_IT_GROUP_RX_FIFO0, FDCAN_IT_GROUP_RX_FIFO1, FDCAN_IT_GROUP_SMSG, FDCAN_IT_GROUP_TX_FIFO_ERROR, FDCAN_IT_LIST_BIT_LINE_ERROR, FDCAN_IT_LIST_MISC, FDCAN_IT_LIST_PROTOCOL_ERROR, FDCAN_IT_LIST_RX_FIFO0, FDCAN_IT_LIST_RX_FIFO1, FDCAN_IT_LIST_SMSG, FDCAN_IT_LIST_TX_FIFO_ERROR, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, and __FDCAN_HandleTypeDef::State.

void HAL_FDCAN_IRQHandler ( FDCAN_HandleTypeDef * hfdcan )

Handles FDCAN interrupt request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2901 of file stm32g4xx_hal_fdcan.c.

References __HAL_FDCAN_CLEAR_FLAG, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_CHECK_FLAG, FDCAN_CHECK_IT_SOURCE, FDCAN_ERROR_MASK, FDCAN_ERROR_STATUS_MASK, FDCAN_FLAG_RAM_ACCESS_FAILURE, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG, FDCAN_FLAG_TIMEOUT_OCCURRED, FDCAN_FLAG_TIMESTAMP_WRAPAROUND, FDCAN_FLAG_TX_ABORT_COMPLETE, FDCAN_FLAG_TX_COMPLETE, FDCAN_FLAG_TX_FIFO_EMPTY, FDCAN_IT_RAM_ACCESS_FAILURE, FDCAN_IT_RX_HIGH_PRIORITY_MSG, FDCAN_IT_TIMEOUT_OCCURRED, FDCAN_IT_TIMESTAMP_WRAPAROUND, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, FDCAN_IT_TX_FIFO_EMPTY, FDCAN_RX_FIFO0_MASK, FDCAN_RX_FIFO1_MASK, FDCAN_TX_EVENT_FIFO_MASK, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_RAM_ACCESS, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::RxFifo0Callback, __FDCAN_HandleTypeDef::RxFifo1Callback, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, __FDCAN_HandleTypeDef::TxEventFifoCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Callback functions

Functions
Callback functions
FDCAN Exported Functions

FDCAN Callback functions. More...

Functions

__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.

Detailed Description

FDCAN Callback functions.

  ==============================================================================
                          ##### Callback functions #####
  ==============================================================================
    [..]
    This subsection provides the following callback functions:
      (+) HAL_FDCAN_TxEventFifoCallback
      (+) HAL_FDCAN_RxFifo0Callback
      (+) HAL_FDCAN_RxFifo1Callback
      (+) HAL_FDCAN_TxFifoEmptyCallback
      (+) HAL_FDCAN_TxBufferCompleteCallback
      (+) HAL_FDCAN_TxBufferAbortCallback
      (+) HAL_FDCAN_HighPriorityMessageCallback
      (+) HAL_FDCAN_TimestampWraparoundCallback
      (+) HAL_FDCAN_TimeoutOccurredCallback
      (+) HAL_FDCAN_ErrorCallback
      (+) HAL_FDCAN_ErrorStatusCallback

Function Documentation

void HAL_FDCAN_ErrorCallback ( FDCAN_HandleTypeDef * hfdcan )

Error callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3331 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_ErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ErrorStatusITs
 | ) |  |

Error status callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorStatusITs indicates which Error Status interrupts are signaled. This parameter can be any combination of
  • FDCAN_Error_Status_Interrupts.
Return values:
None

Definition at line 3349 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void HAL_FDCAN_HighPriorityMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

High Priority Message callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3315 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_RxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo0ITs
 | ) |  |

Rx FIFO 0 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. This parameter can be any combination of
  • FDCAN_Rx_Fifo0_Interrupts.
Return values:
None

Definition at line 3193 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void HAL_FDCAN_RxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo1ITs
 | ) |  |

Rx FIFO 1 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. This parameter can be any combination of
  • FDCAN_Rx_Fifo1_Interrupts.
Return values:
None

Definition at line 3212 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

void HAL_FDCAN_TimeoutOccurredCallback ( FDCAN_HandleTypeDef * hfdcan )

Timeout Occurred callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3299 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TimestampWraparoundCallback ( FDCAN_HandleTypeDef * hfdcan )

Timestamp Wraparound callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3283 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Cancellation callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the aborted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 3266 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void HAL_FDCAN_TxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Complete callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the transmitted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 3247 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void HAL_FDCAN_TxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxEventFifoITs
 | ) |  |

Tx Event callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. This parameter can be any combination of
  • FDCAN_Tx_Event_Fifo_Interrupts.
Return values:
None

Definition at line 3174 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void HAL_FDCAN_TxFifoEmptyCallback ( FDCAN_HandleTypeDef * hfdcan )

Tx FIFO Empty callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3229 of file stm32g4xx_hal_fdcan.c.

References UNUSED.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
FDCAN Exported Functions

FDCAN Peripheral State functions. More...

Functions

HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Detailed Description

FDCAN Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.

Function Documentation

uint32_t HAL_FDCAN_GetError ( const FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN error code.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
FDCAN Error Code

Definition at line 3397 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode.

HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState ( const FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN state.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL state

Definition at line 3385 of file stm32g4xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Private Functions

Functions
FDCAN Private Functions
FDCAN

Functions

static void | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.

Function Documentation

static void FDCAN_CalcultateRamBlockAddresses ( FDCAN_HandleTypeDef * hfdcan ) [static]

Calculate each RAM block start address and size.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
none

Definition at line 3421 of file stm32g4xx_hal_fdcan.c.

References FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, SRAMCAN_FLESA, SRAMCAN_FLSSA, SRAMCAN_RF0SA, SRAMCAN_RF1SA, SRAMCAN_SIZE, SRAMCAN_TEFSA, SRAMCAN_TFQSA, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, FDCAN_InitTypeDef::StdFiltersNbr, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, and FDCAN_MsgRamAddressTypeDef::TxFIFOQSA.

Referenced by HAL_FDCAN_Init().

static void FDCAN_CopyMessageToRAM | ( | const FDCAN_HandleTypeDef * | hfdcan,
 |  | const FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | const uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  | [static]

Copy Tx message to the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
BufferIndex | index of the buffer to be configured.
Return values:
none

Definition at line 3479 of file stm32g4xx_hal_fdcan.c.

References FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, DLCtoBytes, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_TFQ_SIZE, FDCAN_TxHeaderTypeDef::TxEventFifoControl, FDCAN_MsgRamAddressTypeDef::TxFIFOQSA, and FDCAN_TxHeaderTypeDef::TxFrameType.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Exported Types

Data Structures | Typedefs | Enumerations
FDCAN Exported Types
FDCAN

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U,
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, HAL_FDCAN_MSPINIT_CB_ID = 0x05U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U
}
HAL FDCAN common Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __FDCAN_HandleTypeDef FDCAN_HandleTypeDef

FDCAN handle structure definition.

typedef void(* pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan)

HAL FDCAN Callback pointer definition.

pointer to a common FDCAN callback function

Definition at line 489 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

pointer to Error Status callback function

Definition at line 495 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

pointer to Rx Fifo 0 FDCAN callback function

Definition at line 491 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

pointer to Rx Fifo 1 FDCAN callback function

Definition at line 492 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer abort FDCAN callback function

Definition at line 494 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer complete FDCAN callback function

Definition at line 493 of file stm32g4xx_hal_fdcan.h.

typedef void(* pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

pointer to Tx event Fifo FDCAN callback function

Definition at line 490 of file stm32g4xx_hal_fdcan.h.

Enumeration Type Documentation

enum HAL_FDCAN_CallbackIDTypeDef

HAL FDCAN common Callback ID enumeration definition.

Enumerator:
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID

FDCAN Tx Fifo Empty callback ID

HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID

FDCAN High priority message callback ID

HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID

FDCAN Timestamp wraparound callback ID

HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID

FDCAN Timeout occurred callback ID

HAL_FDCAN_ERROR_CALLBACK_CB_ID

FDCAN Error callback ID

HAL_FDCAN_MSPINIT_CB_ID

FDCAN MspInit callback ID

HAL_FDCAN_MSPDEINIT_CB_ID

FDCAN MspDeInit callback ID

Definition at line 473 of file stm32g4xx_hal_fdcan.h.

enum HAL_FDCAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_FDCAN_STATE_RESET

FDCAN not yet initialized or disabled

HAL_FDCAN_STATE_READY

FDCAN initialized and ready for use

HAL_FDCAN_STATE_BUSY

FDCAN process is ongoing

HAL_FDCAN_STATE_ERROR

FDCAN error state

Definition at line 48 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_InitTypeDef Struct Reference
FDCAN Exported Types

FDCAN Init structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | ClockDivider
uint32_t | FrameFormat
uint32_t | Mode
FunctionalState | AutoRetransmission
FunctionalState | TransmitPause
FunctionalState | ProtocolException
uint32_t | NominalPrescaler
uint32_t | NominalSyncJumpWidth
uint32_t | NominalTimeSeg1
uint32_t | NominalTimeSeg2
uint32_t | DataPrescaler
uint32_t | DataSyncJumpWidth
uint32_t | DataTimeSeg1
uint32_t | DataTimeSeg2
uint32_t | StdFiltersNbr
uint32_t | ExtFiltersNbr
uint32_t | TxFifoQueueMode

Detailed Description

FDCAN Init structure definition.

Definition at line 59 of file stm32g4xx_hal_fdcan.h.

Field Documentation

FunctionalState FDCAN_InitTypeDef::AutoRetransmission

Enable or disable the automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 73 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ClockDivider

Specifies the FDCAN kernel clock divider. The clock is common to all FDCAN instances. This parameter is applied only at initialisation of first FDCAN instance. This parameter can be a value of FDCAN Clock Divider.

Definition at line 61 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataPrescaler

Specifies the value by which the oscillator frequency is divided for generating the data bit time quanta. This parameter must be a number between 1 and 32

Definition at line 97 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a data bit to perform resynchronization. This parameter must be a number between 1 and 16

Definition at line 101 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg1

Specifies the number of time quanta in Data Bit Segment 1. This parameter must be a number between 1 and 32

Definition at line 106 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg2

Specifies the number of time quanta in Data Bit Segment 2. This parameter must be a number between 1 and 16

Definition at line 109 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ExtFiltersNbr

Specifies the number of extended Message ID filters. This parameter must be a number between 0 and 8

Definition at line 115 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::FrameFormat

Specifies the FDCAN frame format. This parameter can be a value of FDCAN Frame Format

Definition at line 67 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::Mode

Specifies the FDCAN mode. This parameter can be a value of FDCAN Operating Mode

Definition at line 70 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalPrescaler

Specifies the value by which the oscillator frequency is divided for generating the nominal bit time quanta. This parameter must be a number between 1 and 512

Definition at line 82 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter must be a number between 1 and 128

Definition at line 86 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg1

Specifies the number of time quanta in Bit Segment 1. This parameter must be a number between 2 and 256

Definition at line 91 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg2

Specifies the number of time quanta in Bit Segment 2. This parameter must be a number between 2 and 128

Definition at line 94 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::ProtocolException

Enable or disable the Protocol Exception Handling. This parameter can be set to ENABLE or DISABLE

Definition at line 79 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::StdFiltersNbr

Specifies the number of standard Message ID filters. This parameter must be a number between 0 and 28

Definition at line 112 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::TransmitPause

Enable or disable the Transmit Pause feature. This parameter can be set to ENABLE or DISABLE

Definition at line 76 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueMode

Tx FIFO/Queue Mode selection. This parameter can be a value of FDCAN Tx FIFO/Queue Mode

Definition at line 118 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_FilterTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_FilterTypeDef Struct Reference
FDCAN Exported Types

FDCAN filter structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | IdType
uint32_t | FilterIndex
uint32_t | FilterType
uint32_t | FilterConfig
uint32_t | FilterID1
uint32_t | FilterID2

Detailed Description

FDCAN filter structure definition.

Definition at line 126 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_FilterTypeDef::FilterConfig

Specifies the filter configuration. This parameter can be a value of FDCAN Filter Configuration

Definition at line 141 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID1

Specifies the filter identification 1. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 144 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID2

Specifies the filter identification 2. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 149 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterIndex

Specifies the filter which will be initialized. This parameter must be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
  • 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID

Definition at line 131 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterType

Specifies the filter type. This parameter can be a value of FDCAN Filter Type. The value FDCAN_FILTER_RANGE_NO_EIDM is permitted only when IdType is FDCAN_EXTENDED_ID.

Definition at line 136 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IdType

Specifies the identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 128 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_TxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx header structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxEventFifoControl
uint32_t | MessageMarker

Detailed Description

FDCAN Tx header structure definition.

Definition at line 159 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxHeaderTypeDef::BitRateSwitch

Specifies whether the Tx frame will be transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 179 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::DataLength

Specifies the length of the frame that will be transmitted. This parameter can be a value of FDCAN Data Length Code

Definition at line 173 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 176 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::FDFormat

Specifies whether the Tx frame will be transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 183 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 161 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::IdType

Specifies the identifier type for the message that will be transmitted. This parameter can be a value of FDCAN ID Type

Definition at line 166 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::MessageMarker

Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 190 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxEventFifoControl

Specifies the event FIFO control. This parameter can be a value of FDCAN Event FIFO control

Definition at line 187 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxFrameType

Specifies the frame type of the message that will be transmitted. This parameter can be a value of FDCAN Frame Type

Definition at line 170 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_RxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_RxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Rx header structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | RxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | RxTimestamp
uint32_t | FilterIndex
uint32_t | IsFilterMatchingFrame

Detailed Description

FDCAN Rx header structure definition.

Definition at line 199 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_RxHeaderTypeDef::BitRateSwitch

Specifies whether the Rx frame is received with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 218 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::DataLength

Specifies the received frame length. This parameter can be a value of FDCAN Data Length Code

Definition at line 212 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 215 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FDFormat

Specifies whether the Rx frame is received in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 222 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FilterIndex

Specifies the index of matching Rx acceptance filter element. This parameter must be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
  • 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID When the frame is a Non-Filter matching frame, this parameter is unused.

Definition at line 230 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 201 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IdType

Specifies the identifier type of the received message. This parameter can be a value of FDCAN ID Type

Definition at line 206 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame

Specifies whether the accepted frame did not match any Rx filter. Acceptance of non-matching frames may be enabled via HAL_FDCAN_ConfigGlobalFilter(). This parameter takes 0 if the frame matched an Rx filter or 1 if it did not match any Rx filter

Definition at line 237 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxFrameType

Specifies the the received message frame type. This parameter can be a value of FDCAN Frame Type

Definition at line 209 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxTimestamp

Specifies the timestamp counter value captured on start of frame reception. This parameter must be a number between 0 and 0xFFFF

Definition at line 226 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_TxEventFifoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxEventFifoTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx event FIFO structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxTimestamp
uint32_t | MessageMarker
uint32_t | EventType

Detailed Description

FDCAN Tx event FIFO structure definition.

Definition at line 248 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxEventFifoTypeDef::BitRateSwitch

Specifies whether the Tx frame is transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 267 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::DataLength

Specifies the length of the transmitted frame. This parameter can be a value of FDCAN Data Length Code

Definition at line 261 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 264 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::EventType

Specifies the event type. This parameter can be a value of FDCAN Event Type

Definition at line 283 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::FDFormat

Specifies whether the Tx frame is transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 271 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 250 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::IdType

Specifies the identifier type for the transmitted message. This parameter can be a value of FDCAN ID Type

Definition at line 255 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::MessageMarker

Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 279 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxFrameType

Specifies the frame type of the transmitted message. This parameter can be a value of FDCAN Frame Type

Definition at line 258 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxTimestamp

Specifies the timestamp counter value captured on start of frame transmission. This parameter must be a number between 0 and 0xFFFF

Definition at line 275 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_HpMsgStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_HpMsgStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN High Priority Message Status structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | FilterList
uint32_t | FilterIndex
uint32_t | MessageStorage
uint32_t | MessageIndex

Detailed Description

FDCAN High Priority Message Status structure definition.

Definition at line 291 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_HpMsgStatusTypeDef::FilterIndex

Specifies the index of matching filter element. This parameter can be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
  • 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended)

Definition at line 298 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::FilterList

Specifies the filter list of the matching filter element. This parameter can be:

  • 0 : Standard Filter List
  • 1 : Extended Filter List

Definition at line 293 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageIndex

Specifies the Index of Rx FIFO element to which the message was stored. This parameter is valid only when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or FDCAN_HP_STORAGE_RXFIFO1

Definition at line 306 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageStorage

Specifies the HP Message Storage. This parameter can be a value of FDCAN High Priority Message Storage

Definition at line 303 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_ProtocolStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ProtocolStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN Protocol Status structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | LastErrorCode
uint32_t | DataLastErrorCode
uint32_t | Activity
uint32_t | ErrorPassive
uint32_t | Warning
uint32_t | BusOff
uint32_t | RxESIflag
uint32_t | RxBRSflag
uint32_t | RxFDFflag
uint32_t | ProtocolException
uint32_t | TDCvalue

Detailed Description

FDCAN Protocol Status structure definition.

Definition at line 318 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ProtocolStatusTypeDef::Activity

Specifies the FDCAN module communication state. This parameter can be a value of FDCAN communication state

Definition at line 327 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::BusOff

Specifies the FDCAN module Bus_Off status. This parameter can be:

  • 0 : The FDCAN is not in Bus_Off state
  • 1 : The FDCAN is in Bus_Off state

Definition at line 342 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::DataLastErrorCode

Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. This parameter can be a value of FDCAN protocol error code

Definition at line 323 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ErrorPassive

Specifies the FDCAN module error status. This parameter can be:

  • 0 : The FDCAN is in Error_Active state
  • 1 : The FDCAN is in Error_Passive state

Definition at line 330 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::LastErrorCode

Specifies the type of the last error that occurred on the FDCAN bus. This parameter can be a value of FDCAN protocol error code

Definition at line 320 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ProtocolException

Specifies the FDCAN module Protocol Exception status. This parameter can be:

  • 0 : No protocol exception event occurred since last read access
  • 1 : Protocol exception event occurred

Definition at line 363 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxBRSflag

Specifies BRS flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its BRS flag set
  • 1 : Last received CAN FD message had its BRS flag set

Definition at line 352 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxESIflag

Specifies ESI flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its ESI flag set
  • 1 : Last received CAN FD message had its ESI flag set

Definition at line 347 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxFDFflag

Specifies if CAN FD message (FDF flag set) has been received since last protocol status. This parameter can be:

  • 0 : No CAN FD message received
  • 1 : CAN FD message received

Definition at line 357 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::TDCvalue

Specifies the Transmitter Delay Compensation Value. This parameter can be a number between 0 and 127

Definition at line 368 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::Warning

Specifies the FDCAN module warning status. This parameter can be:

  • 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
  • 1 : at least one of error counters has reached the Error_Warning limit of 96

Definition at line 335 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_ErrorCountersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ErrorCountersTypeDef Struct Reference
FDCAN Exported Types

FDCAN Error Counters structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | TxErrorCnt
uint32_t | RxErrorCnt
uint32_t | RxErrorPassive
uint32_t | ErrorLogging

Detailed Description

FDCAN Error Counters structure definition.

Definition at line 376 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ErrorCountersTypeDef::ErrorLogging

Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW

Definition at line 391 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorCnt

Specifies the Receive Error Counter Value. This parameter can be a number between 0 and 127

Definition at line 381 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorPassive

Specifies the Receive Error Passive status. This parameter can be:

  • 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
  • 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128

Definition at line 384 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::TxErrorCnt

Specifies the Transmit Error Counter Value. This parameter can be a number between 0 and 255

Definition at line 378 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_MsgRamAddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_MsgRamAddressTypeDef Struct Reference
FDCAN Exported Types

FDCAN Message RAM blocks. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

uint32_t | StandardFilterSA
uint32_t | ExtendedFilterSA
uint32_t | RxFIFO0SA
uint32_t | RxFIFO1SA
uint32_t | TxEventFIFOSA
uint32_t | TxFIFOQSA

Detailed Description

FDCAN Message RAM blocks.

Definition at line 403 of file stm32g4xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA

Specifies the Extended Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 408 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO0SA

Specifies the Rx FIFO 0 Start Address. This parameter must be a 32-bit word address

Definition at line 411 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO1SA

Specifies the Rx FIFO 1 Start Address. This parameter must be a 32-bit word address

Definition at line 414 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::StandardFilterSA

Specifies the Standard Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 405 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA

Specifies the Tx Event FIFO Start Address. This parameter must be a 32-bit word address

Definition at line 417 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_MsgRamAddressTypeDef::TxFIFOQSA

Specifies the Tx FIFO/Queue Start Address. This parameter must be a 32-bit word address

Definition at line 420 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and FDCAN_CopyMessageToRAM().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __FDCAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__FDCAN_HandleTypeDef Struct Reference
FDCAN Exported Types

FDCAN handle structure definition. More...

#include <stm32g4xx_hal_fdcan.h>

Data Fields

FDCAN_GlobalTypeDef * | Instance
FDCAN_InitTypeDef Init
FDCAN_MsgRamAddressTypeDef msgRam
uint32_t | LatestTxFifoQRequest
__IO HAL_FDCAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
void(* | TxEventFifoCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
void(* | RxFifo0Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
void(* | RxFifo1Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
void(* | TxFifoEmptyCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TxBufferCompleteCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | TxBufferAbortCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | HighPriorityMessageCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimestampWraparoundCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimeoutOccurredCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorStatusCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
void(* | MspInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | MspDeInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)

Detailed Description

FDCAN handle structure definition.

Definition at line 429 of file stm32g4xx_hal_fdcan.h.

Field Documentation

void(* __FDCAN_HandleTypeDef::ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Error callback

Definition at line 459 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

__IO uint32_t __FDCAN_HandleTypeDef::ErrorCode

FDCAN Error code

Definition at line 447 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetError(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

FDCAN Error status callback

Definition at line 460 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterErrorStatusCallback(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void(* __FDCAN_HandleTypeDef::HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN High priority message callback

Definition at line 456 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

FDCAN_InitTypeDef __FDCAN_HandleTypeDef::Init

FDCAN required parameters

Definition at line 436 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FDCAN_GlobalTypeDef* __FDCAN_HandleTypeDef::Instance

Register base address

Definition at line 434 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetErrorCounters(), HAL_FDCAN_GetHighPriorityMessageStatus(), HAL_FDCAN_GetProtocolStatus(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTimeoutCounter(), HAL_FDCAN_GetTimestampCounter(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_GetTxFifoFreeLevel(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_IsRestrictedOperationMode(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), and HAL_FDCAN_Stop().

uint32_t __FDCAN_HandleTypeDef::LatestTxFifoQRequest

FDCAN Tx buffer index of latest Tx FIFO/Queue request

Definition at line 440 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetLatestTxFifoQRequestBuffer(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

HAL_LockTypeDef __FDCAN_HandleTypeDef::Lock

FDCAN locking object

Definition at line 445 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FDCAN_MsgRamAddressTypeDef __FDCAN_HandleTypeDef::msgRam

FDCAN Message RAM blocks

Definition at line 438 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

void(* __FDCAN_HandleTypeDef::MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp DeInit callback

Definition at line 463 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp Init callback

Definition at line 462 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

FDCAN Rx Fifo 0 callback

Definition at line 451 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo0Callback(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void(* __FDCAN_HandleTypeDef::RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

FDCAN Rx Fifo 1 callback

Definition at line 452 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo1Callback(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

__IO HAL_FDCAN_StateTypeDef __FDCAN_HandleTypeDef::State

FDCAN communication state

Definition at line 443 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetState(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timeout occurred callback

Definition at line 458 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timestamp wraparound callback

Definition at line 457 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer abort callback

Definition at line 455 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferAbortCallback(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void(* __FDCAN_HandleTypeDef::TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer complete callback

Definition at line 454 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void(* __FDCAN_HandleTypeDef::TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

FDCAN Tx Event Fifo callback

Definition at line 450 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxEventFifoCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Tx Fifo Empty callback

Definition at line 453 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fdcan.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL FDCAN Error Code

Defines
HAL FDCAN Error Code
FDCAN Exported Constants

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Define Documentation

#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)

Put element in full FIFO

Definition at line 520 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)

Get element from empty FIFO

Definition at line 521 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Invalid Callback error

Definition at line 529 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO

Overflow of CAN Error Logging Counter

Definition at line 522 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 511 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)

Peripheral not initialized

Definition at line 513 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_ExitRestrictedOperationMode().

#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)

Peripheral not ready

Definition at line 514 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)

Peripheral not started

Definition at line 515 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Stop().

#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)

Mode not supported

Definition at line 516 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter(), and HAL_FDCAN_ResetTimestampCounter().

#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)

Parameter error

Definition at line 517 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)

Pending operation

Definition at line 518 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA

Protocol Error in Arbitration Phase (Nominal Bit Time is used)

Definition at line 524 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED

Protocol Error in Data Phase (Data Bit Time is used)

Definition at line 525 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)

Message RAM Access Failure

Definition at line 519 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI

Message RAM Watchdog event occurred

Definition at line 523 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA

Access to Reserved Address

Definition at line 526 of file stm32g4xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 512 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Frame Format

Defines
FDCAN Frame Format
FDCAN Exported Constants

Defines

#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

Define Documentation

#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)

Classic mode

Definition at line 538 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

FD mode with BitRate Switching

Definition at line 540 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)

FD mode without BitRate Switching

Definition at line 539 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Operating Mode

Defines
FDCAN Operating Mode
FDCAN Exported Constants

Defines

#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)

Bus Monitoring mode

Definition at line 550 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

External LoopBack mode

Definition at line 552 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)

Internal LoopBack mode

Definition at line 551 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 548 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)

Restricted Operation mode

Definition at line 549 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Clock Divider

Defines
FDCAN Clock Divider
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)

Define Documentation

#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)

Divide kernel clock by 1

Definition at line 560 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)

Divide kernel clock by 10

Definition at line 565 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)

Divide kernel clock by 12

Definition at line 566 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)

Divide kernel clock by 14

Definition at line 567 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)

Divide kernel clock by 16

Definition at line 568 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)

Divide kernel clock by 18

Definition at line 569 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)

Divide kernel clock by 2

Definition at line 561 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)

Divide kernel clock by 20

Definition at line 570 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)

Divide kernel clock by 22

Definition at line 571 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)

Divide kernel clock by 24

Definition at line 572 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)

Divide kernel clock by 26

Definition at line 573 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)

Divide kernel clock by 28

Definition at line 574 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)

Divide kernel clock by 30

Definition at line 575 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)

Divide kernel clock by 4

Definition at line 562 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)

Divide kernel clock by 6

Definition at line 563 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)

Divide kernel clock by 8

Definition at line 564 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Tx FIFO/Queue Mode

Defines
FDCAN Tx FIFO/Queue Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Define Documentation

#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)

FIFO mode

Definition at line 583 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Queue mode

Definition at line 584 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN ID Type

Defines
FDCAN ID Type
FDCAN Exported Constants

Defines

#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Define Documentation

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Extended ID element

Definition at line 593 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM().

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U)

Standard ID element

Definition at line 592 of file stm32g4xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Frame Type

Defines
FDCAN Frame Type
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Define Documentation

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U)

Data frame

Definition at line 601 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Remote frame

Definition at line 602 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Data Length Code

Defines
FDCAN Data Length Code
FDCAN Exported Constants

Defines

#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU)

Define Documentation

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)

0 bytes data field

Definition at line 610 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U)

1 bytes data field

Definition at line 611 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U)

12 bytes data field

Definition at line 619 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU)

16 bytes data field

Definition at line 620 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U)

2 bytes data field

Definition at line 612 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU)

20 bytes data field

Definition at line 621 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU)

24 bytes data field

Definition at line 622 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U)

3 bytes data field

Definition at line 613 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU)

32 bytes data field

Definition at line 623 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U)

4 bytes data field

Definition at line 614 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU)

48 bytes data field

Definition at line 624 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U)

5 bytes data field

Definition at line 615 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U)

6 bytes data field

Definition at line 616 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU)

64 bytes data field

Definition at line 625 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U)

7 bytes data field

Definition at line 617 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U)

8 bytes data field

Definition at line 618 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Error State Indicator

Defines
FDCAN Error State Indicator
FDCAN Exported Constants

Defines

#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)

Transmitting node is error active

Definition at line 633 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Transmitting node is error passive

Definition at line 634 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Bit Rate Switching

Defines
FDCAN Bit Rate Switching
FDCAN Exported Constants

Defines

#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)

Define Documentation

#define FDCAN_BRS_OFF ((uint32_t)0x00000000U)

FDCAN frames transmitted/received without bit rate switching

Definition at line 642 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_BRS_ON ((uint32_t)0x00100000U)

FDCAN frames transmitted/received with bit rate switching

Definition at line 643 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN format

Defines
FDCAN format
FDCAN Exported Constants

Defines

#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)

Define Documentation

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)

Frame transmitted/received in Classic CAN format

Definition at line 651 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FD_CAN ((uint32_t)0x00200000U)

Frame transmitted/received in FDCAN format

Definition at line 652 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Event FIFO control

Defines
FDCAN Event FIFO control
FDCAN Exported Constants

Defines

#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)

Do not store Tx events

Definition at line 660 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Store Tx events

Definition at line 661 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Filter Type

Defines
FDCAN Filter Type
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)

Dual ID filter for FilterID1 or FilterID2

Definition at line 670 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U)

Classic filter: FilterID1 = filter, FilterID2 = mask

Definition at line 671 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)

Range filter from FilterID1 to FilterID2

Definition at line 669 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Range filter from FilterID1 to FilterID2, EIDM mask not applied

Definition at line 672 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Filter Configuration

Defines
FDCAN Filter Configuration
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)

Disable filter element

Definition at line 680 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_HP ((uint32_t)0x00000004U)

Set high priority if filter matches

Definition at line 684 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)

Reject ID if filter matches

Definition at line 683 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)

Store in Rx FIFO 0 if filter matches

Definition at line 681 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)

Set high priority and store in FIFO 0 if filter matches

Definition at line 685 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)

Store in Rx FIFO 1 if filter matches

Definition at line 682 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Set high priority and store in FIFO 1 if filter matches

Definition at line 686 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Tx Location

Defines
FDCAN Tx Location
FDCAN Exported Constants

Defines

#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)

Add message to Tx Buffer 0

Definition at line 694 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)

Add message to Tx Buffer 1

Definition at line 695 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Add message to Tx Buffer 2

Definition at line 696 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Rx Location

Defines
FDCAN Rx Location
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Define Documentation

#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)

Get received message from Rx FIFO 0

Definition at line 704 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Get received message from Rx FIFO 1

Definition at line 705 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Event Type

Defines
FDCAN Event Type
FDCAN Exported Constants

Defines

#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_TX_EVENT ((uint32_t)0x00400000U)

Tx event

Definition at line 713 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Transmission in spite of cancellation

Definition at line 714 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN High Priority Message Storage

Defines
FDCAN High Priority Message Storage
FDCAN Exported Constants

Defines

#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)

FIFO message lost

Definition at line 723 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)

No FIFO selected

Definition at line 722 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)

Message stored in FIFO 0

Definition at line 724 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Message stored in FIFO 1

Definition at line 725 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN protocol error code

Defines
FDCAN protocol error code
FDCAN Exported Constants

Defines

#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)

Acknowledge error

Definition at line 736 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)

Bit 0 (dominant) error

Definition at line 738 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)

Bit 1 (recessive) error

Definition at line 737 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)

CRC check sum error

Definition at line 739 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)

Form error

Definition at line 735 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

No change since last read

Definition at line 740 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)

No error occurred

Definition at line 733 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)

Stuff error

Definition at line 734 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN communication state

Defines
FDCAN communication state
FDCAN Exported Constants

Defines

#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Define Documentation

#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)

Node is neither receiver nor transmitter

Definition at line 749 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)

Node is operating as receiver

Definition at line 750 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)

Node is synchronizing on CAN communication

Definition at line 748 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Node is operating as transmitter

Definition at line 751 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN FIFO operation mode

Defines
FDCAN FIFO operation mode
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)

Rx FIFO blocking mode

Definition at line 759 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)

Rx FIFO overwrite mode

Definition at line 760 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN non-matching frames

Defines
FDCAN non-matching frames
FDCAN Exported Constants

Defines

#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)

Accept in Rx FIFO 0

Definition at line 768 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)

Accept in Rx FIFO 1

Definition at line 769 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_REJECT ((uint32_t)0x00000002U)

Reject

Definition at line 770 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN reject remote frames

Defines
FDCAN reject remote frames
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)

Filter remote frames

Definition at line 778 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Reject all remote frames

Definition at line 779 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN interrupt line

Defines
FDCAN interrupt line
FDCAN Exported Constants

Defines

#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)

Interrupt Line 0

Definition at line 787 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_DeInit().

#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Interrupt Line 1

Definition at line 788 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_DeInit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN timestamp

Defines
FDCAN timestamp
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

External timestamp counter value used

Definition at line 797 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimestampCounter().

#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)

Timestamp counter value incremented according to TCP

Definition at line 796 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN timestamp prescaler

Defines
FDCAN timestamp prescaler
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)

Timestamp counter time unit in equal to CAN bit time

Definition at line 805 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 10

Definition at line 814 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 11

Definition at line 815 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 12

Definition at line 816 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 13

Definition at line 817 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 14

Definition at line 818 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 15

Definition at line 819 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 16

Definition at line 820 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 2

Definition at line 806 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 3

Definition at line 807 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 4

Definition at line 808 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 5

Definition at line 809 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 6

Definition at line 810 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 7

Definition at line 811 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 8

Definition at line 812 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 9

Definition at line 813 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN timeout operation

Defines
FDCAN timeout operation
FDCAN Exported Constants

Defines

#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)

Timeout continuous operation

Definition at line 828 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter().

#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)

Timeout controlled by Rx FIFO 0

Definition at line 830 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Timeout controlled by Rx FIFO 1

Definition at line 831 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)

Timeout controlled by Tx Event FIFO

Definition at line 829 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt masks

Defines
Interrupt masks
FDCAN Exported Constants

Defines

#define | FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)
#define | FDCAN_ILS_MASK ((uint32_t)0x0000007FU)

Define Documentation

#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU)

FDCAN interrupts group mask

Definition at line 840 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)

FDCAN interrupts mask

Definition at line 839 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Flags

Defines
FDCAN Flags
FDCAN Exported Constants

Defines

#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Define Documentation

#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA

Protocol error in arbitration phase detected

Definition at line 867 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO

Bus_Off status changed

Definition at line 865 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED

Protocol error in data phase detected

Definition at line 868 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO

Overflow of FDCAN Error Logging Counter occurred

Definition at line 862 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP

Error_Passive status changed

Definition at line 863 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW

Error_Warning status changed

Definition at line 864 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF

Message RAM access failure occurred

Definition at line 861 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI

Message RAM Watchdog event due to missing READY

Definition at line 866 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA

Access to reserved address occurred

Definition at line 869 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F

Rx FIFO 0 full

Definition at line 856 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L

Rx FIFO 0 message lost

Definition at line 855 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N

New message written to Rx FIFO 0

Definition at line 857 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F

Rx FIFO 1 full

Definition at line 859 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L

Rx FIFO 1 message lost

Definition at line 858 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N

New message written to Rx FIFO 1

Definition at line 860 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM

High priority message received

Definition at line 851 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Timeout reached

Definition at line 871 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW

Timestamp counter wrapped around

Definition at line 870 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF

Transmission Cancellation Finished

Definition at line 849 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC

Transmission Completed

Definition at line 848 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL

Tx Event FIFO element lost

Definition at line 852 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF

Tx Event FIFO full

Definition at line 853 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN

Tx Handler wrote Tx Event FIFO element

Definition at line 854 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE

Tx FIFO Empty

Definition at line 850 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Tx Interrupts

Defines
FDCAN Tx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Define Documentation

#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE

Transmission Cancellation Finished

Definition at line 884 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE

Transmission Completed

Definition at line 883 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Tx FIFO Empty

Definition at line 885 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Rx Interrupts

Defines
FDCAN Rx Interrupts
FDCAN Interrupts

Defines

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

Define Documentation

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

High priority message received

Definition at line 893 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Counter Interrupts

Defines
FDCAN Counter Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Define Documentation

#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Timeout reached

Definition at line 902 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE

Timestamp counter wrapped around

Definition at line 901 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Tx Event FIFO Interrupts

Defines
FDCAN Tx Event FIFO Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Define Documentation

#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE

Tx Event FIFO element lost

Definition at line 910 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE

Tx Event FIFO full

Definition at line 911 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Tx Handler wrote Tx Event FIFO element

Definition at line 912 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Rx FIFO 0 Interrupts

Defines
FDCAN Rx FIFO 0 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

Define Documentation

#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE

Rx FIFO 0 full

Definition at line 921 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE

Rx FIFO 0 message lost

Definition at line 920 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

New message written to Rx FIFO 0

Definition at line 922 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Rx FIFO 1 Interrupts

Defines
FDCAN Rx FIFO 1 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

Define Documentation

#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE

Rx FIFO 1 full

Definition at line 931 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE

Rx FIFO 1 message lost

Definition at line 930 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

New message written to Rx FIFO 1

Definition at line 932 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Error Interrupts

Defines
FDCAN Error Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Define Documentation

#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE

Protocol error in arbitration phase detected

Definition at line 943 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE

Protocol error in data phase detected

Definition at line 944 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE

Overflow of FDCAN Error Logging Counter occurred

Definition at line 941 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE

Message RAM access failure occurred

Definition at line 940 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE

Message RAM Watchdog event due to missing READY

Definition at line 942 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Access to reserved address occurred

Definition at line 945 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Error Status Interrupts

Defines
FDCAN Error Status Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Define Documentation

#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Bus_Off status changed

Definition at line 955 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE

Error_Passive status changed

Definition at line 953 of file stm32g4xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE

Error_Warning status changed

Definition at line 954 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Interrupts List

Defines
FDCAN Interrupts List
FDCAN Exported Constants

Defines

#define | FDCAN_IT_LIST_RX_FIFO0
#define | FDCAN_IT_LIST_RX_FIFO1
#define | FDCAN_IT_LIST_SMSG
#define | FDCAN_IT_LIST_TX_FIFO_ERROR
#define | FDCAN_IT_LIST_MISC
#define | FDCAN_IT_LIST_BIT_LINE_ERROR
#define | FDCAN_IT_LIST_PROTOCOL_ERROR

Define Documentation

#define FDCAN_IT_LIST_BIT_LINE_ERROR
Value:
(FDCAN_IT_ERROR_PASSIVE | \
                                        FDCAN_IT_ERROR_LOGGING_OVERFLOW)

Bit and Line Error Interrupts List

Definition at line 983 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_MISC
Value:
(FDCAN_IT_TIMEOUT_OCCURRED | \
                                        FDCAN_IT_RAM_ACCESS_FAILURE | \
                                        FDCAN_IT_TIMESTAMP_WRAPAROUND)

Misc. Interrupts List

Definition at line 980 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_PROTOCOL_ERROR
Value:
(FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
                                        FDCAN_IT_DATA_PROTOCOL_ERROR | \
                                        FDCAN_IT_ARB_PROTOCOL_ERROR | \
                                        FDCAN_IT_RAM_WATCHDOG | \
                                        FDCAN_IT_BUS_OFF | \
                                        FDCAN_IT_ERROR_WARNING)

Protocol Error Interrupts List

Definition at line 985 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_RX_FIFO0
Value:
(FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
                                        FDCAN_IT_RX_FIFO0_FULL         | \
                                        FDCAN_IT_RX_FIFO0_NEW_MESSAGE)

RX FIFO 0 Interrupts List

Definition at line 967 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_RX_FIFO1
Value:
(FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
                                        FDCAN_IT_RX_FIFO1_FULL         | \
                                        FDCAN_IT_RX_FIFO1_NEW_MESSAGE)

RX FIFO 1 Interrupts List

Definition at line 970 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_SMSG
Value:
(FDCAN_IT_TX_ABORT_COMPLETE | \
                                        FDCAN_IT_TX_COMPLETE | \
                                        FDCAN_IT_RX_HIGH_PRIORITY_MSG)

Status Message Interrupts List

Definition at line 973 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_TX_FIFO_ERROR
Value:
(FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
                                        FDCAN_IT_TX_EVT_FIFO_FULL | \
                                        FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
                                        FDCAN_IT_TX_FIFO_EMPTY)

TX FIFO Error Interrupts List

Definition at line 976 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Interrupts Group

Defines
FDCAN Interrupts Group
FDCAN Exported Constants

Defines

#define | FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0
#define | FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1
#define | FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG
#define | FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR
#define | FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC
#define | FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR
#define | FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR

Define Documentation

#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR

Bit and Line Error Interrupts Group: EPL: Error Passive ELOL: Error Logging Overflow

Definition at line 1019 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC

Misc. Interrupts Group: TOOL: Timeout Occurred MRAFL: Message RAM Access Failure TSWL: Timestamp Wraparound

Definition at line 1015 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR

Protocol Error Group: ARAL: Access to Reserved Address Line PEDL: Protocol Error in Data Phase Line PEAL: Protocol Error in Arbitration Phase Line WDIL: Watchdog Interrupt Line BOL: Bus_Off Status EWL: Warning Status

Definition at line 1022 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0

RX FIFO 0 Interrupts Group: RF0LL: Rx FIFO 0 Message Lost RF0FL: Rx FIFO 0 is Full RF0NL: Rx FIFO 0 Has New Message

Definition at line 998 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1

RX FIFO 1 Interrupts Group: RF1LL: Rx FIFO 1 Message Lost RF1FL: Rx FIFO 1 is Full RF1NL: Rx FIFO 1 Has New Message

Definition at line 1002 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG

Status Message Interrupts Group: TCFL: Transmission Cancellation Finished TCL: Transmission Completed HPML: High Priority Message

Definition at line 1006 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR

TX FIFO Error Interrupts Group: TEFLL: Tx Event FIFO Element Lost TEFFL: Tx Event FIFO Full TEFNL: Tx Event FIFO New Entry TFEL: Tx FIFO Empty Interrupt Line

Definition at line 1010 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Exported Macros

Defines
FDCAN Exported Macros
FDCAN

Defines

#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR) = (__FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
Check if the specified FDCAN interrupt source is enabled or disabled.

Define Documentation

#define __HAL_FDCAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IR) = (__FLAG__)

Clear the specified FDCAN flags.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ specifies the flags to clear. This parameter can be any combination of
  • FDCAN_flags
Return values:
None

Definition at line 1111 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)

Clear the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the interrupts to clear. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1092 of file stm32g4xx_hal_fdcan.h.

#define __HAL_FDCAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)

Disable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1073 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeactivateNotification().

#define __HAL_FDCAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (__HANDLE__)->Instance->IE |= (__INTERRUPT__)

Enable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1063 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification().

#define __HAL_FDCAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IR & (__FLAG__))

Check whether the specified FDCAN flag is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ FDCAN flag. This parameter can be one of
  • FDCAN_flags
Return values:
FlagStatus

Definition at line 1102 of file stm32g4xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IR & (__INTERRUPT__))

Check whether the specified FDCAN interrupt is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be one of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1083 of file stm32g4xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IE & (__INTERRUPT__))

Check if the specified FDCAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the FDCAN interrupt source to check. This parameter can be a value of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1120 of file stm32g4xx_hal_fdcan.h.

#define __HAL_FDCAN_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                 \
                                                       (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
                                                       (__HANDLE__)->MspInitCallback = NULL;           \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                     } while(0)

Reset FDCAN handle state.

Parameters:
__HANDLE__ FDCAN handle.
Return values:
None

Definition at line 1047 of file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Private Variables

Variables
FDCAN Private Variables
FDCAN

Variables

static const uint8_t DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Variable Documentation

const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64} [static]

Definition at line 242 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_GetRxMessage().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Private Constants

Defines
FDCAN Private Constants
FDCAN

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define | SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define | SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define | SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define | SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define | SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define | SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define | SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define | SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define | SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define | SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define | SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define | SRAMCAN_FLSSA
#define | SRAMCAN_FLESA
#define | SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define | SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define | SRAMCAN_TEFSA
#define | SRAMCAN_TFQSA
#define | SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Define Documentation

#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */

Definition at line 208 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */

Definition at line 203 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */

Definition at line 202 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */

Definition at line 205 of file stm32g4xx_hal_fdcan.c.

#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */

Definition at line 200 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Definition at line 209 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */

Definition at line 197 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */

Definition at line 204 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */

Definition at line 207 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */

Definition at line 206 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */

Definition at line 198 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */

Definition at line 196 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */

Definition at line 201 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */

Definition at line 199 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)

Definition at line 193 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)

Definition at line 194 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)

Definition at line 191 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)

Definition at line 192 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TIMEOUT_VALUE 10U

Definition at line 188 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)

Definition at line 190 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */

Definition at line 212 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */

Definition at line 219 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_ConfigFilter().

#define SRAMCAN_FLESA
Value:
((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
                                                                                Address                  */

Definition at line 226 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */

Definition at line 211 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */

Definition at line 218 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_ConfigFilter().

#define SRAMCAN_FLSSA
Value:
((uint32_t)0)                                                      /* Filter List Standard Start
                                                                                Address                  */

Definition at line 225 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */

Definition at line 213 of file stm32g4xx_hal_fdcan.c.

#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */

Definition at line 220 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */

Definition at line 227 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */

Definition at line 214 of file stm32g4xx_hal_fdcan.c.

#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */

Definition at line 221 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */

Definition at line 228 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Definition at line 231 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */

Definition at line 215 of file stm32g4xx_hal_fdcan.c.

#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */

Definition at line 222 of file stm32g4xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define SRAMCAN_TEFSA
Value:
((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
                                                                                Address */

Definition at line 229 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */

Definition at line 216 of file stm32g4xx_hal_fdcan.c.

#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */

Definition at line 223 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM().

#define SRAMCAN_TFQSA
Value:
((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
                                                                                Address                  */

Definition at line 230 of file stm32g4xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Private Macros

Defines
FDCAN Private Macros
FDCAN

Defines

#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
#define | IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_TX_LOCATION_LIST(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
#define | IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Define Documentation

#define FDCAN_CHECK_FLAG | ( | __IR__,
 |  | __FLAG__
 | ) | ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 1421 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_CHECK_IT_SOURCE | ( | __IE__,
 |  | __IT__
 | ) | ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 1419 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define IS_FDCAN_BRS ( BRS )
Value:
(((BRS) == FDCAN_BRS_OFF) || \
                           ((BRS) == FDCAN_BRS_ON ))

Definition at line 1381 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_CKDIV ( CKDIV )
Value:
(((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV30))

Definition at line 1309 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))

Definition at line 1329 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 16U))

Definition at line 1330 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))

Definition at line 1331 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))

Definition at line 1332 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DLC ( DLC )
Value:
(((DLC) == FDCAN_DLC_BYTES_0 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_12) || \
                           ((DLC) == FDCAN_DLC_BYTES_16) || \
                           ((DLC) == FDCAN_DLC_BYTES_20) || \
                           ((DLC) == FDCAN_DLC_BYTES_24) || \
                           ((DLC) == FDCAN_DLC_BYTES_32) || \
                           ((DLC) == FDCAN_DLC_BYTES_48) || \
                           ((DLC) == FDCAN_DLC_BYTES_64))

Definition at line 1363 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EFC ( EFC )
Value:
(((EFC) == FDCAN_NO_TX_EVENTS   ) || \
                           ((EFC) == FDCAN_STORE_TX_EVENTS))

Definition at line 1385 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ESI ( ESI )
Value:
(((ESI) == FDCAN_ESI_ACTIVE ) || \
                           ((ESI) == FDCAN_ESI_PASSIVE))

Definition at line 1379 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EXT_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE        ) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))

Definition at line 1357 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FDF ( FDF )
Value:
(((FDF) == FDCAN_CLASSIC_CAN) || \
                           ((FDF) == FDCAN_FD_CAN     ))

Definition at line 1383 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_FILTER_CFG ( CONFIG )
Value:
(((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))

Definition at line 1339 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FRAME_FORMAT ( FORMAT )
Value:
(((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))

Definition at line 1301 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_FRAME_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_DATA_FRAME  ) || \
                                   ((TYPE) == FDCAN_REMOTE_FRAME))

Definition at line 1361 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ID_TYPE ( ID_TYPE )
Value:
(((ID_TYPE) == FDCAN_STANDARD_ID) || \
                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))

Definition at line 1337 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), and HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_IT ( IT ) (((IT) & ~(FDCAN_IR_MASK)) == 0U)

Definition at line 1387 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define IS_FDCAN_IT_GROUP ( IT_GROUP ) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)

Definition at line 1388 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines().

#define IS_FDCAN_IT_LINE ( IT_LINE )
Value:
(((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))

Definition at line 1394 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines().

#define IS_FDCAN_MAX_VALUE | ( | VALUE,
 |  | _MAX_
 | ) | ((VALUE) <= (_MAX_))

Definition at line 1333 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), and HAL_FDCAN_Init().

#define IS_FDCAN_MIN_VALUE | ( | VALUE,
 |  | _MIN_
 | ) | ((VALUE) >= (_MIN_))

Definition at line 1334 of file stm32g4xx_hal_fdcan.h.

#define IS_FDCAN_MODE ( MODE )
Value:
(((MODE) == FDCAN_MODE_NORMAL              ) || \
                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))

Definition at line 1304 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))

Definition at line 1325 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 128U))

Definition at line 1326 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))

Definition at line 1327 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))

Definition at line 1328 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NON_MATCHING ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
                                            ((DESTINATION) == FDCAN_REJECT            ))

Definition at line 1389 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_REJECT_REMOTE ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_FILTER_REMOTE) || \
                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))

Definition at line 1392 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_RX_FIFO ( FIFO )
Value:
(((FIFO) == FDCAN_RX_FIFO0) || \
                                ((FIFO) == FDCAN_RX_FIFO1))

Definition at line 1350 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define IS_FDCAN_RX_FIFO_MODE ( MODE )
Value:
(((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))

Definition at line 1352 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite().

#define IS_FDCAN_STD_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK ))

Definition at line 1354 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_TIMEOUT ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))

Definition at line 1414 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimeoutCounter().

#define IS_FDCAN_TIMESTAMP ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))

Definition at line 1396 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnableTimestampCounter().

#define IS_FDCAN_TIMESTAMP_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))

Definition at line 1398 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimestampCounter().

#define IS_FDCAN_TX_FIFO_QUEUE_MODE ( MODE )
Value:
(((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))

Definition at line 1335 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_TX_LOCATION ( LOCATION )
Value:
(((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER2 ))

Definition at line 1346 of file stm32g4xx_hal_fdcan.h.

#define IS_FDCAN_TX_LOCATION_LIST ( LOCATION )
Value:
(((LOCATION) >= FDCAN_TX_BUFFER0) && \
                                             ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))

Definition at line 1348 of file stm32g4xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_IsTxBufferMessagePending().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN_Private_Functions_Prototypes

FDCAN_Private_Functions_Prototypes
FDCAN
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | FLASH_NB_DOUBLE_WORDS_IN_ROW 32
#define | FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#define | FLASH_SIZE
#define | FLASH_BANK_SIZE (FLASH_SIZE)
#define | FLASH_PAGE_NB
#define | FLASH_PAGE_SIZE 0x800U /* 2 KB */
#define | FLASH_TIMEOUT_VALUE 1000U /* 1 s */

Define Documentation

#define FLASH_BANK_SIZE (FLASH_SIZE)

Definition at line 882 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), and FLASH_OB_PCROPConfig().

#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32

Definition at line 106 of file stm32g4xx_hal_flash.c.

Referenced by FLASH_Program_Fast().

#define FLASH_PAGE_NB
Value:
((FLASH_SIZE == 0x00080000U) ? 256U : \
                                        ((FLASH_SIZE == 0x00040000U) ? 128U : 64U))

Definition at line 883 of file stm32g4xx_hal_flash.h.

#define FLASH_PAGE_SIZE 0x800U /* 2 KB */

Definition at line 887 of file stm32g4xx_hal_flash.h.

#define FLASH_SIZE
Value:
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
                                        (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))

Definition at line 880 of file stm32g4xx_hal_flash.h.

#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE

Definition at line 870 of file stm32g4xx_hal_flash.h.

#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */

Definition at line 889 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_BootLockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash
Initial value:
 {.Lock = HAL_UNLOCKED,
                                .ErrorCode = HAL_FLASH_ERROR_NONE,
                                .ProcedureOnGoing = FLASH_PROC_NONE,
                                .Address = 0U,
                                .Bank = FLASH_BANK_1,
                                .Page = 0U,
                                .NbPagesToErase = 0U,
                                .CacheToReactivate = FLASH_CACHE_DISABLED}

Variable used for Program/Erase sectors under interruption.

Definition at line 120 of file stm32g4xx_hal_flash.c.

Referenced by FLASH_FlushCaches(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program double-word (64-bit) at a specified address.

Parameters:
Address | specifies the address to be programmed.
Data | specifies the data to be programmed.
Return values:
None

Definition at line 725 of file stm32g4xx_hal_flash.c.

References assert_param, and IS_FLASH_PROGRAM_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_Fast | ( | uint32_t | Address,
 |  | uint32_t | DataAddress
 | ) |  | [static]

Fast program a row double-word (64-bit) at a specified address.

Parameters:
Address | specifies the address to be programmed.
DataAddress | specifies the address where the data are stored.
Return values:
None

Definition at line 750 of file stm32g4xx_hal_flash.c.

References assert_param, FLASH_NB_DOUBLE_WORDS_IN_ROW, and IS_FLASH_MAIN_MEM_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout maximum flash operation timeout.
Return values:
HAL_Status

Definition at line 678 of file stm32g4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_SR_ERRORS, and HAL_GetTick().

Referenced by FLASH_OB_BootLockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure:
  • Mass Erase: Bank number which has been requested to erase
  • Page Erase: Page which has been erased (if 0xFFFFFFFF, it means that all the selected pages have been erased)
  • Program: Address which was selected for data program
Return values:
None

Definition at line 467 of file stm32g4xx_hal_flash.c.

References UNUSED.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

Handle FLASH interrupt request.

Return values:
None

Definition at line 327 of file stm32g4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Bank, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_EOP, FLASH_FLAG_SR_ERRORS, FLASH_FlushCaches(), FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_PageErase(), FLASH_PROC_MASS_ERASE, FLASH_PROC_NONE, FLASH_PROC_PAGE_ERASE, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST, HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbPagesToErase, FLASH_ProcessTypeDef::Page, and FLASH_ProcessTypeDef::ProcedureOnGoing.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure:
  • Mass Erase: Bank number which has been requested to erase
  • Page Erase: Page number which returned an error
  • Program: Address which was selected for data program
Return values:
None

Definition at line 485 of file stm32g4xx_hal_flash.c.

References UNUSED.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type.
Address | specifies the address to be programmed.
Data | specifies the data to be programmed. This parameter is the data for the double word program and the address where are stored the data for the row fast program.
Return values:
HAL_Status

Definition at line 173 of file stm32g4xx_hal_flash.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, assert_param, FLASH_ProcessTypeDef::CacheToReactivate, FLASH_ProcessTypeDef::ErrorCode, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_DISABLED, FLASH_FlushCaches(), FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, FLASH_TYPEPROGRAM_FAST_AND_LAST, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address with interrupt enabled.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type.
Address | specifies the address to be programmed.
Data | specifies the data to be programmed. This parameter is the data for the double word program and the address where are stored the data for the row fast program.
Return values:
HAL_Status

Definition at line 255 of file stm32g4xx_hal_flash.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::CacheToReactivate, FLASH_ProcessTypeDef::ErrorCode, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_DISABLED, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, FLASH_TYPEPROGRAM_FAST_AND_LAST, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Lock the FLASH control register access.

Return values:
HAL_Status

Definition at line 542 of file stm32g4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL_Status

Definition at line 606 of file stm32g4xx_hal_flash.c.

References FLASH_TIMEOUT_VALUE, and FLASH_WaitForLastOperation().

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Bytes Registers access.

Return values:
HAL_Status

Definition at line 586 of file stm32g4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Bytes Registers access.

Return values:
HAL_Status

Definition at line 562 of file stm32g4xx_hal_flash.c.

References FLASH_OPTKEY1, and FLASH_OPTKEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL_Status

Definition at line 518 of file stm32g4xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode. The returned value can be:
  • HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
  • HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
  • HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
  • HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
  • HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
  • HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
  • HAL_FLASH_ERROR_NONE: No error set
  • HAL_FLASH_ERROR_OP: FLASH Operation error
  • HAL_FLASH_ERROR_PROG: FLASH Programming error
  • HAL_FLASH_ERROR_WRP: FLASH Write protection error
  • HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
  • HAL_FLASH_ERROR_SIZ: FLASH Size error
  • HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
  • HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
  • HAL_FLASH_ERROR_FAST: FLASH Fast programming error
  • HAL_FLASH_ERROR_RD: FLASH PCROP read error
  • HAL_FLASH_ERROR_OPTV: FLASH Option validity error

Definition at line 654 of file stm32g4xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM,
FLASH_PROC_PROGRAM_LAST
}
FLASH Procedure structure definition. More...
enum | FLASH_CacheTypeDef { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED }
FLASH Cache structure definition. More...

Enumeration Type Documentation

enum FLASH_CacheTypeDef

FLASH Cache structure definition.

Enumerator:
FLASH_CACHE_DISABLED
FLASH_CACHE_ICACHE_ENABLED
FLASH_CACHE_DCACHE_ENABLED
FLASH_CACHE_ICACHE_DCACHE_ENABLED

Definition at line 123 of file stm32g4xx_hal_flash.h.

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_PAGE_ERASE
FLASH_PROC_MASS_ERASE
FLASH_PROC_PROGRAM
FLASH_PROC_PROGRAM_LAST

Definition at line 111 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32g4xx_hal_flash.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Page
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 45 of file stm32g4xx_hal_flash.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select bank to erase. This parameter must be a value of FLASH Banks (FLASH_BANK_BOTH should be used only for mass erase)

Definition at line 49 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbPages

Number of pages to be erased. This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)

Definition at line 55 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Page

Initial Flash page to erase when page erase is disabled. This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 127 for 512KB dual bank)

Definition at line 52 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or page erase. This parameter can be a value of FLASH Erase Type

Definition at line 47 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_flash.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32g4xx_hal_flash.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPArea
uint32_t | WRPStartOffset
uint32_t | WRPEndOffset
uint32_t | RDPLevel
uint32_t | USERType
uint32_t | USERConfig
uint32_t | PCROPConfig
uint32_t | PCROPStartAddr
uint32_t | PCROPEndAddr
uint32_t | BootEntryPoint
uint32_t | SecBank
uint32_t | SecSize

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 62 of file stm32g4xx_hal_flash.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::BootEntryPoint

Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK). This parameter can be a value of FLASH Boot Lock

Definition at line 94 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a combination of the values of FLASH Option Bytes Type

Definition at line 64 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of FLASH Banks (except FLASH_BANK_BOTH) and FLASH Option Bytes PCROP On RDP Level Type

Definition at line 86 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank

Definition at line 92 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address

Definition at line 89 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level.. (used for OPTIONBYTE_RDP). This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 73 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecBank

Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC). Only one securable memory area could be programmed at the same time. This parameter can be one of the following values: FLASH_BANK_1: Securable memory area to be programmed in bank 1 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)

Note:
(*) availability depends on devices

Definition at line 96 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecSize

Size of securable memory area to be programmed (used for OPTIONBYTE_SEC), in number of pages. Securable memory area is starting from first page of the bank. Only one securable memory could be programmed at the same time. This parameter must be a value between 0 and (max number of pages in the bank - 1)

Definition at line 102 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User BOR Level, FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby, FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH_OB_USER_BFB2 (*), FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes User SRAM Parity Check Type, FLASH Option Bytes User CCMSRAM Erase On Reset Type

Note:
(*) availability depends on devices

Definition at line 77 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User Type

Definition at line 75 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPArea

Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of FLASH WRP Area

Definition at line 66 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPEndOffset

Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1)

Definition at line 71 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPStartOffset

Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and (max number of pages in the bank - 1)

Definition at line 69 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_flash.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32g4xx_hal_flash.h>

Data Fields

HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | Address
__IO uint32_t | Bank
__IO uint32_t | Page
__IO uint32_t | NbPagesToErase
__IO FLASH_CacheTypeDef | CacheToReactivate

Detailed Description

FLASH handle Structure definition.

Definition at line 134 of file stm32g4xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Definition at line 139 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::Bank

Definition at line 140 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_CacheTypeDef FLASH_ProcessTypeDef::CacheToReactivate

Definition at line 143 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 137 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_GetError(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 136 of file stm32g4xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbPagesToErase

Definition at line 142 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Page

Definition at line 141 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 138 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_flash.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Error

Defines
FLASH Error
FLASH Exported Constants

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define | HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
#define | HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD

Define Documentation

#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC

Definition at line 169 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD

Definition at line 170 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR

Definition at line 166 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR

Definition at line 165 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_NONE 0x00000000U

Definition at line 158 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR

Definition at line 159 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR

Definition at line 168 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR

Definition at line 162 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR

Definition at line 164 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR

Definition at line 160 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR

Definition at line 167 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR

Definition at line 163 of file stm32g4xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR

Definition at line 161 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Erase Type

Defines
FLASH Erase Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_PAGES 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x01U

Define Documentation

#define FLASH_TYPEERASE_MASSERASE 0x01U

Flash mass erase activation

Definition at line 183 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES 0x00U

Pages erase only

Definition at line 182 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define | FLASH_BANK_1 0x00000001U
#define | FLASH_BANK_BOTH FLASH_BANK_1

Define Documentation

#define FLASH_BANK_1 0x00000001U

Bank 1

Definition at line 191 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_GetPCROP(), FLASH_OB_GetSecMem(), FLASH_OB_PCROPConfig(), FLASH_OB_SecMemConfig(), FLASH_PageErase(), HAL_FLASHEx_EnableSecMemProtection(), and HAL_FLASHEx_OBGetConfig().

#define FLASH_BANK_BOTH FLASH_BANK_1

Bank 1

Definition at line 196 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), and FLASH_OB_PCROPConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Program Type

Defines
FLASH Program Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U
#define | FLASH_TYPEPROGRAM_FAST 0x01U
#define | FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U

Program a double-word (64-bit) at a specified address.

Definition at line 206 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST 0x01U

Fast program a 32 row double-word (64-bit) at a specified address. And another 32 row double-word (64-bit) will be programmed

Definition at line 207 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U

Fast program a 32 row double-word (64-bit) at a specified address. And this is the last 32 row double-word (64-bit) programmed

Definition at line 209 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes Type

Defines
FLASH Option Bytes Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_PCROP 0x08U
#define | OPTIONBYTE_BOOT_LOCK 0x10U
#define | OPTIONBYTE_SEC 0x20U

Define Documentation

#define OPTIONBYTE_BOOT_LOCK 0x10U

Boot lock option byte configuration

Definition at line 222 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_PCROP 0x08U

PCROP option byte configuration

Definition at line 221 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP 0x02U

RDP option byte configuration

Definition at line 219 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_SEC 0x20U

Securable memory option byte configuration

Definition at line 223 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER 0x04U

USER option byte configuration

Definition at line 220 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP 0x01U

WRP option byte configuration

Definition at line 218 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH WRP Area

Defines
FLASH WRP Area
FLASH Exported Constants

Defines

#define | OB_WRPAREA_BANK1_AREAA 0x00U
#define | OB_WRPAREA_BANK1_AREAB 0x01U

Define Documentation

#define OB_WRPAREA_BANK1_AREAA 0x00U

Flash Bank 1 Area A

Definition at line 231 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), FLASH_OB_WRPConfig(), and HAL_FLASHEx_OBGetConfig().

#define OB_WRPAREA_BANK1_AREAB 0x01U

Flash Bank 1 Area B

Definition at line 232 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), FLASH_OB_WRPConfig(), and HAL_FLASHEx_OBGetConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Boot Lock

Defines
FLASH Boot Lock
FLASH Exported Constants

Defines

#define | OB_BOOT_LOCK_DISABLE 0x00000000U
#define | OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK

Define Documentation

#define OB_BOOT_LOCK_DISABLE 0x00000000U

Boot Lock Disable

Definition at line 244 of file stm32g4xx_hal_flash.h.

#define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK

Boot Lock Enable

Definition at line 245 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 0xAAU
#define | OB_RDP_LEVEL_1 0xBBU
#define | OB_RDP_LEVEL_2 0xCCU

Define Documentation

#define OB_RDP_LEVEL_0 0xAAU

Definition at line 253 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 0xBBU

Definition at line 254 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 0xCCU

Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0

Definition at line 255 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User Type

Defines
FLASH Option Bytes User Type
FLASH Exported Constants

Defines

#define | OB_USER_BOR_LEV 0x00000001U
#define | OB_USER_nRST_STOP 0x00000002U
#define | OB_USER_nRST_STDBY 0x00000004U
#define | OB_USER_IWDG_SW 0x00000008U
#define | OB_USER_IWDG_STOP 0x00000010U
#define | OB_USER_IWDG_STDBY 0x00000020U
#define | OB_USER_WWDG_SW 0x00000040U
#define | OB_USER_nBOOT1 0x00000200U
#define | OB_USER_SRAM_PE 0x00000400U
#define | OB_USER_CCMSRAM_RST 0x00000800U
#define | OB_USER_nRST_SHDW 0x00001000U
#define | OB_USER_nSWBOOT0 0x00002000U
#define | OB_USER_nBOOT0 0x00004000U
#define | OB_USER_NRST_MODE 0x00008000U
#define | OB_USER_IRHEN 0x00010000U

Define Documentation

#define OB_USER_BOR_LEV 0x00000001U

BOR reset Level

Definition at line 264 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_CCMSRAM_RST 0x00000800U

CCMSRAM Erase when system reset

Definition at line 280 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IRHEN 0x00010000U

Internal Reset Holder enable

Definition at line 285 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STDBY 0x00000020U

Independent watchdog counter freeze in standby mode

Definition at line 269 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STOP 0x00000010U

Independent watchdog counter freeze in stop mode

Definition at line 268 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_SW 0x00000008U

Independent watchdog selection

Definition at line 267 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nBOOT0 0x00004000U

nBOOT0 option bit

Definition at line 283 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nBOOT1 0x00000200U

Boot configuration

Definition at line 278 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_NRST_MODE 0x00008000U

Reset pin configuration

Definition at line 284 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_SHDW 0x00001000U

Reset generated when entering the shutdown mode

Definition at line 281 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_STDBY 0x00000004U

Reset generated when entering the standby mode

Definition at line 266 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_STOP 0x00000002U

Reset generated when entering the stop mode

Definition at line 265 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nSWBOOT0 0x00002000U

Software BOOT0

Definition at line 282 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SRAM_PE 0x00000400U

SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM)

Definition at line 279 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_WWDG_SW 0x00000040U

Window watchdog selection

Definition at line 270 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User BOR Level

Defines
FLASH Option Bytes User BOR Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0
#define | OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1
#define | OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2
#define | OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3
#define | OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4

Define Documentation

#define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0

Reset level threshold is around 1.7V

Definition at line 293 of file stm32g4xx_hal_flash.h.

#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1

Reset level threshold is around 2.0V

Definition at line 294 of file stm32g4xx_hal_flash.h.

#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2

Reset level threshold is around 2.2V

Definition at line 295 of file stm32g4xx_hal_flash.h.

#define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3

Reset level threshold is around 2.5V

Definition at line 296 of file stm32g4xx_hal_flash.h.

#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4

Reset level threshold is around 2.8V

Definition at line 297 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User Reset On Stop

Defines
FLASH Option Bytes User Reset On Stop
FLASH Exported Constants

Defines

#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP

Define Documentation

#define OB_STOP_NORST FLASH_OPTR_nRST_STOP

No reset generated when entering the stop mode

Definition at line 306 of file stm32g4xx_hal_flash.h.

#define OB_STOP_RST 0x00000000U

Reset generated when entering the stop mode

Definition at line 305 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User Reset On Standby

Defines
FLASH Option Bytes User Reset On Standby
FLASH Exported Constants

Defines

#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

Define Documentation

#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

No reset generated when entering the standby mode

Definition at line 315 of file stm32g4xx_hal_flash.h.

#define OB_STANDBY_RST 0x00000000U

Reset generated when entering the standby mode

Definition at line 314 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User Reset On Shutdown

Defines
FLASH Option Bytes User Reset On Shutdown
FLASH Exported Constants

Defines

#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

Define Documentation

#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

No reset generated when entering the shutdown mode

Definition at line 324 of file stm32g4xx_hal_flash.h.

#define OB_SHUTDOWN_RST 0x00000000U

Reset generated when entering the shutdown mode

Definition at line 323 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User IWDG Type

Defines
FLASH Option Bytes User IWDG Type
FLASH Exported Constants

Defines

#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW

Define Documentation

#define OB_IWDG_HW 0x00000000U

Hardware independent watchdog

Definition at line 332 of file stm32g4xx_hal_flash.h.

#define OB_IWDG_SW FLASH_OPTR_IWDG_SW

Software independent watchdog

Definition at line 333 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Stop

Defines
FLASH Option Bytes User IWDG Mode On Stop
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Define Documentation

#define OB_IWDG_STOP_FREEZE 0x00000000U

Independent watchdog counter is frozen in Stop mode

Definition at line 341 of file stm32g4xx_hal_flash.h.

#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Independent watchdog counter is running in Stop mode

Definition at line 342 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Standby

Defines
FLASH Option Bytes User IWDG Mode On Standby
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Define Documentation

#define OB_IWDG_STDBY_FREEZE 0x00000000U

Independent watchdog counter is frozen in Standby mode

Definition at line 350 of file stm32g4xx_hal_flash.h.

#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Independent watchdog counter is running in Standby mode

Definition at line 351 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User WWDG Type

Defines
FLASH Option Bytes User WWDG Type
FLASH Exported Constants

Defines

#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW

Define Documentation

#define OB_WWDG_HW 0x00000000U

Hardware window watchdog

Definition at line 359 of file stm32g4xx_hal_flash.h.

#define OB_WWDG_SW FLASH_OPTR_WWDG_SW

Software window watchdog

Definition at line 360 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User BOOT1 Type

Defines
FLASH Option Bytes User BOOT1 Type
FLASH Exported Constants

Defines

#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

Define Documentation

#define OB_BOOT1_SRAM 0x00000000U

Embedded SRAM1 is selected as boot space (if BOOT0=1)

Definition at line 399 of file stm32g4xx_hal_flash.h.

#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

System memory is selected as boot space (if BOOT0=1)

Definition at line 400 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User SRAM Parity Check Type

Defines
FLASH Option Bytes User SRAM Parity Check Type
FLASH Exported Constants

Defines

#define | OB_SRAM_PARITY_ENABLE 0x00000000U
#define | OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE

Define Documentation

#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE

SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM)

Definition at line 409 of file stm32g4xx_hal_flash.h.

#define OB_SRAM_PARITY_ENABLE 0x00000000U

SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM)

Definition at line 408 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User CCMSRAM Erase On Reset Type

Defines
FLASH Option Bytes User CCMSRAM Erase On Reset Type
FLASH Exported Constants

Defines

#define | OB_CCMSRAM_RST_ERASE 0x00000000U
#define | OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST

Define Documentation

#define OB_CCMSRAM_RST_ERASE 0x00000000U

CCMSRAM erased when a system reset occurs

Definition at line 417 of file stm32g4xx_hal_flash.h.

#define OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST

CCMSRAM is not erased when a system reset occurs

Definition at line 418 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User Software BOOT0

Defines
FLASH Option Bytes User Software BOOT0
FLASH Exported Constants

Defines

#define | OB_BOOT0_FROM_OB 0x00000000U
#define | OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0

Define Documentation

#define OB_BOOT0_FROM_OB 0x00000000U

BOOT0 taken from the option bit nBOOT0

Definition at line 426 of file stm32g4xx_hal_flash.h.

#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0

BOOT0 taken from PB8/BOOT0 pin

Definition at line 427 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User nBOOT0 option bit

Defines
FLASH Option Bytes User nBOOT0 option bit
FLASH Exported Constants

Defines

#define | OB_nBOOT0_RESET 0x00000000U
#define | OB_nBOOT0_SET FLASH_OPTR_nBOOT0

Define Documentation

#define OB_nBOOT0_RESET 0x00000000U

nBOOT0 = 0

Definition at line 435 of file stm32g4xx_hal_flash.h.

#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0

nBOOT0 = 1

Definition at line 436 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User NRST mode bit

Defines
FLASH Option Bytes User NRST mode bit
FLASH Exported Constants

Defines

#define | OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0
#define | OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1
#define | OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE

Define Documentation

#define OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1

Reset pin is in GPIO mode only

Definition at line 445 of file stm32g4xx_hal_flash.h.

#define OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0

Reset pin is in Reset input mode only

Definition at line 444 of file stm32g4xx_hal_flash.h.

#define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE

Reset pin is in reset input and output mode

Definition at line 446 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes User internal reset holder bit

Defines
FLASH Option Bytes User internal reset holder bit
FLASH Exported Constants

Defines

#define | OB_IRH_DISABLE 0x00000000U
#define | OB_IRH_ENABLE FLASH_OPTR_IRHEN

Define Documentation

#define OB_IRH_DISABLE 0x00000000U

Internal Reset holder disable

Definition at line 454 of file stm32g4xx_hal_flash.h.

#define OB_IRH_ENABLE FLASH_OPTR_IRHEN

Internal Reset holder enable

Definition at line 455 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Option Bytes PCROP On RDP Level Type

Defines
FLASH Option Bytes PCROP On RDP Level Type
FLASH Exported Constants

Defines

#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP

Define Documentation

#define OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 465 of file stm32g4xx_hal_flash.h.

#define OB_PCROP_RDP_NOT_ERASE 0x00000000U

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0

Definition at line 463 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 474 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 475 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS

FLASH Ten wait state

Definition at line 484 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS

FLASH Eleven wait state

Definition at line 485 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS

FLASH Twelve wait states

Definition at line 486 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS

FLASH Thirteen wait states

Definition at line 487 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS

FLASH Fourteen wait states

Definition at line 488 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

FLASH Fifteen wait states

Definition at line 489 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 476 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 477 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four wait states

Definition at line 478 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH Five wait state

Definition at line 479 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH Six wait state

Definition at line 480 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH Seven wait states

Definition at line 481 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS

FLASH Eight wait states

Definition at line 482 of file stm32g4xx_hal_flash.h.

#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS

FLASH Nine wait states

Definition at line 483 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_PDKEY1 0x04152637U
#define | FLASH_PDKEY2 0xFAFBFCFDU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU

Define Documentation

#define FLASH_KEY1 0x45670123U

Flash key1

Definition at line 497 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 0xCDEF89ABU

Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access

Definition at line 498 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPTKEY1 0x08192A3BU

Flash option byte key1

Definition at line 505 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPTKEY2 0x4C5D6E7FU

Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations

Definition at line 506 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_PDKEY1 0x04152637U

Flash power down key1

Definition at line 501 of file stm32g4xx_hal_flash.h.

#define FLASH_PDKEY2 0xFAFBFCFDU

Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR

Definition at line 502 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Flags Definition

Defines
FLASH Flags Definition
FLASH Exported Constants

Defines

#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_SR_ERRORS
#define | FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define | FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)

Define Documentation

#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)

Definition at line 543 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 526 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC

FLASH ECC correction in 64 LSB bits

Definition at line 527 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD

FLASH ECC detection in 64 LSB bits

Definition at line 528 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)

Definition at line 541 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of operation flag

Definition at line 515 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR

FLASH Fast programming error flag

Definition at line 523 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_MISERR FLASH_SR_MISERR

FLASH Fast programming data miss error flag

Definition at line 522 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_OPERR FLASH_SR_OPERR

FLASH Operation error flag

Definition at line 516 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR

FLASH Option validity error flag

Definition at line 525 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming alignment error flag

Definition at line 519 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

FLASH Programming sequence error flag

Definition at line 521 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR

FLASH Programming error flag

Definition at line 517 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_RDERR FLASH_SR_RDERR

FLASH PCROP read error flag

Definition at line 524 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR

FLASH Size error flag

Definition at line 520 of file stm32g4xx_hal_flash.h.

#define FLASH_FLAG_SR_ERRORS
Value:
(FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
                                   FLASH_FLAG_OPTVERR)

Definition at line 534 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protection error flag

Definition at line 518 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Interrupts Definition

Defines
FLASH Interrupts Definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U)

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U)

ECC Correction Interrupt source

Definition at line 555 of file stm32g4xx_hal_flash.h.

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 552 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_OPERR FLASH_CR_ERRIE

Error Interrupt source

Definition at line 553 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_RDERR FLASH_CR_RDERRIE

PCROP Read Error Interrupt source

Definition at line 554 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.
#define | __HAL_FLASH_POWER_DOWN_ENABLE()
Enable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_POWER_DOWN_DISABLE()
Disable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Enable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Disable the FLASH power down during Low-Power sleep mode.

Detailed Description

macros to control FLASH features

Define Documentation

#define __HAL_FLASH_DATA_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Disable the FLASH data cache.

Return values:
none

Definition at line 651 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_Init().

#define __HAL_FLASH_DATA_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Enable the FLASH data cache.

Return values:
none

Definition at line 645 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_DATA_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
                                                   } while (0)

Reset the FLASH data Cache.

Note:
This function must be used only when the data Cache is disabled.
Return values:
None

Definition at line 667 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_GET_LATENCY ( ) READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)

Get the FLASH Latency.

Return values:
FLASH_Latency. This parameter can be one of the following values :
  • FLASH_LATENCY_0: FLASH Zero wait state
  • FLASH_LATENCY_1: FLASH One wait state
  • FLASH_LATENCY_2: FLASH Two wait states
  • FLASH_LATENCY_3: FLASH Three wait states
  • FLASH_LATENCY_4: FLASH Four wait states
  • FLASH_LATENCY_5: FLASH Five wait states
  • FLASH_LATENCY_6: FLASH Six wait states
  • FLASH_LATENCY_7: FLASH Seven wait states
  • FLASH_LATENCY_8: FLASH Eight wait states
  • FLASH_LATENCY_9: FLASH Nine wait states
  • FLASH_LATENCY_10: FLASH Ten wait state
  • FLASH_LATENCY_11: FLASH Eleven wait state
  • FLASH_LATENCY_12: FLASH Twelve wait states
  • FLASH_LATENCY_13: FLASH Thirteen wait states
  • FLASH_LATENCY_14: FLASH Fourteen wait states
  • FLASH_LATENCY_15: FLASH Fifteen wait states

Definition at line 615 of file stm32g4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Disable the FLASH instruction cache.

Return values:
none

Definition at line 639 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Enable the FLASH instruction cache.

Return values:
none

Definition at line 633 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_INSTRUCTION_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
                                                   } while (0)

Reset the FLASH instruction Cache.

Note:
This function must be used only when the Instruction Cache is disabled.
Return values:
None

Definition at line 658 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_POWER_DOWN_DISABLE ( )
Value:
do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
                                                   } while (0)

Disable the FLASH power down during Low-power run mode.

Note:
Writing this bit to 0, automatically the keys are lost and a new unlock sequence is necessary to re-write it to 1.

Definition at line 686 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_DisableRunPowerDown().

#define __HAL_FLASH_POWER_DOWN_ENABLE ( )
Value:
do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
                                                   } while (0)

Enable the FLASH power down during Low-power run mode.

Note:
Writing this bit to 1, automatically the keys are lost and a new unlock sequence is necessary to re-write it to 0.

Definition at line 676 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_EnableRunPowerDown().

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 627 of file stm32g4xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 621 of file stm32g4xx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__ FLASH Latency. This parameter can be one of the following values :
  • FLASH_LATENCY_0: FLASH Zero wait state
  • FLASH_LATENCY_1: FLASH One wait state
  • FLASH_LATENCY_2: FLASH Two wait states
  • FLASH_LATENCY_3: FLASH Three wait states
  • FLASH_LATENCY_4: FLASH Four wait states
  • FLASH_LATENCY_5: FLASH Five wait states
  • FLASH_LATENCY_6: FLASH Six wait states
  • FLASH_LATENCY_7: FLASH Seven wait states
  • FLASH_LATENCY_8: FLASH Eight wait states
  • FLASH_LATENCY_9: FLASH Nine wait states
  • FLASH_LATENCY_10: FLASH Ten wait state
  • FLASH_LATENCY_11: FLASH Eleven wait state
  • FLASH_LATENCY_12: FLASH Twelve wait states
  • FLASH_LATENCY_13: FLASH Thirteen wait states
  • FLASH_LATENCY_14: FLASH Fourteen wait states
  • FLASH_LATENCY_15: FLASH Fifteen wait states
Return values:
None

Definition at line 592 of file stm32g4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)

Disable the FLASH power down during Low-Power sleep mode.

Return values:
none

Definition at line 701 of file stm32g4xx_hal_flash.h.

#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)

Enable the FLASH power down during Low-Power sleep mode.

Return values:
none

Definition at line 695 of file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Interrupts Macros

Defines
FLASH Interrupts Macros
FLASH

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
                                                   } while (0)

Clear the FLASH's pending flags.

Parameters:
__FLAG__ specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPERR: FLASH Operation error flag
  • FLASH_FLAG_PROGERR: FLASH Programming error flag
  • FLASH_FLAG_WRPERR: FLASH Write protection error flag
  • FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR: FLASH Size error flag
  • FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR: FLASH Fast programming error flag
  • FLASH_FLAG_RDERR: FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
  • FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
  • FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
  • FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
  • FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
  • FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
Note:
(*) availability depends on devices
Return values:
None

Definition at line 791 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while (0)

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_OPERR: Error Interrupt
  • FLASH_IT_RDERR: PCROP Read Error Interrupt
  • FLASH_IT_ECCC: ECC Correction Interrupt
Return values:
none

Definition at line 736 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while (0)

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_OPERR: Error Interrupt
  • FLASH_IT_RDERR: PCROP Read Error Interrupt
  • FLASH_IT_ECCC: ECC Correction Interrupt
Return values:
none

Definition at line 722 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))

Check whether the specified FLASH flag is set or not.

Parameters:
__FLAG__ specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPERR: FLASH Operation error flag
  • FLASH_FLAG_PROGERR: FLASH Programming error flag
  • FLASH_FLAG_WRPERR: FLASH Write protection error flag
  • FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR: FLASH Size error flag
  • FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR: FLASH Fast programming error flag
  • FLASH_FLAG_RDERR: FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
  • FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
  • FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
  • FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
  • FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
Note:
(*) availability depends on devices
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 763 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Exported Variables

Variables
FLASH Exported Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Variable used for Program/Erase sectors under interruption.

Definition at line 120 of file stm32g4xx_hal_flash.c.

Referenced by FLASH_FlushCaches(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
#define | IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#define | IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
#define | IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
#define | IS_OB_USER_BOR_LEVEL(LEVEL)
#define | IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define | IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define | IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define | IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define | IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#define | IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define | IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
#define | IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
#define | IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
#define | IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
#define | IS_OB_USER_NRST_MODE(VALUE)
#define | IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
#define | IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
#define | IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
#define | IS_FLASH_LATENCY(LATENCY)

Define Documentation

#define IS_FLASH_BANK ( BANK ) ((BANK) == FLASH_BANK_1)

Definition at line 911 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_MassErase(), and HAL_FLASHEx_EnableSecMemProtection().

#define IS_FLASH_BANK_EXCLUSIVE ( BANK ) ((BANK) == FLASH_BANK_1)

Definition at line 913 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), FLASH_OB_SecMemConfig(), and FLASH_PageErase().

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
                                            ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
                                            ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
                                            ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
                                            ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
                                            ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
                                            ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
                                            ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))

Definition at line 993 of file stm32g4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_MAIN_MEM_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))

Definition at line 920 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), and FLASH_Program_Fast().

#define IS_FLASH_OTP_ADDRESS ( ADDRESS ) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))

Definition at line 922 of file stm32g4xx_hal_flash.h.

#define IS_FLASH_PAGE ( PAGE ) ((PAGE) < FLASH_PAGE_NB)

Definition at line 926 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_WRPConfig(), and FLASH_PageErase().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS ) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))

Definition at line 924 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_Program_DoubleWord().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_PAGES) || \
                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 900 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))

Definition at line 916 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_OB_BOOT_LOCK ( VALUE ) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))

Definition at line 938 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_BootLockConfig().

#define IS_OB_PCROP_RDP ( VALUE ) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))

Definition at line 989 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0) ||\
                                            ((LEVEL) == OB_RDP_LEVEL_1) ||\
                                            ((LEVEL) == OB_RDP_LEVEL_2))

Definition at line 940 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_RDPConfig().

#define IS_OB_SECMEM_SIZE ( VALUE ) ((VALUE) <= FLASH_PAGE_NB)

Definition at line 991 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_SecMemConfig().

#define IS_OB_USER_BOOT0 ( VALUE ) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))

Definition at line 982 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_BOOT1 ( VALUE ) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))

Definition at line 974 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
                                            ((LEVEL) == OB_BOR_LEVEL_4))

Definition at line 946 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_CCMSRAM_RST ( VALUE ) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))

Definition at line 978 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IRHEN ( VALUE ) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))

Definition at line 987 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG ( VALUE ) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))

Definition at line 956 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STDBY ( VALUE ) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))

Definition at line 960 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STOP ( VALUE ) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))

Definition at line 958 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_NRST_MODE ( VALUE )
Value:
(((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
                                            ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))

Definition at line 984 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SHUTDOWN ( VALUE ) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))

Definition at line 954 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SRAM_PARITY ( VALUE ) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))

Definition at line 976 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_STANDBY ( VALUE ) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))

Definition at line 952 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_STOP ( VALUE ) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))

Definition at line 950 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SWBOOT0 ( VALUE ) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))

Definition at line 980 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_TYPE ( TYPE ) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))

Definition at line 944 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_WWDG ( VALUE ) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))

Definition at line 962 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRPAREA ( VALUE ) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))

Definition at line 935 of file stm32g4xx_hal_flash.h.

Referenced by FLASH_OB_WRPConfig().

#define IS_OPTIONBYTE ( VALUE )
Value:
(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
                                            OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))

Definition at line 928 of file stm32g4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
static HAL_StatusTypeDef | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection area into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
Configure the Proprietary code readout protection area into Option Bytes.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the Write Protection configuration into Option Bytes.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level into Option Bytes.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
Return the FLASH PCROP configuration into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_SecMemConfig (uint32_t SecBank, uint32_t SecSize)
Configure the Securable memory area into Option Bytes.
static void | FLASH_OB_GetSecMem (uint32_t SecBank, uint32_t *SecSize)
Return the Securable memory area configuration into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_BootLockConfig (uint32_t BootLockConfig)
Configure the Boot Lock into Option Bytes.
static uint32_t | FLASH_OB_GetBootLock (void)
Return the Boot Lock configuration into Option Byte.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Function Documentation

void FLASH_FlushCaches ( void )

Flush the instruction and data caches.

Return values:
None

Definition at line 613 of file stm32g4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, __HAL_FLASH_INSTRUCTION_CACHE_RESET, FLASH_ProcessTypeDef::CacheToReactivate, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_DISABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_ENABLED, and pFlash.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

static void FLASH_MassErase ( uint32_t Banks ) [static]

Mass erase of FLASH memory.

Parameters:
Banks Banks to be erased. This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased (*)
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
Note:
(*) availability depends on devices
Return values:
None

Definition at line 533 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, and IS_FLASH_BANK.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_BootLockConfig ( uint32_t BootLockConfig ) [static]

Configure the Boot Lock into Option Bytes.

Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Parameters:
BootLockConfig specifies the boot lock configuration. This parameter can be one of the following values:
  • OB_BOOT_LOCK_ENABLE: Enable Boot Lock
  • OB_BOOT_LOCK_DISABLE: Disable Boot Lock
Return values:
HAL_Status

Definition at line 1168 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_BOOT_LOCK.

Referenced by HAL_FLASHEx_OBProgram().

static uint32_t FLASH_OB_GetBootLock ( void ) [static]

Return the Boot Lock configuration into Option Byte.

Return values:
BootLockConfig. This return value can be one of the following values:
  • OB_BOOT_LOCK_ENABLE: Boot lock enabled
  • OB_BOOT_LOCK_DISABLE: Boot lock disabled

Definition at line 1229 of file stm32g4xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROPStartAddr,
 |  | uint32_t * | PCROPEndAddr
 | ) |  | [static]

Return the FLASH PCROP configuration into Option Bytes.

Parameters:
[in,out] | PCROPConfig | specifies the configuration (Bank to be configured and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
[out] | PCROPStartAddr | specifies the address where to copied the start address of the Proprietary code readout protection.
[out] | PCROPEndAddr | specifies the address where to copied the end address of the Proprietary code readout protection.
Return values:
None

Definition at line 1334 of file stm32g4xx_hal_flash_ex.c.

References FLASH_BANK_1, FLASH_BANK_BOTH, and FLASH_BANK_SIZE.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Return the FLASH Read Protection level into Option Bytes.

Return values:
RDP_Level This return value can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 1287 of file stm32g4xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetSecMem | ( | uint32_t | SecBank,
 |  | uint32_t * | SecSize
 | ) |  | [static]

Return the Securable memory area configuration into Option Bytes.

Parameters:
[in] SecBank specifies the bank where securable memory area is located. This parameter can be one of the following values:
  • FLASH_BANK_1: Securable memory in Bank1
  • FLASH_BANK_2: Securable memory in Bank2 (*)
Note:
(*) availability depends on devices
Parameters:
[out] SecSize specifies the number of pages used in the securable memory area of the bank.
Return values:
None

Definition at line 1203 of file stm32g4xx_hal_flash_ex.c.

References FLASH_BANK_1.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
OB_user_config This return value is a combination of FLASH Option Bytes User BOR Level, FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby, FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH Option Bytes User WWDG Type, FLASH_OB_USER_BFB2 (*), FLASH_OB_USER_DBANK (*), FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes User SRAM Parity Check Type, FLASH Option Bytes User CCMSRAM Erase On Reset Type, OB_USER_nSWBOOT0,FLASH Option Bytes User nBOOT0 option bit, FLASH Option Bytes User NRST mode bit, FLASH Option Bytes User internal reset holder bit
Note:
(*) availability depends on devices

Definition at line 1315 of file stm32g4xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetWRP | ( | uint32_t | WRPArea,
 |  | uint32_t * | WRPStartOffset,
 |  | uint32_t * | WRDPEndOffset
 | ) |  | [static]

Return the Write Protection configuration into Option Bytes.

Parameters:
[in] WRPArea specifies the area to be returned. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
  • OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x devices)
  • OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x devices)
[out] | WRPStartOffset | specifies the address where to copied the start page of the write protected area.
[out] | WRDPEndOffset | specifies the address where to copied the end page of the write protected area.
Return values:
None

Definition at line 1248 of file stm32g4xx_hal_flash_ex.c.

References OB_WRPAREA_BANK1_AREAA, and OB_WRPAREA_BANK1_AREAB.

Referenced by HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_PCROPConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROPStartAddr,
 |  | uint32_t | PCROPEndAddr
 | ) |  | [static]

Configure the Proprietary code readout protection area into Option Bytes.

Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Parameters:
PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*) with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
Note:
(*) availability depends on devices
Parameters:
PCROPStartAddr | specifies the start address of the Proprietary code readout protection. This parameter can be an address between begin and end of the bank.
PCROPEndAddr | specifies the end address of the Proprietary code readout protection. This parameter can be an address between PCROPStartAddr and end of the bank.
Return values:
HAL_Status

Definition at line 997 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_BOTH, FLASH_BANK_SIZE, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_MAIN_MEM_ADDRESS, and IS_OB_PCROP_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_RDPConfig ( uint32_t RDPLevel ) [static]

Set the read protection level into Option Bytes.

Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
!!! Warning : When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 !!!
Parameters:
RDPLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Memory Read protection
  • OB_RDP_LEVEL_2: Full chip protection
Return values:
HAL_Status

Definition at line 732 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_SecMemConfig | ( | uint32_t | SecBank,
 |  | uint32_t | SecSize
 | ) |  | [static]

Configure the Securable memory area into Option Bytes.

Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Parameters:
SecBank specifies bank of securable memory area to be configured. This parameter can be one of the following values:
  • FLASH_BANK_1: Securable memory in Bank1 to be configured
  • FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
Note:
(*) availability depends on devices
Parameters:
SecSize specifies the number of pages of the Securable memory area, starting from first page of the bank. This parameter can be page number between 0 and (max number of pages in the bank - 1)
Return values:
HAL Status

Definition at line 1115 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK_EXCLUSIVE, and IS_OB_SECMEM_SIZE.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig
 | ) |  | [static]

Program the FLASH User Option Bytes.

Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Parameters:
UserType | The FLASH User Option Bytes to be modified. This parameter can be a combination of FLASH Option Bytes User Type.
UserConfig | The selected User Option Bytes values: This parameter can be a combination of FLASH Option Bytes User BOR Level, FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby , FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH Option Bytes User WWDG Type, FLASH_OB_USER_BFB2 (*), FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes User SRAM Parity Check Type, FLASH Option Bytes User CCMSRAM Erase On Reset Type, FLASH Option Bytes User Software BOOT0, FLASH Option Bytes User nBOOT0 option bit, FLASH Option Bytes User NRST mode bit, FLASH Option Bytes User internal reset holder bit
Note:
(*) availability depends on devices
Return values:
HAL_Status

Definition at line 779 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_USER_BOOT0, IS_OB_USER_BOOT1, IS_OB_USER_BOR_LEVEL, IS_OB_USER_CCMSRAM_RST, IS_OB_USER_IRHEN, IS_OB_USER_IWDG, IS_OB_USER_IWDG_STDBY, IS_OB_USER_IWDG_STOP, IS_OB_USER_NRST_MODE, IS_OB_USER_SHUTDOWN, IS_OB_USER_SRAM_PARITY, IS_OB_USER_STANDBY, IS_OB_USER_STOP, IS_OB_USER_SWBOOT0, IS_OB_USER_TYPE, IS_OB_USER_WWDG, OB_USER_BOR_LEV, OB_USER_CCMSRAM_RST, OB_USER_IRHEN, OB_USER_IWDG_STDBY, OB_USER_IWDG_STOP, OB_USER_IWDG_SW, OB_USER_nBOOT0, OB_USER_nBOOT1, OB_USER_NRST_MODE, OB_USER_nRST_SHDW, OB_USER_nRST_STDBY, OB_USER_nRST_STOP, OB_USER_nSWBOOT0, OB_USER_SRAM_PE, and OB_USER_WWDG_SW.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_WRPConfig | ( | uint32_t | WRPArea,
 |  | uint32_t | WRPStartOffset,
 |  | uint32_t | WRDPEndOffset
 | ) |  | [static]

Configure the write protection area into Option Bytes.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated.
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Parameters:
WRPArea specifies the area to be configured. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
  • OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
  • OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
Note:
(*) availability depends on devices
Parameters:
WRPStartOffset | specifies the start page of the write protected area. This parameter can be page number between 0 and (max number of pages in the bank - 1).
WRDPEndOffset | specifies the end page of the write protected area. This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1).
Return values:
HAL_Status

Definition at line 667 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_PAGE, IS_OB_WRPAREA, OB_WRPAREA_BANK1_AREAA, and OB_WRPAREA_BANK1_AREAB.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase | ( | uint32_t | Page,
 |  | uint32_t | Banks
 | ) |  |

Erase the specified FLASH memory page.

Parameters:
Page FLASH page to erase. This parameter must be a value between 0 and (max number of pages in the bank - 1).
Banks Bank where the page will be erased. This parameter can be one of the following values:
  • FLASH_BANK_1: Page in bank 1 to be erased
  • FLASH_BANK_2: Page in bank 2 to be erased (*)
Note:
(*) availability depends on devices
Return values:
None

Definition at line 578 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_BANK_EXCLUSIVE, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASHEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
HAL_StatusTypeDef | HAL_FLASHEx_EnableSecMemProtection (uint32_t Bank)
Enable the FLASH Securable Memory protection.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extended FLASH
    programming operations Operations.

Function Documentation

void HAL_FLASHEx_DisableDebugger ( void )

Disable Debugger.

Note:
After calling this API, Debugger is disabled: it's no more possible to break, see CPU register, etc...
Return values:
None

Definition at line 505 of file stm32g4xx_hal_flash_ex.c.

void HAL_FLASHEx_EnableDebugger ( void )

Enable Debugger.

Note:
After calling this API, flash interface allow debugger intrusion.
Return values:
None

Definition at line 493 of file stm32g4xx_hal_flash_ex.c.

HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection ( uint32_t Bank )

Enable the FLASH Securable Memory protection.

Parameters:
Bank,: Bank to be protected This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be protected
  • FLASH_BANK_2: Bank2 to be protected (*)
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
Note:
(*) availability depends on devices
Return values:
HAL Status

Definition at line 459 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, and IS_FLASH_BANK.

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | PageError | pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased).
Return values:
HAL_Status

Definition at line 138 of file stm32g4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::CacheToReactivate, FLASH_ProcessTypeDef::ErrorCode, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_DISABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_ENABLED, FLASH_FlushCaches(), FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::Page, pFlash, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL_Status

Definition at line 237 of file stm32g4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_ENABLE_IT, assert_param, FLASH_ProcessTypeDef::Bank, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::CacheToReactivate, FLASH_ProcessTypeDef::ErrorCode, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_DISABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_ENABLED, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_MassErase(), FLASH_PageErase(), FLASH_PROC_MASS_ERASE, FLASH_PROC_PAGE_ERASE, FLASH_TYPEERASE_MASSERASE, HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_ProcessTypeDef::NbPagesToErase, FLASH_EraseInitTypeDef::Page, FLASH_ProcessTypeDef::Page, pFlash, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option bytes configuration.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information.
Note:
The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate which area is requested for the WRP and PCROP, else no information will be returned.
Return values:
None

Definition at line 399 of file stm32g4xx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::BootEntryPoint, FLASH_BANK_1, FLASH_OB_GetBootLock(), FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetSecMem(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OB_WRPAREA_BANK1_AREAA, OB_WRPAREA_BANK1_AREAB, OPTIONBYTE_BOOT_LOCK, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SEC, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecBank, FLASH_OBProgramInitTypeDef::SecSize, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program Option bytes.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account in two cases:
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • after a power reset (BOR reset or exit from Standby/Shutdown modes)
Return values:
HAL_Status

Definition at line 310 of file stm32g4xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::BootEntryPoint, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_BootLockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_ERROR_NONE, IS_OPTIONBYTE, OPTIONBYTE_BOOT_LOCK, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SEC, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, pFlash, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecBank, FLASH_OBProgramInitTypeDef::SecSize, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral features functions

Functions
Peripheral features functions
FLASH_RAMFUNC Exported Functions

Data transfers functions. More...

Functions

__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### ramfunc functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions that should be executed from RAM.

Function Documentation

__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown ( void )

Disable the Power down in Run Mode.

Note:
This function should be called and executed from SRAM memory.
Return values:
None

Definition at line 106 of file stm32g4xx_hal_flash_ramfunc.c.

References __HAL_FLASH_POWER_DOWN_DISABLE.

__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown ( void )

Enable the Power down in Run Mode.

Note:
This function should be called and executed from SRAM memory.
Return values:
None

Definition at line 92 of file stm32g4xx_hal_flash_ramfunc.c.

References __HAL_FLASH_POWER_DOWN_ENABLE.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Private Constants

Defines
FMAC Private Constants
FMAC

Defines

#define | MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
#define | MAX_PRELOAD_INDEX 0xFFU
#define | PRELOAD_ACCESS_DMA 0x00U
#define | PRELOAD_ACCESS_POLLING 0x01U
#define | POLLING_DISABLED 0U
#define | POLLING_ENABLED 1U
#define | POLLING_NOT_STOPPED 0U
#define | POLLING_STOPPED 1U
#define | HAL_FMAC_TIMEOUT_VALUE 1000U
#define | HAL_FMAC_RESET_TIMEOUT_VALUE 500U
#define | FMAC_DMA_REN FMAC_CR_DMAREN
#define | FMAC_DMA_WEN FMAC_CR_DMAWEN
#define | FMAC_START FMAC_PARAM_START
#define | FMAC_PARAM_P_MAX_IIR 64U
#define | FMAC_PARAM_P_MAX_FIR 127U
#define | FMAC_PARAM_P_MIN 2U
#define | FMAC_PARAM_Q_MAX 63U
#define | FMAC_PARAM_Q_MIN 1U
#define | FMAC_PARAM_R_MAX 7U

Define Documentation

#define FMAC_DMA_REN FMAC_CR_DMAREN

Definition at line 246 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_FilterStart(), and HAL_FMAC_FilterStop().

#define FMAC_DMA_WEN FMAC_CR_DMAWEN

Definition at line 248 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_FilterStart(), and HAL_FMAC_FilterStop().

#define FMAC_PARAM_P_MAX_FIR 127U

Maximum value of P parameter with FIR

Definition at line 492 of file stm32g4xx_hal_fmac.h.

#define FMAC_PARAM_P_MAX_IIR 64U

Maximum value of P parameter with IIR

Definition at line 491 of file stm32g4xx_hal_fmac.h.

#define FMAC_PARAM_P_MIN 2U

Minimum value of P parameter

Definition at line 493 of file stm32g4xx_hal_fmac.h.

#define FMAC_PARAM_Q_MAX 63U

Maximum value of Q parameter

Definition at line 494 of file stm32g4xx_hal_fmac.h.

#define FMAC_PARAM_Q_MIN 1U

Minimum value of Q parameter

Definition at line 495 of file stm32g4xx_hal_fmac.h.

#define FMAC_PARAM_R_MAX 7U

Maximum value of R parameter

Definition at line 496 of file stm32g4xx_hal_fmac.h.

#define FMAC_START FMAC_PARAM_START

Definition at line 250 of file stm32g4xx_hal_fmac.c.

#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U

Definition at line 244 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_Reset().

#define HAL_FMAC_TIMEOUT_VALUE 1000U

Definition at line 242 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig(), and FMAC_FilterPreload().

#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)

Definition at line 233 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_PollFilterData().

#define MAX_PRELOAD_INDEX 0xFFU

Definition at line 234 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_DMAFilterConfig(), and FMAC_DMAFilterPreload().

#define POLLING_DISABLED 0U

Definition at line 237 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_PollFilterData().

#define POLLING_ENABLED 1U

Definition at line 238 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_PollFilterData().

#define POLLING_NOT_STOPPED 0U

Definition at line 239 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_PollFilterData().

#define POLLING_STOPPED 1U

Definition at line 240 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_PollFilterData().

#define PRELOAD_ACCESS_DMA 0x00U

Definition at line 235 of file stm32g4xx_hal_fmac.c.

Referenced by HAL_FMAC_FilterConfig_DMA(), and HAL_FMAC_FilterPreload_DMA().

#define PRELOAD_ACCESS_POLLING 0x01U

Definition at line 236 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_FMAC_FilterConfig(), and HAL_FMAC_FilterPreload().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Private Macros

Defines
FMAC Private Macros
FMAC

Defines

#define | FMAC_GET_X1_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
Get the X1 memory area size.
#define | FMAC_GET_X1_FULL_WM(__HANDLE__) (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
Get the X1 watermark.
#define | FMAC_GET_X2_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
Get the X2 memory area size.
#define | FMAC_GET_Y_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
Get the Y memory area size.
#define | FMAC_GET_Y_EMPTY_WM(__HANDLE__) (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
Get the Y watermark.
#define | FMAC_GET_START_BIT(__HANDLE__) ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
Get the start bit state.
#define | FMAC_GET_THRESHOLD_FROM_WM(__WM__)
Get the threshold matching the watermark.
#define | IS_FMAC_FUNCTION(__FUNCTION__)
Verify the FMAC function.
#define | IS_FMAC_LOAD_FUNCTION(__FUNCTION__)
Verify the FMAC load function used for input data, output data or coefficients.
#define | IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__)
Verify the FMAC load function used with N values as input or output data.
#define | IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
Verify the FMAC load function used with N + M values as coefficients.
#define | IS_FMAC_FILTER_FUNCTION(__FUNCTION__)
Verify the FMAC filter function.
#define | IS_FMAC_THRESHOLD(__THRESHOLD__)
Verify the FMAC threshold.
#define | IS_FMAC_PARAM_P(__FUNCTION__, __P__)
Verify the FMAC filter parameter P.
#define | IS_FMAC_PARAM_Q(__FUNCTION__, __Q__)
Verify the FMAC filter parameter Q.
#define | IS_FMAC_PARAM_R(__FUNCTION__, __R__)
Verify the FMAC filter parameter R.
#define | IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__)
Verify the FMAC buffer access.
#define | IS_FMAC_CLIP_STATE(__CLIP_STATE__)
Verify the FMAC clip feature.
#define | IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__)
Check whether the threshold is applicable.

Define Documentation

#define FMAC_GET_START_BIT ( __HANDLE__ ) ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))

Get the start bit state.

Parameters:
__HANDLE__ FMAC handle.
Return values:
START

Definition at line 306 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_FMAC_AppendFilterData(), HAL_FMAC_ConfigFilterOutputBuffer(), HAL_FMAC_FilterStart(), and HAL_FMAC_PollFilterData().

#define FMAC_GET_THRESHOLD_FROM_WM ( __WM__ )
Value:
(((__WM__) == FMAC_THRESHOLD_1)? 1U: \
                                            ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
                                            ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)

Get the threshold matching the watermark.

Parameters:
__WM__ Watermark value.
Return values:
THRESHOLD

Definition at line 314 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_ReadDataIncrementPtr(), and FMAC_WriteDataIncrementPtr().

#define FMAC_GET_X1_FULL_WM ( __HANDLE__ ) (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))

Get the X1 watermark.

Parameters:
__HANDLE__ FMAC handle.
Return values:
FULL_WM

Definition at line 274 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_WriteDataIncrementPtr().

#define FMAC_GET_X1_SIZE ( __HANDLE__ ) ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))

Get the X1 memory area size.

Parameters:
__HANDLE__ FMAC handle.
Return values:
X1_BUF_SIZE

Definition at line 266 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig(), FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define FMAC_GET_X2_SIZE ( __HANDLE__ ) ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))

Get the X2 memory area size.

Parameters:
__HANDLE__ FMAC handle.
Return values:
X2_BUF_SIZE

Definition at line 282 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig().

#define FMAC_GET_Y_EMPTY_WM ( __HANDLE__ ) (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))

Get the Y watermark.

Parameters:
__HANDLE__ FMAC handle.
Return values:
EMPTY_WM

Definition at line 298 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_ReadDataIncrementPtr().

#define FMAC_GET_Y_SIZE ( __HANDLE__ ) ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))

Get the Y memory area size.

Parameters:
__HANDLE__ FMAC handle.
Return values:
Y_BUF_SIZE

Definition at line 290 of file stm32g4xx_hal_fmac.c.

Referenced by FMAC_FilterConfig(), FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define IS_FMAC_BUFFER_ACCESS ( __BUFFER_ACCESS__ )
Value:
(((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE)    || \
                                                  ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA)     || \
                                                  ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
                                                  ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))

Verify the FMAC buffer access.

Parameters:
__BUFFER_ACCESS__ Type of access.
Return values:
SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)

Definition at line 600 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_CLIP_STATE ( __CLIP_STATE__ )
Value:
(((__CLIP_STATE__) == FMAC_CLIP_DISABLED)                  || \
                                            ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))

Verify the FMAC clip feature.

Parameters:
__CLIP_STATE__ Clip state.
Return values:
SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)

Definition at line 610 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_FILTER_FUNCTION ( __FUNCTION__ )
Value:
(((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                || \
                                               ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))

Verify the FMAC filter function.

Parameters:
__FUNCTION__ ID of the filter function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 547 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_FUNCTION ( __FUNCTION__ )
Value:
(((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                         || \
                                        ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)                         || \
                                        ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)                          || \
                                        ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                       || \
                                        ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))

Verify the FMAC function.

Parameters:
__FUNCTION__ ID of the function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 512 of file stm32g4xx_hal_fmac.h.

#define IS_FMAC_LOAD_FUNCTION ( __FUNCTION__ )
Value:
(((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                    || \
                                             ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)                    || \
                                             ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))

Verify the FMAC load function used for input data, output data or coefficients.

Parameters:
__FUNCTION__ ID of the load function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 523 of file stm32g4xx_hal_fmac.h.

#define IS_FMAC_N_LOAD_FUNCTION ( __FUNCTION__ )
Value:
(((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                  || \
                                               ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))

Verify the FMAC load function used with N values as input or output data.

Parameters:
__FUNCTION__ ID of the load function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 532 of file stm32g4xx_hal_fmac.h.

#define IS_FMAC_N_M_LOAD_FUNCTION ( __FUNCTION__ ) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)

Verify the FMAC load function used with N + M values as coefficients.

Parameters:
__FUNCTION__ ID of the load function.
Return values:
SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)

Definition at line 540 of file stm32g4xx_hal_fmac.h.

#define IS_FMAC_PARAM_P | ( | __FUNCTION__,
 |  | __P__
 | ) |
Value:
((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               && \
                                               (((__P__) >= FMAC_PARAM_P_MIN) && \
                                                ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
                                              (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
                                               (((__P__) >= FMAC_PARAM_P_MIN) && \
                                                ((__P__) <= FMAC_PARAM_P_MAX_IIR))))

Verify the FMAC filter parameter P.

Parameters:
__P__ | Value of the filter parameter P.
__FUNCTION__ | ID of the filter function.
Return values:
SET (__P__ is a valid value) or RESET (__P__ is invalid)

Definition at line 568 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_PARAM_Q | ( | __FUNCTION__,
 |  | __Q__
 | ) |
Value:
( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                || \
                                               (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
                                                (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )

Verify the FMAC filter parameter Q.

Parameters:
__Q__ | Value of the filter parameter Q.
__FUNCTION__ | ID of the filter function.
Return values:
SET (__Q__ is a valid value) or RESET (__Q__ is invalid)

Definition at line 581 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_PARAM_R | ( | __FUNCTION__,
 |  | __R__
 | ) |
Value:
( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               || \
                                                ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))      && \
                                               ((__R__) <= FMAC_PARAM_R_MAX))

Verify the FMAC filter parameter R.

Parameters:
__R__ | Value of the filter parameter.
__FUNCTION__ | ID of the filter function.
Return values:
SET (__R__ is a valid value) or RESET (__R__ is invalid)

Definition at line 591 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == FMAC_THRESHOLD_1)                       || \
                                          ((__THRESHOLD__) == FMAC_THRESHOLD_2)                       || \
                                          ((__THRESHOLD__) == FMAC_THRESHOLD_4)                       || \
                                          ((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE)                || \
                                          ((__THRESHOLD__) == FMAC_THRESHOLD_8))

Verify the FMAC threshold.

Parameters:
__THRESHOLD__ Value of the threshold.
Return values:
SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)

Definition at line 556 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define IS_FMAC_THRESHOLD_APPLICABLE | ( | __SIZE__,
 |  | __WM__,
 |  | __ACCESS__
 | ) |
Value:
(( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
                    ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
                    ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
   ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
     ((__WM__) == FMAC_THRESHOLD_1))|| \
    ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))

Check whether the threshold is applicable.

Parameters:
__SIZE__ | Size of the matching buffer.
__WM__ | Watermark value.
__ACCESS__ | Access to the buffer (polling, it, dma, none).
Return values:
THRESHOLD

Definition at line 620 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FMAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FMAC_Init (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_FMAC_DeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC peripheral.
__weak void | HAL_FMAC_MspInit (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC MSP.
__weak void | HAL_FMAC_MspDeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC MSP.
HAL_StatusTypeDef | HAL_FMAC_RegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID, pFMAC_CallbackTypeDef pCallback)
Register a User FMAC Callback.
HAL_StatusTypeDef | HAL_FMAC_UnRegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
Unregister a FMAC CallBack.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
     #####       Initialization and de-initialization functions       #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Initialize the FMAC peripheral and the associated handle
      (+) DeInitialize the FMAC peripheral
      (+) Initialize the FMAC MSP (MCU Specific Package)
      (+) De-Initialize the FMAC MSP
      (+) Register a User FMAC Callback
      (+) Unregister a FMAC CallBack

    [..]

Function Documentation

HAL_StatusTypeDef HAL_FMAC_DeInit ( FMAC_HandleTypeDef * hfmac )

De-initialize the FMAC peripheral.

Parameters:
hfmac pointer to a FMAC structure.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 455 of file stm32g4xx_hal_fmac.c.

References assert_param, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterParam, FMAC_ResetDataPointers(), HAL_FMAC_ERROR_NONE, HAL_FMAC_MspDeInit(), HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_RESET, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::MspDeInitCallback, and __FMAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMAC_Init ( FMAC_HandleTypeDef * hfmac )

Initialize the FMAC peripheral and the associated handle.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 382 of file stm32g4xx_hal_fmac.c.

References assert_param, __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterConfigCallback, __FMAC_HandleTypeDef::FilterParam, __FMAC_HandleTypeDef::FilterPreloadCallback, FMAC_Reset(), FMAC_ResetDataPointers(), __FMAC_HandleTypeDef::GetDataCallback, HAL_FMAC_ERROR_NONE, HAL_FMAC_ERROR_RESET, HAL_FMAC_ErrorCallback(), HAL_FMAC_FilterConfigCallback(), HAL_FMAC_FilterPreloadCallback(), HAL_FMAC_GetDataCallback(), HAL_FMAC_HalfGetDataCallback(), HAL_FMAC_HalfOutputDataReadyCallback(), HAL_FMAC_MspInit(), HAL_FMAC_OutputDataReadyCallback(), HAL_FMAC_STATE_READY, HAL_FMAC_STATE_RESET, HAL_FMAC_STATE_TIMEOUT, __FMAC_HandleTypeDef::HalfGetDataCallback, __FMAC_HandleTypeDef::HalfOutputDataReadyCallback, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::Lock, __FMAC_HandleTypeDef::MspInitCallback, __FMAC_HandleTypeDef::OutputDataReadyCallback, and __FMAC_HandleTypeDef::State.

void HAL_FMAC_MspDeInit ( FMAC_HandleTypeDef * hfmac )

De-initialize the FMAC MSP.

Parameters:
hfmac FMAC handle.
Return values:
None

Definition at line 517 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by HAL_FMAC_DeInit(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_MspInit ( FMAC_HandleTypeDef * hfmac )

Initialize the FMAC MSP.

Parameters:
hfmac FMAC handle.
Return values:
None

Definition at line 502 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by HAL_FMAC_Init(), and HAL_FMAC_UnRegisterCallback().

HAL_StatusTypeDef HAL_FMAC_RegisterCallback | ( | FMAC_HandleTypeDef * | hfmac,
 |  | HAL_FMAC_CallbackIDTypeDef | CallbackID,
 |  | pFMAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User FMAC Callback.

Note:
The User FMAC Callback is to be used instead of the weak predefined callback.
The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_FMAC_ERROR_CB_ID Error Callback ID
  • HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
  • HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
  • HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
  • HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
  • HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
  • HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
  • HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
  • HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
pCallback | pointer to the Callback function.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 549 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterConfigCallback, __FMAC_HandleTypeDef::FilterPreloadCallback, __FMAC_HandleTypeDef::GetDataCallback, HAL_FMAC_ERROR_CB_ID, HAL_FMAC_ERROR_INVALID_CALLBACK, HAL_FMAC_FILTER_CONFIG_CB_ID, HAL_FMAC_FILTER_PRELOAD_CB_ID, HAL_FMAC_GET_DATA_CB_ID, HAL_FMAC_HALF_GET_DATA_CB_ID, HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID, HAL_FMAC_MSPDEINIT_CB_ID, HAL_FMAC_MSPINIT_CB_ID, HAL_FMAC_OUTPUT_DATA_READY_CB_ID, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_RESET, __FMAC_HandleTypeDef::HalfGetDataCallback, __FMAC_HandleTypeDef::HalfOutputDataReadyCallback, __FMAC_HandleTypeDef::MspDeInitCallback, __FMAC_HandleTypeDef::MspInitCallback, __FMAC_HandleTypeDef::OutputDataReadyCallback, and __FMAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback | ( | FMAC_HandleTypeDef * | hfmac,
 |  | HAL_FMAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a FMAC CallBack.

Note:
The FMAC callback is redirected to the weak predefined callback.
The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_FMAC_ERROR_CB_ID Error Callback ID
  • HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
  • HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
  • HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
  • HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
  • HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
  • HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
  • HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
  • HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
Return values:
HAL_StatusTypeDef HAL status

Definition at line 670 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterConfigCallback, __FMAC_HandleTypeDef::FilterPreloadCallback, __FMAC_HandleTypeDef::GetDataCallback, HAL_FMAC_ERROR_CB_ID, HAL_FMAC_ERROR_INVALID_CALLBACK, HAL_FMAC_ErrorCallback(), HAL_FMAC_FILTER_CONFIG_CB_ID, HAL_FMAC_FILTER_PRELOAD_CB_ID, HAL_FMAC_FilterConfigCallback(), HAL_FMAC_FilterPreloadCallback(), HAL_FMAC_GET_DATA_CB_ID, HAL_FMAC_GetDataCallback(), HAL_FMAC_HALF_GET_DATA_CB_ID, HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID, HAL_FMAC_HalfGetDataCallback(), HAL_FMAC_HalfOutputDataReadyCallback(), HAL_FMAC_MspDeInit(), HAL_FMAC_MSPDEINIT_CB_ID, HAL_FMAC_MspInit(), HAL_FMAC_MSPINIT_CB_ID, HAL_FMAC_OUTPUT_DATA_READY_CB_ID, HAL_FMAC_OutputDataReadyCallback(), HAL_FMAC_STATE_READY, HAL_FMAC_STATE_RESET, __FMAC_HandleTypeDef::HalfGetDataCallback, __FMAC_HandleTypeDef::HalfOutputDataReadyCallback, __FMAC_HandleTypeDef::MspDeInitCallback, __FMAC_HandleTypeDef::MspInitCallback, __FMAC_HandleTypeDef::OutputDataReadyCallback, and __FMAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FMAC Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_FMAC_FilterConfig (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterConfig_DMA (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload_DMA (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterStart (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Start the FMAC processing according to the existing FMAC configuration.
HAL_StatusTypeDef | HAL_FMAC_AppendFilterData (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
Provide a new input buffer that will be loaded into the FMAC input memory area.
HAL_StatusTypeDef | HAL_FMAC_ConfigFilterOutputBuffer (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Provide a new output buffer to be filled with the data computed by FMAC unit.
HAL_StatusTypeDef | HAL_FMAC_PollFilterData (FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
Handle the input and/or output data in polling mode.
HAL_StatusTypeDef | HAL_FMAC_FilterStop (FMAC_HandleTypeDef *hfmac)
Stop the FMAC processing.

Detailed Description

Control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the FMAC peripheral: memory area, filter type and parameters,
          way to access to the input and output memory area (none, polling, IT, DMA).
      (+) Start the FMAC processing (filter).
      (+) Handle the input data that will be provided into FMAC.
      (+) Handle the output data provided by FMAC.
      (+) Stop the FMAC processing (filter).

Function Documentation

HAL_StatusTypeDef HAL_FMAC_AppendFilterData | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pInput,
 |  | uint16_t * | pInputSize
 | ) |  |

Provide a new input buffer that will be loaded into the FMAC input memory area.

Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pInput | New input vector (additional input data).
pInputSize | Size of the input vector (if all the data can't be written, it will be updated with the number of data read from FMAC).
Return values:
HAL_StatusTypeDef HAL status

Definition at line 968 of file stm32g4xx_hal_fmac.c.

References FMAC_AppendFilterDataUpdateState(), FMAC_BUFFER_ACCESS_NONE, FMAC_GET_START_BIT, HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::InputAccess, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::pInputSize, and __FMAC_HandleTypeDef::WrState.

HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pOutput,
 |  | uint16_t * | pOutputSize
 | ) |  |

Provide a new output buffer to be filled with the data computed by FMAC unit.

Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pOutput | New output vector.
pOutputSize | Size of the output vector (if the vector can't be entirely filled, pOutputSize will be updated with the number of data read from FMAC).
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1024 of file stm32g4xx_hal_fmac.c.

References FMAC_BUFFER_ACCESS_NONE, FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_GET_START_BIT, HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::OutputAccess, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pOutputSize, and __FMAC_HandleTypeDef::RdState.

HAL_StatusTypeDef HAL_FMAC_FilterConfig | ( | FMAC_HandleTypeDef * | hfmac,
 |  | FMAC_FilterConfigTypeDef * | pConfig
 | ) |  |

Configure the FMAC filter.

Note:
The configuration is done according to the parameters specified in the FMAC_FilterConfigTypeDef structure. The provided data will be loaded using polling mode.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pConfig | pointer to a FMAC_FilterConfigTypeDef structure that contains the FMAC configuration information.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 800 of file stm32g4xx_hal_fmac.c.

References FMAC_FilterConfig(), and PRELOAD_ACCESS_POLLING.

HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA | ( | FMAC_HandleTypeDef * | hfmac,
 |  | FMAC_FilterConfigTypeDef * | pConfig
 | ) |  |

Configure the FMAC filter.

Note:
The configuration is done according to the parameters specified in the FMAC_FilterConfigTypeDef structure. The provided data will be loaded using DMA.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pConfig | pointer to a FMAC_FilterConfigTypeDef structure that contains the FMAC configuration information.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 816 of file stm32g4xx_hal_fmac.c.

References FMAC_FilterConfig(), and PRELOAD_ACCESS_DMA.

HAL_StatusTypeDef HAL_FMAC_FilterPreload | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pInput,
 |  | uint8_t | InputSize,
 |  | int16_t * | pOutput,
 |  | uint8_t | OutputSize
 | ) |  |

Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.

Note:
The set(s) of data will be used by FMAC as soon as HAL_FMAC_FilterStart is called. The provided data will be loaded using polling mode.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pInput | Preloading of the first elements of the input buffer (X1). If not needed (no data available when starting), it should be set to NULL.
InputSize | Size of the input vector. As pInput is used for preloading data, it cannot be bigger than the input memory area.
pOutput | [IIR] Preloading of the first elements of the output vector (Y). If not needed, it should be set to NULL.
OutputSize | Size of the output vector. As pOutput is used for preloading data, it cannot be bigger than the output memory area.
Note:
The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload (each call filling partly the buffers). In case of overflow (too much data provided through all these calls), an error will be returned.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 840 of file stm32g4xx_hal_fmac.c.

References FMAC_FilterPreload(), and PRELOAD_ACCESS_POLLING.

HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pInput,
 |  | uint8_t | InputSize,
 |  | int16_t * | pOutput,
 |  | uint8_t | OutputSize
 | ) |  |

Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.

Note:
The set(s) of data will be used by FMAC as soon as HAL_FMAC_FilterStart is called. The provided data will be loaded using DMA.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pInput | Preloading of the first elements of the input buffer (X1). If not needed (no data available when starting), it should be set to NULL.
InputSize | Size of the input vector. As pInput is used for preloading data, it cannot be bigger than the input memory area.
pOutput | [IIR] Preloading of the first elements of the output vector (Y). If not needed, it should be set to NULL.
OutputSize | Size of the output vector. As pOutput is used for preloading data, it cannot be bigger than the output memory area.
Note:
The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload (each call filling partly the buffers). In case of overflow (too much data provided through all these calls), an error will be returned.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 865 of file stm32g4xx_hal_fmac.c.

References FMAC_FilterPreload(), and PRELOAD_ACCESS_DMA.

HAL_StatusTypeDef HAL_FMAC_FilterStart | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pOutput,
 |  | uint16_t * | pOutputSize
 | ) |  |

Start the FMAC processing according to the existing FMAC configuration.

Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pOutput | pointer to buffer where output data of FMAC processing will be stored in the next steps. If it is set to NULL, the output will not be read and it will be up to an external IP to empty the output buffer.
pOutputSize | pointer to the size of the output buffer. The number of read data will be written here.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 883 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::FilterParam, FMAC_BUFFER_ACCESS_DMA, FMAC_BUFFER_ACCESS_IT, FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMA_REN, FMAC_DMA_WEN, FMAC_GET_START_BIT, FMAC_IT_RIEN, FMAC_IT_WIEN, HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::InputAccess, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::OutputAccess, and __FMAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMAC_FilterStop ( FMAC_HandleTypeDef * hfmac )

Stop the FMAC processing.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1204 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCode, FMAC_BUFFER_ACCESS_IT, FMAC_DMA_REN, FMAC_DMA_WEN, FMAC_IT_RIEN, FMAC_IT_WIEN, FMAC_Reset(), FMAC_ResetDataPointers(), HAL_FMAC_ERROR_RESET, HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_TIMEOUT, __FMAC_HandleTypeDef::InputAccess, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::OutputAccess, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::pInputSize, __FMAC_HandleTypeDef::pOutput, __FMAC_HandleTypeDef::pOutputSize, and __FMAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMAC_PollFilterData | ( | FMAC_HandleTypeDef * | hfmac,
 |  | uint32_t | Timeout
 | ) |  |

Handle the input and/or output data in polling mode.

Note:
This function writes the previously provided user's input data and fills the previously provided user's output buffer, according to the existing FMAC configuration (polling mode only). The function returns when the input data has been handled or when the output data is filled. The possible unused data isn't kept. It will be up to the user to handle it. The previously provided pInputSize and pOutputSize will be used to indicate to the size of the read/written data to the user.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Timeout | timeout value.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1085 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCode, FMAC_BUFFER_ACCESS_POLLING, FMAC_GET_START_BIT, FMAC_ReadDataIncrementPtr(), FMAC_ResetInputStateAndDataPointers(), FMAC_ResetOutputStateAndDataPointers(), FMAC_WriteDataIncrementPtr(), HAL_FMAC_ERROR_TIMEOUT, HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_READY, HAL_GetTick(), __FMAC_HandleTypeDef::InputAccess, __FMAC_HandleTypeDef::InputCurrentSize, MAX_FILTER_DATA_SIZE_TO_HANDLE, __FMAC_HandleTypeDef::OutputAccess, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::pInputSize, POLLING_DISABLED, POLLING_ENABLED, POLLING_NOT_STOPPED, POLLING_STOPPED, __FMAC_HandleTypeDef::pOutput, __FMAC_HandleTypeDef::pOutputSize, and __FMAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Callback functions

Functions
Callback functions
FMAC Exported Functions

Callback functions. More...

Functions

__weak void | HAL_FMAC_ErrorCallback (FMAC_HandleTypeDef *hfmac)
FMAC error callback.
__weak void | HAL_FMAC_HalfGetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get half data callback.
__weak void | HAL_FMAC_GetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get data callback.
__weak void | HAL_FMAC_HalfOutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC half output data ready callback.
__weak void | HAL_FMAC_OutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC output data ready callback.
__weak void | HAL_FMAC_FilterConfigCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter configuration callback.
__weak void | HAL_FMAC_FilterPreloadCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter preload callback.

Detailed Description

Callback functions.

  ==============================================================================
                      ##### Callback functions  #####
  ==============================================================================
    [..]  This section provides Interruption and DMA callback functions:
      (+) DMA or Interrupt: the user's input data is half written (DMA only)
          or completely written.
      (+) DMA or Interrupt: the user's output buffer is half filled (DMA only)
          or completely filled.
      (+) DMA or Interrupt: error handling.

Function Documentation

void HAL_FMAC_ErrorCallback ( FMAC_HandleTypeDef * hfmac )

FMAC error callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1285 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAError(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_FilterConfigCallback ( FMAC_HandleTypeDef * hfmac )

FMAC filter configuration callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1365 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAFilterConfig(), HAL_FMAC_Init(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_FilterPreloadCallback ( FMAC_HandleTypeDef * hfmac )

FMAC filter preload callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1381 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAFilterPreload(), HAL_FMAC_Init(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_GetDataCallback ( FMAC_HandleTypeDef * hfmac )

FMAC get data callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1317 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAGetData(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_HalfGetDataCallback ( FMAC_HandleTypeDef * hfmac )

FMAC get half data callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1301 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAHalfGetData(), HAL_FMAC_Init(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_HalfOutputDataReadyCallback ( FMAC_HandleTypeDef * hfmac )

FMAC half output data ready callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1333 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAHalfOutputDataReady(), HAL_FMAC_Init(), and HAL_FMAC_UnRegisterCallback().

void HAL_FMAC_OutputDataReadyCallback ( FMAC_HandleTypeDef * hfmac )

FMAC output data ready callback.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1349 of file stm32g4xx_hal_fmac.c.

References UNUSED.

Referenced by FMAC_DMAOutputDataReady(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), and HAL_FMAC_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRQ handler management

Functions
IRQ handler management
FMAC Exported Functions

IRQ handler. More...

Functions

void HAL_FMAC_IRQHandler (FMAC_HandleTypeDef *hfmac)
Handle FMAC interrupt request.

Detailed Description

IRQ handler.

  ==============================================================================
                ##### IRQ handler management #####
  ==============================================================================
[..]  This section provides IRQ handler function.

Function Documentation

void HAL_FMAC_IRQHandler ( FMAC_HandleTypeDef * hfmac )

Handle FMAC interrupt request.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
None

Definition at line 1414 of file stm32g4xx_hal_fmac.c.

References __HAL_FMAC_GET_FLAG, __HAL_FMAC_GET_IT_SOURCE, __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, FMAC_FLAG_OVFL, FMAC_FLAG_SAT, FMAC_FLAG_UNFL, FMAC_FLAG_X1FULL, FMAC_FLAG_YEMPTY, FMAC_GET_X1_SIZE, FMAC_GET_Y_SIZE, FMAC_IT_OVFLIEN, FMAC_IT_RIEN, FMAC_IT_SATIEN, FMAC_IT_UNFLIEN, FMAC_IT_WIEN, FMAC_ReadDataIncrementPtr(), FMAC_ResetInputStateAndDataPointers(), FMAC_ResetOutputStateAndDataPointers(), FMAC_WriteDataIncrementPtr(), __FMAC_HandleTypeDef::GetDataCallback, HAL_FMAC_ERROR_NONE, HAL_FMAC_ERROR_OVFL, HAL_FMAC_ERROR_SAT, HAL_FMAC_ERROR_UNFL, HAL_FMAC_ErrorCallback(), HAL_FMAC_GetDataCallback(), HAL_FMAC_OutputDataReadyCallback(), __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::OutputDataReadyCallback, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::pInputSize, __FMAC_HandleTypeDef::pOutput, and __FMAC_HandleTypeDef::pOutputSize.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
FMAC Exported Functions

Peripheral State and Error functions. More...

Functions

HAL_FMAC_StateTypeDef | HAL_FMAC_GetState (const FMAC_HandleTypeDef *hfmac)
Return the FMAC state.
uint32_t | HAL_FMAC_GetError (const FMAC_HandleTypeDef *hfmac)
Return the FMAC peripheral error.

Detailed Description

Peripheral State and Error functions.

  ==============================================================================
                 ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]  This subsection provides functions allowing to
      (+) Check the FMAC state
      (+) Get error code

Function Documentation

uint32_t HAL_FMAC_GetError ( const FMAC_HandleTypeDef * hfmac )

Return the FMAC peripheral error.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Note:
The returned error is a bit-map combination of possible errors.
Return values:
uint32_t Error bit-map based on FMAC Error code

Definition at line 1543 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCode.

HAL_FMAC_StateTypeDef HAL_FMAC_GetState ( const FMAC_HandleTypeDef * hfmac )

Return the FMAC state.

Parameters:
hfmac pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
Return values:
HAL_FMAC_StateTypeDef FMAC state

Definition at line 1530 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Private Functions

Functions
FMAC Private Functions
FMAC

Functions

static HAL_StatusTypeDef | FMAC_Reset (FMAC_HandleTypeDef *hfmac)
============================================================================== ##### FMAC Private Functions ##### ==============================================================================
static void | FMAC_ResetDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the data pointers of the FMAC unit.
static void | FMAC_ResetInputStateAndDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the input data pointers of the FMAC unit.
static void | FMAC_ResetOutputStateAndDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the output data pointers of the FMAC unit.
static HAL_StatusTypeDef | FMAC_FilterConfig (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess)
Configure the FMAC filter.
static HAL_StatusTypeDef | FMAC_FilterPreload (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
static void | FMAC_WritePreloadDataIncrementPtr (FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
Write data into FMAC internal memory through WDATA and increment input buffer pointer.
static HAL_StatusTypeDef | FMAC_WaitOnStartUntilTimeout (FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
Handle FMAC Function Timeout.
static HAL_StatusTypeDef | FMAC_AppendFilterDataUpdateState (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
Register the new input buffer, update DMA configuration if needed and change the FMAC state.
static HAL_StatusTypeDef | FMAC_ConfigFilterOutputBufferUpdateState (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Register the new output buffer, update DMA configuration if needed and change the FMAC state.
static void | FMAC_ReadDataIncrementPtr (FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
Read available output data until Y EMPTY is set.
static void | FMAC_WriteDataIncrementPtr (FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
Write available input data until X1 FULL is set.
static void | FMAC_DMAHalfGetData (DMA_HandleTypeDef *hdma)
DMA FMAC Input Data process half complete callback.
static void | FMAC_DMAGetData (DMA_HandleTypeDef *hdma)
DMA FMAC Input Data process complete callback.
static void | FMAC_DMAHalfOutputDataReady (DMA_HandleTypeDef *hdma)
DMA FMAC Output Data process half complete callback.
static void | FMAC_DMAOutputDataReady (DMA_HandleTypeDef *hdma)
DMA FMAC Output Data process complete callback.
static void | FMAC_DMAFilterConfig (DMA_HandleTypeDef *hdma)
DMA FMAC Filter Configuration process complete callback.
static void | FMAC_DMAFilterPreload (DMA_HandleTypeDef *hdma)
DMA FMAC Filter Configuration process complete callback.
static void | FMAC_DMAError (DMA_HandleTypeDef *hdma)
DMA FMAC communication error callback.

Function Documentation

static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pInput,
 |  | uint16_t * | pInputSize
 | ) |  | [static]

Register the new input buffer, update DMA configuration if needed and change the FMAC state.

Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pInput | New input vector (additional input data).
pInputSize | Size of the input vector (if all the data can't be written, it will be updated with the number of data read from FMAC).
Return values:
HAL_StatusTypeDef HAL status

Definition at line 2051 of file stm32g4xx_hal_fmac.c.

References FMAC_BUFFER_ACCESS_DMA, FMAC_DMAError(), FMAC_DMAGetData(), FMAC_DMAHalfGetData(), HAL_DMA_Start_IT(), HAL_FMAC_STATE_BUSY_WR, __FMAC_HandleTypeDef::hdmaIn, __FMAC_HandleTypeDef::InputAccess, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::pInputSize, __FMAC_HandleTypeDef::WrState, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_FMAC_AppendFilterData().

static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pOutput,
 |  | uint16_t * | pOutputSize
 | ) |  | [static]

Register the new output buffer, update DMA configuration if needed and change the FMAC state.

Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pOutput | New output vector.
pOutputSize | Size of the output vector (if the vector can't be entirely filled, pOutputSize will be updated with the number of data read from FMAC).
Return values:
HAL_StatusTypeDef HAL status

Definition at line 2095 of file stm32g4xx_hal_fmac.c.

References FMAC_BUFFER_ACCESS_DMA, FMAC_BUFFER_ACCESS_NONE, FMAC_DMAError(), FMAC_DMAHalfOutputDataReady(), FMAC_DMAOutputDataReady(), HAL_DMA_Start_IT(), HAL_FMAC_STATE_BUSY_RD, HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::hdmaOut, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::OutputAccess, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pOutput, __FMAC_HandleTypeDef::pOutputSize, __FMAC_HandleTypeDef::RdState, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_FMAC_ConfigFilterOutputBuffer(), and HAL_FMAC_FilterStart().

static void FMAC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2502 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, HAL_FMAC_ERROR_DMA, HAL_FMAC_ErrorCallback(), HAL_FMAC_STATE_ERROR, and __FMAC_HandleTypeDef::State.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), and FMAC_FilterPreload().

static void FMAC_DMAFilterConfig ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Filter Configuration process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2346 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterConfigCallback, FMAC_DMAError(), HAL_DMA_Start_IT(), HAL_FMAC_ERROR_DMA, HAL_FMAC_ErrorCallback(), HAL_FMAC_FilterConfigCallback(), HAL_FMAC_STATE_ERROR, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_TIMEOUT, __FMAC_HandleTypeDef::hdmaPreload, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, MAX_PRELOAD_INDEX, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by FMAC_FilterConfig().

static void FMAC_DMAFilterPreload ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Filter Configuration process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2421 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCallback, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterPreloadCallback, FMAC_DMAError(), FMAC_FUNC_LOAD_Y, HAL_DMA_Start_IT(), HAL_FMAC_ERROR_DMA, HAL_FMAC_ERROR_NONE, HAL_FMAC_ERROR_TIMEOUT, HAL_FMAC_ErrorCallback(), HAL_FMAC_FilterPreloadCallback(), HAL_FMAC_STATE_ERROR, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_TIMEOUT, __FMAC_HandleTypeDef::hdmaPreload, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, MAX_PRELOAD_INDEX, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by FMAC_FilterPreload().

static void FMAC_DMAGetData ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Input Data process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2289 of file stm32g4xx_hal_fmac.c.

References FMAC_ResetInputStateAndDataPointers(), __FMAC_HandleTypeDef::GetDataCallback, and HAL_FMAC_GetDataCallback().

Referenced by FMAC_AppendFilterDataUpdateState().

static void FMAC_DMAHalfGetData ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Input Data process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2272 of file stm32g4xx_hal_fmac.c.

References HAL_FMAC_HalfGetDataCallback(), and __FMAC_HandleTypeDef::HalfGetDataCallback.

Referenced by FMAC_AppendFilterDataUpdateState().

static void FMAC_DMAHalfOutputDataReady ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Output Data process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2309 of file stm32g4xx_hal_fmac.c.

References HAL_FMAC_HalfOutputDataReadyCallback(), and __FMAC_HandleTypeDef::HalfOutputDataReadyCallback.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState().

static void FMAC_DMAOutputDataReady ( DMA_HandleTypeDef * hdma ) [static]

DMA FMAC Output Data process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2326 of file stm32g4xx_hal_fmac.c.

References FMAC_ResetOutputStateAndDataPointers(), HAL_FMAC_OutputDataReadyCallback(), and __FMAC_HandleTypeDef::OutputDataReadyCallback.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState().

static HAL_StatusTypeDef FMAC_FilterConfig | ( | FMAC_HandleTypeDef * | hfmac,
 |  | FMAC_FilterConfigTypeDef * | pConfig,
 |  | uint8_t | PreloadAccess
 | ) |  | [static]

Configure the FMAC filter.

Note:
The configuration is done according to the parameters specified in the FMAC_FilterConfigTypeDef structure.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pConfig | pointer to a FMAC_FilterConfigTypeDef structure that contains the FMAC configuration information.
PreloadAccess | access mode used for the preload (polling or DMA).
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1643 of file stm32g4xx_hal_fmac.c.

References assert_param, FMAC_FilterConfigTypeDef::Clip, FMAC_FilterConfigTypeDef::CoeffASize, FMAC_FilterConfigTypeDef::CoeffBaseAddress, FMAC_FilterConfigTypeDef::CoeffBSize, FMAC_FilterConfigTypeDef::CoeffBufferSize, __FMAC_HandleTypeDef::ErrorCode, FMAC_FilterConfigTypeDef::Filter, __FMAC_HandleTypeDef::FilterParam, FMAC_BUFFER_ACCESS_DMA, FMAC_BUFFER_ACCESS_IT, FMAC_DMAError(), FMAC_DMAFilterConfig(), FMAC_FUNC_CONVO_FIR, FMAC_FUNC_IIR_DIRECT_FORM_1, FMAC_FUNC_LOAD_X2, FMAC_GET_START_BIT, FMAC_GET_X1_SIZE, FMAC_GET_X2_SIZE, FMAC_GET_Y_SIZE, FMAC_IT_OVFLIEN, FMAC_IT_UNFLIEN, FMAC_THRESHOLD_NO_VALUE, FMAC_WaitOnStartUntilTimeout(), FMAC_WritePreloadDataIncrementPtr(), HAL_DMA_Start_IT(), HAL_FMAC_ERROR_TIMEOUT, HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_TIMEOUT, HAL_FMAC_TIMEOUT_VALUE, HAL_GetTick(), __FMAC_HandleTypeDef::hdmaPreload, __FMAC_HandleTypeDef::InputAccess, FMAC_FilterConfigTypeDef::InputAccess, FMAC_FilterConfigTypeDef::InputBaseAddress, FMAC_FilterConfigTypeDef::InputBufferSize, __FMAC_HandleTypeDef::InputCurrentSize, FMAC_FilterConfigTypeDef::InputThreshold, __FMAC_HandleTypeDef::Instance, IS_FMAC_BUFFER_ACCESS, IS_FMAC_CLIP_STATE, IS_FMAC_FILTER_FUNCTION, IS_FMAC_PARAM_P, IS_FMAC_PARAM_Q, IS_FMAC_PARAM_R, IS_FMAC_THRESHOLD, IS_FMAC_THRESHOLD_APPLICABLE, __FMAC_HandleTypeDef::OutputAccess, FMAC_FilterConfigTypeDef::OutputAccess, FMAC_FilterConfigTypeDef::OutputBaseAddress, FMAC_FilterConfigTypeDef::OutputBufferSize, FMAC_FilterConfigTypeDef::OutputThreshold, FMAC_FilterConfigTypeDef::P, FMAC_FilterConfigTypeDef::pCoeffA, FMAC_FilterConfigTypeDef::pCoeffB, __FMAC_HandleTypeDef::pInput, PRELOAD_ACCESS_POLLING, FMAC_FilterConfigTypeDef::Q, FMAC_FilterConfigTypeDef::R, __FMAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_FMAC_FilterConfig(), and HAL_FMAC_FilterConfig_DMA().

static HAL_StatusTypeDef FMAC_FilterPreload | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t * | pInput,
 |  | uint8_t | InputSize,
 |  | int16_t * | pOutput,
 |  | uint8_t | OutputSize,
 |  | uint8_t | PreloadAccess
 | ) |  | [static]

Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.

Note:
The set(s) of data will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
pInput | Preloading of the first elements of the input buffer (X1). If not needed (no data available when starting), it should be set to NULL.
InputSize | Size of the input vector. As pInput is used for preloading data, it cannot be bigger than the input memory area.
pOutput | [IIR] Preloading of the first elements of the output vector (Y). If not needed, it should be set to NULL.
OutputSize | Size of the output vector. As pOutput is used for preloading data, it cannot be bigger than the output memory area.
PreloadAccess | access mode used for the preload (polling or DMA).
Note:
The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload (each call filling partly the buffers). In case of overflow (too much data provided through all these calls), an error will be returned.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1856 of file stm32g4xx_hal_fmac.c.

References __HAL_FMAC_GET_FLAG, __FMAC_HandleTypeDef::ErrorCode, __FMAC_HandleTypeDef::FilterParam, FMAC_DMAError(), FMAC_DMAFilterPreload(), FMAC_FLAG_OVFL, FMAC_FLAG_SAT, FMAC_FLAG_UNFL, FMAC_FUNC_LOAD_X1, FMAC_FUNC_LOAD_Y, FMAC_GET_START_BIT, FMAC_GET_X1_SIZE, FMAC_GET_Y_SIZE, FMAC_WaitOnStartUntilTimeout(), FMAC_WritePreloadDataIncrementPtr(), HAL_DMA_Start_IT(), HAL_FMAC_ERROR_NONE, HAL_FMAC_ERROR_OVFL, HAL_FMAC_ERROR_SAT, HAL_FMAC_ERROR_TIMEOUT, HAL_FMAC_ERROR_UNFL, HAL_FMAC_STATE_BUSY, HAL_FMAC_STATE_READY, HAL_FMAC_STATE_TIMEOUT, HAL_FMAC_TIMEOUT_VALUE, HAL_GetTick(), __FMAC_HandleTypeDef::hdmaPreload, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::pInput, PRELOAD_ACCESS_POLLING, __FMAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_FMAC_FilterPreload(), and HAL_FMAC_FilterPreload_DMA().

static void FMAC_ReadDataIncrementPtr | ( | FMAC_HandleTypeDef * | hfmac,
 |  | uint16_t | MaxSizeToRead
 | ) |  | [static]

Read available output data until Y EMPTY is set.

Parameters:
hfmac | FMAC handle.
MaxSizeToRead | Maximum number of data to read (this serves as a timeout if FMAC continuously writes into the output buffer).
Return values:
None

Definition at line 2149 of file stm32g4xx_hal_fmac.c.

References FMAC_GET_THRESHOLD_FROM_WM, FMAC_GET_Y_EMPTY_WM, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pOutput, and __FMAC_HandleTypeDef::pOutputSize.

Referenced by HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

static HAL_StatusTypeDef FMAC_Reset ( FMAC_HandleTypeDef * hfmac ) [static]

============================================================================== ##### FMAC Private Functions ##### ==============================================================================

Perform a reset of the FMAC unit.

Parameters:
hfmac FMAC handle.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 1571 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCode, HAL_FMAC_ERROR_NONE, HAL_FMAC_ERROR_TIMEOUT, HAL_FMAC_RESET_TIMEOUT_VALUE, HAL_GetTick(), and __FMAC_HandleTypeDef::Instance.

Referenced by HAL_FMAC_FilterStop(), and HAL_FMAC_Init().

static void FMAC_ResetDataPointers ( FMAC_HandleTypeDef * hfmac ) [static]

Reset the data pointers of the FMAC unit.

Parameters:
hfmac FMAC handle.
Return values:
None

Definition at line 1600 of file stm32g4xx_hal_fmac.c.

References FMAC_ResetInputStateAndDataPointers(), and FMAC_ResetOutputStateAndDataPointers().

Referenced by HAL_FMAC_DeInit(), HAL_FMAC_FilterStop(), and HAL_FMAC_Init().

static void FMAC_ResetInputStateAndDataPointers ( FMAC_HandleTypeDef * hfmac ) [static]

Reset the input data pointers of the FMAC unit.

Parameters:
hfmac FMAC handle.
Return values:
None

Definition at line 1611 of file stm32g4xx_hal_fmac.c.

References HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::pInput, __FMAC_HandleTypeDef::pInputSize, and __FMAC_HandleTypeDef::WrState.

Referenced by FMAC_DMAGetData(), FMAC_ResetDataPointers(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

static void FMAC_ResetOutputStateAndDataPointers ( FMAC_HandleTypeDef * hfmac ) [static]

Reset the output data pointers of the FMAC unit.

Parameters:
hfmac FMAC handle.
Return values:
None

Definition at line 1624 of file stm32g4xx_hal_fmac.c.

References HAL_FMAC_STATE_READY, __FMAC_HandleTypeDef::OutputCurrentSize, __FMAC_HandleTypeDef::pOutput, __FMAC_HandleTypeDef::pOutputSize, and __FMAC_HandleTypeDef::RdState.

Referenced by FMAC_DMAOutputDataReady(), FMAC_ResetDataPointers(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout | ( | FMAC_HandleTypeDef * | hfmac,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle FMAC Function Timeout.

Parameters:
hfmac | FMAC handle.
Tickstart | Tick start value.
Timeout | Timeout duration.
Return values:
HAL_StatusTypeDef HAL status

Definition at line 2027 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::ErrorCode, HAL_FMAC_ERROR_TIMEOUT, HAL_GetTick(), and __FMAC_HandleTypeDef::Instance.

Referenced by FMAC_FilterConfig(), and FMAC_FilterPreload().

static void FMAC_WriteDataIncrementPtr | ( | FMAC_HandleTypeDef * | hfmac,
 |  | uint16_t | MaxSizeToWrite
 | ) |  | [static]

Write available input data until X1 FULL is set.

Parameters:
hfmac | FMAC handle.
MaxSizeToWrite | Maximum number of data to write (this serves as a timeout if FMAC continuously empties the input buffer).
Return values:
None

Definition at line 2213 of file stm32g4xx_hal_fmac.c.

References FMAC_GET_THRESHOLD_FROM_WM, FMAC_GET_X1_FULL_WM, __FMAC_HandleTypeDef::InputCurrentSize, __FMAC_HandleTypeDef::Instance, __FMAC_HandleTypeDef::pInput, and __FMAC_HandleTypeDef::pInputSize.

Referenced by HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

static void FMAC_WritePreloadDataIncrementPtr | ( | FMAC_HandleTypeDef * | hfmac,
 |  | int16_t ** | ppData,
 |  | uint8_t | Size
 | ) |  | [static]

Write data into FMAC internal memory through WDATA and increment input buffer pointer.

Note:
This function is only used with preload functions.
Parameters:
hfmac | pointer to a FMAC_HandleTypeDef structure that contains the configuration information for FMAC module.
ppData | pointer to pointer to the data buffer.
Size | size of the data buffer.
Return values:
None

Definition at line 2008 of file stm32g4xx_hal_fmac.c.

References __FMAC_HandleTypeDef::Instance.

Referenced by FMAC_FilterConfig(), and FMAC_FilterPreload().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Types

Data Structures | Typedefs | Enumerations
FMAC Exported Types
FMAC

Data Structures

struct | __FMAC_HandleTypeDef
FMAC Handle Structure definition. More...
struct | FMAC_FilterConfigTypeDef
FMAC Filter Configuration Structure definition. More...

Typedefs

typedef struct __FMAC_HandleTypeDef | FMAC_HandleTypeDef
FMAC Handle Structure definition.
typedef void(* | pFMAC_CallbackTypeDef )(FMAC_HandleTypeDef *hfmac)
HAL FMAC Callback pointer definition.

Enumerations

enum HAL_FMAC_StateTypeDef {
HAL_FMAC_STATE_RESET = 0x00U, HAL_FMAC_STATE_READY = 0x20U, HAL_FMAC_STATE_BUSY = 0x24U, HAL_FMAC_STATE_BUSY_RD = 0x25U,
HAL_FMAC_STATE_BUSY_WR = 0x26U, HAL_FMAC_STATE_TIMEOUT = 0xA0U, HAL_FMAC_STATE_ERROR = 0xE0U
}
FMAC HAL State Structure definition. More...
enum HAL_FMAC_CallbackIDTypeDef {
HAL_FMAC_ERROR_CB_ID = 0x00U, HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, HAL_FMAC_GET_DATA_CB_ID = 0x02U, HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U,
HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, HAL_FMAC_MSPINIT_CB_ID = 0x07U,
HAL_FMAC_MSPDEINIT_CB_ID = 0x08U
}
FMAC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __FMAC_HandleTypeDef FMAC_HandleTypeDef

FMAC Handle Structure definition.

typedef void(* pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac)

HAL FMAC Callback pointer definition.

pointer to an FMAC callback function

Definition at line 161 of file stm32g4xx_hal_fmac.h.

Enumeration Type Documentation

enum HAL_FMAC_CallbackIDTypeDef

FMAC Callback ID enumeration definition.

Enumerator:
HAL_FMAC_ERROR_CB_ID

FMAC error callback ID

HAL_FMAC_HALF_GET_DATA_CB_ID

FMAC get half data callback ID

HAL_FMAC_GET_DATA_CB_ID

FMAC get data callback ID

HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID

FMAC half output data ready callback ID

HAL_FMAC_OUTPUT_DATA_READY_CB_ID

FMAC output data ready callback ID

HAL_FMAC_FILTER_CONFIG_CB_ID

FMAC filter configuration callback ID

HAL_FMAC_FILTER_PRELOAD_CB_ID

FMAC filter preload callback ID

HAL_FMAC_MSPINIT_CB_ID

FMAC MspInit callback ID

HAL_FMAC_MSPDEINIT_CB_ID

FMAC MspDeInit callback ID

Definition at line 144 of file stm32g4xx_hal_fmac.h.

enum HAL_FMAC_StateTypeDef

FMAC HAL State Structure definition.

Enumerator:
HAL_FMAC_STATE_RESET

FMAC not yet initialized or disabled

HAL_FMAC_STATE_READY

FMAC initialized and ready for use

HAL_FMAC_STATE_BUSY

FMAC internal process is ongoing

HAL_FMAC_STATE_BUSY_RD

FMAC reading configuration is ongoing

HAL_FMAC_STATE_BUSY_WR

FMAC writing configuration is ongoing

HAL_FMAC_STATE_TIMEOUT

FMAC in Timeout state

HAL_FMAC_STATE_ERROR

FMAC in Error state

Definition at line 47 of file stm32g4xx_hal_fmac.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __FMAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__FMAC_HandleTypeDef Struct Reference
FMAC Exported Types

FMAC Handle Structure definition. More...

#include <stm32g4xx_hal_fmac.h>

Data Fields

FMAC_TypeDef * | Instance
uint32_t | FilterParam
uint8_t | InputAccess
uint8_t | OutputAccess
int16_t * | pInput
uint16_t | InputCurrentSize
uint16_t * | pInputSize
int16_t * | pOutput
uint16_t | OutputCurrentSize
uint16_t * | pOutputSize
DMA_HandleTypeDef * hdmaIn
DMA_HandleTypeDef * hdmaOut
DMA_HandleTypeDef * hdmaPreload
void(* | ErrorCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | HalfGetDataCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | GetDataCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | HalfOutputDataReadyCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | OutputDataReadyCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | FilterConfigCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | FilterPreloadCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | MspInitCallback )(struct __FMAC_HandleTypeDef *hfmac)
void(* | MspDeInitCallback )(struct __FMAC_HandleTypeDef *hfmac)
HAL_LockTypeDef | Lock
__IO HAL_FMAC_StateTypeDef | State
__IO HAL_FMAC_StateTypeDef | RdState
__IO HAL_FMAC_StateTypeDef | WrState
__IO uint32_t | ErrorCode

Detailed Description

FMAC Handle Structure definition.

Definition at line 62 of file stm32g4xx_hal_fmac.h.

Field Documentation

void(* __FMAC_HandleTypeDef::ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC error callback

Definition at line 104 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAError(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

__IO uint32_t __FMAC_HandleTypeDef::ErrorCode

FMAC peripheral error code This parameter can be a value of FMAC Error code

Definition at line 135 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAError(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_Reset(), FMAC_WaitOnStartUntilTimeout(), HAL_FMAC_DeInit(), HAL_FMAC_FilterStop(), HAL_FMAC_GetError(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), HAL_FMAC_PollFilterData(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

void(* __FMAC_HandleTypeDef::FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC filter configuration callback

Definition at line 114 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterConfig(), HAL_FMAC_Init(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

uint32_t __FMAC_HandleTypeDef::FilterParam

Filter configuration (operation and parameters). Set to 0 if no valid configuration was applied.

Definition at line 69 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_FMAC_DeInit(), HAL_FMAC_FilterStart(), and HAL_FMAC_Init().

void(* __FMAC_HandleTypeDef::FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC filter preload callback

Definition at line 116 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterPreload(), HAL_FMAC_Init(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

void(* __FMAC_HandleTypeDef::GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC get data callback

Definition at line 108 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAGetData(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

void(* __FMAC_HandleTypeDef::HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC get half data callback

Definition at line 106 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAHalfGetData(), HAL_FMAC_Init(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

void(* __FMAC_HandleTypeDef::HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC half output data ready callback

Definition at line 110 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAHalfOutputDataReady(), HAL_FMAC_Init(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

DMA_HandleTypeDef* __FMAC_HandleTypeDef::hdmaIn

FMAC peripheral input data DMA handle parameters

Definition at line 96 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState().

DMA_HandleTypeDef* __FMAC_HandleTypeDef::hdmaOut

FMAC peripheral output data DMA handle parameters

Definition at line 98 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState().

DMA_HandleTypeDef* __FMAC_HandleTypeDef::hdmaPreload

FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters

Definition at line 100 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), and FMAC_FilterPreload().

uint8_t __FMAC_HandleTypeDef::InputAccess

Access to the input buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of FMAC Buffer Access.

Definition at line 72 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_FilterConfig(), HAL_FMAC_AppendFilterData(), HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), and HAL_FMAC_PollFilterData().

uint16_t __FMAC_HandleTypeDef::InputCurrentSize

Number of the input elements already written into FMAC

Definition at line 82 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_ResetInputStateAndDataPointers(), FMAC_WriteDataIncrementPtr(), HAL_FMAC_AppendFilterData(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

FMAC_TypeDef* __FMAC_HandleTypeDef::Instance

Register base address

Definition at line 67 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_ReadDataIncrementPtr(), FMAC_Reset(), FMAC_WaitOnStartUntilTimeout(), FMAC_WriteDataIncrementPtr(), FMAC_WritePreloadDataIncrementPtr(), HAL_FMAC_DeInit(), HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), and HAL_FMAC_Init().

HAL_LockTypeDef __FMAC_HandleTypeDef::Lock

FMAC locking object

Definition at line 124 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_Init().

void(* __FMAC_HandleTypeDef::MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC Msp DeInit callback

Definition at line 120 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_DeInit(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

void(* __FMAC_HandleTypeDef::MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC Msp Init callback

Definition at line 118 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_Init(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

uint8_t __FMAC_HandleTypeDef::OutputAccess

Access to the output buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of FMAC Buffer Access.

Definition at line 76 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_FilterConfig(), HAL_FMAC_ConfigFilterOutputBuffer(), HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), and HAL_FMAC_PollFilterData().

uint16_t __FMAC_HandleTypeDef::OutputCurrentSize

Number of the output elements already read from FMAC

Definition at line 90 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_ReadDataIncrementPtr(), FMAC_ResetOutputStateAndDataPointers(), HAL_FMAC_ConfigFilterOutputBuffer(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

void(* __FMAC_HandleTypeDef::OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac)

FMAC output data ready callback

Definition at line 112 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAOutputDataReady(), HAL_FMAC_Init(), HAL_FMAC_IRQHandler(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

int16_t* __FMAC_HandleTypeDef::pInput

Pointer to FMAC input data buffer

Definition at line 80 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_ResetInputStateAndDataPointers(), FMAC_WriteDataIncrementPtr(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

uint16_t* __FMAC_HandleTypeDef::pInputSize

Number of input elements to write (memory allocated to pInput). In case of early interruption of the filter operation, its value will be updated.

Definition at line 84 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ResetInputStateAndDataPointers(), FMAC_WriteDataIncrementPtr(), HAL_FMAC_AppendFilterData(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

int16_t* __FMAC_HandleTypeDef::pOutput

Pointer to FMAC output data buffer

Definition at line 88 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_ReadDataIncrementPtr(), FMAC_ResetOutputStateAndDataPointers(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

uint16_t* __FMAC_HandleTypeDef::pOutputSize

Number of output elements to read (memory allocated to pOutput). In case of early interruption of the filter operation, its value will be updated.

Definition at line 92 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_ReadDataIncrementPtr(), FMAC_ResetOutputStateAndDataPointers(), HAL_FMAC_ConfigFilterOutputBuffer(), HAL_FMAC_FilterStop(), HAL_FMAC_IRQHandler(), and HAL_FMAC_PollFilterData().

__IO HAL_FMAC_StateTypeDef __FMAC_HandleTypeDef::RdState

FMAC state related to read operations (access to Y buffer) This parameter can be a value of HAL_FMAC_StateTypeDef

Definition at line 129 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_ResetOutputStateAndDataPointers(), and HAL_FMAC_ConfigFilterOutputBuffer().

__IO HAL_FMAC_StateTypeDef __FMAC_HandleTypeDef::State

FMAC state related to global handle management This parameter can be a value of HAL_FMAC_StateTypeDef

Definition at line 126 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAError(), FMAC_DMAFilterConfig(), FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), HAL_FMAC_DeInit(), HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), HAL_FMAC_GetState(), HAL_FMAC_Init(), HAL_FMAC_PollFilterData(), HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

__IO HAL_FMAC_StateTypeDef __FMAC_HandleTypeDef::WrState

FMAC state related to write operations (access to X1 buffer) This parameter can be a value of HAL_FMAC_StateTypeDef

Definition at line 132 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ResetInputStateAndDataPointers(), and HAL_FMAC_AppendFilterData().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fmac.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC_FilterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FMAC_FilterConfigTypeDef Struct Reference
FMAC Exported Types

FMAC Filter Configuration Structure definition. More...

#include <stm32g4xx_hal_fmac.h>

Data Fields

uint8_t | InputBaseAddress
uint8_t | InputBufferSize
uint32_t | InputThreshold
uint8_t | CoeffBaseAddress
uint8_t | CoeffBufferSize
uint8_t | OutputBaseAddress
uint8_t | OutputBufferSize
uint32_t | OutputThreshold
int16_t * | pCoeffA
uint8_t | CoeffASize
int16_t * | pCoeffB
uint8_t | CoeffBSize
uint8_t | InputAccess
uint8_t | OutputAccess
uint32_t | Clip
uint32_t | Filter
uint8_t | P
uint8_t | Q
uint8_t | R

Detailed Description

FMAC Filter Configuration Structure definition.

Definition at line 168 of file stm32g4xx_hal_fmac.h.

Field Documentation

uint32_t FMAC_FilterConfigTypeDef::Clip

Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping is done when the clipping feature is disabled and saturation is done when the clipping feature is enabled. This parameter can be a value of FMAC Clip State.

Definition at line 225 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::CoeffASize

Size of the coefficient vector A.

Definition at line 209 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::CoeffBaseAddress

Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly.

Definition at line 184 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::CoeffBSize

Size of the coefficient vector B.

Definition at line 215 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::CoeffBufferSize

Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept.

Definition at line 189 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint32_t FMAC_FilterConfigTypeDef::Filter

Filter type. This parameter can be a value of FMAC Functions (filter related values).

Definition at line 230 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::InputAccess

Access to the input buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of FMAC Buffer Access.

Definition at line 217 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::InputBaseAddress

Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). Ignored if InputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly.

Definition at line 170 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::InputBufferSize

Number of 16-bit words allocated to the input buffer (including the optional "headroom"). 0 if a previous configuration should be kept.

Definition at line 175 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint32_t FMAC_FilterConfigTypeDef::InputThreshold

Input threshold: the buffer full flag will be set if the number of free spaces in the buffer is lower than this threshold. This parameter can be a value of FMAC Data Buffer Threshold.

Definition at line 179 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::OutputAccess

Access to the output buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of FMAC Buffer Access.

Definition at line 221 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::OutputBaseAddress

Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly.

Definition at line 192 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::OutputBufferSize

Number of 16-bit words allocated to the output buffer (including the optional "headroom"). 0 if a previous configuration should be kept.

Definition at line 197 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint32_t FMAC_FilterConfigTypeDef::OutputThreshold

Output threshold: the buffer empty flag will be set if the number of unread values in the buffer is lower than this threshold. This parameter can be a value of FMAC Data Buffer Threshold.

Definition at line 201 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::P

Parameter P (vector length, number of filter taps, etc.).

Definition at line 234 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

int16_t* FMAC_FilterConfigTypeDef::pCoeffA

[IIR only] Initialization of the coefficient vector A. If not needed, it should be set to NULL.

Definition at line 206 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

int16_t* FMAC_FilterConfigTypeDef::pCoeffB

Initialization of the coefficient vector B. If not needed (re-use of a previously loaded buffer), it should be set to NULL.

Definition at line 211 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::Q

Parameter Q (vector length, etc.). Ignored if not needed.

Definition at line 236 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

uint8_t FMAC_FilterConfigTypeDef::R

Parameter R (gain, etc.). Ignored if not needed.

Definition at line 238 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_fmac.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Error code

Defines
FMAC Error code
FMAC Exported Constants

Defines

#define | HAL_FMAC_ERROR_NONE 0x00000000U
#define | HAL_FMAC_ERROR_SAT 0x00000001U
#define | HAL_FMAC_ERROR_UNFL 0x00000002U
#define | HAL_FMAC_ERROR_OVFL 0x00000004U
#define | HAL_FMAC_ERROR_DMA 0x00000008U
#define | HAL_FMAC_ERROR_RESET 0x00000010U
#define | HAL_FMAC_ERROR_PARAM 0x00000020U
#define | HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U
#define | HAL_FMAC_ERROR_TIMEOUT 0x00000080U

Define Documentation

#define HAL_FMAC_ERROR_DMA 0x00000008U

DMA error

Definition at line 261 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAError(), FMAC_DMAFilterConfig(), and FMAC_DMAFilterPreload().

#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U

Invalid Callback error

Definition at line 265 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_RegisterCallback(), and HAL_FMAC_UnRegisterCallback().

#define HAL_FMAC_ERROR_NONE 0x00000000U

No error

Definition at line 257 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterPreload(), FMAC_FilterPreload(), FMAC_Reset(), HAL_FMAC_DeInit(), HAL_FMAC_Init(), and HAL_FMAC_IRQHandler().

#define HAL_FMAC_ERROR_OVFL 0x00000004U

Overflow error

Definition at line 260 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define HAL_FMAC_ERROR_PARAM 0x00000020U

Parameter error

Definition at line 263 of file stm32g4xx_hal_fmac.h.

#define HAL_FMAC_ERROR_RESET 0x00000010U

Reset error

Definition at line 262 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_FilterStop(), and HAL_FMAC_Init().

#define HAL_FMAC_ERROR_SAT 0x00000001U

Saturation error

Definition at line 258 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U

Timeout error

Definition at line 267 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterPreload(), FMAC_FilterConfig(), FMAC_FilterPreload(), FMAC_Reset(), FMAC_WaitOnStartUntilTimeout(), and HAL_FMAC_PollFilterData().

#define HAL_FMAC_ERROR_UNFL 0x00000002U

Underflow error

Definition at line 259 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Functions

Defines
FMAC Functions
FMAC Exported Constants

Defines

#define | FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)
#define | FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)
#define | FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)
#define | FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)
#define | FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)

Define Documentation

#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)

Convolution (FIR filter)

Definition at line 279 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)

IIR filter (direct form 1)

Definition at line 280 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)

Load X1 buffer

Definition at line 276 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload().

#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)

Load X2 buffer

Definition at line 277 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)

Load Y buffer

Definition at line 278 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_DMAFilterPreload(), and FMAC_FilterPreload().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Data Buffer Threshold

Defines
FMAC Data Buffer Threshold
FMAC Exported Constants

Defines

#define | FMAC_THRESHOLD_1 0x00000000U
#define | FMAC_THRESHOLD_2 0x01000000U
#define | FMAC_THRESHOLD_4 0x02000000U
#define | FMAC_THRESHOLD_8 0x03000000U
#define | FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU

Detailed Description

Note:
This parameter sets a watermark for buffer full (input) or buffer empty (output).

Define Documentation

#define FMAC_THRESHOLD_1 0x00000000U

Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. Output: Buffer empty flag set if the number of unread values in the buffer is less than 1.

Definition at line 289 of file stm32g4xx_hal_fmac.h.

#define FMAC_THRESHOLD_2 0x01000000U

Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. Output: Buffer empty flag set if the number of unread values in the buffer is less than 2.

Definition at line 293 of file stm32g4xx_hal_fmac.h.

#define FMAC_THRESHOLD_4 0x02000000U

Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. Output: Buffer empty flag set if the number of unread values in the buffer is less than 4.

Definition at line 297 of file stm32g4xx_hal_fmac.h.

#define FMAC_THRESHOLD_8 0x03000000U

Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. Output: Buffer empty flag set if the number of unread values in the buffer is less than 8.

Definition at line 301 of file stm32g4xx_hal_fmac.h.

#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU

The configured threshold value shouldn't be changed

Definition at line 305 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Buffer Access

Defines
FMAC Buffer Access
FMAC Exported Constants

Defines

#define | FMAC_BUFFER_ACCESS_NONE 0x00U
#define | FMAC_BUFFER_ACCESS_DMA 0x01U
#define | FMAC_BUFFER_ACCESS_POLLING 0x02U
#define | FMAC_BUFFER_ACCESS_IT 0x03U

Define Documentation

#define FMAC_BUFFER_ACCESS_DMA 0x01U

Buffer accessed through DMA

Definition at line 314 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_AppendFilterDataUpdateState(), FMAC_ConfigFilterOutputBufferUpdateState(), FMAC_FilterConfig(), and HAL_FMAC_FilterStart().

#define FMAC_BUFFER_ACCESS_IT 0x03U

Buffer accessed through interruptions

Definition at line 316 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig(), HAL_FMAC_FilterStart(), and HAL_FMAC_FilterStop().

#define FMAC_BUFFER_ACCESS_NONE 0x00U

Buffer handled by an external IP (ADC for instance)

Definition at line 313 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_ConfigFilterOutputBufferUpdateState(), HAL_FMAC_AppendFilterData(), and HAL_FMAC_ConfigFilterOutputBuffer().

#define FMAC_BUFFER_ACCESS_POLLING 0x02U

Buffer accessed through polling

Definition at line 315 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_PollFilterData().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Clip State

Defines
FMAC Clip State
FMAC Exported Constants

Defines

#define | FMAC_CLIP_DISABLED 0x00000000U
#define | FMAC_CLIP_ENABLED FMAC_CR_CLIPEN

Define Documentation

#define FMAC_CLIP_DISABLED 0x00000000U

Clipping disabled

Definition at line 324 of file stm32g4xx_hal_fmac.h.

#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN

Clipping enabled

Definition at line 325 of file stm32g4xx_hal_fmac.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC status flags

Defines
FMAC status flags
FMAC Exported Constants

Defines

#define | FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY
#define | FMAC_FLAG_X1FULL FMAC_SR_X1FULL
#define | FMAC_FLAG_OVFL FMAC_SR_OVFL
#define | FMAC_FLAG_UNFL FMAC_SR_UNFL
#define | FMAC_FLAG_SAT FMAC_SR_SAT

Define Documentation

#define FMAC_FLAG_OVFL FMAC_SR_OVFL

Overflow Error Flag

Definition at line 335 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define FMAC_FLAG_SAT FMAC_SR_SAT

Saturation Error Flag (this helps in debugging a filter)

Definition at line 337 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define FMAC_FLAG_UNFL FMAC_SR_UNFL

Underflow Error Flag

Definition at line 336 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL

X1 Buffer Full Flag

Definition at line 334 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_IRQHandler().

#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY

Y Buffer Empty Flag

Definition at line 333 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Interrupts Enable bit

Defines
FMAC Interrupts Enable bit
FMAC Exported Constants

Defines

#define | FMAC_IT_RIEN FMAC_CR_RIEN
#define | FMAC_IT_WIEN FMAC_CR_WIEN
#define | FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN
#define | FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN
#define | FMAC_IT_SATIEN FMAC_CR_SATIEN

Define Documentation

#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN

Overflow Error Interrupt Enable

Definition at line 348 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig(), and HAL_FMAC_IRQHandler().

#define FMAC_IT_RIEN FMAC_CR_RIEN

Read Interrupt Enable

Definition at line 346 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), and HAL_FMAC_IRQHandler().

#define FMAC_IT_SATIEN FMAC_CR_SATIEN

Saturation Error Interrupt Enable (this helps in debugging a filter)

Definition at line 350 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_IRQHandler().

#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN

Underflow Error Interrupt Enable

Definition at line 349 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterConfig(), and HAL_FMAC_IRQHandler().

#define FMAC_IT_WIEN FMAC_CR_WIEN

Write Interrupt Enable

Definition at line 347 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_FilterStart(), HAL_FMAC_FilterStop(), and HAL_FMAC_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported variables

FMAC Exported variables
FMAC
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Macros

Defines
FMAC Exported Macros
FMAC

Defines

#define | __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__)
Reset FMAC handle state.
#define | __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the specified FMAC interrupt.
#define | __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the FMAC interrupt.
#define | __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
Check whether the specified FMAC interrupt occurred or not.
#define | __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Clear specified FMAC interrupt status.
#define | __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified FMAC status flag is set or not.
#define | __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
Clear specified FMAC status flag.
#define | __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
Check whether the specified FMAC interrupt is enabled or not.

Define Documentation

#define __HAL_FMAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* Dummy macro */

Clear specified FMAC status flag.

Dummy macro as no flag can be cleared.

Parameters:
__HANDLE__ | FMAC handle.
__FLAG__ | FMAC flag to clear.
Return values:
None

Definition at line 465 of file stm32g4xx_hal_fmac.h.

#define __HAL_FMAC_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | /* Dummy macro */

Clear specified FMAC interrupt status.

Dummy macro as the interrupt status flags are read-only.

Parameters:
__HANDLE__ | FMAC handle.
__INTERRUPT__ | FMAC interrupt to clear.
Return values:
None

Definition at line 441 of file stm32g4xx_hal_fmac.h.

#define __HAL_FMAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the FMAC interrupt.

Parameters:
__HANDLE__ FMAC handle.
__INTERRUPT__ FMAC Interrupt. This parameter can be any combination of the following values:
  • FMAC_IT_RIEN Read interrupt enable
  • FMAC_IT_WIEN Write interrupt enable
  • FMAC_IT_OVFLIEN Overflow error interrupt enable
  • FMAC_IT_UNFLIEN Underflow error interrupt enable
  • FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
Return values:
None

Definition at line 416 of file stm32g4xx_hal_fmac.h.

#define __HAL_FMAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the specified FMAC interrupt.

Parameters:
__HANDLE__ FMAC handle.
__INTERRUPT__ FMAC Interrupt. This parameter can be any combination of the following values:
  • FMAC_IT_RIEN Read interrupt enable
  • FMAC_IT_WIEN Write interrupt enable
  • FMAC_IT_OVFLIEN Overflow error interrupt enable
  • FMAC_IT_UNFLIEN Underflow error interrupt enable
  • FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
Return values:
None

Definition at line 401 of file stm32g4xx_hal_fmac.h.

#define __HAL_FMAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified FMAC status flag is set or not.

Parameters:
__HANDLE__ FMAC handle.
__FLAG__ FMAC flag to check. This parameter can be any combination of the following values:
  • FMAC_FLAG_YEMPTY Y Buffer Empty Flag
  • FMAC_FLAG_X1FULL X1 Buffer Full Flag
  • FMAC_FLAG_OVFL Overflow Error Flag
  • FMAC_FLAG_UNFL Underflow Error Flag
  • FMAC_FLAG_SAT Saturation error Flag
Return values:
SET (flag is set) or RESET (flag is reset)

Definition at line 455 of file stm32g4xx_hal_fmac.h.

Referenced by FMAC_FilterPreload(), and HAL_FMAC_IRQHandler().

#define __HAL_FMAC_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))

Check whether the specified FMAC interrupt occurred or not.

Parameters:
__HANDLE__ FMAC handle.
__INTERRUPT__ FMAC interrupt to check. This parameter can be any combination of the following values:
  • FMAC_FLAG_YEMPTY Y Buffer Empty Flag
  • FMAC_FLAG_X1FULL X1 Buffer Full Flag
  • FMAC_FLAG_OVFL Overflow Error Flag
  • FMAC_FLAG_UNFL Underflow Error Flag
  • FMAC_FLAG_SAT Saturation Error Flag
Return values:
SET (interrupt occurred) or RESET (interrupt did not occurred)

Definition at line 431 of file stm32g4xx_hal_fmac.h.

#define __HAL_FMAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))

Check whether the specified FMAC interrupt is enabled or not.

Parameters:
__HANDLE__ FMAC handle.
__INTERRUPT__ FMAC interrupt to check. This parameter can be one of the following values:
  • FMAC_IT_RIEN Read interrupt enable
  • FMAC_IT_WIEN Write interrupt enable
  • FMAC_IT_OVFLIEN Overflow error interrupt enable
  • FMAC_IT_UNFLIEN Underflow error interrupt enable
  • FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
Return values:
FlagStatus

Definition at line 479 of file stm32g4xx_hal_fmac.h.

Referenced by HAL_FMAC_IRQHandler().

#define __HAL_FMAC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                           \
                                                      (__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback = NULL;       \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                    } while(0U)

Reset FMAC handle state.

Parameters:
__HANDLE__ FMAC handle.
Return values:
None

Definition at line 380 of file stm32g4xx_hal_fmac.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 68 of file stm32g4xx_hal_gpio.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32g4xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 47 of file stm32g4xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins This parameter can be a value of GPIOEx Alternate function selection

Definition at line 61 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode

Definition at line 52 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins

Definition at line 49 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull

Definition at line 55 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed

Definition at line 58 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO pins

Defines
GPIO pins
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 84 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 85 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 94 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 95 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 96 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 97 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 98 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 99 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 86 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 87 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 88 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 89 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 90 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 91 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 92 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 93 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 100 of file stm32g4xx_hal_gpio.h.

#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */

Definition at line 102 of file stm32g4xx_hal_gpio.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO mode

Defines
GPIO mode
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0x00WX00YZ. More...

Defines

#define | GPIO_MODE_INPUT MODE_INPUT
#define | GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
#define | GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
#define | GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
#define | GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
#define | GPIO_MODE_ANALOG MODE_ANALOG
#define | GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
#define | GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
#define | GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
#define | GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)

Detailed Description

GPIO Configuration Mode Elements values convention: 0x00WX00YZ.

  • W : EXTI trigger detection on 3 bits
  • X : EXTI mode (IT or Event) on 2 bits
  • Y : Output type (Push Pull or Open Drain) on 1 bit
  • Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits

Define Documentation

#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)

Alternate Function Open Drain Mode

Definition at line 120 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)

Alternate Function Push Pull Mode

Definition at line 119 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG MODE_ANALOG

Analog Mode

Definition at line 122 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)

External Event Mode with Falling edge trigger detection

Definition at line 129 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)

External Event Mode with Rising edge trigger detection

Definition at line 128 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 130 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_INPUT MODE_INPUT

Input Floating Mode

Definition at line 116 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)

External Interrupt Mode with Falling edge trigger detection

Definition at line 125 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)

External Interrupt Mode with Rising edge trigger detection

Definition at line 124 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 126 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)

Output Open Drain Mode

Definition at line 118 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)

Output Push Pull Mode

Definition at line 117 of file stm32g4xx_hal_gpio.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO speed

Defines
GPIO speed
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH (0x00000002U)

range 25 MHz to 50 MHz, please refer to the product datasheet

Definition at line 141 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define GPIO_SPEED_FREQ_LOW (0x00000000U)

range up to 5 MHz, please refer to the product datasheet

Definition at line 139 of file stm32g4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U)

range 5 MHz to 25 MHz, please refer to the product datasheet

Definition at line 140 of file stm32g4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)

range 50 MHz to 120 MHz, please refer to the product datasheet

Definition at line 142 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO pull

Defines
GPIO pull
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL (0x00000000U)

No Pull-up or Pull-down activation

Definition at line 151 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

#define GPIO_PULLDOWN (0x00000002U)

Pull-down activation

Definition at line 153 of file stm32g4xx_hal_gpio.h.

#define GPIO_PULLUP (0x00000001U)

Pull-up activation

Definition at line 152 of file stm32g4xx_hal_gpio.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending flags.

Parameters:
__EXTI_LINE__ specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 181 of file stm32g4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 197 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generate a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 205 of file stm32g4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 173 of file stm32g4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 189 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit. More...

Defines

#define | GPIO_NUMBER (16U)
#define | GPIO_MODE_Pos 0U
#define | GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define | MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define | MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define | MODE_AF (0x2UL << GPIO_MODE_Pos)
#define | MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define | OUTPUT_TYPE_Pos 4U
#define | OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define | OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define | OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define | EXTI_MODE_Pos 16U
#define | EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define | EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define | EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define | TRIGGER_MODE_Pos 20U
#define | TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define | TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define | TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

Define Documentation

#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)

Definition at line 228 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_IT (0x1UL << EXTI_MODE_Pos)

Definition at line 227 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)

Definition at line 226 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_MODE_Pos 16U

Definition at line 225 of file stm32g4xx_hal_gpio.h.

#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)

Definition at line 216 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_Pos 0U

Definition at line 215 of file stm32g4xx_hal_gpio.h.

#define GPIO_NUMBER (16U)

Definition at line 129 of file stm32g4xx_hal_gpio.c.

Referenced by HAL_GPIO_TogglePin().

#define MODE_AF (0x2UL << GPIO_MODE_Pos)

Definition at line 219 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)

Definition at line 220 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)

Definition at line 217 of file stm32g4xx_hal_gpio.h.

#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)

Definition at line 218 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)

Definition at line 224 of file stm32g4xx_hal_gpio.h.

#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)

Definition at line 223 of file stm32g4xx_hal_gpio.h.

#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)

Definition at line 222 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define OUTPUT_TYPE_Pos 4U

Definition at line 221 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)

Definition at line 232 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)

Definition at line 230 of file stm32g4xx_hal_gpio.h.

#define TRIGGER_MODE_Pos 20U

Definition at line 229 of file stm32g4xx_hal_gpio.h.

#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)

Definition at line 231 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Define Documentation

#define IS_GPIO_MODE ( __MODE__ )
Value:
(((__MODE__) == GPIO_MODE_INPUT)              ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG))

Definition at line 245 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ )
Value:
((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))

Definition at line 242 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 240 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( __PULL__ )
Value:
(((__PULL__) == GPIO_NOPULL)   ||\
                                     ((__PULL__) == GPIO_PULLUP)   || \
                                     ((__PULL__) == GPIO_PULLDOWN))

Definition at line 263 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( __SPEED__ )
Value:
(((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 258 of file stm32g4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initialize the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Pin | specifies the port bit to be written. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 292 of file stm32g4xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Init | pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 162 of file stm32g4xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_EVT, EXTI_IT, EXTI_MODE, GPIO_GET_INDEX, GPIO_MODE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, MODE_AF, MODE_ANALOG, MODE_OUTPUT, OUTPUT_TYPE, OUTPUT_TYPE_Pos, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, GPIO_InitTypeDef::Speed, TRIGGER_FALLING, and TRIGGER_RISING.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

IO operation functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

IO operation functions.

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 505 of file stm32g4xx_hal_gpio.c.

References UNUSED.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 490 of file stm32g4xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Lock GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Pin | specifies the port bits to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 455 of file stm32g4xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Read the specified input port pin.

Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Pin | specifies the port bit to read. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 373 of file stm32g4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggle the specified GPIO pin.

Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Pin | specifies the pin to be toggled. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 430 of file stm32g4xx_hal_gpio.c.

References assert_param, GPIO_NUMBER, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Set or clear the selected data port bit.

Note:
This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx | where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
GPIO_Pin | specifies the port bit to be written. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
PinState specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 407 of file stm32g4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIOEx Alternate function selection

Defines
GPIOEx Alternate function selection
GPIOEx Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
#define | GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
#define | GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
#define | GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
#define | GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
#define | GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
#define | GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define | GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define | GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
#define | GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
#define | GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
#define | GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
#define | GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
#define | GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
#define | GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
#define | GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
#define | GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
#define | GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
#define | GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
#define | GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
#define | GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
#define | GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
#define | GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
#define | GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define | GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
#define | GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
#define | GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define | GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
#define | GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define | GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define | GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
#define | GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define | GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
#define | GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
#define | GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)

Define Documentation

#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 54 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 53 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 55 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */

Definition at line 56 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */

Definition at line 234 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */

Definition at line 236 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */

AF 10 selection.

Definition at line 230 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */

Definition at line 231 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */

Definition at line 232 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */

Definition at line 233 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */

Definition at line 235 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */

AF 11 selection.

Definition at line 244 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */

Definition at line 251 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */

Definition at line 248 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */

Definition at line 249 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 250 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */

AF 12 selection.

Definition at line 256 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */

Definition at line 266 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */

Definition at line 257 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */

Definition at line 258 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */

Definition at line 259 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */

AF 13 selection.

Definition at line 274 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */

Definition at line 282 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */

Definition at line 280 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */

AF 14 selection.

Definition at line 279 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */

Definition at line 283 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */

Definition at line 281 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 291 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */

Definition at line 70 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */

Definition at line 69 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */

Definition at line 68 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */

Definition at line 65 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */

Definition at line 66 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */

Definition at line 67 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */

AF 1 selection.

Definition at line 61 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */

Definition at line 96 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */

Definition at line 95 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */

AF 2 selection.

Definition at line 75 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */

Definition at line 83 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */

Definition at line 89 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */

Definition at line 84 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */

Definition at line 90 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */

Definition at line 88 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */

Definition at line 76 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */

Definition at line 77 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */

Definition at line 78 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */

Definition at line 82 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */

Definition at line 118 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */

Definition at line 106 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */

Definition at line 117 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */

AF 3 selection.

Definition at line 101 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */

Definition at line 116 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */

Definition at line 105 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */

Definition at line 128 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */

Definition at line 129 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */

Definition at line 130 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */

AF 4 selection.

Definition at line 123 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */

Definition at line 125 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */

Definition at line 126 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */

Definition at line 124 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 127 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */

Definition at line 150 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */

Definition at line 143 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */

AF 5 selection.

Definition at line 138 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */

Definition at line 139 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */

Definition at line 144 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 145 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */

Definition at line 146 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */

Definition at line 169 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */

Definition at line 168 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */

AF 6 selection.

Definition at line 155 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */

Definition at line 156 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */

Definition at line 157 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */

Definition at line 165 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */

Definition at line 166 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */

Definition at line 161 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */

Definition at line 167 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */

AF 7 selection.

Definition at line 174 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */

Definition at line 175 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */

Definition at line 176 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */

AF 8 selection.

Definition at line 190 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */

Definition at line 191 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */

Definition at line 192 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */

Definition at line 193 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */

Definition at line 203 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */

Definition at line 207 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */

Definition at line 208 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */

Definition at line 222 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */

AF 9 selection.

Definition at line 216 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */

Definition at line 218 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */

Definition at line 221 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */

Definition at line 219 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */

Definition at line 217 of file stm32g4xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 220 of file stm32g4xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0F)

Definition at line 293 of file stm32g4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIOEx Get Port Index

Defines
GPIOEx Get Port Index
GPIOEx Exported Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0UL :\
                                      ((__GPIOx__) == (GPIOB))? 1UL :\
                                      ((__GPIOx__) == (GPIOC))? 2UL :\
                                      ((__GPIOx__) == (GPIOD))? 3UL :\
                                      ((__GPIOx__) == (GPIOE))? 4UL :\
                                      ((__GPIOx__) == (GPIOF))? 5UL : 6UL)

Definition at line 311 of file stm32g4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SLAVE_ADDR_SHIFT 7U
#define | SLAVE_ADDR_MSK 0x06U
#define | I2C_STATE_MSK
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX
#define | I2C_STATE_MASTER_BUSY_RX
#define | I2C_STATE_SLAVE_BUSY_TX
#define | I2C_STATE_SLAVE_BUSY_RX
#define | I2C_STATE_MEM_BUSY_TX
#define | I2C_STATE_MEM_BUSY_RX
#define | I2C_XFER_TX_IT (uint16_t)(0x0001U)
#define | I2C_XFER_RX_IT (uint16_t)(0x0002U)
#define | I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)
#define | I2C_XFER_ERROR_IT (uint16_t)(0x0010U)
#define | I2C_XFER_CPLT_IT (uint16_t)(0x0020U)
#define | I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 398 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_STATE_MASTER_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 367 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MASTER_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 364 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MEM_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 379 of file stm32g4xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 376 of file stm32g4xx_hal_i2c.c.

#define I2C_STATE_MSK
Value:
((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 358 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 362 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_TreatErrorCallback().

#define I2C_STATE_SLAVE_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 373 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_STATE_SLAVE_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 370 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 343 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 344 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 345 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 351 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 346 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 347 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_IsErrorOccurred().

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 348 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 349 of file stm32g4xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 350 of file stm32g4xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U)

Bit definition to manage only STOP evenement

Definition at line 394 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Mem_ISR_DMA().

#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U)

Bit definition to manage addition of global Error and NACK treatment

Definition at line 392 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), and I2C_Mem_ISR_DMA().

#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)

Bit field can be combinated with I2C_XFER_TX_IT and I2C_XFER_RX_IT

Definition at line 389 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)

Bit definition to manage only Reload of NBYTE

Definition at line 395 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (uint16_t)(0x0002U)

Bit field can be combinated with I2C_XFER_LISTEN_IT

Definition at line 387 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Mem_ISR_IT().

#define I2C_XFER_TX_IT (uint16_t)(0x0001U)

Bit field can be combinated with I2C_XFER_LISTEN_IT

Definition at line 385 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define MAX_NBYTE_SIZE 255U

Definition at line 353 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define SLAVE_ADDR_MSK 0x06U

Definition at line 355 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SLAVE_ADDR_SHIFT 7U

Definition at line 354 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 342 of file stm32g4xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Mem_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Mem_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsErrorOccurred (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles errors detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_TreatErrorCallback (I2C_HandleTypeDef *hi2c)
I2C Error callback treatment.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.

Function Documentation

static void I2C_ConvertOtherXferOptions ( I2C_HandleTypeDef * hi2c ) [static]

Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 7444 of file stm32g4xx_hal_i2c.c.

References I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_OTHER_AND_LAST_FRAME, I2C_OTHER_FRAME, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

static void I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 7381 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 6896 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_TreatErrorCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6877 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6797 of file stm32g4xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6717 of file stm32g4xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6848 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::hdmarx, I2C_GET_DMA_REMAIN_DATA, I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6768 of file stm32g4xx_hal_i2c.c.

References I2C_FIRST_FRAME, I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 7290 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Mem_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6696 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsErrorOccurred | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles errors detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 7122 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_OVR, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_BUSY, I2C_FLAG_OVR, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, I2C_TIMEOUT_STOPF, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5895 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SLAVE_ADDR_MSK, SLAVE_ADDR_SHIFT, __I2C_HandleTypeDef::State, and UNUSED.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 6527 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_GetState(), HAL_DMA_STATE_READY, HAL_I2C_ERROR_AF, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_TreatErrorCallback(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 6476 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 6117 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, UNUSED, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

static void I2C_ITMasterSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5990 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 6260 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_IT_NACKI, I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6043 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5359 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4925 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Master_Transmit_IT().

static HAL_StatusTypeDef I2C_Mem_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5499 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GENERATE_START_READ, I2C_GENERATE_START_WRITE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Mem_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5076 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GENERATE_START_READ, I2C_GENERATE_START_WRITE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5846 of file stm32g4xx_hal_i2c.c.

References I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5791 of file stm32g4xx_hal_i2c.c.

References I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5647 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5219 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 7263 of file stm32g4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static void I2C_TreatErrorCallback ( I2C_HandleTypeDef * hi2c ) [static]

I2C Error callback treatment.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6658 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, I2C_STATE_NONE, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMAAbort(), and I2C_ITError().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The actual Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6926 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_IsErrorOccurred(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 7045 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsErrorOccurred(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 7007 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsErrorOccurred(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6966 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsErrorOccurred(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 650 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 535 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_AbortCpltCallback(), HAL_I2C_AddrCallback(), HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspInitCallback, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 712 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_DeInit(), and HAL_I2C_UnRegisterCallback().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 696 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), and HAL_I2C_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | pI2C_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 974 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_RegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID,
 |  | pI2C_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2C Callback To be used instead of the weak predefined callback.

Note:
The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 746 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback ( I2C_HandleTypeDef * hi2c )

UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 1009 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_AddrCallback(), HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.

Note:
The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 872 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_ErrorCallback(), HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_ListenCpltCallback(), HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MspDeInit(), HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MspInit(), HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()
        (++) HAL_I2C_Master_Seq_Transmit_IT()
        (++) HAL_I2C_Master_Seq_Receive_IT()
        (++) HAL_I2C_Slave_Seq_Transmit_IT()
        (++) HAL_I2C_Slave_Seq_Receive_IT()
        (++) HAL_I2C_EnableListen_IT()
        (++) HAL_I2C_DisableListen_IT()
        (++) HAL_I2C_Master_Abort_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()
        (++) HAL_I2C_Master_Seq_Transmit_DMA()
        (++) HAL_I2C_Master_Seq_Receive_DMA()
        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
        (++) HAL_I2C_Slave_Seq_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_AddrCallback()
        (++) HAL_I2C_ListenCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 4529 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 4505 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3251 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 4562 of file stm32g4xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1260 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2121 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1773 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3775 of file stm32g4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3688 of file stm32g4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3491 of file stm32g4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3377 of file stm32g4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1119 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1958 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1683 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2648 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 3106 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_DMA(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2873 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_IT(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2511 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2960 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_DMA(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2785 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_IT(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1553 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2402 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1906 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4325 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4225 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4041 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3941 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1378 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_NOSTRETCH_ENABLE, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2266 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_NOSTRETCH_ENABLE, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1842 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_NOSTRETCH_ENABLE, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4842 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C Transfer Direction Master Point of View
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 4760 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4643 of file stm32g4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4826 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4624 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4778 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4711 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4695 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4810 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4794 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4742 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4726 of file stm32g4xx_hal_i2c.c.

References UNUSED.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (const I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (const I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (const I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( const I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 4900 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( const I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 4889 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( const I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 4877 of file stm32g4xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32g4xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 47 of file stm32g4xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 56 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 59 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 69 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 72 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 53 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 62 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected. This parameter can be a value of I2C Own Address2 Masks

Definition at line 65 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 49 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_i2c.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U
}

Detailed Description

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 Peripheral initialization status
0 : Reset (peripheral not initialized)
1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (peripheral in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (peripheral busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

Definition at line 108 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 146 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 166 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 165 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 164 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 168 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)

DMA Parameter Error

Definition at line 171 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 173 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterAddrCallback(), and HAL_I2C_UnRegisterCallback().

#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 175 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 163 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 167 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 170 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 169 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsErrorOccurred(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs | Enumerations
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
typedef void(* pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an I2C Address Match callback function

Definition at line 280 of file stm32g4xx_hal_i2c.h.

typedef void(* pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c)

HAL I2C Callback pointer definition.

pointer to an I2C callback function

Definition at line 278 of file stm32g4xx_hal_i2c.h.

Enumeration Type Documentation

enum HAL_I2C_CallbackIDTypeDef

HAL I2C Callback ID enumeration definition.

Enumerator:
HAL_I2C_MASTER_TX_COMPLETE_CB_ID

I2C Master Tx Transfer completed callback ID

HAL_I2C_MASTER_RX_COMPLETE_CB_ID

I2C Master Rx Transfer completed callback ID

HAL_I2C_SLAVE_TX_COMPLETE_CB_ID

I2C Slave Tx Transfer completed callback ID

HAL_I2C_SLAVE_RX_COMPLETE_CB_ID

I2C Slave Rx Transfer completed callback ID

HAL_I2C_LISTEN_COMPLETE_CB_ID

I2C Listen Complete callback ID

HAL_I2C_MEM_TX_COMPLETE_CB_ID

I2C Memory Tx Transfer callback ID

HAL_I2C_MEM_RX_COMPLETE_CB_ID

I2C Memory Rx Transfer completed callback ID

HAL_I2C_ERROR_CB_ID

I2C Error callback ID

HAL_I2C_ABORT_CB_ID

I2C Abort callback ID

HAL_I2C_MSPINIT_CB_ID

I2C Msp Init callback ID

HAL_I2C_MSPDEINIT_CB_ID

I2C Msp DeInit callback ID

Definition at line 258 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32g4xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount
__IO uint32_t | Devaddress
__IO uint32_t | Memaddress
void(* | MasterTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MasterRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ListenCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ErrorCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AbortCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AddrCallback )(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MspDeInitCallback )(struct __I2C_HandleTypeDef *hi2c)

Detailed Description

Definition at line 184 of file stm32g4xx_hal_i2c.h.

Field Documentation

void(* __I2C_HandleTypeDef::AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Abort callback

Definition at line 240 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void(* __I2C_HandleTypeDef::AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

I2C Slave Address Match callback

Definition at line 243 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 217 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::Devaddress

I2C Target device address

Definition at line 219 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

void(* __I2C_HandleTypeDef::ErrorCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Error callback

Definition at line 238 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 215 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 206 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 204 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 188 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 186 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

void(* __I2C_HandleTypeDef::ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Listen Complete callback

Definition at line 232 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 209 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

void(* __I2C_HandleTypeDef::MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Rx Transfer completed callback

Definition at line 226 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Tx Transfer completed callback

Definition at line 224 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

__IO uint32_t __I2C_HandleTypeDef::Memaddress

I2C Target memory address

Definition at line 221 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

void(* __I2C_HandleTypeDef::MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Rx Transfer completed callback

Definition at line 236 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void(* __I2C_HandleTypeDef::MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Tx Transfer completed callback

Definition at line 234 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 213 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

void(* __I2C_HandleTypeDef::MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp DeInit callback

Definition at line 248 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

void(* __I2C_HandleTypeDef::MspInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp Init callback

Definition at line 246 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 190 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 199 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Slave_ISR_DMA(), and I2C_TreatErrorCallback().

void(* __I2C_HandleTypeDef::SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Rx Transfer completed callback

Definition at line 230 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Tx Transfer completed callback

Definition at line 228 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 211 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_IsErrorOccurred(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_TreatErrorCallback(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 194 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 201 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 196 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 192 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_i2c.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 304 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 302 of file stm32g4xx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 301 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 305 of file stm32g4xx_hal_i2c.h.

#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 306 of file stm32g4xx_hal_i2c.h.

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 303 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Definition at line 312 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

#define I2C_OTHER_FRAME (0x000000AAU)

Definition at line 311 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 321 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 320 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 329 of file stm32g4xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 330 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 339 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 340 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 341 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 342 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 343 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 344 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 345 of file stm32g4xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 338 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 353 of file stm32g4xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 354 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 362 of file stm32g4xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 363 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 372 of file stm32g4xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 371 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Transfer Direction Master Point of View

Defines
I2C Transfer Direction Master Point of View
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 381 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 380 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 390 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 389 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 391 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), and I2C_RequestMemoryRead().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 401 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 402 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 400 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 399 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 417 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 413 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 416 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 418 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 415 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 414 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 419 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 430 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 431 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 440 of file stm32g4xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 436 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 435 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 441 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), and I2C_IsErrorOccurred().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 442 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 437 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 438 of file stm32g4xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 429 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 432 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 433 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 434 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 439 of file stm32g4xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 427 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 428 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? \
                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 564 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 578 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 501 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 572 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 485 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 584 of file stm32g4xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__HANDLE__)->Instance->ISR) & \
                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 544 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR1 & \
                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 517 of file stm32g4xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                             \
                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                                  } while(0)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 462 of file stm32g4xx_hal_i2c.h.

#define I2C_FLAG_MASK (0x0001FFFFU)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 543 of file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__)
#define | I2C_GET_ADDR_MATCH(__HANDLE__)
#define | I2C_GET_DIR(__HANDLE__)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Define Documentation

#define I2C_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) |
Value:
((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

Definition at line 809 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 811 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
                                                                (~I2C_CR2_RD_WRN)) : \
                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START) | \
                                                                 (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))

Definition at line 801 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ )
Value:
((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
                                                              >> 16U))

Definition at line 786 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ )
Value:
((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
                                                             >> 16U))

Definition at line 788 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_DMA_REMAIN_DATA ( __HANDLE__ ) __HAL_DMA_GET_COUNTER(__HANDLE__)

Definition at line 408 of file stm32g4xx_hal_i2c.c.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))

Definition at line 791 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

Definition at line 792 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 790 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 799 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ )
Value:
((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
                                                                         (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 797 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR2 &= \
                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
                                                                          I2C_CR2_RD_WRN)))

Definition at line 781 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsErrorOccurred(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 737 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 740 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 752 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 758 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 755 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 794 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 795 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 743 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 770 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_OTHER_FRAME)     || \
                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

Definition at line 778 of file stm32g4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 761 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 765 of file stm32g4xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Filter Mode Functions

Functions
Filter Mode Functions
I2C Extended Exported Functions

Filter Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.

Detailed Description

Filter Mode Functions.

 ===============================================================================
                      ##### Filter Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 96 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 140 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WakeUp Mode Functions

Functions
WakeUp Mode Functions
I2C Extended Exported Functions

WakeUp Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).

Detailed Description

WakeUp Mode Functions.

 ===============================================================================
                      ##### WakeUp Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 247 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 208 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Fast Mode Plus Functions

Functions
Fast Mode Plus Functions
I2C Extended Exported Functions

Fast Mode Plus Functions. More...

Functions

void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Fast Mode Plus Functions.

 ===============================================================================
                      ##### Fast Mode Plus Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Fast Mode Plus

Function Documentation

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 343 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 314 of file stm32g4xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 48 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE 0x00000000U

Definition at line 47 of file stm32g4xx_hal_i2c_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED)

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 61 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 62 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 63 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED)

Fast Mode Plus I2C4 not supported

Definition at line 67 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 57 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 58 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 59 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 60 of file stm32g4xx_hal_i2c_ex.h.

#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 56 of file stm32g4xx_hal_i2c_ex.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Exported Macros

I2C Extended Exported Macros
I2CEx
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
I2CEx
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
I2CEx

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 136 of file stm32g4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 139 of file stm32g4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))

Definition at line 141 of file stm32g4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
I2CEx
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2S

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1731 of file stm32g4xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1687 of file stm32g4xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1713 of file stm32g4xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback(), and __I2S_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1642 of file stm32g4xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1669 of file stm32g4xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback(), and __I2S_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_Receive_IT ( I2S_HandleTypeDef * hi2s ) [static]

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1786 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

static void I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1758 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag | Flag checked
State | Value of the flag expected
Timeout | Duration of the timeout
Return values:
HAL status

Definition at line 1817 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity

     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 429 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::MspDeInitCallback, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 264 of file stm32g4xx_hal_i2s.c.

References assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_PRESCALER, HAL_I2S_ErrorCallback(), HAL_I2S_MspInit(), HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), HAL_RCCEx_GetPeriphCLKFreq(), I2S_AUDIOFREQ_DEFAULT, I2S_DATAFORMAT_16B, I2S_MCLKOUTPUT_ENABLE, I2S_STANDARD_LSB, I2S_STANDARD_PCM_LONG, I2S_STANDARD_PCM_SHORT, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, __I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::MspInitCallback, RCC_PERIPHCLK_I2S, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, I2S_InitTypeDef::Standard, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 489 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_DeInit(), and HAL_I2S_UnRegisterCallback().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 473 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), and HAL_I2S_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2S_RegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID,
 |  | pI2S_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2S Callback To be used instead of the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 509 of file stm32g4xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_UnRegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 608 of file stm32g4xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_ErrorCallback(), HAL_I2S_MspDeInit(), HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MspInit(), HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1279 of file stm32g4xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1311 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Stops the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1350 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_DISABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_I2S_ERROR_BUSY_LINE_RX, HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, __I2S_HandleTypeDef::hdmatx, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_MODE_MASTER_RX, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_TIMEOUT_FLAG, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, and __I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1575 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1450 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_CHECK_FLAG, I2S_CHECK_IT_SOURCE, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2S_Receive_IT(), I2S_Transmit_IT(), __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 871 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_MODE_MASTER_RX, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1190 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronization between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 1035 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_RXNE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, and __I2S_HandleTypeDef::State.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1559 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), and I2S_Receive_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1543 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 752 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ERROR_UDR, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Transmit data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1099 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 969 of file stm32g4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_TXE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1527 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), and I2S_Transmit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1511 of file stm32g4xx_hal_i2s.c.

References UNUSED.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1621 of file stm32g4xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1610 of file stm32g4xx_hal_i2s.c.

References __I2S_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Types

Data Structures | Typedefs | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U,
HAL_I2S_ERROR_CB_ID = 0x06U, HAL_I2S_MSPINIT_CB_ID = 0x07U, HAL_I2S_MSPDEINIT_CB_ID = 0x08U
}
HAL I2S Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __I2S_HandleTypeDef I2S_HandleTypeDef

I2S handle Structure definition.

typedef void(* pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s)

HAL I2S Callback pointer definition.

pointer to an I2S callback function

Definition at line 153 of file stm32g4xx_hal_i2s.h.

Enumeration Type Documentation

enum HAL_I2S_CallbackIDTypeDef

HAL I2S Callback ID enumeration definition.

Enumerator:
HAL_I2S_TX_COMPLETE_CB_ID

I2S Tx Completed callback ID

HAL_I2S_RX_COMPLETE_CB_ID

I2S Rx Completed callback ID

HAL_I2S_TX_HALF_COMPLETE_CB_ID

I2S Tx Half Completed callback ID

HAL_I2S_RX_HALF_COMPLETE_CB_ID

I2S Rx Half Completed callback ID

HAL_I2S_ERROR_CB_ID

I2S Error callback ID

HAL_I2S_MSPINIT_CB_ID

I2S Msp Init callback ID

HAL_I2S_MSPDEINIT_CB_ID

I2S Msp DeInit callback ID

Definition at line 138 of file stm32g4xx_hal_i2s.h.

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 71 of file stm32g4xx_hal_i2s.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32g4xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL

Detailed Description

I2S Init structure definition.

Definition at line 47 of file stm32g4xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 61 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 64 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 55 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S MCLK Output

Definition at line 58 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 49 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 52 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_i2s.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32g4xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | TxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | ErrorCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspInitCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspDeInitCallback )(struct __I2S_HandleTypeDef *hi2s)

Detailed Description

I2S handle Structure definition.

Definition at line 86 of file stm32g4xx_hal_i2s.h.

Field Documentation

void(* __I2S_HandleTypeDef::ErrorCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Error callback

Definition at line 127 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

__IO uint32_t __I2S_HandleTypeDef::ErrorCode

I2S Error code This parameter can be a value of I2S Error

Definition at line 119 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAStop(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmarx

I2S Rx DMA handle parameters

Definition at line 113 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmatx

I2S Tx DMA handle parameters

Definition at line 111 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef __I2S_HandleTypeDef::Init

I2S communication parameters

Definition at line 93 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Init().

SPI_TypeDef* __I2S_HandleTypeDef::Instance

I2S registers base address

Definition at line 91 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), and I2S_Transmit_IT().

__IO HAL_LockTypeDef __I2S_HandleTypeDef::Lock

I2S locking object

Definition at line 115 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

void(* __I2S_HandleTypeDef::MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp DeInit callback

Definition at line 129 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

void(* __I2S_HandleTypeDef::MspInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp Init callback

Definition at line 128 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

uint16_t* __I2S_HandleTypeDef::pRxBuffPtr

Pointer to I2S Rx transfer buffer

Definition at line 101 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

uint16_t* __I2S_HandleTypeDef::pTxBuffPtr

Pointer to I2S Tx transfer buffer

Definition at line 95 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

void(* __I2S_HandleTypeDef::RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Completed callback

Definition at line 124 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), and I2S_Receive_IT().

void(* __I2S_HandleTypeDef::RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Half Completed callback

Definition at line 126 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

__IO uint16_t __I2S_HandleTypeDef::RxXferCount

I2S Rx transfer counter (This field is initialized at the same value as transfer size at the beginning of the transfer and decremented when a sample is received NbSamplesReceived = RxBufferSize-RxBufferCount)

Definition at line 105 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), I2S_DMAError(), I2S_DMARxCplt(), and I2S_Receive_IT().

__IO uint16_t __I2S_HandleTypeDef::RxXferSize

I2S Rx transfer size

Definition at line 103 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

__IO HAL_I2S_StateTypeDef __I2S_HandleTypeDef::State

I2S communication state

Definition at line 117 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_WaitFlagStateUntilTimeout().

void(* __I2S_HandleTypeDef::TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Completed callback

Definition at line 123 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), and I2S_Transmit_IT().

void(* __I2S_HandleTypeDef::TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Half Completed callback

Definition at line 125 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

__IO uint16_t __I2S_HandleTypeDef::TxXferCount

I2S Tx transfer Counter

Definition at line 99 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMATxCplt(), and I2S_Transmit_IT().

__IO uint16_t __I2S_HandleTypeDef::TxXferSize

I2S Tx transfer size

Definition at line 97 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_i2s.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Error

Defines
I2S Error
I2S Exported Constants

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010U)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)
#define | HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)

Define Documentation

#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)

Busy Rx Line error

Definition at line 176 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define HAL_I2S_ERROR_DMA (0x00000008U)

DMA transfer error

Definition at line 171 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), and I2S_DMAError().

#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)

Invalid Callback error

Definition at line 174 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

#define HAL_I2S_ERROR_NONE (0x00000000U)

No error

Definition at line 167 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_OVR (0x00000002U)

OVR error

Definition at line 169 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define HAL_I2S_ERROR_PRESCALER (0x00000010U)

Prescaler Calculation error

Definition at line 172 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define HAL_I2S_ERROR_TIMEOUT (0x00000001U)

Timeout error

Definition at line 168 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UDR (0x00000004U)

UDR error

Definition at line 170 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))

Define Documentation

#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))

Definition at line 187 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Definition at line 186 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Definition at line 185 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define I2S_MODE_SLAVE_TX (0x00000000U)

Definition at line 184 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define | I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))

Define Documentation

#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

Definition at line 197 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

Definition at line 196 of file stm32g4xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))

Definition at line 199 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))

Definition at line 198 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PHILIPS (0x00000000U)

Definition at line 195 of file stm32g4xx_hal_i2s.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define | I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))

Define Documentation

#define I2S_DATAFORMAT_16B (0x00000000U)

Definition at line 207 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Definition at line 208 of file stm32g4xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))

Definition at line 209 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))

Definition at line 210 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S MCLK Output

Defines
I2S MCLK Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Definition at line 219 of file stm32g4xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Definition at line 218 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)

Define Documentation

#define I2S_AUDIOFREQ_11K (11025U)

Definition at line 234 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K (16000U)

Definition at line 233 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K (192000U)

Definition at line 227 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K (22050U)

Definition at line 232 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K (32000U)

Definition at line 231 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K (44100U)

Definition at line 230 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K (48000U)

Definition at line 229 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K (8000U)

Definition at line 235 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K (96000U)

Definition at line 228 of file stm32g4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT (2U)

Definition at line 236 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Definition at line 245 of file stm32g4xx_hal_i2s.h.

#define I2S_CPOL_LOW (0x00000000U)

Definition at line 244 of file stm32g4xx_hal_i2s.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Interrupts Definition

Defines
I2S Interrupts Definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define I2S_IT_ERR SPI_CR2_ERRIE

Definition at line 255 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define I2S_IT_RXNE SPI_CR2_RXNEIE

Definition at line 254 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

#define I2S_IT_TXE SPI_CR2_TXEIE

Definition at line 253 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Flags Definition

Defines
I2S Flags Definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | I2S_FLAG_MASK

Define Documentation

#define I2S_FLAG_BSY SPI_SR_BSY

Definition at line 271 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE

Definition at line 270 of file stm32g4xx_hal_i2s.h.

#define I2S_FLAG_FRE SPI_SR_FRE

Definition at line 268 of file stm32g4xx_hal_i2s.h.

#define I2S_FLAG_MASK
Value:
(SPI_SR_RXNE\
                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)

Definition at line 273 of file stm32g4xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR

Definition at line 267 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_RXNE SPI_SR_RXNE

Definition at line 264 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXE SPI_SR_TXE

Definition at line 263 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR

Definition at line 266 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_FLUSH_RX_DR(__HANDLE__)
Flush the I2S DR Register.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{ \
                                                __IO uint32_t tmpreg_ovr = 0x00U; \
                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
                                                UNUSED(tmpreg_ovr); \
                                              }while(0U)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 368 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ )
Value:
do{\
                                                __IO uint32_t tmpreg_udr = 0x00U;\
                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
                                                UNUSED(tmpreg_udr); \
                                              }while(0U)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 378 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define __HAL_I2S_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))

Disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 312 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), and HAL_I2S_DMAStop().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))

Disable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 334 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))

Enable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 306 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))

Enable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 323 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_FLUSH_RX_DR ( __HANDLE__ )
Value:
do{\
                                                __IO uint32_t tmpreg_dr = 0x00U;\
                                                tmpreg_dr = ((__HANDLE__)->Instance->DR);\
                                                UNUSED(tmpreg_dr); \
                                              }while(0U)

Flush the I2S DR Register.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 387 of file stm32g4xx_hal_i2s.h.

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__ specifies the I2S Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_FRE: Frame error flag
  • I2S_FLAG_CHSIDE: Channel Side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 362 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR2\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 346 of file stm32g4xx_hal_i2s.h.

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset I2S handle state.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 293 of file stm32g4xx_hal_i2s.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | I2S_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
Checks if I2S Serial clock steady state parameter is in allowed range.

Define Documentation

#define I2S_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) |
Value:
((((__SR__)\
                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of I2S SR register.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun error flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_CHSIDE: Channel side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
SET or RESET.

Definition at line 485 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_CHECK_IT_SOURCE | ( | __CR2__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__CR2__)\
                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__CR2__ copy of I2S CR2 register.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
SET or RESET.

Definition at line 497 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define IS_I2S_AUDIO_FREQ ( __FREQ__ )
Value:
((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 524 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == I2S_CPOL_LOW) || \
                               ((__CPOL__) == I2S_CPOL_HIGH))

Checks if I2S Serial clock steady state parameter is in allowed range.

Parameters:
__CPOL__ specifies the I2S serial clock steady state. This parameter can be a value of I2S Clock Polarity
Return values:
None

Definition at line 533 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))

Definition at line 516 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 521 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( __MODE__ )
Value:
(((__MODE__) == I2S_MODE_SLAVE_TX)  || \
                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
                               ((__MODE__) == I2S_MODE_MASTER_RX))

Checks if I2S Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the I2S Mode. This parameter can be a value of I2S Mode
Return values:
None

Definition at line 505 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_STANDARD ( __STANDARD__ )
Value:
(((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))

Definition at line 510 of file stm32g4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S

Modules | Defines
I2S
STM32G4xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Private Functions
I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Macros

Defines

#define I2S_TIMEOUT_FLAG 100U

Detailed Description

I2S HAL module driver.

Define Documentation

#define I2S_TIMEOUT_FLAG 100U

Timeout 100 ms

Definition at line 203 of file stm32g4xx_hal_i2s.c.

Referenced by HAL_I2S_DMAStop().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                     | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 209 of file stm32g4xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000U

IRDA TX or RX enable acknowledge time-out value

Definition at line 207 of file stm32g4xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 214 of file stm32g4xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 212 of file stm32g4xx_hal_irda.c.

Referenced by IRDA_SetConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) |
Value:
((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
                                                                  + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | IRDA clock source.
__BAUD__ | Baud rate set by the user.
__PRESCALER__ | IRDA clock prescaler value.
Return values:
Division result

Definition at line 229 of file stm32g4xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201U)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__ specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 703 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))

Ensure that IRDA clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ IRDA clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 737 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__ IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 782 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__ IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 775 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__ IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 761 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__ IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 768 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__ IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 715 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__ IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 730 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0U)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__ specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 709 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__ IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 789 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__ IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 754 of file stm32g4xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ )
Value:
((((__MODE__)\
                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__ IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 723 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 393 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::MspDeInitCallback, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 328 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, __IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_InitCallbacksToDefault(), IRDA_SetConfig(), __IRDA_HandleTypeDef::Lock, and __IRDA_HandleTypeDef::MspInitCallback.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 452 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_UnRegisterCallback().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 436 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_Init(), and HAL_IRDA_UnRegisterCallback().

HAL_StatusTypeDef HAL_IRDA_RegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID,
 |  | pIRDA_CallbackTypeDef | pCallback
 | ) |  |

Register a User IRDA Callback To be used to override the weak predefined callback.

Note:
The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
Parameters:
hirda | irda handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 484 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Note:
The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
Parameters:
hirda irda handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 603 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_ErrorCallback(), HAL_IRDA_MspDeInit(), HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MspInit(), HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

 ===============================================================================
                         ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

  [..]
    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_IRDA_Abort()
        (++) HAL_IRDA_AbortTransmit()
        (++) HAL_IRDA_AbortReceive()
        (++) HAL_IRDA_Abort_IT()
        (++) HAL_IRDA_AbortTransmit_IT()
        (++) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_IRDA_AbortCpltCallback()
        (++) HAL_IRDA_AbortTransmitCpltCallback()
        (++) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
             in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
             to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
             Transfer is kept ongoing on IRDA side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and
             HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1393 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1590 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2117 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1532 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1801 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2149 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1480 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1723 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2133 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1240 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1278 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_InitTypeDef::Parity, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1316 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and __IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2101 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1877 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 886 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
When the IRDA parity is enabled (PCE = 1), the received data contains the parity bit (MSB position).
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1161 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_PARITY_NONE, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1021 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2069 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2085 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 797 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1081 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 976 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and __IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2037 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 2053 of file stm32g4xx_hal_irda.c.

References UNUSED.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( const IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 2205 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( const IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 2188 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, and __IRDA_HandleTypeDef::RxState.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2333 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2602 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_ErrorCallback(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2562 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2507 of file stm32g4xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2543 of file stm32g4xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2673 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2748 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2452 of file stm32g4xx_hal_irda.c.

References HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2488 of file stm32g4xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2625 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2721 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2435 of file stm32g4xx_hal_irda.c.

References HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static void IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2817 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::TxCpltCallback.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2420 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and __IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

void IRDA_InitCallbacksToDefault ( IRDA_HandleTypeDef * hirda )

Initialize the callbacks to their default values.

Parameters:
hirda IRDA handle.
Return values:
none

Definition at line 2228 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ErrorCallback(), HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Init().

static void IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2842 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2249 of file stm32g4xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, IRDA_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK1, IRDA_CLOCKSOURCE_PCLK2, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CR1_FIELDS, IRDA_DIV_SAMPLING16, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_CLOCKPRESCALER, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, USART_BRR_MAX, USART_BRR_MIN, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static void IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2778 of file stm32g4xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | The actual Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2385 of file stm32g4xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Exported Types

Data Structures | Typedefs | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U,
IRDA_CLOCKSOURCE_LSE = 0x10U, IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_IRDA_StateTypeDef

HAL IRDA State definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState (see IRDA State Code Definition).
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 118 of file stm32g4xx_hal_irda.h.

typedef struct __IRDA_HandleTypeDef IRDA_HandleTypeDef

IRDA handle Structure definition.

typedef void(* pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda)

HAL IRDA Callback pointer definition.

pointer to an IRDA callback function

Definition at line 223 of file stm32g4xx_hal_irda.h.

Enumeration Type Documentation

enum HAL_IRDA_CallbackIDTypeDef

HAL IRDA Callback ID enumeration definition.

Enumerator:
HAL_IRDA_TX_HALFCOMPLETE_CB_ID

IRDA Tx Half Complete Callback ID

HAL_IRDA_TX_COMPLETE_CB_ID

IRDA Tx Complete Callback ID

HAL_IRDA_RX_HALFCOMPLETE_CB_ID

IRDA Rx Half Complete Callback ID

HAL_IRDA_RX_COMPLETE_CB_ID

IRDA Rx Complete Callback ID

HAL_IRDA_ERROR_CB_ID

IRDA Error Callback ID

HAL_IRDA_ABORT_COMPLETE_CB_ID

IRDA Abort Complete Callback ID

HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID

IRDA Abort Transmit Complete Callback ID

HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID

IRDA Abort Receive Complete Callback ID

HAL_IRDA_MSPINIT_CB_ID

IRDA MspInit callback ID

HAL_IRDA_MSPDEINIT_CB_ID

IRDA MspDeInit callback ID

Definition at line 204 of file stm32g4xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK1

PCLK1 clock source

IRDA_CLOCKSOURCE_PCLK2

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 123 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32g4xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode
uint32_t | ClockPrescaler

Detailed Description

IRDA Init Structure definition.

Definition at line 46 of file stm32g4xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) where usart_ker_ckpres is the IRDA input clock divided by a prescaler

Definition at line 48 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the IRDA clock source. This parameter can be a value of IRDA Clock Prescaler.

Definition at line 73 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 63 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 56 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 70 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 66 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDAEx Word Length

Definition at line 53 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_irda.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32g4xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | TxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | ErrorCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortTransmitCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortReceiveCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspInitCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspDeInitCallback )(struct __IRDA_HandleTypeDef *hirda)

Detailed Description

IRDA handle Structure definition.

Definition at line 137 of file stm32g4xx_hal_irda.h.

Field Documentation

void(* __IRDA_HandleTypeDef::AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Complete Callback

Definition at line 186 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Receive Complete Callback

Definition at line 190 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Transmit Complete Callback

Definition at line 188 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::ErrorCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Error Callback

Definition at line 184 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

__IO uint32_t __IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 173 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DeInit(), HAL_IRDA_DMAStop(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 166 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 162 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 160 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef __IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 144 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* __IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 142 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef __IRDA_HandleTypeDef::Lock

Locking object

Definition at line 164 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t __IRDA_HandleTypeDef::Mask

USART RX RDR register mask

Definition at line 158 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp DeInit callback

Definition at line 195 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

void(* __IRDA_HandleTypeDef::MspInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp Init callback

Definition at line 193 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

uint8_t* __IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 152 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

const uint8_t* __IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 146 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

void(* __IRDA_HandleTypeDef::RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Complete Callback

Definition at line 182 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Half Complete Callback

Definition at line 180 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 170 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t __IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 156 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t __IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 154 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Complete Callback

Definition at line 178 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Half Complete Callback

Definition at line 176 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO uint16_t __IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 150 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t __IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 148 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_irda.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA State Code Definition

Defines
IRDA State Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_IRDA_STATE_BUSY 0x00000024U

An internal process is ongoing Value is allowed for gState only

Definition at line 243 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define HAL_IRDA_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 247 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), and IRDA_Receive_IT().

#define HAL_IRDA_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 245 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), and IRDA_Transmit_IT().

#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 249 of file stm32g4xx_hal_irda.h.

#define HAL_IRDA_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 255 of file stm32g4xx_hal_irda.h.

#define HAL_IRDA_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 241 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define HAL_IRDA_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 239 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 253 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Error Code Definition

Defines
IRDA Error Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_IRDA_ERROR_BUSY (0x00000020U)

Busy Error

Definition at line 270 of file stm32g4xx_hal_irda.h.

#define HAL_IRDA_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 269 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), and IRDA_DMAError().

#define HAL_IRDA_ERROR_FE (0x00000004U)

frame error

Definition at line 267 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 272 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_ERROR_NE (0x00000002U)

Noise error

Definition at line 266 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE (0x00000000U)

No error

Definition at line 264 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 268 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE (0x00000001U)

Parity error

Definition at line 265 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define IRDA_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 282 of file stm32g4xx_hal_irda.h.

#define IRDA_PARITY_NONE 0x00000000U

No parity

Definition at line 281 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 283 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define IRDA_MODE_RX USART_CR1_RE

RX mode

Definition at line 291 of file stm32g4xx_hal_irda.h.

#define IRDA_MODE_TX USART_CR1_TE

TX mode

Definition at line 292 of file stm32g4xx_hal_irda.h.

#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 293 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

Define Documentation

#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

IRDA low power mode

Definition at line 302 of file stm32g4xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL 0x00000000U

IRDA normal power mode

Definition at line 301 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Clock Prescaler

Defines
IRDA Clock Prescaler
IRDA Exported Constants

Defines

#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define IRDA_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 310 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 315 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 316 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 320 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 317 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 311 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 321 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 318 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 312 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 313 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 319 of file stm32g4xx_hal_irda.h.

#define IRDA_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 314 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE

Define Documentation

#define IRDA_STATE_DISABLE 0x00000000U

IRDA disabled

Definition at line 329 of file stm32g4xx_hal_irda.h.

#define IRDA_STATE_ENABLE USART_CR1_UE

IRDA enabled

Definition at line 330 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN

Define Documentation

#define IRDA_MODE_DISABLE 0x00000000U

Associated UART disabled in IRDA mode

Definition at line 338 of file stm32g4xx_hal_irda.h.

#define IRDA_MODE_ENABLE USART_CR3_IREN

Associated UART enabled in IRDA mode

Definition at line 339 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disabled

Definition at line 347 of file stm32g4xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enabled

Definition at line 348 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define IRDA_DMA_TX_DISABLE 0x00000000U

IRDA DMA TX disabled

Definition at line 356 of file stm32g4xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT

IRDA DMA TX enabled

Definition at line 357 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define IRDA_DMA_RX_DISABLE 0x00000000U

IRDA DMA RX disabled

Definition at line 365 of file stm32g4xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR

IRDA DMA RX enabled

Definition at line 366 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 374 of file stm32g4xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 375 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 376 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE USART_ISR_ABRE

IRDA auto Baud rate error

Definition at line 390 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_ABRF USART_ISR_ABRF

IRDA auto Baud rate flag

Definition at line 389 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_BUSY USART_ISR_BUSY

IRDA busy flag

Definition at line 388 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_FE USART_ISR_FE

IRDA frame error

Definition at line 396 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_NE USART_ISR_NE

IRDA noise error

Definition at line 395 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_ORE USART_ISR_ORE

IRDA overrun error

Definition at line 394 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_PE USART_ISR_PE

IRDA parity error

Definition at line 397 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_REACK USART_ISR_REACK

IRDA receive enable acknowledge flag

Definition at line 386 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE

IRDA read data register not empty

Definition at line 393 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC USART_ISR_TC

IRDA transmission complete

Definition at line 392 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK USART_ISR_TEACK

IRDA transmit enable acknowledge flag

Definition at line 387 of file stm32g4xx_hal_irda.h.

#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF

IRDA transmit data register empty

Definition at line 391 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR 0x0060U

IRDA Error interruption

Definition at line 424 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_FE 0x0100U

IRDA Frame error interruption

Definition at line 430 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_IDLE 0x0424U

IRDA Idle interruption

Definition at line 416 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_NE 0x0200U

IRDA Noise error interruption

Definition at line 429 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_ORE 0x0300U

IRDA Overrun error interruption

Definition at line 428 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_PE 0x0028U

IRDA Parity error interruption

Definition at line 412 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_RXNE 0x0525U

IRDA Read data register not empty interruption

Definition at line 415 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_TC 0x0626U

IRDA Transmission complete interruption

Definition at line 414 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_TXE 0x0727U

IRDA Transmit data register empty interruption

Definition at line 413 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 439 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 442 of file stm32g4xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 440 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 441 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 438 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 443 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U

Define Documentation

#define IRDA_CR_MASK 0x00E0U

IRDA control register mask

Definition at line 452 of file stm32g4xx_hal_irda.h.

#define IRDA_CR_POS 5U

IRDA control register position

Definition at line 453 of file stm32g4xx_hal_irda.h.

#define IRDA_ISR_MASK 0x1F00U

IRDA ISR register mask

Definition at line 454 of file stm32g4xx_hal_irda.h.

#define IRDA_ISR_POS 8U

IRDA ISR register position

Definition at line 455 of file stm32g4xx_hal_irda.h.

#define IRDA_IT_MASK 0x001FU

IRDA Interruptions flags mask

Definition at line 451 of file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 522 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 509 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 540 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 651 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 528 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 534 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 515 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 688 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 596 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 682 of file stm32g4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
                                                           ((__HANDLE__)->Instance->CR1 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
                                                           ((__HANDLE__)->Instance->CR2 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 575 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the IRDA DR register.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 491 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 560 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 619 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
      & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
     & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 634 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 675 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 669 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset IRDA handle state.

Parameters:
__HANDLE__ IRDA handle.
Return values:
None

Definition at line 474 of file stm32g4xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 663 of file stm32g4xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDAEx Word Length

Defines
IRDAEx Word Length
IRDAEx Extended Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define IRDA_WORDLENGTH_7B USART_CR1_M1

7-bit long frame

Definition at line 48 of file stm32g4xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_8B 0x00000000U

8-bit long frame

Definition at line 49 of file stm32g4xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_9B USART_CR1_M0

9-bit long frame

Definition at line 50 of file stm32g4xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__ | specifies the IRDA Handle.
__CLOCKSOURCE__ | output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 186 of file stm32g4xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 355 of file stm32g4xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__ IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 400 of file stm32g4xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define | IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))

Definition at line 129 of file stm32g4xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Definition at line 130 of file stm32g4xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32g4xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 46 of file stm32g4xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 48 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 51 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 54 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_iwdg.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32g4xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 62 of file stm32g4xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 66 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 64 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_iwdg.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 87 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 84 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 88 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 85 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 82 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 86 of file stm32g4xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 83 of file stm32g4xx_hal_iwdg.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 96 of file stm32g4xx_hal_iwdg.h.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 123 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 115 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 170 of file stm32g4xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_KERNEL_UPDATE_FLAGS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 257 of file stm32g4xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 165 of file stm32g4xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 164 of file stm32g4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 167 of file stm32g4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 166 of file stm32g4xx_hal_iwdg.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 197 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 210 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 217 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 190 of file stm32g4xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 183 of file stm32g4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 355 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_GetState(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::MspDeInitCallback, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 223 of file stm32g4xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, __LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, __LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ResetCallback(), LPTIM_TRIGSOURCE_SOFTWARE, __LPTIM_HandleTypeDef::MspInitCallback, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 417 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_DeInit(), and HAL_LPTIM_UnRegisterCallback().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 402 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_Init(), and HAL_LPTIM_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1550 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1629 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1599 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1698 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1134 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1226 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1193 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1303 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 689 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 776 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 744 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 861 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 466 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 553 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 521 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 638 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 913 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1000 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 968 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1085 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1346 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1438 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_CMPM, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1401 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1510 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and __LPTIM_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( const LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim LPTIM handle
Return values:
Autoreload value.

Definition at line 1767 of file stm32g4xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( const LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim LPTIM handle
Return values:
Compare value.

Definition at line 1780 of file stm32g4xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( const LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim LPTIM handle
Return values:
Counter value.

Definition at line 1754 of file stm32g4xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Detailed Description

LPTIM IRQ handler.

LPTIM IRQ handler and callback functions.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler:
   (+) LPTIM interrupt request handler
   (+) Compare match Callback
   (+) Auto-reload match Callback
   (+) External trigger event detection Callback
   (+) Compare register write complete Callback
   (+) Auto-reload register write complete Callback
   (+) Up-counting direction change Callback
   (+) Down-counting direction change Callback

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1961 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2006 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1946 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1991 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2036 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2021 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1819 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_LPTIM_RegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID,
 |  | pLPTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User LPTIM callback to be used instead of the weak predefined callback.

Parameters:
hlptim | LPTIM handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 2064 of file stm32g4xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1976 of file stm32g4xx_hal_lptim.c.

References UNUSED.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Parameters:
hlptim LPTIM handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
Return values:
status

Definition at line 2165 of file stm32g4xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MspInit(), HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, HAL_LPTIM_TriggerCallback(), __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (const LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( const LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim LPTIM handle
Return values:
HAL state

Definition at line 2278 of file stm32g4xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::State.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Functions

Functions
LPTIM Private Functions
LPTIM | LPTIM

Functions

void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.
static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.

Function Documentation

void LPTIM_Disable ( LPTIM_HandleTypeDef * hlptim )

Disable LPTIM HW instance.

Parameters:
hlptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 2350 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM1_FORCE_RESET, __HAL_RCC_LPTIM1_RELEASE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), RCC_LPTIM1CLKSOURCE_PCLK1, and __LPTIM_HandleTypeDef::State.

static void LPTIM_ResetCallback ( LPTIM_HandleTypeDef * lptim ) [static]

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
lptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Return values:
None

Definition at line 2305 of file stm32g4xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), and __LPTIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_LPTIM_Init().

static HAL_StatusTypeDef LPTIM_WaitForFlag | ( | const LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | flag
 | ) |  | [static]

LPTimer Wait for flag set.

Parameters:
hlptim | pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
flag | The lptim flag
Return values:
HAL status

Definition at line 2325 of file stm32g4xx_hal_lptim.c.

References __HAL_LPTIM_GET_FLAG, and TIMEOUT.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Types

Data Structures | Defines | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM37

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Define Documentation

#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM37

External interrupt line 37 Connected to the LPTIM EXTI Line

Definition at line 44 of file stm32g4xx_hal_lptim.h.

Typedef Documentation

typedef struct __LPTIM_HandleTypeDef LPTIM_HandleTypeDef

LPTIM handle Structure definition.

typedef void(* pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim)

HAL TIM Callback pointer definition.

pointer to the LPTIM callback function

Definition at line 189 of file stm32g4xx_hal_lptim.h.

Enumeration Type Documentation

enum HAL_LPTIM_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_LPTIM_MSPINIT_CB_ID

LPTIM Base Msp Init Callback ID

HAL_LPTIM_MSPDEINIT_CB_ID

LPTIM Base Msp DeInit Callback ID

HAL_LPTIM_COMPARE_MATCH_CB_ID

Compare match Callback ID

HAL_LPTIM_AUTORELOAD_MATCH_CB_ID

Auto-reload match Callback ID

HAL_LPTIM_TRIGGER_CB_ID

External trigger event detection Callback ID

HAL_LPTIM_COMPARE_WRITE_CB_ID

Compare register write complete Callback ID

HAL_LPTIM_AUTORELOAD_WRITE_CB_ID

Auto-reload register write complete Callback ID

HAL_LPTIM_DIRECTION_UP_CB_ID

Up-counting direction change Callback ID

HAL_LPTIM_DIRECTION_DOWN_CB_ID

Down-counting direction change Callback ID

Definition at line 173 of file stm32g4xx_hal_lptim.h.

enum HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 128 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32g4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 49 of file stm32g4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 54 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 51 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_lptim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32g4xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 62 of file stm32g4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 64 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 71 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_lptim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32g4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 80 of file stm32g4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 85 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 89 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 82 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_lptim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32g4xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 97 of file stm32g4xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 99 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 112 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 116 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 119 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 105 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 103 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 101 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 108 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_lptim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32g4xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State
void(* | MspInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | MspDeInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | TriggerCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionUpCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionDownCallback )(struct __LPTIM_HandleTypeDef *hlptim)

Detailed Description

LPTIM handle Structure definition.

Definition at line 141 of file stm32g4xx_hal_lptim.h.

Field Documentation

void(* __LPTIM_HandleTypeDef::AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload match Callback

Definition at line 160 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload register write complete Callback

Definition at line 163 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare match Callback

Definition at line 159 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare register write complete Callback

Definition at line 162 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Down-counting direction change Callback

Definition at line 165 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Up-counting direction change Callback

Definition at line 164 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

LPTIM_InitTypeDef __LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 148 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* __LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 146 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), and LPTIM_Disable().

HAL_LockTypeDef __LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 152 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

void(* __LPTIM_HandleTypeDef::MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp DeInit Callback

Definition at line 158 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_DeInit(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

void(* __LPTIM_HandleTypeDef::MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp Init Callback

Definition at line 157 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

__IO HAL_LPTIM_StateTypeDef __LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 154 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_Disable().

HAL_StatusTypeDef __LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 150 of file stm32g4xx_hal_lptim.h.

void(* __LPTIM_HandleTypeDef::TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim)

External trigger event detection Callback

Definition at line 161 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_lptim.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U

Definition at line 204 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 205 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LPTIM_PRESCALER_DIV1 0x00000000U

Definition at line 213 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Definition at line 220 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 217 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 214 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)

Definition at line 218 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 215 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)

Definition at line 219 of file stm32g4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)

Definition at line 216 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U

Definition at line 229 of file stm32g4xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Definition at line 230 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 239 of file stm32g4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 240 of file stm32g4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 241 of file stm32g4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 238 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 250 of file stm32g4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U

Definition at line 249 of file stm32g4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 251 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3
#define | LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)

Define Documentation

#define LPTIM_TRIGSOURCE_0 0x00000000U

Definition at line 260 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0

Definition at line 261 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)

Definition at line 270 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)

Definition at line 271 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)

Definition at line 272 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 262 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 263 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 264 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 265 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 266 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 267 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3

Definition at line 268 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)

Definition at line 269 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU

Definition at line 259 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 281 of file stm32g4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 280 of file stm32g4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 282 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 291 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 292 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 293 of file stm32g4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 290 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 303 of file stm32g4xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE 0x00000000U

Definition at line 302 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 313 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U

Definition at line 312 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0
#define | LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0

Definition at line 323 of file stm32g4xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)

Definition at line 324 of file stm32g4xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U

Definition at line 322 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0
#define | LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0

Definition at line 340 of file stm32g4xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)

Definition at line 341 of file stm32g4xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U

Definition at line 339 of file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 358 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 355 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 359 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 356 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 353 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 357 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 354 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 372 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 369 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 373 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 370 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 367 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 371 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 368 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()
Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()
Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()
Enable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()
Disable event on the LPTIM Wake-up Timer associated Exti line.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Autoreload value This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
Return values:
None
Note:
The ARR register can only be modified when the LPTIM instance is enabled.

Definition at line 455 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__ LPTIM handle.
__FLAG__ LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 496 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Compare value
Return values:
None
Note:
The CMP register can only be modified when the LPTIM instance is enabled.

Definition at line 464 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) LPTIM_Disable(__HANDLE__)

Disable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Please call HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to check for TIMEOUT.
Return values:
None

Definition at line 418 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.

Definition at line 530 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 406 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.

Definition at line 513 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__ LPTIM handle
__FLAG__ LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 480 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), and LPTIM_WaitForFlag().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->IER\
                                                                & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt source is enabled or not.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 547 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_RESET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)

Reset the LPTIM Counter register in synchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 438 of file stm32g4xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)

Reset after read of the LPTIM Counter register in asynchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 445 of file stm32g4xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                        (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback   = NULL;                  \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;                  \
                                                      } while(0)

Reset LPTIM handle state.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 392 of file stm32g4xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 425 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Start the LPTIM peripheral in single mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 431 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT ( )
Value:
(EXTI->EMR2\
                                                        &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 575 of file stm32g4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT ( )
Value:
(EXTI->IMR2\
                                                        &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the LPTIM Wake-up Timer associated Exti line.

Return values:
None

Definition at line 561 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT ( )
Value:
(EXTI->EMR2\
                                                        |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 568 of file stm32g4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT ( )
Value:
(EXTI->IMR2\
                                                        |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the LPTIM Wake-up Timer associated Exti line.

Return values:
None

Definition at line 554 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Constants

Defines
LPTIM Private Constants
LPTIM

Defines

#define TIMEOUT 1000UL /* Timeout is 1s */

Define Documentation

#define TIMEOUT 1000UL /* Timeout is 1s */

Definition at line 180 of file stm32g4xx_hal_lptim.c.

Referenced by LPTIM_WaitForFlag().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 765 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 746 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 755 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 760 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 742 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFFUL)

Definition at line 813 of file stm32g4xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 810 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 798 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                       \
    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||        \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))

Definition at line 829 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
(((__INSTANCE__) == LPTIM1) &&                       \
   (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
    ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) ||        \
    ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))

Definition at line 844 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 757 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ )
Value:
((0x00000001UL <= (__PERIOD__)) &&\
                                                 ((__PERIOD__) <= 0x0000FFFFUL))

Definition at line 815 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFFUL)

Definition at line 818 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_9))

Definition at line 785 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 802 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 807 of file stm32g4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Private Define

Defines
OPAMP Private Define
OPAMP

Defines

#define | OPAMP_CSR_RESET_VALUE (0x00000000UL)
#define | OPAMP_CSR_RESET_CHECK_MASK (~(OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP))
#define | OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK
#define | OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK

Define Documentation

#define OPAMP_CSR_RESET_CHECK_MASK (~(OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP))

Definition at line 250 of file stm32g4xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_CSR_RESET_VALUE (0x00000000UL)

Definition at line 248 of file stm32g4xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK
Value:
(OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
                                               | OPAMP_CSR_HIGHSPEEDEN | OPAMP_CSR_OPAMPINTEN \
                                               | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSEL \
                                               | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)

Definition at line 252 of file stm32g4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK
Value:
(OPAMP_TCMR_T20CMEN | OPAMP_TCMR_T8CMEN \
                                                | OPAMP_TCMR_T1CMEN | OPAMP_TCMR_VPSSEL \
                                                | OPAMP_TCMR_VMSSEL)

Definition at line 257 of file stm32g4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitializes the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization  functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_DeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitializes the OPAMP peripheral.

Note:
Deinitialization can't be performed if the OPAMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 460 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspDeInit(), HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, __OPAMP_HandleTypeDef::MspDeInitCallback, OPAMP_CSR_RESET_CHECK_MASK, OPAMP_CSR_RESET_VALUE, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Init ( OPAMP_HandleTypeDef * hopamp )

Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.

Note:
If the selected opamp is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 294 of file stm32g4xx_hal_opamp.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, HAL_OPAMP_MspInit(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, OPAMP_InitTypeDef::InternalOutput, OPAMP_InitTypeDef::InvertingInput, OPAMP_InitTypeDef::InvertingInputSecondary, IS_OPAMP_FUNCTIONAL_NORMALMODE, IS_OPAMP_INVERTING_INPUT, IS_OPAMP_NONINVERTING_INPUT, IS_OPAMP_PGA_GAIN, IS_OPAMP_PGACONNECT, IS_OPAMP_POWERMODE, IS_OPAMP_SEC_INVERTING_INPUT, IS_OPAMP_SEC_NONINVERTING_INPUT, IS_OPAMP_TIMERCONTROLLED_MUXMODE, IS_OPAMP_TRIMMING, IS_OPAMP_TRIMMINGVALUE, __OPAMP_HandleTypeDef::Lock, OPAMP_InitTypeDef::Mode, __OPAMP_HandleTypeDef::MspInitCallback, OPAMP_InitTypeDef::NonInvertingInput, OPAMP_InitTypeDef::NonInvertingInputSecondary, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, OPAMP_FOLLOWER_MODE, OPAMP_INPUT_INVERTING, OPAMP_INPUT_NONINVERTING, OPAMP_PGA_MODE, OPAMP_STANDALONE_MODE, OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK, OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PgaConnect, OPAMP_InitTypeDef::PgaGain, OPAMP_InitTypeDef::PowerMode, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TimerControlledMuxmode, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueP, and OPAMP_InitTypeDef::UserTrimming.

void HAL_OPAMP_MspDeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize OPAMP MSP.

Parameters:
hopamp OPAMP handle
Return values:
None

Definition at line 541 of file stm32g4xx_hal_opamp.c.

References UNUSED.

Referenced by HAL_OPAMP_DeInit(), and HAL_OPAMP_UnRegisterCallback().

void HAL_OPAMP_MspInit ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP MSP.

Parameters:
hopamp OPAMP handle
Return values:
None

Definition at line 524 of file stm32g4xx_hal_opamp.c.

References UNUSED.

Referenced by HAL_OPAMP_Init(), and HAL_OPAMP_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
OPAMP Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the opamp.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the opamp.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the OPAMP data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate ( OPAMP_HandleTypeDef * hopamp )

Run the self calibration of one OPAMP.

Note:
Calibration is performed in the mode specified in OPAMP init structure (mode normal or high-speed).
Parameters:
hopamp handle
Return values:
Updated | offset trimming values (PMOS & NMOS), user trimming is enabled
HAL | status
Note:
Calibration runs about 25 ms.

Definition at line 672 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, OPAMP_INPUT_INVERTING, OPAMP_INPUT_NONINVERTING, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueP, and OPAMP_InitTypeDef::UserTrimming.

HAL_StatusTypeDef HAL_OPAMP_Start ( OPAMP_HandleTypeDef * hopamp )

Start the opamp.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 578 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Stop ( OPAMP_HandleTypeDef * hopamp )

Stop the opamp.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 621 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMP Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp configuration.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_LockTimerMux (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp timer controlled mux configuration.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the OPAMP data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_Lock ( OPAMP_HandleTypeDef * hopamp )

Lock the selected opamp configuration.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 874 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_LockTimerMux ( OPAMP_HandleTypeDef * hopamp )

Lock the selected opamp timer controlled mux configuration.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 913 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_RegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId,
 |  | pOPAMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hopamp | : OPAMP handle
CallbackID : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1064 of file stm32g4xx_hal_opamp.c.

References HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hopamp : OPAMP handle
CallbackID : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID
  • HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
Return values:
status

Definition at line 1132 of file stm32g4xx_hal_opamp.c.

References HAL_OPAMP_ALL_CB_ID, HAL_OPAMP_MspDeInit(), HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MspInit(), HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
OPAMP | OPAMP Exported Functions

Peripheral State functions. More...

Functions

HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP state.
OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState ( OPAMP_HandleTypeDef * hopamp )

Return the OPAMP state.

Parameters:
hopamp OPAMP handle
Return values:
HAL state

Definition at line 968 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | uint32_t | trimmingoffset
 | ) |  |

Return the OPAMP factory trimming value.

Parameters:
hopamp | OPAMP handle
trimmingoffset | Trimming offset (P or N)
Return values:
Trimming value (P or N): range: 0->31 or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available

Definition at line 990 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Instance, IS_OPAMP_FACTORYTRIMMING, OPAMP_FACTORYTRIMMING_DUMMY, OPAMP_FACTORYTRIMMING_P, OPAMP_INPUT_INVERTING, OPAMP_INPUT_NONINVERTING, OPAMP_TRIMMING_USER, and __OPAMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Functions

Modules | Functions
OPAMP Exported Functions
OPAMP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef HAL_OPAMP_LockTimerMux (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp timer controlled mux configuration.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_LockTimerMux ( OPAMP_HandleTypeDef * hopamp )

Lock the selected opamp timer controlled mux configuration.

Parameters:
hopamp OPAMP handle
Return values:
HAL status

Definition at line 913 of file stm32g4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::Instance, and __OPAMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Types

Data Structures | Typedefs | Enumerations
OPAMP Exported Types
OPAMP

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | __OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Typedefs

typedef struct
__OPAMP_HandleTypeDef 		OPAMP_HandleTypeDef
OPAMP Handle Structure definition.
typedef uint32_t | OPAMP_TrimmingValueTypeDef
OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000UL, HAL_OPAMP_STATE_READY = 0x00000001UL, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002UL, HAL_OPAMP_STATE_BUSY = 0x00000004UL,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005UL
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __OPAMP_HandleTypeDef OPAMP_HandleTypeDef

OPAMP Handle Structure definition.

typedef uint32_t OPAMP_TrimmingValueTypeDef

OPAMP_TrimmingValueTypeDef definition.

Definition at line 163 of file stm32g4xx_hal_opamp.h.

Enumeration Type Documentation

enum HAL_OPAMP_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_OPAMP_STATE_RESET

OPAMP is not yet Initialized

HAL_OPAMP_STATE_READY

OPAMP is initialized and ready for use

HAL_OPAMP_STATE_CALIBBUSY

OPAMP is enabled in auto calibration mode

HAL_OPAMP_STATE_BUSY

OPAMP is enabled and running in normal mode

HAL_OPAMP_STATE_BUSYLOCKED

OPAMP control register is locked only system reset allows reconfiguring the opamp.

Definition at line 124 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_InitTypeDef Struct Reference
OPAMP Exported Types

OPAMP Init structure definition. More...

#include <stm32g4xx_hal_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | Mode
uint32_t | InvertingInput
uint32_t | NonInvertingInput
FunctionalState | InternalOutput
uint32_t | TimerControlledMuxmode
uint32_t | InvertingInputSecondary
uint32_t | NonInvertingInputSecondary
uint32_t | PgaConnect
uint32_t | PgaGain
uint32_t | UserTrimming
uint32_t | TrimmingValueP
uint32_t | TrimmingValueN

Detailed Description

OPAMP Init structure definition.

Definition at line 47 of file stm32g4xx_hal_opamp.h.

Field Documentation

FunctionalState OPAMP_InitTypeDef::InternalOutput

Specifies the configuration of the internal output from OPAMP to ADC. This parameter can be ENABLE or DISABLE Note: When this output is enabled, regular output to I/O is disabled

Definition at line 68 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::InvertingInput

Specifies the inverting input in Standalone & Pga modes

  • In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE This parameter must be a value of OPAMP Inverting Input InvertingInput is either VINM0 or VINM1
  • In PGA mode: i.e when mode is OPAMP_PGA_MODE & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE This parameter is Not Applicable

Definition at line 56 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::InvertingInputSecondary

Specifies the inverting input (secondary) of the opamp when TimerControlledMuxmode is enabled i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE

  • In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE This parameter must be a value of OPAMP Inverting Input Secondary InvertingInputSecondary is either VINM0 or VINM1
  • In PGA mode: i.e when mode is OPAMP_PGA_MODE & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE This parameter must be a value of OPAMP Inverting Input Secondary and is used to choose secondary mode (PGA or follower)

Definition at line 77 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::Mode

Specifies the OPAMP mode This parameter must be a value of OPAMP Mode mode is either Standalone, Follower or PGA

Definition at line 52 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::NonInvertingInput

Specifies the non inverting input of the opamp: This parameter must be a value of OPAMP Non Inverting Input NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3

Definition at line 64 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::NonInvertingInputSecondary

Specifies the non inverting input (secondary) of the opamp when TimerControlledMuxmode is enabled i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE This parameter must be a value of OPAMP Non Inverting Input Secondary NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3

Definition at line 88 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaConnect

Specifies the inverting pin in PGA mode i.e. when mode is OPAMP_PGA_MODE This parameter must be a value of OPAMP Pga Connect Either: not connected, connected to VINM0 In this last case, VINM0 can then be used to input signal (negative gain case with or without bias on VINPx) or to input bias (positive gain case with bias)

Definition at line 94 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaGain

Specifies the gain in PGA mode i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of OPAMP Pga Gain (2, 4, 8, 16, 32 or 64) for positive gain & (-1, -3 ,-7, -15, -31 or -63) for negative gain

Definition at line 101 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PowerMode

Specifies the power mode Normal or High Speed. This parameter must be a value of OPAMP PowerMode

Definition at line 49 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::TimerControlledMuxmode

Specifies if the Timer controlled Mux mode is enabled or disabled This parameter must be a single value of OPAMP Timer Controlled Mux mode or a combination of them to build a more complex switch scheme by using different timers

Definition at line 72 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::TrimmingValueN

Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 114 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueP

Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 110 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::UserTrimming

Specifies the trimming mode This parameter must be a value of OPAMP User Trimming UserTrimming is either factory or user trimming

Definition at line 106 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_opamp.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __OPAMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__OPAMP_HandleTypeDef Struct Reference
OPAMP Exported Types

OPAMP Handle Structure definition. More...

#include <stm32g4xx_hal_opamp.h>

Data Fields

OPAMP_TypeDef * | Instance
OPAMP_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_OPAMP_StateTypeDef | State
void(* | MspInitCallback )(struct __OPAMP_HandleTypeDef *hopamp)
void(* | MspDeInitCallback )(struct __OPAMP_HandleTypeDef *hopamp)

Detailed Description

OPAMP Handle Structure definition.

Definition at line 141 of file stm32g4xx_hal_opamp.h.

Field Documentation

OPAMP_InitTypeDef __OPAMP_HandleTypeDef::Init

OPAMP required parameters

Definition at line 147 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

OPAMP_TypeDef* __OPAMP_HandleTypeDef::Instance

OPAMP instance's registers base address

Definition at line 146 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_LockTimerMux(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), and HAL_OPAMPEx_SelfCalibrateAll().

HAL_LockTypeDef __OPAMP_HandleTypeDef::Lock

Locking object

Definition at line 149 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

void(* __OPAMP_HandleTypeDef::MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp)

Definition at line 154 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_RegisterCallback(), and HAL_OPAMP_UnRegisterCallback().

void(* __OPAMP_HandleTypeDef::MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp)

Definition at line 153 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_RegisterCallback(), and HAL_OPAMP_UnRegisterCallback().

__IO HAL_OPAMP_StateTypeDef __OPAMP_HandleTypeDef::State

OPAMP communication state

Definition at line 150 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_LockTimerMux(), HAL_OPAMP_RegisterCallback(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMP_UnRegisterCallback(), and HAL_OPAMPEx_SelfCalibrateAll().

HAL_StatusTypeDef __OPAMP_HandleTypeDef::Status

OPAMP peripheral status

Definition at line 148 of file stm32g4xx_hal_opamp.h.

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_opamp.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Mode

Defines
OPAMP Mode
OPAMP Exported Constants

Defines

#define | OPAMP_STANDALONE_MODE (0x00000000UL)
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL

Define Documentation

#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL

follower mode

Definition at line 195 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1

PGA mode

Definition at line 194 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_STANDALONE_MODE (0x00000000UL)

standalone mode

Definition at line 193 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Non Inverting Input

Defines
OPAMP Non Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0
#define | OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1
#define | OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL
#define | OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL

Define Documentation

#define OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL

Non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 214 of file stm32g4xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL)

Non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 203 of file stm32g4xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0

Non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 206 of file stm32g4xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1

Non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 209 of file stm32g4xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL

Non inverting input connected to I/O VINP3 (PD14 for OPAMP2)

Definition at line 212 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Inverting Input

Defines
OPAMP Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_INVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

Define Documentation

#define OPAMP_INVERTINGINPUT_IO0 (0x00000000UL)

Inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 224 of file stm32g4xx_hal_opamp.h.

#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

Inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 227 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Timer Controlled Mux mode

Defines
OPAMP Timer Controlled Mux mode
OPAMP Exported Constants

Defines

#define | OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000UL)
#define | OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 OPAMP_TCMR_T1CMEN
#define | OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN

Detailed Description

Note:
The switch can be controlled either by a single timer or a combination of them, in this case application has to 'ORed' the values below ex OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6

Define Documentation

#define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000UL)

Timer controlled Mux mode disabled

Definition at line 240 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 OPAMP_TCMR_T1CMEN

Timer controlled Mux mode enabled using TIM1 OC6

Definition at line 241 of file stm32g4xx_hal_opamp.h.

#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN

Timer controlled Mux mode enabled using TIM8 OC6

Definition at line 242 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Non Inverting Input Secondary

Defines
OPAMP Non Inverting Input Secondary
OPAMP Exported Constants

Defines

#define | OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0
#define | OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1
#define | OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL
#define | OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL

Define Documentation

#define OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL

Secondary non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 265 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL)

Secondary non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 254 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0

Secondary non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 257 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1

Secondary non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 260 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL

Secondary non inverting input connected to I/O VINP3 (PD14 for OPAMP2)

Definition at line 263 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Inverting Input Secondary

Defines
OPAMP Inverting Input Secondary
OPAMP Exported Constants

Defines

#define | OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL
#define | OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL)
#define | OPAMP_SEC_INVERTINGINPUT_FOLLOWER OPAMP_TCMR_VMSSEL

Define Documentation

#define OPAMP_SEC_INVERTINGINPUT_FOLLOWER OPAMP_TCMR_VMSSEL

OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to HAL_OPAMP_Init() is OPAMP_PGA_MODE or OPAMP_FOLLOWER_MODE. OPAMP secondary inverting input is not connected.

Definition at line 292 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000UL)

OPAMP secondary mode is standalone mode - Only applicable if OPAMP_STANDALONE_MODE has been configured by call to HAL_OPAMP_Init(). Secondary inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 275 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL

OPAMP secondary mode is standalone mode - Only applicable if OPAMP_STANDALONE_MODE has been configured by call to HAL_OPAMP_Init(). Secondary inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 280 of file stm32g4xx_hal_opamp.h.

#define OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL)

OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to HAL_OPAMP_Init() is OPAMP_PGA_MODE or OPAMP_FOLLOWER_MODE. OPAMP secondary inverting input is:

  • Not connected if configured mode is OPAMP_FOLLOWER_MODE
  • Not connected if configured mode is OPAMP_PGA_MODE and PGA connect mode is OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
  • Connected to VINM0 and possibly VINM1 if any of the other modes as been configured (see OPAMP Pga Connect description for more details on PGA connection modes)

Definition at line 285 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Pga Connect

Defines
OPAMP Pga Connect
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000UL)
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_4
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3)

Define Documentation

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_4

In PGA mode, the inverting input is connected to VINM0 for filtering

Definition at line 303 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain

Definition at line 304 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3)

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain And VINM1 is connected too for filtering

Definition at line 307 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000UL)

In PGA mode, the inverting input is not connected

Definition at line 302 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Pga Gain

Defines
OPAMP Pga Gain
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)
#define | OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )
#define | OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)

Detailed Description

Note:
Gain sign:
  • is positive if the OPAMP Pga Connect configuration is OPAMP_PGA_CONNECT_INVERTINGINPUT_NO or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
  • may be positive or negative if the OPAMP Pga Connect configuration is OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS see OPAMP Pga Connect for more details

Define Documentation

#define OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)

PGA gain could be 16 or -15

Definition at line 327 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)

PGA gain could be 2 or -1

Definition at line 324 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )

PGA gain could be 32 or -31

Definition at line 328 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)

PGA gain could be 4 or -3

Definition at line 325 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)

PGA gain could be 64 or -63

Definition at line 329 of file stm32g4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )

PGA gain could be 8 or -7

Definition at line 326 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN

Define Documentation

#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN

Output in highspeed mode

Definition at line 338 of file stm32g4xx_hal_opamp.h.

#define OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)

Output in normal mode

Definition at line 337 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP User Trimming

Defines
OPAMP User Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_TRIMMING_FACTORY (0x00000000UL)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

Define Documentation

#define OPAMP_TRIMMING_FACTORY (0x00000000UL)

Factory trimming

Definition at line 346 of file stm32g4xx_hal_opamp.h.

#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

User trimming

Definition at line 347 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Factory Trimming

Defines
OPAMP Factory Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFUL)
#define | OPAMP_FACTORYTRIMMING_N (0x00000000UL)
#define | OPAMP_FACTORYTRIMMING_P (0x00000001UL)

Define Documentation

#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFUL)

Dummy trimming value

Definition at line 355 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define OPAMP_FACTORYTRIMMING_N (0x00000000UL)

Offset trimming N

Definition at line 357 of file stm32g4xx_hal_opamp.h.

#define OPAMP_FACTORYTRIMMING_P (0x00000001UL)

Offset trimming P

Definition at line 358 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP VREF

Defines
OPAMP VREF
OPAMP Exported Constants

Defines

#define | OPAMP_VREF_3VDDA (0x00000000UL)
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

Define Documentation

#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0

OPAMP Vref = 10% VDDA

Definition at line 367 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_VREF_3VDDA (0x00000000UL)

OPAMP Vref = 3.3% VDDA

Definition at line 366 of file stm32g4xx_hal_opamp.h.

#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1

OPAMP Vref = 50% VDDA

Definition at line 368 of file stm32g4xx_hal_opamp.h.

#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL

OPAMP Vref = 90% VDDA

Definition at line 369 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Input

Defines
OPAMP Input
OPAMP Private Constants

Defines

#define | OPAMP_INPUT_INVERTING ( 24UL)
#define | OPAMP_INPUT_NONINVERTING ( 19UL)
#define | IS_OPAMP_INPUT(INPUT)

Define Documentation

#define IS_OPAMP_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_INPUT_INVERTING) || \
                               ((INPUT) == OPAMP_INPUT_NONINVERTING))

Definition at line 390 of file stm32g4xx_hal_opamp.h.

#define OPAMP_INPUT_INVERTING ( 24UL)

Inverting input

Definition at line 387 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_INPUT_NONINVERTING ( 19UL)

Non inverting input

Definition at line 388 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_INVERTING_INPUT(INPUT)
#define | IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE)
#define | IS_OPAMP_SEC_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_SEC_INVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_POWERMODE(POWERMODE)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FUL)
#define | IS_OPAMP_VREF(VREF)

Define Documentation

#define IS_OPAMP_FACTORYTRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
                                            ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))

Definition at line 460 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define IS_OPAMP_FUNCTIONAL_NORMALMODE ( INPUT )
Value:
(((INPUT) == OPAMP_STANDALONE_MODE) || \
                                               ((INPUT) == OPAMP_PGA_MODE) || \
                                               ((INPUT) == OPAMP_FOLLOWER_MODE))

Definition at line 407 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_INVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                         ((INPUT) == OPAMP_INVERTINGINPUT_IO1))

Definition at line 417 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_NONINVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC))

Definition at line 411 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGA_GAIN ( GAIN )
Value:
(((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1)   || \
                                 ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3)   || \
                                 ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7)   || \
                                 ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63))

Definition at line 447 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGACONNECT ( CONNECT )
Value:
(((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)            || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0)           || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS)      || \
                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))

Definition at line 442 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_POWERMODE ( POWERMODE )
Value:
(((POWERMODE) == OPAMP_POWERMODE_NORMALSPEED) || \
                                       ((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) )

Definition at line 454 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_SEC_INVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
                                             ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1) || \
                                             ((INPUT) == OPAMP_SEC_INVERTINGINPUT_PGA) || \
                                             ((INPUT) == OPAMP_SEC_INVERTINGINPUT_FOLLOWER))

Definition at line 437 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_SEC_NONINVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3) || \
                                                ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_DAC))

Definition at line 431 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TIMERCONTROLLED_MUXMODE ( MUXMODE )
Value:
((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 |    \
                 OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6))

Definition at line 426 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

Definition at line 457 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FUL)

Definition at line 463 of file stm32g4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_VREF ( VREF )
Value:
(((VREF) == OPAMP_VREF_3VDDA)  || \
                             ((VREF) == OPAMP_VREF_10VDDA) || \
                             ((VREF) == OPAMP_VREF_50VDDA) || \
                             ((VREF) == OPAMP_VREF_90VDDA))

Definition at line 465 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Macros

Defines
OPAMP Exported Macros
OPAMP

Defines

#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.

Define Documentation

#define __HAL_OPAMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

Reset OPAMP handle state.

Parameters:
__HANDLE__ OPAMP handle.
Return values:
None

Definition at line 483 of file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP

Modules | Typedefs | Enumerations | Functions
OPAMP
STM32G4xx_HAL_Driver

OPAMP HAL module driver. More...

Modules

OPAMP Private Define
OPAMP Exported Functions
Peripheral State functions

Peripheral State functions.

OPAMP Exported Types
OPAMP Exported Constants
OPAMP Private Constants

OPAMP Private constants and defines.

OPAMP Private Macros
OPAMP Exported Macros

Typedefs

typedef void(* | pOPAMP_CallbackTypeDef )(OPAMP_HandleTypeDef *hopamp)
HAL OPAMP Callback pointer definition.

Enumerations

enum | HAL_OPAMP_CallbackIDTypeDef { HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, HAL_OPAMP_ALL_CB_ID = 0x03UL }
HAL OPAMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

OPAMP HAL module driver.

Typedef Documentation

typedef void(* pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp)

HAL OPAMP Callback pointer definition.

Definition at line 182 of file stm32g4xx_hal_opamp.h.

Enumeration Type Documentation

enum HAL_OPAMP_CallbackIDTypeDef

HAL OPAMP Callback ID enumeration definition.

Enumerator:
HAL_OPAMP_MSPINIT_CB_ID

OPAMP MspInit Callback ID

HAL_OPAMP_MSPDEINIT_CB_ID

OPAMP MspDeInit Callback ID

HAL_OPAMP_ALL_CB_ID

OPAMP All ID

Definition at line 172 of file stm32g4xx_hal_opamp.h.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_RegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId,
 |  | pOPAMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hopamp | : OPAMP handle
CallbackID : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 1064 of file stm32g4xx_hal_opamp.c.

References HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | HAL_OPAMP_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hopamp : OPAMP handle
CallbackID : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID
  • HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID
  • HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
Return values:
status

Definition at line 1132 of file stm32g4xx_hal_opamp.c.

References HAL_OPAMP_ALL_CB_ID, HAL_OPAMP_MspDeInit(), HAL_OPAMP_MSPDEINIT_CB_ID, HAL_OPAMP_MspInit(), HAL_OPAMP_MSPINIT_CB_ID, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, __OPAMP_HandleTypeDef::MspDeInitCallback, __OPAMP_HandleTypeDef::MspInitCallback, and __OPAMP_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
#define | USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define | USB_CNTRX_BLSIZE (0x1U << 15)
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum)
#define | PCD_EP_RX_CNT(USBx, bEpNum)
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr)
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr)
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(pdwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(pdwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount)
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr)
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr)
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Define Documentation

#define PCD_CALC_BLK2 | ( | pdwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
do { \
    (wNBlocks) = (wCount) >> 1; \
    if (((wCount) & 0x1U) != 0U) \
    { \
      (wNBlocks)++; \
    } \
    *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
  } while(0) /* PCD_CALC_BLK2 */

Definition at line 793 of file stm32g4xx_hal_pcd.h.

#define PCD_CALC_BLK32 | ( | pdwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
do { \
    (wNBlocks) = (wCount) >> 5; \
    if (((wCount) & 0x1fU) == 0U) \
    { \
      (wNBlocks)--; \
    } \
    *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
  } while(0) /* PCD_CALC_BLK32 */

Sets counter of rx buffer with no.

of blocks.

Parameters:
pdwReg | Register pointer
wCount | Counter.
wNBlocks | no. of Blocks.
Return values:
None

Definition at line 783 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_BULK_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 628 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_CLEAR_EP_KIND */

Definition at line 603 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 619 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
    \
    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
    { \
      PCD_RX_DTOG((USBx), (bEpNum)); \
    } \
  } while(0) /* PCD_CLEAR_RX_DTOG */

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 683 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_RX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
  } while(0) /* PCD_CLEAR_RX_EP_CTR */

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 636 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_CLEAR_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
    \
    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
    { \
      PCD_TX_DTOG((USBx), (bEpNum)); \
    } \
  } while(0) /* PCD_CLEAR_TX_DTOG */

Definition at line 695 of file stm32g4xx_hal_pcd.h.

#define PCD_CLEAR_TX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
  } while(0) /* PCD_CLEAR_TX_EP_CTR */

Definition at line 645 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) |
Value:
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
                  ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))

Definition at line 735 of file stm32g4xx_hal_pcd.h.

#define PCD_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) |
Value:
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
                  ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))

Definition at line 731 of file stm32g4xx_hal_pcd.h.

#define PCD_FREE_USER_BUFFER | ( | USBx,
 |  | bEpNum,
 |  | bDir
 | ) |
Value:
do { \
    if ((bDir) == 0U) \
    { \
      /* OUT double buffered endpoint */ \
      PCD_TX_DTOG((USBx), (bEpNum)); \
    } \
    else if ((bDir) == 1U) \
    { \
      /* IN double buffered endpoint */ \
      PCD_RX_DTOG((USBx), (bEpNum)); \
    } \
  } while(0)

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx USB device.
bEpNum,bDir
Return values:
None

Definition at line 459 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_ENDPOINT | ( | USBx,
 |  | bEpNum
 | ) | (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))

Definition at line 429 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))

Gets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 729 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 909 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))

Gets buffer 0/1 rx/tx counter for double buffering.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 972 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 910 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Definition at line 973 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 774 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)

Definition at line 870 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)

Definition at line 586 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)

Definition at line 568 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
address of the buffer.

Definition at line 773 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)

gets counter of the tx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Counter value

Definition at line 869 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_TX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)

checks stall condition in an endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
TRUE = endpoint in stall condition.

Definition at line 585 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)

gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
status

Definition at line 567 of file stm32g4xx_hal_pcd.h.

#define PCD_GET_EPTYPE | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)

gets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Endpoint Type

Definition at line 450 of file stm32g4xx_hal_pcd.h.

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 80 of file stm32g4xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 79 of file stm32g4xx_hal_pcd.c.

#define PCD_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wEPVal; \
    \
    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
  } while(0) /* PCD_RX_DTOG */

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 660 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_BULK_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly EP_KIND bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 627 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_ENDPOINT | ( | USBx,
 |  | bEpNum,
 |  | wRegValue
 | ) | (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))

Definition at line 425 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | bAddr
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_ADDRESS */

Sets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bAddr | Address.
Return values:
None

Definition at line 714 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_CNT_RX_REG | ( | pdwReg,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t wNBlocks; \
    \
    *(pdwReg) &= 0x3FFU; \
    \
    if ((wCount) > 62U) \
    { \
      PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
    } \
    else \
    { \
      if ((wCount) == 0U) \
      { \
        *(pdwReg) |= USB_CNTRX_BLSIZE; \
      } \
      else \
      { \
        PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
      } \
    } \
  } while(0) /* PCD_SET_EP_CNT_RX_REG */

Definition at line 803 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr
 | ) |
Value:
do { \
    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
  } while(0) /* PCD_SET_EP_DBUF0_ADDR */

Sets buffer 0/1 address in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr | buffer 0 address.
Return values:
Counter value

Definition at line 879 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    if ((bDir) == 0U) \
      /* OUT endpoint */ \
    { \
      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
    } \
    else \
    { \
      if ((bDir) == 1U) \
      { \
        /* IN endpoint */ \
        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
      } \
    } \
  } while(0) /* SetEPDblBuf0Count*/

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bDir | endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount,: Counter value
Return values:
None

Definition at line 921 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf1Addr
 | ) |
Value:
do { \
    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
  } while(0) /* PCD_SET_EP_DBUF1_ADDR */

Definition at line 884 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t _wBase = (uint32_t)(USBx); \
    __IO uint16_t *_wEPRegVal; \
    \
    if ((bDir) == 0U) \
    { \
      /* OUT endpoint */ \
      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
    } \
    else \
    { \
      if ((bDir) == 1U) \
      { \
        /* IN endpoint */ \
        _wBase += (uint32_t)(USBx)->BTABLE; \
        _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
        *_wEPRegVal = (uint16_t)(wCount); \
      } \
    } \
  } while(0) /* SetEPDblBuf1Count */

Definition at line 938 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_DBUF_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr,
 |  | wBuf1Addr
 | ) |
Value:
do { \
    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
  } while(0) /* PCD_SET_EP_DBUF_ADDR */

Sets addresses in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr,: buffer 0 address.
wBuf1Addr | = buffer 1 address.
Return values:
None

Definition at line 897 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_DBUF_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  } while(0) /* PCD_SET_EP_DBUF_CNT */

Definition at line 960 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
  } while(0) /* PCD_SET_EP_KIND */

set & clear EP_KIND bit.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 594 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) |
Value:
do { \
    __IO uint16_t *_wRegVal; \
    uint32_t _wRegBase = (uint32_t)USBx; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
    *_wRegVal = ((wAddr) >> 1) << 1; \
  } while(0) /* PCD_SET_EP_RX_ADDRESS */

Definition at line 757 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_RX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t _wRegBase = (uint32_t)(USBx); \
    __IO uint16_t *_wRegVal; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
  } while(0)

Definition at line 853 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t _wRegBase = (uint32_t)(USBx); \
    __IO uint16_t *pdwReg; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
  } while(0)

Definition at line 826 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
    /* toggle first bit ? */ \
    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG1; \
    } \
    /* toggle second bit ? */ \
    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG2; \
    } \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_RX_STATUS */

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 505 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))

Definition at line 577 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) |
Value:
do { \
    __IO uint16_t *_wRegVal; \
    uint32_t _wRegBase = (uint32_t)USBx; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
    *_wRegVal = ((wAddr) >> 1) << 1; \
  } while(0) /* PCD_SET_EP_TX_ADDRESS */

sets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wAddr | address to be set (must be word aligned).
Return values:
None

Definition at line 747 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_TX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t _wRegBase = (uint32_t)(USBx); \
    __IO uint16_t *_wRegVal; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
    *_wRegVal = (uint16_t)(wCount); \
  } while(0)

sets counter for the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wCount | Counter value.
Return values:
None

Definition at line 843 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
    /* toggle first bit ? */ \
    if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG1; \
    } \
    /* toggle second bit ?  */ \
    if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG2; \
    } \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_TX_STATUS */

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 480 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit().

#define PCD_SET_EP_TX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))

sets directly the VALID tx/rx-status into the endpoint register

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 576 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EP_TXRX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wStaterx,
 |  | wStatetx
 | ) |
Value:
do { \
    uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
    /* toggle first bit ? */ \
    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG1; \
    } \
    /* toggle second bit ? */ \
    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG2; \
    } \
    /* toggle first bit ? */ \
    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG1; \
    } \
    /* toggle second bit ?  */ \
    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG2; \
    } \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_TXRX_STATUS */

sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wStaterx | new state.
wStatetx | new state.
Return values:
None

Definition at line 531 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_EPTYPE | ( | USBx,
 |  | bEpNum,
 |  | wType
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                    ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))

sets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wType | Endpoint Type.
Return values:
None

Definition at line 439 of file stm32g4xx_hal_pcd.h.

#define PCD_SET_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly STATUS_OUT bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 618 of file stm32g4xx_hal_pcd.h.

#define PCD_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    uint16_t _wEPVal; \
    \
    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
  } while(0) /* PCD_TX_DTOG */

Definition at line 669 of file stm32g4xx_hal_pcd.h.

#define USB_CNTRX_BLSIZE (0x1U << 15)

Definition at line 422 of file stm32g4xx_hal_pcd.h.

#define USB_CNTRX_NBLK_MSK (0x1FU << 10)

Definition at line 421 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
static HAL_StatusTypeDef | HAL_PCD_EP_DB_Transmit (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk IN transaction from ISR.
static uint16_t | HAL_PCD_EP_DB_Receive (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk out transaction from ISR.

Function Documentation

static uint16_t HAL_PCD_EP_DB_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_EPTypeDef * | ep,
 |  | uint16_t | wEPVal
 | ) |  | [static]

Manage double buffer bulk out transaction from ISR.

Parameters:
hpcd | PCD handle
ep | current endpoint handle
wEPVal | Last snapshot of EPRx register value taken in ISR
Return values:
HAL status

Definition at line 1987 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, PCD_FREE_USER_BUFFER, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, and PCD_SET_EP_RX_STATUS.

Referenced by PCD_EP_ISR_Handler().

static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_EPTypeDef * | ep,
 |  | uint16_t | wEPVal
 | ) |  | [static]

Manage double buffer bulk IN transaction from ISR.

Parameters:
hpcd | PCD handle
ep | current endpoint handle
wEPVal | Last snapshot of EPRx register value taken in ISR
Return values:
HAL status

Definition at line 2068 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, HAL_PCD_DataInStageCallback(), __PCD_HandleTypeDef::Instance, PCD_FREE_USER_BUFFER, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, PCD_SET_EP_DBUF0_CNT, PCD_SET_EP_DBUF1_CNT, and PCD_SET_EP_TX_STATUS.

Referenced by PCD_EP_ISR_Handler().

static HAL_StatusTypeDef PCD_EP_ISR_Handler ( PCD_HandleTypeDef * hpcd ) [static]

This function handles PCD Endpoint interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1708 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), HAL_PCD_SetupStageCallback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_EP_CTR, PCD_CLEAR_TX_EP_CTR, PCD_ENDP0, PCD_FREE_USER_BUFFER, PCD_GET_ENDPOINT, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, PCD_GET_EP_RX_CNT, PCD_GET_EP_TX_CNT, PCD_SET_EP_DBUF0_CNT, PCD_SET_EP_DBUF1_CNT, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, __PCD_HandleTypeDef::Setup, __PCD_HandleTypeDef::SetupStageCallback, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL USB OTG PCD Callback ID enumeration definition

Enumerations
HAL USB OTG PCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback ID enumeration definition. More...

Enumerations

enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Detailed Description

HAL USB OTG PCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_PCD_CallbackIDTypeDef
Enumerator:
HAL_PCD_SOF_CB_ID

USB PCD SOF callback ID

HAL_PCD_SETUPSTAGE_CB_ID

USB PCD Setup Stage callback ID

HAL_PCD_RESET_CB_ID

USB PCD Reset callback ID

HAL_PCD_SUSPEND_CB_ID

USB PCD Suspend callback ID

HAL_PCD_RESUME_CB_ID

USB PCD Resume callback ID

HAL_PCD_CONNECT_CB_ID

USB PCD Connect callback ID

HAL_PCD_DISCONNECT_CB_ID

USB PCD Disconnect callback ID

HAL_PCD_MSPINIT_CB_ID

USB PCD MspInit callback ID

HAL_PCD_MSPDEINIT_CB_ID

USB PCD MspDeInit callback ID

Definition at line 230 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL USB OTG PCD Callback pointer definition

Typedefs
HAL USB OTG PCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback pointer definition. More...

Typedefs

typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Detailed Description

HAL USB OTG PCD Callback pointer definition.

Typedef Documentation

typedef void(* pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

pointer to USB OTG PCD BCD callback

Definition at line 259 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd)

pointer to a common USB OTG PCD callback function

Definition at line 253 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data IN Stage callback

Definition at line 255 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data OUT Stage callback

Definition at line 254 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO IN Incomplete callback

Definition at line 257 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO OUT Incomplete callback

Definition at line 256 of file stm32g4xx_hal_pcd.h.

typedef void(* pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

pointer to USB OTG PCD LPM callback

Definition at line 258 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG PCD Callback ID enumeration definition

HAL USB OTG PCD Callback ID enumeration definition.

HAL USB OTG PCD Callback pointer definition

HAL USB OTG PCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 219 of file stm32g4xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::MspDeInitCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 124 of file stm32g4xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::DisconnectCallback, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_MspInit(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SuspendCallback(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::ISOINIncompleteCallback, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, __PCD_HandleTypeDef::Lock, __PCD_HandleTypeDef::LPMCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::OUT_ep, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, __PCD_HandleTypeDef::SuspendCallback, and __PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 273 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_DeInit(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 258 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_BcdCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD BCD Callback function
Return values:
HAL status

Definition at line 812 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID,
 |  | pPCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB PCD Callback To be used instead of the weak predefined callback.

Parameters:
hpcd | USB PCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 302 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_RESUME_CB_ID, HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SOF_CB_ID, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataInStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data IN Stage Callback function
Return values:
HAL status

Definition at line 588 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataOutStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data OUT Stage Callback function
Return values:
HAL status

Definition at line 514 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoInIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso IN incomplete Callback function
Return values:
HAL status

Definition at line 737 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoOutIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso OUT incomplete Callback function
Return values:
HAL status

Definition at line 662 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_LpmCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD LPM Callback function
Return values:
HAL status

Definition at line 885 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 852 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_BCD_Callback(), and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.

Parameters:
hpcd USB PCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 415 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_ConnectCallback(), HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_DisconnectCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MspDeInit(), HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MspInit(), HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_ResetCallback(), HAL_PCD_RESUME_CB_ID, HAL_PCD_ResumeCallback(), HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SetupStageCallback(), HAL_PCD_SOF_CB_ID, HAL_PCD_SOFCallback(), HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, HAL_PCD_SuspendCallback(), __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 629 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataInStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 555 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataOutStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 779 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 704 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 925 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1294 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1170 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_EP_DB_Transmit(), HAL_PCD_Init(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1153 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1309 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1007 of file stm32g4xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __PCD_HandleTypeDef::BESL, HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetAddress(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, __PCD_HandleTypeDef::LPM_State, __PCD_HandleTypeDef::LPMCallback, PCD_EP_ISR_Handler(), PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SOFCallback, and __PCD_HandleTypeDef::SuspendCallback.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1278 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1261 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1215 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1245 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1185 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1200 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 976 of file stm32g4xx_hal_pcd.c.

References __HAL_PCD_ENABLE, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 991 of file stm32g4xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and __PCD_HandleTypeDef::Instance.

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1230 of file stm32g4xx_hal_pcd.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1645 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1655 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1343 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1357 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Abort | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Abort an USB EP transaction.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1596 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1429 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1560 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1622 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

uint32_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef const * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
Data Size

Definition at line 1484 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_mps | endpoint max packet size
ep_type | endpoint type
Return values:
HAL status

Definition at line 1389 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the reception buffer
len | amount of data to be received
Return values:
HAL status

Definition at line 1460 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1522 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the transmission buffer
len | amount of data to be sent
Return values:
HAL status

Definition at line 1496 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd | PCD handle
address | new device address
Return values:
HAL status

Definition at line 1372 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef const *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef const * hpcd )

Return the PCD handle state.

Parameters:
hpcd PCD handle
Return values:
HAL state

Definition at line 1684 of file stm32g4xx_hal_pcd.c.

References __PCD_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Typedef Documentation

typedef USB_EPTypeDef PCD_EPTypeDef

Definition at line 89 of file stm32g4xx_hal_pcd.h.

typedef struct __PCD_HandleTypeDef PCD_HandleTypeDef

PCD Handle Structure definition.

typedef USB_CfgTypeDef PCD_InitTypeDef

Definition at line 88 of file stm32g4xx_hal_pcd.h.

typedef USB_TypeDef PCD_TypeDef

Definition at line 87 of file stm32g4xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 72 of file stm32g4xx_hal_pcd.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 66 of file stm32g4xx_hal_pcd.h.

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 58 of file stm32g4xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 48 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32g4xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [8]
PCD_EPTypeDef | OUT_ep [8]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData
void(* | SOFCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SetupStageCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResetCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SuspendCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResumeCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ConnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DisconnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DataOutStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | DataInStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOOUTIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOINIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | BCDCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
void(* | LPMCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
void(* | MspInitCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | MspDeInitCallback )(struct __PCD_HandleTypeDef *hpcd)

Detailed Description

PCD Handle Structure definition.

Definition at line 96 of file stm32g4xx_hal_pcd.h.

Field Documentation

uint32_t __PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 117 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

void(* __PCD_HandleTypeDef::BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

USB OTG PCD BCD callback

Definition at line 134 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t __PCD_HandleTypeDef::BESL

Definition at line 111 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

void(* __PCD_HandleTypeDef::ConnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Connect callback

Definition at line 127 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data IN Stage callback

Definition at line 131 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), HAL_PCD_Init(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data OUT Stage callback

Definition at line 130 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Disconnect callback

Definition at line 128 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint32_t __PCD_HandleTypeDef::ErrorCode

PCD Error code

Definition at line 108 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::IN_ep[8]

IN endpoint parameters

Definition at line 104 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

PCD_InitTypeDef __PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 102 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_ClrStall(), HAL_PCD_EP_SetStall(), and HAL_PCD_Init().

PCD_TypeDef* __PCD_HandleTypeDef::Instance

Register base address

Definition at line 101 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DeInit(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO IN Incomplete callback

Definition at line 133 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoInIncpltCallback(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void(* __PCD_HandleTypeDef::ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO OUT Incomplete callback

Definition at line 132 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

HAL_LockTypeDef __PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 106 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t __PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 114 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef __PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 110 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

void(* __PCD_HandleTypeDef::LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

USB OTG PCD LPM callback

Definition at line 135 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterLpmCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp DeInit callback

Definition at line 138 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::MspInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp Init callback

Definition at line 137 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::OUT_ep[8]

OUT endpoint parameters

Definition at line 105 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

void* __PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 119 of file stm32g4xx_hal_pcd.h.

void(* __PCD_HandleTypeDef::ResetCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Reset callback

Definition at line 124 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::ResumeCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Resume callback

Definition at line 126 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

uint32_t __PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 109 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Setup Stage callback

Definition at line 123 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SOFCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD SOF callback

Definition at line 122 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO PCD_StateTypeDef __PCD_HandleTypeDef::State

PCD communication state

Definition at line 107 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::SuspendCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Suspend callback

Definition at line 125 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint8_t __PCD_HandleTypeDef::USB_Address

USB Address

Definition at line 103 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_SetAddress(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_pcd.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define PCD_SPEED_FULL USBD_FS_SPEED

Define Documentation

#define PCD_SPEED_FULL USBD_FS_SPEED

Definition at line 157 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 166 of file stm32g4xx_hal_pcd.h.

#define PCD_PHY_ULPI 1U

Definition at line 165 of file stm32g4xx_hal_pcd.h.

#define PCD_PHY_UTMI 3U

Definition at line 167 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Error Code definition

Defines
PCD Error Code definition
PCD Exported Constants

PCD Error Code definition. More...

Defines

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

PCD Error Code definition.

Define Documentation

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 177 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->ISTR)\
                                                                   &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 200 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 194 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 193 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 196 of file stm32g4xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)

Definition at line 204 of file stm32g4xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE

Definition at line 203 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define USB_WAKEUP_EXTI_LINE (0x1U << 18)

Define Documentation

#define USB_WAKEUP_EXTI_LINE (0x1U << 18)

USB FS EXTI Line WakeUp Interrupt

Definition at line 369 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD EP0 MPS

Defines
PCD EP0 MPS
PCD Private Constants

Defines

#define | PCD_EP0MPS_64 EP_MPS_64
#define | PCD_EP0MPS_32 EP_MPS_32
#define | PCD_EP0MPS_16 EP_MPS_16
#define | PCD_EP0MPS_08 EP_MPS_8

Define Documentation

#define PCD_EP0MPS_08 EP_MPS_8

Definition at line 382 of file stm32g4xx_hal_pcd.h.

#define PCD_EP0MPS_16 EP_MPS_16

Definition at line 381 of file stm32g4xx_hal_pcd.h.

#define PCD_EP0MPS_32 EP_MPS_32

Definition at line 380 of file stm32g4xx_hal_pcd.h.

#define PCD_EP0MPS_64 EP_MPS_64

Definition at line 379 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD ENDP

Defines
PCD ENDP
PCD Private Constants

Defines

#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U

Define Documentation

#define PCD_ENDP0 0U

Definition at line 390 of file stm32g4xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_ENDP1 1U

Definition at line 391 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP2 2U

Definition at line 392 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP3 3U

Definition at line 393 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP4 4U

Definition at line 394 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP5 5U

Definition at line 395 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP6 6U

Definition at line 396 of file stm32g4xx_hal_pcd.h.

#define PCD_ENDP7 7U

Definition at line 397 of file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Endpoint Kind

Defines
PCD Endpoint Kind
PCD Private Constants

Defines

#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U

Define Documentation

#define PCD_DBL_BUF 1U

Definition at line 406 of file stm32g4xx_hal_pcd.h.

#define PCD_SNG_BUF 0U

Definition at line 405 of file stm32g4xx_hal_pcd.h.

Referenced by HAL_PCDEx_PMAConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 122 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 251 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::lpm_active, LPM_L0, and __PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 306 of file stm32g4xx_hal_pcd_ex.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 159 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::BCDCallback, HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_DeActivateBCD(), __PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 143 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

Deactivate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 269 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 289 of file stm32g4xx_hal_pcd_ex.c.

References UNUSED.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterLpmCallback().

HAL_StatusTypeDef HAL_PCDEx_PMAConfig | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | ep_addr,
 |  | uint16_t | ep_kind,
 |  | uint32_t | pmaadress
 | ) |  |

Configure PMA for EP.

Parameters:
hpcd | Device instance
ep_addr | endpoint address
ep_kind | endpoint Kind USB_SNG_BUF: Single Buffer used USB_DBL_BUF: Double Buffer used
pmaadress,: EP address in The PMA: In case of single buffer endpoint this parameter is 16-bit value providing the address in PMA allocated to endpoint. In case of double buffer endpoint this parameter is a 32-bit value providing the endpoint buffer 0 address in the LSB part of 32-bit value and endpoint buffer 1 address in the MSB part of 32-bit value.
Return values:
HAL status

Definition at line 80 of file stm32g4xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::OUT_ep, and PCD_SNG_BUF.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Defines

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)

Define Documentation

#define PVD_FALLING_EDGE ((uint32_t)0x00000002)

Mask for falling edge set as PVD trigger

Definition at line 51 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT ((uint32_t)0x00020000)

Mask for event yielded by PVD threshold crossing

Definition at line 49 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT ((uint32_t)0x00010000)

Mask for interruption yielded by PVD threshold crossing

Definition at line 48 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE ((uint32_t)0x00000001)

Mask for rising edge set as PVD trigger

Definition at line 50 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 86 of file stm32g4xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain (RTC registers, RTC backup data registers).

Return values:
None

Definition at line 114 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC registers, RTC backup data registers).

Note:
After reset, the backup domain is protected against possible unwanted write accesses.
RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. In order to set or modify the RTC clock, the backup domain access must be disabled.
LSEON bit that switches on and off the LSE crystal belongs as well to the back-up domain.
Return values:
None

Definition at line 104 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

     [..]
     *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).

      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
          The polarity of these pins can be set to configure event detection on high
          level (rising edge) or low level (falling edge).

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 8 low-power modes:
      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.

   *** Low-power run mode ***
   ==========================
    [..]
      (+) Entry: (from main run mode)
        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.

      (+) Exit:
        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
             then can the system clock frequency be increased above 2 MHz.

   *** Sleep mode / Low-power sleep mode ***
   =========================================
    [..]
      (+) Entry:
          The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) WFI Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) or any wake-up event.

      (+) WFE Exit:
        (++) Any wake-up event such as an EXTI line configured in event mode.

         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
             the MCU is in Low-power Run mode.

   *** Stop 0, Stop 1 modes ***
   ===============================
    [..]
      (+) Entry:
          The Stop 0, Stop 1 modes are entered through the following API's:
          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
          (++) PWR_MAINREGULATOR_ON
          (++) PWR_LOWPOWERREGULATOR_ON
      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction

      (+) WFI Exit:
          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
               when programmed in wakeup mode.
      (+) WFE Exit:
          (++) Any EXTI Line (Internal or External) configured in Event mode.

       [..]
          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
          depending on the LPR bit setting.

   *** Standby mode ***
   ====================
     [..]
      The Standby mode offers two options:
      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
        and Standby circuitry.
      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
        SRAM and register contents are lost except for the RTC registers, RTC backup registers
        and Standby circuitry.

      (++) Entry:
          (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
                SRAM1 and register contents are lost except for registers in the Backup domain and
                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
                to set RRS bit.

      (++) Exit:
          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
                external reset in NRST pin, IWDG reset.

      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.

    *** Shutdown mode ***
   ======================
     [..]
      In Shutdown mode,
        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
        SRAM and registers contents are lost except for backup domain registers.

      (+) Entry:
          The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.

      (+) Exit:
          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
               external reset in NRST pin.

         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wakeup mode).

      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes

        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to configure the RTC to detect the tamper or time stamp event using the
             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.

        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

HAL_StatusTypeDef HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the voltage threshold detected by the Power Voltage Detector (PVD).

Parameters:
sConfigPVD,: pointer to a PWR_PVDTypeDef structure that contains the PVD configuration information.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level.
Return values:
None

Definition at line 308 of file stm32g4xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 363 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disable CORTEX M4 SEVONPEND bit.

Note:
Clear SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 615 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 588 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
Return values:
None

Definition at line 409 of file stm32g4xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 354 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enable CORTEX M4 SEVONPEND bit.

Note:
Set SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 602 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 575 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity,: Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values which set the default polarity i.e. detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
or one of the following value where the user can explicitly specify the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 388 of file stm32g4xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_WUP_POLARITY_SHIFT.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter Sleep or Low-power Sleep mode.

Note:
In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator,: Specifies the regulator state in Sleep/Low-power Sleep mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
  • PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
Note:
Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWR_EnterSLEEPMode() API.
When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
Parameters:
SLEEPEntry,: Specifies if Sleep mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
  • PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
Note:
When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source.
Return values:
None

Definition at line 441 of file stm32g4xx_hal_pwr.c.

References assert_param, HAL_PWREx_DisableLowPowerRunMode(), HAL_PWREx_EnableLowPowerRunMode(), IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR_MAINREGULATOR_ON, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter Standby mode.

Note:
In Standby mode, the PLL, the HSI and the HSE oscillators are switched off. The voltage regulator is disabled, except when SRAM2 content is preserved in which case the regulator is in low-power mode. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. The BOR is available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the same. These states are effective in Standby mode only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
Return values:
None

Definition at line 549 of file stm32g4xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter Stop mode.

Note:
This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running on devices where only "Stop mode" is mentioned with main or low power regulator ON.
In Stop mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available. The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode (Stop 1), an additional startup delay is incurred when waking up. By keeping the internal regulator ON during Stop mode (Stop 0), the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
  • PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
STOPEntry,: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
  • PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
Return values:
None

Definition at line 516 of file stm32g4xx_hal_pwr.c.

References assert_param, HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), IS_PWR_REGULATOR, and PWR_LOWPOWERREGULATOR_ON.

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 629 of file stm32g4xx_hal_pwr.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32g4xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 47 of file stm32g4xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD interrupt and event mode.

Definition at line 52 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of Programmable Voltage Detection levels.

Definition at line 49 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_pwr.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Programmable Voltage Detection levels

Defines
Programmable Voltage Detection levels
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0

PVD threshold around 2.0 V

Definition at line 71 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1

PVD threshold around 2.2 V

Definition at line 72 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2

PVD threshold around 2.4 V

Definition at line 73 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3

PVD threshold around 2.5 V

Definition at line 74 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4

PVD threshold around 2.6 V

Definition at line 75 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5

PVD threshold around 2.8 V

Definition at line 76 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6

PVD threshold around 2.9 V

Definition at line 77 of file stm32g4xx_hal_pwr.h.

#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7

External input analog voltage (compared internally to VREFINT)

Definition at line 78 of file stm32g4xx_hal_pwr.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVD interrupt and event mode

Defines
PWR PVD interrupt and event mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)

Event Mode with Falling edge trigger detection

Definition at line 91 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)

Event Mode with Rising edge trigger detection

Definition at line 90 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Event Mode with Rising/Falling edge trigger detection

Definition at line 92 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)

External Interrupt Mode with Falling edge trigger detection

Definition at line 88 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)

External Interrupt Mode with Rising edge trigger detection

Definition at line 87 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 89 of file stm32g4xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)

Basic mode is used

Definition at line 86 of file stm32g4xx_hal_pwr.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR regulator mode

Defines
PWR regulator mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Regulator in low-power mode

Definition at line 104 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)

Regulator in main mode

Definition at line 103 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Sleep mode

Definition at line 113 of file stm32g4xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Sleep mode

Definition at line 112 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Stop mode

Definition at line 122 of file stm32g4xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Stop mode

Definition at line 121 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), and HAL_PWREx_EnterSTOP1Mode().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVD external interrupt line

Defines
PWR PVD external interrupt line
PWR Exported Constants

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 131 of file stm32g4xx_hal_pwr.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVD event line

Defines
PWR PVD event line
PWR Exported Constants

Defines

#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)

Define Documentation

#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)

Event line 16 Connected to the PVD Event Line

Definition at line 139 of file stm32g4xx_hal_pwr.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Macros

Defines
PWR Exported Macros
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ )
Value:
( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
                                         (PWR->SCR  = (__FLAG__)) :\
                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )

Clear a specific PWR flag.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_WU Encompasses all five Wake Up Flags.
  • PWR_FLAG_SB Standby Flag. Indicates that the system entered Standby mode.
Return values:
None

Definition at line 215 of file stm32g4xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )

Check whether or not a specific PWR flag is set.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_SB StandBy Flag. Indicates that the system entered StandBy mode.
  • PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on the internal wakeup line.
  • PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the low-power regulator is ready.
  • PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the regulator is ready in main mode or is in low-power mode.
  • PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready in the selected voltage range or is still changing to the required voltage level.
  • PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below or above the selected PVD threshold.
  • PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is is below or above PVM3 threshold.
  • PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is is below or above PVM4 threshold.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 193 of file stm32g4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI interrupt flag.

Return values:
None

Definition at line 304 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Disable the PVD Event Line.

Return values:
None

Definition at line 240 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 265 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 228 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 252 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 282 of file stm32g4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Enable the PVD Event Line.

Return values:
None

Definition at line 234 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 258 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 222 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 246 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                   \
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 272 of file stm32g4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 292 of file stm32g4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR1 & PWR_EXTI_LINE_PVD)

Check whether or not the PVD EXTI interrupt flag is set.

Return values:
EXTI PVD Line Status.

Definition at line 298 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 316 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))

Definition at line 321 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 329 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 332 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Definition at line 334 of file stm32g4xx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), and HAL_PWREx_EnterSTOP1Mode().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVM Mode Mask

Defines
PWR PVM Mode Mask
PWR Extended Private Defines

Defines

#define | PVM_MODE_IT 0x00010000U
#define | PVM_MODE_EVT 0x00020000U
#define | PVM_RISING_EDGE 0x00000001U
#define | PVM_FALLING_EDGE 0x00000002U

Define Documentation

#define PVM_FALLING_EDGE 0x00000002U

Mask for falling edge set as PVM trigger

Definition at line 60 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_EVT 0x00020000U

Mask for event yielded by PVM threshold crossing

Definition at line 58 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_IT 0x00010000U

Mask for interruption yielded by PVM threshold crossing

Definition at line 57 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_RISING_EDGE 0x00000001U

Mask for rising edge set as PVM trigger

Definition at line 59 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Flag Setting Time Out Value

Defines
PWR Extended Flag Setting Time Out Value
PWR Extended Private Defines

Defines

#define PWR_FLAG_SETTING_DELAY_US 50UL

Define Documentation

#define PWR_FLAG_SETTING_DELAY_US 50UL

Time out value for REGLPF and VOSF flags setting

Definition at line 68 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_DisableLowPowerRunMode().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
PWR Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.
void | HAL_PWREx_EnableUCPDStandbyMode (void)
Enable UCPD configuration memorization in Standby.
void | HAL_PWREx_DisableUCPDStandbyMode (void)
Disable UCPD configuration memorization in Standby.
void | HAL_PWREx_EnableUCPDDeadBattery (void)
Enable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.
void | HAL_PWREx_DisableUCPDDeadBattery (void)
Disable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ConfigPVM ( PWR_PVMTypeDef * sConfigPVM )

Configure the Peripheral Voltage Monitoring (PVM).

Parameters:
sConfigPVM,: pointer to a PWR_PVMTypeDef structure that contains the PVM configuration information.
Note:
The API configures a single PVM according to the information contained in the input structure. To configure several PVMs, the API must be singly called for each PVM used.
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level and to each monitored supply.
Return values:
HAL status

Definition at line 674 of file stm32g4xx_hal_pwr_ex.c.

References __HAL_PWR_PVM1_EXTI_DISABLE_EVENT, __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_DISABLE_IT, __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_EVENT, __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_IT, __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM2_EXTI_DISABLE_EVENT, __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM2_EXTI_DISABLE_IT, __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM2_EXTI_ENABLE_EVENT, __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM2_EXTI_ENABLE_IT, __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_EVENT, __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_IT, __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_EVENT, __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_IT, __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM4_EXTI_DISABLE_EVENT, __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM4_EXTI_DISABLE_IT, __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM4_EXTI_ENABLE_EVENT, __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM4_EXTI_ENABLE_IT, __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVM_MODE, IS_PWR_PVM_TYPE, PWR_PVMTypeDef::Mode, PVM_FALLING_EDGE, PVM_MODE_EVT, PVM_MODE_IT, PVM_RISING_EDGE, PWR_PVMTypeDef::PVMType, PWR_PVM_1, PWR_PVM_2, PWR_PVM_3, and PWR_PVM_4.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage.

Parameters:
VoltageScaling,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, typical output voltage at 1.28 V, system frequency up to 170 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 150 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
Note:
When moving from Range 1 to Range 2, the system frequency must be decreased to a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1, the system frequency can be increased to a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
When moving from Range 2 to Range 1, the API waits for VOSF flag to be cleared before returning the status. If the flag is not cleared within 50 microseconds, HAL_TIMEOUT status is reported.
Return values:
HAL Status

Definition at line 153 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_VOLTAGE_SCALING_RANGE, PWR_FLAG_SETTING_DELAY_US, PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE1_BOOST, and PWR_REGULATOR_VOLTAGE_SCALE2.

void HAL_PWREx_DisableBatteryCharging ( void )

Disable battery charging.

Return values:
None

Definition at line 254 of file stm32g4xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Note:
Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O in pull-down state in Standby and Shutdown modes.
Even if a PDy bit to reset is reserved, the other PDy bits entered as input parameter at the same time are reset.
Parameters:
GPIO,: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 485 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_10, PWR_GPIO_BIT_13, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_PORTF_AVAILABLE_PINS, and PWR_PORTG_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby mode and Shutdown modes.

Note:
Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O in pull-up state in Standby and Shutdown modes.
Even if a PUy bit to reset is reserved, the other PUy bits entered as input parameter at the same time are reset.
Parameters:
GPIO,: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 363 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_14, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_PORTF_AVAILABLE_PINS, and PWR_PORTG_AVAILABLE_PINS.

void HAL_PWREx_DisableInternalWakeUpLine ( void )

Disable Internal Wake-up Line.

Return values:
None

Definition at line 274 of file stm32g4xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode ( void )

Exit Low-power Run mode.

Note:
Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system clock frequency can then be increased above 2 MHz.
Return values:
HAL Status

Definition at line 850 of file stm32g4xx_hal_pwr_ex.c.

References PWR_FLAG_SETTING_DELAY_US.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_DisablePullUpPullDownConfig ( void )

Disable pull-up and pull-down configuration.

Note:
When APC bit is cleared, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
Return values:
None

Definition at line 547 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_DisablePVM1 ( void )

Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.

Return values:
None

Definition at line 594 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_DisablePVM2 ( void )

Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.

Return values:
None

Definition at line 615 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_2.

void HAL_PWREx_DisablePVM3 ( void )

Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.

Return values:
None

Definition at line 635 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_DisablePVM4 ( void )

Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.

Return values:
None

Definition at line 654 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_4.

void HAL_PWREx_DisableSRAM2ContentRetention ( void )

Disable SRAM2 content retention in Standby mode.

Note:
When RRS bit is reset, SRAM2 is powered off in Standby mode and its content is lost.
Return values:
None

Definition at line 572 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_DisableUCPDDeadBattery ( void )

Disable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.

Note:
After exiting reset, the USB Type-C dead battery behavior will be enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable).
Return values:
None

Definition at line 1157 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_DisableUCPDStandbyMode ( void )

Disable UCPD configuration memorization in Standby.

Note:
This function must be called on exiting the Standby mode and before any UCPD configuration update.
Return values:
None

Definition at line 1127 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorSelection )

Enable battery charging.

When VDD is present, charge the external battery on VBAT through an internal resistor.

Parameters:
ResistorSelection,: specifies the resistor impedance. This parameter can be one of the following values:
  • PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
Return values:
None

Definition at line 238 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Note:
Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in pull-down state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
Even if a PDy bit to set is reserved, the other PDy bits entered as input parameter at the same time are set.
Parameters:
GPIO,: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 424 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_10, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_PORTF_AVAILABLE_PINS, and PWR_PORTG_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Note:
Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in pull-up state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
Even if a PUy bit to set is reserved, the other PUy bits entered as input parameter at the same time are set.
Parameters:
GPIO,: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 302 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_10, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_PORTF_AVAILABLE_PINS, and PWR_PORTG_AVAILABLE_PINS.

void HAL_PWREx_EnableInternalWakeUpLine ( void )

Enable Internal Wake-up Line.

Return values:
None

Definition at line 264 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableLowPowerRunMode ( void )

Enter Low-power Run mode.

Note:
In Low-power Run mode, all I/O pins keep the same state as in Run mode.
When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
Return values:
None

Definition at line 835 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_EnablePullUpPullDownConfig ( void )

Enable pull-up and pull-down configuration.

Note:
When APC bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict when setting PUy or PDy bit.
Return values:
None

Definition at line 535 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnablePVM1 ( void )

Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.

Return values:
None

Definition at line 585 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_EnablePVM2 ( void )

Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.

Return values:
None

Definition at line 606 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_2.

void HAL_PWREx_EnablePVM3 ( void )

Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.

Return values:
None

Definition at line 626 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_EnablePVM4 ( void )

Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.

Return values:
None

Definition at line 645 of file stm32g4xx_hal_pwr_ex.c.

References PWR_PVM_4.

void HAL_PWREx_EnableSRAM2ContentRetention ( void )

Enable SRAM2 content retention in Standby mode.

Note:
When RRS bit is set, SRAM2 is powered by the low-power regulator in Standby mode and its content is kept.
Return values:
None

Definition at line 560 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableUCPDDeadBattery ( void )

Enable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.

Return values:
None

Definition at line 1141 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableUCPDStandbyMode ( void )

Enable UCPD configuration memorization in Standby.

Return values:
None

Definition at line 1115 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnterSHUTDOWNMode ( void )

Enter Shutdown mode.

Note:
In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched off. The voltage regulator is disabled and Vcore domain is powered off. SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. The BOR is not available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
Return values:
None

Definition at line 986 of file stm32g4xx_hal_pwr_ex.c.

void HAL_PWREx_EnterSTOP0Mode ( uint8_t STOPEntry )

Enter Stop 0 mode.

Note:
In Stop 0 mode, main and low voltage regulators are ON.
In Stop 0 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the HSI oscillator is selected if STOPWUCK is cleared.
By keeping the internal regulator ON during Stop 0 mode, the consumption is higher although the startup time is reduced.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 894 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

void HAL_PWREx_EnterSTOP1Mode ( uint8_t STOPEntry )

Enter Stop 1 mode.

Note:
In Stop 1 mode, only low power voltage regulator is ON.
In Stop 1 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set.
Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 945 of file stm32g4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

uint32_t HAL_PWREx_GetVoltageRange ( void )

Return Voltage Scaling Range.

Return values:
VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)

Definition at line 109 of file stm32g4xx_hal_pwr_ex.c.

References PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE1_BOOST, and PWR_REGULATOR_VOLTAGE_SCALE2.

void HAL_PWREx_PVD_PVM_IRQHandler ( void )

This function handles the PWR PVD/PVMx interrupt request.

Note:
This API should be called under the PVD_PVM_IRQHandler().
Return values:
None

Definition at line 1011 of file stm32g4xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, __HAL_PWR_PVM1_EXTI_CLEAR_FLAG, __HAL_PWR_PVM1_EXTI_GET_FLAG, __HAL_PWR_PVM2_EXTI_CLEAR_FLAG, __HAL_PWR_PVM2_EXTI_GET_FLAG, __HAL_PWR_PVM3_EXTI_CLEAR_FLAG, __HAL_PWR_PVM3_EXTI_GET_FLAG, __HAL_PWR_PVM4_EXTI_CLEAR_FLAG, __HAL_PWR_PVM4_EXTI_GET_FLAG, HAL_PWR_PVDCallback(), HAL_PWREx_PVM1Callback(), HAL_PWREx_PVM2Callback(), HAL_PWREx_PVM3Callback(), and HAL_PWREx_PVM4Callback().

void HAL_PWREx_PVM1Callback ( void )

PWR PVM1 interrupt callback.

Return values:
None

Definition at line 1067 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM2Callback ( void )

PWR PVM2 interrupt callback.

Return values:
None

Definition at line 1080 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM3Callback ( void )

PWR PVM3 interrupt callback.

Return values:
None

Definition at line 1092 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM4Callback ( void )

PWR PVM4 interrupt callback.

Return values:
None

Definition at line 1103 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR_PVMTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVMTypeDef Struct Reference
PWR Extended Exported Types

PWR PVM configuration structure definition. More...

#include <stm32g4xx_hal_pwr_ex.h>

Data Fields

uint32_t | PVMType
uint32_t | Mode

Detailed Description

PWR PVM configuration structure definition.

Definition at line 49 of file stm32g4xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVMTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVM interrupt and event mode.

Definition at line 53 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

uint32_t PWR_PVMTypeDef::PVMType

PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of Peripheral Voltage Monitoring type.

Definition at line 51 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_pwr_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants

Defines
Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR Extended Exported Constants

Defines

#define PWR_WUP_POLARITY_SHIFT 0x05U

Define Documentation

#define PWR_WUP_POLARITY_SHIFT 0x05U

Internal constant used to retrieve wakeup pin polariry

Definition at line 70 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWR_EnableWakeUpPin().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR wake-up pins

Defines
PWR wake-up pins
PWR Extended Exported Constants

Defines

#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 79 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 84 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)

Wakeup pin 1 (with low level polarity)

Definition at line 89 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 80 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 85 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)

Wakeup pin 2 (with low level polarity)

Definition at line 90 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 81 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 86 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)

Wakeup pin 3 (with low level polarity)

Definition at line 91 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 82 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 87 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)

Wakeup pin 4 (with low level polarity)

Definition at line 92 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 83 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 88 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Wakeup pin 5 (with low level polarity)

Definition at line 93 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Voltage Monitoring type

Defines
Peripheral Voltage Monitoring type
PWR Extended Exported Constants

Defines

#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_2 PWR_CR2_PVME2
#define | PWR_PVM_3 PWR_CR2_PVME3
#define | PWR_PVM_4 PWR_CR2_PVME4

Define Documentation

#define PWR_PVM_1 PWR_CR2_PVME1

Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported)

Definition at line 102 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM1(), and HAL_PWREx_EnablePVM1().

#define PWR_PVM_2 PWR_CR2_PVME2

Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device)

Definition at line 105 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM2(), and HAL_PWREx_EnablePVM2().

#define PWR_PVM_3 PWR_CR2_PVME3

Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V

Definition at line 107 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM3(), and HAL_PWREx_EnablePVM3().

#define PWR_PVM_4 PWR_CR2_PVME4

Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V

Definition at line 108 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM4(), and HAL_PWREx_EnablePVM4().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVM interrupt and event mode

Defines
PWR PVM interrupt and event mode
PWR Extended Exported Constants

Defines

#define | PWR_PVM_MODE_NORMAL 0x00000000U
#define | PWR_PVM_MODE_IT_RISING 0x00010001U
#define | PWR_PVM_MODE_IT_FALLING 0x00010002U
#define | PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U
#define | PWR_PVM_MODE_EVENT_RISING 0x00020001U
#define | PWR_PVM_MODE_EVENT_FALLING 0x00020002U
#define | PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U

Define Documentation

#define PWR_PVM_MODE_EVENT_FALLING 0x00020002U

Event Mode with Falling edge trigger detection

Definition at line 121 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING 0x00020001U

Event Mode with Rising edge trigger detection

Definition at line 120 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U

Event Mode with Rising/Falling edge trigger detection

Definition at line 122 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_FALLING 0x00010002U

External Interrupt Mode with Falling edge trigger detection

Definition at line 118 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING 0x00010001U

External Interrupt Mode with Rising edge trigger detection

Definition at line 117 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 119 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_NORMAL 0x00000000U

basic mode is used

Definition at line 116 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Regulator voltage scale

Defines
PWR Regulator voltage scale
PWR Extended Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0

Voltage scaling range 1 normal mode

Definition at line 135 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_GetVoltageRange().

#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000)

Voltage scaling range 1 boost mode

Definition at line 133 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_GetVoltageRange().

#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Voltage scaling range 2

Definition at line 136 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_GetVoltageRange().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 146 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U

VBAT charging through a 5 kOhms resistor

Definition at line 145 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR battery charging

Defines
PWR battery charging
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_DISABLE 0x00000000U
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Define Documentation

#define PWR_BATTERY_CHARGING_DISABLE 0x00000000U

Definition at line 154 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Definition at line 155 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO bit number for I/O setting in standby/shutdown mode

Defines
GPIO bit number for I/O setting in standby/shutdown mode
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRA_PA14
#define | PWR_GPIO_BIT_15 PWR_PUCRA_PA15

Define Documentation

#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0

GPIO port I/O pin 0

Definition at line 163 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1

GPIO port I/O pin 1

Definition at line 164 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10

GPIO port I/O pin 10

Definition at line 173 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11

GPIO port I/O pin 11

Definition at line 174 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12

GPIO port I/O pin 12

Definition at line 175 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13

GPIO port I/O pin 13

Definition at line 176 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14

GPIO port I/O pin 14

Definition at line 177 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15

GPIO port I/O pin 15

Definition at line 178 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2

GPIO port I/O pin 2

Definition at line 165 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3

GPIO port I/O pin 3

Definition at line 166 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4

GPIO port I/O pin 4

Definition at line 167 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5

GPIO port I/O pin 5

Definition at line 168 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6

GPIO port I/O pin 6

Definition at line 169 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7

GPIO port I/O pin 7

Definition at line 170 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8

GPIO port I/O pin 8

Definition at line 171 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9

GPIO port I/O pin 9

Definition at line 172 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO port

Defines
GPIO port
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_A 0x00000000U
#define | PWR_GPIO_B 0x00000001U
#define | PWR_GPIO_C 0x00000002U
#define | PWR_GPIO_D 0x00000003U
#define | PWR_GPIO_E 0x00000004U
#define | PWR_GPIO_F 0x00000005U
#define | PWR_GPIO_G 0x00000006U

Define Documentation

#define PWR_GPIO_A 0x00000000U

GPIO port A

Definition at line 186 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_B 0x00000001U

GPIO port B

Definition at line 187 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_C 0x00000002U

GPIO port C

Definition at line 188 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_D 0x00000003U

GPIO port D

Definition at line 189 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_E 0x00000004U

GPIO port E

Definition at line 190 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_F 0x00000005U

GPIO port F

Definition at line 191 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_G 0x00000006U

GPIO port G

Definition at line 192 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVM external interrupts lines

Defines
PWR PVM external interrupts lines
PWR Extended Exported Constants

Defines

#define | PWR_EXTI_LINE_PVM1 0x00000008U
#define | PWR_EXTI_LINE_PVM2 0x00000010U
#define | PWR_EXTI_LINE_PVM3 0x00000020U
#define | PWR_EXTI_LINE_PVM4 0x00000040U

Define Documentation

#define PWR_EXTI_LINE_PVM1 0x00000008U

External interrupt line 35 Connected to the PVM1 EXTI Line

Definition at line 201 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM2 0x00000010U

External interrupt line 36 Connected to the PVM2 EXTI Line

Definition at line 204 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM3 0x00000020U

External interrupt line 37 Connected to the PVM3 EXTI Line

Definition at line 206 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM4 0x00000040U

External interrupt line 38 Connected to the PVM4 EXTI Line

Definition at line 207 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR PVM event lines

Defines
PWR PVM event lines
PWR Extended Exported Constants

Defines

#define | PWR_EVENT_LINE_PVM1 0x00000008U
#define | PWR_EVENT_LINE_PVM2 0x00000010U
#define | PWR_EVENT_LINE_PVM3 0x00000020U
#define | PWR_EVENT_LINE_PVM4 0x00000040U

Define Documentation

#define PWR_EVENT_LINE_PVM1 0x00000008U

Event line 35 Connected to the PVM1 EXTI Line

Definition at line 216 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM2 0x00000010U

Event line 36 Connected to the PVM2 EXTI Line

Definition at line 219 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM3 0x00000020U

Event line 37 Connected to the PVM3 EXTI Line

Definition at line 221 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM4 0x00000040U

Event line 38 Connected to the PVM4 EXTI Line

Definition at line 222 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Status Flags

Defines
PWR Status Flags
PWR Extended Exported Constants

Elements values convention: 0000 0000 0XXY YYYYb. More...

Defines

#define | PWR_FLAG_WUF1 0x0020U
#define | PWR_FLAG_WUF2 0x0021U
#define | PWR_FLAG_WUF3 0x0022U
#define | PWR_FLAG_WUF4 0x0023U
#define | PWR_FLAG_WUF5 0x0024U
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_SB 0x0028U
#define | PWR_FLAG_WUFI 0x002FU
#define | PWR_FLAG_REGLPS 0x0048U
#define | PWR_FLAG_REGLPF 0x0049U
#define | PWR_FLAG_VOSF 0x004AU
#define | PWR_FLAG_PVDO 0x004BU
#define | PWR_FLAG_PVMO1 0x004CU
#define | PWR_FLAG_PVMO2 0x004DU
#define | PWR_FLAG_PVMO3 0x004EU
#define | PWR_FLAG_PVMO4 0x004FU

Detailed Description

Elements values convention: 0000 0000 0XXY YYYYb.

  • Y YYYY : Flag position in the XX register (5 bits)
  • XX : Status register (2 bits)
    • 01: SR1 register
    • 10: SR2 register The only exception is PWR_FLAG_WU, encompassing all wake-up flags and set to PWR_SR1_WUF.

Define Documentation

#define PWR_FLAG_PVDO 0x004BU

Power Voltage Detector output flag

Definition at line 249 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO1 0x004CU

Power Voltage Monitoring 1 output flag

Definition at line 251 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO2 0x004DU

Power Voltage Monitoring 2 output flag

Definition at line 254 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO3 0x004EU

Power Voltage Monitoring 3 output flag

Definition at line 256 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO4 0x004FU

Power Voltage Monitoring 4 output flag

Definition at line 257 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPF 0x0049U

Low-power regulator flag

Definition at line 247 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPS 0x0048U

Low-power regulator start flag

Definition at line 246 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_SB 0x0028U

Standby flag

Definition at line 243 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_VOSF 0x004AU

Voltage scaling flag

Definition at line 248 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WU PWR_SR1_WUF

Encompass wakeup event on all wakeup pins

Definition at line 242 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF1 0x0020U

Wakeup event on wakeup pin 1

Definition at line 237 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF2 0x0021U

Wakeup event on wakeup pin 2

Definition at line 238 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF3 0x0022U

Wakeup event on wakeup pin 3

Definition at line 239 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF4 0x0023U

Wakeup event on wakeup pin 4

Definition at line 240 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF5 0x0024U

Wakeup event on wakeup pin 5

Definition at line 241 of file stm32g4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUFI 0x002FU

Wakeup on internal wakeup line

Definition at line 244 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Exported Macros

Defines
PWR Extended Exported Macros
PWREx

Defines

#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Enable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Disable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Enable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Disable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM2 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
Check whether the specified PVM2 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
Clear the PVM2 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Enable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Disable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Enable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Disable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM4 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
Check whether or not the specified PVM4 EXTI interrupt flag is set.
#define | __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
Clear the PVM4 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.

Define Documentation

#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)

Clear the PVM1 EXTI flag.

Return values:
None

Definition at line 358 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)

Disable the PVM1 Event Line.

Return values:
None

Definition at line 294 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 319 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Line.

Return values:
None

Definition at line 282 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 306 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM1 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 336 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)

Enable the PVM1 Event Line.

Return values:
None

Definition at line 288 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 312 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Line.

Return values:
None

Definition at line 276 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 300 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM1 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 326 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 346 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM1)

Check whether the specified PVM1 EXTI interrupt flag is set or not.

Return values:
EXTI PVM1 Line Status.

Definition at line 352 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)

Clear the PVM2 EXTI flag.

Return values:
None

Definition at line 450 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)

Disable the PVM2 Event Line.

Return values:
None

Definition at line 386 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 411 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Line.

Return values:
None

Definition at line 374 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 398 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM2 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 428 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)

Enable the PVM2 Event Line.

Return values:
None

Definition at line 380 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 404 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Line.

Return values:
None

Definition at line 368 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 392 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM2 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 418 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 438 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM2)

Check whether the specified PVM2 EXTI interrupt flag is set or not.

Return values:
EXTI PVM2 Line Status.

Definition at line 444 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)

Clear the PVM3 EXTI flag.

Return values:
None

Definition at line 541 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)

Disable the PVM3 Event Line.

Return values:
None

Definition at line 477 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 502 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Line.

Return values:
None

Definition at line 465 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 489 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM3 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 519 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)

Enable the PVM3 Event Line.

Return values:
None

Definition at line 471 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 495 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Line.

Return values:
None

Definition at line 459 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 483 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM3 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 509 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 529 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM3)

Check whether the specified PVM3 EXTI interrupt flag is set or not.

Return values:
EXTI PVM3 Line Status.

Definition at line 535 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)

Clear the PVM4 EXTI flag.

Return values:
None

Definition at line 632 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)

Disable the PVM4 Event Line.

Return values:
None

Definition at line 568 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 593 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Line.

Return values:
None

Definition at line 556 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 580 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM4 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 610 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)

Enable the PVM4 Event Line.

Return values:
None

Definition at line 562 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 586 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Line.

Return values:
None

Definition at line 550 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 574 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM4 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 600 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 620 of file stm32g4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM4)

Check whether or not the specified PVM4 EXTI interrupt flag is set.

Return values:
EXTI PVM4 Line Status.

Definition at line 626 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                     \
                                                            __IO uint32_t tmpreg;                               \
                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
                                                            /* Delay after an RCC peripheral clock enabling */  \
                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
                                                            UNUSED(tmpreg);                                     \
                                                          } while(0)

Configure the main internal regulator output voltage.

Parameters:
__REGULATOR__,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode, typical output voltage at 1.28 V, system frequency up to 170 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 150 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
Note:
This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check whether or not VOSF flag is cleared when moving from range 2 to range 1. User may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
Return values:
None

Definition at line 654 of file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Private Macros

Defines
PWR Extended Private Macros
PWREx

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
#define | IS_PWR_GPIO(GPIO)

Define Documentation

#define IS_PWR_BATTERY_CHARGING ( CHARGING )
Value:
(((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))

Definition at line 713 of file stm32g4xx_hal_pwr_ex.h.

#define IS_PWR_BATTERY_RESISTOR_SELECT ( RESISTOR )
Value:
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 710 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_GPIO ( GPIO )
Value:
(((GPIO) == PWR_GPIO_A) ||\
                           ((GPIO) == PWR_GPIO_B) ||\
                           ((GPIO) == PWR_GPIO_C) ||\
                           ((GPIO) == PWR_GPIO_D) ||\
                           ((GPIO) == PWR_GPIO_E) ||\
                           ((GPIO) == PWR_GPIO_F) ||\
                           ((GPIO) == PWR_GPIO_G))

Definition at line 717 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_GPIO_BIT_NUMBER ( BIT_NUMBER ) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)

Definition at line 716 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_PVM_MODE ( MODE )
Value:
(((MODE) == PWR_PVM_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))

Definition at line 692 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_PVM_TYPE ( TYPE )
Value:
(((TYPE) == PWR_PVM_1) ||\
                               ((TYPE) == PWR_PVM_2) ||\
                               ((TYPE) == PWR_PVM_3) ||\
                               ((TYPE) == PWR_PVM_4))

Definition at line 687 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_VOLTAGE_SCALING_RANGE ( RANGE )
Value:
(((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1)       || \
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))

Definition at line 701 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1) || \
                                ((PIN) == PWR_WAKEUP_PIN2) || \
                                ((PIN) == PWR_WAKEUP_PIN3) || \
                                ((PIN) == PWR_WAKEUP_PIN4) || \
                                ((PIN) == PWR_WAKEUP_PIN5) || \
                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN5_LOW))

Definition at line 671 of file stm32g4xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWREx

Modules | Defines
PWREx
STM32G4xx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWR Extended Private Defines
PWR Extended Exported Functions
PWR Extended Exported Types
PWR Extended Exported Constants
PWR Extended Exported Macros
PWR Extended Private Macros

Defines

#define | PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
#define | PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */

Detailed Description

PWR Extended HAL module driver.

Define Documentation

#define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */

Definition at line 46 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */

Definition at line 47 of file stm32g4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2)

Define Documentation

#define BDCR_REG_INDEX 2U

Definition at line 3239 of file stm32g4xx_hal_rcc.h.

#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */

Definition at line 75 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

#define CR_REG_INDEX 1U

Definition at line 3238 of file stm32g4xx_hal_rcc.h.

#define CRRCR_REG_INDEX 4U

Definition at line 3241 of file stm32g4xx_hal_rcc.h.

#define CSR_REG_INDEX 3U

Definition at line 3240 of file stm32g4xx_hal_rcc.h.

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 70 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 73 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 71 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 72 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 74 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2)

All clcoktype to configure

Definition at line 3246 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_MASK 0x1FU

Definition at line 3243 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
#define | RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
#define | RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
#define | RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
#define | IS_RCC_PLLQ_VALUE(__VALUE__)
#define | IS_RCC_PLLR_VALUE(__VALUE__)
#define | IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)

Define Documentation

#define IS_RCC_CLOCKTYPE ( __CLK__ ) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))

Definition at line 3297 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 3303 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                              ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 3264 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 3270 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI48 ( __HSI48__ ) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))

Definition at line 3276 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))

Definition at line 3272 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                              ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 3267 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE_DRIVE ( __DRIVE__ )
Value:
(((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))

Definition at line 3334 of file stm32g4xx_hal_rcc.h.

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 3274 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCOX__ )
Value:
(((__MCOX__) == RCC_MCO_PA8) || \
                              ((__MCOX__) == RCC_MCO_PG10))

Definition at line 3318 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))

Definition at line 3321 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( __DIV__ )
Value:
(((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
                                ((__DIV__) == RCC_MCODIV_16))

Definition at line 3330 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))

Definition at line 3257 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                               ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 3309 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 3278 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))

Definition at line 3285 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))

Definition at line 3287 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( __VALUE__ ) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))

Definition at line 3289 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 3291 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 3294 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 3281 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NONE)   || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))

Definition at line 3313 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 3299 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_GET_MCO_GPIO_AF ( __RCC_MCOx__ ) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)

Definition at line 86 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_GET_MCO_GPIO_INDEX ( __RCC_MCOx__ ) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)

Definition at line 88 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_GET_MCO_GPIO_PIN ( __RCC_MCOx__ ) ((__RCC_MCOx__) & GPIO_PIN_MASK)

Definition at line 84 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_GET_MCO_GPIO_PORT ( __RCC_MCOx__ ) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))

Definition at line 90 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_PLL_OSCSOURCE_CONFIG ( __HAL_RCC_PLLSOURCE__ ) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))

Definition at line 92 of file stm32g4xx_hal_rcc.c.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Functions

Functions
RCC Private Functions
RCC

Functions

static uint32_t RCC_GetSysClockFreqFromPLLSource (void)
Compute SYSCLK frequency based on PLL SYSCLK source.

Function Documentation

static uint32_t RCC_GetSysClockFreqFromPLLSource ( void ) [static]

Compute SYSCLK frequency based on PLL SYSCLK source.

Return values:
SYSCLK frequency

Definition at line 1359 of file stm32g4xx_hal_rcc.c.

References HSE_VALUE, HSI_VALUE, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCC_ClockConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal and external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
       and APB2).

    [..] Internal/external clock and PLL configuration
         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also optionally as RTC clock source.

         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.

         (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
           (++) The first output is used to generate the high speed system clock (up to 170 MHz).
           (++) The second output is used to generate the clock for the USB (48 MHz),
                the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
           (++) The third output is used to generate a clock for ADC

         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
             exception vector.

         (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE,
             main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin.

    [..] System, AHB and APB buses clocks configuration
         (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
             HSE and main PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these buses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                divided by 2 to 31.
                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
                to configure this clock.
           (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
                to work correctly, while the RNG peripheral requires a frequency
                equal or lower than to 48 MHz. This clock is derived of the main PLL
                through PLLQ divider. You have to enable the peripheral clock and use
                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) IWDG clock which is always the LSI clock.

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz.
             The clock source frequency should be adapted depending on the device voltage range
             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.

Table 1. HCLK clock frequency for STM32G4xx devices +----------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |----------------------------------------------------------| | | voltage range 1 | voltage range 1 | voltage range 2 | | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | |-----------------|-------------------|-------------------|------------------| |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | |-----------------|-------------------|-------------------|------------------| |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | |-----------------|-------------------|-------------------|------------------| |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | |-----------------|-------------------|-------------------|------------------| |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | |-----------------|-------------------|-------------------|------------------| |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | +----------------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH 0 Latency cycle
  • FLASH_LATENCY_1 FLASH 1 Latency cycle
  • FLASH_LATENCY_2 FLASH 2 Latency cycles
  • FLASH_LATENCY_3 FLASH 3 Latency cycles
  • FLASH_LATENCY_4 FLASH 4 Latency cycles
  • FLASH_LATENCY_5 FLASH 5 Latency cycles
  • FLASH_LATENCY_6 FLASH 6 Latency cycles
  • FLASH_LATENCY_7 FLASH 7 Latency cycles
  • FLASH_LATENCY_8 FLASH 8 Latency cycles
  • FLASH_LATENCY_9 FLASH 9 Latency cycles
  • FLASH_LATENCY_10 FLASH 10 Latency cycles
  • FLASH_LATENCY_11 FLASH 11 Latency cycles
  • FLASH_LATENCY_12 FLASH 12 Latency cycles
  • FLASH_LATENCY_13 FLASH 13 Latency cycles
  • FLASH_LATENCY_14 FLASH 14 Latency cycles
  • FLASH_LATENCY_15 FLASH 15 Latency cycles
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used by default as system clock source after startup from Reset, wake-up from STANDBY mode. After restart from Reset, the HSI frequency is set to its default value 16 MHz.
The HSI can be selected as system clock source after from STOP modes or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.
You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 766 of file stm32g4xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_GetSysClockFreqFromPLLSource(), RCC_HCLK_DIV16, RCC_SYSCLK_DIV1, RCC_SYSCLK_DIV2, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 OFF
  • All interrupts disabled
  • All interrupt and reset flags cleared
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
HAL status

Definition at line 219 of file stm32g4xx_hal_rcc.c.

References CLOCKSWITCH_TIMEOUT_VALUE, HAL_GetTick(), HAL_InitTick(), HSI_TIMEOUT_VALUE, HSI_VALUE, PLL_TIMEOUT_VALUE, RCC_HSICALIBRATION_DEFAULT, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 312 of file stm32g4xx_hal_rcc.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI48_DISABLE, __HAL_RCC_HSI48_ENABLE, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, assert_param, HAL_GetTick(), HAL_InitTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI48, IS_RCC_HSI_CALIBRATION_VALUE, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK, RCC_PLL_NONE, RCC_PLL_OFF, RCC_PLL_ON, RCC_PLL_SYSCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, and uwTickPrio.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8/PG10).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to:

    (+) Output clock to MCO pin.
    (+) Retrieve current clock frequencies.
    (+) Enable the Clock Security System.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1335 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableLSECSS ( void )

Disable the LSE Clock Security System.

Note:
After LSE failure detection, the software must disable LSECSSON
The Clock Security System can only be cleared by reset otherwise.
Return values:
None

Definition at line 1308 of file stm32g4xx_hal_rcc.c.

void HAL_RCC_EnableCSS ( void )

Enable the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
The Clock Security System can only be cleared by reset.
Return values:
None

Definition at line 1283 of file stm32g4xx_hal_rcc.c.

void HAL_RCC_EnableLSECSS ( void )

Enable the LSE Clock Security System.

Note:
If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers. If enabled, an interrupt will be generated and handle through RCC LSE CSS external interrupt line
The Clock Security System can only be cleared by reset or after a LSE failure detection.
Return values:
None

Definition at line 1297 of file stm32g4xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1248 of file stm32g4xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Return the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
Return values:
HCLK frequency in Hz

Definition at line 1118 of file stm32g4xx_hal_rcc.c.

Referenced by HAL_DAC_ConfigChannel(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configure the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1154 of file stm32g4xx_hal_rcc.c.

References assert_param, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Return the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency in Hz

Definition at line 1129 of file stm32g4xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Return the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency in Hz

Definition at line 1141 of file stm32g4xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Return the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), HSI_VALUE(*) Value multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1063 of file stm32g4xx_hal_rcc.c.

References __HAL_RCC_GET_SYSCLK_SOURCE, HSE_VALUE, HSI_VALUE, RCC_PLLSOURCE_HSE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCC_ClockConfig(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Select the clock source to output on MCO pin(PA8/PG10).

Note:
PA8/PG10 should be configured in alternate function mode.
The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin) and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it as an MCO pin. The HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value.
Parameters:
RCC_MCOx specifies the output direction for the clock source. For STM32G4xx family this parameter can have only one value:
  • RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8).
  • RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10).
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
  • RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
  • RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
RCC_MCODiv specifies the MCO prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
  • RCC_MCODIV_2 division by 2 applied to MCO clock
  • RCC_MCODIV_4 division by 4 applied to MCO clock
  • RCC_MCODIV_8 division by 8 applied to MCO clock
  • RCC_MCODIV_16 division by 16 applied to MCO clock
Return values:
None

Definition at line 994 of file stm32g4xx_hal_rcc.c.

References GPIO_InitTypeDef::Alternate, assert_param, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCODIV, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_GET_MCO_GPIO_AF, RCC_GET_MCO_GPIO_INDEX, RCC_GET_MCO_GPIO_PIN, RCC_GET_MCO_GPIO_PORT, RCC_MCO1_INDEX, RCC_MCO_INDEX_MASK, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

Handle the RCC Clock Security System interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1318 of file stm32g4xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32g4xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR

Detailed Description

RCC PLL configuration structure definition.

Definition at line 45 of file stm32g4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a value of PLLM Clock Divider

Definition at line 53 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 127

Definition at line 56 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for ADC clock. This parameter must be a value of PLLP Clock Divider

Definition at line 59 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks. This parameter must be a value of PLLQ Clock Divider

Definition at line 62 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ. This parameter must be a value of PLLR Clock Divider

Definition at line 65 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 50 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 47 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32g4xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | HSI48State
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 74 of file stm32g4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 79 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48. This parameter can be a value of HSI48 Config

Definition at line 94 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 88 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 85 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 82 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 91 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 76 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

Main PLL structure parameters

Definition at line 97 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32g4xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 104 of file stm32g4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 112 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 115 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 118 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of System Clock Type

Definition at line 106 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source used as system clock (SYSCLK). This parameter can be a value of System Clock Source

Definition at line 109 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Timeout Values

Defines
Timeout Values
RCC Exported Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Define Documentation

#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 135 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 136 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000020U

Define Documentation

#define RCC_OSCILLATORTYPE_HSE 0x00000001U

HSE to configure

Definition at line 145 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI 0x00000002U

HSI to configure

Definition at line 146 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI48 0x00000020U

HSI48 to configure

Definition at line 149 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE 0x00000004U

LSE to configure

Definition at line 147 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI 0x00000008U

LSI to configure

Definition at line 148 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE 0x00000000U

Oscillator configuration unchanged

Definition at line 144 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)

Define Documentation

#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)

External clock source for HSE clock

Definition at line 159 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF 0x00000000U

HSE clock deactivation

Definition at line 157 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 158 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)

Define Documentation

#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)

External clock source for LSE clock

Definition at line 169 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF 0x00000000U

LSE clock deactivation

Definition at line 167 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 168 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */

Define Documentation

#define RCC_HSI_OFF 0x00000000U

HSI clock deactivation

Definition at line 177 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 178 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */

Definition at line 179 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_DeInit().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF 0x00000000U

LSI clock deactivation

Definition at line 187 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

LSI clock activation

Definition at line 188 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSI48 Config

Defines
HSI48 Config
RCC Exported Constants

Defines

#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CRRCR_HSI48ON

Define Documentation

#define RCC_HSI48_OFF 0x00000000U

HSI48 clock deactivation

Definition at line 196 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI48_ON RCC_CRRCR_HSI48ON

HSI48 clock activation

Definition at line 197 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U

Define Documentation

#define RCC_PLL_NONE 0x00000000U

PLL configuration unchanged

Definition at line 205 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF 0x00000001U

PLL deactivation

Definition at line 206 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_PLL_ON 0x00000002U

PLL activation

Definition at line 207 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLLM Clock Divider

Defines
PLLM Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLM_DIV1 0x00000001U
#define | RCC_PLLM_DIV2 0x00000002U
#define | RCC_PLLM_DIV3 0x00000003U
#define | RCC_PLLM_DIV4 0x00000004U
#define | RCC_PLLM_DIV5 0x00000005U
#define | RCC_PLLM_DIV6 0x00000006U
#define | RCC_PLLM_DIV7 0x00000007U
#define | RCC_PLLM_DIV8 0x00000008U
#define | RCC_PLLM_DIV9 0x00000009U
#define | RCC_PLLM_DIV10 0x0000000AU
#define | RCC_PLLM_DIV11 0x0000000BU
#define | RCC_PLLM_DIV12 0x0000000CU
#define | RCC_PLLM_DIV13 0x0000000DU
#define | RCC_PLLM_DIV14 0x0000000EU
#define | RCC_PLLM_DIV15 0x0000000FU
#define | RCC_PLLM_DIV16 0x00000010U

Define Documentation

#define RCC_PLLM_DIV1 0x00000001U

PLLM division factor = 1

Definition at line 215 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV10 0x0000000AU

PLLM division factor = 10

Definition at line 224 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV11 0x0000000BU

PLLM division factor = 11

Definition at line 225 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV12 0x0000000CU

PLLM division factor = 12

Definition at line 226 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV13 0x0000000DU

PLLM division factor = 13

Definition at line 227 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV14 0x0000000EU

PLLM division factor = 14

Definition at line 228 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV15 0x0000000FU

PLLM division factor = 15

Definition at line 229 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV16 0x00000010U

PLLM division factor = 16

Definition at line 230 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV2 0x00000002U

PLLM division factor = 2

Definition at line 216 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV3 0x00000003U

PLLM division factor = 3

Definition at line 217 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV4 0x00000004U

PLLM division factor = 4

Definition at line 218 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV5 0x00000005U

PLLM division factor = 5

Definition at line 219 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV6 0x00000006U

PLLM division factor = 6

Definition at line 220 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV7 0x00000007U

PLLM division factor = 7

Definition at line 221 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV8 0x00000008U

PLLM division factor = 8

Definition at line 222 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLM_DIV9 0x00000009U

PLLM division factor = 9

Definition at line 223 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV2 0x00000002U
#define | RCC_PLLP_DIV3 0x00000003U
#define | RCC_PLLP_DIV4 0x00000004U
#define | RCC_PLLP_DIV5 0x00000005U
#define | RCC_PLLP_DIV6 0x00000006U
#define | RCC_PLLP_DIV7 0x00000007U
#define | RCC_PLLP_DIV8 0x00000008U
#define | RCC_PLLP_DIV9 0x00000009U
#define | RCC_PLLP_DIV10 0x0000000AU
#define | RCC_PLLP_DIV11 0x0000000BU
#define | RCC_PLLP_DIV12 0x0000000CU
#define | RCC_PLLP_DIV13 0x0000000DU
#define | RCC_PLLP_DIV14 0x0000000EU
#define | RCC_PLLP_DIV15 0x0000000FU
#define | RCC_PLLP_DIV16 0x00000010U
#define | RCC_PLLP_DIV17 0x00000011U
#define | RCC_PLLP_DIV18 0x00000012U
#define | RCC_PLLP_DIV19 0x00000013U
#define | RCC_PLLP_DIV20 0x00000014U
#define | RCC_PLLP_DIV21 0x00000015U
#define | RCC_PLLP_DIV22 0x00000016U
#define | RCC_PLLP_DIV23 0x00000017U
#define | RCC_PLLP_DIV24 0x00000018U
#define | RCC_PLLP_DIV25 0x00000019U
#define | RCC_PLLP_DIV26 0x0000001AU
#define | RCC_PLLP_DIV27 0x0000001BU
#define | RCC_PLLP_DIV28 0x0000001CU
#define | RCC_PLLP_DIV29 0x0000001DU
#define | RCC_PLLP_DIV30 0x0000001EU
#define | RCC_PLLP_DIV31 0x0000001FU

Define Documentation

#define RCC_PLLP_DIV10 0x0000000AU

PLLP division factor = 10

Definition at line 246 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV11 0x0000000BU

PLLP division factor = 11

Definition at line 247 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV12 0x0000000CU

PLLP division factor = 12

Definition at line 248 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV13 0x0000000DU

PLLP division factor = 13

Definition at line 249 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV14 0x0000000EU

PLLP division factor = 14

Definition at line 250 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV15 0x0000000FU

PLLP division factor = 15

Definition at line 251 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV16 0x00000010U

PLLP division factor = 16

Definition at line 252 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV17 0x00000011U

PLLP division factor = 17

Definition at line 253 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV18 0x00000012U

PLLP division factor = 18

Definition at line 254 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV19 0x00000013U

PLLP division factor = 19

Definition at line 255 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV2 0x00000002U

PLLP division factor = 2

Definition at line 238 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV20 0x00000014U

PLLP division factor = 20

Definition at line 256 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV21 0x00000015U

PLLP division factor = 21

Definition at line 257 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV22 0x00000016U

PLLP division factor = 22

Definition at line 258 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV23 0x00000017U

PLLP division factor = 23

Definition at line 259 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV24 0x00000018U

PLLP division factor = 24

Definition at line 260 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV25 0x00000019U

PLLP division factor = 25

Definition at line 261 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV26 0x0000001AU

PLLP division factor = 26

Definition at line 262 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV27 0x0000001BU

PLLP division factor = 27

Definition at line 263 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV28 0x0000001CU

PLLP division factor = 28

Definition at line 264 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV29 0x0000001DU

PLLP division factor = 29

Definition at line 265 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV3 0x00000003U

PLLP division factor = 3

Definition at line 239 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV30 0x0000001EU

PLLP division factor = 30

Definition at line 266 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV31 0x0000001FU

PLLP division factor = 31

Definition at line 267 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV4 0x00000004U

PLLP division factor = 4

Definition at line 240 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV5 0x00000005U

PLLP division factor = 5

Definition at line 241 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV6 0x00000006U

PLLP division factor = 6

Definition at line 242 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV7 0x00000007U

PLLP division factor = 7

Definition at line 243 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV8 0x00000008U

PLLP division factor = 8

Definition at line 244 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLP_DIV9 0x00000009U

PLLP division factor = 9

Definition at line 245 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLLQ Clock Divider

Defines
PLLQ Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLQ_DIV2 0x00000002U
#define | RCC_PLLQ_DIV4 0x00000004U
#define | RCC_PLLQ_DIV6 0x00000006U
#define | RCC_PLLQ_DIV8 0x00000008U

Define Documentation

#define RCC_PLLQ_DIV2 0x00000002U

PLLQ division factor = 2

Definition at line 275 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLQ_DIV4 0x00000004U

PLLQ division factor = 4

Definition at line 276 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLQ_DIV6 0x00000006U

PLLQ division factor = 6

Definition at line 277 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLQ_DIV8 0x00000008U

PLLQ division factor = 8

Definition at line 278 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLLR Clock Divider

Defines
PLLR Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLR_DIV2 0x00000002U
#define | RCC_PLLR_DIV4 0x00000004U
#define | RCC_PLLR_DIV6 0x00000006U
#define | RCC_PLLR_DIV8 0x00000008U

Define Documentation

#define RCC_PLLR_DIV2 0x00000002U

PLLR division factor = 2

Definition at line 286 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLR_DIV4 0x00000004U

PLLR division factor = 4

Definition at line 287 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLR_DIV6 0x00000006U

PLLR division factor = 6

Definition at line 288 of file stm32g4xx_hal_rcc.h.

#define RCC_PLLR_DIV8 0x00000008U

PLLR division factor = 8

Definition at line 289 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_NONE 0x00000000U
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 299 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetSysClockFreqFromPLLSource().

#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI clock selected as PLL entry clock source

Definition at line 298 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetSysClockFreqFromPLLSource().

#define RCC_PLLSOURCE_NONE 0x00000000U

No clock selected as PLL entry clock source

Definition at line 297 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL Clock Output

Defines
PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN

Define Documentation

#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN

PLL48M1CLK selection from main PLL

Definition at line 308 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN

PLLADCCLK selection from main PLL

Definition at line 307 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN

PLLCLK selection from main PLL

Definition at line 309 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U

Define Documentation

#define RCC_CLOCKTYPE_HCLK 0x00000002U

HCLK to configure

Definition at line 318 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 0x00000004U

PCLK1 to configure

Definition at line 319 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 0x00000008U

PCLK2 to configure

Definition at line 320 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK 0x00000001U

SYSCLK to configure

Definition at line 317 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 329 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 328 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 330 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 339 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 338 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 340 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 348 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 354 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 352 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 349 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 355 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 350 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 356 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 353 of file stm32g4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 351 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 APB2 Clock Source

Defines
APB1 APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 364 of file stm32g4xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 368 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 365 of file stm32g4xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 366 of file stm32g4xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 367 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NONE 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 379 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 377 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 378 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 376 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO_GPIOPORT_POS 16U
#define | RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
#define | RCC_MCO_GPIOAF_POS 20U
#define | RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
#define | RCC_MCO_INDEX_POS 28U
#define | RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
#define | RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS)
#define | RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
#define | RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
#define | RCC_MCO1 RCC_MCO_PA8
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 2 MCOs

Definition at line 405 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1 RCC_MCO_PA8

Definition at line 404 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS)

MCO1 index

Definition at line 399 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)

Definition at line 396 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_GPIOAF_POS 20U

Definition at line 395 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)

Definition at line 394 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_GPIOPORT_POS 16U

Definition at line 393 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)

Definition at line 398 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO_INDEX_POS 28U

Definition at line 397 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)

Definition at line 400 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)

Definition at line 401 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 416 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI selection as MCO1 source

Definition at line 415 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3

HSI48 selection as MCO1 source

Definition at line 420 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 419 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 418 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO1 output disabled, no clock on MCO1

Definition at line 413 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

PLLCLK selection as MCO1 source

Definition at line 417 of file stm32g4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 414 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO1 Clock Prescaler

Defines
MCO1 Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4
#define | RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16

Define Documentation

#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1

MCO not divided

Definition at line 428 of file stm32g4xx_hal_rcc.h.

#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16

MCO divided by 16

Definition at line 432 of file stm32g4xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2

MCO divided by 2

Definition at line 429 of file stm32g4xx_hal_rcc.h.

#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4

MCO divided by 4

Definition at line 430 of file stm32g4xx_hal_rcc.h.

#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8

MCO divided by 8

Definition at line 431 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF

Define Documentation

#define RCC_IT_CSS RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 445 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 443 of file stm32g4xx_hal_rcc.h.

#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 447 of file stm32g4xx_hal_rcc.h.

#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF

HSI16 Ready Interrupt flag

Definition at line 442 of file stm32g4xx_hal_rcc.h.

#define RCC_IT_LSECSS RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 446 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS(), HAL_RCCEx_EnableLSECSS_IT(), and HAL_RCCEx_LSECSS_IRQHandler().

#define RCC_IT_LSERDY RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 441 of file stm32g4xx_hal_rcc.h.

#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 440 of file stm32g4xx_hal_rcc.h.

#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 444 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
#define | RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register
    • 100: CRRCR register

Define Documentation

#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)

BOR reset flag

Definition at line 475 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)

HSE Ready flag

Definition at line 464 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)

HSI48 Ready flag

Definition at line 482 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)

HSI Ready flag

Definition at line 463 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)

Independent Watchdog reset flag

Definition at line 477 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

Low-Power reset flag

Definition at line 479 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)

LSE Clock Security System Interrupt flag

Definition at line 469 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)

LSE Ready flag

Definition at line 468 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)

LSI Ready flag

Definition at line 472 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)

Option Byte Loader reset flag

Definition at line 473 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)

PIN reset flag

Definition at line 474 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)

PLL Ready flag

Definition at line 465 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)

Software Reset flag

Definition at line 476 of file stm32g4xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)

Window watchdog reset flag

Definition at line 478 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSE Drive Config

Defines
LSE Drive Config
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW 0x00000000U
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

LSE high drive capability

Definition at line 493 of file stm32g4xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW 0x00000000U

LSE low drive capability

Definition at line 490 of file stm32g4xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

LSE medium high drive capability

Definition at line 492 of file stm32g4xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

LSE medium low drive capability

Definition at line 491 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_DMAMUX1_CLK_ENABLE()
#define | __HAL_RCC_CORDIC_CLK_ENABLE()
#define | __HAL_RCC_FMAC_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
#define | __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
#define | __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
#define | __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CORDIC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)

Definition at line 578 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CORDIC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 540 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)

Definition at line 584 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 564 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)

Definition at line 572 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 516 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)

Definition at line 574 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 524 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)

Definition at line 576 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 532 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)

Definition at line 582 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 556 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)

Definition at line 580 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 548 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 Peripheral Clock Enable Disable

Defines
AHB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_DAC3_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
#define | __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
#define | __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)

Detailed Description

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC12_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)

Definition at line 741 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 654 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)

Definition at line 747 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 672 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)

Definition at line 753 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 690 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)

Definition at line 727 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 598 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)

Definition at line 729 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 606 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)

Definition at line 731 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 614 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)

Definition at line 733 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 622 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)

Definition at line 735 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 630 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)

Definition at line 737 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 638 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)

Definition at line 739 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 646 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)

Definition at line 763 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 718 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 Peripheral Clock Enable Disable

AHB3 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock. More...

Enable or disable the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_UCPD1_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
#define | __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
#define | __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
#define | __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)

Detailed Description

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRS_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);

Definition at line 1041 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 867 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)

Definition at line 1070 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 968 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)

Definition at line 1063 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 943 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)

Definition at line 1065 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 951 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)

Definition at line 1075 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 985 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)

Definition at line 1077 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 993 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)

Definition at line 1079 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1001 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)

Definition at line 1073 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 977 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTCAPB_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);

Definition at line 1043 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 875 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)

Definition at line 1047 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 891 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)

Definition at line 1049 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 899 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)

Definition at line 1027 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 817 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)

Definition at line 1029 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 825 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)

Definition at line 1031 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 833 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)

Definition at line 1037 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 851 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)

Definition at line 1039 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 859 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)

Definition at line 1056 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 924 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)

Definition at line 1085 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1019 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)

Definition at line 1051 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 907 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)

Definition at line 1053 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 915 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)

Definition at line 1067 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 959 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)

Definition at line 1045 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 883 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)

Detailed Description

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)

Definition at line 1225 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1183 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)

Definition at line 1205 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1115 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)

Definition at line 1201 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1099 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_GPIO_Init(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_EnableFastModePlus(), HAL_OPAMP_Init(), HAL_SMBUSEx_DisableFastModePlus(), and HAL_SMBUSEx_EnableFastModePlus().

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)

Definition at line 1215 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1149 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)

Definition at line 1217 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1157 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)

Definition at line 1219 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1165 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)

Definition at line 1203 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1107 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)

Definition at line 1207 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1123 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)

Definition at line 1209 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1131 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 Peripheral Clock Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
#define | __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
#define | __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)

Detailed Description

Check whether the AHB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CORDIC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)

Definition at line 1263 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CORDIC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)

Definition at line 1249 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)

Definition at line 1269 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)

Definition at line 1255 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)

Definition at line 1257 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)

Definition at line 1243 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)

Definition at line 1259 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)

Definition at line 1245 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)

Definition at line 1261 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)

Definition at line 1247 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)

Definition at line 1267 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)

Definition at line 1253 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)

Definition at line 1265 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)

Definition at line 1251 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 Peripheral Clock Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
#define | __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
#define | __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)

Detailed Description

Check whether the AHB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC12_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)

Definition at line 1336 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)

Definition at line 1297 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)

Definition at line 1342 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)

Definition at line 1303 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)

Definition at line 1348 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)

Definition at line 1309 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)

Definition at line 1322 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)

Definition at line 1283 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)

Definition at line 1324 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)

Definition at line 1285 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)

Definition at line 1326 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)

Definition at line 1287 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)

Definition at line 1328 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)

Definition at line 1289 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)

Definition at line 1330 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)

Definition at line 1291 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)

Definition at line 1332 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)

Definition at line 1293 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)

Definition at line 1334 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)

Definition at line 1295 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)

Definition at line 1358 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)

Definition at line 1319 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 Peripheral Clock Enabled or Disabled Status

AHB3 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock is enabled or not. More...

Check whether the AHB3 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 Peripheral Clock Enabled or Disabled Status

Defines
APB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)

Detailed Description

Check whether the APB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRS_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)

Definition at line 1474 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)

Definition at line 1414 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)

Definition at line 1505 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)

Definition at line 1443 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)

Definition at line 1496 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)

Definition at line 1436 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)

Definition at line 1498 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)

Definition at line 1438 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)

Definition at line 1510 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)

Definition at line 1448 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)

Definition at line 1512 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)

Definition at line 1450 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)

Definition at line 1514 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)

Definition at line 1452 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)

Definition at line 1508 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)

Definition at line 1446 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)

Definition at line 1476 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)

Definition at line 1416 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)

Definition at line 1480 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)

Definition at line 1420 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)

Definition at line 1482 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)

Definition at line 1422 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)

Definition at line 1460 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)

Definition at line 1400 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)

Definition at line 1462 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)

Definition at line 1402 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)

Definition at line 1464 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)

Definition at line 1404 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)

Definition at line 1470 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)

Definition at line 1410 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)

Definition at line 1472 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)

Definition at line 1412 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)

Definition at line 1489 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)

Definition at line 1429 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)

Definition at line 1520 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)

Definition at line 1458 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)

Definition at line 1484 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)

Definition at line 1424 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)

Definition at line 1486 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)

Definition at line 1426 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)

Definition at line 1501 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)

Definition at line 1440 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)

Definition at line 1478 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)

Definition at line 1418 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 Peripheral Clock Enabled or Disabled Status

Defines
APB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)

Detailed Description

Check whether the APB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_SAI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)

Definition at line 1589 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)

Definition at line 1558 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)

Definition at line 1569 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)

Definition at line 1538 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)

Definition at line 1565 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)

Definition at line 1534 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)

Definition at line 1579 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)

Definition at line 1548 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)

Definition at line 1581 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)

Definition at line 1550 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)

Definition at line 1583 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)

Definition at line 1552 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)

Definition at line 1567 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)

Definition at line 1536 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)

Definition at line 1571 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)

Definition at line 1540 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)

Definition at line 1573 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)

Definition at line 1542 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 Peripheral Force Release Reset

Defines
AHB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define | __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define | __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define | __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define | __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB1_FORCE_RESET ( ) WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)

Definition at line 1603 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) WRITE_REG(RCC->AHB1RSTR, 0x00000000U)

Definition at line 1620 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CORDIC_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)

Definition at line 1611 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CORDIC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)

Definition at line 1628 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)

Definition at line 1617 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)

Definition at line 1634 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)

Definition at line 1605 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)

Definition at line 1622 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)

Definition at line 1607 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)

Definition at line 1624 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)

Definition at line 1609 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)

Definition at line 1626 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)

Definition at line 1615 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)

Definition at line 1632 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)

Definition at line 1613 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)

Definition at line 1630 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 Peripheral Force Release Reset

Defines
AHB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB2 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#define | __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#define | __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Detailed Description

Force or release AHB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC12_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)

Definition at line 1660 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_ADC12_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)

Definition at line 1701 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_AHB2_FORCE_RESET ( ) WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)

Definition at line 1644 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) WRITE_REG(RCC->AHB2RSTR, 0x00000000U)

Definition at line 1685 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_DAC1_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)

Definition at line 1666 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)

Definition at line 1707 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)

Definition at line 1672 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)

Definition at line 1713 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)

Definition at line 1646 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)

Definition at line 1687 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)

Definition at line 1648 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)

Definition at line 1689 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)

Definition at line 1650 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)

Definition at line 1691 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)

Definition at line 1652 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)

Definition at line 1693 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)

Definition at line 1654 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)

Definition at line 1695 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)

Definition at line 1656 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)

Definition at line 1697 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)

Definition at line 1658 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)

Definition at line 1699 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Definition at line 1682 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Definition at line 1723 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 Peripheral Force Release Reset

Defines
AHB3 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB3 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)

Detailed Description

Force or release AHB3 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB3_FORCE_RESET ( ) WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)

Definition at line 1733 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) WRITE_REG(RCC->AHB3RSTR, 0x00000000U)

Definition at line 1743 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 Peripheral Force Release Reset

Defines
APB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)

Definition at line 1761 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) WRITE_REG(RCC->APB1RSTR1, 0x00000000U)

Definition at line 1819 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CRS_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)

Definition at line 1777 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRS_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)

Definition at line 1835 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_FDCAN_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)

Definition at line 1802 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)

Definition at line 1860 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)

Definition at line 1795 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)

Definition at line 1853 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)

Definition at line 1797 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)

Definition at line 1855 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)

Definition at line 1807 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)

Definition at line 1865 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)

Definition at line 1809 of file stm32g4xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)

Definition at line 1867 of file stm32g4xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)

Definition at line 1811 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)

Definition at line 1869 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)

Definition at line 1805 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)

Definition at line 1863 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_SPI2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)

Definition at line 1779 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)

Definition at line 1837 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)

Definition at line 1781 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)

Definition at line 1839 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)

Definition at line 1763 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)

Definition at line 1821 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)

Definition at line 1765 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)

Definition at line 1823 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)

Definition at line 1767 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)

Definition at line 1825 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)

Definition at line 1773 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)

Definition at line 1831 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)

Definition at line 1775 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)

Definition at line 1833 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)

Definition at line 1788 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)

Definition at line 1846 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)

Definition at line 1817 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)

Definition at line 1875 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)

Definition at line 1783 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)

Definition at line 1841 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)

Definition at line 1785 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)

Definition at line 1843 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)

Definition at line 1799 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)

Definition at line 1857 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 Peripheral Force Release Reset

Defines
APB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_APB2_FORCE_RESET ( ) WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)

Definition at line 1885 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) WRITE_REG(RCC->APB2RSTR, 0x00000000U)

Definition at line 1918 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SAI1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)

Definition at line 1911 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)

Definition at line 1944 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)

Definition at line 1891 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)

Definition at line 1924 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)

Definition at line 1887 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)

Definition at line 1920 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)

Definition at line 1901 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)

Definition at line 1934 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)

Definition at line 1903 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)

Definition at line 1936 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)

Definition at line 1905 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)

Definition at line 1938 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)

Definition at line 1889 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)

Definition at line 1922 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)

Definition at line 1893 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)

Definition at line 1926 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)

Definition at line 1895 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)

Definition at line 1928 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 Peripheral Clock Sleep Enable Disable

Defines
AHB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define | __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define | __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define | __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define | __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)

Detailed Description

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)

Definition at line 1986 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)

Definition at line 1969 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)

Definition at line 1994 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)

Definition at line 1977 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)

Definition at line 1980 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)

Definition at line 1963 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)

Definition at line 1982 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)

Definition at line 1965 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)

Definition at line 1984 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)

Definition at line 1967 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)

Definition at line 1990 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)

Definition at line 1973 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)

Definition at line 1988 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)

Definition at line 1971 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)

Definition at line 1992 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)

Definition at line 1975 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 Peripheral Clock Sleep Enable Disable

Defines
AHB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#define | __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#define | __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Detailed Description

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)

Definition at line 2070 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)

Definition at line 2027 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)

Definition at line 2068 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)

Definition at line 2025 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)

Definition at line 2076 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)

Definition at line 2033 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)

Definition at line 2082 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)

Definition at line 2039 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)

Definition at line 2052 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)

Definition at line 2009 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)

Definition at line 2054 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)

Definition at line 2011 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)

Definition at line 2056 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)

Definition at line 2013 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)

Definition at line 2058 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)

Definition at line 2015 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)

Definition at line 2060 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)

Definition at line 2017 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)

Definition at line 2062 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)

Definition at line 2019 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)

Definition at line 2064 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)

Definition at line 2021 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Definition at line 2092 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Definition at line 2049 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)

Definition at line 2066 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)

Definition at line 2023 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 Peripheral Clock Sleep Enable Disable

AHB3 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. More...

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 Peripheral Clock Sleep Enable Disable

Defines
APB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)

Definition at line 2213 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)

Definition at line 2150 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)

Definition at line 2244 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)

Definition at line 2181 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)

Definition at line 2235 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)

Definition at line 2172 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)

Definition at line 2237 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)

Definition at line 2174 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)

Definition at line 2249 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)

Definition at line 2186 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)

Definition at line 2251 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)

Definition at line 2188 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)

Definition at line 2253 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)

Definition at line 2190 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)

Definition at line 2247 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)

Definition at line 2184 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)

Definition at line 2215 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)

Definition at line 2152 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)

Definition at line 2219 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)

Definition at line 2156 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)

Definition at line 2221 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)

Definition at line 2158 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)

Definition at line 2199 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)

Definition at line 2136 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)

Definition at line 2201 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)

Definition at line 2138 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)

Definition at line 2203 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)

Definition at line 2140 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)

Definition at line 2209 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)

Definition at line 2146 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)

Definition at line 2211 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)

Definition at line 2148 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)

Definition at line 2228 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)

Definition at line 2165 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)

Definition at line 2259 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)

Definition at line 2196 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)

Definition at line 2223 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)

Definition at line 2160 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)

Definition at line 2225 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)

Definition at line 2162 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)

Definition at line 2240 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)

Definition at line 2177 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)

Definition at line 2217 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)

Definition at line 2154 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 Peripheral Clock Sleep Enable Disable

Defines
APB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)

Definition at line 2329 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)

Definition at line 2298 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)

Definition at line 2309 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)

Definition at line 2278 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)

Definition at line 2305 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)

Definition at line 2274 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)

Definition at line 2319 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)

Definition at line 2288 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)

Definition at line 2321 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)

Definition at line 2290 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)

Definition at line 2323 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)

Definition at line 2292 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)

Definition at line 2307 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)

Definition at line 2276 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)

Definition at line 2311 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)

Definition at line 2280 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)

Definition at line 2313 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)

Definition at line 2282 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
#define | __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
#define | __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)

Detailed Description

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)

Definition at line 2371 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)

Definition at line 2354 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)

Definition at line 2379 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)

Definition at line 2362 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)

Definition at line 2365 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)

Definition at line 2348 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)

Definition at line 2367 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)

Definition at line 2350 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)

Definition at line 2369 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)

Definition at line 2352 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)

Definition at line 2375 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)

Definition at line 2358 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)

Definition at line 2373 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)

Definition at line 2356 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)

Definition at line 2377 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)

Definition at line 2360 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
#define | __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
#define | __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
#define | __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
#define | __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)

Detailed Description

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)

Definition at line 2455 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)

Definition at line 2412 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)

Definition at line 2453 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)

Definition at line 2410 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)

Definition at line 2461 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)

Definition at line 2418 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)

Definition at line 2467 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)

Definition at line 2424 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)

Definition at line 2437 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)

Definition at line 2394 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)

Definition at line 2439 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)

Definition at line 2396 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)

Definition at line 2441 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)

Definition at line 2398 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)

Definition at line 2443 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)

Definition at line 2400 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)

Definition at line 2445 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)

Definition at line 2402 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)

Definition at line 2447 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)

Definition at line 2404 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)

Definition at line 2449 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)

Definition at line 2406 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)

Definition at line 2477 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)

Definition at line 2434 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)

Definition at line 2451 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)

Definition at line 2408 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 Peripheral Clock Sleep Enabled or Disabled Status

AHB3 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)

Detailed Description

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)

Definition at line 2596 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)

Definition at line 2535 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)

Definition at line 2625 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)

Definition at line 2564 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)

Definition at line 2618 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)

Definition at line 2557 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)

Definition at line 2620 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)

Definition at line 2559 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)

Definition at line 2630 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)

Definition at line 2569 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)

Definition at line 2632 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)

Definition at line 2571 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)

Definition at line 2634 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)

Definition at line 2573 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)

Definition at line 2628 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)

Definition at line 2567 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)

Definition at line 2598 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)

Definition at line 2537 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)

Definition at line 2602 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)

Definition at line 2541 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)

Definition at line 2604 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)

Definition at line 2543 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)

Definition at line 2582 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)

Definition at line 2521 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)

Definition at line 2584 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)

Definition at line 2523 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)

Definition at line 2586 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)

Definition at line 2525 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)

Definition at line 2592 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)

Definition at line 2531 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)

Definition at line 2594 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)

Definition at line 2533 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)

Definition at line 2611 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)

Definition at line 2550 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)

Definition at line 2640 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)

Definition at line 2579 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)

Definition at line 2606 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)

Definition at line 2545 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)

Definition at line 2608 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)

Definition at line 2547 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)

Definition at line 2622 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)

Definition at line 2561 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)

Definition at line 2600 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)

Definition at line 2539 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)

Detailed Description

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)

Definition at line 2710 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)

Definition at line 2679 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)

Definition at line 2690 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)

Definition at line 2659 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)

Definition at line 2686 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)

Definition at line 2655 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)

Definition at line 2700 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)

Definition at line 2669 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)

Definition at line 2702 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)

Definition at line 2671 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)

Definition at line 2704 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)

Definition at line 2673 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)

Definition at line 2688 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)

Definition at line 2657 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)

Definition at line 2692 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)

Definition at line 2661 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)

Definition at line 2694 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)

Definition at line 2663 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Backup Domain Reset

Defines
RCC Backup Domain Reset
RCC Exported Macros

Defines

#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Return values:
None

Definition at line 2731 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Definition at line 2733 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Define Documentation

#define __HAL_RCC_RTC_DISABLE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Definition at line 2753 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the RTC clock.

Note:
As the RTC is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the RTC (to be done once after reset).
These macros must be used after the RTC clock source was selected.
Return values:
None

Definition at line 2751 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 3175 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->CSR |= RCC_CSR_RMVF)

Set RMVF bit to clear the reset flags.

The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Return values:
None

Definition at line 3197 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 3159 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 3144 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                     \
                                        ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                  \
                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                   \
                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &    \
                                          ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
                                            ? 1U : 0U)

Check whether the selected RCC flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY HSI oscillator clock ready
  • RCC_FLAG_HSERDY HSE oscillator clock ready
  • RCC_FLAG_PLLRDY Main PLL clock ready
  • RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
  • RCC_FLAG_LSERDY LSE oscillator clock ready
  • RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
  • RCC_FLAG_LSIRDY LSI oscillator clock ready
  • RCC_FLAG_BORRST BOR reset
  • RCC_FLAG_OBLRST OBLRST reset
  • RCC_FLAG_PINRST Pin reset
  • RCC_FLAG_SFTRST Software reset
  • RCC_FLAG_IWDGRST Independent Watchdog reset
  • RCC_FLAG_WWDGRST Window Watchdog reset
  • RCC_FLAG_LPWRRST Low Power reset
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 3218 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the RCC interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 3190 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Macros

Modules | Defines
RCC Exported Macros
RCC

Modules

AHB1 Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB2 Peripheral Clock Enable Disable

Enable or disable the AHB2 peripheral clock.

AHB3 Peripheral Clock Enable Disable

Enable or disable the AHB3 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the APB2 peripheral clock.

AHB1 Peripheral Clock Enabled or Disabled Status

Check whether the AHB1 peripheral clock is enabled or not.

AHB2 Peripheral Clock Enabled or Disabled Status

Check whether the AHB2 peripheral clock is enabled or not.

AHB3 Peripheral Clock Enabled or Disabled Status

Check whether the AHB3 peripheral clock is enabled or not.

APB1 Peripheral Clock Enabled or Disabled Status

Check whether the APB1 peripheral clock is enabled or not.

APB2 Peripheral Clock Enabled or Disabled Status

Check whether the APB2 peripheral clock is enabled or not.

AHB1 Peripheral Force Release Reset

Force or release AHB1 peripheral reset.

AHB2 Peripheral Force Release Reset

Force or release AHB2 peripheral reset.

AHB3 Peripheral Force Release Reset

Force or release AHB3 peripheral reset.

APB1 Peripheral Force Release Reset

Force or release APB1 peripheral reset.

APB2 Peripheral Force Release Reset

Force or release APB2 peripheral reset.

AHB1 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

AHB2 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

AHB3 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Clock Sleep Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Clock Sleep Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB3 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

RCC Backup Domain Reset
RCC RTC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
Macro to configure the PLL source division factor M.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO clock.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 3035 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLCLKOUT_CONFIG ( __PLLCLOCKOUT__ ) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)

Parameters:
__PLLCLOCKOUT__ specifies the output PLL clock to be checked. This parameter can be one of the following values:
  • RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
  • RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
Return values:
SET / RESET

Definition at line 3064 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RTC_SOURCE ( ) (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

Macro to get the RTC clock source.

Return values:
The returned value can be one of the following:
  • RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Definition at line 2941 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.

Definition at line 3085 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                                   \
                      if((__STATE__) == RCC_HSE_ON)                        \
                      {                                                    \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
                      }                                                    \
                      else if((__STATE__) == RCC_HSE_BYPASS)               \
                      {                                                    \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                   \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
                      }                                                    \
                      else                                                 \
                      {                                                    \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                  \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                 \
                      }                                                    \
                    } while(0)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__ specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON Turn ON the HSE oscillator.
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2839 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_DISABLE ( ) CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)

Definition at line 2904 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE ( ) SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)

Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).

Note:
The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2902 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICALIBRATIONVALUE__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)

Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICALIBRATIONVALUE__ specifies the calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 0x7F.
Return values:
None

Definition at line 2787 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Definition at line 2777 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 2775 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 2801 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI startup time.
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2799 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                                       \
                      if((__STATE__) == RCC_LSE_ON)                            \
                      {                                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
                      }                                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)                   \
                      {                                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                   \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
                      }                                                        \
                      else                                                     \
                      {                                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                  \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                 \
                      }                                                        \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__ specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON Turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2877 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__LSEDRIVE__ specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Return values:
None

Definition at line 3101 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE ( ) CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 2814 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

Definition at line 2812 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
  • RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 MCO clock source is divided by 1
  • RCC_MCODIV_2 MCO clock source is divided by 2
  • RCC_MCODIV_4 MCO clock source is divided by 4
  • RCC_MCODIV_8 MCO clock source is divided by 8
  • RCC_MCODIV_16 MCO clock source is divided by 16

Definition at line 3123 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PLL_CONFIG | ( | __PLLSOURCE__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
MODIFY_REG(RCC->PLLCFGR, \
                             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
                              RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
                             ((__PLLSOURCE__) | \
                              (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
                              ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
                              ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
                              ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
                              ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This macro must be used only when the main PLL is disabled.
This macro preserves the PLL's output clocks enable state.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
__PLLM__ specifies the division factor for PLL VCO input clock. This parameter must be a value of PLLM Clock Divider
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency of 8 MHz to limit PLL jitter.
Parameters:
__PLLN__ specifies the multiplication factor for PLL VCO output clock. This parameter must be a number between 8 and 127.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.
Parameters:
__PLLP__ | specifies the division factor for SAI clock. This parameter must be a number in the range (2 to 31).
__PLLQ__ | specifies the division factor for OTG FS, SDMMC1 and RNG clocks. This parameter must be in the range (2, 4, 6 or 8).
Note:
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Parameters:
__PLLR__ specifies the division factor for the main system clock.
Note:
You have to set the PLLR parameter correctly to not exceed 170MHZ. This parameter must be in the range (2, 4, 6 or 8).
Return values:
None

Definition at line 3017 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 2953 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLON)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 2951 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)

Macro to configure the PLL source division factor M.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__ specifies the division factor for PLL VCO input clock This parameter must be a value of PLLM Clock Divider.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency of 8 MHz to limit PLL jitter.
Return values:
None

Definition at line 2978 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Return values:
None

Definition at line 2965 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __PLLCLOCKOUT__ ) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Definition at line 3052 of file stm32g4xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __PLLCLOCKOUT__ ) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)

Note:
Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.
Parameters:
__PLLCLOCKOUT__ specifies the PLL clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
  • RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), FDCAN (<=48 MHz) and QSPI (<=48 MHz).
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
Return values:
None

Definition at line 3050 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__ specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 2930 of file stm32g4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__ specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Return values:
None

Definition at line 3075 of file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Private Constants

Defines
RCCEx Private Constants
RCCEx

Defines

#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U
#define | __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Define Documentation

#define __LSCO_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 49 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define DIVIDER_P_UPDATE 0U

Definition at line 45 of file stm32g4xx_hal_rcc_ex.c.

#define DIVIDER_Q_UPDATE 1U

Definition at line 46 of file stm32g4xx_hal_rcc_ex.c.

#define DIVIDER_R_UPDATE 2U

Definition at line 47 of file stm32g4xx_hal_rcc_ex.c.

#define LSCO_GPIO_PORT GPIOA

Definition at line 50 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define LSCO_PIN GPIO_PIN_2

Definition at line 51 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 43 of file stm32g4xx_hal_rcc_ex.c.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Private Functions

RCCEx Private Functions
RCCEx
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4, LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
Return values:
None

Definition at line 485 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC12_SOURCE, __HAL_RCC_GET_FDCAN_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_I2S_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::Adc12ClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::I2sClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PERIPHCLK_ADC12, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for peripherals with clock source from PLL.

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART2 peripheral clock
  • RCC_PERIPHCLK_USART3 USART3 peripheral clock
  • RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
  • RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_I2S SPI peripheral clock
  • RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN)
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
  • RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
  • RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
  • RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for devices with QSPI)
  • RCC_PERIPHCLK_RTC RTC peripheral clock
Return values:
Frequency in Hz

Definition at line 648 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC12_SOURCE, __HAL_RCC_GET_FDCAN_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_I2S_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_PLLCLKOUT_CONFIG, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, assert_param, EXTERNAL_CLOCK_VALUE, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSE_VALUE, HSI48_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LSE_VALUE, LSI_VALUE, RCC_ADC12CLKSOURCE_PLL, RCC_ADC12CLKSOURCE_SYSCLK, RCC_FDCANCLKSOURCE_HSE, RCC_FDCANCLKSOURCE_PCLK1, RCC_FDCANCLKSOURCE_PLL, RCC_I2C1CLKSOURCE_HSI, RCC_I2C1CLKSOURCE_PCLK1, RCC_I2C1CLKSOURCE_SYSCLK, RCC_I2C2CLKSOURCE_HSI, RCC_I2C2CLKSOURCE_PCLK1, RCC_I2C2CLKSOURCE_SYSCLK, RCC_I2C3CLKSOURCE_HSI, RCC_I2C3CLKSOURCE_PCLK1, RCC_I2C3CLKSOURCE_SYSCLK, RCC_I2SCLKSOURCE_EXT, RCC_I2SCLKSOURCE_HSI, RCC_I2SCLKSOURCE_PLL, RCC_I2SCLKSOURCE_SYSCLK, RCC_LPTIM1CLKSOURCE_HSI, RCC_LPTIM1CLKSOURCE_LSE, RCC_LPTIM1CLKSOURCE_LSI, RCC_LPTIM1CLKSOURCE_PCLK1, RCC_LPUART1CLKSOURCE_HSI, RCC_LPUART1CLKSOURCE_LSE, RCC_LPUART1CLKSOURCE_PCLK1, RCC_LPUART1CLKSOURCE_SYSCLK, RCC_PERIPHCLK_ADC12, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_RNGCLKSOURCE_HSI48, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_HSE_DIV32, RCC_RTCCLKSOURCE_LSE, RCC_RTCCLKSOURCE_LSI, RCC_SAI1CLKSOURCE_EXT, RCC_SAI1CLKSOURCE_HSI, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_SYSCLK, RCC_UART4CLKSOURCE_HSI, RCC_UART4CLKSOURCE_LSE, RCC_UART4CLKSOURCE_PCLK1, RCC_UART4CLKSOURCE_SYSCLK, RCC_USART1CLKSOURCE_HSI, RCC_USART1CLKSOURCE_LSE, RCC_USART1CLKSOURCE_PCLK2, RCC_USART1CLKSOURCE_SYSCLK, RCC_USART2CLKSOURCE_HSI, RCC_USART2CLKSOURCE_LSE, RCC_USART2CLKSOURCE_PCLK1, RCC_USART2CLKSOURCE_SYSCLK, RCC_USART3CLKSOURCE_HSI, RCC_USART3CLKSOURCE_LSE, RCC_USART3CLKSOURCE_PCLK1, RCC_USART3CLKSOURCE_SYSCLK, RCC_USBCLKSOURCE_HSI48, and RCC_USBCLKSOURCE_PLL.

Referenced by HAL_I2S_Init(), and HAL_SAI_Init().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that contains a field PeriphClockSelection which can be a combination of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART2 peripheral clock
  • RCC_PERIPHCLK_USART3 USART3 peripheral clock
  • RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
  • RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_I2S I2S peripheral clock
  • RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN)
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
  • RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
  • RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
  • RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for devices with QuadSPI)
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source: in this case the access to Backup domain is enabled.
Return values:
HAL status

Definition at line 123 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_ADC12_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_FDCAN_CONFIG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_I2C3_CONFIG, __HAL_RCC_I2S_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __HAL_RCC_RNG_CONFIG, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_UART4_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::Adc12ClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::I2sClockSelection, IS_RCC_ADC12CLKSOURCE, IS_RCC_FDCANCLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_I2C3CLKSOURCE, IS_RCC_I2SCLKSOURCE, IS_RCC_LPTIM1CLKSOURCE, IS_RCC_LPUART1CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RNGCLKSOURCE, IS_RCC_RTCCLKSOURCE, IS_RCC_SAI1CLKSOURCE, IS_RCC_UART4CLKSOURCE, IS_RCC_USART1CLKSOURCE, IS_RCC_USART2CLKSOURCE, IS_RCC_USART3CLKSOURCE, IS_RCC_USBCLKSOURCE, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_ADC12CLKSOURCE_PLL, RCC_DBP_TIMEOUT_VALUE, RCC_FDCANCLKSOURCE_PLL, RCC_I2SCLKSOURCE_PLL, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC12, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_NONE, RCC_SAI1CLKSOURCE_PLL, RCC_USBCLKSOURCE_PLL, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Clock management functions

Functions
Extended Clock management functions
RCCEx Exported Functions

Extended Clock management functions. More...

Functions

void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.

Detailed Description

Extended Clock management functions.

 ===============================================================================
                ##### Extended clock management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the
    activation or deactivation of LSE CSS,
    Low speed clock output and clock after wake-up from STOP mode.

Function Documentation

void HAL_RCCEx_DisableLSCO ( void )

Disable the Low Speed clock output.

Return values:
None

Definition at line 1405 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, HAL_PWR_DisableBkUpAccess(), and HAL_PWR_EnableBkUpAccess().

void HAL_RCCEx_DisableLSECSS ( void )

Disable the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 1296 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, and RCC_IT_LSECSS.

void HAL_RCCEx_EnableLSCO ( uint32_t LSCOSource )

Select the Low Speed clock source to output on LSCO pin (PA2).

Parameters:
LSCOSource specifies the Low Speed clock source to output. This parameter can be one of the following values:
  • RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
  • RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
Return values:
None

Definition at line 1358 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __LSCO_CLK_ENABLE, assert_param, GPIO_MODE_ANALOG, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, HAL_GPIO_Init(), HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), IS_RCC_LSCOSOURCE, LSCO_GPIO_PORT, LSCO_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCCEx_EnableLSECSS ( void )

Enable the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 1286 of file stm32g4xx_hal_rcc_ex.c.

void HAL_RCCEx_EnableLSECSS_IT ( void )

Enable the LSE Clock Security System Interrupt & corresponding EXTI line.

Note:
LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
Return values:
None

Definition at line 1309 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, and RCC_IT_LSECSS.

void HAL_RCCEx_LSECSS_Callback ( void )

RCCEx LSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1343 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSECSS_IRQHandler().

void HAL_RCCEx_LSECSS_IRQHandler ( void )

Handle the RCC LSE Clock Security System interrupt request.

Return values:
None

Definition at line 1326 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCCEx_LSECSS_Callback(), and RCC_IT_LSECSS.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Clock Recovery System Control functions

Functions
Extended Clock Recovery System Control functions
RCCEx Exported Functions

Extended Clock Recovery System Control functions. More...

Functions

void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended Clock Recovery System Control functions.

 ===============================================================================
                ##### Extended Clock Recovery System Control functions  #####
 ===============================================================================
    [..]
      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:

      (#) In System clock config, HSI48 needs to be enabled

      (#) Enable CRS clock in IP MSP init which will use CRS functions

      (#) Call CRS functions as follows:
          (##) Prepare synchronization configuration necessary for HSI48 calibration
              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
                        and also HSI48 oscillator smooth trimming.
              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
                        directly reload value with target and sychronization frequencies values
          (##) Call function HAL_RCCEx_CRSConfig which
              (+++) Resets CRS registers to their default values.
              (+++) Configures CRS registers with synchronization configuration
              (+++) Enables automatic calibration and frequency error counter feature
           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
           should be used as SYNC signal.

          (##) A polling function is provided to wait for complete synchronization
              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
              (+++) According to CRS status, user can decide to adjust again the calibration or continue
                        application if synchronization is OK

      (#) User can retrieve information related to synchronization in calling function
            HAL_RCCEx_CRSGetSynchronizationInfo()

      (#) Regarding synchronization status and synchronization information, user can try a new calibration
           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
           incremented), while when it is detected during the upcounting phase it means that the actual frequency
           is higher (and that the TRIM value should be decremented).

      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
              (++) Call function HAL_RCCEx_CRSConfig()
              (++) Enable CRS_IRQn (thanks to NVIC functions)
              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
              (++) Implement CRS status management in the following user callbacks called from
                   HAL_RCCEx_CRS_IRQHandler():
                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
                   (+++) HAL_RCCEx_CRS_ErrorCallback()

      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)

Function Documentation

void HAL_RCCEx_CRS_ErrorCallback ( uint32_t Error )

RCCEx Clock Recovery System Error interrupt callback.

Parameters:
Error Combination of Error status. This parameter can be a combination of the following values:
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF
Return values:
none

Definition at line 1784 of file stm32g4xx_hal_rcc_ex.c.

References UNUSED.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_ExpectedSyncCallback ( void )

RCCEx Clock Recovery System Expected SYNC interrupt callback.

Return values:
none

Definition at line 1768 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_IRQHandler ( void )

Handle the Clock Recovery System interrupt request.

Return values:
None

Definition at line 1681 of file stm32g4xx_hal_rcc_ex.c.

References HAL_RCCEx_CRS_ErrorCallback(), HAL_RCCEx_CRS_ExpectedSyncCallback(), HAL_RCCEx_CRS_SyncOkCallback(), HAL_RCCEx_CRS_SyncWarnCallback(), RCC_CRS_FLAG_ERR, RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_IT_ERR, RCC_CRS_IT_ESYNC, RCC_CRS_IT_SYNCOK, RCC_CRS_IT_SYNCWARN, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, and RCC_CRS_TRIMOVF.

void HAL_RCCEx_CRS_SyncOkCallback ( void )

RCCEx Clock Recovery System SYNCOK interrupt callback.

Return values:
none

Definition at line 1746 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_SyncWarnCallback ( void )

RCCEx Clock Recovery System SYNCWARN interrupt callback.

Return values:
none

Definition at line 1757 of file stm32g4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRSConfig ( RCC_CRSInitTypeDef * pInit )

Start automatic synchronization for polling mode.

Parameters:
pInit Pointer on RCC_CRSInitTypeDef structure
Return values:
None

Definition at line 1513 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_FORCE_RESET, __HAL_RCC_CRS_RELEASE_RESET, assert_param, RCC_CRSInitTypeDef::ErrorLimitValue, RCC_CRSInitTypeDef::HSI48CalibrationValue, IS_RCC_CRS_ERRORLIMIT, IS_RCC_CRS_HSI48CALIBRATION, IS_RCC_CRS_RELOADVALUE, IS_RCC_CRS_SYNC_DIV, IS_RCC_CRS_SYNC_POLARITY, IS_RCC_CRS_SYNC_SOURCE, RCC_CRSInitTypeDef::Polarity, RCC_CRSInitTypeDef::Prescaler, RCC_CRSInitTypeDef::ReloadValue, and RCC_CRSInitTypeDef::Source.

void HAL_RCCEx_CRSGetSynchronizationInfo ( RCC_CRSSynchroInfoTypeDef * pSynchroInfo )

Return synchronization info.

Parameters:
pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
Return values:
None

Definition at line 1565 of file stm32g4xx_hal_rcc_ex.c.

References assert_param, RCC_CRSSynchroInfoTypeDef::FreqErrorCapture, RCC_CRSSynchroInfoTypeDef::FreqErrorDirection, RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue, and RCC_CRSSynchroInfoTypeDef::ReloadValue.

void HAL_RCCEx_CRSSoftwareSynchronizationGenerate ( void )

Generate the software synchronization event.

Return values:
None

Definition at line 1555 of file stm32g4xx_hal_rcc_ex.c.

uint32_t HAL_RCCEx_CRSWaitSynchronization ( uint32_t Timeout )

Wait for CRS Synchronization status.

Parameters:
Timeout Duration of the timeout
Note:
Timeout is based on the maximum time to receive a SYNC event based on synchronization frequency.
If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
Return values:
Combination of Synchronization status This parameter can be a combination of the following values:
  • RCC_CRS_TIMEOUT
  • RCC_CRS_SYNCOK
  • RCC_CRS_SYNCWARN
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF

Definition at line 1598 of file stm32g4xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_CLEAR_FLAG, __HAL_RCC_CRS_GET_FLAG, HAL_GetTick(), RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, RCC_CRS_SYNCOK, RCC_CRS_SYNCWARN, RCC_CRS_TIMEOUT, and RCC_CRS_TRIMOVF.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32g4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
uint32_t | Usart1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | Uart4ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | I2c3ClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Sai1ClockSelection
uint32_t | I2sClockSelection
uint32_t | FdcanClockSelection
uint32_t | UsbClockSelection
uint32_t | RngClockSelection
uint32_t | Adc12ClockSelection
uint32_t | RTCClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 46 of file stm32g4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::Adc12ClockSelection

Specifies ADC12 interface clock source. This parameter can be a value of ADC12 Clock Source

Definition at line 111 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FdcanClockSelection

Specifies FDCAN clock source. This parameter can be a value of FDCAN Clock Source

Definition at line 99 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

Specifies I2C1 clock source. This parameter can be a value of I2C1 Clock Source

Definition at line 74 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

Specifies I2C2 clock source. This parameter can be a value of I2C2 Clock Source

Definition at line 77 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c3ClockSelection

Specifies I2C3 clock source. This parameter can be a value of I2C3 Clock Source

Definition at line 80 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2sClockSelection

Specifies I2S clock source. This parameter can be a value of I2S Clock Source

Definition at line 95 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source. This parameter can be a value of LPTIM1 Clock Source

Definition at line 89 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source. This parameter can be a value of LPUART1 Clock Source

Definition at line 71 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of Periph Clock Selection

Definition at line 48 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source (warning: same source for USB). This parameter can be a value of RNG Clock Source

Definition at line 108 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC clock source. This parameter can be a value of RTC Clock Source

Definition at line 124 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 clock source. This parameter can be a value of SAI1 Clock Source

Definition at line 92 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart4ClockSelection

Specifies UART4 clock source. This parameter can be a value of UART4 Clock Source

Definition at line 61 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

Specifies USART1 clock source. This parameter can be a value of USART1 Clock Source

Definition at line 51 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

Specifies USART2 clock source. This parameter can be a value of USART2 Clock Source

Definition at line 54 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

Specifies USART3 clock source. This parameter can be a value of USART3 Clock Source

Definition at line 57 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB clock source (warning: same source for RNG). This parameter can be a value of USB Clock Source

Definition at line 104 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_CRSInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSInitTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Init structure definition. More...

#include <stm32g4xx_hal_rcc_ex.h>

Data Fields

uint32_t | Prescaler
uint32_t | Source
uint32_t | Polarity
uint32_t | ReloadValue
uint32_t | ErrorLimitValue
uint32_t | HSI48CalibrationValue

Detailed Description

RCC_CRS Init structure definition.

Definition at line 131 of file stm32g4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSInitTypeDef::ErrorLimitValue

Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of RCCEx CRS ErrorLimitDefault

Definition at line 146 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::HSI48CalibrationValue

Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x7F or a value of RCCEx CRS HSI48CalibrationDefault

Definition at line 149 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Polarity

Specifies the input polarity for the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroPolarity

Definition at line 139 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Prescaler

Specifies the division factor of the SYNC signal. This parameter can be a value of RCCEx CRS SynchroDivider

Definition at line 133 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::ReloadValue

Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of RCCEx CRS ReloadValueDefault .

Definition at line 142 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Source

Specifies the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroSource

Definition at line 136 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC_CRSSynchroInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSSynchroInfoTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Synchronization structure definition. More...

#include <stm32g4xx_hal_rcc_ex.h>

Data Fields

uint32_t | ReloadValue
uint32_t | HSI48CalibrationValue
uint32_t | FreqErrorCapture
uint32_t | FreqErrorDirection

Detailed Description

RCC_CRS Synchronization structure definition.

Definition at line 157 of file stm32g4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorCapture

Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF

Definition at line 165 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorDirection

Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of RCCEx CRS FreqErrorDirection

Definition at line 169 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue

Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x7F

Definition at line 162 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::ReloadValue

Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF

Definition at line 159 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rcc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Low Speed Clock Source

Defines
Low Speed Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LSCOSOURCE_LSI 0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock output

Definition at line 189 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_LSCOSOURCE_LSI 0x00000000U

LSI selection for low speed clock output

Definition at line 188 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Periph Clock Selection

Defines
Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_USART2 0x00000002U
#define | RCC_PERIPHCLK_USART3 0x00000004U
#define | RCC_PERIPHCLK_UART4 0x00000008U
#define | RCC_PERIPHCLK_LPUART1 0x00000020U
#define | RCC_PERIPHCLK_I2C1 0x00000040U
#define | RCC_PERIPHCLK_I2C2 0x00000080U
#define | RCC_PERIPHCLK_I2C3 0x00000100U
#define | RCC_PERIPHCLK_LPTIM1 0x00000200U
#define | RCC_PERIPHCLK_SAI1 0x00000400U
#define | RCC_PERIPHCLK_I2S 0x00000800U
#define | RCC_PERIPHCLK_FDCAN 0x00001000U
#define | RCC_PERIPHCLK_USB 0x00002000U
#define | RCC_PERIPHCLK_RNG 0x00004000U
#define | RCC_PERIPHCLK_ADC12 0x00008000U
#define | RCC_PERIPHCLK_RTC 0x00080000U

Define Documentation

#define RCC_PERIPHCLK_ADC12 0x00008000U

Definition at line 218 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_FDCAN 0x00001000U

Definition at line 214 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 0x00000040U

Definition at line 207 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 0x00000080U

Definition at line 208 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C3 0x00000100U

Definition at line 209 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2S 0x00000800U

Definition at line 212 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 0x00000200U

Definition at line 210 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 0x00000020U

Definition at line 206 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG 0x00004000U

Definition at line 217 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC 0x00080000U

Definition at line 228 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 0x00000400U

Definition at line 211 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_UART4 0x00000008U

Definition at line 201 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 0x00000001U

Definition at line 197 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 0x00000002U

Definition at line 198 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 0x00000004U

Definition at line 199 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB 0x00002000U

Definition at line 216 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART1 Clock Source

Defines
USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK2 0x00000000U
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

Define Documentation

#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1

Definition at line 239 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

Definition at line 240 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U

Definition at line 237 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0

Definition at line 238 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART2 Clock Source

Defines
USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

Define Documentation

#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1

Definition at line 250 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

Definition at line 251 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U

Definition at line 248 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0

Definition at line 249 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART3 Clock Source

Defines
USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

Define Documentation

#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1

Definition at line 261 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

Definition at line 262 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U

Definition at line 259 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0

Definition at line 260 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART4 Clock Source

Defines
UART4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART4CLKSOURCE_PCLK1 0x00000000U
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)

Define Documentation

#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1

Definition at line 273 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)

Definition at line 274 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U

Definition at line 271 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0

Definition at line 272 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART1 Clock Source

Defines
LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

Define Documentation

#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

Definition at line 298 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

Definition at line 299 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U

Definition at line 296 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

Definition at line 297 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C1 Clock Source

Defines
I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

Definition at line 309 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U

Definition at line 307 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0

Definition at line 308 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C2 Clock Source

Defines
I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

Define Documentation

#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

Definition at line 319 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U

Definition at line 317 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0

Definition at line 318 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C3 Clock Source

Defines
I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1

Define Documentation

#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1

Definition at line 329 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U

Definition at line 327 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0

Definition at line 328 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM1 Clock Source

Defines
LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1

Definition at line 339 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Definition at line 340 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0

Definition at line 338 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U

Definition at line 337 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI1 Clock Source

Defines
SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)

Define Documentation

#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1

Definition at line 350 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)

Definition at line 351 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0

Definition at line 349 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U

Definition at line 348 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Clock Source

Defines
I2S Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
#define | RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
#define | RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)

Define Documentation

#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1

Definition at line 361 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)

Definition at line 362 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0

Definition at line 360 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U

Definition at line 359 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Clock Source

Defines
FDCAN Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FDCANCLKSOURCE_HSE 0x00000000U
#define | RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1

Define Documentation

#define RCC_FDCANCLKSOURCE_HSE 0x00000000U

Definition at line 370 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1

Definition at line 372 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0

Definition at line 371 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Clock Source

Defines
RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_HSI48 0x00000000U
#define | RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Define Documentation

#define RCC_RNGCLKSOURCE_HSI48 0x00000000U

Definition at line 381 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Definition at line 382 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USB Clock Source

Defines
USB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_HSI48 0x00000000U
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Define Documentation

#define RCC_USBCLKSOURCE_HSI48 0x00000000U

Definition at line 390 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Definition at line 391 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC12 Clock Source

Defines
ADC12 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADC12CLKSOURCE_NONE 0x00000000U
#define | RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
#define | RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1

Define Documentation

#define RCC_ADC12CLKSOURCE_NONE 0x00000000U

Definition at line 399 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0

Definition at line 400 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1

Definition at line 401 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC LSE CSS external interrupt line

Defines
RCC LSE CSS external interrupt line
RCCEx Exported Constants

Defines

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19

Define Documentation

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19

External interrupt line 19 connected to the LSE CSS EXTI Line

Definition at line 445 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS Status

Defines
RCCEx CRS Status
RCCEx Exported Constants

Defines

#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U

Define Documentation

#define RCC_CRS_NONE 0x00000000U

Definition at line 453 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCERR 0x00000008U

Definition at line 457 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCMISS 0x00000010U

Definition at line 458 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCOK 0x00000002U

Definition at line 455 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCWARN 0x00000004U

Definition at line 456 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TIMEOUT 0x00000001U

Definition at line 454 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TRIMOVF 0x00000020U

Definition at line 459 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS SynchroSource

Defines
RCCEx CRS SynchroSource
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U

Synchro Signal source GPIO

Definition at line 467 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 468 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 469 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS SynchroDivider

Defines
RCCEx CRS SynchroDivider
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_DIV1 0x00000000U
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Define Documentation

#define RCC_CRS_SYNC_DIV1 0x00000000U

Synchro Signal not divided (default)

Definition at line 477 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 484 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 481 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 478 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 482 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 479 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 483 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 480 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS SynchroPolarity

Defines
RCCEx CRS SynchroPolarity
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 493 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U

Synchro Active on rising edge (default)

Definition at line 492 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS ReloadValueDefault

Defines
RCCEx CRS ReloadValueDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

Define Documentation

#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB).

Definition at line 501 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS ErrorLimitDefault

Defines
RCCEx CRS ErrorLimitDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Define Documentation

#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Default Frequency error limit

Definition at line 510 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS HSI48CalibrationDefault

Defines
RCCEx CRS HSI48CalibrationDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

Define Documentation

#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency

Definition at line 518 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS FreqErrorDirection

Defines
RCCEx CRS FreqErrorDirection
RCCEx Exported Constants

Defines

#define | RCC_CRS_FREQERRORDIR_UP 0x00000000U
#define | RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR

Define Documentation

#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR

Downcounting direction, the actual frequency is below the target

Definition at line 529 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_FREQERRORDIR_UP 0x00000000U

Upcounting direction, the actual frequency is above the target

Definition at line 528 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS Interrupt Sources

Defines
RCCEx CRS Interrupt Sources
RCCEx Exported Constants

Defines

#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Define Documentation

#define RCC_CRS_IT_ERR CRS_CR_ERRIE

Error

Definition at line 539 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE

Expected SYNC

Definition at line 540 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE

SYNC error

Definition at line 541 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE

SYNC missed

Definition at line 542 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE

SYNC event OK

Definition at line 537 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE

SYNC warning

Definition at line 538 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Trimming overflow or underflow

Definition at line 543 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS Flags

Defines
RCCEx CRS Flags
RCCEx Exported Constants

Defines

#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Define Documentation

#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF

Error flag

Definition at line 554 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF

Expected SYNC flag

Definition at line 555 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR

SYNC error

Definition at line 556 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS

SYNC missed

Definition at line 557 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF

SYNC event OK flag

Definition at line 552 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF

SYNC warning flag

Definition at line 553 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Trimming overflow or underflow

Definition at line 558 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCCEx Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                 } \
                                               } while(0)

Definition at line 1188 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )
Value:
do { \
                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                 } \
                                               } while(0)

Definition at line 1144 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1117 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1105 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Return values:
The new state of _FLAG_ (TRUE or FALSE).

Definition at line 1168 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the CRS interrupt source to check. This parameter can be one of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1128 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)

Clear the RCC LSE CSS EXTI flag.

Return values:
None.

Definition at line 1086 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event Line.

Return values:
None.

Definition at line 1027 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1041 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Line.

Return values:
None

Definition at line 1015 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1054 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                       \
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1070 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event Line.

Return values:
None.

Definition at line 1021 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1034 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Line.

Return values:
None

Definition at line 1009 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1048 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                      \
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1060 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)

Generate a Software interrupt on the RCC LSE CSS EXTI line.

Return values:
None.

Definition at line 1092 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GET_FLAG ( ) (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

Return values:
EXTI RCC LSE CSS Line Status.

Definition at line 1080 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)

Clear the CRS specified FLAG.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Note:
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values:
None

Definition at line 1186 of file stm32g4xx_hal_rcc_ex.h.

#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)

Clear the CRS interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
  • RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
  • RCC_CRS_IT_SYNCERR SYNC error interrupt
  • RCC_CRS_IT_SYNCMISS SYNC missed interrupt

Definition at line 1142 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx CRS Extended Features

Defines
RCCEx CRS Extended Features
RCCEx Exported Macros

Defines

#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable or disable the automatic hardware adjustment of TRIM bits.

Return values:
None

Definition at line 1231 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable the automatic hardware adjustment of TRIM bits.

Note:
When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1225 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_CEN)

Disable the oscillator clock for frequency error counter.

Return values:
None

Definition at line 1218 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_CEN)

Enable the oscillator clock for frequency error counter.

Note:
when the CEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1212 of file stm32g4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
None

Definition at line 1243 of file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

RCCEx CRS Extended Features

Defines

#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
Macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
Macro to get the UART4 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
Macro to get the I2C3 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
Macro to configure the I2S clock source.
#define | __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
Macro to get the I2S clock source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
Macro to configure the FDCAN clock source.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
Macro to get the FDCAN clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
Macro to get the RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
Macro to configure the ADC12 interface clock.
#define | __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
Macro to get the ADC12 clock source.

Define Documentation

#define __HAL_RCC_ADC12_CONFIG ( __ADC12_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))

Macro to configure the ADC12 interface clock.

Parameters:
__ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. This parameter can be one of the following values:
  • RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
  • RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
  • RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock
Return values:
None

Definition at line 945 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_FDCAN_CONFIG ( __FDCAN_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))

Macro to configure the FDCAN clock source.

Parameters:
__FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived from the HSE, system PLL or PCLK1. This parameter can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
  • RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
  • RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
Return values:
None

Definition at line 880 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC12_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))

Macro to get the ADC12 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
  • RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
  • RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock

Definition at line 954 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_FDCAN_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))

Macro to get the FDCAN clock source.

Return values:
The clock source can be one of the following values:
  • RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
  • RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
  • RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1

Definition at line 890 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 729 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))

Macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 750 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))

Macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock

Definition at line 770 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2S_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))

Macro to get the I2S clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
  • RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
  • RCC_I2SCLKSOURCE_EXT I2S clock = EXT
  • RCC_I2SCLKSOURCE_HSI I2S clock = HSI

Definition at line 866 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))

Macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 816 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))

Macro to get the LPUART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 709 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RNG_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))

Macro to get the RNG clock.

Return values:
The clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
  • RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock

Definition at line 911 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
  • RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
  • RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI

Definition at line 841 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_UART4_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))

Macro to get the UART4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock

Definition at line 660 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))

Macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 593 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))

Macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 615 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART3_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))

Macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 637 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USB_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock

Definition at line 933 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1_CLKSOURCE__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Return values:
None

Definition at line 720 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2_CLKSOURCE__ specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Return values:
None

Definition at line 741 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))

Macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3_CLKSOURCE__ specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Return values:
None

Definition at line 761 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2S_CONFIG ( __I2S_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))

Macro to configure the I2S clock source.

Parameters:
__I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived from the HSI, system PLL, System Clock or external clock. This parameter can be one of the following values:
  • RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
  • RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
  • RCC_I2SCLKSOURCE_EXT I2S clock = EXT
  • RCC_I2SCLKSOURCE_HSI I2S clock = HSI
Return values:
None

Definition at line 855 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:
__LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
Return values:
None

Definition at line 806 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))

Macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:
__LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Return values:
None

Definition at line 699 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RNG_CONFIG ( __RNG_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))

Macro to configure the RNG clock.

Note:
USB and RNG peripherals share the same 48MHz clock source.
Parameters:
__RNG_CLKSOURCE__ specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
  • RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
Return values:
None

Definition at line 903 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __SAI1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))

Macro to configure the SAI1 clock source.

Parameters:
__SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived from the HSI, system PLL, System Clock or external clock. This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
  • RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
  • RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
Return values:
None

Definition at line 830 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG ( __UART4_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))

Macro to configure the UART4 clock (UART4CLK).

Parameters:
__UART4_CLKSOURCE__ specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Return values:
None

Definition at line 650 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1_CLKSOURCE__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
Return values:
None

Definition at line 583 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2_CLKSOURCE__ specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Return values:
None

Definition at line 605 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3_CLKSOURCE__ specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Return values:
None

Definition at line 627 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USB_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))

Macro to configure the USB clock (USBCLK).

Note:
USB, RNG peripherals share the same 48MHz clock source.
Parameters:
__USB_CLKSOURCE__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Return values:
None

Definition at line 925 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx_Private_Macros

Defines
RCCEx_Private_Macros
RCCEx

Defines

#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART4CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2SCLKSOURCE(__SOURCE__)
#define | IS_RCC_FDCANCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADC12CLKSOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Define Documentation

#define IS_RCC_ADC12CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE)    || \
                ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))

Definition at line 1547 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__ ) (((__VALUE__) <= 0xFFU))

Definition at line 1582 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__ )
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

Definition at line 1586 of file stm32g4xx_hal_rcc_ex.h.

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__ ) (((__VALUE__) <= 0x3FU))

Definition at line 1584 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__ ) (((__VALUE__) <= 0xFFFFU))

Definition at line 1580 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

Definition at line 1572 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

Definition at line 1577 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))

Definition at line 1568 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_FDCANCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))

Definition at line 1530 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))

Definition at line 1487 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))

Definition at line 1492 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))

Definition at line 1497 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2SCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK)  || \
                ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT)     || \
                ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))

Definition at line 1523 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 1511 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPUART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 1481 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSCOSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))

Definition at line 1313 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define IS_RCC_PERIPHCLOCK ( __SELECTION__ )
Value:
((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))

Definition at line 1408 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_RNGCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))

Definition at line 1536 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK)  || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT)     || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))

Definition at line 1517 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART4CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))

Definition at line 1465 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))

Definition at line 1446 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))

Definition at line 1452 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))

Definition at line 1458 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USBCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))

Definition at line 1541 of file stm32g4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 118 of file stm32g4xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_InitTypeDef Struct Reference
RNG Init Structure definition

#include <stm32g4xx_hal_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

Definition at line 50 of file stm32g4xx_hal_rng.h.

Field Documentation

uint32_t RNG_InitTypeDef::ClockErrorDetection

CED Clock error detection

Definition at line 52 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rng.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 62 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Handle Structure definition

Data Structures | Typedefs | Enumerations
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct | __RNG_HandleTypeDef

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng)

HAL RNG Callback pointer definition.

pointer to a common RNG callback function

Definition at line 123 of file stm32g4xx_hal_rng.h.

typedef void(* pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit)

pointer to an RNG Data Ready specific callback function

Definition at line 124 of file stm32g4xx_hal_rng.h.

typedef struct __RNG_HandleTypeDef RNG_HandleTypeDef

Enumeration Type Documentation

enum HAL_RNG_CallbackIDTypeDef

HAL RNG Callback ID enumeration definition.

Enumerator:
HAL_RNG_ERROR_CB_ID

RNG Error Callback ID

HAL_RNG_MSPINIT_CB_ID

RNG MspInit callback ID

HAL_RNG_MSPDEINIT_CB_ID

RNG MspDeInit callback ID

Definition at line 111 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32g4xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
RNG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | RandomNumber
void(* | ReadyDataCallback )(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)
void(* | ErrorCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspInitCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspDeInitCallback )(struct __RNG_HandleTypeDef *hrng)

Detailed Description

Definition at line 80 of file stm32g4xx_hal_rng.h.

Field Documentation

void(* __RNG_HandleTypeDef::ErrorCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Error Callback

Definition at line 99 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

__IO uint32_t __RNG_HandleTypeDef::ErrorCode

RNG Error code

Definition at line 93 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetError(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

RNG_InitTypeDef __RNG_HandleTypeDef::Init

RNG configuration parameters

Definition at line 87 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

RNG_TypeDef* __RNG_HandleTypeDef::Instance

Register base address

Definition at line 85 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef __RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 89 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

void(* __RNG_HandleTypeDef::MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp DeInit callback

Definition at line 102 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

void(* __RNG_HandleTypeDef::MspInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp Init callback

Definition at line 101 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

uint32_t __RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 95 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

void(* __RNG_HandleTypeDef::ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)

RNG Data Ready Callback

Definition at line 98 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterReadyDataCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

__IO HAL_RNG_StateTypeDef __RNG_HandleTypeDef::State

RNG communication state

Definition at line 91 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rng.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 145 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 144 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 146 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 155 of file stm32g4xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 154 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 156 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Clock Error Detection

Defines
RNG Clock Error Detection
RNG Exported Constants

Defines

#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define RNG_CED_DISABLE RNG_CR_CED

Clock error detection Disabled

Definition at line 165 of file stm32g4xx_hal_rng.h.

#define RNG_CED_ENABLE 0x00000000U

Clock error detection Enabled

Definition at line 164 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Error Definition

Defines
RNG Error Definition
RNG Exported Constants

Defines

#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U

Define Documentation

#define HAL_RNG_ERROR_BUSY 0x00000004U

Busy error

Definition at line 178 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), and HAL_RNG_GenerateRandomNumber_IT().

#define HAL_RNG_ERROR_CLOCK 0x00000010U

Clock error

Definition at line 180 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U

Invalid Callback error

Definition at line 175 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

#define HAL_RNG_ERROR_NONE 0x00000000U

No error

Definition at line 173 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_Init().

#define HAL_RNG_ERROR_SEED 0x00000008U

Seed error

Definition at line 179 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_TIMEOUT 0x00000002U

Timeout error

Definition at line 177 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__ | RNG handle
__FLAG__ | RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 242 of file stm32g4xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 280 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 220 of file stm32g4xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 256 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 213 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 249 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__ RNG Handle
__FLAG__ RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 232 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 268 of file stm32g4xx_hal_rng.h.

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0U)

Reset RNG handle state.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 199 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and configuration functions

Functions
Initialization and configuration functions
RNG Exported Functions

Initialization and configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Detailed Description

Initialization and configuration functions.

 ===============================================================================
          ##### Initialization and configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 219 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::MspDeInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 155 of file stm32g4xx_hal_rng.c.

References __HAL_RNG_ENABLE, assert_param, RNG_InitTypeDef::ClockErrorDetection, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_ErrorCallback(), HAL_RNG_MspInit(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Init, __RNG_HandleTypeDef::Instance, IS_RNG_CED, __RNG_HandleTypeDef::Lock, __RNG_HandleTypeDef::MspInitCallback, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 282 of file stm32g4xx_hal_rng.c.

References UNUSED.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_UnRegisterCallback().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 267 of file stm32g4xx_hal_rng.c.

References UNUSED.

Referenced by HAL_RNG_Init(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_RegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID,
 |  | pRNG_CallbackTypeDef | pCallback
 | ) |  |

Register a User RNG Callback To be used instead of the weak predefined callback.

Parameters:
hrng | RNG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 304 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | pRNG_ReadyDataCallbackTypeDef | pCallback
 | ) |  |

Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng | RNG handle
pCallback | pointer to the Data Ready Callback function
Return values:
HAL status

Definition at line 449 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.

Parameters:
hrng RNG handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 382 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ErrorCallback(), HAL_RNG_MspDeInit(), HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MspInit(), HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback ( RNG_HandleTypeDef * hrng )

UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng RNG handle
Return values:
HAL status

Definition at line 485 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (const RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 764 of file stm32g4xx_hal_rng.c.

References UNUSED.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
This function checks value of RNG_FLAG_DRDY flag to know if valid random number is available in the DR register (RNG_FLAG_DRDY flag set whenever a random number is available through the RNG_DR register). After transitioning from 0 to 1 (random number available), RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading four words from the RNG_DR register, i.e. further function calls will immediately return a new u32 random number (additional words are available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
When no more random number data is available in DR register, RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 549 of file stm32g4xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 607 of file stm32g4xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and __RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 656 of file stm32g4xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CLOCK, HAL_RNG_ERROR_SEED, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, __RNG_HandleTypeDef::ReadyDataCallback, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and __RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( const RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 731 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Note:
When RNG_FLAG_DRDY flag value is set, first random number has been read from DR register in IRQ Handler and is provided as callback parameter. Depending on valid data available in the conditioning output buffer, additional words can be read by the application from DR register till DRDY bit remains high.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | generated random number.
Return values:
None

Definition at line 748 of file stm32g4xx_hal_rng.c.

References UNUSED.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterReadyDataCallback().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef | HAL_RNG_GetState (const RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (const RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_RNG_GetError ( const RNG_HandleTypeDef * hrng )

Return the RNG handle error code.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
RNG Error Code

Definition at line 808 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode.

HAL_RNG_StateTypeDef HAL_RNG_GetState ( const RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 798 of file stm32g4xx_hal_rng.c.

References __RNG_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Define Documentation

#define IS_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == RNG_CED_ENABLE) || \
                                ((__MODE__) == RNG_CED_DISABLE))

Verify the RNG Clock Error Detection mode.

Parameters:
__MODE__ RNG Clock Error Detection mode
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 357 of file stm32g4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                           ((FLAG) == RNG_FLAG_CECS) || \
                           ((FLAG) == RNG_FLAG_SECS))

Definition at line 348 of file stm32g4xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 345 of file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Types

Data Structures | Typedefs | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 0x07U,
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 0x08U, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU,
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 0x0DU, HAL_RTC_MSPINIT_CB_ID = 0x0EU, HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL LPTIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc)

HAL RTC Callback pointer definition.

pointer to an RTC callback function

Definition at line 240 of file stm32g4xx_hal_rtc.h.

typedef struct __RTC_HandleTypeDef RTC_HandleTypeDef

RTC Handle Structure definition.

Enumeration Type Documentation

enum HAL_RTC_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_RTC_ALARM_A_EVENT_CB_ID

RTC Alarm A Event Callback ID

HAL_RTC_ALARM_B_EVENT_CB_ID

RTC Alarm B Event Callback ID

HAL_RTC_TIMESTAMP_EVENT_CB_ID

RTC TimeStamp Event Callback ID

HAL_RTC_WAKEUPTIMER_EVENT_CB_ID

RTC WakeUp Timer Event Callback ID

HAL_RTC_TAMPER1_EVENT_CB_ID

RTC Tamper 1 Callback ID

HAL_RTC_TAMPER2_EVENT_CB_ID

RTC Tamper 2 Callback ID

HAL_RTC_TAMPER3_EVENT_CB_ID

RTC Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID

RTC Internal Tamper 1 Callback ID

HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID

RTC Internal Tamper 2 Callback ID

HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID

RTC Internal Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID

RTC Internal Tamper 4 Callback ID

HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID

RTC Internal Tamper 5 Callback ID

HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID

RTC Internal Tamper 6 Callback ID

HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID

RTC Internal Tamper 7 Callback ID

HAL_RTC_MSPINIT_CB_ID

RTC Msp Init callback ID

HAL_RTC_MSPDEINIT_CB_ID

RTC Msp DeInit callback ID

Definition at line 217 of file stm32g4xx_hal_rtc.h.

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 46 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32g4xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType
uint32_t | OutPutPullUp

Detailed Description

RTC Configuration Structure definition.

Definition at line 59 of file stm32g4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 64 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 61 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTCEx Output Selection Definition

Definition at line 70 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 76 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPullUp

Specifies the RTC Output Pull-Up mode. This parameter can be a value of RTC Output Pull-Up ALARM OUT

Definition at line 82 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 73 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 79 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 67 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32g4xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 89 of file stm32g4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions

Definition at line 114 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 91 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 95 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 108 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 98 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions

Definition at line 117 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 104 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 101 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32g4xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 124 of file stm32g4xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 132 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 129 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 126 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 135 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32g4xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 142 of file stm32g4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 159 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 155 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC AlarmDateWeekDay Definitions

Definition at line 152 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC AlarmMask Definitions

Definition at line 146 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 149 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 144 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32g4xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State
void(* | AlarmAEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | AlarmBEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | TimeStampEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | WakeUpTimerEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper2EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper4EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper5EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper6EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspInitCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspDeInitCallback )(struct __RTC_HandleTypeDef *hrtc)

Detailed Description

RTC Handle Structure definition.

Definition at line 167 of file stm32g4xx_hal_rtc.h.

Field Documentation

void(* __RTC_HandleTypeDef::AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm A Event callback

Definition at line 182 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm B Event callback

Definition at line 183 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

RTC_InitTypeDef __RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 175 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* __RTC_HandleTypeDef::Instance

Legacy register base address. Not used anymore, the driver directly uses cmsis base address

Definition at line 172 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_ReadStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), RTC_EnterInitMode(), and RTC_ExitInitMode().

void(* __RTC_HandleTypeDef::InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 1 Event callback

Definition at line 192 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 3 Event callback

Definition at line 196 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 4 Event callback

Definition at line 197 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 5 Event callback

Definition at line 198 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 6 Event callback

Definition at line 200 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

HAL_LockTypeDef __RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 177 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

void(* __RTC_HandleTypeDef::MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp DeInit callback

Definition at line 207 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::MspInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp Init callback

Definition at line 206 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

__IO HAL_RTCStateTypeDef __RTC_HandleTypeDef::State

Time communication state

Definition at line 179 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_RegisterCallback(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_UnRegisterCallback(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), RTC_EnterInitMode(), and RTC_ExitInitMode().

void(* __RTC_HandleTypeDef::Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 1 Event callback

Definition at line 187 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 2 Event callback

Definition at line 188 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 3 Event callback

Definition at line 190 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC TimeStamp Event callback

Definition at line 184 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TimeStampIRQHandler().

void(* __RTC_HandleTypeDef::WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC WakeUpTimer Event callback

Definition at line 185 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 0x00000000U
#define | RTC_HOURFORMAT_12 RTC_CR_FMT

Define Documentation

#define RTC_HOURFORMAT_12 RTC_CR_FMT

Definition at line 256 of file stm32g4xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 0x00000000U

Definition at line 255 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Output Selection Definition

Defines
RTCEx Output Selection Definition
RTC Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE 0x00000000U
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Define Documentation

#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0

Definition at line 265 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1

Definition at line 266 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_DISABLE 0x00000000U

Definition at line 264 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Definition at line 268 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL

Definition at line 267 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U

Definition at line 277 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Definition at line 278 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000U
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

Definition at line 287 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000U

Definition at line 286 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Output Pull-Up ALARM OUT

Defines
RTC Output Pull-Up ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_PULLUP_NONE 0x00000000U
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Define Documentation

#define RTC_OUTPUT_PULLUP_NONE 0x00000000U

Definition at line 295 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Definition at line 296 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE 0x00000000U
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Define Documentation

#define RTC_OUTPUT_REMAP_NONE 0x00000000U

Definition at line 304 of file stm32g4xx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Definition at line 305 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM 0x0U
#define | RTC_HOURFORMAT12_PM 0x1U

Define Documentation

#define RTC_HOURFORMAT12_AM 0x0U

Definition at line 313 of file stm32g4xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM 0x1U

Definition at line 314 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC DayLightSaving Definitions

Defines
RTC DayLightSaving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000U

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H

Definition at line 323 of file stm32g4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE 0x00000000U

Definition at line 324 of file stm32g4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H

Definition at line 322 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC StoreOperation Definitions

Defines
RTC StoreOperation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET 0x00000000U
#define | RTC_STOREOPERATION_SET RTC_CR_BKP

Define Documentation

#define RTC_STOREOPERATION_RESET 0x00000000U

Definition at line 332 of file stm32g4xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET RTC_CR_BKP

Definition at line 333 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN 0x00000000U
#define | RTC_FORMAT_BCD 0x00000001U

Define Documentation

#define RTC_FORMAT_BCD 0x00000001U

Definition at line 342 of file stm32g4xx_hal_rtc.h.

#define RTC_FORMAT_BIN 0x00000000U

Definition at line 341 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04U)

Definition at line 355 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08U)

Definition at line 359 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Definition at line 363 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

Definition at line 353 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01U)

Definition at line 352 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07U)

Definition at line 358 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06U)

Definition at line 357 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03U)

Definition at line 354 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05U)

Definition at line 356 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

Definition at line 362 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)

Definition at line 361 of file stm32g4xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

Definition at line 360 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Definition at line 376 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Definition at line 372 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Definition at line 377 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Definition at line 378 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Definition at line 375 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Definition at line 373 of file stm32g4xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Definition at line 374 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC AlarmDateWeekDay Definitions

Defines
RTC AlarmDateWeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U

Definition at line 387 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Definition at line 388 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC AlarmMask Definitions

Defines
RTC AlarmMask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE 0x00000000U
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL

Define Documentation

#define RTC_ALARMMASK_ALL
Value:
(RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS  | \
                                             RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)

Definition at line 402 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 398 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 399 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 400 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE 0x00000000U

Definition at line 397 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 401 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 412 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 413 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 423 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

SS[14:0] are compared and must match to activate alarm.

Definition at line 454 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14] not used in Alarm comparison. Only SS[13:0] are compared

Definition at line 452 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0

SS[14:1] not used in Alarm comparison. Only SS[0] is compared.

Definition at line 426 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared

Definition at line 444 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared

Definition at line 446 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared

Definition at line 448 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared

Definition at line 450 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1

SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared

Definition at line 428 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)

SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared

Definition at line 430 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2

SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared

Definition at line 432 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)

SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared

Definition at line 434 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared

Definition at line 436 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared

Definition at line 438 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3

SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared

Definition at line 440 of file stm32g4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)

SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared

Definition at line 442 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE

Define Documentation

#define RTC_IT_ALRA RTC_CR_ALRAIE

Enable Alarm A Interrupt

Definition at line 465 of file stm32g4xx_hal_rtc.h.

#define RTC_IT_ALRB RTC_CR_ALRBIE

Enable Alarm B Interrupt

Definition at line 466 of file stm32g4xx_hal_rtc.h.

#define RTC_IT_TS RTC_CR_TSIE

Enable Timestamp Interrupt

Definition at line 463 of file stm32g4xx_hal_rtc.h.

#define RTC_IT_WUT RTC_CR_WUTIE

Enable Wakeup timer Interrupt

Definition at line 464 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Flag Mask (5bits) describe in RTC_Flags_Definitions

Defines
RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
RTC Exported Constants

Defines

#define RTC_FLAG_MASK 0x001FU

Define Documentation

#define RTC_FLAG_MASK 0x001FU

RTC flags mask (5bits)

Definition at line 474 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Elements values convention: 000000XX000YYYYYb. More...

Defines

#define | RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)
#define | RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)
#define | RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)
#define | RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)
#define | RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)
#define | RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)
#define | RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)
#define | RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)
#define | RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)
#define | RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)
#define | RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)
#define | RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)
#define | RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)
#define | RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)

Detailed Description

Elements values convention: 000000XX000YYYYYb.

  • YYYYY : Interrupt flag position in the XX register (5bits)
  • XX : Interrupt status register (2bits)
    • 01: ICSR register
    • 10: SR or SCR or MISR registers

Define Documentation

#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)

Alarm A flag

Definition at line 500 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)

Alarm A write flag

Definition at line 494 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)

Alarm B flag

Definition at line 499 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)

Alarm B write flag

Definition at line 493 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)

Initialization flag

Definition at line 488 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)

Initialization status flag

Definition at line 490 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)

Internal Time-stamp flag

Definition at line 495 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)

Recalibration pending Flag

Definition at line 487 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)

Registers synchronization flag

Definition at line 489 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)

Shift operation pending flag

Definition at line 491 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)

Time-stamp flag

Definition at line 497 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)

Time-stamp overflow flag

Definition at line 496 of file stm32g4xx_hal_rtc.h.

#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)

Wakeup timer flag

Definition at line 498 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)

Wakeup timer write flag

Definition at line 492 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Clear Flags Definitions

Defines
RTC Clear Flags Definitions
RTC Exported Constants

Defines

#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Define Documentation

#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Clear Alarm A flag

Definition at line 513 of file stm32g4xx_hal_rtc.h.

#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF

Clear Alarm B flag

Definition at line 512 of file stm32g4xx_hal_rtc.h.

#define RTC_CLEAR_ITSF RTC_SCR_CITSF

Clear Internal Time-stamp flag

Definition at line 508 of file stm32g4xx_hal_rtc.h.

#define RTC_CLEAR_TSF RTC_SCR_CTSF

Clear Time-stamp flag

Definition at line 510 of file stm32g4xx_hal_rtc.h.

#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF

Clear Time-stamp overflow flag

Definition at line 509 of file stm32g4xx_hal_rtc.h.

#define RTC_CLEAR_WUTF RTC_SCR_CWUTF

Clear Wakeup timer flag

Definition at line 511 of file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
Check whether the RTC Calendar is initialized.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC Alarms flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the RTC Alarms pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
set rising edge interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)
set rising edge interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
clear interrupt on the RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \
                                                            ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))

Clear the RTC Alarms pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 701 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 655 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 644 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_CLEAR_IT ( ) (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)

clear interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 785 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 725 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 737 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 713 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 749 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                                __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                              } while(0)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 764 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 719 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 731 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 707 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 743 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                                __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                              } while(0)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 755 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_FALLING_IT ( ) (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)

set rising edge interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 779 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_RISING_IT ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

set rising edge interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 773 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC Alarms flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 690 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 666 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 677 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 619 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 612 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 633 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 626 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                              \
    __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
    SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);            \
    MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
    __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
  } while(0);

Add 1 hour (summer time change).

Note:
This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 580 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                              \
    __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
    SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);            \
    MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
    __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
  } while(0);

Subtract 1 hour (winter time change).

Note:
This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 599 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_IS_CALENDAR_INITIALIZED ( __HANDLE__ ) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)

Check whether the RTC Calendar is initialized.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 567 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0)

Reset RTC handle state.

Parameters:
__HANDLE__ RTC handle.
Return values:
None

Definition at line 532 of file stm32g4xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
    (__HANDLE__)->Instance->WPR = 0xCAU;   \
    (__HANDLE__)->Instance->WPR = 0x53U;   \
  } while(0U)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 546 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
    (__HANDLE__)->Instance->WPR = 0xFFU;   \
  } while(0U)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 557 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Note:
This function does not reset the RTC Backup Data registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 429 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::MspDeInitCallback, RTC_EnterInitMode(), RTC_INT_TAMPER_ALL, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC peripheral.

Parameters:
hrtc RTC handle
Return values:
HAL status

< Legacy weak InternalTamper3EventCallback

< Legacy weak InternalTamper4EventCallback

< Legacy weak InternalTamper5EventCallback

< Legacy weak InternalTamper6EventCallback

Definition at line 301 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_IS_CALENDAR_INITIALIZED, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), RTC_InitTypeDef::HourFormat, __RTC_HandleTypeDef::Init, __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_PULLUP, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, __RTC_HandleTypeDef::Lock, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutPullUp, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_ExitInitMode(), __RTC_HandleTypeDef::State, RTC_InitTypeDef::SynchPrediv, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 828 of file stm32g4xx_hal_rtc.c.

References UNUSED.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 813 of file stm32g4xx_hal_rtc.c.

References UNUSED.

Referenced by HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTC_RegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID,
 |  | pRTC_CallbackTypeDef | pCallback
 | ) |  |

Register a User RTC Callback To be used instead of the weak predefined callback.

Parameters:
hrtc | RTC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 535 of file stm32g4xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID, HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

HAL_StatusTypeDef HAL_RTC_UnRegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.

Parameters:
hrtc RTC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
Return values:
HAL status

Definition at line 687 of file stm32g4xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_AlarmAEventCallback(), HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID, HAL_RTC_MspDeInit(), HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MspInit(), HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

void HAL_RTC_DST_Add1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1972 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_ClearStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Clear the store operation bit.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 2010 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint32_t HAL_RTC_DST_ReadStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Read the store operation bit.

Parameters:
hrtc RTC handle
Return values:
operation see RTC_StoreOperation_Definitions

Definition at line 2022 of file stm32g4xx_hal_rtc.c.

References __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_SetStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Set the store operation bit.

Note:
It can be used by the software in order to memorize the DST status.
Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1998 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_Sub1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1985 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Parameters:
hrtc | RTC handle
sDate | Pointer to Date structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1101 of file stm32g4xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 973 of file stm32g4xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1017 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FORMAT_BIN, __RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 866 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1723 of file stm32g4xx_hal_rtc.c.

References UNUSED.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1681 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_ALARM_EXTI_CLEAR_IT, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc RTC handle
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1529 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_ALARM_EXTI_CLEAR_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, RTC_ALARM_A, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Date structure
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1621 of file stm32g4xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1739 of file stm32g4xx_hal_rtc.c.

References HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1155 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FORMAT_BIN, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1342 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_ALARM_EXTI_CLEAR_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_RISING_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FORMAT_BIN, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1802 of file stm32g4xx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_ICSR_RESERVED_MASK, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTCEx_SetSynchroShift(), and RTC_ExitInitMode().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 1846 of file stm32g4xx_hal_rtc.c.

References __RTC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_ICSR_RESERVED_MASK
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_TIMEOUT_VALUE 1000U

Define Documentation

#define RTC_DR_RESERVED_MASK
Value:
(RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
                                             RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
                                             RTC_DR_DU)

Definition at line 884 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_ICSR_RESERVED_MASK
Value:
(RTC_ICSR_RECALPF | RTC_ICSR_INIT | RTC_ICSR_INITF | \
                                            RTC_ICSR_RSF | RTC_ICSR_INITS | RTC_ICSR_SHPF | \
                                            RTC_ICSR_WUTWF | RTC_ICSR_ALRBWF | RTC_ICSR_ALRAWF)

Definition at line 887 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_INIT_MASK 0xFFFFFFFFU

Definition at line 891 of file stm32g4xx_hal_rtc.h.

#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))

Definition at line 890 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000U

Definition at line 893 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK
Value:
(RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
                                             RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
                                             RTC_TR_SU)

Definition at line 881 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Define Documentation

#define IS_RTC_ALARM ( ALARM )
Value:
(((ALARM) == RTC_ALARM_A) || \
                                  ((ALARM) == RTC_ALARM_B))

Definition at line 970 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >0u) && ((DATE) <= 31u))

Definition at line 955 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 965 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 957 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)

Definition at line 968 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == 0UL) || \
                                                     (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))

Definition at line 975 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= RTC_ALRMASSR_SS)

Definition at line 973 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))

Definition at line 978 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1u) && ((DATE) <= 31u))

Definition at line 945 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 931 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_FORMAT_BIN) || \
                               ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 938 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > 0u) && ((HOUR) <= 12u))

Definition at line 982 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23u)

Definition at line 984 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 913 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM )
Value:
(((PM) == RTC_HOURFORMAT12_AM) || \
                                  ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 928 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59u)

Definition at line 986 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1u) && ((MONTH) <= 12u))

Definition at line 943 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
                               ((OUTPUT) == RTC_OUTPUT_TAMPER))

Definition at line 907 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 916 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_PULLUP ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))

Definition at line 922 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 925 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 919 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59u)

Definition at line 988 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 935 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))

Definition at line 980 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 947 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99u)

Definition at line 941 of file stm32g4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Function Documentation

void HAL_RTC_DST_Add1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1972 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_ClearStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Clear the store operation bit.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 2010 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint32_t HAL_RTC_DST_ReadStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Read the store operation bit.

Parameters:
hrtc RTC handle
Return values:
operation see RTC_StoreOperation_Definitions

Definition at line 2022 of file stm32g4xx_hal_rtc.c.

References __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_SetStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Set the store operation bit.

Note:
It can be used by the software in order to memorize the DST status.
Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1998 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_Sub1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1985 of file stm32g4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 1959 of file stm32g4xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 1940 of file stm32g4xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1869 of file stm32g4xx_hal_rtc.c.

References HAL_GetTick(), HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

HAL_StatusTypeDef RTC_ExitInitMode ( RTC_HandleTypeDef * hrtc )

Exit the RTC Initialization mode.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1901 of file stm32g4xx_hal_rtc.c.

References HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

Referenced by HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Tamper structure definition

#include <stm32g4xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 46 of file stm32g4xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the TAMP Filter Tamper. This parameter can be a value of RTCEx Tamper Filter

Definition at line 60 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTCEx Tamper MaskFlag

Definition at line 57 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTCEx Tamper EraseBackUp

Definition at line 54 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTCEx Tamper Pin Precharge Duration

Definition at line 66 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTCEx Tamper Sampling Frequencies

Definition at line 63 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTCEx Tamper Pins Definition

Definition at line 48 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTCEx Tamper Pull UP

Definition at line 69 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStamp On Tamper Detection

Definition at line 72 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTCEx Tamper Trigger

Definition at line 51 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC_InternalTamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InternalTamperTypeDef Struct Reference
RTCEx Internal Tamper structure definition

#include <stm32g4xx_hal_rtc_ex.h>

Data Fields

uint32_t | IntTamper
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 83 of file stm32g4xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_InternalTamperTypeDef::IntTamper

Specifies the Internal Tamper Pin. This parameter can be a value of RTCEx Internal Tamper Pins Definition

Definition at line 85 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

uint32_t RTC_InternalTamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStamp On Tamper Detection

Definition at line 88 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_rtc_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Time Stamp Edges definition

Defines
RTCEx Time Stamp Edges definition
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Definition at line 108 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING 0x00000000U

Definition at line 107 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx TimeStamp Pin Selection

Defines
RTCEx TimeStamp Pin Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U

Definition at line 116 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Wakeup Timer Definitions

Defines
RTCEx Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2

Definition at line 128 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Definition at line 129 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U

Definition at line 124 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)

Definition at line 127 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1

Definition at line 126 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0

Definition at line 125 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Smooth calib period Definitions

Defines
RTCEx Smooth calib period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK pulses

Definition at line 139 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK pulses

Definition at line 137 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK pulses

Definition at line 141 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Smooth calib Plus pulses Definitions

Defines
RTCEx Smooth calib Plus pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 153 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 150 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Calib Output selection Definitions

Defines
RTCEx Calib Output selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ 0x00000000U
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Define Documentation

#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Definition at line 164 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ 0x00000000U

Definition at line 163 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Add 1 Second Parameter Definitions

Defines
RTCEx Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET 0x00000000U
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Define Documentation

#define RTC_SHIFTADD1S_RESET 0x00000000U

Definition at line 174 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Definition at line 175 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Pins Definition

Defines
RTCEx Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )

Define Documentation

#define RTC_TAMPER_1 TAMP_CR1_TAMP1E

Definition at line 183 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_2 TAMP_CR1_TAMP2E

Definition at line 184 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_3 TAMP_CR1_TAMP3E

Definition at line 186 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )

Definition at line 187 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Internal Tamper Pins Definition

Defines
RTCEx Internal Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_INT_TAMPER_1 0U
#define | RTC_INT_TAMPER_2 0U
#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_7 0U
#define | RTC_INT_TAMPER_8 0U
#define | RTC_INT_TAMPER_ALL

Define Documentation

#define RTC_INT_TAMPER_1 0U

Definition at line 212 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_2 0U

Definition at line 217 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E

Definition at line 219 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E

Definition at line 220 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E

Definition at line 221 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E

Definition at line 223 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_7 0U

Definition at line 230 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_8 0U

Definition at line 235 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_INT_TAMPER_ALL
Value:
( RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
                                          RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
                                          RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
                                          RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 )

Definition at line 238 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTC_DeInit().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Trigger

Defines
RTCEx Tamper Trigger
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00U
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x01U
#define | RTC_TAMPERTRIGGER_LOWLEVEL 0x02U
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x03U

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01U

Warning : Filter must be RTC_TAMPERFILTER_DISABLE

Definition at line 250 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper().

#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03U

Warning : Filter must not be RTC_TAMPERFILTER_DISABLE

Definition at line 252 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper().

#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02U

Warning : Filter must not be RTC_TAMPERFILTER_DISABLE

Definition at line 251 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper().

#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00U

Warning : Filter must be RTC_TAMPERFILTER_DISABLE

Definition at line 249 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper MaskFlag

Defines
RTCEx Tamper MaskFlag
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00U
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01U

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE 0x00U

Definition at line 260 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE 0x01U

Definition at line 261 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper EraseBackUp

Defines
RTCEx Tamper EraseBackUp
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00U
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01U

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01U

Definition at line 270 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00U

Definition at line 269 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Filter

Defines
RTCEx Tamper Filter
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 279 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 281 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level

Definition at line 283 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 278 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Sampling Frequencies

Defines
RTCEx Tamper Sampling Frequencies
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 302 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 294 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 300 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
Value:
(TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
                                                 TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 306 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 292 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 298 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 304 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 296 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Pin Precharge Duration

Defines
RTCEx Tamper Pin Precharge Duration
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 316 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 318 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 320 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 322 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper Pull UP

Defines
RTCEx Tamper Pull UP
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000U
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS

Tamper pins pre-charge is disabled

Definition at line 332 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U

Tamper pins are pre-charged before sampling

Definition at line 331 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper TimeStamp On Tamper Detection

Defines
RTCEx Tamper TimeStamp On Tamper Detection
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U

TimeStamp on Tamper Detection event is not saved

Definition at line 340 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS

TimeStamp on Tamper Detection event saved

Definition at line 341 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Internal Tamper Interrupt

Defines
RTCEx Internal Tamper Interrupt
RTCEx Exported Constants

Defines

#define | RTC_IT_TAMP_1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP_2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP_3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )
#define | RTC_IT_INT_TAMP_1 0U
#define | RTC_IT_INT_TAMP_2 0U
#define | RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE
#define | RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE
#define | RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE
#define | RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE
#define | RTC_IT_INT_TAMP_7 0U
#define | RTC_IT_INT_TAMP_8 0U
#define | RTC_IT_INT_TAMP_ALL

Define Documentation

#define RTC_IT_INT_TAMP_1 0U

Definition at line 372 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_2 0U

Definition at line 377 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE

Tamper 3 internal Interrupt

Definition at line 379 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE

Tamper 4 internal Interrupt

Definition at line 380 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE

Tamper 5 internal Interrupt

Definition at line 381 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE

Tamper 6 internal Interrupt

Definition at line 383 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_7 0U

Definition at line 390 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_8 0U

Definition at line 395 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP_ALL
Value:
(RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
                                             RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\
                                             RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\
                                             RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 )

Definition at line 398 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE

Tamper 1 Interrupt

Definition at line 349 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE

Tamper 2 Interrupt

Definition at line 350 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE

Tamper 3 Interrupt

Definition at line 352 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )

Definition at line 353 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Flags

Defines
RTCEx Flags
RTCEx Exported Constants

Defines

#define | RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
#define | RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)
#define | RTC_FLAG_INT_TAMP_1 0U
#define | RTC_FLAG_INT_TAMP_2 0U
#define | RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F
#define | RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F
#define | RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F
#define | RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F
#define | RTC_FLAG_INT_TAMP_7 0U
#define | RTC_FLAG_INT_TAMP_8 0U
#define | RTC_FLAG_INT_TAMP_ALL

Define Documentation

#define RTC_FLAG_INT_TAMP_1 0U

Definition at line 433 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_2 0U

Definition at line 438 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F

Tamper 3 Interrupt flag

Definition at line 440 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F

Tamper 4 Interrupt flag

Definition at line 441 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F

Tamper 5 Interrupt flag

Definition at line 442 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F

Tamper 6 Interrupt flag

Definition at line 444 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_7 0U

Definition at line 451 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_8 0U

Definition at line 456 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP_ALL
Value:
(RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\
                                             RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\
                                             RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_6 |\
                                             RTC_FLAG_INT_TAMP_7 | RTC_FLAG_INT_TAMP_8)

Definition at line 458 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F

Definition at line 410 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F

Definition at line 411 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F

Definition at line 413 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)

Definition at line 414 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Backup Registers Definition

Defines
RTCEx Backup Registers Definition
RTCEx Exported Constants

Defines

#define | RTC_BKP_NUMBER RTC_BACKUP_NB
#define | RTC_BKP_DR0 0x00U
#define | RTC_BKP_DR1 0x01U
#define | RTC_BKP_DR2 0x02U
#define | RTC_BKP_DR3 0x03U
#define | RTC_BKP_DR4 0x04U
#define | RTC_BKP_DR5 0x05U
#define | RTC_BKP_DR6 0x06U
#define | RTC_BKP_DR7 0x07U
#define | RTC_BKP_DR8 0x08U
#define | RTC_BKP_DR9 0x09U
#define | RTC_BKP_DR10 0x0AU
#define | RTC_BKP_DR11 0x0BU
#define | RTC_BKP_DR12 0x0CU
#define | RTC_BKP_DR13 0x0DU
#define | RTC_BKP_DR14 0x0EU
#define | RTC_BKP_DR15 0x0FU

Define Documentation

#define RTC_BKP_DR0 0x00U

Definition at line 478 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 0x01U

Definition at line 479 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 0x0AU

Definition at line 488 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 0x0BU

Definition at line 489 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 0x0CU

Definition at line 490 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 0x0DU

Definition at line 491 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 0x0EU

Definition at line 492 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 0x0FU

Definition at line 493 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 0x02U

Definition at line 480 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 0x03U

Definition at line 481 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 0x04U

Definition at line 482 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 0x05U

Definition at line 483 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 0x06U

Definition at line 484 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 0x07U

Definition at line 485 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 0x08U

Definition at line 486 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 0x09U

Definition at line 487 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_BKP_NUMBER RTC_BACKUP_NB

Definition at line 470 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC WakeUp Timer

Defines
RTC WakeUp Timer
RTCEx Exported Macros

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC WakeUpTimers flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
Clear the RTC Wake Up timers pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.

Define Documentation

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))

Clear the RTC Wake Up timers pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 660 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 597 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 617 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 590 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 607 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 698 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT ( ) (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 692 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 710 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 674 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 704 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 668 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 686 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 680 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC WakeUpTimers flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 650 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__HANDLE__)->Instance->MISR)\
                                                                         & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 628 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__HANDLE__)->Instance->CR)\
                                                                            & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 638 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Timestamp

Defines
RTC Timestamp
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC TimeStamps flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
Clear the RTC Time Stamps pending flags.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
Clear the interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC Internal Time Stamps flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
Clear the RTC Internal Time Stamps pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.

Define Documentation

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))

Clear the RTC Internal Time Stamps pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 880 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 860 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 853 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))

Get the selected RTC Internal Time Stamps flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 870 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))

Disable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 908 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))

Enable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 901 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))

Disable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 894 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))

Enable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 887 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))

Clear the RTC Time Stamps pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 795 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 732 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 752 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 725 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 742 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)

Clear the interrupt on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 834 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT ( ) (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)

Clear the interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 828 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))

Disable event on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 846 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))

Disable interrupt on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 810 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

Enable event on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 840 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

Enable interrupt on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 804 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT ( ) (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 822 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_RISING_IT ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 816 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))

Get the selected RTC TimeStamps flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 784 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__HANDLE__)->Instance->MISR)\
                                                                        & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 762 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__HANDLE__)->Instance->CR)\
                                                                            & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 772 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Calibration

Defines
RTC Calibration
RTCEx Exported Macros

Defines

#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC shift operations flag status.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 933 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 926 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 948 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 941 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC shift operations flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 959 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx tamper

Defines
RTCEx tamper
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__))
Enable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
Disable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__))
Enable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
Disable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified TAMP Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TAMP Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0UL)
Get the selected TAMP Tampers flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__))
Clear the TAMP Tampers pending flags.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable interrupt on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable event on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable event on the RTC Tamper associated Exti line.

Define Documentation

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((TAMP->SCR) = (__FLAG__))

Clear the TAMP Tampers pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMP_ALL: All tampers flag
  • RTC_FLAG_TAMP_1: Tamper1 flag
  • RTC_FLAG_TAMP_2: Tamper2 flag
Return values:
None

Definition at line 1072 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_DISABLE | ( | __HANDLE__,
 |  | __TAMPER__
 | ) | (TAMP->CR1 &= ~(__TAMPER__))

Disable the TAMP Tamper input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
__TAMPER__ specifies the RTC Tamper sources to be enabled. This parameter can be any combination of the following values:
  • RTC_TAMPER_ALL: All tampers
  • RTC_TAMPER_1: Tamper1
  • RTC_TAMPER_2: Tamper2

Definition at line 990 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (TAMP->IER &= ~(__INTERRUPT__))

Disable the TAMP Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP_ALL: All tampers interrupts
  • RTC_IT_TAMP_1: Tamper1 interrupt
  • RTC_IT_TAMP_2: Tamper2 interrupt
Return values:
None

Definition at line 1017 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE | ( | __HANDLE__,
 |  | __TAMPER__
 | ) | (TAMP->CR1 |= (__TAMPER__))

Enable the TAMP Tamper input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
__TAMPER__ specifies the RTC Tamper source to be enabled. This parameter can be any combination of the following values:
  • RTC_TAMPER_ALL: All tampers
  • RTC_TAMPER_1: Tamper1
  • RTC_TAMPER_2: Tamper2
Return values:
None

Definition at line 979 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (TAMP->IER |= (__INTERRUPT__))

Enable the TAMP Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP_ALL: All tampers interrupts
  • RTC_IT_TAMP_1: Tamper1 interrupt
  • RTC_IT_TAMP_2: Tamper2 interrupt
Return values:
None

Definition at line 1004 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_CLEAR_IT ( ) (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)

Clear the interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1107 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_TamperIRQHandler().

#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))

Disable event on the RTC Tamper associated Exti line.

Return values:
None

Definition at line 1121 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))

Disable interrupt on the RTC Tamper associated Exti line.

Return values:
None

Definition at line 1086 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable event on the RTC Tamper associated Exti line.

Return values:
None

Definition at line 1114 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable interrupt on the RTC Tamper associated Exti line.

Return values:
None

Definition at line 1079 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper_IT(), and HAL_RTCEx_SetTamper_IT().

#define __HAL_RTC_TAMPER_EXTI_FALLING_IT ( ) (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1100 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_RISING_IT ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 1093 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper_IT(), and HAL_RTCEx_SetTamper_IT().

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((TAMP->SR) & (__FLAG__)) != 0UL)

Get the selected TAMP Tampers flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP_ALL: All tampers flag
  • RTC_FLAG_TAMP_1: Tamper1 flag
  • RTC_FLAG_TAMP_2: Tamper2 flag
Return values:
None

Definition at line 1059 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((TAMP->MISR)\
                                                                      & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)

Check whether the specified TAMP Tamper interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP_ALL: All tampers interrupts
  • RTC_IT_TAMP_1: Tamper1 interrupt
  • RTC_IT_TAMP_2: Tamper2 interrupt
Return values:
None

Definition at line 1031 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((TAMP->IER)\
                                                                      & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)

Check whether the specified TAMP Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP_ALL: All tampers interrupts
  • RTC_IT_TAMP_1: Tamper1 interrupt
  • RTC_IT_TAMP_2: Tamper2 interrupt
Return values:
None

Definition at line 1045 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Exported Macros

Modules | Defines
RTCEx Exported Macros
RTCEx

Modules

RTC WakeUp Timer
RTC Timestamp
RTC Calibration
RTCEx tamper

Defines

#define | __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__))
Clear the specified RTC pending flag.
#define | __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified RTC flag is set or not.

Define Documentation

#define __HAL_RTC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR = (__FLAG__))

Clear the specified RTC pending flag.

Parameters:
__HANDLE__ specifies the RTC Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • RTC_CLEAR_ITSF Clear Internal Time-stamp flag
  • RTC_CLEAR_TSOVF Clear Time-stamp overflow flag
  • RTC_CLEAR_TSF Clear Time-stamp flag
  • RTC_CLEAR_WUTF Clear Wakeup timer flag
  • RTC_CLEAR_ALRBF Clear Alarm B flag
  • RTC_CLEAR_ALRAF Clear Alarm A flag
Return values:
None

Definition at line 555 of file stm32g4xx_hal_rtc_ex.h.

#define __HAL_RTC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
                                                     ((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))

Check whether the specified RTC flag is set or not.

Parameters:
__HANDLE__ specifies the RTC Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • RTC_FLAG_RECALPF Recalibration pending Flag
  • RTC_FLAG_INITF Initialization flag
  • RTC_FLAG_RSF Registers synchronization flag
  • RTC_FLAG_INITS Initialization status flag
  • RTC_FLAG_SHPF Shift operation pending flag
  • RTC_FLAG_WUTWF Wakeup timer write flag
  • RTC_FLAG_ALRBWF Alarm B write flag
  • RTC_FLAG_ALRAWF Alarm A write flag
  • RTC_FLAG_ITSF Internal Time-stamp flag
  • RTC_FLAG_TSOVF Time-stamp overflow flag
  • RTC_FLAG_TSF Time-stamp flag
  • RTC_FLAG_WUTF Wakeup timer flag
  • RTC_FLAG_ALRBF Alarm B flag
  • RTC_FLAG_ALRAF Alarm A flag
Return values:
None

Definition at line 578 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended RTC TimeStamp functions

Functions
Extended RTC TimeStamp functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 329 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 264 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc | RTC handle
sTimeStamp | Pointer to Time structure
sTimeStampDate | Pointer to Date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 364 of file stm32g4xx_hal_rtc_ex.c.

References assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 470 of file stm32g4xx_hal_rtc_ex.c.

References HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 299 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 166 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, __RTC_HandleTypeDef::State, and UNUSED.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 217 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TIMESTAMP_EXTI_RISING_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, __RTC_HandleTypeDef::State, and UNUSED.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 414 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TimeStampIRQHandler().

void HAL_RTCEx_TimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 429 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_TimeStampEventCallback(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::TimeStampEventCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended RTC Wake-up functions

Functions
Extended RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 678 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
Counter value

Definition at line 730 of file stm32g4xx_hal_rtc_ex.c.

References __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 785 of file stm32g4xx_hal_rtc_ex.c.

References HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 532 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 603 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 768 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 741 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1066 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1138 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_ExitInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1214 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1182 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
CalibOutput Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1030 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1096 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_ExitInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue must be equal to 0.
Parameters:
hrtc | RTC handle
SmoothCalibPeriod Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue | Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Return values:
HAL status

Definition at line 866 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc | RTC handle
ShiftAdd1S Select to add or not 1 second to the time calendar. This parameter can be one of the following values:
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS | Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 937 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1263 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1279 of file stm32g4xx_hal_rtc_ex.c.

References HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended RTC Tamper functions

Functions
Extended RTC Tamper functions
RTCEx Exported Functions

Extended RTC Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.

Detailed Description

Extended RTC Tamper functions.

  ==============================================================================
                         ##### Tamper functions #####
  ==============================================================================
  [..]
   (+) Before calling any tamper or internal tamper function, you have to call first
       HAL_RTC_Init() function.
   (+) In that ine you can select to output tamper event on RTC pin.
  [..]
   (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
       or Level according to the Tamper filter (if equal to 0 Edge else Level)
       value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
       Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
       You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
   (+) The default configuration of the Tamper erases the backup registers. To avoid
       erase, enable the NoErase field on the TAMP_TAMPCR register.
  [..]
   (+) Enable Internal Tamper and configure it with interrupt, timestamp using
       the HAL_RTCEx_SetInternalTamper() function.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper
 | ) |  |

Deactivate Internal Tamper.

Parameters:
hrtc | RTC handle
IntTamper | Selected internal tamper event. This parameter can be any combination of existing internal tampers.
Return values:
HAL status

Definition at line 1607 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_CLEAR_IT, assert_param, IS_RTC_INTERNAL_TAMPER, and UNUSED.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc RTC handle
Tamper Selected tamper pin. This parameter can be a combination of the following values:
  • RTC_TAMPER_1
  • RTC_TAMPER_2
Return values:
HAL status

Definition at line 1479 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_CLEAR_IT, assert_param, and IS_RTC_TAMPER.

void HAL_RTCEx_InternalTamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1903 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper4EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 4 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1918 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper5EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 5 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1933 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper6EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 6 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1950 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper,
 |  | uint32_t | Timeout
 | ) |  |

Internal Tamper event polling.

Parameters:
hrtc | RTC handle
IntTamper | selected tamper. This parameter can be any combination of existing internal tampers.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1637 of file stm32g4xx_hal_rtc_ex.c.

References assert_param, HAL_GetTick(), IS_RTC_INTERNAL_TAMPER, and UNUSED.

HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper,
 |  | uint32_t | Timeout
 | ) |  |

Tamper event polling.

Parameters:
hrtc | RTC handle
Tamper Selected tamper pin. This parameter can be a combination of the following values:
  • RTC_TAMPER_1
  • RTC_TAMPER_2
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1512 of file stm32g4xx_hal_rtc_ex.c.

References assert_param, HAL_GetTick(), IS_RTC_TAMPER, and UNUSED.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper in interrupt mode.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1545 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, __RTC_HandleTypeDef::Instance, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1573 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_EXTI_RISING_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, __RTC_HandleTypeDef::Instance, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 1346 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERFILTER_DISABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_FALLINGEDGE, RTC_TAMPERTRIGGER_HIGHLEVEL, RTC_TAMPERTRIGGER_LOWLEVEL, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper in IT mode.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 1409 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_CLEAR_IT, __HAL_RTC_TAMPER_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_EXTI_RISING_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1822 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1837 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1853 of file stm32g4xx_hal_rtc_ex.c.

References UNUSED.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_TamperIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Tamper interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1669 of file stm32g4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_CLEAR_IT, HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), __RTC_HandleTypeDef::InternalTamper1EventCallback, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, RTC_INT_TAMPER_1, RTC_INT_TAMPER_2, RTC_INT_TAMPER_3, RTC_INT_TAMPER_4, RTC_INT_TAMPER_5, RTC_INT_TAMPER_6, RTC_INT_TAMPER_7, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, and __RTC_HandleTypeDef::Tamper3EventCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended RTC Backup register functions

Functions
Extended RTC Backup register functions
RTCEx Exported Functions

Extended RTC Backup register functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified TAMP Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified TAMP Backup data Register.

Detailed Description

Extended RTC Backup register functions.

  ===============================================================================
             ##### Extended RTC Backup register functions #####
  ===============================================================================
  [..]
   (+) Before calling any tamper or internal tamper function, you have to call first
       HAL_RTC_Init() function.
   (+) In that ine you can select to output tamper event on RTC pin.
  [..]
   This subsection provides functions allowing to
   (+) Write a data in a specified RTC Backup data register
   (+) Read a data in a specified RTC Backup data register

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified TAMP Backup data Register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB to specify the register.
Return values:
Read value

Definition at line 2036 of file stm32g4xx_hal_rtc_ex.c.

References assert_param, IS_RTC_BKP, and UNUSED.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified TAMP Backup data register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data | Data to be written in the specified TAMP Backup data register.
Return values:
None

Definition at line 2012 of file stm32g4xx_hal_rtc_ex.c.

References assert_param, IS_RTC_BKP, and UNUSED.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17
#define | RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20

Define Documentation

#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 1260 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events

Definition at line 1262 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events

Definition at line 1261 of file stm32g4xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20

External interrupt line 20 Connected to the RTC Wakeup event

Definition at line 1263 of file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_LOW_POWER_CALIB(LPCAL)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( __BKP__ ) ((__BKP__) < RTC_BKP_NUMBER)

Definition at line 1354 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1361 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_INTERNAL_TAMPER ( __INT_TAMPER__ )
Value:
((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
                                                  (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))

Definition at line 1315 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

#define IS_RTC_LOW_POWER_CALIB ( LPCAL )
Value:
(((LPCAL) == RTC_LPCAL_SET) || \
                                       ((LPCAL) == RTC_LPCAL_RESET))

Definition at line 1309 of file stm32g4xx_hal_rtc_ex.h.

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1356 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= RTC_SHIFTR_SUBFS)

Definition at line 1359 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= RTC_CALR_CALM)

Definition at line 1307 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1300 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1304 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ )
Value:
((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
                                                  (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))

Definition at line 1312 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( __MODE__ )
Value:
(((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                  ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 1323 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( __FILTER__ )
Value:
(((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
                                                  ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
                                                  ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
                                                  ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 1329 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                  ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 1326 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 1343 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
                                                  ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 1348 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( __FREQ__ )
Value:
(((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 1334 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT ( MODE )
Value:
(((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
                                                      ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))

Definition at line 1287 of file stm32g4xx_hal_rtc_ex.h.

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1351 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( __TRIGGER__ )
Value:
(((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 1318 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1280 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                       ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1284 of file stm32g4xx_hal_rtc_ex.h.

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1291 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= RTC_WUTR_WUT)

Definition at line 1298 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1276 of file stm32g4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 231 of file stm32g4xx_hal_sai.c.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U
#define | SAI_SPDIF_FRAME_LENGTH 64U
#define | SAI_AC97_FRAME_LENGTH 256U

Define Documentation

#define SAI_AC97_FRAME_LENGTH 256U

Definition at line 247 of file stm32g4xx_hal_sai.c.

Referenced by HAL_SAI_Init().

#define SAI_DEFAULT_TIMEOUT 4U

Definition at line 244 of file stm32g4xx_hal_sai.c.

Referenced by SAI_Disable().

#define SAI_LONG_TIMEOUT 1000U

Definition at line 245 of file stm32g4xx_hal_sai.c.

Referenced by HAL_SAI_Transmit_DMA().

#define SAI_SPDIF_FRAME_LENGTH 64U

Definition at line 246 of file stm32g4xx_hal_sai.c.

Referenced by HAL_SAI_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Private Functions

Functions
SAI Private Functions
SAI

Private functions. More...

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.

Detailed Description

Private functions.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

Disable the SAI and wait for the disabling.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2335 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_DEFAULT_TIMEOUT.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Transmit(), SAI_DMAAbort(), and SAI_DMAError().

static void SAI_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI Abort callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2696 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_IRQHandler().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2662 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_DMA, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2617 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __SAI_HandleTypeDef::RxCpltCallback, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2645 of file stm32g4xx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback(), and __SAI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2571 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2600 of file stm32g4xx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback(), and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2259 of file stm32g4xx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol.
datasize | one of the supported datasize SAI protocol data size.
nbslot | number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 2094 of file stm32g4xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol
datasize | one of the supported datasize SAI protocol data size
nbslot | number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 2189 of file stm32g4xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | const SAI_HandleTypeDef * | hsai,
 |  | SAI_ModeTypedef | mode
 | ) |  | [static]

Return the interrupt flag to set according the SAI setup.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode | SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 2302 of file stm32g4xx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2495 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2531 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2464 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2394 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2427 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2365 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
             ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config
        (++) PDM Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI peripheral.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 622 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::MspDeInitCallback, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initialize the SAI according to the specified parameters.

in the SAI_InitTypeDef structure and initialize the associated handle.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 369 of file stm32g4xx_hal_sai.c.

References SAI_PdmInitTypeDef::Activation, SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_PdmInitTypeDef::ClockEnable, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_RCCEx_GetPeriphCLKFreq(), HAL_SAI_ERROR_NONE, HAL_SAI_ErrorCallback(), HAL_SAI_MspInit(), HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MASTER_DIVIDER, IS_SAI_BLOCK_MCK_OUTPUT, IS_SAI_BLOCK_MCK_OVERSAMPLING, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_PDM_CLOCK_ENABLE, IS_SAI_PDM_MIC_PAIRS_NUMBER, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MckOutput, SAI_InitTypeDef::MckOverSampling, SAI_PdmInitTypeDef::MicPairsNbr, SAI_InitTypeDef::MonoStereoMode, __SAI_HandleTypeDef::MspInitCallback, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::PdmInit, SAI_InitTypeDef::Protocol, RCC_PERIPHCLK_SAI1, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, SAI_AC97_FRAME_LENGTH, SAI_AC97_PROTOCOL, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_FREE_PROTOCOL, SAI_MASTERDIVIDER_DISABLE, SAI_MCK_OVERSAMPLING_ENABLE, SAI_MODEMASTER_RX, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_SPDIF_FRAME_LENGTH, SAI_SPDIF_PROTOCOL, SAI_SYNCHRONOUS, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, SAI_InitTypeDef::TriState, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol SAI Supported protocol
datasize | one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot | Number of slot.
Return values:
HAL status

Definition at line 330 of file stm32g4xx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 706 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_DeInit(), and HAL_SAI_UnRegisterCallback().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

Initialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 690 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), and HAL_SAI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SAI_RegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID,
 |  | pSAI_CallbackTypeDef | pCallback
 | ) |  |

Register a user SAI callback to be used instead of the weak predefined callback.

Parameters:
hsai | SAI handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 733 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_SAI_UnRegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user SAI callback.

SAI callback is redirected to the weak predefined callback.

Parameters:
hsai SAI handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 825 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_ErrorCallback(), HAL_SAI_MspDeInit(), HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MspInit(), HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
      (++) Blocking mode : The communication is performed in the polling mode.
           The status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode : The communication is performed using Interrupts
           or DMA. These functions return the status of the transfer startup.
           The end of the data processing will be indicated through the
           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.

    (+) Blocking mode functions are :
      (++) HAL_SAI_Transmit()
      (++) HAL_SAI_Receive()

    (+) Non Blocking mode functions with Interrupt are :
      (++) HAL_SAI_Transmit_IT()
      (++) HAL_SAI_Receive_IT()

    (+) Non Blocking mode functions with DMA are :
      (++) HAL_SAI_Transmit_DMA()
      (++) HAL_SAI_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
      (++) HAL_SAI_TxCpltCallback()
      (++) HAL_SAI_RxCpltCallback()
      (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disable the SAI.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1387 of file stm32g4xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Rx mute detection.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1663 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Tx mute mode.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1622 of file stm32g4xx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pause the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1290 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resume the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1310 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stop the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1337 of file stm32g4xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the Rx mute detection.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback | function called when the mute is detected.
counter | number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1640 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the Tx mute mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val | value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1603 of file stm32g4xx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2019 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

Handle SAI interrupt request.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1682 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_DMA, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_DMAAbort(), SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __SAI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1060 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1534 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1232 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1987 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2003 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 947 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1447 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_FIFOSTATUS_EMPTY, SAI_InterruptFlag(), SAI_LONG_TIMEOUT, SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1170 of file stm32g4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1955 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1971 of file stm32g4xx_hal_sai.c.

References UNUSED.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (const SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (const SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

  ===============================================================================
                ##### Peripheral State and Errors functions #####
  ===============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( const SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 2065 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( const SAI_HandleTypeDef * hsai )

Return the SAI handle state.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 2054 of file stm32g4xx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI_PdmInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_PdmInitTypeDef Struct Reference
SAI PDM Structure definition

#include <stm32g4xx_hal_sai.h>

Data Fields

FunctionalState | Activation
uint32_t | MicPairsNbr
uint32_t | ClockEnable

Detailed Description

Definition at line 64 of file stm32g4xx_hal_sai.h.

Field Documentation

FunctionalState SAI_PdmInitTypeDef::Activation

Enable/disable PDM interface

Definition at line 66 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::ClockEnable

Specifies which clock must be enabled. This parameter can be a values combination of SAI PDM Clock Enable

Definition at line 69 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::MicPairsNbr

Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 67 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Init Structure definition

#include <stm32g4xx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | MckOutput
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MckOverSampling
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
SAI_PdmInitTypeDef PdmInit
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

Definition at line 80 of file stm32g4xx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 112 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 82 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 146 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 126 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 140 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 109 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 143 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider. This parameter must be a number between Min_Data = 0 and Max_Data = 63.

Note:
This parameter is used only if AudioFrequency is set to SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed.

Definition at line 115 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOutput

Specifies whether master clock output will be generated or not. This parameter can be a value of SAI Block Master Clock Output

Definition at line 94 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOverSampling

Specifies the master clock oversampling. This parameter can be a value of SAI Block Master Clock OverSampling

Definition at line 120 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 123 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values from 8 to 256.

Definition at line 102 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
This value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 97 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAI_PdmInitTypeDef SAI_InitTypeDef::PdmInit

Specifies the PDM configuration.

Definition at line 132 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 137 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 85 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of SAI External synchronisation

Note:
If both audio blocks of same SAI are used, this parameter has to be set to the same value for each audio block

Definition at line 88 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 129 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Frame Structure definition

#include <stm32g4xx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

Definition at line 158 of file stm32g4xx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 167 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 161 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 172 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 178 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 175 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Slot Structure definition

#include <stm32g4xx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

Definition at line 192 of file stm32g4xx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 194 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 203 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 200 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 197 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Handle Structure definition

Data Structures | Typedefs
SAI Handle Structure definition
SAI Exported Types

SAI handle Structure definition. More...

Data Structures

struct | __SAI_HandleTypeDef

Typedefs

typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Detailed Description

SAI handle Structure definition.

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Handle Structure definition

#include <stm32g4xx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | RxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | RxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | ErrorCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspInitCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspDeInitCallback )(struct __SAI_HandleTypeDef *hsai)

Detailed Description

Definition at line 214 of file stm32g4xx_hal_sai.h.

Field Documentation

void(* __SAI_HandleTypeDef::ErrorCallback)(struct __SAI_HandleTypeDef *hsai)

SAI error callback

Definition at line 249 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 242 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), SAI_Disable(), SAI_DMAAbort(), and SAI_DMAError().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 220 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 232 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Receive_DMA().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 230 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Transmit_DMA().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 218 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 216 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_Disable(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 236 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 238 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

void(* __SAI_HandleTypeDef::MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP de-init callback

Definition at line 251 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

void(* __SAI_HandleTypeDef::MspInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP init callback

Definition at line 250 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 234 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 224 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::RxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive complete callback

Definition at line 245 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void(* __SAI_HandleTypeDef::RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive half complete callback

Definition at line 246 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 222 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 240 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit complete callback

Definition at line 247 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit half complete callback

Definition at line 248 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 228 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 226 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Exported Types

Modules | Typedefs | Enumerations
SAI Exported Types
SAI

Modules

SAI PDM Structure definition

SAI PDM Init structure definition.

SAI Init Structure definition

SAI Init Structure definition.

SAI Frame Structure definition

SAI Frame Init structure definition.

SAI Slot Structure definition

SAI Block Slot Init Structure definition.

SAI Handle Structure definition

SAI handle Structure definition.

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai)

SAI callback pointer definition.

Definition at line 276 of file stm32g4xx_hal_sai.h.

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 58 of file stm32g4xx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_CallbackIDTypeDef

SAI callback ID enumeration definition.

Enumerator:
HAL_SAI_RX_COMPLETE_CB_ID

SAI receive complete callback ID

HAL_SAI_RX_HALFCOMPLETE_CB_ID

SAI receive half complete callback ID

HAL_SAI_TX_COMPLETE_CB_ID

SAI transmit complete callback ID

HAL_SAI_TX_HALFCOMPLETE_CB_ID

SAI transmit half complete callback ID

HAL_SAI_ERROR_CB_ID

SAI error callback ID

HAL_SAI_MSPINIT_CB_ID

SAI MSP init callback ID

HAL_SAI_MSPDEINIT_CB_ID

SAI MSP de-init callback ID

Definition at line 262 of file stm32g4xx_hal_sai.h.

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

Definition at line 46 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Define Documentation

#define HAL_SAI_ERROR_AFSDET 0x00000004U

Anticipated Frame synchronisation detection

Definition at line 294 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY 0x00000010U

codec not ready

Definition at line 296 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_DMA 0x00000080U

DMA error

Definition at line 299 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAError().

#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Invalid callback error

Definition at line 301 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

#define HAL_SAI_ERROR_LFSDET 0x00000008U

Late Frame synchronisation detection

Definition at line 295 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE 0x00000000U

No error

Definition at line 291 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR 0x00000001U

Overrun Error

Definition at line 292 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT 0x00000040U

Timeout error

Definition at line 298 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR 0x00000002U

Underrun error

Definition at line 293 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG 0x00000020U

Wrong clock configuration

Definition at line 297 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAAbort().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define SAI_SYNCEXT_DISABLE 0U

Define Documentation

#define SAI_SYNCEXT_DISABLE 0U

Definition at line 310 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Master Clock Output

Defines
SAI Block Master Clock Output
SAI Exported Constants

Defines

#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Define Documentation

#define SAI_MCK_OUTPUT_DISABLE 0x00000000U

Definition at line 318 of file stm32g4xx_hal_sai.h.

#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Definition at line 319 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U

Define Documentation

#define SAI_I2S_LSBJUSTIFIED 2U

Definition at line 329 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED 1U

Definition at line 328 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_I2S_STANDARD 0U

Definition at line 327 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG 3U

Definition at line 330 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_PCM_SHORT 4U

Definition at line 331 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT 0U

Definition at line 339 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U

Definition at line 340 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT 2U

Definition at line 341 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT 3U

Definition at line 342 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K 11025U

Definition at line 357 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K 16000U

Definition at line 356 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K 192000U

Definition at line 350 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K 22050U

Definition at line 355 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K 32000U

Definition at line 354 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K 44100U

Definition at line 353 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K 48000U

Definition at line 352 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K 8000U

Definition at line 358 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K 96000U

Definition at line 351 of file stm32g4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV 0U

Definition at line 359 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Master Clock OverSampling

Defines
SAI Block Master Clock OverSampling
SAI Exported Constants

Defines

#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Define Documentation

#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U

Definition at line 367 of file stm32g4xx_hal_sai.h.

#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Definition at line 368 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI PDM Clock Enable

Defines
SAI PDM Clock Enable
SAI Exported Constants

Defines

#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Define Documentation

#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1

Definition at line 376 of file stm32g4xx_hal_sai.h.

#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Definition at line 377 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Define Documentation

#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0

Definition at line 386 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_MODEMASTER_TX 0x00000000U

Definition at line 385 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Definition at line 388 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1

Definition at line 387 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Define Documentation

#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Definition at line 399 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL 0x00000000U

Definition at line 397 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0

Definition at line 398 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Define Documentation

#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 408 of file stm32g4xx_hal_sai.h.

#define SAI_DATASIZE_16 SAI_xCR1_DS_2

Definition at line 409 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)

Definition at line 410 of file stm32g4xx_hal_sai.h.

#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)

Definition at line 411 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 412 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 SAI_xCR1_DS_1

Definition at line 407 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Define Documentation

#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Definition at line 421 of file stm32g4xx_hal_sai.h.

#define SAI_FIRSTBIT_MSB 0x00000000U

Definition at line 420 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE 0U

Definition at line 429 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE 1U

Definition at line 430 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U

Define Documentation

#define SAI_ASYNCHRONOUS 0U

Asynchronous

Definition at line 438 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS 1U

Synchronous with other block of same SAI

Definition at line 439 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U

Definition at line 447 of file stm32g4xx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Definition at line 448 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Definition at line 457 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_MASTERDIVIDER_ENABLE 0x00000000U

Definition at line 456 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Definition at line 466 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME 0x00000000U

Definition at line 465 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Define Documentation

#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Definition at line 475 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW 0x00000000U

Definition at line 474 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Definition at line 484 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT 0x00000000U

Definition at line 483 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Define Documentation

#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0

Definition at line 493 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Definition at line 494 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE 0x00000000U

Definition at line 492 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU

Define Documentation

#define SAI_SLOT_NOTACTIVE 0x00000000U

Definition at line 502 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_0 0x00000001U

Definition at line 503 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_1 0x00000002U

Definition at line 504 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_10 0x00000400U

Definition at line 513 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_11 0x00000800U

Definition at line 514 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_12 0x00001000U

Definition at line 515 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_13 0x00002000U

Definition at line 516 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_14 0x00004000U

Definition at line 517 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_15 0x00008000U

Definition at line 518 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_2 0x00000004U

Definition at line 505 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_3 0x00000008U

Definition at line 506 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_4 0x00000010U

Definition at line 507 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_5 0x00000020U

Definition at line 508 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_6 0x00000040U

Definition at line 509 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_7 0x00000080U

Definition at line 510 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_8 0x00000100U

Definition at line 511 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_9 0x00000200U

Definition at line 512 of file stm32g4xx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL 0x0000FFFFU

Definition at line 519 of file stm32g4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO

Define Documentation

#define SAI_MONOMODE SAI_xCR1_MONO

Definition at line 528 of file stm32g4xx_hal_sai.h.

#define SAI_STEREOMODE 0x00000000U

Definition at line 527 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Define Documentation

#define SAI_OUTPUT_NOTRELEASED 0x00000000U

Definition at line 536 of file stm32g4xx_hal_sai.h.

#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Definition at line 537 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0

Definition at line 546 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)

Definition at line 548 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U

Definition at line 545 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Definition at line 549 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1

Definition at line 547 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)

Definition at line 559 of file stm32g4xx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Definition at line 561 of file stm32g4xx_hal_sai.h.

#define SAI_NOCOMPANDING 0x00000000U

Definition at line 557 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1

Definition at line 558 of file stm32g4xx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)

Definition at line 560 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Define Documentation

#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Definition at line 570 of file stm32g4xx_hal_sai.h.

#define SAI_ZERO_VALUE 0x00000000U

Definition at line 569 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Define Documentation

#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE

Definition at line 583 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE

Definition at line 582 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ SAI_xIMR_FREQIE

Definition at line 581 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Definition at line 584 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE

Definition at line 579 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE

Definition at line 578 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE

Definition at line 580 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET

Define Documentation

#define SAI_FLAG_AFSDET SAI_xSR_AFSDET

Definition at line 597 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY SAI_xSR_CNRDY

Definition at line 596 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ SAI_xSR_FREQ

Definition at line 595 of file stm32g4xx_hal_sai.h.

#define SAI_FLAG_LFSDET SAI_xSR_LFSDET

Definition at line 598 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET

Definition at line 593 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR

Definition at line 592 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG

Definition at line 594 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U

Definition at line 608 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U

Definition at line 610 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY 0x00000000U

Definition at line 606 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), and HAL_SAI_Transmit_DMA().

#define SAI_FIFOSTATUS_FULL 0x00050000U

Definition at line 611 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL 0x00030000U

Definition at line 609 of file stm32g4xx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U

Definition at line 607 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the specified SAI pending flag.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 715 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Disable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 727 of file stm32g4xx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Disable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 668 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Enable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 721 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 653 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 699 of file stm32g4xx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->IMR\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SAI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 683 of file stm32g4xx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
                                                     (__HANDLE__)->MspInitCallback = NULL;      \
                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
                                                   } while(0)

Reset SAI handle state.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 631 of file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Private Macros

Defines
SAI Private Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 833 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Definition at line 927 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 866 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 886 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 856 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 892 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 863 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24U)

Definition at line 912 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))

Definition at line 925 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 920 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 914 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 917 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 63U)

Definition at line 923 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MCK_OUTPUT ( VALUE )
Value:
(((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
                                        ((VALUE) == SAI_MCK_OUTPUT_DISABLE))

Definition at line 872 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MCK_OVERSAMPLING ( VALUE )
Value:
(((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))

Definition at line 839 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                  ((MODE) == SAI_MODEMASTER_RX) || \
                                  ((MODE) == SAI_MODESLAVE_TX)  || \
                                  ((MODE) == SAI_MODESLAVE_RX))

Definition at line 847 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63U)

Definition at line 881 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 883 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 878 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 875 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 852 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))

Definition at line 906 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 908 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE ) ((STATE) == SAI_SYNCEXT_DISABLE)

Definition at line 820 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS))

Definition at line 869 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 898 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 901 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_CLOCK_ENABLE ( CLOCK )
Value:
(((CLOCK) != 0U) && \
                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))

Definition at line 844 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_MIC_PAIRS_NUMBER ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 3U))

Definition at line 842 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), and HAL_SAIEx_ConfigPdmMicDelay().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 828 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 904 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 822 of file stm32g4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx Extended Private Defines

Defines
SAIEx Extended Private Defines
SAIEx

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Define Documentation

#define SAI_PDM_DELAY_MASK 0x77U

Definition at line 42 of file stm32g4xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_DELAY_OFFSET 8U

Definition at line 43 of file stm32g4xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_RIGHT_DELAY_OFFSET 4U

Definition at line 44 of file stm32g4xx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SAIEx Extended Exported Functions

SAIEx control functions. More...

Functions

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay (const SAI_HandleTypeDef *hsai, const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAIEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Modify PDM microphone delays

Function Documentation

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay | ( | const SAI_HandleTypeDef * | hsai,
 |  | const SAIEx_PdmMicDelayParamTypeDef * | pdmMicDelay
 | ) |  |

Configure PDM microphone delays.

Parameters:
hsai | SAI handle.
pdmMicDelay | Microphone delays configuration.
Return values:
HAL status

Definition at line 76 of file stm32g4xx_hal_sai_ex.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_PDM_MIC_DELAY, IS_SAI_PDM_MIC_PAIRS_NUMBER, SAIEx_PdmMicDelayParamTypeDef::LeftDelay, SAIEx_PdmMicDelayParamTypeDef::MicPair, SAIEx_PdmMicDelayParamTypeDef::RightDelay, SAI_PDM_DELAY_MASK, SAI_PDM_DELAY_OFFSET, SAI_PDM_RIGHT_DELAY_OFFSET, and __SAI_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx_PdmMicDelayParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAIEx_PdmMicDelayParamTypeDef Struct Reference
SAIEx Exported Types

PDM microphone delay structure definition. More...

#include <stm32g4xx_hal_sai_ex.h>

Data Fields

uint32_t | MicPair
uint32_t | LeftDelay
uint32_t | RightDelay

Detailed Description

PDM microphone delay structure definition.

Definition at line 46 of file stm32g4xx_hal_sai_ex.h.

Field Documentation

uint32_t SAIEx_PdmMicDelayParamTypeDef::LeftDelay

Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 51 of file stm32g4xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::MicPair

Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 48 of file stm32g4xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::RightDelay

Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 54 of file stm32g4xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_sai_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx Extended Private Macros

Defines
SAIEx Extended Private Macros
SAIEx

Defines

#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Define Documentation

#define IS_SAI_PDM_MIC_DELAY ( VALUE ) ((VALUE) <= 7U)

Definition at line 86 of file stm32g4xx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 202 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 219 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 217 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
                                      USART_CR1_RE | USART_CR1_OVER8| \
                                      USART_CR1_FIFOEN))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 204 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS
Value:
((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
                                          USART_CR2_CPHA | USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 208 of file stm32g4xx_hal_smartcard.c.

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
                                      USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 211 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 214 of file stm32g4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 391 of file stm32g4xx_hal_smartcard.c.

References assert_param, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::MspDeInitCallback, and __SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 318 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::Lock, __SMARTCARD_HandleTypeDef::MspInitCallback, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 457 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_DeInit(), and HAL_SMARTCARD_UnRegisterCallback().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 441 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_Init(), and HAL_SMARTCARD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID,
 |  | pSMARTCARD_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMARTCARD Callback To be used to override the weak predefined callback.

Note:
The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID and HAL_SMARTCARD_MSPDEINIT_CB_ID
Parameters:
hsmartcard | smartcard handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 490 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Note:
The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID and HAL_SMARTCARD_MSPDEINIT_CB_ID
Parameters:
hsmartcard smartcard handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 612 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (#) There are two modes of transfer:
        (##) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (##) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (#) Blocking mode APIs are :
        (##) HAL_SMARTCARD_Transmit()
        (##) HAL_SMARTCARD_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (##) HAL_SMARTCARD_Transmit_IT()
        (##) HAL_SMARTCARD_Receive_IT()
        (##) HAL_SMARTCARD_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (##) HAL_SMARTCARD_Transmit_DMA()
        (##) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (##) HAL_SMARTCARD_TxCpltCallback()
        (##) HAL_SMARTCARD_RxCpltCallback()
        (##) HAL_SMARTCARD_ErrorCallback()

  [..]
    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (##) HAL_SMARTCARD_Abort()
        (##) HAL_SMARTCARD_AbortTransmit()
        (##) HAL_SMARTCARD_AbortReceive()
        (##) HAL_SMARTCARD_Abort_IT()
        (##) HAL_SMARTCARD_AbortTransmit_IT()
        (##) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
        a set of Abort Complete Callbacks are provided:
        (##) HAL_SMARTCARD_AbortCpltCallback()
        (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (##) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error,
           Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer,
           Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
           If user wants to abort it, Abort services should be called by user.
       (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
           mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1317 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1539 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2203 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1471 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1776 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2235 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1408 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1681 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2219 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2187 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1870 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback, __SMARTCARD_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 913 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 1237 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_RDR register can be read, i.e one interrupt per data to receive.
When FIFO mode is enabled, USART interrupt is generated whenever RXFIFO threshold reached. In that case the interrupt rate depends on RXFIFO threshold configuration.
This function sets the hsmartcard->RxIsr function pointer according to the FIFO mode (data reception processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 1075 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2171 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 807 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX, SMARTCARD_MODE_TX_RX, SMARTCARD_NACK_ENABLE, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 1139 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_MODE_TX, SMARTCARD_NACK_ENABLE, __SMARTCARD_HandleTypeDef::TxXferCount, __SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_TDR register is empty, i.e one interrupt per data to transmit.
When FIFO mode is enabled, USART interrupt is generated whenever TXFIFO threshold reached. In that case the interrupt rate depends on TXFIFO threshold configuration.
This function sets the hsmartcard->TxIsr function pointer according to the FIFO mode (data transmission processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 981 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_MODE_TX, SMARTCARD_NACK_ENABLE, SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2155 of file stm32g4xx_hal_smartcard.c.

References UNUSED.

Referenced by HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( const SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 2291 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( const SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 2274 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, and __SMARTCARD_HandleTypeDef::RxState.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2472 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2534 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2747 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxXferCount, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2707 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2676 of file stm32g4xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxState, and __SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2819 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2897 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2657 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2770 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2868 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2640 of file stm32g4xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static void SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2997 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_MODE_TX, SMARTCARD_MODE_TX_RX, SMARTCARD_NACK_ENABLE, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxISR.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2623 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void SMARTCARD_InitCallbacksToDefault ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the callbacks to their default values.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
none

Definition at line 2314 of file stm32g4xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_RxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3050 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_Receive_IT(), and SMARTCARD_RxISR_FIFOEN().

static void SMARTCARD_RxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3103 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_RXDATA_FLUSH_REQUEST, and SMARTCARD_RxISR().

Referenced by HAL_SMARTCARD_Receive_IT().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2339 of file stm32g4xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::ClockPrescaler, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_CLOCKPRESCALER, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, __SMARTCARD_HandleTypeDef::RxISR, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK1, SMARTCARD_CLOCKSOURCE_PCLK2, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, __SMARTCARD_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_TxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2929 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static void SMARTCARD_TxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2960 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The actual Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 2588 of file stm32g4xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Typedefs | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initialization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U,
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Typedef Documentation

typedef uint32_t HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see SMARTCARD State Code Definition).
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 191 of file stm32g4xx_hal_smartcard.h.

typedef void(* pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard)

HAL SMARTCARD Callback pointer definition.

pointer to an SMARTCARD callback function

Definition at line 292 of file stm32g4xx_hal_smartcard.h.

typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_HandleTypeDef

SMARTCARD handle Structure definition.

Enumeration Type Documentation

enum HAL_SMARTCARD_CallbackIDTypeDef

HAL SMARTCARD Callback ID enumeration definition.

Enumerator:
HAL_SMARTCARD_TX_COMPLETE_CB_ID

SMARTCARD Tx Complete Callback ID

HAL_SMARTCARD_RX_COMPLETE_CB_ID

SMARTCARD Rx Complete Callback ID

HAL_SMARTCARD_ERROR_CB_ID

SMARTCARD Error Callback ID

HAL_SMARTCARD_ABORT_COMPLETE_CB_ID

SMARTCARD Abort Complete Callback ID

HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID

SMARTCARD Abort Transmit Complete Callback ID

HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID

SMARTCARD Abort Receive Complete Callback ID

HAL_SMARTCARD_RX_FIFO_FULL_CB_ID

SMARTCARD Rx Fifo Full Callback ID

HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID

SMARTCARD Tx Fifo Empty Callback ID

HAL_SMARTCARD_MSPINIT_CB_ID

SMARTCARD MspInit callback ID

HAL_SMARTCARD_MSPDEINIT_CB_ID

SMARTCARD MspDeInit callback ID

Definition at line 273 of file stm32g4xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK1

PCLK1 clock source

SMARTCARD_CLOCKSOURCE_PCLK2

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 299 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32g4xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount
uint32_t | ClockPrescaler

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 46 of file stm32g4xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 104 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) where usart_ker_ckpres is the USART input clock divided by a prescaler

Definition at line 48 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 101 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 75 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 72 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 69 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of SMARTCARD Clock Prescaler.

Definition at line 109 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 88 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 66 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 90 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 79 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 60 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler. This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency

Definition at line 84 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 57 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 94 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 97 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 53 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_smartcard.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initialization structure definition. More...

#include <stm32g4xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initialization structure definition.

Definition at line 117 of file stm32g4xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 119 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 129 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 139 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 142 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 136 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 126 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 133 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 145 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 123 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_smartcard.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32g4xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | FifoMode
void(* | RxISR )(struct __SMARTCARD_HandleTypeDef *huart)
void(* | TxISR )(struct __SMARTCARD_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | ErrorCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortTransmitCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortReceiveCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxFifoFullCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | TxFifoEmptyCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspDeInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 196 of file stm32g4xx_hal_smartcard.h.

Field Documentation

void(* __SMARTCARD_HandleTypeDef::AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Complete Callback

Definition at line 252 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Receive Complete Callback

Definition at line 256 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Transmit Complete Callback

Definition at line 254 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

SMARTCARD_AdvFeatureInitTypeDef __SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 202 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Error Callback

Definition at line 250 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

__IO uint32_t __SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 243 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

uint32_t __SMARTCARD_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of SMARTCARD FIFO mode.

Definition at line 220 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 234 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 230 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 228 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef __SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 200 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* __SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 198 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), SMARTCARD_WaitOnFlagUntilTimeout(), and SMARTCARDEx_SetNbDataToProcess().

HAL_LockTypeDef __SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 232 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

void(* __SMARTCARD_HandleTypeDef::MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp DeInit callback

Definition at line 264 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

void(* __SMARTCARD_HandleTypeDef::MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp Init callback

Definition at line 262 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

uint16_t __SMARTCARD_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 216 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

uint16_t __SMARTCARD_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 218 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARDEx_SetNbDataToProcess().

uint8_t* __SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 210 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

const uint8_t* __SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 204 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Complete Callback

Definition at line 248 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Fifo Full Callback

Definition at line 258 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::RxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 224 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_SetConfig().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 239 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t __SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 214 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 212 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

void(* __SMARTCARD_HandleTypeDef::TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Complete Callback

Definition at line 246 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Fifo Empty Callback

Definition at line 260 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 226 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

__IO uint16_t __SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 208 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 206 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_smartcard.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD State Code Definition

Defines
SMARTCARD State Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_SMARTCARD_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 326 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 330 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 328 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 332 of file stm32g4xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 339 of file stm32g4xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_READY 0x00000020U

Peripheral Initialized and ready for use. Value is allowed for gState and RxState

Definition at line 323 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define HAL_SMARTCARD_STATE_RESET 0x00000000U

Peripheral is not initialized. Value is allowed for gState and RxState

Definition at line 321 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 337 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Error Code Definition

Defines
SMARTCARD Error Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 353 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), and SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE (0x00000004U)

frame error

Definition at line 351 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 356 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_ERROR_NE (0x00000002U)

Noise error

Definition at line 350 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE (0x00000000U)

No error

Definition at line 348 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 352 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE (0x00000001U)

Parity error

Definition at line 349 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO (0x00000020U)

Receiver TimeOut error

Definition at line 354 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

SMARTCARD frame length

Definition at line 365 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

Define Documentation

#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0

SMARTCARD frame with 0.5 stop bit

Definition at line 373 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

SMARTCARD frame with 1.5 stop bits

Definition at line 374 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define SMARTCARD_PARITY_EVEN USART_CR1_PCE

SMARTCARD frame even parity

Definition at line 382 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

SMARTCARD frame odd parity

Definition at line 383 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define SMARTCARD_MODE_RX USART_CR1_RE

SMARTCARD RX mode

Definition at line 391 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX USART_CR1_TE

SMARTCARD TX mode

Definition at line 392 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

SMARTCARD RX and TX mode

Definition at line 393 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

SMARTCARD frame high polarity

Definition at line 402 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW 0x00000000U

SMARTCARD frame low polarity

Definition at line 401 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define SMARTCARD_PHASE_1EDGE 0x00000000U

SMARTCARD frame phase on first clock transition

Definition at line 410 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

SMARTCARD frame phase on second clock transition

Definition at line 411 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE 0x00000000U

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 419 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 420 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U

SMARTCARD frame one-bit sample disabled

Definition at line 428 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

SMARTCARD frame one-bit sample enabled

Definition at line 429 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK

Define Documentation

#define SMARTCARD_NACK_DISABLE 0x00000000U

SMARTCARD NACK transmission disabled

Definition at line 437 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE USART_CR3_NACK

SMARTCARD NACK transmission enabled

Definition at line 438 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U

SMARTCARD receiver timeout disabled

Definition at line 446 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

SMARTCARD receiver timeout enabled

Definition at line 447 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Clock Prescaler

Defines
SMARTCARD Clock Prescaler
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define SMARTCARD_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 455 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 460 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 461 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 465 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 462 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 456 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 466 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 463 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 457 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 458 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 464 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 459 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 474 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 475 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 483 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 484 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 492 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 493 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 501 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 502 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 511 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 510 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 520 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 519 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 528 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 529 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive data flush request

Definition at line 537 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush request

Definition at line 538 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U

Define Documentation

#define SMARTCARD_CR_MASK 0x00E0U

SMARTCARD control register mask

Definition at line 547 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_CR_POS 5U

SMARTCARD control register position

Definition at line 548 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ISR_MASK 0x1F00U

SMARTCARD ISR register mask

Definition at line 549 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_ISR_POS 8U

SMARTCARD ISR register position

Definition at line 550 of file stm32g4xx_hal_smartcard.h.

#define SMARTCARD_IT_MASK 0x001FU

SMARTCARD interruptions flags mask

Definition at line 546 of file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 620 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
Return values:
None

Definition at line 608 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 638 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 811 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 626 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 632 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 614 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 846 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 1U)?\
                                                                ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 2U)?\
                                                                ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 723 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 840 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 1U)?\
                                                                ((__HANDLE__)->Instance->CR1 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 2U)?\
                                                                ((__HANDLE__)->Instance->CR2 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 690 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                     \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 586 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
  • SMARTCARD_FLAG_TXFNF TXFIFO not full flag
  • SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
  • SMARTCARD_FLAG_TXFE TXFIFO Empty flag
  • SMARTCARD_FLAG_RXFF RXFIFO Full flag
  • SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
  • SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 666 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
                                                               & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
                                                           ? SET : RESET)

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 756 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                       SMARTCARD_CR_POS) == 0x01U)?\
                                                                     (__HANDLE__)->Instance->CR1 : \
                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                        SMARTCARD_CR_POS) == 0x02U)?\
                                                                      (__HANDLE__)->Instance->CR2 : \
                                                                      (__HANDLE__)->Instance->CR3)) &\
                                                                    (0x01UL << (((uint16_t)(__INTERRUPT__))\
                                                                                & SMARTCARD_IT_MASK)))  != 0U)\
                                                                  ? SET : RESET)

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 783 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 833 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 827 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
                                                          } while(0U)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__ SMARTCARD handle.
Return values:
None

Definition at line 569 of file stm32g4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 821 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9375001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__ SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1077 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1098 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__ SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1050 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__ SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1105 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__ SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1070 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1084 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__ SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1063 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7U)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__ number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 960 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 9375001U)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on G4 (150 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__ Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 939 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFFU)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__ block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 946 of file stm32g4xx_hal_smartcard.h.

#define IS_SMARTCARD_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))

Ensure that SMARTCARD clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1033 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 1005 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__ SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 986 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__ SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 1019 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__ SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1012 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__ SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1091 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__ SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 979 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__ SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 999 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ )
Value:
(((__CPOL__) == SMARTCARD_POLARITY_LOW)\
                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__ SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 992 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__ SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1112 of file stm32g4xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__ SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 972 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__ SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1026 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 953 of file stm32g4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__ SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 966 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__ | specifies the SMARTCARD Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 862 of file stm32g4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Extended Private Constants

Defines
SMARTCARD Extended Private Constants
SMARTCARDEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 62 of file stm32g4xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 65 of file stm32g4xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength | SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 104 of file stm32g4xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 157 of file stm32g4xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 127 of file stm32g4xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 116 of file stm32g4xx_hal_smartcard_ex.c.

References assert_param, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral IO operation functions

Functions
Extended Peripheral IO operation functions
SMARTCARD Extended Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (++) HAL_SMARTCARDEx_RxFifoFullCallback()
        (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()

Function Documentation

void HAL_SMARTCARDEx_RxFifoFullCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD RX Fifo full callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 210 of file stm32g4xx_hal_smartcard_ex.c.

References UNUSED.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARDEx_TxFifoEmptyCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD TX Fifo empty callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 226 of file stm32g4xx_hal_smartcard_ex.c.

References UNUSED.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral FIFO Control functions

Functions
Extended Peripheral FIFO Control functions
SMARTCARD Extended Exported Functions

SMARTCARD control functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD control functions.

 ===============================================================================
                  ##### Peripheral FIFO Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SMARTCARD
    FIFO feature.
     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 304 of file stm32g4xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 263 of file stm32g4xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FIFOMODE_ENABLE, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_RXFIFO_THRESHOLD_1_8
  • SMARTCARD_RXFIFO_THRESHOLD_1_4
  • SMARTCARD_RXFIFO_THRESHOLD_1_2
  • SMARTCARD_RXFIFO_THRESHOLD_3_4
  • SMARTCARD_RXFIFO_THRESHOLD_7_8
  • SMARTCARD_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 399 of file stm32g4xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_RXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_TXFIFO_THRESHOLD_1_8
  • SMARTCARD_TXFIFO_THRESHOLD_1_4
  • SMARTCARD_TXFIFO_THRESHOLD_1_2
  • SMARTCARD_TXFIFO_THRESHOLD_3_4
  • SMARTCARD_TXFIFO_THRESHOLD_7_8
  • SMARTCARD_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 350 of file stm32g4xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Extended Private Functions

Functions
SMARTCARD Extended Private Functions
SMARTCARDEx

Functions

static void SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void SMARTCARDEx_SetNbDataToProcess ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
hsmartcard SMARTCARD handle.
Return values:
None

Definition at line 454 of file stm32g4xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, SMARTCARD_FIFOMODE_DISABLE, and TX_FIFO_DEPTH.

Referenced by HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Define Documentation

#define IS_SMARTCARD_FIFOMODE_STATE ( __STATE__ )
Value:
(((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

Ensure that SMARTCARD FIFO mode is valid.

Parameters:
__STATE__ SMARTCARD FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 239 of file stm32g4xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 257 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetRxFifoThreshold().

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ )
Value:
(((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 232 of file stm32g4xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 246 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetTxFifoThreshold().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))

Return the transmission completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is reported.
Return values:
Transmission completion flag

Definition at line 224 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                                                                       \
    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
    {                                                                                                        \
      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
    }                                                                                                        \
    else                                                                                                     \
    {                                                                                                        \
      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
    }                                                                                                        \
  } while(0U)

Set the Transmission Completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
If TCBGT (Transmission Complete Before Guard Time) flag is not available or if AdvancedInit.TxCompletionIndication is not already filled, the latter is forced to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
Return values:
None

Definition at line 205 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 49 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT

SMARTCARD transmission complete before guard time

Definition at line 48 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 60 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 63 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 64 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 57 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 59 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 62 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 61 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

TX completion indication before of after guard time

Definition at line 65 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 58 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD FIFO mode

Defines
SMARTCARD FIFO mode
SMARTCARD Extended Exported Constants

SMARTCARD FIFO mode. More...

Defines

#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

SMARTCARD FIFO mode.

Define Documentation

#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 74 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 75 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), and HAL_SMARTCARDEx_EnableFifoMode().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD TXFIFO threshold level

Defines
SMARTCARD TXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD TXFIFO level. More...

Defines

#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

SMARTCARD TXFIFO level.

Define Documentation

#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 86 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 85 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 84 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 87 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 88 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 89 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD RXFIFO threshold level

Defines
SMARTCARD RXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD RXFIFO level. More...

Defines

#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

SMARTCARD RXFIFO level.

Define Documentation

#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 100 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 99 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 98 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 101 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 102 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 103 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 116 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 117 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 127 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 124 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 126 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 125 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 128 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 114 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 118 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF

SMARTCARD RXFIFO Full flag

Definition at line 130 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE

SMARTCARD RXFIFO not empty

Definition at line 123 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT

SMARTCARD RXFIFO threshold flag

Definition at line 131 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE

SMARTCARD read data register not empty

Definition at line 122 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 121 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT

SMARTCARD transmission complete before guard time completion

Definition at line 113 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 115 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF

SMARTCARD transmit data register empty

Definition at line 119 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE

SMARTCARD TXFIFO Empty flag

Definition at line 129 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF

SMARTCARD TXFIFO not full

Definition at line 120 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT

SMARTCARD TXFIFO threshold flag

Definition at line 132 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB 0x0C3BU

SMARTCARD end of block interruption

Definition at line 160 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ERR 0x0060U

SMARTCARD error interruption

Definition at line 155 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_FE 0x0100U

SMARTCARD frame error interruption

Definition at line 158 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_IDLE 0x0424U

SMARTCARD idle line detection interruption

Definition at line 153 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE 0x0200U

SMARTCARD noise error interruption

Definition at line 157 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ORE 0x0300U

SMARTCARD overrun error interruption

Definition at line 156 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_PE 0x0028U

SMARTCARD parity error interruption

Definition at line 147 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RTO 0x0B3AU

SMARTCARD receiver timeout interruption

Definition at line 161 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFF 0x183FU

SMARTCARD RXFIFO full interruption

Definition at line 164 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFNE 0x0525U

SMARTCARD RXFIFO not empty interruption

Definition at line 152 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFT 0x1A7CU

SMARTCARD RXFIFO threshold reached interruption

Definition at line 166 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXNE 0x0525U

SMARTCARD read data register not empty interruption

Definition at line 151 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TC 0x0626U

SMARTCARD transmission complete interruption

Definition at line 150 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TCBGT 0x1978U

SMARTCARD transmission complete before guard time completion interruption

Definition at line 162 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE 0x0727U

SMARTCARD transmit data register empty interruption

Definition at line 148 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFE 0x173EU

SMARTCARD TXFIFO empty interruption

Definition at line 165 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFNF 0x0727U

SMARTCARD TX FIFO not full interruption

Definition at line 149 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFT 0x1B77U

SMARTCARD TXFIFO threshold reached interruption

Definition at line 167 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 184 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 176 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 179 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NECF

SMARTCARD noise error detected clear flag

Definition at line 177 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 178 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 175 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 183 of file stm32g4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF

SMARTCARD transmission complete before guard time completion clear flag

Definition at line 182 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 181 of file stm32g4xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty Clear Flag

Definition at line 180 of file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Define Documentation

#define HAL_TIMEOUT_ADDR (10000U)

10 s

Definition at line 192 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY (25U)

25 ms

Definition at line 193 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR (25U)

25 ms

Definition at line 194 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE (25U)

25 ms

Definition at line 195 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF (25U)

25 ms

Definition at line 196 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_TC (25U)

25 ms

Definition at line 197 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR (25U)

25 ms

Definition at line 198 of file stm32g4xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS (25U)

25 ms

Definition at line 199 of file stm32g4xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255U

Definition at line 200 of file stm32g4xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK (0xF0FFFFFFUL)

SMBUS TIMING clear register Mask

Definition at line 191 of file stm32g4xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
          HAL_SMBUS_ConfigDigitalFilter().

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure Analog noise filter.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
AnalogFilter This parameter can be one of the following values:
  • SMBUS_ANALOGFILTER_ENABLE
  • SMBUS_ANALOGFILTER_DISABLE
Return values:
HAL status

Definition at line 494 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ANALOG_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital noise filter.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 538 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_DIGITAL_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 414 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 289 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::AddrCallback, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspInit(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::Lock, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspInitCallback, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, __SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 475 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_UnRegisterCallback().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 459 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | pSMBUS_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 809 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_RegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID,
 |  | pSMBUS_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMBUS Callback To be used instead of the weak predefined callback.

Note:
The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and HAL_SMBUS_MSPDEINIT_CB_ID.
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 605 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback ( SMBUS_HandleTypeDef * hsmbus )

UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 845 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.

Note:
The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and HAL_SMBUS_MSPDEINIT_CB_ID
Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 718 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspDeInit(), HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MspInit(), HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1483 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1462 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1419 of file stm32g4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1443 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1403 of file stm32g4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1160 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1063 of file stm32g4xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 925 of file stm32g4xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_FIRST_FRAME_WITH_PEC, SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1323 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1225 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection | Master request Transfer Direction (Write/Read)
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 1778 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1702 of file stm32g4xx_hal_smbus.c.

References SMBUS_ITErrorHandler().

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1813 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1624 of file stm32g4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, SMBUS_CHECK_FLAG, SMBUS_CHECK_IT_SOURCE, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and __SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1797 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1729 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1713 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1760 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1744 of file stm32g4xx_hal_smbus.c.

References UNUSED.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( const SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1860 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( const SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1848 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1462 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1419 of file stm32g4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1443 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1403 of file stm32g4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1483 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1160 of file stm32g4xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1063 of file stm32g4xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 925 of file stm32g4xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_FIRST_FRAME_WITH_PEC, SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1323 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1225 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static void | SMBUS_Flush_TXDR (SMBUS_HandleTypeDef *hsmbus)
SMBUS Tx data register flush process.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2762 of file stm32g4xx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and __SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Disable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2483 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_Enable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2443 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Flush_TXDR ( SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS Tx data register flush process.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2703 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_TXE, and SMBUS_FLAG_TXIS.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_ITErrorHandler ( SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS interrupts error handler.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2555 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_Flush_TXDR(), SMBUS_IT_ERRI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_ER_IRQHandler(), and SMBUS_Master_ISR().

static HAL_StatusTypeDef SMBUS_Master_ISR | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 1885 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_Flush_TXDR(), SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_ITErrorHandler(), SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 2175 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::ListenCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_Flush_TXDR(), SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus | SMBUS handle.
DevAddress | specifies the slave address to be programmed.
Size | specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_RELOAD_MODE Enable Reload mode.
  • SMBUS_AUTOEND_MODE Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  • SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
Request New state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 2739 of file stm32g4xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag | Specifies the SMBUS flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2668 of file stm32g4xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32g4xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 47 of file stm32g4xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 58 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 52 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 61 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 71 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 74 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 55 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 64 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS ownaddress2 masks.

Definition at line 67 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 77 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 80 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 83 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 49 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_smbus.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 98 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUSEx_DisableWakeUp(), and HAL_SMBUSEx_EnableWakeUp().

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 103 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 100 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 99 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 97 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 96 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 102 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 101 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 115 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 119 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 114 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 113 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 118 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 117 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 122 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 124 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 112 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 116 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 120 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS handle Structure definition

Data Structures | Typedefs | Enumerations
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct | __SMBUS_HandleTypeDef

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Detailed Description

SMBUS handle Structure definition.

Typedef Documentation

typedef void(* pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an SMBUS Address Match callback function

Definition at line 207 of file stm32g4xx_hal_smbus.h.

typedef void(* pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus)

HAL SMBUS Callback pointer definition.

pointer to an SMBUS callback function

Definition at line 205 of file stm32g4xx_hal_smbus.h.

typedef struct __SMBUS_HandleTypeDef SMBUS_HandleTypeDef

Enumeration Type Documentation

enum HAL_SMBUS_CallbackIDTypeDef

HAL SMBUS Callback ID enumeration definition.

Enumerator:
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID

SMBUS Master Tx Transfer completed callback ID

HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID

SMBUS Master Rx Transfer completed callback ID

HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID

SMBUS Slave Tx Transfer completed callback ID

HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID

SMBUS Slave Rx Transfer completed callback ID

HAL_SMBUS_LISTEN_COMPLETE_CB_ID

SMBUS Listen Complete callback ID

HAL_SMBUS_ERROR_CB_ID

SMBUS Error callback ID

HAL_SMBUS_MSPINIT_CB_ID

SMBUS Msp Init callback ID

HAL_SMBUS_MSPDEINIT_CB_ID

SMBUS Msp DeInit callback ID

Definition at line 188 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32g4xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
void(* | MasterTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MasterRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ListenCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ErrorCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | AddrCallback )(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MspDeInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)

Detailed Description

Definition at line 134 of file stm32g4xx_hal_smbus.h.

Field Documentation

void(* __SMBUS_HandleTypeDef::AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

SMBUS Slave Address Match callback

Definition at line 173 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Error callback

Definition at line 170 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 157 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

SMBUS_InitTypeDef __SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 141 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* __SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 139 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Flush_TXDR(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

void(* __SMBUS_HandleTypeDef::ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Listen Complete callback

Definition at line 168 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

HAL_LockTypeDef __SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 153 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

void(* __SMBUS_HandleTypeDef::MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Rx Transfer completed callback

Definition at line 162 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Tx Transfer completed callback

Definition at line 160 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp DeInit callback

Definition at line 178 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

void(* __SMBUS_HandleTypeDef::MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp Init callback

Definition at line 176 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

uint8_t* __SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 143 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 151 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

void(* __SMBUS_HandleTypeDef::SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Rx Transfer completed callback

Definition at line 166 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Tx Transfer completed callback

Definition at line 164 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 155 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), SMBUS_WaitOnFlagUntilTimeout(), and SPI_WaitFifoStateUntilTimeout().

__IO uint16_t __SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 147 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 149 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t __SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 145 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_smbus.h
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 229 of file stm32g4xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 228 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 238 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 237 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 247 of file stm32g4xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 248 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS ownaddress2 masks

Defines
SMBUS ownaddress2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 258 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 259 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 260 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 261 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 262 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 263 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 264 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 257 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 273 of file stm32g4xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 274 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 282 of file stm32g4xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 283 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 291 of file stm32g4xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 292 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 300 of file stm32g4xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 301 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 302 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 313 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 312 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 314 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 311 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 325 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 326 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 324 of file stm32g4xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 323 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 341 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), and SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 344 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), and SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 339 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), and SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 343 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 342 of file stm32g4xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 345 of file stm32g4xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 340 of file stm32g4xx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 352 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 353 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 350 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 351 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX
#define | SMBUS_IT_RX
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 376 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 368 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 375 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 364 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_ITErrorHandler().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 367 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX
Value:
(SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
                                                 SMBUS_IT_RXI)

Definition at line 373 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 369 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 366 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 365 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX
Value:
(SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 371 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 370 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 391 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 392 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 401 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and SMBUS_ITErrorHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 397 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 396 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 402 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 403 of file stm32g4xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 398 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 399 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 390 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 393 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 394 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 395 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 400 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 388 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Flush_TXDR().

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 389 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Flush_TXDR(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == SMBUS_FLAG_TXE) ? \
                                                       ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
                                                       ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 525 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Flush_TXDR(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 539 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 461 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 533 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_Init(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 445 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 545 of file stm32g4xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 504 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), SMBUS_Flush_TXDR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 477 of file stm32g4xx_hal_smbus.h.

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                               \
                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                               } while(0)

Reset SMBUS handle state.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 422 of file stm32g4xx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_TXIS Transmit interrupt status
  • SMBUS_FLAG_RXNE Receive data register not empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_TC Transfer complete (master mode)
  • SMBUS_FLAG_TCR Transfer complete reload
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
  • SMBUS_FLAG_BUSY Bus busy
  • SMBUS_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 503 of file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__)
#define | SMBUS_RESET_CR2(__HANDLE__)
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                         ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 564 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                         ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 559 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), and HAL_SMBUS_Init().

#define IS_SMBUS_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 562 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigDigitalFilter().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                         ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 567 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 579 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 582 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 649 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 650 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 570 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                         ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 585 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 588 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                          || \
                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
                                                                  SMBUS_RELOAD_MODE )))

Definition at line 592 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

Definition at line 609 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 618 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
                                                         ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 603 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) |
Value:
((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
                                                          ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 645 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 647 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
                                                                      (~I2C_CR2_RD_WRN)) : \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 631 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

Definition at line 639 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 643 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 640 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 642 of file stm32g4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 641 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR1 &= \
                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
                                                                               I2C_CR1_PECEN)))

Definition at line 623 of file stm32g4xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR2 &= \
                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
                                                                               I2C_CR2_RD_WRN)))

Definition at line 626 of file stm32g4xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WakeUp Mode Functions

Functions
WakeUp Mode Functions
SMBUS Extended Exported Functions

WakeUp Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).

Detailed Description

WakeUp Mode Functions.

 ===============================================================================
                      ##### WakeUp Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp ( SMBUS_HandleTypeDef * hsmbus )

Disable SMBUS wakeup from Stop mode(s).

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 127 of file stm32g4xx_hal_smbus_ex.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp ( SMBUS_HandleTypeDef * hsmbus )

Enable SMBUS wakeup from Stop mode(s).

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 88 of file stm32g4xx_hal_smbus_ex.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, and __SMBUS_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Fast Mode Plus Functions

Functions
Fast Mode Plus Functions
SMBUS Extended Exported Functions

Fast Mode Plus Functions. More...

Functions

void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

Fast Mode Plus Functions.

 ===============================================================================
                      ##### Fast Mode Plus Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Fast Mode Plus

Function Documentation

void HAL_SMBUSEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the SMBUS fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the SMBUS Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 223 of file stm32g4xx_hal_smbus_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_SMBUS_FASTMODEPLUS.

void HAL_SMBUSEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the SMBUS fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the SMBUS Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
For all I2C4 pins fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
Return values:
None

Definition at line 194 of file stm32g4xx_hal_smbus_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_SMBUS_FASTMODEPLUS.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Fast Mode Plus

Defines
SMBUS Extended Fast Mode Plus
SMBUS Extended Exported Constants

Defines

#define | SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED)

Define Documentation

#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 52 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 53 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 54 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED)

Fast Mode Plus I2C4 not supported

Definition at line 58 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 48 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 49 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 50 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 51 of file stm32g4xx_hal_smbus_ex.h.

#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 47 of file stm32g4xx_hal_smbus_ex.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Exported Macros

SMBUS Extended Exported Macros
SMBUSEx
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Private Constants

SMBUS Extended Private Constants
SMBUSEx
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Private Macros

Defines
SMBUS Extended Private Macros
SMBUSEx

Defines

#define IS_SMBUS_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_SMBUS_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
                                           ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)))

Definition at line 118 of file stm32g4xx_hal_smbus_ex.h.

Referenced by HAL_SMBUSEx_DisableFastModePlus(), and HAL_SMBUSEx_EnableFastModePlus().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Private Functions

SMBUS Extended Private Functions
SMBUSEx
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 217 of file stm32g4xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3695 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3729 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and UNUSED.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3563 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3614 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, __SPI_HandleTypeDef::TxXferCount, and UNUSED.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3751 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3648 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Rx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4360 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx/Tx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4404 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4254 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4177 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxRxCpltCallback.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4311 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxCpltCallback.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3410 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3387 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3351 of file stm32g4xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback(), and __SPI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3333 of file stm32g4xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback(), and __SPI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3369 of file stm32g4xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback(), and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3116 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_IT_ERR, SPI_MODE_MASTER, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, and UNUSED.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3498 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3059 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3233 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_IT_ERR, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxRxCpltCallback, __SPI_HandleTypeDef::TxXferCount, and UNUSED.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3432 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 4109 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi | SPI handle
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 4145 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3872 of file stm32g4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3850 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, and UNUSED.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3816 of file stm32g4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3789 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), and UNUSED.

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3930 of file stm32g4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3905 of file stm32g4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | Fifo to check
State | Fifo state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 4029 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SMBUS_HandleTypeDef::State, and UNUSED.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | SPI flag to check
State | flag state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3960 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 489 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::MspDeInitCallback, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 314 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_MspInit(), HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::MspInitCallback, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, SPI_BAUDRATEPRESCALER_2, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_MODE_MASTER, SPI_PHASE_1EDGE, SPI_POLARITY_LOW, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, SPI_InitTypeDef::TIMode, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 549 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_DeInit(), and HAL_SPI_UnRegisterCallback().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 533 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), and HAL_SPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SPI_RegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID,
 |  | pSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User SPI Callback To be used instead of the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 569 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_UnRegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 680 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_ErrorCallback(), HAL_SPI_MspDeInit(), HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MspInit(), HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 2365 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2525 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2987 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2686 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2706 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2726 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SPI_ERROR_DMA, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2969 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2766 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_CHECK_FLAG, SPI_CHECK_IT_SOURCE, SPI_DMAAbortOnError(), SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1011 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, and UNUSED.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Note:
In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 2031 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1688 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2889 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2937 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 821 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_MODE_SLAVE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1907 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_IT_ERR, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1602 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1256 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, and UNUSED.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 2175 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Return values:
HAL status

Definition at line 1797 of file stm32g4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2873 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2921 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2905 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2953 of file stm32g4xx_hal_spi.c.

References UNUSED.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 3034 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 3022 of file stm32g4xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi)

HAL SPI Callback pointer definition.

pointer to an SPI callback function

Definition at line 186 of file stm32g4xx_hal_spi.h.

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_CallbackIDTypeDef

HAL SPI Callback ID enumeration definition.

Enumerator:
HAL_SPI_TX_COMPLETE_CB_ID

SPI Tx Completed callback ID

HAL_SPI_RX_COMPLETE_CB_ID

SPI Rx Completed callback ID

HAL_SPI_TX_RX_COMPLETE_CB_ID

SPI TxRx Completed callback ID

HAL_SPI_TX_HALF_COMPLETE_CB_ID

SPI Tx Half Completed callback ID

HAL_SPI_RX_HALF_COMPLETE_CB_ID

SPI Rx Half Completed callback ID

HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID

SPI TxRx Half Completed callback ID

HAL_SPI_ERROR_CB_ID

SPI Error callback ID

HAL_SPI_ABORT_CB_ID

SPI Abort callback ID

HAL_SPI_MSPINIT_CB_ID

SPI Msp Init callback ID

HAL_SPI_MSPDEINIT_CB_ID

SPI Msp DeInit callback ID

Definition at line 168 of file stm32g4xx_hal_spi.h.

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 100 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32g4xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 46 of file stm32g4xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 67 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 60 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 57 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 79 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 85 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535

Definition at line 82 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 54 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 51 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 73 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 48 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 63 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 89 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 76 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_spi.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32g4xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | ErrorCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | AbortCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspInitCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspDeInitCallback )(struct __SPI_HandleTypeDef *hspi)

Detailed Description

SPI handle Structure definition.

Definition at line 115 of file stm32g4xx_hal_spi.h.

Field Documentation

void(* __SPI_HandleTypeDef::AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Abort callback

Definition at line 157 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 133 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

void(* __SPI_HandleTypeDef::ErrorCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Error callback

Definition at line 156 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 147 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 141 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 139 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 119 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 117 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFifoStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 143 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

void(* __SPI_HandleTypeDef::MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp DeInit callback

Definition at line 159 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

void(* __SPI_HandleTypeDef::MspInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp Init callback

Definition at line 158 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 127 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 121 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Completed callback

Definition at line 151 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void(* __SPI_HandleTypeDef::RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Half Completed callback

Definition at line 154 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 135 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 131 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 129 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 145 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Completed callback

Definition at line 150 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void(* __SPI_HandleTypeDef::TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Half Completed callback

Definition at line 153 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 137 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

void(* __SPI_HandleTypeDef::TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Completed callback

Definition at line 152 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void(* __SPI_HandleTypeDef::TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Half Completed callback

Definition at line 155 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 125 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 123 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_spi.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040U)

Error during SPI Abort procedure

Definition at line 208 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_CRC (0x00000002U)

CRC error

Definition at line 203 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 206 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), and SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020U)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 207 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (0x00000008U)

FRE error

Definition at line 205 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Invalid Callback error

Definition at line 210 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

#define HAL_SPI_ERROR_MODF (0x00000001U)

MODF error

Definition at line 202 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (0x00000000U)

No error

Definition at line 201 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR (0x00000004U)

OVR error

Definition at line 204 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 220 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE (0x00000000U)

Definition at line 219 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 230 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES (0x00000000U)

Definition at line 228 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 229 of file stm32g4xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000900U)

Definition at line 244 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x00000A00U)

Definition at line 245 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x00000B00U)

Definition at line 246 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x00000C00U)

Definition at line 247 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x00000D00U)

Definition at line 248 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x00000E00U)

Definition at line 249 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x00000F00U)

Definition at line 250 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT (0x00000300U)

Definition at line 238 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000400U)

Definition at line 239 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000500U)

Definition at line 240 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000600U)

Definition at line 241 of file stm32g4xx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000700U)

Definition at line 242 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT (0x00000800U)

Definition at line 243 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 259 of file stm32g4xx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000U)

Definition at line 258 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000U)

Definition at line 267 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 268 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000U)

Definition at line 277 of file stm32g4xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Definition at line 278 of file stm32g4xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 276 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000U)

Definition at line 287 of file stm32g4xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 286 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

Definition at line 301 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 298 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)

Definition at line 295 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 302 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)

Definition at line 299 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)

Definition at line 296 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

Definition at line 300 of file stm32g4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)

Definition at line 297 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 311 of file stm32g4xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000U)

Definition at line 310 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000U)

Definition at line 319 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 320 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000U)

Definition at line 328 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 329 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT (0x00000002U)

Definition at line 343 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT (0x00000001U)

Definition at line 342 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)

Definition at line 341 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/2(16 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 356 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Definition at line 358 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 357 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 368 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 367 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 366 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 378 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 379 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 382 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 384 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 383 of file stm32g4xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FLAG_MASK
Value:
(SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)

Definition at line 385 of file stm32g4xx_hal_spi.h.

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 380 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 381 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 376 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 377 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)

Define Documentation

#define SPI_FTLVL_EMPTY (0x00000000U)

Definition at line 394 of file stm32g4xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL (0x00001800U)

Definition at line 397 of file stm32g4xx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL (0x00001000U)

Definition at line 396 of file stm32g4xx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL (0x00000800U)

Definition at line 395 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)

Define Documentation

#define SPI_FRLVL_EMPTY (0x00000000U)

Definition at line 406 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL (0x00000600U)

Definition at line 409 of file stm32g4xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL (0x00000400U)

Definition at line 408 of file stm32g4xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL (0x00000200U)

Definition at line 407 of file stm32g4xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 498 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_fre = 0x00U;              \
    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_fre);                            \
  }while(0U)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 531 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                                    \
    __IO uint32_t tmpreg_modf = 0x00U;                   \
    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
    UNUSED(tmpreg_modf);                                 \
  } while(0U)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 505 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_ovr = 0x00U;              \
    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_ovr);                            \
  } while(0U)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 518 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 550 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI handle. This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 460 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 543 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 448 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 491 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR2\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 472 of file stm32g4xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset SPI handle state.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 429 of file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__)
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))

Checks if SPI Baudrate prescaler parameter is in allowed range.

Parameters:
__PRESCALER__ specifies the SPI Baudrate prescaler. This parameter can be a value of SPI BaudRate Prescaler
Return values:
None

Definition at line 700 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( __CPHA__ )
Value:
(((__CPHA__) == SPI_PHASE_1EDGE) || \
                                    ((__CPHA__) == SPI_PHASE_2EDGE))

Checks if SPI Clock Phase parameter is in allowed range.

Parameters:
__CPHA__ specifies the SPI Clock Phase. This parameter can be a value of SPI Clock Phase
Return values:
None

Definition at line 675 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == SPI_POLARITY_LOW) || \
                                    ((__CPOL__) == SPI_POLARITY_HIGH))

Checks if SPI Serial clock steady state parameter is in allowed range.

Parameters:
__CPOL__ specifies the SPI serial clock steady state. This parameter can be a value of SPI Clock Polarity
Return values:
None

Definition at line 667 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( __CALCULATION__ )
Value:
(((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))

Checks if SPI CRC calculation enabled state is in allowed range.

Parameters:
__CALCULATION__ specifies the SPI CRC calculation enable state. This parameter can be a value of SPI CRC Calculation
Return values:
None

Definition at line 730 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)     || \
                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))

Checks if SPI CRC length is in allowed range.

Parameters:
__LENGTH__ specifies the SPI CRC length. This parameter can be a value of SPI CRC Length
Return values:
None

Definition at line 738 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( __POLYNOMIAL__ )
Value:
(((__POLYNOMIAL__) >= 0x1U)    && \
                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \
                                              (((__POLYNOMIAL__)&0x1U) != 0U))

Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.

Parameters:
__POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535
Return values:
None

Definition at line 747 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( __DATASIZE__ )
Value:
(((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))

Checks if SPI Data Size parameter is in allowed range.

Parameters:
__DATASIZE__ specifies the SPI Data Size. This parameter can be a value of SPI Data Size
Return values:
None

Definition at line 648 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES)        || \
                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Direction Mode. This parameter can be a value of SPI Direction Mode
Return values:
None

Definition at line 626 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( __MODE__ ) ((__MODE__) == SPI_DIRECTION_2LINES)

Checks if SPI Direction Mode parameter is 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 634 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES) || \
                                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is 1 or 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 640 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_DMA_HANDLE ( __HANDLE__ ) ((__HANDLE__) != NULL)

Checks if DMA handle is valid.

Parameters:
__HANDLE__ specifies a DMA Handle.
Return values:
None

Definition at line 755 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define IS_SPI_FIRST_BIT ( __BIT__ )
Value:
(((__BIT__) == SPI_FIRSTBIT_MSB) || \
                                    ((__BIT__) == SPI_FIRSTBIT_LSB))

Checks if SPI MSB LSB transmission parameter is in allowed range.

Parameters:
__BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). This parameter can be a value of SPI MSB LSB Transmission
Return values:
None

Definition at line 714 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( __MODE__ )
Value:
(((__MODE__) == SPI_MODE_SLAVE)   || \
                                    ((__MODE__) == SPI_MODE_MASTER))

Checks if SPI Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Mode. This parameter can be a value of SPI Mode
Return values:
None

Definition at line 618 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( __NSS__ )
Value:
(((__NSS__) == SPI_NSS_SOFT)       || \
                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \
                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))

Checks if SPI Slave Select parameter is in allowed range.

Parameters:
__NSS__ specifies the SPI Slave Select management parameter. This parameter can be a value of SPI Slave Select Management
Return values:
None

Definition at line 683 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( __NSSP__ )
Value:
(((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
                                    ((__NSSP__) == SPI_NSS_PULSE_DISABLE))

Checks if SPI NSS Pulse parameter is in allowed range.

Parameters:
__NSSP__ specifies the SPI NSS Pulse Mode parameter. This parameter can be a value of SPI NSS Pulse Mode
Return values:
None

Definition at line 692 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( __MODE__ )
Value:
(((__MODE__) == SPI_TIMODE_DISABLE) || \
                                    ((__MODE__) == SPI_TIMODE_ENABLE))

Checks if SPI TI mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI TI mode. This parameter can be a value of SPI TI Mode
Return values:
None

Definition at line 722 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI receive-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 573 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 566 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) |
Value:
((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of SPI SR register.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
SET or RESET.

Definition at line 598 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_CHECK_IT_SOURCE | ( | __CR2__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__CR2__) & (__INTERRUPT__)) == \
                                                     (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__CR2__ copy of SPI CR2 register.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
SET or RESET.

Definition at line 610 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 580 of file stm32g4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPIEx Private Constants

Defines
SPIEx Private Constants
SPIEx

Defines

#define SPI_FIFO_SIZE 4UL

Define Documentation

#define SPI_FIFO_SIZE 4UL

Definition at line 41 of file stm32g4xx_hal_spi_ex.c.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (const SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) Rx data flush function:
        (++) HAL_SPIEx_FlushRxFifo()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( const SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 79 of file stm32g4xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FIFO_SIZE, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, and UNUSED.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Time Base functions

Functions
TIM Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 341 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_Base_MspDeInit(), HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 281 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, __TIM_HandleTypeDef::Base_MspInitCallback, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_Base_MspInit(), HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 399 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_Base_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 384 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_Base_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 415 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | TIM Base handle
pData | The source Buffer address.
Length | The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 541 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 474 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 454 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 610 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 516 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, and TIM_IT_UPDATE.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Compare functions

Functions
TIM Output Compare functions
TIM Exported Functions

TIM Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

TIM Output Compare functions.

  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 725 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 665 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OC_MspInitCallback, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 783 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_OC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 768 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_OC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 806 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1067 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 897 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 862 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1231 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 990 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM PWM functions

Functions
TIM PWM functions
TIM Exported Functions

TIM PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

TIM PWM functions.

  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the TIM PWM.
    (+) Stop the TIM PWM.
    (+) Start the TIM PWM and enable interrupt.
    (+) Stop the TIM PWM and disable interrupt.
    (+) Start the TIM PWM and enable DMA transfer.
    (+) Stop the TIM PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1394 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1334 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1452 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_PWM_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1437 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_PWM_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1475 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | TIM PWM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1736 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1566 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1531 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1899 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1659 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Input Capture functions

Functions
TIM Input Capture functions
TIM Exported Functions

TIM Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

TIM Input Capture functions.

  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture.
   (+) Stop the TIM Input Capture.
   (+) Start the TIM Input Capture and enable interrupt.
   (+) Stop the TIM Input Capture and disable interrupt.
   (+) Start the TIM Input Capture and enable DMA transfer.
   (+) Stop the TIM Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 2062 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 2002 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2120 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim TIM Input Capture handle
Return values:
None

Definition at line 2105 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2141 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2387 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2223 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2193 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2546 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2315 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CCX_CHANNEL, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM One Pulse functions

Functions
TIM One Pulse functions
TIM Exported Functions

TIM One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

TIM One Pulse functions.

  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the TIM One Pulse.
    (+) Stop the TIM One Pulse.
    (+) Start the TIM One Pulse and enable interrupt.
    (+) Stop the TIM One Pulse and disable interrupt.
    (+) Start the TIM One Pulse and enable DMA transfer.
    (+) Stop the TIM One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim TIM One Pulse handle
Return values:
HAL status

Definition at line 2720 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
When the timer instance is initialized in One Pulse mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim TIM One Pulse handle
OnePulseMode Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 2651 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OnePulse_MspInitCallback, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_ResetCallback().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2780 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_OnePulse_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2765 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_OnePulse_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2800 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, and UNUSED.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2900 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, and UNUSED.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2857 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and UNUSED.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2963 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, and UNUSED.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Encoder functions

Functions
TIM Encoder functions
TIM Exported Functions

TIM Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

TIM Encoder functions.

  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the TIM Encoder.
    (+) Stop the TIM Encoder.
    (+) Start the TIM Encoder and enable interrupt.
    (+) Stop the TIM Encoder and disable interrupt.
    (+) Start the TIM Encoder and enable DMA transfer.
    (+) Stop the TIM Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL status

Definition at line 3157 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
Encoder mode and External clock mode 2 are not compatible and must not be selected together Ex: A call for HAL_TIM_Encoder_Init will erase the settings of HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
When the timer instance is initialized in Encoder mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 3042 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, __TIM_HandleTypeDef::Encoder_MspInitCallback, TIM_Encoder_InitTypeDef::EncoderMode, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_ENCODERINPUT_POLARITY, IS_TIM_IC_FILTER, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_ResetCallback().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 3217 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_Encoder_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 3202 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3237 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1 | The destination Buffer address for IC1.
pData2 | The destination Buffer address for IC2.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 3556 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3391 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3331 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3769 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, and TIM_DMA_ID_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3491 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

TIM IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

TIM IRQ handler management.

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3846 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_CLEAR_FLAG, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::DirectionChangeCallback, __TIM_HandleTypeDef::EncoderIndexCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_DirectionChangeCallback(), HAL_TIMEx_EncoderIndexCallback(), HAL_TIMEx_IndexErrorCallback(), HAL_TIMEx_TransitionErrorCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IndexErrorCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_DIR, TIM_FLAG_IDX, TIM_FLAG_IERR, TIM_FLAG_SYSTEM_BREAK, TIM_FLAG_TERR, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_DIR, TIM_IT_IDX, TIM_IT_IERR, TIM_IT_TERR, TIM_IT_TRIGGER, TIM_IT_UPDATE, __TIM_HandleTypeDef::TransitionErrorCallback, and __TIM_HandleTypeDef::TriggerCallback.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Peripheral Control functions

Functions
TIM Peripheral Control functions
TIM Exported Functions

TIM Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

TIM Peripheral Control functions.

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | TIM handle
sClockSourceConfig | pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 5562 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, IS_TIM_CLOCKSOURCE_INSTANCE, __TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR10, TIM_CLOCKSOURCE_ITR11, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_ITR5, TIM_CLOCKSOURCE_ITR6, TIM_CLOCKSOURCE_ITR7, TIM_CLOCKSOURCE_ITR8, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | TIM handle
sClearInputConfig | pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
HAL status

Definition at line 5360 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTPRESCALER_DIV1, TIM_CLEARINPUTSOURCE_COMP1, TIM_CLEARINPUTSOURCE_COMP2, TIM_CLEARINPUTSOURCE_COMP3, TIM_CLEARINPUTSOURCE_COMP4, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, TIM_ETR_SetConfig(), and TIMx_AF2_OCRSEL.

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim TIM handle.
TI1_Selection Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 5730 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_DTR2
  • TIM_DMABASE_ECR
  • TIM_DMABASE_TISEL
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_OR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 5053 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_BUSY, HAL_DMA_BURST_STATE_READY, HAL_DMA_Start_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_ReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | const uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_DTR2
  • TIM_DMABASE_ECR
  • TIM_DMABASE_TISEL
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_OR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 4699 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_BUSY, HAL_DMA_BURST_STATE_READY, HAL_DMA_Start_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_WriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_DTR2
  • TIM_DMABASE_ECR
  • TIM_DMABASE_TISEL
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_OR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4993 of file stm32g4xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 5237 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_Abort_IT(), HAL_DMA_BURST_STATE_READY, __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | const uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_DTR2
  • TIM_DMABASE_ECR
  • TIM_DMABASE_TISEL
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_OR
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4637 of file stm32g4xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiWriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 4883 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_Abort_IT(), HAL_DMA_BURST_STATE_READY, __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim TIM handle
EventSource specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Note:
Basic timers can only generate an update event.
TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant only for timer instances supporting break input(s).
Return values:
HAL status

Definition at line 5321 of file stm32g4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | TIM IC handle
sConfig | TIM Input Capture configuration structure
Channel TIM Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 4231 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM Output Compare handle
sConfig | TIM Output Compare configuration structure
Channel TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 4132 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_CHANNEL_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | TIM One Pulse handle
sConfig | TIM One Pulse configuration structure
OutputChannel TIM output channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel TIM input Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Note:
To output a waveform with a minimum delay user can enable the fast mode by calling the __HAL_TIM_ENABLE_OCxFAST macro. Then CCx output is forced in response to the edge detection on TIx input, without taking in account the comparison.
Return values:
HAL status

Definition at line 4480 of file stm32g4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM PWM handle
sConfig | TIM PWM configuration structure
Channel TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 4332 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim TIM handle.
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 5845 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
Return values:
HAL status

Definition at line 5762 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_INSTANCE, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
Return values:
HAL status

Definition at line 5802 of file stm32g4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_INSTANCE, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback
   (+) TIM Index callback
   (+) TIM Direction change callback
   (+) TIM Index error callback
   (+) TIM Transition error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 6068 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5978 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureHalfCpltCallback ( TIM_HandleTypeDef * htim )

Input Capture half complete callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5993 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non-blocking mode.

Parameters:
htim TIM OC handle
Return values:
None

Definition at line 5963 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5933 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedHalfCpltCallback ( TIM_HandleTypeDef * htim )

Period elapsed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5948 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 6008 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedHalfCpltCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 6023 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_RegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID,
 |  | pTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User TIM callback to be used instead of the weak predefined callback.

Parameters:
htim | tim handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
  • HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
  • HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
  • HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
  • HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 6119 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::DirectionChangeCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::EncoderIndexCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_DIRECTION_CHANGE_CB_ID, HAL_TIM_ENCODER_INDEX_CB_ID, HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_INDEX_ERROR_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRANSITION_ERROR_CB_ID, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::IndexErrorCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TransitionErrorCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 6038 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void HAL_TIM_TriggerHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 6053 of file stm32g4xx_hal_tim.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_UnRegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Parameters:
htim tim handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
  • HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
  • HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
  • HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
  • HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
Return values:
status

Definition at line 6382 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::DirectionChangeCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::EncoderIndexCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_Base_MspInit(), HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_DIRECTION_CHANGE_CB_ID, HAL_TIM_ENCODER_INDEX_CB_ID, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_Encoder_MspInit(), HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_ErrorCallback(), HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_IC_MspDeInit(), HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MspInit(), HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_INDEX_ERROR_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_OC_MspDeInit(), HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MspInit(), HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_OnePulse_MspInit(), HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_MspDeInit(), HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MspInit(), HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRANSITION_ERROR_CB_ID, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_DirectionChangeCallback(), HAL_TIMEx_EncoderIndexCallback(), HAL_TIMEx_HallSensor_MspDeInit(), HAL_TIMEx_HallSensor_MspInit(), HAL_TIMEx_IndexErrorCallback(), HAL_TIMEx_TransitionErrorCallback(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::IndexErrorCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TransitionErrorCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Peripheral State functions

Functions
TIM Peripheral State functions
TIM Exported Functions

TIM Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.

Detailed Description

TIM Peripheral State functions.

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim TIM Base handle
Return values:
HAL state

Definition at line 6670 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState ( const TIM_HandleTypeDef * htim )

Return actual state of a DMA burst operation.

Parameters:
htim TIM handle
Return values:
DMA burst state

Definition at line 6765 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::DMABurstState, and __TIM_HandleTypeDef::Instance.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL state

Definition at line 6720 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel ( const TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM handle
Return values:
Active channel

Definition at line 6730 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel.

HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Return actual state of the TIM channel.

Parameters:
htim TIM handle
Channel TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
TIM Channel state

Definition at line 6748 of file stm32g4xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and TIM_CHANNEL_STATE_GET.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim TIM IC handle
Return values:
HAL state

Definition at line 6700 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM OC handle state.

Parameters:
htim TIM Output Compare handle
Return values:
HAL state

Definition at line 6680 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim TIM OPM handle
Return values:
HAL state

Definition at line 6710 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim TIM handle
Return values:
HAL state

Definition at line 6690 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | TIM peripheral
Structure | TIM Base configuration structure
Return values:
None

Definition at line 7108 of file stm32g4xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, TIM_Base_InitTypeDef::RepetitionCounter, and TIM_FLAG_UPDATE.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
ChannelState | specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
Return values:
None

Definition at line 8063 of file stm32g4xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), and HAL_TIMEx_OnePulseN_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6931 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_IC_CaptureCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureCallback, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMACaptureHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6994 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureHalfCpltCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

static void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Delay Pulse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6833 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_PulseFinishedCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), and HAL_TIM_PWM_Start_DMA().

void TIM_DMADelayPulseHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6892 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6790 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7033 of file stm32g4xx_hal_tim.c.

References DMA_NORMAL, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::State, and TIM_DMA_ID_UPDATE.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMAPeriodElapsedHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7054 of file stm32g4xx_hal_tim.c.

References HAL_TIM_PeriodElapsedHalfCpltCallback(), and __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7070 of file stm32g4xx_hal_tim.c.

References DMA_NORMAL, HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::State, TIM_DMA_ID_TRIGGER, and __TIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 7091 of file stm32g4xx_hal_tim.c.

References HAL_TIM_TriggerHalfCpltCallback(), and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 8031 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIMEx_ConfigEncoderIndex(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_ITR4: Internal Trigger 4 (*)
  • TIM_TS_ITR5: Internal Trigger 5
  • TIM_TS_ITR6: Internal Trigger 6
  • TIM_TS_ITR7: Internal Trigger 7
  • TIM_TS_ITR8: Internal Trigger 8
  • TIM_TS_ITR9: Internal Trigger 9 (*)
  • TIM_TS_ITR10: Internal Trigger 10
  • TIM_TS_ITR11: Internal Trigger 11
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
(*) Value not defined in all devices.
Return values:
None

Definition at line 8001 of file stm32g4xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7163 of file stm32g4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Timer Output Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7239 of file stm32g4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7315 of file stm32g4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7390 of file stm32g4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_4.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 5 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7468 of file stm32g4xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 6 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7522 of file stm32g4xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_ResetCallback ( TIM_HandleTypeDef * htim )

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
htim pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 8087 of file stm32g4xx_hal_tim.c.

References __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::DirectionChangeCallback, __TIM_HandleTypeDef::EncoderIndexCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_DirectionChangeCallback(), HAL_TIMEx_EncoderIndexCallback(), HAL_TIMEx_IndexErrorCallback(), HAL_TIMEx_TransitionErrorCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IndexErrorCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::TransitionErrorCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Slave Timer configuration function.

Parameters:
htim | TIM handle
sSlaveConfig | Slave timer configuration
Return values:
None

Definition at line 7577 of file stm32g4xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_SLAVEMODE_COMBINED_GATEDRESET, TIM_SLAVEMODE_GATED, TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR10, TIM_TS_ITR11, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_ITR5, TIM_TS_ITR6, TIM_TS_ITR7, TIM_TS_ITR8, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 7773 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 7726 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 7856 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 7816 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 7899 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 7947 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Types

Data Structures | Typedefs | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum | HAL_TIM_ChannelStateTypeDef { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
TIM Channel States definition. More...
enum | HAL_TIM_DMABurstStateTypeDef { HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
DMA Burst States definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU,
HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU, HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU, HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU, HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU
}
HAL TIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim)

HAL TIM Callback pointer definition.

pointer to the TIM callback function

Definition at line 456 of file stm32g4xx_hal_tim.h.

typedef struct __TIM_HandleTypeDef TIM_HandleTypeDef

TIM Time Base Handle Structure definition.

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 346 of file stm32g4xx_hal_tim.h.

enum HAL_TIM_CallbackIDTypeDef

HAL TIM Callback ID enumeration definition.

Enumerator:
HAL_TIM_BASE_MSPINIT_CB_ID

TIM Base MspInit Callback ID

HAL_TIM_BASE_MSPDEINIT_CB_ID

TIM Base MspDeInit Callback ID

HAL_TIM_IC_MSPINIT_CB_ID

TIM IC MspInit Callback ID

HAL_TIM_IC_MSPDEINIT_CB_ID

TIM IC MspDeInit Callback ID

HAL_TIM_OC_MSPINIT_CB_ID

TIM OC MspInit Callback ID

HAL_TIM_OC_MSPDEINIT_CB_ID

TIM OC MspDeInit Callback ID

HAL_TIM_PWM_MSPINIT_CB_ID

TIM PWM MspInit Callback ID

HAL_TIM_PWM_MSPDEINIT_CB_ID

TIM PWM MspDeInit Callback ID

HAL_TIM_ONE_PULSE_MSPINIT_CB_ID

TIM One Pulse MspInit Callback ID

HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID

TIM One Pulse MspDeInit Callback ID

HAL_TIM_ENCODER_MSPINIT_CB_ID

TIM Encoder MspInit Callback ID

HAL_TIM_ENCODER_MSPDEINIT_CB_ID

TIM Encoder MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_PERIOD_ELAPSED_CB_ID

TIM Period Elapsed Callback ID

HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID

TIM Period Elapsed half complete Callback ID

HAL_TIM_TRIGGER_CB_ID

TIM Trigger Callback ID

HAL_TIM_TRIGGER_HALF_CB_ID

TIM Trigger half complete Callback ID

HAL_TIM_IC_CAPTURE_CB_ID

TIM Input Capture Callback ID

HAL_TIM_IC_CAPTURE_HALF_CB_ID

TIM Input Capture half complete Callback ID

HAL_TIM_OC_DELAY_ELAPSED_CB_ID

TIM Output Compare Delay Elapsed Callback ID

HAL_TIM_PWM_PULSE_FINISHED_CB_ID

TIM PWM Pulse Finished Callback ID

HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID

TIM PWM Pulse Finished half complete Callback ID

HAL_TIM_ERROR_CB_ID

TIM Error Callback ID

HAL_TIM_COMMUTATION_CB_ID

TIM Commutation Callback ID

HAL_TIM_COMMUTATION_HALF_CB_ID

TIM Commutation half complete Callback ID

HAL_TIM_BREAK_CB_ID

TIM Break Callback ID

HAL_TIM_BREAK2_CB_ID

TIM Break2 Callback ID

HAL_TIM_ENCODER_INDEX_CB_ID

TIM Encoder Index Callback ID

HAL_TIM_DIRECTION_CHANGE_CB_ID

TIM Direction Change Callback ID

HAL_TIM_INDEX_ERROR_CB_ID

TIM Index Error Callback ID

HAL_TIM_TRANSITION_ERROR_CB_ID

TIM Transition Error Callback ID

Definition at line 417 of file stm32g4xx_hal_tim.h.

enum HAL_TIM_ChannelStateTypeDef

TIM Channel States definition.

Enumerator:
HAL_TIM_CHANNEL_STATE_RESET

TIM Channel initial state

HAL_TIM_CHANNEL_STATE_READY

TIM Channel ready for use

HAL_TIM_CHANNEL_STATE_BUSY

An internal process is ongoing on the TIM channel

Definition at line 326 of file stm32g4xx_hal_tim.h.

enum HAL_TIM_DMABurstStateTypeDef

DMA Burst States definition.

Enumerator:
HAL_DMA_BURST_STATE_RESET

DMA Burst initial state

HAL_DMA_BURST_STATE_READY

DMA Burst ready for use

HAL_DMA_BURST_STATE_BUSY

Ongoing DMA Burst

Definition at line 336 of file stm32g4xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 314 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 46 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 76 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 62 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 52 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value

Definition at line 55 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value

Definition at line 48 of file stm32g4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 65 of file stm32g4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 83 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 101 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 106 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 85 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 110 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 97 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 94 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value

Definition at line 88 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 118 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 150 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 144 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 147 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 136 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 120 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 140 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 132 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 129 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value

Definition at line 123 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 157 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 168 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 159 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 165 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 162 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 175 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 177 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 189 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 180 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 186 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 183 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 201 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 192 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 198 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 195 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 208 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 216 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 212 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 214 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 210 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 223 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 234 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 229 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off

Definition at line 231 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Clear Input Source

Definition at line 227 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 225 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 243 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 245 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 247 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Note:
When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode.

Definition at line 249 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 261 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 265 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 263 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 271 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 267 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 269 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | BreakAFMode
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | Break2AFMode
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 281 of file stm32g4xx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state, This parameter can be a value of TIM Automatic Output Enable

Definition at line 307 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2AFMode

Specifies the alternate function mode of the break2 input.This parameter can be a value of TIM Break2 Input Alternate Function Mode

Definition at line 305 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 303 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity, This parameter can be a value of TIM Break Input 2 Polarity

Definition at line 301 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State, This parameter can be a value of TIM Break input 2 Enable

Definition at line 299 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakAFMode

Specifies the alternate function mode of the break input.This parameter can be a value of TIM Break Input Alternate Function Mode

Definition at line 297 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 295 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity, This parameter can be a value of TIM Break Input Polarity

Definition at line 293 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State, This parameter can be a value of TIM Break Input Enable

Definition at line 291 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 289 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level, This parameter can be a value of TIM Lock level

Definition at line 287 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode, This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 285 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode, This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 283 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32g4xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State
__IO HAL_TIM_ChannelStateTypeDef | ChannelState [6]
__IO HAL_TIM_ChannelStateTypeDef | ChannelNState [4]
__IO HAL_TIM_DMABurstStateTypeDef | DMABurstState
void(* | Base_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Base_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_DelayElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | ErrorCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | BreakCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Break2Callback )(struct __TIM_HandleTypeDef *htim)
void(* | EncoderIndexCallback )(struct __TIM_HandleTypeDef *htim)
void(* | DirectionChangeCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IndexErrorCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TransitionErrorCallback )(struct __TIM_HandleTypeDef *htim)

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 361 of file stm32g4xx_hal_tim.h.

Field Documentation

void(* __TIM_HandleTypeDef::Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp DeInit Callback

Definition at line 379 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp Init Callback

Definition at line 378 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Break2Callback)(struct __TIM_HandleTypeDef *htim)

TIM Break2 Callback

Definition at line 405 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::BreakCallback)(struct __TIM_HandleTypeDef *htim)

TIM Break Callback

Definition at line 404 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

HAL_TIM_ActiveChannel __TIM_HandleTypeDef::Channel

Active channel

Definition at line 368 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_GetActiveChannel(), HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

__IO HAL_TIM_ChannelStateTypeDef __TIM_HandleTypeDef::ChannelNState[4]

TIM complementary channel operation state

Definition at line 374 of file stm32g4xx_hal_tim.h.

__IO HAL_TIM_ChannelStateTypeDef __TIM_HandleTypeDef::ChannelState[6]

TIM channel operation state

Definition at line 373 of file stm32g4xx_hal_tim.h.

void(* __TIM_HandleTypeDef::CommutationCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation Callback

Definition at line 402 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void(* __TIM_HandleTypeDef::CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation half complete Callback

Definition at line 403 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim)

TIM Direction Change Callback

Definition at line 407 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

__IO HAL_TIM_DMABurstStateTypeDef __TIM_HandleTypeDef::DMABurstState

DMA burst operation state

Definition at line 375 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_DeInit(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp DeInit Callback

Definition at line 389 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp Init Callback

Definition at line 388 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Index Callback

Definition at line 406 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::ErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Error Callback

Definition at line 401 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp DeInit Callback

Definition at line 391 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void(* __TIM_HandleTypeDef::HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp Init Callback

Definition at line 390 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

DMA_HandleTypeDef* __TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 369 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), and UART_DMARxOnlyAbortCallback().

void(* __TIM_HandleTypeDef::IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture Callback

Definition at line 396 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture half complete Callback

Definition at line 397 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp DeInit Callback

Definition at line 381 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp Init Callback

Definition at line 380 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::IndexErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Index Error Callback

Definition at line 408 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

TIM_Base_InitTypeDef __TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 367 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* __TIM_HandleTypeDef::Instance

Register base address

Definition at line 366 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_GetChannelState(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigAsymmetricalDeadTime(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_ConfigDeadTime(), HAL_TIMEx_ConfigEncoderIndex(), HAL_TIMEx_ConfigSlaveModePreload(), HAL_TIMEx_DisableAsymmetricalDeadTime(), HAL_TIMEx_DisableDeadTimePreload(), HAL_TIMEx_DisableEncoderFirstIndex(), HAL_TIMEx_DisableEncoderIndex(), HAL_TIMEx_DisableSlaveModePreload(), HAL_TIMEx_DisarmBreakInput(), HAL_TIMEx_DitheringDisable(), HAL_TIMEx_DitheringEnable(), HAL_TIMEx_EnableAsymmetricalDeadTime(), HAL_TIMEx_EnableDeadTimePreload(), HAL_TIMEx_EnableEncoderFirstIndex(), HAL_TIMEx_EnableEncoderIndex(), HAL_TIMEx_EnableSlaveModePreload(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OC_ConfigPulseOnCompare(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_ReArmBreakInput(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef __TIM_HandleTypeDef::Lock

Locking object

Definition at line 371 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Output Compare Delay Elapsed Callback

Definition at line 398 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp DeInit Callback

Definition at line 383 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp Init Callback

Definition at line 382 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp DeInit Callback

Definition at line 387 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp Init Callback

Definition at line 386 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed Callback

Definition at line 392 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed half complete Callback

Definition at line 393 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp DeInit Callback

Definition at line 385 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp Init Callback

Definition at line 384 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished Callback

Definition at line 399 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished half complete Callback

Definition at line 400 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

__IO HAL_TIM_StateTypeDef __TIM_HandleTypeDef::State

TIM operation state

Definition at line 372 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIM_UnRegisterCallback(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OC_ConfigPulseOnCompare(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Transition Error Callback

Definition at line 409 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::TriggerCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger Callback

Definition at line 394 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger half complete Callback

Definition at line 395 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_COMP1 0x00000000U
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0
#define | TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1
#define | TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)

Define Documentation

#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U

OCREF_CLR_INT is connected to COMP1 output

Definition at line 475 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0

OCREF_CLR_INT is connected to COMP2 output

Definition at line 476 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1

OCREF_CLR_INT is connected to COMP3 output

Definition at line 477 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)

OCREF_CLR_INT is connected to COMP4 output

Definition at line 478 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U

OCREF_CLR is connected to ETRF input

Definition at line 474 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU

OCREF_CLR is disabled

Definition at line 473 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_CCR5 0x00000012U
#define | TIM_DMABASE_CCR6 0x00000013U
#define | TIM_DMABASE_CCMR3 0x00000014U
#define | TIM_DMABASE_DTR2 0x00000015U
#define | TIM_DMABASE_ECR 0x00000016U
#define | TIM_DMABASE_TISEL 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_OR 0x0000001AU

Define Documentation

#define TIM_DMABASE_AF1 0x00000018U

Definition at line 519 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_AF2 0x00000019U

Definition at line 520 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_ARR 0x0000000BU

Definition at line 506 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_BDTR 0x00000011U

Definition at line 512 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCER 0x00000008U

Definition at line 503 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 0x00000006U

Definition at line 501 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 0x00000007U

Definition at line 502 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCMR3 0x00000014U

Definition at line 515 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR1 0x0000000DU

Definition at line 508 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR2 0x0000000EU

Definition at line 509 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR3 0x0000000FU

Definition at line 510 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR4 0x00000010U

Definition at line 511 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR5 0x00000012U

Definition at line 513 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CCR6 0x00000013U

Definition at line 514 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CNT 0x00000009U

Definition at line 504 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CR1 0x00000000U

Definition at line 495 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_CR2 0x00000001U

Definition at line 496 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_DIER 0x00000003U

Definition at line 498 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_DTR2 0x00000015U

Definition at line 516 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_ECR 0x00000016U

Definition at line 517 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_EGR 0x00000005U

Definition at line 500 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_OR 0x0000001AU

Definition at line 521 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_PSC 0x0000000AU

Definition at line 505 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_RCR 0x0000000CU

Definition at line 507 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_SMCR 0x00000002U

Definition at line 497 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_SR 0x00000004U

Definition at line 499 of file stm32g4xx_hal_tim.h.

#define TIM_DMABASE_TISEL 0x00000017U

Definition at line 518 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 536 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 537 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 530 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 531 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 532 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 533 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 534 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 535 of file stm32g4xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 529 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 547 of file stm32g4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P

Polarity for TIx source

Definition at line 546 of file stm32g4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U

Polarity for TIx source

Definition at line 545 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Define Documentation

#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP

Polarity for ETR source

Definition at line 555 of file stm32g4xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Polarity for ETR source

Definition at line 556 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define TIM_ETRPRESCALER_DIV1 0x00000000U

No prescaler is used

Definition at line 564 of file stm32g4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR input source is divided by 2

Definition at line 565 of file stm32g4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR input source is divided by 4

Definition at line 566 of file stm32g4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

ETR input source is divided by 8

Definition at line 567 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Center-aligned mode 1

Definition at line 577 of file stm32g4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Center-aligned mode 2

Definition at line 578 of file stm32g4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Center-aligned mode 3

Definition at line 579 of file stm32g4xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as down-counter

Definition at line 576 of file stm32g4xx_hal_tim.h.

#define TIM_COUNTERMODE_UP 0x00000000U

Counter used as up-counter

Definition at line 575 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Update Interrupt Flag Remap

Defines
TIM Update Interrupt Flag Remap
TIM Exported Constants

Defines

#define | TIM_UIFREMAP_DISABLE 0x00000000U
#define | TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP

Define Documentation

#define TIM_UIFREMAP_DISABLE 0x00000000U

Update interrupt flag remap disabled

Definition at line 587 of file stm32g4xx_hal_tim.h.

#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP

Update interrupt flag remap enabled

Definition at line 588 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 0x00000000U

Clock division: tDTS=tCK_INT

Definition at line 596 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

Clock division: tDTS=2*tCK_INT

Definition at line 597 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Clock division: tDTS=4*tCK_INT

Definition at line 598 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE 0x00000000U

Capture/Compare 1 output disabled

Definition at line 606 of file stm32g4xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Capture/Compare 1 output enabled

Definition at line 607 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U

TIMx_ARR register is not buffered

Definition at line 615 of file stm32g4xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

TIMx_ARR register is buffered

Definition at line 616 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Define Documentation

#define TIM_OCFAST_DISABLE 0x00000000U

Output Compare fast disable

Definition at line 625 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Output Compare fast enable

Definition at line 626 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U

OCxN is disabled

Definition at line 634 of file stm32g4xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

OCxN is enabled

Definition at line 635 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define TIM_OCPOLARITY_HIGH 0x00000000U

Capture/Compare output polarity

Definition at line 643 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Capture/Compare output polarity

Definition at line 644 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Define Documentation

#define TIM_OCNPOLARITY_HIGH 0x00000000U

Capture/Compare complementary output polarity

Definition at line 652 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Capture/Compare complementary output polarity

Definition at line 653 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCIDLESTATE_RESET 0x00000000U

Output Idle state: OCx=0 when MOE=0

Definition at line 662 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1

Output Idle state: OCx=1 when MOE=0

Definition at line 661 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCNIDLESTATE_RESET 0x00000000U

Complementary output Idle state: OCxN=0 when MOE=0

Definition at line 671 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N

Complementary output Idle state: OCxN=1 when MOE=0

Definition at line 670 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Capture triggered by both rising and falling edges on timer input

Definition at line 681 of file stm32g4xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Capture triggered by falling edge on timer input

Definition at line 680 of file stm32g4xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Capture triggered by rising edge on timer input

Definition at line 679 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Encoder Input Polarity

Defines
TIM Encoder Input Polarity
TIM Exported Constants

Defines

#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Define Documentation

#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Encoder input with falling edge polarity

Definition at line 690 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Encoder input with rising edge polarity

Definition at line 689 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

Define Documentation

#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 698 of file stm32g4xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 699 of file stm32g4xx_hal_tim.h.

#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 700 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Define Documentation

#define TIM_ICPSC_DIV1 0x00000000U

Capture performed each time an edge is detected on the capture input

Definition at line 708 of file stm32g4xx_hal_tim.h.

#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0

Capture performed once every 2 events

Definition at line 709 of file stm32g4xx_hal_tim.h.

#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1

Capture performed once every 4 events

Definition at line 710 of file stm32g4xx_hal_tim.h.

#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Capture performed once every 8 events

Definition at line 711 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U

Define Documentation

#define TIM_OPMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 720 of file stm32g4xx_hal_tim.h.

#define TIM_OPMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 719 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)
#define | TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P

Definition at line 732 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)

Encoder mode: Clock plus direction, x2 mode

Definition at line 731 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P

Definition at line 734 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)

Encoder mode: Directional Clock, x2 mode

Definition at line 733 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 728 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

Definition at line 730 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level.

Definition at line 729 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P

Definition at line 735 of file stm32g4xx_hal_tim.h.

#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P

Definition at line 736 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE
#define | TIM_IT_IDX TIM_DIER_IDXIE
#define | TIM_IT_DIR TIM_DIER_DIRIE
#define | TIM_IT_IERR TIM_DIER_IERRIE
#define | TIM_IT_TERR TIM_DIER_TERRIE

Define Documentation

#define TIM_IT_BREAK TIM_DIER_BIE

Break interrupt

Definition at line 751 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 TIM_DIER_CC1IE

Capture/Compare 1 interrupt

Definition at line 745 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 TIM_DIER_CC2IE

Capture/Compare 2 interrupt

Definition at line 746 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 TIM_DIER_CC3IE

Capture/Compare 3 interrupt

Definition at line 747 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 TIM_DIER_CC4IE

Capture/Compare 4 interrupt

Definition at line 748 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM TIM_DIER_COMIE

Commutation interrupt

Definition at line 749 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_IT_DIR TIM_DIER_DIRIE

Direction change interrupt

Definition at line 753 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_IT_IDX TIM_DIER_IDXIE

Index interrupt

Definition at line 752 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_IT_IERR TIM_DIER_IERRIE

Index error interrupt

Definition at line 754 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_IT_TERR TIM_DIER_TERRIE

Transition error interrupt

Definition at line 755 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_IT_TRIGGER TIM_DIER_TIE

Trigger interrupt

Definition at line 750 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_IT_UPDATE TIM_DIER_UIE

Update interrupt

Definition at line 744 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U

Define Documentation

#define TIM_COMMUTATION_SOFTWARE 0x00000000U

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit

Definition at line 764 of file stm32g4xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input

Definition at line 763 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE

Define Documentation

#define TIM_DMA_CC1 TIM_DIER_CC1DE

DMA request is triggered by the capture/compare macth 1 event

Definition at line 773 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 TIM_DIER_CC2DE

DMA request is triggered by the capture/compare macth 2 event event

Definition at line 774 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 TIM_DIER_CC3DE

DMA request is triggered by the capture/compare macth 3 event event

Definition at line 775 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 TIM_DIER_CC4DE

DMA request is triggered by the capture/compare macth 4 event event

Definition at line 776 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM TIM_DIER_COMDE

DMA request is triggered by the commutation event

Definition at line 777 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_DMA_TRIGGER TIM_DIER_TDE

DMA request is triggered by the trigger event

Definition at line 778 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_DMA_UPDATE TIM_DIER_UDE

DMA request is triggered by the update event

Definition at line 772 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CCx DMA request selection

Defines
CCx DMA request selection
TIM Exported Constants

Defines

#define | TIM_CCDMAREQUEST_CC 0x00000000U
#define | TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when capture or compare match event occurs

Definition at line 786 of file stm32g4xx_hal_tim.h.

#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 787 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF
#define | TIM_FLAG_IDX TIM_SR_IDXF
#define | TIM_FLAG_DIR TIM_SR_DIRF
#define | TIM_FLAG_IERR TIM_SR_IERRF
#define | TIM_FLAG_TERR TIM_SR_TERRF

Define Documentation

#define TIM_FLAG_BREAK TIM_SR_BIF

Break interrupt flag

Definition at line 804 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 TIM_SR_B2IF

Break 2 interrupt flag

Definition at line 805 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 TIM_SR_CC1IF

Capture/Compare 1 interrupt flag

Definition at line 796 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF TIM_SR_CC1OF

Capture 1 overcapture flag

Definition at line 807 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_CC2 TIM_SR_CC2IF

Capture/Compare 2 interrupt flag

Definition at line 797 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF TIM_SR_CC2OF

Capture 2 overcapture flag

Definition at line 808 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_CC3 TIM_SR_CC3IF

Capture/Compare 3 interrupt flag

Definition at line 798 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF TIM_SR_CC3OF

Capture 3 overcapture flag

Definition at line 809 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_CC4 TIM_SR_CC4IF

Capture/Compare 4 interrupt flag

Definition at line 799 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF TIM_SR_CC4OF

Capture 4 overcapture flag

Definition at line 810 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_CC5 TIM_SR_CC5IF

Capture/Compare 5 interrupt flag

Definition at line 800 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_CC6 TIM_SR_CC6IF

Capture/Compare 6 interrupt flag

Definition at line 801 of file stm32g4xx_hal_tim.h.

#define TIM_FLAG_COM TIM_SR_COMIF

Commutation interrupt flag

Definition at line 802 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_DIR TIM_SR_DIRF

Direction change flag

Definition at line 812 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_IDX TIM_SR_IDXF

Encoder index flag

Definition at line 811 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_IERR TIM_SR_IERRF

Index error flag

Definition at line 813 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF

System Break interrupt flag

Definition at line 806 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TERR TIM_SR_TERRF

Transition error flag

Definition at line 814 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TRIGGER TIM_SR_TIF

Trigger interrupt flag

Definition at line 803 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE TIM_SR_UIF

Update interrupt flag

Definition at line 795 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and TIM_Base_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU

Define Documentation

#define TIM_CHANNEL_1 0x00000000U

Capture/compare channel 1 identifier

Definition at line 822 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 0x00000004U

Capture/compare channel 2 identifier

Definition at line 823 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 0x00000008U

Capture/compare channel 3 identifier

Definition at line 824 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 0x0000000CU

Capture/compare channel 4 identifier

Definition at line 825 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC4_SetConfig().

#define TIM_CHANNEL_5 0x00000010U

Compare channel 5 identifier

Definition at line 826 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 0x00000014U

Compare channel 6 identifier

Definition at line 827 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL 0x0000003CU

Global Capture/compare channel identifier

Definition at line 828 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
#define | TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
#define | TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8
#define | TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10
#define | TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF

External clock source mode 1 (ETRF)

Definition at line 837 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1

External clock source mode 2

Definition at line 838 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0

Internal clock source

Definition at line 836 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0

External clock source mode 1 (ITR0)

Definition at line 842 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1

External clock source mode 1 (ITR1)

Definition at line 843 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10

External clock source mode 1 (ITR10)

Definition at line 856 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11

External clock source mode 1 (ITR11)

Definition at line 857 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2

External clock source mode 1 (ITR2)

Definition at line 844 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3

External clock source mode 1 (ITR3)

Definition at line 845 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5

External clock source mode 1 (ITR5)

Definition at line 849 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6

External clock source mode 1 (ITR6)

Definition at line 850 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7

External clock source mode 1 (ITR7)

Definition at line 851 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8

External clock source mode 1 (ITR8)

Definition at line 852 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1

External clock source mode 1 (TTI1FP1)

Definition at line 840 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED

External clock source mode 1 (TTI1FP1 + edge detect.)

Definition at line 839 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2

External clock source mode 1 (TTI2FP2)

Definition at line 841 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 869 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 868 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 865 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 866 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 867 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 877 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 878 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 879 of file stm32g4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 880 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 888 of file stm32g4xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 889 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 897 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 898 of file stm32g4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 899 of file stm32g4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 900 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSR_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 909 of file stm32g4xx_hal_tim.h.

#define TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 908 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSI_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 918 of file stm32g4xx_hal_tim.h.

#define TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 917 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 926 of file stm32g4xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 927 of file stm32g4xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 928 of file stm32g4xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF

Definition at line 925 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U

Define Documentation

#define TIM_BREAK_DISABLE 0x00000000U

Break input BRK is disabled

Definition at line 937 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK_ENABLE TIM_BDTR_BKE

Break input BRK is enabled

Definition at line 936 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 946 of file stm32g4xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 945 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break Input Alternate Function Mode

Defines
TIM Break Input Alternate Function Mode
TIM Exported Constants

Defines

#define | TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Define Documentation

#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Break input BRK in bidirectional mode

Definition at line 955 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK_AFMODE_INPUT 0x00000000U

Break input BRK in input mode

Definition at line 954 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break input 2 Enable

Defines
TIM Break input 2 Enable
TIM Exported Constants

Defines

#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define TIM_BREAK2_DISABLE 0x00000000U

Break input BRK2 is disabled

Definition at line 963 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break input BRK2 is enabled

Definition at line 964 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break Input 2 Polarity

Defines
TIM Break Input 2 Polarity
TIM Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 973 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK2POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 972 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break2 Input Alternate Function Mode

Defines
TIM Break2 Input Alternate Function Mode
TIM Exported Constants

Defines

#define | TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Define Documentation

#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Break2 input BRK2 in bidirectional mode

Definition at line 982 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK2_AFMODE_INPUT 0x00000000U

Break2 input BRK2 in input mode

Definition at line 981 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 990 of file stm32g4xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Definition at line 991 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Group Channel 5 and Channel 1, 2 or 3

Defines
TIM Group Channel 5 and Channel 1, 2 or 3
TIM Exported Constants

Defines

#define | TIM_GROUPCH5_NONE 0x00000000U
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 999 of file stm32g4xx_hal_tim.h.

#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 1000 of file stm32g4xx_hal_tim.h.

#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 1001 of file stm32g4xx_hal_tim.h.

#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 1002 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3

Define Documentation

#define TIM_TRGO_ENABLE TIM_CR2_MMS_0

TIMx_CR1.CEN bit is used as trigger output (TRGO)

Definition at line 1011 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3

Encoder clock is used as trigger output(TRGO)

Definition at line 1018 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Capture or a compare match 1 is used as trigger output (TRGO)

Definition at line 1013 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output (TRGO)

Definition at line 1014 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output(TRGO)

Definition at line 1015 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output(TRGO)

Definition at line 1016 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output(TRGO)

Definition at line 1017 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO)

Definition at line 1010 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output (TRGO)

Definition at line 1012 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

TIMx_CR1.CEN bit is used as trigger output (TRGO2)

Definition at line 1027 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Capture or a compare match 1 is used as trigger output (TRGO2)

Definition at line 1029 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2

OC1REF signal is used as trigger output (TRGO2)

Definition at line 1030 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output (TRGO2)

Definition at line 1031 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output (TRGO2)

Definition at line 1032 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output (TRGO2)

Definition at line 1033 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges generate pulses on TRGO2

Definition at line 1039 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 1038 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges generate pulses on TRGO2

Definition at line 1036 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3

OC5REF signal is used as trigger output (TRGO2)

Definition at line 1034 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 1041 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 1040 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output (TRGO2)

Definition at line 1035 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges generate pulses on TRGO2

Definition at line 1037 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO2)

Definition at line 1026 of file stm32g4xx_hal_tim.h.

#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output (TRGO2)

Definition at line 1028 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Master/slave mode is selected

Definition at line 1050 of file stm32g4xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM

No action

Definition at line 1049 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)

Combined gated + reset mode

Definition at line 1064 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode

Definition at line 1063 of file stm32g4xx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE 0x00000000U

Slave mode disabled

Definition at line 1058 of file stm32g4xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

External Clock Mode 1

Definition at line 1062 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode

Definition at line 1060 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode

Definition at line 1059 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode

Definition at line 1061 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M
#define | TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)
#define | TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)

Define Documentation

#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

Set channel to active level on match

Definition at line 1073 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 1084 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M

Asymmetric PWM mode 2

Definition at line 1085 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 1082 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 1083 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)

Direction output (CH3&CH4 only)

Definition at line 1087 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Force active level

Definition at line 1078 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

Force inactive level

Definition at line 1079 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

Set channel to inactive level on match

Definition at line 1074 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)

Pulse on compare (CH3&CH4 only)

Definition at line 1086 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

PWM mode 1

Definition at line 1076 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

PWM mode 2

Definition at line 1077 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 1080 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 1081 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_TIMING 0x00000000U

Frozen

Definition at line 1072 of file stm32g4xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Toggle

Definition at line 1075 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU

Define Documentation

#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered External Trigger input (ETRF)

Definition at line 1114 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0)

Definition at line 1095 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1)

Definition at line 1096 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 10 (ITR10)

Definition at line 1109 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 11 (ITR11)

Definition at line 1110 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2)

Definition at line 1097 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3)

Definition at line 1098 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)

Internal Trigger 5 (ITR5)

Definition at line 1102 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 6 (ITR6)

Definition at line 1103 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 7 (ITR7)

Definition at line 1104 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)

Internal Trigger 8 (ITR8)

Definition at line 1105 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE 0x0000FFFFU

No trigger selected

Definition at line 1115 of file stm32g4xx_hal_tim.h.

#define TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED)

Definition at line 1111 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Filtered Timer Input 1 (TI1FP1)

Definition at line 1112 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered Timer Input 2 (TI2FP2)

Definition at line 1113 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1127 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1126 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 1123 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 1124 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1125 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 1135 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 1136 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 1137 of file stm32g4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 1138 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

Define Documentation

#define TIM_TI1SELECTION_CH1 0x00000000U

The TIMx_CH1 pin is connected to TI1 input

Definition at line 1146 of file stm32g4xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Definition at line 1147 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U
#define | TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U
#define | TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U
#define | TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U
#define | TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U
#define | TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U
#define | TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U
#define | TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1164 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1165 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1166 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1167 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1168 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1169 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1170 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1171 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1172 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U

The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1173 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1155 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U

The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1174 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U

The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1175 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U

The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1176 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U

The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1177 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U

The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1178 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U

The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1179 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U

The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1180 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1156 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1157 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1158 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1159 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1160 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1161 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1162 of file stm32g4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1163 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 1189 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 1190 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 1191 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 1192 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)

Index of the DMA handle used for Commutation DMA requests

Definition at line 1193 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Index of the DMA handle used for Trigger DMA requests

Definition at line 1194 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and TIM_DMATriggerCplt().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)

Index of the DMA handle used for Update DMA requests

Definition at line 1188 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and TIM_DMAPeriodElapsedCplt().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U

Define Documentation

#define TIM_CCx_DISABLE 0x00000000U

Input or output channel is disabled

Definition at line 1203 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), and HAL_TIMEx_OnePulseN_Stop_IT().

#define TIM_CCx_ENABLE 0x00000001U

Input or output channel is enabled

Definition at line 1202 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OnePulseN_Start(), and HAL_TIMEx_OnePulseN_Start_IT().

#define TIM_CCxN_DISABLE 0x00000000U

Complementary output channel is enabled

Definition at line 1205 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE 0x00000004U

Complementary output channel is enabled

Definition at line 1204 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Break System

Defines
TIM Break System
TIM Exported Constants

Defines

#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20

Definition at line 1213 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20

Definition at line 1216 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1214 of file stm32g4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20

Definition at line 1215 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
#define | __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
Disable update interrupt flag (UIF) remapping.
#define | __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
Get update interrupt flag (UIF) copy status.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
Select the Capture/compare DMA request source.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  • TIM_FLAG_IDX: Index interrupt flag
  • TIM_FLAG_DIR: Direction change interrupt flag
  • TIM_FLAG_IERR: Index error interrupt flag
  • TIM_FLAG_TERR: Transition error interrupt flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1461 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
  • TIM_IT_IDX: Index interrupt
  • TIM_IT_DIR: Direction change interrupt
  • TIM_IT_IERR: Index error interrupt
  • TIM_IT_TERR: Transition error interrupt
Return values:
None

Definition at line 1503 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
      } \
    } \
  } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1300 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1405 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
  • TIM_IT_IDX: Index interrupt
  • TIM_IT_DIR: Direction change interrupt
  • TIM_IT_IERR: Index error interrupt
  • TIM_IT_TERR: Transition error interrupt
Return values:
None

Definition at line 1375 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchro(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))

Disable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is disabled CCx output behaves normally depending on counter and CCRx values even when the trigger is ON. The minimum delay to activate CCx output when an active edge occurs on the trigger input is 5 clock cycles.
Return values:
None

Definition at line 1784 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))

Reset the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1734 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1286 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1390 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
  • TIM_IT_IDX: Index interrupt
  • TIM_IT_DIR: Direction change interrupt
  • TIM_IT_IERR: Index error interrupt
  • TIM_IT_TERR: Transition error interrupt
Return values:
None

Definition at line 1355 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))

Enable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is enabled an active edge on the trigger input acts like a compare match on CCx output. Delay to sample the trigger input and to activate CCx output is reduced to 3 clock cycles.
Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
Return values:
None

Definition at line 1759 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))

Set the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1713 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1583 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1610 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
   ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1692 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1564 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  • TIM_FLAG_IDX: Index interrupt flag
  • TIM_FLAG_DIR: Direction change interrupt flag
  • TIM_FLAG_IERR: Index error interrupt flag
  • TIM_FLAG_TERR: Transition error interrupt flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1433 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1651 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
                                                             == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
  • TIM_IT_IDX: Index interrupt
  • TIM_IT_DIR: Direction change interrupt
  • TIM_IT_IERR: Index error interrupt
  • TIM_IT_TERR: Transition error interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1482 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_GET_UIFCPY ( __COUNTER__ ) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))

Get update interrupt flag (UIF) copy status.

Parameters:
__COUNTER__ Counter value.
Return values:
The state of UIFCPY (TRUE or FALSE). mode.

Definition at line 1529 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__ TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1538 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
      } \
    } \
  } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1318 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled unconditionally

Definition at line 1335 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1293 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                               \
                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
                                                     } while(0)

Reset TIM handle state.

Parameters:
__HANDLE__ TIM handle.
Return values:
None

Definition at line 1236 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SELECT_CCDMAREQUEST | ( | __HANDLE__,
 |  | __CCDMA__
 | ) | MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))

Select the Capture/compare DMA request source.

Parameters:
__HANDLE__ specifies the TIM Handle.
__CCDMA__ specifies Capture/compare DMA request source This parameter can be one of the following values:
  • TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
  • TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
Return values:
None

Definition at line 1844 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
  } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ | TIM handle.
__AUTORELOAD__ | specifies the Counter register new value.
Return values:
None

Definition at line 1572 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__ Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1830 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                   \
    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
  } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ TIM handle.
__CKD__ specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1595 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__ | TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__ | specifies the Capture Compare register new value.
Return values:
None

Definition at line 1671 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.

Parameters:
__HANDLE__ | TIM handle.
__COUNTER__ | specifies the Counter register new value.
Return values:
None

Definition at line 1557 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__ specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1630 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__ | TIM handle.
__PRESC__ | specifies the Prescaler new value.
Return values:
None

Definition at line 1546 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_UIFREMAP_DISABLE ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))

Disable update interrupt flag (UIF) remapping.

Parameters:
__HANDLE__ TIM handle.
Return values:
None mode.

Definition at line 1521 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_UIFREMAP_ENABLE ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Parameters:
__HANDLE__ TIM handle.
Return values:
None mode.

Definition at line 1513 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1813 of file stm32g4xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1800 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1858 of file stm32g4xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))

Definition at line 1859 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL

Definition at line 209 of file stm32g4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_UIFREMAP_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_PERIOD(__HANDLE__, __PERIOD__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK_AFMODE(__AFMODE__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_AFMODE(__AFMODE__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 2131 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1931 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK2_AFMODE ( __AFMODE__ )
Value:
(((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
                                          ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))

Definition at line 2127 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 2124 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 2121 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_AFMODE ( __AFMODE__ )
Value:
(((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
                                         ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))

Definition at line 2117 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xFUL)

Definition at line 2109 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 2114 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 2111 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 2242 of file stm32g4xx_hal_tim.h.

#define IS_TIM_CCX_CHANNEL | ( | __INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
                                                       ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
                                                       ((__CHANNEL__) != (TIM_CHANNEL_6)))

Definition at line 1965 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), and HAL_TIM_PWM_Stop_IT().

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1984 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2096 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 2088 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 2091 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 1880 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1927 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2086 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 2075 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 2081 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))

Definition at line 2058 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_4))

Definition at line 1999 of file stm32g4xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1918 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFFU)

Definition at line 2240 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigAsymmetricalDeadTime(), HAL_TIMEx_ConfigBreakDeadTime(), and HAL_TIMEx_ConfigDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
                                   ((__BASE__) == TIM_DMABASE_TISEL) || \
                                   ((__BASE__) == TIM_DMABASE_DTR2)  || \
                                   ((__BASE__) == TIM_DMABASE_ECR)  || \
                                   ((__BASE__) == TIM_DMABASE_OR))

Definition at line 1888 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_DATA_LENGTH ( LENGTH ) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

Definition at line 2236 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))

Definition at line 2209 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1982 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1)                      || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2)                      || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12)                     || \
                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2)    || \
                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1)    || \
                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2)      || \
                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI1)                   || \
                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI2))

Definition at line 1972 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_ENCODERINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

Definition at line 1949 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1916 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1934 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

Definition at line 2134 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2238 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1952 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1960 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1956 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 2104 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 2164 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
                                   ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT)   || \
                                   ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))

Definition at line 2182 of file stm32g4xx_hal_tim.h.

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1937 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1943 of file stm32g4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1940 of file stm32g4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1946 of file stm32g4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1992 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1969 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 2101 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 2098 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PERIOD | ( | __HANDLE__,
 |  | __PERIOD__
 | ) |
Value:
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
                                               (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
                                               ((__PERIOD__) > 0U))

Definition at line 1995 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))

Definition at line 2175 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)               || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)                 || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)                 || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)               || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)             || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))

Definition at line 2167 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED ( __TRIGGER__ )
Value:
(((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 2247 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 2206 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 2146 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF) || \
                                        ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))

Definition at line 2136 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2204 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 2193 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 2199 of file stm32g4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_UIFREMAP_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_UIFREMAP_DISABLE) || \
                                            ((__MODE__) == TIM_UIFREMAP_ENABLE))

Definition at line 1924 of file stm32g4xx_hal_tim.h.

#define TIM_CHANNEL_N_STATE_GET | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
   (__HANDLE__)->ChannelNState[3])

Definition at line 2305 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define TIM_CHANNEL_N_STATE_SET | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))

Definition at line 2311 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), TIM_DMACaptureCplt(), TIM_DMADelayPulseNCplt(), and TIM_DMAErrorCCxN().

#define TIM_CHANNEL_N_STATE_SET_ALL | ( | __HANDLE__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
do { \
                                                                         (__HANDLE__)->ChannelNState[0] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[1] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[2] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[3] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                       } while(0)

Definition at line 2317 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_PWM_DeInit(), and HAL_TIM_PWM_Init().

#define TIM_CHANNEL_STATE_GET | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
   (__HANDLE__)->ChannelState[5])

Definition at line 2274 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_GetChannelState(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OnePulseN_Start(), and HAL_TIMEx_OnePulseN_Start_IT().

#define TIM_CHANNEL_STATE_SET | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
   ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))

Definition at line 2282 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), and TIM_DMAError().

#define TIM_CHANNEL_STATE_SET_ALL | ( | __HANDLE__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
do { \
                                                                       (__HANDLE__)->ChannelState[0]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[1]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[2]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[3]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[4]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[5]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                     } while(0)

Definition at line 2290 of file stm32g4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_PWM_DeInit(), and HAL_TIM_PWM_Init().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 2268 of file stm32g4xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

Definition at line 2256 of file stm32g4xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

Definition at line 2262 of file stm32g4xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Definition at line 2250 of file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Private Constants

Defines
TIM Extended Private Constants
TIMEx

Defines

#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Define Documentation

#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Definition at line 109 of file stm32g4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ReArmBreakInput().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 259 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Note:
When the timer instance is initialized in Hall Sensor Interface mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim | TIM Hall Sensor Interface handle
sConfig | TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 157 of file stm32g4xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspInitCallback, TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_Base_InitTypeDef::Period, TIM_OC_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_ResetCallback(), TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 319 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 304 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 334 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | TIM Hall Sensor Interface handle
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 506 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 416 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 388 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 582 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, and TIM_DMA_ID_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 473 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_IT_CC1.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 645 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_N_STATE_GET, and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 908 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAErrorCCxN(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 730 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 697 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1068 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 825 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCER_CCxNE_MASK, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1167 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_N_STATE_GET, and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1428 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAErrorCCxN(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1251 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1218 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1588 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1345 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCER_CCxNE_MASK, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to enable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1687 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to enable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1775 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1736 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1830 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (const TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_DitheringEnable (TIM_HandleTypeDef *htim)
Enable dithering.
HAL_StatusTypeDef | HAL_TIMEx_DitheringDisable (TIM_HandleTypeDef *htim)
Disable dithering.
HAL_StatusTypeDef | HAL_TIMEx_OC_ConfigPulseOnCompare (TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth)
Initializes the pulse on compare pulse width and pulse prescaler.
HAL_StatusTypeDef | HAL_TIMEx_ConfigSlaveModePreload (TIM_HandleTypeDef *htim, uint32_t Source)
Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableSlaveModePreload (TIM_HandleTypeDef *htim)
Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_DisableSlaveModePreload (TIM_HandleTypeDef *htim)
Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableDeadTimePreload (TIM_HandleTypeDef *htim)
Enable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_DisableDeadTimePreload (TIM_HandleTypeDef *htim)
Disable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_ConfigDeadTime (TIM_HandleTypeDef *htim, uint32_t Deadtime)
Configure deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigAsymmetricalDeadTime (TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
Configure asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_EnableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Enable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_DisableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Disable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigEncoderIndex (TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
Configures the encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderIndex (TIM_HandleTypeDef *htim)
Enable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderIndex (TIM_HandleTypeDef *htim)
Disable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Enable encoder first index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Disable encoder first index.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Select timer input source.
      (+) Enable or disable channel grouping.
      (+) Configure Pulse on compare.
      (+) Configure Encoder index.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | FallingDeadtime
 | ) |  |

Configure asymmetrical deadtime.

Parameters:
htim | TIM handle
FallingDeadtime | Falling edge deadtime value
Note:
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
Return values:
HAL status

Definition at line 3165 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_DEADTIME.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | TIM handle
sBreakDeadTimeConfig | pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Note:
Interrupts can be generated when an active level is detected on the break input, the break 2 input or the system break input. Break interrupt can be enabled by calling the __HAL_TIM_ENABLE_IT macro.
Return values:
HAL status

Definition at line 2253 of file stm32g4xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::Break2AFMode, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakAFMode, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, __TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_AFMODE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_AFMODE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | const TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim | TIM handle.
BreakInput Break input to configure This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig | Break input source configuration
Return values:
HAL status

Definition at line 2321 of file stm32g4xx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, TIM_BREAKINPUTSOURCE_COMP2, TIM_BREAKINPUTSOURCE_COMP3, and TIM_BREAKINPUTSOURCE_COMP4.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR4: Internal trigger 4 selected (*)
  • TIM_TS_ITR5: Internal trigger 5 selected
  • TIM_TS_ITR6: Internal trigger 6 selected
  • TIM_TS_ITR7: Internal trigger 7 selected
  • TIM_TS_ITR8: Internal trigger 8 selected
  • TIM_TS_ITR9: Internal trigger 9 selected (*)
  • TIM_TS_ITR10: Internal trigger 10 selected
  • TIM_TS_ITR11: Internal trigger 11 selected
  • TIM_TS_NONE: No trigger is needed
(*) Value not defined in all devices.
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1924 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR10, TIM_TS_ITR11, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_ITR5, TIM_TS_ITR6, TIM_TS_ITR7, and TIM_TS_ITR8.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR4: Internal trigger 4 selected (*)
  • TIM_TS_ITR5: Internal trigger 5 selected
  • TIM_TS_ITR6: Internal trigger 6 selected
  • TIM_TS_ITR7: Internal trigger 7 selected
  • TIM_TS_ITR8: Internal trigger 8 selected
  • TIM_TS_ITR9: Internal trigger 9 selected (*)
  • TIM_TS_ITR10: Internal trigger 10 selected
  • TIM_TS_ITR11: Internal trigger 11 selected
  • TIM_TS_NONE: No trigger is needed
(*) Value not defined in all devices.
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 2107 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_IT, __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR10, TIM_TS_ITR11, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_ITR5, TIM_TS_ITR6, TIM_TS_ITR7, TIM_TS_ITR8, TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_ITR4: Internal trigger 4 selected (*)
  • TIM_TS_ITR5: Internal trigger 5 selected
  • TIM_TS_ITR6: Internal trigger 6 selected
  • TIM_TS_ITR7: Internal trigger 7 selected
  • TIM_TS_ITR8: Internal trigger 8 selected
  • TIM_TS_ITR9: Internal trigger 9 selected (*)
  • TIM_TS_ITR10: Internal trigger 10 selected
  • TIM_TS_ITR11: Internal trigger 11 selected
  • TIM_TS_NONE: No trigger is needed
(*) Value not defined in all devices.
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 2015 of file stm32g4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR10, TIM_TS_ITR11, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_ITR5, TIM_TS_ITR6, TIM_TS_ITR7, and TIM_TS_ITR8.

HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Deadtime
 | ) |  |

Configure deadtime.

Parameters:
htim | TIM handle
Deadtime | Deadtime value
Note:
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
Return values:
HAL status

Definition at line 3148 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_DEADTIME.

HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex | ( | TIM_HandleTypeDef * | htim,
 |  | TIMEx_EncoderIndexConfigTypeDef * | sEncoderIndexConfig
 | ) |  |

Configures the encoder index.

Note:
warning in case of encoder mode clock plus direction TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 Direction must be set to TIM_ENCODERINDEX_DIRECTION_UP_DOWN
Parameters:
htim | TIM handle.
sEncoderIndexConfig | Encoder index configuration
Return values:
HAL status

Definition at line 3212 of file stm32g4xx_hal_tim_ex.c.

References assert_param, TIMEx_EncoderIndexConfigTypeDef::Direction, TIMEx_EncoderIndexConfigTypeDef::Filter, TIMEx_EncoderIndexConfigTypeDef::FirstIndexEnable, __TIM_HandleTypeDef::Instance, IS_TIM_ENCODERINDEX_DIRECTION, IS_TIM_ENCODERINDEX_FILTER, IS_TIM_ENCODERINDEX_POLARITY, IS_TIM_ENCODERINDEX_POSITION, IS_TIM_ENCODERINDEX_PRESCALER, TIMEx_EncoderIndexConfigTypeDef::Polarity, TIMEx_EncoderIndexConfigTypeDef::Position, TIMEx_EncoderIndexConfigTypeDef::Prescaler, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Source
 | ) |  |

Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)

Parameters:
htim TIM handle
Source Source of slave mode selection preload This parameter can be one of the following values:
  • TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
  • TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
Return values:
HAL status

Definition at line 3075 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_SLAVE_PRELOAD_SOURCE.

HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime ( TIM_HandleTypeDef * htim )

Disable asymmetrical deadtime.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3194 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload ( TIM_HandleTypeDef * htim )

Disable deadtime preload.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3132 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex ( TIM_HandleTypeDef * htim )

Disable encoder first index.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3293 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex ( TIM_HandleTypeDef * htim )

Disable encoder index.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3265 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload ( TIM_HandleTypeDef * htim )

Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3104 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput
 | ) |  |

Disarm the designated break input (when it operates in bidirectional mode).

Parameters:
htim TIM handle.
BreakInput Break input to disarm This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
Note:
The break input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output .
Return values:
HAL status

Definition at line 2851 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, TIM_BREAKINPUT_BRK, and TIM_BREAKINPUT_BRK2.

HAL_StatusTypeDef HAL_TIMEx_DitheringDisable ( TIM_HandleTypeDef * htim )

Disable dithering.

Parameters:
htim TIM handle
Note:
This function must be called when timer is stopped or disabled (CEN =0)
If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
  • CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
  • ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
  • CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
  • ARR and CCRx values are limited to 0xFFEF in dithering mode (corresponds to 4094 for the integer part and 15 for the dithered part).
Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. So it may be necessary to read ARR value or CCRx value with macros __HAL_TIM_GET_AUTORELOAD() __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
Return values:
HAL status

Definition at line 3012 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_DitheringEnable ( TIM_HandleTypeDef * htim )

Enable dithering.

Parameters:
htim TIM handle
Note:
Main usage is PWM mode
This function must be called when timer is stopped or disabled (CEN =0)
If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
  • CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
  • ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
  • CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
  • ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers (corresponds to 4094 for the integer part and 15 for the dithered part).
Macros __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate period (ARR) and delay (CCRx) value.
Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. So it may be necessary to read ARR value or CCRx value with macros __HAL_TIM_GET_AUTORELOAD() __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
Return values:
HAL status

Definition at line 2988 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime ( TIM_HandleTypeDef * htim )

Enable asymmetrical deadtime.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3180 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload ( TIM_HandleTypeDef * htim )

Enable deadtime preload.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3118 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex ( TIM_HandleTypeDef * htim )

Enable encoder first index.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3279 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex ( TIM_HandleTypeDef * htim )

Enable encoder index.

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3251 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload ( TIM_HandleTypeDef * htim )

Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)

Parameters:
htim TIM handle
Return values:
HAL status

Definition at line 3090 of file stm32g4xx_hal_tim_ex.c.

References assert_param, and __TIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim | TIM handle.
Channels | specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 2813 of file stm32g4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | TIM handle.
sMasterConfig | pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 2180 of file stm32g4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, TIM_MasterConfigTypeDef::MasterSlaveMode, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | PulseWidthPrescaler,
 |  | uint32_t | PulseWidth
 | ) |  |

Initializes the pulse on compare pulse width and pulse prescaler.

Parameters:
htim | TIM Output Compare handle
PulseWidthPrescaler | Pulse width prescaler This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
PulseWidth | Pulse width This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
Return values:
HAL status

Definition at line 3030 of file stm32g4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_PULSEONCOMPARE_INSTANCE, IS_TIM_PULSEONCOMPARE_WIDTH, IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput
 | ) |  |

Arm the designated break input (when it operates in bidirectional mode).

Parameters:
htim TIM handle.
BreakInput Break input to arm This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
Note:
Arming is possible at anytime, even if fault is present.
Break input is automatically armed as soon as MOE bit is set.
Return values:
HAL status

Definition at line 2905 of file stm32g4xx_hal_tim_ex.c.

References assert_param, HAL_GetTick(), __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, and TIM_BREAKINPUT_REARM_TIMEOUT.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim TIM handle.
Remap specifies the TIM remapping source. For TIM1, the parameter can take one of the following values:
  • TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
  • TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
  • TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output
  • TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3 output
  • TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4 output
  • TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5 output (*)
  • TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6 output (*)
  • TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7 output (*)
  • TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
  • TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 (*)
  • TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 (*)
  • TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 (*)
For TIM2, the parameter can take one of the following values:
  • TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
  • TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
  • TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output
  • TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3 output
  • TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4 output
  • TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5 output (*)
  • TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6 output (*)
  • TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7 output (*)
  • TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
  • TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
  • TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*)
  • TIM_TIM2_ETR_LSE
For TIM3, the parameter can take one of the following values:
  • TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
  • TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
  • TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output
  • TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3 output
  • TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4 output
  • TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5 output (*)
  • TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6 output (*)
  • TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7 output (*)
  • TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
  • TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
  • TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1
  • TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2
  • TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3
For TIM4, the parameter can take one of the following values:
  • TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
  • TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
  • TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output
  • TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3 output
  • TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4 output
  • TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5 output (*)
  • TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6 output (*)
  • TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7 output (*)
  • TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
  • TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin (*)
For TIM5, the parameter can take one of the following values: (**)
  • TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*)
  • TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*)
  • TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*)
  • TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3 output (*)
  • TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4 output (*)
  • TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5 output (*)
  • TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6 output (*)
  • TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7 output (*)
  • TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin (*)
  • TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin (*)
For TIM8, the parameter can take one of the following values:
  • TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
  • TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
  • TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output
  • TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3 output
  • TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4 output
  • TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5 output (*)
  • TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6 output (*)
  • TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7 output (*)
  • TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1
  • TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2
  • TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3
  • TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*)
  • TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*)
  • TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*)
For TIM20, the parameter can take one of the following values: (**)
  • TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO
  • TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1 output (*)
  • TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2 output (*)
  • TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3 output (*)
  • TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4 output (*)
  • TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5 output (*)
  • TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6 output (*)
  • TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7 output (*)
  • TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3 AWD1 (*)
  • TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3 AWD2 (*)
  • TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3 AWD3 (*)
  • TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5 AWD1 (*)
  • TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5 AWD2 (*)
  • TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5 AWD3 (*)
(*) Value not defined in all devices.
(**) Register not available in all devices.
Return values:
HAL status

Definition at line 2584 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_REMAP.

HAL_StatusTypeDef HAL_TIMEx_TISelection | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TISelection,
 |  | uint32_t | Channel
 | ) |  |

Select the timer input source.

Parameters:
htim TIM handle.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TI1 input channel
  • TIM_CHANNEL_2: TI2 input channel
  • TIM_CHANNEL_3: TI3 input channel
  • TIM_CHANNEL_4: TI4 input channel
TISelection specifies the timer input source For TIM1 this parameter can be one of the following values:
  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
  • TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
  • TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output
  • TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output
For TIM2 this parameter can be one of the following values:
  • TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
  • TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
  • TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output
  • TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to COMP3 output
  • TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to COMP4 output
  • TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to COMP5 output (*)
  • TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to GPIO
  • TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
  • TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output
  • TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to COMP3 output
  • TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to COMP4 output
  • TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to COMP6 output (*)
  • TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
  • TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to COMP4 output
  • TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
  • TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
  • TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
For TIM3 this parameter can be one of the following values:
  • TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
  • TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to COMP3 output
  • TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to COMP4 output
  • TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to COMP5 output (*)
  • TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to COMP6 output (*)
  • TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to COMP7 output (*)
  • TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
  • TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
  • TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output
  • TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to COMP3 output
  • TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to COMP4 output
  • TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to COMP5 output (*)
  • TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to COMP6 output (*)
  • TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to COMP7 output (*)
  • TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO
  • TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output
For TIM4 this parameter can be one of the following values:
  • TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
  • TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
  • TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output
  • TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to COMP3 output
  • TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to COMP4 output
  • TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to COMP5 output (*)
  • TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to COMP6 output (*)
  • TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to COMP7 output (*)
  • TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
  • TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
  • TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
  • TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to COMP3 output
  • TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to COMP4 output
  • TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to COMP5 output (*)
  • TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to COMP6 output (*)
  • TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to COMP7 output (*)
  • TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
  • TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to COMP5 output (*)
  • TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO
  • TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to COMP6 output (*)
For TIM5 this parameter can be one of the following values: (**)
  • TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
  • TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI clock (*)
  • TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE clock (*)
  • TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to RTC Wakeup (*)
  • TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output (*)
  • TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*)
  • TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to COMP3 output (*)
  • TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to COMP4 output (*)
  • TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to COMP5 output (*)
  • TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to COMP6 output (*)
  • TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to COMP7 output (*)
  • TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
  • TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
  • TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output
  • TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to COMP3 output
  • TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to COMP4 output
  • TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to COMP5 output (*)
  • TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to COMP6 output (*)
  • TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to COMP7 output (*)
For TIM8 this parameter can be one of the following values:
  • TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
  • TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
  • TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
  • TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to COMP3 output
  • TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to COMP4 output
For TIM15 this parameter can be one of the following values:
  • TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE clock
  • TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output
  • TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output
  • TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to COMP5 output (*)
  • TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to COMP7 output (*)
  • TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
  • TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output
  • TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to COMP3 output
  • TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to COMP6 output (*)
  • TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to COMP7 output (*)
For TIM16 this parameter can be one of the following values:
  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to COMP6 output (*)
  • TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to MCO output
  • TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to HSE div 32
  • TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to RTC wakeup
  • TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to LSE clock
  • TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to LSI clock
For TIM17 this parameter can be one of the following values:
  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to COMP5 output (*)
  • TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO output
  • TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
  • TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to RTC wakeup
  • TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE clock
  • TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI clock
For TIM20 this parameter can be one of the following values: (**)
  • TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to GPIO
  • TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to COMP1 output (*)
  • TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to COMP2 output (*)
  • TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to COMP3 output (*)
  • TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to COMP4 output (*)
(*) Value not defined in all devices.
(**) Register not available in all devices.
Return values:
HAL status

Definition at line 2758 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_TISEL, IS_TIM_TISEL_TIX_INSTANCE, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Commutation callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Commutation half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Break2 detection callback in non blocking mode.
__weak void | HAL_TIMEx_EncoderIndexCallback (TIM_HandleTypeDef *htim)
Encoder index callback in non-blocking mode.
__weak void | HAL_TIMEx_DirectionChangeCallback (TIM_HandleTypeDef *htim)
Direction change callback in non-blocking mode.
__weak void | HAL_TIMEx_IndexErrorCallback (TIM_HandleTypeDef *htim)
Index error callback in non-blocking mode.
__weak void | HAL_TIMEx_TransitionErrorCallback (TIM_HandleTypeDef *htim)
Transition error callback in non-blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_Break2Callback ( TIM_HandleTypeDef * htim )

Break2 detection callback in non blocking mode.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 3371 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Break detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3356 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_CommutCallback ( TIM_HandleTypeDef * htim )

Commutation callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3327 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void HAL_TIMEx_CommutHalfCpltCallback ( TIM_HandleTypeDef * htim )

Commutation half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3341 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

void HAL_TIMEx_DirectionChangeCallback ( TIM_HandleTypeDef * htim )

Direction change callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3401 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_EncoderIndexCallback ( TIM_HandleTypeDef * htim )

Encoder index callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3386 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_IndexErrorCallback ( TIM_HandleTypeDef * htim )

Index error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3416 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_TransitionErrorCallback ( TIM_HandleTypeDef * htim )

Transition error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3431 of file stm32g4xx_hal_tim_ex.c.

References UNUSED.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | ChannelN
 | ) |  |

Return actual state of the TIM complementary channel.

Parameters:
htim TIM handle
ChannelN TIM Complementary channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
Return values:
TIM Complementary channel state

Definition at line 3481 of file stm32g4xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and TIM_CHANNEL_N_STATE_GET.

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface handle state.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL state

Definition at line 3465 of file stm32g4xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Private Functions

Functions
TIM Extended Private Functions
TIMEx

Functions

void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.
static void | TIM_DMADelayPulseNCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback (complementary channel).
static void | TIM_DMAErrorCCxN (DMA_HandleTypeDef *hdma)
TIM DMA error callback (complementary channel)
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
ChannelNState | specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 3659 of file stm32g4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

static void TIM_DMADelayPulseNCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Delay Pulse complete callback (complementary channel).

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3549 of file stm32g4xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_PulseFinishedCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAErrorCCxN ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA error callback (complementary channel)

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3608 of file stm32g4xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_ErrorCallback(), __TIM_HandleTypeDef::hdma, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3510 of file stm32g4xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

void TIMEx_DMACommutationHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3529 of file stm32g4xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationHalfCpltCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32g4xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 47 of file stm32g4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 58 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 55 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 49 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 52 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32g4xx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 65 of file stm32g4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 69 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity

Definition at line 71 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 67 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIMEx_EncoderIndexConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_EncoderIndexConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Encoder index configuration. More...

#include <stm32g4xx_hal_tim_ex.h>

Data Fields

uint32_t | Polarity
uint32_t | Prescaler
uint32_t | Filter
FunctionalState | FirstIndexEnable
uint32_t | Position
uint32_t | Direction

Detailed Description

TIM Encoder index configuration.

Definition at line 78 of file stm32g4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_EncoderIndexConfigTypeDef::Direction

Specifies in which counter direction the index event resets the counter.This parameter can be a value of TIM Extended Encoder index direction

Definition at line 90 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

uint32_t TIMEx_EncoderIndexConfigTypeDef::Filter

TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 84 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

FunctionalState TIMEx_EncoderIndexConfigTypeDef::FirstIndexEnable

Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE.

Definition at line 86 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

uint32_t TIMEx_EncoderIndexConfigTypeDef::Polarity

TIM Encoder index polarity.This parameter can be a value of TIM Extended Encoder index polarity

Definition at line 80 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

uint32_t TIMEx_EncoderIndexConfigTypeDef::Position

Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of TIM Extended Encoder index position

Definition at line 88 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

uint32_t TIMEx_EncoderIndexConfigTypeDef::Prescaler

TIM Encoder index prescaler.This parameter can be a value of TIM Extended Encodder index prescaler

Definition at line 82 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_tim_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)
#define | TIM_TIM2_ETR_GPIO 0x00000000U
#define | TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_GPIO 0x00000000U
#define | TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)
#define | TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM4_ETR_GPIO 0x00000000U
#define | TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM8_ETR_GPIO 0x00000000U
#define | TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

Define Documentation

#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3

ADC1 analog watchdog 1

Definition at line 121 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ADC1 analog watchdog 2

Definition at line 122 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

ADC1 analog watchdog 3

Definition at line 123 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 108 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 109 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 110 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 111 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 107 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 131 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 132 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 133 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 134 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 130 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to LSE

Definition at line 149 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM3 ETR

Definition at line 144 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ETR input is connected to TIM4 ETR

Definition at line 145 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 1

Definition at line 167 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)

ADC2 analog watchdog 2

Definition at line 168 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 3

Definition at line 169 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 152 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 153 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 154 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 155 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 151 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM2 ETR

Definition at line 165 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ETR input is connected to TIM4 ETR

Definition at line 166 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 172 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 173 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 174 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 175 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 171 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM3 ETR

Definition at line 185 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3

ADC2 analog watchdog 1

Definition at line 223 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 2

Definition at line 224 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

ADC2 analog watchdog 3

Definition at line 225 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 210 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 211 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 212 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 213 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 209 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUT_BRK 0x00000001U
#define | TIM_BREAKINPUT_BRK2 0x00000002U

Define Documentation

#define TIM_BREAKINPUT_BRK 0x00000001U

Timer break input

Definition at line 263 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

#define TIM_BREAKINPUT_BRK2 0x00000002U

Timer break2 input

Definition at line 264 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U
#define | TIM_BREAKINPUTSOURCE_COMP3 0x00000008U
#define | TIM_BREAKINPUTSOURCE_COMP4 0x00000010U

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U

An external source (GPIO) is connected to the BKIN pin

Definition at line 272 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U

The COMP1 output is connected to the break input

Definition at line 273 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U

The COMP2 output is connected to the break input

Definition at line 274 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U

The COMP3 output is connected to the break input

Definition at line 275 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U

The COMP4 output is connected to the break input

Definition at line 276 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U

Break input source is disabled

Definition at line 293 of file stm32g4xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U

Break input source is enabled

Definition at line 294 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U

Break input source is active_high

Definition at line 303 of file stm32g4xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U

Break input source is active low

Definition at line 302 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Timer input selection

Defines
TIM Extended Timer input selection
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_TI1_GPIO 0x00000000U
#define | TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM2_TI1_GPIO 0x00000000U
#define | TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM2_TI2_GPIO 0x00000000U
#define | TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM2_TI3_GPIO 0x00000000U
#define | TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0
#define | TIM_TIM2_TI4_GPIO 0x00000000U
#define | TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0
#define | TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1
#define | TIM_TIM3_TI1_GPIO 0x00000000U
#define | TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM3_TI2_GPIO 0x00000000U
#define | TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM3_TI3_GPIO 0x00000000U
#define | TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0
#define | TIM_TIM4_TI1_GPIO 0x00000000U
#define | TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM4_TI2_GPIO 0x00000000U
#define | TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM4_TI3_GPIO 0x00000000U
#define | TIM_TIM4_TI4_GPIO 0x00000000U
#define | TIM_TIM8_TI1_GPIO 0x00000000U
#define | TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM15_TI1_GPIO 0x00000000U
#define | TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0
#define | TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1
#define | TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM15_TI2_GPIO 0x00000000U
#define | TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0
#define | TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1
#define | TIM_TIM16_TI1_GPIO 0x00000000U
#define | TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1
#define | TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2
#define | TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
#define | TIM_TIM17_TI1_GPIO 0x00000000U
#define | TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1
#define | TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2
#define | TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

Define Documentation

#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1

TIM15 input 1 is connected to COMP1_OUT

Definition at line 464 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM15 input 1 is connected to COMP2_OUT

Definition at line 465 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_GPIO 0x00000000U

TIM15 input 1 is connected to GPIO

Definition at line 462 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0

TIM15 input 1 is connected to LSE

Definition at line 463 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0

TIM15 input 2 is connected to COMP2_OUT

Definition at line 474 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1

TIM15 input 2 is connected to COMP3_OUT

Definition at line 475 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_GPIO 0x00000000U

TIM15 input 2 is connected to GPIO

Definition at line 473 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_GPIO 0x00000000U

TIM16 input 1 is connected to GPIO

Definition at line 484 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM16 input 1 is connected to HSE/32

Definition at line 489 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)

TIM16 input 1 is connected to LSE

Definition at line 491 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

TIM16 input 1 is connected to LSI

Definition at line 492 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1

TIM16 input 1 is connected to MCO

Definition at line 488 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2

TIM16 input 1 is connected to RTC_WAKEUP

Definition at line 490 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO 0x00000000U

TIM17 input 1 is connected to GPIO

Definition at line 495 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM17 input 1 is connected to HSE/32

Definition at line 500 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)

TIM17 input 1 is connected to LSE

Definition at line 502 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

TIM17 input 1 is connected to LSI

Definition at line 503 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1

TIM17 input 1 is connected to MCO

Definition at line 499 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2

TIM17 input 1 is connected to RTC_WAKEUP

Definition at line 501 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0

TIM1 input 1 is connected to COMP1_OUT

Definition at line 312 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1

TIM1 input 1 is connected to COMP2_OUT

Definition at line 313 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM1 input 1 is connected to COMP3_OUT

Definition at line 314 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2

TIM1 input 1 is connected to COMP4_OUT

Definition at line 315 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO 0x00000000U

TIM1 input 1 is connected to GPIO

Definition at line 311 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0

TIM2 input 1 is connected to COMP1_OUT

Definition at line 319 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1

TIM2 input 1 is connected to COMP2_OUT

Definition at line 320 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM2 input 1 is connected to COMP3_OUT

Definition at line 321 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2

TIM2 input 1 is connected to COMP4_OUT

Definition at line 322 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_GPIO 0x00000000U

TIM2 input 1 is connected to GPIO

Definition at line 318 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0

TIM2 input 2 is connected to COMP1_OUT

Definition at line 328 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1

TIM2 input 2 is connected to COMP2_OUT

Definition at line 329 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM2 input 2 is connected to COMP3_OUT

Definition at line 330 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2

TIM2 input 2 is connected to COMP4_OUT

Definition at line 331 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_GPIO 0x00000000U

TIM2 input 2 is connected to GPIO

Definition at line 327 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0

TIM2 input 3 is connected to COMP4_OUT

Definition at line 337 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI3_GPIO 0x00000000U

TIM2 input 3 is connected to GPIO

Definition at line 336 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0

TIM2 input 4 is connected to COMP1_OUT

Definition at line 340 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1

TIM2 input 4 is connected to COMP2_OUT

Definition at line 341 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_GPIO 0x00000000U

TIM2 input 4 is connected to GPIO

Definition at line 339 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0

TIM3 input 1 is connected to COMP1_OUT

Definition at line 345 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1

TIM3 input 1 is connected to COMP2_OUT

Definition at line 346 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM3 input 1 is connected to COMP3_OUT

Definition at line 347 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2

TIM3 input 1 is connected to COMP4_OUT

Definition at line 348 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_GPIO 0x00000000U

TIM3 input 1 is connected to GPIO

Definition at line 344 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0

TIM3 input 2 is connected to COMP1_OUT

Definition at line 360 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1

TIM3 input 2 is connected to COMP2_OUT

Definition at line 361 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM3 input 2 is connected to COMP3_OUT

Definition at line 362 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2

TIM3 input 2 is connected to COMP4_OUT

Definition at line 363 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_GPIO 0x00000000U

TIM3 input 2 is connected to GPIO

Definition at line 359 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0

TIM3 input 3 is connected to COMP3_OUT

Definition at line 375 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM3_TI3_GPIO 0x00000000U

TIM3 input 3 is connected to GPIO

Definition at line 374 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0

TIM4 input 1 is connected to COMP1_OUT

Definition at line 379 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1

TIM4 input 1 is connected to COMP2_OUT

Definition at line 380 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM4 input 1 is connected to COMP3_OUT

Definition at line 381 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2

TIM4 input 1 is connected to COMP4_OUT

Definition at line 382 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_GPIO 0x00000000U

TIM4 input 1 is connected to GPIO

Definition at line 378 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0

TIM4 input 2 is connected to COMP1_OUT

Definition at line 394 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1

TIM4 input 2 is connected to COMP2_OUT

Definition at line 395 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM4 input 2 is connected to COMP3_OUT

Definition at line 396 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2

TIM4 input 2 is connected to COMP4_OUT

Definition at line 397 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_GPIO 0x00000000U

TIM4 input 2 is connected to GPIO

Definition at line 393 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI3_GPIO 0x00000000U

TIM4 input 3 is connected to GPIO

Definition at line 408 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM4_TI4_GPIO 0x00000000U

TIM4 input 4 is connected to GPIO

Definition at line 413 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0

TIM8 input 1 is connected to COMP1_OUT

Definition at line 456 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1

TIM8 input 1 is connected to COMP2_OUT

Definition at line 457 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM8 input 1 is connected to COMP3_OUT

Definition at line 458 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2

TIM8 input 1 is connected to COMP4_OUT

Definition at line 459 of file stm32g4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_GPIO 0x00000000U

TIM8 input 1 is connected to GPIO

Definition at line 455 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Bitfield SMS preload enabling

Defines
TIM Extended Bitfield SMS preload enabling
TIM Extended Exported Constants

Defines

#define | TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U
#define | TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS

Define Documentation

#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS

Preload of SMS bitfield is enabled

Definition at line 521 of file stm32g4xx_hal_tim_ex.h.

#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U

Prelaod of SMS bitfield is disabled

Definition at line 520 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Encoder index position

Defines
TIM Extended Encoder index position
TIM Extended Exported Constants

Defines

#define | TIM_ENCODERINDEX_POSITION_00 0x00000000U
#define | TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0
#define | TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1
#define | TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)
#define | TIM_ENCODERINDEX_POSITION_0 0x00000000U
#define | TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0

Define Documentation

#define TIM_ENCODERINDEX_POSITION_0 0x00000000U

In directional clock mode or clock plus direction mode, index resets the counter when clock is 0

Definition at line 533 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POSITION_00 0x00000000U

Encoder index position is AB=00

Definition at line 529 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0

Encoder index position is AB=01

Definition at line 530 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0

In directional clock mode or clock plus direction mode, index resets the counter when clock is 1

Definition at line 534 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1

Encoder index position is AB=10

Definition at line 531 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)

Encoder index position is AB=11

Definition at line 532 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Encoder index direction

Defines
TIM Extended Encoder index direction
TIM Extended Exported Constants

Defines

#define | TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U
#define | TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0
#define | TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1

Define Documentation

#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1

Index resets the counter when down-counting only

Definition at line 544 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0

Index resets the counter when up-counting only

Definition at line 543 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U

Index resets the counter whatever the direction

Definition at line 542 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Encoder index polarity

Defines
TIM Extended Encoder index polarity
TIM Extended Exported Constants

Defines

#define | TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 552 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 553 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Encodder index prescaler

Defines
TIM Extended Encodder index prescaler
TIM Extended Exported Constants

Defines

#define | TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 561 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 562 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 563 of file stm32g4xx_hal_tim_ex.h.

#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 564 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Exported Macros

Defines
TIM Extended Exported Macros
TIMEx

Defines

#define | __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.
#define | __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.
#define | __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).

Define Documentation

#define __HAL_TIM_CALC_PERIOD | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 597 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PERIOD_BY_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 651 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PERIOD_DITHER | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) |
Value:
(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
  (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U

HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.

Note:
ex: __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
This macro should be used only if dithering is already enabled
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65519)

Definition at line 610 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
This macro should be used only if dithering is already enabled
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65519)

Definition at line 666 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __HAL_TIM_CALC_PSC(80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 586 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __HAL_TIM_CALC_PULSE(1000000, 0, 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 623 of file stm32g4xx_hal_tim_ex.h.

#define __HAL_TIM_CALC_PULSE_DITHER | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.

Note:
ex: __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
This macro should be used only if dithering is already enabled
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65519)

Definition at line 637 of file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIMEx

Defines

#define | IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
#define | IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
#define | IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__)
#define | IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__)
#define | IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__)
#define | IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__)
#define | IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
#define | IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
#define | IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U)
#define | IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__)
#define | IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__)
#define | IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__)
#define | IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
#define | IS_TIM_ENCODERINDEX_POSITION(__POSITION__)
#define | IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__)

Define Documentation

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 681 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))

Definition at line 696 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 706 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 703 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_CLOCKSOURCE_INSTANCE | ( | INSTANCE,
 |  | __CLOCK__
 | ) |

Definition at line 1675 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_ENCODERINDEX_DIRECTION ( __DIRECTION__ )
Value:
(((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP)      || \
                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))

Definition at line 1943 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

#define IS_TIM_ENCODERINDEX_FILTER ( __FILTER__ ) ((__FILTER__) <= 0xFUL)

Definition at line 1934 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

#define IS_TIM_ENCODERINDEX_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED)  || \
                                                           ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))

Definition at line 1926 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

#define IS_TIM_ENCODERINDEX_POSITION ( __POSITION__ )
Value:
(((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0)  || \
                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))

Definition at line 1936 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

#define IS_TIM_ENCODERINDEX_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))

Definition at line 1929 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigEncoderIndex().

#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE | ( | INSTANCE,
 |  | __SELECTION__
 | ) |

Definition at line 1844 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define IS_TIM_OC_CHANNEL_MODE | ( | __MODE__,
 |  | __CHANNEL__
 | ) |
Value:
(IS_TIM_OC_MODE(__MODE__) \
   && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
       ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1)))

Definition at line 1908 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_PULSEONCOMPARE_CHANNEL ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_3) ||    \
   ((__CHANNEL__) == TIM_CHANNEL_4))

Definition at line 1913 of file stm32g4xx_hal_tim_ex.h.

#define IS_TIM_PULSEONCOMPARE_INSTANCE ( INSTANCE ) IS_TIM_CC3_INSTANCE(INSTANCE)

Definition at line 1917 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_OC_ConfigPulseOnCompare().

#define IS_TIM_PULSEONCOMPARE_WIDTH ( __WIDTH__ ) ((__WIDTH__) <= 0xFFU)

Definition at line 1919 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_OC_ConfigPulseOnCompare().

#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER ( __PRESCALER__ ) ((__PRESCALER__) <= 0x7U)

Definition at line 1921 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_OC_ConfigPulseOnCompare().

#define IS_TIM_REMAP ( __REMAP__ ) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))

Definition at line 679 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_SLAVE_PRELOAD_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
                                                    || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))

Definition at line 1923 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigSlaveModePreload().

#define IS_TIM_TISEL ( __TISEL__ ) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))

Definition at line 709 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_TISelection().

#define IS_TIM_TISEL_TIX_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) | (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))

Definition at line 711 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_TISelection().

#define IS_TIM_TRIGGER_INSTANCE | ( | INSTANCE,
 |  | __SELECTION__
 | ) |

Definition at line 1765 of file stm32g4xx_hal_tim_ex.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Define Documentation

#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */

Definition at line 187 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */

Definition at line 186 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Definition at line 190 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */

Definition at line 189 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
                                      USART_CR1_OVER8 | USART_CR1_FIFOEN))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 180 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
                                      USART_CR3_RXFTCFG))

UART or USART CR3 fields of parameters set by UART_SetConfig API

Definition at line 183 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 382 of file stm32g4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
BreakDetectLength Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 457 of file stm32g4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart | UART handle.
Address | UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod Specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 556 of file stm32g4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 632 of file stm32g4xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 307 of file stm32g4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, UART_InitCallbacksToDefault(), and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 694 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_DeInit(), and HAL_UART_UnRegisterCallback().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 679 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UART_UnRegisterCallback().

HAL_StatusTypeDef HAL_UART_RegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID,
 |  | pUART_CallbackTypeDef | pCallback
 | ) |  |

Register a User UART Callback To be used to override the weak predefined callback.

Note:
The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
Parameters:
huart | uart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 730 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_WAKEUP_CB_ID, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback | ( | UART_HandleTypeDef * | huart,
 |  | pUART_RxEventCallbackTypeDef | pCallback
 | ) |  |

Register a User UART Rx Event Callback To be used instead of the weak predefined callback.

Parameters:
huart | Uart handle
pCallback | Pointer to the Rx Event Callback function
Return values:
HAL status

Definition at line 963 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_STATE_READY, __UART_HandleTypeDef::RxEventCallback, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_UnRegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Note:
The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
Parameters:
huart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 858 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_ErrorCallback(), HAL_UART_MspDeInit(), HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MspInit(), HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UART_WAKEUP_CB_ID, HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback ( UART_HandleTypeDef * huart )

UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.

Parameters:
huart Uart handle
Return values:
HAL status

Definition at line 994 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::RxEventCallback, and __UART_HandleTypeDef::RxState.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (+) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_UART_Abort()
        (+) HAL_UART_AbortTransmit()
        (+) HAL_UART_AbortReceive()
        (+) HAL_UART_Abort_IT()
        (+) HAL_UART_AbortTransmit_IT()
        (+) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_UART_AbortCpltCallback()
        (+) HAL_UART_AbortTransmitCpltCallback()
        (+) HAL_UART_AbortReceiveCpltCallback()

    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
        reception services:
        (+) HAL_UARTEx_RxEventCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
           in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
           Transfer is kept ongoing on UART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
           user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1642 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1872 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2614 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_Abort_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1804 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2116 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2644 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1745 of file stm32g4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2025 of file stm32g4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2629 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1506 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1536 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxState, UART_CLEAR_OREF, and UART_PARITY_NONE.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1567 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2599 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2209 of file stm32g4xx_hal_uart.c.

References __HAL_DMA_GET_COUNTER, __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ERROR_RTO, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_IDLE, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::hdmarx, __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxISR, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_RTOF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), __UART_HandleTypeDef::WakeupCallback, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1207 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1470 of file stm32g4xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, and UART_Start_Receive_DMA().

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1359 of file stm32g4xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, and UART_Start_Receive_IT().

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2569 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2584 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1117 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1400 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1291 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FIFOMODE_ENABLE, UART_PARITY_NONE, UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2539 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2554 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_RxEventCallback | ( | UART_HandleTypeDef * | huart,
 |  | uint16_t | Size
 | ) |  |

Reception Event Callback (Rx event notification called after use of advanced reception service).

Parameters:
huart | UART handle
Size | Number of data available in application reception buffer (indicates a position in reception buffer until which, data are available)
Return values:
None

Definition at line 2661 of file stm32g4xx_hal_uart.c.

References UNUSED.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterRxEventCallback(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart UART handle.
Return values:
HAL status.

Definition at line 2873 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2850 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2897 of file stm32g4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2820 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2800 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart UART handle.
Return values:
None

Definition at line 2840 of file stm32g4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout ( UART_HandleTypeDef * huart )

Disable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2762 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout ( UART_HandleTypeDef * huart )

Enable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2724 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

void HAL_UART_ReceiverTimeout_Config | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | TimeoutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
huart | Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
TimeoutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 2709 of file stm32g4xx_hal_uart.c.

References assert_param, __UART_HandleTypeDef::Instance, and IS_UART_RECEIVER_TIMEOUT_VALUE.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( const UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2958 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( const UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 2942 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, and __UART_HandleTypeDef::RxState.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart UART handle.
Return values:
None

Definition at line 3221 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, __UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3295 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3794 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3754 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Transmit_DMA(), and UART_Start_Receive_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3655 of file stm32g4xx_hal_uart.c.

References HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::RxXferSize.

Referenced by UART_Start_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3872 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3716 of file stm32g4xx_hal_uart.c.

References HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_HT, HAL_UART_RxHalfCpltCallback(), HAL_UARTEx_RxEventCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxHalfCpltCallback, and __UART_HandleTypeDef::RxXferSize.

Referenced by UART_Start_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3957 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __TIM_HandleTypeDef::hdma, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3603 of file stm32g4xx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3817 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3637 of file stm32g4xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3924 of file stm32g4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, and UART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3577 of file stm32g4xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxISR, and __UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), UART_DMAError(), and UART_WaitOnFlagUntilTimeout().

static void UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 4132 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxISR.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3561 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

void UART_InitCallbacksToDefault ( UART_HandleTypeDef * huart )

Initialize the callbacks to their default values.

Parameters:
huart UART handle.
Return values:
none

Definition at line 2980 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ErrorCallback(), HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UARTEx_RxEventCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_RxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 9 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4248 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, and UART_RXDATA_FLUSH_REQUEST.

Referenced by UART_RxISR_16BIT_FIFOEN(), and UART_Start_Receive_IT().

static void UART_RxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4503 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_PEF, UART_FLAG_IDLE, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_16BIT().

Referenced by UART_Start_Receive_IT().

static void UART_RxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 7 or 8 bits data word length .

Parameters:
huart UART handle.
Return values:
None

Definition at line 4157 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, and UART_RXDATA_FLUSH_REQUEST.

Referenced by UART_RxISR_8BIT_FIFOEN(), and UART_Start_Receive_IT().

static void UART_RxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4341 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_PEF, UART_FLAG_IDLE, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_8BIT().

Referenced by UART_Start_Receive_IT().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3004 of file stm32g4xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, UART_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_PRESCALER, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LPUART_BRR_MAX, LPUART_BRR_MIN, LSE_VALUE, UART_InitTypeDef::Mode, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxISR, UART_InitTypeDef::StopBits, __UART_HandleTypeDef::TxISR, UART_BRR_MAX, UART_BRR_MIN, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_OVERSAMPLING_8, UARTPrescTable, USART_CR1_FIELDS, USART_CR3_FIELDS, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_Start_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Start Receive operation in DMA mode.

Note:
This function could be called by all HAL UART API providing reception in DMA mode.
When calling this function, parameters validity is considered as already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as Locked.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 3504 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_PARITY_NONE, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_UART_Receive_DMA(), and HAL_UARTEx_ReceiveToIdle_DMA().

HAL_StatusTypeDef UART_Start_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Start Receive operation in interrupt mode.

Note:
This function could be called by all HAL UART API providing reception in Interrupt mode.
When calling this function, parameters validity is considered as already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as Locked.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 3432 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FIFOMODE_ENABLE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_Receive_IT(), and HAL_UARTEx_ReceiveToIdle_IT().

static void UART_TxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 9 bits data word length.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4019 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4091 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 7 or 8 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3990 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4051 of file stm32g4xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

This function handles UART Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
huart | UART handle.
Flag | Specifies the UART flag to check
Status | The actual Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3364 of file stm32g4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_ORE, HAL_UART_ERROR_RTO, __UART_HandleTypeDef::Instance, UART_CLEAR_OREF, UART_CLEAR_RTOF, UART_EndRxTransfer(), UART_FLAG_ORE, UART_FLAG_RTOF, UART_FLAG_TC, and UART_FLAG_TXE.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Exported Types

Data Structures | Typedefs | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef uint32_t | HAL_UART_RxTypeTypeDef
HAL UART Reception type definition.
typedef uint32_t | HAL_UART_RxEventTypeTypeDef
HAL UART Rx Event type definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.
typedef void(* | pUART_RxEventCallbackTypeDef )(struct __UART_HandleTypeDef *huart, uint16_t Pos)

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_UART_RxEventTypeTypeDef

HAL UART Rx Event type definition.

Note:
HAL UART Rx Event type value aims to identify which type of Event has occurred leading to call of the RxEvent callback. This parameter can be a value of UART RxEvent type values : HAL_UART_RXEVENT_TC = 0x00U, HAL_UART_RXEVENT_HT = 0x01U, HAL_UART_RXEVENT_IDLE = 0x02U,

Definition at line 214 of file stm32g4xx_hal_uart.h.

typedef uint32_t HAL_UART_RxTypeTypeDef

HAL UART Reception type definition.

Note:
HAL UART Reception type value aims to identify which type of Reception is ongoing. This parameter can be a value of UART Reception type values : HAL_UART_RECEPTION_STANDARD = 0x00U, HAL_UART_RECEPTION_TOIDLE = 0x01U, HAL_UART_RECEPTION_TORTO = 0x02U, HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,

Definition at line 203 of file stm32g4xx_hal_uart.h.

typedef uint32_t HAL_UART_StateTypeDef

HAL UART State definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState (see UART State Code Definition).
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 179 of file stm32g4xx_hal_uart.h.

typedef void(* pUART_CallbackTypeDef)(UART_HandleTypeDef *huart)

HAL UART Callback pointer definition.

pointer to an UART callback function

Definition at line 317 of file stm32g4xx_hal_uart.h.

typedef void(* pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos)

pointer to a UART Rx Event specific callback function

Definition at line 319 of file stm32g4xx_hal_uart.h.

typedef struct __UART_HandleTypeDef UART_HandleTypeDef

UART handle Structure definition.

Enumeration Type Documentation

enum HAL_UART_CallbackIDTypeDef

HAL UART Callback ID enumeration definition.

Enumerator:
HAL_UART_TX_HALFCOMPLETE_CB_ID

UART Tx Half Complete Callback ID

HAL_UART_TX_COMPLETE_CB_ID

UART Tx Complete Callback ID

HAL_UART_RX_HALFCOMPLETE_CB_ID

UART Rx Half Complete Callback ID

HAL_UART_RX_COMPLETE_CB_ID

UART Rx Complete Callback ID

HAL_UART_ERROR_CB_ID

UART Error Callback ID

HAL_UART_ABORT_COMPLETE_CB_ID

UART Abort Complete Callback ID

HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID

UART Abort Transmit Complete Callback ID

HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID

UART Abort Receive Complete Callback ID

HAL_UART_WAKEUP_CB_ID

UART Wakeup Callback ID

HAL_UART_RX_FIFO_FULL_CB_ID

UART Rx Fifo Full Callback ID

HAL_UART_TX_FIFO_EMPTY_CB_ID

UART Tx Fifo Empty Callback ID

HAL_UART_MSPINIT_CB_ID

UART MspInit callback ID

HAL_UART_MSPDEINIT_CB_ID

UART MspDeInit callback ID

Definition at line 295 of file stm32g4xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_PCLK2

PCLK2 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 184 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32g4xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling
uint32_t | ClockPrescaler

Detailed Description

UART Init Structure definition.

Definition at line 46 of file stm32g4xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula: LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: =====

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock divided by a prescaler

Definition at line 48 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of UART Clock Prescaler.

Definition at line 94 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 82 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 79 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 90 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 86 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 72 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_SetConfig(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 69 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length.

Definition at line 66 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_SetConfig(), and UART_Start_Receive_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_uart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initialization structure definition. More...

#include <stm32g4xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initialization structure definition.

Definition at line 102 of file stm32g4xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 104 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable.

Definition at line 128 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 131 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 115 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 125 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 135 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 122 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 112 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 119 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 109 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_uart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32g4xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint32_t | FifoMode
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
__IO HAL_UART_RxTypeTypeDef | ReceptionType
__IO HAL_UART_RxEventTypeTypeDef | RxEventType
void(* | RxISR )(struct __UART_HandleTypeDef *huart)
void(* | TxISR )(struct __UART_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | ErrorCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortTransmitCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortReceiveCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | WakeupCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxFifoFullCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxFifoEmptyCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxEventCallback )(struct __UART_HandleTypeDef *huart, uint16_t Pos)
void(* | MspInitCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspDeInitCallback )(struct __UART_HandleTypeDef *huart)

Detailed Description

UART handle Structure definition.

Definition at line 219 of file stm32g4xx_hal_uart.h.

Field Documentation

void(* __UART_HandleTypeDef::AbortCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Complete Callback

Definition at line 277 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Receive Complete Callback

Definition at line 279 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Transmit Complete Callback

Definition at line 278 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

UART_AdvFeatureInitTypeDef __UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 225 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

void(* __UART_HandleTypeDef::ErrorCallback)(struct __UART_HandleTypeDef *huart)

UART Error Callback

Definition at line 276 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

__IO uint32_t __UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 269 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DeInit(), HAL_UART_DMAStop(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_ReceiveToIdle(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), UART_Start_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

uint32_t __UART_HandleTypeDef::FifoMode

Specifies if the FIFO mode is being used. This parameter can be a value of UARTEx FIFO mode.

Definition at line 241 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_Start_Receive_IT(), and UARTEx_SetNbDataToProcess().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 262 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 258 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_Start_Receive_DMA().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 256 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef __UART_HandleTypeDef::Init

UART communication parameters

Definition at line 223 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_DMAResume(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_SetConfig(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

USART_TypeDef* __UART_HandleTypeDef::Instance

UART registers base address

Definition at line 221 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_ReceiverTimeout_Config(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_Start_Receive_DMA(), UART_Start_Receive_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WaitOnFlagUntilTimeout(), UARTEx_SetNbDataToProcess(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef __UART_HandleTypeDef::Lock

Locking object

Definition at line 260 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t __UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 239 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::MspDeInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp DeInit callback

Definition at line 286 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

void(* __UART_HandleTypeDef::MspInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp Init callback

Definition at line 285 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

uint16_t __UART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 244 of file stm32g4xx_hal_uart.h.

Referenced by UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_Start_Receive_IT(), UARTEx_SetNbDataToProcess(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 246 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT_FIFOEN(), and UARTEx_SetNbDataToProcess().

uint8_t* __UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 233 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

const uint8_t* __UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 227 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

__IO HAL_UART_RxTypeTypeDef __UART_HandleTypeDef::ReceptionType

Type of ongoing reception

Definition at line 248 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Complete Callback

Definition at line 275 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos)

UART Reception Event Callback

Definition at line 283 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterRxEventCallback(), HAL_UART_UnRegisterRxEventCallback(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

__IO HAL_UART_RxEventTypeTypeDef __UART_HandleTypeDef::RxEventType

Type of Rx Event

Definition at line 250 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UARTEx_GetRxEventType(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxFifoFullCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Fifo Full Callback

Definition at line 281 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Half Complete Callback

Definition at line 274 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 252 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_IRQHandler(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), and UART_Start_Receive_IT().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 266 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterRxEventCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

__IO uint16_t __UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 237 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_Start_Receive_IT().

uint16_t __UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 235 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

void(* __UART_HandleTypeDef::TxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Complete Callback

Definition at line 273 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Fifo Empty Callback

Definition at line 282 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Half Complete Callback

Definition at line 272 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 254 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_EndTransmit_IT(), and UART_SetConfig().

__IO uint16_t __UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 231 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 229 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

void(* __UART_HandleTypeDef::WakeupCallback)(struct __UART_HandleTypeDef *huart)

UART Wakeup Callback

Definition at line 280 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_uart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART State Code Definition

Defines
UART State Code Definition
UART Exported Constants

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_UART_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 339 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define HAL_UART_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 343 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAError(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define HAL_UART_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 341 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState.Value is result of combination (Or) between gState and RxState values

Definition at line 345 of file stm32g4xx_hal_uart.h.

#define HAL_UART_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 350 of file stm32g4xx_hal_uart.h.

#define HAL_UART_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 337 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_Start_Receive_DMA().

#define HAL_UART_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 335 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 348 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Error Definition

Defines
UART Error Definition
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_RTO (0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_UART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 364 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMAError(), and UART_Start_Receive_DMA().

#define HAL_UART_ERROR_FE (0x00000004U)

Frame error

Definition at line 362 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 368 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_UnRegisterCallback(), and HAL_UART_UnRegisterRxEventCallback().

#define HAL_UART_ERROR_NE (0x00000002U)

Noise error

Definition at line 361 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_NONE (0x00000000U)

No error

Definition at line 359 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_CheckIdleState(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define HAL_UART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 363 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define HAL_UART_ERROR_PE (0x00000001U)

Parity error

Definition at line 360 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_RTO (0x00000020U)

Receiver Timeout error

Definition at line 365 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 377 of file stm32g4xx_hal_uart.h.

#define UART_STOPBITS_1 0x00000000U

UART frame with 1 stop bit

Definition at line 378 of file stm32g4xx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 379 of file stm32g4xx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 380 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define UART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 389 of file stm32g4xx_hal_uart.h.

#define UART_PARITY_NONE 0x00000000U

No parity

Definition at line 388 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 390 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define UART_HWCONTROL_CTS USART_CR3_CTSE

Clear To Send

Definition at line 400 of file stm32g4xx_hal_uart.h.

#define UART_HWCONTROL_NONE 0x00000000U

No hardware control

Definition at line 398 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS USART_CR3_RTSE

Request To Send

Definition at line 399 of file stm32g4xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Request and Clear To Send

Definition at line 401 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define UART_MODE_RX USART_CR1_RE

RX mode

Definition at line 409 of file stm32g4xx_hal_uart.h.

#define UART_MODE_TX USART_CR1_TE

TX mode

Definition at line 410 of file stm32g4xx_hal_uart.h.

#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 411 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE

Define Documentation

#define UART_STATE_DISABLE 0x00000000U

UART disabled

Definition at line 419 of file stm32g4xx_hal_uart.h.

#define UART_STATE_ENABLE USART_CR1_UE

UART enabled

Definition at line 420 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define UART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 428 of file stm32g4xx_hal_uart.h.

#define UART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 429 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disable

Definition at line 437 of file stm32g4xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enable

Definition at line 438 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Clock Prescaler

Defines
UART Clock Prescaler
UART Exported Constants

Defines

#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define UART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 446 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 451 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 452 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 456 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 453 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 447 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 457 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 454 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 448 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 449 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 455 of file stm32g4xx_hal_uart.h.

#define UART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 450 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Auto Baud rate detection on 0x55 frame detection

Definition at line 471 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1

Auto Baud rate detection on 0x7F frame detection

Definition at line 469 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0

Auto Baud rate detection on falling edge

Definition at line 467 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U

Auto Baud rate detection on start bit

Definition at line 465 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Receiver Timeout

Defines
UART Receiver Timeout
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U

UART Receiver Timeout disable

Definition at line 480 of file stm32g4xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

UART Receiver Timeout enable

Definition at line 481 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN

Define Documentation

#define UART_LIN_DISABLE 0x00000000U

Local Interconnect Network disable

Definition at line 489 of file stm32g4xx_hal_uart.h.

#define UART_LIN_ENABLE USART_CR2_LINEN

Local Interconnect Network enable

Definition at line 490 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U

LIN 10-bit break detection length

Definition at line 498 of file stm32g4xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

LIN 11-bit break detection length

Definition at line 499 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define UART_DMA_TX_DISABLE 0x00000000U

UART DMA TX disabled

Definition at line 507 of file stm32g4xx_hal_uart.h.

#define UART_DMA_TX_ENABLE USART_CR3_DMAT

UART DMA TX enabled

Definition at line 508 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define UART_DMA_RX_DISABLE 0x00000000U

UART DMA RX disabled

Definition at line 516 of file stm32g4xx_hal_uart.h.

#define UART_DMA_RX_ENABLE USART_CR3_DMAR

UART DMA RX enabled

Definition at line 517 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

Define Documentation

#define UART_HALF_DUPLEX_DISABLE 0x00000000U

UART half-duplex disabled

Definition at line 525 of file stm32g4xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

UART half-duplex enabled

Definition at line 526 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

UART wake-up on address mark

Definition at line 535 of file stm32g4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U

UART wake-up on idle line

Definition at line 534 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 543 of file stm32g4xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ

Mute Mode Request

Definition at line 545 of file stm32g4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 546 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ

Send Break Request

Definition at line 544 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 547 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U

Auto Baud rate detection initialization

Definition at line 562 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 558 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 561 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 563 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 555 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 557 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 560 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 559 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 556 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 571 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 572 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 580 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 581 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 589 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 590 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 598 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 599 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 608 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 607 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U

RX Auto Baud rate detection enable

Definition at line 616 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

RX Auto Baud rate detection disable

Definition at line 617 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 626 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 625 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 634 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 636 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U

UART stop mode disable

Definition at line 645 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

UART stop mode enable

Definition at line 646 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U

UART mute mode disable

Definition at line 654 of file stm32g4xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

UART mute mode enable

Definition at line 655 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS 24U

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS 24U

UART address-matching LSB position in CR2 register

Definition at line 663 of file stm32g4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

Define Documentation

#define UART_WAKEUP_ON_ADDRESS 0x00000000U

UART wake-up on address

Definition at line 671 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

UART wake-up on receive data register not empty or RXFIFO is not empty

Definition at line 673 of file stm32g4xx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

UART wake-up on start bit

Definition at line 672 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define UART_DE_POLARITY_HIGH 0x00000000U

Driver enable signal is active high

Definition at line 682 of file stm32g4xx_hal_uart.h.

#define UART_DE_POLARITY_LOW USART_CR3_DEP

Driver enable signal is active low

Definition at line 683 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 691 of file stm32g4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 700 of file stm32g4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK 0x001FU

Define Documentation

#define UART_IT_MASK 0x001FU

UART interruptions flags mask

Definition at line 709 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

UART polling-based communications time-out value

Definition at line 717 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE USART_ISR_ABRE

UART auto Baud rate error

Definition at line 739 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_ABRF USART_ISR_ABRF

UART auto Baud rate flag

Definition at line 738 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_BUSY USART_ISR_BUSY

UART busy flag

Definition at line 737 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_CMF USART_ISR_CMF

UART character match flag

Definition at line 736 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_CTS USART_ISR_CTS

UART clear to send flag

Definition at line 741 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_CTSIF USART_ISR_CTSIF

UART clear to send interrupt flag

Definition at line 742 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_FE USART_ISR_FE

UART frame error

Definition at line 752 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_IDLE USART_ISR_IDLE

UART idle flag

Definition at line 749 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_FLAG_LBDF USART_ISR_LBDF

UART LIN break detection flag

Definition at line 743 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_NE USART_ISR_NE

UART noise error

Definition at line 751 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_ORE USART_ISR_ORE

UART overrun error

Definition at line 750 of file stm32g4xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_PE USART_ISR_PE

UART parity error

Definition at line 753 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_REACK USART_ISR_REACK

UART receive enable acknowledge flag

Definition at line 731 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_RTOF USART_ISR_RTOF

UART receiver timeout flag

Definition at line 740 of file stm32g4xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_RWU USART_ISR_RWU

UART receiver wake-up from mute mode flag

Definition at line 734 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_RXFF USART_ISR_RXFF

UART RXFIFO Full flag

Definition at line 729 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

UART RXFIFO not empty

Definition at line 748 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_RXFT USART_ISR_RXFT

UART RXFIFO threshold flag

Definition at line 728 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE

UART read data register not empty

Definition at line 747 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and HAL_UARTEx_ReceiveToIdle().

#define UART_FLAG_SBKF USART_ISR_SBKF

UART send break flag

Definition at line 735 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_TC USART_ISR_TC

UART transmission complete

Definition at line 746 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), and UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_TEACK USART_ISR_TEACK

UART transmit enable acknowledge flag

Definition at line 732 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_TXE USART_ISR_TXE_TXFNF

UART transmit data register empty

Definition at line 744 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), and UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_TXFE USART_ISR_TXFE

UART TXFIFO Empty flag

Definition at line 730 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF

UART TXFIFO not full

Definition at line 745 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_TXFT USART_ISR_TXFT

UART TXFIFO threshold flag

Definition at line 727 of file stm32g4xx_hal_uart.h.

#define UART_FLAG_WUF USART_ISR_WUF

UART wake-up from stop mode flag

Definition at line 733 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits) Elements values convention: 000000000XXYYYYYb
  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register Elements values convention: 0000ZZZZ00000000b
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define UART_IT_CM 0x112EU

UART character match interruption

Definition at line 785 of file stm32g4xx_hal_uart.h.

#define UART_IT_CTS 0x096AU

UART CTS interruption

Definition at line 784 of file stm32g4xx_hal_uart.h.

#define UART_IT_ERR 0x0060U

UART error interruption

Definition at line 793 of file stm32g4xx_hal_uart.h.

#define UART_IT_FE 0x0100U

UART frame error interruption

Definition at line 797 of file stm32g4xx_hal_uart.h.

#define UART_IT_IDLE 0x0424U

UART idle interruption

Definition at line 782 of file stm32g4xx_hal_uart.h.

#define UART_IT_LBD 0x0846U

UART LIN break detection interruption

Definition at line 783 of file stm32g4xx_hal_uart.h.

#define UART_IT_NE 0x0200U

UART noise error interruption

Definition at line 796 of file stm32g4xx_hal_uart.h.

#define UART_IT_ORE 0x0300U

UART overrun error interruption

Definition at line 795 of file stm32g4xx_hal_uart.h.

#define UART_IT_PE 0x0028U

UART parity error interruption

Definition at line 776 of file stm32g4xx_hal_uart.h.

#define UART_IT_RTO 0x0B3AU

UART receiver timeout interruption

Definition at line 791 of file stm32g4xx_hal_uart.h.

#define UART_IT_RXFF 0x183FU

UART RXFIFO full interruption

Definition at line 787 of file stm32g4xx_hal_uart.h.

#define UART_IT_RXFNE 0x0525U

UART RXFIFO not empty interruption

Definition at line 781 of file stm32g4xx_hal_uart.h.

#define UART_IT_RXFT 0x1A7CU

UART RXFIFO threshold reached interruption

Definition at line 789 of file stm32g4xx_hal_uart.h.

#define UART_IT_RXNE 0x0525U

UART read data register not empty interruption

Definition at line 780 of file stm32g4xx_hal_uart.h.

#define UART_IT_TC 0x0626U

UART transmission complete interruption

Definition at line 779 of file stm32g4xx_hal_uart.h.

#define UART_IT_TXE 0x0727U

UART transmit data register empty interruption

Definition at line 777 of file stm32g4xx_hal_uart.h.

#define UART_IT_TXFE 0x173EU

UART TXFIFO empty interruption

Definition at line 788 of file stm32g4xx_hal_uart.h.

#define UART_IT_TXFNF 0x0727U

UART TX FIFO not full interruption

Definition at line 778 of file stm32g4xx_hal_uart.h.

#define UART_IT_TXFT 0x1B77U

UART TXFIFO threshold reached interruption

Definition at line 790 of file stm32g4xx_hal_uart.h.

#define UART_IT_WUF 0x1476U

UART wake-up from stop mode interruption

Definition at line 786 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 814 of file stm32g4xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 813 of file stm32g4xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 806 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 809 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 812 of file stm32g4xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 807 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 808 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_WaitOnFlagUntilTimeout().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 805 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

UART receiver timeout clear flag

Definition at line 816 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 811 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 810 of file stm32g4xx_hal_uart.h.

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 815 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Reception type values

Defines
UART Reception type values
UART Exported Constants

Defines

#define | HAL_UART_RECEPTION_STANDARD (0x00000000U)
#define | HAL_UART_RECEPTION_TOIDLE (0x00000001U)
#define | HAL_UART_RECEPTION_TORTO (0x00000002U)
#define | HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)

Define Documentation

#define HAL_UART_RECEPTION_STANDARD (0x00000000U)

Standard reception

Definition at line 824 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)

Reception till completion or CM event

Definition at line 827 of file stm32g4xx_hal_uart.h.

#define HAL_UART_RECEPTION_TOIDLE (0x00000001U)

Reception till completion or IDLE event

Definition at line 825 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_RECEPTION_TORTO (0x00000002U)

Reception till completion or RTO event

Definition at line 826 of file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART RxEvent type values

Defines
UART RxEvent type values
UART Exported Constants

Defines

#define | HAL_UART_RXEVENT_TC (0x00000000U)
#define | HAL_UART_RXEVENT_HT (0x00000001U)
#define | HAL_UART_RXEVENT_IDLE (0x00000002U)

Define Documentation

#define HAL_UART_RXEVENT_HT (0x00000001U)

RxEvent linked to Half Transfer event

Definition at line 836 of file stm32g4xx_hal_uart.h.

Referenced by UART_DMARxHalfCplt().

#define HAL_UART_RXEVENT_IDLE (0x00000002U)

RxEvent linked to IDLE event

Definition at line 837 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and HAL_UARTEx_ReceiveToIdle().

#define HAL_UART_RXEVENT_TC (0x00000000U)

RxEvent linked to Transfer Complete event

Definition at line 835 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 909 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TXFECF TXFIFO empty clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_RTOF Receiver Timeout clear flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 897 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 927 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_RTOF Receiver timeout clear flag
  • UART_CLEAR_TXFECF TXFIFO empty Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 1111 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 915 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 921 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 903 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

Clear the UART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 933 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1148 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 1025 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1142 of file stm32g4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
Return values:
None

Definition at line 992 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
  }  while(0U)

Flush the UART Data registers.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 873 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_TXFT TXFIFO threshold flag
  • UART_FLAG_RXFT RXFIFO threshold flag
  • UART_FLAG_RXFF RXFIFO Full flag
  • UART_FLAG_TXFE TXFIFO Empty flag
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_CTS CTS Change flag
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TXFNF UART TXFIFO not full flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_RXFNE UART RXFIFO not empty flag
  • UART_FLAG_RTOF Receiver Timeout flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 967 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1058 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
                                                                (__HANDLE__)->Instance->CR1 : \
                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
                                                                 (__HANDLE__)->Instance->CR2 : \
                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
                                                                     (((uint16_t)(__INTERRUPT__)) &\
                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1084 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                              \
    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
  } while(0U)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1182 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                             \
    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
  } while(0U)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1163 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                             \
    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
  } while(0U)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1220 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                            \
    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
  } while(0U)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1201 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1136 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1130 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset UART handle states.

Parameters:
__HANDLE__ UART handle.
Return values:
None

Definition at line 856 of file stm32g4xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 1124 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__ LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1321 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__ UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1519 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__ UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1380 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__ UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1495 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1528 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__ UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1464 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__ UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1536 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__ UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1487 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__ UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1544 of file stm32g4xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1503 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__ UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1479 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__ 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1298 of file stm32g4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 18750001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1292 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__ UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1569 of file stm32g4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__ 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1304 of file stm32g4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__ UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1429 of file stm32g4xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__ UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1421 of file stm32g4xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__ UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1437 of file stm32g4xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__ UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1338 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__ UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1405 of file stm32g4xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__ UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1413 of file stm32g4xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that UART communication mode is valid.

Parameters:
__MODE__ UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1349 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__ UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1552 of file stm32g4xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__ UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1372 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__ UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1511 of file stm32g4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__ UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1364 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__ UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1329 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))

Ensure that UART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ UART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1577 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__ UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1390 of file stm32g4xx_hal_uart.h.

#define IS_UART_RECEIVER_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum UART receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 1398 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UART_ReceiverTimeout_Config().

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__ UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1453 of file stm32g4xx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__ UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1356 of file stm32g4xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__ UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1311 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__ UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1560 of file stm32g4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__ UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1445 of file stm32g4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
  )

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__ | LPUART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1257 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) | ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1277 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) | (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1268 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)

Get UART clok division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ UART prescaler value.
Return values:
UART clock division factor

Definition at line 1237 of file stm32g4xx_hal_uart.h.

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1284 of file stm32g4xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Private variables

Variables
UART Private variables
UART

Variables

const uint16_t | UARTPrescTable [12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}
const uint16_t | UARTPrescTable [12]

Variable Documentation

const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}

Definition at line 229 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

const uint16_t UARTPrescTable[12]

Definition at line 229 of file stm32g4xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Private Constants

Defines
UARTEx Private Constants
UARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 63 of file stm32g4xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 66 of file stm32g4xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void UARTEx_SetNbDataToProcess ( UART_HandleTypeDef * huart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the UART configuration registers.
Parameters:
huart UART handle.
Return values:
None

Definition at line 1003 of file stm32g4xx_hal_uart_ex.c.

References __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and UART_FIFOMODE_DISABLE.

Referenced by HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), and HAL_UARTEx_SetTxFifoThreshold().

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart | UART handle.
WakeUpSelection | UART wake up from stop mode parameters.
Return values:
None

Definition at line 985 of file stm32g4xx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart | UART handle.
Polarity Select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime | Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime | Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), and UART_SetConfig().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
UARTEx Exported Functions

Extended functions. More...

Functions

__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.

Detailed Description

Extended functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of Wakeup and FIFO mode related callback functions.

    (#) Wakeup from Stop mode Callback:
        (+) HAL_UARTEx_WakeupCallback()

    (#) TX/RX Fifos Callbacks:
        (+) HAL_UARTEx_RxFifoFullCallback()
        (+) HAL_UARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_UARTEx_RxFifoFullCallback ( UART_HandleTypeDef * huart )

UART RX Fifo full callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 289 of file stm32g4xx_hal_uart_ex.c.

References UNUSED.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_TxFifoEmptyCallback ( UART_HandleTypeDef * huart )

UART TX Fifo empty callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 304 of file stm32g4xx_hal_uart_ex.c.

References UNUSED.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 274 of file stm32g4xx_hal_uart_ex.c.

References UNUSED.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (const UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

    [..] This subsection also provides a set of additional functions providing enhanced reception
    services to user. (For example, these functions allow application to handle use cases
    where number of data to be received is unknown).

    (#) Compared to standard reception services which only consider number of received
        data elements as reception completion criteria, these functions also consider additional events
        as triggers for updating reception status to caller :
       (+) Detection of inactivity period (RX line has not been active for a given period).
          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
               for 1 frame time, after last received byte.
          (++) RX inactivity detected by RTO, i.e. line has been in idle state
               for a programmable time, after last received byte.
       (+) Detection that a specific character has been received.

    (#) There are two mode of transfer:
       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
           or till IDLE event occurs. Reception is handled only during function execution.
           When function exits, no data reception could occur. HAL status and number of actually received data elements,
           are returned by function after finishing transfer.
       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.

    (#) Blocking mode API:
        (+) HAL_UARTEx_ReceiveToIdle()

    (#) Non-Blocking mode API with Interrupt:
        (+) HAL_UARTEx_ReceiveToIdle_IT()

    (#) Non-Blocking mode API with DMA:
        (+) HAL_UARTEx_ReceiveToIdle_DMA()

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart UART handle.
AddressLength This parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 389 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode ( UART_HandleTypeDef * huart )

Disable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 561 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 501 of file stm32g4xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode ( UART_HandleTypeDef * huart )

Enable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 520 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, UART_FIFOMODE_ENABLE, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 482 of file stm32g4xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType ( const UART_HandleTypeDef * huart )

Provide Rx Event type that has lead to RxEvent callback execution.

Note:
When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress of reception process is provided to application through calls of Rx Event callback (either default one HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead to Rx Event callback execution.
This function is expected to be called within the user implementation of Rx Event Callback, in order to provide the accurate value : In Interrupt Mode :
  • HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
  • HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of received data is lower than expected one) In DMA Mode :
  • HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
  • HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
  • HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of received data is lower than expected one). In DMA mode, RxEvent callback could be called several times; When DMA is configured in Normal Mode, HT event does not stop Reception process; When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
Parameters:
huart UART handle.
Return values:
Rx Event Type (return vale will be a value of UART RxEvent type values)

Definition at line 961 of file stm32g4xx_hal_uart_ex.c.

References __UART_HandleTypeDef::RxEventType.

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint16_t * | RxLen,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.

Note:
HAL_OK is returned if reception is completed (expected number of data has been received) or if reception is stopped after IDLE event (less than the expected number of data has been received) In this case, RxLen output parameter indicates number of data available in reception buffer.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
RxLen | Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
Timeout | Timeout duration expressed in ms (covers the whole reception sequence).
Return values:
HAL status

Definition at line 713 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_IDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.

Note:
Reception is initiated by this function call. Further progress of reception is achieved thanks to DMA services, transferring automatically received data elements in user reception buffer and calling registered callbacks at half/end of reception. UART IDLE events are also used to consider reception phase as ended. In all cases, callback execution will indicate number of received data elements.
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
Return values:
HAL status

Definition at line 893 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, UART_CLEAR_IDLEF, and UART_Start_Receive_DMA().

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.

Note:
Reception is initiated by this function call. Further progress of reception is achieved thanks to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating number of received data elements.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
Return values:
HAL status

Definition at line 836 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, UART_CLEAR_IDLEF, and UART_Start_Receive_IT().

HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
huart UART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • UART_RXFIFO_THRESHOLD_1_8
  • UART_RXFIFO_THRESHOLD_1_4
  • UART_RXFIFO_THRESHOLD_1_2
  • UART_RXFIFO_THRESHOLD_3_4
  • UART_RXFIFO_THRESHOLD_7_8
  • UART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 656 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_RXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
huart UART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • UART_TXFIFO_THRESHOLD_1_8
  • UART_TXFIFO_THRESHOLD_1_4
  • UART_TXFIFO_THRESHOLD_1_2
  • UART_TXFIFO_THRESHOLD_3_4
  • UART_TXFIFO_THRESHOLD_7_8
  • UART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 607 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_TXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Note:
It is the application responsibility to enable the interrupt used as usart_wkup interrupt source before entering low-power mode.
Parameters:
huart UART handle.
WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 427 of file stm32g4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32g4xx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 46 of file stm32g4xx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 56 of file stm32g4xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UARTEx WakeUp Address Length.

Definition at line 53 of file stm32g4xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 48 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_uart_ex.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define UART_WORDLENGTH_7B USART_CR1_M1

7-bit long UART frame

Definition at line 71 of file stm32g4xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B 0x00000000U

8-bit long UART frame

Definition at line 72 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B USART_CR1_M0

9-bit long UART frame

Definition at line 73 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), and UART_Start_Receive_IT().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx WakeUp Address Length

Defines
UARTEx WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define UART_ADDRESS_DETECT_4B 0x00000000U

4-bit long wake-up address

Definition at line 81 of file stm32g4xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit long wake-up address

Definition at line 82 of file stm32g4xx_hal_uart_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx FIFO mode

Defines
UARTEx FIFO mode
UARTEx Exported Constants

UART FIFO mode. More...

Defines

#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

UART FIFO mode.

Define Documentation

#define UART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 91 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_DisableFifoMode(), and UARTEx_SetNbDataToProcess().

#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 92 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), and UART_Start_Receive_IT().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx TXFIFO threshold level

Defines
UARTEx TXFIFO threshold level
UARTEx Exported Constants

UART TXFIFO threshold level. More...

Defines

#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

UART TXFIFO threshold level.

Define Documentation

#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TX FIFO reaches 1/2 of its depth

Definition at line 103 of file stm32g4xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TX FIFO reaches 1/4 of its depth

Definition at line 102 of file stm32g4xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U

TX FIFO reaches 1/8 of its depth

Definition at line 101 of file stm32g4xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TX FIFO reaches 3/4 of its depth

Definition at line 104 of file stm32g4xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TX FIFO reaches 7/8 of its depth

Definition at line 105 of file stm32g4xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TX FIFO becomes empty

Definition at line 106 of file stm32g4xx_hal_uart_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx RXFIFO threshold level

Defines
UARTEx RXFIFO threshold level
UARTEx Exported Constants

UART RXFIFO threshold level. More...

Defines

#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

UART RXFIFO threshold level.

Define Documentation

#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RX FIFO reaches 1/2 of its depth

Definition at line 117 of file stm32g4xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RX FIFO reaches 1/4 of its depth

Definition at line 116 of file stm32g4xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U

RX FIFO reaches 1/8 of its depth

Definition at line 115 of file stm32g4xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RX FIFO reaches 3/4 of its depth

Definition at line 118 of file stm32g4xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RX FIFO reaches 7/8 of its depth

Definition at line 119 of file stm32g4xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RX FIFO becomes full

Definition at line 120 of file stm32g4xx_hal_uart_ex.h.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__ UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 607 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

Ensure that UART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 627 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetRxFifoThreshold().

#define IS_UART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

Ensure that UART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 615 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetTxFifoThreshold().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__ UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 598 of file stm32g4xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__ | specifies the UART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 337 of file stm32g4xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 552 of file stm32g4xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), and UART_Start_Receive_IT().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Define Documentation

#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Definition at line 171 of file stm32g4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */

Definition at line 170 of file stm32g4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
                                              USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 160 of file stm32g4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
                                              USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
                                              USART_CR2_DIS_NSS))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 164 of file stm32g4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART or USART CR3 fields of parameters set by USART_SetConfig API

Definition at line 168 of file stm32g4xx_hal_usart.c.

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 158 of file stm32g4xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TEACK_REACK_TIMEOUT 1000U

USART TX or RX enable acknowledge time-out value

Definition at line 159 of file stm32g4xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 338 of file stm32g4xx_hal_usart.c.

References assert_param, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::MspDeInitCallback, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 276 of file stm32g4xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Lock, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::State, USART_CheckIdleState(), USART_InitCallbacksToDefault(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 396 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_DeInit(), and HAL_USART_UnRegisterCallback().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 381 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_Init(), and HAL_USART_UnRegisterCallback().

HAL_StatusTypeDef HAL_USART_RegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID,
 |  | pUSART_CallbackTypeDef | pCallback
 | ) |  |

Register a User USART Callback To be used to override the weak predefined callback.

Note:
The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
Parameters:
husart | usart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status +

Definition at line 429 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

HAL_StatusTypeDef HAL_USART_UnRegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USART Callback USART callaback is redirected to the weak predefined callback.

Note:
The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
Parameters:
husart usart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 553 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_ErrorCallback(), HAL_USART_MspDeInit(), HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MspInit(), HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    [..]

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT() in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA() in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_USART_Abort()
        (++) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (++) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error,
             Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
             error type, and HAL_USART_ErrorCallback() user callback is executed.
             Transfer is kept ongoing on USART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type,
             and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1885 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1983 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2445 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_Abort_IT(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1731 of file stm32g4xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1778 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, USART_CLEAR_OREF, and USART_PARITY_NONE.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1825 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2430 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2115 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, __HAL_USART_CLEAR_UDRFLAG, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ERROR_RTO, HAL_USART_ERROR_UDR, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxISR, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_CLEAR_RTOF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 842 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1491 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, UNUSED, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1184 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2385 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2400 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 744 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1406 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1101 of file stm32g4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_IT_TXE, USART_IT_TXFT, USART_PARITY_NONE, USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 954 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_ENABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received/sent.
Return values:
HAL status

Definition at line 1611 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, UNUSED, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_PARITY_NONE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Return values:
HAL status

Definition at line 1298 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2355 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2370 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2415 of file stm32g4xx_hal_usart.c.

References UNUSED.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( const USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 2493 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( const USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 2482 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::State.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2981 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2729 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, and __USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2703 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2610 of file stm32g4xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2800 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2685 of file stm32g4xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2552 of file stm32g4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2752 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2592 of file stm32g4xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 2536 of file stm32g4xx_hal_usart.c.

References HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static void USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 3190 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, __HAL_USART_DISABLE_IT, __HAL_USART_SEND_REQ, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxRxCpltCallback, USART_IT_ERR, USART_IT_TC, and USART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_IRQHandler().

void USART_InitCallbacksToDefault ( USART_HandleTypeDef * husart )

Initialize the callbacks to their default values.

Parameters:
husart USART handle.
Return values:
none

Definition at line 2516 of file stm32g4xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, HAL_USART_AbortCpltCallback(), HAL_USART_ErrorCallback(), HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Init().

static void USART_RxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3338 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_16BIT_FIFOEN().

static void USART_RxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3564 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_16BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_RxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3247 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_8BIT_FIFOEN().

static void USART_RxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3431 of file stm32g4xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_8BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2877 of file stm32g4xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, USART_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_PRESCALER, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxISR, USART_InitTypeDef::StopBits, __USART_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK1, USART_CLOCKSOURCE_PCLK2, USART_CLOCKSOURCE_SYSCLK, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_DIV_SAMPLING8, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static void USART_TxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3066 of file stm32g4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3147 of file stm32g4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3031 of file stm32g4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3102 of file stm32g4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the actual Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 2849 of file stm32g4xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Types

Data Structures | Typedefs | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U,
USART_CLOCKSOURCE_LSE = 0x08U, USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart)

HAL USART Callback pointer definition.

pointer to an USART callback function

Definition at line 206 of file stm32g4xx_hal_usart.h.

typedef struct __USART_HandleTypeDef USART_HandleTypeDef

USART handle Structure definition.

Enumeration Type Documentation

enum HAL_USART_CallbackIDTypeDef

HAL USART Callback ID enumeration definition.

Enumerator:
HAL_USART_TX_HALFCOMPLETE_CB_ID

USART Tx Half Complete Callback ID

HAL_USART_TX_COMPLETE_CB_ID

USART Tx Complete Callback ID

HAL_USART_RX_HALFCOMPLETE_CB_ID

USART Rx Half Complete Callback ID

HAL_USART_RX_COMPLETE_CB_ID

USART Rx Complete Callback ID

HAL_USART_TX_RX_COMPLETE_CB_ID

USART Tx Rx Complete Callback ID

HAL_USART_ERROR_CB_ID

USART Error Callback ID

HAL_USART_ABORT_COMPLETE_CB_ID

USART Abort Complete Callback ID

HAL_USART_RX_FIFO_FULL_CB_ID

USART Rx Fifo Full Callback ID

HAL_USART_TX_FIFO_EMPTY_CB_ID

USART Tx Fifo Empty Callback ID

HAL_USART_MSPINIT_CB_ID

USART MspInit callback ID

HAL_USART_MSPDEINIT_CB_ID

USART MspDeInit callback ID

Definition at line 186 of file stm32g4xx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 93 of file stm32g4xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK1

PCLK1 clock source

USART_CLOCKSOURCE_PCLK2

PCLK2 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 108 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32g4xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | ClockPrescaler

Detailed Description

USART Init Structure definition.

Definition at line 46 of file stm32g4xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.

Note:
Oversampling by 8 is systematically applied to achieve high baud rates.

Definition at line 48 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 82 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 79 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 76 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of USART Clock Prescaler.

Definition at line 86 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 73 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 66 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 63 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 60 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_usart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32g4xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | SlaveMode
uint32_t | FifoMode
void(* | RxISR )(struct __USART_HandleTypeDef *husart)
void(* | TxISR )(struct __USART_HandleTypeDef *husart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxRxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | ErrorCallback )(struct __USART_HandleTypeDef *husart)
void(* | AbortCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxFifoFullCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxFifoEmptyCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspInitCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspDeInitCallback )(struct __USART_HandleTypeDef *husart)

Detailed Description

USART handle Structure definition.

Definition at line 121 of file stm32g4xx_hal_usart.h.

Field Documentation

void(* __USART_HandleTypeDef::AbortCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Abort Complete Callback

Definition at line 172 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort_IT(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::ErrorCallback)(struct __USART_HandleTypeDef *husart)

USART Error Callback

Definition at line 171 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

__IO uint32_t __USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 163 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

uint32_t __USART_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of USARTEx FIFO mode.

Definition at line 148 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_EnableFifoMode(), and USARTEx_SetNbDataToProcess().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 157 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 155 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef __USART_HandleTypeDef::Init

USART communication parameters

Definition at line 125 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

USART_TypeDef* __USART_HandleTypeDef::Instance

USART registers base address

Definition at line 123 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

HAL_LockTypeDef __USART_HandleTypeDef::Lock

Locking object

Definition at line 159 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t __USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 139 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::MspDeInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp DeInit callback

Definition at line 177 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

void(* __USART_HandleTypeDef::MspInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp Init callback

Definition at line 176 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

uint16_t __USART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 141 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), and USARTEx_SetNbDataToProcess().

uint16_t __USART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 143 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

uint8_t* __USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 133 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

const uint8_t* __USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 127 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Complete Callback

Definition at line 169 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxFifoFullCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Fifo Full Callback

Definition at line 173 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Half Complete Callback

Definition at line 168 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Rx IRQ handler

Definition at line 151 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), and USART_SetConfig().

__IO uint16_t __USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 137 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 135 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

uint32_t __USART_HandleTypeDef::SlaveMode

Enable/Disable USART SPI Slave Mode. This parameter can be a value of USARTEx Synchronous Slave mode enable

Definition at line 145 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO HAL_USART_StateTypeDef __USART_HandleTypeDef::State

USART communication state

Definition at line 161 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

void(* __USART_HandleTypeDef::TxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Complete Callback

Definition at line 167 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Fifo Empty Callback

Definition at line 174 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Half Complete Callback

Definition at line 166 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Tx IRQ handler

Definition at line 153 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), and USART_SetConfig().

void(* __USART_HandleTypeDef::TxRxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Rx Complete Callback

Definition at line 170 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO uint16_t __USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 131 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 129 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_usart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Error Definition

Defines
USART Error Definition
USART Exported Constants

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)
#define | HAL_USART_ERROR_UDR (0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | HAL_USART_ERROR_RTO (0x00000080U)

Define Documentation

#define HAL_USART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 227 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and USART_DMAError().

#define HAL_USART_ERROR_FE (0x00000004U)

Frame error

Definition at line 225 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 230 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

#define HAL_USART_ERROR_NE (0x00000002U)

Noise error

Definition at line 224 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE (0x00000000U)

No error

Definition at line 222 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 226 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE (0x00000001U)

Parity error

Definition at line 223 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_RTO (0x00000080U)

Receiver Timeout error

Definition at line 232 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_UDR (0x00000020U)

SPI slave underrun error

Definition at line 228 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define USART_STOPBITS_0_5 USART_CR2_STOP_0

USART frame with 0.5 stop bit

Definition at line 240 of file stm32g4xx_hal_usart.h.

#define USART_STOPBITS_1 0x00000000U

USART frame with 1 stop bit

Definition at line 241 of file stm32g4xx_hal_usart.h.

#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

USART frame with 1.5 stop bits

Definition at line 242 of file stm32g4xx_hal_usart.h.

#define USART_STOPBITS_2 USART_CR2_STOP_1

USART frame with 2 stop bits

Definition at line 243 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define USART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 252 of file stm32g4xx_hal_usart.h.

#define USART_PARITY_NONE 0x00000000U

No parity

Definition at line 251 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 253 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define USART_MODE_RX USART_CR1_RE

RX mode

Definition at line 261 of file stm32g4xx_hal_usart.h.

#define USART_MODE_TX USART_CR1_TE

TX mode

Definition at line 262 of file stm32g4xx_hal_usart.h.

#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 263 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define USART_CLOCK_DISABLE 0x00000000U

USART clock disable

Definition at line 271 of file stm32g4xx_hal_usart.h.

#define USART_CLOCK_ENABLE USART_CR2_CLKEN

USART clock enable

Definition at line 272 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define USART_POLARITY_HIGH USART_CR2_CPOL

Driver enable signal is active low

Definition at line 281 of file stm32g4xx_hal_usart.h.

#define USART_POLARITY_LOW 0x00000000U

Driver enable signal is active high

Definition at line 280 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define USART_PHASE_1EDGE 0x00000000U

USART frame phase on first clock transition

Definition at line 289 of file stm32g4xx_hal_usart.h.

#define USART_PHASE_2EDGE USART_CR2_CPHA

USART frame phase on second clock transition

Definition at line 290 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define USART_LASTBIT_DISABLE 0x00000000U

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 298 of file stm32g4xx_hal_usart.h.

#define USART_LASTBIT_ENABLE USART_CR2_LBCL

USART frame last data bit clock pulse output to SCLK pin

Definition at line 299 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Clock Prescaler

Defines
USART Clock Prescaler
USART Exported Constants

Defines

#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define USART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 307 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 312 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 313 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 317 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 314 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 308 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 318 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 315 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 309 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 310 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 316 of file stm32g4xx_hal_usart.h.

#define USART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 311 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 327 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 328 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_RTOF USART_ISR_RTOF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY USART_ISR_BUSY

USART busy flag

Definition at line 344 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_FE USART_ISR_FE

USART frame error

Definition at line 355 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_IDLE USART_ISR_IDLE

USART idle flag

Definition at line 352 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_NE USART_ISR_NE

USART noise error

Definition at line 354 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_ORE USART_ISR_ORE

USART overrun error

Definition at line 353 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_PE USART_ISR_PE

USART parity error

Definition at line 356 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_REACK USART_ISR_REACK

USART receive enable acknowledge flag

Definition at line 342 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_RTOF USART_ISR_RTOF

USART receiver timeout flag

Definition at line 348 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_RXFF USART_ISR_RXFF

USART RXFIFO Full flag

Definition at line 340 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

USART RXFIFO not empty

Definition at line 351 of file stm32g4xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_FLAG_RXFT USART_ISR_RXFT

USART RXFIFO threshold flag

Definition at line 339 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE

USART read data register not empty

Definition at line 350 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TC USART_ISR_TC

USART transmission complete

Definition at line 349 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit().

#define USART_FLAG_TEACK USART_ISR_TEACK

USART transmit enable acknowledge flag

Definition at line 343 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_TXE USART_ISR_TXE_TXFNF

USART transmit data register empty

Definition at line 346 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TXFE USART_ISR_TXFE

USART TXFIFO Empty flag

Definition at line 341 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF

USART TXFIFO not full

Definition at line 347 of file stm32g4xx_hal_usart.h.

Referenced by USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

#define USART_FLAG_TXFT USART_ISR_TXFT

USART TXFIFO threshold flag

Definition at line 338 of file stm32g4xx_hal_usart.h.

#define USART_FLAG_UDR USART_ISR_UDR

SPI slave underrun error flag

Definition at line 345 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR 0x0060U

USART error interruption

Definition at line 379 of file stm32g4xx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE 0x0100U

USART frame error interruption

Definition at line 382 of file stm32g4xx_hal_usart.h.

#define USART_IT_IDLE 0x0424U

USART idle interruption

Definition at line 378 of file stm32g4xx_hal_usart.h.

#define USART_IT_NE 0x0200U

USART noise error interruption

Definition at line 381 of file stm32g4xx_hal_usart.h.

#define USART_IT_ORE 0x0300U

USART overrun error interruption

Definition at line 380 of file stm32g4xx_hal_usart.h.

#define USART_IT_PE 0x0028U

USART parity error interruption

Definition at line 372 of file stm32g4xx_hal_usart.h.

#define USART_IT_RXFF 0x183FU

USART RXFIFO full interruption

Definition at line 383 of file stm32g4xx_hal_usart.h.

#define USART_IT_RXFNE 0x0525U

USART RXFIFO not empty interruption

Definition at line 377 of file stm32g4xx_hal_usart.h.

#define USART_IT_RXFT 0x1A7CU

USART RXFIFO threshold reached interruption

Definition at line 385 of file stm32g4xx_hal_usart.h.

#define USART_IT_RXNE 0x0525U

USART read data register not empty interruption

Definition at line 376 of file stm32g4xx_hal_usart.h.

#define USART_IT_TC 0x0626U

USART transmission complete interruption

Definition at line 375 of file stm32g4xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define USART_IT_TXE 0x0727U

USART transmit data register empty interruption

Definition at line 373 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT(), and USART_TxISR_8BIT().

#define USART_IT_TXFE 0x173EU

USART TXFIFO empty interruption

Definition at line 384 of file stm32g4xx_hal_usart.h.

#define USART_IT_TXFNF 0x0727U

USART TX FIFO not full interruption

Definition at line 374 of file stm32g4xx_hal_usart.h.

#define USART_IT_TXFT 0x1B77U

USART TXFIFO threshold reached interruption

Definition at line 386 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 396 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 399 of file stm32g4xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 397 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 398 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 395 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_RTOF USART_ICR_RTOCF

USART receiver timeout clear flag

Definition at line 403 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 400 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO Empty Clear Flag

Definition at line 402 of file stm32g4xx_hal_usart.h.

#define USART_CLEAR_UDRF USART_ICR_UDRCF

SPI slave underrun error Clear Flag

Definition at line 401 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U

Define Documentation

#define USART_CR_MASK 0x00E0U

USART control register mask

Definition at line 412 of file stm32g4xx_hal_usart.h.

#define USART_CR_POS 5U

USART control register position

Definition at line 413 of file stm32g4xx_hal_usart.h.

#define USART_ISR_MASK 0x1F00U

USART ISR register mask

Definition at line 414 of file stm32g4xx_hal_usart.h.

#define USART_ISR_POS 8U

USART ISR register position

Definition at line 415 of file stm32g4xx_hal_usart.h.

#define USART_IT_MASK 0x001FU

USART interruptions flags mask

Definition at line 411 of file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 497 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
  • USART_CLEAR_RTOF Receiver Timeout clear flag
  • USART_CLEAR_UDRF SPI slave underrun error Clear Flag
Return values:
None

Definition at line 485 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 515 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_RTOF Receiver timeout clear flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 646 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 503 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 509 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), and USART_EndTransmit_IT().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 491 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)

Clear the USART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 521 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_CLEAR_UDRFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)

Clear SPI slave underrun error flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 527 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 681 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
   ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
   ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 572 of file stm32g4xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 675 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Init(), and HAL_USARTEx_EnableSlaveMode().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
   ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
   ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 547 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__ specifies the USART Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXFT TXFIFO threshold flag
  • USART_FLAG_RXFT RXFIFO threshold flag
  • USART_FLAG_RXFF RXFIFO Full flag
  • USART_FLAG_TXFE TXFIFO Empty flag
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_UDR SPI slave underrun error flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TXFNF TXFIFO not full flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_RXFNE RXFIFO not empty flag
  • USART_FLAG_RTOF Receiver Timeout flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 468 of file stm32g4xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                         & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
                                                                      USART_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 599 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
                                                                 (__HANDLE__)->Instance->CR1 : \
                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
                                                                  (__HANDLE__)->Instance->CR2 : \
                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U <<\
                                                                      (((uint16_t)(__INTERRUPT__)) &\
                                                                       USART_IT_MASK)))  != 0U) ? SET : RESET)

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 623 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 669 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 663 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback = NULL;        \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
                                                      } while(0U)

Reset USART handle state.

Parameters:
__HANDLE__ USART handle.
Return values:
None

Definition at line 434 of file stm32g4xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__REQ__ specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 657 of file stm32g4xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 18750000U)

Check USART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 801 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__ USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 834 of file stm32g4xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 856 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__ USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 827 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__ USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 818 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__ USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 849 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__ USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 842 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))

Ensure that USART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ USART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 872 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__ USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 864 of file stm32g4xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__ USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 808 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
    + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | USART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | USART prescaler value.
Return values:
Division result

Definition at line 716 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)

Get USART clock division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ USART prescaler value.
Return values:
USART clock division factor

Definition at line 696 of file stm32g4xx_hal_usart.h.

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__ | specifies the USART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 725 of file stm32g4xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Private Constants

Defines
USARTEx Private Constants
USARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 61 of file stm32g4xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 64 of file stm32g4xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Private Functions

Functions
USARTEx Private Functions
USARTEx

Functions

static void USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void USARTEx_SetNbDataToProcess ( USART_HandleTypeDef * husart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
husart USART handle.
Return values:
None

Definition at line 499 of file stm32g4xx_hal_usart_ex.c.

References __USART_HandleTypeDef::FifoMode, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and USART_FIFOMODE_DISABLE.

Referenced by HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
USARTEx Exported Functions

Extended USART Transmit/Receive functions. More...

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.

Detailed Description

Extended USART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (+) HAL_USARTEx_RxFifoFullCallback()
        (+) HAL_USARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_USARTEx_RxFifoFullCallback ( USART_HandleTypeDef * husart )

USART RX Fifo full callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 109 of file stm32g4xx_hal_usart_ex.c.

References UNUSED.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void HAL_USARTEx_TxFifoEmptyCallback ( USART_HandleTypeDef * husart )

USART TX Fifo empty callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 124 of file stm32g4xx_hal_usart_ex.c.

References UNUSED.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
USARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_USARTEx_ConfigNSS | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | NSSConfig
 | ) |  |

Configure the Slave Select input pin (NSS).

Note:
Software NSS management: SPI slave will always be selected and NSS input pin will be ignored.
Hardware NSS management: the SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high.
Parameters:
husart USART handle.
NSSConfig NSS configuration. This parameter can be one of the following values:
  • USART_NSS_HARD
  • USART_NSS_SOFT
Return values:
HAL status

Definition at line 270 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_NSS, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode ( USART_HandleTypeDef * husart )

Disable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 349 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode ( USART_HandleTypeDef * husart )

Disable the SPI slave mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 222 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode ( USART_HandleTypeDef * husart )

Enable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 308 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_FIFOMODE_ENABLE, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode ( USART_HandleTypeDef * husart )

Enable the SPI slave mode.

Note:
When the USART operates in SPI slave mode, it handles data flow using the serial interface clock derived from the external SCLK signal provided by the external master SPI device.
In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it will become desynchronized with the master.
The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave will transmit zeros.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 174 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
husart USART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • USART_RXFIFO_THRESHOLD_1_8
  • USART_RXFIFO_THRESHOLD_1_4
  • USART_RXFIFO_THRESHOLD_1_2
  • USART_RXFIFO_THRESHOLD_3_4
  • USART_RXFIFO_THRESHOLD_7_8
  • USART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 444 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_RXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
husart USART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • USART_TXFIFO_THRESHOLD_1_8
  • USART_TXFIFO_THRESHOLD_1_4
  • USART_TXFIFO_THRESHOLD_1_2
  • USART_TXFIFO_THRESHOLD_3_4
  • USART_TXFIFO_THRESHOLD_7_8
  • USART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 395 of file stm32g4xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_TXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B (USART_CR1_M1)
#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B (USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B (USART_CR1_M1)

7-bit long USART frame

Definition at line 47 of file stm32g4xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B (0x00000000U)

8-bit long USART frame

Definition at line 48 of file stm32g4xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B (USART_CR1_M0)

9-bit long USART frame

Definition at line 49 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Slave Select Management

Defines
USARTEx Slave Select Management
USARTEx Exported Constants

Defines

#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS

Define Documentation

#define USART_NSS_HARD 0x00000000U

SPI slave selection depends on NSS input pin

Definition at line 57 of file stm32g4xx_hal_usart_ex.h.

#define USART_NSS_SOFT USART_CR2_DIS_NSS

SPI slave is always selected and NSS input pin is ignored

Definition at line 58 of file stm32g4xx_hal_usart_ex.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Synchronous Slave mode enable

Defines
USARTEx Synchronous Slave mode enable
USARTEx Exported Constants

USART SLAVE mode. More...

Defines

#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

Detailed Description

USART SLAVE mode.

Define Documentation

#define USART_SLAVEMODE_DISABLE 0x00000000U

USART SPI Slave Mode Enable

Definition at line 68 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USARTEx_DisableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

USART SPI Slave Mode Disable

Definition at line 69 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx FIFO mode

Defines
USARTEx FIFO mode
USARTEx Exported Constants

USART FIFO mode. More...

Defines

#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

USART FIFO mode.

Define Documentation

#define USART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 78 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_DisableFifoMode(), and USARTEx_SetNbDataToProcess().

#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 79 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), and HAL_USARTEx_EnableFifoMode().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx TXFIFO threshold level

Defines
USARTEx TXFIFO threshold level
USARTEx Exported Constants

USART TXFIFO level. More...

Defines

#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

USART TXFIFO level.

Define Documentation

#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 90 of file stm32g4xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 89 of file stm32g4xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 88 of file stm32g4xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 91 of file stm32g4xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 92 of file stm32g4xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 93 of file stm32g4xx_hal_usart_ex.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx RXFIFO threshold level

Defines
USARTEx RXFIFO threshold level
USARTEx Exported Constants

USART RXFIFO level. More...

Defines

#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

USART RXFIFO level.

Define Documentation

#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 104 of file stm32g4xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 103 of file stm32g4xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 102 of file stm32g4xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 105 of file stm32g4xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 106 of file stm32g4xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 107 of file stm32g4xx_hal_usart_ex.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Define Documentation

#define IS_USART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == USART_FIFOMODE_DISABLE ) || \
                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

Ensure that USART FIFO mode is valid.

Parameters:
__STATE__ USART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 201 of file stm32g4xx_hal_usart_ex.h.

#define IS_USART_NSS ( __NSS__ )
Value:
(((__NSS__) == USART_NSS_HARD) || \
                               ((__NSS__) == USART_NSS_SOFT))

Ensure that USART Negative Slave Select (NSS) pin management is valid.

Parameters:
__NSS__ USART Negative Slave Select pin management.
Return values:
SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

Definition at line 185 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_ConfigNSS().

#define IS_USART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

Ensure that USART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 221 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetRxFifoThreshold().

#define IS_USART_SLAVEMODE ( __STATE__ )
Value:
(((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

Ensure that USART Slave Mode is valid.

Parameters:
__STATE__ USART Slave Mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 193 of file stm32g4xx_hal_usart_ex.h.

#define IS_USART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

Ensure that USART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 209 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetTxFifoThreshold().

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__ USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 176 of file stm32g4xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 130 of file stm32g4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 175 of file stm32g4xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::EwiCallback, WWDG_InitTypeDef::EWIMode, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_MspInit(), __WWDG_HandleTypeDef::Init, __WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, __WWDG_HandleTypeDef::MspInitCallback, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 229 of file stm32g4xx_hal_wwdg.c.

References UNUSED.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_UnRegisterCallback().

HAL_StatusTypeDef HAL_WWDG_RegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID,
 |  | pWWDG_CallbackTypeDef | pCallback
 | ) |  |

Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hwwdg | WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 252 of file stm32g4xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EWI_CB_ID, HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hwwdg WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
Return values:
status

Definition at line 293 of file stm32g4xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_EWI_CB_ID, HAL_WWDG_MspInit(), HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 394 of file stm32g4xx_hal_wwdg.c.

References UNUSED.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), and HAL_WWDG_UnRegisterCallback().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 365 of file stm32g4xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 342 of file stm32g4xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::Init, and __WWDG_HandleTypeDef::Instance.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Types

Data Structures | Typedefs | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00U, HAL_WWDG_MSPINIT_CB_ID = 0x01U }
HAL WWDG common Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp)

HAL WWDG Callback pointer definition.

pointer to a WWDG common callback functions

Definition at line 96 of file stm32g4xx_hal_wwdg.h.

typedef struct __WWDG_HandleTypeDef WWDG_HandleTypeDef

WWDG handle Structure definition.

Enumeration Type Documentation

enum HAL_WWDG_CallbackIDTypeDef

HAL WWDG common Callback ID enumeration definition.

Enumerator:
HAL_WWDG_EWI_CB_ID

WWDG EWI callback ID

HAL_WWDG_MSPINIT_CB_ID

WWDG MspInit callback ID

Definition at line 87 of file stm32g4xx_hal_wwdg.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32g4xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 47 of file stm32g4xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 55 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 58 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 49 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 52 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: __WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32g4xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
void(* | EwiCallback )(struct __WWDG_HandleTypeDef *hwwdg)
void(* | MspInitCallback )(struct __WWDG_HandleTypeDef *hwwdg)

Detailed Description

WWDG handle Structure definition.

Definition at line 67 of file stm32g4xx_hal_wwdg.h.

Field Documentation

void(* __WWDG_HandleTypeDef::EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Early WakeUp Interrupt callback

Definition at line 77 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

WWDG_InitTypeDef __WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 74 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* __WWDG_HandleTypeDef::Instance

Register base address

Definition at line 72 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

void(* __WWDG_HandleTypeDef::MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Msp Init callback

Definition at line 79 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 112 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 121 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 129 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/128

Definition at line 136 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 133 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 130 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 134 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 131 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 135 of file stm32g4xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 132 of file stm32g4xx_hal_wwdg.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 144 of file stm32g4xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 145 of file stm32g4xx_hal_wwdg.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 170 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 172 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

Definition at line 159 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 168 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 240 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 220 of file stm32g4xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 190 of file stm32g4xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 201 of file stm32g4xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 230 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 211 of file stm32g4xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CFR\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 249 of file stm32g4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRYP

CRYP
STM32G4xx_HAL_Driver
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRYPEx

CRYPEx
STM32G4xx_HAL_Driver
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
OPAMP Extended Exported Functions

Functions

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3)

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2,
 |  | OPAMP_HandleTypeDef * | hopamp3
 | ) |  |
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
#define | ADC_CHANNEL_ID_MASK
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
#define | ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
#define | ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
#define | ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_15_NUMBER
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS
#define | ADC_AWD_TRX_BIT_HIGH_MASK
#define | ADC_AWD_TRX_BIT_HIGH_POS
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK
#define | ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define | ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
#define | ADC_CR_BITS_PROPERTY_RS
#define | VREFINT_CAL_ADDR
#define | VREFINT_CAL_VREF
#define | TEMPSENSOR_CAL1_ADDR
#define | TEMPSENSOR_CAL2_ADDR
#define | TEMPSENSOR_CAL1_TEMP
#define | TEMPSENSOR_CAL2_TEMP
#define | TEMPSENSOR_CAL_VREFANALOG

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 302 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)

Definition at line 303 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 307 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)

Definition at line 296 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 308 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)

Definition at line 297 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)

Definition at line 298 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 309 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 305 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_POS
Value:
(20UL)                      /* Position of bits ADC_AWD_CRx_REGOFFSET
                                                                          in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 311 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 314 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 315 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 316 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_MASK
Value:
(0x00010000UL)                   /* Selection of 1 bit to discriminate
                                                                               threshold high: mask of bit */

Definition at line 319 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds().

#define ADC_AWD_TRX_BIT_HIGH_POS
Value:
(16UL)                           /* Selection of 1 bit to discriminate
                                                                               threshold high: position of bit */

Definition at line 320 of file stm32g4xx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_SHIFT4
Value:
(ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
                                                                               position to perform a shift of 4 ranks */

Definition at line 321 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 317 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAWDFilteringConfiguration().

#define ADC_AWD_TRX_REGOFFSET_POS
Value:
(ADC_AWD_CRX_REGOFFSET_POS)      /* Position of bits ADC_SQRx_REGOFFSET
                                                                               in ADC_AWD_TRX_REGOFFSET_MASK */

Definition at line 318 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAWDFilteringConfiguration().

#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)

Definition at line 336 of file stm32g4xx_ll_adc.h.

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)

Definition at line 335 of file stm32g4xx_ll_adc.h.

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)

Definition at line 337 of file stm32g4xx_ll_adc.h.

#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)

Definition at line 334 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 227 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER (0x00000000UL)

Definition at line 204 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 251 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)

Definition at line 237 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)

Definition at line 214 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 261 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)

Definition at line 238 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 215 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 262 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)

Definition at line 239 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)

Definition at line 216 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 263 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)

Definition at line 240 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 217 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 264 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)

Definition at line 241 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)

Definition at line 218 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 265 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)

Definition at line 242 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER
Value:
(ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 219 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 266 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)

Definition at line 243 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)

Definition at line 221 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 267 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)

Definition at line 244 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)

Definition at line 222 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 268 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)

Definition at line 245 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)

Definition at line 223 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 269 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 228 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)

Definition at line 205 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 252 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 229 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)

Definition at line 206 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 253 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 230 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 207 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 254 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 231 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)

Definition at line 208 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 255 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 232 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 209 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 256 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)

Definition at line 233 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)

Definition at line 210 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 257 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)

Definition at line 234 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 211 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 258 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)

Definition at line 235 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)

Definition at line 212 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 259 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)

Definition at line 236 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)

Definition at line 213 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))

Definition at line 260 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 180 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */

Definition at line 188 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2
Value:
(0x00080000UL) /* Marker of internal channel for other ADC instances, in case
                                                             of different ADC internal channels mapped on same channel
                                                             number on different ADC instances */

Definition at line 189 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 190 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK
Value:
(ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
                                            | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 182 of file stm32g4xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)

Definition at line 181 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetContinuousMode(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)

Definition at line 179 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetOffset().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
Value:
(ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
  >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

Definition at line 185 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetContinuousMode(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 196 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)

Definition at line 199 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS
Value:
(20UL)           /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
                                                               position in register */

Definition at line 200 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)

Definition at line 68 of file stm32g4xx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS
Value:
(ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
                                            | ADC_CR_JADSTART | ADC_CR_JADSTP \
                                            | ADC_CR_ADSTART | ADC_CR_ADSTP)            /* ADC register CR bits with
                                           HW property "rs": Software can read as well as set this bit.
                                           Writing '0' has no effect on the bit value. */

Definition at line 342 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_INJ_IsStopConversionOngoing(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsStopConversionOngoing(), LL_ADC_REG_StartConversion(), and LL_ADC_REG_StartSamplingPhase().

#define ADC_INJ_JDRX_REGOFFSET_MASK
Value:
(ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
                                            | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 98 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)

Definition at line 105 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)

Definition at line 106 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)

Definition at line 107 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)

Definition at line 108 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 100 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetTrigAuto(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_INJ_TRIG_EDGE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 157 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT
Value:
(ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
                                                                  compatibility with some ADC on other STM32 series
                                                                  having this setting set by HW default value) */

Definition at line 144 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)

Definition at line 164 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_SetTriggerEdge().

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)

Definition at line 163 of file stm32g4xx_ll_adc.h.

#define ADC_INJ_TRIG_SOURCE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

Definition at line 149 of file stm32g4xx_ll_adc.h.

#define ADC_JDR1_REGOFFSET (0x00000000UL)

Definition at line 93 of file stm32g4xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET (0x00000100UL)

Definition at line 94 of file stm32g4xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET (0x00000200UL)

Definition at line 95 of file stm32g4xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET (0x00000300UL)

Definition at line 96 of file stm32g4xx_ll_adc.h.

#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/

Definition at line 101 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_EOS().

#define ADC_OFR1_REGOFFSET (0x00000000UL)

Definition at line 325 of file stm32g4xx_ll_adc.h.

#define ADC_OFR2_REGOFFSET (0x00000001UL)

Definition at line 326 of file stm32g4xx_ll_adc.h.

#define ADC_OFR3_REGOFFSET (0x00000002UL)

Definition at line 327 of file stm32g4xx_ll_adc.h.

#define ADC_OFR4_REGOFFSET (0x00000003UL)

Definition at line 328 of file stm32g4xx_ll_adc.h.

#define ADC_OFRx_REGOFFSET_MASK
Value:
(ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
                                            | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

Definition at line 329 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)

Definition at line 76 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)

Definition at line 77 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)

Definition at line 78 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)

Definition at line 79 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)

Definition at line 80 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)

Definition at line 81 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)

Definition at line 82 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)

Definition at line 67 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)

Definition at line 68 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)

Definition at line 69 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)

Definition at line 70 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)

Definition at line 71 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)

Definition at line 72 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)

Definition at line 73 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)

Definition at line 74 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)

Definition at line 75 of file stm32g4xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 63 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetContinuousMode(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK
Value:
(ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
                                            | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 60 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetContinuousMode(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

Definition at line 129 of file stm32g4xx_ll_adc.h.

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT
Value:
(ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
                                                                 compatibility with some ADC on other STM32 series
                                                                 having this setting set by HW default value) */

Definition at line 116 of file stm32g4xx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)

Definition at line 136 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_SetTriggerEdge().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)

Definition at line 135 of file stm32g4xx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
                                            ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
                                            ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
                                            ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

Definition at line 121 of file stm32g4xx_ll_adc.h.

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK
Value:
(0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
                                           mask of bit */

Definition at line 282 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetResolution().

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS
Value:
(16UL)         /* Selection of 1 bit to discriminate differential mode:
                                           position of bit */

Definition at line 283 of file stm32g4xx_ll_adc.h.

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4
Value:
(ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
                                           ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */

Definition at line 284 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetResolution().

#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

Definition at line 279 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetResolution().

#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)

Definition at line 278 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_StartConversion().

#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

Definition at line 280 of file stm32g4xx_ll_adc.h.

#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK
Value:
(ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
                                           to perform of shift when single mode is selected, shift value out of
                                           channels bits range. */

Definition at line 281 of file stm32g4xx_ll_adc.h.

#define ADC_SMPR1_REGOFFSET (0x00000000UL)

Definition at line 194 of file stm32g4xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET (0x02000000UL)

Definition at line 195 of file stm32g4xx_ll_adc.h.

#define ADC_SMPRX_REGOFFSET_POS
Value:
(25UL)           /* Position of bits ADC_SMPRx_REGOFFSET
                                                               in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

Definition at line 197 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_SQR1_REGOFFSET (0x00000000UL)

Definition at line 55 of file stm32g4xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET (0x00000100UL)

Definition at line 56 of file stm32g4xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET (0x00000200UL)

Definition at line 57 of file stm32g4xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET (0x00000300UL)

Definition at line 58 of file stm32g4xx_ll_adc.h.

#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/

Definition at line 62 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetContinuousMode(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 69 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 70 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)

Definition at line 338 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds().

#define TEMPSENSOR_CAL1_ADDR
Value:
((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
                                           temperature sensor ADC raw data acquired at temperature  30 DegC
                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 352 of file stm32g4xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP
Value:
(30L)                        /* Temperature at which temperature sensor
                                           has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
                                           (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 354 of file stm32g4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR
Value:
((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
                                           temperature sensor ADC raw data acquired at temperature 110 DegC
                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 353 of file stm32g4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP
Value:
(110L)                       /* Temperature at which temperature sensor
                                           has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
                                           (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 355 of file stm32g4xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG
Value:
(3000UL)                     /* Analog voltage reference (Vref+) value
                                           with which temperature sensor has been calibrated in production
                                           (tolerance +-10 mV) (unit: mV). */

Definition at line 356 of file stm32g4xx_ll_adc.h.

#define VREFINT_CAL_ADDR
Value:
((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
                                           parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 349 of file stm32g4xx_ll_adc.h.

#define VREFINT_CAL_VREF
Value:
(3000UL)                     /* Analog voltage reference (Vref+) value
                                           with which VrefInt has been calibrated in production
                                           (tolerance: +-10 mV) (unit: mV). */

Definition at line 350 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 376 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_GetGainCompensation(), LL_ADC_GetOffsetLevel(), LL_ADC_GetOffsetState(), LL_ADC_IsActiveFlag_EOS(), LL_ADC_REG_GetContinuousMode(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAWDFilteringConfiguration(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetGainCompensation(), LL_ADC_SetOffset(), and LL_ADC_SetOffsetState().

#define IS_LL_ADC_COMMON_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
  )

Definition at line 84 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
  )

Definition at line 111 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
  )

Definition at line 576 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
  )

Definition at line 569 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
  )

Definition at line 564 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_EXT_EDGE ( __INJ_TRIG_EXT_EDGE__ )
Value:
(((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
  )

Definition at line 558 of file stm32g4xx_ll_adc.c.

#define IS_LL_ADC_INJ_TRIG_SOURCE | ( | __ADC_INSTANCE__,
 |  | __INJ_TRIG_SOURCE__
 | ) |
Value:
(((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
  )

Definition at line 494 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_LOW_POWER ( __LOW_POWER__ )
Value:
(((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
  )

Definition at line 116 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_MULTI_DMA_TRANSFER ( __MULTI_DMA_TRANSFER__ )
Value:
(((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)                 \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
  )

Definition at line 595 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_MASTER_SLAVE ( __MULTI_MASTER_SLAVE__ )
Value:
(((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
  )

Definition at line 618 of file stm32g4xx_ll_adc.c.

#define IS_LL_ADC_MULTI_MODE ( __MULTI_MODE__ )
Value:
(((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
  )

Definition at line 584 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_TWOSMP_DELAY ( __MULTI_TWOSMP_DELAY__ )
Value:
(((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)              \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
  )

Definition at line 603 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 318 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
  )

Definition at line 323 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR ( __REG_OVR_DATA_BEHAVIOR__ )
Value:
(((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
  )

Definition at line 329 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
  )

Definition at line 353 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
  )

Definition at line 334 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE | ( | __ADC_INSTANCE__,
 |  | __REG_TRIG_SOURCE__
 | ) |
Value:
(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
  )

Definition at line 254 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
  )

Definition at line 104 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_Init().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32g4xx_ll_adc.h>

Data Fields

uint32_t | CommonClock
uint32_t | Multimode
uint32_t | MultiDMATransfer
uint32_t | MultiTwoSamplingDelay

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 400 of file stm32g4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::CommonClock

Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of ADC common - Clock source

Note:
On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. This feature can be modified afterwards using unitary function LL_ADC_SetCommonClock().

Definition at line 402 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiDMATransfer

Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of Multimode - DMA transfer This feature can be modified afterwards using unitary function LL_ADC_SetMultiDMATransfer().

Definition at line 417 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::Multimode

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of Multimode - Mode This feature can be modified afterwards using unitary function LL_ADC_SetMultimode().

Definition at line 411 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay

Set ADC multimode delay between 2 sampling phases. This parameter can be a value of Multimode - Delay between two sampling phases This feature can be modified afterwards using unitary function LL_ADC_SetMultiTwoSamplingDelay().

Definition at line 422 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32g4xx_ll_adc.h>

Data Fields

uint32_t | Resolution
uint32_t | DataAlignment
uint32_t | LowPowerMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 series). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 450 of file stm32g4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 457 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::LowPowerMode

Set ADC low power mode. This parameter can be a value of ADC instance - Low power mode This feature can be modified afterwards using unitary function LL_ADC_SetLowPowerMode().

Definition at line 462 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::Resolution

Set ADC resolution. This parameter can be a value of ADC instance - Resolution This feature can be modified afterwards using unitary function LL_ADC_SetResolution().

Definition at line 452 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32g4xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer
uint32_t | Overrun

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 488 of file stm32g4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 515 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer of ADC conversion data This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 525 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::Overrun

Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of ADC group regular - Overrun behavior on conversion data This feature can be modified afterwards using unitary function LL_ADC_REG_SetOverrun().

Definition at line 531 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 507 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 502 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge(default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge(). This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 490 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32g4xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 558 of file stm32g4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 577 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 572 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 585 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge(). This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 560 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag ADC instance ready

Definition at line 609 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOSMP(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOSMP().

#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST

ADC flag ADC multimode master instance ready

Definition at line 626 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOS().

#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV

ADC flag ADC multimode slave instance ready

Definition at line 627 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOS().

#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag ADC analog watchdog 1

Definition at line 622 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOC(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_SLV_ADRDY().

#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST

ADC flag ADC multimode master analog watchdog 1 of the ADC master

Definition at line 656 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD3().

#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV

ADC flag ADC multimode slave analog watchdog 1 of the ADC slave

Definition at line 658 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD3().

#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag ADC analog watchdog 2

Definition at line 623 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_MST_EOC().

#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST

ADC flag ADC multimode master analog watchdog 2 of the ADC master

Definition at line 660 of file stm32g4xx_ll_adc.h.

#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV

ADC flag ADC multimode slave analog watchdog 2 of the ADC slave

Definition at line 662 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_EnableIT_ADRDY().

#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag ADC analog watchdog 3

Definition at line 624 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_OVR(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_SLV_EOC().

#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST

ADC flag ADC multimode master analog watchdog 3 of the ADC master

Definition at line 664 of file stm32g4xx_ll_adc.h.

#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

ADC flag ADC multimode slave analog watchdog 3 of the ADC slave

Definition at line 666 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_EnableIT_OVR().

#define LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag ADC group regular end of unitary conversion

Definition at line 610 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST

ADC flag ADC multimode master group regular end of unitary conversion

Definition at line 628 of file stm32g4xx_ll_adc.h.

#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV

ADC flag ADC multimode slave group regular end of unitary conversion

Definition at line 630 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_OVR(), and LL_ADC_IsActiveFlag_SLV_OVR().

#define LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag ADC group regular end of sequence conversions

Definition at line 612 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST

ADC flag ADC multimode master group regular end of sequence conversions

Definition at line 632 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOSMP().

#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV

ADC flag ADC multimode slave group regular end of sequence conversions

Definition at line 634 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOSMP().

#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag ADC group regular end of sampling phase

Definition at line 615 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST

ADC flag ADC multimode master group regular end of sampling phase

Definition at line 640 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOS().

#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV

ADC flag ADC multimode slave group regular end of sampling phase

Definition at line 642 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOS().

#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC

ADC flag ADC group injected end of unitary conversion

Definition at line 616 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST

ADC flag ADC multimode master group injected end of unitary conversion

Definition at line 644 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JQOVF().

#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV

ADC flag ADC multimode slave group injected end of unitary conversion

Definition at line 646 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JQOVF().

#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS

ADC flag ADC group injected end of sequence conversions

Definition at line 618 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST

ADC flag ADC multimode master group injected end of sequence conversions

Definition at line 648 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD1().

#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV

ADC flag ADC multimode slave group injected end of sequence conversions

Definition at line 650 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD1().

#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC flag ADC group injected contexts queue overflow

Definition at line 620 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_ADRDY(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_MST_ADRDY().

#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST

ADC flag ADC multimode master group injected contexts queue overflow

Definition at line 652 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD2().

#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV

ADC flag ADC multimode slave group injected contexts queue overflow

Definition at line 654 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD2().

#define LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag ADC group regular overrun

Definition at line 614 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST

ADC flag ADC multimode master group regular overrun

Definition at line 636 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOC().

#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV

ADC flag ADC multimode slave group regular overrun

Definition at line 638 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOC().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption ADC instance ready

Definition at line 677 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_EnableIT_EOSMP(), and LL_ADC_IsEnabledIT_EOSMP().

#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption ADC analog watchdog 1

Definition at line 691 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_EOC().

#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption ADC analog watchdog 2

Definition at line 692 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption ADC analog watchdog 3

Definition at line 693 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_OVR().

#define LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption ADC group regular end of unitary conversion

Definition at line 678 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_JEOC().

#define LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption ADC group regular end of sequence conversions

Definition at line 680 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_JEOS().

#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption ADC group regular end of sampling phase

Definition at line 683 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_JEOC ADC_IER_JEOCIE

ADC interruption ADC group injected end of unitary conversion

Definition at line 685 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_AWD2().

#define LL_ADC_IT_JEOS ADC_IER_JEOSIE

ADC interruption ADC group injected end of sequence conversions

Definition at line 687 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_AWD3().

#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC interruption ADC group injected contexts queue overflow

Definition at line 689 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_ADRDY().

#define LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption ADC group regular overrun

Definition at line 682 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), and LL_ADC_IsEnabledIT_JQOVF().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define | LL_ADC_DMA_REG_REGULAR_DATA
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA
Value:
(0x00000000UL)      /* ADC group regular conversion data register
                                           (corresponding to register DR) to be used with ADC configured in independent
                                           mode. Without DMA transfer, register accessed by LL function
                                           @ref LL_ADC_REG_ReadConversionData32() and other
                                           functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 704 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DMA_GetRegAddr().

#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI
Value:
(0x00000001UL)      /* ADC group regular conversion data register
                                           (corresponding to register CDR) to be used with ADC configured in multimode
                                           (available on STM32 devices with several ADC instances).
                                           Without DMA transfer, register accessed by LL function
                                           @ref LL_ADC_REG_ReadMultiConversionData32() */

Definition at line 706 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV16
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256

Define Documentation

#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)

ADC asynchronous clock without prescaler

Definition at line 721 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10

Definition at line 731 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 12

Definition at line 733 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128

Definition at line 742 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV16
Value:
(ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
                                            | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 16

Definition at line 735 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2

Definition at line 723 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV256
Value:
(ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
                                            | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 256

Definition at line 744 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32

Definition at line 738 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 4

Definition at line 725 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6

Definition at line 727 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64

Definition at line 740 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)

ADC asynchronous clock with prescaler division by 8

Definition at line 729 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 715 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1)

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 717 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 719 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)

ADC measurement paths all disabled

Definition at line 759 of file stm32g4xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL)

ADC measurement path to internal channel temperature sensor

Definition at line 761 of file stm32g4xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL)

ADC measurement path to internal channel Vbat

Definition at line 763 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

Definition at line 760 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

Define Documentation

#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)

ADC resolution 10 bits

Definition at line 772 of file stm32g4xx_ll_adc.h.

#define LL_ADC_RESOLUTION_12B (0x00000000UL)

ADC resolution 12 bits

Definition at line 771 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

ADC resolution 6 bits

Definition at line 774 of file stm32g4xx_ll_adc.h.

#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )

ADC resolution 8 bits

Definition at line 773 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)

Definition at line 784 of file stm32g4xx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 782 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Low power mode

Defines
ADC instance - Low power mode
ADC Exported Constants

Defines

#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

Define Documentation

#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode().

Definition at line 794 of file stm32g4xx_ll_adc.h.

#define LL_ADC_LP_MODE_NONE (0x00000000UL)

No ADC low power mode activated

Definition at line 793 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Offset instance

Defines
ADC instance - Offset instance
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

Define Documentation

#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET

ADC offset instance 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected)

Definition at line 805 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET

ADC offset instance 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected)

Definition at line 808 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET

ADC offset instance 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected)

Definition at line 811 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

ADC offset instance 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected)

Definition at line 814 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Offset state

Defines
ADC instance - Offset state
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

Define Documentation

#define LL_ADC_OFFSET_DISABLE (0x00000000UL)

ADC offset disabled (setting offset instance wise)

Definition at line 824 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

ADC offset enabled (setting offset instance wise)

Definition at line 826 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Offset sign

Defines
ADC instance - Offset sign
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
#define | LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)

Define Documentation

#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)

ADC offset is negative

Definition at line 835 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)

ADC offset is positive

Definition at line 836 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Offset saturation mode

Defines
ADC instance - Offset saturation mode
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN)

Define Documentation

#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL)

ADC offset saturation is disabled (among ADC selected offset instance 1, 2, 3 or 4)

Definition at line 844 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN)

ADC offset saturation is enabled (among ADC selected offset instance 1, 2, 3 or 4)

Definition at line 846 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

Define Documentation

#define LL_ADC_GROUP_INJECTED (0x00000002UL)

ADC group injected (not available on all STM32 devices)

Definition at line 855 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR (0x00000001UL)

ADC group regular (available on all STM32 devices)

Definition at line 854 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

ADC both groups regular and injected

Definition at line 857 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0
#define | LL_ADC_CHANNEL_1
#define | LL_ADC_CHANNEL_2
#define | LL_ADC_CHANNEL_3
#define | LL_ADC_CHANNEL_4
#define | LL_ADC_CHANNEL_5
#define | LL_ADC_CHANNEL_6
#define | LL_ADC_CHANNEL_7
#define | LL_ADC_CHANNEL_8
#define | LL_ADC_CHANNEL_9
#define | LL_ADC_CHANNEL_10
#define | LL_ADC_CHANNEL_11
#define | LL_ADC_CHANNEL_12
#define | LL_ADC_CHANNEL_13
#define | LL_ADC_CHANNEL_14
#define | LL_ADC_CHANNEL_15
#define | LL_ADC_CHANNEL_16
#define | LL_ADC_CHANNEL_17
#define | LL_ADC_CHANNEL_18
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP2
#define | LL_ADC_CHANNEL_VOPAMP3_ADC2
#define | LL_ADC_CHANNEL_VOPAMP3_ADC3
#define | LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP6

Define Documentation

#define LL_ADC_CHANNEL_0
Value:
(ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP \
                                            | ADC_CHANNEL_0_BITFIELD)

ADC channel ADCx_IN0

Definition at line 865 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_1
Value:
(ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP \
                                            | ADC_CHANNEL_1_BITFIELD)

ADC channel ADCx_IN1

Definition at line 867 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_10
Value:
(ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
                                            | ADC_CHANNEL_10_BITFIELD)

ADC channel ADCx_IN10

Definition at line 885 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_11
Value:
(ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
                                            | ADC_CHANNEL_11_BITFIELD)

ADC channel ADCx_IN11

Definition at line 887 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_12
Value:
(ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
                                            | ADC_CHANNEL_12_BITFIELD)

ADC channel ADCx_IN12

Definition at line 889 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_13
Value:
(ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
                                            | ADC_CHANNEL_13_BITFIELD)

ADC channel ADCx_IN13

Definition at line 891 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_14
Value:
(ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
                                            | ADC_CHANNEL_14_BITFIELD)

ADC channel ADCx_IN14

Definition at line 893 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_15
Value:
(ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
                                            | ADC_CHANNEL_15_BITFIELD)

ADC channel ADCx_IN15

Definition at line 895 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_16
Value:
(ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
                                           ADC_CHANNEL_16_BITFIELD)

ADC channel ADCx_IN16

Definition at line 897 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_17
Value:
(ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
                                           ADC_CHANNEL_17_BITFIELD)

ADC channel ADCx_IN17

Definition at line 899 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_18
Value:
(ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
                                           ADC_CHANNEL_18_BITFIELD)

ADC channel ADCx_IN18

Definition at line 901 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_2
Value:
(ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP \
                                            | ADC_CHANNEL_2_BITFIELD)

ADC channel ADCx_IN2

Definition at line 869 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_3
Value:
(ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP \
                                            | ADC_CHANNEL_3_BITFIELD)

ADC channel ADCx_IN3

Definition at line 871 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_4
Value:
(ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP \
                                            | ADC_CHANNEL_4_BITFIELD)

ADC channel ADCx_IN4

Definition at line 873 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_5
Value:
(ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP \
                                            | ADC_CHANNEL_5_BITFIELD)

ADC channel ADCx_IN5

Definition at line 875 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_6
Value:
(ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP \
                                            | ADC_CHANNEL_6_BITFIELD)

ADC channel ADCx_IN6

Definition at line 877 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_7
Value:
(ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP \
                                            | ADC_CHANNEL_7_BITFIELD)

ADC channel ADCx_IN7

Definition at line 879 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_8
Value:
(ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP \
                                            | ADC_CHANNEL_8_BITFIELD)

ADC channel ADCx_IN8

Definition at line 881 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_9
Value:
(ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP \
                                            | ADC_CHANNEL_9_BITFIELD)

ADC channel ADCx_IN9

Definition at line 883 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to internal temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance.

Definition at line 906 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to internal temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility

Definition at line 909 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility

Definition at line 913 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance.

Definition at line 918 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP2
Value:
(LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
                                           ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance.

Definition at line 921 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP3_ADC2
Value:
(LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
                                           ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance.

Definition at line 924 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP3_ADC3
Value:
(LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
                                           ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability

Definition at line 927 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability

Definition at line 931 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability

Definition at line 934 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VOPAMP6
Value:
(LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
                                           ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability

Definition at line 937 of file stm32g4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2.

Definition at line 903 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM7_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH2
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH3
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG2
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG4
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE2
#define | LL_ADC_REG_TRIG_EXT_LPTIM_OUT

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11
Value:
(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1159 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2
Value:
(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1165 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1095 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1153 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1101 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1108 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1114 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1121 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1128 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1134 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1140 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1146 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting).

Definition at line 1171 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1057 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 959 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 965 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 971 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 951 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 955 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM20_CH1
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1072 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM20_CH2
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1079 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM20_CH3
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1087 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1061 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1066 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH1
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 979 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2
Value:
(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 987 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 994 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 975 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1003 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_CH4
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1009 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1000 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH1
Value:
(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1021 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH4
Value:
(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1028 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1017 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO
Value:
(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1035 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO
Value:
(ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
                                           ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1039 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_CH1
Value:
(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1050 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO
Value:
(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1043 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 1047 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)

ADC group regular conversion trigger internal: SW start.

Definition at line 949 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1)
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1)

ADC group regular conversion trigger polarity set to falling edge

Definition at line 1185 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 1183 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 1187 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Sampling mode

Defines
ADC group regular - Sampling mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL)
#define | LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)
#define | LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)

Define Documentation

#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)

ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see Channel - Sampling time)

Definition at line 1198 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL)

ADC conversions sampling phase duration is defined using Channel - Sampling time

Definition at line 1196 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)

ADC conversions sampling phase is controlled by trigger events: trigger rising edge for start sampling, trigger falling edge for stop sampling and start conversion

Definition at line 1202 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

ADC conversions performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 1214 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)

ADC conversions performed in single mode: one conversion per trigger

Definition at line 1212 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - DMA transfer of ADC conversion data

Defines
ADC group regular - DMA transfer of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

Definition at line 1225 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)

ADC conversions are not transferred by DMA

Definition at line 1224 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 1229 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC instance - ADC sampling time common configuration

Defines
ADC instance - ADC sampling time common configuration
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS)

Define Documentation

#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS)

ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected).

Definition at line 1242 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL)

ADC sampling time let to default settings.

Definition at line 1241 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

Define Documentation

#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 1256 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)

ADC group regular behavior in case of overrun: data preserved

Definition at line 1254 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 1265 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 1284 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 1286 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
Value:
(ADC_SQR1_L_3 | ADC_SQR1_L_1 \
                                            | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 1288 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 1291 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
Value:
(ADC_SQR1_L_3 | ADC_SQR1_L_2 \
                                            | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 1293 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
Value:
(ADC_SQR1_L_3 | ADC_SQR1_L_2 \
                                            | ADC_SQR1_L_1)

ADC group regular sequencerenable with 15 ranks in the sequence

Definition at line 1296 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Value:
(ADC_SQR1_L_3 | ADC_SQR1_L_2 \
                                            | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 1299 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 1267 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1)

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 1269 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 1271 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2)

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 1273 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 1275 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1)

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 1277 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
Value:
(ADC_SQR1_L_2 | ADC_SQR1_L_1 \
                                            | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 1279 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3)

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 1282 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 1311 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 1313 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 1315 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS
Value:
(ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
                                            | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 1317 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 1320 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS
Value:
(ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
                                            | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 1322 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS
Value:
(ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
                                            | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 1325 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS
Value:
(ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
                                            | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 1328 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group regular sequencer discontinuous mode disable

Definition at line 1309 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 1338 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 1356 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 1358 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 1360 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 1362 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 1364 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 1366 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 1368 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 1340 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 1342 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 1344 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 1346 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 1348 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 1350 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 1352 of file stm32g4xx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 1354 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH3
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_CH4
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH2
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM16_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
#define | LL_ADC_INJ_TRIG_EXT_TIM20_CH2
#define | LL_ADC_INJ_TRIG_EXT_TIM20_CH4
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE3
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
#define | LL_ADC_INJ_TRIG_EXT_LPTIM_OUT

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
Value:
(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances.

Definition at line 1579 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1573 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1511 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices.Refer to device datasheet for more details

Definition at line 1567 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1518 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1524 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1531 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1537 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1543 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1549 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1555 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details

Definition at line 1561 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting).

Definition at line 1585 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1475 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1479 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1385 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1392 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1379 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 1382 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1497 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1504 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1486 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 1491 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1
Value:
(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1399 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1396 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1410 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1417 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances

Definition at line 1424 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1406 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1434 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4
Value:
(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1440 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
Value:
(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1430 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1447 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
Value:
(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
                                           ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1451 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2
Value:
(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility

Definition at line 1463 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4
Value:
(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 1470 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 1455 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
Value:
(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 1459 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)

ADC group injected conversion trigger internal: SW start.

Definition at line 1377 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), and LL_ADC_INJ_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )

ADC group injected conversion trigger polarity set to falling edge

Definition at line 1598 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to rising edge

Definition at line 1596 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to both rising and falling edges

Definition at line 1600 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 1612 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 1609 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and LL_ADC_INJ_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Context queue mode

Defines
ADC group injected - Context queue mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
#define | LL_ADC_INJ_QUEUE_DISABLE

Define Documentation

#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
Value:
(ADC_CFGR_JQM)   /* Group injected sequence context queue is enabled
                                           and can contain up to 2 contexts. When all contexts have been processed,
                                           the queue is empty and injected group triggers are disabled. */

Definition at line 1625 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
Value:
(0x00000000UL)   /* Group injected sequence context queue is enabled
                                           and can contain up to 2 contexts. When all contexts have been processed,
                                           the queue maintains the last context active perpetually. */

Definition at line 1624 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_QUEUE_DISABLE
Value:
(ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
                                           only 1 sequence can be configured and is active perpetually. */

Definition at line 1626 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 1634 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 1636 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 1638 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 1640 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 1651 of file stm32g4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group injected sequencer discontinuous mode disable

Definition at line 1649 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1
#define | LL_ADC_INJ_RANK_2
#define | LL_ADC_INJ_RANK_3
#define | LL_ADC_INJ_RANK_4

Define Documentation

#define LL_ADC_INJ_RANK_1
Value:
(ADC_JDR1_REGOFFSET \
                                            | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)

ADC group inj. sequencer rank 1

Definition at line 1660 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_2
Value:
(ADC_JDR2_REGOFFSET \
                                            | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)

ADC group inj. sequencer rank 2

Definition at line 1662 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_3
Value:
(ADC_JDR3_REGOFFSET \
                                            | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)

ADC group inj. sequencer rank 3

Definition at line 1664 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_4
Value:
(ADC_JDR4_REGOFFSET \
                                            | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

ADC group inj. sequencer rank 4

Definition at line 1666 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1)
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2)
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5

Define Documentation

#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1)

Sampling time 12.5 ADC clock cycles

Definition at line 1677 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_247CYCLES_5
Value:
(ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_1)

Sampling time 247.5 ADC clock cycles

Definition at line 1683 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_24CYCLES_5
Value:
(ADC_SMPR2_SMP10_1 \
                                            | ADC_SMPR2_SMP10_0)

Sampling time 24.5 ADC clock cycles

Definition at line 1678 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)

Sampling time 2.5 ADC clock cycles

Definition at line 1675 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2)

Sampling time 47.5 ADC clock cycles

Definition at line 1680 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_640CYCLES_5
Value:
(ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_1 \
                                            | ADC_SMPR2_SMP10_0)

Sampling time 640.5 ADC clock cycles

Definition at line 1685 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0)

Sampling time 6.5 ADC clock cycles

Definition at line 1676 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_92CYCLES_5
Value:
(ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_0)

Sampling time 92.5 ADC clock cycles

Definition at line 1681 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Exported Constants

Defines

#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to both single ended and differential (literal used only to set calibration factors)

Definition at line 1699 of file stm32g4xx_ll_adc.h.

#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 1697 of file stm32g4xx_ll_adc.h.

#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 1695 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | LL_ADC_AWD1
#define | LL_ADC_AWD2
#define | LL_ADC_AWD3

Define Documentation

#define LL_ADC_AWD1
Value:
(ADC_AWD_CR1_CHANNEL_MASK \
                                            | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 1709 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and LL_ADC_GetAnalogWDMonitChannels().

#define LL_ADC_AWD2
Value:
(ADC_AWD_CR23_CHANNEL_MASK \
                                            | ADC_AWD_CR2_REGOFFSET)

ADC analog watchdog number 2

Definition at line 1711 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD3
Value:
(ADC_AWD_CR23_CHANNEL_MASK \
                                            | ADC_AWD_CR3_REGOFFSET)

ADC analog watchdog number 3

Definition at line 1713 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG
#define | LL_ADC_AWD_ALL_CHANNELS_INJ
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ
#define | LL_ADC_AWD_CHANNEL_0_REG
#define | LL_ADC_AWD_CHANNEL_0_INJ
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ
#define | LL_ADC_AWD_CHANNEL_1_REG
#define | LL_ADC_AWD_CHANNEL_1_INJ
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ
#define | LL_ADC_AWD_CHANNEL_2_REG
#define | LL_ADC_AWD_CHANNEL_2_INJ
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ
#define | LL_ADC_AWD_CHANNEL_3_REG
#define | LL_ADC_AWD_CHANNEL_3_INJ
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ
#define | LL_ADC_AWD_CHANNEL_4_REG
#define | LL_ADC_AWD_CHANNEL_4_INJ
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ
#define | LL_ADC_AWD_CHANNEL_5_REG
#define | LL_ADC_AWD_CHANNEL_5_INJ
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ
#define | LL_ADC_AWD_CHANNEL_6_REG
#define | LL_ADC_AWD_CHANNEL_6_INJ
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ
#define | LL_ADC_AWD_CHANNEL_7_REG
#define | LL_ADC_AWD_CHANNEL_7_INJ
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ
#define | LL_ADC_AWD_CHANNEL_8_REG
#define | LL_ADC_AWD_CHANNEL_8_INJ
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ
#define | LL_ADC_AWD_CHANNEL_9_REG
#define | LL_ADC_AWD_CHANNEL_9_INJ
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ
#define | LL_ADC_AWD_CHANNEL_10_REG
#define | LL_ADC_AWD_CHANNEL_10_INJ
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ
#define | LL_ADC_AWD_CHANNEL_11_REG
#define | LL_ADC_AWD_CHANNEL_11_INJ
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ
#define | LL_ADC_AWD_CHANNEL_12_REG
#define | LL_ADC_AWD_CHANNEL_12_INJ
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ
#define | LL_ADC_AWD_CHANNEL_13_REG
#define | LL_ADC_AWD_CHANNEL_13_INJ
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ
#define | LL_ADC_AWD_CHANNEL_14_REG
#define | LL_ADC_AWD_CHANNEL_14_INJ
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ
#define | LL_ADC_AWD_CHANNEL_15_REG
#define | LL_ADC_AWD_CHANNEL_15_INJ
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ
#define | LL_ADC_AWD_CHANNEL_16_REG
#define | LL_ADC_AWD_CHANNEL_16_INJ
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ
#define | LL_ADC_AWD_CHANNEL_17_REG
#define | LL_ADC_AWD_CHANNEL_17_INJ
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ
#define | LL_ADC_AWD_CHANNEL_18_REG
#define | LL_ADC_AWD_CHANNEL_18_INJ
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ
#define | LL_ADC_AWD_CH_VREFINT_REG
#define | LL_ADC_AWD_CH_VREFINT_INJ
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ
#define | LL_ADC_AWD_CH_VBAT_REG
#define | LL_ADC_AWD_CH_VBAT_INJ
#define | LL_ADC_AWD_CH_VBAT_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP1_REG
#define | LL_ADC_AWD_CH_VOPAMP1_INJ
#define | LL_ADC_AWD_CH_VOPAMP1_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP2_REG
#define | LL_ADC_AWD_CH_VOPAMP2_INJ
#define | LL_ADC_AWD_CH_VOPAMP2_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_REG
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_REG
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP4_REG
#define | LL_ADC_AWD_CH_VOPAMP4_INJ
#define | LL_ADC_AWD_CH_VOPAMP4_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP5_REG
#define | LL_ADC_AWD_CH_VOPAMP5_INJ
#define | LL_ADC_AWD_CH_VOPAMP5_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP6_REG
#define | LL_ADC_AWD_CH_VOPAMP6_INJ
#define | LL_ADC_AWD_CH_VOPAMP6_REG_INJ

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ
Value:
(ADC_AWD_CR23_CHANNEL_MASK \
                                            | ADC_CFGR_JAWD1EN)

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 1727 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG
Value:
(ADC_AWD_CR23_CHANNEL_MASK \
                                            | ADC_CFGR_AWD1EN)

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 1724 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ
Value:
(ADC_AWD_CR23_CHANNEL_MASK \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 1730 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog of ADC1 internal channel connected to internal temperature sensor, converted by group injected only

Definition at line 1941 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC1 internal channel connected to internal temperature sensor, converted by group regular only

Definition at line 1937 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC1 internal channel connected to internal temperature sensor, converted by either group regular or injected

Definition at line 1945 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)

ADC analog of ADC5 internal channel connected to internal temperature sensor, converted by group injected only

Definition at line 1954 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC5 internal channel connected to internal temperature sensor, converted by group regular only

Definition at line 1950 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ
Value:
((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC5 internal channel connected to internal temperature sensor, converted by either group regular or injected

Definition at line 1958 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_INJ
Value:
((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda, converted by group injected only

Definition at line 1968 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG
Value:
((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda, converted by group regular only

Definition at line 1963 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG_INJ
Value:
((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda

Definition at line 1973 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP1_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only

Definition at line 1983 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP1_REG
Value:
((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only

Definition at line 1979 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected

Definition at line 1987 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP2_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only

Definition at line 1995 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP2_REG
Value:
((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring channel specific to ADC2, converted by group regular only

Definition at line 1992 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected

Definition at line 1999 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only

Definition at line 2008 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only

Definition at line 2004 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected

Definition at line 2012 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only

Definition at line 2021 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only

Definition at line 2017 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected

Definition at line 2025 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP4_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only

Definition at line 2034 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP4_REG
Value:
((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only

Definition at line 2030 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected

Definition at line 2038 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP5_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only

Definition at line 2047 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP5_REG
Value:
((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only

Definition at line 2043 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected

Definition at line 2051 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP6_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only

Definition at line 2060 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP6_REG
Value:
((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only

Definition at line 2056 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ
Value:
((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected

Definition at line 2064 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ
Value:
((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 1928 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG
Value:
((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 1924 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ
Value:
((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 1932 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ
Value:
((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by group injected only

Definition at line 1736 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG
Value:
((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by group regular only

Definition at line 1733 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ
Value:
((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by either group regular or injected

Definition at line 1739 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ
Value:
((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by group injected only

Definition at line 1836 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG
Value:
((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by group regular only

Definition at line 1833 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ
Value:
((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by either group regular or injected

Definition at line 1839 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ
Value:
((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by group injected only

Definition at line 1846 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG
Value:
((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by group regular only

Definition at line 1843 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ
Value:
((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by either group regular or injected

Definition at line 1849 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ
Value:
((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by group injected only

Definition at line 1856 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG
Value:
((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by group regular only

Definition at line 1853 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ
Value:
((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by either group regular or injected

Definition at line 1859 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ
Value:
((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by group injected only

Definition at line 1866 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG
Value:
((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by group regular only

Definition at line 1863 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ
Value:
((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by either group regular or injected

Definition at line 1869 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ
Value:
((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by group only

Definition at line 1876 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG
Value:
((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by group regular only

Definition at line 1873 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ
Value:
((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by either group regular or injected

Definition at line 1879 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ
Value:
((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN15, converted by group injected only

Definition at line 1886 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG
Value:
((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring monitoring of ADC channel ADCx_IN15, converted by group regular only

Definition at line 1883 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ
Value:
((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN15, converted by either group regular or injected

Definition at line 1889 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ
Value:
((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by group injected only

Definition at line 1897 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG
Value:
((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by group regular only

Definition at line 1894 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ
Value:
((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by either group regular or injected

Definition at line 1900 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ
Value:
((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by group injected only

Definition at line 1907 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG
Value:
((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by group regular only

Definition at line 1904 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ
Value:
((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by either group regular or injected

Definition at line 1910 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_INJ
Value:
((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by group injected only

Definition at line 1917 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG
Value:
((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by group regular only

Definition at line 1914 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG_INJ
Value:
((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by either group regular or injected

Definition at line 1920 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ
Value:
((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by group injected only

Definition at line 1746 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG
Value:
((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by group regular only

Definition at line 1743 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ
Value:
((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by either group regular or injected

Definition at line 1749 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ
Value:
((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by group injected only

Definition at line 1756 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG
Value:
((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by group regular only

Definition at line 1753 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ
Value:
((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by either group regular or injected

Definition at line 1759 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ
Value:
((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by group injected only

Definition at line 1766 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG
Value:
((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by group regular only

Definition at line 1763 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ
Value:
((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by either group regular or injected

Definition at line 1769 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ
Value:
((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by group injected only

Definition at line 1776 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG
Value:
((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by group regular only

Definition at line 1773 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ
Value:
((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by either group regular or injected

Definition at line 1779 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ
Value:
((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by group injected only

Definition at line 1786 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG
Value:
((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by group regular only

Definition at line 1783 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ
Value:
((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by either group regular or injected

Definition at line 1789 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ
Value:
((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by group injected only

Definition at line 1796 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG
Value:
((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by group regular only

Definition at line 1793 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ
Value:
((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by either group regular or injected

Definition at line 1799 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ
Value:
((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by group injected only

Definition at line 1806 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG
Value:
((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by group regular only

Definition at line 1803 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ
Value:
((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by either group regular or injected

Definition at line 1809 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ
Value:
((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by group injected only

Definition at line 1816 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG
Value:
((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by group regular only

Definition at line 1813 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ
Value:
((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by either group regular or injected

Definition at line 1819 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ
Value:
((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by group injected only

Definition at line 1826 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG
Value:
((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by group regular only

Definition at line 1823 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ
Value:
((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
                                            | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by either group regular or injected

Definition at line 1829 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE (0x00000000UL)

ADC analog watchdog monitoring disabled

Definition at line 1722 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1)

ADC analog watchdog threshold high

Definition at line 2076 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1)

ADC analog watchdog threshold low

Definition at line 2077 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Value:
(ADC_TR1_HT1 \
                                            | ADC_TR1_LT1)

ADC analog watchdog both thresholds high and low concatenated into the same data

Definition at line 2078 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog watchdog - filtering config

Defines
Analog watchdog - filtering config
ADC Exported Constants

Defines

#define | LL_ADC_AWD_FILTERING_NONE (0x00000000UL)
#define | LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1)
#define | LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2)
#define | LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)
#define | LL_ADC_AWD_FILTERING_8SAMPLES

Define Documentation

#define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0)

ADC analog watchdog 2 out-of-window samples are needed to raise flag or interrupt

Definition at line 2090 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1)

ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2092 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)

ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2094 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2)

ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2096 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)

ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2098 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)

ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2100 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_8SAMPLES
Value:
(ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
                                            | ADC_TR1_AWDFILT_0)

ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt

Definition at line 2102 of file stm32g4xx_ll_adc.h.

#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL)

ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt

Definition at line 2088 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Oversampling scope

Defines
Oversampling - Oversampling scope
ADC Exported Constants

Defines

#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE)
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

Define Documentation

#define LL_ADC_OVS_DISABLE (0x00000000UL)

ADC oversampling disabled.

Definition at line 2112 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 2123 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE)

ADC oversampling on conversions of ADC group injected.

Definition at line 2121 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards.

Definition at line 2113 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 2117 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

Define Documentation

#define LL_ADC_OVS_REG_CONT (0x00000000UL)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 2134 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 2136 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1)
#define | LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2)
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)
#define | LL_ADC_OVS_RATIO_256

Define Documentation

#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)

ADC oversampling ratio of 128 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2163 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 16 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2154 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_2 (0x00000000UL)

ADC oversampling ratio of 2 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2145 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_256
Value:
(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
                                            | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 256 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2166 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2)

ADC oversampling ratio of 32 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2157 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 4 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2148 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 64 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2160 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1)

ADC oversampling ratio of 8 (sum of conversions data computed to result as oversampling conversion data (before potential shift)

Definition at line 2151 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling - Data right shift

Defines
Oversampling - Data right shift
ADC Exported Constants

Defines

#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1)
#define | LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2)
#define | LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)
#define | LL_ADC_OVS_SHIFT_RIGHT_7
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3)

Define Documentation

#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as oversampling conversion data)

Definition at line 2177 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0)

ADC oversampling right shift of 1 (sum of the ADC conversions data (after OVS ratio) is divided by 2 to result as oversampling conversion data)

Definition at line 2180 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1)

ADC oversampling right shift of 2 (sum of the ADC conversions data (after OVS ratio) is divided by 4 to result as oversampling conversion data)

Definition at line 2183 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling right shift of 3 (sum of the ADC conversions data (after OVS ratio) is divided by 8 to result as oversampling conversion data)

Definition at line 2186 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2)

ADC oversampling right shift of 4 (sum of the ADC conversions data (after OVS ratio) is divided by 16 to result as oversampling conversion data)

Definition at line 2189 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)

ADC oversampling right shift of 5 (sum of the ADC conversions data (after OVS ratio) is divided by 32 to result as oversampling conversion data)

Definition at line 2192 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)

ADC oversampling right shift of 6 (sum of the ADC conversions data (after OVS ratio) is divided by 64 to result as oversampling conversion data)

Definition at line 2195 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_7
Value:
(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
                                            | ADC_CFGR2_OVSS_0)

ADC oversampling right shift of 7 (sum of the ADC conversions data (after OVS ratio) is divided by 128 to result as oversampling conversion data)

Definition at line 2198 of file stm32g4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3)

ADC oversampling right shift of 8 (sum of the ADC conversions data (after OVS ratio) is divided by 256 to result as oversampling conversion data)

Definition at line 2202 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - Mode

Defines
Multimode - Mode
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)
#define | LL_ADC_MULTI_DUAL_REG_INTERL
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1)
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

Define Documentation

#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not SW start)

Definition at line 2222 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected simultaneous

Definition at line 2220 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Definition at line 2228 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTERL
Value:
(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
                                            | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved

Definition at line 2217 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1)

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 2226 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 2224 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)

ADC dual mode enabled: group regular simultaneous

Definition at line 2215 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL)

ADC dual mode disabled (ADC independent mode)

Definition at line 2213 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - DMA transfer

Defines
Multimode - DMA transfer
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B

Define Documentation

#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)

ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings

Definition at line 2237 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits

Definition at line 2240 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits

Definition at line 2246 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits

Definition at line 2252 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
Value:
(ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
                                              | ADC_CCR_MDMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits

Definition at line 2258 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - Delay between two sampling phases

Defines
Multimode - Delay between two sampling phases
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3)
#define | LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES

Define Documentation

#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 10 ADC clock cycles

Definition at line 2291 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 11 ADC clock cycles

Definition at line 2293 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
Value:
(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
                                            | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 12 ADC clock cycles

Definition at line 2295 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL)

ADC multimode delay between two sampling phases: 1 ADC clock cycle

Definition at line 2272 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 2 ADC clock cycles

Definition at line 2274 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 3 ADC clock cycles

Definition at line 2276 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 4 ADC clock cycles

Definition at line 2278 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2)

ADC multimode delay between two sampling phases: 5 ADC clock cycles

Definition at line 2280 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 6 ADC clock cycles

Definition at line 2282 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 7 ADC clock cycles

Definition at line 2284 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
Value:
(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
                                            | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 8 ADC clock cycles

Definition at line 2286 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3)

ADC multimode delay between two sampling phases: 9 ADC clock cycles

Definition at line 2289 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Multimode - ADC master or slave

Defines
Multimode - ADC master or slave
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV)
#define | LL_ADC_MULTI_MASTER_SLAVE

Define Documentation

#define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: ADC master

Definition at line 2305 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_MASTER_SLAVE
Value:
(ADC_CDR_RDATA_SLV \
                                            | ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: both ADC master and ADC slave

Definition at line 2309 of file stm32g4xx_ll_adc.h.

#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV)

In multimode, selection among several ADC instances: ADC slave

Definition at line 2307 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Definitions of constants used by helper macro

Defines
Definitions of constants used by helper macro
ADC Exported Constants

Defines

#define LL_ADC_TEMPERATURE_CALC_ERROR

Define Documentation

#define LL_ADC_TEMPERATURE_CALC_ERROR
Value:
((int16_t)0x7FFF)  /* Temperature calculation error using helper macro
                                                                 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
                                                                 calibration parameters. This value is coded on 16 bits
                                                                 (to fit on signed word or double word) and corresponds
                                                                 to an inconsistent temperature value. */

Definition at line 2321 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)

Detailed Description

Note:
Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)

Delay required between ADC end of calibration and ADC enable

Definition at line 2382 of file stm32g4xx_ll_adc.h.

#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)

Delay for ADC stabilization time (ADC voltage regulator start-up time)

Definition at line 2356 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init().

#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)

Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to LL_ADC_Enable())

Definition at line 2371 of file stm32g4xx_ll_adc.h.

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)

Delay for temperature sensor stabilization time

Definition at line 2370 of file stm32g4xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)

Delay for internal voltage reference stabilization time

Definition at line 2363 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 2418 of file stm32g4xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 2410 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__)
Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
   :                                                                                                      \
   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
   :                                                                                                      \
   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
(1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
  • LL_ADC_AWD_CH_VBAT_REG (0)(6)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(6)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (6)
  • LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
  • LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
  • LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
  • LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
  • LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
  • LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
  • LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
  • LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
  • LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
  • LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
  • LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
  • LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
  • LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
  • LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
  • LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
(0) On STM32G4, parameter available only on analog watchdog number: AWD1.
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.

Definition at line 3038 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3090 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_ConfigAnalogWDThresholds() or LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3068 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW | ( | __AWD_THRESHOLD_TYPE__,
 |  | __AWD_THRESHOLDS__
 | ) |
Value:
(((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
   & LL_ADC_AWD_THRESHOLD_LOW)

Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, to get analog watchdog threshold high from the register raw value: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
Parameters:
__AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
__AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3105 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
)

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 3310 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
 - (int32_t)(__VREFANALOG_VOLTAGE__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.

Note:
ADC data from ADC data register is unsigned and centered around middle code in. Converted voltage can be positive or negative depending on differential input voltages.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 3336 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ?       \
 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                   (__ADC_RESOLUTION__),          \
                                                   LL_ADC_RESOLUTION_12B)         \
                  * (__VREFANALOG_VOLTAGE__))                                     \
                 / TEMPSENSOR_CAL_VREFANALOG)                                     \
       - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
    ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
   ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
  ) + TEMPSENSOR_CAL1_TEMP                                                        \
 )                                                                                \
 :                                                                                \
 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR)                                         \
)

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 series, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius) In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)

Definition at line 3422 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
               / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
              * 1000UL)                                                     \
    -                                                                       \
    (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
              * 1000UL)                                                     \
   )                                                                        \
  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
)

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12 bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32G4, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) value (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 3487 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
                                    (__ADC_RESOLUTION__),                    \
                                    LL_ADC_RESOLUTION_12B)                   \
)

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 series, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 3368 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF | ( | __CALIB_FACTOR_SINGLE_ENDED__,
 |  | __CALIB_FACTOR_DIFFERENTIAL__
 | ) | (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.

Note:
To be used with function LL_ADC_SetCalibrationFactor(). Example, to set calibration factors single ended to 0x55 and differential ended to 0x2A: LL_ADC_SetCalibrationFactor( ADC1, __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
Parameters:
__CALIB_FACTOR_SINGLE_ENDED__ | Value between Min_Data=0x00 and Max_Data=0x7F
__CALIB_FACTOR_DIFFERENTIAL__ | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 3122 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18

Definition at line 2713 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ )
Value:
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
   (                                                                                       \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
   )                                                                                       \
   :                                                                                       \
   (                                                                                       \
       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
   )                                                                                       \
  )

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 2483 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADCEx_InjectedConfigChannel(), and LL_ADC_GetAnalogWDMonitChannels().

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC12_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 3202 of file stm32g4xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), and LL_ADC_DMA_GetRegAddr().

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
)

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 3286 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9UL) ?                                                                          \
   (                                                                                                    \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                              |          \
       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
   )                                                                                                    \
   :                                                                                                    \
   (                                                                                                    \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       | \
       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
   )                                                                                                    \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
(1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2550 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

Definition at line 3265 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 2631 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((__ADC_INSTANCE__) == ADC1)                                               \
    &&(                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
      )                                                                        \
   )                                                                           \
   ||                                                                          \
   (((__ADC_INSTANCE__) == ADC2)                                               \
    &&(                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
      )                                                                        \
   )                                                                           \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 2825 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 3248 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADCEx_MultiModeConfigChannel(), and LL_ADC_CommonInit().

#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled: refer to function LL_ADC_SetMultiDMATransfer(). In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3139 of file stm32g4xx_ll_adc.h.

#define __LL_ADC_MULTI_INSTANCE_MASTER ( __ADCx__ )
Value:
( ( ((__ADCx__) == ADC2)                                                     \
    )?                                                                         \
    (ADC1)                                                                     \
    :                                                                          \
    (__ADCx__)                                                                 \
  )

Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).

Note:
In case of device with multimode available and a mix of ADC instances compliant and not compliant with multimode feature, ADC instances not compliant with multimode feature are considered as master instances (do not depend to any other ADC instance).
Parameters:
__ADCx__ ADC instance
Return values:
__ADCx__ ADC instance master of the corresponding ADC common instance

Definition at line 3170 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (const ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_DMA_GetRegAddr
CDR RDATA_MST LL_ADC_DMA_GetRegAddr
CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
(1) Available on devices with several ADC instances.
Return values:
ADC register address

Definition at line 3556 of file stm32g4xx_ll_adc.h.

References __LL_ADC_COMMON_INSTANCE, and LL_ADC_DMA_REG_REGULAR_DATA.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: common to several

Functions
Configuration of ADC hierarchical scope: common to several
ADC Exported Functions

ADC instances. More...

Functions

__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (const ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChAdd (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChRem (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (const ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Detailed Description

ADC instances.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonClock ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: Clock source and prescaler.

Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_GetCommonClock
CCR PRESC LL_ADC_GetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256

Definition at line 3655 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_GetCommonPathInternalCh
CCR VSENSESEL LL_ADC_GetCommonPathInternalCh
CCR VBATSEL LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT

Definition at line 3774 of file stm32g4xx_ll_adc.h.

Referenced by ADC_Enable(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonClock | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonClock
 | ) |  |

Set parameter common to several ADC: Clock source and prescaler.

Note:
On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_SetCommonClock
CCR PRESC LL_ADC_SetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonClock This parameter can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256
Return values:
None

Definition at line 3627 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init(), and LL_ADC_CommonInit().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Configure all paths (overwrite current configuration).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR) The values not selected are removed from configuration.
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literals LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalCh
CCR VSENSESEL LL_ADC_SetCommonPathInternalCh
CCR VBATSEL LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 3692 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Add paths to the current configuration.

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literals LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalChAdd
CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd
CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 3728 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Remove paths to the current configuration.

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalChRem
CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem
CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 3752 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (const ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (const ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (const ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (const ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset instance 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset instance 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void | LL_ADC_SetOffsetSign (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset sign.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSign (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset sign if positive or negative.
__STATIC_INLINE void | LL_ADC_SetOffsetSaturation (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset saturation mode.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSaturation (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset saturation if enabled or disabled.
__STATIC_INLINE void | LL_ADC_SetGainCompensation (ADC_TypeDef *ADCx, uint32_t GainCompensation)
Set ADC gain compensation.
__STATIC_INLINE uint32_t | LL_ADC_GetGainCompensation (const ADC_TypeDef *ADCx)
Get the ADC gain compensation value.
__STATIC_INLINE void | LL_ADC_SetSamplingTimeCommonConfig (ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
Set ADC sampling time common configuration impacting settings of sampling time channel wise.
__STATIC_INLINE uint32_t | LL_ADC_GetSamplingTimeCommonConfig (const ADC_TypeDef *ADCx)
Get ADC sampling time common configuration impacting settings of sampling time channel wise.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_GetCalibrationFactor
CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
Value between Min_Data=0x00 and Max_Data=0x7F

Definition at line 3843 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_GetValue().

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( const ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_GetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 3924 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation ( const ADC_TypeDef * ADCx )

Get the ADC gain compensation value.

Reference Manual to LL API cross reference:
GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation
CFGR2 GCOMP LL_ADC_GetGainCompensation
Parameters:
ADCx ADC instance
Return values:
Returned value can be: 0 Gain compensation is disabled 1 -> 16393 Gain compensation is enabled with returned value

Definition at line 4434 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode ( const ADC_TypeDef * ADCx )

Get ADC low power mode:

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • It is not recommended to use with interruption or DMA since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_GetLowPowerMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT

Definition at line 4019 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset instance 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
On STM32G4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
(1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 4197 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset instance 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).

Note:
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
OFR1 OFFSET1 LL_ADC_GetOffsetLevel
OFR2 OFFSET2 LL_ADC_GetOffsetLevel
OFR3 OFFSET3 LL_ADC_GetOffsetLevel
OFR4 OFFSET4 LL_ADC_GetOffsetLevel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 4223 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset instance 1, 2, 3 or 4: offset saturation if enabled or disabled.

Reference Manual to LL API cross reference:
OFR1 SATEN LL_ADC_GetOffsetSaturation
OFR2 SATEN LL_ADC_GetOffsetSaturation
OFR3 SATEN LL_ADC_GetOffsetSaturation
OFR4 SATEN LL_ADC_GetOffsetSaturation
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_SATURATION_ENABLE
  • LL_ADC_OFFSET_SATURATION_DISABLE

Definition at line 4392 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset instance 1, 2, 3 or 4: offset sign if positive or negative.

Reference Manual to LL API cross reference:
OFR1 OFFSETPOS LL_ADC_GetOffsetSign
OFR2 OFFSETPOS LL_ADC_GetOffsetSign
OFR3 OFFSETPOS LL_ADC_GetOffsetSign
OFR4 OFFSETPOS LL_ADC_GetOffsetSign
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_SIGN_NEGATIVE
  • LL_ADC_OFFSET_SIGN_POSITIVE

Definition at line 4337 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetState | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset instance 1, 2, 3 or 4: offset state disabled or enabled.

Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_GetOffsetState
OFR2 OFFSET2_EN LL_ADC_GetOffsetState
OFR3 OFFSET3_EN LL_ADC_GetOffsetState
OFR4 OFFSET4_EN LL_ADC_GetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE

Definition at line 4282 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetResolution ( const ADC_TypeDef * ADCx )

Get ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Reference Manual to LL API cross reference:
CFGR RES LL_ADC_GetResolution
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B

Definition at line 3889 of file stm32g4xx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK, ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4, and ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig ( const ADC_TypeDef * ADCx )

Get ADC sampling time common configuration impacting settings of sampling time channel wise.

Reference Manual to LL API cross reference:
SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
  • LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5

Definition at line 4469 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
This function is intended to set calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration factor must be specified for each of these differential modes, if used afterwards and if the application requires their calibration).
In case of setting calibration factors of both modes single ended and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): both calibration factors must be concatenated. To perform this processing, use helper macro __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_SetCalibrationFactor
CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
Parameters:
ADCx | ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
None

Definition at line 3818 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 3909 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetGainCompensation | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | GainCompensation
 | ) |  |

Set ADC gain compensation.

Note:
This function set the gain compensation coefficient that is applied to raw converted data using the formula: DATA = DATA(raw) * (gain compensation coef) / 4096
This function enables the gain compensation if given coefficient is above 0, otherwise it disables it.
Gain compensation when enabled is applied to all channels.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation
CFGR2 GCOMP LL_ADC_SetGainCompensation
Parameters:
ADCx | ADC instance
GainCompensation | This parameter can be: 0 Gain compensation will be disabled and value set to 0 1 -> 16393 Gain compensation will be enabled with specified value
Return values:
None

Definition at line 4419 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE void LL_ADC_SetLowPowerMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LowPowerMode
 | ) |  |

Set ADC low power mode.

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • It is not recommended to use with interruption or DMA since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_SetLowPowerMode
Parameters:
ADCx ADC instance
LowPowerMode This parameter can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
Return values:
None

Definition at line 3974 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | Channel,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC selected offset instance 1, 2, 3 or 4.

Note:
This function set the 2 items of offset configuration:
  • ADC channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
  • Offset level (offset to be subtracted from the raw converted data).
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
This function enables the offset, by default. It can be forced to disable state using function LL_ADC_SetOffsetState().
If a channel is mapped on several offsets numbers, only the offset with the lowest value is considered for the subtraction.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
On STM32G4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_SetOffset
OFR1 OFFSET1 LL_ADC_SetOffset
OFR1 OFFSET1_EN LL_ADC_SetOffset
OFR2 OFFSET2_CH LL_ADC_SetOffset
OFR2 OFFSET2 LL_ADC_SetOffset
OFR2 OFFSET2_EN LL_ADC_SetOffset
OFR3 OFFSET3_CH LL_ADC_SetOffset
OFR3 OFFSET3 LL_ADC_SetOffset
OFR3 OFFSET3_EN LL_ADC_SetOffset
OFR4 OFFSET4_CH LL_ADC_SetOffset
OFR4 OFFSET4 LL_ADC_SetOffset
OFR4 OFFSET4_EN LL_ADC_SetOffset
Parameters:
ADCx | ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 4111 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and ADC_CHANNEL_ID_NUMBER_MASK.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetOffsetSaturation | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetSaturation
 | ) |  |

Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset saturation mode.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
OFR1 SATEN LL_ADC_SetOffsetSaturation
OFR2 SATEN LL_ADC_SetOffsetSaturation
OFR3 SATEN LL_ADC_SetOffsetSaturation
OFR4 SATEN LL_ADC_SetOffsetSaturation
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetSaturation This parameter can be one of the following values:
  • LL_ADC_OFFSET_SATURATION_ENABLE
  • LL_ADC_OFFSET_SATURATION_DISABLE
Return values:
None

Definition at line 4366 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetOffsetSign | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetSign
 | ) |  |

Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset sign.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
OFR1 OFFSETPOS LL_ADC_SetOffsetSign
OFR2 OFFSETPOS LL_ADC_SetOffsetSign
OFR3 OFFSETPOS LL_ADC_SetOffsetSign
OFR4 OFFSETPOS LL_ADC_SetOffsetSign
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetSign This parameter can be one of the following values:
  • LL_ADC_OFFSET_SIGN_NEGATIVE
  • LL_ADC_OFFSET_SIGN_POSITIVE
Return values:
None

Definition at line 4311 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetOffsetState | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetState
 | ) |  |

Set for the ADC selected offset instance 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.

Note:
This function should be needed only in case of offset to be enabled-disabled dynamically, and should not be needed in other cases: function LL_ADC_SetOffset() automatically enables the offset.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_SetOffsetState
OFR2 OFFSET2_EN LL_ADC_SetOffsetState
OFR3 OFFSET3_EN LL_ADC_SetOffsetState
OFR4 OFFSET4_EN LL_ADC_SetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetState This parameter can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE
Return values:
None

Definition at line 4256 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetResolution | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Resolution
 | ) |  |

Set ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR RES LL_ADC_SetResolution
Parameters:
ADCx ADC instance
Resolution This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
None

Definition at line 3872 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SamplingTimeCommonConfig
 | ) |  |

Set ADC sampling time common configuration impacting settings of sampling time channel wise.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
Parameters:
ADCx ADC instance
SamplingTimeCommonConfig This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
  • LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
Return values:
None

Definition at line 4455 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSamplingMode (ADC_TypeDef *ADCx, uint32_t SamplingMode)
Set ADC sampling mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSamplingMode (const ADC_TypeDef *ADCx)
Get the ADC sampling mode.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (const ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (const ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (const ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (const ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( const ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 5156 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_GetMultiDMATransfer().
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_GetDMATransfer
CFGR DMACFG LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 5231 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun ( const ADC_TypeDef * ADCx )

Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_GetOverrun
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 5270 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode ( const ADC_TypeDef * ADCx )

Get the ADC sampling mode.

Reference Manual to LL API cross reference:
CFGR2 BULB LL_ADC_REG_GetSamplingMode
CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SAMPLING_MODE_NORMAL
  • LL_ADC_REG_SAMPLING_MODE_BULB
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED

Definition at line 4717 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( const ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 4885 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( const ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 4830 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 series, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
(1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 5109 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 4679 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_GetTriggerSource
CFGR EXTEN LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM7_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM20_CH1
  • LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
  • LL_ADC_REG_TRIG_EXT_LPTIM_OUT
(1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.
(2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.

Definition at line 4617 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 4644 of file stm32g4xx_ll_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 5139 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_SetMultiDMATransfer().
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_SetDMATransfer
CFGR DMACFG LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 5196 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetOverrun | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Overrun
 | ) |  |

Set ADC group regular behavior in case of overrun: data preserved or overwritten.

Note:
Compatibility with devices without feature overrun: other devices without this feature have a behavior equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_SetOverrun
Parameters:
ADCx ADC instance
Overrun This parameter can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN
Return values:
None

Definition at line 5256 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSamplingMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SamplingMode
 | ) |  |

Set ADC sampling mode.

Note:
This function set the ADC conversion sampling mode
This mode applies to regular group only.
Set sampling mode is applied to all conversion of regular group.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR2 BULB LL_ADC_REG_SetSamplingMode
CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
Parameters:
ADCx ADC instance
SamplingMode This parameter can be one of the following values:
  • LL_ADC_REG_SAMPLING_MODE_NORMAL
  • LL_ADC_REG_SAMPLING_MODE_BULB
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
Return values:
None

Definition at line 4702 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 4862 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 4776 of file stm32g4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 series, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
None

Definition at line 4991 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 4664 of file stm32g4xx_ll_adc.h.

References ADC_REG_TRIG_EXTEN_BITOFFSET_POS.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_SetTriggerSource
CFGR EXTEN LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM7_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM20_CH1
  • LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
  • LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
  • LL_ADC_REG_TRIG_EXT_LPTIM_OUT
(1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.
(2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
Return values:
None

Definition at line 4550 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (const ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (const ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (const ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.

Function Documentation

__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource,
 |  | uint32_t | ExternalTriggerEdge,
 |  | uint32_t | SequencerNbRanks,
 |  | uint32_t | Rank1_Channel,
 |  | uint32_t | Rank2_Channel,
 |  | uint32_t | Rank3_Channel,
 |  | uint32_t | Rank4_Channel
 | ) |  |

Set one context on ADC group injected that will be checked in contexts queue.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks This function is intended to be used when contexts queue is enabled, because the sequence must be fully configured in one time (functions to set separately injected trigger and sequencer channels cannot be used): Refer to function LL_ADC_INJ_SetQueueMode().
In the contexts queue, only the active context can be read. The parameters of this function can be read using functions:
  • LL_ADC_INJ_GetTriggerSource()
  • LL_ADC_INJ_GetTriggerEdge()
  • LL_ADC_INJ_GetSequencerRanks()
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32G4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
JSQR JL LL_ADC_INJ_ConfigQueueContext
JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
  • LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
(1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.
(2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Note: This parameter is discarded in case of SW start: parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Rank1_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Rank2_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Rank3_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Rank4_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
None

Definition at line 6115 of file stm32g4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_INJ_RANK_ID_JSQR_MASK, LL_ADC_INJ_RANK_1, LL_ADC_INJ_RANK_2, LL_ADC_INJ_RANK_3, LL_ADC_INJ_RANK_4, and LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode ( const ADC_TypeDef * ADCx )

Get ADC group injected context queue mode.

Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_GetQueueMode
CFGR JQDIS LL_ADC_INJ_GetQueueMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Definition at line 5836 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( const ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 5557 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( const ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 5524 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
(1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 5722 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( const ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 5775 of file stm32g4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge ( const ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Definition at line 5477 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( const ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
  • LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
(1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.
(2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.

Definition at line 5415 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( const ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 5442 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_INJ_SetQueueMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | QueueMode
 | ) |  |

Set ADC group injected contexts queue mode.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks If contexts queue is disabled:
  • only 1 sequence can be configured and is active perpetually. If contexts queue is enabled:
  • up to 2 contexts can be queued and are checked in and out as a FIFO stack (first-in, first-out).
  • If a new context is set when queues is full, error is triggered by interruption "Injected Queue Overflow".
  • Two behaviors are possible when all contexts have been processed: the contexts queue can maintain the last context active perpetually or can be empty and injected group triggers are disabled.
  • Triggers can be only external (not internal SW start)
  • Caution: The sequence must be fully configured in one time (one write of register JSQR makes a check-in of a new context into the queue). Therefore functions to set separately injected trigger and sequencer channels cannot be used, register JSQR must be set using function LL_ADC_INJ_ConfigQueueContext().
This parameter can be modified only when no conversion is on going on either groups regular or injected.
A modification of the context mode (bit JQDIS) causes the contexts queue to be flushed and the register JSQR is cleared.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_SetQueueMode
CFGR JQDIS LL_ADC_INJ_SetQueueMode
Parameters:
ADCx ADC instance
QueueMode This parameter can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
Return values:
None

Definition at line 5821 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 5542 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 5503 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32G4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
None

Definition at line 5634 of file stm32g4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 5761 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 5462 of file stm32g4xx_ll_adc.h.

References ADC_INJ_TRIG_EXTEN_BITOFFSET_POS.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
  • LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
(1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.
(2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
Return values:
None

Definition at line 5349 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (const ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (const ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. On this STM32 series, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5
(1) On some devices, ADC sampling time 2.5 ADC clock cycles can be replaced by 3.5 ADC clock cycles. Refer to function LL_ADC_SetSamplingTimeCommonConfig().

Definition at line 6371 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get mode single-ended or differential input of the selected ADC channel.

Note:
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Therefore, to ensure a channel is configured in single-ended mode, the configuration of channel itself and the channel 'i-1' must be read back (to ensure that the selected channel channel has not been configured in differential mode by the previous channel).
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32G4, some channels are internally fixed to single-ended inputs configuration:
  • ADC1: Channels 12, 15, 16, 17 and 18
  • ADC2: Channels 15, 17 and 18
  • ADC3: Channels 12, 16, 17 and 18 (1)
  • ADC4: Channels 16, 17 and 18 (1)
  • ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) (1) ADC3/4/5 are not available on all devices, refer to device datasheet for more details.
One or several values can be selected. In this case, the value returned is null if all channels are in single ended-mode. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
Return values:
0,: channel in single-ended mode, else: channel in differential mode

Definition at line 6496 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. On this STM32 series, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (8)
  • LL_ADC_CHANNEL_2 (8)
  • LL_ADC_CHANNEL_3 (8)
  • LL_ADC_CHANNEL_4 (8)
  • LL_ADC_CHANNEL_5 (8)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (7)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
  • LL_ADC_CHANNEL_VBAT (6)
  • LL_ADC_CHANNEL_VOPAMP1 (1)
  • LL_ADC_CHANNEL_VOPAMP2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
  • LL_ADC_CHANNEL_VOPAMP4 (5)
  • LL_ADC_CHANNEL_VOPAMP5 (5)
  • LL_ADC_CHANNEL_VOPAMP6 (4)
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5
(1) On some devices, ADC sampling time 2.5 ADC clock cycles can be replaced by 3.5 ADC clock cycles. Refer to function LL_ADC_SetSamplingTimeCommonConfig().
Return values:
None

Definition at line 6267 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SingleDiff
 | ) |  |

Set mode single-ended or differential input of the selected ADC channel.

Note:
Channel ending is on channel scope: independently of channel mapped on ADC group regular or injected. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32G4, some channels are internally fixed to single-ended inputs configuration:
  • ADC1: Channels 12, 15, 16, 17 and 18
  • ADC2: Channels 15, 17 and 18
  • ADC3: Channels 12, 16, 17 and 18 (1)
  • ADC4: Channels 16, 17 and 18 (1)
  • ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) (1) ADC3/4/5 are not available on all devices, refer to device datasheet for more details.
For ADC channels configured in differential mode, both inputs should be biased at (Vref+)/2 +/-200mV. (Vref+ is the analog voltage reference)
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
SingleDiff This parameter can be a combination of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 6438 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (const ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetAWDFilteringConfiguration (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
Set ADC analog watchdog filtering configuration.
__STATIC_INLINE uint32_t | LL_ADC_GetAWDFilteringConfiguration (const ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog filtering configuration.

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdHighValue,
 |  | uint32_t | AWDThresholdLowValue
 | ) |  |

Set ADC analog watchdog thresholds value of both thresholds high and low.

Note:
If value of only one threshold high or low must be set, use function LL_ADC_SetAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). Examples:
  • Oversampling ratio and shift selected to have ADC conversion data on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): ADC analog watchdog thresholds must be divided by 16.
  • Oversampling ratio and shift selected to have ADC conversion data on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): ADC analog watchdog thresholds must be divided by 4.
  • Oversampling ratio and shift selected to have ADC conversion data on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): ADC analog watchdog thresholds match directly to ADC data register.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdHighValue | Value between Min_Data=0x000 and Max_Data=0xFFF
AWDThresholdLowValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 6916 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_REGOFFSET_MASK, ADC_AWD_TRX_REGOFFSET_POS, and ADC_TR1_HT1_BITOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2 (1)
  • LL_ADC_AWD3 (1)
(1) On this AWD number, monitored channel can be retrieved if only 1 channel is programmed (or none or all channels). This function cannot retrieve monitored channel if multiple channels are programmed simultaneously by bitfield.
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
(0) On STM32G4, parameter available only on analog watchdog number: AWD1.

Definition at line 6800 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR23_CHANNEL_MASK, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, ADC_AWD_CRX_REGOFFSET_POS, and LL_ADC_AWD1.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Note:
If raw data with ADC thresholds high and low is retrieved, the data of each threshold high or low can be isolated using helper macro: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_GetAnalogWDThresholds
TR2 HT2 LL_ADC_GetAnalogWDThresholds
TR3 HT3 LL_ADC_GetAnalogWDThresholds
TR1 LT1 LL_ADC_GetAnalogWDThresholds
TR2 LT2 LL_ADC_GetAnalogWDThresholds
TR3 LT3 LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 7040 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_BIT_HIGH_MASK, ADC_AWD_TRX_BIT_HIGH_SHIFT4, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog filtering configuration.

Note:
On this STM32 series, this feature is only available on first analog watchdog (AWD1)
Reference Manual to LL API cross reference:
TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
Return values:
Returned value can be:
  • LL_ADC_AWD_FILTERING_NONE
  • LL_ADC_AWD_FILTERING_2SAMPLES
  • LL_ADC_AWD_FILTERING_3SAMPLES
  • LL_ADC_AWD_FILTERING_4SAMPLES
  • LL_ADC_AWD_FILTERING_5SAMPLES
  • LL_ADC_AWD_FILTERING_6SAMPLES
  • LL_ADC_AWD_FILTERING_7SAMPLES
  • LL_ADC_AWD_FILTERING_8SAMPLES

Definition at line 7100 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
  • LL_ADC_AWD_CH_VBAT_REG (0)(6)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(6)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (6)
  • LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
  • LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
  • LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
  • LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
  • LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
  • LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
  • LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
  • LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
  • LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
  • LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
  • LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
  • LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
  • LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
  • LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
  • LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
(0) On STM32G4, parameter available only on analog watchdog number: AWD1.
(1) On STM32G4, parameter available only on ADC instance: ADC1.
(2) On STM32G4, parameter available only on ADC instance: ADC2.
(3) On STM32G4, parameter available only on ADC instance: ADC3.
(4) On STM32G4, parameter available only on ADC instance: ADC4.
(5) On STM32G4, parameter available only on ADC instance: ADC5.
(6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.
(7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.
On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
Return values:
None

Definition at line 6662 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, and ADC_AWD_CRX_REGOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
If values of both thresholds high or low must be set, use function LL_ADC_ConfigAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). Examples:
  • Oversampling ratio and shift selected to have ADC conversion data on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): ADC analog watchdog thresholds must be divided by 16.
  • Oversampling ratio and shift selected to have ADC conversion data on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): ADC analog watchdog thresholds must be divided by 4.
  • Oversampling ratio and shift selected to have ADC conversion data on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): ADC analog watchdog thresholds match directly to ADC data register.
On this STM32 series, setting of this feature is not conditioned to ADC state: ADC can be disabled, enabled with or without conversion on going on either ADC groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_SetAnalogWDThresholds
TR2 HT2 LL_ADC_SetAnalogWDThresholds
TR3 HT3 LL_ADC_SetAnalogWDThresholds
TR1 LT1 LL_ADC_SetAnalogWDThresholds
TR2 LT2 LL_ADC_SetAnalogWDThresholds
TR3 LT3 LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 6996 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | FilteringConfig
 | ) |  |

Set ADC analog watchdog filtering configuration.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
On this STM32 series, this feature is only available on first analog watchdog (AWD1)
Reference Manual to LL API cross reference:
TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
FilteringConfig This parameter can be one of the following values:
  • LL_ADC_AWD_FILTERING_NONE
  • LL_ADC_AWD_FILTERING_2SAMPLES
  • LL_ADC_AWD_FILTERING_3SAMPLES
  • LL_ADC_AWD_FILTERING_4SAMPLES
  • LL_ADC_AWD_FILTERING_5SAMPLES
  • LL_ADC_AWD_FILTERING_6SAMPLES
  • LL_ADC_AWD_FILTERING_7SAMPLES
  • LL_ADC_AWD_FILTERING_8SAMPLES
Return values:
None

Definition at line 7075 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC transversal scope: oversampling

Functions
Configuration of ADC transversal scope: oversampling
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (const ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (const ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (const ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (const ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Ratio,
 |  | uint32_t | Shift
 | ) |  |

Set ADC oversampling (impacting both ADC groups regular and injected)

Note:
This function set the 2 items of oversampling configuration:
  • ratio
  • shift
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
Parameters:
ADCx ADC instance
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
Return values:
None

Definition at line 7250 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont ( const ADC_TypeDef * ADCx )

Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT

Definition at line 7211 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio ( const ADC_TypeDef * ADCx )

Get ADC oversampling ratio (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSR LL_ADC_GetOverSamplingRatio
Parameters:
ADCx ADC instance
Return values:
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256

Definition at line 7270 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope ( const ADC_TypeDef * ADCx )

Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_GetOverSamplingScope
CFGR2 JOVSE LL_ADC_GetOverSamplingScope
CFGR2 ROVSM LL_ADC_GetOverSamplingScope
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED

Definition at line 7165 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift ( const ADC_TypeDef * ADCx )

Get ADC oversampling shift (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_GetOverSamplingShift
Parameters:
ADCx ADC instance
Return values:
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8

Definition at line 7291 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OverSamplingDiscont
 | ) |  |

Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
On this STM32 series, oversampling discontinuous mode (triggered mode) can be used only when oversampling is set on group regular only and in resumed mode.
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
Parameters:
ADCx ADC instance
OverSamplingDiscont This parameter can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT
Return values:
None

Definition at line 7192 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingScope | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OvsScope
 | ) |  |

Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_SetOverSamplingScope
CFGR2 JOVSE LL_ADC_SetOverSamplingScope
CFGR2 ROVSM LL_ADC_SetOverSamplingScope
Parameters:
ADCx ADC instance
OvsScope This parameter can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED
Return values:
None

Definition at line 7140 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of ADC hierarchical scope: multimode

Functions
Configuration of ADC hierarchical scope: multimode
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
Reference Manual to LL API cross reference:
CCR MDMA LL_ADC_GetMultiDMATransfer
CCR DMACFG LL_ADC_GetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B

Definition at line 7452 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

__STATIC_INLINE uint32_t LL_ADC_GetMultimode ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_GetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

Definition at line 7355 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode delay between 2 sampling phases.

Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
(1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
(2) Parameter available only if ADC resolution is 12 or 10 bits.
(3) Parameter available only if ADC resolution is 12 bits.

Definition at line 7520 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiDMATransfer | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiDMATransfer
 | ) |  |

Set ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CCR MDMA LL_ADC_SetMultiDMATransfer
CCR DMACFG LL_ADC_SetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiDMATransfer This parameter can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
Return values:
None

Definition at line 7406 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultimode | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | Multimode
 | ) |  |

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_SetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Multimode This parameter can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
Return values:
None

Definition at line 7331 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiTwoSamplingDelay
 | ) |  |

Set ADC multimode delay between 2 sampling phases.

Note:
The sampling delay range depends on ADC resolution:
  • ADC resolution 12 bits can have maximum delay of 12 cycles.
  • ADC resolution 10 bits can have maximum delay of 10 cycles.
  • ADC resolution 8 bits can have maximum delay of 8 cycles.
  • ADC resolution 6 bits can have maximum delay of 6 cycles.
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiTwoSamplingDelay This parameter can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
(1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
(2) Parameter available only if ADC resolution is 12 or 10 bits.
(3) Parameter available only if ADC resolution is 12 bits.
Return values:
None

Definition at line 7492 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (const ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (const ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be not disabled. Must be enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7673 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_DisableDeepPowerDown ( ADC_TypeDef * ADCx )

Disable ADC deep power down mode.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_DisableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7569 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_DisableInternalRegulator ( ADC_TypeDef * ADCx )

Disable ADC internal voltage regulator.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_DisableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7621 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_DisableVoltageRegulator().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 series, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled and ADC internal voltage regulator enabled.
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7653 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Enable().

__STATIC_INLINE void LL_ADC_EnableDeepPowerDown ( ADC_TypeDef * ADCx )

Put ADC instance in deep power down state.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_EnableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7546 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_EnterADCDeepPowerDownMode().

__STATIC_INLINE void LL_ADC_EnableInternalRegulator ( ADC_TypeDef * ADCx )

Enable ADC instance internal voltage regulator.

Note:
On this STM32 series, after ADC internal voltage regulator enable, a delay for ADC internal voltage regulator stabilization is required before performing a ADC calibration or ADC enable. Refer to device datasheet, parameter tADCVREG_STUP. Refer to literal LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_EnableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7602 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( const ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 7747 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled ( const ADC_TypeDef * ADCx )

Get the selected ADC instance deep power down state.

Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
Parameters:
ADCx ADC instance
Return values:
0,: deep power down is disabled, 1: deep power down is enabled.

Definition at line 7583 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing ( const ADC_TypeDef * ADCx )

Get the selected ADC instance disable state.

Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_IsDisableOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no ADC disable command on going.

Definition at line 7703 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( const ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 7692 of file stm32g4xx_ll_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled ( const ADC_TypeDef * ADCx )

Get the selected ADC instance internal voltage regulator state.

Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
Parameters:
ADCx ADC instance
Return values:
0,: internal regulator is disabled, 1: internal regulator is enabled.

Definition at line 7632 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_StartCalibration | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 series, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Refer to literal LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration run must be performed for each of these differential modes, if used afterwards and if the application requires their calibration).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_StartCalibration
CR ADCALDIF LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 7731 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE void | LL_ADC_REG_StartSamplingPhase (ADC_TypeDef *ADCx)
Start ADC sampling phase for sampling time trigger mode.
__STATIC_INLINE void | LL_ADC_REG_StopSamplingPhase (ADC_TypeDef *ADCx)
Stop ADC sampling phase for sampling time trigger mode and start conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion state.

Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group regular.

Definition at line 7814 of file stm32g4xx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing ( const ADC_TypeDef * ADCx )

Get ADC group regular command of conversion stop state.

Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group regular.

Definition at line 7825 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10 ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData10
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 7911 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 7896 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 7881 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6 ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData6
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 7941 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8 ( const ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData8
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 7926 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32 | ( | const ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | ConversionData
 | ) |  |

Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Note:
If raw data with ADC master and slave concatenated is retrieved, a macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). (however this macro is mainly intended for multimode transfer by DMA, because this function can do the same by getting multimode conversion data of ADC master or ADC slave separately).
Reference Manual to LL API cross reference:
CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ConversionData This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
  • LL_ADC_MULTI_MASTER_SLAVE
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 7968 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 series, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7778 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS, and ADC_SINGLEDIFF_CALIB_START_MASK.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase ( ADC_TypeDef * ADCx )

Start ADC sampling phase for sampling time trigger mode.

Note:
This function is relevant only when
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set using LL_ADC_REG_SetSamplingMode
  • LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7845 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_REG_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7798 of file stm32g4xx_ll_adc.h.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase ( ADC_TypeDef * ADCx )

Stop ADC sampling phase for sampling time trigger mode and start conversion.

Note:
This function is relevant only when
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set using LL_ADC_REG_SetSamplingMode
  • LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
  • LL_ADC_REG_StartSamplingPhase has been called to start the sampling phase
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7867 of file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing ( const ADC_TypeDef * ADCx )

Get ADC group injected conversion state.

Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group injected.

Definition at line 8040 of file stm32g4xx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing ( const ADC_TypeDef * ADCx )

Get ADC group injected command of conversion stop state.

Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group injected.

Definition at line 8051 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10 | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData10
JDR2 JDATA LL_ADC_INJ_ReadConversionData10
JDR3 JDATA LL_ADC_INJ_ReadConversionData10
JDR4 JDATA LL_ADC_INJ_ReadConversionData10
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 8129 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 8101 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 8073 of file stm32g4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6 | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData6
JDR2 JDATA LL_ADC_INJ_ReadConversionData6
JDR3 JDATA LL_ADC_INJ_ReadConversionData6
JDR4 JDATA LL_ADC_INJ_ReadConversionData6
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 8185 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8 | ( | const ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData8
JDR2 JDATA LL_ADC_INJ_ReadConversionData8
JDR3 JDATA LL_ADC_INJ_ReadConversionData8
JDR4 JDATA LL_ADC_INJ_ReadConversionData8
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 8157 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 series, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group injected, without conversion stop command on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8004 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE void LL_ADC_INJ_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8024 of file stm32g4xx_ll_adc.h.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (const ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (const ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (const ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (const ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (const ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY ( ADC_TypeDef * ADCx )

Clear flag ADC ready.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_ClearFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8336 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8424 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD2 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_ClearFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8435 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD3 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_ClearFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8446 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_EOC ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_ClearFlag_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8347 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8358 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_ClearFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8380 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOC ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_ClearFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8391 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8402 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF ( ADC_TypeDef * ADCx )

Clear flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_ClearFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8413 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_ClearFlag_OVR ( ADC_TypeDef * ADCx )

Clear flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_ClearFlag_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8369 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY ( const ADC_TypeDef * ADCx )

Get flag ADC ready.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8212 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( const ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8300 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2 ( const ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_IsActiveFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8311 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3 ( const ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_IsActiveFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8322 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC ( const ADC_TypeDef * ADCx )

Get flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_IsActiveFlag_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8223 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( const ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8234 of file stm32g4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP ( const ADC_TypeDef * ADCx )

Get flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8256 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC ( const ADC_TypeDef * ADCx )

Get flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_IsActiveFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8267 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( const ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8278 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF ( const ADC_TypeDef * ADCx )

Get flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8289 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC master.

Reference Manual to LL API cross reference:
CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8459 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 1 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8651 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8675 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8699 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8483 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8507 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC master.

Reference Manual to LL API cross reference:
CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8555 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8579 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_OVR_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8603 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC master.

Reference Manual to LL API cross reference:
CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8627 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC master.

Reference Manual to LL API cross reference:
CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8531 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR ( const ADC_TypeDef * ADCx )

Get flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_IsActiveFlag_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8245 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC slave.

Reference Manual to LL API cross reference:
CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8471 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode analog watchdog 1 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8663 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8687 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3 ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8711 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8495 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8519 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8567 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8591 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_OVR_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8615 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC slave.

Reference Manual to LL API cross reference:
CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8639 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR ( const ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC slave.

Reference Manual to LL API cross reference:
CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 8543 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (const ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (const ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (const ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (const ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_ADRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_DisableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8852 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_DisableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8940 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD2 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_DisableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8951 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD3 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_DisableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8962 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_EOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_DisableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8863 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8874 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_EOSMP ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_DisableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8896 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_JEOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_DisableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8907 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_DisableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8918 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_JQOVF ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_DisableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8929 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_OVR ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_DisableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8885 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_ADRDY ( ADC_TypeDef * ADCx )

Enable ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_EnableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8731 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2_SLV.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8819 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD2 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_EnableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8830 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD3 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_EnableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8841 of file stm32g4xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_EOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_EnableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8742 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8753 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_EOSMP ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_EnableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8775 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_EnableIT_JEOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_EnableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8786 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8797 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_JQOVF ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_EnableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8808 of file stm32g4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_OVR ( ADC_TypeDef * ADCx )

Enable ADC group regular interruption overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_EnableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 8764 of file stm32g4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY ( const ADC_TypeDef * ADCx )

Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8974 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( const ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_IsEnabledIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9070 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2 ( const ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_IsEnabledIT_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9082 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3 ( const ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_IsEnabledIT_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9094 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_IsEnabledIT_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8986 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 8998 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9022 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_IsEnabledIT_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9034 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_IsEnabledIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9046 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9058 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR ( const ADC_TypeDef * ADCx )

Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_IsEnabledIT_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 9010 of file stm32g4xx_ll_adc.h.

References LL_ADC_IT_AWD3.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (const ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( const ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Note:
This function is performing a hard reset, using high level clock source RCC ADC reset. Caution: On this STM32 series, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. To de-initialize only 1 ADC instance, use function LL_ADC_DeInit().
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 657 of file stm32g4xx_ll_adc.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_ADC12, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | const LL_ADC_CommonInitTypeDef * | pADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
pADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 699 of file stm32g4xx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, LL_ADC_CommonInitTypeDef::CommonClock, IS_LL_ADC_COMMON_CLOCK, IS_LL_ADC_MULTI_DMA_TRANSFER, IS_LL_ADC_MULTI_MODE, IS_LL_ADC_MULTI_TWOSMP_DELAY, LL_ADC_MULTI_INDEPENDENT, LL_ADC_SetCommonClock(), LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
pADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 781 of file stm32g4xx_ll_adc.c.

References LL_ADC_CommonInitTypeDef::CommonClock, LL_ADC_CLOCK_SYNC_PCLK_DIV2, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE, LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
If this functions returns error status, it means that ADC instance is in an unknown state. In this case, perform a hard reset using high level clock source RCC ADC reset. Caution: On this STM32 series, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. Refer to function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 814 of file stm32g4xx_ll_adc.c.

References ADC_TIMEOUT_DISABLE_CPU_CYCLES, ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES, assert_param, LL_ADC_Disable(), LL_ADC_FLAG_ADRDY, LL_ADC_FLAG_AWD1, LL_ADC_FLAG_AWD2, LL_ADC_FLAG_AWD3, LL_ADC_FLAG_EOC, LL_ADC_FLAG_EOS, LL_ADC_FLAG_EOSMP, LL_ADC_FLAG_JEOC, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JQOVF, LL_ADC_FLAG_OVR, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsStopConversionOngoing(), LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY, LL_ADC_INJ_SetQueueMode(), LL_ADC_INJ_StopConversion(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), LL_ADC_IT_ADRDY, LL_ADC_IT_AWD1, LL_ADC_IT_AWD2, LL_ADC_IT_AWD3, LL_ADC_IT_EOC, LL_ADC_IT_EOS, LL_ADC_IT_EOSMP, LL_ADC_IT_JEOC, LL_ADC_IT_JEOS, LL_ADC_IT_JQOVF, LL_ADC_IT_OVR, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsStopConversionOngoing(), and LL_ADC_REG_StopConversion().

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | const LL_ADC_InitTypeDef * | pADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 series). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
pADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1088 of file stm32g4xx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_LOW_POWER, IS_LL_ADC_RESOLUTION, LL_ADC_IsEnabled(), LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | const LL_ADC_INJ_InitTypeDef * | pADC_InjInitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Caution if feature ADC group injected contexts queue is enabled (refer to with function LL_ADC_INJ_SetQueueMode() ): using successively several times this function will appear as having no effect. To set several features of ADC group injected, use function LL_ADC_INJ_ConfigQueueContext().
Parameters:
ADCx | ADC instance
pADC_InjInitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1320 of file stm32g4xx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
pADC_InjInitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1391 of file stm32g4xx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | const LL_ADC_REG_InitTypeDef * | pADC_RegInitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 series. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
pADC_RegInitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 1176 of file stm32g4xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_OVR_DATA_BEHAVIOR, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * pADC_RegInitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
pADC_RegInitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1268 of file stm32g4xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_OVR_DATA_OVERWRITTEN, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * pADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
pADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1134 of file stm32g4xx_ll_adc.c.

References LL_ADC_InitTypeDef::DataAlignment, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_LP_MODE_NONE, LL_ADC_RESOLUTION_12B, LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
#define | LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
#define | LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 72 of file stm32g4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN

Definition at line 76 of file stm32g4xx_ll_bus.h.

Referenced by LL_CORDIC_DeInit().

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN

Definition at line 80 of file stm32g4xx_ll_bus.h.

Referenced by LL_CRC_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN

Definition at line 73 of file stm32g4xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN

Definition at line 74 of file stm32g4xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN

Definition at line 75 of file stm32g4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN

Definition at line 78 of file stm32g4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN

Definition at line 77 of file stm32g4xx_ll_bus.h.

Referenced by LL_FMAC_DeInit().

#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN

Definition at line 79 of file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2 GRP1 PERIPH

Defines
AHB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
#define | LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
#define | LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
#define | LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
#define | LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
#define | LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
#define | LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN

Define Documentation

#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN

Definition at line 98 of file stm32g4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 88 of file stm32g4xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN

Definition at line 96 of file stm32g4xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN

Definition at line 102 of file stm32g4xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN

Definition at line 106 of file stm32g4xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN

Definition at line 89 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN

Definition at line 90 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN

Definition at line 91 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN

Definition at line 92 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN

Definition at line 93 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN

Definition at line 94 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN

Definition at line 95 of file stm32g4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN

Definition at line 113 of file stm32g4xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN

Definition at line 97 of file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3 GRP1 PERIPH

Defines
AHB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU

Define Documentation

#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 121 of file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 135 of file stm32g4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN

Definition at line 144 of file stm32g4xx_ll_bus.h.

Referenced by LL_CRS_DeInit().

#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN

Definition at line 161 of file stm32g4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN

Definition at line 157 of file stm32g4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN

Definition at line 158 of file stm32g4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN

Definition at line 164 of file stm32g4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Definition at line 165 of file stm32g4xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN

Definition at line 163 of file stm32g4xx_ll_bus.h.

Referenced by LL_PWR_DeInit().

#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN

Definition at line 145 of file stm32g4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN

Definition at line 147 of file stm32g4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN

Definition at line 148 of file stm32g4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN

Definition at line 136 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN

Definition at line 137 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN

Definition at line 138 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN

Definition at line 142 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN

Definition at line 143 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN

Definition at line 152 of file stm32g4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN

Definition at line 149 of file stm32g4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN

Definition at line 150 of file stm32g4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN

Definition at line 159 of file stm32g4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN

Definition at line 146 of file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1 GRP2 PERIPH

Defines
APB1 GRP2 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN

Define Documentation

#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU

Definition at line 174 of file stm32g4xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN

Definition at line 175 of file stm32g4xx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN

Definition at line 179 of file stm32g4xx_ll_bus.h.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 187 of file stm32g4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Definition at line 202 of file stm32g4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 190 of file stm32g4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN

Definition at line 188 of file stm32g4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN

Definition at line 189 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN

Definition at line 196 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN

Definition at line 197 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN

Definition at line 198 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN

Definition at line 191 of file stm32g4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 192 of file stm32g4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock
AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock
AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 295 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 401 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock
AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock
AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 243 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 371 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset
AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 320 of file stm32g4xx_ll_bus.h.

Referenced by LL_CORDIC_DeInit(), LL_CRC_DeInit(), LL_DMA_DeInit(), and LL_FMAC_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
State of Periphs (1 or 0).

Definition at line 271 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CORDIC
  • LL_AHB1_GRP1_PERIPH_FMAC
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
Return values:
None

Definition at line 345 of file stm32g4xx_ll_bus.h.

Referenced by LL_CORDIC_DeInit(), LL_CRC_DeInit(), LL_DMA_DeInit(), and LL_FMAC_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB2

Functions
AHB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB2 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock
AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock
AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock
AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock
AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock
AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock
AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock
AHB2ENR AESEN LL_AHB2_GRP1_DisableClock
AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 539 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_CCM
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 719 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock
AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock
AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock
AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock
AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock
AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock
AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock
AHB2ENR AESEN LL_AHB2_GRP1_EnableClock
AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 451 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_CCM
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 669 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset ( uint32_t Periphs )

Force AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset
AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset
AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset
AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset
AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset
AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 581 of file stm32g4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_DAC_DeInit(), LL_GPIO_DeInit(), and LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 497 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOF
  • LL_AHB2_GRP1_PERIPH_GPIOG
  • LL_AHB2_GRP1_PERIPH_ADC12
  • LL_AHB2_GRP1_PERIPH_ADC345 (*)
  • LL_AHB2_GRP1_PERIPH_DAC1
  • LL_AHB2_GRP1_PERIPH_DAC2 (*)
  • LL_AHB2_GRP1_PERIPH_DAC3
  • LL_AHB2_GRP1_PERIPH_DAC4 (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 623 of file stm32g4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_DAC_DeInit(), LL_GPIO_DeInit(), and LL_RNG_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB3

Functions
AHB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB3 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB3_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 779 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB3 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep
AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 849 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 743 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB3 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep
AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 829 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ForceReset ( uint32_t Periphs )

Force AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 796 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 763 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 813 of file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock
APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock
APB1ENR1 USBEN LL_APB1_GRP1_DisableClock
APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock
APB1ENR1 PWREN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1069 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1365 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock
APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock
APB1ENR1 USBEN LL_APB1_GRP1_EnableClock
APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock
APB1ENR1 PWREN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 913 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1283 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset
APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1139 of file stm32g4xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 995 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_FDCAN (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1209 of file stm32g4xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock
APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock
APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1
(*) value not defined in all devices.
Return values:
None

Definition at line 1087 of file stm32g4xx_ll_bus.h.

Referenced by LL_UCPD_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep ( uint32_t Periphs )

Disable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1383 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock
APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock
APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1
(*) value not defined in all devices.
Return values:
None

Definition at line 935 of file stm32g4xx_ll_bus.h.

Referenced by LL_UCPD_Init().

__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep ( uint32_t Periphs )

Enable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1305 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset
APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1
(*) value not defined in all devices.
Return values:
None

Definition at line 1157 of file stm32g4xx_ll_bus.h.

Referenced by LL_I2C_DeInit(), LL_LPUART_DeInit(), and LL_UCPD_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 1013 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_I2C4 (*)
  • LL_APB1_GRP2_PERIPH_UCPD1
(*) value not defined in all devices.
Return values:
None

Definition at line 1227 of file stm32g4xx_ll_bus.h.

Referenced by LL_I2C_DeInit(), LL_LPUART_DeInit(), and LL_UCPD_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM8EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI4EN LL_APB2_GRP1_DisableClock
APB2ENR TIM15EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR TIM20EN LL_APB2_GRP1_DisableClock
APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1503 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1651 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM8EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI4EN LL_APB2_GRP1_EnableClock
APB2ENR TIM15EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR TIM20EN LL_APB2_GRP1_EnableClock
APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1427 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1611 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1539 of file stm32g4xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 1467 of file stm32g4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_SPI4 (*)
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_TIM20 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_HRTIM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1575 of file stm32g4xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Private Macros

Defines
COMP Private Macros
COMP

Defines

#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)

Define Documentation

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                         \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_10MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_20MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_30MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_40MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_50MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_60MV)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_70MV)                      \
  )

Definition at line 122 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)  ||                   \
   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)  ||                   \
   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)  ||                   \
   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)     ||                   \
   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)         ||                   \
   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)         ||                   \
   (((__COMP_INSTANCE__) == COMP1)                        &&                   \
    (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
     ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
   )                                                      ||                   \
   (((__COMP_INSTANCE__) == COMP2)                        &&                   \
    (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)  ||                   \
     ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
   )                                                      ||                   \
   (((__COMP_INSTANCE__) == COMP3)                        &&                   \
    (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
     ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
   )                                                      ||                   \
   (((__COMP_INSTANCE__) == COMP4)                        &&                   \
    (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
     ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
   ))

Definition at line 97 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                                \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
  )

Definition at line 56 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE | ( | __INSTANCE__,
 |  | __OUTPUT_BLANKING_SOURCE__
 | ) |
Value:
((((__INSTANCE__) == COMP1) &&                                                  \
    (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1)))       \
   ||                                                                             \
   (((__INSTANCE__) == COMP2) &&                                                  \
    (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)))       \
   ||                                                                             \
   (((__INSTANCE__) == COMP3) &&                                                  \
    (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3)))       \
   ||                                                                             \
   (((__INSTANCE__) == COMP4) &&                                                  \
    (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||     \
     ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)))      \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)             \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3)              \
  )

Definition at line 193 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                           \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 133 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_Init().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32g4xx_ll_comp.h>

Data Fields

uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputPolarity
uint32_t | OutputBlankingSource

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 62 of file stm32g4xx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 74 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 69 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 64 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputBlankingSource

Set comparator blanking source. This parameter can be a value of Comparator output - Blanking source This feature can be modified afterwards using unitary function LL_COMP_SetOutputBlankingSource().

Definition at line 84 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 79 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_comp.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)

Define Documentation

#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 104 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)

Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 105 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 114 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 113 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 115 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 117 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 118 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 119 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 120 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 121 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 122 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet

Definition at line 123 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 124 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 125 of file stm32g4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 116 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )
#define | LL_COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_LOW LL_COMP_HYSTERESIS_10MV
#define | LL_COMP_HYSTERESIS_MEDIUM LL_COMP_HYSTERESIS_40MV
#define | LL_COMP_HYSTERESIS_HIGH LL_COMP_HYSTERESIS_70MV

Define Documentation

#define LL_COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)

Hysteresis level 10mV

Definition at line 135 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )

Hysteresis level 20mV

Definition at line 136 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level 30mV

Definition at line 137 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )

Hysteresis level 40mV

Definition at line 138 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)

Hysteresis level 50mV

Definition at line 139 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )

Hysteresis level 60mV

Definition at line 140 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level 70mV

Definition at line 141 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_HIGH LL_COMP_HYSTERESIS_70MV

Hysteresis level high

Definition at line 144 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW LL_COMP_HYSTERESIS_10MV

Hysteresis level low

Definition at line 142 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM LL_COMP_HYSTERESIS_40MV

Hysteresis level medium

Definition at line 143 of file stm32g4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 134 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 153 of file stm32g4xx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 152 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator output - Blanking source

Defines
Comparator output - Blanking source
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Define Documentation

#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 161 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM15 OC1 (Common to all COMP instances).

Definition at line 191 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet

Definition at line 187 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet

Definition at line 188 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 189 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet

Definition at line 162 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet

Definition at line 163 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet

Definition at line 164 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet

Definition at line 165 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet

Definition at line 166 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet

Definition at line 167 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 168 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM20 OC5 (Common to all COMP instances). Note: For TIM20 instance availability, please refer to datasheet

Definition at line 190 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet

Definition at line 169 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet

Definition at line 170 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet

Definition at line 171 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet

Definition at line 172 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet

Definition at line 173 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet

Definition at line 174 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet

Definition at line 175 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet

Definition at line 176 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet

Definition at line 177 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 178 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet

Definition at line 179 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)

Comparator output blanking source TIM4 OC3 (Common to all COMP instances).

Definition at line 192 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet

Definition at line 180 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet

Definition at line 181 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet

Definition at line 182 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet

Definition at line 183 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet

Definition at line 184 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet

Definition at line 185 of file stm32g4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet

Definition at line 186 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 202 of file stm32g4xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 201 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ( 5UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Detailed Description

Note:
Only COMP peripheral HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ( 5UL)

Delay for COMP startup time

Definition at line 220 of file stm32g4xx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 228 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 261 of file stm32g4xx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 253 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_DeInit().

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP helper macro

COMP helper macro
COMP Exported Macros
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (const COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (const COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (const COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 series, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_ConfigInputs
CSR INPSEL LL_COMP_ConfigInputs
CSR BRGEN LL_COMP_ConfigInputs
CSR SCALEN LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
  • LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
  • LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
  • LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
  • LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
  • LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
  • LL_COMP_INPUT_MINUS_DAC4_CH2 (6) (a,b...) Only available for COMPa, COMPb... For COMPx & DACx instances availability, please refer to datasheet
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
Return values:
None

Definition at line 330 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( const COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_10MV
  • LL_COMP_HYSTERESIS_20MV
  • LL_COMP_HYSTERESIS_30MV
  • LL_COMP_HYSTERESIS_40MV
  • LL_COMP_HYSTERESIS_50MV
  • LL_COMP_HYSTERESIS_60MV
  • LL_COMP_HYSTERESIS_70MV

Definition at line 482 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( const COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_GetInputMinus
CSR BRGEN LL_COMP_GetInputMinus
CSR SCALEN LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
  • LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
  • LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
  • LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
  • LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
  • LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
  • LL_COMP_INPUT_MINUS_DAC4_CH2 (6) (a,b...) Only available for COMPa, COMPb... For COMPx & DACx instances availability, please refer to datasheet
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2

Definition at line 440 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( const COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2

Definition at line 365 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_10MV
  • LL_COMP_HYSTERESIS_20MV
  • LL_COMP_HYSTERESIS_30MV
  • LL_COMP_HYSTERESIS_40MV
  • LL_COMP_HYSTERESIS_50MV
  • LL_COMP_HYSTERESIS_60MV
  • LL_COMP_HYSTERESIS_70MV
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 463 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 series, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_SetInputMinus
CSR BRGEN LL_COMP_SetInputMinus
CSR SCALEN LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
  • LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
  • LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
  • LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
  • LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
  • LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
  • LL_COMP_INPUT_MINUS_DAC4_CH2 (6) (a,b...) Only available for COMPa, COMPb... For COMPx & DACx instances availability, please refer to datasheet
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
Return values:
None

Definition at line 409 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
Return values:
None

Definition at line 349 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (const COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (const COMP_TypeDef *COMPx)
Get comparator instance blanking source.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource ( const COMP_TypeDef * COMPx )

Get comparator instance blanking source.

Note:
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_GetOutputBlankingSource
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
  • LL_COMP_BLANKINGSRC_TIM20_OC5
  • LL_COMP_BLANKINGSRC_TIM15_OC1
  • LL_COMP_BLANKINGSRC_TIM4_OC3
On STM32G4 series, blanking sources are linked to COMP instance (except those without COMPx suffix that are common to all instances) Note: For COMPx & TIMx instances availability, please refer to datasheet

Definition at line 620 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( const COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 517 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputBlankingSource | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | BlankingSource
 | ) |  |

Set comparator instance blanking source.

Note:
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_SetOutputBlankingSource
Parameters:
COMPx Comparator instance
BlankingSource This parameter can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
  • LL_COMP_BLANKINGSRC_TIM20_OC5
  • LL_COMP_BLANKINGSRC_TIM15_OC1
  • LL_COMP_BLANKINGSRC_TIM4_OC3
On STM32G4 series, blanking sources are linked to COMP instance (except those without COMPx suffix that are common to all instances) Note: For COMPx & TIMx instances availability, please refer to datasheet
Return values:
None

Definition at line 569 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 504 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (const COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (const COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (const COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CSR EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 653 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CSR EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 642 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( const COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CSR EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 665 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( const COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 692 of file stm32g4xx_ll_comp.h.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 678 of file stm32g4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( const COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
On this STM32 series, comparator 'value' is taken before polarity and blanking are applied, thus:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CSR VALUE LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 711 of file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 285 of file stm32g4xx_ll_comp.c.

References assert_param, LL_COMP_IsLocked(), and LL_COMP_WriteReg.

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | const LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 322 of file stm32g4xx_ll_comp.c.

References assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_BLANKING_SOURCE, IS_LL_COMP_OUTPUT_POLARITY, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputBlankingSource, and LL_COMP_InitTypeDef::OutputPolarity.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct Pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 376 of file stm32g4xx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_BLANKINGSRC_NONE, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_InitTypeDef::OutputBlankingSource, and LL_COMP_InitTypeDef::OutputPolarity.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
CORDIC Exported Constants

Flags defines which can be used with LL_CORDIC_ReadReg function. More...

Defines

#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY

Detailed Description

Flags defines which can be used with LL_CORDIC_ReadReg function.

Define Documentation

#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY

Definition at line 57 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
CORDIC Exported Constants

IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions. More...

Defines

#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN

Detailed Description

IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.

Define Documentation

#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN

Result Ready interrupt enable

Definition at line 66 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FUNCTION

Defines
FUNCTION
CORDIC Exported Constants

Defines

#define | LL_CORDIC_FUNCTION_COSINE (0x00000000U)
#define | LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))
#define | LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))
#define | LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))
#define | LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))
#define | LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))

Define Documentation

#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))

Arctangent

Definition at line 78 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_COSINE (0x00000000U)

Cosine

Definition at line 74 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))

Hyperbolic Arctangent

Definition at line 81 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))

Hyperbolic Cosine

Definition at line 79 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))

Hyperbolic Sine

Definition at line 80 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))

Modulus

Definition at line 77 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))

Natural Logarithm

Definition at line 82 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))

Phase

Definition at line 76 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))

Sine

Definition at line 75 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))

Square Root

Definition at line 83 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PRECISION

Defines
PRECISION
CORDIC Exported Constants

Defines

#define | LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define | LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_7CYCLES
#define | LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define | LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_11CYCLES
#define | LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define | LL_CORDIC_PRECISION_13CYCLES
#define | LL_CORDIC_PRECISION_14CYCLES
#define | LL_CORDIC_PRECISION_15CYCLES

Define Documentation

#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))

Definition at line 101 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_11CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                       | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 102 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))

Definition at line 104 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_13CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                       | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))

Definition at line 105 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_14CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                       | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))

Definition at line 107 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_15CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_3\
                                                       | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
                                                       | CORDIC_CSR_PRECISION_0))

Definition at line 109 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))

Definition at line 91 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))

Definition at line 92 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 93 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))

Definition at line 94 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))

Definition at line 95 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))

Definition at line 96 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_7CYCLES
Value:
((uint32_t)(CORDIC_CSR_PRECISION_2\
                                                       | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))

Definition at line 97 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))

Definition at line 99 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))

Definition at line 100 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SCALE

Defines
SCALE
CORDIC Exported Constants

Defines

#define | LL_CORDIC_SCALE_0 (0x00000000U)
#define | LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define | LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define | LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define | LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Define Documentation

#define LL_CORDIC_SCALE_0 (0x00000000U)

Definition at line 119 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))

Definition at line 120 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))

Definition at line 121 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Definition at line 122 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))

Definition at line 123 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))

Definition at line 124 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))

Definition at line 125 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))

Definition at line 126 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: NBWRITE

Defines
NBWRITE
CORDIC Exported Constants

Defines

#define | LL_CORDIC_NBWRITE_1 (0x00000000U)
#define | LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS

Define Documentation

#define LL_CORDIC_NBWRITE_1 (0x00000000U)

One 32-bits write containing either only one 32-bit data input (Q1.31 format), or two 16-bit data input (Q1.15 format) packed in one 32 bits Data

Definition at line 134 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS

Two 32-bit write containing two 32-bits data input (Q1.31 format)

Definition at line 138 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: NBREAD

Defines
NBREAD
CORDIC Exported Constants

Defines

#define | LL_CORDIC_NBREAD_1 (0x00000000U)
#define | LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES

Define Documentation

#define LL_CORDIC_NBREAD_1 (0x00000000U)

One 32-bits read containing either only one 32-bit data output (Q1.31 format), or two 16-bit data output (Q1.15 format) packed in one 32 bits Data

Definition at line 147 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES

Two 32-bit Data containing two 32-bits data output (Q1.31 format)

Definition at line 151 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: INSIZE

Defines
INSIZE
CORDIC Exported Constants

Defines

#define | LL_CORDIC_INSIZE_32BITS (0x00000000U)
#define | LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE

Define Documentation

#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE

16 bits input data size (Q1.15 format)

Definition at line 161 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_INSIZE_32BITS (0x00000000U)

32 bits input data size (Q1.31 format)

Definition at line 160 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OUTSIZE

Defines
OUTSIZE
CORDIC Exported Constants

Defines

#define | LL_CORDIC_OUTSIZE_32BITS (0x00000000U)
#define | LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE

Define Documentation

#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE

16 bits output data size (Q1.15 format)

Definition at line 170 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U)

32 bits output data size (Q1.31 format)

Definition at line 169 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA register data

Defines
DMA register data
CORDIC Exported Constants

Defines

#define | LL_CORDIC_DMA_REG_DATA_IN (0x00000000U)
#define | LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U)

Define Documentation

#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U)

Get address of input data register

Definition at line 178 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U)

Get address of output data register

Definition at line 179 of file stm32g4xx_ll_cordic.h.

Referenced by LL_CORDIC_DMA_GetRegAddr().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CORDIC Exported Macros

Defines

#define | LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CORDIC register.
#define | LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CORDIC register.

Define Documentation

#define LL_CORDIC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CORDIC register.

Parameters:
__INSTANCE__ | CORDIC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 212 of file stm32g4xx_ll_cordic.h.

#define LL_CORDIC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CORDIC register.

Parameters:
__INSTANCE__ | CORDIC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 204 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Configuration functions

Functions
CORDIC Configuration functions
CORDIC Exported Functions

Functions

__STATIC_INLINE void | LL_CORDIC_Config (CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
Configure the CORDIC processing.
__STATIC_INLINE void | LL_CORDIC_SetFunction (CORDIC_TypeDef *CORDICx, uint32_t Function)
Configure function.
__STATIC_INLINE uint32_t | LL_CORDIC_GetFunction (const CORDIC_TypeDef *CORDICx)
Return function.
__STATIC_INLINE void | LL_CORDIC_SetPrecision (CORDIC_TypeDef *CORDICx, uint32_t Precision)
Configure precision in cycles number.
__STATIC_INLINE uint32_t | LL_CORDIC_GetPrecision (const CORDIC_TypeDef *CORDICx)
Return precision in cycles number.
__STATIC_INLINE void | LL_CORDIC_SetScale (CORDIC_TypeDef *CORDICx, uint32_t Scale)
Configure scaling factor.
__STATIC_INLINE uint32_t | LL_CORDIC_GetScale (const CORDIC_TypeDef *CORDICx)
Return scaling factor.
__STATIC_INLINE void | LL_CORDIC_SetNbWrite (CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
Configure number of 32-bit write expected for one calculation.
__STATIC_INLINE uint32_t | LL_CORDIC_GetNbWrite (const CORDIC_TypeDef *CORDICx)
Return number of 32-bit write expected for one calculation.
__STATIC_INLINE void | LL_CORDIC_SetNbRead (CORDIC_TypeDef *CORDICx, uint32_t NbRead)
Configure number of 32-bit read expected after one calculation.
__STATIC_INLINE uint32_t | LL_CORDIC_GetNbRead (const CORDIC_TypeDef *CORDICx)
Return number of 32-bit read expected after one calculation.
__STATIC_INLINE void | LL_CORDIC_SetInSize (CORDIC_TypeDef *CORDICx, uint32_t InSize)
Configure width of input data.
__STATIC_INLINE uint32_t | LL_CORDIC_GetInSize (const CORDIC_TypeDef *CORDICx)
Return width of input data.
__STATIC_INLINE void | LL_CORDIC_SetOutSize (CORDIC_TypeDef *CORDICx, uint32_t OutSize)
Configure width of output data.
__STATIC_INLINE uint32_t | LL_CORDIC_GetOutSize (const CORDIC_TypeDef *CORDICx)
Return width of output data.

Function Documentation

__STATIC_INLINE void LL_CORDIC_Config | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | Function,
 |  | uint32_t | Precision,
 |  | uint32_t | Scale,
 |  | uint32_t | NbWrite,
 |  | uint32_t | NbRead,
 |  | uint32_t | InSize,
 |  | uint32_t | OutSize
 | ) |  |

Configure the CORDIC processing.

Note:
This function set all parameters of CORDIC processing. These parameters can also be set individually using dedicated functions:
  • LL_CORDIC_SetFunction()
  • LL_CORDIC_SetPrecision()
  • LL_CORDIC_SetScale()
  • LL_CORDIC_SetNbWrite()
  • LL_CORDIC_SetNbRead()
  • LL_CORDIC_SetInSize()
  • LL_CORDIC_SetOutSize()
Reference Manual to LL API cross reference:
CSR FUNC LL_CORDIC_Config
CSR PRECISION LL_CORDIC_Config
CSR SCALE LL_CORDIC_Config
CSR NARGS LL_CORDIC_Config
CSR NRES LL_CORDIC_Config
CSR ARGSIZE LL_CORDIC_Config
CSR RESIZE LL_CORDIC_Config
Parameters:
CORDICx CORDIC instance
Function parameter can be one of the following values:
  • LL_CORDIC_FUNCTION_COSINE
  • LL_CORDIC_FUNCTION_SINE
  • LL_CORDIC_FUNCTION_PHASE
  • LL_CORDIC_FUNCTION_MODULUS
  • LL_CORDIC_FUNCTION_ARCTANGENT
  • LL_CORDIC_FUNCTION_HCOSINE
  • LL_CORDIC_FUNCTION_HSINE
  • LL_CORDIC_FUNCTION_HARCTANGENT
  • LL_CORDIC_FUNCTION_NATURALLOG
  • LL_CORDIC_FUNCTION_SQUAREROOT
Precision parameter can be one of the following values:
  • LL_CORDIC_PRECISION_1CYCLE
  • LL_CORDIC_PRECISION_2CYCLES
  • LL_CORDIC_PRECISION_3CYCLES
  • LL_CORDIC_PRECISION_4CYCLES
  • LL_CORDIC_PRECISION_5CYCLES
  • LL_CORDIC_PRECISION_6CYCLES
  • LL_CORDIC_PRECISION_7CYCLES
  • LL_CORDIC_PRECISION_8CYCLES
  • LL_CORDIC_PRECISION_9CYCLES
  • LL_CORDIC_PRECISION_10CYCLES
  • LL_CORDIC_PRECISION_11CYCLES
  • LL_CORDIC_PRECISION_12CYCLES
  • LL_CORDIC_PRECISION_13CYCLES
  • LL_CORDIC_PRECISION_14CYCLES
  • LL_CORDIC_PRECISION_15CYCLES
Scale parameter can be one of the following values:
  • LL_CORDIC_SCALE_0
  • LL_CORDIC_SCALE_1
  • LL_CORDIC_SCALE_2
  • LL_CORDIC_SCALE_3
  • LL_CORDIC_SCALE_4
  • LL_CORDIC_SCALE_5
  • LL_CORDIC_SCALE_6
  • LL_CORDIC_SCALE_7
NbWrite parameter can be one of the following values:
  • LL_CORDIC_NBWRITE_1
  • LL_CORDIC_NBWRITE_2
NbRead parameter can be one of the following values:
  • LL_CORDIC_NBREAD_1
  • LL_CORDIC_NBREAD_2
InSize parameter can be one of the following values:
  • LL_CORDIC_INSIZE_32BITS
  • LL_CORDIC_INSIZE_16BITS
OutSize parameter can be one of the following values:
  • LL_CORDIC_OUTSIZE_32BITS
  • LL_CORDIC_OUTSIZE_16BITS
Return values:
None

Definition at line 302 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetFunction ( const CORDIC_TypeDef * CORDICx )

Return function.

Reference Manual to LL API cross reference:
CSR FUNC LL_CORDIC_GetFunction
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_FUNCTION_COSINE
  • LL_CORDIC_FUNCTION_SINE
  • LL_CORDIC_FUNCTION_PHASE
  • LL_CORDIC_FUNCTION_MODULUS
  • LL_CORDIC_FUNCTION_ARCTANGENT
  • LL_CORDIC_FUNCTION_HCOSINE
  • LL_CORDIC_FUNCTION_HSINE
  • LL_CORDIC_FUNCTION_HARCTANGENT
  • LL_CORDIC_FUNCTION_NATURALLOG
  • LL_CORDIC_FUNCTION_SQUAREROOT

Definition at line 350 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetInSize ( const CORDIC_TypeDef * CORDICx )

Return width of input data.

Reference Manual to LL API cross reference:
CSR ARGSIZE LL_CORDIC_GetInSize
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_INSIZE_32BITS
  • LL_CORDIC_INSIZE_16BITS

Definition at line 523 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead ( const CORDIC_TypeDef * CORDICx )

Return number of 32-bit read expected after one calculation.

Reference Manual to LL API cross reference:
CSR NRES LL_CORDIC_GetNbRead
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_NBREAD_1
  • LL_CORDIC_NBREAD_2

Definition at line 496 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite ( const CORDIC_TypeDef * CORDICx )

Return number of 32-bit write expected for one calculation.

Reference Manual to LL API cross reference:
CSR NARGS LL_CORDIC_GetNbWrite
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_NBWRITE_1
  • LL_CORDIC_NBWRITE_2

Definition at line 469 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize ( const CORDIC_TypeDef * CORDICx )

Return width of output data.

Reference Manual to LL API cross reference:
CSR RESIZE LL_CORDIC_GetOutSize
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_OUTSIZE_32BITS
  • LL_CORDIC_OUTSIZE_16BITS

Definition at line 550 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision ( const CORDIC_TypeDef * CORDICx )

Return precision in cycles number.

Reference Manual to LL API cross reference:
CSR PRECISION LL_CORDIC_GetPrecision
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_PRECISION_1CYCLE
  • LL_CORDIC_PRECISION_2CYCLES
  • LL_CORDIC_PRECISION_3CYCLES
  • LL_CORDIC_PRECISION_4CYCLES
  • LL_CORDIC_PRECISION_5CYCLES
  • LL_CORDIC_PRECISION_6CYCLES
  • LL_CORDIC_PRECISION_7CYCLES
  • LL_CORDIC_PRECISION_8CYCLES
  • LL_CORDIC_PRECISION_9CYCLES
  • LL_CORDIC_PRECISION_10CYCLES
  • LL_CORDIC_PRECISION_11CYCLES
  • LL_CORDIC_PRECISION_12CYCLES
  • LL_CORDIC_PRECISION_13CYCLES
  • LL_CORDIC_PRECISION_14CYCLES
  • LL_CORDIC_PRECISION_15CYCLES

Definition at line 403 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_GetScale ( const CORDIC_TypeDef * CORDICx )

Return scaling factor.

Reference Manual to LL API cross reference:
CSR SCALE LL_CORDIC_GetScale
Parameters:
CORDICx CORDIC Instance
Return values:
Returned value can be one of the following values:
  • LL_CORDIC_SCALE_0
  • LL_CORDIC_SCALE_1
  • LL_CORDIC_SCALE_2
  • LL_CORDIC_SCALE_3
  • LL_CORDIC_SCALE_4
  • LL_CORDIC_SCALE_5
  • LL_CORDIC_SCALE_6
  • LL_CORDIC_SCALE_7

Definition at line 442 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetFunction | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | Function
 | ) |  |

Configure function.

Reference Manual to LL API cross reference:
CSR FUNC LL_CORDIC_SetFunction
Parameters:
CORDICx CORDIC Instance
Function parameter can be one of the following values:
  • LL_CORDIC_FUNCTION_COSINE
  • LL_CORDIC_FUNCTION_SINE
  • LL_CORDIC_FUNCTION_PHASE
  • LL_CORDIC_FUNCTION_MODULUS
  • LL_CORDIC_FUNCTION_ARCTANGENT
  • LL_CORDIC_FUNCTION_HCOSINE
  • LL_CORDIC_FUNCTION_HSINE
  • LL_CORDIC_FUNCTION_HARCTANGENT
  • LL_CORDIC_FUNCTION_NATURALLOG
  • LL_CORDIC_FUNCTION_SQUAREROOT
Return values:
None

Definition at line 329 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetInSize | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | InSize
 | ) |  |

Configure width of input data.

Reference Manual to LL API cross reference:
CSR ARGSIZE LL_CORDIC_SetInSize
Parameters:
CORDICx CORDIC Instance
InSize parameter can be one of the following values:
  • LL_CORDIC_INSIZE_32BITS
  • LL_CORDIC_INSIZE_16BITS
Return values:
None

Definition at line 510 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetNbRead | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | NbRead
 | ) |  |

Configure number of 32-bit read expected after one calculation.

Reference Manual to LL API cross reference:
CSR NRES LL_CORDIC_SetNbRead
Parameters:
CORDICx CORDIC Instance
NbRead parameter can be one of the following values:
  • LL_CORDIC_NBREAD_1
  • LL_CORDIC_NBREAD_2
Return values:
None

Definition at line 483 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetNbWrite | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | NbWrite
 | ) |  |

Configure number of 32-bit write expected for one calculation.

Reference Manual to LL API cross reference:
CSR NARGS LL_CORDIC_SetNbWrite
Parameters:
CORDICx CORDIC Instance
NbWrite parameter can be one of the following values:
  • LL_CORDIC_NBWRITE_1
  • LL_CORDIC_NBWRITE_2
Return values:
None

Definition at line 456 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetOutSize | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | OutSize
 | ) |  |

Configure width of output data.

Reference Manual to LL API cross reference:
CSR RESIZE LL_CORDIC_SetOutSize
Parameters:
CORDICx CORDIC Instance
OutSize parameter can be one of the following values:
  • LL_CORDIC_OUTSIZE_32BITS
  • LL_CORDIC_OUTSIZE_16BITS
Return values:
None

Definition at line 537 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetPrecision | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | Precision
 | ) |  |

Configure precision in cycles number.

Reference Manual to LL API cross reference:
CSR PRECISION LL_CORDIC_SetPrecision
Parameters:
CORDICx CORDIC Instance
Precision parameter can be one of the following values:
  • LL_CORDIC_PRECISION_1CYCLE
  • LL_CORDIC_PRECISION_2CYCLES
  • LL_CORDIC_PRECISION_3CYCLES
  • LL_CORDIC_PRECISION_4CYCLES
  • LL_CORDIC_PRECISION_5CYCLES
  • LL_CORDIC_PRECISION_6CYCLES
  • LL_CORDIC_PRECISION_7CYCLES
  • LL_CORDIC_PRECISION_8CYCLES
  • LL_CORDIC_PRECISION_9CYCLES
  • LL_CORDIC_PRECISION_10CYCLES
  • LL_CORDIC_PRECISION_11CYCLES
  • LL_CORDIC_PRECISION_12CYCLES
  • LL_CORDIC_PRECISION_13CYCLES
  • LL_CORDIC_PRECISION_14CYCLES
  • LL_CORDIC_PRECISION_15CYCLES
Return values:
None

Definition at line 377 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_SetScale | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | Scale
 | ) |  |

Configure scaling factor.

Reference Manual to LL API cross reference:
CSR SCALE LL_CORDIC_SetScale
Parameters:
CORDICx CORDIC Instance
Scale parameter can be one of the following values:
  • LL_CORDIC_SCALE_0
  • LL_CORDIC_SCALE_1
  • LL_CORDIC_SCALE_2
  • LL_CORDIC_SCALE_3
  • LL_CORDIC_SCALE_4
  • LL_CORDIC_SCALE_5
  • LL_CORDIC_SCALE_6
  • LL_CORDIC_SCALE_7
Return values:
None

Definition at line 423 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
CORDIC Exported Functions

Functions

__STATIC_INLINE void | LL_CORDIC_EnableIT (CORDIC_TypeDef *CORDICx)
Enable CORDIC result ready interrupt.
__STATIC_INLINE void | LL_CORDIC_DisableIT (CORDIC_TypeDef *CORDICx)
Disable CORDIC result ready interrupt.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledIT (const CORDIC_TypeDef *CORDICx)
Check CORDIC result ready interrupt state.

Function Documentation

__STATIC_INLINE void LL_CORDIC_DisableIT ( CORDIC_TypeDef * CORDICx )

Disable CORDIC result ready interrupt.

Reference Manual to LL API cross reference:
CSR IEN LL_CORDIC_DisableIT
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 580 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_EnableIT ( CORDIC_TypeDef * CORDICx )

Enable CORDIC result ready interrupt.

Reference Manual to LL API cross reference:
CSR IEN LL_CORDIC_EnableIT
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 569 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT ( const CORDIC_TypeDef * CORDICx )

Check CORDIC result ready interrupt state.

Reference Manual to LL API cross reference:
CSR IEN LL_CORDIC_IsEnabledIT
Parameters:
CORDICx CORDIC Instance
Return values:
State of bit (1 or 0).

Definition at line 591 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA_Management

Functions
DMA_Management
CORDIC Exported Functions

Functions

__STATIC_INLINE void | LL_CORDIC_EnableDMAReq_RD (CORDIC_TypeDef *CORDICx)
Enable CORDIC DMA read channel request.
__STATIC_INLINE void | LL_CORDIC_DisableDMAReq_RD (CORDIC_TypeDef *CORDICx)
Disable CORDIC DMA read channel request.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledDMAReq_RD (const CORDIC_TypeDef *CORDICx)
Check CORDIC DMA read channel request state.
__STATIC_INLINE void | LL_CORDIC_EnableDMAReq_WR (CORDIC_TypeDef *CORDICx)
Enable CORDIC DMA write channel request.
__STATIC_INLINE void | LL_CORDIC_DisableDMAReq_WR (CORDIC_TypeDef *CORDICx)
Disable CORDIC DMA write channel request.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledDMAReq_WR (const CORDIC_TypeDef *CORDICx)
Check CORDIC DMA write channel request state.
__STATIC_INLINE uint32_t | LL_CORDIC_DMA_GetRegAddr (const CORDIC_TypeDef *CORDICx, uint32_t Direction)
Get the CORDIC data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD ( CORDIC_TypeDef * CORDICx )

Disable CORDIC DMA read channel request.

Reference Manual to LL API cross reference:
CSR DMAREN LL_CORDIC_DisableDMAReq_RD
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 621 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR ( CORDIC_TypeDef * CORDICx )

Disable CORDIC DMA write channel request.

Reference Manual to LL API cross reference:
CSR DMAWEN LL_CORDIC_DisableDMAReq_WR
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 654 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr | ( | const CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | Direction
 | ) |  |

Get the CORDIC data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDATA RES LL_CORDIC_DMA_GetRegAddr
Reference Manual to LL API cross reference:
WDATA ARG LL_CORDIC_DMA_GetRegAddr
Parameters:
CORDICx CORDIC Instance
Direction parameter can be one of the following values:
  • LL_CORDIC_DMA_REG_DATA_IN
  • LL_CORDIC_DMA_REG_DATA_OUT
Return values:
Address of data register

Definition at line 680 of file stm32g4xx_ll_cordic.h.

References LL_CORDIC_DMA_REG_DATA_OUT.

__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD ( CORDIC_TypeDef * CORDICx )

Enable CORDIC DMA read channel request.

Reference Manual to LL API cross reference:
CSR DMAREN LL_CORDIC_EnableDMAReq_RD
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 610 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR ( CORDIC_TypeDef * CORDICx )

Enable CORDIC DMA write channel request.

Reference Manual to LL API cross reference:
CSR DMAWEN LL_CORDIC_EnableDMAReq_WR
Parameters:
CORDICx CORDIC Instance
Return values:
None

Definition at line 643 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD ( const CORDIC_TypeDef * CORDICx )

Check CORDIC DMA read channel request state.

Reference Manual to LL API cross reference:
CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD
Parameters:
CORDICx CORDIC Instance
Return values:
State of bit (1 or 0).

Definition at line 632 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR ( const CORDIC_TypeDef * CORDICx )

Check CORDIC DMA write channel request state.

Reference Manual to LL API cross reference:
CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR
Parameters:
CORDICx CORDIC Instance
Return values:
State of bit (1 or 0).

Definition at line 665 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
CORDIC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY (const CORDIC_TypeDef *CORDICx)
Check CORDIC result ready flag state.

Function Documentation

__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY ( const CORDIC_TypeDef * CORDICx )

Check CORDIC result ready flag state.

Reference Manual to LL API cross reference:
CSR RRDY LL_CORDIC_IsActiveFlag_RRDY
Parameters:
CORDICx CORDIC Instance
Return values:
State of bit (1 or 0).

Definition at line 712 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
CORDIC Exported Functions

Functions

__STATIC_INLINE void | LL_CORDIC_WriteData (CORDIC_TypeDef *CORDICx, uint32_t InData)
Write 32-bit input data for the CORDIC processing.
__STATIC_INLINE uint32_t | LL_CORDIC_ReadData (const CORDIC_TypeDef *CORDICx)
Return 32-bit output data of CORDIC processing.

Function Documentation

__STATIC_INLINE uint32_t LL_CORDIC_ReadData ( const CORDIC_TypeDef * CORDICx )

Return 32-bit output data of CORDIC processing.

Reference Manual to LL API cross reference:
RDATA RES LL_CORDIC_ReadData
Parameters:
CORDICx CORDIC Instance
Return values:
32-bit output data of CORDIC processing.

Definition at line 743 of file stm32g4xx_ll_cordic.h.

__STATIC_INLINE void LL_CORDIC_WriteData | ( | CORDIC_TypeDef * | CORDICx,
 |  | uint32_t | InData
 | ) |  |

Write 32-bit input data for the CORDIC processing.

Reference Manual to LL API cross reference:
WDATA ARG LL_CORDIC_WriteData
Parameters:
CORDICx | CORDIC Instance
InData | 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
Return values:
None

Definition at line 732 of file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORDIC Exported Functions

Functions

ErrorStatus LL_CORDIC_DeInit (const CORDIC_TypeDef *CORDICx)
De-Initialize CORDIC peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_CORDIC_DeInit ( const CORDIC_TypeDef * CORDICx )

De-Initialize CORDIC peripheral registers to their default reset values.

Parameters:
CORDICx CORDIC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CORDIC registers are de-initialized
  • ERROR: CORDIC registers are not de-initialized

Definition at line 61 of file stm32g4xx_ll_cordic.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CORDIC, and LL_AHB1_GRP1_ReleaseReset().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 70 of file stm32g4xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 69 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 79 of file stm32g4xx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 80 of file stm32g4xx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 78 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 91 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 93 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U

Disable NMI and privileged SW access

Definition at line 90 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 92 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U

Define Documentation

#define LL_MPU_REGION_NUMBER0 0x00U

REGION Number 0

Definition at line 101 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 0x01U

REGION Number 1

Definition at line 102 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 0x02U

REGION Number 2

Definition at line 103 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 0x03U

REGION Number 3

Definition at line 104 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 0x04U

REGION Number 4

Definition at line 105 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 0x05U

REGION Number 5

Definition at line 106 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 0x06U

REGION Number 6

Definition at line 107 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 0x07U

REGION Number 7

Definition at line 108 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

Define Documentation

#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)

128B Size of the MPU protection region

Definition at line 118 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)

128KB Size of the MPU protection region

Definition at line 128 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)

128MB Size of the MPU protection region

Definition at line 138 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)

16KB Size of the MPU protection region

Definition at line 125 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)

16MB Size of the MPU protection region

Definition at line 135 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)

1GB Size of the MPU protection region

Definition at line 141 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)

1KB Size of the MPU protection region

Definition at line 121 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)

1MB Size of the MPU protection region

Definition at line 131 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)

256B Size of the MPU protection region

Definition at line 119 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)

256KB Size of the MPU protection region

Definition at line 129 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)

256MB Size of the MPU protection region

Definition at line 139 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)

2GB Size of the MPU protection region

Definition at line 142 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)

2KB Size of the MPU protection region

Definition at line 122 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)

2MB Size of the MPU protection region

Definition at line 132 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)

32B Size of the MPU protection region

Definition at line 116 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)

32KB Size of the MPU protection region

Definition at line 126 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)

32MB Size of the MPU protection region

Definition at line 136 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

4GB Size of the MPU protection region

Definition at line 143 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)

4KB Size of the MPU protection region

Definition at line 123 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)

4MB Size of the MPU protection region

Definition at line 133 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)

512B Size of the MPU protection region

Definition at line 120 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)

512KB Size of the MPU protection region

Definition at line 130 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)

512MB Size of the MPU protection region

Definition at line 140 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)

64B Size of the MPU protection region

Definition at line 117 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)

64KB Size of the MPU protection region

Definition at line 127 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)

64MB Size of the MPU protection region

Definition at line 137 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)

8KB Size of the MPU protection region

Definition at line 124 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)

8MB Size of the MPU protection region

Definition at line 134 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)

RW privileged & user (Full access)

Definition at line 154 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)

No access

Definition at line 151 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)

RO privileged (privileged read only)

Definition at line 155 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

RO privileged & user (read only)

Definition at line 156 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)

RW privileged (privileged access only)

Definition at line 152 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 153 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

Define Documentation

#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)

b000 for TEX bits

Definition at line 164 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)

b001 for TEX bits

Definition at line 165 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)

b010 for TEX bits

Definition at line 166 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

b100 for TEX bits

Definition at line 167 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 176 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U

Instruction fetches enabled

Definition at line 175 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Not Shareable memory attribute

Definition at line 185 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 184 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 193 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Not Cacheable memory attribute

Definition at line 194 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 202 of file stm32g4xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Not Bufferable memory attribute

Definition at line 203 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 281 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 271 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 261 of file stm32g4xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 229 of file stm32g4xx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 291 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 242 of file stm32g4xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 368 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 344 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 320 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 356 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 309 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 333 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 406 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 391 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetArchitecture (void)
Get Architecture number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture ( void )

Get Architecture number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
Return values:
Value should be equal to 0xF for Cortex-M4 devices

Definition at line 445 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 425 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC24 for Cortex-M4

Definition at line 455 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 465 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 435 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_32B or LL_MPU_REGION_SIZE_64B or LL_MPU_REGION_SIZE_128B or LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Return values:
None

Definition at line 582 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 504 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 607 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 489 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 536 of file stm32g4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 517 of file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 55 of file stm32g4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B 0x00000000U

32 bits Polynomial size

Definition at line 54 of file stm32g4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 57 of file stm32g4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 56 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 66 of file stm32g4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 67 of file stm32g4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U

Input Data bit order not affected

Definition at line 65 of file stm32g4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 68 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 77 of file stm32g4xx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U

Output Data bit order not affected

Definition at line 76 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Default CRC generating polynomial value

Definition at line 87 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 95 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 128 of file stm32g4xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, __VALUE__)

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 120 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (const CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (const CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (const CRC_TypeDef *CRCx)
Return type of reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (const CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (const CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( const CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 273 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( const CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 218 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( const CRC_TypeDef * CRCx )

Return type of reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 245 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( const CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 304 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( const CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 187 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 156 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 260 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 203 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 232 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 290 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 172 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (const CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 336 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 324 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 351 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( const CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 32-bit data register).

Definition at line 410 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( const CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 374 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( const CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 362 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( const CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 398 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( const CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 386 of file stm32g4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 423 of file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (const CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( const CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 62 of file stm32g4xx_ll_crc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CRC, and LL_AHB1_GRP1_ReleaseReset().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
CRS Exported Constants

Flags defines which can be used with LL_CRS_ReadReg function. More...

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Detailed Description

Flags defines which can be used with LL_CRS_ReadReg function.

Define Documentation

#define LL_CRS_ISR_ERRF CRS_ISR_ERRF

Definition at line 57 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF

Definition at line 58 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR

Definition at line 59 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS

Definition at line 60 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF

Definition at line 55 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF

Definition at line 56 of file stm32g4xx_ll_crs.h.

#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Definition at line 61 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
CRS Exported Constants

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions. More...

Defines

#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Detailed Description

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Define Documentation

#define LL_CRS_CR_ERRIE CRS_CR_ERRIE

Definition at line 72 of file stm32g4xx_ll_crs.h.

#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Definition at line 73 of file stm32g4xx_ll_crs.h.

#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE

Definition at line 70 of file stm32g4xx_ll_crs.h.

#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE

Definition at line 71 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Synchronization Signal Divider

Defines
Synchronization Signal Divider
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U)
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Define Documentation

#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U)

Synchro Signal not divided (default)

Definition at line 81 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 88 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 85 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 82 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 86 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 83 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 87 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 84 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Synchronization Signal Source

Defines
Synchronization Signal Source
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U)
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U)

Synchro Signal source GPIO

Definition at line 96 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 97 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 98 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U)
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 107 of file stm32g4xx_ll_crs.h.

#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U)

Synchro Active on rising edge (default)

Definition at line 106 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Frequency Error Direction

Defines
Frequency Error Direction
CRS Exported Constants

Defines

#define | LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U)
#define | LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR)

Define Documentation

#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR)

Downcounting direction, the actual frequency is below the target

Definition at line 116 of file stm32g4xx_ll_crs.h.

#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U)

Upcounting direction, the actual frequency is above the target

Definition at line 115 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Default Values

Defines
Default Values
CRS Exported Constants

Defines

#define | LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
Reset value of the HSI48 Calibration field.

Define Documentation

#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)

Reset value of Frequency error limit.

Definition at line 134 of file stm32g4xx_ll_crs.h.

#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)

Reset value of the HSI48 Calibration field.

Note:
The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency

Definition at line 142 of file stm32g4xx_ll_crs.h.

#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)

Reset value of the RELOAD field.

Note:
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB)

Definition at line 129 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRS Exported Macros

Defines

#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.

Define Documentation

#define LL_CRS_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 174 of file stm32g4xx_ll_crs.h.

#define LL_CRS_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 166 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Exported_Macros_Calculate_Reload

Defines
Exported_Macros_Calculate_Reload
CRS Exported Macros

Defines

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
Reload value (in Hz)

Definition at line 194 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.

Function Documentation

__STATIC_INLINE void LL_CRS_ConfigSynchronization | ( | uint32_t | HSI48CalibrationValue,
 |  | uint32_t | ErrorLimitValue,
 |  | uint32_t | ReloadValue,
 |  | uint32_t | Settings
 | ) |  |

Configure CRS for the synchronization.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_ConfigSynchronization
CFGR RELOAD LL_CRS_ConfigSynchronization
CFGR FELIM LL_CRS_ConfigSynchronization
CFGR SYNCDIV LL_CRS_ConfigSynchronization
CFGR SYNCSRC LL_CRS_ConfigSynchronization
CFGR SYNCPOL LL_CRS_ConfigSynchronization
Parameters:
HSI48CalibrationValue | a number between Min_Data = 0 and Max_Data = 63
ErrorLimitValue | a number between Min_Data = 0 and Max_Data = 0xFFFF
ReloadValue | a number between Min_Data = 0 and Max_Data = 255
Settings This parameter can be a combination of the following values:
  • LL_CRS_SYNC_DIV_1 or LL_CRS_SYNC_DIV_2 or LL_CRS_SYNC_DIV_4 or LL_CRS_SYNC_DIV_8 or LL_CRS_SYNC_DIV_16 or LL_CRS_SYNC_DIV_32 or LL_CRS_SYNC_DIV_64 or LL_CRS_SYNC_DIV_128
  • LL_CRS_SYNC_SOURCE_GPIO or LL_CRS_SYNC_SOURCE_LSE or LL_CRS_SYNC_SOURCE_USB
  • LL_CRS_SYNC_POLARITY_RISING or LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 449 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableAutoTrimming ( void )

Disable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
Return values:
None

Definition at line 259 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter ( void )

Disable Frequency error counter.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_DisableFreqErrorCounter
Return values:
None

Definition at line 229 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableAutoTrimming ( void )

Enable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
Return values:
None

Definition at line 249 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter ( void )

Enable Frequency error counter.

Note:
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
Reference Manual to LL API cross reference:
CR CEN LL_CRS_EnableFreqErrorCounter
Return values:
None

Definition at line 219 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit ( void )

Get frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_GetFreqErrorLimit
Return values:
A number between Min_Data = 0 and Max_Data = 255

Definition at line 337 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming ( void )

Get HSI48 oscillator smooth trimming.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_GetHSI48SmoothTrimming
Return values:
a number between Min_Data = 0 and Max_Data = 63

Definition at line 292 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter ( void )

Get counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_GetReloadCounter
Return values:
a number between Min_Data = 0 and Max_Data = 0xFFFF

Definition at line 315 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider ( void )

Get division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_GetSyncDivider
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128

Definition at line 374 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity ( void )

Get input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_GetSyncPolarity
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING

Definition at line 426 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource ( void )

Get SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_GetSyncSignalSource
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB

Definition at line 401 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming ( void )

Check if Automatic trimming is enabled or not.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
Return values:
State of bit (1 or 0).

Definition at line 269 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter ( void )

Check if Frequency error counter is enabled or not.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_IsEnabledFreqErrorCounter
Return values:
State of bit (1 or 0).

Definition at line 239 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetFreqErrorLimit ( uint32_t Value )

Set frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_SetFreqErrorLimit
Parameters:
Value a number between Min_Data = 0 and Max_Data = 255
Note:
Default value can be set thanks to LL_CRS_ERRORLIMIT_DEFAULT
Return values:
None

Definition at line 327 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming ( uint32_t Value )

Set HSI48 oscillator smooth trimming.

Note:
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
Reference Manual to LL API cross reference:
CR TRIM LL_CRS_SetHSI48SmoothTrimming
Parameters:
Value a number between Min_Data = 0 and Max_Data = 63
Note:
Default value can be set thanks to LL_CRS_HSI48CALIBRATION_DEFAULT
Return values:
None

Definition at line 282 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetReloadCounter ( uint32_t Value )

Set counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_SetReloadCounter
Parameters:
Value a number between Min_Data = 0 and Max_Data = 0xFFFF
Note:
Default value can be set thanks to LL_CRS_RELOADVALUE_DEFAULT Otherwise it can be calculated in using macro __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
Return values:
None

Definition at line 305 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncDivider ( uint32_t Divider )

Set division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_SetSyncDivider
Parameters:
Divider This parameter can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128
Return values:
None

Definition at line 356 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncPolarity ( uint32_t Polarity )

Set input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_SetSyncPolarity
Parameters:
Polarity This parameter can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 414 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncSignalSource ( uint32_t Source )

Set SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_SetSyncSignalSource
Parameters:
Source This parameter can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB
Return values:
None

Definition at line 388 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRS_Management

Functions
CRS_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.

Function Documentation

__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC ( void )

Generate software SYNC event.

Reference Manual to LL API cross reference:
CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
Return values:
None

Definition at line 471 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture ( void )

Get the frequency error counter value latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FECAP LL_CRS_GetFreqErrorCapture
Return values:
A number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 494 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection ( void )

Get the frequency error direction latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FEDIR LL_CRS_GetFreqErrorDirection
Return values:
Returned value can be one of the following values:
  • LL_CRS_FREQ_ERROR_DIR_UP
  • LL_CRS_FREQ_ERROR_DIR_DOWN

Definition at line 484 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
CRS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.

Function Documentation

__STATIC_INLINE void LL_CRS_ClearFlag_ERR ( void )

Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.

Reference Manual to LL API cross reference:
ICR ERRC LL_CRS_ClearFlag_ERR
Return values:
None

Definition at line 603 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC ( void )

Clear Expected SYNC flag.

Reference Manual to LL API cross reference:
ICR ESYNCC LL_CRS_ClearFlag_ESYNC
Return values:
None

Definition at line 613 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK ( void )

Clear the SYNC event OK flag.

Reference Manual to LL API cross reference:
ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
Return values:
None

Definition at line 582 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN ( void )

Clear the SYNC warning flag.

Reference Manual to LL API cross reference:
ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
Return values:
None

Definition at line 592 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR ( void )

Check if Synchronization or trimming error signal occurred or not.

Reference Manual to LL API cross reference:
ISR ERRF LL_CRS_IsActiveFlag_ERR
Return values:
State of bit (1 or 0).

Definition at line 532 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC ( void )

Check if Expected SYNC signal occurred or not.

Reference Manual to LL API cross reference:
ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 542 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR ( void )

Check if SYNC error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
Return values:
State of bit (1 or 0).

Definition at line 552 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS ( void )

Check if SYNC missed error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
Return values:
State of bit (1 or 0).

Definition at line 562 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK ( void )

Check if SYNC event OK signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 512 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN ( void )

Check if SYNC warning signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 522 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF ( void )

Check if Trimming overflow or underflow occurred or not.

Reference Manual to LL API cross reference:
ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
Return values:
State of bit (1 or 0).

Definition at line 572 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_CRS_DisableIT_ERR ( void )

Disable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_DisableIT_ERR
Return values:
None

Definition at line 701 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_ESYNC ( void )

Disable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_DisableIT_ESYNC
Return values:
None

Definition at line 731 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK ( void )

Disable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
Return values:
None

Definition at line 641 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN ( void )

Disable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
Return values:
None

Definition at line 671 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ERR ( void )

Enable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_EnableIT_ERR
Return values:
None

Definition at line 691 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ESYNC ( void )

Enable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_EnableIT_ESYNC
Return values:
None

Definition at line 721 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK ( void )

Enable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
Return values:
None

Definition at line 631 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN ( void )

Enable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
Return values:
None

Definition at line 661 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR ( void )

Check if Synchronization or trimming error interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_IsEnabledIT_ERR
Return values:
State of bit (1 or 0).

Definition at line 711 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC ( void )

Check if Expected SYNC interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 741 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK ( void )

Check if SYNC event OK interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 651 of file stm32g4xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN ( void )

Check if SYNC warning interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 681 of file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRS Exported Functions

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_CRS_DeInit ( void )

De-Initializes CRS peripheral registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRS registers are de-initialized
  • ERROR: not applicable

Definition at line 55 of file stm32g4xx_ll_crs.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_CRS, and LL_APB1_GRP1_ReleaseReset().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | DAC_CR_CH1_BITOFFSET
#define | DAC_CR_CH2_BITOFFSET
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
#define | DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
#define | DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET
#define | DAC_REG_DHR8R1_REGOFFSET
#define | DAC_REG_DHR12R2_REGOFFSET
#define | DAC_REG_DHR12L2_REGOFFSET
#define | DAC_REG_DHR8R2_REGOFFSET
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
#define | DAC_REG_STR2_REGOFFSET
#define | DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_STRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_STRX_REGOFFSET_BITOFFSET_POS
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS

Define Documentation

#define DAC_CR_CH1_BITOFFSET
Value:
0UL   /* Position of channel bits into registers
                                                CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */

Definition at line 57 of file stm32g4xx_ll_dac.h.

#define DAC_CR_CH2_BITOFFSET
Value:
16UL  /* Position of channel bits into registers
                                                CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */

Definition at line 58 of file stm32g4xx_ll_dac.h.

#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

Definition at line 59 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Disable(), LL_DAC_DisableDMADoubleDataMode(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_EnableDMADoubleDataMode(), LL_DAC_EnableTrigger(), LL_DAC_GetMode(), LL_DAC_GetOutputBuffer(), LL_DAC_GetOutputMode(), LL_DAC_GetSampleAndHoldHoldTime(), LL_DAC_GetSampleAndHoldRefreshTime(), LL_DAC_GetSignedFormat(), LL_DAC_GetTrimmingValue(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveSawtoothResetTriggerSource(), LL_DAC_GetWaveSawtoothStepTriggerSource(), LL_DAC_Init(), LL_DAC_IsDMADoubleDataModeEnabled(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsReady(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetOutputBuffer(), LL_DAC_SetSampleAndHoldRefreshTime(), LL_DAC_SetSampleAndHoldSampleTime(), LL_DAC_SetTriggerSource(), LL_DAC_SetTrimmingValue(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), LL_DAC_SetWaveSawtoothPolarity(), LL_DAC_SetWaveSawtoothResetTriggerSource(), LL_DAC_SetWaveSawtoothStepTriggerSource(), and LL_DAC_SetWaveTriangleAmplitude().

#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos

Definition at line 110 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData8RightAligned().

#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos

Definition at line 109 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12LeftAligned().

#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos

Definition at line 111 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_DIGITAL_SCALE_12BITS
Value:
4095UL   /* Full-scale digital value with a resolution of 12
                                                              bits (voltage range determined by analog voltage
                                                              references Vref+ and Vref-, refer to reference manual) */

Definition at line 114 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12L1_REGOFFSET
Value:
0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */

Definition at line 70 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12L2_REGOFFSET
Value:
0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */

Definition at line 74 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
Value:
20UL  /* Position of bits register offset of DHR12Lx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 20 bits)                   */

Definition at line 102 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData8RightAligned().

#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL

Definition at line 78 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */

Definition at line 69 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12R2_REGOFFSET
Value:
0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 28 bits)   */

Definition at line 73 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
Value:
28UL  /* Position of bits register offset of DHR12Rx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 28 bits)                   */

Definition at line 101 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned().

#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL

Definition at line 77 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR8R1_REGOFFSET
Value:
0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */

Definition at line 71 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR8R2_REGOFFSET
Value:
0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */

Definition at line 75 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
Value:
24UL  /* Position of bits register offset of DHR8Rx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 24 bits)                   */

Definition at line 103 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12RightAligned().

#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL

Definition at line 79 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
Value:
0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
                                                                   DHR12Lx, DHR8Rx, ...) when shifted to position 0 */

Definition at line 96 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData8RightAligned(), and LL_DAC_ConvertDualData12RightAligned().

#define DAC_REG_DHRX_REGOFFSET_MASK
Value:
(DAC_REG_DHR12RX_REGOFFSET_MASK\
                                        | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

Definition at line 80 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */

Definition at line 83 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DOR2_REGOFFSET
Value:
0x00000020UL            /* Register offset of DORx channel 1 versus
                                                                  DORx channel 2 (shifted left of 5 bits)    */

Definition at line 85 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
Value:
5UL  /* Position of bits register offset of DORx
                                                                   channel 1 or 2 versus DORx channel 1
                                                                   (shifted left of 5 bits)                    */

Definition at line 104 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

Definition at line 86 of file stm32g4xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
Value:
0x00000001UL /* Mask of DORx registers offset when shifted
                                                                   to position 0                                    */

Definition at line 97 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */

Definition at line 88 of file stm32g4xx_ll_dac.h.

#define DAC_REG_SHSR2_REGOFFSET
Value:
0x00000040UL            /* Register offset of SHSRx channel 1 versus
                                                                  SHSRx channel 2 (shifted left of 6 bits)    */

Definition at line 89 of file stm32g4xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
Value:
6UL  /* Position of bits register offset of SHSRx
                                                                   channel 1 or 2 versus SHSRx channel 1
                                                                   (shifted left of 6 bits)                    */

Definition at line 105 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldHoldTime().

#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)

Definition at line 90 of file stm32g4xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
Value:
0x00000001UL /* Mask of SHSRx registers offset when shifted
                                                                   to position 0                                    */

Definition at line 98 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldHoldTime().

#define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */

Definition at line 92 of file stm32g4xx_ll_dac.h.

#define DAC_REG_STR2_REGOFFSET
Value:
0x00000080UL            /* Register offset of STRx channel 1 versus
                                                                  STRx channel 2 (shifted left of 7 bits)     */

Definition at line 93 of file stm32g4xx_ll_dac.h.

#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS
Value:
7UL  /* Position of bits register offset of STRx
                                                                   channel 1 or 2 versus STRx channel 1
                                                                   (shifted left of 7 bits)                    */

Definition at line 106 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_GetWaveSawtoothPolarity(), LL_DAC_GetWaveSawtoothResetData(), LL_DAC_GetWaveSawtoothStepData(), LL_DAC_Init(), and LL_DAC_SetWaveSawtoothResetData().

#define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)

Definition at line 94 of file stm32g4xx_ll_dac.h.

#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0
Value:
0x00000001UL /* Mask of STRx registers offset when shifted
                                                                   to position 0                                    */

Definition at line 99 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_GetWaveSawtoothPolarity(), LL_DAC_GetWaveSawtoothResetData(), LL_DAC_GetWaveSawtoothStepData(), LL_DAC_Init(), and LL_DAC_SetWaveSawtoothResetData().

#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */

Definition at line 61 of file stm32g4xx_ll_dac.h.

#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */

Definition at line 62 of file stm32g4xx_ll_dac.h.

#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)

Definition at line 63 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_TrigSWConversion().

#define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/

Definition at line 65 of file stm32g4xx_ll_dac.h.

#define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/

Definition at line 66 of file stm32g4xx_ll_dac.h.

#define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)

Definition at line 67 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12RightAligned().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__)
#define | IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __DAC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 134 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_ConvertDualData12RightAligned(), LL_DAC_GetSampleAndHoldSampleTime(), LL_DAC_GetWaveSawtoothPolarity(), LL_DAC_GetWaveSawtoothResetData(), LL_DAC_GetWaveSawtoothStepData(), LL_DAC_Init(), LL_DAC_IsActiveFlag_CAL1(), LL_DAC_SetSampleAndHoldHoldTime(), and LL_DAC_SetWaveSawtoothResetData().

#define IS_LL_DAC_CHANNEL | ( | __DACX__,
 |  | __DAC_CHANNEL__
 | ) |
Value:
(((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                 \
   ||  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                             \
  )

Definition at line 57 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_BUFFER ( __OUTPUT_BUFFER__ )
Value:
(((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                        \
   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
  )

Definition at line 177 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_CONNECTION ( __OUTPUT_CONNECTION__ )
Value:
(((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                     \
   || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
  )

Definition at line 182 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_MODE ( __OUTPUT_MODE__ )
Value:
(((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                            \
   || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
  )

Definition at line 187 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE | ( | __DACX__,
 |  | __TRIGGER_SOURCE__
 | ) |
Value:
(((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
   || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
       : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
  )

Definition at line 87 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE2 | ( | __DACX__,
 |  | __TRIGGER_SOURCE__
 | ) |
Value:
(((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE10)                          \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
   || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
       : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
  )

Definition at line 121 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG | ( | __WAVE_AUTO_GENERATION_MODE__,
 |  | __WAVE_AUTO_GENERATION_CONFIG__
 | ) |

Definition at line 142 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_MODE ( __WAVE_AUTO_GENERATION_MODE__ )
Value:
(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH) \
  )

Definition at line 135 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_DAC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DAC_InitTypeDef Struct Reference
DAC Exported Init structure

Structure definition of some features of DAC instance. More...

#include <stm32g4xx_ll_dac.h>

Data Fields

uint32_t | TriggerSource
uint32_t | TriggerSource2
uint32_t | WaveAutoGeneration
uint32_t | WaveAutoGenerationConfig
uint32_t | OutputBuffer
uint32_t | OutputConnection
uint32_t | OutputMode

Detailed Description

Structure definition of some features of DAC instance.

Definition at line 151 of file stm32g4xx_ll_dac.h.

Field Documentation

uint32_t LL_DAC_InitTypeDef::OutputBuffer

Set the output buffer for the selected DAC channel. This parameter can be a value of DAC channel output buffer

This feature can be modified afterwards using unitary function LL_DAC_SetOutputBuffer().

Definition at line 198 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputConnection

Set the output connection for the selected DAC channel. This parameter can be a value of DAC channel output connection

This feature can be modified afterwards using unitary function LL_DAC_SetOutputConnection().

Definition at line 204 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputMode

Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of DAC channel output mode

This feature can be modified afterwards using unitary function LL_DAC_SetOutputMode().

Definition at line 210 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource

Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource().

Note:
If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth RESET trigger

Definition at line 153 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource2

Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource2().

Note:
If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth step trigger

Definition at line 163 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGeneration

Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of DAC waveform automatic generation mode

This feature can be modified afterwards using unitary function LL_DAC_SetWaveAutoGeneration().

Definition at line 173 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGenerationConfig

Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of DAC wave generation - Noise LFSR unmask bits If waveform automatic generation mode is set to triangle, this parameter can be a value of DAC wave generation - Triangle amplitude If waveform automatic generation mode is set to sawtooth, this parameter host the sawtooth configuration: polarity, reset data, increment data. Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.

Note:
If waveform automatic generation mode is disabled, this parameter is discarded.

This feature can be modified afterwards using unitary function LL_DAC_SetWaveNoiseLFSR(), LL_DAC_SetWaveTriangleAmplitude(), LL_DAC_SetWaveSawtoothPolarity(), LL_DAC_SetWaveSawtoothResetData() or LL_DAC_SetWaveSawtoothStepData(), depending on the wave automatic generation selected.

Definition at line 179 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_dac.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC flags

Defines
DAC flags
DAC Exported Constants

Flags defines which can be used with LL_DAC_ReadReg function. More...

Defines

#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define | LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
#define | LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
#define | LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2)

Detailed Description

Flags defines which can be used with LL_DAC_ReadReg function.

Define Documentation

#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)

DAC channel 1 flag busy writing sample time

Definition at line 234 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DAC1RDY().

#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

DAC channel 2 flag busy writing sample time

Definition at line 241 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DAC2RDY().

#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)

DAC channel 1 flag offset calibration status

Definition at line 233 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST1().

#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)

DAC channel 2 flag offset calibration status

Definition at line 240 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST2().

#define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)

DAC channel 1 flag ready

Definition at line 235 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DORSTAT1().

#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)

DAC channel 2 flag ready

Definition at line 242 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DORSTAT2().

#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

DAC channel 1 flag DMA underrun

Definition at line 232 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR1().

#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

DAC channel 2 flag DMA underrun

Definition at line 239 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR2(), and LL_DAC_EnableIT_DMAUDR1().

#define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1)

DAC channel 1 flag output register

Definition at line 236 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DMAUDR1().

#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2)

DAC channel 2 flag output register

Definition at line 243 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DMAUDR2().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC interruptions

Defines
DAC interruptions
DAC Exported Constants

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions. More...

Defines

#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

Detailed Description

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

Define Documentation

#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)

DAC channel 1 interruption DMA underrun

Definition at line 253 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR1(), and LL_DAC_IsEnabledIT_DMAUDR1().

#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

DAC channel 2 interruption DMA underrun

Definition at line 255 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR2(), and LL_DAC_IsEnabledIT_DMAUDR2().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channels

Defines
DAC channels
DAC Exported Constants

Defines

#define | LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2)

Define Documentation

#define LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1)

DAC channel 1

Definition at line 264 of file stm32g4xx_ll_dac.h.

#define LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2)

DAC channel 2

Definition at line 265 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC high frequency interface mode

Defines
DAC high frequency interface mode
DAC Exported Constants

High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode. More...

Defines

#define | LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL
#define | LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)
#define | LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)

Detailed Description

High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode.

Define Documentation

#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)

High frequency interface mode compatible to AHB>160MHz enabled

Definition at line 277 of file stm32g4xx_ll_dac.h.

#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)

High frequency interface mode compatible to AHB>80MHz enabled

Definition at line 276 of file stm32g4xx_ll_dac.h.

#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL

High frequency interface mode disabled

Definition at line 275 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC operating mode

Defines
DAC operating mode
DAC Exported Constants

Defines

#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

Define Documentation

#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

DAC channel in mode calibration

Definition at line 286 of file stm32g4xx_ll_dac.h.

#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL

DAC channel in mode normal operation

Definition at line 285 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC trigger source

Defines
DAC trigger source
DAC Exported Constants

Defines

#define | LL_DAC_TRIG_SOFTWARE 0x00000000UL
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

Define Documentation

#define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger

Definition at line 302 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger

Definition at line 301 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 306 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 308 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 310 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 312 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 314 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 316 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 305 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 307 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 309 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 311 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 313 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 315 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 317 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability)

Definition at line 318 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 319 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO.

Definition at line 298 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)

DAC3 channel conversion trigger from external peripheral: TIM1 TRGO.

Definition at line 295 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 )

DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO.

Definition at line 299 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 )

DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO.

Definition at line 304 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO.

Definition at line 300 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO.

Definition at line 303 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )

DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO.

Definition at line 297 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)

DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability.

Definition at line 296 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIG_SOFTWARE 0x00000000UL

DAC (all) channel conversion trigger internal (SW start)

Definition at line 294 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC waveform automatic generation mode

Defines
DAC waveform automatic generation mode
DAC Exported Constants

Defines

#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
#define | LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0)

Define Documentation

#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated noise waveform.

Definition at line 328 of file stm32g4xx_ll_dac.h.

#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL

DAC channel wave auto generation mode disabled.

Definition at line 327 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

#define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated sawtooth waveform.

Definition at line 330 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_Init().

#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )

DAC channel wave auto generation mode enabled, set generated triangle waveform.

Definition at line 329 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC wave generation - Noise LFSR unmask bits

Defines
DAC wave generation - Noise LFSR unmask bits
DAC Exported Constants

Defines

#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL

Noise wave generation, unmask LFSR bit0, for the selected DAC channel

Definition at line 338 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel

Definition at line 348 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel

Definition at line 349 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel

Definition at line 339 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel

Definition at line 340 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel

Definition at line 341 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel

Definition at line 342 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel

Definition at line 343 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel

Definition at line 344 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel

Definition at line 345 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel

Definition at line 346 of file stm32g4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel

Definition at line 347 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC wave generation - Triangle amplitude

Defines
DAC wave generation - Triangle amplitude
DAC Exported Constants

Defines

#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL

Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel

Definition at line 357 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel

Definition at line 366 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel

Definition at line 363 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel

Definition at line 360 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel

Definition at line 367 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel

Definition at line 364 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel

Definition at line 358 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel

Definition at line 361 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel

Definition at line 368 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )

Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel

Definition at line 365 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel

Definition at line 362 of file stm32g4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel

Definition at line 359 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC wave generation - Sawtooth polarity mode

Defines
DAC wave generation - Sawtooth polarity mode
DAC Exported Constants

Defines

#define | LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL
#define | LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)

Define Documentation

#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL

Sawtooth wave generation, polarity is decrement

Definition at line 376 of file stm32g4xx_ll_dac.h.

#define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)

Sawtooth wave generation, polarity is increment

Definition at line 377 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channel output mode

Defines
DAC channel output mode
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

Define Documentation

#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL

The selected DAC channel output is on mode normal.

Definition at line 385 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function LL_DAC_ConfigOutput() or LL_DAC_SetOutputMode().

Definition at line 386 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channel output buffer

Defines
DAC channel output buffer
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption

Definition at line 395 of file stm32g4xx_ll_dac.h.

#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL

The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption

Definition at line 394 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channel output connection

Defines
DAC channel output connection
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

Define Documentation

#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL

The selected DAC channel output is connected to external pin

Definition at line 403 of file stm32g4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function LL_DAC_SetOutputConnection().

Definition at line 404 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channel signed format

Defines
DAC channel signed format
DAC Exported Constants

Defines

#define | LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL
#define | LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1)

Define Documentation

#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL

The selected DAC channel data format is not signed

Definition at line 412 of file stm32g4xx_ll_dac.h.

#define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1)

The selected DAC channel data format is signed

Definition at line 413 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC channel output resolution

Defines
DAC channel output resolution
DAC Exported Constants

Defines

#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL

Define Documentation

#define LL_DAC_RESOLUTION_12B 0x00000000UL

DAC channel resolution 12 bits

Definition at line 421 of file stm32g4xx_ll_dac.h.

#define LL_DAC_RESOLUTION_8B 0x00000002UL

DAC channel resolution 8 bits

Definition at line 422 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC registers compliant with specific purpose

Defines
DAC registers compliant with specific purpose
DAC Exported Constants

Defines

#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

Define Documentation

#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits left aligned

Definition at line 434 of file stm32g4xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits right aligned

Definition at line 433 of file stm32g4xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 8 bits right aligned

Definition at line 435 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Definitions of DAC hardware constraints delays

Defines
Definitions of DAC hardware constraints delays
DAC Exported Constants

Defines

#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Detailed Description

Note:
Only DAC peripheral HW delays are defined in DAC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 460 of file stm32g4xx_ll_dac.h.

#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Delay for DAC channel voltage settling time

Definition at line 473 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common write and read registers macros

Defines
Common write and read registers macros
DAC Exported Macros

Defines

#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.

Define Documentation

#define LL_DAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 507 of file stm32g4xx_ll_dac.h.

#define LL_DAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 499 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC helper macro

Defines
DAC helper macro
DAC Exported Macros

Defines

#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).
#define | __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__)
Helper macro to format sawtooth wave generation configuration value to be filled into WaveAutoGenerationConfig parameter of LL_DAC_InitTypeDef.

Define Documentation

#define __LL_DAC_CALC_VOLTAGE_TO_DATA | ( | __VREFANALOG_VOLTAGE__,
 |  | __DAC_VOLTAGE__,
 |  | __DAC_RESOLUTION__
 | ) |
Value:
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                                      \
   / (__VREFANALOG_VOLTAGE__)                                                                          \
  )

Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Note:
This helper macro is intended to provide input data in voltage rather than digital value, to be used with LL DAC functions such as LL_DAC_ConvertData12RightAligned().
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__DAC_VOLTAGE__ | Voltage to be generated by DAC channel (unit: mVolt).
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
DAC conversion data (unit: digital value)

Definition at line 587 of file stm32g4xx_ll_dac.h.

#define __LL_DAC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.

Example: __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) will return decimal number "1".

Note:
The input can be a value from functions where a channel number is returned.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
1...2

Definition at line 533 of file stm32g4xx_ll_dac.h.

#define __LL_DAC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))

Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.

Example: __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) will return a data equivalent to "LL_DAC_CHANNEL_1".

Note:
If the input parameter does not correspond to a DAC channel, this macro returns value '0'.
Parameters:
__DECIMAL_NB__ 1...2
Return values:
Returned value can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.

Definition at line 552 of file stm32g4xx_ll_dac.h.

#define __LL_DAC_DIGITAL_SCALE ( __DAC_RESOLUTION__ ) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))

Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.

Note:
DAC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 566 of file stm32g4xx_ll_dac.h.

#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG | ( | __POLARITY__,
 |  | __RESET_DATA__,
 |  | __STEP_DATA__
 | ) |
Value:
( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk)                          \
    | ((__POLARITY__) & DAC_STR1_STDIR1_Msk)                                                          \
    | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk)                       \
  )

Helper macro to format sawtooth wave generation configuration value to be filled into WaveAutoGenerationConfig parameter of LL_DAC_InitTypeDef.

Note:
This helper will format information to fit in DAC_STRx register.
Parameters:
__POLARITY__ | sawtooth wave polarity (must be value of DAC wave generation - Sawtooth polarity mode)
__RESET_DATA__ | sawtooth reset data.
__STEP_DATA__ | sawtooth step data
Return values:
Sawtooth configuration organized in DAC_STRx compatible format.

Definition at line 601 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of DAC instance

Functions
Configuration of DAC instance
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetHighFrequencyMode (DAC_TypeDef *DACx, uint32_t HighFreqMode)
Set the high frequency interface mode for the selected DAC instance.
__STATIC_INLINE uint32_t | LL_DAC_GetHighFrequencyMode (const DAC_TypeDef *DACx)
Get the high frequency interface mode for the selected DAC instance.

Function Documentation

__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode ( const DAC_TypeDef * DACx )

Get the high frequency interface mode for the selected DAC instance.

Reference Manual to LL API cross reference:
MCR HFSEL LL_DAC_GetHighFrequencyMode
Parameters:
DACx DAC instance
Return values:
Returned value can be one of the following values:
  • LL_DAC_HIGH_FREQ_MODE_DISABLE
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ

Definition at line 647 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetHighFrequencyMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | HighFreqMode
 | ) |  |

Set the high frequency interface mode for the selected DAC instance.

Reference Manual to LL API cross reference:
MCR HFSEL LL_DAC_SetHighFrequencyMode
Parameters:
DACx DAC instance
HighFreqMode This parameter can be one of the following values:
  • LL_DAC_HIGH_FREQ_MODE_DISABLE
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
Return values:
None

Definition at line 633 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of DAC channels

Functions
Configuration of DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothPolarity (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
Set the swatooth waveform generation polarity.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothPolarity (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation polarity.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothResetData (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
Set the swatooth waveform generation reset data.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothResetData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation reset data.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothStepData (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
Set the sawtooth waveform generation step data.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothStepData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation step data.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothResetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the sawtooth waveform generation reset trigger source.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothResetTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation reset trigger source.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothStepTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the swatooth waveform generation step trigger source.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothStepTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation step trigger source.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE void | LL_DAC_SetSignedFormat (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
Set the signed format for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetSignedFormat (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the signed format state for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConfigOutput | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode,
 |  | uint32_t | OutputBuffer,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output for the selected DAC channel.

Note:
This function set several features:
  • mode normal or sample-and-hold
  • buffer
  • connection to GPIO or internal path. These features can also be set individually using dedicated functions:
  • LL_DAC_SetOutputBuffer()
  • LL_DAC_SetOutputMode()
  • LL_DAC_SetOutputConnection()
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_ConfigOutput
CR MODE2 LL_DAC_ConfigOutput
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 1467 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetMode | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_GetMode
CR CEN2 LL_DAC_GetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION

Definition at line 700 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output buffer state for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputBuffer
CR MODE2 LL_DAC_GetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE

Definition at line 1569 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output connection for the selected DAC channel.

Note:
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputConnection
CR MODE2 LL_DAC_GetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL

Definition at line 1634 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetOutputMode | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output mode normal or sample-and-hold for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputMode
CR MODE2 LL_DAC_GetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

Definition at line 1520 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1726 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1769 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: sample time.

Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1682 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the signed format state for the selected DAC channel.

Reference Manual to LL API cross reference:
MCR SINFORMAT1 LL_DAC_GetSignedFormat
MCR SINFORMAT2 LL_DAC_GetSignedFormat
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_SIGNED_FORMAT_ENABLE
  • LL_DAC_SIGNED_FORMAT_DISABLE

Definition at line 1821 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_GetTriggerSource
CR TSEL2 LL_DAC_GetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. (3) On this STM32 series, parameter only available on DAC1&4. (4) On this STM32 series, parameter only available on DAC2. Refer to device datasheet for DACx instances availability. (5) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 850 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_GetTrimmingValue
CCR OTRIM2 LL_DAC_GetTrimmingValue
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 745 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_GetWaveAutoGeneration
CR WAVE2 LL_DAC_GetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  • LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH

Definition at line 901 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveNoiseLFSR
CR MAMP2 LL_DAC_GetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

Definition at line 973 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sawtooth waveform generation polarity.

Reference Manual to LL API cross reference:
STR1 STDIR1 LL_DAC_GetWaveSawtoothPolarity
STR2 STDIR2 LL_DAC_GetWaveSawtoothPolarity
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_SAWTOOTH_POLARITY_DECREMENT
  • LL_DAC_SAWTOOTH_POLARITY_INCREMENT

Definition at line 1100 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_STRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_STRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sawtooth waveform generation reset data.

Reference Manual to LL API cross reference:
STR1 STRSTDATA1 LL_DAC_GetWaveSawtoothResetData
STR2 STRSTDATA2 LL_DAC_GetWaveSawtoothResetData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value is the sawtooth reset value. Range is from 0 to DAC full range 4095 (0xFFF)

Definition at line 1154 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_STRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_STRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sawtooth waveform generation reset trigger source.

Reference Manual to LL API cross reference:
STMODR STRSTTRIGSEL1 LL_DAC_GetWaveSawtoothResetTriggerSource
STMODR STRSTTRIGSEL2 LL_DAC_GetWaveSawtoothResetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. (3) On this STM32 series, parameter only available on DAC1&4. (4) On this STM32 series, parameter only available on DAC2. Refer to device datasheet for DACx instances availability. (5) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 1316 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sawtooth waveform generation step data.

Reference Manual to LL API cross reference:
STR1 STINCDATA1 LL_DAC_GetWaveSawtoothStepData
STR2 STINCDATA2 LL_DAC_GetWaveSawtoothStepData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value is the sawtooth step value. 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa Step value step is 1/16 = 0.0625 Step value range is 0.0000 to 4095.9375 (0xFFF.F)

Definition at line 1212 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_STRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_STRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sawtooth waveform generation step trigger source.

Reference Manual to LL API cross reference:
STMODR STINCTRIGSEL1 LL_DAC_GetWaveSawtoothStepTriggerSource
STMODR STINCTRIGSEL2 LL_DAC_GetWaveSawtoothStepTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE10
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. Refer to device datasheet for DACx instances availability. (3) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)

Definition at line 1411 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095

Definition at line 1046 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | ChannelMode
 | ) |  |

Set the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_SetMode
CR CEN2 LL_DAC_SetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
ChannelMode This parameter can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION
Return values:
None

Definition at line 677 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputBuffer
 | ) |  |

Set the output buffer for the selected DAC channel.

Note:
On this STM32 series, when buffer is enabled, its offset can be trimmed: factory calibration default values can be replaced by user trimming values, using function LL_DAC_SetTrimmingValue().
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputBuffer
CR MODE2 LL_DAC_SetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
Return values:
None

Definition at line 1547 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output connection for the selected DAC channel.

Note:
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputConnection
CR MODE2 LL_DAC_SetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 1602 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode
 | ) |  |

Set the output mode normal or sample-and-hold for the selected DAC channel.

Note:
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputMode
CR MODE2 LL_DAC_SetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
Return values:
None

Definition at line 1498 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | HoldTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
HoldTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1705 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | RefreshTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
RefreshTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1748 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | SampleTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: sample time.

Note:
Sample time must be set when DAC channel is disabled or during DAC operation when DAC channel flag BWSTx is reset, otherwise the setting is ignored. Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
SampleTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1660 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSignedFormat | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | SignedFormat
 | ) |  |

Set the signed format for the selected DAC channel.

Note:
On this STM32 series, signed format can be used to inject Q1.15, Q1.11, Q1.7 signed format data to DAC. Ex when using 12bits data format (Q1.11 is used): 0x800 will output 0v level 0xFFF will output mid-scale level 0x000 will output mid-scale level 0x7FF will output full-scale level
Reference Manual to LL API cross reference:
MCR SINFORMAT1 LL_DAC_SetSignedFormat
MCR SINFORMAT2 LL_DAC_SetSignedFormat
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
SignedFormat This parameter can be one of the following values:
  • LL_DAC_SIGNED_FORMAT_ENABLE
  • LL_DAC_SIGNED_FORMAT_DISABLE
Return values:
None

Definition at line 1799 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
To set conversion trigger source, DAC channel must be disabled. Otherwise, the setting is discarded.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_SetTriggerSource
CR TSEL2 LL_DAC_SetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. (3) On this STM32 series, parameter only available on DAC1&4. (4) On this STM32 series, parameter only available on DAC2. Refer to device datasheet for DACx instances availability. (5) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
Return values:
None

Definition at line 799 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_SetTrimmingValue
CCR OTRIM2 LL_DAC_SetTrimmingValue
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
TrimmingValue | Value between Min_Data=0x00 and Max_Data=0x1F
Return values:
None

Definition at line 723 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveAutoGeneration
 | ) |  |

Set the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_SetWaveAutoGeneration
CR WAVE2 LL_DAC_SetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
WaveAutoGeneration This parameter can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
  • LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
Return values:
None

Definition at line 876 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | NoiseLFSRMask
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveNoiseLFSR
CR MAMP2 LL_DAC_SetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
NoiseLFSRMask This parameter can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
Return values:
None

Definition at line 940 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the swatooth waveform generation polarity.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
STR1 STDIR1 LL_DAC_SetWaveSawtoothPolarity
STR2 STDIR2 LL_DAC_SetWaveSawtoothPolarity
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Polarity This parameter can be one of the following values:
  • LL_DAC_SAWTOOTH_POLARITY_DECREMENT
  • LL_DAC_SAWTOOTH_POLARITY_INCREMENT
Return values:
None

Definition at line 1074 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | ResetData
 | ) |  |

Set the swatooth waveform generation reset data.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
STR1 STRSTDATA1 LL_DAC_SetWaveSawtoothResetData
STR2 STRSTDATA2 LL_DAC_SetWaveSawtoothResetData
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
ResetData | This parameter is the sawtooth reset value. Range is from 0 to DAC full range 4095 (0xFFF)
Return values:
None

Definition at line 1129 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_STRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_STRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the sawtooth waveform generation reset trigger source.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
STMODR STRSTTRIGSEL1 LL_DAC_SetWaveSawtoothResetTriggerSource
STMODR STRSTTRIGSEL2 LL_DAC_SetWaveSawtoothResetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. (3) On this STM32 series, parameter only available on DAC1&4. (4) On this STM32 series, parameter only available on DAC2. Refer to device datasheet for DACx instances availability. (5) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
Return values:
None

Definition at line 1267 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | StepData
 | ) |  |

Set the sawtooth waveform generation step data.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
STR1 STINCDATA1 LL_DAC_SetWaveSawtoothStepData
STR2 STINCDATA2 LL_DAC_SetWaveSawtoothStepData
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
StepData | This parameter is the sawtooth step value. 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa Step value step is 1/16 = 0.0625 Step value range is 0.0000 to 4095.9375 (0xFFF.F)
Return values:
None

Definition at line 1185 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the swatooth waveform generation step trigger source.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
STMODR STINCTRIGSEL1 LL_DAC_SetWaveSawtoothStepTriggerSource
STMODR STINCTRIGSEL2 LL_DAC_SetWaveSawtoothStepTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO (1)
  • LL_DAC_TRIG_EXT_TIM8_TRGO (2)
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE10
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
(1) On this STM32 series, parameter only available on DAC3. (2) On this STM32 series, parameter only available on DAC1/2/4. Refer to device datasheet for DACx instances availability. (3) On this STM32 series, parameter not available on all devices. Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
Return values:
None

Definition at line 1366 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriangleAmplitude
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
TriangleAmplitude This parameter can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095
Return values:
None

Definition at line 1012 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Management

Functions
DMA Management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableDMADoubleDataMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA Double data mode of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMADoubleDataMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA Double data mode of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMADoubleDataModeEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA double data mode state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA Double data mode of the selected channel.

Reference Manual to LL API cross reference:
MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode
MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1931 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_DisableDMAReq
CR DMAEN2 LL_DAC_DisableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1872 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Note:
These DAC registers are data holding registers: when DAC conversion is requested, DAC generates a DMA transfer request to have data available in DAC data holding registers.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, (uint32_t)&< array or variable >, LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Register This parameter can be one of the following values:
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Return values:
DAC register address

Definition at line 1993 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA Double data mode of the selected channel.

Reference Manual to LL API cross reference:
MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode
MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1912 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_EnableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_EnableDMAReq
CR DMAEN2 LL_DAC_EnableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 1851 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA double data mode state of the selected channel.

(0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)

Reference Manual to LL API cross reference:
MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled
MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 1951 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA transfer request state of the selected channel.

(0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_IsDMAReqEnabled
CR DMAEN2 LL_DAC_IsDMAReqEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 1892 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on DAC channels

Functions
Operation on DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsReady (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC ready for conversion state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion2 (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by secondary software trigger for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2263 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2239 of file stm32g4xx_ll_dac.h.

References DAC_SWTRB_CHX_MASK.

__STATIC_INLINE void LL_DAC_ConvertData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2287 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned
DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2326 of file stm32g4xx_ll_dac.h.

References DAC_DHR12RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned
DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2307 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned
DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x00 and Max_Data=0xFF
DataChannel2 | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2348 of file stm32g4xx_ll_dac.h.

References DAC_DHR12LD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_Disable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Disable
CR EN2 LL_DAC_Disable
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2043 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC trigger of the selected channel.

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_DisableTrigger
CR TEN2 LL_DAC_DisableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2131 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_Enable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Enable
CR EN2 LL_DAC_Enable
Note:
After enable from off state, DAC channel requires a delay for output voltage to reach accuracy +/- 1 LSB. Refer to device datasheet, parameter "tWAKEUP".
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2024 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_EnableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC trigger of the selected channel.

Note:
- If DAC trigger is disabled, DAC conversion is performed automatically once the data holding register is updated, using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...
  • If DAC trigger is enabled, DAC conversion is performed only when a hardware of software trigger event is occurring. Select trigger source using function LL_DAC_SetTriggerSource().
Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_EnableTrigger
CR TEN2 LL_DAC_EnableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2112 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsEnabled | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC enable state of the selected channel.

(0: DAC channel is disabled, 1: DAC channel is enabled)

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_IsEnabled
CR EN2 LL_DAC_IsEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 2063 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_Init().

__STATIC_INLINE uint32_t LL_DAC_IsReady | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC ready for conversion state of the selected channel.

(0: DAC channel is not ready, 1: DAC channel is ready)

Reference Manual to LL API cross reference:
SR DAC1RDY LL_DAC_IsReady
SR DAC2RDY LL_DAC_IsReady
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 2084 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC trigger state of the selected channel.

(0: DAC trigger is disabled, 1: DAC trigger is enabled)

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_IsTriggerEnabled
CR TEN2 LL_DAC_IsTriggerEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
State of bit (1 or 0).

Definition at line 2151 of file stm32g4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData | ( | const DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Retrieve output data currently generated for the selected DAC channel.

Note:
Whatever alignment and resolution settings (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...), output data format is 12 bits right aligned (LSB aligned on bit 0).
Reference Manual to LL API cross reference:
DOR1 DACC1DOR LL_DAC_RetrieveOutputData
DOR2 DACC2DOR LL_DAC_RetrieveOutputData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 2374 of file stm32g4xx_ll_dac.h.

References DAC_DHR8RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_TrigSWConversion | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by software for the selected DAC channel.

Note:
Preliminarily, DAC trigger must be set to software trigger using function LL_DAC_Init() LL_DAC_SetTriggerSource() LL_DAC_SetWaveSawtoothResetTriggerSource() (1) with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().

(1) In case, Sawtooth wave generation has been configured.

Note:
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2185 of file stm32g4xx_ll_dac.h.

References DAC_SWTR_CHX_MASK.

__STATIC_INLINE void LL_DAC_TrigSWConversion2 | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by secondary software trigger for the selected DAC channel.

Note:
Preliminarily, DAC secondary trigger must be set to software trigger using function LL_DAC_Init() LL_DAC_SetWaveSawtoothStepTriggerSource() (1) with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().

(1) In case, Sawtooth wave generation has been configured.

Note:
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIGB1 LL_DAC_TrigSWConversion2
SWTRIGR SWTRIGB2 LL_DAC_TrigSWConversion2
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
Return values:
None

Definition at line 2217 of file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
DAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (const DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (const DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (const DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (const DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DAC1RDY (const DAC_TypeDef *DACx)
Get DAC ready status flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DAC2RDY (const DAC_TypeDef *DACx)
Get DAC ready status flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DORSTAT1 (const DAC_TypeDef *DACx)
Get DAC output register status flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DORSTAT2 (const DAC_TypeDef *DACx)
Get DAC output register status flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (const DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (const DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2514 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2526 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1 ( const DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR BWST1 LL_DAC_IsActiveFlag_BWST1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2420 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_CAL1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2 ( const DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR BWST2 LL_DAC_IsActiveFlag_BWST2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2431 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_CAL2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1 ( const DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2396 of file stm32g4xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DORX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DORX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2 ( const DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2408 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY ( const DAC_TypeDef * DACx )

Get DAC ready status flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2443 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_BWST1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY ( const DAC_TypeDef * DACx )

Get DAC ready status flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2455 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_BWST2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1 ( const DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2490 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DORSTAT1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2 ( const DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2502 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DORSTAT2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1 ( const DAC_TypeDef * DACx )

Get DAC output register status flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2467 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DAC1RDY.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2 ( const DAC_TypeDef * DACx )

Get DAC output register status flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2479 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DAC2RDY.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT management

Functions
IT management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (const DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (const DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2570 of file stm32g4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2582 of file stm32g4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2546 of file stm32g4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 2558 of file stm32g4xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1 ( const DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2594 of file stm32g4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2 ( const DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 2606 of file stm32g4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Functions

ErrorStatus | LL_DAC_DeInit (const DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DAC_DeInit ( const DAC_TypeDef * DACx )

De-initialize registers of the selected DAC instance to their default reset values.

Parameters:
DACx DAC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are de-initialized
  • ERROR: not applicable

Definition at line 216 of file stm32g4xx_ll_dac.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_DAC1, LL_AHB2_GRP1_PERIPH_DAC3, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_DAC_Init | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | const LL_DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initialize some features of DAC channel.

Note:
LL_DAC_Init() aims to ease basic configuration of a DAC channel. Leaving it ready to be enabled and output: a level by calling one of LL_DAC_ConvertData12RightAligned LL_DAC_ConvertData12LeftAligned LL_DAC_ConvertData8RightAligned or one of the supported autogenerated wave.
This function allows configuration of:
  • Output mode
  • Trigger
  • Wave generation
The setting of these parameters by function LL_DAC_Init() is conditioned to DAC state: DAC channel must be disabled.
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2 (1)
(1) On this STM32 series, parameter not available on all instances. Refer to device datasheet for channels availability.
DAC_InitStruct | Pointer to a LL_DAC_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are initialized
  • ERROR: DAC registers are not initialized

Definition at line 293 of file stm32g4xx_ll_dac.c.

References __DAC_PTR_REG_OFFSET, assert_param, DAC_CR_CHX_BITOFFSET_MASK, DAC_REG_STRX_REGOFFSET_BITOFFSET_POS, DAC_REG_STRX_REGOFFSET_MASK_POSBIT0, IS_LL_DAC_CHANNEL, IS_LL_DAC_OUTPUT_BUFFER, IS_LL_DAC_OUTPUT_CONNECTION, IS_LL_DAC_OUTPUT_MODE, IS_LL_DAC_TRIGGER_SOURCE, IS_LL_DAC_TRIGGER_SOURCE2, IS_LL_DAC_WAVE_AUTO_GENER_CONFIG, IS_LL_DAC_WAVE_AUTO_GENER_MODE, LL_DAC_IsEnabled(), LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::TriggerSource2, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

void LL_DAC_StructInit ( LL_DAC_InitTypeDef * DAC_InitStruct )

Set each LL_DAC_InitTypeDef field to default value.

Parameters:
DAC_InitStruct pointer to a LL_DAC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 398 of file stm32g4xx_ll_dac.c.

References LL_DAC_NOISE_LFSR_UNMASK_BIT0, LL_DAC_OUTPUT_BUFFER_ENABLE, LL_DAC_OUTPUT_CONNECT_GPIO, LL_DAC_OUTPUT_MODE_NORMAL, LL_DAC_TRIG_SOFTWARE, LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::TriggerSource2, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t CHANNEL_OFFSET_TAB []

Variable Documentation

const uint8_t CHANNEL_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)

}

Definition at line 47 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

Defines

#define | DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
#define | DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))

Define Documentation

#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)

Definition at line 73 of file stm32g4xx_ll_dma.h.

#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))

Definition at line 76 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 115U)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Define Documentation

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_6))) || \
                                                            (((INSTANCE) == DMA2) && \
                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_6))))

Definition at line 97 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 47 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 64 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 57 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 51 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x0000FFFFU)

Definition at line 68 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 60 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 54 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHREQUEST ( __VALUE__ ) ((__VALUE__) <= 115U)

Definition at line 70 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 72 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32g4xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority

Detailed Description

Definition at line 96 of file stm32g4xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 108 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 103 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 139 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 127 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 114 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 145 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 98 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 133 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 121 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of Transfer request

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphRequest().

Definition at line 152 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 157 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_dma.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 176 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 180 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 184 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 188 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 192 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 196 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 178 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 182 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 186 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 190 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 194 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 198 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 177 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 181 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 185 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 189 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 193 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 197 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 179 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 183 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 187 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 191 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 195 of file stm32g4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 199 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 220 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 224 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 228 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 232 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 236 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 240 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 222 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 226 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 230 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 234 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 238 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 242 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 221 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 225 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 229 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 233 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 237 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 241 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 223 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 227 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 231 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 235 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 239 of file stm32g4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 243 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 265 of file stm32g4xx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 264 of file stm32g4xx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 266 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 0x00000000U
#define | LL_DMA_CHANNEL_2 0x00000001U
#define | LL_DMA_CHANNEL_3 0x00000002U
#define | LL_DMA_CHANNEL_4 0x00000003U
#define | LL_DMA_CHANNEL_5 0x00000004U
#define | LL_DMA_CHANNEL_6 0x00000005U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_CHANNEL_1 0x00000000U

DMA Channel 1

Definition at line 274 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 0x00000001U

DMA Channel 2

Definition at line 275 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 0x00000002U

DMA Channel 3

Definition at line 276 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 0x00000003U

DMA Channel 4

Definition at line 277 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 0x00000004U

DMA Channel 5

Definition at line 278 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 0x00000005U

DMA Channel 6

Definition at line 279 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL 0xFFFF0000U

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 287 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 298 of file stm32g4xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 297 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 296 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 307 of file stm32g4xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 306 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 315 of file stm32g4xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 316 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 324 of file stm32g4xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 325 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 333 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 334 of file stm32g4xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 335 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 343 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 344 of file stm32g4xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 345 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 355 of file stm32g4xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 353 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 354 of file stm32g4xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 356 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 388 of file stm32g4xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 380 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
   LL_DMA_CHANNEL_6)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 431 of file stm32g4xx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
   DMA2_Channel6)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 470 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 405 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
Set DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA instance on Channel x.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA channel is enabled.
Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 1054 of file stm32g4xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 599 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 539 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 517 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 971 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1022 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 655 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1259 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1236 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1140 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 810 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 916 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 708 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1163 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 759 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA request for DMA instance on Channel x.

Reference Manual to LL API cross reference:
CSELR C1S LL_DMA_GetPeriphRequest
CSELR C2S LL_DMA_GetPeriphRequest
CSELR C3S LL_DMA_GetPeriphRequest
CSELR C4S LL_DMA_GetPeriphRequest
CSELR C5S LL_DMA_GetPeriphRequest
CSELR C6S LL_DMA_GetPeriphRequest
CSELR C7S LL_DMA_GetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_SPI3_RX
  • LL_DMAMUX_REQ_SPI3_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX (*)
  • LL_DMAMUX_REQ_I2C4_RX (*)
  • LL_DMAMUX_REQ_I2C4_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_UART4_RX
  • LL_DMAMUX_REQ_UART4_TX
  • LL_DMAMUX_REQ_UART5_RX (*)
  • LL_DMAMUX_REQ_UART5_TX (*)
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_ADC2
  • LL_DMAMUX_REQ_ADC3 (*)
  • LL_DMAMUX_REQ_ADC4 (*)
  • LL_DMAMUX_REQ_ADC5 (*)
  • LL_DMAMUX_REQ_QSPI (*)
  • LL_DMAMUX_REQ_DAC2_CH1 (*)
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM8_CH1
  • LL_DMAMUX_REQ_TIM8_CH2
  • LL_DMAMUX_REQ_TIM8_CH3
  • LL_DMAMUX_REQ_TIM8_CH4
  • LL_DMAMUX_REQ_TIM8_UP
  • LL_DMAMUX_REQ_TIM8_TRIG
  • LL_DMAMUX_REQ_TIM8_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM4_CH1
  • LL_DMAMUX_REQ_TIM4_CH2
  • LL_DMAMUX_REQ_TIM4_CH3
  • LL_DMAMUX_REQ_TIM4_CH4
  • LL_DMAMUX_REQ_TIM4_UP
  • LL_DMAMUX_REQ_TIM5_CH1 (*)
  • LL_DMAMUX_REQ_TIM5_CH2 (*)
  • LL_DMAMUX_REQ_TIM5_CH3 (*)
  • LL_DMAMUX_REQ_TIM5_CH4 (*)
  • LL_DMAMUX_REQ_TIM5_UP (*)
  • LL_DMAMUX_REQ_TIM5_TRIG (*)
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM15_TRIG
  • LL_DMAMUX_REQ_TIM15_COM
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_TIM20_CH1 (*)
  • LL_DMAMUX_REQ_TIM20_CH2 (*)
  • LL_DMAMUX_REQ_TIM20_CH3 (*)
  • LL_DMAMUX_REQ_TIM20_CH4 (*)
  • LL_DMAMUX_REQ_TIM20_UP (*)
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_TIM20_TRIG (*)
  • LL_DMAMUX_REQ_TIM20_COM (*)
  • LL_DMAMUX_REQ_HRTIM1_M (*)
  • LL_DMAMUX_REQ_HRTIM1_A (*)
  • LL_DMAMUX_REQ_HRTIM1_B (*)
  • LL_DMAMUX_REQ_HRTIM1_C (*)
  • LL_DMAMUX_REQ_HRTIM1_D (*)
  • LL_DMAMUX_REQ_HRTIM1_E (*)
  • LL_DMAMUX_REQ_HRTIM1_F (*)
  • LL_DMAMUX_REQ_DAC3_CH1
  • LL_DMAMUX_REQ_DAC3_CH2
  • LL_DMAMUX_REQ_DAC4_CH1 (*)
  • LL_DMAMUX_REQ_DAC4_CH2 (*)
  • LL_DMAMUX_REQ_SPI4_RX (*)
  • LL_DMAMUX_REQ_SPI4_TX (*)
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_FMAC_READ
  • LL_DMAMUX_REQ_CORDIC_WRITE
  • LL_DMAMUX_REQ_CORDIC_READ
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX (*) Not on all G4 devices

Definition at line 1551 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 863 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
State of bit (1 or 0).

Definition at line 561 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 944 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 997 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 628 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1213 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1188 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1092 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 785 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 890 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 683 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1117 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 734 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphRequest
 | ) |  |

Set DMA request for DMA instance on Channel x.

Note:
Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
Reference Manual to LL API cross reference:
CSELR C1S LL_DMA_SetPeriphRequest
CSELR C2S LL_DMA_SetPeriphRequest
CSELR C3S LL_DMA_SetPeriphRequest
CSELR C4S LL_DMA_SetPeriphRequest
CSELR C5S LL_DMA_SetPeriphRequest
CSELR C6S LL_DMA_SetPeriphRequest
CSELR C7S LL_DMA_SetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
PeriphRequest This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_SPI3_RX
  • LL_DMAMUX_REQ_SPI3_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX (*)
  • LL_DMAMUX_REQ_I2C4_RX (*)
  • LL_DMAMUX_REQ_I2C4_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_UART4_RX
  • LL_DMAMUX_REQ_UART4_TX
  • LL_DMAMUX_REQ_UART5_RX (*)
  • LL_DMAMUX_REQ_UART5_TX (*)
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_ADC2
  • LL_DMAMUX_REQ_ADC3 (*)
  • LL_DMAMUX_REQ_ADC4 (*)
  • LL_DMAMUX_REQ_ADC5 (*)
  • LL_DMAMUX_REQ_QSPI (*)
  • LL_DMAMUX_REQ_DAC2_CH1 (*)
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM8_CH1
  • LL_DMAMUX_REQ_TIM8_CH2
  • LL_DMAMUX_REQ_TIM8_CH3
  • LL_DMAMUX_REQ_TIM8_CH4
  • LL_DMAMUX_REQ_TIM8_UP
  • LL_DMAMUX_REQ_TIM8_TRIG
  • LL_DMAMUX_REQ_TIM8_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM4_CH1
  • LL_DMAMUX_REQ_TIM4_CH2
  • LL_DMAMUX_REQ_TIM4_CH3
  • LL_DMAMUX_REQ_TIM4_CH4
  • LL_DMAMUX_REQ_TIM4_UP
  • LL_DMAMUX_REQ_TIM5_CH1 (*)
  • LL_DMAMUX_REQ_TIM5_CH2 (*)
  • LL_DMAMUX_REQ_TIM5_CH3 (*)
  • LL_DMAMUX_REQ_TIM5_CH4 (*)
  • LL_DMAMUX_REQ_TIM5_UP (*)
  • LL_DMAMUX_REQ_TIM5_TRIG (*)
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM15_TRIG
  • LL_DMAMUX_REQ_TIM15_COM
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_TIM20_CH1 (*)
  • LL_DMAMUX_REQ_TIM20_CH2 (*)
  • LL_DMAMUX_REQ_TIM20_CH3 (*)
  • LL_DMAMUX_REQ_TIM20_CH4 (*)
  • LL_DMAMUX_REQ_TIM20_UP (*)
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_TIM20_TRIG (*)
  • LL_DMAMUX_REQ_TIM20_COM (*)
  • LL_DMAMUX_REQ_HRTIM1_M (*)
  • LL_DMAMUX_REQ_HRTIM1_A (*)
  • LL_DMAMUX_REQ_HRTIM1_B (*)
  • LL_DMAMUX_REQ_HRTIM1_C (*)
  • LL_DMAMUX_REQ_HRTIM1_D (*)
  • LL_DMAMUX_REQ_HRTIM1_E (*)
  • LL_DMAMUX_REQ_HRTIM1_F (*)
  • LL_DMAMUX_REQ_DAC3_CH1
  • LL_DMAMUX_REQ_DAC3_CH2
  • LL_DMAMUX_REQ_DAC4_CH1 (*)
  • LL_DMAMUX_REQ_DAC4_CH2 (*)
  • LL_DMAMUX_REQ_SPI4_RX (*)
  • LL_DMAMUX_REQ_SPI4_TX (*)
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_FMAC_READ
  • LL_DMAMUX_REQ_CORDIC_WRITE
  • LL_DMAMUX_REQ_CORDIC_READ
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX (*) Not on all G4 devices
Return values:
None

Definition at line 1406 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 837 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Note:
Do not Clear Channel 1 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1943 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Note:
Do not Clear Channel 2 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1958 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Note:
Do not Clear Channel 3 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1973 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Note:
Do not Clear Channel 4 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1988 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Note:
Do not Clear Channel 5 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2003 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Note:
Do not Clear Channel 6 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2018 of file stm32g4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2155 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2166 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2177 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2188 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2199 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2210 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2063 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2074 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2085 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2096 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2107 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2118 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2247 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2258 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2269 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2280 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2291 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2302 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1571 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1582 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1593 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1604 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1615 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1626 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1755 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1766 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1777 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1788 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1799 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1810 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1663 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1674 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1685 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1696 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1707 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1718 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1847 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1858 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1869 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1880 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1891 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1902 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2444 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2422 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2466 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2378 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2356 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
None

Definition at line 2400 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
State of bit (1 or 0).

Definition at line 2511 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
State of bit (1 or 0).

Definition at line 2488 of file stm32g4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
Return values:
State of bit (1 or 0).

Definition at line 2534 of file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*)
  • LL_DMA_CHANNEL_ALL (*) Not on all G4 devices
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 145 of file stm32g4xx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_PERIPH_DMA2, LL_AHB1_GRP1_ReleaseReset(), LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_ALL, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_SetPeriphRequest(), and LL_DMAMUX_REQ_MEM2MEM.

uint32_t LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7 (*)
  • LL_DMA_CHANNEL_8 (*) (*) Not on all G4 devices
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 273 of file stm32g4xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PERIPHREQUEST, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphRequest(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 341 of file stm32g4xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMAMUX_REQ_MEM2MEM, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Private Constants

Defines
DMAMUX Private Constants
DMAMUX

Defines

#define | DMAMUX_CCR_SIZE 0x00000004U
#define | DMAMUX_RGCR_SIZE 0x00000004U

Define Documentation

#define DMAMUX_CCR_SIZE 0x00000004U

Definition at line 47 of file stm32g4xx_ll_dmamux.h.

#define DMAMUX_RGCR_SIZE 0x00000004U

Definition at line 50 of file stm32g4xx_ll_dmamux.h.

Referenced by LL_DMAMUX_DisableIT_RGO(), LL_DMAMUX_DisableRequestGen(), LL_DMAMUX_EnableIT_RGO(), LL_DMAMUX_EnableRequestGen(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsEnabledIT_RGO(), LL_DMAMUX_IsEnabledRequestGen(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), and LL_DMAMUX_SetRequestSignalID().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Private Macros

Defines
DMAMUX Private Macros
DMAMUX

Defines

#define UNUSED(X) (void)X

Define Documentation

#define UNUSED ( X ) (void)X

Definition at line 59 of file stm32g4xx_ll_dmamux.h.

Referenced by HAL_ADC_ConvCpltCallback(), HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspDeInit(), HAL_ADC_MspInit(), HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), HAL_ADCEx_MultiModeGetValue(), HAL_COMP_MspDeInit(), HAL_COMP_MspInit(), HAL_COMP_TriggerCallback(), HAL_CORDIC_CalculateCpltCallback(), HAL_CORDIC_ErrorCallback(), HAL_CORDIC_MspDeInit(), HAL_CORDIC_MspInit(), HAL_CRC_MspDeInit(), HAL_CRC_MspInit(), HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MspInit(), HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), HAL_EXTI_ClearPending(), HAL_EXTI_GetPending(), HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspDeInit(), HAL_FDCAN_MspInit(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), HAL_FMAC_ErrorCallback(), HAL_FMAC_FilterConfigCallback(), HAL_FMAC_FilterPreloadCallback(), HAL_FMAC_GetDataCallback(), HAL_FMAC_HalfGetDataCallback(), HAL_FMAC_HalfOutputDataReadyCallback(), HAL_FMAC_MspDeInit(), HAL_FMAC_MspInit(), HAL_FMAC_OutputDataReadyCallback(), HAL_GPIO_EXTI_Callback(), HAL_I2C_AbortCpltCallback(), HAL_I2C_AddrCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MspDeInit(), HAL_I2C_MspInit(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2S_ErrorCallback(), HAL_I2S_MspDeInit(), HAL_I2S_MspInit(), HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ErrorCallback(), HAL_IRDA_MspDeInit(), HAL_IRDA_MspInit(), HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MspInit(), HAL_LPTIM_TriggerCallback(), HAL_OPAMP_MspDeInit(), HAL_OPAMP_MspInit(), HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_MspDeInit(), HAL_PCD_MspInit(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_LPM_Callback(), HAL_RCCEx_CRS_ErrorCallback(), HAL_RNG_ErrorCallback(), HAL_RNG_MspDeInit(), HAL_RNG_MspInit(), HAL_RNG_ReadyDataCallback(), HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MspInit(), HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), HAL_SAI_ErrorCallback(), HAL_SAI_MspDeInit(), HAL_SAI_MspInit(), HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), HAL_SMBUS_AddrCallback(), HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspDeInit(), HAL_SMBUS_MspInit(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ErrorCallback(), HAL_SPI_MspDeInit(), HAL_SPI_MspInit(), HAL_SPI_Receive(), HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_TransmitReceive(), HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), HAL_SPIEx_FlushRxFifo(), HAL_TIM_Base_MspDeInit(), HAL_TIM_Base_MspInit(), HAL_TIM_Encoder_MspDeInit(), HAL_TIM_Encoder_MspInit(), HAL_TIM_ErrorCallback(), HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_IC_MspDeInit(), HAL_TIM_IC_MspInit(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_OC_MspDeInit(), HAL_TIM_OC_MspInit(), HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_OnePulse_MspInit(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_MspDeInit(), HAL_TIM_PWM_MspInit(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_DirectionChangeCallback(), HAL_TIMEx_EncoderIndexCallback(), HAL_TIMEx_HallSensor_MspDeInit(), HAL_TIMEx_HallSensor_MspInit(), HAL_TIMEx_IndexErrorCallback(), HAL_TIMEx_TransitionErrorCallback(), HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ErrorCallback(), HAL_UART_MspDeInit(), HAL_UART_MspInit(), HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UARTEx_RxEventCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), HAL_USART_AbortCpltCallback(), HAL_USART_ErrorCallback(), HAL_USART_MspDeInit(), HAL_USART_MspInit(), HAL_USART_Receive_DMA(), HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_MspInit(), I2C_ITAddrCplt(), I2C_ITMasterCplt(), LL_DMAMUX_ClearFlag_RGO0(), LL_DMAMUX_ClearFlag_RGO1(), LL_DMAMUX_ClearFlag_RGO2(), LL_DMAMUX_ClearFlag_RGO3(), LL_DMAMUX_ClearFlag_SO0(), LL_DMAMUX_ClearFlag_SO1(), LL_DMAMUX_ClearFlag_SO10(), LL_DMAMUX_ClearFlag_SO11(), LL_DMAMUX_ClearFlag_SO2(), LL_DMAMUX_ClearFlag_SO3(), LL_DMAMUX_ClearFlag_SO4(), LL_DMAMUX_ClearFlag_SO5(), LL_DMAMUX_ClearFlag_SO6(), LL_DMAMUX_ClearFlag_SO7(), LL_DMAMUX_ClearFlag_SO8(), LL_DMAMUX_ClearFlag_SO9(), LL_DMAMUX_DisableIT_RGO(), LL_DMAMUX_EnableIT_RGO(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsActiveFlag_RGO0(), LL_DMAMUX_IsActiveFlag_RGO1(), LL_DMAMUX_IsActiveFlag_RGO2(), LL_DMAMUX_IsActiveFlag_RGO3(), LL_DMAMUX_IsActiveFlag_SO0(), LL_DMAMUX_IsActiveFlag_SO1(), LL_DMAMUX_IsActiveFlag_SO10(), LL_DMAMUX_IsActiveFlag_SO11(), LL_DMAMUX_IsActiveFlag_SO2(), LL_DMAMUX_IsActiveFlag_SO3(), LL_DMAMUX_IsActiveFlag_SO4(), LL_DMAMUX_IsActiveFlag_SO5(), LL_DMAMUX_IsActiveFlag_SO6(), LL_DMAMUX_IsActiveFlag_SO7(), LL_DMAMUX_IsActiveFlag_SO8(), LL_DMAMUX_IsActiveFlag_SO9(), LL_DMAMUX_IsEnabledIT_RGO(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), LL_DMAMUX_SetRequestSignalID(), LL_RTC_BKP_GetRegister(), LL_RTC_BKP_SetRegister(), LL_RTC_ClearFlag_ITAMP3(), LL_RTC_ClearFlag_ITAMP4(), LL_RTC_ClearFlag_ITAMP5(), LL_RTC_ClearFlag_ITAMP6(), LL_RTC_ClearFlag_TAMP1(), LL_RTC_ClearFlag_TAMP2(), LL_RTC_ClearFlag_TAMP3(), LL_RTC_DisableIT_ITAMP3(), LL_RTC_DisableIT_ITAMP4(), LL_RTC_DisableIT_ITAMP5(), LL_RTC_DisableIT_ITAMP6(), LL_RTC_DisableIT_TAMP1(), LL_RTC_DisableIT_TAMP2(), LL_RTC_DisableIT_TAMP3(), LL_RTC_EnableIT_ITAMP3(), LL_RTC_EnableIT_ITAMP4(), LL_RTC_EnableIT_ITAMP5(), LL_RTC_EnableIT_ITAMP6(), LL_RTC_EnableIT_TAMP1(), LL_RTC_EnableIT_TAMP2(), LL_RTC_EnableIT_TAMP3(), LL_RTC_IsActiveFlag_ITAMP3(), LL_RTC_IsActiveFlag_ITAMP3M(), LL_RTC_IsActiveFlag_ITAMP4(), LL_RTC_IsActiveFlag_ITAMP4M(), LL_RTC_IsActiveFlag_ITAMP5(), LL_RTC_IsActiveFlag_ITAMP5M(), LL_RTC_IsActiveFlag_ITAMP6(), LL_RTC_IsActiveFlag_ITAMP6M(), LL_RTC_IsActiveFlag_TAMP1(), LL_RTC_IsActiveFlag_TAMP1M(), LL_RTC_IsActiveFlag_TAMP2(), LL_RTC_IsActiveFlag_TAMP2M(), LL_RTC_IsActiveFlag_TAMP3(), LL_RTC_IsActiveFlag_TAMP3M(), LL_RTC_IsEnabledIT_ITAMP3(), LL_RTC_IsEnabledIT_ITAMP4(), LL_RTC_IsEnabledIT_ITAMP5(), LL_RTC_IsEnabledIT_ITAMP6(), LL_RTC_IsEnabledIT_TAMP1(), LL_RTC_IsEnabledIT_TAMP2(), LL_RTC_IsEnabledIT_TAMP3(), LL_RTC_TAMPER_Disable(), LL_RTC_TAMPER_DisableActiveLevel(), LL_RTC_TAMPER_DisableEraseBKP(), LL_RTC_TAMPER_DisableMask(), LL_RTC_TAMPER_DisablePullUp(), LL_RTC_TAMPER_Enable(), LL_RTC_TAMPER_EnableActiveLevel(), LL_RTC_TAMPER_EnableEraseBKP(), LL_RTC_TAMPER_EnableMask(), LL_RTC_TAMPER_EnablePullUp(), LL_RTC_TAMPER_GetFilterCount(), LL_RTC_TAMPER_GetPrecharge(), LL_RTC_TAMPER_GetSamplingFreq(), LL_RTC_TAMPER_ITAMP_Disable(), LL_RTC_TAMPER_ITAMP_Enable(), LL_RTC_TAMPER_SetFilterCount(), LL_RTC_TAMPER_SetPrecharge(), LL_RTC_TAMPER_SetSamplingFreq(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BITCRC(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BITCRC(), and SPI_WaitFifoStateUntilTimeout().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_WriteReg function. More...

Defines

#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14
#define | LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Define Documentation

#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 73 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 74 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 83 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 84 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 85 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 86 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14

Synchronization Event Overrun Flag Channel 14

Definition at line 87 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15

Synchronization Event Overrun Flag Channel 15

Definition at line 88 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 75 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 76 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 77 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 78 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 79 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 80 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 81 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 82 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 89 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 90 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 91 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 92 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_ReadReg function. More...

Defines

#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14
#define | LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_ReadReg function.

Define Documentation

#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 101 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 102 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 111 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 112 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 113 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 114 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14

Synchronization Event Overrun Flag Channel 14

Definition at line 115 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15

Synchronization Event Overrun Flag Channel 15

Definition at line 116 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 103 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 104 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 105 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 106 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 107 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 108 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 109 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 110 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 117 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 118 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 119 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 120 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
DMAMUX Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions. More...

Defines

#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Define Documentation

#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE

Synchronization Event Overrun Interrupt

Definition at line 129 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Request Generation Trigger Event Overrun Interrupt

Definition at line 130 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer request

Defines
Transfer request
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_DAC1_CH1 0x00000006U
#define | LL_DMAMUX_REQ_DAC1_CH2 0x00000007U
#define | LL_DMAMUX_REQ_TIM6_UP 0x00000008U
#define | LL_DMAMUX_REQ_TIM7_UP 0x00000009U
#define | LL_DMAMUX_REQ_SPI1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_SPI1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_SPI2_RX 0x0000000CU
#define | LL_DMAMUX_REQ_SPI2_TX 0x0000000DU
#define | LL_DMAMUX_REQ_SPI3_RX 0x0000000EU
#define | LL_DMAMUX_REQ_SPI3_TX 0x0000000FU
#define | LL_DMAMUX_REQ_I2C1_RX 0x00000010U
#define | LL_DMAMUX_REQ_I2C1_TX 0x00000011U
#define | LL_DMAMUX_REQ_I2C2_RX 0x00000012U
#define | LL_DMAMUX_REQ_I2C2_TX 0x00000013U
#define | LL_DMAMUX_REQ_I2C3_RX 0x00000014U
#define | LL_DMAMUX_REQ_I2C3_TX 0x00000015U
#define | LL_DMAMUX_REQ_I2C4_RX 0x00000016U
#define | LL_DMAMUX_REQ_I2C4_TX 0x00000017U
#define | LL_DMAMUX_REQ_USART1_RX 0x00000018U
#define | LL_DMAMUX_REQ_USART1_TX 0x00000019U
#define | LL_DMAMUX_REQ_USART2_RX 0x0000001AU
#define | LL_DMAMUX_REQ_USART2_TX 0x0000001BU
#define | LL_DMAMUX_REQ_USART3_RX 0x0000001CU
#define | LL_DMAMUX_REQ_USART3_TX 0x0000001DU
#define | LL_DMAMUX_REQ_UART4_RX 0x0000001EU
#define | LL_DMAMUX_REQ_UART4_TX 0x0000001FU
#define | LL_DMAMUX_REQ_UART5_RX 0x00000020U
#define | LL_DMAMUX_REQ_UART5_TX 0x00000021U
#define | LL_DMAMUX_REQ_LPUART1_RX 0x00000022U
#define | LL_DMAMUX_REQ_LPUART1_TX 0x00000023U
#define | LL_DMAMUX_REQ_ADC2 0x00000024U
#define | LL_DMAMUX_REQ_ADC3 0x00000025U
#define | LL_DMAMUX_REQ_ADC4 0x00000026U
#define | LL_DMAMUX_REQ_ADC5 0x00000027U
#define | LL_DMAMUX_REQ_QSPI 0x00000028U
#define | LL_DMAMUX_REQ_DAC2_CH1 0x00000029U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU
#define | LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU
#define | LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU
#define | LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU
#define | LL_DMAMUX_REQ_TIM1_UP 0x0000002EU
#define | LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU
#define | LL_DMAMUX_REQ_TIM1_COM 0x00000030U
#define | LL_DMAMUX_REQ_TIM8_CH1 0x00000031U
#define | LL_DMAMUX_REQ_TIM8_CH2 0x00000032U
#define | LL_DMAMUX_REQ_TIM8_CH3 0x00000033U
#define | LL_DMAMUX_REQ_TIM8_CH4 0x00000034U
#define | LL_DMAMUX_REQ_TIM8_UP 0x00000035U
#define | LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U
#define | LL_DMAMUX_REQ_TIM8_COM 0x00000037U
#define | LL_DMAMUX_REQ_TIM2_CH1 0x00000038U
#define | LL_DMAMUX_REQ_TIM2_CH2 0x00000039U
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU
#define | LL_DMAMUX_REQ_TIM2_UP 0x0000003CU
#define | LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU
#define | LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU
#define | LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU
#define | LL_DMAMUX_REQ_TIM3_CH4 0x00000040U
#define | LL_DMAMUX_REQ_TIM3_UP 0x00000041U
#define | LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U
#define | LL_DMAMUX_REQ_TIM4_CH1 0x00000043U
#define | LL_DMAMUX_REQ_TIM4_CH2 0x00000044U
#define | LL_DMAMUX_REQ_TIM4_CH3 0x00000045U
#define | LL_DMAMUX_REQ_TIM4_CH4 0x00000046U
#define | LL_DMAMUX_REQ_TIM4_UP 0x00000047U
#define | LL_DMAMUX_REQ_TIM5_CH1 0x00000048U
#define | LL_DMAMUX_REQ_TIM5_CH2 0x00000049U
#define | LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU
#define | LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU
#define | LL_DMAMUX_REQ_TIM5_UP 0x0000004CU
#define | LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU
#define | LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU
#define | LL_DMAMUX_REQ_TIM15_UP 0x0000004FU
#define | LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U
#define | LL_DMAMUX_REQ_TIM15_COM 0x00000051U
#define | LL_DMAMUX_REQ_TIM16_CH1 0x00000052U
#define | LL_DMAMUX_REQ_TIM16_UP 0x00000053U
#define | LL_DMAMUX_REQ_TIM17_CH1 0x00000054U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000055U
#define | LL_DMAMUX_REQ_TIM20_CH1 0x00000056U
#define | LL_DMAMUX_REQ_TIM20_CH2 0x00000057U
#define | LL_DMAMUX_REQ_TIM20_CH3 0x00000058U
#define | LL_DMAMUX_REQ_TIM20_CH4 0x00000059U
#define | LL_DMAMUX_REQ_TIM20_UP 0x0000005AU
#define | LL_DMAMUX_REQ_AES_IN 0x0000005BU
#define | LL_DMAMUX_REQ_AES_OUT 0x0000005CU
#define | LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU
#define | LL_DMAMUX_REQ_TIM20_COM 0x0000005EU
#define | LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU
#define | LL_DMAMUX_REQ_HRTIM1_A 0x00000060U
#define | LL_DMAMUX_REQ_HRTIM1_B 0x00000061U
#define | LL_DMAMUX_REQ_HRTIM1_C 0x00000062U
#define | LL_DMAMUX_REQ_HRTIM1_D 0x00000063U
#define | LL_DMAMUX_REQ_HRTIM1_E 0x00000064U
#define | LL_DMAMUX_REQ_HRTIM1_F 0x00000065U
#define | LL_DMAMUX_REQ_DAC3_CH1 0x00000066U
#define | LL_DMAMUX_REQ_DAC3_CH2 0x00000067U
#define | LL_DMAMUX_REQ_DAC4_CH1 0x00000068U
#define | LL_DMAMUX_REQ_DAC4_CH2 0x00000069U
#define | LL_DMAMUX_REQ_SPI4_RX 0x0000006AU
#define | LL_DMAMUX_REQ_SPI4_TX 0x0000006BU
#define | LL_DMAMUX_REQ_SAI1_A 0x0000006CU
#define | LL_DMAMUX_REQ_SAI1_B 0x0000006DU
#define | LL_DMAMUX_REQ_FMAC_READ 0x0000006EU
#define | LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU
#define | LL_DMAMUX_REQ_CORDIC_READ 0x00000070U
#define | LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U
#define | LL_DMAMUX_REQ_UCPD1_RX 0x00000072U
#define | LL_DMAMUX_REQ_UCPD1_TX 0x00000073U

Define Documentation

#define LL_DMAMUX_REQ_ADC1 0x00000005U

DMAMUX ADC1 request

Definition at line 143 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_ADC2 0x00000024U

DMAMUX ADC2 request

Definition at line 174 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_ADC3 0x00000025U

DMAMUX ADC3 request

Definition at line 175 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_ADC4 0x00000026U

DMAMUX ADC4 request

Definition at line 176 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_ADC5 0x00000027U

DMAMUX ADC5 request

Definition at line 177 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES_IN 0x0000005BU

DMAMUX AES_IN request

Definition at line 229 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES_OUT 0x0000005CU

DMAMUX AES_OUT request

Definition at line 230 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_CORDIC_READ 0x00000070U

DMAMUX CORDIC READ request

Definition at line 250 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U

DMAMUX CORDIC WRITE request

Definition at line 251 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC1_CH1 0x00000006U

DMAMUX DAC1 CH1 request

Definition at line 144 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC1_CH2 0x00000007U

DMAMUX DAC1 CH2 request

Definition at line 145 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC2_CH1 0x00000029U

DMAMUX DAC2 CH1 request

Definition at line 179 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC3_CH1 0x00000066U

DMAMUX DAC3 CH1 request

Definition at line 240 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC3_CH2 0x00000067U

DMAMUX DAC3 CH2 request

Definition at line 241 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC4_CH1 0x00000068U

DMAMUX DAC4 CH1 request

Definition at line 242 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC4_CH2 0x00000069U

DMAMUX DAC4 CH2 request

Definition at line 243 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU

DMAMUX FMAC READ request

Definition at line 248 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU

DMAMUX FMAC WRITE request

Definition at line 249 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U

DMAMUX request generator 0

Definition at line 139 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U

DMAMUX request generator 1

Definition at line 140 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U

DMAMUX request generator 2

Definition at line 141 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U

DMAMUX request generator 3

Definition at line 142 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_A 0x00000060U

DMAMUX HRTIM A request

Definition at line 234 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_B 0x00000061U

DMAMUX HRTIM B request

Definition at line 235 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_C 0x00000062U

DMAMUX HRTIM C request

Definition at line 236 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_D 0x00000063U

DMAMUX HRTIM D request

Definition at line 237 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_E 0x00000064U

DMAMUX HRTIM E request

Definition at line 238 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_F 0x00000065U

DMAMUX HRTIM F request

Definition at line 239 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU

DMAMUX HRTIM M request

Definition at line 233 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_RX 0x00000010U

DMAMUX I2C1 RX request

Definition at line 154 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_TX 0x00000011U

DMAMUX I2C1 TX request

Definition at line 155 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C2_RX 0x00000012U

DMAMUX I2C2 RX request

Definition at line 156 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C2_TX 0x00000013U

DMAMUX I2C2 TX request

Definition at line 157 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_RX 0x00000014U

DMAMUX I2C3 RX request

Definition at line 158 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_TX 0x00000015U

DMAMUX I2C3 TX request

Definition at line 159 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C4_RX 0x00000016U

DMAMUX I2C4 RX request

Definition at line 160 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C4_TX 0x00000017U

DMAMUX I2C4 TX request

Definition at line 161 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_RX 0x00000022U

DMAMUX LPUART1 RX request

Definition at line 172 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_TX 0x00000023U

DMAMUX LPUART1 TX request

Definition at line 173 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U

Memory to memory transfer

Definition at line 138 of file stm32g4xx_ll_dmamux.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_StructInit().

#define LL_DMAMUX_REQ_QSPI 0x00000028U

DMAMUX QSPI request

Definition at line 178 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SAI1_A 0x0000006CU

DMAMUX SAI1 A request

Definition at line 246 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SAI1_B 0x0000006DU

DMAMUX SAI1 B request

Definition at line 247 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI1_RX 0x0000000AU

DMAMUX SPI1 RX request

Definition at line 148 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI1_TX 0x0000000BU

DMAMUX SPI1 TX request

Definition at line 149 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_RX 0x0000000CU

DMAMUX SPI2 RX request

Definition at line 150 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_TX 0x0000000DU

DMAMUX SPI2 TX request

Definition at line 151 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI3_RX 0x0000000EU

DMAMUX SPI3 RX request

Definition at line 152 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI3_TX 0x0000000FU

DMAMUX SPI3 TX request

Definition at line 153 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI4_RX 0x0000006AU

DMAMUX SPI4 RX request

Definition at line 244 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU

DMAMUX SPI4 TX request

Definition at line 245 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU

DMAMUX TIM15 CH1 request

Definition at line 216 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_COM 0x00000051U

DMAMUX TIM15 COM request

Definition at line 219 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U

DMAMUX TIM15 TRIG request

Definition at line 218 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_UP 0x0000004FU

DMAMUX TIM15 UP request

Definition at line 217 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_CH1 0x00000052U

DMAMUX TIM16 CH1 request

Definition at line 220 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_UP 0x00000053U

DMAMUX TIM16 UP request

Definition at line 221 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_CH1 0x00000054U

DMAMUX TIM17 CH1 request

Definition at line 222 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_UP 0x00000055U

DMAMUX TIM17 UP request

Definition at line 223 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU

DMAMUX TIM1 CH1 request

Definition at line 180 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU

DMAMUX TIM1 CH2 request

Definition at line 181 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU

DMAMUX TIM1 CH3 request

Definition at line 182 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU

DMAMUX TIM1 CH4 request

Definition at line 183 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_COM 0x00000030U

DMAMUX TIM1 COM request

Definition at line 186 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU

DMAMUX TIM1 TRIG request

Definition at line 185 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_UP 0x0000002EU

DMAMUX TIM1 UP request

Definition at line 184 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_CH1 0x00000056U

DMAMUX TIM20 CH1 request

Definition at line 224 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_CH2 0x00000057U

DMAMUX TIM20 CH2 request

Definition at line 225 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_CH3 0x00000058U

DMAMUX TIM20 CH3 request

Definition at line 226 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_CH4 0x00000059U

DMAMUX TIM20 CH4 request

Definition at line 227 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_COM 0x0000005EU

DMAMUX TIM20 COM request

Definition at line 232 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU

DMAMUX TIM20 TRIG request

Definition at line 231 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM20_UP 0x0000005AU

DMAMUX TIM20 UP request

Definition at line 228 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH1 0x00000038U

DMAMUX TIM2 CH1 request

Definition at line 194 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH2 0x00000039U

DMAMUX TIM2 CH2 request

Definition at line 195 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU

DMAMUX TIM2 CH3 request

Definition at line 196 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU

DMAMUX TIM2 CH4 request

Definition at line 197 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_UP 0x0000003CU

DMAMUX TIM2 UP request

Definition at line 198 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU

DMAMUX TIM3 CH1 request

Definition at line 199 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU

DMAMUX TIM3 CH2 request

Definition at line 200 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU

DMAMUX TIM3 CH3 request

Definition at line 201 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH4 0x00000040U

DMAMUX TIM3 CH4 request

Definition at line 202 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U

DMAMUX TIM3 TRIG request

Definition at line 204 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_UP 0x00000041U

DMAMUX TIM3 UP request

Definition at line 203 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH1 0x00000043U

DMAMUX TIM4 CH1 request

Definition at line 205 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH2 0x00000044U

DMAMUX TIM4 CH2 request

Definition at line 206 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH3 0x00000045U

DMAMUX TIM4 CH3 request

Definition at line 207 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH4 0x00000046U

DMAMUX TIM4 CH4 request

Definition at line 208 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_UP 0x00000047U

DMAMUX TIM4 UP request

Definition at line 209 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_CH1 0x00000048U

DMAMUX TIM5 CH1 request

Definition at line 210 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_CH2 0x00000049U

DMAMUX TIM5 CH2 request

Definition at line 211 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU

DMAMUX TIM5 CH3 request

Definition at line 212 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU

DMAMUX TIM5 CH4 request

Definition at line 213 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU

DMAMUX TIM5 TRIG request

Definition at line 215 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM5_UP 0x0000004CU

DMAMUX TIM5 UP request

Definition at line 214 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM6_UP 0x00000008U

DMAMUX TIM6 UP request

Definition at line 146 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM7_UP 0x00000009U

DMAMUX TIM7 UP request

Definition at line 147 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_CH1 0x00000031U

DMAMUX TIM8 CH1 request

Definition at line 187 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_CH2 0x00000032U

DMAMUX TIM8 CH2 request

Definition at line 188 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_CH3 0x00000033U

DMAMUX TIM8 CH3 request

Definition at line 189 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_CH4 0x00000034U

DMAMUX TIM8 CH4 request

Definition at line 190 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_COM 0x00000037U

DMAMUX TIM8 COM request

Definition at line 193 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U

DMAMUX TIM8 TRIG request

Definition at line 192 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM8_UP 0x00000035U

DMAMUX TIM8 UP request

Definition at line 191 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UART4_RX 0x0000001EU

DMAMUX UART4 RX request

Definition at line 168 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UART4_TX 0x0000001FU

DMAMUX UART4 TX request

Definition at line 169 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UART5_RX 0x00000020U

DMAMUX UART5 RX request

Definition at line 170 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UART5_TX 0x00000021U

DMAMUX UART5 TX request

Definition at line 171 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U

DMAMUX USBPD1_RX request

Definition at line 252 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U

DMAMUX USBPD1_TX request

Definition at line 253 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_RX 0x00000018U

DMAMUX USART1 RX request

Definition at line 162 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_TX 0x00000019U

DMAMUX USART1 TX request

Definition at line 163 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART2_RX 0x0000001AU

DMAMUX USART2 RX request

Definition at line 164 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART2_TX 0x0000001BU

DMAMUX USART2 TX request

Definition at line 165 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART3_RX 0x0000001CU

DMAMUX USART3 RX request

Definition at line 166 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART3_TX 0x0000001DU

DMAMUX USART3 TX request

Definition at line 167 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Channel

Defines
DMAMUX Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU
#define | LL_DMAMUX_CHANNEL_14 0x0000000EU
#define | LL_DMAMUX_CHANNEL_15 0x0000000FU

Define Documentation

#define LL_DMAMUX_CHANNEL_0 0x00000000U

DMAMUX Channel 0 connected to DMA1 Channel 1

Definition at line 262 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_1 0x00000001U

DMAMUX Channel 1 connected to DMA1 Channel 2

Definition at line 263 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_10 0x0000000AU

DMAMUX Channel 10 connected to DMA2 Channel 3

Definition at line 272 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_11 0x0000000BU

DMAMUX Channel 11 connected to DMA2 Channel 4

Definition at line 273 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_12 0x0000000CU

DMAMUX Channel 12 connected to DMA2 Channel 5

Definition at line 274 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_13 0x0000000DU

DMAMUX Channel 13 connected to DMA2 Channel 6

Definition at line 275 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_14 0x0000000EU

DMAMUX Channel 14 connected to DMA2 Channel 7

Definition at line 276 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_15 0x0000000FU

DMAMUX Channel 15 connected to DMA2 Channel 8

Definition at line 277 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_2 0x00000002U

DMAMUX Channel 2 connected to DMA1 Channel 3

Definition at line 264 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_3 0x00000003U

DMAMUX Channel 3 connected to DMA1 Channel 4

Definition at line 265 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_4 0x00000004U

DMAMUX Channel 4 connected to DMA1 Channel 5

Definition at line 266 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_5 0x00000005U

DMAMUX Channel 5 connected to DMA1 Channel 6

Definition at line 267 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_6 0x00000006U

DMAMUX Channel 6 connected to DMA1 Channel 7

Definition at line 268 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_7 0x00000007U

DMAMUX Channel 7 connected to DMA1 Channel 8

Definition at line 269 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_8 0x00000008U

DMAMUX Channel 8 connected to DMA2 Channel 1

Definition at line 270 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_9 0x00000009U

DMAMUX Channel 9 connected to DMA2 Channel 2

Definition at line 271 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Define Documentation

#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U

All requests are blocked

Definition at line 285 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1

Synchronization on event on falling edge

Definition at line 287 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0

Synchronization on event on rising edge

Definition at line 286 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Synchronization on event on rising and falling edge

Definition at line 288 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Synchronization Signal Event

Defines
Synchronization Signal Event
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)

Define Documentation

#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4

Synchronization signal from DMAMUX channel0 Event

Definition at line 312 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from DMAMUX channel1 Event

Definition at line 313 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from DMAMUX channel2 Event

Definition at line 314 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from DMAMUX channel3 Event

Definition at line 315 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U

Synchronization signal from EXTI Line0

Definition at line 296 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0

Synchronization signal from EXTI Line1

Definition at line 297 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line10

Definition at line 306 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line11

Definition at line 307 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)

Synchronization signal from EXTI Line12

Definition at line 308 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line13

Definition at line 309 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line14

Definition at line 310 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line15

Definition at line 311 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1

Synchronization signal from EXTI Line2

Definition at line 298 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line3

Definition at line 299 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2

Synchronization signal from EXTI Line4

Definition at line 300 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line5

Definition at line 301 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line6

Definition at line 302 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line7

Definition at line 303 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3

Synchronization signal from EXTI Line8

Definition at line 304 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line9

Definition at line 305 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)

Synchronization signal from LPTIM1 Output

Definition at line 316 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Request Generator Channel

Defines
Request Generator Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U

Define Documentation

#define LL_DMAMUX_REQ_GEN_0 0x00000000U

Definition at line 324 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_1 0x00000001U

Definition at line 325 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_2 0x00000002U

Definition at line 326 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_3 0x00000003U

Definition at line 327 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Request Signal Generation Polarity

Defines
External Request Signal Generation Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

Define Documentation

#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

No external DMA request generation

Definition at line 335 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1

External DMA request generation on event on falling edge

Definition at line 337 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0

External DMA request generation on event on rising edge

Definition at line 336 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

External DMA request generation on rising and falling edge

Definition at line 338 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Request Signal Generation

Defines
External Request Signal Generation
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)

Define Documentation

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4

Request signal generation from DMAMUX channel0 Event

Definition at line 362 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from DMAMUX channel1 Event

Definition at line 363 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from DMAMUX channel2 Event

Definition at line 364 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from DMAMUX channel3 Event

Definition at line 365 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U

Request signal generation from EXTI Line0

Definition at line 346 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0

Request signal generation from EXTI Line1

Definition at line 347 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line10

Definition at line 356 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line11

Definition at line 357 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)

Request signal generation from EXTI Line12

Definition at line 358 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line13

Definition at line 359 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line14

Definition at line 360 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line15

Definition at line 361 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1

Request signal generation from EXTI Line2

Definition at line 348 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line3

Definition at line 349 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2

Request signal generation from EXTI Line4

Definition at line 350 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line5

Definition at line 351 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line6

Definition at line 352 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line7

Definition at line 353 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3

Request signal generation from EXTI Line8

Definition at line 354 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line9

Definition at line 355 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)

Request signal generation from LPTIM1 Output

Definition at line 366 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMAMUX Exported Macros

Defines

#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Define Documentation

#define LL_DMAMUX_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 397 of file stm32g4xx_ll_dmamux.h.

#define LL_DMAMUX_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 389 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_DisableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 891 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_DisableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_DisableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1142 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_DisableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 978 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_EnableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 862 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_EnableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1125 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_EnableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 949 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the number of DMA request that will be autorized after a generation event.

Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 1243 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Definition at line 1204 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8. DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15 (*) Not on all G4 devices
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_SPI3_RX
  • LL_DMAMUX_REQ_SPI3_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX (*)
  • LL_DMAMUX_REQ_I2C4_RX (*)
  • LL_DMAMUX_REQ_I2C4_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_UART4_RX
  • LL_DMAMUX_REQ_UART4_TX
  • LL_DMAMUX_REQ_UART5_RX (*)
  • LL_DMAMUX_REQ_UART5_TX (*)
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_ADC2
  • LL_DMAMUX_REQ_ADC3 (*)
  • LL_DMAMUX_REQ_ADC4 (*)
  • LL_DMAMUX_REQ_ADC5 (*)
  • LL_DMAMUX_REQ_QSPI (*)
  • LL_DMAMUX_REQ_DAC2_CH1 (*)
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM8_CH1
  • LL_DMAMUX_REQ_TIM8_CH2
  • LL_DMAMUX_REQ_TIM8_CH3
  • LL_DMAMUX_REQ_TIM8_CH4
  • LL_DMAMUX_REQ_TIM8_UP
  • LL_DMAMUX_REQ_TIM8_TRIG
  • LL_DMAMUX_REQ_TIM8_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM4_CH1
  • LL_DMAMUX_REQ_TIM4_CH2
  • LL_DMAMUX_REQ_TIM4_CH3
  • LL_DMAMUX_REQ_TIM4_CH4
  • LL_DMAMUX_REQ_TIM4_UP
  • LL_DMAMUX_REQ_TIM5_CH1 (*)
  • LL_DMAMUX_REQ_TIM5_CH2 (*)
  • LL_DMAMUX_REQ_TIM5_CH3 (*)
  • LL_DMAMUX_REQ_TIM5_CH4 (*)
  • LL_DMAMUX_REQ_TIM5_UP (*)
  • LL_DMAMUX_REQ_TIM5_TRIG (*)
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM15_TRIG
  • LL_DMAMUX_REQ_TIM15_COM
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_TIM20_CH1 (*)
  • LL_DMAMUX_REQ_TIM20_CH2 (*)
  • LL_DMAMUX_REQ_TIM20_CH3 (*)
  • LL_DMAMUX_REQ_TIM20_CH4 (*)
  • LL_DMAMUX_REQ_TIM20_UP (*)
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_TIM20_TRIG (*)
  • LL_DMAMUX_REQ_TIM20_COM (*)
  • LL_DMAMUX_REQ_HRTIM1_M (*)
  • LL_DMAMUX_REQ_HRTIM1_A (*)
  • LL_DMAMUX_REQ_HRTIM1_B (*)
  • LL_DMAMUX_REQ_HRTIM1_C (*)
  • LL_DMAMUX_REQ_HRTIM1_D (*)
  • LL_DMAMUX_REQ_HRTIM1_E (*)
  • LL_DMAMUX_REQ_HRTIM1_F (*)
  • LL_DMAMUX_REQ_DAC3_CH1
  • LL_DMAMUX_REQ_DAC3_CH2
  • LL_DMAMUX_REQ_DAC4_CH1 (*)
  • LL_DMAMUX_REQ_DAC4_CH2 (*)
  • LL_DMAMUX_REQ_SPI4_RX (*)
  • LL_DMAMUX_REQ_SPI4_TX (*)
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_CORDIC_WRITE
  • LL_DMAMUX_REQ_CORDIC_READ
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX (*) Not on all G4 devices

Definition at line 707 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT

Definition at line 1323 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_GetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_DMAMUX_CH2
  • LL_DMAMUX_SYNC_DMAMUX_CH3
  • LL_DMAMUX_SYNC_LPTIM1_OUT

Definition at line 1108 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_GetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING

Definition at line 833 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 766 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Event Generation on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 920 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generator is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_IsEnabledRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 1159 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the synchronization mode is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_IsEnabledSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1007 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a generation event.

Note:
This field can only be written when Generator is disabled.
Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 1224 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
Return values:
None

Definition at line 1181 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE void LL_DMAMUX_SetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8. DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Request This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_SPI3_RX
  • LL_DMAMUX_REQ_SPI3_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX (*)
  • LL_DMAMUX_REQ_I2C4_RX (*)
  • LL_DMAMUX_REQ_I2C4_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_UART4_RX
  • LL_DMAMUX_REQ_UART4_TX
  • LL_DMAMUX_REQ_UART5_RX (*)
  • LL_DMAMUX_REQ_UART5_TX (*)
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_ADC2
  • LL_DMAMUX_REQ_ADC3 (*)
  • LL_DMAMUX_REQ_ADC4 (*)
  • LL_DMAMUX_REQ_ADC5 (*)
  • LL_DMAMUX_REQ_QSPI (*)
  • LL_DMAMUX_REQ_DAC2_CH1 (*)
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM8_CH1
  • LL_DMAMUX_REQ_TIM8_CH2
  • LL_DMAMUX_REQ_TIM8_CH3
  • LL_DMAMUX_REQ_TIM8_CH4
  • LL_DMAMUX_REQ_TIM8_UP
  • LL_DMAMUX_REQ_TIM8_TRIG
  • LL_DMAMUX_REQ_TIM8_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM4_CH1
  • LL_DMAMUX_REQ_TIM4_CH2
  • LL_DMAMUX_REQ_TIM4_CH3
  • LL_DMAMUX_REQ_TIM4_CH4
  • LL_DMAMUX_REQ_TIM4_UP
  • LL_DMAMUX_REQ_TIM5_CH1 (*)
  • LL_DMAMUX_REQ_TIM5_CH2 (*)
  • LL_DMAMUX_REQ_TIM5_CH3 (*)
  • LL_DMAMUX_REQ_TIM5_CH4 (*)
  • LL_DMAMUX_REQ_TIM5_UP (*)
  • LL_DMAMUX_REQ_TIM5_TRIG (*)
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM15_TRIG
  • LL_DMAMUX_REQ_TIM15_COM
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_TIM20_CH1 (*)
  • LL_DMAMUX_REQ_TIM20_CH2 (*)
  • LL_DMAMUX_REQ_TIM20_CH3 (*)
  • LL_DMAMUX_REQ_TIM20_CH4 (*)
  • LL_DMAMUX_REQ_TIM20_UP (*)
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_TIM20_TRIG (*)
  • LL_DMAMUX_REQ_TIM20_COM (*)
  • LL_DMAMUX_REQ_HRTIM1_M (*)
  • LL_DMAMUX_REQ_HRTIM1_A (*)
  • LL_DMAMUX_REQ_HRTIM1_B (*)
  • LL_DMAMUX_REQ_HRTIM1_C (*)
  • LL_DMAMUX_REQ_HRTIM1_D (*)
  • LL_DMAMUX_REQ_HRTIM1_E (*)
  • LL_DMAMUX_REQ_HRTIM1_F (*)
  • LL_DMAMUX_REQ_DAC3_CH1
  • LL_DMAMUX_REQ_DAC3_CH2
  • LL_DMAMUX_REQ_DAC4_CH1 (*)
  • LL_DMAMUX_REQ_DAC4_CH2 (*)
  • LL_DMAMUX_REQ_SPI4_RX (*)
  • LL_DMAMUX_REQ_SPI4_TX (*)
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_FMAC_WRITE
  • LL_DMAMUX_REQ_CORDIC_WRITE
  • LL_DMAMUX_REQ_CORDIC_READ
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX (*) Not on all G4 devices
Return values:
None

Definition at line 557 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestSignalID
 | ) |  |

Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestSignalID This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT
Return values:
None

Definition at line 1283 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE void LL_DMAMUX_SetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | SyncID
 | ) |  |

Set DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_SetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
SyncID This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_DMAMUX_CH2
  • LL_DMAMUX_SYNC_DMAMUX_CH3
  • LL_DMAMUX_SYNC_LPTIM1_OUT
Return values:
None

Definition at line 1058 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_SetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING
Return values:
None

Definition at line 800 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 737 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1792 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1804 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1816 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1828 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1592 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1604 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1712 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1724 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1616 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1628 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1640 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1652 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1664 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1676 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1688 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1700 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1544 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1556 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1568 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1580 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1344 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1356 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1464 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1476 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1368 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1380 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1392 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1404 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1416 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1428 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1440 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1452 of file stm32g4xx_ll_dmamux.h.

References UNUSED.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_DisableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1958 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE void LL_DMAMUX_DisableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_DisableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1894 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_EnableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1940 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE void LL_DMAMUX_EnableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_EnableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
None

Definition at line 1865 of file stm32g4xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 1976 of file stm32g4xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE, and UNUSED.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
  • LL_DMAMUX_CHANNEL_14
  • LL_DMAMUX_CHANNEL_15
Return values:
State of bit (1 or 0).

Definition at line 1923 of file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 46 of file stm32g4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_32_63 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)

Definition at line 47 of file stm32g4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                      || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                      || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 49 of file stm32g4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 54 of file stm32g4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32g4xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
uint32_t | Line_32_63
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 57 of file stm32g4xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 60 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_32_63

Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of LINE

Definition at line 63 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 66 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 69 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 72 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_exti.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE 0x00000000U

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR1_IM0

Extended line 0

Definition at line 89 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR1_IM1

Extended line 1

Definition at line 90 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR1_IM10

Extended line 10

Definition at line 99 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR1_IM11

Extended line 11

Definition at line 100 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR1_IM12

Extended line 12

Definition at line 101 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR1_IM13

Extended line 13

Definition at line 102 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR1_IM14

Extended line 14

Definition at line 103 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR1_IM15

Extended line 15

Definition at line 104 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR1_IM16

Extended line 16

Definition at line 106 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR1_IM17

Extended line 17

Definition at line 108 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR1_IM18

Extended line 18

Definition at line 110 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR1_IM19

Extended line 19

Definition at line 112 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR1_IM2

Extended line 2

Definition at line 91 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR1_IM20

Extended line 20

Definition at line 114 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR1_IM21

Extended line 21

Definition at line 117 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR1_IM22

Extended line 22

Definition at line 120 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR1_IM23

Extended line 23

Definition at line 122 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR1_IM24

Extended line 24

Definition at line 124 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR1_IM25

Extended line 25

Definition at line 127 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_26 EXTI_IMR1_IM26

Extended line 26

Definition at line 130 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_27 EXTI_IMR1_IM27

Extended line 27

Definition at line 133 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR1_IM28

Extended line 28

Definition at line 136 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_29 EXTI_IMR1_IM29

Extended line 29

Definition at line 139 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR1_IM3

Extended line 3

Definition at line 92 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_30 EXTI_IMR1_IM30

Extended line 30

Definition at line 142 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_34 EXTI_IMR2_IM34

Extended line 34

Definition at line 156 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_36 EXTI_IMR2_IM36

Extended line 36

Definition at line 162 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_37 EXTI_IMR2_IM37

Extended line 37

Definition at line 165 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_38 EXTI_IMR2_IM38

Extended line 38

Definition at line 168 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_39 EXTI_IMR2_IM39

Extended line 39

Definition at line 171 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR1_IM4

Extended line 4

Definition at line 93 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_40 EXTI_IMR2_IM40

Extended line 40

Definition at line 174 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_41 EXTI_IMR2_IM41

Extended line 41

Definition at line 177 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR1_IM5

Extended line 5

Definition at line 94 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR1_IM6

Extended line 6

Definition at line 95 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR1_IM7

Extended line 7

Definition at line 96 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR1_IM8

Extended line 8

Definition at line 97 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR1_IM9

Extended line 9

Definition at line 98 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL (0xFFFFFFFFU)

All Extended line

Definition at line 185 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM

All Extended line not reserved

Definition at line 147 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM

All Extended line not reserved

Definition at line 182 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_LINE_NONE 0x00000000U

None Extended line

Definition at line 188 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 200 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 199 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 201 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 211 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 209 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 210 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 212 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 248 of file stm32g4xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 241 of file stm32g4xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 387 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
None

Definition at line 414 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
  • LL_EXTI_LINE_ALL_0_31
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 312 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
None

Definition at line 338 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
  • LL_EXTI_LINE_ALL_0_31
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 463 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
State of bit (1 or 0).

Definition at line 490 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
  • LL_EXTI_LINE_ALL_0_31
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 615 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
None

Definition at line 639 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 544 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
None

Definition at line 569 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 685 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35 (*)
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42(*)
  • LL_EXTI_LINE_ALL_32_63
Note:
(*): Available in some devices
Return values:
State of bit (1 or 0).

Definition at line 710 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 833 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 859 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 763 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 788 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 897 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
State of bit (1 or 0).

Definition at line 915 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1037 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 1061 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 968 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 993 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1099 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
State of bit (1 or 0).

Definition at line 1117 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR1 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1168 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 32 to 63.

Note:
If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR2 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 1191 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1359 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

__STATIC_INLINE void LL_EXTI_ClearFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ClearFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
None

Definition at line 1379 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1239 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_IsActiveFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
State of bit (1 or 0).

Definition at line 1259 of file stm32g4xx_ll_exti.h.

Referenced by HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31 (*)
Note:
(*): Available in some devices
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1299 of file stm32g4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ReadFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32 (*)
  • LL_EXTI_LINE_33 (*)
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Note:
(*): Available in some devices
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1319 of file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

uint32_t LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • 0x00: EXTI registers are de-initialized

Definition at line 79 of file stm32g4xx_ll_exti.c.

References LL_EXTI_WriteReg.

uint32_t LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • 0x00: EXTI registers are initialized
  • any other value : wrong configuration

Definition at line 121 of file stm32g4xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_LINE_32_63, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableFallingTrig_32_63(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_DisableRisingTrig_32_63(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableFallingTrig_32_63(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_EnableRisingTrig_32_63(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 268 of file stm32g4xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flag Defines

Defines
Get Flag Defines
FMAC Exported Constants

Flag defines which can be used with LL_FMAC_ReadReg function. More...

Defines

#define | LL_FMAC_SR_SAT FMAC_SR_SAT
#define | LL_FMAC_SR_UNFL FMAC_SR_UNFL
#define | LL_FMAC_SR_OVFL FMAC_SR_OVFL
#define | LL_FMAC_SR_X1FULL FMAC_SR_X1FULL
#define | LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY

Detailed Description

Flag defines which can be used with LL_FMAC_ReadReg function.

Define Documentation

#define LL_FMAC_SR_OVFL FMAC_SR_OVFL

Overflow Error Flag

Definition at line 54 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_SR_SAT FMAC_SR_SAT

Saturation Error Flag (this helps in debugging a filter)

Definition at line 51 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_SR_UNFL FMAC_SR_UNFL

Underflow Error Flag

Definition at line 53 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL

X1 Buffer Full Flag

Definition at line 55 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY

Y Buffer Empty Flag

Definition at line 56 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
FMAC Exported Constants

IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions. More...

Defines

#define | LL_FMAC_CR_SATIEN FMAC_CR_SATIEN
#define | LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN
#define | LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN
#define | LL_FMAC_CR_WIEN FMAC_CR_WIEN
#define | LL_FMAC_CR_RIEN FMAC_CR_RIEN

Detailed Description

IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions.

Define Documentation

#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN

Overflow Error Interrupt Enable

Definition at line 68 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_CR_RIEN FMAC_CR_RIEN

Read Interrupt Enable

Definition at line 70 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN

Saturation Error Interrupt Enable (this helps in debugging a filter)

Definition at line 65 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN

Underflow Error Interrupt Enable

Definition at line 67 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_CR_WIEN FMAC_CR_WIEN

Write Interrupt Enable

Definition at line 69 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC watermarks

Defines
FMAC watermarks
FMAC Exported Constants

Watermark defines that can be used for buffer full (input) or buffer empty (output) More...

Defines

#define | LL_FMAC_WM_0_THRESHOLD_1 0x00000000U
#define | LL_FMAC_WM_1_THRESHOLD_2 0x01000000U
#define | LL_FMAC_WM_2_THRESHOLD_4 0x02000000U
#define | LL_FMAC_WM_3_THRESHOLD_8 0x03000000U

Detailed Description

Watermark defines that can be used for buffer full (input) or buffer empty (output)

Define Documentation

#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U

Buffer full/empty flag set if there is less than 1 free/unread space.

Definition at line 79 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U

Buffer full/empty flag set if there are less than 2 free/unread spaces.

Definition at line 81 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U

Buffer full/empty flag set if there are less than 4 free/unread spaces.

Definition at line 83 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U

Buffer full/empty flag set if there are less than 8 free/empty spaces.

Definition at line 85 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC functions

Defines
FMAC functions
FMAC Exported Constants

Defines

#define | LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)
#define | LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)
#define | LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)
#define | LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)
#define | LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)

Define Documentation

#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)

Convolution (FIR filter)

Definition at line 97 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)

IIR filter (direct form 1)

Definition at line 98 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)

Load X1 buffer

Definition at line 94 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)

Load X2 buffer

Definition at line 95 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)

Load Y buffer

Definition at line 96 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC processing

Defines
FMAC processing
FMAC Exported Constants

Defines

#define | LL_FMAC_PROCESSING_STOP 0x00U
#define | LL_FMAC_PROCESSING_START 0x01U

Define Documentation

#define LL_FMAC_PROCESSING_START 0x01U

Start FMAC Processing

Definition at line 107 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_PROCESSING_STOP 0x00U

Stop FMAC Processing

Definition at line 106 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
FMAC Exported Macros

Defines

#define | LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in FMAC register.
#define | LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in FMAC register.

Define Documentation

#define LL_FMAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in FMAC register.

Parameters:
__INSTANCE__ | FMAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 141 of file stm32g4xx_ll_fmac.h.

#define LL_FMAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in FMAC register.

Parameters:
__INSTANCE__ | FMAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 133 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Configuration functions

Functions
FMAC Configuration functions
FMAC Exported Functions

Functions

__STATIC_INLINE void | LL_FMAC_SetX1FullWatermark (FMAC_TypeDef *FMACx, uint32_t Watermark)
Configure X1 full watermark.
__STATIC_INLINE uint32_t | LL_FMAC_GetX1FullWatermark (const FMAC_TypeDef *FMACx)
Return X1 full watermark.
__STATIC_INLINE void | LL_FMAC_SetX1BufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure X1 buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetX1BufferSize (const FMAC_TypeDef *FMACx)
Return X1 buffer size.
__STATIC_INLINE void | LL_FMAC_SetX1Base (FMAC_TypeDef *FMACx, uint8_t Base)
Configure X1 base.
__STATIC_INLINE uint8_t | LL_FMAC_GetX1Base (const FMAC_TypeDef *FMACx)
Return X1 base.
__STATIC_INLINE void | LL_FMAC_SetX2BufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure X2 buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetX2BufferSize (const FMAC_TypeDef *FMACx)
Return X2 buffer size.
__STATIC_INLINE void | LL_FMAC_SetX2Base (FMAC_TypeDef *FMACx, uint8_t Base)
Configure X2 base.
__STATIC_INLINE uint8_t | LL_FMAC_GetX2Base (const FMAC_TypeDef *FMACx)
Return X2 base.
__STATIC_INLINE void | LL_FMAC_SetYEmptyWatermark (FMAC_TypeDef *FMACx, uint32_t Watermark)
Configure Y empty watermark.
__STATIC_INLINE uint32_t | LL_FMAC_GetYEmptyWatermark (const FMAC_TypeDef *FMACx)
Return Y empty watermark.
__STATIC_INLINE void | LL_FMAC_SetYBufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure Y buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetYBufferSize (const FMAC_TypeDef *FMACx)
Return Y buffer size.
__STATIC_INLINE void | LL_FMAC_SetYBase (FMAC_TypeDef *FMACx, uint8_t Base)
Configure Y base.
__STATIC_INLINE uint8_t | LL_FMAC_GetYBase (const FMAC_TypeDef *FMACx)
Return Y base.
__STATIC_INLINE void | LL_FMAC_EnableStart (FMAC_TypeDef *FMACx)
Start FMAC processing.
__STATIC_INLINE void | LL_FMAC_DisableStart (FMAC_TypeDef *FMACx)
Stop FMAC processing.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledStart (const FMAC_TypeDef *FMACx)
Check the state of FMAC processing.
__STATIC_INLINE void | LL_FMAC_SetFunction (FMAC_TypeDef *FMACx, uint32_t Function)
Configure function.
__STATIC_INLINE uint32_t | LL_FMAC_GetFunction (const FMAC_TypeDef *FMACx)
Return function.
__STATIC_INLINE void | LL_FMAC_SetParamR (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter R.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamR (const FMAC_TypeDef *FMACx)
Return input parameter R.
__STATIC_INLINE void | LL_FMAC_SetParamQ (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter Q.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamQ (const FMAC_TypeDef *FMACx)
Return input parameter Q.
__STATIC_INLINE void | LL_FMAC_SetParamP (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter P.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamP (const FMAC_TypeDef *FMACx)
Return input parameter P.
__STATIC_INLINE void | LL_FMAC_EnableClipping (FMAC_TypeDef *FMACx)
Enable Clipping.
__STATIC_INLINE void | LL_FMAC_DisableClipping (FMAC_TypeDef *FMACx)
Disable Clipping.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledClipping (const FMAC_TypeDef *FMACx)
Check Clipping State.
__STATIC_INLINE void | LL_FMAC_ConfigX1 (FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
Configure memory for X1 buffer.
__STATIC_INLINE void | LL_FMAC_ConfigX2 (FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
Configure memory for X2 buffer.
__STATIC_INLINE void | LL_FMAC_ConfigY (FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
Configure memory for Y buffer.
__STATIC_INLINE void | LL_FMAC_ConfigFunc (FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP, uint8_t ParamQ, uint8_t ParamR)
Configure the FMAC processing.

Function Documentation

__STATIC_INLINE void LL_FMAC_ConfigFunc | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Start,
 |  | uint32_t | Function,
 |  | uint8_t | ParamP,
 |  | uint8_t | ParamQ,
 |  | uint8_t | ParamR
 | ) |  |

Configure the FMAC processing.

Reference Manual to LL API cross reference:
PARAM START LL_FMAC_ConfigFunc
PARAM FUNC LL_FMAC_ConfigFunc
PARAM P LL_FMAC_ConfigFunc
PARAM Q LL_FMAC_ConfigFunc
PARAM R LL_FMAC_ConfigFunc
Parameters:
FMACx | FMAC instance
Start This parameter can be one of the following values:
  • LL_FMAC_PROCESSING_STOP
  • LL_FMAC_PROCESSING_START
Function This parameter can be one of the following values:
  • LL_FMAC_FUNC_LOAD_X1
  • LL_FMAC_FUNC_LOAD_X2
  • LL_FMAC_FUNC_LOAD_Y
  • LL_FMAC_FUNC_CONVO_FIR
  • LL_FMAC_FUNC_IIR_DIRECT_FORM_1
ParamP | Parameter P (vector length, number of filter taps, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
ParamQ | Parameter Q (vector length, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
ParamR | Parameter R (gain, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1024 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_ConfigX1 | ( | FMAC_TypeDef * | FMACx,
 |  | uint32_t | Watermark,
 |  | uint8_t | Base,
 |  | uint8_t | BufferSize
 | ) |  |

Configure memory for X1 buffer.

Reference Manual to LL API cross reference:
X1BUFCFG FULL_WM LL_FMAC_ConfigX1
X1BUFCFG X1_BASE LL_FMAC_ConfigX1
X1BUFCFG X1_BUF_SIZE LL_FMAC_ConfigX1
Parameters:
FMACx | FMAC instance
Watermark This parameter can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8
Base | Base address of the input buffer (X1) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
BufferSize | Number of 16-bit words allocated to the input buffer (including the optional "headroom"). This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 950 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_ConfigX2 | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Base,
 |  | uint8_t | BufferSize
 | ) |  |

Configure memory for X2 buffer.

Reference Manual to LL API cross reference:
X2BUFCFG X2_BASE LL_FMAC_ConfigX2
X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
Parameters:
FMACx | FMAC instance
Base | Base address of the coefficient buffer (X2) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
BufferSize | Number of 16-bit words allocated to the coefficient buffer. This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 968 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_ConfigY | ( | FMAC_TypeDef * | FMACx,
 |  | uint32_t | Watermark,
 |  | uint8_t | Base,
 |  | uint8_t | BufferSize
 | ) |  |

Configure memory for Y buffer.

Reference Manual to LL API cross reference:
YBUFCFG EMPTY_WM LL_FMAC_ConfigY
YBUFCFG Y_BASE LL_FMAC_ConfigY
YBUFCFG Y_BUF_SIZE LL_FMAC_ConfigY
Parameters:
FMACx | FMAC instance
Watermark This parameter can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8
Base | Base address of the output buffer (Y) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
BufferSize | Number of 16-bit words allocated to the output buffer (including the optional "headroom"). This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 992 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableClipping ( FMAC_TypeDef * FMACx )

Disable Clipping.

Reference Manual to LL API cross reference:
CR CLIPEN LL_FMAC_DisableClipping
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 567 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableStart ( FMAC_TypeDef * FMACx )

Stop FMAC processing.

Reference Manual to LL API cross reference:
PARAM START LL_FMAC_DisableStart
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 390 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableClipping ( FMAC_TypeDef * FMACx )

Enable Clipping.

Reference Manual to LL API cross reference:
CR CLIPEN LL_FMAC_EnableClipping
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 556 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableStart ( FMAC_TypeDef * FMACx )

Start FMAC processing.

Reference Manual to LL API cross reference:
PARAM START LL_FMAC_EnableStart
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 379 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_GetFunction ( const FMAC_TypeDef * FMACx )

Return function.

Reference Manual to LL API cross reference:
PARAM FUNC LL_FMAC_GetFunction
Parameters:
FMACx FMAC instance
Return values:
uint32_t Returned value can be one of the following values:
  • LL_FMAC_FUNC_LOAD_X1
  • LL_FMAC_FUNC_LOAD_X2
  • LL_FMAC_FUNC_LOAD_Y
  • LL_FMAC_FUNC_CONVO_FIR
  • LL_FMAC_FUNC_IIR_DIRECT_FORM_1

Definition at line 434 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetParamP ( const FMAC_TypeDef * FMACx )

Return input parameter P.

Reference Manual to LL API cross reference:
PARAM P LL_FMAC_GetParamP
Parameters:
FMACx FMAC instance
Return values:
uint8_t Parameter P (vector length, number of filter taps, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 507 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetParamQ ( const FMAC_TypeDef * FMACx )

Return input parameter Q.

Reference Manual to LL API cross reference:
PARAM Q LL_FMAC_GetParamQ
Parameters:
FMACx FMAC instance
Return values:
uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 482 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetParamR ( const FMAC_TypeDef * FMACx )

Return input parameter R.

Reference Manual to LL API cross reference:
PARAM R LL_FMAC_GetParamR
Parameters:
FMACx FMAC instance
Return values:
uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 458 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetX1Base ( const FMAC_TypeDef * FMACx )

Return X1 base.

Reference Manual to LL API cross reference:
X1BUFCFG X1_BASE LL_FMAC_GetX1Base
Parameters:
FMACx FMAC instance
Return values:
uint8_t Base address of the input buffer (X1) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 237 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize ( const FMAC_TypeDef * FMACx )

Return X1 buffer size.

Reference Manual to LL API cross reference:
X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
Parameters:
FMACx FMAC instance
Return values:
uint8_t Number of 16-bit words allocated to the input buffer (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).

Definition at line 212 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark ( const FMAC_TypeDef * FMACx )

Return X1 full watermark.

Reference Manual to LL API cross reference:
X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
Parameters:
FMACx FMAC instance
Return values:
uint32_t Returned value can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8

Definition at line 187 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetX2Base ( const FMAC_TypeDef * FMACx )

Return X2 base.

Reference Manual to LL API cross reference:
X2BUFCFG X2_BASE LL_FMAC_GetX2Base
Parameters:
FMACx FMAC instance
Return values:
uint8_t Base address of the coefficient buffer (X2) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 287 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize ( const FMAC_TypeDef * FMACx )

Return X2 buffer size.

Reference Manual to LL API cross reference:
X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
Parameters:
FMACx FMAC instance
Return values:
uint8_t Number of 16-bit words allocated to the coefficient buffer (value between Min_Data=0x01 and Max_Data=0xFF).

Definition at line 262 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetYBase ( const FMAC_TypeDef * FMACx )

Return Y base.

Reference Manual to LL API cross reference:
YBUFCFG Y_BASE LL_FMAC_GetYBase
Parameters:
FMACx FMAC instance
Return values:
uint8_t Base address of the output buffer (Y) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).

Definition at line 368 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize ( const FMAC_TypeDef * FMACx )

Return Y buffer size.

Reference Manual to LL API cross reference:
YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
Parameters:
FMACx FMAC instance
Return values:
uint8_t Number of 16-bit words allocated to the output buffer (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).

Definition at line 343 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark ( const FMAC_TypeDef * FMACx )

Return Y empty watermark.

Reference Manual to LL API cross reference:
YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
Parameters:
FMACx FMAC instance
Return values:
uint32_t Returned value can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8

Definition at line 318 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping ( const FMAC_TypeDef * FMACx )

Check Clipping State.

Reference Manual to LL API cross reference:
CR CLIPEN LL_FMAC_IsEnabledClipping
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 578 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart ( const FMAC_TypeDef * FMACx )

Check the state of FMAC processing.

Reference Manual to LL API cross reference:
PARAM START LL_FMAC_IsEnabledStart
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 401 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetFunction | ( | FMAC_TypeDef * | FMACx,
 |  | uint32_t | Function
 | ) |  |

Configure function.

Reference Manual to LL API cross reference:
PARAM FUNC LL_FMAC_SetFunction
Parameters:
FMACx FMAC instance
Function This parameter can be one of the following values:
  • LL_FMAC_FUNC_LOAD_X1
  • LL_FMAC_FUNC_LOAD_X2
  • LL_FMAC_FUNC_LOAD_Y
  • LL_FMAC_FUNC_CONVO_FIR
  • LL_FMAC_FUNC_IIR_DIRECT_FORM_1
Return values:
None

Definition at line 418 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetParamP | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Param
 | ) |  |

Configure input parameter P.

Reference Manual to LL API cross reference:
PARAM P LL_FMAC_SetParamP
Parameters:
FMACx | FMAC instance
Param | Parameter P (vector length, number of filter taps, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 495 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetParamQ | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Param
 | ) |  |

Configure input parameter Q.

Reference Manual to LL API cross reference:
PARAM Q LL_FMAC_SetParamQ
Parameters:
FMACx | FMAC instance
Param | Parameter Q (vector length, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 471 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetParamR | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Param
 | ) |  |

Configure input parameter R.

Reference Manual to LL API cross reference:
PARAM R LL_FMAC_SetParamR
Parameters:
FMACx | FMAC instance
Param | Parameter R (gain, etc.). This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 447 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetX1Base | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Base
 | ) |  |

Configure X1 base.

Reference Manual to LL API cross reference:
X1BUFCFG X1_BASE LL_FMAC_SetX1Base
Parameters:
FMACx | FMAC instance
Base | Base address of the input buffer (X1) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 225 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetX1BufferSize | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | BufferSize
 | ) |  |

Configure X1 buffer size.

Reference Manual to LL API cross reference:
X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
Parameters:
FMACx | FMAC instance
BufferSize | Number of 16-bit words allocated to the input buffer (including the optional "headroom"). This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 200 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetX1FullWatermark | ( | FMAC_TypeDef * | FMACx,
 |  | uint32_t | Watermark
 | ) |  |

Configure X1 full watermark.

Reference Manual to LL API cross reference:
X1BUFCFG FULL_WM LL_FMAC_SetX1FullWatermark
Parameters:
FMACx FMAC instance
Watermark This parameter can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8
Return values:
None

Definition at line 172 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetX2Base | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Base
 | ) |  |

Configure X2 base.

Reference Manual to LL API cross reference:
X2BUFCFG X2_BASE LL_FMAC_SetX2Base
Parameters:
FMACx | FMAC instance
Base | Base address of the coefficient buffer (X2) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 275 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetX2BufferSize | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | BufferSize
 | ) |  |

Configure X2 buffer size.

Reference Manual to LL API cross reference:
X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
Parameters:
FMACx | FMAC instance
BufferSize | Number of 16-bit words allocated to the coefficient buffer. This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 250 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetYBase | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | Base
 | ) |  |

Configure Y base.

Reference Manual to LL API cross reference:
YBUFCFG Y_BASE LL_FMAC_SetYBase
Parameters:
FMACx | FMAC instance
Base | Base address of the output buffer (Y) within the internal memory. This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 356 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetYBufferSize | ( | FMAC_TypeDef * | FMACx,
 |  | uint8_t | BufferSize
 | ) |  |

Configure Y buffer size.

Reference Manual to LL API cross reference:
YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
Parameters:
FMACx | FMAC instance
BufferSize | Number of 16-bit words allocated to the output buffer (including the optional "headroom"). This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
Return values:
None

Definition at line 331 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_SetYEmptyWatermark | ( | FMAC_TypeDef * | FMACx,
 |  | uint32_t | Watermark
 | ) |  |

Configure Y empty watermark.

Reference Manual to LL API cross reference:
YBUFCFG EMPTY_WM LL_FMAC_SetYEmptyWatermark
Parameters:
FMACx FMAC instance
Watermark This parameter can be one of the following values:
  • LL_FMAC_WM_0_THRESHOLD_1
  • LL_FMAC_WM_1_THRESHOLD_2
  • LL_FMAC_WM_2_THRESHOLD_4
  • LL_FMAC_WM_3_THRESHOLD_8
Return values:
None

Definition at line 303 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Reset_Management

Functions
Reset_Management
FMAC Exported Functions

Functions

__STATIC_INLINE void | LL_FMAC_EnableReset (FMAC_TypeDef *FMACx)
Start the FMAC reset.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledReset (const FMAC_TypeDef *FMACx)
Check the state of the FMAC reset.

Function Documentation

__STATIC_INLINE void LL_FMAC_EnableReset ( FMAC_TypeDef * FMACx )

Start the FMAC reset.

Reference Manual to LL API cross reference:
CR RESET LL_FMAC_EnableReset
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 526 of file stm32g4xx_ll_fmac.h.

Referenced by LL_FMAC_Init().

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset ( const FMAC_TypeDef * FMACx )

Check the state of the FMAC reset.

Reference Manual to LL API cross reference:
CR RESET LL_FMAC_IsEnabledReset
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 537 of file stm32g4xx_ll_fmac.h.

Referenced by LL_FMAC_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA_Management

Functions
DMA_Management
FMAC Exported Functions

Functions

__STATIC_INLINE void | LL_FMAC_EnableDMAReq_WRITE (FMAC_TypeDef *FMACx)
Enable FMAC DMA write channel request.
__STATIC_INLINE void | LL_FMAC_DisableDMAReq_WRITE (FMAC_TypeDef *FMACx)
Disable FMAC DMA write channel request.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledDMAReq_WRITE (const FMAC_TypeDef *FMACx)
Check FMAC DMA write channel request state.
__STATIC_INLINE void | LL_FMAC_EnableDMAReq_READ (FMAC_TypeDef *FMACx)
Enable FMAC DMA read channel request.
__STATIC_INLINE void | LL_FMAC_DisableDMAReq_READ (FMAC_TypeDef *FMACx)
Disable FMAC DMA read channel request.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledDMAReq_READ (const FMAC_TypeDef *FMACx)
Check FMAC DMA read channel request state.

Function Documentation

__STATIC_INLINE void LL_FMAC_DisableDMAReq_READ ( FMAC_TypeDef * FMACx )

Disable FMAC DMA read channel request.

Reference Manual to LL API cross reference:
CR DMAREN LL_FMAC_DisableDMAReq_READ
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 641 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE ( FMAC_TypeDef * FMACx )

Disable FMAC DMA write channel request.

Reference Manual to LL API cross reference:
CR DMAWEN LL_FMAC_DisableDMAReq_WRITE
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 608 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableDMAReq_READ ( FMAC_TypeDef * FMACx )

Enable FMAC DMA read channel request.

Reference Manual to LL API cross reference:
CR DMAREN LL_FMAC_EnableDMAReq_READ
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 630 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE ( FMAC_TypeDef * FMACx )

Enable FMAC DMA write channel request.

Reference Manual to LL API cross reference:
CR DMAWEN LL_FMAC_EnableDMAReq_WRITE
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 597 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ ( const FMAC_TypeDef * FMACx )

Check FMAC DMA read channel request state.

Reference Manual to LL API cross reference:
CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 652 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE ( const FMAC_TypeDef * FMACx )

Check FMAC DMA write channel request state.

Reference Manual to LL API cross reference:
CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 619 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
FMAC Exported Functions

Functions

__STATIC_INLINE void | LL_FMAC_EnableIT_SAT (FMAC_TypeDef *FMACx)
Enable FMAC saturation error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_SAT (FMAC_TypeDef *FMACx)
Disable FMAC saturation error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_SAT (const FMAC_TypeDef *FMACx)
Check FMAC saturation error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_UNFL (FMAC_TypeDef *FMACx)
Enable FMAC underflow error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_UNFL (FMAC_TypeDef *FMACx)
Disable FMAC underflow error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_UNFL (const FMAC_TypeDef *FMACx)
Check FMAC underflow error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_OVFL (FMAC_TypeDef *FMACx)
Enable FMAC overflow error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_OVFL (FMAC_TypeDef *FMACx)
Disable FMAC overflow error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_OVFL (const FMAC_TypeDef *FMACx)
Check FMAC overflow error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_WR (FMAC_TypeDef *FMACx)
Enable FMAC write interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_WR (FMAC_TypeDef *FMACx)
Disable FMAC write interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_WR (const FMAC_TypeDef *FMACx)
Check FMAC write interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_RD (FMAC_TypeDef *FMACx)
Enable FMAC read interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_RD (FMAC_TypeDef *FMACx)
Disable FMAC read interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_RD (const FMAC_TypeDef *FMACx)
Check FMAC read interrupt state.

Function Documentation

__STATIC_INLINE void LL_FMAC_DisableIT_OVFL ( FMAC_TypeDef * FMACx )

Disable FMAC overflow error interrupt.

Reference Manual to LL API cross reference:
CR OVFLIEN LL_FMAC_DisableIT_OVFL
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 748 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableIT_RD ( FMAC_TypeDef * FMACx )

Disable FMAC read interrupt.

Reference Manual to LL API cross reference:
CR RIEN LL_FMAC_DisableIT_RD
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 814 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableIT_SAT ( FMAC_TypeDef * FMACx )

Disable FMAC saturation error interrupt.

Reference Manual to LL API cross reference:
CR SATIEN LL_FMAC_DisableIT_SAT
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 682 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableIT_UNFL ( FMAC_TypeDef * FMACx )

Disable FMAC underflow error interrupt.

Reference Manual to LL API cross reference:
CR UNFLIEN LL_FMAC_DisableIT_UNFL
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 715 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_DisableIT_WR ( FMAC_TypeDef * FMACx )

Disable FMAC write interrupt.

Reference Manual to LL API cross reference:
CR WIEN LL_FMAC_DisableIT_WR
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 781 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableIT_OVFL ( FMAC_TypeDef * FMACx )

Enable FMAC overflow error interrupt.

Reference Manual to LL API cross reference:
CR OVFLIEN LL_FMAC_EnableIT_OVFL
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 737 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableIT_RD ( FMAC_TypeDef * FMACx )

Enable FMAC read interrupt.

Reference Manual to LL API cross reference:
CR RIEN LL_FMAC_EnableIT_RD
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 803 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableIT_SAT ( FMAC_TypeDef * FMACx )

Enable FMAC saturation error interrupt.

Reference Manual to LL API cross reference:
CR SATIEN LL_FMAC_EnableIT_SAT
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 671 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableIT_UNFL ( FMAC_TypeDef * FMACx )

Enable FMAC underflow error interrupt.

Reference Manual to LL API cross reference:
CR UNFLIEN LL_FMAC_EnableIT_UNFL
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 704 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_EnableIT_WR ( FMAC_TypeDef * FMACx )

Enable FMAC write interrupt.

Reference Manual to LL API cross reference:
CR WIEN LL_FMAC_EnableIT_WR
Parameters:
FMACx FMAC instance
Return values:
None

Definition at line 770 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL ( const FMAC_TypeDef * FMACx )

Check FMAC overflow error interrupt state.

Reference Manual to LL API cross reference:
CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 759 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD ( const FMAC_TypeDef * FMACx )

Check FMAC read interrupt state.

Reference Manual to LL API cross reference:
CR RIEN LL_FMAC_IsEnabledIT_RD
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 825 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT ( const FMAC_TypeDef * FMACx )

Check FMAC saturation error interrupt state.

Reference Manual to LL API cross reference:
CR SATIEN LL_FMAC_IsEnabledIT_SAT
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 693 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL ( const FMAC_TypeDef * FMACx )

Check FMAC underflow error interrupt state.

Reference Manual to LL API cross reference:
CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 726 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR ( const FMAC_TypeDef * FMACx )

Check FMAC write interrupt state.

Reference Manual to LL API cross reference:
CR WIEN LL_FMAC_IsEnabledIT_WR
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 792 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
FMAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_SAT (const FMAC_TypeDef *FMACx)
Check FMAC saturation error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_UNFL (const FMAC_TypeDef *FMACx)
Check FMAC underflow error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_OVFL (const FMAC_TypeDef *FMACx)
Check FMAC overflow error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_X1FULL (const FMAC_TypeDef *FMACx)
Check FMAC X1 buffer full flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_YEMPTY (const FMAC_TypeDef *FMACx)
Check FMAC Y buffer empty flag state.

Function Documentation

__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL ( const FMAC_TypeDef * FMACx )

Check FMAC overflow error flag state.

Reference Manual to LL API cross reference:
SR OVFL LL_FMAC_IsActiveFlag_OVFL
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 866 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT ( const FMAC_TypeDef * FMACx )

Check FMAC saturation error flag state.

Reference Manual to LL API cross reference:
SR SAT LL_FMAC_IsActiveFlag_SAT
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 844 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL ( const FMAC_TypeDef * FMACx )

Check FMAC underflow error flag state.

Reference Manual to LL API cross reference:
SR UNFL LL_FMAC_IsActiveFlag_UNFL
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 855 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL ( const FMAC_TypeDef * FMACx )

Check FMAC X1 buffer full flag state.

Reference Manual to LL API cross reference:
SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 877 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY ( const FMAC_TypeDef * FMACx )

Check FMAC Y buffer empty flag state.

Reference Manual to LL API cross reference:
SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
Parameters:
FMACx FMAC instance
Return values:
uint32_t State of bit (1 or 0).

Definition at line 888 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
FMAC Exported Functions

Functions

__STATIC_INLINE void | LL_FMAC_WriteData (FMAC_TypeDef *FMACx, uint16_t InData)
Write 16-bit input data for the FMAC processing.
__STATIC_INLINE uint16_t | LL_FMAC_ReadData (const FMAC_TypeDef *FMACx)
Return 16-bit output data of FMAC processing.

Function Documentation

__STATIC_INLINE uint16_t LL_FMAC_ReadData ( const FMAC_TypeDef * FMACx )

Return 16-bit output data of FMAC processing.

Reference Manual to LL API cross reference:
RDATA RDATA LL_FMAC_ReadData
Parameters:
FMACx FMAC instance
Return values:
uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).

Definition at line 920 of file stm32g4xx_ll_fmac.h.

__STATIC_INLINE void LL_FMAC_WriteData | ( | FMAC_TypeDef * | FMACx,
 |  | uint16_t | InData
 | ) |  |

Write 16-bit input data for the FMAC processing.

Reference Manual to LL API cross reference:
WDATA WDATA LL_FMAC_WriteData
Parameters:
FMACx | FMAC instance
InData | 16-bit value to be provided as input data for FMAC processing. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
Return values:
None

Definition at line 909 of file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FMAC Exported Functions

Functions

ErrorStatus | LL_FMAC_Init (FMAC_TypeDef *FMACx)
Initialize FMAC peripheral registers to their default reset values.
ErrorStatus | LL_FMAC_DeInit (const FMAC_TypeDef *FMACx)
De-Initialize FMAC peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_FMAC_DeInit ( const FMAC_TypeDef * FMACx )

De-Initialize FMAC peripheral registers to their default reset values.

Parameters:
FMACx FMAC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: FMAC registers are de-initialized
  • ERROR: FMAC registers are not de-initialized

Definition at line 93 of file stm32g4xx_ll_fmac.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_FMAC, and LL_AHB1_GRP1_ReleaseReset().

ErrorStatus LL_FMAC_Init ( FMAC_TypeDef * FMACx )

Initialize FMAC peripheral registers to their default reset values.

Parameters:
FMACx FMAC Instance
Return values:
ErrorStatus enumeration value:
  • SUCCESS: FMAC registers are initialized
  • ERROR: FMAC registers are not initialized

Definition at line 61 of file stm32g4xx_ll_fmac.c.

References assert_param, LL_FMAC_EnableReset(), and LL_FMAC_IsEnabledReset().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15. More...

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : LL_GPIO_Init.

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_15 ))

Definition at line 70 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 53 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 58 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 51 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 66 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 61 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32g4xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 71 of file stm32g4xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 96 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 76 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 86 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 73 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 91 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 81 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_gpio.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS0

Select pin 0

Definition at line 115 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS1

Select pin 1

Definition at line 116 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS10

Select pin 10

Definition at line 125 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS11

Select pin 11

Definition at line 126 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS12

Select pin 12

Definition at line 127 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS13

Select pin 13

Definition at line 128 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS14

Select pin 14

Definition at line 129 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS15

Select pin 15

Definition at line 130 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS2

Select pin 2

Definition at line 117 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS3

Select pin 3

Definition at line 118 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS4

Select pin 4

Definition at line 119 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS5

Select pin 5

Definition at line 120 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS6

Select pin 6

Definition at line 121 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS7

Select pin 7

Definition at line 122 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS8

Select pin 8

Definition at line 123 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_PIN_9 GPIO_BSRR_BS9

Select pin 9

Definition at line 124 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
                                           GPIO_BSRR_BS15)

Select all pins

Definition at line 131 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1

Select alternate function mode

Definition at line 146 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Select analog mode

Definition at line 147 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT (0x00000000U)

Select input mode

Definition at line 144 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0

Select output mode

Definition at line 145 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Select open-drain as output type

Definition at line 156 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)

Select push-pull as output type

Definition at line 155 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1

Select I/O fast output speed

Definition at line 166 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U)

Select I/O low output speed

Definition at line 164 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0

Select I/O medium output speed

Definition at line 165 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Select I/O high output speed

Definition at line 167 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Select I/O pull down

Definition at line 181 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_PULL_NO (0x00000000U)

Select I/O no pull

Definition at line 179 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0

Select I/O pull up

Definition at line 180 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)

Define Documentation

#define LL_GPIO_AF_0 (0x0000000U)

Select alternate function 0

Definition at line 189 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 (0x0000001U)

Select alternate function 1

Definition at line 190 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_10 (0x000000AU)

Select alternate function 10

Definition at line 199 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_11 (0x000000BU)

Select alternate function 11

Definition at line 200 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_12 (0x000000CU)

Select alternate function 12

Definition at line 201 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_13 (0x000000DU)

Select alternate function 13

Definition at line 202 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_14 (0x000000EU)

Select alternate function 14

Definition at line 203 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_15 (0x000000FU)

Select alternate function 15

Definition at line 204 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_2 (0x0000002U)

Select alternate function 2

Definition at line 191 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_3 (0x0000003U)

Select alternate function 3

Definition at line 192 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_4 (0x0000004U)

Select alternate function 4

Definition at line 193 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_5 (0x0000005U)

Select alternate function 5

Definition at line 194 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_6 (0x0000006U)

Select alternate function 6

Definition at line 195 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_7 (0x0000007U)

Select alternate function 7

Definition at line 196 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_8 (0x0000008U)

Select alternate function 8

Definition at line 197 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_AF_9 (0x0000009U)

Select alternate function 9

Definition at line 198 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Constants

Modules | Defines
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function

Defines

#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Define Documentation

#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH

Definition at line 173 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 174 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW

Definition at line 171 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM

Definition at line 172 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 237 of file stm32g4xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 229 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 605 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 683 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 319 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 388 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 528 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 462 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 765 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 754 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 719 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 568 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 645 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 285 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 354 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 496 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH
Return values:
None

Definition at line 425 of file stm32g4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 813 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 865 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 784 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 836 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 923 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 894 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 952 of file stm32g4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 825 of file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 108 of file stm32g4xx_ll_gpio.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_GPIOA, LL_AHB2_GRP1_PERIPH_GPIOB, LL_AHB2_GRP1_PERIPH_GPIOC, LL_AHB2_GRP1_PERIPH_GPIOD, LL_AHB2_GRP1_PERIPH_GPIOE, LL_AHB2_GRP1_PERIPH_GPIOF, LL_AHB2_GRP1_PERIPH_GPIOG, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx | GPIO Port
GPIO_InitStruct | pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 168 of file stm32g4xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_PIN_8, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 240 of file stm32g4xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 52 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 55 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 57 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 62 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 47 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 59 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32g4xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 66 of file stm32g4xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection.

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 81 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 87 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 93 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length.

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 106 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode.

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 68 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS().

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 74 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation.

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 99 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_i2c.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 126 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 134 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 130 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 129 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 127 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 131 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 132 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 128 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 133 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 146 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 156 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 152 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 151 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 157 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 147 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 153 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 154 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 145 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 148 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 149 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 150 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 155 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 143 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 144 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 168 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 172 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 169 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 167 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 170 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 171 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 166 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 180 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U

SMBus Device default mode (Default address not acknowledge)

Definition at line 182 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 184 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 181 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 193 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

Definition at line 192 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 202 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

Definition at line 201 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 211 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

Definition at line 210 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 220 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 221 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 222 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 223 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 224 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 225 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 226 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 219 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

Definition at line 235 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 236 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 245 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

Definition at line 244 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 254 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

Definition at line 253 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 263 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 262 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 269 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 273 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 267 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 271 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 275 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 265 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don't Generate Stop and Start condition.

Definition at line 284 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ
Value:
(uint32_t)(0x80000000U | I2C_CR2_START | \
                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 296 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 10Bit address.

Definition at line 299 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 292 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 7Bit address.

Definition at line 294 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 288 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Start for write request.

Definition at line 290 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Generate Stop condition (Size should be set to 0).

Definition at line 286 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 310 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

Definition at line 308 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 321 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 319 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

TimeoutA is used to detect SCL low level timeout.

Definition at line 330 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 332 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT
Value:
(uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
                                                       I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 344 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 341 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 342 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 379 of file stm32g4xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 371 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __SETUP_TIME__,
 |  | __HOLD_TIME__,
 |  | __SCLH_PERIOD__,
 |  | __SCLL_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF.
__SETUP_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
__HOLD_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
__SCLH_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
__SCLL_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 400 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (const I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (const I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (const I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (const I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (const I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (const I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (const I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (const I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (const I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (const I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (const I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (const I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (const I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (const I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (const I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (const I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (const I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (const I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (const I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (const I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (const I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (const I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (const I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (const I2C_TypeDef *I2Cx)
Get the SMBus Extended Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 475 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Return values:
None

Definition at line 1123 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 443 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 527 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 656 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 593 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 560 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 764 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 841 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 897 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 689 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1050 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1089 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1249 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 727 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | const I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 619 of file stm32g4xx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 429 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 515 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 644 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 582 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 549 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 752 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 830 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 886 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 678 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1032 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1076 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1231 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 714 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( const I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 955 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( const I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 944 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( const I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 966 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( const I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 977 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( const I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 503 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( const I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 803 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( const I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 1014 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( const I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1153 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( const I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1185 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( const I2C_TypeDef * I2Cx )

Get the SMBus Extended Cumulative Clock TimeoutB setting.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1213 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( const I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 933 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( const I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 454 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( const I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 538 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( const I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 667 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( const I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 604 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( const I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 571 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( const I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 775 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( const I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 852 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( const I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 908 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( const I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 700 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( const I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1063 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( const I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1102 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | const I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1267 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( const I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 740 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 492 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 790 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 996 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 819 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between Min_Data=0 and Max_Data=0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 875 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1140 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1170 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1200 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 922 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (const I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (const I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (const I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (const I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (const I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (const I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (const I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1364 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1520 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1397 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1331 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1430 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1469 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1298 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1353 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1500 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1386 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1320 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1419 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1455 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1287 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( const I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1375 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( const I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1531 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( const I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1408 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( const I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1342 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( const I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1441 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( const I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1480 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( const I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1309 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (const I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (const I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (const I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (const I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (const I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (const I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (const I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (const I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (const I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (const I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (const I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (const I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1752 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1808 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1797 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1763 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1819 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1774 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1786 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1858 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1832 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1845 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( const I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1591 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( const I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1669 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( const I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( const I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1741 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( const I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1604 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( const I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1682 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( const I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1578 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( const I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1617 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( const I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1630 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( const I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1643 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( const I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1552 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( const I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1565 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( const I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1728 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( const I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1697 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( const I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1712 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (const I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (const I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (const I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (const I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (const I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (const I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (const I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (const I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (const I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (const I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (const I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1977 of file stm32g4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2027 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1891 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1926 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2015 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1879 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1914 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2188 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1990 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2001 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( const I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2171 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( const I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2090 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( const I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2214 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( const I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2160 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( const I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2066 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( const I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1961 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between Min_Data=0 and Max_Data=255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2133 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( const I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2038 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( const I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1902 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( const I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1937 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( const I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte internal comparison is requested or not.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2201 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( const I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2225 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2079 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2053 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1950 of file stm32g4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2237 of file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

ErrorStatus | LL_I2C_DeInit (const I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_I2C_DeInit ( const I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 86 of file stm32g4xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, LL_APB1_GRP1_PERIPH_I2C3, LL_APB1_GRP1_ReleaseReset(), LL_APB1_GRP2_ForceReset(), and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | const LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 144 of file stm32g4xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 212 of file stm32g4xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 48 of file stm32g4xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 47 of file stm32g4xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 50 of file stm32g4xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 49 of file stm32g4xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 67 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 68 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 69 of file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 82 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 79 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 83 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 80 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 77 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 81 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 78 of file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 116 of file stm32g4xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 108 of file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (const IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (const IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (const IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 174 of file stm32g4xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 141 of file stm32g4xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 163 of file stm32g4xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( const IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 211 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( const IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 234 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( const IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 257 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 152 of file stm32g4xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 193 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 223 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 246 of file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (const IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (const IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (const IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( const IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 276 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( const IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 287 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( const IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 298 of file stm32g4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 311 of file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Define Documentation

#define IS_LL_LPTIM_CLOCK_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))

Definition at line 52 of file stm32g4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_CLOCK_SOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
                                             || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))

Definition at line 49 of file stm32g4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_OUTPUT_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
                                                || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))

Definition at line 64 of file stm32g4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_WAVEFORM ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
                                         || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))

Definition at line 61 of file stm32g4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPTIM_InitTypeDef Struct Reference
LPTIM Exported Init structure

LPTIM Init structure definition. More...

#include <stm32g4xx_ll_lptim.h>

Data Fields

uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | Waveform
uint32_t | Polarity

Detailed Description

LPTIM Init structure definition.

Definition at line 64 of file stm32g4xx_ll_lptim.h.

Field Documentation

uint32_t LL_LPTIM_InitTypeDef::ClockSource

Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of Clock Source.

This feature can be modified afterwards using unitary function LL_LPTIM_SetClockSource().

Definition at line 66 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Polarity

Specifies waveform polarity. This parameter can be a value of Output Polarity.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 84 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Prescaler

Specifies the prescaler division ratio. This parameter can be a value of Prescaler Value.

This feature can be modified afterwards using using unitary function LL_LPTIM_SetPrescaler().

Definition at line 72 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Waveform

Specifies the waveform shape. This parameter can be a value of Output Waveform Type.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 78 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_lptim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPTIM Exported Constants

Flags defines which can be used with LL_LPTIM_ReadReg function. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Detailed Description

Flags defines which can be used with LL_LPTIM_ReadReg function.

Define Documentation

#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

Definition at line 107 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

Definition at line 109 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM

Compare match

Definition at line 105 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK

Compare register update OK

Definition at line 106 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

Definition at line 111 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

Definition at line 108 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

Definition at line 110 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
LPTIM Exported Constants

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions. More...

Defines

#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Detailed Description

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Define Documentation

#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE

Autoreload match

Definition at line 122 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE

Autoreload register update OK

Definition at line 124 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE

Compare match

Definition at line 120 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE

Compare register update OK

Definition at line 121 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Counter direction change up to down

Definition at line 126 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE

External trigger edge event

Definition at line 123 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE

Counter direction change down to up

Definition at line 125 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operating Mode

Defines
Operating Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

Define Documentation

#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode

Definition at line 134 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Tilmer starts in single mode

Definition at line 135 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Update Mode

Defines
Update Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

preload is enabled: registers are updated at the end of the current LPTIM period

Definition at line 144 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U

Preload is disabled: registers are updated after each APB bus write access

Definition at line 143 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Counter Mode

Defines
Counter Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1

Definition at line 153 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U

The counter is incremented following each internal clock pulse

Definition at line 152 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Waveform Type

Defines
Output Waveform Type
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

Define Documentation

#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U

LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE

Definition at line 161 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a Set Once waveform

Definition at line 162 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Polarity

Defines
Output Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

Define Documentation

#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 171 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 170 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Prescaler Value

Defines
Prescaler Value
LPTIM Exported Constants

Defines

#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LL_LPTIM_PRESCALER_DIV1 0x00000000U

Prescaler division factor is set to 1

Definition at line 179 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128

Definition at line 186 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16

Definition at line 183 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2

Definition at line 180 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32

Definition at line 184 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4

Definition at line 181 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64

Definition at line 185 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8

Definition at line 182 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Source

Defines
Trigger Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3
#define | LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0)

Define Documentation

#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

Definition at line 200 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to COMP2 output

Definition at line 201 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3

External input trigger is connected to COMP3 output

Definition at line 202 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to COMP4 output

Definition at line 203 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U

External input trigger is connected to TIMx_ETR input

Definition at line 194 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

Definition at line 195 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

Definition at line 196 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

Definition at line 197 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

Definition at line 198 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 3

Definition at line 199 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Filter

Defines
Trigger Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Define Documentation

#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger

Definition at line 221 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger

Definition at line 222 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Definition at line 223 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U

Any trigger active level change is considered as a valid trigger

Definition at line 220 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Polarity

Defines
Trigger Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

Definition at line 232 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

Definition at line 231 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Definition at line 233 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Source

Defines
Clock Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

Define Documentation

#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Definition at line 242 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

Definition at line 241 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Filter

Defines
Clock Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

Define Documentation

#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

Definition at line 251 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Definition at line 252 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Definition at line 253 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U

Any external clock signal level change is considered as a valid transition

Definition at line 250 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 262 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 261 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 263 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 272 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 271 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 273 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input1 Source

Defines
Input1 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
#define | LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)

Define Documentation

#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0

Definition at line 282 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)

Definition at line 283 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U

Definition at line 281 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input2 Source

Defines
Input2 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
#define | LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)

Define Documentation

#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0

Definition at line 298 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)

Definition at line 299 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U

Definition at line 297 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPTIM Exported Macros

Defines

#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Define Documentation

#define LL_LPTIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 335 of file stm32g4xx_ll_lptim.h.

#define LL_LPTIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 327 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
LPTIM Exported Functions

Legacy definitions for compatibility purpose. More...

Functions

ErrorStatus | LL_LPTIM_DeInit (const LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Detailed Description

Legacy definitions for compatibility purpose.

Function Documentation

ErrorStatus LL_LPTIM_DeInit ( const LPTIM_TypeDef * LPTIMx )

Set LPTIMx registers to their reset values.

Parameters:
LPTIMx LP Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx registers are de-initialized
  • ERROR: invalid LPTIMx instance

Definition at line 95 of file stm32g4xx_ll_lptim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPTIM1, and LL_APB1_GRP1_ReleaseReset().

Referenced by LL_LPTIM_Disable().

void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 183 of file stm32g4xx_ll_lptim.c.

References assert_param, LL_LPTIM_ClearFlag_ARROK(), LL_LPTIM_ClearFlag_CMPOK(), LL_LPTIM_DeInit(), LL_LPTIM_IsActiveFlag_ARROK(), LL_LPTIM_IsActiveFlag_CMPOK(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSystemClocksFreq(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_SetLPTIMClockSource(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

ErrorStatus LL_LPTIM_Init | ( | LPTIM_TypeDef * | LPTIMx,
 |  | const LL_LPTIM_InitTypeDef * | LPTIM_InitStruct
 | ) |  |

Configure the LPTIMx peripheral according to the specified parameters.

Note:
LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
LPTIMx can be disabled using unitary function LL_LPTIM_Disable().
Parameters:
LPTIMx | LP Timer Instance
LPTIM_InitStruct | pointer to a LL_LPTIM_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx instance has been initialized
  • ERROR: LPTIMx instance hasn't been initialized

Definition at line 140 of file stm32g4xx_ll_lptim.c.

References assert_param, LL_LPTIM_InitTypeDef::ClockSource, IS_LL_LPTIM_CLOCK_PRESCALER, IS_LL_LPTIM_CLOCK_SOURCE, IS_LL_LPTIM_OUTPUT_POLARITY, IS_LL_LPTIM_WAVEFORM, LL_LPTIM_IsEnabled(), LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

void LL_LPTIM_StructInit ( LL_LPTIM_InitTypeDef * LPTIM_InitStruct )

Set each fields of the LPTIM_InitStruct structure to its default value.

Parameters:
LPTIM_InitStruct pointer to a LL_LPTIM_InitTypeDef structure
Return values:
None

Definition at line 121 of file stm32g4xx_ll_lptim.c.

References LL_LPTIM_InitTypeDef::ClockSource, LL_LPTIM_CLK_SOURCE_INTERNAL, LL_LPTIM_OUTPUT_POLARITY_REGULAR, LL_LPTIM_OUTPUT_WAVEFORM_PWM, LL_LPTIM_PRESCALER_DIV1, LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Configuration

Functions
LPTIM Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (const LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (const LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (const LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (const LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (const LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (const LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (const LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (const LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigOutput | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform,
 |  | uint32_t | Polarity
 | ) |  |

Configure the LPTIM instance output (LPTIMx_OUT)

Note:
This function must be called when the LPTIM instance is disabled.
Regarding the LPTIM output polarity the change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_ConfigOutput
CFGR WAVPOL LL_LPTIM_ConfigOutput
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 616 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Disable reset after read.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_DisableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 441 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Enable ( LPTIM_TypeDef * LPTIMx )

Enable the LPTIM instance.

Note:
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM instance is actually enabled.
Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Enable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 388 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Enable reset after read.

Note:
After calling this function any read access to LPTIM_CNT register will asynchronously reset the LPTIM_CNT register content.
Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_EnableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 430 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload ( const LPTIM_TypeDef * LPTIMx )

Get actual auto reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_GetAutoReload
Parameters:
LPTIMx Low-Power Timer instance
Return values:
AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF

Definition at line 524 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCompare ( const LPTIM_TypeDef * LPTIMx )

Get actual compare value.

Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_GetCompare
Parameters:
LPTIMx Low-Power Timer instance
Return values:
CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 551 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounter ( const LPTIM_TypeDef * LPTIMx )

Get actual counter value.

Note:
When the LPTIM instance is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Reference Manual to LL API cross reference:
CNT CNT LL_LPTIM_GetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Counter value

Definition at line 566 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode ( const LPTIM_TypeDef * LPTIMx )

Get the counter mode.

Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_GetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL

Definition at line 594 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_GetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE

Definition at line 670 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler ( const LPTIM_TypeDef * LPTIMx )

Get actual prescaler division ratio.

Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_GetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128

Definition at line 714 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode ( const LPTIM_TypeDef * LPTIMx )

Get the LPTIM registers update mode.

Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_GetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

Definition at line 495 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform ( const LPTIM_TypeDef * LPTIMx )

Get actual waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_GetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

Definition at line 643 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM instance is enabled.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_IsEnabled
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 399 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init().

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead ( const LPTIM_TypeDef * LPTIMx )

Indicate whether the reset after read feature is enabled.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 452 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ResetCounter ( LPTIM_TypeDef * LPTIMx )

Reset of the LPTIM_CNT counter register (synchronous).

Note:
Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTIM core clock cycles (LPTIM core clock may be different from APB clock).
COUNTRST is automatically cleared by hardware
Reference Manual to LL API cross reference:
CR COUNTRST LL_LPTIM_ResetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 467 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetAutoReload | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto reload value.

Note:
The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
After a write to the LPTIMx_ARR register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the ARROK flag is set, will lead to unpredictable results.
autoreload value be strictly greater than the compare value.
Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_SetAutoReload
Parameters:
LPTIMx | Low-Power Timer instance
AutoReload | Value between Min_Data=0x0001 and Max_Data=0xFFFF
Return values:
None

Definition at line 513 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCompare | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set the compare value.

Note:
After a write to the LPTIMx_CMP register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the CMPOK flag is set, will lead to unpredictable results.
Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_SetCompare
Parameters:
LPTIMx | Low-Power Timer instance
CompareValue | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 540 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCounterMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the counter mode (selection of the LPTIM counter clock source).

Note:
The counter mode can be set only when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_SetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
CounterMode This parameter can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL
Return values:
None

Definition at line 581 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput1Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 1 source (default GPIO).

Reference Manual to LL API cross reference:
OR IN1 LL_LPTIM_SetInput1Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT1_SRC_GPIO
  • LL_LPTIM_INPUT1_SRC_COMP1
  • LL_LPTIM_INPUT1_SRC_COMP3
  • LL_LPTIM_INPUT1_SRC_COMP5 (*)
  • LL_LPTIM_INPUT1_SRC_COMP7 (*) (*) Value not defined for all devices
Return values:
None

Definition at line 732 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput2Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 2 source (default GPIO).

Reference Manual to LL API cross reference:
OR IN2 LL_LPTIM_SetInput2Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT2_SRC_GPIO
  • LL_LPTIM_INPUT2_SRC_COMP2
  • LL_LPTIM_INPUT2_SRC_COMP4
  • LL_LPTIM_INPUT2_SRC_COMP6 (*) (*) Value not defined for all devices
Return values:
None

Definition at line 749 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPolarity | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Polarity
 | ) |  |

Set output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_SetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 657 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPrescaler | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set actual prescaler division ratio.

Note:
This function must be called when the LPTIM instance is disabled.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled.
Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_SetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Prescaler This parameter can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128
Return values:
None

Definition at line 695 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetUpdateMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | UpdateMode
 | ) |  |

Set the LPTIM registers update mode (enable/disable register preload)

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_SetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
UpdateMode This parameter can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
Return values:
None

Definition at line 482 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetWaveform | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform
 | ) |  |

Set waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_SetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Return values:
None

Definition at line 630 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_StartCounter | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | OperatingMode
 | ) |  |

Starts the LPTIM counter in the desired mode.

Note:
LPTIM instance must be enabled before starting the counter.
It is possible to change on the fly from One Shot mode to Continuous mode.
Reference Manual to LL API cross reference:
CR CNTSTRT LL_LPTIM_StartCounter
CR SNGSTRT LL_LPTIM_StartCounter
Parameters:
LPTIMx Low-Power Timer instance
OperatingMode This parameter can be one of the following values:
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS
  • LL_LPTIM_OPERATING_MODE_ONESHOT
Return values:
None

Definition at line 417 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Configuration

Functions
Trigger Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (const LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigTrigger | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Source,
 |  | uint32_t | Filter,
 |  | uint32_t | Polarity
 | ) |  |

Configure the external trigger used as a trigger event for the LPTIM.

Note:
This function must be called when the LPTIM instance is disabled.
An internal clock source must be present when a digital filter is required for the trigger.
Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_ConfigTrigger
CFGR TRGFLT LL_LPTIM_ConfigTrigger
CFGR TRIGEN LL_LPTIM_ConfigTrigger
Parameters:
LPTIMx Low-Power Timer instance
Source This parameter can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_COMP3
  • LL_LPTIM_TRIG_SOURCE_COMP4
  • LL_LPTIM_TRIG_SOURCE_COMP5 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP6 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP7 (*)
(*) Value not defined in all devices.
Filter This parameter can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8
Polarity This parameter can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Return values:
None

Definition at line 853 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableTimeout ( LPTIM_TypeDef * LPTIMx )

Disable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
A trigger event arriving when the timer is already started will be ignored.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_DisableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 788 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableTimeout ( LPTIM_TypeDef * LPTIMx )

Enable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_EnableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 774 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger filter.

Reference Manual to LL API cross reference:
CFGR TRGFLT LL_LPTIM_GetTriggerFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8

Definition at line 894 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger polarity.

Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING

Definition at line 908 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger source.

Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_GetTriggerSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_COMP3
  • LL_LPTIM_TRIG_SOURCE_COMP4
  • LL_LPTIM_TRIG_SOURCE_COMP5 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP6 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP7 (*)
(*) Value not defined in all devices.

Definition at line 879 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout ( const LPTIM_TypeDef * LPTIMx )

Indicate whether the timeout function is enabled.

Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 799 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_TrigSw ( LPTIM_TypeDef * LPTIMx )

Start the LPTIM counter.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_TrigSw
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 811 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Configuration

Functions
Clock Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (const LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (const LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigClock | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockFilter,
 |  | uint32_t | ClockPolarity
 | ) |  |

Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

Note:
This function must be called when the LPTIM instance is disabled.
When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.
An internal clock source must be present when a digital filter is required for external clock.
Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_ConfigClock
CFGR CKPOL LL_LPTIM_ConfigClock
Parameters:
LPTIMx Low-Power Timer instance
ClockFilter This parameter can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8
ClockPolarity This parameter can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING
Return values:
None

Definition at line 972 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter ( const LPTIM_TypeDef * LPTIMx )

Get actual clock digital filter.

Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_GetClockFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8

Definition at line 1001 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual clock polarity.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetClockPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING

Definition at line 986 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource ( const LPTIM_TypeDef * LPTIMx )

Get actual LPTIM instance clock source.

Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_GetClockSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL

Definition at line 944 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetClockSource | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the source of the clock used by the LPTIM instance.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_SetClockSource
Parameters:
LPTIMx Low-Power Timer instance
ClockSource This parameter can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL
Return values:
None

Definition at line 931 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Encoder Mode

Functions
Encoder Mode
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (const LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Disable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_DisableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1067 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Enable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
In this mode the LPTIM instance must be clocked by an internal clock source. Also, the prescaler division ratio must be equal to 1.
LPTIM instance must be configured in continuous mode prior enabling the encoder mode.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_EnableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1055 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode ( const LPTIM_TypeDef * LPTIMx )

Get actual encoder mode.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING

Definition at line 1039 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM operates in encoder mode.

Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_IsEnabledEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1078 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetEncoderMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Configure the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_SetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING
Return values:
None

Definition at line 1025 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload match flag (ARRMCF)

Reference Manual to LL API cross reference:
ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1120 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload register update interrupt flag (ARROKCF).

Reference Manual to LL API cross reference:
ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1187 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM ( LPTIM_TypeDef * LPTIMx )

Clear the compare match flag (CMPMCF)

Reference Manual to LL API cross reference:
ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1098 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Clear the compare register update interrupt flag (CMPOKCF).

Reference Manual to LL API cross reference:
ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1164 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to down interrupt flag (DOWNCF).

Reference Manual to LL API cross reference:
ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1233 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Clear the external trigger valid edge flag(EXTTRIGCF).

Reference Manual to LL API cross reference:
ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1142 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_UP ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to up interrupt flag (UPCF).

Reference Manual to LL API cross reference:
ICR UPCF LL_LPTIM_ClearFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1210 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a autoreload match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1131 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK ( const LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1199 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a compare match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1109 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK ( const LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1176 of file stm32g4xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN ( const LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1245 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a valid edge on the selected external trigger input has occurred.

Reference Manual to LL API cross reference:
ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1153 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP ( const LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR UP LL_LPTIM_IsActiveFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1222 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Disable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_DisableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1308 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Disable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_DisableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1407 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Disable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_DisableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1275 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Disable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1374 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Disable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_DisableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1473 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Disable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1341 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_UP ( LPTIM_TypeDef * LPTIMx )

Disable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_DisableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1440 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Enable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_EnableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1297 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Enable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_EnableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1396 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Enable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_EnableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1264 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Enable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1363 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Enable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_EnableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1462 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Enable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1330 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_UP ( LPTIM_TypeDef * LPTIMx )

Enable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_EnableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1429 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1319 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1418 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the compare match interrupt (CMPMIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1286 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1385 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1484 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG ( const LPTIM_TypeDef * LPTIMx )

Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1352 of file stm32g4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to up interrupt (UPIE) is enabled.

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_IsEnabledIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1451 of file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Private Variables

Variables
LPUART Private Variables
LPUART

Variables

static const uint16_t LPUART_PRESCALER_TAB []

Variable Documentation

const uint16_t LPUART_PRESCALER_TAB[] [static]
Initial value:
{
  (uint16_t)1,
  (uint16_t)2,
  (uint16_t)4,
  (uint16_t)6,
  (uint16_t)8,
  (uint16_t)10,
  (uint16_t)12,
  (uint16_t)16,
  (uint16_t)32,
  (uint16_t)64,
  (uint16_t)128,
  (uint16_t)256
}

Definition at line 46 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Private Constants

Defines
LPUART Private Constants
LPUART

Defines

#define | LPUART_DEFAULT_BAUDRATE (9600U)
#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U

Define Documentation

#define LPUART_BRR_MASK 0x000FFFFFU

Definition at line 71 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_BRR_MIN_VALUE 0x00000300U

Definition at line 72 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_DEFAULT_BAUDRATE (9600U)

Definition at line 48 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_StructInit().

#define LPUART_LPUARTDIV_FREQ_MUL 256U

Definition at line 70 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Private Macros

Defines
LPUART Private Macros
LPUART

Defines

#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 50000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_LPUART_BAUDRATE ( __BAUDRATE__ ) (((__BAUDRATE__) <= 50000000U) && ((__BAUDRATE__) >= 8U))

Definition at line 81 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x000FFFFFU)

Definition at line 87 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 0x300U)

Definition at line 84 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))

Definition at line 98 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))

Definition at line 89 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))

Definition at line 105 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PARITY_NONE) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))

Definition at line 94 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))

Definition at line 62 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_STOPBITS_1) \
                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))

Definition at line 102 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_LPUART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPUART_InitTypeDef Struct Reference
LPUART Exported Init structures

LL LPUART Init Structure definition. More...

#include <stm32g4xx_ll_lpuart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL LPUART Init Structure definition.

Definition at line 97 of file stm32g4xx_ll_lpuart.h.

Field Documentation

uint32_t LL_LPUART_InitTypeDef::BaudRate

This field defines expected LPUART communication baud rate.

This feature can be modified afterwards using unitary function LL_LPUART_SetBaudRate().

Definition at line 105 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_LPUART_SetDataWidth().

Definition at line 110 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetHWFlowCtrl().

Definition at line 134 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetParity().

Definition at line 122 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_LPUART_SetPrescaler().

Definition at line 99 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_LPUART_SetStopBitsLength().

Definition at line 116 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Direction.

This feature can be modified afterwards using unitary function LL_LPUART_SetTransferDirection().

Definition at line 128 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_lpuart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_WriteReg function. More...

Defines

#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_LPUART_WriteReg function.

Define Documentation

#define LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match clear flag

Definition at line 163 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS clear flag

Definition at line 162 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error clear flag

Definition at line 157 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected clear flag

Definition at line 160 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_NCF USART_ICR_NECF

Noise error detected clear flag

Definition at line 158 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error clear flag

Definition at line 159 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error clear flag

Definition at line 156 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete clear flag

Definition at line 161 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode clear flag

Definition at line 164 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_ReadReg function. More...

Defines

#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_LPUART_ReadReg function.

Define Documentation

#define LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 183 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 184 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 182 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 181 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 174 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 177 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 175 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 176 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 173 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 189 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 186 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 191 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 192 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 178 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 185 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 179 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 188 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 180 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 190 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 193 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 187 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
LPUART Exported Constants

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions. More...

Defines

#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Define Documentation

#define LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 209 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 202 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 208 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 211 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 203 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 205 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 206 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 210 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 213 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 212 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 216 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 215 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 214 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
LPUART Exported Constants

Defines

#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 226 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 225 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 224 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 227 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 228 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 229 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Direction

Defines
Direction
LPUART Exported Constants

Defines

#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_LPUART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 237 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 238 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 239 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 240 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Parity Control

Defines
Parity Control
LPUART Exported Constants

Defines

#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 249 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 248 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 250 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Wakeup

Defines
Wakeup
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Definition at line 259 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U

LPUART wake up from Mute mode on Idle Line

Definition at line 258 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Datawidth

Defines
Datawidth
LPUART Exported Constants

Defines

#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 267 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 268 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 269 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
LPUART Exported Constants

Defines

#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10
#define | LL_LPUART_PRESCALER_DIV12
#define | LL_LPUART_PRESCALER_DIV16
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64
#define | LL_LPUART_PRESCALER_DIV128
#define | LL_LPUART_PRESCALER_DIV256

Define Documentation

#define LL_LPUART_PRESCALER_DIV1 0x00000000U

Input clock not divided

Definition at line 277 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PRESCALER_DIV10
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 10

Definition at line 283 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV12
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_1)

Input clock divided by 12

Definition at line 285 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV128
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_1)

Input clock divided by 128

Definition at line 293 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV16
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 16

Definition at line 287 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock divided by 2

Definition at line 278 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV256
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 256

Definition at line 295 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock divided by 32

Definition at line 290 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock divided by 4

Definition at line 279 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV6
Value:
(USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 6

Definition at line 280 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV64
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 64

Definition at line 291 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock divided by 8

Definition at line 282 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Stop Bits

Defines
Stop Bits
LPUART Exported Constants

Defines

#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_LPUART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 305 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 306 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
LPUART Exported Constants

Defines

#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_LPUART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 314 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 315 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 324 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 323 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 333 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 332 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 343 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 341 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Bit Order

Defines
Bit Order
LPUART Exported Constants

Defines

#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 353 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 355 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
LPUART Exported Constants

Defines

#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 364 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 365 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Hardware Control

Defines
Hardware Control
LPUART Exported Constants

Defines

#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 376 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 373 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 374 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 378 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 386 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 388 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 387 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
LPUART Exported Constants

Defines

#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 396 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 397 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
LPUART Exported Constants

Defines

#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 406 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 405 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_DMA_GetRegAddr().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPUART Exported Macros

Defines

#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.

Define Documentation

#define LL_LPUART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 439 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 431 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Helper Macros

Defines
Helper Macros
LPUART Exported Macros

Defines

#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Define Documentation

#define __LL_LPUART_DIV | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(uint32_t)\
  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)

Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for LPUART Instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
__BAUDRATE__ | Baud Rate value to achieve
Return values:
LPUARTDIV value to be used for BRR register filling

Definition at line 468 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_SetBaudRate().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions

Functions
Configuration functions
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (const USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (const USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (const USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (const USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (const USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (const USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (const USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (const USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (const USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (const USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (const USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (const USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (const USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (const USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (const USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (const USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Function Documentation

__STATIC_INLINE void LL_LPUART_ConfigCharacter | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_LPUART_SetDataWidth() function
  • Parity Control and mode configuration using LL_LPUART_SetParity() function
  • Stop bits configuration using LL_LPUART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_ConfigCharacter
CR1 PCE LL_LPUART_ConfigCharacter
CR1 M LL_LPUART_ConfigCharacter
CR2 STOP LL_LPUART_ConfigCharacter
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 996 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
Parameters:
LPUARTx LPUART Instance
TXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 654 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigNodeAddress | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the LPUART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_ConfigNodeAddress
CR2 ADDM7 LL_LPUART_ConfigNodeAddress
Parameters:
LPUARTx | LPUART Instance
AddressLen This parameter can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the LPUART node.
Return values:
None

Definition at line 1168 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Disable ( USART_TypeDef * LPUARTx )

LPUART Disable.

Note:
When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their default values.
In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Disable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 514 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1241 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_DisableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 714 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_DisableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 736 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Disable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_DisableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 547 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableInStopMode ( USART_TypeDef * LPUARTx )

LPUART disabled in STOP Mode.

Note:
When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_DisableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 680 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableMuteMode ( USART_TypeDef * LPUARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_DisableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 882 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableOverrunDetect ( USART_TypeDef * LPUARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_DisableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1296 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1219 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Enable ( USART_TypeDef * LPUARTx )

LPUART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Enable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 495 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1230 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_EnableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 703 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_EnableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 725 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Enable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_EnableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 536 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableInStopMode ( USART_TypeDef * LPUARTx )

LPUART enabled in STOP Mode.

Note:
When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_EnableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 668 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableMuteMode ( USART_TypeDef * LPUARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_EnableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 871 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableOverrunDetect ( USART_TypeDef * LPUARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_EnableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1285 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1208 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate | ( | const USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue
 | ) |  |

Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_GetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
Baud Rate

Definition at line 1401 of file stm32g4xx_ll_lpuart.h.

References LPUART_BRR_MASK, LPUART_BRR_MIN_VALUE, and LPUART_LPUARTDIV_FREQ_MUL.

__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic ( const USART_TypeDef * LPUARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_GetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE

Definition at line 1109 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth ( const USART_TypeDef * LPUARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_GetDataWidth
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B

Definition at line 860 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl ( const USART_TypeDef * LPUARTx )

Return HW Flow Control configuration (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_GetHWFlowCtrl
CR3 CTSE LL_LPUART_GetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS

Definition at line 1274 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress ( const USART_TypeDef * LPUARTx )

Return 8 bit Address of the LPUART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_GetNodeAddress
Parameters:
LPUARTx LPUART Instance
Return values:
Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1184 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen ( const USART_TypeDef * LPUARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_LPUART_GetNodeAddressLen
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B

Definition at line 1197 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetParity ( const USART_TypeDef * LPUARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_GetParity
CR1 PCE LL_LPUART_GetParity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD

Definition at line 804 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler ( const USART_TypeDef * LPUARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_GetPrescaler
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256

Definition at line 940 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold ( const USART_TypeDef * LPUARTx )

Return RX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 628 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel ( const USART_TypeDef * LPUARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_GetRXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED

Definition at line 1052 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength ( const USART_TypeDef * LPUARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_GetStopBitsLength
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2

Definition at line 967 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder ( const USART_TypeDef * LPUARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST

Definition at line 1140 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection ( const USART_TypeDef * LPUARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_GetTransferDirection
CR1 TE LL_LPUART_GetTransferDirection
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX

Definition at line 770 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold ( const USART_TypeDef * LPUARTx )

Return TX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 593 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel ( const USART_TypeDef * LPUARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_GetTXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED

Definition at line 1079 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap ( const USART_TypeDef * LPUARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_GetTXRXSwap
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED

Definition at line 1025 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod ( const USART_TypeDef * LPUARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_GetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK

Definition at line 831 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType ( const USART_TypeDef * LPUARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_GetWKUPType
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE

Definition at line 1336 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabled ( const USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_IsEnabled
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 525 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO ( const USART_TypeDef * LPUARTx )

Indicate if FIFO Mode is enabled.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_IsEnabledFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 558 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode ( const USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_IsEnabledInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 692 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode ( const USART_TypeDef * LPUARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_IsEnabledMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 893 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect ( const USART_TypeDef * LPUARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1307 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | BaudRate
 | ) |  |

Configure LPUART BRR register for achieving expected Baud Rate value.

Note:
Compute and set LPUARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock and expected Baud Rate values
Peripheral clock and Baud Rate values provided as function parameters should be valid (Baud rate value != 0).
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baud rates using high PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_SetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
BaudRate | Baud Rate
Return values:
None

Definition at line 1370 of file stm32g4xx_ll_lpuart.h.

References __LL_LPUART_DIV.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_SetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
DataLogic This parameter can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1096 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDataWidth | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_SetDataWidth
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Return values:
None

Definition at line 846 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_SetHWFlowCtrl
CR3 CTSE LL_LPUART_SetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1258 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetParity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled)

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_SetParity
CR1 PCE LL_LPUART_SetParity
Parameters:
LPUARTx LPUART Instance
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
Return values:
None

Definition at line 789 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetPrescaler | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_SetPrescaler
Parameters:
LPUARTx LPUART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
None

Definition at line 917 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 611 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetRXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_SetRXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1039 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetStopBitsLength | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_SetStopBitsLength
Parameters:
LPUARTx LPUART Instance
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 954 of file stm32g4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetTransferBitOrder | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
BitOrder This parameter can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1125 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTransferDirection | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_SetTransferDirection
CR1 TE LL_LPUART_SetTransferDirection
Parameters:
LPUARTx LPUART Instance
TransferDirection This parameter can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX
Return values:
None

Definition at line 754 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 576 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_SetTXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1066 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXRXSwap | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_SetTXRXSwap
Parameters:
LPUARTx LPUART Instance
SwapConfig This parameter can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED
Return values:
None

Definition at line 1012 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWakeUpMethod | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_SetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Method This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 818 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWKUPType | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_SetWKUPType
Parameters:
LPUARTx LPUART Instance
Type This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1322 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (const USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableHalfDuplex ( USART_TypeDef * LPUARTx )

Disable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_DisableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1447 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableHalfDuplex ( USART_TypeDef * LPUARTx )

Enable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_EnableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1436 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex ( const USART_TypeDef * LPUARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1458 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (const USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (const USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (const USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (const USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDEMode ( USART_TypeDef * LPUARTx )

Disable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_DisableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1534 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDEMode ( USART_TypeDef * LPUARTx )

Enable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_EnableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1523 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime ( const USART_TypeDef * LPUARTx )

Return DEAT (Driver Enable Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_GetDEAssertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

Definition at line 1512 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime ( const USART_TypeDef * LPUARTx )

Return DEDT (Driver Enable De-Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_GetDEDeassertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : c

Definition at line 1489 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity ( const USART_TypeDef * LPUARTx )

Return Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_GetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW

Definition at line 1572 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode ( const USART_TypeDef * LPUARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_IsEnabledDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1545 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEAssertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_SetDEAssertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1501 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_SetDEDeassertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1478 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDESignalPolarity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_SetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Polarity This parameter can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW
Return values:
None

Definition at line 1559 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (const USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (const USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (const USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (const USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (const USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 1640 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 1664 of file stm32g4xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_ClearFlag_CM ( USART_TypeDef * LPUARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_LPUART_ClearFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1903 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_FE ( USART_TypeDef * LPUARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_LPUART_ClearFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1837 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE ( USART_TypeDef * LPUARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_LPUART_ClearFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1870 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS ( USART_TypeDef * LPUARTx )

Clear CTS Interrupt Flag.

Reference Manual to LL API cross reference:
ICR CTSCF LL_LPUART_ClearFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1892 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_NE ( USART_TypeDef * LPUARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_LPUART_ClearFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1848 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_ORE ( USART_TypeDef * LPUARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_LPUART_ClearFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1859 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_PE ( USART_TypeDef * LPUARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_LPUART_ClearFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1826 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TC ( USART_TypeDef * LPUARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_LPUART_ClearFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1881 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP ( USART_TypeDef * LPUARTx )

Clear Wake Up from stop mode Flag.

Reference Manual to LL API cross reference:
ICR WUCF LL_LPUART_ClearFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1914 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY ( const USART_TypeDef * LPUARTx )

Check if the LPUART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_LPUART_IsActiveFlag_BUSY
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1705 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM ( const USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_LPUART_IsActiveFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1716 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTS LL_LPUART_IsActiveFlag_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1694 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_LPUART_IsActiveFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE ( const USART_TypeDef * LPUARTx )

Check if the LPUART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_LPUART_IsActiveFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1635 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1683 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_LPUART_IsActiveFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1613 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE ( const USART_TypeDef * LPUARTx )

Check if the LPUART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_LPUART_IsActiveFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1624 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_LPUART_IsActiveFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1591 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_LPUART_IsActiveFlag_REACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1771 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU ( const USART_TypeDef * LPUARTx )

Check if the LPUART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_LPUART_IsActiveFlag_RWU
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1738 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFF LL_LPUART_IsActiveFlag_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1793 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFT LL_LPUART_IsActiveFlag_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1815 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1648 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_LPUART_IsActiveFlag_SBK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1727 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_LPUART_IsActiveFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1659 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_LPUART_IsActiveFlag_TEACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1760 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1672 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFE LL_LPUART_IsActiveFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1782 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFT LL_LPUART_IsActiveFlag_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1804 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP ( const USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from stop mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR WUF LL_LPUART_IsActiveFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1749 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (const USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (const USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (const USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 2089 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 2113 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 1938 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 1962 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 2240 of file stm32g4xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 2264 of file stm32g4xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableIT_CM ( USART_TypeDef * LPUARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_DisableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2143 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_CTS ( USART_TypeDef * LPUARTx )

Disable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_DisableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2191 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_ERROR ( USART_TypeDef * LPUARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_DisableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2180 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_IDLE ( USART_TypeDef * LPUARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_DisableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2084 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_PE ( USART_TypeDef * LPUARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_DisableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2132 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFF ( USART_TypeDef * LPUARTx )

Disable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_DisableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2165 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFT ( USART_TypeDef * LPUARTx )

Disable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_DisableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2224 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2097 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TC ( USART_TypeDef * LPUARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_DisableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2108 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2121 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFE ( USART_TypeDef * LPUARTx )

Disable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_DisableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2154 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFT ( USART_TypeDef * LPUARTx )

Disable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_DisableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2213 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_WKUP ( USART_TypeDef * LPUARTx )

Disable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_DisableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2202 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CM ( USART_TypeDef * LPUARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_EnableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1992 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CTS ( USART_TypeDef * LPUARTx )

Enable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_EnableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2040 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_ERROR ( USART_TypeDef * LPUARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_EnableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2029 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_IDLE ( USART_TypeDef * LPUARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_EnableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1933 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_PE ( USART_TypeDef * LPUARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_EnableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1981 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFF ( USART_TypeDef * LPUARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_EnableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2014 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFT ( USART_TypeDef * LPUARTx )

Enable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_EnableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2073 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1946 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TC ( USART_TypeDef * LPUARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_EnableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1957 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1970 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFE ( USART_TypeDef * LPUARTx )

Enable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_EnableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2003 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFT ( USART_TypeDef * LPUARTx )

Enable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_EnableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2062 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_WKUP ( USART_TypeDef * LPUARTx )

Enable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_EnableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2051 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM ( const USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_IsEnabledIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2294 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2338 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR ( const USART_TypeDef * LPUARTx )

Check if the LPUART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_IsEnabledIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2327 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE ( const USART_TypeDef * LPUARTx )

Check if the LPUART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2235 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_IsEnabledIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2283 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2316 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT ( const USART_TypeDef * LPUARTx )

Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2371 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2248 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_IsEnabledIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2259 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2272 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2305 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT ( const USART_TypeDef * LPUARTx )

Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2360 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP ( const USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2349 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA_Management

Functions
DMA_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (const USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2467 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_DisableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2401 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_DisableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2434 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr | ( | const USART_TypeDef * | LPUARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the LPUART data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_DMA_GetRegAddr
Parameters:
LPUARTx LPUART Instance
Direction This parameter can be one of the following values:
  • LL_LPUART_DMA_REG_DATA_TRANSMIT
  • LL_LPUART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 2493 of file stm32g4xx_ll_lpuart.h.

References LL_LPUART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2456 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_EnableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2390 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_EnableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2423 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr ( const USART_TypeDef * LPUARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2478 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX ( const USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2412 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX ( const USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2445 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8 ( const USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData8
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2525 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9 ( const USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData9
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2536 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData8 | ( | USART_TypeDef * | LPUARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData8
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2548 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData9 | ( | USART_TypeDef * | LPUARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData9
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2560 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Execution

Functions
Execution
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_LPUART_RequestBreakSending ( USART_TypeDef * LPUARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_LPUART_RequestBreakSending
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2579 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode ( USART_TypeDef * LPUARTx )

Put LPUART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_LPUART_RequestEnterMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2590 of file stm32g4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestRxDataFlush ( USART_TypeDef * LPUARTx )

Request a Receive Data and FIFO flush.

Note:
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_LPUART_RequestRxDataFlush
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2603 of file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
LPUART Exported Functions

Functions

ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_LPUART_DeInit ( const USART_TypeDef * LPUARTx )

De-initialize LPUART registers (Registers restored to their default values).

Parameters:
LPUARTx LPUART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are de-initialized
  • ERROR: not applicable

Definition at line 132 of file stm32g4xx_ll_lpuart.c.

References assert_param, LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_LPUART1, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_LPUART_Init | ( | USART_TypeDef * | LPUARTx,
 |  | const LL_LPUART_InitTypeDef * | LPUART_InitStruct
 | ) |  |

Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.

Note:
As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
LPUARTx | LPUART Instance
LPUART_InitStruct | pointer to a LL_LPUART_InitTypeDef structure that contains the configuration information for the specified LPUART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
  • ERROR: Problem occurred during LPUART Registers initialization

Definition at line 170 of file stm32g4xx_ll_lpuart.c.

References assert_param, LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, IS_LL_LPUART_BAUDRATE, IS_LL_LPUART_BRR_MAX, IS_LL_LPUART_BRR_MIN, IS_LL_LPUART_DATAWIDTH, IS_LL_LPUART_DIRECTION, IS_LL_LPUART_HWCONTROL, IS_LL_LPUART_PARITY, IS_LL_LPUART_PRESCALER, IS_LL_LPUART_STOPBITS, LL_LPUART_IsEnabled(), LL_LPUART_SetBaudRate(), LL_LPUART_SetHWFlowCtrl(), LL_LPUART_SetPrescaler(), LL_LPUART_SetStopBitsLength(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_PERIPH_FREQUENCY_NO, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

void LL_LPUART_StructInit ( LL_LPUART_InitTypeDef * LPUART_InitStruct )

Set each LL_LPUART_InitTypeDef field to default value.

Parameters:
LPUART_InitStruct pointer to a LL_LPUART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 255 of file stm32g4xx_ll_lpuart.c.

References LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, LL_LPUART_DATAWIDTH_8B, LL_LPUART_DIRECTION_TX_RX, LL_LPUART_HWCONTROL_NONE, LL_LPUART_PARITY_NONE, LL_LPUART_PRESCALER_DIV1, LL_LPUART_STOPBITS_1, LPUART_DEFAULT_BAUDRATE, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

Defines

#define | OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)

Define Documentation

#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)

Definition at line 53 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_SetCalibrationSelection().

#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)

Definition at line 54 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __OPAMP_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Register address

Definition at line 74 of file stm32g4xx_ll_opamp.h.

#define IS_LL_OPAMP_FUNCTIONAL_MODE ( __FUNCTIONAL_MODE__ )
Value:
(   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0)                         \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_BIAS)                    \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_IO1_BIAS)                \
  )

Definition at line 55 of file stm32g4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_INVERTING ( __INPUT_INVERTING__ )
Value:
(   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
  )

Definition at line 72 of file stm32g4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_NONINVERTING ( __INPUT_NONINVERTING__ )
Value:
(   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC)               \
  )

Definition at line 64 of file stm32g4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMALSPEED)                     \
   || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_HIGHSPEED))

Definition at line 51 of file stm32g4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_OPAMP_InitTypeDef Struct Reference
OPAMP Exported Init structure

Structure definition of some features of OPAMP instance. More...

#include <stm32g4xx_ll_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | FunctionalMode
uint32_t | InputNonInverting
uint32_t | InputInverting

Detailed Description

Structure definition of some features of OPAMP instance.

Definition at line 94 of file stm32g4xx_ll_opamp.h.

Field Documentation

uint32_t LL_OPAMP_InitTypeDef::FunctionalMode

Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ... This parameter can be a value of OPAMP functional mode

Note:
If OPAMP is configured in mode PGA, the gain can be configured using function LL_OPAMP_SetPGAGain().

This feature can be modified afterwards using unitary function LL_OPAMP_SetFunctionalMode().

Definition at line 102 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputInverting

Set OPAMP inverting input connection. This parameter can be a value of OPAMP input inverting

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputInverting().

Definition at line 113 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputNonInverting

Set OPAMP input non-inverting connection. This parameter can be a value of OPAMP input non-inverting

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputNonInverting().

Definition at line 108 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::PowerMode

Set OPAMP power mode. This parameter can be a value of OPAMP_LL_EC_POWERMODE

This feature can be modified afterwards using unitary function LL_OPAMP_SetPowerMode().

Definition at line 96 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_opamp.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP mode calibration or functional.

Defines
OPAMP mode calibration or functional.
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_FUNCTIONAL (0x00000000UL)
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)

Define Documentation

#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)

OPAMP calibration mode

Definition at line 135 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_MODE_FUNCTIONAL (0x00000000UL)

OPAMP functional mode

Definition at line 134 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP functional mode

Defines
OPAMP functional mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_STANDALONE (0x00000000UL)
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)

Define Documentation

#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)

OPAMP functional mode, OPAMP operation in follower

Definition at line 144 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)

OPAMP functional mode, OPAMP operation in PGA

Definition at line 145 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0 for filtering

Definition at line 146 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain

Definition at line 147 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)

In PGA mode, the inverting input is connected to VINM0

  • Input signal on VINM0, bias on VINPx: negative gain
  • Bias on VINM0, input signal on VINPx: positive gain And VINM1 is connected too for filtering

Definition at line 150 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_MODE_STANDALONE (0x00000000UL)

OPAMP functional mode, OPAMP operation in standalone

Definition at line 143 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)

Defines
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP Exported Constants

Defines

#define | LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)
#define | LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )
#define | LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)

Detailed Description

Note:
Gain sign:
  • is positive if the OPAMP functional mode configuration is LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0
  • may be positive or negative if the OPAMP functional mode configuration is LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS see OPAMP functional mode for more details

Define Documentation

#define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 16 or -15

Definition at line 171 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)

OPAMP PGA gain 2 or -1

Definition at line 168 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )

OPAMP PGA gain 32 or -31

Definition at line 172 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 4 or -3

Definition at line 169 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 64 or -63

Definition at line 173 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )

OPAMP PGA gain 8 or -7

Definition at line 170 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP input non-inverting

Defines
OPAMP input non-inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000UL)
#define | LL_OPAMP_INPUT_NONINVERT_IO1 OPAMP_CSR_VPSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_IO2 OPAMP_CSR_VPSEL_1
#define | LL_OPAMP_INPUT_NONINVERT_IO3 OPAMP_CSR_VPSEL
#define | LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL

Define Documentation

#define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL

OPAMP non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 192 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000UL)

OPAMP non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 181 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

#define LL_OPAMP_INPUT_NONINVERT_IO1 OPAMP_CSR_VPSEL_0

OPAMP non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 184 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO2 OPAMP_CSR_VPSEL_1

OPAMP non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 187 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO3 OPAMP_CSR_VPSEL

OPAMP non inverting input connected to I/O VINP3 (PD14 for OPAMP2)

Definition at line 190 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP input inverting

Defines
OPAMP input inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_INVERT_IO0 (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1

Detailed Description

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

Define Documentation

#define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1

OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias). Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA.

Definition at line 210 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

#define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000UL)

OPAMP inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 204 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0

OPAMP inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 207 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP input non-inverting secondary

Defines
OPAMP input non-inverting secondary
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_NONINVERT_IO0_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_NONINVERT_IO1_SEC OPAMP_TCMR_VPSSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_IO2_SEC OPAMP_TCMR_VPSSEL_1
#define | LL_OPAMP_INPUT_NONINVERT_IO3_SEC OPAMP_TCMR_VPSSEL
#define | LL_OPAMP_INPUT_NONINVERT_DAC_SEC OPAMP_TCMR_VPSSEL

Define Documentation

#define LL_OPAMP_INPUT_NONINVERT_DAC_SEC OPAMP_TCMR_VPSSEL

OPAMP secondary non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 230 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (0x00000000UL)

OPAMP secondary non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 219 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC OPAMP_TCMR_VPSSEL_0

OPAMP secondary non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 222 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC OPAMP_TCMR_VPSSEL_1

OPAMP secondary non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 225 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC OPAMP_TCMR_VPSSEL

OPAMP secondary non inverting input connected to I/O VINP3 (PD14 for OPAMP2)

Definition at line 228 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP input inverting secondary

Defines
OPAMP input inverting secondary
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_INVERT_IO0_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_IO1_SEC OPAMP_TCMR_VMSSEL
#define | LL_OPAMP_INPUT_INVERT_PGA_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC OPAMP_TCMR_VMSSEL

Detailed Description

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

Define Documentation

#define LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC OPAMP_TCMR_VMSSEL

OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to LL_OPAMP_Init() or LL_OPAMP_SetFunctionalMode() is NOT LL_OPAMP_MODE_STANDALONE. OPAMP secondary inverting input is not connected.

Definition at line 258 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_IO0_SEC (0x00000000UL)

OPAMP secondary mode is standalone mode - Only applicable if LL_OPAMP_MODE_STANDALONE has been configured by call to LL_OPAMP_Init() or LL_OPAMP_SetFunctionalMode(). OPAMP secondary inverting input connected to I/O VINM0. (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 242 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_IO1_SEC OPAMP_TCMR_VMSSEL

OPAMP secondary mode is standalone mode - Only applicable if LL_OPAMP_MODE_STANDALONE has been configured by call to LL_OPAMP_Init() or LL_OPAMP_SetFunctionalMode(). OPAMP secondary inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 247 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_PGA_SEC (0x00000000UL)

OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to LL_OPAMP_Init() or LL_OPAMP_SetFunctionalMode() is NOT LL_OPAMP_MODE_STANDALONE. OPAMP secondary inverting input is:

  • Not connected if configured mode is LL_OPAMP_MODE_FOLLOWER or LL_OPAMP_MODE_PGA
  • Connected to VINM0 and possibly VINM1 if any of the other modes as been configured (see OPAMP functional mode description for more details on PGA connection modes)

Definition at line 252 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP internal output mode

Defines
OPAMP internal output mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INTERNAL_OUPUT_DISABLED (0x00000000UL)
#define | LL_OPAMP_INTERNAL_OUPUT_ENABLED OPAMP_CSR_OPAMPINTEN

Define Documentation

#define LL_OPAMP_INTERNAL_OUPUT_DISABLED (0x00000000UL)

OPAMP internal output to ADC disabled.

Definition at line 268 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INTERNAL_OUPUT_ENABLED OPAMP_CSR_OPAMPINTEN

OPAMP internal output to ADC enabled.

  • OPAMP1 internal output is connected to ADC1/Channel13
  • OPAMP2 internal output is connected to ADC2/Channel16
  • OPAMP3 internal output is connected to ADC2/Channel18 & ADC3/Channel13
  • OPAMP4 internal output is connected to ADC5/Channel5
  • OPAMP5 internal output is connected to ADC5/Channel3
  • OPAMP6 internal output is connected to ADC4/Channel17 Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details

Definition at line 269 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP inputs multiplexer mode

Defines
OPAMP inputs multiplexer mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_MUX_DISABLE (0x00000000UL)
#define | LL_OPAMP_INPUT_MUX_TIM1_CH6 OPAMP_TCMR_T1CMEN
#define | LL_OPAMP_INPUT_MUX_TIM8_CH6 OPAMP_TCMR_T8CMEN
#define | LL_OPAMP_INPUT_MUX_TIM20_CH6 OPAMP_TCMR_T20CMEN

Detailed Description

Note:
The switch can be controlled either by a single timer or a combination of them, in this case application has to 'ORed' the values below ex LL_OPAMP_INPUT_MUX_TIM1_CH6 | LL_OPAMP_INPUT_MUX_TIM20_CH6

Define Documentation

#define LL_OPAMP_INPUT_MUX_DISABLE (0x00000000UL)

OPAMP inputs timer controlled multiplexer mode disabled.

Definition at line 287 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_MUX_TIM1_CH6 OPAMP_TCMR_T1CMEN

OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM1 OC6.

Definition at line 288 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_MUX_TIM20_CH6 OPAMP_TCMR_T20CMEN

OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM20 OC6. Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details

Definition at line 290 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_MUX_TIM8_CH6 OPAMP_TCMR_T8CMEN

OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM8 OC6.

Definition at line 289 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)
#define | LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN
#define | LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED

Define Documentation

#define LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN

OPAMP output in highspeed mode

Definition at line 300 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED

OPAMP power mode normal - Old Naming for compatibility

Definition at line 302 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)

OPAMP output in normal mode

Definition at line 299 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP trimming mode

Defines
OPAMP trimming mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_FACTORY (0x00000000UL)
#define | LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

Define Documentation

#define LL_OPAMP_TRIMMING_FACTORY (0x00000000UL)

OPAMP trimming factors set to factory values

Definition at line 311 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

OPAMP trimming factors set to user values

Definition at line 312 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP trimming of transistors differential pair NMOS or PMOS

Defines
OPAMP trimming of transistors differential pair NMOS or PMOS
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0)
#define | LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 )
#define | LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0)
#define | LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP )
#define | LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)
#define | LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)

Define Documentation

#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 324 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 )

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda).

Definition at line 321 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0)

OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 320 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 325 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0)

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS).

Definition at line 322 of file stm32g4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP )

OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda).

Definition at line 323 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Definitions of OPAMP hardware constraints delays

Defines
Definitions of OPAMP hardware constraints delays
OPAMP Exported Constants

Defines

#define LL_OPAMP_DELAY_STARTUP_US (6)

Detailed Description

Note:
Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_OPAMP_DELAY_STARTUP_US (6)

Delay for OPAMP startup time

Definition at line 347 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
OPAMP Exported Macros

Defines

#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in OPAMP register.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in OPAMP register.

Define Documentation

#define LL_OPAMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in OPAMP register.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 378 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit().

#define LL_OPAMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in OPAMP register.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 370 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit().

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of OPAMP hierarchical scope: OPAMP instance

Functions
Configuration of OPAMP hierarchical scope: OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.
__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode normal or highspeed.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode normal or highspeed.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP functional mode from setting of internal connections.

OPAMP operation in standalone, follower, ...

Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_GetFunctionalMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA
  • LL_OPAMP_MODE_PGA_IO0
  • LL_OPAMP_MODE_PGA_IO0_BIAS
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS

Definition at line 472 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_GetMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION

Definition at line 430 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain ( OPAMP_TypeDef * OPAMPx )

Get OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_GetPGAGain
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
  • LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
  • LL_OPAMP_PGA_GAIN_64_OR_MINUS_63

Definition at line 511 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP power mode normal or highspeed.

Note:
OPAMP highspeed mode allows output stage to have a better slew rate.
Reference Manual to LL API cross reference:
CSR HIGHSPEEDEN LL_OPAMP_GetPowerMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMALSPEED
  • LL_OPAMP_POWERMODE_HIGHSPEED

Definition at line 540 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetFunctionalMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | FunctionalMode
 | ) |  |

Set OPAMP functional mode by setting internal connections.

OPAMP operation in standalone, follower, ...

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_SetFunctionalMode
Parameters:
OPAMPx OPAMP instance
FunctionalMode This parameter can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA
  • LL_OPAMP_MODE_PGA_IO0
  • LL_OPAMP_MODE_PGA_IO0_BIAS
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
Return values:
None

Definition at line 453 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | Mode
 | ) |  |

Set OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_SetMode
Parameters:
OPAMPx OPAMP instance
Mode This parameter can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION
Return values:
None

Definition at line 411 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPGAGain | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PGAGain
 | ) |  |

Set OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_SetPGAGain
Parameters:
OPAMPx OPAMP instance
PGAGain This parameter can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
  • LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
  • LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
Return values:
None

Definition at line 492 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPowerMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set OPAMP power mode normal or highspeed.

Note:
OPAMP highspeed mode allows output stage to have a better slew rate.
Reference Manual to LL API cross reference:
CSR HIGHSPEEDEN LL_OPAMP_SetPowerMode
Parameters:
OPAMPx OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMALSPEED
  • LL_OPAMP_POWERMODE_HIGHSPEED
Return values:
None

Definition at line 526 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration of OPAMP inputs

Functions
Configuration of OPAMP inputs
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputNonInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input secondary connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInvertingSecondary (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input secondary connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input secondary connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input secondary connection.
__STATIC_INLINE void | LL_OPAMP_SetInputsMuxMode (OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
Set OPAMP inputs multiplexer mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputsMuxMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP inputs multiplexer mode.
__STATIC_INLINE void | LL_OPAMP_SetInternalOutput (OPAMP_TypeDef *OPAMPx, uint32_t InternalOutput)
Set OPAMP internal output.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInternalOutput (OPAMP_TypeDef *OPAMPx)
Get OPAMP internal output state.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP inverting input connection.

Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_GetInputInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO

Definition at line 616 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary ( OPAMP_TypeDef * OPAMPx )

Get OPAMP inverting input secondary connection.

Reference Manual to LL API cross reference:
TCMR VMSSEL LL_OPAMP_GetInputInvertingSecondary
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0_SEC
  • LL_OPAMP_INPUT_INVERT_IO1_SEC
  • LL_OPAMP_INPUT_INVERT_PGA_SEC
  • LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC

Definition at line 688 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_GetInputNonInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_IO1
  • LL_OPAMP_INPUT_NONINVERT_IO2
  • LL_OPAMP_INPUT_NONINVERT_IO3
  • LL_OPAMP_INPUT_NONINVERT_DAC

Definition at line 580 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary ( OPAMP_TypeDef * OPAMPx )

Get OPAMP non-inverting input secondary connection.

Reference Manual to LL API cross reference:
TCMR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO1_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO2_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO3_SEC
  • LL_OPAMP_INPUT_NONINVERT_DAC_SEC

Definition at line 653 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP inputs multiplexer mode.

Reference Manual to LL API cross reference:
TCMR TCMEN LL_OPAMP_GetInputsMuxMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_MUX_DISABLE
  • LL_OPAMP_INPUT_MUX_TIM1_CH6
  • LL_OPAMP_INPUT_MUX_TIM8_CH6
  • LL_OPAMP_INPUT_MUX_TIM20_CH6 (1) On this STM32 series, this value is not available on all devices. Refer to datasheet for details.

Definition at line 721 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInternalOutput ( OPAMP_TypeDef * OPAMPx )

Get OPAMP internal output state.

Reference Manual to LL API cross reference:
CSR OPAMPINTEN LL_OPAMP_GetInternalOutput
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INTERNAL_OUPUT_DISABLED
  • LL_OPAMP_INTERNAL_OUPUT_ENABLED

Definition at line 749 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputInverting
 | ) |  |

Set OPAMP inverting input connection.

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_SetInputInverting
Parameters:
OPAMPx OPAMP instance
InputInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO
Return values:
None

Definition at line 599 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputInverting
 | ) |  |

Set OPAMP inverting input secondary connection.

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
Reference Manual to LL API cross reference:
TCMR VMSSEL LL_OPAMP_SetInputInvertingSecondary
Parameters:
OPAMPx OPAMP instance
InputInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0_SEC
  • LL_OPAMP_INPUT_INVERT_IO1_SEC
  • LL_OPAMP_INPUT_INVERT_PGA_SEC
  • LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
Return values:
None

Definition at line 673 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputNonInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputNonInverting
 | ) |  |

Set OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_SetInputNonInverting
Parameters:
OPAMPx OPAMP instance
InputNonInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_IO1
  • LL_OPAMP_INPUT_NONINVERT_IO2
  • LL_OPAMP_INPUT_NONINVERT_IO3
  • LL_OPAMP_INPUT_NONINVERT_DAC
Return values:
None

Definition at line 564 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputNonInverting
 | ) |  |

Set OPAMP non-inverting input secondary connection.

Reference Manual to LL API cross reference:
TCMR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
Parameters:
OPAMPx OPAMP instance
InputNonInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO1_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO2_SEC
  • LL_OPAMP_INPUT_NONINVERT_IO3_SEC
  • LL_OPAMP_INPUT_NONINVERT_DAC_SEC
Return values:
None

Definition at line 637 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputsMuxMode
 | ) |  |

Set OPAMP inputs multiplexer mode.

Reference Manual to LL API cross reference:
TCMR TCMEN LL_OPAMP_SetInputsMuxMode
Parameters:
OPAMPx OPAMP instance
InputsMuxMode This parameter can be one of the following values:
  • LL_OPAMP_INPUT_MUX_DISABLE
  • LL_OPAMP_INPUT_MUX_TIM1_CH6
  • LL_OPAMP_INPUT_MUX_TIM8_CH6
  • LL_OPAMP_INPUT_MUX_TIM20_CH6 (1) On this STM32 series, this value is not available on all devices. Refer to datasheet for details.
Return values:
None

Definition at line 705 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInternalOutput | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InternalOutput
 | ) |  |

Set OPAMP internal output.

Note:
OPAMP internal output is used to link OPAMP output to ADC input internally.
Reference Manual to LL API cross reference:
CSR OPAMPINTEN LL_OPAMP_SetInternalOutput
Parameters:
OPAMPx OPAMP instance
InternalOutput This parameter can be one of the following values:
  • LL_OPAMP_INTERNAL_OUPUT_DISABLED
  • LL_OPAMP_INTERNAL_OUPUT_ENABLED
Return values:
None

Definition at line 736 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration and operation of OPAMP trimming

Functions
Configuration and operation of OPAMP trimming
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection ( OPAMP_TypeDef * OPAMPx )

Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_GetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS (1)
  • LL_OPAMP_TRIMMING_PMOS (1)
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
(1) Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS)

Definition at line 831 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_GetTrimmingMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER

Definition at line 784 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue
CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
Parameters:
OPAMPx OPAMP instance
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
Return values:
0x0...0x1F

Definition at line 886 of file stm32g4xx_ll_opamp.h.

References LL_OPAMP_TRIMMING_NMOS, and OPAMP_TRIMMING_VALUE_MASK.

__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet ( OPAMP_TypeDef * OPAMPx )

Get OPAMP calibration result of toggling output.

Note:
This functions returns: 0 if OPAMP calibration output is reset 1 if OPAMP calibration output is set
Reference Manual to LL API cross reference:
CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 848 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_SetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS (1)
  • LL_OPAMP_TRIMMING_PMOS (1)
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
(1) Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS)
Return values:
None

Definition at line 807 of file stm32g4xx_ll_opamp.h.

References OPAMP_TRIMMING_SELECT_MASK.

__STATIC_INLINE void LL_OPAMP_SetTrimmingMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TrimmingMode
 | ) |  |

Set OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_SetTrimmingMode
Parameters:
OPAMPx OPAMP instance
TrimmingMode This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER
Return values:
None

Definition at line 771 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TransistorsDiffPair,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
Parameters:
OPAMPx | OPAMP instance
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
TrimmingValue | 0x00...0x1F
Return values:
None

Definition at line 866 of file stm32g4xx_ll_opamp.h.

References LL_OPAMP_TRIMMING_NMOS, and OPAMP_TRIMMING_VALUE_MASK.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation on OPAMP instance

Functions
Operation on OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)
__STATIC_INLINE void | LL_OPAMP_Lock (OPAMP_TypeDef *OPAMPx)
Lock OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsLocked (OPAMP_TypeDef *OPAMPx)
Get OPAMP lock state (0: OPAMP is unlocked, 1: OPAMP is locked).
__STATIC_INLINE void | LL_OPAMP_LockTimerMux (OPAMP_TypeDef *OPAMPx)
Lock OPAMP instance timer controlled mux.
__STATIC_INLINE uint32_t | LL_OPAMP_IsTimerMuxLocked (OPAMP_TypeDef *OPAMPx)
Get OPAMP timer controlled mux lock state (0: OPAMP timer controlled mux is unlocked, 1: OPAMP timer controlled mux is locked).

Function Documentation

__STATIC_INLINE void LL_OPAMP_Disable ( OPAMP_TypeDef * OPAMPx )

Disable OPAMP instance.

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Disable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 919 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_Enable ( OPAMP_TypeDef * OPAMPx )

Enable OPAMP instance.

Note:
After enable from off state, OPAMP requires a delay to fulfill wake up time specification. Refer to device datasheet, parameter "tWAKEUP".
Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Enable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 908 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled ( OPAMP_TypeDef * OPAMPx )

Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_IsEnabled
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 931 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_IsLocked ( OPAMP_TypeDef * OPAMPx )

Get OPAMP lock state (0: OPAMP is unlocked, 1: OPAMP is locked).

Note:
Once locked, OPAMP configuration can be accessed in read-only.
The only way to unlock the OPAMP is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_OPAMP_IsLocked
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 958 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit(), and LL_OPAMP_Init().

__STATIC_INLINE uint32_t LL_OPAMP_IsTimerMuxLocked ( OPAMP_TypeDef * OPAMPx )

Get OPAMP timer controlled mux lock state (0: OPAMP timer controlled mux is unlocked, 1: OPAMP timer controlled mux is locked).

Note:
Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
Reference Manual to LL API cross reference:
TCMR LOCK LL_OPAMP_IsTimerMuxLocked
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 985 of file stm32g4xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit().

__STATIC_INLINE void LL_OPAMP_Lock ( OPAMP_TypeDef * OPAMPx )

Lock OPAMP instance.

Note:
Once locked, OPAMP configuration can be accessed in read-only.
The only way to unlock the OPAMP is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_OPAMP_Lock
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 944 of file stm32g4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_LockTimerMux ( OPAMP_TypeDef * OPAMPx )

Lock OPAMP instance timer controlled mux.

Note:
Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
Reference Manual to LL API cross reference:
TCMR LOCK LL_OPAMP_LockTimerMux
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 971 of file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_OPAMP_DeInit ( OPAMP_TypeDef * OPAMPx )

De-initialize registers of the selected OPAMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
OPAMPx OPAMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are de-initialized
  • ERROR: OPAMP registers are not de-initialized

Definition at line 105 of file stm32g4xx_ll_opamp.c.

References assert_param, LL_OPAMP_IsLocked(), LL_OPAMP_IsTimerMuxLocked(), LL_OPAMP_ReadReg, and LL_OPAMP_WriteReg.

ErrorStatus LL_OPAMP_Init | ( | OPAMP_TypeDef * | OPAMPx,
 |  | LL_OPAMP_InitTypeDef * | OPAMP_InitStruct
 | ) |  |

Initialize some features of OPAMP instance.

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
Parameters:
OPAMPx | OPAMP instance
OPAMP_InitStruct | Pointer to a LL_OPAMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are initialized
  • ERROR: OPAMP registers are not initialized

Definition at line 157 of file stm32g4xx_ll_opamp.c.

References assert_param, LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, IS_LL_OPAMP_FUNCTIONAL_MODE, IS_LL_OPAMP_INPUT_INVERTING, IS_LL_OPAMP_INPUT_NONINVERTING, IS_LL_OPAMP_POWER_MODE, LL_OPAMP_IsLocked(), LL_OPAMP_MODE_FOLLOWER, and LL_OPAMP_InitTypeDef::PowerMode.

void LL_OPAMP_StructInit ( LL_OPAMP_InitTypeDef * OPAMP_InitStruct )

Set each LL_OPAMP_InitTypeDef field to default value.

Parameters:
OPAMP_InitStruct pointer to a LL_OPAMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 231 of file stm32g4xx_ll_opamp.c.

References LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, LL_OPAMP_INPUT_INVERT_CONNECT_NO, LL_OPAMP_INPUT_NONINVERT_IO0, LL_OPAMP_MODE_FOLLOWER, LL_OPAMP_POWERMODE_NORMALSPEED, and LL_OPAMP_InitTypeDef::PowerMode.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_SCR_CSBF PWR_SCR_CSBF

Definition at line 57 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF PWR_SCR_CWUF

Definition at line 58 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Definition at line 63 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2

Definition at line 62 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3

Definition at line 61 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4

Definition at line 60 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5

Definition at line 59 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_SR1_SBF PWR_SR1_SBF

Definition at line 73 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1

Definition at line 78 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2

Definition at line 77 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3

Definition at line 76 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4

Definition at line 75 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5

Definition at line 74 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR1_WUFI PWR_SR1_WUFI

Definition at line 72 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_PVDO PWR_SR2_PVDO

Definition at line 91 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1

Definition at line 89 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2

Definition at line 86 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3

Definition at line 83 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4

Definition at line 80 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF

Definition at line 93 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Definition at line 94 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_SR2_VOSF PWR_SR2_VOSF

Definition at line 92 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: REGU VOLTAGE

Defines
REGU VOLTAGE
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)

Definition at line 102 of file stm32g4xx_ll_pwr.h.

Referenced by LL_SetFlashLatency().

#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)

Definition at line 103 of file stm32g4xx_ll_pwr.h.

Referenced by LL_SetFlashLatency().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MODE PWR

Defines
MODE PWR
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)

Define Documentation

#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)

Definition at line 114 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)

Definition at line 113 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)

Definition at line 111 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)

Definition at line 112 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral voltage monitoring

Defines
Peripheral voltage monitoring
PWR Exported Constants

Defines

#define | LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
#define | LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
#define | LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#define | LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */

Define Documentation

#define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */

Definition at line 129 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */

Definition at line 123 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */

Definition at line 126 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */

Definition at line 132 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PVDLEVEL

Defines
PVDLEVEL
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */

Define Documentation

#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */

Definition at line 141 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */

Definition at line 142 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */

Definition at line 143 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */

Definition at line 144 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */

Definition at line 145 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */

Definition at line 146 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */

Definition at line 147 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */

Definition at line 148 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WAKEUP

Defines
WAKEUP
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)

Definition at line 156 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)

Definition at line 157 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)

Definition at line 158 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)

Definition at line 159 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Definition at line 160 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BATT CHARG RESISTOR

Defines
BATT CHARG RESISTOR
PWR Exported Constants

Defines

#define | LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Define Documentation

#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)

Definition at line 168 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Definition at line 169 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO

Defines
GPIO
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define | LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))

Define Documentation

#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))

Definition at line 177 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))

Definition at line 178 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))

Definition at line 179 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))

Definition at line 180 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))

Definition at line 181 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))

Definition at line 182 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))

Definition at line 183 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO BIT

Defines
GPIO BIT
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
#define | LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
#define | LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
#define | LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
#define | LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
#define | LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
#define | LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
#define | LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
#define | LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
#define | LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
#define | LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
#define | LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
#define | LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
#define | LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
#define | LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
#define | LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)

Define Documentation

#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)

Definition at line 191 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)

Definition at line 192 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)

Definition at line 201 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)

Definition at line 202 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)

Definition at line 203 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)

Definition at line 204 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)

Definition at line 205 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)

Definition at line 206 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)

Definition at line 193 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)

Definition at line 194 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)

Definition at line 195 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)

Definition at line 196 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)

Definition at line 197 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)

Definition at line 198 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)

Definition at line 199 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)

Definition at line 200 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 237 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 230 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableRange1BoostMode (void)
Enable main regulator voltage range 1 boost mode.
__STATIC_INLINE void | LL_PWR_DisableRange1BoostMode (void)
Disable main regulator voltage range 1 boost mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledRange1BoostMode (void)
Check if the main regulator voltage range 1 boost mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_EnableUCPDStandbyMode (void)
Enable the USB Type-C and Power Delivery memorization in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableUCPDStandbyMode (void)
Disable the USB Type-C and Power Delivery memorization in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUCPDStandbyMode (void)
Check the USB Type-C and Power Delivery Standby mode memorization state.
__STATIC_INLINE void | LL_PWR_EnableUCPDDeadBattery (void)
Enable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE void | LL_PWR_DisableUCPDDeadBattery (void)
Disable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUCPDDeadBattery (void)
Check the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBatteryCharging ( void )

Disable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_DisableBatteryCharging
Return values:
None

Definition at line 922 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 385 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_DisableGPIOPullDown
PDCRB PD0-15 LL_PWR_DisableGPIOPullDown
PDCRC PD0-15 LL_PWR_DisableGPIOPullDown
PDCRD PD0-15 LL_PWR_DisableGPIOPullDown
PDCRE PD0-15 LL_PWR_DisableGPIOPullDown
PDCRF PD0-15 LL_PWR_DisableGPIOPullDown
PDCRG PD0-15 LL_PWR_DisableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1213 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_DisableGPIOPullUp
PUCRB PU0-15 LL_PWR_DisableGPIOPullUp
PUCRC PU0-15 LL_PWR_DisableGPIOPullUp
PUCRD PU0-15 LL_PWR_DisableGPIOPullUp
PUCRE PU0-15 LL_PWR_DisableGPIOPullUp
PUCRF PU0-15 LL_PWR_DisableGPIOPullUp
PUCRG PU0-15 LL_PWR_DisableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1084 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableInternWU ( void )

Disable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_DisableInternWU
Return values:
None

Definition at line 738 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode ( void )

Switch the regulator from low-power mode to main mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_DisableLowPowerRunMode
Return values:
None

Definition at line 271 of file stm32g4xx_ll_pwr.h.

Referenced by LL_PWR_ExitLowPowerRunMode().

__STATIC_INLINE void LL_PWR_DisablePUPDCfg ( void )

Disable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_DisablePUPDCfg
Return values:
None

Definition at line 768 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 705 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVM ( uint32_t PeriphVoltage )

Disable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_DisablePVM
CR2 PVME2 LL_PWR_DisablePVM
CR2 PVME3 LL_PWR_DisablePVM
CR2 PVME4 LL_PWR_DisablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDA_COMP (*)
  • LL_PWR_PVM_VDDA_FASTDAC (*)
  • LL_PWR_PVM_VDDA_ADC
  • LL_PWR_PVM_VDDA_OPAMP_DAC
(*) value not defined in all devices
Return values:
None

Definition at line 624 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableRange1BoostMode ( void )

Disable main regulator voltage range 1 boost mode.

Reference Manual to LL API cross reference:
CR5 R1MODE LL_PWR_DisableRange1BoostMode
Return values:
None

Definition at line 351 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSRAM2Retention ( void )

Disable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_DisableSRAM2Retention
Return values:
None

Definition at line 801 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery ( void )

Disable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.

Note:
After exiting reset, the USB Type-C dead battery behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable).
Reference Manual to LL API cross reference:
CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
Return values:
None

Definition at line 496 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode ( void )

Disable the USB Type-C and Power Delivery memorization in Standby mode.

Note:
This function must be called after exiting Standby mode and before any UCPD configuration update.
Reference Manual to LL API cross reference:
CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
Return values:
None

Definition at line 452 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_DisableWakeUpPin
CR3 EWUP2 LL_PWR_DisableWakeUpPin
CR3 EWUP3 LL_PWR_DisableWakeUpPin
CR3 EWUP4 LL_PWR_DisableWakeUpPin
CR3 EWUP5 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 854 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBatteryCharging ( void )

Enable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_EnableBatteryCharging
Return values:
None

Definition at line 912 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 375 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_EnableGPIOPullDown
PDCRB PD0-15 LL_PWR_EnableGPIOPullDown
PDCRC PD0-15 LL_PWR_EnableGPIOPullDown
PDCRD PD0-15 LL_PWR_EnableGPIOPullDown
PDCRE PD0-15 LL_PWR_EnableGPIOPullDown
PDCRF PD0-15 LL_PWR_EnableGPIOPullDown
PDCRG PD0-15 LL_PWR_EnableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1170 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_EnableGPIOPullUp
PUCRB PU0-15 LL_PWR_EnableGPIOPullUp
PUCRC PU0-15 LL_PWR_EnableGPIOPullUp
PUCRD PU0-15 LL_PWR_EnableGPIOPullUp
PUCRE PU0-15 LL_PWR_EnableGPIOPullUp
PUCRF PU0-15 LL_PWR_EnableGPIOPullUp
PUCRG PU0-15 LL_PWR_EnableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1041 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableInternWU ( void )

Enable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_EnableInternWU
Return values:
None

Definition at line 728 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode ( void )

Switch the regulator from main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnableLowPowerRunMode
Return values:
None

Definition at line 261 of file stm32g4xx_ll_pwr.h.

Referenced by LL_PWR_EnterLowPowerRunMode().

__STATIC_INLINE void LL_PWR_EnablePUPDCfg ( void )

Enable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_EnablePUPDCfg
Return values:
None

Definition at line 758 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 695 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVM ( uint32_t PeriphVoltage )

Enable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_EnablePVM
CR2 PVME2 LL_PWR_EnablePVM
CR2 PVME3 LL_PWR_EnablePVM
CR2 PVME4 LL_PWR_EnablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDA_COMP (*)
  • LL_PWR_PVM_VDDA_FASTDAC (*)
  • LL_PWR_PVM_VDDA_ADC
  • LL_PWR_PVM_VDDA_OPAMP_DAC
(*) value not defined in all devices
Return values:
None

Definition at line 604 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableRange1BoostMode ( void )

Enable main regulator voltage range 1 boost mode.

Reference Manual to LL API cross reference:
CR5 R1MODE LL_PWR_EnableRange1BoostMode
Return values:
None

Definition at line 341 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSRAM2Retention ( void )

Enable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_EnableSRAM2Retention
Return values:
None

Definition at line 791 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery ( void )

Enable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.

Note:
After exiting reset, the USB Type-C dead battery behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable).
Reference Manual to LL API cross reference:
CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
Return values:
None

Definition at line 481 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode ( void )

Enable the USB Type-C and Power Delivery memorization in Standby mode.

Note:
This function must be called just before entering Standby mode.
Reference Manual to LL API cross reference:
CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
Return values:
None

Definition at line 440 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_EnableWakeUpPin
CR3 EWUP2 LL_PWR_EnableWakeUpPin
CR3 EWUP3 LL_PWR_EnableWakeUpPin
CR3 EWUP4 LL_PWR_EnableWakeUpPin
CR3 EWUP5 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 834 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode ( void )

Switch from run main mode to run low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnterLowPowerRunMode
Return values:
None

Definition at line 295 of file stm32g4xx_ll_pwr.h.

References LL_PWR_EnableLowPowerRunMode().

__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode ( void )

Switch from run main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_ExitLowPowerRunMode
Return values:
None

Definition at line 305 of file stm32g4xx_ll_pwr.h.

References LL_PWR_DisableLowPowerRunMode().

__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor ( void )

Get the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_GetBattChargResistor
Return values:
Returned value can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K

Definition at line 902 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN

Definition at line 428 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 685 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling ( void )

Get the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_GetRegulVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2

Definition at line 330 of file stm32g4xx_ll_pwr.h.

Referenced by LL_SetFlashLatency().

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging ( void )

Check if battery charging is enabled.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_IsEnabledBatteryCharging
Return values:
State of bit (1 or 0).

Definition at line 932 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 395 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-down state is enabled.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1256 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-up state is enabled.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F
  • LL_PWR_GPIO_G
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1127 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU ( void )

Check if Internal Wake-up line is enabled.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_IsEnabledInternWU
Return values:
State of bit (1 or 0).

Definition at line 748 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode ( void )

Check if the regulator is in low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
Return values:
State of bit (1 or 0).

Definition at line 281 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg ( void )

Check if pull-up and pull-down configuration is enabled.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_IsEnabledPUPDCfg
Return values:
State of bit (1 or 0).

Definition at line 778 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 715 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM ( uint32_t PeriphVoltage )

Check if Power Voltage Monitoring is enabled on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_IsEnabledPVM
CR2 PVME2 LL_PWR_IsEnabledPVM
CR2 PVME3 LL_PWR_IsEnabledPVM
CR2 PVME4 LL_PWR_IsEnabledPVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDA_COMP (*)
  • LL_PWR_PVM_VDDA_FASTDAC (*)
  • LL_PWR_PVM_VDDA_ADC
  • LL_PWR_PVM_VDDA_OPAMP_DAC
(*) value not defined in all devices
Return values:
State of bit (1 or 0).

Definition at line 644 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode ( void )

Check if the main regulator voltage range 1 boost mode is enabled.

Reference Manual to LL API cross reference:
CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
Return values:
Inverted state of bit (0 or 1).

Definition at line 361 of file stm32g4xx_ll_pwr.h.

Referenced by LL_SetFlashLatency().

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention ( void )

Check if SRAM2 content retention in Standby mode is enabled.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_IsEnabledSRAM2Retention
Return values:
State of bit (1 or 0).

Definition at line 811 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery ( void )

Check the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.

Note:
After exiting reset, the USB Type-C dead battery behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable).
Reference Manual to LL API cross reference:
CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
Return values:
State of feature (1 : enabled; 0 : disabled).

Definition at line 511 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode ( void )

Check the USB Type-C and Power Delivery Standby mode memorization state.

Reference Manual to LL API cross reference:
CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
Return values:
State of bit (1 or 0).

Definition at line 462 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
State of bit (1 or 0).

Definition at line 874 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Get the Wake-Up pin polarity for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
State of bit (1 or 0).

Definition at line 995 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBattChargResistor ( uint32_t Resistor )

Set the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_SetBattChargResistor
Parameters:
Resistor This parameter can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K
Return values:
None

Definition at line 890 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t LowPowerMode )

Set Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_SetPowerMode
Parameters:
LowPowerMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN
Return values:
None

Definition at line 414 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 667 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling ( uint32_t VoltageScaling )

Set the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_SetRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
Return values:
None

Definition at line 318 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity high for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 975 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity low for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 955 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO4 (void)
Indicate whether VDDA voltage is below or above PVM4 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO2 (void)
Indicate whether VDDIO2 voltage is below or above PVM2 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SB ( void )

Clear Stand-By Flag.

Reference Manual to LL API cross reference:
SCR CSBF LL_PWR_ClearFlag_SB
Return values:
None

Definition at line 1367 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
SCR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 1377 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU1 ( void )

Clear Wake-up Flag 1.

Reference Manual to LL API cross reference:
SCR CWUF1 LL_PWR_ClearFlag_WU1
Return values:
None

Definition at line 1427 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU2 ( void )

Clear Wake-up Flag 2.

Reference Manual to LL API cross reference:
SCR CWUF2 LL_PWR_ClearFlag_WU2
Return values:
None

Definition at line 1417 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU3 ( void )

Clear Wake-up Flag 3.

Reference Manual to LL API cross reference:
SCR CWUF3 LL_PWR_ClearFlag_WU3
Return values:
None

Definition at line 1407 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU4 ( void )

Clear Wake-up Flag 4.

Reference Manual to LL API cross reference:
SCR CWUF4 LL_PWR_ClearFlag_WU4
Return values:
None

Definition at line 1397 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU5 ( void )

Clear Wake-up Flag 5.

Reference Manual to LL API cross reference:
SCR CWUF5 LL_PWR_ClearFlag_WU5
Return values:
None

Definition at line 1387 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU ( void )

Get Internal Wake-up line Flag.

Reference Manual to LL API cross reference:
SR1 WUFI LL_PWR_IsActiveFlag_InternWU
Return values:
State of bit (1 or 0).

Definition at line 1274 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below or above the selected PVD threshold.

Reference Manual to LL API cross reference:
SR2 PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 1497 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1 ( void )

Indicate whether VDDUSB voltage is below or above PVM1 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
Return values:
State of bit (1 or 0).

Definition at line 1482 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2 ( void )

Indicate whether VDDIO2 voltage is below or above PVM2 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
Return values:
State of bit (1 or 0).

Definition at line 1466 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3 ( void )

Indicate whether VDDA voltage is below or above PVM3 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
Return values:
State of bit (1 or 0).

Definition at line 1451 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4 ( void )

Indicate whether VDDA voltage is below or above PVM4 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
Return values:
State of bit (1 or 0).

Definition at line 1437 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF ( void )

Indicate whether the regulator is ready in main mode or is in low-power mode.

Note:
: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
Reference Manual to LL API cross reference:
SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
Return values:
State of bit (1 or 0).

Definition at line 1526 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS ( void )

Indicate whether or not the low-power regulator is ready.

Reference Manual to LL API cross reference:
SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
Return values:
State of bit (1 or 0).

Definition at line 1540 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB ( void )

Get Stand-By Flag.

Reference Manual to LL API cross reference:
SR1 SBF LL_PWR_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 1288 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS ( void )

Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.

Reference Manual to LL API cross reference:
SR2 VOSF LL_PWR_IsActiveFlag_VOS
Return values:
State of bit (1 or 0).

Definition at line 1511 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1 ( void )

Get Wake-up Flag 1.

Reference Manual to LL API cross reference:
SR1 WUF1 LL_PWR_IsActiveFlag_WU1
Return values:
State of bit (1 or 0).

Definition at line 1354 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2 ( void )

Get Wake-up Flag 2.

Reference Manual to LL API cross reference:
SR1 WUF2 LL_PWR_IsActiveFlag_WU2
Return values:
State of bit (1 or 0).

Definition at line 1341 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3 ( void )

Get Wake-up Flag 3.

Reference Manual to LL API cross reference:
SR1 WUF3 LL_PWR_IsActiveFlag_WU3
Return values:
State of bit (1 or 0).

Definition at line 1328 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4 ( void )

Get Wake-up Flag 4.

Reference Manual to LL API cross reference:
SR1 WUF4 LL_PWR_IsActiveFlag_WU4
Return values:
State of bit (1 or 0).

Definition at line 1315 of file stm32g4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5 ( void )

Get Wake-up Flag 5.

Reference Manual to LL API cross reference:
SR1 WUF5 LL_PWR_IsActiveFlag_WU5
Return values:
State of bit (1 or 0).

Definition at line 1302 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: De-initialization function

Functions
De-initialization function
PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 55 of file stm32g4xx_ll_pwr.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_PWR, and LL_APB1_GRP1_ReleaseReset().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Legacy functions name

Defines
Legacy functions name
PWR Exported Functions

Defines

#define | LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
#define | LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
#define | LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
#define | LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
#define | LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
#define | LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
#define | LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
#define | LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
#define | LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
#define | LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
#define | LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode

Define Documentation

#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery

Definition at line 1573 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode

Definition at line 1577 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery

Definition at line 1570 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode

Definition at line 1576 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery

Definition at line 1572 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode

Definition at line 1575 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery

Definition at line 1569 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode

Definition at line 1574 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS

Definition at line 1568 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery

Definition at line 1571 of file stm32g4xx_ll_pwr.h.

#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode

Definition at line 1578 of file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

static uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
static uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
static uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
static uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
static uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
static uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock frequency used for ADC domain.
static uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock frequency used for 48 MHz domain.

Function Documentation

static uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency ) [static]

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 1038 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency ) [static]

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1049 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency ) [static]

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1060 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_GetSystemClockFreq ( void ) [static]

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 1006 of file stm32g4xx_ll_rcc.c.

References HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_48M ( void ) [static]

Return PLL clock frequency used for 48 MHz domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1132 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetUSBClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_ADC ( void ) [static]

Return PLL clock frequency used for ADC domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1101 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetADCClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_SYS ( void ) [static]

Return PLL clock frequency used for system domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1070 of file stm32g4xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by RCC_GetSystemClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | RCC_OFFSET_CCIPR 0U
#define | RCC_OFFSET_CCIPR2 0x14U

Define Documentation

#define RCC_OFFSET_CCIPR 0U

Definition at line 53 of file stm32g4xx_ll_rcc.h.

#define RCC_OFFSET_CCIPR2 0x14U

Definition at line 54 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
#define | IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))

Definition at line 78 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_FDCAN_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))

Definition at line 86 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetFDCANClockFreq().

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))

Definition at line 60 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_I2S_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)

Definition at line 68 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetI2SClockFreq().

#define IS_LL_RCC_LPTIM_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))

Definition at line 64 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define IS_LL_RCC_LPUART_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))

Definition at line 51 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define IS_LL_RCC_RNG_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))

Definition at line 70 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetRNGClockFreq().

#define IS_LL_RCC_SAI_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)

Definition at line 66 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetSAIClockFreq().

#define IS_LL_RCC_UART_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)

Definition at line 48 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetUARTClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))

Definition at line 41 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 72 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32g4xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 83 of file stm32g4xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

HCLK clock frequency

Definition at line 86 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 87 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

PCLK2 clock frequency

Definition at line 88 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 85 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rcc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oscillator Values adaptation

Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CICR_CSSC RCC_CICR_CSSC

Clock Security System Interrupt Clear

Definition at line 150 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 146 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC

HSI48 Ready Interrupt Clear

Definition at line 148 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 145 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC

LSE Clock Security System Interrupt Clear

Definition at line 149 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 144 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC

LSI Ready Interrupt Clear

Definition at line 143 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 147 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 166 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 162 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 164 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 161 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 165 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 160 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 159 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 163 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

BOR reset flag

Definition at line 173 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 171 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 167 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF

OBL reset flag

Definition at line 168 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 169 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 170 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 172 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 185 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE

HSI48 Ready Interrupt Enable

Definition at line 187 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 184 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

LSE CSS Interrupt Enable

Definition at line 188 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 183 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE

LSI Ready Interrupt Enable

Definition at line 182 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 186 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 199 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW 0x00000000U

Xtal mode lower driving capability

Definition at line 196 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

Xtal mode medium high driving capability

Definition at line 198 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

Xtal mode medium low driving capability

Definition at line 197 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSCO Selection

Defines
LSCO Selection
RCC Exported Constants

Defines

#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock

Definition at line 208 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U

LSI selection for low speed clock

Definition at line 207 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 217 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 216 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 218 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 227 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 226 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), and RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 228 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 236 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 242 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 240 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 237 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 243 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 238 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 244 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 241 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 239 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 252 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 256 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 253 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 254 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 255 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: APB high-speed prescaler (APB2)

Defines
APB high-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

Define Documentation

#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1

HCLK not divided

Definition at line 264 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

HCLK divided by 16

Definition at line 268 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2

HCLK divided by 2

Definition at line 265 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4

HCLK divided by 4

Definition at line 266 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8

HCLK divided by 8

Definition at line 267 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 279 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI16 selection as MCO1 source

Definition at line 278 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3

HSI48 selection as MCO1 source

Definition at line 283 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 282 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 281 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO output disabled, no clock on MCO

Definition at line 276 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

Main PLL selection as MCO1 source

Definition at line 280 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 277 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO1 prescaler

Defines
MCO1 prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
#define | LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16

Define Documentation

#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1

MCO not divided

Definition at line 291 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16

MCO divided by 16

Definition at line 295 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2

MCO divided by 2

Definition at line 292 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4

MCO divided by 4

Definition at line 293 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8

MCO divided by 8

Definition at line 294 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 305 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSBClockFreq().

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 304 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral USART clock source selection

Defines
Peripheral USART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)

Define Documentation

#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)

HSI clock used as USART1 clock source

Definition at line 316 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)

LSE clock used as USART1 clock source

Definition at line 317 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U)

PCLK2 clock used as USART1 clock source

Definition at line 314 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)

SYSCLK clock used as USART1 clock source

Definition at line 315 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)

HSI clock used as USART2 clock source

Definition at line 320 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)

LSE clock used as USART2 clock source

Definition at line 321 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U)

PCLK1 clock used as USART2 clock source

Definition at line 318 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)

SYSCLK clock used as USART2 clock source

Definition at line 319 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)

HSI clock used as USART3 clock source

Definition at line 324 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)

LSE clock used as USART3 clock source

Definition at line 325 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U)

PCLK1 clock used as USART3 clock source

Definition at line 322 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)

SYSCLK clock used as USART3 clock source

Definition at line 323 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral UART clock source selection

Defines
Peripheral UART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U)
#define | LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)
#define | LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)
#define | LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)

Define Documentation

#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)

HSI clock used as UART4 clock source

Definition at line 336 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)

LSE clock used as UART4 clock source

Definition at line 337 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U)

PCLK1 clock used as UART4 clock source

Definition at line 334 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)

SYSCLK clock used as UART4 clock source

Definition at line 335 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral LPUART clock source selection

Defines
Peripheral LPUART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

HSI clock used as LPUART1 clock source

Definition at line 354 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

LSE clock used as LPUART1 clock source

Definition at line 355 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U

PCLK1 clock used as LPUART1 clock source

Definition at line 352 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

SYSCLK clock used as LPUART1 clock source

Definition at line 353 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral I2C clock source selection

Defines
Peripheral I2C clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U))
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))

HSI clock used as I2C1 clock source

Definition at line 365 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U))

PCLK1 clock used as I2C1 clock source

Definition at line 363 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))

SYSCLK clock used as I2C1 clock source

Definition at line 364 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))

HSI clock used as I2C2 clock source

Definition at line 368 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U))

PCLK1 clock used as I2C2 clock source

Definition at line 366 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))

SYSCLK clock used as I2C2 clock source

Definition at line 367 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))

HSI clock used as I2C3 clock source

Definition at line 371 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U))

PCLK1 clock used as I2C3 clock source

Definition at line 369 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))

SYSCLK clock used as I2C3 clock source

Definition at line 370 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral LPTIM clock source selection

Defines
Peripheral LPTIM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1

HSI clock used as LPTIM1 clock source

Definition at line 386 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

LSE clock used as LPTIM1 clock source

Definition at line 387 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0

LSI clock used as LPTIM1 clock source

Definition at line 385 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U

PCLK1 clock used as LPTIM1 clock source

Definition at line 384 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral SAI clock source selection

Defines
Peripheral SAI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1
#define | LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1)

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1)

HSI clock used as SAI1 clock source

Definition at line 398 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1

EXT clock used as SAI1 clock source

Definition at line 397 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0

PLL clock used as SAI1 clock source

Definition at line 396 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U

System clock used as SAI1 clock source

Definition at line 395 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral I2S clock source selection

Defines
Peripheral I2S clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
#define | LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1
#define | LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1)

Define Documentation

#define LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1)

HSI clock used as I2S clock source

Definition at line 409 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1

EXT clock used as I2S clock source

Definition at line 408 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0

PLL clock used as I2S clock source

Definition at line 407 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U

System clock used as I2S clock source

Definition at line 406 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral FDCAN clock source selection

Defines
Peripheral FDCAN clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U
#define | LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
#define | LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1

Define Documentation

#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U

HSE clock used as FDCAN clock source

Definition at line 418 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1

PCLK1 clock used as FDCAN clock source

Definition at line 420 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0

PLL clock used as FDCAN clock source

Definition at line 419 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral RNG clock source selection

Defines
Peripheral RNG clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Define Documentation

#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as RNG clock source

Definition at line 429 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

PLL clock used as RNG clock source

Definition at line 430 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Define Documentation

#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as USB clock source

Definition at line 438 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

PLL clock used as USB clock source

Definition at line 439 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC12_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U))
#define | LL_RCC_ADC12_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos))
#define | LL_RCC_ADC12_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos))

Define Documentation

#define LL_RCC_ADC12_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U))

No clock used as ADC12 clock source

Definition at line 447 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC12_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos))

PLL clock used as ADC12 clock source

Definition at line 448 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC12_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos))

SYSCLK clock used as ADC12 clock source

Definition at line 449 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral QUADSPI get clock source

Defines
Peripheral QUADSPI get clock source
RCC Exported Constants

Defines

#define | LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
#define | LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
#define | LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL

Define Documentation

#define LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL

QuadSPI Clock source selection

Definition at line 579 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0

HSI used as QuadSPI clock source

Definition at line 463 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1

PLL used as QuadSPI clock source

Definition at line 464 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U

SYSCLK used as QuadSPI clock source

Definition at line 462 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral USART get clock source

Defines
Peripheral USART get clock source
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

Define Documentation

#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL

USART1 Clock source selection

Definition at line 473 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL

USART2 Clock source selection

Definition at line 474 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

USART3 Clock source selection

Definition at line 475 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral UART get clock source

Defines
Peripheral UART get clock source
RCC Exported Constants

Defines

#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL

Define Documentation

#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL

UART4 Clock source selection

Definition at line 484 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq(), and LL_USART_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral LPUART get clock source

Defines
Peripheral LPUART get clock source
RCC Exported Constants

Defines

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

LPUART1 Clock source selection

Definition at line 496 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPUART_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral I2C get clock source

Defines
Peripheral I2C get clock source
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos))

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos))

I2C1 Clock source selection

Definition at line 504 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos))

I2C2 Clock source selection

Definition at line 505 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos))

I2C3 Clock source selection

Definition at line 506 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral LPTIM get clock source

Defines
Peripheral LPTIM get clock source
RCC Exported Constants

Defines

#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL

LPTIM1 Clock source selection

Definition at line 517 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral SAI get clock source

Defines
Peripheral SAI get clock source
RCC Exported Constants

Defines

#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL

SAI1 Clock source selection

Definition at line 525 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral I2S get clock source

Defines
Peripheral I2S get clock source
RCC Exported Constants

Defines

#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL

Define Documentation

#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL

I2S Clock source selection

Definition at line 533 of file stm32g4xx_ll_rcc.h.

Referenced by LL_I2S_Init(), and LL_RCC_GetI2SClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral FDCAN get clock source

Defines
Peripheral FDCAN get clock source
RCC Exported Constants

Defines

#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL

Define Documentation

#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL

FDCAN Clock source selection

Definition at line 542 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral RNG get clock source

Defines
Peripheral RNG get clock source
RCC Exported Constants

Defines

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL

RNG Clock source selection

Definition at line 552 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral USB get clock source

Defines
Peripheral USB get clock source
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL

USB Clock source selection

Definition at line 560 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral ADC get clock source

Defines
Peripheral ADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_ADC12_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos))

Define Documentation

#define LL_RCC_ADC12_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos))

ADC12 Clock source selection

Definition at line 568 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 590 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 588 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 589 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 587 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL entry clock source

Defines
PLL entry clock source
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 601 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI16 clock selected as PLL entry clock source

Definition at line 600 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

#define LL_RCC_PLLSOURCE_NONE 0x00000000U

No clock

Definition at line 599 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL division factor

Defines
PLL division factor
RCC Exported Constants

Defines

#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0
#define | LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1
#define | LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2
#define | LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3
#define | LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

Define Documentation

#define LL_RCC_PLLM_DIV_1 0x00000000U

PLL division factor by 1

Definition at line 609 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 10

Definition at line 618 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)

PLL division factor by 11

Definition at line 619 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 12

Definition at line 620 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)

PLL division factor by 13

Definition at line 621 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 14

Definition at line 622 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)

PLL division factor by 15

Definition at line 623 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 16

Definition at line 624 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0

PLL division factor by 2

Definition at line 610 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1

PLL division factor by 3

Definition at line 611 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 4

Definition at line 612 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2

PLL division factor by 5

Definition at line 613 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 6

Definition at line 614 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)

PLL division factor by 7

Definition at line 615 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

PLL division factor by 8

Definition at line 616 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3

PLL division factor by 9

Definition at line 617 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL division factor (PLLR)

Defines
PLL division factor (PLLR)
RCC Exported Constants

Defines

#define | LL_RCC_PLLR_DIV_2 0x00000000U
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Define Documentation

#define LL_RCC_PLLR_DIV_2 0x00000000U

Main PLL division factor for PLLCLK (system clock) by 2

Definition at line 632 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 4

Definition at line 633 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 6

Definition at line 634 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Main PLL division factor for PLLCLK (system clock) by 8

Definition at line 635 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL division factor (PLLP)

Defines
PLL division factor (PLLP)
RCC Exported Constants

Defines

#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Define Documentation

#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 10

Definition at line 651 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 11

Definition at line 652 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)

Main PLL division factor for PLLP output by 12

Definition at line 653 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 13

Definition at line 654 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 14

Definition at line 655 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 15

Definition at line 656 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4)

Main PLL division factor for PLLP output by 16

Definition at line 657 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 17

Definition at line 658 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_PLL_GetP().

#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 18

Definition at line 659 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 19

Definition at line 660 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 2

Definition at line 643 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)

Main PLL division factor for PLLP output by 20

Definition at line 661 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 21

Definition at line 662 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 22

Definition at line 663 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 23

Definition at line 664 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)

Main PLL division factor for PLLP output by 24

Definition at line 665 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 25

Definition at line 666 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 26

Definition at line 667 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 27

Definition at line 668 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)

Main PLL division factor for PLLP output by 28

Definition at line 669 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 29

Definition at line 670 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 3

Definition at line 644 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 30

Definition at line 671 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 31

Definition at line 672 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2)

Main PLL division factor for PLLP output by 4

Definition at line 645 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 5

Definition at line 646 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)

Main PLL division factor for PLLP output by 6

Definition at line 647 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 7

Definition at line 648 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_PLL_GetP().

#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3)

Main PLL division factor for PLLP output by 8

Definition at line 649 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)

Main PLL division factor for PLLP output by 9

Definition at line 650 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL division factor (PLLQ)

Defines
PLL division factor (PLLQ)
RCC Exported Constants

Defines

#define | LL_RCC_PLLQ_DIV_2 0x00000000U
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Define Documentation

#define LL_RCC_PLLQ_DIV_2 0x00000000U

Main PLL division factor for PLLQ output by 2

Definition at line 680 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 4

Definition at line 681 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 6

Definition at line 682 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Main PLL division factor for PLLQ output by 8

Definition at line 683 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 714 of file stm32g4xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, __VALUE__)

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 707 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
Helper macro to calculate the PCLK2 frequency (ABP2)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHBPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
__AHBPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 864 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 877 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 890 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_48M_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))

Helper macro to calculate the PLLCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
__PLLN__ | Between Min_Data = 8 and Max_Data = 127
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 846 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLCLK_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))

Helper macro to calculate the PLLCLK frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
__PLLN__ | Between Min_Data = 8 and Max_Data = 127
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
Return values:
PLL clock frequency (in Hz)

Definition at line 813 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLR__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))

Helper macro to calculate the PLLCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
__PLLN__ | Between Min_Data = 8 and Max_Data = 127
__PLLR__ This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 753 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 954 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 934 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 944 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 924 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 914 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 964 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_RCC_GetFDCANClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1013 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode ( void )

Disable HSI in stop mode.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_DisableInStopMode
Return values:
None

Definition at line 993 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1003 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode ( void )

Enable HSI even in stop mode.

Note:
HSI oscillator is forced ON even in Stop mode
Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_EnableInStopMode
Return values:
None

Definition at line 983 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 1035 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0 and Max_Data = 127

Definition at line 1059 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1023 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_DeInit(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 16, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 127
Return values:
None

Definition at line 1049 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSI48

Functions
HSI48
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI48_Disable ( void )

Disable HSI48.

Reference Manual to LL API cross reference:
CRRCR HSI48ON LL_RCC_HSI48_Disable
Return values:
None

Definition at line 1087 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI48_Enable ( void )

Enable HSI48.

Reference Manual to LL API cross reference:
CRRCR HSI48ON LL_RCC_HSI48_Enable
Return values:
None

Definition at line 1077 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration ( void )

Get HSI48 Calibration value.

Reference Manual to LL API cross reference:
CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0x1FF

Definition at line 1107 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady ( void )

Check if HSI48 oscillator Ready.

Reference Manual to LL API cross reference:
CRRCR HSI48RDY LL_RCC_HSI48_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1097 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 1135 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 1155 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableCSS ( void )

Disable Clock security system on LSE.

Note:
Clock security system can be disabled only after a LSE failure detection. In that case it MUST be disabled by software.
Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_DisableCSS
Return values:
None

Definition at line 1207 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 1125 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 1145 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableCSS ( void )

Enable Clock security system on LSE.

Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_EnableCSS
Return values:
None

Definition at line 1195 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 1185 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected ( void )

Check if CSS on LSE failure Detection.

Reference Manual to LL API cross reference:
BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Return values:
State of bit (1 or 0).

Definition at line 1227 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1217 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 1171 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 1255 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 1245 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1265 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LSCO

Functions
LSCO
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSCO_Disable ( void )

Disable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Disable
Return values:
None

Definition at line 1293 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_Enable ( void )

Enable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Enable
Return values:
None

Definition at line 1283 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource ( void )

Get Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_GetSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE

Definition at line 1318 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_SetSource ( uint32_t Source )

Configure Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_SetSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE
Return values:
None

Definition at line 1306 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 1424 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 1439 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 1454 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL

Definition at line 1353 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 1373 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 1389 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 1405 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
Return values:
None

Definition at line 1340 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCOSEL LL_RCC_ConfigMCO
CFGR MCOPRE LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_HSI48
  • LL_RCC_MCO1SOURCE_PLLCLK
  • LL_RCC_MCO1SOURCE_LSI
  • LL_RCC_MCO1SOURCE_LSE
(*) value not defined in all devices.
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2
  • LL_RCC_MCO1_DIV_4
  • LL_RCC_MCO1_DIV_8
  • LL_RCC_MCO1_DIV_16
Return values:
None

Definition at line 1490 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetUARTClockSource (uint32_t UARTxSource)
Configure UARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetI2SClockSource (uint32_t I2SxSource)
Configure I2S clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t FDCANxSource)
Configure FDCAN clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUARTClockSource (uint32_t UARTx)
Get UARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2SClockSource (uint32_t I2Sx)
Get I2Sx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t FDCANx)
Get FDCANx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC12_CLKSOURCE
  • LL_RCC_ADC345_CLKSOURCE (*)
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC12_CLKSOURCE_NONE
  • LL_RCC_ADC12_CLKSOURCE_PLL
  • LL_RCC_ADC12_CLKSOURCE_SYSCLK
  • LL_RCC_ADC345_CLKSOURCE_NONE (*)
  • LL_RCC_ADC345_CLKSOURCE_PLL (*)
  • LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
(*) value not defined in all devices.

Definition at line 1928 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource ( uint32_t FDCANx )

Get FDCANx clock source.

Reference Manual to LL API cross reference:
CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
Parameters:
FDCANx This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_HSE
  • LL_RCC_FDCAN_CLKSOURCE_PLL
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1
None

Definition at line 1878 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t I2Cx )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_GetI2CClockSource
Parameters:
I2Cx This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE
  • LL_RCC_I2C3_CLKSOURCE
  • LL_RCC_I2C4_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK
  • LL_RCC_I2C2_CLKSOURCE_HSI
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
  • LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C4_CLKSOURCE_HSI (*)
(*) value not defined in all devices.

Definition at line 1808 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource ( uint32_t I2Sx )

Get I2Sx clock source.

Reference Manual to LL API cross reference:
CCIPR I2S23SEL LL_RCC_GetI2SClockSource
Parameters:
I2Sx This parameter can be one of the following values:
  • LL_RCC_I2S_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2S_CLKSOURCE_SYSCLK
  • LL_RCC_I2S_CLKSOURCE_PLL
  • LL_RCC_I2S_CLKSOURCE_PIN
  • LL_RCC_I2S_CLKSOURCE_HSI

Definition at line 1861 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource ( uint32_t LPTIMx )

Get LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
Parameters:
LPTIMx This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE

Definition at line 1825 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource ( uint32_t LPUARTx )

Get LPUARTx clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Parameters:
LPUARTx This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE

Definition at line 1777 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource ( uint32_t RNGx )

Get RNGx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetRNGClockSource
Parameters:
RNGx This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_HSI48
  • LL_RCC_RNG_CLKSOURCE_PLL

Definition at line 1893 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource ( uint32_t SAIx )

Get SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAI1SEL LL_RCC_GetSAIClockSource
Parameters:
SAIx This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_SYSCLK
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_PIN
  • LL_RCC_SAI1_CLKSOURCE_HSI
(*) value not defined in all devices.

Definition at line 1845 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource ( uint32_t UARTx )

Get UARTx clock source.

Reference Manual to LL API cross reference:
CCIPR UARTxSEL LL_RCC_GetUARTClockSource
Parameters:
UARTx This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE (*)
  • LL_RCC_UART5_CLKSOURCE (*)
Return values:
Returned value can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
  • LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
  • LL_RCC_UART4_CLKSOURCE_HSI (*)
  • LL_RCC_UART4_CLKSOURCE_LSE (*)
  • LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
  • LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
  • LL_RCC_UART5_CLKSOURCE_HSI (*)
  • LL_RCC_UART5_CLKSOURCE_LSE (*)
(*) value not defined in all devices.

Definition at line 1760 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t USARTx )

Get USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
Parameters:
USARTx This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1
  • LL_RCC_USART3_CLKSOURCE_SYSCLK
  • LL_RCC_USART3_CLKSOURCE_HSI
  • LL_RCC_USART3_CLKSOURCE_LSE

Definition at line 1736 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLL

Definition at line 1907 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CCIPR ADC12SEL LL_RCC_SetADCClockSource
CCIPR ADC345SEL LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC12_CLKSOURCE_NONE
  • LL_RCC_ADC12_CLKSOURCE_PLL
  • LL_RCC_ADC12_CLKSOURCE_SYSCLK
  • LL_RCC_ADC345_CLKSOURCE_NONE (*)
  • LL_RCC_ADC345_CLKSOURCE_PLL (*)
  • LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1694 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetFDCANClockSource ( uint32_t FDCANxSource )

Configure FDCAN clock source.

Reference Manual to LL API cross reference:
CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
Parameters:
FDCANxSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_HSE
  • LL_RCC_FDCAN_CLKSOURCE_PLL
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1
Return values:
None

Definition at line 1647 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t I2CxSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_SetI2CClockSource
Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK
  • LL_RCC_I2C2_CLKSOURCE_HSI
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI
  • LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
  • LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C4_CLKSOURCE_HSI (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1584 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2SClockSource ( uint32_t I2SxSource )

Configure I2S clock source.

Reference Manual to LL API cross reference:
CCIPR I2S23SEL LL_RCC_SetI2SClockSource
Parameters:
I2SxSource This parameter can be one of the following values:
  • LL_RCC_I2S_CLKSOURCE_SYSCLK
  • LL_RCC_I2S_CLKSOURCE_PLL
  • LL_RCC_I2S_CLKSOURCE_PIN
  • LL_RCC_I2S_CLKSOURCE_HSI
Return values:
None

Definition at line 1632 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetLPTIMClockSource ( uint32_t LPTIMxSource )

Configure LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
Return values:
None

Definition at line 1600 of file stm32g4xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_RCC_SetLPUARTClockSource ( uint32_t LPUARTxSource )

Configure LPUART1x clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
Return values:
None

Definition at line 1559 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockSource ( uint32_t RNGxSource )

Configure RNG clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetRNGClockSource
Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_HSI48
  • LL_RCC_RNG_CLKSOURCE_PLL
Return values:
None

Definition at line 1661 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSAIClockSource ( uint32_t SAIxSource )

Configure SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAI1SEL LL_RCC_SetSAIClockSource
Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_SYSCLK
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_PIN
  • LL_RCC_SAI1_CLKSOURCE_HSI
(*) value not defined in all devices.
Return values:
None

Definition at line 1617 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUARTClockSource ( uint32_t UARTxSource )

Configure UARTx clock source.

Reference Manual to LL API cross reference:
CCIPR UARTxSEL LL_RCC_SetUARTClockSource
Parameters:
UARTxSource This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
  • LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
  • LL_RCC_UART4_CLKSOURCE_HSI (*)
  • LL_RCC_UART4_CLKSOURCE_LSE (*)
  • LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
  • LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
  • LL_RCC_UART5_CLKSOURCE_HSI (*)
  • LL_RCC_UART5_CLKSOURCE_LSE (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1543 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t USARTxSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1
  • LL_RCC_USART3_CLKSOURCE_SYSCLK
  • LL_RCC_USART3_CLKSOURCE_HSI
  • LL_RCC_USART3_CLKSOURCE_LSE
Return values:
None

Definition at line 1521 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLL
Return values:
None

Definition at line 1674 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 2004 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 1994 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 2024 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Definition at line 1984 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 2014 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 2034 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Return values:
None

Definition at line 1970 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_ADC (void)
Check if PLL output mapped on ADC domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_48M (void)
Check if PLL output mapped on 48MHz domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_SYS (void)
Check if PLL output mapped on SYSCLK domain clock is enabled.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, is disabled.
PLLN/PLLQ can be written only when PLL is disabled.
This can be selected for USB, RNG
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
PLLN Between Min_Data = 8 and Max_Data = 127
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2232 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled.
PLLN/PLLP can be written only when PLL is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
PLLN Between Min_Data = 8 and Max_Data = 127
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
Return values:
None

Definition at line 2187 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLL used for SYSCLK Domain.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled.
PLLN/PLLR can be written only when PLL is disabled.
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16
PLLN Between Min_Data = 8 and Max_Data = 127
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8
Return values:
None

Definition at line 2117 of file stm32g4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 2064 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M ( void )

Disable PLL output mapped on 48MHz domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
Return values:
None

Definition at line 2426 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC ( void )

Disable PLL output mapped on ADC domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
Return values:
None

Definition at line 2392 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS ( void )

Disable PLL output mapped on SYSCLK domain.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Return values:
None

Definition at line 2460 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 2053 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M ( void )

Enable PLL output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
Return values:
None

Definition at line 2412 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC ( void )

Enable PLL output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
Return values:
None

Definition at line 2378 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS ( void )

Enable PLL output mapped on SYSCLK domain.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Return values:
None

Definition at line 2446 of file stm32g4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider ( void )

Get Division factor for the main PLL and other PLL.

Reference Manual to LL API cross reference:
PLLCFGR PLLM LL_RCC_PLL_GetDivider
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
  • LL_RCC_PLLM_DIV_9
  • LL_RCC_PLLM_DIV_10
  • LL_RCC_PLLM_DIV_11
  • LL_RCC_PLLM_DIV_12
  • LL_RCC_PLLM_DIV_13
  • LL_RCC_PLLM_DIV_14
  • LL_RCC_PLLM_DIV_15
  • LL_RCC_PLLM_DIV_16

Definition at line 2368 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE

Definition at line 2260 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN ( void )

Get Main PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLCFGR PLLN LL_RCC_PLL_GetN
Return values:
Between Min_Data = 8 and Max_Data = 127

Definition at line 2270 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP ( void )

Get Main PLL division factor for PLLP.

Note:
Used for PLLADCCLK (ADC clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLPDIV LL_RCC_PLL_GetP
Reference Manual to LL API cross reference:
PLLCFGR PLLP LL_RCC_PLL_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31

Definition at line 2312 of file stm32g4xx_ll_rcc.h.

References LL_RCC_PLLP_DIV_17, and LL_RCC_PLLP_DIV_7.

Referenced by RCC_PLL_GetFreqDomain_ADC().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ ( void )

Get Main PLL division factor for PLLQ.

Note:
Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLQ LL_RCC_PLL_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8

Definition at line 2327 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR ( void )

Get Main PLL division factor for PLLR.

Note:
Used for PLLCLK (system clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLR LL_RCC_PLL_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8

Definition at line 2342 of file stm32g4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M ( void )

Check if PLL output mapped on 48MHz domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
Return values:
State of bit (1 or 0).

Definition at line 2436 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetUSBClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC ( void )

Check if PLL output mapped on ADC domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
Return values:
State of bit (1 or 0).

Definition at line 2402 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS ( void )

Check if PLL output mapped on SYSCLK domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
Return values:
State of bit (1 or 0).

Definition at line 2470 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2074 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

__STATIC_INLINE void LL_RCC_PLL_SetMainSource ( uint32_t PLLSource )

Configure PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
Parameters:
PLLSource This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
Return values:
None

Definition at line 2247 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 2548 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 2518 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY ( void )

Clear HSI48 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Return values:
None

Definition at line 2538 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 2508 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS ( void )

Clear LSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Return values:
None

Definition at line 2558 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 2498 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 2488 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 2528 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 2718 of file stm32g4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST ( void )

Check if RCC flag BOR reset is set or not.

Reference Manual to LL API cross reference:
CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Return values:
State of bit (1 or 0).

Definition at line 2708 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 2628 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 2598 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY ( void )

Check if HSI48 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 2618 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2588 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 2648 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 2658 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS ( void )

Check if LSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 2638 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 2578 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2568 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST ( void )

Check if RCC flag Option byte reset is set or not.

Reference Manual to LL API cross reference:
CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Return values:
State of bit (1 or 0).

Definition at line 2668 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 2678 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 2608 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 2688 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 2698 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 2836 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY ( void )

Disable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Return values:
None

Definition at line 2856 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 2826 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSECSS ( void )

Disable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Return values:
None

Definition at line 2866 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 2816 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 2806 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 2846 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 2766 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY ( void )

Enable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Return values:
None

Definition at line 2786 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 2756 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSECSS ( void )

Enable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Return values:
None

Definition at line 2796 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 2746 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 2736 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 2776 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 2906 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY ( void )

Checks if HSI48 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 2926 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2896 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS ( void )

Checks if LSECSS interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 2936 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 2886 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2876 of file stm32g4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 2916 of file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 133 of file stm32g4xx_ll_rcc.c.

References LL_RCC_ClearResetFlags(), LL_RCC_GetSysClkSource(), LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_HSI_SetCalibTrimming(), LL_RCC_PLL_IsReady(), LL_RCC_SYS_CLKSOURCE_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, and LL_RCC_WriteReg.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN kernel clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) or HSI_VALUE(**) multiplied/divided by the PLL factors.
(**) HSI_VALUE is a constant defined in this file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in this file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC12_CLKSOURCE
  • LL_RCC_ADC345_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
ADC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 879 of file stm32g4xx_ll_rcc.c.

References assert_param, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_ADC12_CLKSOURCE, LL_RCC_ADC12_CLKSOURCE_NONE, LL_RCC_ADC12_CLKSOURCE_PLL, LL_RCC_ADC12_CLKSOURCE_SYSCLK, LL_RCC_GetADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_ADC(), LL_RCC_PLL_IsReady(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_ADC().

uint32_t LL_RCC_GetFDCANClockFreq ( uint32_t FDCANxSource )

Return FDCAN kernel clock frequency.

Parameters:
FDCANxSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
FDCAN kernel clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 742 of file stm32g4xx_ll_rcc.c.

References assert_param, HSE_VALUE, IS_LL_RCC_FDCAN_CLKSOURCE, LL_RCC_FDCAN_CLKSOURCE_HSE, LL_RCC_FDCAN_CLKSOURCE_PCLK1, LL_RCC_FDCAN_CLKSOURCE_PLL, LL_RCC_GetFDCANClockSource(), LL_RCC_HSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_48M(), LL_RCC_PLL_IsReady(), RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_48M().

uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE
  • LL_RCC_I2C3_CLKSOURCE
  • LL_RCC_I2C4_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready

Definition at line 429 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_GetI2CClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_PCLK1, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C2_CLKSOURCE, LL_RCC_I2C2_CLKSOURCE_HSI, LL_RCC_I2C2_CLKSOURCE_PCLK1, LL_RCC_I2C2_CLKSOURCE_SYSCLK, LL_RCC_I2C3_CLKSOURCE, LL_RCC_I2C3_CLKSOURCE_HSI, LL_RCC_I2C3_CLKSOURCE_PCLK1, LL_RCC_I2C3_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetI2SClockFreq ( uint32_t I2SxSource )

Return I2Sx clock frequency.

Parameters:
I2SxSource This parameter can be one of the following values:
  • LL_RCC_I2S_CLKSOURCE
Return values:
I2S clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 690 of file stm32g4xx_ll_rcc.c.

References assert_param, EXTERNAL_CLOCK_VALUE, HSI_VALUE, IS_LL_RCC_I2S_CLKSOURCE, LL_RCC_GetI2SClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2S_CLKSOURCE, LL_RCC_I2S_CLKSOURCE_HSI, LL_RCC_I2S_CLKSOURCE_PIN, LL_RCC_I2S_CLKSOURCE_PLL, LL_RCC_I2S_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_48M(), LL_RCC_PLL_IsReady(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_48M().

Referenced by LL_I2S_Init().

uint32_t LL_RCC_GetLPTIMClockFreq ( uint32_t LPTIMxSource )

Return LPTIMx clock frequency.

Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
Return values:
LPTIM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready

Definition at line 588 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPTIM_CLKSOURCE, LL_RCC_GetLPTIMClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_HSI, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, LSI_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPUARTClockFreq ( uint32_t LPUARTxSource )

Return LPUARTx clock frequency.

Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
LPUART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 544 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPUART_CLKSOURCE, LL_RCC_GetLPUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_PCLK1, LL_RCC_LPUART1_CLKSOURCE_SYSCLK, LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_LPUART_Init().

uint32_t LL_RCC_GetRNGClockFreq ( uint32_t RNGxSource )

Return RNGx clock frequency.

Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
RNG clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 789 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI48_VALUE, IS_LL_RCC_RNG_CLKSOURCE, LL_RCC_GetRNGClockSource(), LL_RCC_HSI48_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_48M(), LL_RCC_PLL_IsReady(), LL_RCC_RNG_CLKSOURCE_HSI48, LL_RCC_RNG_CLKSOURCE_PLL, and RCC_PLL_GetFreqDomain_48M().

uint32_t LL_RCC_GetSAIClockFreq ( uint32_t SAIxSource )

Return SAIx clock frequency.

Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
Return values:
SAI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready

Definition at line 639 of file stm32g4xx_ll_rcc.c.

References assert_param, EXTERNAL_CLOCK_VALUE, HSI_VALUE, IS_LL_RCC_SAI_CLKSOURCE, LL_RCC_GetSAIClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_48M(), LL_RCC_PLL_IsReady(), LL_RCC_SAI1_CLKSOURCE, LL_RCC_SAI1_CLKSOURCE_HSI, LL_RCC_SAI1_CLKSOURCE_PIN, LL_RCC_SAI1_CLKSOURCE_PLL, LL_RCC_SAI1_CLKSOURCE_SYSCLK, RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_48M().

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 208 of file stm32g4xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_LPTIM_Disable().

uint32_t LL_RCC_GetUARTClockFreq ( uint32_t UARTxSource )

Return UARTx clock frequency.

Parameters:
UARTxSource This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE (*)
  • LL_RCC_UART5_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
UART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 344 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_UART_CLKSOURCE, LL_RCC_GetUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_UART4_CLKSOURCE, LL_RCC_UART4_CLKSOURCE_HSI, LL_RCC_UART4_CLKSOURCE_LSE, LL_RCC_UART4_CLKSOURCE_PCLK1, LL_RCC_UART4_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 233 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_PCLK2, LL_RCC_USART1_CLKSOURCE_SYSCLK, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART2_CLKSOURCE_HSI, LL_RCC_USART2_CLKSOURCE_LSE, LL_RCC_USART2_CLKSOURCE_PCLK1, LL_RCC_USART2_CLKSOURCE_SYSCLK, LL_RCC_USART3_CLKSOURCE, LL_RCC_USART3_CLKSOURCE_HSI, LL_RCC_USART3_CLKSOURCE_LSE, LL_RCC_USART3_CLKSOURCE_PCLK1, LL_RCC_USART3_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 833 of file stm32g4xx_ll_rcc.c.

References assert_param, HSI48_VALUE, IS_LL_RCC_USB_CLKSOURCE, LL_RCC_GetUSBClockSource(), LL_RCC_HSI48_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_48M(), LL_RCC_PLL_IsReady(), LL_RCC_USB_CLKSOURCE_HSI48, LL_RCC_USB_CLKSOURCE_PLL, and RCC_PLL_GetFreqDomain_48M().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define IS_LL_RNG_CED(__MODE__)

Define Documentation

#define IS_LL_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == LL_RNG_CED_ENABLE) || \
                                 ((__MODE__) == LL_RNG_CED_DISABLE))

Definition at line 47 of file stm32g4xx_ll_rng.c.

Referenced by LL_RNG_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RNG_InitTypeDef Struct Reference
RNG Exported Init structures

LL RNG Init Structure Definition. More...

#include <stm32g4xx_ll_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

LL RNG Init Structure Definition.

Definition at line 56 of file stm32g4xx_ll_rng.h.

Field Documentation

uint32_t LL_RNG_InitTypeDef::ClockErrorDetection

Clock error detection. This parameter can be one value of Clock Error Detection. This parameter can be modified using unitary functions LL_RNG_EnableClkErrorDetect().

Definition at line 58 of file stm32g4xx_ll_rng.h.

Referenced by LL_RNG_Init(), and LL_RNG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rng.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Error Detection

Defines
Clock Error Detection
RNG Exported Constants

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define LL_RNG_CED_DISABLE RNG_CR_CED

Clock error detection disabled

Definition at line 77 of file stm32g4xx_ll_rng.h.

#define LL_RNG_CED_ENABLE 0x00000000U

Clock error detection enabled

Definition at line 76 of file stm32g4xx_ll_rng.h.

Referenced by LL_RNG_StructInit().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RNG Exported Constants

Flags defines which can be used with LL_RNG_ReadReg function. More...

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS

Detailed Description

Flags defines which can be used with LL_RNG_ReadReg function.

Define Documentation

#define LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

Definition at line 87 of file stm32g4xx_ll_rng.h.

#define LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

Definition at line 89 of file stm32g4xx_ll_rng.h.

#define LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

Definition at line 86 of file stm32g4xx_ll_rng.h.

#define LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

Definition at line 88 of file stm32g4xx_ll_rng.h.

#define LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Definition at line 90 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
RNG Exported Constants

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros. More...

Defines

#define LL_RNG_CR_IE RNG_CR_IE

Detailed Description

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Define Documentation

#define LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable

Definition at line 99 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RNG Exported Macros

Defines

#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Define Documentation

#define LL_RNG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 132 of file stm32g4xx_ll_rng.h.

#define LL_RNG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 124 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Configuration functions

Functions
RNG Configuration functions
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (const RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (const RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.

Function Documentation

__STATIC_INLINE void LL_RNG_Disable ( RNG_TypeDef * RNGx )

Disable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Disable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 167 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableClkErrorDetect ( RNG_TypeDef * RNGx )

Disable RNG Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_DisableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 200 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Enable ( RNG_TypeDef * RNGx )

Enable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Enable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 156 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableClkErrorDetect ( RNG_TypeDef * RNGx )

Enable Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_EnableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 189 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabled ( const RNG_TypeDef * RNGx )

Check if Random Number Generator is enabled.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_IsEnabled
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 178 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect ( const RNG_TypeDef * RNGx )

Check if RNG Clock Error Detection is enabled.

Reference Manual to LL API cross reference:
CR CED LL_RNG_IsEnabledClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 211 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (const RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (const RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (const RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (const RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (const RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.

Function Documentation

__STATIC_INLINE void LL_RNG_ClearFlag_CEIS ( RNG_TypeDef * RNGx )

Clear Clock Error interrupt Status (CEIS) Flag.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_ClearFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 285 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_ClearFlag_SEIS ( RNG_TypeDef * RNGx )

Clear Seed Error interrupt Status (SEIS) Flag.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_ClearFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 296 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS ( const RNG_TypeDef * RNGx )

Indicate if the Clock Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CECS LL_RNG_IsActiveFlag_CECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 241 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS ( const RNG_TypeDef * RNGx )

Indicate if the Clock Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_IsActiveFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 263 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY ( const RNG_TypeDef * RNGx )

Indicate if the RNG Data ready Flag is set or not.

Reference Manual to LL API cross reference:
SR DRDY LL_RNG_IsActiveFlag_DRDY
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 230 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS ( const RNG_TypeDef * RNGx )

Indicate if the Seed Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SECS LL_RNG_IsActiveFlag_SECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 252 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS ( const RNG_TypeDef * RNGx )

Indicate if the Seed Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_IsActiveFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 274 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Management

Functions
IT Management
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (const RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Function Documentation

__STATIC_INLINE void LL_RNG_DisableIT ( RNG_TypeDef * RNGx )

Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_DisableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 328 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableIT ( RNG_TypeDef * RNGx )

Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_EnableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 316 of file stm32g4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT ( const RNG_TypeDef * RNGx )

Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_IsEnabledIT
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 340 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Management

Functions
Data Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 (const RNG_TypeDef *RNGx)
Return32-bit Random Number value.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 ( const RNG_TypeDef * RNGx )

Return32-bit Random Number value.

Reference Manual to LL API cross reference:
DR RNDATA LL_RNG_ReadRandData32
Parameters:
RNGx RNG Instance
Return values:
Generated 32-bit random value

Definition at line 359 of file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Functions

ErrorStatus | LL_RNG_DeInit (const RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_RNG_DeInit ( const RNG_TypeDef * RNGx )

De-initialize RNG registers (Registers restored to their default values).

Parameters:
RNGx RNG Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are de-initialized
  • ERROR: not applicable

Definition at line 71 of file stm32g4xx_ll_rng.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_RNG, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_RNG_Init | ( | RNG_TypeDef * | RNGx,
 |  | LL_RNG_InitTypeDef * | RNG_InitStruct
 | ) |  |

Initialize RNG registers according to the specified parameters in RNG_InitStruct.

Parameters:
RNGx | RNG Instance
RNG_InitStruct | pointer to a LL_RNG_InitTypeDef structure that contains the configuration information for the specified RNG peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are initialized according to RNG_InitStruct content
  • ERROR: not applicable

Definition at line 102 of file stm32g4xx_ll_rng.c.

References assert_param, LL_RNG_InitTypeDef::ClockErrorDetection, and IS_LL_RNG_CED.

void LL_RNG_StructInit ( LL_RNG_InitTypeDef * RNG_InitStruct )

Set each LL_RNG_InitTypeDef field to default value.

Parameters:
RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 120 of file stm32g4xx_ll_rng.c.

References LL_RNG_InitTypeDef::ClockErrorDetection, and LL_RNG_CED_ENABLE.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
#define | RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
#define | RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF
#define | RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
#define | RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)

Definition at line 46 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */

Definition at line 50 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_LL_INIT_MASK 0xFFFFFFFFU

Definition at line 47 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_EnableInitMode().

#define RTC_LL_RSF_MASK 0xFFFFFF5FU

Definition at line 48 of file stm32g4xx_ll_rtc.h.

#define RTC_OFFSET_DAY 16U

Definition at line 57 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR 16U

Definition at line 59 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE 8U

Definition at line 60 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH 8U

Definition at line 58 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY 24U

Definition at line 56 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)

Definition at line 47 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */

Definition at line 51 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF

Definition at line 51 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA

Definition at line 52 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53

Definition at line 53 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
#define | IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 107 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 92 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 110 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 99 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FU)

Definition at line 63 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))

Definition at line 86 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                     || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 67 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 73 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 74 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                         || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 60 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 75 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __MONTH__ ) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))

Definition at line 88 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 76 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FFFU)

Definition at line 65 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                          || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 70 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                      || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 78 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 90 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32g4xx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 89 of file stm32g4xx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 97 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 91 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 103 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32g4xx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 113 of file stm32g4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 120 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 126 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 131 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 115 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32g4xx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 140 of file stm32g4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 152 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 147 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 142 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 157 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32g4xx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 166 of file stm32g4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 184 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 177 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 170 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 168 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_rtc.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U

Define Documentation

#define LL_RTC_FORMAT_BCD 0x00000001U

BCD data format

Definition at line 212 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN 0x00000000U

Binary data format

Definition at line 211 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm A Date is selected

Definition at line 220 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 221 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm B Date is selected

Definition at line 229 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 230 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_CSR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define | LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF
#define | LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF

Definition at line 246 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF

Definition at line 255 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF

Definition at line 254 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_INITF RTC_ICSR_INITF

Definition at line 249 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_INITS RTC_ICSR_INITS

Definition at line 251 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF

Definition at line 248 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_RSF RTC_ICSR_RSF

Definition at line 250 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF

Definition at line 252 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF

Definition at line 253 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF

Definition at line 245 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SCR_ITSF RTC_SCR_CITSF

Definition at line 241 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SCR_TSF RTC_SCR_CTSF

Definition at line 243 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF

Definition at line 242 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF

Definition at line 244 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 267 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 266 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 264 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 265 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
#define | LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
#define | LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
#define | LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
#define | LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
#define | LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
#define | LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05

Friday

Definition at line 279 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01

Monday

Definition at line 275 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06

Saturday

Definition at line 280 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07

Sunday

Definition at line 281 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04

Thrusday

Definition at line 278 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02

Tuesday

Definition at line 276 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03

Wednesday

Definition at line 277 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY (uint8_t)0x01
#define | LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
#define | LL_RTC_MONTH_MARCH (uint8_t)0x03
#define | LL_RTC_MONTH_APRIL (uint8_t)0x04
#define | LL_RTC_MONTH_MAY (uint8_t)0x05
#define | LL_RTC_MONTH_JUNE (uint8_t)0x06
#define | LL_RTC_MONTH_JULY (uint8_t)0x07
#define | LL_RTC_MONTH_AUGUST (uint8_t)0x08
#define | LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
#define | LL_RTC_MONTH_OCTOBER (uint8_t)0x10
#define | LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
#define | LL_RTC_MONTH_DECEMBER (uint8_t)0x12

Define Documentation

#define LL_RTC_MONTH_APRIL (uint8_t)0x04

April

Definition at line 292 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST (uint8_t)0x08

August

Definition at line 296 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12

December

Definition at line 300 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02

February

Definition at line 290 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY (uint8_t)0x01

January

Definition at line 289 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY (uint8_t)0x07

July

Definition at line 295 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE (uint8_t)0x06

June

Definition at line 294 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH (uint8_t)0x03

March

Definition at line 291 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_MAY (uint8_t)0x05

May

Definition at line 293 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11

November

Definition at line 299 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10

October

Definition at line 298 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09

September

Definition at line 297 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U

24 hour/day format

Definition at line 308 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 309 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 318 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 319 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE 0x00000000U

Output disabled

Definition at line 317 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 320 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

RTC_ALARM is open-drain output

Definition at line 328 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

RTC_ALARM is push-pull output

Definition at line 329 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 337 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 338 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U

AM or 24-hour format

Definition at line 346 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 347 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 356 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 355 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 369 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 365 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 366 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 367 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE 0x00000000U

No masks applied on Alarm A

Definition at line 364 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 368 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 377 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 378 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 391 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 387 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 388 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 389 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE 0x00000000U

No masks applied on Alarm B

Definition at line 386 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 390 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 399 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 400 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 409 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 408 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 417 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 418 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E

Tamper 1 input detection

Definition at line 426 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E

Tamper 2 input detection

Definition at line 427 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Tamper 3 input detection

Definition at line 429 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MF

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased

Definition at line 448 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MF

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 449 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF

Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 451 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 469 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 470 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 472 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 490 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 491 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 492 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 493 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 502 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 503 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 504 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 501 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 517 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 513 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 516 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 519 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 512 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 515 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 518 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 514 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG

Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 527 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG

Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 528 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 530 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: INTERNAL TAMPER

Defines
INTERNAL TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E
#define | LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E
#define | LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E
#define | LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E
#define | LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E

Define Documentation

#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E

Internal tamper 1: RTC supply voltage monitoring

Definition at line 547 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E

Internal tamper 3: LSE monitoring

Definition at line 551 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E

Internal tamper 4: HSE monitoring

Definition at line 552 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E

Internal tamper 5: RTC calendar overflow

Definition at line 553 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E

Internal tamper 6: Test mode entry

Definition at line 555 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_NUMBER RTC_BACKUP_NB
#define | LL_RTC_BKP_DR0 0x00U
#define | LL_RTC_BKP_DR1 0x01U
#define | LL_RTC_BKP_DR2 0x02U
#define | LL_RTC_BKP_DR3 0x03U
#define | LL_RTC_BKP_DR4 0x04U
#define | LL_RTC_BKP_DR5 0x05U
#define | LL_RTC_BKP_DR6 0x06U
#define | LL_RTC_BKP_DR7 0x07U
#define | LL_RTC_BKP_DR8 0x08U
#define | LL_RTC_BKP_DR9 0x09U
#define | LL_RTC_BKP_DR10 0x0AU
#define | LL_RTC_BKP_DR11 0x0BU
#define | LL_RTC_BKP_DR12 0x0CU
#define | LL_RTC_BKP_DR13 0x0DU
#define | LL_RTC_BKP_DR14 0x0EU
#define | LL_RTC_BKP_DR15 0x0FU

Define Documentation

#define LL_RTC_BKP_DR0 0x00U

Definition at line 579 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR1 0x01U

Definition at line 580 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR10 0x0AU

Definition at line 589 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR11 0x0BU

Definition at line 590 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR12 0x0CU

Definition at line 591 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR13 0x0DU

Definition at line 592 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR14 0x0EU

Definition at line 593 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR15 0x0FU

Definition at line 594 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR2 0x02U

Definition at line 581 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR3 0x03U

Definition at line 582 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR4 0x04U

Definition at line 583 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR5 0x05U

Definition at line 584 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR6 0x06U

Definition at line 585 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR7 0x07U

Definition at line 586 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR8 0x08U

Definition at line 587 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_DR9 0x09U

Definition at line 588 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB

Definition at line 571 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2

ck_spre (usually 1 Hz) clock is selected

Definition at line 643 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 644 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U

RTC/16 clock is selected

Definition at line 639 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 642 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1

RTC/4 clock is selected

Definition at line 641 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0

RTC/8 clock is selected

Definition at line 640 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 1 Hz

Definition at line 653 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Calibration output is 512 Hz

Definition at line 654 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U

Calibration output disabled

Definition at line 652 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U

No RTCCLK pulses are added

Definition at line 662 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 663 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 672 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U

Use a 32-second calibration cycle period

Definition at line 671 of file stm32g4xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 673 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 699 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 692 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 754 of file stm32g4xx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 747 of file stm32g4xx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 721 of file stm32g4xx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 728 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 769 of file stm32g4xx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 776 of file stm32g4xx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 783 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableAlarmPullUp ( RTC_TypeDef * RTCx )

Disable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1127 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 912 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisableOutput2 ( RTC_TypeDef * RTCx )

Disable RTC_OUT2 output.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_DisableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1163 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1001 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 964 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableTamperOutput ( RTC_TypeDef * RTCx )

Disable tamper output.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_DisableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1094 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1069 of file stm32g4xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableAlarmPullUp ( RTC_TypeDef * RTCx )

Enable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1116 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 900 of file stm32g4xx_ll_rtc.h.

References RTC_LL_INIT_MASK.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnableOutput2 ( RTC_TypeDef * RTCx )

Enable RTC_OUT2 output.

Note:
RTC_OUT2 mapping depends on both OSEL (LL_RTC_SetAlarmOutEvent) and COE (LL_RTC_CAL_SetOutputFreq) settings.
RTC_OUT2 is not available ins VBAT mode.
Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_EnableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1152 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 988 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 953 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableTamperOutput ( RTC_TypeDef * RTCx )

Enable tamper output.

Note:
When the tamper output is enabled, all external and internal tamper flags are ORed and routed to the TAMPALRM output.
Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_EnableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1083 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1058 of file stm32g4xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 858 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 885 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 1036 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 826 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 941 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 1047 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled ( RTC_TypeDef * RTCx )

Check if internal pull-up in output mode is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1138 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled ( RTC_TypeDef * RTCx )

Check if RTC_OUT2 output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1174 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 975 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled ( RTC_TypeDef * RTCx )

Check if tamper output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1105 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 843 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 872 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 1013 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 813 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 928 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 1025 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_Config
RTC_TR HT LL_RTC_TIME_Config
RTC_TR HU LL_RTC_TIME_Config
RTC_TR MNT LL_RTC_TIME_Config
RTC_TR MNU LL_RTC_TIME_Config
RTC_TR ST LL_RTC_TIME_Config
RTC_TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1346 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1427 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1404 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1392 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_Get
RTC_TR HU LL_RTC_TIME_Get
RTC_TR MNT LL_RTC_TIME_Get
RTC_TR MNU LL_RTC_TIME_Get
RTC_TR ST LL_RTC_TIME_Get
RTC_TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1375 of file stm32g4xx_ll_rtc.h.

References RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1215 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_GetHour
RTC_TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1250 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_GetMinute
RTC_TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1285 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_GetSecond
RTC_TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1320 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
RTC_SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1457 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1439 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1415 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1198 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_SetHour
RTC_TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1231 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_SetMinute
RTC_TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1266 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_SetSecond
RTC_TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1301 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize
RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1476 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Config
RTC_DR MT LL_RTC_DATE_Config
RTC_DR MU LL_RTC_DATE_Config
RTC_DR DT LL_RTC_DATE_Config
RTC_DR DU LL_RTC_DATE_Config
RTC_DR YT LL_RTC_DATE_Config
RTC_DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1677 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Get
RTC_DR MT LL_RTC_DATE_Get
RTC_DR MU LL_RTC_DATE_Get
RTC_DR DT LL_RTC_DATE_Get
RTC_DR DU LL_RTC_DATE_Get
RTC_DR YT LL_RTC_DATE_Get
RTC_DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1706 of file stm32g4xx_ll_rtc.h.

References RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_GetDay
RTC_DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1637 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_GetMonth
RTC_DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1607 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1553 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_GetYear
RTC_DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1514 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_SetDay
RTC_DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1621 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_SetMonth
RTC_DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1579 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1533 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_SetYear
RTC_DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1498 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime
RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime
RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime
RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime
RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime
RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime
RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2006 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1744 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1807 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1732 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1796 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_GetDay
RTC_ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1835 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetHour
RTC_ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1927 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 1785 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute
RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1955 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_GetSecond
RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1983 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2080 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2057 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetTime
RTC_ALRMAR HU LL_RTC_ALMA_GetTime
RTC_ALRMAR MNT LL_RTC_ALMA_GetTime
RTC_ALRMAR MNU LL_RTC_ALMA_GetTime
RTC_ALRMAR ST LL_RTC_ALMA_GetTime
RTC_ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2032 of file stm32g4xx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 1899 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1872 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_SetDay
RTC_ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1821 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_SetHour
RTC_ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1913 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 1765 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute
RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1941 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_SetSecond
RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1969 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2069 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2046 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 1886 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1854 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime
RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime
RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime
RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime
RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime
RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime
RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2374 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2112 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2175 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2100 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2164 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_GetDay
RTC_ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2203 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetHour
RTC_ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2295 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2153 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute
RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2323 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_GetSecond
RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2351 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2448 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2425 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetTime
RTC_ALRMBR HU LL_RTC_ALMB_GetTime
RTC_ALRMBR MNT LL_RTC_ALMB_GetTime
RTC_ALRMBR MNU LL_RTC_ALMB_GetTime
RTC_ALRMBR ST LL_RTC_ALMB_GetTime
RTC_ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2400 of file stm32g4xx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2267 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2240 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_SetDay
RTC_ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2189 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_SetHour
RTC_ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2281 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2133 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute
RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2309 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_SetSecond
RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2337 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2437 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2414 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2254 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2222 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2504 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent ( RTC_TypeDef * RTCx )

Disable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2480 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2711 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2492 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent ( RTC_TypeDef * RTCx )

Enable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2468 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2700 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2534 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetDate
RTC_TSDR MT LL_RTC_TS_GetDate
RTC_TSDR MU LL_RTC_TS_GetDate
RTC_TSDR DT LL_RTC_TS_GetDate
RTC_TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2678 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR DT LL_RTC_TS_GetDay
RTC_TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2661 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetHour
RTC_TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2560 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR MNT LL_RTC_TS_GetMinute
RTC_TSTR HU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2573 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR MT LL_RTC_TS_GetMonth
RTC_TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2648 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR ST LL_RTC_TS_GetSecond
RTC_TSTR HU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2586 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
RTC_TSDR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2689 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetTime
RTC_TSTR HU LL_RTC_TS_GetTime
RTC_TSTR MNT LL_RTC_TS_GetTime
RTC_TSTR MNU LL_RTC_TS_GetTime
RTC_TSTR ST LL_RTC_TS_GetTime
RTC_TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2604 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
RTC_TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2547 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2623 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2520 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Clear TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable
TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
Return values:
None

Definition at line 2753 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel
TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_DisableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
Return values:
None

Definition at line 2987 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_DisableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
Return values:
None

Definition at line 2822 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_DisableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Disable Tamper mask flag.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask
TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
Return values:
None

Definition at line 2788 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( RTC_TypeDef * RTCx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2834 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable
TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
Return values:
None

Definition at line 2736 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel
TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_EnableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
Return values:
None

Definition at line 2970 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_EnableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
Return values:
None

Definition at line 2805 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_EnableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Enable Tamper mask flag.

Note:
Associated Tamper IT must not enabled when tamper mask is set.
Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask
TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
Return values:
None

Definition at line 2771 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( RTC_TypeDef * RTCx )

Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2846 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( RTC_TypeDef * RTCx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 2912 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( RTC_TypeDef * RTCx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 2879 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( RTC_TypeDef * RTCx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 2953 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
RTCx RTC Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 2896 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
RTCx RTC Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 2863 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
RTCx RTC Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 2933 of file stm32g4xx_ll_rtc.h.

References UNUSED.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Internal Tamper

Functions
Internal Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Enable (RTC_TypeDef *RTCx, uint32_t InternalTamper)
Enable internal tamper detection.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Disable (RTC_TypeDef *RTCx, uint32_t InternalTamper)
Disable internal tamper detection.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | InternalTamper
 | ) |  |

Disable internal tamper detection.

Reference Manual to LL API cross reference:
TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP7E... LL_RTC_TAMPER_ITAMP_Disable
Parameters:
RTCx RTC Instance
InternalTamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ITAMP1
  • LL_RTC_TAMPER_ITAMP3
  • LL_RTC_TAMPER_ITAMP4
  • LL_RTC_TAMPER_ITAMP5
  • LL_RTC_TAMPER_ITAMP6
Return values:
None

Definition at line 3049 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | InternalTamper
 | ) |  |

Enable internal tamper detection.

Reference Manual to LL API cross reference:
TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP7E... LL_RTC_TAMPER_ITAMP_Enable
Parameters:
RTCx RTC Instance
InternalTamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ITAMP1
  • LL_RTC_TAMPER_ITAMP3
  • LL_RTC_TAMPER_ITAMP4
  • LL_RTC_TAMPER_ITAMP5
  • LL_RTC_TAMPER_ITAMP6
Return values:
None

Definition at line 3022 of file stm32g4xx_ll_rtc.h.

References UNUSED.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3083 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3071 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3155 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 3131 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3094 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1 in RTC_ICSR
Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3144 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 3114 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Backup_Registers

Functions
Backup_Registers
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_BKP_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BKP_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Reference Manual to LL API cross reference:
TAMP_BKPxR BKP LL_RTC_BKP_GetRegister
Parameters:
RTCx RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3 ...
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

Definition at line 3205 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_BKP_SetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified Backup data register.

Reference Manual to LL API cross reference:
TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
Parameters:
RTCx | RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3 ...
Data | Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 3181 of file stm32g4xx_ll_rtc.h.

References UNUSED.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 3337 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_GetOutputFreq
RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3252 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_GetPeriod
RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3312 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3279 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ICSR
Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3326 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_SetOutputFreq
RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3237 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ICSR
Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_SetPeriod
RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3297 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ICSR
Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3268 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3 (RTC_TypeDef *RTCx)
Get internal tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4 (RTC_TypeDef *RTCx)
Get internal tamper 4 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5 (RTC_TypeDef *RTCx)
Get internal tamper 5 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6 (RTC_TypeDef *RTCx)
Get internal tamper 6 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (RTC_TypeDef *RTCx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (RTC_TypeDef *RTCx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (RTC_TypeDef *RTCx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3M (RTC_TypeDef *RTCx)
Get internal tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4M (RTC_TypeDef *RTCx)
Get internal tamper 4 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5M (RTC_TypeDef *RTCx)
Get internal tamper 5 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6M (RTC_TypeDef *RTCx)
Get internal tamper 6 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP3 (RTC_TypeDef *RTCx)
Clear internal tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP4 (RTC_TypeDef *RTCx)
Clear internal tamper 4 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP5 (RTC_TypeDef *RTCx)
Clear internal tamper 5 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP6 (RTC_TypeDef *RTCx)
Clear internal tamper 6 detection flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3488 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3477 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3 ( RTC_TypeDef * RTCx )

Clear internal tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4307 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4 ( RTC_TypeDef * RTCx )

Clear internal tamper 4 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP4F LL_RTC_ClearFlag_ITAMP4
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4319 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5 ( RTC_TypeDef * RTCx )

Clear internal tamper 5 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4331 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6 ( RTC_TypeDef * RTCx )

Clear internal tamper 6 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4344 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_ITS ( RTC_TypeDef * RTCx )

Clear Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CITSF LL_RTC_ClearFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3433 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3521 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( RTC_TypeDef * RTCx )

Clear tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4173 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( RTC_TypeDef * RTCx )

Clear tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4185 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( RTC_TypeDef * RTCx )

Clear tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4198 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3455 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3444 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3466 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3422 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM ( RTC_TypeDef * RTCx )

Get Alarm A masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3587 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3576 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3411 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM ( RTC_TypeDef * RTCx )

Get Alarm B masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3598 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3565 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3499 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3532 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3 ( RTC_TypeDef * RTCx )

Get internal tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3787 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M ( RTC_TypeDef * RTCx )

Get internal tamper 3 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4095 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4 ( RTC_TypeDef * RTCx )

Get internal tamper 4 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP4F LL_RTC_IsActiveFlag_ITAMP4
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3799 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M ( RTC_TypeDef * RTCx )

Get internal tamper 4 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP4MF LL_RTC_IsActiveFlag_ITAMP4M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4107 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5 ( RTC_TypeDef * RTCx )

Get internal tamper 5 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3810 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M ( RTC_TypeDef * RTCx )

Get internal tamper 5 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4119 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6 ( RTC_TypeDef * RTCx )

Get internal tamper 6 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3823 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M ( RTC_TypeDef * RTCx )

Get internal tamper 6 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4132 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS ( RTC_TypeDef * RTCx )

Get Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3356 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM ( RTC_TypeDef * RTCx )

Get Internal Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3642 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3367 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3510 of file stm32g4xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3543 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( RTC_TypeDef * RTCx )

Get tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3653 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M ( RTC_TypeDef * RTCx )

Get tamper 1 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3962 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( RTC_TypeDef * RTCx )

Get tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3665 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M ( RTC_TypeDef * RTCx )

Get tamper 2 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3974 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( RTC_TypeDef * RTCx )

Get tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3678 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M ( RTC_TypeDef * RTCx )

Get tamper 3 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3987 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3389 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM ( RTC_TypeDef * RTCx )

Get Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3620 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3378 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM ( RTC_TypeDef * RTCx )

Get Time-stamp overflow masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3631 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3400 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM ( RTC_TypeDef * RTCx )

Get Wakeup timer masked flag.

Reference Manual to LL API cross reference:
RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3609 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3554 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP3 (RTC_TypeDef *RTCx)
Enable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP3 (RTC_TypeDef *RTCx)
Disable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP4 (RTC_TypeDef *RTCx)
Enable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP4 (RTC_TypeDef *RTCx)
Disable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP5 (RTC_TypeDef *RTCx)
Enable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP5 (RTC_TypeDef *RTCx)
Disable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP6 (RTC_TypeDef *RTCx)
Enable internal tamper 6 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP6 (RTC_TypeDef *RTCx)
Disable internal tamper 6 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP3 (RTC_TypeDef *RTCx)
Check if internal tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP4 (RTC_TypeDef *RTCx)
Check if internal tamper 4 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP5 (RTC_TypeDef *RTCx)
Check if internal tamper 5 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP6 (RTC_TypeDef *RTCx)
Check if internal tamper 6 interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4478 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4454 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3 ( RTC_TypeDef * RTCx )

Disable internal tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_DisableIT_ITAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4991 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4 ( RTC_TypeDef * RTCx )

Disable internal tamper 4 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP4IE LL_RTC_DisableIT_ITAMP4
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5014 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5 ( RTC_TypeDef * RTCx )

Disable internal tamper 5 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP5IE LL_RTC_DisableIT_ITAMP5
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5037 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6 ( RTC_TypeDef * RTCx )

Disable internal tamper 6 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP6IE LL_RTC_DisableIT_ITAMP6
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5061 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP1 ( RTC_TypeDef * RTCx )

Disable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4545 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP2 ( RTC_TypeDef * RTCx )

Disable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4569 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP3 ( RTC_TypeDef * RTCx )

Disable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4593 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4406 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4430 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4466 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4442 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3 ( RTC_TypeDef * RTCx )

Enable internal tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4980 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4 ( RTC_TypeDef * RTCx )

Enable internal tamper 4 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP4IE LL_RTC_EnableIT_ITAMP4
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5003 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5 ( RTC_TypeDef * RTCx )

Enable internal tamper 5 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5026 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6 ( RTC_TypeDef * RTCx )

Enable internal tamper 6 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 5050 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP1 ( RTC_TypeDef * RTCx )

Enable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4533 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP2 ( RTC_TypeDef * RTCx )

Enable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4557 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP3 ( RTC_TypeDef * RTCx )

Enable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4582 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4394 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 4418 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4522 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4511 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3 ( RTC_TypeDef * RTCx )

Check if internal tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5449 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4 ( RTC_TypeDef * RTCx )

Check if internal tamper 4 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP4IE LL_RTC_IsEnabledIT_ITAMP4
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5460 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5 ( RTC_TypeDef * RTCx )

Check if internal tamper 5 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5472 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6 ( RTC_TypeDef * RTCx )

Check if internal tamper 6 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5485 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1 ( RTC_TypeDef * RTCx )

Check if tamper 1 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5312 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2 ( RTC_TypeDef * RTCx )

Check if tamper 2 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5324 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3 ( RTC_TypeDef * RTCx )

Check if tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 5338 of file stm32g4xx_ll_rtc.h.

References UNUSED.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4489 of file stm32g4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 4500 of file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMB field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 466 of file stm32g4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 698 of file stm32g4xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 586 of file stm32g4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMB field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 720 of file stm32g4xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 376 of file stm32g4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 443 of file stm32g4xx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function does not reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 134 of file stm32g4xx_ll_rtc.c.

References assert_param, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_WaitForSynchro(), and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 745 of file stm32g4xx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 789 of file stm32g4xx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 213 of file stm32g4xx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 253 of file stm32g4xx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 273 of file stm32g4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 355 of file stm32g4xx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 816 of file stm32g4xx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 49 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 94 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 103 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 109 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 106 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 70 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 67 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT)          \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 90 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 87 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 84 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 62 of file stm32g4xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32g4xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 53 of file stm32g4xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 85 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 91 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 75 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 70 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 96 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 101 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 65 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 60 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 80 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 55 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_spi.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 124 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 125 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 128 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 126 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 127 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 122 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 123 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants | I2S Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Error interrupt enable

Definition at line 1495 of file stm32g4xx_ll_spi.h.

#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 1493 of file stm32g4xx_ll_spi.h.

#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 1494 of file stm32g4xx_ll_spi.h.

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 139 of file stm32g4xx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 137 of file stm32g4xx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 138 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 147 of file stm32g4xx_ll_spi.h.

#define LL_SPI_MODE_SLAVE 0x00000000U

Slave configuration

Definition at line 148 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Serial Protocol

Defines
Serial Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U

Motorola mode. Used as default value

Definition at line 156 of file stm32g4xx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

TI mode

Definition at line 157 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE 0x00000000U

First clock transition is the first data capture edge

Definition at line 165 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 166 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 175 of file stm32g4xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW 0x00000000U

Clock to 0 when idle

Definition at line 174 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 189 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 186 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U

BaudRate control equal to fPCLK/2

Definition at line 183 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 190 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 187 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 184 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 188 of file stm32g4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 185 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 198 of file stm32g4xx_ll_spi.h.

#define LL_SPI_MSB_FIRST 0x00000000U

Data is transmitted/received with the MSB first

Definition at line 199 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX 0x00000000U

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 207 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 209 of file stm32g4xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 210 of file stm32g4xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 208 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT 0x00000000U

NSS pin used in Input. Only used in Master mode

Definition at line 219 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 220 of file stm32g4xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 218 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)

Data length for SPI transfer: 10 bits

Definition at line 234 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)

Data length for SPI transfer: 11 bits

Definition at line 235 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 12 bits

Definition at line 236 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)

Data length for SPI transfer: 13 bits

Definition at line 237 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 14 bits

Definition at line 238 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 15 bits

Definition at line 239 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 16 bits

Definition at line 240 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)

Data length for SPI transfer: 4 bits

Definition at line 228 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)

Data length for SPI transfer: 5 bits

Definition at line 229 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 6 bits

Definition at line 230 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 7 bits

Definition at line 231 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 8 bits

Definition at line 232 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)

Data length for SPI transfer: 9 bits

Definition at line 233 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U

CRC calculation disabled

Definition at line 249 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 250 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Length

Defines
CRC Length
SPI Exported Constants

Defines

#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

Define Documentation

#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

16-bit CRC length

Definition at line 260 of file stm32g4xx_ll_spi.h.

#define LL_SPI_CRC_8BIT 0x00000000U

8-bit CRC length

Definition at line 259 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RX FIFO Threshold

Defines
RX FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

Define Documentation

#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U

RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit)

Definition at line 268 of file stm32g4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)

Definition at line 269 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RX FIFO Level

Defines
RX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_EMPTY 0x00000000U

FIFO reception empty

Definition at line 277 of file stm32g4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

FIFO reception full

Definition at line 280 of file stm32g4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)

FIFO reception 1/2

Definition at line 279 of file stm32g4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)

FIFO reception 1/4

Definition at line 278 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TX FIFO Level

Defines
TX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

Define Documentation

#define LL_SPI_TX_FIFO_EMPTY 0x00000000U

FIFO transmission empty

Definition at line 288 of file stm32g4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

FIFO transmission full

Definition at line 291 of file stm32g4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)

FIFO transmission 1/2

Definition at line 290 of file stm32g4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)

FIFO transmission 1/4

Definition at line 289 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Parity

Defines
DMA Parity
SPI Exported Constants

Defines

#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U

Define Documentation

#define LL_SPI_DMA_PARITY_EVEN 0x00000000U

Select DMA parity Even

Definition at line 299 of file stm32g4xx_ll_spi.h.

#define LL_SPI_DMA_PARITY_ODD 0x00000001U

Select DMA parity Odd

Definition at line 300 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 334 of file stm32g4xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 326 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 370 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 358 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 537 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 468 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 497 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 651 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 411 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_GetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER

Definition at line 678 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get serial protocol used.

Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 439 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 565 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 602 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 381 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 518 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 455 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 484 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 627 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 397 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_SetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER
Return values:
None

Definition at line 665 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set serial protocol used.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 426 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 552 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 585 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 710 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 698 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 785 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT

Definition at line 750 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 796 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 807 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 722 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 762 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 774 of file stm32g4xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT
Return values:
None

Definition at line 737 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 874 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 862 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 848 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 886 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 832 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1019 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Note:
Clearing this flag is done by reading SPIx_SR register
Reference Manual to LL API cross reference:
SR FRE LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1064 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_FRE().

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1032 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1048 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO reception Level.

Reference Manual to LL API cross reference:
SR FRLVL LL_SPI_GetRxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_EMPTY
  • LL_SPI_RX_FIFO_QUARTER_FULL
  • LL_SPI_RX_FIFO_HALF_FULL
  • LL_SPI_RX_FIFO_FULL

Definition at line 993 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO Transmission Level.

Reference Manual to LL API cross reference:
SR FTLVL LL_SPI_GetTxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TX_FIFO_EMPTY
  • LL_SPI_TX_FIFO_QUARTER_FULL
  • LL_SPI_TX_FIFO_HALF_FULL
  • LL_SPI_TX_FIFO_FULL

Definition at line 1008 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 967 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 927 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 978 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 938 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 949 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 905 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 916 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_TXE().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1120 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_ERR().

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1131 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_RXNE().

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1142 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_TXE().

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1086 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_ERR().

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1097 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_RXNE().

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1108 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1153 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1164 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1175 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_TXE().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1205 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_RX().

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1238 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1314 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1194 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_RX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1227 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_GetDMAParity_RX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1276 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_GetDMAParity_TX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1303 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1216 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1249 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_TX().

__STATIC_INLINE void LL_SPI_SetDMAParity_RX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_SetDMAParity_RX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1263 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_TX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_SetDMAParity_TX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1290 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1344 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData16().

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1333 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1373 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_TransmitData16().

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1356 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 133 of file stm32g4xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_PERIPH_SPI3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

Referenced by LL_I2S_DeInit().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 200 of file stm32g4xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_DATAWIDTH_9BIT, LL_SPI_IsEnabled(), LL_SPI_RX_FIFO_TH_QUARTER, LL_SPI_SetCRCPolynomial(), LL_SPI_SetRxFIFOThreshold(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 278 of file stm32g4xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Private Constants

Defines
I2S Private Constants
I2S

Defines

#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U

Define Documentation

#define I2S_I2SCFGR_CLEAR_MASK
Value:
(SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )

Definition at line 317 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define I2S_I2SPR_CLEAR_MASK 0x0002U

Definition at line 321 of file stm32g4xx_ll_spi.c.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Define Documentation

#define IS_LL_I2S_AUDIO_FREQ ( __VALUE__ )
Value:
((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))

Definition at line 352 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_CPOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_POLARITY_LOW)  \
                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))

Definition at line 335 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_DATAFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))

Definition at line 330 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MCLK_OUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))

Definition at line 349 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))

Definition at line 344 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_PRESCALER_LINEAR ( __VALUE__ ) ((__VALUE__) >= 0x2U)

Definition at line 356 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_PRESCALER_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))

Definition at line 358 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_STANDARD ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))

Definition at line 338 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2S_InitTypeDef Struct Reference
I2S Exported Init structure

I2S Init structure definition. More...

#include <stm32g4xx_ll_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | ClockPolarity

Detailed Description

I2S Init structure definition.

Definition at line 1426 of file stm32g4xx_ll_spi.h.

Field Documentation

uint32_t LL_I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of Audio Frequency

Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity and unitary functions LL_I2S_SetPrescalerLinear() and LL_I2S_SetPrescalerParity() to set it.

Definition at line 1451 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::ClockPolarity

Specifies the idle state of the I2S clock. This parameter can be a value of Clock Polarity

This feature can be modified afterwards using unitary function LL_I2S_SetClockPolarity().

Definition at line 1458 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of Data format

This feature can be modified afterwards using unitary function LL_I2S_SetDataFormat().

Definition at line 1439 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of MCLK Output

This feature can be modified afterwards using unitary functions LL_I2S_EnableMasterClock() or LL_I2S_DisableMasterClock.

Definition at line 1445 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of Operation Mode

This feature can be modified afterwards using unitary function LL_I2S_SetTransferMode().

Definition at line 1428 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2s Standard

This feature can be modified afterwards using unitary function LL_I2S_SetStandard().

Definition at line 1433 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_spi.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2S Exported Constants

Flags defines which can be used with LL_I2S_ReadReg function. More...

Defines

#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_I2S_ReadReg function.

Define Documentation

#define LL_I2S_SR_BSY LL_SPI_SR_BSY

Busy flag

Definition at line 1481 of file stm32g4xx_ll_spi.h.

#define LL_I2S_SR_FRE LL_SPI_SR_FRE

TI mode frame format error flag

Definition at line 1484 of file stm32g4xx_ll_spi.h.

#define LL_I2S_SR_OVR LL_SPI_SR_OVR

Overrun flag

Definition at line 1483 of file stm32g4xx_ll_spi.h.

#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 1479 of file stm32g4xx_ll_spi.h.

#define LL_I2S_SR_TXE LL_SPI_SR_TXE

Tx buffer empty flag

Definition at line 1480 of file stm32g4xx_ll_spi.h.

#define LL_I2S_SR_UDR SPI_SR_UDR

Underrun flag

Definition at line 1482 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data format

Defines
Data format
I2S Exported Constants

Defines

#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define LL_I2S_DATAFORMAT_16B 0x00000000U

Data length 16 bits, Channel length 16bit

Definition at line 1503 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Data length 16 bits, Channel length 32bit

Definition at line 1504 of file stm32g4xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

Data length 24 bits, Channel length 32bit

Definition at line 1505 of file stm32g4xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Data length 16 bits, Channel length 32bit

Definition at line 1506 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
I2S Exported Constants

Defines

#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Clock steady state is high level

Definition at line 1515 of file stm32g4xx_ll_spi.h.

#define LL_I2S_POLARITY_LOW 0x00000000U

Clock steady state is low level

Definition at line 1514 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2s Standard

Defines
I2s Standard
I2S Exported Constants

Defines

#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

LSB justified standard (right justified)

Definition at line 1525 of file stm32g4xx_ll_spi.h.

#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

MSB justified standard (left justified)

Definition at line 1524 of file stm32g4xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

PCM standard, long frame synchronization

Definition at line 1527 of file stm32g4xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

PCM standard, short frame synchronization

Definition at line 1526 of file stm32g4xx_ll_spi.h.

#define LL_I2S_STANDARD_PHILIPS 0x00000000U

I2S standard philips

Definition at line 1523 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Operation Mode

Defines
Operation Mode
I2S Exported Constants

Defines

#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Define Documentation

#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Master Rx configuration

Definition at line 1538 of file stm32g4xx_ll_spi.h.

#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Master Tx configuration

Definition at line 1537 of file stm32g4xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Slave Rx configuration

Definition at line 1536 of file stm32g4xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_TX 0x00000000U

Slave Tx configuration

Definition at line 1535 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Prescaler Factor

Defines
Prescaler Factor
I2S Exported Constants

Defines

#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Define Documentation

#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U

Odd factor: Real divider value is = I2SDIV * 2

Definition at line 1546 of file stm32g4xx_ll_spi.h.

#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Odd factor: Real divider value is = (I2SDIV * 2)+1

Definition at line 1547 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MCLK Output

Defines
MCLK Output
I2S Exported Constants

Defines

#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Define Documentation

#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U

Master clock output is disabled

Definition at line 1557 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Master clock output is enabled

Definition at line 1558 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Audio Frequency

Defines
Audio Frequency
I2S Exported Constants

Defines

#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U

Define Documentation

#define LL_I2S_AUDIOFREQ_11K 11025U

Audio Frequency configuration 11025 Hz

Definition at line 1574 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_16K 16000U

Audio Frequency configuration 16000 Hz

Definition at line 1573 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_192K 192000U

Audio Frequency configuration 192000 Hz

Definition at line 1567 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_22K 22050U

Audio Frequency configuration 22050 Hz

Definition at line 1572 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_32K 32000U

Audio Frequency configuration 32000 Hz

Definition at line 1571 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_44K 44100U

Audio Frequency configuration 44100 Hz

Definition at line 1570 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_48K 48000U

Audio Frequency configuration 48000 Hz

Definition at line 1569 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_8K 8000U

Audio Frequency configuration 8000 Hz

Definition at line 1575 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_96K 96000U

Audio Frequency configuration 96000 Hz

Definition at line 1568 of file stm32g4xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_DEFAULT 2U

Audio Freq not specified. Register I2SDIV = 2

Definition at line 1576 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2S Exported Macros

Defines

#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Define Documentation

#define LL_I2S_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1610 of file stm32g4xx_ll_spi.h.

#define LL_I2S_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1602 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock output (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.
__STATIC_INLINE void | LL_I2S_EnableAsyncStart (SPI_TypeDef *SPIx)
Enable asynchronous start.
__STATIC_INLINE void | LL_I2S_DisableAsyncStart (SPI_TypeDef *SPIx)
Disable asynchronous start.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledAsyncStart (SPI_TypeDef *SPIx)
Check if asynchronous start is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_Disable ( SPI_TypeDef * SPIx )

Disable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1648 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableAsyncStart ( SPI_TypeDef * SPIx )

Disable asynchronous start.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1891 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableMasterClock ( SPI_TypeDef * SPIx )

Disable the master clock output (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_DisableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1857 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_Enable ( SPI_TypeDef * SPIx )

Select I2S mode and Enable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SMOD LL_I2S_Enable
I2SCFGR I2SE LL_I2S_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1637 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableAsyncStart ( SPI_TypeDef * SPIx )

Enable asynchronous start.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1880 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableMasterClock ( SPI_TypeDef * SPIx )

Enable the master clock output (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_EnableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1846 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity ( SPI_TypeDef * SPIx )

Get I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH

Definition at line 1719 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetDataFormat ( SPI_TypeDef * SPIx )

Get I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_GetDataFormat
I2SCFGR CHLEN LL_I2S_GetDataFormat
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B

Definition at line 1692 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear ( SPI_TypeDef * SPIx )

Get I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_GetPrescalerLinear
Parameters:
SPIx SPI Instance
Return values:
PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF

Definition at line 1808 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity ( SPI_TypeDef * SPIx )

Get I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_GetPrescalerParity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD

Definition at line 1835 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetStandard ( SPI_TypeDef * SPIx )

Get I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_GetStandard
I2SCFGR PCMSYNC LL_I2S_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG

Definition at line 1754 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetTransferMode ( SPI_TypeDef * SPIx )

Get I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_GetTransferMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX

Definition at line 1785 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabled ( SPI_TypeDef * SPIx )

Check if I2S peripheral is enabled.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1659 of file stm32g4xx_ll_spi.h.

Referenced by LL_I2S_Init().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart ( SPI_TypeDef * SPIx )

Check if asynchronous start is enabled.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1902 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock ( SPI_TypeDef * SPIx )

Check if the master clock output (Pin MCK) is enabled.

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_IsEnabledMasterClock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1868 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH
Return values:
None

Definition at line 1706 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetDataFormat | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataFormat
 | ) |  |

Set I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_SetDataFormat
I2SCFGR CHLEN LL_I2S_SetDataFormat
Parameters:
SPIx SPI Instance
DataFormat This parameter can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B
Return values:
None

Definition at line 1676 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerLinear | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | PrescalerLinear
 | ) |  |

Set I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_SetPrescalerLinear
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x02 and Max_Data=0xFF
Return values:
None

Definition at line 1797 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerParity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_SetPrescalerParity
Parameters:
SPIx SPI Instance
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 1822 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_SetStandard
I2SCFGR PCMSYNC LL_I2S_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG
Return values:
None

Definition at line 1737 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetTransferMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_SetTransferMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
Return values:
None

Definition at line 1770 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
I2S Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_I2S_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2026 of file stm32g4xx_ll_spi.h.

References LL_SPI_ClearFlag_FRE().

__STATIC_INLINE void LL_I2S_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2002 of file stm32g4xx_ll_spi.h.

References LL_SPI_ClearFlag_OVR().

__STATIC_INLINE void LL_I2S_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2013 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Reference Manual to LL API cross reference:
SR BSY LL_I2S_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1944 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE ( SPI_TypeDef * SPIx )

Get channel side flag.

Note:
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
It has no significance in PCM mode.
Reference Manual to LL API cross reference:
SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1991 of file stm32g4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1977 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1955 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_I2S_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1922 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_I2S_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1933 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsActiveFlag_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1966 of file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2080 of file stm32g4xx_ll_spi.h.

References LL_SPI_DisableIT_ERR().

__STATIC_INLINE void LL_I2S_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2091 of file stm32g4xx_ll_spi.h.

References LL_SPI_DisableIT_RXNE().

__STATIC_INLINE void LL_I2S_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2102 of file stm32g4xx_ll_spi.h.

References LL_SPI_DisableIT_TXE().

__STATIC_INLINE void LL_I2S_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2046 of file stm32g4xx_ll_spi.h.

References LL_SPI_EnableIT_ERR().

__STATIC_INLINE void LL_I2S_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2057 of file stm32g4xx_ll_spi.h.

References LL_SPI_EnableIT_RXNE().

__STATIC_INLINE void LL_I2S_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2068 of file stm32g4xx_ll_spi.h.

References LL_SPI_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if ERR IT is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2113 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if RXNE IT is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2124 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if TXE IT is enabled.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2135 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsEnabledIT_TXE().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Management

Functions
DMA Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2165 of file stm32g4xx_ll_spi.h.

References LL_SPI_DisableDMAReq_RX().

__STATIC_INLINE void LL_I2S_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2198 of file stm32g4xx_ll_spi.h.

References LL_SPI_DisableDMAReq_TX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2154 of file stm32g4xx_ll_spi.h.

References LL_SPI_EnableDMAReq_RX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2187 of file stm32g4xx_ll_spi.h.

References LL_SPI_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2176 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2209 of file stm32g4xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_TX().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DATA Management

Functions
DATA Management
I2S Exported Functions

Functions

__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.

Function Documentation

__STATIC_INLINE uint16_t LL_I2S_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF

Definition at line 2228 of file stm32g4xx_ll_spi.h.

References LL_SPI_ReceiveData16().

__STATIC_INLINE void LL_I2S_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x0000 and Max_Data=0xFFFF
Return values:
None

Definition at line 2240 of file stm32g4xx_ll_spi.h.

References LL_SPI_TransmitData16().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | value Min_Data=0x02 and Max_Data=0xFF.
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 526 of file stm32g4xx_ll_spi.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 382 of file stm32g4xx_ll_spi.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 397 of file stm32g4xx_ll_spi.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_IsEnabled(), LL_I2S_MCLK_OUTPUT_ENABLE, LL_RCC_GetI2SClockFreq(), LL_RCC_I2S_CLKSOURCE, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 504 of file stm32g4xx_ll_spi.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTEM Private Constants

Defines
SYSTEM Private Constants
SYSTEM

Defines

#define | DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
#define | FLASH_PDKEY1 0x04152637U
Power-down in Run mode Flash key.
#define | FLASH_PDKEY2 0xFAFBFCFDU

Define Documentation

#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)

Definition at line 63 of file stm32g4xx_ll_system.h.

Referenced by LL_DBGMCU_GetRevisionID().

#define FLASH_PDKEY1 0x04152637U

Power-down in Run mode Flash key.

Flash power down key1

Definition at line 68 of file stm32g4xx_ll_system.h.

Referenced by LL_FLASH_DisableRunPowerDown(), and LL_FLASH_EnableRunPowerDown().

#define FLASH_PDKEY2 0xFAFBFCFDU

Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR

Definition at line 69 of file stm32g4xx_ll_system.h.

Referenced by LL_FLASH_DisableRunPowerDown(), and LL_FLASH_EnableRunPowerDown().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG REMAP

Defines
SYSCFG REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

Define Documentation

#define LL_SYSCFG_REMAP_FLASH 0x00000000U

Main Flash memory mapped at 0x00000000

Definition at line 87 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

QUADSPI memory mapped at 0x00000000

Definition at line 93 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)

SRAM1 mapped at 0x00000000

Definition at line 89 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0

System Flash memory mapped at 0x00000000

Definition at line 88 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG BANK MODE

Defines
SYSCFG BANK MODE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_BANKMODE_BANK1 0x00000000U
#define | LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE

Define Documentation

#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U

Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000)

Definition at line 102 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE

Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000)

Definition at line 104 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 122 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 124 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 126 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 114 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 115 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 117 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 120 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG EXTI PORT

Defines
SYSCFG EXTI PORT
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTF 5U
#define | LL_SYSCFG_EXTI_PORTG 6U

Define Documentation

#define LL_SYSCFG_EXTI_PORTA 0U

EXTI PORT A

Definition at line 137 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTB 1U

EXTI PORT B

Definition at line 138 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTC 2U

EXTI PORT C

Definition at line 139 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTD 3U

EXTI PORT D

Definition at line 140 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTE 4U

EXTI PORT E

Definition at line 141 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTF 5U

EXTI PORT F

Definition at line 142 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTG 6U

EXTI PORT G

Definition at line 143 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG EXTI LINE

Defines
SYSCFG EXTI LINE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */

Define Documentation

#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */

Definition at line 151 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */

Definition at line 152 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */

Definition at line 161 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */

Definition at line 162 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */

Definition at line 163 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */

Definition at line 164 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */

Definition at line 165 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */

Definition at line 166 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */

Definition at line 153 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */

Definition at line 154 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */

Definition at line 155 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */

Definition at line 156 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */

Definition at line 157 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */

Definition at line 158 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */

Definition at line 159 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */

Definition at line 160 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 174 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17

Definition at line 181 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 176 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 179 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG CCMSRAM WRP

Defines
SYSCFG CCMSRAM WRP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9

Define Documentation

#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0

CCMSRAM Write protection page 0

Definition at line 190 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1

CCMSRAM Write protection page 1

Definition at line 191 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2

CCMSRAM Write protection page 2

Definition at line 192 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3

CCMSRAM Write protection page 3

Definition at line 193 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4

CCMSRAM Write protection page 4

Definition at line 194 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5

CCMSRAM Write protection page 5

Definition at line 195 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6

CCMSRAM Write protection page 6

Definition at line 196 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7

CCMSRAM Write protection page 7

Definition at line 197 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8

CCMSRAM Write protection page 8

Definition at line 198 of file stm32g4xx_ll_system.h.

#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9

CCMSRAM Write protection page 9

Definition at line 199 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU TRACE Pin Assignment

Defines
DBGMCU TRACE Pin Assignment
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

Define Documentation

#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN

TRACE pin assignment for Asynchronous Mode

Definition at line 232 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_TRACE_NONE 0x00000000U

TRACE pins not assigned (default state)

Definition at line 231 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1

Definition at line 233 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2

Definition at line 234 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4

Definition at line 235 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen

Definition at line 260 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP

The I2C2 SMBus timeout is frozen

Definition at line 262 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP

The I2C3 SMBus timeout is frozen

Definition at line 264 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is halted

Definition at line 259 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is halted

Definition at line 265 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP

The clock of the RTC counter is stopped when the core is halted

Definition at line 257 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is halted

Definition at line 243 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP

The counter clock of TIM3 is stopped when the core is halted

Definition at line 245 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP

The counter clock of TIM4 is stopped when the core is halted

Definition at line 248 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP

The counter clock of TIM6 is stopped when the core is halted

Definition at line 253 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP

The counter clock of TIM7 is stopped when the core is halted

Definition at line 255 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP

The window watchdog counter clock is stopped when the core is halted

Definition at line 258 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU APB1 GRP2 STOP IP

DBGMCU APB1 GRP2 STOP IP
SYSTEM Exported Constants
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP

The counter clock of TIM15 is stopped when the core is halted

Definition at line 287 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is halted

Definition at line 288 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is halted

Definition at line 290 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is halted

Definition at line 283 of file stm32g4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP

The counter clock of TIM8 is stopped when the core is halted

Definition at line 285 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: VREFBUF VOLTAGE

Defines
VREFBUF VOLTAGE
SYSTEM Exported Constants

Defines

#define | LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
#define | LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1

Define Documentation

#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)

Voltage reference scale 0 (VREFBUF_OUT = 2.048V)

Definition at line 306 of file stm32g4xx_ll_system.h.

#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0

Voltage reference scale 1 (VREFBUF_OUT = 2.5V)

Definition at line 307 of file stm32g4xx_ll_system.h.

#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1

Voltage reference scale 2 (VREFBUF_OUT = 2.9V)

Definition at line 308 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

Define Documentation

#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 317 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 318 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS

FLASH ten wait states

Definition at line 328 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS

FLASH eleven wait states

Definition at line 329 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS

FLASH twelve wait states

Definition at line 330 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS

FLASH thirteen wait states

Definition at line 331 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS

FLASH fourteen wait states

Definition at line 332 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

FLASH fifteen wait states

Definition at line 333 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 319 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 320 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four wait states

Definition at line 321 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH five wait state

Definition at line 323 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH six wait state

Definition at line 324 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH seven wait states

Definition at line 325 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS

FLASH eight wait states

Definition at line 326 of file stm32g4xx_ll_system.h.

#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS

FLASH nine wait states

Definition at line 327 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG

Functions
SYSCFG
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetFlashBankMode (uint32_t Bank)
Select Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashBankMode (void)
Get Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableCCMSRAMErase (void)
Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsCCMSRAMEraseOngoing (void)
Check if CCMSRAM erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableCCMSRAMPageWRP (uint32_t CCMSRAMWRP)
Enable CCMSRAM page write protection.
__STATIC_INLINE void | LL_SYSCFG_LockCCMSRAMWRP (void)
CCMSRAM page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockCCMSRAMWRP (void)
CCMSRAM page write protection unlock prior to erase.

Function Documentation

__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP ( void )

Clear SRAM parity error flag.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
Return values:
None

Definition at line 832 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster ( void )

Disable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP, OPAMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
Return values:
None

Definition at line 449 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 493 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC ( void )

Disable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
Return values:
None

Definition at line 573 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC ( void )

Disable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
Return values:
None

Definition at line 603 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC ( void )

Disable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
Return values:
None

Definition at line 563 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC ( void )

Disable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
Return values:
None

Definition at line 613 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC ( void )

Disable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
Return values:
None

Definition at line 593 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC ( void )

Disable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
Return values:
None

Definition at line 583 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster ( void )

Enable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP, OPAMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
Return values:
None

Definition at line 430 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase ( void )

Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation.

This bit is automatically cleared at the end of the CCMSRAM erase operation.)

Note:
This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register as described in the Reference Manual.
Reference Manual to LL API cross reference:
SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
Return values:
None

Definition at line 766 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP ( uint32_t CCMSRAMWRP )

Enable CCMSRAM page write protection.

Note:
Write protection is cleared only by a system reset
Reference Manual to LL API cross reference:
SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
Parameters:
CCMSRAMWRP This parameter can be a combination of the following values:
  • LL_SYSCFG_CCMSRAMWRP_PAGE0
  • LL_SYSCFG_CCMSRAMWRP_PAGE1
  • LL_SYSCFG_CCMSRAMWRP_PAGE2
  • LL_SYSCFG_CCMSRAMWRP_PAGE3
  • LL_SYSCFG_CCMSRAMWRP_PAGE4
  • LL_SYSCFG_CCMSRAMWRP_PAGE5
  • LL_SYSCFG_CCMSRAMWRP_PAGE6
  • LL_SYSCFG_CCMSRAMWRP_PAGE7
  • LL_SYSCFG_CCMSRAMWRP_PAGE8
  • LL_SYSCFG_CCMSRAMWRP_PAGE9
  • LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
  • LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 878 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 471 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC ( void )

Enable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
Return values:
None

Definition at line 513 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC ( void )

Enable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
Return values:
None

Definition at line 543 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC ( void )

Enable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
Return values:
None

Definition at line 503 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC ( void )

Enable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
Return values:
None

Definition at line 553 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC ( void )

Enable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
Return values:
None

Definition at line 533 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC ( void )

Enable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
Return values:
None

Definition at line 523 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG
(*) value not defined in all devices

Definition at line 752 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode ( void )

Get Flash bank mode (Bank flashed at 0x08000000)

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_BANKMODE_BANK1
  • LL_SYSCFG_BANKMODE_BANK2

Definition at line 410 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory ( void )

Get memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
  • LL_SYSCFG_REMAP_QUADSPI (*)
(*) value not defined in all devices

Definition at line 384 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIM1/8/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP

Definition at line 812 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP ( void )

Check if SRAM parity error detected.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
Return values:
State of bit (1 or 0).

Definition at line 822 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing ( void )

Check if CCMSRAM erase operation is on going.

Reference Manual to LL API cross reference:
SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
Return values:
State of bit (1 or 0).

Definition at line 777 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC ( void )

Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
Return values:
State of bit (1 or 0).

Definition at line 633 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC ( void )

Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
Return values:
State of bit (1 or 0).

Definition at line 663 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC ( void )

Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
Return values:
State of bit (1 or 0).

Definition at line 623 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC ( void )

Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
Return values:
State of bit (1 or 0).

Definition at line 673 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC ( void )

Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
Return values:
State of bit (1 or 0).

Definition at line 653 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC ( void )

Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
Return values:
State of bit (1 or 0).

Definition at line 643 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP ( void )

CCMSRAM page write protection lock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
Return values:
None

Definition at line 888 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF
  • LL_SYSCFG_EXTI_PORTG
(*) value not defined in all devices
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
None

Definition at line 713 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode ( uint32_t Bank )

Select Flash bank mode (Bank flashed at 0x08000000)

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
Parameters:
Bank This parameter can be one of the following values:
  • LL_SYSCFG_BANKMODE_BANK1
  • LL_SYSCFG_BANKMODE_BANK2
Return values:
None

Definition at line 398 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapMemory ( uint32_t Memory )

Set memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
Parameters:
Memory This parameter can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
  • LL_SYSCFG_REMAP_QUADSPI (*)
(*) value not defined in all devices
Return values:
None

Definition at line 367 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIM1/8/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP
Return values:
None

Definition at line 795 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP ( void )

CCMSRAM page write protection unlock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
Return values:
None

Definition at line 899 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
(*) value not defined in all devices.
Return values:
None

Definition at line 1050 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
(*) value not defined in all devices.
Return values:
None

Definition at line 1090 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1064 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1104 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
  • LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1124 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
  • LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
  • LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1144 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Return values:
None

Definition at line 951 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 991 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 971 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Return values:
None

Definition at line 941 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 981 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 961 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)

Definition at line 920 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device.
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 931 of file stm32g4xx_ll_system.h.

References DBGMCU_REVID_POSITION.

__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment ( void )

Get Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
Return values:
Returned value can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4

Definition at line 1024 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment ( uint32_t PinAssignment )

Set Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
Parameters:
PinAssignment This parameter can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4
Return values:
None

Definition at line 1008 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: VREFBUF

Functions
VREFBUF
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Function Documentation

__STATIC_INLINE void LL_VREFBUF_Disable ( void )

Disable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Disable
Return values:
None

Definition at line 1173 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_DisableHIZ ( void )

Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
Return values:
None

Definition at line 1193 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_Enable ( void )

Enable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Enable
Return values:
None

Definition at line 1163 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_EnableHIZ ( void )

Enable high impedance (VREF+pin is high impedance)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
Return values:
None

Definition at line 1183 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming ( void )

Get the trimming code for VREFBUF calibration.

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
Return values:
Between 0 and 0x3F

Definition at line 1240 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling ( void )

Get the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1
  • LL_VREFBUF_VOLTAGE_SCALE2

Definition at line 1220 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady ( void )

Check if Voltage reference buffer is ready.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
Return values:
State of bit (1 or 0).

Definition at line 1230 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetTrimming ( uint32_t Value )

Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
Parameters:
Value Between 0 and 0x3F
Return values:
None

Definition at line 1251 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling ( uint32_t Scale )

Set the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
Parameters:
Scale This parameter can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1
  • LL_VREFBUF_VOLTAGE_SCALE2
Return values:
None

Definition at line 1207 of file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_EnableRunPowerDown (void)
Enable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_DisableRunPowerDown (void)
Disable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_EnableSleepPowerDown (void)
Enable Flash Power-down mode during Sleep or Low-power sleep mode.
__STATIC_INLINE void | LL_FLASH_DisableSleepPowerDown (void)
Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Function Documentation

__STATIC_INLINE void LL_FLASH_DisableDataCache ( void )

Disable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_DisableDataCache
Return values:
None

Definition at line 1387 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableDataCacheReset ( void )

Disable Data cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
Return values:
None

Definition at line 1429 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCache ( void )

Disable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_DisableInstCache
Return values:
None

Definition at line 1367 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCacheReset ( void )

Disable Instruction cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
Return values:
None

Definition at line 1408 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 1337 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableRunPowerDown ( void )

Disable Flash Power-down mode during run mode or Low-power run mode.

Reference Manual to LL API cross reference:
FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown
FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown
FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
Return values:
None

Definition at line 1462 of file stm32g4xx_ll_system.h.

References FLASH_PDKEY1, and FLASH_PDKEY2.

__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown ( void )

Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Reference Manual to LL API cross reference:
FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
Return values:
None

Definition at line 1488 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCache ( void )

Enable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_EnableDataCache
Return values:
None

Definition at line 1377 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCacheReset ( void )

Enable Data cache reset.

Note:
bit can be written only when the data cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
Return values:
None

Definition at line 1419 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCache ( void )

Enable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_EnableInstCache
Return values:
None

Definition at line 1357 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCacheReset ( void )

Enable Instruction cache reset.

Note:
bit can be written only when the instruction cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
Return values:
None

Definition at line 1398 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 1327 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableRunPowerDown ( void )

Enable Flash Power-down mode during run mode or Low-power run mode.

Note:
Flash memory can be put in power-down mode only when the code is executed from RAM
Flash must not be accessed when power down is enabled
Flash must not be put in power-down while a program or an erase operation is on-going
Reference Manual to LL API cross reference:
FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown
FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown
FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
Return values:
None

Definition at line 1446 of file stm32g4xx_ll_system.h.

References FLASH_PDKEY1, and FLASH_PDKEY2.

__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown ( void )

Enable Flash Power-down mode during Sleep or Low-power sleep mode.

Note:
Flash must not be put in power-down while a program or an erase operation is on-going
Reference Manual to LL API cross reference:
FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
Return values:
None

Definition at line 1478 of file stm32g4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
  • LL_FLASH_LATENCY_5 (*)
  • LL_FLASH_LATENCY_6 (*)
  • LL_FLASH_LATENCY_7 (*)
  • LL_FLASH_LATENCY_8 (*)
  • LL_FLASH_LATENCY_9 (*)
  • LL_FLASH_LATENCY_10 (*)
  • LL_FLASH_LATENCY_11 (*)
  • LL_FLASH_LATENCY_12 (*)
  • LL_FLASH_LATENCY_13 (*)
  • LL_FLASH_LATENCY_14 (*)
  • LL_FLASH_LATENCY_15 (*)
(*) value not defined in all devices.

Definition at line 1317 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 1347 of file stm32g4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
  • LL_FLASH_LATENCY_5 (*)
  • LL_FLASH_LATENCY_6 (*)
  • LL_FLASH_LATENCY_7 (*)
  • LL_FLASH_LATENCY_8 (*)
  • LL_FLASH_LATENCY_9 (*)
  • LL_FLASH_LATENCY_10 (*)
  • LL_FLASH_LATENCY_11 (*)
  • LL_FLASH_LATENCY_12 (*)
  • LL_FLASH_LATENCY_13 (*)
  • LL_FLASH_LATENCY_14 (*)
  • LL_FLASH_LATENCY_15 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1289 of file stm32g4xx_ll_system.h.

Referenced by LL_SetFlashLatency().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1242 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1275 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1308 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1341 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 805 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 884 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 963 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1042 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC5Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 5.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 5 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1121 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH5(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC6Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 6.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 6 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1182 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH6(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U,
  0x04U,
  0x38U,
  0x38U

}

Definition at line 45 of file stm32g4xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  14U,
  16U,
  20U
}

Definition at line 88 of file stm32g4xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U,
  0U
}

Definition at line 74 of file stm32g4xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U,
  8U
}

Definition at line 60 of file stm32g4xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  7U,
  8U,
  10U
}

Definition at line 102 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | OCREF_CLEAR_SELECT_Pos (28U)
Legacy definitions for compatibility purpose.
#define | OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7F)

Definition at line 133 of file stm32g4xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3F)

Definition at line 134 of file stm32g4xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1F)

Definition at line 135 of file stm32g4xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1F)

Definition at line 136 of file stm32g4xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00)

Definition at line 139 of file stm32g4xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80)

Definition at line 140 of file stm32g4xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0)

Definition at line 141 of file stm32g4xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0)

Definition at line 142 of file stm32g4xx_ll_tim.h.

#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)

0x10000000

Definition at line 152 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_SetOCRefClearInputSource().

#define OCREF_CLEAR_SELECT_Pos (28U)

Legacy definitions for compatibility purpose.

Definition at line 151 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_SetOCRefClearInputSource().

#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)

Definition at line 125 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_BKINP TIM1_AF1_BKINP

BRK BKIN input polarity

Definition at line 128 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

TIMx ETR source selection

Definition at line 129 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK_AFMODE(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_AFMODE(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 83 of file stm32g4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 189 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_AFMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
                                            || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))

Definition at line 186 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))

Definition at line 169 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))

Definition at line 166 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))

Definition at line 163 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_AFMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
                                           || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))

Definition at line 160 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))

Definition at line 143 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 140 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 137 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 53 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 47 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))

Definition at line 113 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 92 of file stm32g4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 109 of file stm32g4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 123 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 87 of file stm32g4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 132 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 80 of file stm32g4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))

Definition at line 57 of file stm32g4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 77 of file stm32g4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 74 of file stm32g4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 129 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 126 of file stm32g4xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 194 of file stm32g4xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
none

Definition at line 175 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint32_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 212 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 226 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 235 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 220 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 214 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 241 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 259 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 279 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 298 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 261 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 304 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 291 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 273 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 285 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 267 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 315 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 324 of file stm32g4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 336 of file stm32g4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 318 of file stm32g4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 330 of file stm32g4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 347 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 349 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 361 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 373 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 355 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 367 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 385 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 397 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 379 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 391 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 408 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 432 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 425 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 411 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 417 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32g4xx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | BreakAFMode
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | Break2AFMode
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 444 of file stm32g4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 556 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2AFMode

Specifies the alternate function mode of the break2 input. This parameter can be a value of BREAK2 AF MODE

This feature can be modified afterwards using unitary functions LL_TIM_ConfigBRK2()

Note:
Bidirectional break input is only supported by advanced timers instances.
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 545 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Filter

Specifies the TIM Break2 Filter. This parameter can be a value of BREAK2 FILTER

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 536 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Polarity

Specifies the TIM Break2 Input pin polarity. This parameter can be a value of BREAK2 POLARITY

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 527 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2State

Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of Break2 Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK2() or LL_TIM_DisableBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 518 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakAFMode

Specifies the alternate function mode of the break input. This parameter can be a value of BREAK AF MODE

This feature can be modified afterwards using unitary functions LL_TIM_ConfigBRK()

Note:
Bidirectional break input is only supported by advanced timers instances.
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 507 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakFilter

Specifies the TIM Break Filter. This parameter can be a value of break filter

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 498 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 489 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 480 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 470 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 464 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 455 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 446 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_SR_IDXF TIM_SR_IDXF
#define | LL_TIM_SR_DIRF TIM_SR_DIRF
#define | LL_TIM_SR_IERRF TIM_SR_IERRF
#define | LL_TIM_SR_TERRF TIM_SR_TERRF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 590 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 589 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 581 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 591 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 582 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 592 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 583 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 593 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 584 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 594 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC5IF TIM_SR_CC5IF

Capture/compare 5 interrupt flag

Definition at line 585 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_CC6IF TIM_SR_CC6IF

Capture/compare 6 interrupt flag

Definition at line 586 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 587 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_DIRF TIM_SR_DIRF

Direction Change interrupt flag

Definition at line 597 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_IDXF TIM_SR_IDXF

Index interrupt flag

Definition at line 596 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_IERRF TIM_SR_IERRF

Index Error flag

Definition at line 598 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_SBIF TIM_SR_SBIF

System Break interrupt flag

Definition at line 595 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_TERRF TIM_SR_TERRF

Transition Error flag

Definition at line 599 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 588 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 580 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 608 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 609 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Break2 Enable

Defines
Break2 Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define LL_TIM_BREAK2_DISABLE 0x00000000U

Break2 function disabled

Definition at line 617 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break2 function enabled

Definition at line 618 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 626 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 627 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_DIER_IDXIE TIM_DIER_IDXIE
#define | LL_TIM_DIER_DIRIE TIM_DIER_DIRIE
#define | LL_TIM_DIER_IERRIE TIM_DIER_IERRIE
#define | LL_TIM_DIER_TERRIE TIM_DIER_TERRIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 644 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 638 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 639 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 640 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 641 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 642 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE

Direction Change interrupt enable

Definition at line 646 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE

Index interrupt enable

Definition at line 645 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE

Index Error interrupt enable

Definition at line 647 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE

Transition Error interrupt enable

Definition at line 648 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 643 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 637 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 657 of file stm32g4xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 656 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 666 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 665 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 676 of file stm32g4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 677 of file stm32g4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 678 of file stm32g4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 675 of file stm32g4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 674 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 686 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 687 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 688 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 697 of file stm32g4xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 696 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 706 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 705 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 714 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 715 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 724 of file stm32g4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 725 of file stm32g4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 726 of file stm32g4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 723 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 734 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 735 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 736 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 737 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 738 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 739 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 740 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE

Timer complementary output channel 4

Definition at line 741 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

Definition at line 742 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

Definition at line 743 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 752 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 753 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Legacy definitions for compatibility purpose. More...

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)
#define | LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)

Detailed Description

Legacy definitions for compatibility purpose.

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 772 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 783 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Asymmetric PWM mode 2

Definition at line 784 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 781 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 782 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)

Direction output mode

Definition at line 786 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 776 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 775 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 771 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 773 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)

Pulse on Compare mode

Definition at line 785 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 777 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 778 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 779 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 780 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 774 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 794 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 795 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 804 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 803 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GROUPCH5

Defines
GROUPCH5
TIM Exported Constants

Defines

#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define LL_TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 812 of file stm32g4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 813 of file stm32g4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 814 of file stm32g4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 815 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 823 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 824 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 825 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 833 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 834 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 835 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 836 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 844 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 854 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 855 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 856 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 845 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 846 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 847 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 848 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 849 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 857 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 858 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 859 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 850 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 851 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 852 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 853 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 869 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 868 of file stm32g4xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 867 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected input

Definition at line 878 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 879 of file stm32g4xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 877 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)
#define | LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)
#define | LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P

Definition at line 891 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)

Encoder mode: Clock plus direction - x2 mode

Definition at line 890 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P

Definition at line 893 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)

Encoder mode: Directional Clock, x2 mode

Definition at line 892 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P

Definition at line 894 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P

Definition at line 895 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 887 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 888 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

Definition at line 889 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 906 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 904 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3

Encoder clock signal is used as trigger output

Definition at line 911 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 907 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 908 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 909 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 910 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 903 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 905 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Output 2

Defines
Trigger Output 2
TIM Exported Constants

Defines

#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

CC1 capture or a compare match is used as trigger output 2

Definition at line 922 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

Counter Enable signal (CNT_EN) is used as trigger output 2

Definition at line 920 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2

OC1REF signal is used as trigger output 2

Definition at line 923 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output 2

Definition at line 924 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output 2

Definition at line 925 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output 2

Definition at line 926 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 932 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges are used as trigger output 2

Definition at line 931 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges are used as trigger output 2

Definition at line 929 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3

OC5REF signal is used as trigger output 2

Definition at line 927 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 934 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges are used as trigger output 2

Definition at line 933 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output 2

Definition at line 928 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges are used as trigger output 2

Definition at line 930 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output 2

Definition at line 919 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output 2

Definition at line 921 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)

Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of the counter are controlled.

Definition at line 947 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

Definition at line 946 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 942 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 944 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 943 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 945 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMS Preload Source

Defines
SMS Preload Source
TIM Exported Constants

Defines

#define | LL_TIM_SMSPS_TIMUPDATE 0x00000000U
#define | LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS

Define Documentation

#define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS

The SMS preload transfer is triggered by the Index event

Definition at line 957 of file stm32g4xx_ll_tim.h.

#define LL_TIM_SMSPS_TIMUPDATE 0x00000000U

The SMS preload transfer is triggered by the Timer's Update event

Definition at line 956 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR4 TIM_SMCR_TS_3
#define | LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)
#define | LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 980 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 965 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 966 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Internal Trigger 10 (ITR10) is used as trigger input

Definition at line 975 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Internal Trigger 11 (ITR11) is used as trigger input

Definition at line 976 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 967 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 968 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR4 TIM_SMCR_TS_3

Internal Trigger 4 (ITR4) is used as trigger input

Definition at line 969 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)

Internal Trigger 5 (ITR5) is used as trigger input

Definition at line 970 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)

Internal Trigger 6 (ITR6) is used as trigger input

Definition at line 971 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Internal Trigger 7 (ITR7) is used as trigger input

Definition at line 972 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)

Internal Trigger 8 (ITR8) is used as trigger input

Definition at line 973 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Internal Trigger 9 (ITR9) is used as trigger input

Definition at line 974 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 977 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 978 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 979 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 989 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 988 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 997 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 998 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 999 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 1000 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 1008 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=5

Definition at line 1018 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=6

Definition at line 1019 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=8

Definition at line 1020 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 1009 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 1010 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 1011 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 1012 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 1013 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 1021 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 1022 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 1023 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 1014 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 1015 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=6

Definition at line 1016 of file stm32g4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 1017 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Source TIM1

Defines
External Trigger Source TIM1
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

Define Documentation

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3

ADC1 analog watchdog 1

Definition at line 1045 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ADC1 analog watchdog 2

Definition at line 1046 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

ADC1 analog watchdog 3

Definition at line 1047 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 1032 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 1033 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 1034 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 1035 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 1031 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Source TIM2

Defines
External Trigger Source TIM2
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

Define Documentation

#define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 1061 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 1062 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 1063 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 1064 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 1060 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to LSE

Definition at line 1079 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM3 ETR

Definition at line 1074 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ETR input is connected to TIM4 ETR

Definition at line 1075 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Source TIM3

Defines
External Trigger Source TIM3
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

Define Documentation

#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 1

Definition at line 1103 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)

ADC2 analog watchdog 2

Definition at line 1104 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 3

Definition at line 1105 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 1088 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 1089 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 1090 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 1091 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 1087 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM2 ETR

Definition at line 1101 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ETR input is connected to TIM4 ETR

Definition at line 1102 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Source TIM4

Defines
External Trigger Source TIM4
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3

Define Documentation

#define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 1114 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 1115 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 1116 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 1117 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 1113 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3

ETR input is connected to TIM3 ETR

Definition at line 1127 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: External Trigger Source TIM8

Defines
External Trigger Source TIM8
TIM Exported Constants

Defines

#define | LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

Define Documentation

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3

ADC2 analog watchdog 1

Definition at line 1177 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)

ADC2 analog watchdog 2

Definition at line 1178 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)

ADC2 analog watchdog 3

Definition at line 1179 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 1164 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 1165 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to COMP3_OUT

Definition at line 1166 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2

ETR input is connected to COMP4_OUT

Definition at line 1167 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 1163 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 1226 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 1225 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: break filter

Defines
break filter
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

Define Documentation

#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 1234 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U

fSAMPLING=fDTS/16, N=5

Definition at line 1244 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U

fSAMPLING=fDTS/16, N=6

Definition at line 1245 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U

fSAMPLING=fDTS/16, N=8

Definition at line 1246 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U

fSAMPLING=fCK_INT, N=2

Definition at line 1235 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U

fSAMPLING=fCK_INT, N=4

Definition at line 1236 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U

fSAMPLING=fCK_INT, N=8

Definition at line 1237 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U

fSAMPLING=fDTS/2, N=6

Definition at line 1238 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U

fSAMPLING=fDTS/2, N=8

Definition at line 1239 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U

fSAMPLING=fDTS/32, N=5

Definition at line 1247 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U

fSAMPLING=fDTS/32, N=6

Definition at line 1248 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

fSAMPLING=fDTS/32, N=8

Definition at line 1249 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U

fSAMPLING=fDTS/4, N=6

Definition at line 1240 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U

fSAMPLING=fDTS/4, N=8

Definition at line 1241 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U

fSAMPLING=fDTS/8, N=6

Definition at line 1242 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U

fSAMPLING=fDTS/8, N=8

Definition at line 1243 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BREAK2 POLARITY

Defines
BREAK2 POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 1258 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 1257 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BREAK2 FILTER

Defines
BREAK2 FILTER
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

Define Documentation

#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 1266 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U

fSAMPLING=fDTS/16, N=5

Definition at line 1276 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U

fSAMPLING=fDTS/16, N=6

Definition at line 1277 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U

fSAMPLING=fDTS/16, N=8

Definition at line 1278 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U

fSAMPLING=fCK_INT, N=2

Definition at line 1267 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U

fSAMPLING=fCK_INT, N=4

Definition at line 1268 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U

fSAMPLING=fCK_INT, N=8

Definition at line 1269 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U

fSAMPLING=fDTS/2, N=6

Definition at line 1270 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U

fSAMPLING=fDTS/2, N=8

Definition at line 1271 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U

fSAMPLING=fDTS/32, N=5

Definition at line 1279 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U

fSAMPLING=fDTS/32, N=6

Definition at line 1280 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

fSAMPLING=fDTS/32, N=8

Definition at line 1281 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U

fSAMPLING=fDTS/4, N=6

Definition at line 1272 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U

fSAMPLING=fDTS/4, N=8

Definition at line 1273 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U

fSAMPLING=fDTS/8, N=6

Definition at line 1274 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U

fSAMPLING=fDTS/8, N=8

Definition at line 1275 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1289 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 1290 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1298 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 1299 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BREAK INPUT

Defines
BREAK INPUT
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

Define Documentation

#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U

TIMx_BKIN input

Definition at line 1307 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

TIMx_BKIN2 input

Definition at line 1308 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BKIN SOURCE

Defines
BKIN SOURCE
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E
#define | LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E

Define Documentation

#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E

internal signal: COMP1 output

Definition at line 1317 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E

internal signal: COMP2 output

Definition at line 1318 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E

internal signal: COMP3 output

Definition at line 1319 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E

internal signal: COMP4 output

Definition at line 1320 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE

BKIN input from AF controller

Definition at line 1316 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BKIN POLARITY

Defines
BKIN POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

Define Documentation

#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

BRK BKIN input is active high

Definition at line 1338 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP

BRK BKIN input is active low

Definition at line 1337 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BREAK AF MODE

Defines
BREAK AF MODE
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Define Documentation

#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Break input BRK in bidirectional mode

Definition at line 1347 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U

Break input BRK in input mode

Definition at line 1346 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BREAK2 AF MODE

Defines
BREAK2 AF MODE
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Define Documentation

#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Break2 input BRK2 in bidirectional mode

Definition at line 1356 of file stm32g4xx_ll_tim.h.

#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U

Break2 input BRK2 in input mode

Definition at line 1355 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Legacy definitions for compatibility purpose. More...

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

Detailed Description

Legacy definitions for compatibility purpose.

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)

TIMx_AF1 register is the DMA base address for DMA burst

Definition at line 1397 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_AF2 register is the DMA base address for DMA burst

Definition at line 1398 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 1384 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 1390 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 1381 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 1379 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 1380 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 1393 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 1386 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 1387 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 1388 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 1389 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)

TIMx_CCR5 register is the DMA base address for DMA burst

Definition at line 1391 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR6 register is the DMA base address for DMA burst

Definition at line 1392 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 1382 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 1373 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 1374 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 1376 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_DTR2 register is the DMA base address for DMA burst

Definition at line 1394 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_ECR register is the DMA base address for DMA burst

Definition at line 1395 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 1378 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_OR register is the DMA base address for DMA burst

Definition at line 1399 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 1383 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 1385 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 1375 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 1377 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_TISEL register is the DMA base address for DMA burst

Definition at line 1396 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)
#define | LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1416 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1417 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1418 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1419 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1420 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1421 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1422 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1423 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1424 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)

Transfer is done to 19 registers starting from the DMA burst base address

Definition at line 1425 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1407 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 20 registers starting from the DMA burst base address

Definition at line 1426 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)

Transfer is done to 21 registers starting from the DMA burst base address

Definition at line 1427 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 22 registers starting from the DMA burst base address

Definition at line 1428 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 23 registers starting from the DMA burst base address

Definition at line 1429 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 24 registers starting from the DMA burst base address

Definition at line 1430 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)

Transfer is done to 25 registers starting from the DMA burst base address

Definition at line 1431 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 26 registers starting from the DMA burst base address

Definition at line 1432 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1408 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1409 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1410 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1411 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1412 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1413 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1414 of file stm32g4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1415 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM1 Timer Input Ch1 Remap

Defines
TIM1 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM1 input 1 is connected to COMP1_OUT

Definition at line 1441 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1

TIM1 input 1 is connected to COMP2_OUT

Definition at line 1442 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM1 input 1 is connected to COMP3_OUT

Definition at line 1443 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

TIM1 input 1 is connected to COMP4_OUT

Definition at line 1444 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U

TIM1 input 1 is connected to GPIO

Definition at line 1440 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM2 Timer Input Ch1 Remap

Defines
TIM2 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM2 input 1 is connected to COMP1_OUT

Definition at line 1453 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1

TIM2 input 1 is connected to COMP2_OUT

Definition at line 1454 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM2 input 1 is connected to COMP3_OUT

Definition at line 1455 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

TIM2 input 1 is connected to COMP4_OUT

Definition at line 1456 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U

TIM2 input 1 is connected to GPIO

Definition at line 1452 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM2 Timer Input Ch2 Remap

Defines
TIM2 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

Define Documentation

#define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0

TIM2 input 2 is connected to COMP1_OUT

Definition at line 1468 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1

TIM2 input 2 is connected to COMP2_OUT

Definition at line 1469 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM2 input 2 is connected to COMP3_OUT

Definition at line 1470 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

TIM2 input 2 is connected to COMP4_OUT

Definition at line 1471 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U

TIM2 input 2 is connected to GPIO

Definition at line 1467 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM2 Timer Input Ch3 Remap

Defines
TIM2 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0

TIM2 input 3 is connected to COMP4_OUT

Definition at line 1483 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U

TIM2 input 3 is connected to GPIO

Definition at line 1482 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM2 Timer Input Ch4 Remap

Defines
TIM2 Timer Input Ch4 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0
#define | LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1

Define Documentation

#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0

TIM2 input 4 is connected to COMP1_OUT

Definition at line 1492 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1

TIM2 input 4 is connected to COMP2_OUT

Definition at line 1493 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U

TIM2 input 4 is connected to GPIO

Definition at line 1491 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM3 Timer Input Ch1 Remap

Defines
TIM3 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM3 input 1 is connected to COMP1_OUT

Definition at line 1502 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1

TIM3 input 1 is connected to COMP2_OUT

Definition at line 1503 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM3 input 1 is connected to COMP3_OUT

Definition at line 1504 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

TIM3 input 1 is connected to COMP4_OUT

Definition at line 1505 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U

TIM3 input 1 is connected to GPIO

Definition at line 1501 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM3 Timer Input Ch2 Remap

Defines
TIM3 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

Define Documentation

#define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0

TIM3 input 2 is connected to COMP1_OUT

Definition at line 1523 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1

TIM3 input 2 is connected to COMP2_OUT

Definition at line 1524 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM3 input 2 is connected to COMP3_OUT

Definition at line 1525 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

TIM3 input 2 is connected to COMP4_OUT

Definition at line 1526 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U

TIM3 input 2 is connected to GPIO

Definition at line 1522 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM3 Timer Input Ch3 Remap

Defines
TIM3 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

TIM3 input 3 is connected to COMP3_OUT

Definition at line 1544 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U

TIM3 input 3 is connected to GPIO

Definition at line 1543 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM4 Timer Input Ch1 Remap

Defines
TIM4 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM4 input 1 is connected to COMP1_OUT

Definition at line 1553 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1

TIM4 input 1 is connected to COMP2_OUT

Definition at line 1554 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM4 input 1 is connected to COMP3_OUT

Definition at line 1555 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

TIM4 input 1 is connected to COMP4_OUT

Definition at line 1556 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U

TIM4 input 1 is connected to GPIO

Definition at line 1552 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM4 Timer Input Ch2 Remap

Defines
TIM4 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

Define Documentation

#define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0

TIM4 input 2 is connected to COMP1_OUT

Definition at line 1574 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1

TIM4 input 2 is connected to COMP2_OUT

Definition at line 1575 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)

TIM4 input 2 is connected to COMP3_OUT

Definition at line 1576 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2

TIM4 input 2 is connected to COMP4_OUT

Definition at line 1577 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U

TIM4 input 2 is connected to GPIO

Definition at line 1573 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM4 Timer Input Ch3 Remap

Defines
TIM4 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U

Define Documentation

#define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U

TIM4 input 3 is connected to GPIO

Definition at line 1594 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM4 Timer Input Ch4 Remap

Defines
TIM4 Timer Input Ch4 Remap
TIM Exported Constants

Defines

#define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U

Define Documentation

#define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U

TIM4 input 4 is connected to GPIO

Definition at line 1605 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM8 Timer Input Ch1 Remap

Defines
TIM8 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM8 input 1 is connected to COMP1_OUT

Definition at line 1664 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1

TIM8 input 1 is connected to COMP2_OUT

Definition at line 1665 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM8 input 1 is connected to COMP3_OUT

Definition at line 1666 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2

TIM8 input 1 is connected to COMP4_OUT

Definition at line 1667 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U

TIM8 input 1 is connected to GPIO

Definition at line 1663 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM15 Timer Input Ch1 Remap

Defines
TIM15 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

Define Documentation

#define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1

TIM15 input 1 is connected to COMP1_OUT

Definition at line 1677 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM15 input 1 is connected to COMP2_OUT

Definition at line 1678 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U

TIM15 input 1 is connected to GPIO

Definition at line 1675 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0

TIM15 input 1 is connected to LSE

Definition at line 1676 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM15 Timer Input Ch2 Remap

Defines
TIM15 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1

Define Documentation

#define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

TIM15 input 2 is connected to COMP2_OUT

Definition at line 1693 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1

TIM15 input 2 is connected to COMP3_OUT

Definition at line 1694 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U

TIM15 input 2 is connected to GPIO

Definition at line 1692 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM16 Timer Input Ch1 Remap

Defines
TIM16 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

Define Documentation

#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U

TIM16 input 1 is connected to GPIO

Definition at line 1708 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM16 input 1 is connected to HSE/32

Definition at line 1713 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)

TIM16 input 1 is connected to LSE

Definition at line 1715 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

TIM16 input 1 is connected to LSI

Definition at line 1716 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1

TIM16 input 1 is connected to MCO

Definition at line 1712 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2

TIM16 input 1 is connected to RTC_WAKEUP

Definition at line 1714 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM17 Timer Input Ch1 Remap

Defines
TIM17 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

Define Documentation

#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U

TIM17 input 1 is connected to GPIO

Definition at line 1724 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)

TIM17 input 1 is connected to HSE/32

Definition at line 1729 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)

TIM17 input 1 is connected to LSE

Definition at line 1731 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)

TIM17 input 1 is connected to LSI

Definition at line 1732 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1

TIM17 input 1 is connected to MCO

Definition at line 1728 of file stm32g4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2

TIM17 input 1 is connected to RTC_WAKEUP

Definition at line 1730 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OCREF clear input selection

Defines
OCREF clear input selection
TIM Exported Constants

Defines

#define | LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk
#define | LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0
#define | LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1
#define | LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)

Define Documentation

#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U

OCREF clear input is connected to COMP1_OUT

Definition at line 1755 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0

OCREF clear input is connected to COMP2_OUT

Definition at line 1756 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1

OCREF clear input is connected to COMP3_OUT

Definition at line 1757 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)

OCREF clear input is connected to COMP4_OUT

Definition at line 1758 of file stm32g4xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk

OCREF_CLR_INT is connected to ETRF

Definition at line 1754 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: index direction selection

Defines
index direction selection
TIM Exported Constants

Defines

#define | LL_TIM_INDEX_UP_DOWN 0x00000000U
#define | LL_TIM_INDEX_UP TIM_ECR_IDIR_0
#define | LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1

Define Documentation

#define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1

Index resets the counter when down-counting only

Definition at line 1777 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_UP TIM_ECR_IDIR_0

Index resets the counter when up-counting only

Definition at line 1776 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_UP_DOWN 0x00000000U

Index resets the counter whatever the direction

Definition at line 1775 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: index positioning selection

Defines
index positioning selection
TIM Exported Constants

Defines

#define | LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U
#define | LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0
#define | LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1
#define | LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)
#define | LL_TIM_INDEX_POSITION_DOWN 0x00000000U
#define | LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0

Define Documentation

#define LL_TIM_INDEX_POSITION_DOWN 0x00000000U

Index resets the counter when clock is 0

Definition at line 1789 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U

Index resets the counter when AB = 00

Definition at line 1785 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0

Index resets the counter when AB = 01

Definition at line 1786 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0

Index resets the counter when clock is 1

Definition at line 1790 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1

Index resets the counter when AB = 10

Definition at line 1787 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)

Index resets the counter when AB = 11

Definition at line 1788 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: first index selection

Defines
first index selection
TIM Exported Constants

Defines

#define | LL_TIM_INDEX_ALL 0x00000000U
#define | LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX

Define Documentation

#define LL_TIM_INDEX_ALL 0x00000000U

Index is always active

Definition at line 1798 of file stm32g4xx_ll_tim.h.

#define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX

The first Index only resets the counter

Definition at line 1799 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Pulse on compare pulse width prescaler

Defines
Pulse on compare pulse width prescaler
TIM Exported Constants

Defines

#define | LL_TIM_PWPRSC_X1 0x00000000U
#define | LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0
#define | LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1
#define | LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)
#define | LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2
#define | LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)
#define | LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)
#define | LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)

Define Documentation

#define LL_TIM_PWPRSC_X1 0x00000000U

Pulse on compare pulse width prescaler 1

Definition at line 1806 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)

Pulse on compare pulse width prescaler 128

Definition at line 1813 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2

Pulse on compare pulse width prescaler 16

Definition at line 1810 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0

Pulse on compare pulse width prescaler 2

Definition at line 1807 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)

Pulse on compare pulse width prescaler 32

Definition at line 1811 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1

Pulse on compare pulse width prescaler 4

Definition at line 1808 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)

Pulse on compare pulse width prescaler 64

Definition at line 1812 of file stm32g4xx_ll_tim.h.

#define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)

Pulse on compare pulse width prescaler 8

Definition at line 1809 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock HSE/32 request

Defines
Clock HSE/32 request
TIM Exported Constants

Defines

#define | LL_TIM_HSE_32_NOT_REQUEST 0x00000000U
#define | LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN

Define Documentation

#define LL_TIM_HSE_32_NOT_REQUEST 0x00000000U

Clock HSE/32 not requested

Definition at line 1821 of file stm32g4xx_ll_tim.h.

#define LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN

Clock HSE/32 requested for TIM16/17 TI1SEL remap

Definition at line 1822 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1862 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1854 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Macros

Modules | Defines
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1921 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_ARR_DITHER | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) |
Value:
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
   (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)

HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR_DITHER (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1933 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
    0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1889 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1946 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY_DITHER | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY_DITHER (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1959 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1910 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1973 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE_DITHER | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE_DITHER (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1987 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 2001 of file stm32g4xx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1875 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (const TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (const TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (const TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (const TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (const TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (const TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (const TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (const TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (const TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (const TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (const TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (const TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE uint32_t | LL_TIM_IsActiveUIFCPY (const uint32_t Counter)
Indicate whether update interrupt flag (UIF) copy is set.
__STATIC_INLINE void | LL_TIM_EnableDithering (TIM_TypeDef *TIMx)
Enable dithering.
__STATIC_INLINE void | LL_TIM_DisableDithering (TIM_TypeDef *TIMx)
Disable dithering.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDithering (const TIM_TypeDef *TIMx)
Indicates whether dithering is activated.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2214 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2034 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDithering ( TIM_TypeDef * TIMx )

Disable dithering.

Note:
Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not a timer instance provides dithering.
Reference Manual to LL API cross reference:
CR1 DITHEN LL_TIM_DisableDithering
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2451 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUIFRemap ( TIM_TypeDef * TIMx )

Disable update interrupt flag (UIF) remapping.

Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_DisableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2415 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2067 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2203 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2023 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDithering ( TIM_TypeDef * TIMx )

Enable dithering.

Note:
Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not a timer instance provides dithering.
Reference Manual to LL API cross reference:
CR1 DITHEN LL_TIM_EnableDithering
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2438 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUIFRemap ( TIM_TypeDef * TIMx )

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_EnableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2404 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2056 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( const TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
If dithering is activated, pay attention to the returned value interpretation
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 2363 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( const TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 2262 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( const TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
If dithering is activated, pay attention to the Counter value interpretation
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 2291 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( const TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 2183 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( const TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 2304 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( const TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 2139 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( const TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 2331 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( const TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 2391 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( const TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 2112 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY ( const uint32_t Counter )

Indicate whether update interrupt flag (UIF) copy is set.

Parameters:
Counter Counter value
Return values:
State of bit (1 or 0).

Definition at line 2425 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( const TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2225 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( const TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2045 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering ( const TIM_TypeDef * TIMx )

Indicates whether dithering is activated.

Note:
Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not a timer instance provides dithering.
Reference Manual to LL API cross reference:
CR1 DITHEN LL_TIM_IsEnabledDithering
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2464 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( const TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
Inverted state of bit (0 or 1).

Definition at line 2078 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload parameter.
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2349 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 2244 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
If dithering is activated, pay attention to the Counter value interpretation
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 2277 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 2163 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 2126 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2320 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
Return values:
None

Definition at line 2378 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 2099 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledPreload (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (const TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (const TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC4NE LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2635 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2500 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC4NE LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2604 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2487 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( const TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 2554 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC4NE LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2666 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.

Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_IsEnabledPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2511 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 2541 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 2573 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 2527 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_OC_SetPulseWidthPrescaler (TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
Set the pulse on compare pulse width prescaler.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPulseWidthPrescaler (const TIM_TypeDef *TIMx)
Get the pulse on compare pulse width prescaler.
__STATIC_INLINE void | LL_TIM_OC_SetPulseWidth (TIM_TypeDef *TIMx, uint32_t PulseWidth)
Set the pulse on compare pulse width duration.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPulseWidth (const TIM_TypeDef *TIMx)
Get the pulse on compare pulse width duration.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCMR3 CC5S LL_TIM_OC_ConfigOutput
CCMR3 CC6S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2711 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
CCMR3 OC5CE LL_TIM_OC_DisableClear
CCMR3 OC6CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 3151 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
CCMR3 OC5FE LL_TIM_OC_DisableFast
CCMR3 OC6FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2993 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
CCMR3 OC5PE LL_TIM_OC_DisablePreload
CCMR3 OC6PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 3070 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
CCMR3 OC5CE LL_TIM_OC_EnableClear
CCMR3 OC6CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 3124 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
CCMR3 OC5FE LL_TIM_OC_EnableFast
CCMR3 OC6FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2967 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
CCMR3 OC5PE LL_TIM_OC_EnablePreload
CCMR3 OC6PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 3045 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3318 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3335 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3352 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3369 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR5) set for output channel 5.

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_GetCompareCH5
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3383 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR6) set for output channel 6.

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_GetCompareCH6
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3397 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS4N LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2942 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
CCMR3 OC5M LL_TIM_OC_GetMode
CCMR3 OC6M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASYMMETRIC_PWM1
  • LL_TIM_OCMODE_ASYMMETRIC_PWM2
  • LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
  • LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)

Definition at line 2799 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC4NP LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2869 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth ( const TIM_TypeDef * TIMx )

Get the pulse on compare pulse width duration.

Note:
Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check whether or not the pulse on compare feature is supported by the timer instance.
Reference Manual to LL API cross reference:
ECR PW LL_TIM_OC_GetPulseWidth
Parameters:
TIMx Timer instance
Return values:
Returned value can be between Min_Data=0 and Max_Data=255:

Definition at line 3491 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler ( const TIM_TypeDef * TIMx )

Get the pulse on compare pulse width prescaler.

Note:
Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check whether or not the pulse on compare feature is supported by the timer instance.
Reference Manual to LL API cross reference:
ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_PWPRSC_X1
  • LL_TIM_PWPRSC_X2
  • LL_TIM_PWPRSC_X4
  • LL_TIM_PWPRSC_X8
  • LL_TIM_PWPRSC_X16
  • LL_TIM_PWPRSC_X32
  • LL_TIM_PWPRSC_X64
  • LL_TIM_PWPRSC_X128

Definition at line 3462 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
CCMR3 OC5CE LL_TIM_OC_IsEnabledClear
CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 3180 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
CCMR3 OC5FE LL_TIM_OC_IsEnabledFast
CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 3019 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 3095 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3217 of file stm32g4xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3235 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3253 of file stm32g4xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3271 of file stm32g4xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH5 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 5 (TIMx_CCR5).

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_SetCompareCH5
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3286 of file stm32g4xx_ll_tim.h.

Referenced by OC5Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH6 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 6 (TIMx_CCR6).

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
If dithering is activated, CompareValue can be calculated with macro __LL_TIM_CALC_DELAY_DITHER .
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_SetCompareCH6
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 3301 of file stm32g4xx_ll_tim.h.

Referenced by OC6Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 3199 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS4N LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2908 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
CCMR3 OC5M LL_TIM_OC_SetMode
CCMR3 OC6M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASYMMETRIC_PWM1
  • LL_TIM_OCMODE_ASYMMETRIC_PWM2
  • LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
  • LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
Return values:
None

Definition at line 2758 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC4NP LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH4N
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 2835 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPulseWidth | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | PulseWidth
 | ) |  |

Set the pulse on compare pulse width duration.

Note:
Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check whether or not the pulse on compare feature is supported by the timer instance.
Reference Manual to LL API cross reference:
ECR PW LL_TIM_OC_SetPulseWidth
Parameters:
TIMx | Timer instance
PulseWidth | This parameter can be between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 3477 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | PulseWidthPrescaler
 | ) |  |

Set the pulse on compare pulse width prescaler.

Note:
Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check whether or not the pulse on compare feature is supported by the timer instance.
Reference Manual to LL API cross reference:
ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
Parameters:
TIMx Timer instance
PulseWidthPrescaler This parameter can be one of the following values:
  • LL_TIM_PWPRSC_X1
  • LL_TIM_PWPRSC_X2
  • LL_TIM_PWPRSC_X4
  • LL_TIM_PWPRSC_X8
  • LL_TIM_PWPRSC_X16
  • LL_TIM_PWPRSC_X32
  • LL_TIM_PWPRSC_X64
  • LL_TIM_PWPRSC_X128
Return values:
None

Definition at line 3440 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | GroupCH5
 | ) |  |

Select on which reference signal the OC5REF is combined to.

Note:
Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the combined 3-phase PWM mode.
Reference Manual to LL API cross reference:
CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
Parameters:
TIMx Timer instance
GroupCH5 This parameter can be a combination of the following values:
  • LL_TIM_GROUPCH5_NONE
  • LL_TIM_GROUPCH5_OC1REFC
  • LL_TIM_GROUPCH5_OC2REFC
  • LL_TIM_GROUPCH5_OC3REFC
Return values:
None

Definition at line 3417 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (const TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (const TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (const TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (const TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (const TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 3538 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3802 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3789 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 3591 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3832 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3849 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3866 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
If dithering is activated, pay attention to the returned value interpretation.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3883 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 3717 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 3774 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 3642 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( const TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3815 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 3567 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 3680 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 3746 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 3617 of file stm32g4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (const TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3917 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3904 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( const TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3930 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3954 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
  • LL_TIM_ENCODERMODE_X1_TI1
  • LL_TIM_ENCODERMODE_X1_TI2
Return values:
None

Definition at line 3977 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (const TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableSMSPreload (TIM_TypeDef *TIMx)
Enable SMS preload.
__STATIC_INLINE void | LL_TIM_DisableSMSPreload (TIM_TypeDef *TIMx)
Disable SMS preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledSMSPreload (const TIM_TypeDef *TIMx)
Indicate whether SMS preload is enabled.
__STATIC_INLINE void | LL_TIM_SetSMSPreloadSource (TIM_TypeDef *TIMx, uint32_t PreloadSource)
Set the preload source of SMS.
__STATIC_INLINE uint32_t | LL_TIM_GetSMSPreloadSource (const TIM_TypeDef *TIMx)
Get the preload source of SMS.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 4166 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4113 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableSMSPreload ( TIM_TypeDef * TIMx )

Disable SMS preload.

Note:
Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the preload of SMS field in SMCR register.
Reference Manual to LL API cross reference:
SMCR SMSPE LL_TIM_DisableSMSPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4320 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4100 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableSMSPreload ( TIM_TypeDef * TIMx )

Enable SMS preload.

Note:
Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the preload of SMS field in SMCR register.
Reference Manual to LL API cross reference:
SMCR SMSPE LL_TIM_EnableSMSPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4307 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource ( const TIM_TypeDef * TIMx )

Get the preload source of SMS.

Note:
Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the preload of SMS field in SMCR register.
Reference Manual to LL API cross reference:
SMCR SMSPS LL_TIM_GetSMSPreloadSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_SMSPS_TIMUPDATE
  • LL_TIM_SMSPS_INDEX

Definition at line 4364 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( const TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4126 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload ( const TIM_TypeDef * TIMx )

Indicate whether SMS preload is enabled.

Note:
Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the preload of SMS field in SMCR register.
Reference Manual to LL API cross reference:
SMCR SMSPE LL_TIM_IsEnabledSMSPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4333 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetETRSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRSource
 | ) |  |

Select the external trigger (ETR) input source.

Note:
Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or not a timer instance supports ETR source selection.
Reference Manual to LL API cross reference:
AF1 ETRSEL LL_TIM_SetETRSource
Parameters:
TIMx | Timer instance
ETRSource | This parameter can be one of the following values:

TIM1: any combination of ETR_RMP where

  • LL_TIM_TIM1_ETRSOURCE_GPIO
  • LL_TIM_TIM1_ETRSOURCE_COMP1
  • LL_TIM_TIM1_ETRSOURCE_COMP2
  • LL_TIM_TIM1_ETRSOURCE_COMP3
  • LL_TIM_TIM1_ETRSOURCE_COMP4
  • LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
  • LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
  • LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
  • LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)

TIM2: any combination of ETR_RMP where

  • LL_TIM_TIM2_ETRSOURCE_GPIO
  • LL_TIM_TIM2_ETRSOURCE_COMP1
  • LL_TIM_TIM2_ETRSOURCE_COMP2
  • LL_TIM_TIM2_ETRSOURCE_COMP3
  • LL_TIM_TIM2_ETRSOURCE_COMP4
  • LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
  • LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
  • LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
  • LL_TIM_TIM2_ETRSOURCE_LSE

TIM3: any combination of ETR_RMP where

  • LL_TIM_TIM3_ETRSOURCE_GPIO
  • LL_TIM_TIM3_ETRSOURCE_COMP1
  • LL_TIM_TIM3_ETRSOURCE_COMP2
  • LL_TIM_TIM3_ETRSOURCE_COMP3
  • LL_TIM_TIM3_ETRSOURCE_COMP4
  • LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
  • LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3

TIM4: any combination of ETR_RMP where

  • LL_TIM_TIM4_ETRSOURCE_GPIO
  • LL_TIM_TIM4_ETRSOURCE_COMP1
  • LL_TIM_TIM4_ETRSOURCE_COMP2
  • LL_TIM_TIM4_ETRSOURCE_COMP3
  • LL_TIM_TIM4_ETRSOURCE_COMP4
  • LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
  • LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)

TIM5: any combination of ETR_RMP where (**)

  • LL_TIM_TIM5_ETRSOURCE_GPIO (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
  • LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)

TIM8: any combination of ETR_RMP where

. . ETR_RMP can be one of the following values

  • LL_TIM_TIM8_ETRSOURCE_GPIO
  • LL_TIM_TIM8_ETRSOURCE_COMP1
  • LL_TIM_TIM8_ETRSOURCE_COMP2
  • LL_TIM_TIM8_ETRSOURCE_COMP3
  • LL_TIM_TIM8_ETRSOURCE_COMP4
  • LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
  • LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)

TIM20: any combination of ETR_RMP where (**)

. . ETR_RMP can be one of the following values

  • LL_TIM_TIM20_ETRSOURCE_GPIO (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
  • LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
  • LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)

(*) Value not defined in all devices.
(**) Register not available in all devices.

Return values:
None

Definition at line 4294 of file stm32g4xx_ll_tim.h.

References TIMx_AF1_ETRSEL.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
Return values:
None

Definition at line 4057 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetSMSPreloadSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | PreloadSource
 | ) |  |

Set the preload source of SMS.

Note:
Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the preload of SMS field in SMCR register.
Reference Manual to LL API cross reference:
SMCR SMSPS LL_TIM_SetSMSPreloadSource
Parameters:
TIMx Timer instance
PreloadSource This parameter can be one of the following values:
  • LL_TIM_SMSPS_TIMUPDATE
  • LL_TIM_SMSPS_INDEX
Return values:
None

Definition at line 4349 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_ITR4
  • LL_TIM_TS_ITR5
  • LL_TIM_TS_ITR6
  • LL_TIM_TS_ITR7
  • LL_TIM_TS_ITR8
  • LL_TIM_TS_ITR9
  • LL_TIM_TS_ITR10
  • LL_TIM_TS_ITR11
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
Return values:
None

Definition at line 4087 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
  • LL_TIM_TRGO_ENCODERCLK
Return values:
None

Definition at line 4007 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ADCSynchronization
 | ) |  |

Set the trigger output 2 (TRGO2) used for ADC synchronization .

Note:
Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check whether or not a timer instance can be used for ADC synchronization.
Reference Manual to LL API cross reference:
CR2 MMS2 LL_TIM_SetTriggerOutput2
Parameters:
TIMx Timer Instance
ADCSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO2_RESET
  • LL_TIM_TRGO2_ENABLE
  • LL_TIM_TRGO2_UPDATE
  • LL_TIM_TRGO2_CC1F
  • LL_TIM_TRGO2_OC1
  • LL_TIM_TRGO2_OC2
  • LL_TIM_TRGO2_OC3
  • LL_TIM_TRGO2_OC4
  • LL_TIM_TRGO2_OC5
  • LL_TIM_TRGO2_OC6
  • LL_TIM_TRGO2_OC4_RISINGFALLING
  • LL_TIM_TRGO2_OC6_RISINGFALLING
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
Return values:
None

Definition at line 4037 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode)
Configure the break input.
__STATIC_INLINE void | LL_TIM_DisarmBRK (TIM_TypeDef *TIMx)
Disarm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_DisarmBRK2 (TIM_TypeDef *TIMx)
Disarm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (const TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (const TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_EnableAsymmetricalDeadTime (TIM_TypeDef *TIMx)
Enable asymmetrical deadtime.
__STATIC_INLINE void | LL_TIM_DisableAsymmetricalDeadTime (TIM_TypeDef *TIMx)
Disable asymmetrical dead-time.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAsymmetricalDeadTime (const TIM_TypeDef *TIMx)
Indicates whether asymmetrical deadtime is activated.
__STATIC_INLINE void | LL_TIM_SetFallingDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
__STATIC_INLINE uint32_t | LL_TIM_GetFallingDeadTime (const TIM_TypeDef *TIMx)
Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
__STATIC_INLINE void | LL_TIM_EnableDeadTimePreload (TIM_TypeDef *TIMx)
Enable deadtime preload.
__STATIC_INLINE void | LL_TIM_DisableDeadTimePreload (TIM_TypeDef *TIMx)
Disable dead-time preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDeadTimePreload (const TIM_TypeDef *TIMx)
Indicates whether deadtime preload is activated.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity,
 |  | uint32_t | BreakFilter,
 |  | uint32_t | BreakAFMode
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Bidirectional mode is only supported by advanced timer instances. Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not a timer instance is an advanced-control timer.
In bidirectional mode (BKBID bit set), the Break input is configured both in input mode and in open drain output mode. Any active Break event will assert a low logic level on the Break input to indicate an internal break event to external devices.
When bidirectional mode isn't supported, BreakAFMode must be set to LL_TIM_BREAK_AFMODE_INPUT.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
BDTR BKF LL_TIM_ConfigBRK
BDTR BKBID LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
BreakFilter This parameter can be one of the following values:
  • LL_TIM_BREAK_FILTER_FDIV1
  • LL_TIM_BREAK_FILTER_FDIV1_N2
  • LL_TIM_BREAK_FILTER_FDIV1_N4
  • LL_TIM_BREAK_FILTER_FDIV1_N8
  • LL_TIM_BREAK_FILTER_FDIV2_N6
  • LL_TIM_BREAK_FILTER_FDIV2_N8
  • LL_TIM_BREAK_FILTER_FDIV4_N6
  • LL_TIM_BREAK_FILTER_FDIV4_N8
  • LL_TIM_BREAK_FILTER_FDIV8_N6
  • LL_TIM_BREAK_FILTER_FDIV8_N8
  • LL_TIM_BREAK_FILTER_FDIV16_N5
  • LL_TIM_BREAK_FILTER_FDIV16_N6
  • LL_TIM_BREAK_FILTER_FDIV16_N8
  • LL_TIM_BREAK_FILTER_FDIV32_N5
  • LL_TIM_BREAK_FILTER_FDIV32_N6
  • LL_TIM_BREAK_FILTER_FDIV32_N8
BreakAFMode This parameter can be one of the following values:
  • LL_TIM_BREAK_AFMODE_INPUT
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
Return values:
None

Definition at line 4444 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ConfigBRK2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Break2Polarity,
 |  | uint32_t | Break2Filter,
 |  | uint32_t | Break2AFMode
 | ) |  |

Configure the break 2 input.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Bidirectional mode is only supported by advanced timer instances. Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not a timer instance is an advanced-control timer.
In bidirectional mode (BK2BID bit set), the Break 2 input is configured both in input mode and in open drain output mode. Any active Break event will assert a low logic level on the Break 2 input to indicate an internal break event to external devices.
When bidirectional mode isn't supported, Break2AFMode must be set to LL_TIM_BREAK2_AFMODE_INPUT.
Reference Manual to LL API cross reference:
BDTR BK2P LL_TIM_ConfigBRK2
BDTR BK2F LL_TIM_ConfigBRK2
BDTR BK2BID LL_TIM_ConfigBRK2
Parameters:
TIMx Timer instance
Break2Polarity This parameter can be one of the following values:
  • LL_TIM_BREAK2_POLARITY_LOW
  • LL_TIM_BREAK2_POLARITY_HIGH
Break2Filter This parameter can be one of the following values:
  • LL_TIM_BREAK2_FILTER_FDIV1
  • LL_TIM_BREAK2_FILTER_FDIV1_N2
  • LL_TIM_BREAK2_FILTER_FDIV1_N4
  • LL_TIM_BREAK2_FILTER_FDIV1_N8
  • LL_TIM_BREAK2_FILTER_FDIV2_N6
  • LL_TIM_BREAK2_FILTER_FDIV2_N8
  • LL_TIM_BREAK2_FILTER_FDIV4_N6
  • LL_TIM_BREAK2_FILTER_FDIV4_N8
  • LL_TIM_BREAK2_FILTER_FDIV8_N6
  • LL_TIM_BREAK2_FILTER_FDIV8_N8
  • LL_TIM_BREAK2_FILTER_FDIV16_N5
  • LL_TIM_BREAK2_FILTER_FDIV16_N6
  • LL_TIM_BREAK2_FILTER_FDIV16_N8
  • LL_TIM_BREAK2_FILTER_FDIV32_N5
  • LL_TIM_BREAK2_FILTER_FDIV32_N6
  • LL_TIM_BREAK2_FILTER_FDIV32_N8
Break2AFMode This parameter can be one of the following values:
  • LL_TIM_BREAK2_AFMODE_INPUT
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
Return values:
None

Definition at line 4533 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4638 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime ( TIM_TypeDef * TIMx )

Disable asymmetrical dead-time.

Note:
Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not a timer instance provides asymmetrical deadtime.
Reference Manual to LL API cross reference:
DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4809 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4595 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Disable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_DisableBreakInputSource
AF1 BKCMP1E LL_TIM_DisableBreakInputSource
AF1 BKCMP2E LL_TIM_DisableBreakInputSource
AF1 BKCMP3E LL_TIM_DisableBreakInputSource
AF1 BKCMP4E LL_TIM_DisableBreakInputSource
AF1 BKCMP5E LL_TIM_DisableBreakInputSource
AF1 BKCMP6E LL_TIM_DisableBreakInputSource
AF1 BKCMP7E LL_TIM_DisableBreakInputSource
AF2 BK2INE LL_TIM_DisableBreakInputSource
AF2 BK2CMP1E LL_TIM_DisableBreakInputSource
AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
AF2 BK2CMP3E LL_TIM_DisableBreakInputSource
AF2 BK2CMP4E LL_TIM_DisableBreakInputSource
AF2 BK2CMP5E LL_TIM_DisableBreakInputSource
AF2 BK2CMP6E LL_TIM_DisableBreakInputSource
AF2 BK2CMP7E LL_TIM_DisableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3
  • LL_TIM_BKIN_SOURCE_BKCOMP4
  • LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 4736 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 4397 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK2 ( TIM_TypeDef * TIMx )

Disable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_DisableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4486 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDeadTimePreload ( TIM_TypeDef * TIMx )

Disable dead-time preload.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides deadtime preload.
Reference Manual to LL API cross reference:
DTR2 DTPE LL_TIM_DisableDeadTimePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4882 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisarmBRK ( TIM_TypeDef * TIMx )

Disarm the break input (when it operates in bidirectional mode).

Note:
The break input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output .
Reference Manual to LL API cross reference:
BDTR BKDSRM LL_TIM_DisarmBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4460 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisarmBRK2 ( TIM_TypeDef * TIMx )

Disarm the break 2 input (when it operates in bidirectional mode).

Note:
The break 2 input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output.
Reference Manual to LL API cross reference:
BDTR BK2DSRM LL_TIM_DisarmBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4549 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4623 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime ( TIM_TypeDef * TIMx )

Enable asymmetrical deadtime.

Note:
Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not a timer instance provides asymmetrical deadtime.
Reference Manual to LL API cross reference:
DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4796 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4582 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Enable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_EnableBreakInputSource
AF1 BKCMP1E LL_TIM_EnableBreakInputSource
AF1 BKCMP2E LL_TIM_EnableBreakInputSource
AF1 BKCMP3E LL_TIM_EnableBreakInputSource
AF1 BKCMP4E LL_TIM_EnableBreakInputSource
AF1 BKCMP5E LL_TIM_EnableBreakInputSource
AF1 BKCMP6E LL_TIM_EnableBreakInputSource
AF1 BKCMP7E LL_TIM_EnableBreakInputSource
AF2 BK2NE LL_TIM_EnableBreakInputSource
AF2 BK2CMP1E LL_TIM_EnableBreakInputSource
AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
AF2 BK2CMP3E LL_TIM_EnableBreakInputSource
AF2 BK2CMP4E LL_TIM_EnableBreakInputSource
AF2 BK2CMP5E LL_TIM_EnableBreakInputSource
AF2 BK2CMP6E LL_TIM_EnableBreakInputSource
AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3
  • LL_TIM_BKIN_SOURCE_BKCOMP4
  • LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 4693 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4384 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK2 ( TIM_TypeDef * TIMx )

Enable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_EnableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4473 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDeadTimePreload ( TIM_TypeDef * TIMx )

Enable deadtime preload.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides deadtime preload.
Reference Manual to LL API cross reference:
DTR2 DTPE LL_TIM_EnableDeadTimePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4869 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime ( const TIM_TypeDef * TIMx )

Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).

Note:
Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not asymmetrical dead-time insertion feature is supported by a timer instance.
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Reference Manual to LL API cross reference:
DTR2 DTGF LL_TIM_GetFallingDeadTime
Parameters:
TIMx Timer instance
Return values:
Returned value can be between Min_Data=0 and Max_Data=255:

Definition at line 4856 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( const TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4651 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime ( const TIM_TypeDef * TIMx )

Indicates whether asymmetrical deadtime is activated.

Note:
Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not a timer instance provides asymmetrical deadtime.
Reference Manual to LL API cross reference:
DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4822 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( const TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4608 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload ( const TIM_TypeDef * TIMx )

Indicates whether deadtime preload is activated.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides deadtime preload.
Reference Manual to LL API cross reference:
DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4895 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the break signal for the timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINP LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP5P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP6P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP7P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP5P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP6P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP7P LL_TIM_SetBreakInputSourcePolarity
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3
  • LL_TIM_BKIN_SOURCE_BKCOMP4
  • LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
Polarity This parameter can be one of the following values:
  • LL_TIM_BKIN_POLARITY_LOW
  • LL_TIM_BKIN_POLARITY_HIGH
(*) Value not defined in all devices.
Return values:
None

Definition at line 4782 of file stm32g4xx_ll_tim.h.

References TIM_POSITION_BRK_SOURCE, and TIMx_AF1_BKINP.

__STATIC_INLINE void LL_TIM_SetFallingDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).

Note:
Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not asymmetrical dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Reference Manual to LL API cross reference:
DTR2 DTGF LL_TIM_SetFallingDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 4840 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 4569 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_CCMR3
  • LL_TIM_DMABURST_BASEADDR_CCR5
  • LL_TIM_DMABURST_BASEADDR_CCR6
  • LL_TIM_DMABURST_BASEADDR_DTR2
  • LL_TIM_DMABURST_BASEADDR_ECR
  • LL_TIM_DMABURST_BASEADDR_TISEL
  • LL_TIM_DMABURST_BASEADDR_AF1
  • LL_TIM_DMABURST_BASEADDR_AF2
  • LL_TIM_DMABURST_BASEADDR_OR
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
  • LL_TIM_DMABURST_LENGTH_19TRANSFERS
  • LL_TIM_DMABURST_LENGTH_20TRANSFERS
  • LL_TIM_DMABURST_LENGTH_21TRANSFERS
  • LL_TIM_DMABURST_LENGTH_22TRANSFERS
  • LL_TIM_DMABURST_LENGTH_23TRANSFERS
  • LL_TIM_DMABURST_LENGTH_24TRANSFERS
  • LL_TIM_DMABURST_LENGTH_25TRANSFERS
  • LL_TIM_DMABURST_LENGTH_26TRANSFERS
Return values:
None

Definition at line 4971 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Encoder configuration

Functions
Encoder configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableEncoderIndex (TIM_TypeDef *TIMx)
Enable encoder index.
__STATIC_INLINE void | LL_TIM_DisableEncoderIndex (TIM_TypeDef *TIMx)
Disable encoder index.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledEncoderIndex (const TIM_TypeDef *TIMx)
Indicate whether encoder index is enabled.
__STATIC_INLINE void | LL_TIM_SetIndexDirection (TIM_TypeDef *TIMx, uint32_t IndexDirection)
Set index direction.
__STATIC_INLINE uint32_t | LL_TIM_GetIndexDirection (const TIM_TypeDef *TIMx)
Get actual index direction.
__STATIC_INLINE void | LL_TIM_EnableFirstIndex (TIM_TypeDef *TIMx)
Enable first index.
__STATIC_INLINE void | LL_TIM_DisableFirstIndex (TIM_TypeDef *TIMx)
Disable first index.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledFirstIndex (const TIM_TypeDef *TIMx)
Indicates whether first index is enabled.
__STATIC_INLINE void | LL_TIM_SetIndexPositionning (TIM_TypeDef *TIMx, uint32_t IndexPositionning)
Set index positioning.
__STATIC_INLINE uint32_t | LL_TIM_GetIndexPositionning (const TIM_TypeDef *TIMx)
Get actual index positioning.
__STATIC_INLINE void | LL_TIM_ConfigIDX (TIM_TypeDef *TIMx, uint32_t Configuration)
Configure encoder index.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigIDX | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Configuration
 | ) |  |

Configure encoder index.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IDIR LL_TIM_ConfigIDX
ECR FIDX LL_TIM_ConfigIDX
ECR IPOS LL_TIM_ConfigIDX
Parameters:
TIMx Timer instance
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_INDEX_UP or LL_TIM_INDEX_DOWN or LL_TIM_INDEX_UP_DOWN
  • LL_TIM_INDEX_ALL or LL_TIM_INDEX_FIRST_ONLY
  • LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or LL_TIM_INDEX_POSITION_UP
Return values:
None

Definition at line 5148 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableEncoderIndex ( TIM_TypeDef * TIMx )

Disable encoder index.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IE LL_TIM_DisableEncoderIndex
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5005 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableFirstIndex ( TIM_TypeDef * TIMx )

Disable first index.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR FIDX LL_TIM_DisableFirstIndex
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5077 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableEncoderIndex ( TIM_TypeDef * TIMx )

Enable encoder index.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IE LL_TIM_EnableEncoderIndex
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4992 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableFirstIndex ( TIM_TypeDef * TIMx )

Enable first index.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR FIDX LL_TIM_EnableFirstIndex
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5064 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection ( const TIM_TypeDef * TIMx )

Get actual index direction.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IDIR LL_TIM_GetIndexDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_INDEX_UP_DOWN
  • LL_TIM_INDEX_UP
  • LL_TIM_INDEX_DOWN

Definition at line 5051 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning ( const TIM_TypeDef * TIMx )

Get actual index positioning.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IPOS LL_TIM_GetIndexPositionning
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_INDEX_POSITION_DOWN_DOWN
  • LL_TIM_INDEX_POSITION_DOWN_UP
  • LL_TIM_INDEX_POSITION_UP_DOWN
  • LL_TIM_INDEX_POSITION_UP_UP
  • LL_TIM_INDEX_POSITION_DOWN
  • LL_TIM_INDEX_POSITION_UP

Definition at line 5129 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex ( const TIM_TypeDef * TIMx )

Indicate whether encoder index is enabled.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IE LL_TIM_IsEnabledEncoderIndex
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5018 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex ( const TIM_TypeDef * TIMx )

Indicates whether first index is enabled.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR FIDX LL_TIM_IsEnabledFirstIndex
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5090 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetIndexDirection | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | IndexDirection
 | ) |  |

Set index direction.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IDIR LL_TIM_SetIndexDirection
Parameters:
TIMx Timer instance
IndexDirection This parameter can be one of the following values:
  • LL_TIM_INDEX_UP_DOWN
  • LL_TIM_INDEX_UP
  • LL_TIM_INDEX_DOWN
Return values:
None

Definition at line 5035 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetIndexPositionning | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | IndexPositionning
 | ) |  |

Set index positioning.

Note:
Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an index input.
Reference Manual to LL API cross reference:
ECR IPOS LL_TIM_SetIndexPositionning
Parameters:
TIMx Timer instance
IndexPositionning This parameter can be one of the following values:
  • LL_TIM_INDEX_POSITION_DOWN_DOWN
  • LL_TIM_INDEX_POSITION_DOWN_UP
  • LL_TIM_INDEX_POSITION_UP_DOWN
  • LL_TIM_INDEX_POSITION_UP_UP
  • LL_TIM_INDEX_POSITION_DOWN
  • LL_TIM_INDEX_POSITION_UP
Return values:
None

Definition at line 5110 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_EnableHSE32 (TIM_TypeDef *TIMx)
Enable request for HSE/32 clock used for TISEL remap.
__STATIC_INLINE void | LL_TIM_DisableHSE32 (TIM_TypeDef *TIMx)
Disable request for HSE/32 clock used for TISEL remap.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledHSE32 (const TIM_TypeDef *TIMx)
Indicate whether request for HSE/32 clock is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableHSE32 ( TIM_TypeDef * TIMx )

Disable request for HSE/32 clock used for TISEL remap.

Note:
Only TIM16 and TIM17 support HSE/32 remap
Reference Manual to LL API cross reference:
OR HSE32EN LL_TIM_DisableHSE32
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5390 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableHSE32 ( TIM_TypeDef * TIMx )

Enable request for HSE/32 clock used for TISEL remap.

Note:
Only TIM16 and TIM17 support HSE/32 remap
Reference Manual to LL API cross reference:
OR HSE32EN LL_TIM_EnableHSE32
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5378 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32 ( const TIM_TypeDef * TIMx )

Indicate whether request for HSE/32 clock is enabled.

Note:
Only TIM16 and TIM17 support HSE/32 remap
Reference Manual to LL API cross reference:
OR HSE32EN LL_TIM_IsEnabledHSE32
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5402 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped.
Reference Manual to LL API cross reference:
TIM1_TISEL TI1SEL LL_TIM_SetRemap
TIM2_TISEL TI1SEL LL_TIM_SetRemap
TIM2_TISEL TI2SEL LL_TIM_SetRemap
TIM2_TISEL TI3SEL LL_TIM_SetRemap
TIM2_TISEL TI4SEL LL_TIM_SetRemap
TIM3_TISEL TI1SEL LL_TIM_SetRemap
TIM3_TISEL TI2SEL LL_TIM_SetRemap
TIM3_TISEL TI3SEL LL_TIM_SetRemap
TIM4_TISEL TI1SEL LL_TIM_SetRemap
TIM4_TISEL TI2SEL LL_TIM_SetRemap
TIM4_TISEL TI3SEL LL_TIM_SetRemap
TIM4_TISEL TI4SEL LL_TIM_SetRemap
TIM5_TISEL TI1SEL LL_TIM_SetRemap
TIM5_TISEL TI2SEL LL_TIM_SetRemap
TIM8_TISEL TI1SEL LL_TIM_SetRemap
TIM15_TISEL TI1SEL LL_TIM_SetRemap
TIM15_TISEL TI2SEL LL_TIM_SetRemap
TIM16_TISEL TI1SEL LL_TIM_SetRemap
TIM17_TISEL TI1SEL LL_TIM_SetRemap
TIM20_TISEL TI1SEL LL_TIM_SetRemap
Parameters:
TIMx | Timer instance
Remap | Remap param depends on the TIMx. Description available only in CHM version of the User Manual (not in .pdf). Otherwise see Reference Manual description of TISEL registers.

Below description summarizes "Timer Instance" and "Remap" param combinations:

TIM1: one of the following values

  • LL_TIM_TIM1_TI1_RMP_GPIO
  • LL_TIM_TIM1_TI1_RMP_COMP1
  • LL_TIM_TIM1_TI1_RMP_COMP2
  • LL_TIM_TIM1_TI1_RMP_COMP3
  • LL_TIM_TIM1_TI1_RMP_COMP4

TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM2_TI1_RMP_GPIO
  • LL_TIM_TIM2_TI1_RMP_COMP1
  • LL_TIM_TIM2_TI1_RMP_COMP2
  • LL_TIM_TIM2_TI1_RMP_COMP3
  • LL_TIM_TIM2_TI1_RMP_COMP4
  • LL_TIM_TIM2_TI1_RMP_COMP5 (*)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM2_TI2_RMP_GPIO
  • LL_TIM_TIM2_TI2_RMP_COMP1
  • LL_TIM_TIM2_TI2_RMP_COMP2
  • LL_TIM_TIM2_TI2_RMP_COMP3
  • LL_TIM_TIM2_TI2_RMP_COMP4
  • LL_TIM_TIM2_TI2_RMP_COMP6 (*)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM2_TI3_RMP_GPIO
  • LL_TIM_TIM2_TI3_RMP_COMP4

. . TI4_RMP can be one of the following values

  • LL_TIM_TIM2_TI4_RMP_GPIO
  • LL_TIM_TIM2_TI4_RMP_COMP1
  • LL_TIM_TIM2_TI4_RMP_COMP2

TIM3: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM3_TI1_RMP_GPIO
  • LL_TIM_TIM3_TI1_RMP_COMP1
  • LL_TIM_TIM3_TI1_RMP_COMP2
  • LL_TIM_TIM3_TI1_RMP_COMP3
  • LL_TIM_TIM3_TI1_RMP_COMP4
  • LL_TIM_TIM3_TI1_RMP_COMP5 (*)
  • LL_TIM_TIM3_TI1_RMP_COMP6 (*)
  • LL_TIM_TIM3_TI1_RMP_COMP7 (*)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM3_TI2_RMP_GPIO
  • LL_TIM_TIM3_TI2_RMP_COMP1
  • LL_TIM_TIM3_TI2_RMP_COMP2
  • LL_TIM_TIM3_TI2_RMP_COMP3
  • LL_TIM_TIM3_TI2_RMP_COMP4
  • LL_TIM_TIM3_TI2_RMP_COMP5 (*)
  • LL_TIM_TIM3_TI2_RMP_COMP6 (*)
  • LL_TIM_TIM3_TI2_RMP_COMP7 (*)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM3_TI3_RMP_GPIO
  • LL_TIM_TIM3_TI3_RMP_COMP3

TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM4_TI1_RMP_GPIO
  • LL_TIM_TIM4_TI1_RMP_COMP1
  • LL_TIM_TIM4_TI1_RMP_COMP2
  • LL_TIM_TIM4_TI1_RMP_COMP3
  • LL_TIM_TIM4_TI1_RMP_COMP4
  • LL_TIM_TIM4_TI1_RMP_COMP5 (*)
  • LL_TIM_TIM4_TI1_RMP_COMP6 (*)
  • LL_TIM_TIM4_TI1_RMP_COMP7 (*)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM4_TI2_RMP_GPIO
  • LL_TIM_TIM4_TI2_RMP_COMP1
  • LL_TIM_TIM4_TI2_RMP_COMP2
  • LL_TIM_TIM4_TI2_RMP_COMP3
  • LL_TIM_TIM4_TI2_RMP_COMP4
  • LL_TIM_TIM4_TI2_RMP_COMP5 (*)
  • LL_TIM_TIM4_TI2_RMP_COMP6 (*)
  • LL_TIM_TIM4_TI2_RMP_COMP7 (*)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM4_TI3_RMP_GPIO
  • LL_TIM_TIM4_TI3_RMP_COMP5 (*)

. . TI4_RMP can be one of the following values

  • LL_TIM_TIM4_TI4_RMP_GPIO
  • LL_TIM_TIM4_TI4_RMP_COMP6 (*)

TIM5: any combination of TI1_RMP and TI2_RMP where (**)

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM5_TI1_RMP_GPIO (*)
  • LL_TIM_TIM5_TI1_RMP_LSI (*)
  • LL_TIM_TIM5_TI1_RMP_LSE (*)
  • LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
  • LL_TIM_TIM5_TI1_RMP_COMP1 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP2 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP3 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP4 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP5 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP6 (*)
  • LL_TIM_TIM5_TI1_RMP_COMP7 (*)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM5_TI2_RMP_GPIO (*)
  • LL_TIM_TIM5_TI2_RMP_COMP1 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP2 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP3 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP4 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP5 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP6 (*)
  • LL_TIM_TIM5_TI2_RMP_COMP7 (*)

TIM8: one of the following values

  • LL_TIM_TIM8_TI1_RMP_GPIO
  • LL_TIM_TIM8_TI1_RMP_COMP1
  • LL_TIM_TIM8_TI1_RMP_COMP2
  • LL_TIM_TIM8_TI1_RMP_COMP3
  • LL_TIM_TIM8_TI1_RMP_COMP4

TIM15: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM15_TI1_RMP_GPIO
  • LL_TIM_TIM15_TI1_RMP_LSE
  • LL_TIM_TIM15_TI1_RMP_COMP1
  • LL_TIM_TIM15_TI1_RMP_COMP2
  • LL_TIM_TIM15_TI1_RMP_COMP5 (*)
  • LL_TIM_TIM15_TI1_RMP_COMP7 (*)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM15_TI2_RMP_GPIO
  • LL_TIM_TIM15_TI2_RMP_COMP2
  • LL_TIM_TIM15_TI2_RMP_COMP3
  • LL_TIM_TIM15_TI2_RMP_COMP6 (*)
  • LL_TIM_TIM15_TI2_RMP_COMP7 (*)

TIM16: one of the following values

  • LL_TIM_TIM16_TI1_RMP_GPIO
  • LL_TIM_TIM16_TI1_RMP_COMP6 (*)
  • LL_TIM_TIM16_TI1_RMP_MCO
  • LL_TIM_TIM16_TI1_RMP_HSE_32
  • LL_TIM_TIM16_TI1_RMP_RTC_WK
  • LL_TIM_TIM16_TI1_RMP_LSE
  • LL_TIM_TIM16_TI1_RMP_LSI

TIM17: one of the following values

  • LL_TIM_TIM17_TI1_RMP_GPIO
  • LL_TIM_TIM17_TI1_RMP_COMP5 (*)
  • LL_TIM_TIM17_TI1_RMP_MCO
  • LL_TIM_TIM17_TI1_RMP_HSE_32
  • LL_TIM_TIM17_TI1_RMP_RTC_WK
  • LL_TIM_TIM17_TI1_RMP_LSE
  • LL_TIM_TIM17_TI1_RMP_LSI

TIM20: one of the following values (**)

  • LL_TIM_TIM20_TI1_RMP_GPIO (*)
  • LL_TIM_TIM20_TI1_RMP_COMP1 (*)
  • LL_TIM_TIM20_TI1_RMP_COMP2 (*)
  • LL_TIM_TIM20_TI1_RMP_COMP3 (*)
  • LL_TIM_TIM20_TI1_RMP_COMP4 (*)

(*) Value not defined in all devices.
(**) Register not available in all devices.

Return values:
None

Definition at line 5366 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OCREF_Clear_Management

Functions
OCREF_Clear_Management
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.

Function Documentation

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OCRefClearInputSource
 | ) |  |

Set the OCREF clear input source.

Note:
The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
This function can only be used in Output compare and PWM modes.
Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether or not a timer instance can configure OCREF clear input source.
Reference Manual to LL API cross reference:
SMCR OCCS LL_TIM_SetOCRefClearInputSource
Reference Manual to LL API cross reference:
AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
Parameters:
TIMx Timer instance
OCRefClearInputSource This parameter can be one of the following values:
  • LL_TIM_OCREF_CLR_INT_ETR
  • LL_TIM_OCREF_CLR_INT_COMP1
  • LL_TIM_OCREF_CLR_INT_COMP2
  • LL_TIM_OCREF_CLR_INT_COMP3
  • LL_TIM_OCREF_CLR_INT_COMP4
  • LL_TIM_OCREF_CLR_INT_COMP5 (*)
  • LL_TIM_OCREF_CLR_INT_COMP6 (*)
  • LL_TIM_OCREF_CLR_INT_COMP7 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 5436 of file stm32g4xx_ll_tim.h.

References OCREF_CLEAR_SELECT_Msk, and OCREF_CLEAR_SELECT_Pos.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (const TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (const TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (const TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (const TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (const TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (const TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TERR (TIM_TypeDef *TIMx)
Clear the transition error interrupt flag (TERRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TERR (const TIM_TypeDef *TIMx)
Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_IERR (TIM_TypeDef *TIMx)
Clear the index error interrupt flag (IERRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_IERR (const TIM_TypeDef *TIMx)
Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_DIR (TIM_TypeDef *TIMx)
Clear the direction change interrupt flag (DIRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_DIR (const TIM_TypeDef *TIMx)
Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_IDX (TIM_TypeDef *TIMx)
Clear the index interrupt flag (IDXF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_IDX (const TIM_TypeDef *TIMx)
Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5653 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_BRK2 ( TIM_TypeDef * TIMx )

Clear the break 2 interrupt flag (B2IF).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_ClearFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5675 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5477 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5697 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5499 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5720 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5521 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5743 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5543 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5766 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC5 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 5 interrupt flag (CC5F).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_ClearFlag_CC5
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5565 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC6 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 6 interrupt flag (CC6F).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_ClearFlag_CC6
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5587 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5609 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_DIR ( TIM_TypeDef * TIMx )

Clear the direction change interrupt flag (DIRF).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
SR DIRF LL_TIM_ClearFlag_DIR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5865 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_IDX ( TIM_TypeDef * TIMx )

Clear the index interrupt flag (IDXF).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
SR IDXF LL_TIM_ClearFlag_IDX
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5891 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_IERR ( TIM_TypeDef * TIMx )

Clear the index error interrupt flag (IERRF).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
SR IERRF LL_TIM_ClearFlag_IERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5839 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK ( TIM_TypeDef * TIMx )

Clear the system break interrupt flag (SBIF).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_ClearFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5789 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TERR ( TIM_TypeDef * TIMx )

Clear the transition error interrupt flag (TERRF).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
SR TERRF LL_TIM_ClearFlag_TERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5813 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5631 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5455 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( const TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5664 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2 ( const TIM_TypeDef * TIMx )

Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_IsActiveFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5686 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5488 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5709 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5510 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5732 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5532 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5755 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5554 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5778 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_IsActiveFlag_CC5
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5576 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_IsActiveFlag_CC6
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5598 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( const TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5620 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR ( const TIM_TypeDef * TIMx )

Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
SR DIRF LL_TIM_IsActiveFlag_DIR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5878 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX ( const TIM_TypeDef * TIMx )

Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
SR IDXF LL_TIM_IsActiveFlag_IDX
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5904 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR ( const TIM_TypeDef * TIMx )

Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
SR IERRF LL_TIM_IsActiveFlag_IERR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5852 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK ( const TIM_TypeDef * TIMx )

Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_IsActiveFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5800 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR ( const TIM_TypeDef * TIMx )

Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
SR TERRF LL_TIM_IsActiveFlag_TERR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5826 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( const TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5642 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( const TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5466 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (const TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TERR (TIM_TypeDef *TIMx)
Enable transition error interrupt (TERRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TERR (TIM_TypeDef *TIMx)
Disable transition error interrupt (TERRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TERR (const TIM_TypeDef *TIMx)
Indicates whether the transition error interrupt (TERRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_IERR (TIM_TypeDef *TIMx)
Enable index error interrupt (IERRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_IERR (TIM_TypeDef *TIMx)
Disable index error interrupt (IERRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_IERR (const TIM_TypeDef *TIMx)
Indicates whether the index error interrupt (IERRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_DIR (TIM_TypeDef *TIMx)
Enable direction change interrupt (DIRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_DIR (TIM_TypeDef *TIMx)
Disable direction change interrupt (DIRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_DIR (const TIM_TypeDef *TIMx)
Indicates whether the direction change interrupt (DIRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_IDX (TIM_TypeDef *TIMx)
Enable index interrupt (IDXIE).
__STATIC_INLINE void | LL_TIM_DisableIT_IDX (TIM_TypeDef *TIMx)
Disable index interrupt (IDXIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_IDX (const TIM_TypeDef *TIMx)
Indicates whether the index interrupt (IDXIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6163 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5965 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5998 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6031 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6064 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6097 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_DIR ( TIM_TypeDef * TIMx )

Disable direction change interrupt (DIRIE).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER DIRIE LL_TIM_DisableIT_DIR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6278 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_IDX ( TIM_TypeDef * TIMx )

Disable index interrupt (IDXIE).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER IDXIE LL_TIM_DisableIT_IDX
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6317 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_IERR ( TIM_TypeDef * TIMx )

Disable index error interrupt (IERRIE).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER IERRIE LL_TIM_DisableIT_IERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6239 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TERR ( TIM_TypeDef * TIMx )

Disable transition error interrupt (TERRIE).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER TERRIE LL_TIM_DisableIT_TERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6200 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6130 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5932 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6152 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5954 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5987 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6020 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6053 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6086 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_DIR ( TIM_TypeDef * TIMx )

Enable direction change interrupt (DIRIE).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER DIRIE LL_TIM_EnableIT_DIR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6265 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_IDX ( TIM_TypeDef * TIMx )

Enable index interrupt (IDXIE).

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER IDXIE LL_TIM_EnableIT_IDX
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6304 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_IERR ( TIM_TypeDef * TIMx )

Enable index error interrupt (IERRIE).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER IERRIE LL_TIM_EnableIT_IERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6226 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TERR ( TIM_TypeDef * TIMx )

Enable transition error interrupt (TERRIE).

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER TERRIE LL_TIM_EnableIT_TERR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6187 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6119 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5921 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( const TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6174 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5976 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6009 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6042 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6075 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( const TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6108 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR ( const TIM_TypeDef * TIMx )

Indicates whether the direction change interrupt (DIRIE) is enabled.

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER DIRIE LL_TIM_IsEnabledIT_DIR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6291 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX ( const TIM_TypeDef * TIMx )

Indicates whether the index interrupt (IDXIE) is enabled.

Note:
Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder interrupt management.
Reference Manual to LL API cross reference:
DIER IDXIE LL_TIM_IsEnabledIT_IDX
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6330 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR ( const TIM_TypeDef * TIMx )

Indicates whether the index error interrupt (IERRIE) is enabled.

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER IERRIE LL_TIM_IsEnabledIT_IERR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6252 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR ( const TIM_TypeDef * TIMx )

Indicates whether the transition error interrupt (TERRIE) is enabled.

Note:
Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides encoder error management.
Reference Manual to LL API cross reference:
DIER TERRIE LL_TIM_IsEnabledIT_TERR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6213 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( const TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6141 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( const TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5943 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Management

Functions
DMA Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6392 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6425 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6458 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6491 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6524 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6557 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6359 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6381 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6414 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6447 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6480 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6513 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6546 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6348 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6403 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6436 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6469 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6502 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( const TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6535 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( const TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6568 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( const TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 6370 of file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6663 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2 ( TIM_TypeDef * TIMx )

Generate break 2 event.

Reference Manual to LL API cross reference:
EGR B2G LL_TIM_GenerateEvent_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6674 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6597 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6608 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6619 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6630 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6641 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6652 of file stm32g4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 6586 of file stm32g4xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (const TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 737 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2AFMode, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakAFMode, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK2_AFMODE, IS_LL_TIM_BREAK2_FILTER, IS_LL_TIM_BREAK2_POLARITY, IS_LL_TIM_BREAK2_STATE, IS_LL_TIM_BREAK_AFMODE, IS_LL_TIM_BREAK_FILTER, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 702 of file stm32g4xx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2AFMode, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakAFMode, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK2_AFMODE_INPUT, LL_TIM_BREAK2_DISABLE, LL_TIM_BREAK2_FILTER_FDIV1, LL_TIM_BREAK2_POLARITY_LOW, LL_TIM_BREAK_AFMODE_INPUT, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_FILTER_FDIV1, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( const TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 230 of file stm32g4xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_PERIPH_TIM6, LL_APB1_GRP1_PERIPH_TIM7, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, LL_APB2_GRP1_PERIPH_TIM15, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, LL_APB2_GRP1_PERIPH_TIM8, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 530 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 507 of file stm32g4xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used when TIMx operates in Hall sensor interface mode.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 623 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 593 of file stm32g4xx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 476 of file stm32g4xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 453 of file stm32g4xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 334 of file stm32g4xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 415 of file stm32g4xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6, OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 386 of file stm32g4xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 315 of file stm32g4xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Private Constants

UCPD Private Constants
UCPD
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Private Macros

UCPD Private Macros
UCPD
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_UCPD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UCPD_InitTypeDef Struct Reference
UCPD Exported Init structure

UCPD Init structures definition. More...

#include <stm32g4xx_ll_ucpd.h>

Data Fields

uint32_t | psc_ucpdclk
uint32_t | transwin
uint32_t | IfrGap
uint32_t | HbitClockDiv

Detailed Description

UCPD Init structures definition.

Definition at line 53 of file stm32g4xx_ll_ucpd.h.

Field Documentation

uint32_t LL_UCPD_InitTypeDef::HbitClockDiv

Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : "UCPD1_CLK". This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. This feature can be modified using function LL_UCPD_SetHbitClockDiv().

Definition at line 73 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::IfrGap

Specify the definition of the clock divider (minus 1) in order to generate tInterframeGap from the peripheral clock. This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This feature can be modified afterwards using function LL_UCPD_SetIfrGap().

Definition at line 67 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::psc_ucpdclk

Specify the prescaler for the UCPD clock. This parameter can be a value of prescaler for UCPDCLK. This feature can be modified afterwards using function LL_UCPD_SetPSCClk().

Definition at line 55 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::transwin

Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us). This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This value can be modified afterwards using function LL_UCPD_SetTransWin().

Definition at line 60 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_ucpd.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
UCPD Exported Constants

Flags defines which can be used with LL_ucpd_ReadReg function. More...

Defines

#define | LL_UCPD_SR_TXIS UCPD_SR_TXIS
#define | LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC
#define | LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT
#define | LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT
#define | LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC
#define | LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT
#define | LL_UCPD_SR_TXUND UCPD_SR_TXUND
#define | LL_UCPD_SR_RXNE UCPD_SR_RXNE
#define | LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET
#define | LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET
#define | LL_UCPD_SR_RXOVR UCPD_SR_RXOVR
#define | LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND
#define | LL_UCPD_SR_RXERR UCPD_SR_RXERR
#define | LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1
#define | LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2
#define | LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1
#define | LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2
#define | LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT

Detailed Description

Flags defines which can be used with LL_ucpd_ReadReg function.

Define Documentation

#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT

Fast Role Swap detection event

Definition at line 113 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC

HRST discarded interrupt

Definition at line 100 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT

HRST sent interrupt

Definition at line 101 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXERR UCPD_SR_RXERR

Rx error

Definition at line 108 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET

Rx Hard Reset detect interrupt

Definition at line 105 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND

Rx message received

Definition at line 107 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXNE UCPD_SR_RXNE

Receive data register not empty interrupt

Definition at line 103 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET

Rx ordered set (4 K-codes) detected interrupt

Definition at line 104 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR

Rx data overflow interrupt

Definition at line 106 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TXIS UCPD_SR_TXIS

Transmit interrupt status

Definition at line 96 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT

Transmit message abort interrupt

Definition at line 99 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC

Transmit message discarded interrupt

Definition at line 97 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT

Transmit message sent interrupt

Definition at line 98 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TXUND UCPD_SR_TXUND

Tx data underrun condition interrupt

Definition at line 102 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1

Status of DC level on CC1 pin

Definition at line 111 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2

Status of DC level on CC2 pin

Definition at line 112 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1

Type C voltage level event on CC1

Definition at line 109 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2

Type C voltage level event on CC2

Definition at line 110 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
UCPD Exported Constants

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions. More...

Defines

#define | LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE
#define | LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE
#define | LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE
#define | LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE
#define | LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE
#define | LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE
#define | LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE
#define | LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE
#define | LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE
#define | LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE
#define | LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE
#define | LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE
#define | LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE
#define | LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE
#define | LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE

Detailed Description

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions.

Define Documentation

#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE

Enable fast Role Swap detection event

Definition at line 137 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE

Enable HRST discarded interrupt

Definition at line 127 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE

Enable HRST sent interrupt

Definition at line 128 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE

Enable Rx Hard Reset detect interrupt

Definition at line 132 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE

Enable Rx message received

Definition at line 134 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE

Enable Receive data register not empty interrupt

Definition at line 130 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE

Enable Rx ordered set (4 K-codes) detected interrupt

Definition at line 131 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE

Enable Rx data overflow interrupt

Definition at line 133 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE

Enable transmit interrupt status

Definition at line 123 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE

Enable transmit message abort interrupt

Definition at line 126 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE

Enable transmit message discarded interrupt

Definition at line 124 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE

Enable transmit message sent interrupt

Definition at line 125 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE

Enable tx data underrun condition interrupt

Definition at line 129 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE

Enable Type C voltage level event on CC1

Definition at line 135 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE

Enable Type C voltage level event on CC2

Definition at line 136 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Ordered sets value

Defines
Ordered sets value
UCPD Exported Constants

definition of the usual Ordered sets More...

Defines

#define | LL_UCPD_SYNC1 0x18u
#define | LL_UCPD_SYNC2 0x11u
#define | LL_UCPD_SYNC3 0x06u
#define | LL_UCPD_RST1 0x07u
#define | LL_UCPD_RST2 0x19u
#define | LL_UCPD_EOP 0x0Du
#define | LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
#define | LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))

Detailed Description

definition of the usual Ordered sets

Define Documentation

#define LL_UCPD_EOP 0x0Du

K-code for EOP End of Packet

Definition at line 152 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))

Cable Reset Ordered set coding

Definition at line 158 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))

Hard Reset Ordered set coding

Definition at line 157 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))

SOP Ordered set coding

Definition at line 154 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))

SOP' Ordered set coding

Definition at line 155 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))

SOP' Debug Ordered set coding

Definition at line 159 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))

SOP'' Ordered set coding

Definition at line 156 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))

SOP'' Debug Ordered set coding

Definition at line 160 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RST1 0x07u

K-code for Hard Reset #1

Definition at line 150 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RST2 0x19u

K-code for Hard Reset #2

Definition at line 151 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SYNC1 0x18u

K-code for Startsynch #1

Definition at line 147 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SYNC2 0x11u

K-code for Startsynch #2

Definition at line 148 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SYNC3 0x06u

K-code for Startsynch #3

Definition at line 149 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Role Mode

Defines
Role Mode
UCPD Exported Constants

Defines

#define | LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE
#define | LL_UCPD_ROLE_SRC 0x0U

Define Documentation

#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE

Mode SNK Rd

Definition at line 168 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ROLE_SRC 0x0U

Mode SRC Rp

Definition at line 169 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Resistor value

Defines
Resistor value
UCPD Exported Constants

Defines

#define | LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0
#define | LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1
#define | LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE
#define | LL_UCPD_RESISTOR_NONE 0x0U

Define Documentation

#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1

Rp 1.5 A

Definition at line 178 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE

Rp 3.0 A

Definition at line 179 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0

Rp default

Definition at line 177 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_NONE 0x0U

No resistor

Definition at line 180 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ordered set configuration

Defines
ordered set configuration
UCPD Exported Constants

Defines

#define | LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
#define | LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
#define | LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
#define | LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
#define | LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
#define | LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
#define | LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
#define | LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
#define | LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8

Define Documentation

#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4

Cable Reset Ordered set detection enabled

Definition at line 192 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3

Hard Reset Ordered set detection enabled

Definition at line 191 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0

SOP Ordered set detection enabled

Definition at line 188 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1

SOP' Ordered set detection enabled

Definition at line 189 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5

SOP' Debug Ordered set detection enabled

Definition at line 193 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2

SOP'' Ordered set detection enabled

Definition at line 190 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6

SOP'' Debug Ordered set detection enabled

Definition at line 194 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7

SOP extension#1 Ordered set detection enabled

Definition at line 195 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8

SOP extension#2 Ordered set detection enabled

Definition at line 196 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CCx event

Defines
CCx event
UCPD Exported Constants

Defines

#define | LL_UCPD_SNK_CC1_VOPEN 0x00u
#define | LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
#define | LL_UCPD_SNK_CC2_VOPEN 0x00u
#define | LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
#define | LL_UCPD_SRC_CC1_VRA 0x0U
#define | LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SRC_CC2_VRA 0x0U
#define | LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1

Define Documentation

#define LL_UCPD_SNK_CC1_VOPEN 0x00u

CC1 Sink Open state

Definition at line 204 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0

CC1 Sink vRP default state

Definition at line 205 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1

CC1 Sink vRP 1.5A state

Definition at line 206 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)

CC1 Sink vRP 3.0A state

Definition at line 207 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VOPEN 0x00u

CC2 Sink Open state

Definition at line 209 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0

CC2 Sink vRP default state

Definition at line 210 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1

CC2 Sink vRP 1.5A state

Definition at line 211 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)

CC2 Sink vRP 3.0A state

Definition at line 212 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1

CC1 Source Open state

Definition at line 216 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_VRA 0x0U

CC1 Source vRA state

Definition at line 214 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0

CC1 Source vRD state

Definition at line 215 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1

CC2 Source Open state

Definition at line 220 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_VRA 0x0U

CC2 Source vRA state

Definition at line 218 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0

CC2 Source vRD state

Definition at line 219 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: prescaler for UCPDCLK

Defines
prescaler for UCPDCLK
UCPD Exported Constants

Defines

#define | LL_UCPD_PSC_DIV1 0x0u
#define | LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
#define | LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
#define | LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
#define | LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2

Define Documentation

#define LL_UCPD_PSC_DIV1 0x0u

Bypass pre-scaling / divide by 1

Definition at line 228 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2

Pre-scale clock by dividing by 16

Definition at line 232 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0

Pre-scale clock by dividing by 2

Definition at line 229 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_StructInit().

#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1

Pre-scale clock by dividing by 4

Definition at line 230 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)

Pre-scale clock by dividing by 8

Definition at line 231 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CC pin enable

Defines
CC pin enable
UCPD Exported Constants

Defines

#define | LL_UCPD_CCENABLE_NONE 0x0U
#define | LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
#define | LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
#define | LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)

Define Documentation

#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0

Controls apply to only CC1

Definition at line 241 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)

Controls apply to both CC1 and CC2 (normal usage for sink/source)

Definition at line 243 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1

Controls apply to only CC1

Definition at line 242 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_NONE 0x0U

Neither PHY is activated (e.g. disabled state of source)

Definition at line 240 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CC pin selection

Defines
CC pin selection
UCPD Exported Constants

Defines

#define | LL_UCPD_CCPIN_CC1 0x0U
#define | LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL

Define Documentation

#define LL_UCPD_CCPIN_CC1 0x0U

Use CC1 IO for power delivery communication

Definition at line 251 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL

Use CC2 IO for power delivery communication

Definition at line 252 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Receiver mode

Defines
Receiver mode
UCPD Exported Constants

Defines

#define | LL_UCPD_RXMODE_NORMAL 0x0U
#define | LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE

Define Documentation

#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE

BIST receive mode (BIST Test Data Mode)

Definition at line 261 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXMODE_NORMAL 0x0U

Normal receive mode

Definition at line 260 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Type of Tx packet

Defines
Type of Tx packet
UCPD Exported Constants

Defines

#define | LL_UCPD_TXMODE_NORMAL 0x0U
#define | LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
#define | LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1

Define Documentation

#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1

Trigger a BIST test sequence send (BIST Carrier Mode 2)

Definition at line 271 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0

Trigger a the transfer of a Cable Reset sequence

Definition at line 270 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_TXMODE_NORMAL 0x0U

Initiate the transfer of a Tx message

Definition at line 269 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Rx ordered set code detected

Defines
Rx ordered set code detected
UCPD Exported Constants

Defines

#define | LL_UCPD_RXORDSET_SOP 0x0U
#define | LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
#define | LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
#define | LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
#define | LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)

Define Documentation

#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)

Cable Reset code detected in receiver

Definition at line 284 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP 0x0U

SOP code detected in receiver

Definition at line 279 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0

SOP' code detected in receiver

Definition at line 280 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)

SOP' Debug code detected in receiver

Definition at line 282 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1

SOP'' code detected in receiver

Definition at line 281 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2

SOP'' Debug code detected in receiver

Definition at line 283 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)

SOP extension#1 code detected in receiver

Definition at line 285 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)

SOP extension#2 code detected in receiver

Definition at line 286 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
UCPD Exported Macros

Defines

#define | LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in UCPD register.
#define | LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in UCPD register.

Define Documentation

#define LL_UCPD_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in UCPD register.

Parameters:
__INSTANCE__ | UCPD Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 319 of file stm32g4xx_ll_ucpd.h.

#define LL_UCPD_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in UCPD register.

Parameters:
__INSTANCE__ | UCPD Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 311 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CFG1 register

Functions
CFG1 register
Configuration

Functions

__STATIC_INLINE void | LL_UCPD_Enable (UCPD_TypeDef *UCPDx)
Enable UCPD peripheral.
__STATIC_INLINE void | LL_UCPD_Disable (UCPD_TypeDef *UCPDx)
Disable UCPD peripheral.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabled (UCPD_TypeDef const *const UCPDx)
Check if UCPD peripheral is enabled.
__STATIC_INLINE void | LL_UCPD_SetRxOrderSet (UCPD_TypeDef *UCPDx, uint32_t OrderSet)
Set the receiver ordered set detection enable.
__STATIC_INLINE void | LL_UCPD_SetPSCClk (UCPD_TypeDef *UCPDx, uint32_t Psc)
Set the prescaler for ucpd clock.
__STATIC_INLINE void | LL_UCPD_SetTransWin (UCPD_TypeDef *UCPDx, uint32_t TransWin)
Set the number of cycles (minus 1) of the half bit clock.
__STATIC_INLINE void | LL_UCPD_SetIfrGap (UCPD_TypeDef *UCPDx, uint32_t IfrGap)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_SetHbitClockDiv (UCPD_TypeDef *UCPDx, uint32_t HbitClock)
Set the clock divider value to generate an interframe gap.

Function Documentation

__STATIC_INLINE void LL_UCPD_Disable ( UCPD_TypeDef * UCPDx )

Disable UCPD peripheral.

Note:
When disabling the UCPD, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 358 of file stm32g4xx_ll_ucpd.h.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

__STATIC_INLINE void LL_UCPD_Enable ( UCPD_TypeDef * UCPDx )

Enable UCPD peripheral.

Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 346 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnabled ( UCPD_TypeDef const *const UCPDx )

Check if UCPD peripheral is enabled.

Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_IsEnabled
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 369 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetHbitClockDiv | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | HbitClock
 | ) |  |

Set the clock divider value to generate an interframe gap.

Reference Manual to LL API cross reference:
CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
Parameters:
UCPDx | UCPD Instance
HbitClock | a value between Min_Data=0x0 and Max_Data=0x3F
Return values:
None

Definition at line 443 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetIfrGap | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | IfrGap
 | ) |  |

Set the clock divider value to generate an interframe gap.

Reference Manual to LL API cross reference:
CFG1 IFRGAP LL_UCPD_SetIfrGap
Parameters:
UCPDx | UCPD Instance
IfrGap | a value between Min_Data=0x1 and Max_Data=0x1F
Return values:
None

Definition at line 431 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetPSCClk | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | Psc
 | ) |  |

Set the prescaler for ucpd clock.

Reference Manual to LL API cross reference:
CFG1 UCPDCLK LL_UCPD_SetPSCClk
Parameters:
UCPDx UCPD Instance
Psc This parameter can be one of the following values:
  • LL_UCPD_PSC_DIV1
  • LL_UCPD_PSC_DIV2
  • LL_UCPD_PSC_DIV4
  • LL_UCPD_PSC_DIV8
  • LL_UCPD_PSC_DIV16
Return values:
None

Definition at line 407 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrderSet | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | OrderSet
 | ) |  |

Set the receiver ordered set detection enable.

Reference Manual to LL API cross reference:
CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
Parameters:
UCPDx UCPD Instance
OrderSet This parameter can be combination of the following values:
  • LL_UCPD_ORDERSET_SOP
  • LL_UCPD_ORDERSET_SOP1
  • LL_UCPD_ORDERSET_SOP2
  • LL_UCPD_ORDERSET_HARDRST
  • LL_UCPD_ORDERSET_CABLERST
  • LL_UCPD_ORDERSET_SOP1_DEBUG
  • LL_UCPD_ORDERSET_SOP2_DEBUG
  • LL_UCPD_ORDERSET_SOP_EXT1
  • LL_UCPD_ORDERSET_SOP_EXT2
Return values:
None

Definition at line 390 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetTransWin | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TransWin
 | ) |  |

Set the number of cycles (minus 1) of the half bit clock.

Reference Manual to LL API cross reference:
CFG1 TRANSWIN LL_UCPD_SetTransWin
Parameters:
UCPDx | UCPD Instance
TransWin | a value between Min_Data=0x1 and Max_Data=0x1F
Return values:
None

Definition at line 419 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CFG2 register

Functions
CFG2 register
Configuration

Functions

__STATIC_INLINE void | LL_UCPD_WakeUpEnable (UCPD_TypeDef *UCPDx)
Enable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_WakeUpDisable (UCPD_TypeDef *UCPDx)
Disable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_ForceClockEnable (UCPD_TypeDef *UCPDx)
Force clock enable.
__STATIC_INLINE void | LL_UCPD_ForceClockDisable (UCPD_TypeDef *UCPDx)
Force clock disable.
__STATIC_INLINE void | LL_UCPD_RxFilterEnable (UCPD_TypeDef *UCPDx)
RxFilter enable.
__STATIC_INLINE void | LL_UCPD_RxFilterDisable (UCPD_TypeDef *UCPDx)
RxFilter disable.

Function Documentation

__STATIC_INLINE void LL_UCPD_ForceClockDisable ( UCPD_TypeDef * UCPDx )

Force clock disable.

Reference Manual to LL API cross reference:
CFG2 FORCECLK LL_UCPD_ForceClockDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 495 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ForceClockEnable ( UCPD_TypeDef * UCPDx )

Force clock enable.

Reference Manual to LL API cross reference:
CFG2 FORCECLK LL_UCPD_ForceClockEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 484 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxFilterDisable ( UCPD_TypeDef * UCPDx )

RxFilter disable.

Reference Manual to LL API cross reference:
CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 517 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxFilterEnable ( UCPD_TypeDef * UCPDx )

RxFilter enable.

Reference Manual to LL API cross reference:
CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 506 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WakeUpDisable ( UCPD_TypeDef * UCPDx )

Disable the wakeup mode.

Reference Manual to LL API cross reference:
CFG2 WUPEN LL_UCPD_WakeUpDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 473 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WakeUpEnable ( UCPD_TypeDef * UCPDx )

Enable the wakeup mode.

Reference Manual to LL API cross reference:
CFG2 WUPEN LL_UCPD_WakeUpEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 462 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CR register

Functions
CR register
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 disable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeEnable (UCPD_TypeDef *UCPDx)
Source Vconn discharge enable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeDisable (UCPD_TypeDef *UCPDx)
Source Vconn discharge disable.
__STATIC_INLINE void | LL_UCPD_SignalFRSTX (UCPD_TypeDef *UCPDx)
Signal Fast Role Swap request.
__STATIC_INLINE void | LL_UCPD_FRSDetectionEnable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection enable.
__STATIC_INLINE void | LL_UCPD_FRSDetectionDisable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection disable.
__STATIC_INLINE void | LL_UCPD_SetccEnable (UCPD_TypeDef *UCPDx, uint32_t CCEnable)
Set cc enable.
__STATIC_INLINE void | LL_UCPD_SetSNKRole (UCPD_TypeDef *UCPDx)
Set UCPD SNK role.
__STATIC_INLINE void | LL_UCPD_SetSRCRole (UCPD_TypeDef *UCPDx)
Set UCPD SRC role.
__STATIC_INLINE uint32_t | LL_UCPD_GetRole (UCPD_TypeDef const *const UCPDx)
Get UCPD Role.
__STATIC_INLINE void | LL_UCPD_SetRpResistor (UCPD_TypeDef *UCPDx, uint32_t Resistor)
Set Rp resistor.
__STATIC_INLINE void | LL_UCPD_SetCCPin (UCPD_TypeDef *UCPDx, uint32_t CCPin)
Set CC pin.
__STATIC_INLINE void | LL_UCPD_RxEnable (UCPD_TypeDef *UCPDx)
Rx enable.
__STATIC_INLINE void | LL_UCPD_RxDisable (UCPD_TypeDef *UCPDx)
Rx disable.
__STATIC_INLINE void | LL_UCPD_SetRxMode (UCPD_TypeDef *UCPDx, uint32_t RxMode)
Set Rx mode.
__STATIC_INLINE void | LL_UCPD_SendHardReset (UCPD_TypeDef *UCPDx)
Send Hard Reset.
__STATIC_INLINE void | LL_UCPD_SendMessage (UCPD_TypeDef *UCPDx)
Send message.
__STATIC_INLINE void | LL_UCPD_SetTxMode (UCPD_TypeDef *UCPDx, uint32_t TxMode)
Set Tx mode.

Function Documentation

__STATIC_INLINE void LL_UCPD_FRSDetectionDisable ( UCPD_TypeDef * UCPDx )

Fast Role swap RX detection disable.

Reference Manual to LL API cross reference:
CR FRSRXEN LL_UCPD_FRSDetectionDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 627 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_FRSDetectionEnable ( UCPD_TypeDef * UCPDx )

Fast Role swap RX detection enable.

Reference Manual to LL API cross reference:
CR FRSRXEN LL_UCPD_FRSDetectionEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 616 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_GetRole ( UCPD_TypeDef const *const UCPDx )

Get UCPD Role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_GetRole
Parameters:
UCPDx UCPD Instance
Return values:
Returned value can be one of the following values:
  • LL_UCPD_ROLE_SNK
  • LL_UCPD_ROLE_SRC

Definition at line 678 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDisable ( UCPD_TypeDef * UCPDx )

Rx disable.

Reference Manual to LL API cross reference:
CR PHYRXEN LL_UCPD_RxDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 730 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxEnable ( UCPD_TypeDef * UCPDx )

Rx enable.

Reference Manual to LL API cross reference:
CR PHYRXEN LL_UCPD_RxEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 719 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SendHardReset ( UCPD_TypeDef * UCPDx )

Send Hard Reset.

Reference Manual to LL API cross reference:
CR TXHRST LL_UCPD_SendHardReset
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 755 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SendMessage ( UCPD_TypeDef * UCPDx )

Send message.

Reference Manual to LL API cross reference:
CR TXSEND LL_UCPD_SendMessage
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 766 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetccEnable | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | CCEnable
 | ) |  |

Set cc enable.

Reference Manual to LL API cross reference:
CR CC1VCONNEN LL_UCPD_SetccEnable
Parameters:
UCPDx UCPD Instance
CCEnable This parameter can be one of the following values:
  • LL_UCPD_CCENABLE_NONE
  • LL_UCPD_CCENABLE_CC1
  • LL_UCPD_CCENABLE_CC2
  • LL_UCPD_CCENABLE_CC1CC2
Return values:
None

Definition at line 643 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetCCPin | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | CCPin
 | ) |  |

Set CC pin.

Reference Manual to LL API cross reference:
CR PHYCCSEL LL_UCPD_SetCCPin
Parameters:
UCPDx UCPD Instance
CCPin This parameter can be one of the following values:
  • LL_UCPD_CCPIN_CC1
  • LL_UCPD_CCPIN_CC2
Return values:
None

Definition at line 708 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRpResistor | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | Resistor
 | ) |  |

Set Rp resistor.

Reference Manual to LL API cross reference:
CR ANASUBMODE LL_UCPD_SetRpResistor
Parameters:
UCPDx UCPD Instance
Resistor This parameter can be one of the following values:
  • LL_UCPD_RESISTOR_DEFAULT
  • LL_UCPD_RESISTOR_1_5A
  • LL_UCPD_RESISTOR_3_0A
  • LL_UCPD_RESISTOR_NONE
Return values:
None

Definition at line 694 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxMode | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | RxMode
 | ) |  |

Set Rx mode.

Reference Manual to LL API cross reference:
CR RXMODE LL_UCPD_SetRxMode
Parameters:
UCPDx UCPD Instance
RxMode This parameter can be one of the following values:
  • LL_UCPD_RXMODE_NORMAL
  • LL_UCPD_RXMODE_BIST_TEST_DATA
Return values:
None

Definition at line 744 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetSNKRole ( UCPD_TypeDef * UCPDx )

Set UCPD SNK role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_SetSNKRole
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 654 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetSRCRole ( UCPD_TypeDef * UCPDx )

Set UCPD SRC role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_SetSRCRole
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 665 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetTxMode | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxMode
 | ) |  |

Set Tx mode.

Reference Manual to LL API cross reference:
CR TXMODE LL_UCPD_SetTxMode
Parameters:
UCPDx UCPD Instance
TxMode This parameter can be one of the following values:
  • LL_UCPD_TXMODE_NORMAL
  • LL_UCPD_TXMODE_CABLE_RESET
  • LL_UCPD_TXMODE_BIST_CARRIER2
Return values:
None

Definition at line 781 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SignalFRSTX ( UCPD_TypeDef * UCPDx )

Signal Fast Role Swap request.

Reference Manual to LL API cross reference:
CR FRSTX LL_UCPD_VconnDischargeDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 605 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable ( UCPD_TypeDef * UCPDx )

Type C detector for CC1 disable.

Reference Manual to LL API cross reference:
CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 572 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable ( UCPD_TypeDef * UCPDx )

Type C detector for CC1 enable.

Reference Manual to LL API cross reference:
CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 561 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable ( UCPD_TypeDef * UCPDx )

Type C detector for CC2 disable.

Reference Manual to LL API cross reference:
CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 550 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable ( UCPD_TypeDef * UCPDx )

Type C detector for CC2 enable.

Reference Manual to LL API cross reference:
CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 539 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_VconnDischargeDisable ( UCPD_TypeDef * UCPDx )

Source Vconn discharge disable.

Reference Manual to LL API cross reference:
CR RDCH LL_UCPD_VconnDischargeDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 594 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_VconnDischargeEnable ( UCPD_TypeDef * UCPDx )

Source Vconn discharge enable.

Reference Manual to LL API cross reference:
CR RDCH LL_UCPD_VconnDischargeEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 583 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_EnableIT_FRS (UCPD_TypeDef *UCPDx)
Enable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Enable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Enable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Enable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOvr (UCPD_TypeDef *UCPDx)
Enable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxHRST (UCPD_TypeDef *UCPDx)
Enable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Enable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxNE (UCPD_TypeDef *UCPDx)
Enable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxUND (UCPD_TypeDef *UCPDx)
Enable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Enable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Enable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Enable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Enable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Enable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxIS (UCPD_TypeDef *UCPDx)
Enable Tx data receive interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_FRS (UCPD_TypeDef *UCPDx)
Disable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Disable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Disable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Disable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOvr (UCPD_TypeDef *UCPDx)
Disable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxHRST (UCPD_TypeDef *UCPDx)
Disable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Disable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxNE (UCPD_TypeDef *UCPDx)
Disable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxUND (UCPD_TypeDef *UCPDx)
Disable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Disable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Disable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Disable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Disable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Disable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxIS (UCPD_TypeDef *UCPDx)
Disable Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt enabled.

Function Documentation

__STATIC_INLINE void LL_UCPD_DisableIT_FRS ( UCPD_TypeDef * UCPDx )

Disable FRS interrupt.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_DisableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 965 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST ( UCPD_TypeDef * UCPDx )

Disable Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1020 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Disable Rx message end interrupt.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 998 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxNE ( UCPD_TypeDef * UCPDx )

Disable Rx non empty interrupt.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_DisableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1042 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet ( UCPD_TypeDef * UCPDx )

Disable Rx orderset interrupt.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1031 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr ( UCPD_TypeDef * UCPDx )

Disable Rx overrun interrupt.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1009 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Disable hard reset discard interrupt.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1075 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Disable hard reset sent interrupt.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1064 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxIS ( UCPD_TypeDef * UCPDx )

Disable Tx data receive interrupt.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_DisableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1119 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT ( UCPD_TypeDef * UCPDx )

Disable Tx message abort interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1086 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Disable Tx message discarded interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1108 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Disable Tx message sent interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1097 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxUND ( UCPD_TypeDef * UCPDx )

Disable TX underrun interrupt.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_DisableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1053 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Disable type c event on CC1.

Reference Manual to LL API cross reference:
IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 987 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Disable type c event on CC2.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 976 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_FRS ( UCPD_TypeDef * UCPDx )

Enable FRS interrupt.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_EnableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 800 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST ( UCPD_TypeDef * UCPDx )

Enable Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 855 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Enable Rx message end interrupt.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 833 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxNE ( UCPD_TypeDef * UCPDx )

Enable Rx non empty interrupt.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_EnableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 877 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet ( UCPD_TypeDef * UCPDx )

Enable Rx orderset interrupt.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 866 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr ( UCPD_TypeDef * UCPDx )

Enable Rx overrun interrupt.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 844 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Enable hard reset discard interrupt.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 910 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Enable hard reset sent interrupt.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 899 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxIS ( UCPD_TypeDef * UCPDx )

Enable Tx data receive interrupt.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_EnableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 954 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT ( UCPD_TypeDef * UCPDx )

Enable Tx message abort interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 921 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Enable Tx message discarded interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 943 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Enable Tx message sent interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 932 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxUND ( UCPD_TypeDef * UCPDx )

Enable TX underrun interrupt.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_EnableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 888 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Enable type c event on CC1.

Reference Manual to LL API cross reference:
IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 822 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Enable type c event on CC2.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 811 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS ( UCPD_TypeDef const *const UCPDx )

Check if FRS interrupt enabled.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_DisableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1130 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST ( UCPD_TypeDef const *const UCPDx )

Check if Rx hard resrt interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1185 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd ( UCPD_TypeDef const *const UCPDx )

Check if Rx message end interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1163 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE ( UCPD_TypeDef const *const UCPDx )

Check if Rx non empty interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1207 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet ( UCPD_TypeDef const *const UCPDx )

Check if Rx orderset interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1196 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr ( UCPD_TypeDef const *const UCPDx )

Check if Rx overrun interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1174 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC ( UCPD_TypeDef const *const UCPDx )

Check if hard reset discard interrupt enabled.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1240 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT ( UCPD_TypeDef const *const UCPDx )

Check if hard reset sent interrupt enabled.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1229 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS ( UCPD_TypeDef const *const UCPDx )

Check if Tx data receive interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_IsEnableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1284 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message abort interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1251 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC ( UCPD_TypeDef const *const UCPDx )

Check if Tx message discarded interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1273 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message sent interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1262 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND ( UCPD_TypeDef const *const UCPDx )

Check if TX underrun interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1218 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC1 enabled.

Reference Manual to LL API cross reference:
IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1152 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC2 enabled.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1141 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Interrupt Clear

Functions
Interrupt Clear
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_ClearFlag_FRS (UCPD_TypeDef *UCPDx)
Clear FRS interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Clear type c event on CC2.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Clear type c event on CC1.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxMsgEnd (UCPD_TypeDef *UCPDx)
Clear Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOvr (UCPD_TypeDef *UCPDx)
Clear Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxHRST (UCPD_TypeDef *UCPDx)
Clear Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOrderSet (UCPD_TypeDef *UCPDx)
Clear Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxUND (UCPD_TypeDef *UCPDx)
Clear TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Clear hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Clear hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGABT (UCPD_TypeDef *UCPDx)
Clear Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGSENT (UCPD_TypeDef *UCPDx)
Clear Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGDISC (UCPD_TypeDef *UCPDx)
Clear Tx message discarded interrupt.

Function Documentation

__STATIC_INLINE void LL_UCPD_ClearFlag_FRS ( UCPD_TypeDef * UCPDx )

Clear FRS interrupt.

Reference Manual to LL API cross reference:
ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1303 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST ( UCPD_TypeDef * UCPDx )

Clear Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1358 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Clear Rx message end interrupt.

Reference Manual to LL API cross reference:
ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1336 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet ( UCPD_TypeDef * UCPDx )

Clear Rx orderset interrupt.

Reference Manual to LL API cross reference:
ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1369 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr ( UCPD_TypeDef * UCPDx )

Clear Rx overrun interrupt.

Reference Manual to LL API cross reference:
ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1347 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Clear hard reset discard interrupt.

Reference Manual to LL API cross reference:
ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1402 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Clear hard reset sent interrupt.

Reference Manual to LL API cross reference:
ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1391 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT ( UCPD_TypeDef * UCPDx )

Clear Tx message abort interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1413 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Clear Tx message discarded interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1435 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Clear Tx message sent interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1424 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND ( UCPD_TypeDef * UCPDx )

Clear TX underrun interrupt.

Reference Manual to LL API cross reference:
ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1380 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Clear type c event on CC1.

Reference Manual to LL API cross reference:
IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1325 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Clear type c event on CC2.

Reference Manual to LL API cross reference:
IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1314 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG Management

Functions
FLAG Management
UCPD Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC2 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC2
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC1 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC1

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1 ( UCPD_TypeDef const *const UCPDx )

return the vstate value for CC1

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_GetTypeCVstateCC1
Parameters:
UCPDx UCPD Instance
Return values:
val

Definition at line 1630 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2 ( UCPD_TypeDef const *const UCPDx )

return the vstate value for CC2

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_GetTypeCVstateCC2
Parameters:
UCPDx UCPD Instance
Return values:
val

Definition at line 1619 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS ( UCPD_TypeDef const *const UCPDx )

Check if FRS interrupt.

Reference Manual to LL API cross reference:
SR FRSEVT LL_UCPD_IsActiveFlag_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1454 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST ( UCPD_TypeDef const *const UCPDx )

Check if Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1509 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd ( UCPD_TypeDef const *const UCPDx )

Check if Rx message end interrupt.

Reference Manual to LL API cross reference:
SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1487 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE ( UCPD_TypeDef const *const UCPDx )

Check if Rx non empty interrupt.

Reference Manual to LL API cross reference:
SR RXNE LL_UCPD_IsActiveFlag_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1531 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet ( UCPD_TypeDef const *const UCPDx )

Check if Rx orderset interrupt.

Reference Manual to LL API cross reference:
SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1520 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr ( UCPD_TypeDef const *const UCPDx )

Check if Rx overrun interrupt.

Reference Manual to LL API cross reference:
SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1498 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC ( UCPD_TypeDef const *const UCPDx )

Check if hard reset discard interrupt.

Reference Manual to LL API cross reference:
SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1564 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT ( UCPD_TypeDef const *const UCPDx )

Check if hard reset sent interrupt.

Reference Manual to LL API cross reference:
SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1553 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS ( UCPD_TypeDef const *const UCPDx )

Check if Tx data receive interrupt.

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_IsActiveFlag_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1608 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message abort interrupt.

Reference Manual to LL API cross reference:
SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1575 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC ( UCPD_TypeDef const *const UCPDx )

Check if Tx message discarded interrupt.

Reference Manual to LL API cross reference:
SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1597 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message sent interrupt.

Reference Manual to LL API cross reference:
SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1586 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND ( UCPD_TypeDef const *const UCPDx )

Check if TX underrun interrupt.

Reference Manual to LL API cross reference:
SR TXUND LL_UCPD_IsActiveFlag_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1542 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC1.

Reference Manual to LL API cross reference:
SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1476 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC2.

Reference Manual to LL API cross reference:
SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1465 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Management

Functions
DMA Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_RxDMAEnable (UCPD_TypeDef *UCPDx)
Rx DMA Enable.
__STATIC_INLINE void | LL_UCPD_RxDMADisable (UCPD_TypeDef *UCPDx)
Rx DMA Disable.
__STATIC_INLINE void | LL_UCPD_TxDMAEnable (UCPD_TypeDef *UCPDx)
Tx DMA Enable.
__STATIC_INLINE void | LL_UCPD_TxDMADisable (UCPD_TypeDef *UCPDx)
Tx DMA Disable.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledTxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledRxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Rx is enabled.

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA ( UCPD_TypeDef const *const UCPDx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1705 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA ( UCPD_TypeDef const *const UCPDx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1694 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDMADisable ( UCPD_TypeDef * UCPDx )

Rx DMA Disable.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_UCPD_RxDMADisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1661 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDMAEnable ( UCPD_TypeDef * UCPDx )

Rx DMA Enable.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_UCPD_RxDMAEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1650 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TxDMADisable ( UCPD_TypeDef * UCPDx )

Tx DMA Disable.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_UCPD_TxDMADisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1683 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TxDMAEnable ( UCPD_TypeDef * UCPDx )

Tx DMA Enable.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_UCPD_TxDMAEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1672 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DATA Management

Functions
DATA Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_WriteTxOrderSet (UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
write the orderset for Tx message
__STATIC_INLINE void | LL_UCPD_WriteTxPaySize (UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
write the Tx paysize
__STATIC_INLINE void | LL_UCPD_WriteData (UCPD_TypeDef *UCPDx, uint8_t Data)
Write data.
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxOrderSet (UCPD_TypeDef const *const UCPDx)
read RX the orderset
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxPaySize (UCPD_TypeDef const *const UCPDx)
Read the Rx paysize.
__STATIC_INLINE uint32_t | LL_UCPD_ReadData (UCPD_TypeDef const *const UCPDx)
Read data.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt1 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext1.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt2 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext2.

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_ReadData ( UCPD_TypeDef const *const UCPDx )

Read data.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_UCPD_ReadData
Parameters:
UCPDx UCPD Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1797 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet ( UCPD_TypeDef const *const UCPDx )

read RX the orderset

Reference Manual to LL API cross reference:
RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
RxOrderSet one of the following value
  • LL_UCPD_RXORDSET_SOP
  • LL_UCPD_RXORDSET_SOP1
  • LL_UCPD_RXORDSET_SOP2
  • LL_UCPD_RXORDSET_SOP1_DEBUG
  • LL_UCPD_RXORDSET_SOP2_DEBUG
  • LL_UCPD_RXORDSET_CABLE_RESET
  • LL_UCPD_RXORDSET_SOPEXT1
  • LL_UCPD_RXORDSET_SOPEXT2

Definition at line 1775 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize ( UCPD_TypeDef const *const UCPDx )

Read the Rx paysize.

Reference Manual to LL API cross reference:
RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize
Parameters:
UCPDx UCPD Instance
Return values:
RXPaysize.

Definition at line 1786 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrdExt1 | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | SOPExt
 | ) |  |

Set Rx OrderSet Ext1.

Reference Manual to LL API cross reference:
RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
Parameters:
UCPDx | UCPD Instance
SOPExt | Value between Min_Data=0x00000 and Max_Data=0xFFFFF
Return values:
None

Definition at line 1809 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrdExt2 | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | SOPExt
 | ) |  |

Set Rx OrderSet Ext2.

Reference Manual to LL API cross reference:
RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
Parameters:
UCPDx | UCPD Instance
SOPExt | Value between Min_Data=0x00000 and Max_Data=0xFFFFF
Return values:
None

Definition at line 1821 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteData | ( | UCPD_TypeDef * | UCPDx,
 |  | uint8_t | Data
 | ) |  |

Write data.

Reference Manual to LL API cross reference:
TXDR DR LL_UCPD_WriteData
Parameters:
UCPDx | UCPD Instance
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None.

Definition at line 1756 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteTxOrderSet | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxOrderSet
 | ) |  |

write the orderset for Tx message

Reference Manual to LL API cross reference:
TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
Parameters:
UCPDx UCPD Instance
TxOrderSet one of the following value
  • LL_UCPD_ORDERED_SET_SOP
  • LL_UCPD_ORDERED_SET_SOP1
  • LL_UCPD_ORDERED_SET_SOP2
  • LL_UCPD_ORDERED_SET_HARD_RESET
  • LL_UCPD_ORDERED_SET_CABLE_RESET
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG
Return values:
None

Definition at line 1732 of file stm32g4xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteTxPaySize | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxPaySize
 | ) |  |

write the Tx paysize

Reference Manual to LL API cross reference:
TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
Parameters:
UCPDx UCPD Instance
TxPaySize
Return values:
None.

Definition at line 1744 of file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UCPD Exported Functions

Functions

ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_UCPD_DeInit ( UCPD_TypeDef * UCPDx )

De-initialize the UCPD registers to their default reset values.

Parameters:
UCPDx ucpd Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ucpd registers are de-initialized
  • ERROR: ucpd registers are not de-initialized

Definition at line 79 of file stm32g4xx_ll_ucpd.c.

References assert_param, LL_APB1_GRP2_DisableClock(), LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_UCPD1, LL_APB1_GRP2_ReleaseReset(), and LL_UCPD_Disable().

ErrorStatus LL_UCPD_Init | ( | UCPD_TypeDef * | UCPDx,
 |  | LL_UCPD_InitTypeDef * | UCPD_InitStruct
 | ) |  |

Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.

Note:
As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
UCPDx | UCPD Instance
UCPD_InitStruct | pointer to a LL_UCPD_InitTypeDef structure that contains the configuration information for the UCPD peripheral.
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 115 of file stm32g4xx_ll_ucpd.c.

References assert_param, LL_UCPD_InitTypeDef::HbitClockDiv, LL_UCPD_InitTypeDef::IfrGap, LL_APB1_GRP2_EnableClock(), LL_APB1_GRP2_PERIPH_UCPD1, LL_UCPD_Disable(), LL_UCPD_InitTypeDef::psc_ucpdclk, and LL_UCPD_InitTypeDef::transwin.

void LL_UCPD_StructInit ( LL_UCPD_InitTypeDef * UCPD_InitStruct )

Set each LL_UCPD_InitTypeDef field to default value.

Parameters:
UCPD_InitStruct pointer to a LL_UCPD_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 143 of file stm32g4xx_ll_ucpd.c.

References LL_UCPD_InitTypeDef::HbitClockDiv, LL_UCPD_InitTypeDef::IfrGap, LL_UCPD_PSC_DIV2, LL_UCPD_InitTypeDef::psc_ucpdclk, and LL_UCPD_InitTypeDef::transwin.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Variables

Variables
USART Private Variables
USART

Variables

static const uint32_t USART_PRESCALER_TAB []

Variable Documentation

const uint32_t USART_PRESCALER_TAB[] [static]
Initial value:
{
  1UL,
  2UL,
  4UL,
  6UL,
  8UL,
  10UL,
  12UL,
  16UL,
  32UL,
  64UL,
  128UL,
  256UL
}

Definition at line 46 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define USART_DEFAULT_BAUDRATE (9600U)

Define Documentation

#define USART_DEFAULT_BAUDRATE (9600U)

Definition at line 48 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_StructInit().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 18750000U)

Definition at line 74 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 16U)

Definition at line 77 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 104 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 98 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 101 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_7B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 88 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 79 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 112 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 95 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 92 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                       || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 84 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PRESCALER_DIV1) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))

Definition at line 59 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 107 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32g4xx_ll_usart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 91 of file stm32g4xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 99 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 104 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 128 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 134 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 116 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_USART_SetPrescaler().

Definition at line 93 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 110 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 122 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_usart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32g4xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 145 of file stm32g4xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 147 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 161 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 154 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 168 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_usart.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match clear flag

Definition at line 205 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS clear flag

Definition at line 201 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block clear flag

Definition at line 203 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error clear flag

Definition at line 193 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected clear flag

Definition at line 196 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection clear flag

Definition at line 200 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_NECF USART_ICR_NECF

Noise error detected clear flag

Definition at line 194 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error clear flag

Definition at line 195 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error clear flag

Definition at line 192 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout clear flag

Definition at line 202 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF

Transmission completed before guard time clear flag

Definition at line 199 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete clear flag

Definition at line 198 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty clear flag

Definition at line 197 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_UDRCF USART_ICR_UDRCF

SPI Slave Underrun clear flag

Definition at line 204 of file stm32g4xx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode clear flag

Definition at line 206 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 229 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 230 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 231 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 232 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 225 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 224 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 227 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 216 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 219 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 223 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 217 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 218 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 215 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 237 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 226 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 234 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 239 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 241 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 220 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 233 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 221 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TCBGT USART_ISR_TCBGT

Transmission complete before guard time completion flag

Definition at line 240 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 236 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 222 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 238 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 242 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_UDR USART_ISR_UDR

SPI Slave underrun error flag

Definition at line 228 of file stm32g4xx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 235 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 256 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 258 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 251 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 255 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 257 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 260 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 252 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 253 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 254 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 259 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 261 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 263 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 262 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 267 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE

Transmission complete before guard time interrupt enable

Definition at line 266 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 265 of file stm32g4xx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 264 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
USART Exported Constants

Defines

#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 277 of file stm32g4xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 276 of file stm32g4xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 275 of file stm32g4xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 278 of file stm32g4xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 279 of file stm32g4xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 280 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 288 of file stm32g4xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 289 of file stm32g4xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 290 of file stm32g4xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 291 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 300 of file stm32g4xx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 299 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 301 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 310 of file stm32g4xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 309 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_USART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 318 of file stm32g4xx_ll_usart.h.

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 319 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 320 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 328 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 329 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 339 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 340 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 349 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 350 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 358 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 359 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 368 of file stm32g4xx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 367 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
USART Exported Constants

Defines

#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_USART_PRESCALER_DIV1 0x00000000U

Input clock not divided

Definition at line 376 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock divided by 10

Definition at line 381 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock divided by 12

Definition at line 382 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock divided by 128

Definition at line 386 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 16

Definition at line 383 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock divided by 2

Definition at line 377 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 256

Definition at line 387 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock divided by 32

Definition at line 384 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock divided by 4

Definition at line 378 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 6

Definition at line 379 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock divided by 64

Definition at line 385 of file stm32g4xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock divided by 8

Definition at line 380 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 395 of file stm32g4xx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 396 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 397 of file stm32g4xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 398 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 406 of file stm32g4xx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 407 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 416 of file stm32g4xx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 415 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 425 of file stm32g4xx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 424 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 434 of file stm32g4xx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 433 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 442 of file stm32g4xx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 443 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 454 of file stm32g4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 453 of file stm32g4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 452 of file stm32g4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 451 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 462 of file stm32g4xx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 463 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 473 of file stm32g4xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 471 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 472 of file stm32g4xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 474 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 482 of file stm32g4xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 484 of file stm32g4xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 483 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 493 of file stm32g4xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 492 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 501 of file stm32g4xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 502 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 510 of file stm32g4xx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 511 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 520 of file stm32g4xx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 519 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 553 of file stm32g4xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 545 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 606 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 582 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (const USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (const USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (const USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (const USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (const USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (const USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (const USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (const USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (const USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (const USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (const USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (const USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (const USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (const USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (const USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (const USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (const USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (const USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (const USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (const USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (const USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (const USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (const USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (const USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (const USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (const USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (const USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (const USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (const USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (const USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (const USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (const USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (const USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1352 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1199 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
Parameters:
USARTx USART Instance
TXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 804 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1630 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 648 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1521 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1711 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 869 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 891 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Disable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_DisableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 685 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 834 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1039 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1770 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1803 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1685 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1591 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1276 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 634 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1508 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1698 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 858 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 880 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Enable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_EnableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 672 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 820 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1028 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1759 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1792 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1672 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1580 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1263 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( const USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1569 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | const USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1935 of file stm32g4xx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( const USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1464 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( const USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2007 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( const USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 1140 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( const USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 1171 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( const USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 1017 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( const USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1748 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( const USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 1109 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( const USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1646 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( const USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1659 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( const USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 1077 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( const USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 959 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetPrescaler ( const USART_TypeDef * USARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_GetPrescaler
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256

Definition at line 1250 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold ( const USART_TypeDef * USARTx )

Return RX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 776 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( const USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1408 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( const USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1984 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( const USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1320 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( const USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1495 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( const USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 925 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold ( const USART_TypeDef * USARTx )

Return TX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 737 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( const USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1435 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( const USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1381 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( const USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 986 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( const USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1847 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( const USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 659 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( const USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1534 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO ( const USART_TypeDef * USARTx )

Indicate if FIFO Mode is enabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_IsEnabledFIFO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 698 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( const USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 847 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( const USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1050 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( const USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1781 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( const USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1814 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( const USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( const USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1289 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1552 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1881 of file stm32g4xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, LL_USART_OVERSAMPLING_8, and LL_USART_PRESCALER_DIV256.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1451 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1996 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 1125 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 1156 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 1002 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1730 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1093 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 1064 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 944 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_SetPrescaler
Parameters:
USARTx USART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
Return values:
None

Definition at line 1225 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetRXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 757 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1395 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1973 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1305 of file stm32g4xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1480 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 909 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 718 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1422 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1368 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 973 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1831 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (const USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (const USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (const USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2041 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2028 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( const USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 2085 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( const USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2114 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( const USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2054 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 2070 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2100 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (const USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (const USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (const USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (const USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (const USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2187 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2148 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2174 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2135 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( const USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 2232 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( const USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2290 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( const USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 2261 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( const USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2200 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( const USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2161 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 2219 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2276 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2247 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (const USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2324 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2311 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( const USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2337 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to SPI Slave feature

Functions
Configuration functions related to SPI Slave feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (const USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (const USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.

Function Documentation

__STATIC_INLINE void LL_USART_DisableSPISlave ( USART_TypeDef * USARTx )

Disable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_DisableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2370 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSPISlaveSelect ( USART_TypeDef * USARTx )

Disable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave will be always selected and NSS input pin will be ignored.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2412 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlave ( USART_TypeDef * USARTx )

Enable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_EnableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2357 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlaveSelect ( USART_TypeDef * USARTx )

Enable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave Selection depends on NSS input pin (The slave is selected when NSS is low and deselected when NSS is high).
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2398 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave ( const USART_TypeDef * USARTx )

Indicate if SPI Synchronous Slave mode is enabled.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_IsEnabledSPISlave
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2383 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect ( const USART_TypeDef * USARTx )

Indicate if SPI Slave Selection depends on NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2425 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (const USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (const USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2490 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2477 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( const USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2464 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( const USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2503 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2449 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (const USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (const USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (const USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (const USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2591 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2578 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( const USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2565 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( const USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2538 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( const USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2635 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( const USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2604 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2552 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2525 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2620 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2673 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2790 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2875 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2751 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2914 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2831 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2710 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
USART Exported Functions

Defines

#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (const USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (const USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (const USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (const USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (const USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (const USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (const USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (const USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (const USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (const USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 2987 of file stm32g4xx_ll_usart.h.

#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 3013 of file stm32g4xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3431 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3407 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3289 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3322 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3370 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3383 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise Error detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3300 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3311 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3278 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3394 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3346 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TCBGT ( USART_TypeDef * USARTx )

Clear Smartcard Transmission Complete Before Guard Time Flag.

Reference Manual to LL API cross reference:
ICR TCBGTCF LL_USART_ClearFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3357 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TXFE ( USART_TypeDef * USARTx )

Clear TX FIFO Empty Flag.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR TXFECF LL_USART_ClearFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3335 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_UDR ( USART_TypeDef * USARTx )

Clear SPI Slave Underrun Flag.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR UDRCF LL_USART_ClearFlag_UDR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3420 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3444 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( const USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3125 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( const USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3112 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( const USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3136 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( const USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3147 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( const USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3062 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( const USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3086 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( const USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2949 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( const USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2982 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( const USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3036 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( const USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3049 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( const USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2960 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( const USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2971 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( const USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2938 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( const USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3204 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( const USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3073 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( const USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3169 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFF LL_USART_IsActiveFlag_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3230 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFT LL_USART_IsActiveFlag_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3267 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE ( const USART_TypeDef * USARTx )

Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2997 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( const USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3158 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( const USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3008 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT ( const USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.

Reference Manual to LL API cross reference:
ISR TCBGT LL_USART_IsActiveFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3241 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( const USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3193 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF ( const USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3023 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFE LL_USART_IsActiveFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3217 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFT LL_USART_IsActiveFlag_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3254 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR ( const USART_TypeDef * USARTx )

Check if the SPI Slave Underrun error flag is set or not.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR UDR LL_USART_IsActiveFlag_UDR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3099 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( const USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3182 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
USART Exported Functions

Defines

#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (const USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (const USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (const USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 3683 of file stm32g4xx_ll_usart.h.

#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 3709 of file stm32g4xx_ll_usart.h.

#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 3468 of file stm32g4xx_ll_usart.h.

#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 3494 of file stm32g4xx_ll_usart.h.

#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */

Definition at line 3900 of file stm32g4xx_ll_usart.h.

#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Definition at line 3926 of file stm32g4xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3741 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3832 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3765 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3819 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3678 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3804 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3730 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3752 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFF ( USART_TypeDef * USARTx )

Disable RX FIFO Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_DisableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3791 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFT ( USART_TypeDef * USARTx )

Disable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_DisableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3884 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3693 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3704 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TCBGT ( USART_TypeDef * USARTx )

Disable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_DisableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3871 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3719 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFE ( USART_TypeDef * USARTx )

Disable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_DisableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3778 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFT ( USART_TypeDef * USARTx )

Disable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_DisableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3858 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3845 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3526 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3615 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3550 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3602 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3463 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3587 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3515 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3537 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFF ( USART_TypeDef * USARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_EnableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3574 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFT ( USART_TypeDef * USARTx )

Enable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_EnableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3667 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3478 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3489 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TCBGT ( USART_TypeDef * USARTx )

Enable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_EnableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3654 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3504 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFE ( USART_TypeDef * USARTx )

Enable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_EnableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3563 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFT ( USART_TypeDef * USARTx )

Enable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_EnableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3641 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3628 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( const USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3958 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( const USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4045 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( const USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3982 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( const USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4032 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( const USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3895 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( const USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4021 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( const USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3947 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( const USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3969 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4008 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT ( const USART_TypeDef * USARTx )

Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4097 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE ( const USART_TypeDef * USARTx )

Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3910 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( const USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3921 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT ( const USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4084 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF ( const USART_TypeDef * USARTx )

Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3936 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3995 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT ( const USART_TypeDef * USARTx )

Check if USART TX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4071 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( const USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4058 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (const USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4193 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4127 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4160 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | const USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 4219 of file stm32g4xx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4182 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4116 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4149 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( const USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4204 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( const USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4138 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( const USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4171 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( const USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 4251 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( const USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 4262 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 4274 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 4286 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4307 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4318 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4329 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4344 of file stm32g4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4357 of file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | const LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx | USART Instance
USART_ClockInitStruct | pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 355 of file stm32g4xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 402 of file stm32g4xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( const USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 139 of file stm32g4xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_UART4, LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | const LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx | USART Instance
USART_InitStruct | pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 212 of file stm32g4xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_BRR_MIN, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_PRESCALER, IS_LL_USART_STOPBITS, LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_UART4_CLKSOURCE, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART3_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetPrescaler(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 328 of file stm32g4xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_PRESCALER_DIV1, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, LL_USART_InitTypeDef::TransferDirection, and USART_DEFAULT_BAUDRATE.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 638 of file stm32g4xx_ll_utils.c.

References __LL_RCC_CALC_HCLK_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, assert_param, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_EnableDomain_SYS(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetFlashLatency(), and LL_SetSystemCoreClock().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 584 of file stm32g4xx_ll_utils.c.

References assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLR_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, and LL_UTILS_PLLInitTypeDef::PLLR.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 615 of file stm32g4xx_ll_utils.c.

References LL_RCC_PLL_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_MAX_FREQUENCY_SCALE1 170000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 26000000U
#define | UTILS_PLLVCO_INPUT_MIN 2660000U
#define | UTILS_PLLVCO_INPUT_MAX 16000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 64000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U
#define | UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U
#define | UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U
#define | UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U
#define | UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 30000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 60000000U
#define | UTILS_SCALE1_LATENCY3_FREQ 90000000U
#define | UTILS_SCALE1_LATENCY4_FREQ 120000000U
#define | UTILS_SCALE1_LATENCY5_FREQ 150000000U
#define | UTILS_SCALE2_LATENCY1_FREQ 12000000U
#define | UTILS_SCALE2_LATENCY2_FREQ 24000000U
#define | UTILS_SCALE2_LATENCY3_FREQ 26000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 69 of file stm32g4xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 59 of file stm32g4xx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 74 of file stm32g4xx_ll_utils.h.

Referenced by LL_GetPackageType().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 64 of file stm32g4xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX 48000000U

Frequency max for HSE frequency, in Hz

Definition at line 55 of file stm32g4xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN 4000000U

Frequency min for HSE frequency, in Hz

Definition at line 54 of file stm32g4xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE1 170000000U

Maximum frequency for system clock at power scale1, in Hz

Definition at line 44 of file stm32g4xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE2 26000000U

Maximum frequency for system clock at power scale2, in Hz

Definition at line 45 of file stm32g4xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX 16000000U

Frequency max for PLLVCO input, in Hz

Definition at line 49 of file stm32g4xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN 2660000U

Frequency min for PLLVCO input, in Hz

Definition at line 48 of file stm32g4xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MAX 344000000U

Frequency max for PLLVCO output, in Hz

Definition at line 51 of file stm32g4xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MIN 64000000U

Frequency min for PLLVCO output, in Hz

Definition at line 50 of file stm32g4xx_ll_utils.c.

#define UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U

HCLK frequency to set FLASH latency 1 in power scale 1

Definition at line 58 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY1_FREQ 30000000U

HCLK frequency to set FLASH latency 1 in power scale 1 normal mode

Definition at line 64 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U

HCLK frequency to set FLASH latency 2 in power scale 1

Definition at line 59 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY2_FREQ 60000000U

HCLK frequency to set FLASH latency 2 in power scale 1 normal mode

Definition at line 65 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U

HCLK frequency to set FLASH latency 3 in power scale 1

Definition at line 60 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY3_FREQ 90000000U

HCLK frequency to set FLASH latency 3 in power scale 1 normal mode

Definition at line 66 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U

HCLK frequency to set FLASH latency 4 in power scale 1

Definition at line 61 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY4_FREQ 120000000U

HCLK frequency to set FLASH latency 4 in power scale 1 normal mode

Definition at line 67 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U

HCLK frequency to set FLASH latency 5 in power scale 1

Definition at line 62 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY5_FREQ 150000000U

HCLK frequency to set FLASH latency 5 in power scale 1 normal mode

Definition at line 68 of file stm32g4xx_ll_utils.c.

#define UTILS_SCALE2_LATENCY1_FREQ 12000000U

HCLK frequency to set FLASH latency 1 in power scale 2

Definition at line 70 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE2_LATENCY2_FREQ 24000000U

HCLK frequency to set FLASH latency 2 in power scale 2

Definition at line 71 of file stm32g4xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE2_LATENCY3_FREQ 26000000U

HCLK frequency to set FLASH latency 3 in power scale 2

Definition at line 72 of file stm32g4xx_ll_utils.c.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 91 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 97 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 134 of file stm32g4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 137 of file stm32g4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ )
Value:
((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))

Definition at line 131 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLM_DIV_1) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_16))

Definition at line 103 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLN_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))

Definition at line 120 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLR_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))

Definition at line 122 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_INPUT ( __VALUE__ ) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))

Definition at line 127 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_OUTPUT ( __VALUE__ ) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))

Definition at line 129 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 81 of file stm32g4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32g4xx_ll_utils.h>

Data Fields

uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLR

Detailed Description

UTILS PLL structure definition.

Definition at line 94 of file stm32g4xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLM

Division factor for PLL VCO input clock. This parameter can be a value of PLL division factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 96 of file stm32g4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLN

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 102 of file stm32g4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLR

Division for the main system clock. This parameter can be a value of PLL division factor (PLLR)

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 108 of file stm32g4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_utils.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32g4xx_ll_utils.h>

Data Fields

uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 118 of file stm32g4xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 120 of file stm32g4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 126 of file stm32g4xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB high-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 132 of file stm32g4xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32g4xx_ll_utils.h
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 152 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 153 of file stm32g4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PACKAGE TYPE

Defines
PACKAGE TYPE
UTILS Exported Constants

Defines

#define | LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U
#define | LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U
#define | LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80
#define | LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U
#define | LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U
#define | LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121
#define | LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U
#define | LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U
#define | LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU
#define | LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU
#define | LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU
#define | LL_UTILS_PACKAGETYPE_TFBGA100 0x0000000EU
#define | LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100
#define | LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U

Define Documentation

#define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80

For backward compatibility

Definition at line 167 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U

LQFP100 \ LQFP80 package type

Definition at line 166 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121

For backward compatibility

Definition at line 173 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U

LQFP128 \ UFBGA121 package type

Definition at line 172 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U

LQFP32 package type

Definition at line 175 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU

LQFP48 package type

Definition at line 177 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U

LQFP48 EBIKE package type

Definition at line 182 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U

LQFP64 package type

Definition at line 161 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_TFBGA100 0x0000000EU

TFBGA100 package type

Definition at line 180 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100

For backward compatibility

Definition at line 181 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU

UFBGA64 package type

Definition at line 179 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U

UFQFPN32 package type

Definition at line 174 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU

UFQFPN48 package type

Definition at line 176 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU

WLCSP49 package type

Definition at line 178 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U

WLCSP64 package type

Definition at line 162 of file stm32g4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U

WLCSP81 package type

Definition at line 171 of file stm32g4xx_ll_utils.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 239 of file stm32g4xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetPackageType ( void )

Get Package type.

Return values:
Returned value can be one of the following values:
  • LL_UTILS_PACKAGETYPE_LQFP64
  • LL_UTILS_PACKAGETYPE_LQFP100
  • LL_UTILS_PACKAGETYPE_WLCSP81
  • LL_UTILS_PACKAGETYPE_LQFP128
  • LL_UTILS_PACKAGETYPE_UFQFPN32
  • LL_UTILS_PACKAGETYPE_LQFP32
  • LL_UTILS_PACKAGETYPE_UFQFPN48
  • LL_UTILS_PACKAGETYPE_LQFP48
  • LL_UTILS_PACKAGETYPE_WLCSP49
  • LL_UTILS_PACKAGETYPE_UFBGA64
  • LL_UTILS_PACKAGETYPE_UFBGA100
  • LL_UTILS_PACKAGETYPE_LQFP48_EBIKE

Definition at line 261 of file stm32g4xx_ll_utils.h.

References PACKAGE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0],: X and Y coordinates on the wafer expressed in BCD format

Definition at line 210 of file stm32g4xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32],: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])

Definition at line 219 of file stm32g4xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64],: Lot number (ASCII encoded) - LOT_NUM[55:24]

Definition at line 228 of file stm32g4xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 170 of file stm32g4xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Frequency of Ticks (Hz)
Return values:
None

Definition at line 282 of file stm32g4xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 186 of file stm32g4xx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
             170000000 Hz for STM32G4xx.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSE frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 170000000 Hz is reached (PLLVCO_output / PLLR)
Parameters:
HSEFrequency | Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 488 of file stm32g4xx_ll_utils.c.

References LL_UTILS_ClkInitTypeDef::AHBCLKDivider, assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_RCC_SetAHBPrescaler(), LL_RCC_SYSCLK_DIV_1, LL_RCC_SYSCLK_DIV_2, LL_SetFlashLatency(), LL_SetSystemCoreClock(), LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 170000000 Hz is reach (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 406 of file stm32g4xx_ll_utils.c.

References LL_UTILS_ClkInitTypeDef::AHBCLKDivider, HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_RCC_SetAHBPrescaler(), LL_RCC_SYSCLK_DIV_1, LL_RCC_SYSCLK_DIV_2, LL_SetFlashLatency(), LL_SetSystemCoreClock(), LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_SetFlashLatency ( uint32_t HCLKFrequency )

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
HCLKFrequency HCLK frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 271 of file stm32g4xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_FLASH_SetLatency(), LL_PWR_GetRegulVoltageScaling(), LL_PWR_IsEnabledRange1BoostMode(), LL_PWR_REGU_VOLTAGE_SCALE1, LL_PWR_REGU_VOLTAGE_SCALE2, UTILS_SCALE1_LATENCY1_BOOST_FREQ, UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_BOOST_FREQ, UTILS_SCALE1_LATENCY2_FREQ, UTILS_SCALE1_LATENCY3_BOOST_FREQ, UTILS_SCALE1_LATENCY3_FREQ, UTILS_SCALE1_LATENCY4_BOOST_FREQ, UTILS_SCALE1_LATENCY4_FREQ, UTILS_SCALE1_LATENCY5_BOOST_FREQ, UTILS_SCALE2_LATENCY1_FREQ, and UTILS_SCALE2_LATENCY2_FREQ.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_EnablePLLAndSwitchSystem().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 257 of file stm32g4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 54 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 62 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/128

Definition at line 69 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 66 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 63 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 67 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 64 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 68 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 65 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 100 of file stm32g4xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 92 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (const WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (const WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (const WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (const WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 127 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( const WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 165 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( const WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128

Definition at line 206 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( const WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 238 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( const WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 138 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 154 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128
Return values:
None

Definition at line 187 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 227 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (const WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 270 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( const WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 259 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (const WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 290 of file stm32g4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( const WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 301 of file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • Activation : SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • Adc12ClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • Bank : FLASH_ProcessTypeDef
  • Banks : FLASH_EraseInitTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BootEntryPoint : FLASH_OBProgramInitTypeDef
  • Break2AFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2State : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakAFMode : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CacheToReactivate : FLASH_ProcessTypeDef
  • CalculateCpltCallback : __CORDIC_HandleTypeDef
  • Channel : ADC_AnalogWDGConfTypeDef , __TIM_HandleTypeDef , ADC_ChannelConfTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelNState : __TIM_HandleTypeDef
  • ChannelState : __TIM_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • Clip : FMAC_FilterConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivider : FDCAN_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CoeffASize : FMAC_FilterConfigTypeDef
  • CoeffBaseAddress : FMAC_FilterConfigTypeDef
  • CoeffBSize : FMAC_FilterConfigTypeDef
  • CoeffBufferSize : FMAC_FilterConfigTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • ConnectCallback : __PCD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_DMADoubleDataMode : DAC_ChannelConfTypeDef
  • DAC_HighFrequency : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SignedFormat : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_Trigger2 : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Devaddress : __I2C_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef , LL_DMA_InitTypeDef , TIMEx_EncoderIndexConfigTypeDef
  • DirectionChangeCallback : __TIM_HandleTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMABurstState : __TIM_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADirection : __CORDIC_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderIndexCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCallback : __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __CORDIC_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __DMA_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __RNG_HandleTypeDef , __SPI_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __CORDIC_HandleTypeDef , __DAC_HandleTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_RxHeaderTypeDef
  • FifoMode : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • Filter : FMAC_FilterConfigTypeDef , RTC_TamperTypeDef , TIMEx_EncoderIndexConfigTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterConfigCallback : __FMAC_HandleTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef
  • FilteringConfig : ADC_AnalogWDGConfTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterParam : __FMAC_HandleTypeDef
  • FilterPreloadCallback : __FMAC_HandleTypeDef
  • FilterType : FDCAN_FilterTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstIndexEnable : TIMEx_EncoderIndexConfigTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • Function : CORDIC_ConfigTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GainCompensation : ADC_InitTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GetDataCallback : __FMAC_HandleTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HalfGetDataCallback : __FMAC_HandleTypeDef
  • HalfOutputDataReadyCallback : __FMAC_HandleTypeDef
  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • HbitClockDiv : LL_UCPD_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmaIn : __CORDIC_HandleTypeDef , __FMAC_HandleTypeDef
  • hdmaOut : __CORDIC_HandleTypeDef , __FMAC_HandleTypeDef
  • hdmaPreload : __FMAC_HandleTypeDef
  • hdmarx : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef
  • hdmatx : __SMARTCARD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2sClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IfrGap : LL_UCPD_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • IndexErrorCallback : __TIM_HandleTypeDef
  • Init : __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetSaturation : ADC_InjectionConfTypeDef
  • InjectedOffsetSign : ADC_InjectionConfTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputAccess : __FMAC_HandleTypeDef , FMAC_FilterConfigTypeDef
  • InputBaseAddress : FMAC_FilterConfigTypeDef
  • InputBufferSize : FMAC_FilterConfigTypeDef
  • InputCurrentSize : __FMAC_HandleTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputThreshold : FMAC_FilterConfigTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • InSize : CORDIC_ConfigTypeDef
  • Instance : __COMP_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __FDCAN_HandleTypeDef , __I2S_HandleTypeDef , __ADC_HandleTypeDef , __I2C_HandleTypeDef , __CORDIC_HandleTypeDef , __SPI_HandleTypeDef , __DAC_HandleTypeDef , __WWDG_HandleTypeDef , __PCD_HandleTypeDef , __FMAC_HandleTypeDef , __RTC_HandleTypeDef , __DMA_HandleTypeDef , __SMBUS_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __OPAMP_HandleTypeDef , CRC_HandleTypeDef , IWDG_HandleTypeDef
  • InternalOutput : OPAMP_InitTypeDef
  • InternalTamper1EventCallback : __RTC_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • InvertingInput : OPAMP_InitTypeDef
  • InvertingInputSecondary : OPAMP_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Lock : __UART_HandleTypeDef , __COMP_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CORDIC_HandleTypeDef , __RTC_HandleTypeDef , __RNG_HandleTypeDef , __SMBUS_HandleTypeDef , CRC_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __FMAC_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef , __ADC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Mask : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : LL_I2S_InitTypeDef , I2S_InitTypeDef
  • Memaddress : __I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • Minutes : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • Mode : ADC_MultiModeTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef , PWR_PVDTypeDef , PWR_PVMTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __IRDA_HandleTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __ADC_HandleTypeDef , __FDCAN_HandleTypeDef , __DAC_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __CORDIC_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __COMP_HandleTypeDef
  • MspInitCallback : __CORDIC_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMBUS_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __WWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __FMAC_HandleTypeDef , __FDCAN_HandleTypeDef , __PCD_HandleTypeDef , __OPAMP_HandleTypeDef , __ADC_HandleTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbCalcToGet : __CORDIC_HandleTypeDef
  • NbCalcToOrder : __CORDIC_HandleTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbRead : CORDIC_ConfigTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbWrite : CORDIC_ConfigTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef
  • NonInvertingInputSecondary : OPAMP_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetSaturation : ADC_ChannelConfTypeDef
  • OffsetSign : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputAccess : __FMAC_HandleTypeDef , FMAC_FilterConfigTypeDef
  • OutputBaseAddress : FMAC_FilterConfigTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputBufferSize : FMAC_FilterConfigTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputCurrentSize : __FMAC_HandleTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDataReadyCallback : __FMAC_HandleTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef , LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputThreshold : FMAC_FilterConfigTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutSize : CORDIC_ConfigTypeDef
  • Overrun : LL_ADC_REG_InitTypeDef , ADC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : SMBUS_InitTypeDef , I2C_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • P : FMAC_FilterConfigTypeDef
  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pCoeffA : FMAC_FilterConfigTypeDef
  • pCoeffB : FMAC_FilterConfigTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pData : __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInBuff : __CORDIC_HandleTypeDef
  • pInput : __FMAC_HandleTypeDef
  • pInputSize : __FMAC_HandleTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : TIMEx_EncoderIndexConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • Position : TIMEx_EncoderIndexConfigTypeDef
  • pOutBuff : __CORDIC_HandleTypeDef
  • pOutput : __FMAC_HandleTypeDef
  • pOutputSize : __FMAC_HandleTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef , LL_OPAMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Precision : CORDIC_ConfigTypeDef
  • Prescaler : IRDA_InitTypeDef , WWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , RCC_CRSInitTypeDef , SMARTCARD_InitTypeDef , LL_LPTIM_InitTypeDef , TIMEx_EncoderIndexConfigTypeDef , LL_TIM_InitTypeDef , TIM_Base_InitTypeDef , IWDG_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • ProtocolException : FDCAN_InitTypeDef , FDCAN_ProtocolStatusTypeDef
  • pRxBuffPtr : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef
  • psc_ucpdclk : LL_UCPD_InitTypeDef
  • pTxBuffPtr : __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- q -

  • Q : FMAC_FilterConfigTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • R : FMAC_FilterConfigTypeDef
  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RdState : __FMAC_HandleTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReceptionType : __UART_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxCpltCallback : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxEventCallback : __UART_HandleTypeDef
  • RxEventType : __UART_HandleTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SAI_HandleTypeDef
  • RxISR : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __I2S_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxXferSize : __I2S_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingMode : ADC_InitTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • Scale : CORDIC_ConfigTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecBank : FLASH_OBProgramInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SecSize : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • Size : MPU_Region_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • State : __OPAMP_HandleTypeDef , __FMAC_HandleTypeDef , __I2S_HandleTypeDef , CRC_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __CORDIC_HandleTypeDef , __TIM_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __LPTIM_HandleTypeDef , __SMBUS_HandleTypeDef , __RTC_HandleTypeDef , __SPI_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StopBits : UART_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TimeFormat : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimerControlledMuxmode : OPAMP_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransitionErrorCallback : __TIM_HandleTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • transwin : LL_UCPD_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TriggerSource2 : LL_DAC_InitTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoEmptyCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __FDCAN_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SPI_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SAI_HandleTypeDef
  • TxISR : __USART_HandleTypeDef , __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WordLength : SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef , USART_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
  • WrState : __FMAC_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • Activation : SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • Adc12ClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- b -

  • Bank : FLASH_ProcessTypeDef
  • Banks : FLASH_EraseInitTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BootEntryPoint : FLASH_OBProgramInitTypeDef
  • Break2AFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2State : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakAFMode : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- c -

  • CacheToReactivate : FLASH_ProcessTypeDef
  • CalculateCpltCallback : __CORDIC_HandleTypeDef
  • Channel : ADC_AnalogWDGConfTypeDef , __TIM_HandleTypeDef , ADC_ChannelConfTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelNState : __TIM_HandleTypeDef
  • ChannelState : __TIM_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • Clip : FMAC_FilterConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivider : FDCAN_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CoeffASize : FMAC_FilterConfigTypeDef
  • CoeffBaseAddress : FMAC_FilterConfigTypeDef
  • CoeffBSize : FMAC_FilterConfigTypeDef
  • CoeffBufferSize : FMAC_FilterConfigTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • ConnectCallback : __PCD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_DMADoubleDataMode : DAC_ChannelConfTypeDef
  • DAC_HighFrequency : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SignedFormat : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_Trigger2 : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Devaddress : __I2C_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef , LL_DMA_InitTypeDef , TIMEx_EncoderIndexConfigTypeDef
  • DirectionChangeCallback : __TIM_HandleTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMABurstState : __TIM_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADirection : __CORDIC_HandleTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- e -

  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderIndexCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCallback : __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __CORDIC_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __DMA_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __RNG_HandleTypeDef , __SPI_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __CORDIC_HandleTypeDef , __DAC_HandleTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- f -

  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_RxHeaderTypeDef
  • FifoMode : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • Filter : FMAC_FilterConfigTypeDef , RTC_TamperTypeDef , TIMEx_EncoderIndexConfigTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterConfigCallback : __FMAC_HandleTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_HpMsgStatusTypeDef
  • FilteringConfig : ADC_AnalogWDGConfTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterParam : __FMAC_HandleTypeDef
  • FilterPreloadCallback : __FMAC_HandleTypeDef
  • FilterType : FDCAN_FilterTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FirstIndexEnable : TIMEx_EncoderIndexConfigTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • Function : CORDIC_ConfigTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- g -

  • GainCompensation : ADC_InitTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GetDataCallback : __FMAC_HandleTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- h -

  • HalfGetDataCallback : __FMAC_HandleTypeDef
  • HalfOutputDataReadyCallback : __FMAC_HandleTypeDef
  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • HbitClockDiv : LL_UCPD_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmaIn : __CORDIC_HandleTypeDef , __FMAC_HandleTypeDef
  • hdmaOut : __CORDIC_HandleTypeDef , __FMAC_HandleTypeDef
  • hdmaPreload : __FMAC_HandleTypeDef
  • hdmarx : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef
  • hdmatx : __SMARTCARD_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2sClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IfrGap : LL_UCPD_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • IndexErrorCallback : __TIM_HandleTypeDef
  • Init : __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedOffsetSaturation : ADC_InjectionConfTypeDef
  • InjectedOffsetSign : ADC_InjectionConfTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputAccess : __FMAC_HandleTypeDef , FMAC_FilterConfigTypeDef
  • InputBaseAddress : FMAC_FilterConfigTypeDef
  • InputBufferSize : FMAC_FilterConfigTypeDef
  • InputCurrentSize : __FMAC_HandleTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputThreshold : FMAC_FilterConfigTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • InSize : CORDIC_ConfigTypeDef
  • Instance : __COMP_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __FDCAN_HandleTypeDef , __I2S_HandleTypeDef , __ADC_HandleTypeDef , __I2C_HandleTypeDef , __CORDIC_HandleTypeDef , __SPI_HandleTypeDef , __DAC_HandleTypeDef , __WWDG_HandleTypeDef , __PCD_HandleTypeDef , __FMAC_HandleTypeDef , __RTC_HandleTypeDef , __DMA_HandleTypeDef , __SMBUS_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __OPAMP_HandleTypeDef , CRC_HandleTypeDef , IWDG_HandleTypeDef
  • InternalOutput : OPAMP_InitTypeDef
  • InternalTamper1EventCallback : __RTC_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • InvertingInput : OPAMP_InitTypeDef
  • InvertingInputSecondary : OPAMP_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Lock : __UART_HandleTypeDef , __COMP_HandleTypeDef , __SPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CORDIC_HandleTypeDef , __RTC_HandleTypeDef , __RNG_HandleTypeDef , __SMBUS_HandleTypeDef , CRC_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __FMAC_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef , __ADC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- m -

  • Mask : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MCLKOutput : LL_I2S_InitTypeDef , I2S_InitTypeDef
  • Memaddress : __I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • Minutes : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • Mode : ADC_MultiModeTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef , PWR_PVDTypeDef , PWR_PVMTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __IRDA_HandleTypeDef , __FMAC_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __ADC_HandleTypeDef , __FDCAN_HandleTypeDef , __DAC_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __CORDIC_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __COMP_HandleTypeDef
  • MspInitCallback : __CORDIC_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMBUS_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __WWDG_HandleTypeDef , __LPTIM_HandleTypeDef , __FMAC_HandleTypeDef , __FDCAN_HandleTypeDef , __PCD_HandleTypeDef , __OPAMP_HandleTypeDef , __ADC_HandleTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbCalcToGet : __CORDIC_HandleTypeDef
  • NbCalcToOrder : __CORDIC_HandleTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbRead : CORDIC_ConfigTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbWrite : CORDIC_ConfigTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NonInvertingInput : OPAMP_InitTypeDef
  • NonInvertingInputSecondary : OPAMP_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffsetSaturation : ADC_ChannelConfTypeDef
  • OffsetSign : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputAccess : __FMAC_HandleTypeDef , FMAC_FilterConfigTypeDef
  • OutputBaseAddress : FMAC_FilterConfigTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputBufferSize : FMAC_FilterConfigTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputCurrentSize : __FMAC_HandleTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDataReadyCallback : __FMAC_HandleTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef , LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputThreshold : FMAC_FilterConfigTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutSize : CORDIC_ConfigTypeDef
  • Overrun : LL_ADC_REG_InitTypeDef , ADC_InitTypeDef
  • OverrunDisable : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : SMBUS_InitTypeDef , I2C_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- p -

  • P : FMAC_FilterConfigTypeDef
  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pCoeffA : FMAC_FilterConfigTypeDef
  • pCoeffB : FMAC_FilterConfigTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pData : __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • PgaConnect : OPAMP_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInBuff : __CORDIC_HandleTypeDef
  • pInput : __FMAC_HandleTypeDef
  • pInputSize : __FMAC_HandleTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : TIMEx_EncoderIndexConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • Position : TIMEx_EncoderIndexConfigTypeDef
  • pOutBuff : __CORDIC_HandleTypeDef
  • pOutput : __FMAC_HandleTypeDef
  • pOutputSize : __FMAC_HandleTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef , LL_OPAMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Precision : CORDIC_ConfigTypeDef
  • Prescaler : IRDA_InitTypeDef , WWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , RCC_CRSInitTypeDef , SMARTCARD_InitTypeDef , LL_LPTIM_InitTypeDef , TIMEx_EncoderIndexConfigTypeDef , LL_TIM_InitTypeDef , TIM_Base_InitTypeDef , IWDG_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • ProtocolException : FDCAN_InitTypeDef , FDCAN_ProtocolStatusTypeDef
  • pRxBuffPtr : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef
  • psc_ucpdclk : LL_UCPD_InitTypeDef
  • pTxBuffPtr : __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- q -

  • Q : FMAC_FilterConfigTypeDef
  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- r -

  • R : FMAC_FilterConfigTypeDef
  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RdState : __FMAC_HandleTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReceptionType : __UART_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxCpltCallback : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxEventCallback : __UART_HandleTypeDef
  • RxEventType : __UART_HandleTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SAI_HandleTypeDef
  • RxISR : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __I2S_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxXferSize : __I2S_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingMode : ADC_InitTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • Scale : CORDIC_ConfigTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecBank : FLASH_OBProgramInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SecSize : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • Size : MPU_Region_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • State : __OPAMP_HandleTypeDef , __FMAC_HandleTypeDef , __I2S_HandleTypeDef , CRC_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __CORDIC_HandleTypeDef , __TIM_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __LPTIM_HandleTypeDef , __SMBUS_HandleTypeDef , __RTC_HandleTypeDef , __SPI_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef , __OPAMP_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StopBits : UART_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- t -

  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • TimeFormat : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimerControlledMuxmode : OPAMP_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransitionErrorCallback : __TIM_HandleTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • transwin : LL_UCPD_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef , LL_DAC_InitTypeDef
  • TriggerSource2 : LL_DAC_InitTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoEmptyCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __FDCAN_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SPI_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SAI_HandleTypeDef
  • TxISR : __USART_HandleTypeDef , __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- w -

  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WordLength : SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef , USART_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
  • WrState : __FMAC_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
  • x
  • y

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32g4xx_hal_conf.h File Reference

HAL configuration template file. This file should be copied to the application folder and renamed to stm32g4xx_hal_conf.h. More...

#include "stm32g4xx_hal_rcc.h"
#include "stm32g4xx_hal_gpio.h"
#include "stm32g4xx_hal_dma.h"
#include "stm32g4xx_hal_cortex.h"
#include "stm32g4xx_hal_adc.h"
#include "stm32g4xx_hal_comp.h"
#include "stm32g4xx_hal_cordic.h"
#include "stm32g4xx_hal_crc.h"
#include "stm32g4xx_hal_cryp.h"
#include "stm32g4xx_hal_dac.h"
#include "stm32g4xx_hal_exti.h"
#include "stm32g4xx_hal_fdcan.h"
#include "stm32g4xx_hal_flash.h"
#include "stm32g4xx_hal_fmac.h"
#include "stm32g4xx_hal_hrtim.h"
#include "stm32g4xx_hal_irda.h"
#include "stm32g4xx_hal_iwdg.h"
#include "stm32g4xx_hal_i2c.h"
#include "stm32g4xx_hal_i2s.h"
#include "stm32g4xx_hal_lptim.h"
#include "stm32g4xx_hal_nand.h"
#include "stm32g4xx_hal_nor.h"
#include "stm32g4xx_hal_opamp.h"
#include "stm32g4xx_hal_pcd.h"
#include "stm32g4xx_hal_pwr.h"
#include "stm32g4xx_hal_qspi.h"
#include "stm32g4xx_hal_rng.h"
#include "stm32g4xx_hal_rtc.h"
#include "stm32g4xx_hal_sai.h"
#include "stm32g4xx_hal_smartcard.h"
#include "stm32g4xx_hal_smbus.h"
#include "stm32g4xx_hal_spi.h"
#include "stm32g4xx_hal_sram.h"
#include "stm32g4xx_hal_tim.h"
#include "stm32g4xx_hal_uart.h"
#include "stm32g4xx_hal_usart.h"
#include "stm32g4xx_hal_wwdg.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORDIC_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_EXTI_MODULE_ENABLED
#define | HAL_FDCAN_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_FMAC_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HRTIM_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_OPAMP_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | USE_HAL_ADC_REGISTER_CALLBACKS 1U
This is the list of modules where register callback can be used.
#define | USE_HAL_COMP_REGISTER_CALLBACKS 1U
#define | USE_HAL_CORDIC_REGISTER_CALLBACKS 1U
#define | USE_HAL_CRYP_REGISTER_CALLBACKS 1U
#define | USE_HAL_DAC_REGISTER_CALLBACKS 1U
#define | USE_HAL_EXTI_REGISTER_CALLBACKS 1U
#define | USE_HAL_FDCAN_REGISTER_CALLBACKS 1U
#define | USE_HAL_FMAC_REGISTER_CALLBACKS 1U
#define | USE_HAL_HRTIM_REGISTER_CALLBACKS 1U
#define | USE_HAL_I2C_REGISTER_CALLBACKS 1U
#define | USE_HAL_I2S_REGISTER_CALLBACKS 1U
#define | USE_HAL_IRDA_REGISTER_CALLBACKS 1U
#define | USE_HAL_LPTIM_REGISTER_CALLBACKS 1U
#define | USE_HAL_NAND_REGISTER_CALLBACKS 1U
#define | USE_HAL_NOR_REGISTER_CALLBACKS 1U
#define | USE_HAL_OPAMP_REGISTER_CALLBACKS 1U
#define | USE_HAL_PCD_REGISTER_CALLBACKS 1U
#define | USE_HAL_QSPI_REGISTER_CALLBACKS 1U
#define | USE_HAL_RNG_REGISTER_CALLBACKS 1U
#define | USE_HAL_RTC_REGISTER_CALLBACKS 1U
#define | USE_HAL_SAI_REGISTER_CALLBACKS 1U
#define | USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U
#define | USE_HAL_SMBUS_REGISTER_CALLBACKS 1U
#define | USE_HAL_SPI_REGISTER_CALLBACKS 1U
#define | USE_HAL_SRAM_REGISTER_CALLBACKS 1U
#define | USE_HAL_TIM_REGISTER_CALLBACKS 1U
#define | USE_HAL_UART_REGISTER_CALLBACKS 1U
#define | USE_HAL_USART_REGISTER_CALLBACKS 1U
#define | USE_HAL_WWDG_REGISTER_CALLBACKS 1U
#define | HSE_VALUE (8000000UL)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT (100UL)
#define | HSI_VALUE (16000000UL)
Internal High Speed oscillator (HSI) value.
#define | HSI48_VALUE (48000000UL)
Internal High Speed oscillator (HSI48) value for USB FS and RNG.
#define | LSI_VALUE (32000UL)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE (32768UL)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT (5000UL)
#define | EXTERNAL_CLOCK_VALUE (48000UL)
External clock source for I2S and SAI peripherals This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE (3300UL)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY (0x0FUL)
#define | USE_RTOS 0U
#define | PREFETCH_ENABLE 0U
#define | INSTRUCTION_CACHE_ENABLE 1U
#define | DATA_CACHE_ENABLE 1U
#define | USE_SPI_CRC 1U
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
#define | assert_param(expr) ((void)0U)
Include module's header file.

Detailed Description

HAL configuration template file. This file should be copied to the application folder and renamed to stm32g4xx_hal_conf.h.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Include module's header file.

Definition at line 371 of file stm32g4xx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_MassErase(), FLASH_OB_BootLockConfig(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), FLASH_PageErase(), FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FMAC_FilterConfig(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_StartSampling(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_StopSampling(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Stop(), HAL_CORDIC_Calculate_DMA(), HAL_CORDIC_Configure(), HAL_CORDIC_DeInit(), HAL_CORDIC_Init(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_DualStart(), HAL_DACEx_DualStart_DMA(), HAL_DACEx_DualStop(), HAL_DACEx_DualStop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SawtoothWaveDataReset(), HAL_DACEx_SawtoothWaveDataStep(), HAL_DACEx_SawtoothWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), HAL_DACEx_TriangleWaveGenerate(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_RegisterCallback(), HAL_EXTI_SetConfigLine(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_Init(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_EnableSecMemProtection(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_FMAC_DeInit(), HAL_FMAC_Init(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_LockTimerMux(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ConfigPVM(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableGPIOPullDown(), HAL_PWREx_EnableGPIOPullUp(), HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSConfig(), HAL_RCCEx_CRSGetSynchronizationInfo(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_Init(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SAIEx_ConfigPdmMicDelay(), HAL_SetTickFreq(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUSEx_DisableFastModePlus(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableFastModePlus(), HAL_SMBUSEx_EnableWakeUp(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_GetChannelState(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigAsymmetricalDeadTime(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_ConfigDeadTime(), HAL_TIMEx_ConfigEncoderIndex(), HAL_TIMEx_ConfigSlaveModePreload(), HAL_TIMEx_DisableAsymmetricalDeadTime(), HAL_TIMEx_DisableDeadTimePreload(), HAL_TIMEx_DisableEncoderFirstIndex(), HAL_TIMEx_DisableEncoderIndex(), HAL_TIMEx_DisableSlaveModePreload(), HAL_TIMEx_DisarmBreakInput(), HAL_TIMEx_DitheringDisable(), HAL_TIMEx_DitheringEnable(), HAL_TIMEx_EnableAsymmetricalDeadTime(), HAL_TIMEx_EnableDeadTimePreload(), HAL_TIMEx_EnableEncoderFirstIndex(), HAL_TIMEx_EnableEncoderIndex(), HAL_TIMEx_EnableSlaveModePreload(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OC_ConfigPulseOnCompare(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_ReArmBreakInput(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_ReceiverTimeout_Config(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), HAL_WWDG_Init(), I2C_TransferConfig(), IRDA_SetConfig(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define DATA_CACHE_ENABLE 1U

Definition at line 186 of file stm32g4xx_hal_conf.h.

#define EXTERNAL_CLOCK_VALUE (48000UL)

External clock source for I2S and SAI peripherals This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source frequency, this source is inserted directly through I2S_CKIN pad.

Value of the External clock source in Hz

Definition at line 171 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetI2SClockFreq(), and LL_RCC_GetSAIClockFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 37 of file stm32g4xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 38 of file stm32g4xx_hal_conf.h.

#define HAL_CORDIC_MODULE_ENABLED

Definition at line 39 of file stm32g4xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 40 of file stm32g4xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 41 of file stm32g4xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 42 of file stm32g4xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 43 of file stm32g4xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 44 of file stm32g4xx_hal_conf.h.

#define HAL_EXTI_MODULE_ENABLED

Definition at line 45 of file stm32g4xx_hal_conf.h.

#define HAL_FDCAN_MODULE_ENABLED

Definition at line 46 of file stm32g4xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 47 of file stm32g4xx_hal_conf.h.

#define HAL_FMAC_MODULE_ENABLED

Definition at line 48 of file stm32g4xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 49 of file stm32g4xx_hal_conf.h.

#define HAL_HRTIM_MODULE_ENABLED

Definition at line 50 of file stm32g4xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 53 of file stm32g4xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 54 of file stm32g4xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 51 of file stm32g4xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 52 of file stm32g4xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 55 of file stm32g4xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 36 of file stm32g4xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 56 of file stm32g4xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 57 of file stm32g4xx_hal_conf.h.

#define HAL_OPAMP_MODULE_ENABLED

Definition at line 58 of file stm32g4xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 59 of file stm32g4xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 60 of file stm32g4xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 61 of file stm32g4xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 62 of file stm32g4xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 63 of file stm32g4xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 64 of file stm32g4xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 65 of file stm32g4xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 66 of file stm32g4xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 67 of file stm32g4xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 68 of file stm32g4xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 69 of file stm32g4xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 70 of file stm32g4xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 71 of file stm32g4xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 72 of file stm32g4xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 73 of file stm32g4xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT (100UL)

Time out for HSE start up, in ms

Definition at line 121 of file stm32g4xx_hal_conf.h.

#define HSE_VALUE (8000000UL)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 117 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetFDCANClockFreq(), RCC_GetSysClockFreqFromPLLSource(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_SYS().

#define HSI48_VALUE (48000000UL)

Internal High Speed oscillator (HSI48) value for USB FS and RNG.

This internal oscillator is mainly dedicated to provide a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. When the CRS is not used, the HSI48 RC oscillator runs on it default frequency which is subject to manufacturing process variations. Value of the Internal High Speed oscillator for USB FS/RNG in Hz. The real value my vary depending on manufacturing process variations.

Definition at line 141 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSBClockFreq().

#define HSI_VALUE (16000000UL)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 130 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCC_DeInit(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetSysClockFreqFromPLLSource(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_SYS(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define INSTRUCTION_CACHE_ENABLE 1U

Definition at line 185 of file stm32g4xx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT (5000UL)

Time out for LSE start up, in ms

Definition at line 162 of file stm32g4xx_hal_conf.h.

#define LSE_VALUE (32768UL)

External Low Speed oscillator (LSE) value.

This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 158 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE (32000UL)

Internal Low Speed oscillator (LSI) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. LSI Typical Value in Hz

Definition at line 151 of file stm32g4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define PREFETCH_ENABLE 0U

Definition at line 184 of file stm32g4xx_hal_conf.h.

#define TICK_INT_PRIORITY (0x0FUL)

tick interrupt priority

Definition at line 182 of file stm32g4xx_hal_conf.h.

Referenced by HAL_Init().

#define USE_HAL_ADC_REGISTER_CALLBACKS 1U

This is the list of modules where register callback can be used.

Definition at line 80 of file stm32g4xx_hal_conf.h.

#define USE_HAL_COMP_REGISTER_CALLBACKS 1U

Definition at line 81 of file stm32g4xx_hal_conf.h.

#define USE_HAL_CORDIC_REGISTER_CALLBACKS 1U

Definition at line 82 of file stm32g4xx_hal_conf.h.

#define USE_HAL_CRYP_REGISTER_CALLBACKS 1U

Definition at line 83 of file stm32g4xx_hal_conf.h.

#define USE_HAL_DAC_REGISTER_CALLBACKS 1U

Definition at line 84 of file stm32g4xx_hal_conf.h.

#define USE_HAL_EXTI_REGISTER_CALLBACKS 1U

Definition at line 85 of file stm32g4xx_hal_conf.h.

#define USE_HAL_FDCAN_REGISTER_CALLBACKS 1U

Definition at line 86 of file stm32g4xx_hal_conf.h.

#define USE_HAL_FMAC_REGISTER_CALLBACKS 1U

Definition at line 87 of file stm32g4xx_hal_conf.h.

#define USE_HAL_HRTIM_REGISTER_CALLBACKS 1U

Definition at line 88 of file stm32g4xx_hal_conf.h.

#define USE_HAL_I2C_REGISTER_CALLBACKS 1U

Definition at line 89 of file stm32g4xx_hal_conf.h.

#define USE_HAL_I2S_REGISTER_CALLBACKS 1U

Definition at line 90 of file stm32g4xx_hal_conf.h.

#define USE_HAL_IRDA_REGISTER_CALLBACKS 1U

Definition at line 91 of file stm32g4xx_hal_conf.h.

#define USE_HAL_LPTIM_REGISTER_CALLBACKS 1U

Definition at line 92 of file stm32g4xx_hal_conf.h.

#define USE_HAL_NAND_REGISTER_CALLBACKS 1U

Definition at line 93 of file stm32g4xx_hal_conf.h.

#define USE_HAL_NOR_REGISTER_CALLBACKS 1U

Definition at line 94 of file stm32g4xx_hal_conf.h.

#define USE_HAL_OPAMP_REGISTER_CALLBACKS 1U

Definition at line 95 of file stm32g4xx_hal_conf.h.

#define USE_HAL_PCD_REGISTER_CALLBACKS 1U

Definition at line 96 of file stm32g4xx_hal_conf.h.

#define USE_HAL_QSPI_REGISTER_CALLBACKS 1U

Definition at line 97 of file stm32g4xx_hal_conf.h.

#define USE_HAL_RNG_REGISTER_CALLBACKS 1U

Definition at line 98 of file stm32g4xx_hal_conf.h.

#define USE_HAL_RTC_REGISTER_CALLBACKS 1U

Definition at line 99 of file stm32g4xx_hal_conf.h.

#define USE_HAL_SAI_REGISTER_CALLBACKS 1U

Definition at line 100 of file stm32g4xx_hal_conf.h.

#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U

Definition at line 101 of file stm32g4xx_hal_conf.h.

#define USE_HAL_SMBUS_REGISTER_CALLBACKS 1U

Definition at line 102 of file stm32g4xx_hal_conf.h.

#define USE_HAL_SPI_REGISTER_CALLBACKS 1U

Definition at line 103 of file stm32g4xx_hal_conf.h.

#define USE_HAL_SRAM_REGISTER_CALLBACKS 1U

Definition at line 104 of file stm32g4xx_hal_conf.h.

#define USE_HAL_TIM_REGISTER_CALLBACKS 1U

Definition at line 105 of file stm32g4xx_hal_conf.h.

#define USE_HAL_UART_REGISTER_CALLBACKS 1U

Definition at line 106 of file stm32g4xx_hal_conf.h.

#define USE_HAL_USART_REGISTER_CALLBACKS 1U

Definition at line 107 of file stm32g4xx_hal_conf.h.

#define USE_HAL_WWDG_REGISTER_CALLBACKS 1U

Definition at line 108 of file stm32g4xx_hal_conf.h.

#define USE_RTOS 0U

Definition at line 183 of file stm32g4xx_hal_conf.h.

#define USE_SPI_CRC 1U

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Definition at line 202 of file stm32g4xx_hal_conf.h.

#define VDD_VALUE (3300UL)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 181 of file stm32g4xx_hal_conf.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
              or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA channels. The output channel should have higher
                 priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().

      (#)Initialize the CRYP according to the specified parameters :
         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
         (##) The key size: 128, 192 or 256.
         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
         (##) The initialization vector (counter). It is not used in ECB mode.
         (##) The key buffer used for encryption/decryption.
             (+++) In some specific configurations, the key is written by the application
                   code out of the HAL scope. In that case, user can still resort to the
                   HAL APIs as usual but must make sure that pKey pointer is set to NULL.
         (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
               algorithms) is in words or bytes.
         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
         (##) The HeaderSize providing the size of the header buffer in words or bytes,
              depending upon HeaderWidthUnit field.
         (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms)
              is in words or bytes.
         (##) The B0 block is the first authentication block used only in AES CCM mode.
         (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is configured and processes the buffer in input.
         At second call, no need to Initialize the CRYP, user have to get current configuration via
         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
         new parameters, finally user can  start encryption/decryption.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.

       (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
          without having to configure again the Key or the Initialization Vector between each API call,
          the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
          Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
          or HAL_CRYP_Decrypt_DMA().

    [..]
      The cryptographic processor supports following standards:
      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
         (##)64-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
         (##) keys length supported :64-bit, 128-bit and 192-bit.
      (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
         (##)128-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
             (+++)  Counter mode (CTR)
             (+++)  Galois/counter mode (GCM/GMAC)
             (+++)  Counter with Cipher Block Chaining-Message(CCM)
         (##) keys length Supported :
             (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
             (+++) for TinyAES peripheral:  128-bit and 256-bit

    [..]
    (@) Specific care must be taken to format the key and the Initialization Vector IV!

    [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
         b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
         (+) as a sequence of words where the MSB word comes first (occupies the
           lowest memory address)
          (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
          (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
          (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
          (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
     [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
         The 4 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+0 : 0x B15 B14 B13 B12
          (+)    address n+4 : 0x B11 B10 B9 B8
          (+)    address n+8 : 0x B7 B6 B5 B4
          (+)    address n+C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
          The 8 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+00 : 0x B31 B30 B29 B28
          (+)    address n+04 : 0x B27 B26 B25 B24
          (+)    address n+08 : 0x B23 B22 B21 B20
          (+)    address n+0C : 0x B19 B18 B17 B16
          (+)    address n+10 : 0x B15 B14 B13 B12
          (+)    address n+14 : 0x B11 B10 B9 B8
          (+)    address n+18 : 0x B7 B6 B5 B4
          (+)    address n+1C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR7 = 0x B31 B30 B29 B28
       (+)       AES_KEYR6 = 0x B27 B26 B25 B24
       (+)       AES_KEYR5 = 0x B23 B22 B21 B20
       (+)       AES_KEYR4 = 0x B19 B18 B17 B16
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..] Initialization Vector IV (4 32-bit words) format must follow the same as
         that of a 128-bit long key.

    [..] Note that key and IV registers are not sensitive to swap mode selection.

    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
      (#)  Algorithm supported :
         (##) Galois/counter mode (GCM)
         (##) Galois message authentication code (GMAC) :is exactly the same as
              GCM algorithm composed only by an header.
      (#)  Four phases are performed in GCM :
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)  structure of message construction in GCM is defined as below  :
         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
          this part of the message is only authenticated, not encrypted.
         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
          GCM standard specifies that ciphertext has same bit length as the plaintext.
         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
          (on 64 bits)

    [..]  A more detailed description of the GCM message structure is available below.

    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
          Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
      (#)  Specific parameters for CCM  :

         (##) B0 block  : follows NIST Special Publication 800-38C,
         (##) B1 block (header)
         (##) CTRx block  : control blocks

    [..]  A detailed description of the CCM message structure is available below.

      (#)  Four phases are performed in CCM for CRYP1 peripheral:
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)    CCM in TinyAES peripheral:
         (##) To perform message payload encryption or decryption AES is configured in CTR mode.
         (##) For authentication two phases are performed :
          - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
          only cleartext payload (not the ciphertext payload) is used and no output.
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.

  *** Callback registration ***
  =============================

  [..]
  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
  to register an interrupt callback.

  [..]
  Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.

  [..]
  By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
  or HAL_CRYP_Init() function.

  [..]
  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

  *** Suspend/Resume feature ***
  ==============================

  [..]
  The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
  allows the user to resort to the suspend/resume feature.
  A low priority block processing can be suspended to process a high priority block
  instead. When the high priority block processing is over, the low priority block
  processing can be resumed, restarting from the point where it was suspended. This
  feature is applicable only in non-blocking interrupt mode.

  [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
  processing. This API manages the hardware block processing suspension and saves all the
  internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
  the user can launch the processing of any other block (high priority block processing).

  [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
  to resume the low priority block processing. Ciphering (or deciphering) restarts from
  the suspension point and ends as usual.

  [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
  (i.e when the low priority block processing is about to end). There is no use to
  suspend the tag generation processing for authentication algorithms.

    [..]
    (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
        the block processing suspension/resumption mechanism is NOT applicable.

    [..]
    (@) If the Key and Initialization Vector are configured only once and configuration is
        skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
        the block processing suspension/resumption mechanism is NOT applicable.

Definition in file stm32g4xx_hal_cryp.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_cryp.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cryp_ex.c File Reference

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_cryp_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cryp_ex.h File Reference

Header file of CRYPEx HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of CRYPEx HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_cryp_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_hrtim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_hrtim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

==============================================================================
                      ##### Simple mode v.s. waveform mode #####
==============================================================================
  [..] The HRTIM HAL API is split into 2 categories:
    (#)Simple functions: these functions allow for using a HRTIM timer as a
       general purpose timer with high resolution capabilities.
       HRTIM simple modes are managed through the set of functions named
       HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
       to the one defined for the TIM peripheral. When a HRTIM timer operates in
       simple mode, only a very limited set of HRTIM features are used.
       Following simple modes are proposed:
         (++)Output compare mode,
         (++)PWM output mode,
         (++)Input capture mode,
         (++)One pulse mode.
    (#)Waveform functions: These functions allow taking advantage of the HRTIM
       flexibility to produce numerous types of control signal. When a HRTIM timer
       operates in waveform mode, all the HRTIM features are accessible without
       any restriction. HRTIM waveform modes are managed through the set of
       functions named HAL_HRTIM_Waveform<Function>

==============================================================================
                      ##### How to use this driver #####
==============================================================================
    [..]
     (#)Initialize the HRTIM low level resources by implementing the
        HAL_HRTIM_MspInit() function:
        (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
        (##)Connect HRTIM pins to MCU I/Os
            (+++) Enable the clock for the HRTIM GPIOs using the following
                  function: __HAL_RCC_GPIOx_CLK_ENABLE()
            (+++) Configure these GPIO pins in Alternate Function mode using
                  HAL_GPIO_Init()
        (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
            (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++)Initialize the DMA handle
            (+++)Associate the initialized DMA handle to the appropriate DMA
                 handle of the HRTIM handle using __HAL_LINKDMA()
            (+++)Initialize the DMA channel using HAL_DMA_Init()
            (+++)Configure the priority and enable the NVIC for the transfer
                 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
                 and HAL_NVIC_EnableIRQ()
        (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
            (+++)Configure the priority and enable the NVIC for the concerned
                 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

    (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
       structure (field of the HRTIM handle) specifies which global interrupt of
       whole HRTIM must be enabled (Burst mode period, System fault, Faults).
       It also contains the HRTIM external synchronization configuration. HRTIM
       can act as a master (generating a synchronization signal) or as a slave
       (waiting for a trigger to be synchronized).

    (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
       calibration is executed periodically and compensate for potential voltage
       and temperature drifts. DLL calibration period is specified by the
       CalibrationRate argument.

    (#)HRTIM timers cannot be used until the high resolution unit is ready. This
       can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
       HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
       is still going on when timeout given as argument expires. DLL calibration
       can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
       In that case an interrupt is generated when the DLL calibration is completed.
       Note that as DLL calibration is executed on a periodic basis an interrupt
       will be generated at the end of every DLL calibration operation
      (worst case: one interrupt every 14 micro seconds !).

     (#) Configure HRTIM resources shared by all HRTIM timers
        (##)Burst Mode Controller:
                (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
                     controller: operating mode (continuous or one-shot mode), clock
                     (source, prescaler) , trigger(s), period, idle duration.
        (##)External Events Conditioning:
                (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
                     external event channel: source, polarity, edge-sensitivity.
                     External event can be used as triggers (timer reset, input
                     capture, burst mode, ADC triggers, delayed protection)
                     They can also be used to set or reset timer outputs. Up to
                     10 event channels are available.
                (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
                     event sampling clock (used for digital filtering).
        (##)Fault Conditioning:
                (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
                     fault channel: source, polarity, edge-sensitivity. Fault
                     channels are used to disable the outputs in case of an
                     abnormal operation. Up to 6 fault channels are available.
                (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
                     sampling clock (used for digital filtering).
                (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
                     circuitry. By default all fault inputs are disabled.
        (##)ADC trigger:
                (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
                     the update of the ADC trigger register and the ADC trigger.
                     4 independent triggers are available to start both the regular
                     and the injected sequencers of the 2 ADCs

     (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
         function must be called whatever the HRTIM timer operating mode is
         (simple v.s. waveform). It configures mainly:
        (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
        (##)The HRTIM  timer clock prescaler
        (##)The HRTIM  timer period
        (##)The HRTIM  timer repetition counter

     *** If the HRTIM timer operates in simple mode ***
     ===================================================
     [..]
     (#) Start or Stop simple timers
              (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
                  HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
                  HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
              (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
                  HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
                  HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
                  HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
              (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
                  HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
                  HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
                  HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
              (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
                  HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
                  HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
                  HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
              (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
                  HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
                  HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().

     *** If the HRTIM timer operates in waveform mode ***
     ====================================================
     [..]
     (#) Completes waveform timer configuration
              (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
                  operating in wave form mode mainly consists in:
                (+++)Enabling the HRTIM timer interrupts and DMA requests.
                (+++)Enabling the half mode for the HRTIM timer.
                (+++)Defining how the HRTIM timer reacts to external synchronization input.
                (+++)Enabling the push-pull mode for the HRTIM timer.
                (+++)Enabling the fault channels for the HRTIM timer.
                (+++)Enabling the dead-time insertion for the HRTIM timer.
                (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
                     on which the delayed protection are applied).
                (+++)Specifying the HRTIM timer update and reset triggers.
                (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
              (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
                  event blanking and windowing circuitry of a HRTIM timer:
                (+++)Blanking:  to mask external events during a defined  time period a defined time period
                (+++)Windowing, to enable external events only during a defined time period
              (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
                  unit for a HRTIM timer. Allows to generate a couple of
                  complementary signals from a single reference waveform,
                  with programmable delays between active state.
              (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
                  the high-frequency carrier signal added on top of the timing
                  unit output. Chopper mode can be enabled or disabled for each
                   timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
              (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
                  controller. Allows having multiple HRTIM registers updated
                  with a single DMA request. The burst DMA operation is started
                  by calling HAL_HRTIM_BurstDMATransfer().
              (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
                  of a HRTIM timer. This operation consists in setting the
                  compare value and possibly specifying the auto delayed mode
                  for compare units 2 and 4 (allows to have compare events
                  generated relatively to capture events). Note that when auto
                  delayed mode is needed, the capture unit associated to the
                  compare unit must be configured separately.
              (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
                  of a HRTIM timer. This operation consists in specifying the
                  source(s)  triggering the capture (timer register update event,
                  external event, timer output set/reset event, other HRTIM
                  timer related events).
              (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
                  output mainly consists in:
                (+++)Setting the output polarity (active high or active low),
                (+++)Defining the set/reset crossbar for the output,
                (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,

     (#) Set waveform timer output(s) level
              (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
                  active or inactive level. For example, when deadtime insertion
                  is enabled it is necessary to force the output level by software
                  to have the outputs in a complementary state as soon as the RUN mode is entered.

     (#) Enable or Disable waveform timer output(s)
              (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().

     (#) Start or Stop waveform HRTIM timer(s).
              (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
              (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
              (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
     (#) Burst mode controller enabling:
              (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
                  burst mode controller.

     (#) Some HRTIM operations can be triggered by software:
              (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
                  trigs the burst operation.
              (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
                  capture of the HRTIM timer counter.
              (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
                  update of the pre-loadable registers of the HRTIM timer
              (++)HAL_HRTIM_SoftwareReset():calling this function resets the
                  HRTIM timer counter.

     (#) Some functions can be used any time to retrieve HRTIM timer related
            information
              (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
                  capture register of the designated capture unit.
              (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
                 (ACTIVE/INACTIVE) of the designated timer output.
              (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
                 (IDLE/RUN/FAULT) of the designated timer output.
              (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
                 (ACTIVE/INACTIVE) of the designated output when the delayed
                  protection was triggered.
              (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
                 (ACTIVE/INACTIVE) of the burst mode controller.
              (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the push-pull status indicates on which output the signal is currently
                 active (e.g signal applied on output 1 and output 2 forced
                 inactive or vice versa).
             (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
                 the idle push-pull status indicates during which period the
                 delayed protection request occurred (e.g. protection occurred
                 when the output 1 was active and output 2 forced inactive or
                 vice versa).

     (#) Some functions can be used any time to retrieve actual HRTIM status
             (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.

     *** Callback registration ***
     =============================
     [..]
     The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
     to register an interrupt callback.

     [..]
     Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
       (+) Fault1Callback               : Fault 1 interrupt callback function
       (+) Fault2Callback               : Fault 2 interrupt callback function
       (+) Fault3Callback               : Fault 3 interrupt callback function
       (+) Fault4Callback               : Fault 4 interrupt callback function
       (+) Fault5Callback               : Fault 5 interrupt callback function
       (+) Fault6Callback               : Fault 6 interrupt callback function
       (+) SystemFaultCallback          : System fault interrupt callback function
       (+) DLLCalibrationReadyCallback  : DLL Ready interrupt callback function
       (+) BurstModePeriodCallback      : Burst mode period interrupt callback function
       (+) SynchronizationEventCallback : Sync Input interrupt callback function
       (+) ErrorCallback                : DMA error callback function
       (+) MspInitCallback              : HRTIM MspInit callback function
       (+) MspDeInitCallback            : HRTIM MspInit callback function

     [..]
     Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
       (+) RegistersUpdateCallback   : Timer x Update interrupt callback function
       (+) RepetitionEventCallback   : Timer x Repetition interrupt callback function
       (+) Compare1EventCallback     : Timer x Compare 1 match interrupt callback function
       (+) Compare2EventCallback     : Timer x Compare 2 match interrupt callback function
       (+) Compare3EventCallback     : Timer x Compare 3 match interrupt callback function
       (+) Compare4EventCallback     : Timer x Compare 4 match interrupt callback function
       (+) Capture1EventCallback     : Timer x Capture 1 interrupts callback function
       (+) Capture2EventCallback     : Timer x Capture 2 interrupts callback function
       (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
       (+) CounterResetCallback      : Timer x counter reset/roll-over interrupt callback function
       (+) Output1SetCallback        : Timer x output 1 set interrupt callback function
       (+) Output1ResetCallback      : Timer x output 1 reset interrupt callback function
       (+) Output2SetCallback        : Timer x output 2 set interrupt callback function
       (+) Output2ResetCallback      : Timer x output 2 reset interrupt callback function
       (+) BurstDMATransferCallback  : Timer x Burst DMA completed interrupt callback function

     [..]
     Both functions take as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.

     [..]
     Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
     to reset a callback to the default weak function. Both functions take  as parameters
     the HAL peripheral handle and the Callback ID.

     [..]
     By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
     all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
     Exception done for MspInit and MspDeInit functions that are reset to the legacy
     weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
     callbacks are null (not registered beforehand). If MspInit or MspDeInit are
     not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
     MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

     [..]
     Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
     (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
     or HAL_HRTIM_Init() function.

     [..]
     When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all
     callbacks are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_hrtim.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_hrtim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_hrtim.h File Reference

Header file of HRTIM HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of HRTIM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_hrtim.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nand.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions HAL_NAND_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : NAND MspInit.
        (+) MspDeInitCallback  : NAND MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
      weak (overridden) function. It allows to reset following callbacks:
        (+) MspInitCallback    : NAND MspInit.
        (+) MspDeInitCallback  : NAND MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (overridden) functions in the HAL_NAND_Init
      and  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
      or HAL_NAND_Init function.

      When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (overridden) callbacks are used.

Definition in file stm32g4xx_hal_nand.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nand.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_nand.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nor.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions HAL_NOR_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : NOR MspInit.
        (+) MspDeInitCallback  : NOR MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
      weak (overridden) function. It allows to reset following callbacks:
        (+) MspInitCallback    : NOR MspInit.
        (+) MspDeInitCallback  : NOR MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (overridden) functions in the HAL_NOR_Init
      and  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
      or HAL_NOR_Init function.

      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (overridden) callbacks are used.

Definition in file stm32g4xx_hal_nor.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nor.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_nor.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_opamp_ex.c File Reference

Extended OPAMP HAL module driver. More...

Go to the source code of this file.

HAL_StatusTypeDef OPAMP_HandleTypeDef * | hopamp2
HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1
 | Run the self calibration of up to 6 OPAMPs in parallel.
HAL_StatusTypeDef OPAMP_HandleTypeDef OPAMP_HandleTypeDef *hopamp3 HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6)

Detailed Description

Extended OPAMP HAL module driver.

Author:
MCD Application Team This file provides firmware functions to manage the following functionalities of the operational amplifiers peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2019 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"

/** @addtogroup STM32G4xx_HAL_Driver
  * @{
  */

#ifdef HAL_OPAMP_MODULE_ENABLED

/** @defgroup OPAMPEx OPAMPEx
  * @brief OPAMP Extended HAL module driver
  * @{
  */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
  * @{
  */

/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
  * @brief    Extended Self calibration functions
  *
@verbatim
 ===============================================================================
              ##### Extended IO operation functions #####
 ===============================================================================
  [..]
      (+) OPAMP Self calibration.

Definition in file stm32g4xx_hal_opamp_ex.c.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2,
 |  | OPAMP_HandleTypeDef * | hopamp3,
 |  | OPAMP_HandleTypeDef * | hopamp4,
 |  | OPAMP_HandleTypeDef * | hopamp5,
 |  | OPAMP_HandleTypeDef * | hopamp6
 | ) |  |

Run the self calibration of up to 6 OPAMPs in parallel.

Note:
Calibration is performed in the mode specified in OPAMP init structure (mode normal or high-speed).
Parameters:
hopamp1 | handle
hopamp2 | handle
hopamp3 | handle
hopamp4 | handle (1)
hopamp5 | handle (1)
hopamp6 | handle (1) (1) Parameter not present on STM32GBK1CB/STM32G431xx/STM32G441xx/STM32G471xx devices.
Return values:
HAL status
Note:
Updated offset trimming values (PMOS & NMOS), user trimming is enabled
Calibration runs about 25 ms.
HAL_StatusTypeDef OPAMP_HandleTypeDef OPAMP_HandleTypeDef* hopamp3 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2,
 |  | OPAMP_HandleTypeDef * | hopamp3,
 |  | OPAMP_HandleTypeDef * | hopamp6
 | ) |  |

Definition at line 90 of file stm32g4xx_hal_opamp_ex.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_READY, __OPAMP_HandleTypeDef::Init, __OPAMP_HandleTypeDef::Instance, OPAMP_INPUT_INVERTING, OPAMP_INPUT_NONINVERTING, OPAMP_TRIMMING_USER, OPAMP_VREF_10VDDA, OPAMP_VREF_90VDDA, __OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueP, and OPAMP_InitTypeDef::UserTrimming.

Variable Documentation

HAL_StatusTypeDef OPAMP_HandleTypeDef* hopamp2

Definition at line 87 of file stm32g4xx_hal_opamp_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_qspi.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
              the transfer complete bit is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
      weak (overridden) function. It allows to reset following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (overridden) functions in the HAL_QSPI_Init
      and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
      or HAL_QSPI_Init function.

      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (overridden) callbacks are used.

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer

Definition in file stm32g4xx_hal_qspi.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_qspi.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_qspi.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sram.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()

       *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) MspInitCallback    : SRAM MspInit.
        (+) MspDeInitCallback  : SRAM MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
      weak (overridden) function. It allows to reset following callbacks:
        (+) MspInitCallback    : SRAM MspInit.
        (+) MspDeInitCallback  : SRAM MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
      and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
      or HAL_SRAM_Init function.

      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (overridden) callbacks are used.

Definition in file stm32g4xx_hal_sram.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sram.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_sram.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_adc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32g4xx_ll_adc.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (const ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_comp.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32g4xx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cordic.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_cordic.c File Reference

CORDIC LL module driver. More...

#include "stm32g4xx_ll_cordic.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CORDIC_DeInit (const CORDIC_TypeDef *CORDICx)
De-Initialize CORDIC peripheral registers to their default reset values.

Detailed Description

CORDIC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_cordic.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_cordic.c.

Referenced by LL_CORDIC_DeInit().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32g4xx_ll_crc.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (const CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dac.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32g4xx_ll_dac.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__)
#define | IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)

Functions

ErrorStatus | LL_DAC_DeInit (const DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_dac.c.

Referenced by LL_DAC_DeInit(), and LL_DAC_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dma.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32g4xx_ll_dma.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 115U)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_exti.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32g4xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 25 of file stm32g4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_fmac.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_fmac.c File Reference

Header for stm32g4xx_ll_fmac.c module. More...

#include "stm32g4xx_ll_fmac.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_FMAC_Init (FMAC_TypeDef *FMACx)
Initialize FMAC peripheral registers to their default reset values.
ErrorStatus | LL_FMAC_DeInit (const FMAC_TypeDef *FMACx)
De-Initialize FMAC peripheral registers to their default reset values.

Detailed Description

Header for stm32g4xx_ll_fmac.c module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_fmac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_fmac.c.

Referenced by LL_FMAC_DeInit(), and LL_FMAC_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_gpio.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32g4xx_ll_gpio.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_hrtim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines
stm32g4xx_ll_hrtim.c File Reference

HRTIM LL module driver. More...

#include "stm32g4xx_ll_hrtim.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0U)

Detailed Description

HRTIM LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_hrtim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_hrtim.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_hrtim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_hrtim.h File Reference

Header file of HRTIM LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Detailed Description

Header file of HRTIM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_hrtim.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_i2c.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32g4xx_ll_i2c.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

ErrorStatus | LL_I2C_DeInit (const I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lptim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_lptim.c File Reference

LPTIM LL module driver. More...

#include "stm32g4xx_ll_lptim.h"
#include "stm32g4xx_ll_bus.h"
#include "stm32g4xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Functions

ErrorStatus | LL_LPTIM_DeInit (const LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Detailed Description

LPTIM LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_lptim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 29 of file stm32g4xx_ll_lptim.c.

Referenced by LL_LPTIM_DeInit(), LL_LPTIM_Disable(), and LL_LPTIM_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lpuart.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_lpuart.c File Reference

LPUART LL module driver. More...

#include "stm32g4xx_ll_lpuart.h"
#include "stm32g4xx_ll_rcc.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | LPUART_DEFAULT_BAUDRATE (9600U)
#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 50000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

LPUART LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_lpuart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_lpuart.c.

Referenced by LL_LPUART_DeInit(), and LL_LPUART_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_opamp.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_opamp.c File Reference

OPAMP LL module driver. More...

#include "stm32g4xx_ll_opamp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

OPAMP LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_opamp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_opamp.c.

Referenced by LL_OPAMP_DeInit(), and LL_OPAMP_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rcc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32g4xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
#define | IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))

Functions

static uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
static uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
static uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
static uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
static uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
static uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock frequency used for ADC domain.
static uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock frequency used for 48 MHz domain.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN kernel clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 24 of file stm32g4xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rng.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_rng.c File Reference

RNG LL module driver. More...

#include "stm32g4xx_ll_rng.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RNG_CED(__MODE__)

Functions

ErrorStatus | LL_RNG_DeInit (const RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Detailed Description

RNG LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rng.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_rng.c.

Referenced by LL_RNG_DeInit(), and LL_RNG_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rtc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32g4xx_ll_rtc.h"
#include "stm32g4xx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
#define | RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
#define | RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
#define | IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMB field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_spi.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32g4xx_ll_spi.h"
#include "stm32g4xx_ll_bus.h"
#include "stm32g4xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U
#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32g4xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler(), LL_I2S_Init(), LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_tim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32g4xx_ll_tim.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK_AFMODE(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_AFMODE(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (const TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_ucpd.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_ucpd.c File Reference

UCPD LL module driver. More...

#include "stm32g4xx_ll_ucpd.h"
#include "stm32g4xx_ll_bus.h"
#include "stm32g4xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Detailed Description

UCPD LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_ucpd.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32g4xx_ll_ucpd.c.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_usart.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32g4xx_ll_usart.h"
#include "stm32g4xx_ll_rcc.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | USART_DEFAULT_BAUDRATE (9600U)
#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_utils.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32g4xx_ll_utils.h"
#include "stm32g4xx_ll_rcc.h"
#include "stm32g4xx_ll_system.h"
#include "stm32g4xx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_MAX_FREQUENCY_SCALE1 170000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 26000000U
#define | UTILS_PLLVCO_INPUT_MIN 2660000U
#define | UTILS_PLLVCO_INPUT_MAX 16000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 64000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U
#define | UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U
#define | UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U
#define | UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U
#define | UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 30000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 60000000U
#define | UTILS_SCALE1_LATENCY3_FREQ 90000000U
#define | UTILS_SCALE1_LATENCY4_FREQ 120000000U
#define | UTILS_SCALE1_LATENCY5_FREQ 150000000U
#define | UTILS_SCALE2_LATENCY1_FREQ 12000000U
#define | UTILS_SCALE2_LATENCY2_FREQ 24000000U
#define | UTILS_SCALE2_LATENCY3_FREQ 26000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_PTR_REG_OFFSET : stm32g4xx_ll_adc.h
  • __DAC_PTR_REG_OFFSET : stm32g4xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g4xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32g4xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32g4xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32g4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32g4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32g4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32g4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32g4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32g4xx_hal_adc.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32g4xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32g4xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32g4xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32g4xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32g4xx_hal_comp.h
  • __HAL_CORDIC_CLEAR_FLAG : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_CLEAR_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_DISABLE_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_ENABLE_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_FLAG : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_IT_SOURCE : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_RESET_HANDLE_STATE : stm32g4xx_hal_cordic.h
  • __HAL_CRC_DR_RESET : stm32g4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32g4xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32g4xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32g4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32g4xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32g4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32g4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32g4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32g4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32g4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32g4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32g4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32g4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32g4xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32g4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32g4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32g4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32g4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32g4xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32g4xx_hal_fdcan.h
  • __HAL_FLASH_CLEAR_FLAG : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32g4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32g4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32g4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32g4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FMAC_CLEAR_FLAG : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_CLEAR_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_DISABLE_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_ENABLE_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_FLAG : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_IT_SOURCE : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_RESET_HANDLE_STATE : stm32g4xx_hal_fmac.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32g4xx_hal_gpio.h
  • __HAL_I2C_CLEAR_FLAG : stm32g4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32g4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32g4xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32g4xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32g4xx_hal_i2s.h
  • __HAL_I2S_FLUSH_RX_DR : stm32g4xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32g4xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32g4xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32g4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32g4xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32g4xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32g4xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32g4xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32g4xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32g4xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32g4xx_hal_pwr_ex.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_ADC12_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2S_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32g4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32g4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32g4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32g4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32g4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_FALLING_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_RISING_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32g4xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32g4xx_hal_rtc.h
  • __HAL_RTC_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_IS_CALENDAR_INITIALIZED : stm32g4xx_hal_rtc.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32g4xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32g4xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32g4xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32g4xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32g4xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32g4xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32g4xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32g4xx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32g4xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32g4xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32g4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32g4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32g4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32g4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32g4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32g4xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_ERASE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32g4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32g4xx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32g4xx_hal.h
  • __HAL_TIM_CALC_PERIOD : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_BY_DELAY : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_DITHER : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PSC : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PULSE : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PULSE_DITHER : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CLEAR_FLAG : stm32g4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_UIFCPY : stm32g4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32g4xx_hal_tim.h
  • __HAL_TIM_SELECT_CCDMAREQUEST : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32g4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32g4xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32g4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32g4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32g4xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32g4xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32g4xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32g4xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32g4xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32g4xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g4xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32g4xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g4xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32g4xx_ll_adc.h
  • __LL_ADC_MULTI_INSTANCE_MASTER : stm32g4xx_ll_adc.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32g4xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32g4xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32g4xx_ll_dac.h
  • __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG : stm32g4xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32g4xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32g4xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32g4xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32g4xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32g4xx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32g4xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32g4xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_ARR_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32g4xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32g4xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32g4xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32g4xx_ll_usart.h
  • __LSCO_CLK_ENABLE : stm32g4xx_hal_rcc_ex.c
  • __OPAMP_PTR_REG_OFFSET : stm32g4xx_ll_opamp.h
  • __STM32G4xx_HAL_VERSION : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_MAIN : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_RC : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_SUB1 : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_SUB2 : stm32g4xx_hal.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC_ANALOGWATCHDOG_1 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32g4xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32g4xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_AWD_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_2SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_3SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_4SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_5SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_6SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_7SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_8SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_NONE : stm32g4xx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32g4xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32g4xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_AUTOWAIT : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32g4xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR_ADC1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR_ADC5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP3_ADC2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP3_ADC3 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP4 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP6 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32g4xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32g4xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32g4xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g4xx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32g4xx_hal_adc.c
  • ADC_ConversionStop() : stm32g4xx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32g4xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32g4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32g4xx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32g4xx_hal_adc_ex.h
  • ADC_Disable() : stm32g4xx_hal_adc.c
  • ADC_DISABLE_TIMEOUT : stm32g4xx_hal_adc.c
  • ADC_DMAACCESSMODE_12_10_BITS : stm32g4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_8_6_BITS : stm32g4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32g4xx_hal_adc_ex.h
  • ADC_DMAConvCplt() : stm32g4xx_hal_adc.c
  • ADC_DMAError() : stm32g4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32g4xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_Enable() : stm32g4xx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32g4xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32g4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32g4xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG10 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG5 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG6 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG7 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG8 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG9 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM_OUT : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T7_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM_OUT : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T16_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_CC2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T7_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32g4xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32g4xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32g4xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOC : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOS : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32g4xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32g4xx_hal_adc.h
  • ADC_FLAG_JEOS : stm32g4xx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32g4xx_hal_adc.h
  • ADC_FLAG_OVR : stm32g4xx_hal_adc.h
  • ADC_FLAG_RDY : stm32g4xx_hal_adc.h
  • ADC_FORCE_MODE_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32g4xx_hal_adc.h
  • ADC_HandleTypeDef : stm32g4xx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32g4xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32g4xx_hal_adc_ex.h
  • ADC_IS_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32g4xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32g4xx_hal_adc.h
  • ADC_IT_AWD2 : stm32g4xx_hal_adc.h
  • ADC_IT_AWD3 : stm32g4xx_hal_adc.h
  • ADC_IT_EOC : stm32g4xx_hal_adc.h
  • ADC_IT_EOS : stm32g4xx_hal_adc.h
  • ADC_IT_EOSMP : stm32g4xx_hal_adc.h
  • ADC_IT_JEOC : stm32g4xx_hal_adc.h
  • ADC_IT_JEOS : stm32g4xx_hal_adc.h
  • ADC_IT_JQOVF : stm32g4xx_hal_adc.h
  • ADC_IT_OVR : stm32g4xx_hal_adc.h
  • ADC_IT_RDY : stm32g4xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32g4xx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32g4xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32g4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SIGN_NEGATIVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SIGN_POSITIVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFRx_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32g4xx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32g4xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32g4xx_hal_adc.h
  • ADC_OVR_EVENT : stm32g4xx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32g4xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32g4xx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32g4xx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_BULB : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_NORMAL : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_TRIGGER_CONTROLED : stm32g4xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32g4xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32g4xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32g4xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32g4xx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32g4xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32g4xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_STATE_CLR_SET : stm32g4xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32g4xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32g4xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32g4xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32g4xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32g4xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32g4xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32g4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32g4xx_hal_adc_ex.h
  • assert_param : stm32g4xx_ll_opamp.c , stm32g4xx_ll_adc.c , stm32g4xx_ll_comp.c , stm32g4xx_ll_rng.c , stm32g4xx_ll_tim.c , stm32g4xx_ll_utils.c , stm32g4xx_ll_gpio.c , stm32g4xx_ll_fmac.c , stm32g4xx_hal_conf.h , stm32g4xx_ll_spi.c , stm32g4xx_ll_cordic.c , stm32g4xx_ll_i2c.c , stm32g4xx_ll_lpuart.c , stm32g4xx_ll_lptim.c , stm32g4xx_ll_exti.c , stm32g4xx_ll_rcc.c , stm32g4xx_ll_usart.c , stm32g4xx_ll_dac.c , stm32g4xx_ll_crc.c , stm32g4xx_ll_rtc.c , stm32g4xx_ll_ucpd.c , stm32g4xx_ll_hrtim.c , stm32g4xx_ll_dma.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CCMER_BitNumber : stm32g4xx_hal.c
  • CHANNEL_OFFSET_TAB : stm32g4xx_ll_dma.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM20_OC5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC4_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC4_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM4_OC3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP7 : stm32g4xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32g4xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32g4xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g4xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32g4xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32g4xx_hal_comp.h
  • COMP_EXTI_IT : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP3 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP4 : stm32g4xx_hal_comp.h
  • COMP_EXTI_RISING : stm32g4xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32g4xx_hal_comp.h
  • COMP_HandleTypeDef : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_10MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_20MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_30MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_40MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_50MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_60MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_70MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC2_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC3_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC3_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC4_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC4_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32g4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g4xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32g4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32g4xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32g4xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32g4xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32g4xx_hal_comp.h
  • CORDIC_DMA_DIR_IN : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_IN_OUT : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_NONE : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_OUT : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_REN : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_WEN : stm32g4xx_hal_cordic.h
  • CORDIC_DMAError() : stm32g4xx_hal_cordic.c
  • CORDIC_DMAInCplt() : stm32g4xx_hal_cordic.c
  • CORDIC_DMAOutCplt() : stm32g4xx_hal_cordic.c
  • CORDIC_FLAG_RRDY : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_ARCTANGENT : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_COSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HARCTANGENT : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HCOSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_MODULUS : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_NATURALLOG : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_PHASE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_SINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_SQUAREROOT : stm32g4xx_hal_cordic.h
  • CORDIC_HandleTypeDef : stm32g4xx_hal_cordic.h
  • CORDIC_INSIZE_16BITS : stm32g4xx_hal_cordic.h
  • CORDIC_INSIZE_32BITS : stm32g4xx_hal_cordic.h
  • CORDIC_IT_IEN : stm32g4xx_hal_cordic.h
  • CORDIC_NBREAD_1 : stm32g4xx_hal_cordic.h
  • CORDIC_NBREAD_2 : stm32g4xx_hal_cordic.h
  • CORDIC_NBWRITE_1 : stm32g4xx_hal_cordic.h
  • CORDIC_NBWRITE_2 : stm32g4xx_hal_cordic.h
  • CORDIC_OUTSIZE_16BITS : stm32g4xx_hal_cordic.h
  • CORDIC_OUTSIZE_32BITS : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_10CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_11CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_12CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_13CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_14CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_15CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_1CYCLE : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_2CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_3CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_4CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_5CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_6CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_7CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_8CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_9CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_ReadOutDataIncrementPtr() : stm32g4xx_hal_cordic.c
  • CORDIC_SCALE_0 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_1 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_2 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_3 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_4 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_5 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_6 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_7 : stm32g4xx_hal_cordic.h
  • CORDIC_WriteInDataIncrementPtr() : stm32g4xx_hal_cordic.c
  • CR_REG_INDEX : stm32g4xx_hal_rcc.h
  • CRC_Handle_16() : stm32g4xx_hal_crc.c
  • CRC_Handle_8() : stm32g4xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32g4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32g4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32g4xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32g4xx_hal_crc.h
  • CRRCR_REG_INDEX : stm32g4xx_hal_rcc.h
  • CSR_REG_INDEX : stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32g4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32g4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32g4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32g4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_BOTH : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_EXTERNAL : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_INTERNAL : stm32g4xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32g4xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32g4xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_DELAY_STARTUP_US : stm32g4xx_hal_dac.h
  • DAC_DELAY_TRIM_US : stm32g4xx_hal_dac_ex.c
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32g4xx_ll_dac.h
  • DAC_DMAConvCpltCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32g4xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32g4xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32g4xx_hal_dac_ex.c
  • DAC_FLAG_DAC1RDY : stm32g4xx_hal_dac.h
  • DAC_FLAG_DAC2RDY : stm32g4xx_hal_dac.h
  • DAC_FLAG_DMAUDR1 : stm32g4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32g4xx_hal_dac.h
  • DAC_HandleTypeDef : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE : stm32g4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32g4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32g4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32g4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32g4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32g4xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_STR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_STR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32g4xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32g4xx_hal_dac.h
  • DAC_SAWTOOTH_POLARITY_DECREMENT : stm32g4xx_hal_dac_ex.h
  • DAC_SAWTOOTH_POLARITY_INCREMENT : stm32g4xx_hal_dac_ex.h
  • DAC_SWTR_CH1 : stm32g4xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32g4xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CH1 : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CH2 : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CHX_MASK : stm32g4xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT10 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_EXT_IT9 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG1 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG2 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG3 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG4 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG5 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG6 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG1 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG2 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG3 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG4 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG5 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG6 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG01 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG02 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG03 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T3_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32g4xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32g4xx_hal_dac.h
  • DATA_CACHE_ENABLE : stm32g4xx_hal_conf.h
  • DBGMCU_REVID_POSITION : stm32g4xx_ll_system.h
  • DEFAULT_CRC32_POLY : stm32g4xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32g4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32g4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32g4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32g4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32g4xx_hal_crc.h
  • DIVIDER_P_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DLCtoBytes : stm32g4xx_hal_fdcan.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32g4xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32g4xx_hal_dma.c
  • DMA_CIRCULAR : stm32g4xx_hal_dma.h
  • DMA_CSELR_OFFSET : stm32g4xx_ll_dma.h
  • DMA_FLAG_GL1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32g4xx_hal_dma.h
  • DMA_HandleTypeDef : stm32g4xx_hal_dma.h
  • DMA_IT_HT : stm32g4xx_hal_dma.h
  • DMA_IT_TC : stm32g4xx_hal_dma.h
  • DMA_IT_TE : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32g4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32g4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32g4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32g4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32g4xx_hal_dma.h
  • DMA_NORMAL : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32g4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32g4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32g4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32g4xx_hal_dma.h
  • DMA_POSITION_CSELR_CXS : stm32g4xx_ll_dma.h
  • DMA_PRIORITY_HIGH : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32g4xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_AES_IN : stm32g4xx_hal_dma.h
  • DMA_REQUEST_AES_OUT : stm32g4xx_hal_dma.h
  • DMA_REQUEST_CORDIC_READ : stm32g4xx_hal_dma.h
  • DMA_REQUEST_CORDIC_WRITE : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC1_CHANNEL1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC1_CHANNEL2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC3_CHANNEL1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC3_CHANNEL2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_FMAC_READ : stm32g4xx_hal_dma.h
  • DMA_REQUEST_FMAC_WRITE : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UCPD1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UCPD1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32g4xx_hal_dma.h
  • DMA_SetConfig() : stm32g4xx_hal_dma.c
  • DMAMUX_CCR_SIZE : stm32g4xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32g4xx_ll_dmamux.h
  • DT_DELAY_1 : stm32g4xx_ll_tim.h
  • DT_DELAY_2 : stm32g4xx_ll_tim.h
  • DT_DELAY_3 : stm32g4xx_ll_tim.h
  • DT_DELAY_4 : stm32g4xx_ll_tim.h
  • DT_RANGE_1 : stm32g4xx_ll_tim.h
  • DT_RANGE_2 : stm32g4xx_ll_tim.h
  • DT_RANGE_3 : stm32g4xx_ll_tim.h
  • DT_RANGE_4 : stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EXTERNAL_CLOCK_VALUE : stm32g4xx_hal_conf.h
  • EXTI_CallbackIDTypeDef : stm32g4xx_hal_exti.h
  • EXTI_CONFIG : stm32g4xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32g4xx_hal_exti.c
  • EXTI_DIRECT : stm32g4xx_hal_exti.h
  • EXTI_EVT : stm32g4xx_hal_gpio.h
  • EXTI_GPIO : stm32g4xx_hal_exti.h
  • EXTI_GPIOA : stm32g4xx_hal_exti.h
  • EXTI_GPIOB : stm32g4xx_hal_exti.h
  • EXTI_GPIOC : stm32g4xx_hal_exti.h
  • EXTI_GPIOD : stm32g4xx_hal_exti.h
  • EXTI_GPIOE : stm32g4xx_hal_exti.h
  • EXTI_GPIOF : stm32g4xx_hal_exti.h
  • EXTI_GPIOG : stm32g4xx_hal_exti.h
  • EXTI_IT : stm32g4xx_hal_gpio.h
  • EXTI_LINE_0 : stm32g4xx_hal_exti.h
  • EXTI_LINE_1 : stm32g4xx_hal_exti.h
  • EXTI_LINE_10 : stm32g4xx_hal_exti.h
  • EXTI_LINE_11 : stm32g4xx_hal_exti.h
  • EXTI_LINE_12 : stm32g4xx_hal_exti.h
  • EXTI_LINE_13 : stm32g4xx_hal_exti.h
  • EXTI_LINE_14 : stm32g4xx_hal_exti.h
  • EXTI_LINE_15 : stm32g4xx_hal_exti.h
  • EXTI_LINE_16 : stm32g4xx_hal_exti.h
  • EXTI_LINE_17 : stm32g4xx_hal_exti.h
  • EXTI_LINE_18 : stm32g4xx_hal_exti.h
  • EXTI_LINE_19 : stm32g4xx_hal_exti.h
  • EXTI_LINE_2 : stm32g4xx_hal_exti.h
  • EXTI_LINE_20 : stm32g4xx_hal_exti.h
  • EXTI_LINE_21 : stm32g4xx_hal_exti.h
  • EXTI_LINE_22 : stm32g4xx_hal_exti.h
  • EXTI_LINE_23 : stm32g4xx_hal_exti.h
  • EXTI_LINE_24 : stm32g4xx_hal_exti.h
  • EXTI_LINE_25 : stm32g4xx_hal_exti.h
  • EXTI_LINE_26 : stm32g4xx_hal_exti.h
  • EXTI_LINE_27 : stm32g4xx_hal_exti.h
  • EXTI_LINE_28 : stm32g4xx_hal_exti.h
  • EXTI_LINE_29 : stm32g4xx_hal_exti.h
  • EXTI_LINE_3 : stm32g4xx_hal_exti.h
  • EXTI_LINE_30 : stm32g4xx_hal_exti.h
  • EXTI_LINE_31 : stm32g4xx_hal_exti.h
  • EXTI_LINE_32 : stm32g4xx_hal_exti.h
  • EXTI_LINE_33 : stm32g4xx_hal_exti.h
  • EXTI_LINE_34 : stm32g4xx_hal_exti.h
  • EXTI_LINE_35 : stm32g4xx_hal_exti.h
  • EXTI_LINE_36 : stm32g4xx_hal_exti.h
  • EXTI_LINE_37 : stm32g4xx_hal_exti.h
  • EXTI_LINE_38 : stm32g4xx_hal_exti.h
  • EXTI_LINE_39 : stm32g4xx_hal_exti.h
  • EXTI_LINE_4 : stm32g4xx_hal_exti.h
  • EXTI_LINE_40 : stm32g4xx_hal_exti.h
  • EXTI_LINE_41 : stm32g4xx_hal_exti.h
  • EXTI_LINE_42 : stm32g4xx_hal_exti.h
  • EXTI_LINE_43 : stm32g4xx_hal_exti.h
  • EXTI_LINE_5 : stm32g4xx_hal_exti.h
  • EXTI_LINE_6 : stm32g4xx_hal_exti.h
  • EXTI_LINE_7 : stm32g4xx_hal_exti.h
  • EXTI_LINE_8 : stm32g4xx_hal_exti.h
  • EXTI_LINE_9 : stm32g4xx_hal_exti.h
  • EXTI_LINE_NB : stm32g4xx_hal_exti.h
  • EXTI_MODE : stm32g4xx_hal_gpio.h
  • EXTI_MODE_EVENT : stm32g4xx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32g4xx_hal_exti.h
  • EXTI_MODE_MASK : stm32g4xx_hal_exti.h
  • EXTI_MODE_NONE : stm32g4xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32g4xx_hal_exti.c
  • EXTI_MODE_Pos : stm32g4xx_hal_gpio.h
  • EXTI_PIN_MASK : stm32g4xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32g4xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32g4xx_hal_exti.h
  • EXTI_REG1 : stm32g4xx_hal_exti.h
  • EXTI_REG2 : stm32g4xx_hal_exti.h
  • EXTI_REG_MASK : stm32g4xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32g4xx_hal_exti.h
  • EXTI_RESERVED : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32g4xx_hal_exti.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FB_MODE_BB : stm32g4xx_hal.c
  • FB_MODE_BitNumber : stm32g4xx_hal.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32g4xx_hal_fdcan.h
  • FDCAN_CalcultateRamBlockAddresses() : stm32g4xx_hal_fdcan.c
  • FDCAN_CHECK_FLAG : stm32g4xx_hal_fdcan.h
  • FDCAN_CHECK_IT_SOURCE : stm32g4xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32g4xx_hal_fdcan.h
  • FDCAN_CopyMessageToRAM() : stm32g4xx_hal_fdcan.c
  • FDCAN_DATA_FRAME : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32g4xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32g4xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32g4xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32g4xx_hal_fdcan.h
  • FDCAN_HandleTypeDef : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_ILS_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32g4xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_BIT_LINE_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_MISC : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_SMSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_TX_FIFO_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_BIT_LINE_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_MISC : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_SMSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_TX_FIFO_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32g4xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32g4xx_hal_fdcan.h
  • FDCAN_REJECT : stm32g4xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32g4xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32g4xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32g4xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32g4xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32g4xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32g4xx_hal_flash.h
  • FLASH_BANK_BOTH : stm32g4xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32g4xx_hal_flash.h
  • FLASH_CACHE_DCACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_DISABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_ICACHE_DCACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_ICACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_CacheTypeDef : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCR_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32g4xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_SR_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32g4xx_hal_flash.h
  • FLASH_FlushCaches() : stm32g4xx_hal_flash_ex.c
  • FLASH_IT_ECCC : stm32g4xx_hal_flash.h
  • FLASH_IT_EOP : stm32g4xx_hal_flash.h
  • FLASH_IT_OPERR : stm32g4xx_hal_flash.h
  • FLASH_IT_RDERR : stm32g4xx_hal_flash.h
  • FLASH_KEY1 : stm32g4xx_hal_flash.h
  • FLASH_KEY2 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_10 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_11 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_12 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_13 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_14 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_15 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_3 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_4 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_5 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_6 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_7 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_8 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_9 : stm32g4xx_hal_flash.h
  • FLASH_MassErase() : stm32g4xx_hal_flash_ex.c
  • FLASH_NB_DOUBLE_WORDS_IN_ROW : stm32g4xx_hal_flash.c
  • FLASH_OB_BootLockConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetBootLock() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetSecMem() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_SecMemConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OPTKEY1 : stm32g4xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32g4xx_hal_flash.h
  • FLASH_PAGE_NB : stm32g4xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32g4xx_hal_flash.h
  • FLASH_PageErase() : stm32g4xx_hal_flash_ex.c
  • FLASH_PDKEY1 : stm32g4xx_hal_flash.h , stm32g4xx_ll_system.h
  • FLASH_PDKEY2 : stm32g4xx_hal_flash.h , stm32g4xx_ll_system.h
  • FLASH_PROC_MASS_ERASE : stm32g4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32g4xx_hal_flash.h
  • FLASH_PROC_PAGE_ERASE : stm32g4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32g4xx_hal_flash.h
  • FLASH_PROC_PROGRAM_LAST : stm32g4xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32g4xx_hal_flash.h
  • FLASH_Program_DoubleWord() : stm32g4xx_hal_flash.c
  • FLASH_Program_Fast() : stm32g4xx_hal_flash.c
  • FLASH_SIZE : stm32g4xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32g4xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32g4xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32g4xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST_AND_LAST : stm32g4xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32g4xx_hal_flash.c
  • FLASHSIZE_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • FMAC_AppendFilterDataUpdateState() : stm32g4xx_hal_fmac.c
  • FMAC_BUFFER_ACCESS_DMA : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_IT : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_NONE : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_POLLING : stm32g4xx_hal_fmac.h
  • FMAC_CLIP_DISABLED : stm32g4xx_hal_fmac.h
  • FMAC_CLIP_ENABLED : stm32g4xx_hal_fmac.h
  • FMAC_ConfigFilterOutputBufferUpdateState() : stm32g4xx_hal_fmac.c
  • FMAC_DMA_REN : stm32g4xx_hal_fmac.c
  • FMAC_DMA_WEN : stm32g4xx_hal_fmac.c
  • FMAC_DMAError() : stm32g4xx_hal_fmac.c
  • FMAC_DMAFilterConfig() : stm32g4xx_hal_fmac.c
  • FMAC_DMAFilterPreload() : stm32g4xx_hal_fmac.c
  • FMAC_DMAGetData() : stm32g4xx_hal_fmac.c
  • FMAC_DMAHalfGetData() : stm32g4xx_hal_fmac.c
  • FMAC_DMAHalfOutputDataReady() : stm32g4xx_hal_fmac.c
  • FMAC_DMAOutputDataReady() : stm32g4xx_hal_fmac.c
  • FMAC_FilterConfig() : stm32g4xx_hal_fmac.c
  • FMAC_FilterPreload() : stm32g4xx_hal_fmac.c
  • FMAC_FLAG_OVFL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_SAT : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_UNFL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_X1FULL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_YEMPTY : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_CONVO_FIR : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_IIR_DIRECT_FORM_1 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_X1 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_X2 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_Y : stm32g4xx_hal_fmac.h
  • FMAC_GET_START_BIT : stm32g4xx_hal_fmac.c
  • FMAC_GET_THRESHOLD_FROM_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_X1_FULL_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_X1_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_GET_X2_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_GET_Y_EMPTY_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_Y_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_HandleTypeDef : stm32g4xx_hal_fmac.h
  • FMAC_IT_OVFLIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_RIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_SATIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_UNFLIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_WIEN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MAX_FIR : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MAX_IIR : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MIN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_Q_MAX : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_Q_MIN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_R_MAX : stm32g4xx_hal_fmac.h
  • FMAC_ReadDataIncrementPtr() : stm32g4xx_hal_fmac.c
  • FMAC_Reset() : stm32g4xx_hal_fmac.c
  • FMAC_ResetDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_ResetInputStateAndDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_ResetOutputStateAndDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_START : stm32g4xx_hal_fmac.c
  • FMAC_THRESHOLD_1 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_2 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_4 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_8 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_NO_VALUE : stm32g4xx_hal_fmac.h
  • FMAC_WaitOnStartUntilTimeout() : stm32g4xx_hal_fmac.c
  • FMAC_WriteDataIncrementPtr() : stm32g4xx_hal_fmac.c
  • FMAC_WritePreloadDataIncrementPtr() : stm32g4xx_hal_fmac.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_MCO : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_FDCAN1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_LPTIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_LPUART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_UCPD1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_COMP3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_UCPD1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_I2S2ext : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_I2S3ext : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32g4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32g4xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32g4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32g4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32g4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32g4xx_hal_gpio.h
  • GPIO_MODE_Pos : stm32g4xx_hal_gpio.h
  • GPIO_NOPULL : stm32g4xx_hal_gpio.h
  • GPIO_NUMBER : stm32g4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_All : stm32g4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32g4xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32g4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32g4xx_hal_gpio.h
  • GPIO_PinState : stm32g4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32g4xx_hal_gpio.h
  • GPIO_PULLUP : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32g4xx_hal_adc.c
  • HAL_ADC_CallbackIDTypeDef : stm32g4xx_hal_adc.h
  • HAL_ADC_ConfigChannel() : stm32g4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_ConvHalfCpltCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_DMA : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32g4xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32g4xx_hal_adc.c
  • HAL_ADC_Init() : stm32g4xx_hal_adc.c
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_IRQHandler() : stm32g4xx_hal_adc.c
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LevelOutOfWindowCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_MSPDEINIT_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_MspInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_MSPINIT_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_PollForConversion() : stm32g4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32g4xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32g4xx_hal_adc.c
  • HAL_ADC_StartSampling() : stm32g4xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32g4xx_hal_adc.h
  • HAL_ADC_Stop() : stm32g4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32g4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32g4xx_hal_adc.c
  • HAL_ADC_StopSampling() : stm32g4xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32g4xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_COMP_CallbackIDTypeDef : stm32g4xx_hal_comp.h
  • HAL_COMP_DeInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32g4xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32g4xx_hal_comp.h
  • HAL_COMP_GetError() : stm32g4xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32g4xx_hal_comp.c
  • HAL_COMP_GetState() : stm32g4xx_hal_comp.c
  • HAL_COMP_Init() : stm32g4xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32g4xx_hal_comp.c
  • HAL_COMP_Lock() : stm32g4xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_MSPDEINIT_CB_ID : stm32g4xx_hal_comp.h
  • HAL_COMP_MspInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_MSPINIT_CB_ID : stm32g4xx_hal_comp.h
  • HAL_COMP_RegisterCallback() : stm32g4xx_hal_comp.c
  • HAL_COMP_Start() : stm32g4xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32g4xx_hal_comp.h
  • HAL_COMP_Stop() : stm32g4xx_hal_comp.c
  • HAL_COMP_TRIGGER_CB_ID : stm32g4xx_hal_comp.h
  • HAL_COMP_TriggerCallback() : stm32g4xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32g4xx_hal_comp.c
  • HAL_CORDIC_Calculate() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CALCULATE_CPLT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_Calculate_DMA() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Calculate_IT() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CalculateCpltCallback() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CalculateZO() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CallbackIDTypeDef : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_Configure() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_DeInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_ERROR_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_DMA : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_NONE : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_NOT_READY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_PARAM : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_TIMEOUT : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ErrorCallback() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_GetError() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_GetState() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Init() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_IRQHandler() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CORDIC_MspDeInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_MSPDEINIT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_MspInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_MSPINIT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_RegisterCallback() : stm32g4xx_hal_cordic.c , stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_BUSY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_ERROR : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_READY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_RESET : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_StateTypeDef : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_UnRegisterCallback() : stm32g4xx_hal_cordic.c
  • HAL_CORTEX_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32g4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32g4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32g4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32g4xx_hal_crc.c
  • HAL_CRC_Init() : stm32g4xx_hal_crc.c
  • HAL_CRC_LENGTH_16B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32g4xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32g4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32g4xx_hal_crc.c
  • HAL_CRC_STATE_BUSY : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32g4xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32g4xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32g4xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32g4xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32g4xx_hal_crc_ex.c
  • HAL_CRYP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DAC_ALL_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CallbackIDTypeDef : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_ConfigChannel() : stm32g4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32g4xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetError() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32g4xx_hal_dac.c
  • HAL_DAC_Init() : stm32g4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32g4xx_hal_dac.c
  • HAL_DAC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_MSPDEINIT_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_MspInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_MSPINIT_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_RegisterCallback() : stm32g4xx_hal_dac.c , stm32g4xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32g4xx_hal_dac.c
  • HAL_DAC_Start() : stm32g4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32g4xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32g4xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32g4xx_hal_dac.h
  • HAL_DAC_Stop() : stm32g4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32g4xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32g4xx_hal_dac.c , stm32g4xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStart_DMA() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStop_DMA() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveDataReset() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveDataStep() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32g4xx_hal.c
  • HAL_DeInit() : stm32g4xx_hal.c
  • HAL_Delay() : stm32g4xx_hal.c
  • HAL_DMA_Abort() : stm32g4xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32g4xx_hal_dma.c
  • HAL_DMA_BURST_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_DMA_BURST_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_DMA_BURST_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_DMA_CallbackIDTypeDef : stm32g4xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32g4xx_hal_dma.c
  • HAL_DMA_ERROR_NO_XFER : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32g4xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32g4xx_hal_dma.h
  • HAL_DMA_GetError() : stm32g4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32g4xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32g4xx_hal_dma.h
  • HAL_DMA_Init() : stm32g4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32g4xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32g4xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32g4xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32g4xx_hal_dma.c
  • HAL_DMA_Start() : stm32g4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32g4xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32g4xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32g4xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32g4xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_EXTI_ClearConfigLine() : stm32g4xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32g4xx_hal_exti.c
  • HAL_EXTI_COMMON_CB_ID : stm32g4xx_hal_exti.h
  • HAL_EXTI_GenerateSWI() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32g4xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32g4xx_hal_exti.c
  • HAL_EXTI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_EXTI_RegisterCallback() : stm32g4xx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32g4xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_CallbackIDTypeDef : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ErrorCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FDCAN_MspDeInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_MspInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_MSPINIT_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_RegisterCallback() : stm32g4xx_hal_fdcan.c , stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_STATE_BUSY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_Stop() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32g4xx_hal_flash.c
  • HAL_FLASH_ERROR_ECCC : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_ECCD : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32g4xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32g4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32g4xx_hal_flash.c
  • HAL_FLASHEx_DisableDebugger() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_DisableRunPowerDown() : stm32g4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableDebugger() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableRunPowerDown() : stm32g4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableSecMemProtection() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32g4xx_hal_flash_ex.c
  • HAL_FMAC_AppendFilterData() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_CallbackIDTypeDef : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ConfigFilterOutputBuffer() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_DeInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_ERROR_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_DMA : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_NONE : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_OVFL : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_PARAM : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_RESET : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_SAT : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_TIMEOUT : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_UNFL : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ErrorCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FILTER_CONFIG_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_FILTER_PRELOAD_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_FilterConfig() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterConfig_DMA() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterConfigCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreload() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreload_DMA() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreloadCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterStart() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterStop() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GET_DATA_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_GetDataCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GetError() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GetState() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_HALF_GET_DATA_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_HalfGetDataCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_HalfOutputDataReadyCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_Init() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_IRQHandler() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FMAC_MspDeInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_MSPDEINIT_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_MspInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_MSPINIT_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_OUTPUT_DATA_READY_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_OutputDataReadyCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_PollFilterData() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_RegisterCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_RESET_TIMEOUT_VALUE : stm32g4xx_hal_fmac.c
  • HAL_FMAC_STATE_BUSY : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_BUSY_RD : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_BUSY_WR : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_ERROR : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_READY : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_RESET : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_TIMEOUT : stm32g4xx_hal_fmac.h
  • HAL_FMAC_StateTypeDef : stm32g4xx_hal_fmac.h
  • HAL_FMAC_TIMEOUT_VALUE : stm32g4xx_hal_fmac.c
  • HAL_FMAC_UnRegisterCallback() : stm32g4xx_hal_fmac.c
  • HAL_GetDEVID() : stm32g4xx_hal.c
  • HAL_GetHalVersion() : stm32g4xx_hal.c
  • HAL_GetREVID() : stm32g4xx_hal.c
  • HAL_GetTick() : stm32g4xx_hal.c
  • HAL_GetTickFreq() : stm32g4xx_hal.c
  • HAL_GetTickPrio() : stm32g4xx_hal.c
  • HAL_GetUIDw0() : stm32g4xx_hal.c
  • HAL_GetUIDw1() : stm32g4xx_hal.c
  • HAL_GetUIDw2() : stm32g4xx_hal.c
  • HAL_GPIO_DeInit() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32g4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32g4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32g4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32g4xx_hal_uart.c
  • HAL_HRTIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_I2C_ABORT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_AbortCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_CallbackIDTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2C_DeInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32g4xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32g4xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32g4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32g4xx_hal_i2c.c
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_ListenCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MasterRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_Mem_Write() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32g4xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MSPDEINIT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MspInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MSPINIT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_RegisterAddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_SlaveRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32g4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2C_UnRegisterAddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2S_CallbackIDTypeDef : stm32g4xx_hal_i2s.h
  • HAL_I2S_DeInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32g4xx_hal_i2s.c
  • HAL_I2S_ERROR_BUSY_LINE_RX : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_DMA : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32g4xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32g4xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Init() : stm32g4xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32g4xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_MSPDEINIT_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_MspInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_MSPINIT_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_Receive() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_RxCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32g4xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32g4xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32g4xx_hal_i2s.c
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_TxCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32g4xx_hal_i2s.c
  • HAL_IncTick() : stm32g4xx_hal.c
  • HAL_Init() : stm32g4xx_hal.c
  • HAL_InitTick() : stm32g4xx_hal.c
  • HAL_IRDA_Abort() : stm32g4xx_hal_irda.c
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_Abort_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_AbortCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_CallbackIDTypeDef : stm32g4xx_hal_irda.h
  • HAL_IRDA_DeInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32g4xx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32g4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32g4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32g4xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_MspInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_MSPINIT_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_Receive() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_RxCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32g4xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32g4xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_TxCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32g4xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32g4xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32g4xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32g4xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32g4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32g4xx_hal_uart.c
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_CallbackIDTypeDef : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_MSPINIT_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_STATE_BUSY : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TRIGGER_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32g4xx_hal_lptim.c
  • HAL_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32g4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32g4xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32g4xx_hal_cortex.c
  • HAL_MspDeInit() : stm32g4xx_hal.c
  • HAL_MspInit() : stm32g4xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32g4xx_hal_uart_ex.c
  • HAL_NAND_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_NVIC_ClearPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32g4xx_hal_cortex.c
  • HAL_OPAMP_ALL_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_CallbackIDTypeDef : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_DeInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_LockTimerMux() : stm32g4xx_hal_opamp.c , stm32g4xx_hal_opamp.h
  • HAL_OPAMP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_OPAMP_MspDeInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_MSPDEINIT_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_MspInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_MSPINIT_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_RegisterCallback() : stm32g4xx_hal_opamp.c , stm32g4xx_hal_opamp.h
  • HAL_OPAMP_SelfCalibrate() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_STATE_BUSY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_Stop() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_UnRegisterCallback() : stm32g4xx_hal_opamp.c , stm32g4xx_hal_opamp.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32g4xx_hal_opamp_ex.c , stm32g4xx_hal_opamp_ex.h
  • HAL_PCD_ActivateRemoteWakeup() : stm32g4xx_hal_pcd.c
  • HAL_PCD_CallbackIDTypeDef : stm32g4xx_hal_pcd.h
  • HAL_PCD_CONNECT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DISCONNECT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_DisconnectCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Abort() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_DB_Receive() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_DB_Transmit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32g4xx_hal_pcd.h
  • HAL_PCD_GetState() : stm32g4xx_hal_pcd.c
  • HAL_PCD_Init() : stm32g4xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_MSPDEINIT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_MspInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_MSPINIT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_RegisterBcdCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RESET_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_ResetCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RESUME_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_ResumeCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_SetupStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SOF_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_SOFCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_Start() : stm32g4xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32g4xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SUSPEND_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_SuspendCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32g4xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_PWR_PVDCallback() : stm32g4xx_hal_pwr.c
  • HAL_PWREx_ConfigPVM() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM2() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM4() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAM2ContentRetention() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUCPDDeadBattery() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUCPDStandbyMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM2() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM4() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAM2ContentRetention() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUCPDDeadBattery() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUCPDStandbyMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM2Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM4Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_QSPI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RCC_ClockConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32g4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32g4xx_hal_rcc.c
  • HAL_RCC_DisableLSECSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_EnableLSECSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32g4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32g4xx_hal.c
  • HAL_RNG_CallbackIDTypeDef : stm32g4xx_hal_rng.h
  • HAL_RNG_DeInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_ERROR_BUSY : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32g4xx_hal_rng.h
  • HAL_RNG_ErrorCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32g4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32g4xx_hal_rng.c
  • HAL_RNG_GetError() : stm32g4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32g4xx_hal_rng.c
  • HAL_RNG_Init() : stm32g4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32g4xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_MSPDEINIT_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_MspInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_MSPINIT_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_ReadLastRandomNumber() : stm32g4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32g4xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32g4xx_hal_rng.h
  • HAL_RNG_UnRegisterCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32g4xx_hal_uart_ex.c
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_AlarmAEventCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32g4xx_hal_rtc.c
  • HAL_RTC_CallbackIDTypeDef : stm32g4xx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_DST_Add1Hour() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_ClearStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_ReadStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_SetStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_Sub1Hour() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32g4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32g4xx_hal_rtc.c
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_MSPDEINIT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_MSPINIT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_PollForAlarmAEvent() : stm32g4xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32g4xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_UnRegisterCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32g4xx_hal_rtc.c
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamperEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32g4xx_hal_rtc.h
  • HAL_SAI_Abort() : stm32g4xx_hal_sai.c
  • HAL_SAI_CallbackIDTypeDef : stm32g4xx_hal_sai.h
  • HAL_SAI_DeInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32g4xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32g4xx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_GetError() : stm32g4xx_hal_sai.c
  • HAL_SAI_GetState() : stm32g4xx_hal_sai.c
  • HAL_SAI_Init() : stm32g4xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32g4xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32g4xx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_MSPDEINIT_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_MspInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_MSPINIT_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_Receive() : stm32g4xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32g4xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32g4xx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_RxCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32g4xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32g4xx_hal_sai.h
  • HAL_SAI_Transmit() : stm32g4xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32g4xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32g4xx_hal_sai.c
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_TxCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32g4xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32g4xx_hal_sai_ex.c
  • HAL_SetTickFreq() : stm32g4xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_Abort_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_AbortCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_DeInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_DMA : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_MspInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_Receive() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_TxCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_CallbackIDTypeDef : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ConfigAnalogFilter() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MspInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MSPINIT_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_RegisterAddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUSEx_DisableFastModePlus() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_DisableWakeUp() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableFastModePlus() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableWakeUp() : stm32g4xx_hal_smbus_ex.c
  • HAL_SPI_Abort() : stm32g4xx_hal_spi.c
  • HAL_SPI_ABORT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_Abort_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_CallbackIDTypeDef : stm32g4xx_hal_spi.h
  • HAL_SPI_DeInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32g4xx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32g4xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32g4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32g4xx_hal_spi.c
  • HAL_SPI_Init() : stm32g4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32g4xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_MSPDEINIT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_MspInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_MSPINIT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_Receive() : stm32g4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_RxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32g4xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32g4xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32g4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32g4xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32g4xx_hal_spi_ex.c
  • HAL_SRAM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SuspendTick() : stm32g4xx_hal.c
  • HAL_SYSCFG_CCMSRAM_WriteProtectionEnable() : stm32g4xx_hal.c
  • HAL_SYSCFG_CCMSRAMErase() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableIOSwitchBooster() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableIOSwitchVDD() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableMemorySwappingBank() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableIOSwitchBooster() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableIOSwitchVDD() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableMemorySwappingBank() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32g4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32g4xx_hal_cortex.c
  • HAL_TICK_FREQ_100HZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32g4xx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32g4xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32g4xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_Base_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_Base_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_BREAK2_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_TIM_ChannelStateTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ConfigClockSource() : stm32g4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32g4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32g4xx_hal_tim.c
  • HAL_TIM_DIRECTION_CHANGE_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_DMABurst_MultiReadStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurstState() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurstStateTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_Encoder_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_ENCODER_INDEX_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_Encoder_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_Encoder_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_Encoder_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ErrorCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32g4xx_hal_tim.c
  • HAL_TIM_GetActiveChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_GetChannelState() : stm32g4xx_hal_tim.c
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_CaptureCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_INDEX_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IRQHandler() : stm32g4xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_DelayElapsedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OnePulse_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PeriodElapsedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32g4xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32g4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32g4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_TRANSITION_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32g4xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32g4xx_hal_smbus.c
  • HAL_TIMEx_Break2Callback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DirectionChangeCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableDeadTimePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableEncoderFirstIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisarmBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DitheringDisable() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DitheringEnable() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableDeadTimePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableEncoderFirstIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EncoderIndexCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_GetChannelNState() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_IndexErrorCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OC_ConfigPulseOnCompare() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ReArmBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_TransitionErrorCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32g4xx_hal_uart.c
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_Abort_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_AbortCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_CallbackIDTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_DeInit() : stm32g4xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32g4xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32g4xx_hal_uart.c
  • HAL_UART_ERROR_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32g4xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_GetError() : stm32g4xx_hal_uart.c
  • HAL_UART_GetState() : stm32g4xx_hal_uart.c
  • HAL_UART_Init() : stm32g4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32g4xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32g4xx_hal_uart.c
  • HAL_UART_MSPDEINIT_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_MspInit() : stm32g4xx_hal_uart.c
  • HAL_UART_MSPINIT_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_Receive() : stm32g4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32g4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32g4xx_hal_uart.c
  • HAL_UART_RECEPTION_STANDARD : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TOCHARMATCH : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TOIDLE : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TORTO : stm32g4xx_hal_uart.h
  • HAL_UART_RegisterCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RegisterRxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RX_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RxCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RXEVENT_HT : stm32g4xx_hal_uart.h
  • HAL_UART_RXEVENT_IDLE : stm32g4xx_hal_uart.h
  • HAL_UART_RXEVENT_TC : stm32g4xx_hal_uart.h
  • HAL_UART_RxEventTypeTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_RxHalfCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RxTypeTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32g4xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32g4xx_hal_uart.h
  • HAL_UART_Transmit() : stm32g4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32g4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_TX_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TxCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_UnRegisterRxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_WAKEUP_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UARTEx_DisableFifoMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_GetRxEventType() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_DMA() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_IT() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_RxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32g4xx_hal_usart.c
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_Abort_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_CallbackIDTypeDef : stm32g4xx_hal_usart.h
  • HAL_USART_DeInit() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32g4xx_hal_usart.c
  • HAL_USART_ERROR_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_DMA : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_RTO : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32g4xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_GetError() : stm32g4xx_hal_usart.c
  • HAL_USART_GetState() : stm32g4xx_hal_usart.c
  • HAL_USART_Init() : stm32g4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32g4xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32g4xx_hal_usart.c
  • HAL_USART_MSPDEINIT_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_MspInit() : stm32g4xx_hal_usart.c
  • HAL_USART_MSPINIT_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_Receive() : stm32g4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_RX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32g4xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32g4xx_hal_usart.h
  • HAL_USART_Transmit() : stm32g4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_TX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32g4xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32g4xx_hal_usart_ex.c
  • HAL_WWDG_CallbackIDTypeDef : stm32g4xx_hal_wwdg.h
  • HAL_WWDG_EarlyWakeupCallback() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_EWI_CB_ID : stm32g4xx_hal_wwdg.h
  • HAL_WWDG_Init() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_MSPINIT_CB_ID : stm32g4xx_hal_wwdg.h
  • HAL_WWDG_Refresh() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32g4xx_hal_wwdg.c
  • HFSEL_ENABLE_THRESHOLD_160MHZ : stm32g4xx_hal_dac.c
  • HFSEL_ENABLE_THRESHOLD_80MHZ : stm32g4xx_hal_dac.c
  • hopamp2 : stm32g4xx_hal_opamp_ex.c
  • HSE_STARTUP_TIMEOUT : stm32g4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSE_VALUE : stm32g4xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSI48_VALUE : stm32g4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSI_VALUE : stm32g4xx_hal_conf.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32g4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32g4xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32g4xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32g4xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32g4xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32g4xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32g4xx_hal_i2c.h
  • I2C_ConvertOtherXferOptions() : stm32g4xx_hal_i2c.c
  • I2C_DIRECTION_RECEIVE : stm32g4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32g4xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32g4xx_hal_i2c.c
  • I2C_DMAAbort() : stm32g4xx_hal_i2c.c
  • I2C_DMAError() : stm32g4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32g4xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32g4xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32g4xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32g4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32g4xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32g4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32g4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TC : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32g4xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32g4xx_hal_i2c.c
  • I2C_FMP_NOT_SUPPORTED : stm32g4xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32g4xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32g4xx_hal_i2c.h
  • I2C_GET_DIR : stm32g4xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32g4xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32g4xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32g4xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32g4xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32g4xx_hal_i2c.h
  • I2C_IsErrorOccurred() : stm32g4xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32g4xx_hal_i2c.h
  • I2C_IT_ERRI : stm32g4xx_hal_i2c.h
  • I2C_IT_NACKI : stm32g4xx_hal_i2c.h
  • I2C_IT_RXI : stm32g4xx_hal_i2c.h
  • I2C_IT_STOPI : stm32g4xx_hal_i2c.h
  • I2C_IT_TCI : stm32g4xx_hal_i2c.h
  • I2C_IT_TXI : stm32g4xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITError() : stm32g4xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32g4xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32g4xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32g4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32g4xx_hal_i2c.h
  • I2C_Mem_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Mem_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_MEMADD_SIZE_16BIT : stm32g4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32g4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32g4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32g4xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32g4xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32g4xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32g4xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32g4xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32g4xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32g4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32g4xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32g4xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32g4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32g4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32g4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32g4xx_hal_i2c.c
  • I2C_TransferConfig() : stm32g4xx_hal_i2c.c
  • I2C_TreatErrorCallback() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32g4xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32g4xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32g4xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32g4xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32g4xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32g4xx_hal_i2s.h
  • I2S_DMAError() : stm32g4xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32g4xx_hal_i2s.c
  • I2S_FLAG_BSY : stm32g4xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32g4xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32g4xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32g4xx_hal_i2s.h
  • I2S_HandleTypeDef : stm32g4xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32g4xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32g4xx_ll_spi.c
  • I2S_IT_ERR : stm32g4xx_hal_i2s.h
  • I2S_IT_RXNE : stm32g4xx_hal_i2s.h
  • I2S_IT_TXE : stm32g4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32g4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32g4xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32g4xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32g4xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32g4xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32g4xx_hal_i2s.h
  • I2S_Receive_IT() : stm32g4xx_hal_i2s.c
  • I2S_STANDARD_LSB : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32g4xx_hal_i2s.h
  • I2S_TIMEOUT_FLAG : stm32g4xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32g4xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32g4xx_hal_i2s.c
  • IC1Config() : stm32g4xx_ll_tim.c
  • IC2Config() : stm32g4xx_ll_tim.c
  • IC3Config() : stm32g4xx_ll_tim.c
  • IC4Config() : stm32g4xx_ll_tim.c
  • INSTRUCTION_CACHE_ENABLE : stm32g4xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32g4xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32g4xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32g4xx_hal_irda.c
  • IRDA_CR_MASK : stm32g4xx_hal_irda.h
  • IRDA_CR_POS : stm32g4xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32g4xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32g4xx_hal_irda.c
  • IRDA_DMAError() : stm32g4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32g4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32g4xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32g4xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32g4xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32g4xx_hal_irda.h
  • IRDA_FLAG_FE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32g4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32g4xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32g4xx_hal_irda_ex.h
  • IRDA_HandleTypeDef : stm32g4xx_hal_irda.h
  • IRDA_InitCallbacksToDefault() : stm32g4xx_hal_irda.c
  • IRDA_ISR_MASK : stm32g4xx_hal_irda.h
  • IRDA_ISR_POS : stm32g4xx_hal_irda.h
  • IRDA_IT_ERR : stm32g4xx_hal_irda.h
  • IRDA_IT_FE : stm32g4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32g4xx_hal_irda.h
  • IRDA_IT_MASK : stm32g4xx_hal_irda.h
  • IRDA_IT_NE : stm32g4xx_hal_irda.h
  • IRDA_IT_ORE : stm32g4xx_hal_irda.h
  • IRDA_IT_PE : stm32g4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32g4xx_hal_irda.h
  • IRDA_IT_TC : stm32g4xx_hal_irda.h
  • IRDA_IT_TXE : stm32g4xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32g4xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_MODE_RX : stm32g4xx_hal_irda.h
  • IRDA_MODE_TX : stm32g4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32g4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32g4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32g4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32g4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32g4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32g4xx_hal_irda.h
  • IRDA_Receive_IT() : stm32g4xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_SetConfig() : stm32g4xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32g4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32g4xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32g4xx_hal_irda.c
  • IRDA_WORDLENGTH_7B : stm32g4xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32g4xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32g4xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32g4xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32g4xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DMA_ACCESS_MULTIMODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32g4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32g4xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32g4xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_GAIN_COMPENSATION : stm32g4xx_hal_adc.h
  • IS_ADC_INJECTED_NB_CONV : stm32g4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32g4xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_SIGN : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32g4xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32g4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32g4xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32g4xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32g4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32g4xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32g4xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32g4xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32g4xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32g4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32g4xx_hal_adc_ex.h
  • IS_ADC_SAMPLINGMODE : stm32g4xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32g4xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32g4xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32g4xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32g4xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32g4xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32g4xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32g4xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32g4xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32g4xx_hal_comp.h
  • IS_CORDIC_DMA_DIRECTION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_FUNCTION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_INSIZE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_NBREAD : stm32g4xx_hal_cordic.h
  • IS_CORDIC_NBWRITE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_OUTSIZE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_PRECISION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_SCALE : stm32g4xx_hal_cordic.h
  • IS_CRC_INPUTDATA_FORMAT : stm32g4xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32g4xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32g4xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32g4xx_hal_crc.h
  • IS_DAC_ALIGN : stm32g4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32g4xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32g4xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32g4xx_hal_dac.h
  • IS_DAC_HIGH_FREQUENCY_MODE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_HOLDTIME : stm32g4xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32g4xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32g4xx_hal_dac.h
  • IS_DAC_RESET_DATA : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAMPLEANDHOLD : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAWTOOTH_POLARITY : stm32g4xx_hal_dac_ex.h
  • IS_DAC_STEP_DATA : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER2 : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32g4xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32g4xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32g4xx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32g4xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32g4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32g4xx_hal_dma.h
  • IS_DMA_MODE : stm32g4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32g4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32g4xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32g4xx_hal_dma_ex.h
  • IS_EXTI_CB : stm32g4xx_hal_exti.h
  • IS_EXTI_CONFIG_LINE : stm32g4xx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32g4xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32g4xx_hal_exti.h
  • IS_EXTI_LINE : stm32g4xx_hal_exti.h
  • IS_EXTI_MODE : stm32g4xx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32g4xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32g4xx_hal_exti.h
  • IS_FDCAN_BRS : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT_GROUP : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION_LIST : stm32g4xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32g4xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32g4xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32g4xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_OTP_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_PAGE : stm32g4xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32g4xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32g4xx_hal_flash.h
  • IS_FMAC_BUFFER_ACCESS : stm32g4xx_hal_fmac.h
  • IS_FMAC_CLIP_STATE : stm32g4xx_hal_fmac.h
  • IS_FMAC_FILTER_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_N_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_N_M_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_P : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_Q : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_R : stm32g4xx_hal_fmac.h
  • IS_FMAC_THRESHOLD : stm32g4xx_hal_fmac.h
  • IS_FMAC_THRESHOLD_APPLICABLE : stm32g4xx_hal_fmac.h
  • IS_GPIO_AF : stm32g4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32g4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32g4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32g4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32g4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32g4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32g4xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32g4xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32g4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32g4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32g4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32g4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g4xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32g4xx_hal_i2s.h
  • IS_I2S_CPOL : stm32g4xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32g4xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32g4xx_hal_i2s.h
  • IS_I2S_MODE : stm32g4xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32g4xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32g4xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32g4xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32g4xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32g4xx_hal_irda.h
  • IS_IRDA_MODE : stm32g4xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32g4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32g4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32g4xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32g4xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32g4xx_hal_irda.h
  • IS_IRDA_STATE : stm32g4xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32g4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32g4xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32g4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32g4xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32g4xx_hal_iwdg.h
  • IS_LL_ADC_COMMON_CLOCK : stm32g4xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32g4xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32g4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32g4xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32g4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32g4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE2 : stm32g4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32g4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32g4xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32g4xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32g4xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32g4xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32g4xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32g4xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32g4xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32g4xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32g4xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32g4xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32g4xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32g4xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32g4xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32g4xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32g4xx_ll_lpuart.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32g4xx_ll_opamp.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_FDCAN_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_UART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32g4xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32g4xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32g4xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32g4xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32g4xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32g4xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32g4xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32g4xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32g4xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32g4xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_AFMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_AFMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32g4xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32g4xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32g4xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32g4xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32g4xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32g4xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32g4xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32g4xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32g4xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32g4xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32g4xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32g4xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32g4xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32g4xx_ll_utils.c
  • IS_LPTIM_CLOCK_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32g4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32g4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32g4xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32g4xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32g4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32g4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32g4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32g4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32g4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32g4xx_hal_cortex.h
  • IS_OB_BOOT_LOCK : stm32g4xx_hal_flash.h
  • IS_OB_PCROP_RDP : stm32g4xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32g4xx_hal_flash.h
  • IS_OB_SECMEM_SIZE : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOOT0 : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOOT1 : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32g4xx_hal_flash.h
  • IS_OB_USER_CCMSRAM_RST : stm32g4xx_hal_flash.h
  • IS_OB_USER_IRHEN : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG_STDBY : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG_STOP : stm32g4xx_hal_flash.h
  • IS_OB_USER_NRST_MODE : stm32g4xx_hal_flash.h
  • IS_OB_USER_SHUTDOWN : stm32g4xx_hal_flash.h
  • IS_OB_USER_SRAM_PARITY : stm32g4xx_hal_flash.h
  • IS_OB_USER_STANDBY : stm32g4xx_hal_flash.h
  • IS_OB_USER_STOP : stm32g4xx_hal_flash.h
  • IS_OB_USER_SWBOOT0 : stm32g4xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32g4xx_hal_flash.h
  • IS_OB_USER_WWDG : stm32g4xx_hal_flash.h
  • IS_OB_WRPAREA : stm32g4xx_hal_flash.h
  • IS_OPAMP_FACTORYTRIMMING : stm32g4xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32g4xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_SEC_INVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_SEC_NONINVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TIMERCONTROLLED_MUXMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32g4xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32g4xx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32g4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32g4xx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32g4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32g4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32g4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32g4xx_hal_pwr_ex.h
  • IS_RCC_ADC12CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32g4xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32g4xx_hal_rcc.h
  • IS_RCC_HSE : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2SCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32g4xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32g4xx_hal_rcc.h
  • IS_RCC_LSI : stm32g4xx_hal_rcc.h
  • IS_RCC_MCO : stm32g4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32g4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32g4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32g4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_SAI1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_UART4CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32g4xx_hal_rng.h
  • IS_RNG_FLAG : stm32g4xx_hal_rng.h
  • IS_RNG_IT : stm32g4xx_hal_rng.h
  • IS_RTC_ALARM : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32g4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32g4xx_hal_rtc.h
  • IS_RTC_BKP : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32g4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32g4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32g4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32g4xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_LOW_POWER_CALIB : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32g4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32g4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32g4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32g4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32g4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMPONTAMPER_DETECTION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32g4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32g4xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32g4xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32g4xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32g4xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32g4xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32g4xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32g4xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32g4xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32g4xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32g4xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32g4xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32g4xx_hal_smbus.h
  • IS_SMBUS_FASTMODEPLUS : stm32g4xx_hal_smbus_ex.h
  • IS_SMBUS_GENERAL_CALL : stm32g4xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32g4xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32g4xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32g4xx_hal_spi.h
  • IS_SPI_CPHA : stm32g4xx_hal_spi.h
  • IS_SPI_CPOL : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32g4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32g4xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32g4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32g4xx_hal_spi.h
  • IS_SPI_MODE : stm32g4xx_hal_spi.h
  • IS_SPI_NSS : stm32g4xx_hal_spi.h
  • IS_SPI_NSSP : stm32g4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32g4xx_hal_spi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32g4xx_hal.h
  • IS_SYSCFG_CCMSRAMWRP_PAGE : stm32g4xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32g4xx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32g4xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32g4xx_hal_cortex.h
  • IS_TICKFREQ : stm32g4xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_AFMODE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_AFMODE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32g4xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_CCX_CHANNEL : stm32g4xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_ENCODERINDEX_DIRECTION : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_FILTER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_POLARITY : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_POSITION : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_PRESCALER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32g4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32g4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_LOCK_LEVEL : stm32g4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OC_CHANNEL_MODE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_OC_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_PERIOD : stm32g4xx_hal_tim.h
  • IS_TIM_PULSEONCOMPARE_CHANNEL : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_WIDTH : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PWM_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_REMAP : stm32g4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_SLAVE_PRELOAD_SOURCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32g4xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32g4xx_hal_tim.h
  • IS_TIM_TISEL : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TISEL_TIX_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGER_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TRIGGERFILTER : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_UIFREMAP_MODE : stm32g4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32g4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32g4xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32g4xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32g4xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32g4xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32g4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32g4xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32g4xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32g4xx_hal_uart.h
  • IS_UART_DMA_RX : stm32g4xx_hal_uart.h
  • IS_UART_DMA_TX : stm32g4xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32g4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32g4xx_hal_uart.h
  • IS_UART_LIN : stm32g4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32g4xx_hal_uart.h
  • IS_UART_MODE : stm32g4xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32g4xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32g4xx_hal_uart.h
  • IS_UART_OVERRUN : stm32g4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32g4xx_hal_uart.h
  • IS_UART_PARITY : stm32g4xx_hal_uart.h
  • IS_UART_PRESCALER : stm32g4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32g4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32g4xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32g4xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32g4xx_hal_uart_ex.h
  • IS_UART_STATE : stm32g4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32g4xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32g4xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32g4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32g4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32g4xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32g4xx_hal_usart.h
  • IS_USART_CLOCK : stm32g4xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32g4xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32g4xx_hal_usart.h
  • IS_USART_MODE : stm32g4xx_hal_usart.h
  • IS_USART_NSS : stm32g4xx_hal_usart_ex.h
  • IS_USART_PARITY : stm32g4xx_hal_usart.h
  • IS_USART_PHASE : stm32g4xx_hal_usart.h
  • IS_USART_POLARITY : stm32g4xx_hal_usart.h
  • IS_USART_PRESCALER : stm32g4xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32g4xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32g4xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32g4xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32g4xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32g4xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32g4xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32g4xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32g4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32g4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32g4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32g4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32g4xx_hal_iwdg.h
  • IWDG_KERNEL_UPDATE_FLAGS : stm32g4xx_hal_iwdg.c
  • IWDG_KEY_ENABLE : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32g4xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32g4xx_hal_iwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LL_ADC_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_2SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_3SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_4SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_5SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_6SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_7SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_8SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32g4xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP4 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP6 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g4xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32g4xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32g4xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32g4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32g4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32g4xx_ll_adc.h
  • LL_ADC_DeInit() : stm32g4xx_ll_adc.c
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_Disable() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32g4xx_ll_adc.h
  • LL_ADC_Enable() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32g4xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_GetAWDFilteringConfiguration() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32g4xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32g4xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32g4xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32g4xx_ll_adc.h
  • LL_ADC_GetGainCompensation() : stm32g4xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetSaturation() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetSign() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32g4xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32g4xx_ll_adc.h
  • LL_ADC_GetSamplingTimeCommonConfig() : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM_OUT : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM16_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32g4xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32g4xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32g4xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32g4xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SATURATION_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SATURATION_ENABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SIGN_NEGATIVE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SIGN_POSITIVE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32g4xx_ll_adc.h
  • LL_ADC_ReadReg : stm32g4xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSamplingMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32g4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_BULB : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_NORMAL : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSamplingMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StartSamplingPhase() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StopSamplingPhase() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM_OUT : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_DEFAULT : stm32g4xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32g4xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_SetAWDFilteringConfiguration() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32g4xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32g4xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChAdd() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChRem() : stm32g4xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32g4xx_ll_adc.h
  • LL_ADC_SetGainCompensation() : stm32g4xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetSaturation() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetSign() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32g4xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32g4xx_ll_adc.h
  • LL_ADC_SetSamplingTimeCommonConfig() : stm32g4xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32g4xx_ll_adc.h
  • LL_ADC_StructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_TEMPERATURE_CALC_ERROR : stm32g4xx_ll_adc.h
  • LL_ADC_WriteReg : stm32g4xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CORDIC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FMAC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC12 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_CCM : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DAC1 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DAC3 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOF : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOG : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SRAM2 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_FDCAN : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTCAPB : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_UCPD1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM20_OC5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM4_OC3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_ConfigInputs() : stm32g4xx_ll_comp.h
  • LL_COMP_DeInit() : stm32g4xx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32g4xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g4xx_ll_comp.h
  • LL_COMP_Disable() : stm32g4xx_ll_comp.h
  • LL_COMP_Enable() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32g4xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32g4xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_10MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_20MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_30MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_40MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_50MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_60MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_70MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32g4xx_ll_comp.h
  • LL_COMP_Init() : stm32g4xx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC2_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC3_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC3_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC4_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC4_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32g4xx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32g4xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32g4xx_ll_comp.h
  • LL_COMP_Lock() : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32g4xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32g4xx_ll_comp.h
  • LL_COMP_ReadReg : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32g4xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32g4xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32g4xx_ll_comp.h
  • LL_COMP_StructInit() : stm32g4xx_ll_comp.c
  • LL_COMP_WriteReg : stm32g4xx_ll_comp.h
  • LL_CORDIC_Config() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DeInit() : stm32g4xx_ll_cordic.c
  • LL_CORDIC_DisableDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DisableDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DisableIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DMA_GetRegAddr() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DMA_REG_DATA_IN : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DMA_REG_DATA_OUT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FLAG_RRDY : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_ARCTANGENT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_COSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HARCTANGENT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HCOSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_MODULUS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_NATURALLOG : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_PHASE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_SINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_SQUAREROOT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetFunction() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetInSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetNbRead() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetNbWrite() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetOutSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetPrecision() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetScale() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_INSIZE_16BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_INSIZE_32BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsActiveFlag_RRDY() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IT_IEN : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBREAD_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBREAD_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBWRITE_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBWRITE_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_OUTSIZE_16BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_OUTSIZE_32BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_10CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_11CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_12CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_13CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_14CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_15CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_1CYCLE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_2CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_3CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_4CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_5CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_6CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_7CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_8CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_9CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_ReadData() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_ReadReg : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_0 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_3 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_4 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_5 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_6 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_7 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetFunction() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetInSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetNbRead() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetNbWrite() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetOutSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetPrecision() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetScale() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_WriteData() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_WriteReg : stm32g4xx_ll_cordic.h
  • LL_CPUID_GetArchitecture() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32g4xx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32g4xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32g4xx_ll_crc.h
  • LL_CRC_DeInit() : stm32g4xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32g4xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32g4xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32g4xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32g4xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32g4xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32g4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32g4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32g4xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadReg : stm32g4xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32g4xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32g4xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32g4xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32g4xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32g4xx_ll_crc.h
  • LL_CRC_WriteReg : stm32g4xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32g4xx_ll_crs.h
  • LL_CRS_CR_ERRIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32g4xx_ll_crs.h
  • LL_CRS_DeInit() : stm32g4xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32g4xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32g4xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32g4xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32g4xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32g4xx_ll_crs.h
  • LL_CRS_ReadReg : stm32g4xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32g4xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32g4xx_ll_crs.h
  • LL_CRS_WriteReg : stm32g4xx_ll_crs.h
  • LL_DAC_CHANNEL_1 : stm32g4xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32g4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_DeInit() : stm32g4xx_ll_dac.c
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32g4xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32g4xx_ll_dac.h
  • LL_DAC_Disable() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableDMADoubleDataMode() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_Enable() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableDMADoubleDataMode() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DAC1RDY : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DAC2RDY : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DORSTAT1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DORSTAT2 : stm32g4xx_ll_dac.h
  • LL_DAC_GetHighFrequencyMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSignedFormat() : stm32g4xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothPolarity() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothResetData() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothResetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothStepData() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothStepTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_Init() : stm32g4xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DAC1RDY() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DAC2RDY() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DORSTAT1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DORSTAT2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsDMADoubleDataModeEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsReady() : stm32g4xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32g4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32g4xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32g4xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32g4xx_ll_dac.h
  • LL_DAC_ReadReg : stm32g4xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32g4xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32g4xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32g4xx_ll_dac.h
  • LL_DAC_SAWTOOTH_POLARITY_DECREMENT : stm32g4xx_ll_dac.h
  • LL_DAC_SAWTOOTH_POLARITY_INCREMENT : stm32g4xx_ll_dac.h
  • LL_DAC_SetHighFrequencyMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSignedFormat() : stm32g4xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothPolarity() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothResetData() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothResetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothStepData() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothStepTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32g4xx_ll_dac.h
  • LL_DAC_SIGNED_FORMAT_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_SIGNED_FORMAT_ENABLE : stm32g4xx_ll_dac.h
  • LL_DAC_StructInit() : stm32g4xx_ll_dac.c
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE10 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32g4xx_ll_dac.h
  • LL_DAC_TrigSWConversion() : stm32g4xx_ll_dac.h
  • LL_DAC_TrigSWConversion2() : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32g4xx_ll_dac.h
  • LL_DAC_WriteReg : stm32g4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32g4xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32g4xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32g4xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32g4xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32g4xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32g4xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32g4xx_ll_dma.h
  • LL_DMA_DeInit() : stm32g4xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32g4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32g4xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32g4xx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32g4xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32g4xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32g4xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_Init() : stm32g4xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32g4xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32g4xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32g4xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32g4xx_ll_dma.h
  • LL_DMA_ReadReg : stm32g4xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32g4xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32g4xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32g4xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32g4xx_ll_dma.h
  • LL_DMA_StructInit() : stm32g4xx_ll_dma.c
  • LL_DMA_WriteReg : stm32g4xx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_IN : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_CORDIC_READ : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_CORDIC_WRITE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC2_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC3_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC3_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC4_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC4_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_FMAC_READ : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_FMAC_WRITE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_A : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_B : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_C : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_D : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_E : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_F : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_M : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_QSPI : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_A : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_B : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM6_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM7_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART5_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART5_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32g4xx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32g4xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_Init() : stm32g4xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32g4xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32g4xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32g4xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32g4xx_ll_exti.h
  • LL_FLASH_DisableDataCache() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableRunPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableSleepPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableRunPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableSleepPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32g4xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_10 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_11 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_12 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_13 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_14 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_15 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_5 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_6 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_7 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_8 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_9 : stm32g4xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32g4xx_ll_system.h
  • LL_FMAC_ConfigFunc() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigX1() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigX2() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigY() : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_OVFLIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_RIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_SATIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_UNFLIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_WIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_DeInit() : stm32g4xx_ll_fmac.c
  • LL_FMAC_DisableClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableReset() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_CONVO_FIR : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_IIR_DIRECT_FORM_1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_X1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_X2 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_Y : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetFunction() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamP() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamQ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1FullWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX2Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX2BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYBase() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYBufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYEmptyWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_Init() : stm32g4xx_ll_fmac.c
  • LL_FMAC_IsActiveFlag_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_X1FULL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_YEMPTY() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledReset() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_PROCESSING_START : stm32g4xx_ll_fmac.h
  • LL_FMAC_PROCESSING_STOP : stm32g4xx_ll_fmac.h
  • LL_FMAC_ReadData() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ReadReg : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetFunction() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamP() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamQ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1FullWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX2Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX2BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYBase() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYBufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYEmptyWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_OVFL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_SAT : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_UNFL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_X1FULL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_YEMPTY : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_0_THRESHOLD_1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_1_THRESHOLD_2 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_2_THRESHOLD_4 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_3_THRESHOLD_8 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WriteData() : stm32g4xx_ll_fmac.h
  • LL_FMAC_WriteReg : stm32g4xx_ll_fmac.h
  • LL_GetFlashSize() : stm32g4xx_ll_utils.h
  • LL_GetPackageType() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word0() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word1() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word2() : stm32g4xx_ll_utils.h
  • LL_GPIO_AF_0 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32g4xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32g4xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32g4xx_ll_gpio.h
  • LL_GPIO_Init() : stm32g4xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32g4xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32g4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32g4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32g4xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32g4xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32g4xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32g4xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32g4xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32g4xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32g4xx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32g4xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32g4xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32g4xx_ll_cortex.h
  • LL_I2C_ACK : stm32g4xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32g4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32g4xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32g4xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32g4xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32g4xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_Disable() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_i2c.h
  • LL_I2C_Enable() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32g4xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32g4xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32g4xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32g4xx_ll_i2c.h
  • LL_I2C_Init() : stm32g4xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32g4xx_ll_i2c.h
  • LL_I2C_NACK : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32g4xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32g4xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32g4xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32g4xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32g4xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32g4xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32g4xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32g4xx_ll_spi.h
  • LL_I2S_ClearFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32g4xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32g4xx_ll_spi.c
  • LL_I2S_CR2_ERRIE : stm32g4xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32g4xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32g4xx_ll_spi.h
  • LL_I2S_DeInit() : stm32g4xx_ll_spi.c
  • LL_I2S_Disable() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_Enable() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32g4xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32g4xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32g4xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32g4xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32g4xx_ll_spi.h
  • LL_I2S_Init() : stm32g4xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32g4xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32g4xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32g4xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32g4xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32g4xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32g4xx_ll_spi.h
  • LL_I2S_ReadReg : stm32g4xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32g4xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32g4xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32g4xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32g4xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32g4xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32g4xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32g4xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32g4xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32g4xx_ll_spi.h
  • LL_I2S_StructInit() : stm32g4xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32g4xx_ll_spi.h
  • LL_I2S_WriteReg : stm32g4xx_ll_spi.h
  • LL_Init1msTick() : stm32g4xx_ll_utils.c
  • LL_InitTick() : stm32g4xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32g4xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32g4xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32g4xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32g4xx_ll_cortex.h
  • LL_LPTIM_ClearFlag_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_TRIG_FILTER_2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TrigSw() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32g4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32g4xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_DIRECTION_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_Disable() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32g4xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32g4xx_ll_utils.h
  • LL_mDelay() : stm32g4xx_ll_utils.c
  • LL_MPU_ACCESS_BUFFERABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32g4xx_ll_cortex.h
  • LL_MPU_Disable() : stm32g4xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_Enable() : stm32g4xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32g4xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32g4xx_ll_opamp.c
  • LL_OPAMP_DELAY_STARTUP_US : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Disable() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputsMuxMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInternalOutput() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32g4xx_ll_opamp.c
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_PGA_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_DISABLE : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM1_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM20_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM8_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO1_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO2 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO2_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO3 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO3_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INTERNAL_OUPUT_DISABLED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INTERNAL_OUPUT_ENABLED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsCalibrationOutputSet() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsLocked() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsTimerMuxLocked() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Lock() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_LockTimerMux() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_BIAS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_HIGHSPEED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMALSPEED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputsMuxMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInternalOutput() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32g4xx_ll_opamp.c
  • LL_OPAMP_TRIMMING_FACTORY : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32g4xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32g4xx_ll_opamp.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32g4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32g4xx_ll_utils.c
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32g4xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_SB() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32g4xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32g4xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableDeadBatteryPD : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableDeadBatteryPD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_G : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO2() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO4() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOSF : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_ADC : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_COMP : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_FASTDAC : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_OPAMP_DAC : stm32g4xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32g4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32g4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32g4xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32g4xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32g4xx_ll_pwr.h
  • LL_RCC_ADC12_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32g4xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32g4xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetI2SClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetI2SClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_PIN : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32g4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_10 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_11 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_12 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_13 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_14 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_15 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_9 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32g4xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetI2SClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32g4xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32g4xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32g4xx_ll_rng.h
  • LL_RNG_ClearFlag_CEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_CR_IE : stm32g4xx_ll_rng.h
  • LL_RNG_DeInit() : stm32g4xx_ll_rng.c
  • LL_RNG_Disable() : stm32g4xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32g4xx_ll_rng.h
  • LL_RNG_Enable() : stm32g4xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32g4xx_ll_rng.h
  • LL_RNG_Init() : stm32g4xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32g4xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32g4xx_ll_rng.h
  • LL_RNG_ReadReg : stm32g4xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32g4xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32g4xx_ll_rng.h
  • LL_RNG_StructInit() : stm32g4xx_ll_rng.c
  • LL_RNG_WriteReg : stm32g4xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_GetRegister() : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_NUMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_SetRegister() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CSR_ALRAF : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32g4xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32g4xx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32g4xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32g4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32g4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_ALRAWF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_ALRBWF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32g4xx_ll_rtc.h
  • LL_RTC_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32g4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32g4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32g4xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_TAMPER_1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP4 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP5 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP6 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32g4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32g4xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32g4xx_ll_rtc.h
  • LL_SetFlashLatency() : stm32g4xx_ll_utils.c
  • LL_SetSystemCoreClock() : stm32g4xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32g4xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32g4xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32g4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32g4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DeInit() : stm32g4xx_ll_spi.c
  • LL_SPI_Disable() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32g4xx_ll_spi.h
  • LL_SPI_Enable() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32g4xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32g4xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32g4xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32g4xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32g4xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_GetMode() : stm32g4xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32g4xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32g4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32g4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32g4xx_ll_spi.h
  • LL_SPI_Init() : stm32g4xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32g4xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32g4xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32g4xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32g4xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32g4xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32g4xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32g4xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32g4xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32g4xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32g4xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32g4xx_ll_spi.h
  • LL_SPI_ReadReg : stm32g4xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32g4xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32g4xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32g4xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32g4xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_SetMode() : stm32g4xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32g4xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32g4xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32g4xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32g4xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32g4xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32g4xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32g4xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32g4xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32g4xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32g4xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32g4xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32g4xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32g4xx_ll_spi.h
  • LL_SPI_StructInit() : stm32g4xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32g4xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_WriteReg : stm32g4xx_ll_spi.h
  • LL_SYSCFG_BANKMODE_BANK1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_BANKMODE_BANK2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE0 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE4 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE5 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_ClearFlag_SP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableCCMSRAMErase() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableCCMSRAMPageWRP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetFlashBankMode() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsCCMSRAMEraseOngoing() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_LockCCMSRAMWRP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetFlashBankMode() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32g4xx_ll_system.h
  • LL_SYSCFG_UnlockCCMSRAMWRP() : stm32g4xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32g4xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32g4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32g4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32g4xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_BKIN_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_INPUT : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_INPUT : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32g4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32g4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32g4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigIDX() : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32g4xx_ll_tim.h
  • LL_TIM_DeInit() : stm32g4xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_DIRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_IDXIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_IERRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_TERRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32g4xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_DisarmBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisarmBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DTR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ECR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_19TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_20TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_21TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_22TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_23TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_24TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_25TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_26TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X1_TI1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X1_TI2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32g4xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32g4xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32g4xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_GetFallingDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_GetIndexDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_GetIndexPositionning() : stm32g4xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32g4xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_GetSMSPreloadSource() : stm32g4xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32g4xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_HSE_32_NOT_REQUEST : stm32g4xx_ll_tim.h
  • LL_TIM_HSE_32_REQUEST : stm32g4xx_ll_tim.h
  • LL_TIM_IC_Config() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_ALL : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_FIRST_ONLY : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveUIFCPY() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32g4xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPulseWidth() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPulseWidthPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPulseWidth() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPulseWidthPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ASYMMETRIC_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ASYMMETRIC_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_DIRECTION_OUTPUT : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PULSE_ON_COMPARE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32g4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32g4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X1 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X128 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X16 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X32 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X4 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X64 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X8 : stm32g4xx_ll_tim.h
  • LL_TIM_ReadReg : stm32g4xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32g4xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32g4xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32g4xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetFallingDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_SetIndexDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_SetIndexPositionning() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetSMSPreloadSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32g4xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_GATEDRESET : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32g4xx_ll_tim.h
  • LL_TIM_SMSPS_INDEX : stm32g4xx_ll_tim.h
  • LL_TIM_SMSPS_TIMUPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_DIRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_IDXF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_IERRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_TERRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32g4xx_ll_tim.h
  • LL_TIM_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_TIM15_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_HSE_32 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC_WK : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_LSI : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_RTC_WK : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_TIM3_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_TIM4_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_TIM2_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_TIM4_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_TIM3_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI4_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_ENCODERCLK : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR10 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR11 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR4 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR5 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR6 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR8 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR9 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32g4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32g4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32g4xx_ll_tim.h
  • LL_TIM_WriteReg : stm32g4xx_ll_tim.h
  • LL_UCPD_CCENABLE_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC1CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_NONE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DeInit() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ForceClockDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ForceClockEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_FRSEVT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXHRSTDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXMSGEND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXNE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXORDDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXOVR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXIS : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGABT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXUND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_Init() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_IsActiveFlag_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabled() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabledRxDMA() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabledTxDMA() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_HARD_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_CABLERST : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_HARDRST : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV16 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV4 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV8 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadData() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadReg : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadRxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadRxPaySize() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_1_5A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_3_0A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_DEFAULT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_NONE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ROLE_SNK : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ROLE_SRC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RST1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RST2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDMADisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDMAEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxFilterDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxFilterEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXMODE_BIST_TEST_DATA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXMODE_NORMAL : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SendHardReset() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SendMessage() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetccEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetCCPin() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetHbitClockDiv() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetIfrGap() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetPSCClk() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRpResistor() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxMode() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetSNKRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetSRCRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetTransWin() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetTxMode() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SignalFRSTX() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VOPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP15A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP30A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VOPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP15A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP30A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_FRSEVT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXERR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXHRSTDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXMSGEND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXNE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXORDDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXOVR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXIS : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGABT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXUND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_OPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRD : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_OPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRD : stm32g4xx_ll_ucpd.h
  • LL_UCPD_StructInit() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_SYNC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SYNC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SYNC3 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TxDMADisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TxDMAEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_BIST_CARRIER2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_NORMAL : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WakeUpDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WakeUpEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteData() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteReg : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteTxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteTxPaySize() : stm32g4xx_ll_ucpd.h
  • LL_USART_ADDRESS_DETECT_4B : stm32g4xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32g4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32g4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32g4xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32g4xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32g4xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32g4xx_ll_usart.h
  • LL_USART_ClockInit() : stm32g4xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32g4xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32g4xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32g4xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32g4xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32g4xx_ll_usart.h
  • LL_USART_DeInit() : stm32g4xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32g4xx_ll_usart.h
  • LL_USART_Disable() : stm32g4xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32g4xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32g4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_usart.h
  • LL_USART_Enable() : stm32g4xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32g4xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32g4xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32g4xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32g4xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32g4xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32g4xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32g4xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32g4xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32g4xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32g4xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32g4xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32g4xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32g4xx_ll_usart.h
  • LL_USART_GetParity() : stm32g4xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32g4xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32g4xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32g4xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32g4xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32g4xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32g4xx_ll_usart.h
  • LL_USART_Init() : stm32g4xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32g4xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_FE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_NE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_PE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TC : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32g4xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32g4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32g4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32g4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32g4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32g4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32g4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32g4xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32g4xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32g4xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32g4xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32g4xx_ll_usart.h
  • LL_USART_ReadReg : stm32g4xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32g4xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32g4xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32g4xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32g4xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32g4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32g4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32g4xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32g4xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32g4xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32g4xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32g4xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32g4xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32g4xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32g4xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32g4xx_ll_usart.h
  • LL_USART_SetParity() : stm32g4xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32g4xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32g4xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32g4xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32g4xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32g4xx_ll_usart.h
  • LL_USART_StructInit() : stm32g4xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32g4xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32g4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32g4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32g4xx_ll_usart.h
  • LL_USART_WriteReg : stm32g4xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32g4xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP128 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP32 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48_EBIKE : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN32 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN48 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP49 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP81 : stm32g4xx_ll_utils.h
  • LL_VREFBUF_Disable() : stm32g4xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32g4xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32g4xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32g4xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32g4xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32g4xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32g4xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32g4xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32g4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32g4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32g4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE2 : stm32g4xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32g4xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32g4xx_ll_wwdg.h
  • LPM_L0 : stm32g4xx_hal_pcd.h
  • LPM_L1 : stm32g4xx_hal_pcd.h
  • LPM_L2 : stm32g4xx_hal_pcd.h
  • LPM_L3 : stm32g4xx_hal_pcd.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32g4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32g4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32g4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32g4xx_hal_lptim.h
  • LPTIM_Disable() : stm32g4xx_hal_lptim.c
  • LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32g4xx_hal_lptim.h
  • LPTIM_HandleTypeDef : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP3 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP4 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32g4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32g4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32g4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32g4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32g4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32g4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32g4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32g4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32g4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32g4xx_hal_lptim.h
  • LPTIM_ResetCallback() : stm32g4xx_hal_lptim.c
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_10 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_11 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_12 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_8 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_9 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32g4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32g4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32g4xx_hal_lptim.h
  • LPTIM_WaitForFlag() : stm32g4xx_hal_lptim.c
  • LPUART_BRR_MASK : stm32g4xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32g4xx_hal_uart.c
  • LPUART_BRR_MIN : stm32g4xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32g4xx_ll_lpuart.h
  • LPUART_DEFAULT_BAUDRATE : stm32g4xx_ll_lpuart.c
  • LPUART_LPUARTDIV_FREQ_MUL : stm32g4xx_ll_lpuart.h
  • LPUART_PRESCALER_TAB : stm32g4xx_ll_lpuart.h
  • LSCO_GPIO_PORT : stm32g4xx_hal_rcc_ex.c
  • LSCO_PIN : stm32g4xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32g4xx_hal_conf.h
  • LSE_VALUE : stm32g4xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • LSI_VALUE : stm32g4xx_hal_conf.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_FILTER_DATA_SIZE_TO_HANDLE : stm32g4xx_hal_fmac.c
  • MAX_NBYTE_SIZE : stm32g4xx_hal_i2c.c , stm32g4xx_hal_smbus.c
  • MAX_PRELOAD_INDEX : stm32g4xx_hal_fmac.c
  • MEMRMP_OFFSET : stm32g4xx_hal.c
  • MODE_AF : stm32g4xx_hal_gpio.h
  • MODE_ANALOG : stm32g4xx_hal_gpio.h
  • MODE_INPUT : stm32g4xx_hal_gpio.h
  • MODE_OUTPUT : stm32g4xx_hal_gpio.h
  • MPU_ACCESS_BUFFERABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32g4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32g4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32g4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32g4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32g4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32g4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32g4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32g4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32g4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32g4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL4 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NVIC_PRIORITYGROUP_0 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOT0_FROM_OB : stm32g4xx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32g4xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32g4xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32g4xx_hal_flash.h
  • OB_BOOT_LOCK_DISABLE : stm32g4xx_hal_flash.h
  • OB_BOOT_LOCK_ENABLE : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32g4xx_hal_flash.h
  • OB_CCMSRAM_RST_ERASE : stm32g4xx_hal_flash.h
  • OB_CCMSRAM_RST_NOT_ERASE : stm32g4xx_hal_flash.h
  • OB_IRH_DISABLE : stm32g4xx_hal_flash.h
  • OB_IRH_ENABLE : stm32g4xx_hal_flash.h
  • OB_IWDG_HW : stm32g4xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32g4xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32g4xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32g4xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32g4xx_hal_flash.h
  • OB_IWDG_SW : stm32g4xx_hal_flash.h
  • OB_nBOOT0_RESET : stm32g4xx_hal_flash.h
  • OB_nBOOT0_SET : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_GPIO : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_INPUT_ONLY : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_INPUT_OUTPUT : stm32g4xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32g4xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32g4xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32g4xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32g4xx_hal_flash.h
  • OB_SRAM_PARITY_DISABLE : stm32g4xx_hal_flash.h
  • OB_SRAM_PARITY_ENABLE : stm32g4xx_hal_flash.h
  • OB_STANDBY_NORST : stm32g4xx_hal_flash.h
  • OB_STANDBY_RST : stm32g4xx_hal_flash.h
  • OB_STOP_NORST : stm32g4xx_hal_flash.h
  • OB_STOP_RST : stm32g4xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32g4xx_hal_flash.h
  • OB_USER_CCMSRAM_RST : stm32g4xx_hal_flash.h
  • OB_USER_IRHEN : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32g4xx_hal_flash.h
  • OB_USER_nBOOT0 : stm32g4xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32g4xx_hal_flash.h
  • OB_USER_NRST_MODE : stm32g4xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32g4xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32g4xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32g4xx_hal_flash.h
  • OB_USER_nSWBOOT0 : stm32g4xx_hal_flash.h
  • OB_USER_SRAM_PE : stm32g4xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32g4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32g4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32g4xx_hal_flash.h
  • OB_WWDG_HW : stm32g4xx_hal_flash.h
  • OB_WWDG_SW : stm32g4xx_hal_flash.h
  • OC1Config() : stm32g4xx_ll_tim.c
  • OC2Config() : stm32g4xx_ll_tim.c
  • OC3Config() : stm32g4xx_ll_tim.c
  • OC4Config() : stm32g4xx_ll_tim.c
  • OC5Config() : stm32g4xx_ll_tim.c
  • OC6Config() : stm32g4xx_ll_tim.c
  • OCREF_CLEAR_SELECT_Msk : stm32g4xx_ll_tim.h
  • OCREF_CLEAR_SELECT_Pos : stm32g4xx_ll_tim.h
  • OFFSET_TAB_CCMRx : stm32g4xx_ll_tim.h
  • OPAMP_CSR_RESET_CHECK_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32g4xx_hal_opamp.c
  • OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32g4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32g4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32g4xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_HandleTypeDef : stm32g4xx_hal_opamp.h
  • OPAMP_INPUT_INVERTING : stm32g4xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32g4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO2 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO3 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_32_OR_MINUS_31 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_64_OR_MINUS_63 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32g4xx_hal_opamp.h
  • OPAMP_POWERMODE_NORMALSPEED : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_FOLLOWER : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_PGA : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_DAC : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO2 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO3 : stm32g4xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE : stm32g4xx_hal_opamp.h
  • OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 : stm32g4xx_hal_opamp.h
  • OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32g4xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32g4xx_ll_opamp.h
  • OPAMP_TrimmingValueTypeDef : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_10VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32g4xx_hal_opamp.h
  • OPTIONBYTE_BOOT_LOCK : stm32g4xx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32g4xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32g4xx_hal_flash.h
  • OPTIONBYTE_SEC : stm32g4xx_hal_flash.h
  • OPTIONBYTE_USER : stm32g4xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32g4xx_hal_flash.h
  • OUTPUT_OD : stm32g4xx_hal_gpio.h
  • OUTPUT_PP : stm32g4xx_hal_gpio.h
  • OUTPUT_TYPE : stm32g4xx_hal_gpio.h
  • OUTPUT_TYPE_Pos : stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • pADC_CallbackTypeDef : stm32g4xx_hal_adc.h
  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32g4xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32g4xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32g4xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32g4xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32g4xx_hal_pcd.h
  • PCD_BCD_MsgTypeDef : stm32g4xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32g4xx_hal_pcd.h
  • PCD_CALC_BLK2 : stm32g4xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_BULK_EP_DBUF : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32g4xx_hal_pcd.h
  • PCD_DBL_BUF : stm32g4xx_hal_pcd.h
  • PCD_ENDP0 : stm32g4xx_hal_pcd.h
  • PCD_ENDP1 : stm32g4xx_hal_pcd.h
  • PCD_ENDP2 : stm32g4xx_hal_pcd.h
  • PCD_ENDP3 : stm32g4xx_hal_pcd.h
  • PCD_ENDP4 : stm32g4xx_hal_pcd.h
  • PCD_ENDP5 : stm32g4xx_hal_pcd.h
  • PCD_ENDP6 : stm32g4xx_hal_pcd.h
  • PCD_ENDP7 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32g4xx_hal_pcd.h
  • PCD_EP_ISR_Handler() : stm32g4xx_hal_pcd.c
  • PCD_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_EPTypeDef : stm32g4xx_hal_pcd.h
  • PCD_FREE_USER_BUFFER : stm32g4xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32g4xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32g4xx_hal_pcd.h
  • PCD_InitTypeDef : stm32g4xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32g4xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32g4xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32g4xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32g4xx_hal_pcd.h
  • PCD_MAX : stm32g4xx_hal_pcd.c
  • PCD_MIN : stm32g4xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32g4xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32g4xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32g4xx_hal_pcd.h
  • PCD_RX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_SET_BULK_EP_DBUF : stm32g4xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32g4xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SNG_BUF : stm32g4xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32g4xx_hal_pcd.h
  • PCD_StateTypeDef : stm32g4xx_hal_pcd.h
  • PCD_TX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_TypeDef : stm32g4xx_hal_pcd.h
  • pCOMP_CallbackTypeDef : stm32g4xx_hal_comp.h
  • pCORDIC_CallbackTypeDef : stm32g4xx_hal_cordic.h
  • pDAC_CallbackTypeDef : stm32g4xx_hal_dac.h
  • pFDCAN_CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFlash : stm32g4xx_hal_flash.c , stm32g4xx_hal_flash.h
  • pFMAC_CallbackTypeDef : stm32g4xx_hal_fmac.h
  • pI2C_AddrCallbackTypeDef : stm32g4xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32g4xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32g4xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32g4xx_hal_irda.h
  • PLL_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c , stm32g4xx_hal_rcc_ex.c
  • pLPTIM_CallbackTypeDef : stm32g4xx_hal_lptim.h
  • POLLING_DISABLED : stm32g4xx_hal_fmac.c
  • POLLING_ENABLED : stm32g4xx_hal_fmac.c
  • POLLING_NOT_STOPPED : stm32g4xx_hal_fmac.c
  • POLLING_STOPPED : stm32g4xx_hal_fmac.c
  • pOPAMP_CallbackTypeDef : stm32g4xx_hal_opamp.h
  • pPCD_BcdCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32g4xx_hal_pcd.h
  • PREFETCH_ENABLE : stm32g4xx_hal_conf.h
  • PRELOAD_ACCESS_DMA : stm32g4xx_hal_fmac.c
  • PRELOAD_ACCESS_POLLING : stm32g4xx_hal_fmac.c
  • pRNG_CallbackTypeDef : stm32g4xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32g4xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32g4xx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32g4xx_hal_sai.h
  • pSMARTCARD_CallbackTypeDef : stm32g4xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32g4xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32g4xx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32g4xx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32g4xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32g4xx_hal_uart.h
  • pUART_RxEventCallbackTypeDef : stm32g4xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32g4xx_hal_usart.h
  • PVD_FALLING_EDGE : stm32g4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32g4xx_hal_pwr.c
  • PVD_MODE_IT : stm32g4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32g4xx_hal_pwr.c
  • PVM_FALLING_EDGE : stm32g4xx_hal_pwr_ex.c
  • PVM_MODE_EVT : stm32g4xx_hal_pwr_ex.c
  • PVM_MODE_IT : stm32g4xx_hal_pwr_ex.c
  • PVM_RISING_EDGE : stm32g4xx_hal_pwr_ex.c
  • PWR_BATTERY_CHARGING_DISABLE : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32g4xx_hal_pwr.h
  • PWR_EVENT_LINE_PVM1 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM2 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM3 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM4 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32g4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM2 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO2 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32g4xx_hal_pwr_ex.c
  • PWR_FLAG_VOSF : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_G : stm32g4xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32g4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32g4xx_hal_pwr.h
  • PWR_PORTF_AVAILABLE_PINS : stm32g4xx_hal_pwr_ex.c
  • PWR_PORTG_AVAILABLE_PINS : stm32g4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32g4xx_hal_pwr.h
  • PWR_PVM_1 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_2 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_4 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1_BOOST : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32g4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32g4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32g4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32g4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32g4xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32g4xx_hal_pwr_ex.h
  • pWWDG_CallbackTypeDef : stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADC12CLKSOURCE_NONE : stm32g4xx_hal_rcc_ex.h
  • RCC_ADC12CLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_ADC12CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_ALL : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32g4xx_hal_rcc.h
  • RCC_EXTI_LINE_LSECSS : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32g4xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32g4xx_hal_rcc.h
  • RCC_GET_MCO_GPIO_AF : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_INDEX : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_PIN : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_PORT : stm32g4xx_hal_rcc.c
  • RCC_GetHCLKClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetSysClockFreqFromPLLSource() : stm32g4xx_hal_rcc.c
  • RCC_GetSystemClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32g4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSE_ON : stm32g4xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSI48_ON : stm32g4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSI_ON : stm32g4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32g4xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_EXT : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32g4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32g4xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32g4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32g4xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32g4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32g4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32g4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32g4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32g4xx_hal_rcc.h
  • RCC_LSE_OFF : stm32g4xx_hal_rcc.h
  • RCC_LSE_ON : stm32g4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32g4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32g4xx_hal_rcc.h
  • RCC_LSI_ON : stm32g4xx_hal_rcc.h
  • RCC_MCO : stm32g4xx_hal_rcc.h
  • RCC_MCO1 : stm32g4xx_hal_rcc.h
  • RCC_MCO1_INDEX : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOAF_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOAF_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOPORT_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOPORT_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_INDEX_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_INDEX_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_PA8 : stm32g4xx_hal_rcc.h
  • RCC_MCO_PG10 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32g4xx_hal_rcc.h
  • RCC_OFFSET_CCIPR : stm32g4xx_ll_rcc.h
  • RCC_OFFSET_CCIPR2 : stm32g4xx_ll_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32g4xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC12 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32g4xx_hal_rcc_ex.h
  • RCC_PLL_48M1CLK : stm32g4xx_hal_rcc.h
  • RCC_PLL_ADCCLK : stm32g4xx_hal_rcc.h
  • RCC_PLL_GetFreqDomain_48M() : stm32g4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_ADC() : stm32g4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32g4xx_ll_rcc.c
  • RCC_PLL_NONE : stm32g4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32g4xx_hal_rcc.h
  • RCC_PLL_ON : stm32g4xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32g4xx_hal_rcc.c
  • RCC_PLL_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV10 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV11 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV12 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV13 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV14 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV15 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV9 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32g4xx_hal_rcc.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32g4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32g4xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_EXT : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_UART4CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32g4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RNG_CED_DISABLE : stm32g4xx_hal_rng.h
  • RNG_CED_ENABLE : stm32g4xx_hal_rng.h
  • RNG_FLAG_CECS : stm32g4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32g4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32g4xx_hal_rng.h
  • RNG_HandleTypeDef : stm32g4xx_hal_rng.h
  • RNG_IT_CEI : stm32g4xx_hal_rng.h
  • RNG_IT_DRDY : stm32g4xx_hal_rng.h
  • RNG_IT_SEI : stm32g4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32g4xx_hal_rng.c
  • RTC_ALARM_A : stm32g4xx_hal_rtc.h
  • RTC_ALARM_B : stm32g4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32g4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32g4xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32g4xx_ll_rtc.c
  • RTC_Bcd2ToByte() : stm32g4xx_hal_rtc.c
  • RTC_BKP_DR0 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_NUMBER : stm32g4xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32g4xx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32g4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32g4xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32g4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32g4xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32g4xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TAMPER_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TIMESTAMP_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_ITSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_MASK : stm32g4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32g4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32g4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32g4xx_hal_rtc.h
  • RTC_HandleTypeDef : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32g4xx_hal_rtc.h
  • RTC_ICSR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32g4xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32g4xx_ll_rtc.c
  • RTC_INT_TAMPER_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32g4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32g4xx_hal_rtc.h
  • RTC_IT_INT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32g4xx_hal_rtc.h
  • RTC_IT_WUT : stm32g4xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32g4xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32g4xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32g4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32g4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32g4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32g4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32g4xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32g4xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32g4xx_hal_rtc.h
  • RTC_RSF_MASK : stm32g4xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32g4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32g4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32g4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32g4xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32g4xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32g4xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32g4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32g4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32g4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32g4xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32g4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32g4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32g4xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32g4xx_hal_uart_ex.c , stm32g4xx_hal_smartcard_ex.c , stm32g4xx_hal_usart_ex.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_FRAME_LENGTH : stm32g4xx_hal_sai.c
  • SAI_AC97_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32g4xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32g4xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32g4xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32g4xx_hal_sai.c
  • SAI_Disable() : stm32g4xx_hal_sai.c
  • SAI_DMAAbort() : stm32g4xx_hal_sai.c
  • SAI_DMAError() : stm32g4xx_hal_sai.c
  • SAI_DMARxCplt() : stm32g4xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32g4xx_hal_sai.c
  • SAI_DMATxCplt() : stm32g4xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32g4xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32g4xx_hal_sai.h
  • SAI_FillFifo() : stm32g4xx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32g4xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32g4xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32g4xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32g4xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32g4xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32g4xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32g4xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32g4xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32g4xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32g4xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32g4xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32g4xx_hal_sai.h
  • SAI_HandleTypeDef : stm32g4xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32g4xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32g4xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32g4xx_hal_sai.h
  • SAI_InitI2S() : stm32g4xx_hal_sai.c
  • SAI_InitPCM() : stm32g4xx_hal_sai.c
  • SAI_InterruptFlag() : stm32g4xx_hal_sai.c
  • SAI_IT_AFSDET : stm32g4xx_hal_sai.h
  • SAI_IT_CNRDY : stm32g4xx_hal_sai.h
  • SAI_IT_FREQ : stm32g4xx_hal_sai.h
  • SAI_IT_LFSDET : stm32g4xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32g4xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32g4xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32g4xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32g4xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32g4xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MODE_DMA : stm32g4xx_hal_sai.c
  • SAI_MODE_IT : stm32g4xx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32g4xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32g4xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32g4xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32g4xx_hal_sai.h
  • SAI_ModeTypedef : stm32g4xx_hal_sai.c
  • SAI_MONOMODE : stm32g4xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32g4xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32g4xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32g4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32g4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PCM_LONG : stm32g4xx_hal_sai.h
  • SAI_PCM_SHORT : stm32g4xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32g4xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32g4xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32g4xx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32g4xx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32g4xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32g4xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32g4xx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32g4xx_hal_sai.h
  • SAI_SPDIF_FRAME_LENGTH : stm32g4xx_hal_sai.c
  • SAI_SPDIF_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_STEREOMODE : stm32g4xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32g4xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32g4xx_hal_sai.h
  • SAI_Transmit_IT16Bit() : stm32g4xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32g4xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32g4xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ZERO_VALUE : stm32g4xx_hal_sai.h
  • SAIcallback : stm32g4xx_hal_sai.h
  • SCSR_CCMER_BB : stm32g4xx_hal.c
  • SCSR_OFFSET : stm32g4xx_hal.c
  • SHIFT_TAB_CCxP : stm32g4xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32g4xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32g4xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32g4xx_ll_tim.h
  • SLAVE_ADDR_MSK : stm32g4xx_hal_i2c.c
  • SLAVE_ADDR_SHIFT : stm32g4xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CR_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32g4xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_FIFOMODE_DISABLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_HandleTypeDef : stm32g4xx_hal_smartcard.h
  • SMARTCARD_InitCallbacksToDefault() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_ISR_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32g4xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32g4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RxISR() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32g4xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TxISR() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32g4xx_hal_smartcard.h
  • SMARTCARDEx_SetNbDataToProcess() : stm32g4xx_hal_smartcard_ex.c
  • SMBUS_ADDRESSINGMODE_10BIT : stm32g4xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32g4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32g4xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32g4xx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32g4xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32g4xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32g4xx_hal_smbus.c
  • SMBUS_FASTMODEPLUS_I2C1 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C2 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C3 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C4 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB6 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB7 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB8 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB9 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32g4xx_hal_smbus.h
  • SMBUS_Flush_TXDR() : stm32g4xx_hal_smbus.c
  • SMBUS_FMP_NOT_SUPPORTED : stm32g4xx_hal_smbus_ex.h
  • SMBUS_GENERALCALL_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32g4xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32g4xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32g4xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32g4xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_HandleTypeDef : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_RX : stm32g4xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TX : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32g4xx_hal_smbus.h
  • SMBUS_ITErrorHandler() : stm32g4xx_hal_smbus.c
  • SMBUS_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32g4xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32g4xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32g4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32g4xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32g4xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32g4xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32g4xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32g4xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32g4xx_hal_smbus.c
  • SPI_1LINE_RX : stm32g4xx_hal_spi.h
  • SPI_1LINE_TX : stm32g4xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32g4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32g4xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32g4xx_hal_spi.h
  • SPI_CHECK_FLAG : stm32g4xx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32g4xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32g4xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32g4xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32g4xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32g4xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32g4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32g4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32g4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32g4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32g4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32g4xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32g4xx_hal_spi.c
  • SPI_DMAError() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32g4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32g4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32g4xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32g4xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32g4xx_hal_spi.c
  • SPI_FIFO_SIZE : stm32g4xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32g4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32g4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32g4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32g4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32g4xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32g4xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32g4xx_hal_spi.h
  • SPI_FLAG_MASK : stm32g4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32g4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32g4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32g4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32g4xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32g4xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32g4xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32g4xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32g4xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32g4xx_hal_spi.h
  • SPI_HandleTypeDef : stm32g4xx_hal_spi.h
  • SPI_IT_ERR : stm32g4xx_hal_spi.h
  • SPI_IT_RXNE : stm32g4xx_hal_spi.h
  • SPI_IT_TXE : stm32g4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32g4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32g4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32g4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32g4xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32g4xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32g4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32g4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32g4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32g4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32g4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32g4xx_hal_spi.h
  • SPI_RESET_CRC : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32g4xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32g4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32g4xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32g4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32g4xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32g4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32g4xx_hal_spi.c
  • SRAMCAN_FLE_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLE_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLESA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLS_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLS_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLSSA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0SA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1SA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEF_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEF_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEFSA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQ_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQ_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQSA : stm32g4xx_hal_fdcan.c
  • SYSCFG_BOOT_MAINFLASH : stm32g4xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32g4xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE0 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE1 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE10 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE11 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE12 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE13 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE14 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE15 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE16 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE17 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE18 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE19 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE2 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE20 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE21 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE22 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE23 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE24 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE25 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE26 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE27 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE28 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE29 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE3 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE30 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE31 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE4 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE5 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE6 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE7 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE8 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE9 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32g4xx_hal.h
  • SYSCFG_FLAG_CCMSRAM_BUSY : stm32g4xx_hal.h
  • SYSCFG_FLAG_SRAM_PE : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32g4xx_hal.h
  • SYSCFG_OFFSET : stm32g4xx_hal.c
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32g4xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32g4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32g4xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32g4xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32g4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32g4xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32g4xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32g4xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g4xx_hal_tim.h
  • TIM_BREAK2_AFMODE_INPUT : stm32g4xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g4xx_hal_tim.h
  • TIM_BREAK_AFMODE_INPUT : stm32g4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32g4xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_REARM_TIMEOUT : stm32g4xx_hal_tim_ex.c
  • TIM_BREAKINPUTSOURCE_BKIN : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_CALC_DTS : stm32g4xx_ll_tim.h
  • TIM_CCDMAREQUEST_CC : stm32g4xx_hal_tim.h
  • TIM_CCDMAREQUEST_UPDATE : stm32g4xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32g4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32g4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32g4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32g4xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32g4xx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32g4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32g4xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32g4xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_GET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET_ALL : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_GET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET_ALL : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP3 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP4 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR10 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR11 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR5 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR6 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR8 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32g4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32g4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32g4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32g4xx_hal_tim.h
  • TIM_DMA_COM : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32g4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32g4xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32g4xx_hal_tim.h
  • TIM_DMABASE_DTR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_ECR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_OR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32g4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_19TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_20TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_21TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_22TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_23TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_24TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_25TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_26TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32g4xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseNCplt() : stm32g4xx_hal_tim_ex.c
  • TIM_DMAError() : stm32g4xx_hal_tim.c
  • TIM_DMAErrorCCxN() : stm32g4xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32g4xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32g4xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_ENCODERINDEX_DIRECTION_DOWN : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_DIRECTION_UP : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_DIRECTION_UP_DOWN : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POLARITY_INVERTED : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POLARITY_NONINVERTED : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_0 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_00 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_01 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_1 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_10 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_11 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV1 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV2 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV4 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV8 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_X1_TI1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_X1_TI2 : stm32g4xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32g4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32g4xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32g4xx_hal_tim.h
  • TIM_FLAG_COM : stm32g4xx_hal_tim.h
  • TIM_FLAG_DIR : stm32g4xx_hal_tim.h
  • TIM_FLAG_IDX : stm32g4xx_hal_tim.h
  • TIM_FLAG_IERR : stm32g4xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32g4xx_hal_tim.h
  • TIM_FLAG_TERR : stm32g4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32g4xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32g4xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32g4xx_hal_tim.h
  • TIM_HandleTypeDef : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_IT_BREAK : stm32g4xx_hal_tim.h
  • TIM_IT_CC1 : stm32g4xx_hal_tim.h
  • TIM_IT_CC2 : stm32g4xx_hal_tim.h
  • TIM_IT_CC3 : stm32g4xx_hal_tim.h
  • TIM_IT_CC4 : stm32g4xx_hal_tim.h
  • TIM_IT_COM : stm32g4xx_hal_tim.h
  • TIM_IT_DIR : stm32g4xx_hal_tim.h
  • TIM_IT_IDX : stm32g4xx_hal_tim.h
  • TIM_IT_IERR : stm32g4xx_hal_tim.h
  • TIM_IT_TERR : stm32g4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32g4xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32g4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32g4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ASYMMETRIC_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ASYMMETRIC_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_DIRECTION_OUTPUT : stm32g4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PULSE_ON_COMPARE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32g4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32g4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32g4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32g4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32g4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32g4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32g4xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32g4xx_hal_tim.h
  • TIM_ResetCallback() : stm32g4xx_hal_tim.c
  • TIM_SET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_GATEDRESET : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_SMS_PRELOAD_SOURCE_INDEX : stm32g4xx_hal_tim_ex.h
  • TIM_SMS_PRELOAD_SOURCE_UPDATE : stm32g4xx_hal_tim_ex.h
  • TIM_TI1_ConfigInputStage() : stm32g4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32g4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32g4xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32g4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TIM15_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_HSE_32 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_MCO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC_WK : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_LSI : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RTC_WK : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_TIM3_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_TIM4_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI3_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_TIM2_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_TIM4_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI3_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_TIM3_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI4_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32g4xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32g4xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32g4xx_hal_tim.h
  • TIM_TRGO_ENCODER_CLK : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32g4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_TS_ETRF : stm32g4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR10 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR11 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR5 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR6 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR7 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR8 : stm32g4xx_hal_tim.h
  • TIM_TS_NONE : stm32g4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32g4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32g4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32g4xx_hal_tim.h
  • TIM_UIFREMAP_DISABLE : stm32g4xx_hal_tim.h
  • TIM_UIFREMAP_ENABLE : stm32g4xx_hal_tim.h
  • TIMEOUT : stm32g4xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32g4xx_hal_dac.c
  • TIMEx_DMACommutationCplt() : stm32g4xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32g4xx_hal_tim_ex.c
  • TIMING_CLEAR_MASK : stm32g4xx_hal_smbus.c , stm32g4xx_hal_i2c.c
  • TIMx_AF1_BKINP : stm32g4xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32g4xx_ll_tim.h
  • TIMx_AF2_OCRSEL : stm32g4xx_hal_tim.c
  • TRIGGER_FALLING : stm32g4xx_hal_gpio.h
  • TRIGGER_MODE : stm32g4xx_hal_gpio.h
  • TRIGGER_MODE_Pos : stm32g4xx_hal_gpio.h
  • TRIGGER_RISING : stm32g4xx_hal_gpio.h
  • TX_FIFO_DEPTH : stm32g4xx_hal_uart_ex.c , stm32g4xx_hal_smartcard_ex.c , stm32g4xx_hal_usart_ex.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32g4xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32g4xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32g4xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32g4xx_hal_uart.h
  • UART_BRR_MAX : stm32g4xx_hal_uart.c
  • UART_BRR_MIN : stm32g4xx_hal_uart.c
  • UART_CheckIdleState() : stm32g4xx_hal_uart.c
  • UART_CLEAR_CMF : stm32g4xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32g4xx_hal_uart.h
  • UART_CLEAR_FEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32g4xx_hal_uart.h
  • UART_CLEAR_NEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_OREF : stm32g4xx_hal_uart.h
  • UART_CLEAR_PEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32g4xx_hal_uart.h
  • UART_CLEAR_TCF : stm32g4xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32g4xx_hal_uart.h
  • UART_CLEAR_WUF : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32g4xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32g4xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32g4xx_hal_uart.h
  • UART_DIV_LPUART : stm32g4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32g4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32g4xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32g4xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32g4xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32g4xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32g4xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32g4xx_hal_uart.c
  • UART_DMAError() : stm32g4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32g4xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32g4xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32g4xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32g4xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32g4xx_hal_uart.c
  • UART_EndRxTransfer() : stm32g4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32g4xx_hal_uart.c
  • UART_EndTxTransfer() : stm32g4xx_hal_uart.c
  • UART_FIFOMODE_DISABLE : stm32g4xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32g4xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32g4xx_hal_uart.h
  • UART_FLAG_ABRF : stm32g4xx_hal_uart.h
  • UART_FLAG_BUSY : stm32g4xx_hal_uart.h
  • UART_FLAG_CMF : stm32g4xx_hal_uart.h
  • UART_FLAG_CTS : stm32g4xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32g4xx_hal_uart.h
  • UART_FLAG_FE : stm32g4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32g4xx_hal_uart.h
  • UART_FLAG_LBDF : stm32g4xx_hal_uart.h
  • UART_FLAG_NE : stm32g4xx_hal_uart.h
  • UART_FLAG_ORE : stm32g4xx_hal_uart.h
  • UART_FLAG_PE : stm32g4xx_hal_uart.h
  • UART_FLAG_REACK : stm32g4xx_hal_uart.h
  • UART_FLAG_RTOF : stm32g4xx_hal_uart.h
  • UART_FLAG_RWU : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFF : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFT : stm32g4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32g4xx_hal_uart.h
  • UART_FLAG_SBKF : stm32g4xx_hal_uart.h
  • UART_FLAG_TC : stm32g4xx_hal_uart.h
  • UART_FLAG_TEACK : stm32g4xx_hal_uart.h
  • UART_FLAG_TXE : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFE : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFT : stm32g4xx_hal_uart.h
  • UART_FLAG_WUF : stm32g4xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32g4xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32g4xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32g4xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32g4xx_hal_uart.h
  • UART_HandleTypeDef : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32g4xx_hal_uart.h
  • UART_InitCallbacksToDefault() : stm32g4xx_hal_uart.c
  • UART_INSTANCE_LOWPOWER : stm32g4xx_hal_uart.h
  • UART_IT_CM : stm32g4xx_hal_uart.h
  • UART_IT_CTS : stm32g4xx_hal_uart.h
  • UART_IT_ERR : stm32g4xx_hal_uart.h
  • UART_IT_FE : stm32g4xx_hal_uart.h
  • UART_IT_IDLE : stm32g4xx_hal_uart.h
  • UART_IT_LBD : stm32g4xx_hal_uart.h
  • UART_IT_MASK : stm32g4xx_hal_uart.h
  • UART_IT_NE : stm32g4xx_hal_uart.h
  • UART_IT_ORE : stm32g4xx_hal_uart.h
  • UART_IT_PE : stm32g4xx_hal_uart.h
  • UART_IT_RTO : stm32g4xx_hal_uart.h
  • UART_IT_RXFF : stm32g4xx_hal_uart.h
  • UART_IT_RXFNE : stm32g4xx_hal_uart.h
  • UART_IT_RXFT : stm32g4xx_hal_uart.h
  • UART_IT_RXNE : stm32g4xx_hal_uart.h
  • UART_IT_TC : stm32g4xx_hal_uart.h
  • UART_IT_TXE : stm32g4xx_hal_uart.h
  • UART_IT_TXFE : stm32g4xx_hal_uart.h
  • UART_IT_TXFNF : stm32g4xx_hal_uart.h
  • UART_IT_TXFT : stm32g4xx_hal_uart.h
  • UART_IT_WUF : stm32g4xx_hal_uart.h
  • UART_LIN_DISABLE : stm32g4xx_hal_uart.h
  • UART_LIN_ENABLE : stm32g4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32g4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32g4xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32g4xx_hal_uart_ex.h
  • UART_MODE_RX : stm32g4xx_hal_uart.h
  • UART_MODE_TX : stm32g4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32g4xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32g4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32g4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32g4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32g4xx_hal_uart.h
  • UART_PARITY_NONE : stm32g4xx_hal_uart.h
  • UART_PARITY_ODD : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32g4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32g4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32g4xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_uart_ex.h
  • UART_RxISR_16BIT() : stm32g4xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32g4xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_SENDBREAK_REQUEST : stm32g4xx_hal_uart.h
  • UART_SetConfig() : stm32g4xx_hal_uart.c
  • UART_Start_Receive_DMA() : stm32g4xx_hal_uart.c
  • UART_Start_Receive_IT() : stm32g4xx_hal_uart.c
  • UART_STATE_DISABLE : stm32g4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32g4xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32g4xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_uart_ex.h
  • UART_TxISR_16BIT() : stm32g4xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32g4xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32g4xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32g4xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32g4xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32g4xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32g4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32g4xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32g4xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32g4xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32g4xx_hal_uart_ex.h
  • UARTEx_SetNbDataToProcess() : stm32g4xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32g4xx_hal_uart_ex.c
  • UARTPrescTable : stm32g4xx_hal_uart.c , stm32g4xx_hal_uart.h
  • UID_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • UNUSED : stm32g4xx_ll_dmamux.h
  • USART_BRR_MAX : stm32g4xx_hal_irda.c , stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_BRR_MIN : stm32g4xx_hal_irda.c , stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_CheckIdleState() : stm32g4xx_hal_usart.c
  • USART_CLEAR_FEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_NEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_OREF : stm32g4xx_hal_usart.h
  • USART_CLEAR_PEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_RTOF : stm32g4xx_hal_usart.h
  • USART_CLEAR_TCF : stm32g4xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32g4xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32g4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32g4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32g4xx_hal_usart.h
  • USART_CR1_FIELDS : stm32g4xx_hal_smartcard.c , stm32g4xx_hal_uart.c , stm32g4xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32g4xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_CR3_FIELDS : stm32g4xx_hal_usart.c , stm32g4xx_hal_uart.c , stm32g4xx_hal_smartcard.c
  • USART_CR_MASK : stm32g4xx_hal_usart.h
  • USART_CR_POS : stm32g4xx_hal_usart.h
  • USART_DEFAULT_BAUDRATE : stm32g4xx_ll_usart.c
  • USART_DIV_SAMPLING8 : stm32g4xx_hal_usart.h
  • USART_DMAAbortOnError() : stm32g4xx_hal_usart.c
  • USART_DMAError() : stm32g4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32g4xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32g4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32g4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32g4xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32g4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32g4xx_hal_usart.c
  • USART_DUMMY_DATA : stm32g4xx_hal_usart.c
  • USART_EndTransfer() : stm32g4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32g4xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32g4xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32g4xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32g4xx_hal_usart.h
  • USART_FLAG_FE : stm32g4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32g4xx_hal_usart.h
  • USART_FLAG_NE : stm32g4xx_hal_usart.h
  • USART_FLAG_ORE : stm32g4xx_hal_usart.h
  • USART_FLAG_PE : stm32g4xx_hal_usart.h
  • USART_FLAG_REACK : stm32g4xx_hal_usart.h
  • USART_FLAG_RTOF : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFF : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFT : stm32g4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32g4xx_hal_usart.h
  • USART_FLAG_TC : stm32g4xx_hal_usart.h
  • USART_FLAG_TEACK : stm32g4xx_hal_usart.h
  • USART_FLAG_TXE : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFE : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFT : stm32g4xx_hal_usart.h
  • USART_FLAG_UDR : stm32g4xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32g4xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32g4xx_hal_usart.h
  • USART_HandleTypeDef : stm32g4xx_hal_usart.h
  • USART_InitCallbacksToDefault() : stm32g4xx_hal_usart.c
  • USART_ISR_MASK : stm32g4xx_hal_usart.h
  • USART_ISR_POS : stm32g4xx_hal_usart.h
  • USART_IT_ERR : stm32g4xx_hal_usart.h
  • USART_IT_FE : stm32g4xx_hal_usart.h
  • USART_IT_IDLE : stm32g4xx_hal_usart.h
  • USART_IT_MASK : stm32g4xx_hal_usart.h
  • USART_IT_NE : stm32g4xx_hal_usart.h
  • USART_IT_ORE : stm32g4xx_hal_usart.h
  • USART_IT_PE : stm32g4xx_hal_usart.h
  • USART_IT_RXFF : stm32g4xx_hal_usart.h
  • USART_IT_RXFNE : stm32g4xx_hal_usart.h
  • USART_IT_RXFT : stm32g4xx_hal_usart.h
  • USART_IT_RXNE : stm32g4xx_hal_usart.h
  • USART_IT_TC : stm32g4xx_hal_usart.h
  • USART_IT_TXE : stm32g4xx_hal_usart.h
  • USART_IT_TXFE : stm32g4xx_hal_usart.h
  • USART_IT_TXFNF : stm32g4xx_hal_usart.h
  • USART_IT_TXFT : stm32g4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32g4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32g4xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32g4xx_hal_usart_ex.h
  • USART_MODE_RX : stm32g4xx_hal_usart.h
  • USART_MODE_TX : stm32g4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32g4xx_hal_usart.h
  • USART_NSS_HARD : stm32g4xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32g4xx_hal_usart_ex.h
  • USART_PARITY_EVEN : stm32g4xx_hal_usart.h
  • USART_PARITY_NONE : stm32g4xx_hal_usart.h
  • USART_PARITY_ODD : stm32g4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32g4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32g4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32g4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_TAB : stm32g4xx_ll_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_usart_ex.h
  • USART_RxISR_16BIT() : stm32g4xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32g4xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_SetConfig() : stm32g4xx_hal_usart.c
  • USART_SLAVEMODE_DISABLE : stm32g4xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32g4xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32g4xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32g4xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_usart_ex.h
  • USART_TxISR_16BIT() : stm32g4xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32g4xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32g4xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32g4xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32g4xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32g4xx_hal_usart_ex.h
  • USARTEx_SetNbDataToProcess() : stm32g4xx_hal_usart_ex.c
  • USB_CNTRX_BLSIZE : stm32g4xx_hal_pcd.h
  • USB_CNTRX_NBLK_MSK : stm32g4xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32g4xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_CORDIC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_EXTI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_FMAC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_HRTIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_NAND_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_NOR_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_OPAMP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SRAM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_RTOS : stm32g4xx_hal_conf.h
  • USE_SPI_CRC : stm32g4xx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32g4xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32g4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32g4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32g4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32g4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32g4xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY5_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY5_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32g4xx_ll_utils.c
  • uwTick : stm32g4xx_hal.c , stm32g4xx_hal.h
  • uwTickFreq : stm32g4xx_hal.c , stm32g4xx_hal.h
  • uwTickPrio : stm32g4xx_hal.h , stm32g4xx_hal.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32g4xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32g4xx_hal.c
  • VREFINT_CAL_ADDR : stm32g4xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32g4xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32g4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32g4xx_hal_wwdg.h
  • WWDG_HandleTypeDef : stm32g4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- a -

  • ADC_ConversionStop() : stm32g4xx_hal_adc.c
  • ADC_Disable() : stm32g4xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32g4xx_hal_adc.c
  • ADC_DMAError() : stm32g4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32g4xx_hal_adc.c
  • ADC_Enable() : stm32g4xx_hal_adc.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- c -

  • CORDIC_DMAError() : stm32g4xx_hal_cordic.c
  • CORDIC_DMAInCplt() : stm32g4xx_hal_cordic.c
  • CORDIC_DMAOutCplt() : stm32g4xx_hal_cordic.c
  • CORDIC_ReadOutDataIncrementPtr() : stm32g4xx_hal_cordic.c
  • CORDIC_WriteInDataIncrementPtr() : stm32g4xx_hal_cordic.c
  • CRC_Handle_16() : stm32g4xx_hal_crc.c
  • CRC_Handle_8() : stm32g4xx_hal_crc.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- d -

  • DAC_DMAConvCpltCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32g4xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32g4xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32g4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32g4xx_hal_dac_ex.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32g4xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32g4xx_hal_dma.c
  • DMA_SetConfig() : stm32g4xx_hal_dma.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- f -

  • FDCAN_CalcultateRamBlockAddresses() : stm32g4xx_hal_fdcan.c
  • FDCAN_CopyMessageToRAM() : stm32g4xx_hal_fdcan.c
  • FLASH_FlushCaches() : stm32g4xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_BootLockConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetBootLock() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetSecMem() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_SecMemConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32g4xx_hal_flash_ex.c
  • FLASH_PageErase() : stm32g4xx_hal_flash_ex.c
  • FLASH_Program_DoubleWord() : stm32g4xx_hal_flash.c
  • FLASH_Program_Fast() : stm32g4xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32g4xx_hal_flash.c
  • FMAC_AppendFilterDataUpdateState() : stm32g4xx_hal_fmac.c
  • FMAC_ConfigFilterOutputBufferUpdateState() : stm32g4xx_hal_fmac.c
  • FMAC_DMAError() : stm32g4xx_hal_fmac.c
  • FMAC_DMAFilterConfig() : stm32g4xx_hal_fmac.c
  • FMAC_DMAFilterPreload() : stm32g4xx_hal_fmac.c
  • FMAC_DMAGetData() : stm32g4xx_hal_fmac.c
  • FMAC_DMAHalfGetData() : stm32g4xx_hal_fmac.c
  • FMAC_DMAHalfOutputDataReady() : stm32g4xx_hal_fmac.c
  • FMAC_DMAOutputDataReady() : stm32g4xx_hal_fmac.c
  • FMAC_FilterConfig() : stm32g4xx_hal_fmac.c
  • FMAC_FilterPreload() : stm32g4xx_hal_fmac.c
  • FMAC_ReadDataIncrementPtr() : stm32g4xx_hal_fmac.c
  • FMAC_Reset() : stm32g4xx_hal_fmac.c
  • FMAC_ResetDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_ResetInputStateAndDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_ResetOutputStateAndDataPointers() : stm32g4xx_hal_fmac.c
  • FMAC_WaitOnStartUntilTimeout() : stm32g4xx_hal_fmac.c
  • FMAC_WriteDataIncrementPtr() : stm32g4xx_hal_fmac.c
  • FMAC_WritePreloadDataIncrementPtr() : stm32g4xx_hal_fmac.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32g4xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32g4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32g4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32g4xx_hal_adc.c
  • HAL_ADC_Init() : stm32g4xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32g4xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32g4xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32g4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32g4xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32g4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32g4xx_hal_adc.c
  • HAL_ADC_StartSampling() : stm32g4xx_hal_adc.c
  • HAL_ADC_Stop() : stm32g4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32g4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32g4xx_hal_adc.c
  • HAL_ADC_StopSampling() : stm32g4xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32g4xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32g4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32g4xx_hal_adc_ex.c
  • HAL_COMP_DeInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_GetError() : stm32g4xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32g4xx_hal_comp.c
  • HAL_COMP_GetState() : stm32g4xx_hal_comp.c
  • HAL_COMP_Init() : stm32g4xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32g4xx_hal_comp.c
  • HAL_COMP_Lock() : stm32g4xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32g4xx_hal_comp.c
  • HAL_COMP_RegisterCallback() : stm32g4xx_hal_comp.c
  • HAL_COMP_Start() : stm32g4xx_hal_comp.c
  • HAL_COMP_Stop() : stm32g4xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32g4xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32g4xx_hal_comp.c
  • HAL_CORDIC_Calculate() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Calculate_DMA() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Calculate_IT() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CalculateCpltCallback() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_CalculateZO() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Configure() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_DeInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_ErrorCallback() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_GetError() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_GetState() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_Init() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_IRQHandler() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_MspDeInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_MspInit() : stm32g4xx_hal_cordic.c
  • HAL_CORDIC_RegisterCallback() : stm32g4xx_hal_cordic.c , stm32g4xx_hal_cordic.h
  • HAL_CORDIC_UnRegisterCallback() : stm32g4xx_hal_cordic.c
  • HAL_CRC_Accumulate() : stm32g4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32g4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32g4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32g4xx_hal_crc.c
  • HAL_CRC_Init() : stm32g4xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32g4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32g4xx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32g4xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32g4xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32g4xx_hal_crc_ex.c
  • HAL_DAC_ConfigChannel() : stm32g4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetError() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32g4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32g4xx_hal_dac.c
  • HAL_DAC_Init() : stm32g4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32g4xx_hal_dac.c
  • HAL_DAC_MspDeInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32g4xx_hal_dac.c
  • HAL_DAC_RegisterCallback() : stm32g4xx_hal_dac.c , stm32g4xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32g4xx_hal_dac.c
  • HAL_DAC_Start() : stm32g4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32g4xx_hal_dac.c
  • HAL_DAC_Stop() : stm32g4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32g4xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32g4xx_hal_dac.c , stm32g4xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStart_DMA() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_DualStop_DMA() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveDataReset() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveDataStep() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SawtoothWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32g4xx_hal_dac_ex.c , stm32g4xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32g4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32g4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32g4xx_hal.c
  • HAL_DeInit() : stm32g4xx_hal.c
  • HAL_Delay() : stm32g4xx_hal.c
  • HAL_DMA_Abort() : stm32g4xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32g4xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32g4xx_hal_dma.c
  • HAL_DMA_GetError() : stm32g4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32g4xx_hal_dma.c
  • HAL_DMA_Init() : stm32g4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32g4xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32g4xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32g4xx_hal_dma.c
  • HAL_DMA_Start() : stm32g4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32g4xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32g4xx_hal_dma.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32g4xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32g4xx_hal_dma_ex.c
  • HAL_EXTI_ClearConfigLine() : stm32g4xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GenerateSWI() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32g4xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32g4xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32g4xx_hal_exti.c
  • HAL_EXTI_RegisterCallback() : stm32g4xx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32g4xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ErrorCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_MspDeInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_MspInit() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterCallback() : stm32g4xx_hal_fdcan.c , stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_Stop() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32g4xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32g4xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32g4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32g4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32g4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32g4xx_hal_flash.c
  • HAL_FLASHEx_DisableDebugger() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_DisableRunPowerDown() : stm32g4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableDebugger() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableRunPowerDown() : stm32g4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableSecMemProtection() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32g4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32g4xx_hal_flash_ex.c
  • HAL_FMAC_AppendFilterData() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_ConfigFilterOutputBuffer() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_DeInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_ErrorCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterConfig() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterConfig_DMA() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterConfigCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreload() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreload_DMA() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterPreloadCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterStart() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_FilterStop() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GetDataCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GetError() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_GetState() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_HalfGetDataCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_HalfOutputDataReadyCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_Init() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_IRQHandler() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_MspDeInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_MspInit() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_OutputDataReadyCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_PollFilterData() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_RegisterCallback() : stm32g4xx_hal_fmac.c
  • HAL_FMAC_UnRegisterCallback() : stm32g4xx_hal_fmac.c
  • HAL_GetDEVID() : stm32g4xx_hal.c
  • HAL_GetHalVersion() : stm32g4xx_hal.c
  • HAL_GetREVID() : stm32g4xx_hal.c
  • HAL_GetTick() : stm32g4xx_hal.c
  • HAL_GetTickFreq() : stm32g4xx_hal.c
  • HAL_GetTickPrio() : stm32g4xx_hal.c
  • HAL_GetUIDw0() : stm32g4xx_hal.c
  • HAL_GetUIDw1() : stm32g4xx_hal.c
  • HAL_GetUIDw2() : stm32g4xx_hal.c
  • HAL_GPIO_DeInit() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32g4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32g4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32g4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32g4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32g4xx_hal_uart.c
  • HAL_I2C_AbortCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32g4xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32g4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32g4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32g4xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_RegisterAddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32g4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32g4xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_UnRegisterAddrCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32g4xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32g4xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32g4xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32g4xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32g4xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Init() : stm32g4xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32g4xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32g4xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32g4xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32g4xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32g4xx_hal_i2s.c
  • HAL_IncTick() : stm32g4xx_hal.c
  • HAL_Init() : stm32g4xx_hal.c
  • HAL_InitTick() : stm32g4xx_hal.c
  • HAL_IRDA_Abort() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32g4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32g4xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32g4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32g4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32g4xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32g4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32g4xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32g4xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32g4xx_hal_irda.c
  • HAL_IWDG_Init() : stm32g4xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32g4xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32g4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32g4xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_CompareMatchCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DirectionDownCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_MspDeInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_MspInit() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_TriggerCallback() : stm32g4xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32g4xx_hal_lptim.c
  • HAL_MPU_ConfigRegion() : stm32g4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32g4xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32g4xx_hal_cortex.c
  • HAL_MspDeInit() : stm32g4xx_hal.c
  • HAL_MspInit() : stm32g4xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32g4xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32g4xx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32g4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32g4xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_LockTimerMux() : stm32g4xx_hal_opamp.c , stm32g4xx_hal_opamp.h
  • HAL_OPAMP_MspDeInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_RegisterCallback() : stm32g4xx_hal_opamp.c , stm32g4xx_hal_opamp.h
  • HAL_OPAMP_SelfCalibrate() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_Stop() : stm32g4xx_hal_opamp.c
  • HAL_OPAMP_UnRegisterCallback() : stm32g4xx_hal_opamp.h , stm32g4xx_hal_opamp.c
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32g4xx_hal_opamp_ex.c , stm32g4xx_hal_opamp_ex.h
  • HAL_PCD_ActivateRemoteWakeup() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32g4xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Abort() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_DB_Receive() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_DB_Transmit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32g4xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32g4xx_hal_pcd.c
  • HAL_PCD_Init() : stm32g4xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterBcdCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_Start() : stm32g4xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32g4xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32g4xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32g4xx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32g4xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32g4xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32g4xx_hal_pwr.c
  • HAL_PWREx_ConfigPVM() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM2() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM4() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAM2ContentRetention() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUCPDDeadBattery() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableUCPDStandbyMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM2() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM4() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAM2ContentRetention() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUCPDDeadBattery() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableUCPDStandbyMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM2Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM4Callback() : stm32g4xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32g4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32g4xx_hal_rcc.c
  • HAL_RCC_DisableLSECSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_EnableLSECSS() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32g4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32g4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32g4xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32g4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32g4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32g4xx_hal.c
  • HAL_RNG_DeInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32g4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32g4xx_hal_rng.c
  • HAL_RNG_GetError() : stm32g4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32g4xx_hal_rng.c
  • HAL_RNG_Init() : stm32g4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32g4xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32g4xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32g4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_UnRegisterCallback() : stm32g4xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32g4xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32g4xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32g4xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_DST_Add1Hour() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_ClearStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_ReadStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_SetStoreOperation() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_DST_Sub1Hour() : stm32g4xx_hal_rtc.c , stm32g4xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32g4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32g4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32g4xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32g4xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32g4xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32g4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32g4xx_hal_rtc.c
  • HAL_RTC_UnRegisterCallback() : stm32g4xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32g4xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamperEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32g4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32g4xx_hal_rtc_ex.c
  • HAL_SAI_Abort() : stm32g4xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32g4xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32g4xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32g4xx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_GetError() : stm32g4xx_hal_sai.c
  • HAL_SAI_GetState() : stm32g4xx_hal_sai.c
  • HAL_SAI_Init() : stm32g4xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32g4xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32g4xx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32g4xx_hal_sai.c
  • HAL_SAI_Receive() : stm32g4xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32g4xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32g4xx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_Transmit() : stm32g4xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32g4xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32g4xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32g4xx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32g4xx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32g4xx_hal_sai_ex.c
  • HAL_SetTickFreq() : stm32g4xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32g4xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32g4xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_EnableAlert_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_Master_Receive_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Master_Transmit_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_RegisterAddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32g4xx_hal_smbus.h , stm32g4xx_hal_smbus.c
  • HAL_SMBUS_Slave_Transmit_IT() : stm32g4xx_hal_smbus.c , stm32g4xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32g4xx_hal_smbus.c
  • HAL_SMBUSEx_DisableFastModePlus() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_DisableWakeUp() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableFastModePlus() : stm32g4xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableWakeUp() : stm32g4xx_hal_smbus_ex.c
  • HAL_SPI_Abort() : stm32g4xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32g4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32g4xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32g4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32g4xx_hal_spi.c
  • HAL_SPI_Init() : stm32g4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32g4xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32g4xx_hal_spi.c
  • HAL_SPI_Receive() : stm32g4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32g4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32g4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32g4xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32g4xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32g4xx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32g4xx_hal.c
  • HAL_SYSCFG_CCMSRAM_WriteProtectionEnable() : stm32g4xx_hal.c
  • HAL_SYSCFG_CCMSRAMErase() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableIOSwitchBooster() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableIOSwitchVDD() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableMemorySwappingBank() : stm32g4xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableIOSwitchBooster() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableIOSwitchVDD() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableMemorySwappingBank() : stm32g4xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32g4xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32g4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32g4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32g4xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32g4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32g4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32g4xx_hal_tim.c
  • HAL_TIM_DMABurstState() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32g4xx_hal_tim.c
  • HAL_TIM_GetActiveChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_GetChannelState() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32g4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32g4xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32g4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32g4xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32g4xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32g4xx_hal_tim.c
  • HAL_TIMEx_Break2Callback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DirectionChangeCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableDeadTimePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableEncoderFirstIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisableSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DisarmBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DitheringDisable() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_DitheringEnable() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableAsymmetricalDeadTime() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableDeadTimePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableEncoderFirstIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableEncoderIndex() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EnableSlaveModePreload() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_EncoderIndexCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_GetChannelNState() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_IndexErrorCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OC_ConfigPulseOnCompare() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_ReArmBreakInput() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32g4xx_hal_tim_ex.c
  • HAL_TIMEx_TransitionErrorCallback() : stm32g4xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32g4xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_DeInit() : stm32g4xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32g4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32g4xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32g4xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_GetError() : stm32g4xx_hal_uart.c
  • HAL_UART_GetState() : stm32g4xx_hal_uart.c
  • HAL_UART_Init() : stm32g4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32g4xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32g4xx_hal_uart.c
  • HAL_UART_MspInit() : stm32g4xx_hal_uart.c
  • HAL_UART_Receive() : stm32g4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32g4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32g4xx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RegisterRxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_Transmit() : stm32g4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32g4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32g4xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32g4xx_hal_uart.c
  • HAL_UART_UnRegisterRxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UARTEx_DisableFifoMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_GetRxEventType() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_DMA() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_IT() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_RxEventCallback() : stm32g4xx_hal_uart.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32g4xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32g4xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_DeInit() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32g4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32g4xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_GetError() : stm32g4xx_hal_usart.c
  • HAL_USART_GetState() : stm32g4xx_hal_usart.c
  • HAL_USART_Init() : stm32g4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32g4xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32g4xx_hal_usart.c
  • HAL_USART_MspInit() : stm32g4xx_hal_usart.c
  • HAL_USART_Receive() : stm32g4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_Transmit() : stm32g4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32g4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32g4xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32g4xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32g4xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32g4xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32g4xx_hal_usart_ex.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32g4xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32g4xx_hal_wwdg.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- i -

  • I2C_ConvertOtherXferOptions() : stm32g4xx_hal_i2c.c
  • I2C_Disable_IRQ() : stm32g4xx_hal_i2c.c
  • I2C_DMAAbort() : stm32g4xx_hal_i2c.c
  • I2C_DMAError() : stm32g4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32g4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32g4xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32g4xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32g4xx_hal_i2c.c
  • I2C_IsErrorOccurred() : stm32g4xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITError() : stm32g4xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32g4xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32g4xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_Mem_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Mem_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32g4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32g4xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32g4xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32g4xx_hal_i2c.c
  • I2C_TransferConfig() : stm32g4xx_hal_i2c.c
  • I2C_TreatErrorCallback() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32g4xx_hal_i2c.c
  • I2S_DMAError() : stm32g4xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32g4xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32g4xx_hal_i2s.c
  • I2S_Receive_IT() : stm32g4xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32g4xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32g4xx_hal_i2s.c
  • IC1Config() : stm32g4xx_ll_tim.c
  • IC2Config() : stm32g4xx_ll_tim.c
  • IC3Config() : stm32g4xx_ll_tim.c
  • IC4Config() : stm32g4xx_ll_tim.c
  • IRDA_CheckIdleState() : stm32g4xx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32g4xx_hal_irda.c
  • IRDA_DMAError() : stm32g4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32g4xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32g4xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32g4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32g4xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32g4xx_hal_irda.c
  • IRDA_InitCallbacksToDefault() : stm32g4xx_hal_irda.c
  • IRDA_Receive_IT() : stm32g4xx_hal_irda.c
  • IRDA_SetConfig() : stm32g4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32g4xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32g4xx_hal_irda.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- l -

  • LL_ADC_ClearFlag_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32g4xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32g4xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32g4xx_ll_adc.h
  • LL_ADC_DeInit() : stm32g4xx_ll_adc.c
  • LL_ADC_Disable() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32g4xx_ll_adc.h
  • LL_ADC_Enable() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32g4xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_GetAWDFilteringConfiguration() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32g4xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32g4xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32g4xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32g4xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32g4xx_ll_adc.h
  • LL_ADC_GetGainCompensation() : stm32g4xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32g4xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetSaturation() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetSign() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32g4xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32g4xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32g4xx_ll_adc.h
  • LL_ADC_GetSamplingTimeCommonConfig() : stm32g4xx_ll_adc.h
  • LL_ADC_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32g4xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32g4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32g4xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSamplingMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32g4xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSamplingMode() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StartSamplingPhase() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StopSamplingPhase() : stm32g4xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32g4xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32g4xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32g4xx_ll_adc.h
  • LL_ADC_SetAWDFilteringConfiguration() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32g4xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32g4xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChAdd() : stm32g4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChRem() : stm32g4xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32g4xx_ll_adc.h
  • LL_ADC_SetGainCompensation() : stm32g4xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32g4xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetSaturation() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetSign() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32g4xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32g4xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32g4xx_ll_adc.h
  • LL_ADC_SetSamplingTimeCommonConfig() : stm32g4xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32g4xx_ll_adc.h
  • LL_ADC_StructInit() : stm32g4xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32g4xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32g4xx_ll_comp.h
  • LL_COMP_DeInit() : stm32g4xx_ll_comp.c
  • LL_COMP_Disable() : stm32g4xx_ll_comp.h
  • LL_COMP_Enable() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32g4xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32g4xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32g4xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32g4xx_ll_comp.h
  • LL_COMP_Init() : stm32g4xx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32g4xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32g4xx_ll_comp.h
  • LL_COMP_Lock() : stm32g4xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32g4xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32g4xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32g4xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32g4xx_ll_comp.h
  • LL_COMP_StructInit() : stm32g4xx_ll_comp.c
  • LL_CORDIC_Config() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DeInit() : stm32g4xx_ll_cordic.c
  • LL_CORDIC_DisableDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DisableDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DisableIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DMA_GetRegAddr() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_EnableIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetFunction() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetInSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetNbRead() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetNbWrite() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetOutSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetPrecision() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_GetScale() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsActiveFlag_RRDY() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledDMAReq_RD() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledDMAReq_WR() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IsEnabledIT() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_ReadData() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetFunction() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetInSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetNbRead() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetNbWrite() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetOutSize() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetPrecision() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SetScale() : stm32g4xx_ll_cordic.h
  • LL_CORDIC_WriteData() : stm32g4xx_ll_cordic.h
  • LL_CPUID_GetArchitecture() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32g4xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32g4xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32g4xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32g4xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32g4xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32g4xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32g4xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32g4xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32g4xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32g4xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32g4xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32g4xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32g4xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32g4xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32g4xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32g4xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32g4xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32g4xx_ll_crs.h
  • LL_CRS_DeInit() : stm32g4xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32g4xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32g4xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32g4xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32g4xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32g4xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32g4xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32g4xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32g4xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32g4xx_ll_crs.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32g4xx_ll_dac.h
  • LL_DAC_DeInit() : stm32g4xx_ll_dac.c
  • LL_DAC_Disable() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableDMADoubleDataMode() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32g4xx_ll_dac.h
  • LL_DAC_Enable() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableDMADoubleDataMode() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32g4xx_ll_dac.h
  • LL_DAC_GetHighFrequencyMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32g4xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32g4xx_ll_dac.h
  • LL_DAC_GetSignedFormat() : stm32g4xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothPolarity() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothResetData() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothResetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothStepData() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveSawtoothStepTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32g4xx_ll_dac.h
  • LL_DAC_Init() : stm32g4xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DAC1RDY() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DAC2RDY() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DORSTAT1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DORSTAT2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsDMADoubleDataModeEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32g4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32g4xx_ll_dac.h
  • LL_DAC_IsReady() : stm32g4xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32g4xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32g4xx_ll_dac.h
  • LL_DAC_SetHighFrequencyMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32g4xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32g4xx_ll_dac.h
  • LL_DAC_SetSignedFormat() : stm32g4xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothPolarity() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothResetData() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothResetTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothStepData() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveSawtoothStepTriggerSource() : stm32g4xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32g4xx_ll_dac.h
  • LL_DAC_StructInit() : stm32g4xx_ll_dac.c
  • LL_DAC_TrigSWConversion() : stm32g4xx_ll_dac.h
  • LL_DAC_TrigSWConversion2() : stm32g4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32g4xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32g4xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32g4xx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32g4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32g4xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32g4xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32g4xx_ll_dma.h
  • LL_DMA_DeInit() : stm32g4xx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32g4xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32g4xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32g4xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32g4xx_ll_dma.h
  • LL_DMA_GetMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32g4xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32g4xx_ll_dma.h
  • LL_DMA_Init() : stm32g4xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32g4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32g4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32g4xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32g4xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32g4xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32g4xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32g4xx_ll_dma.h
  • LL_DMA_SetMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32g4xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32g4xx_ll_dma.h
  • LL_DMA_StructInit() : stm32g4xx_ll_dma.c
  • LL_DMAMUX_ClearFlag_RGO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32g4xx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32g4xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_Init() : stm32g4xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32g4xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32g4xx_ll_exti.c
  • LL_FLASH_DisableDataCache() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableRunPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_DisableSleepPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32g4xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableRunPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_EnableSleepPowerDown() : stm32g4xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32g4xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32g4xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32g4xx_ll_system.h
  • LL_FMAC_ConfigFunc() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigX1() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigX2() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ConfigY() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DeInit() : stm32g4xx_ll_fmac.c
  • LL_FMAC_DisableClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_DisableStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableReset() : stm32g4xx_ll_fmac.h
  • LL_FMAC_EnableStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetFunction() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamP() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamQ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetParamR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX1FullWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX2Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetX2BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYBase() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYBufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_GetYEmptyWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_Init() : stm32g4xx_ll_fmac.c
  • LL_FMAC_IsActiveFlag_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_X1FULL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsActiveFlag_YEMPTY() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledClipping() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledDMAReq_READ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledDMAReq_WRITE() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_OVFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_RD() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_SAT() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_UNFL() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledIT_WR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledReset() : stm32g4xx_ll_fmac.h
  • LL_FMAC_IsEnabledStart() : stm32g4xx_ll_fmac.h
  • LL_FMAC_ReadData() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetFunction() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamP() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamQ() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetParamR() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX1FullWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX2Base() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetX2BufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYBase() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYBufferSize() : stm32g4xx_ll_fmac.h
  • LL_FMAC_SetYEmptyWatermark() : stm32g4xx_ll_fmac.h
  • LL_FMAC_WriteData() : stm32g4xx_ll_fmac.h
  • LL_GetFlashSize() : stm32g4xx_ll_utils.h
  • LL_GetPackageType() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word0() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word1() : stm32g4xx_ll_utils.h
  • LL_GetUID_Word2() : stm32g4xx_ll_utils.h
  • LL_GPIO_DeInit() : stm32g4xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32g4xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32g4xx_ll_gpio.h
  • LL_GPIO_Init() : stm32g4xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32g4xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32g4xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32g4xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32g4xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32g4xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32g4xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32g4xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32g4xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32g4xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32g4xx_ll_cortex.h
  • LL_I2C_AcknowledgeNextData() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32g4xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32g4xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32g4xx_ll_i2c.c
  • LL_I2C_Disable() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_Enable() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32g4xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32g4xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32g4xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32g4xx_ll_i2c.h
  • LL_I2C_Init() : stm32g4xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32g4xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32g4xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32g4xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32g4xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32g4xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32g4xx_ll_i2c.h
  • LL_I2S_ClearFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32g4xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32g4xx_ll_spi.c
  • LL_I2S_DeInit() : stm32g4xx_ll_spi.c
  • LL_I2S_Disable() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_Enable() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32g4xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32g4xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32g4xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32g4xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32g4xx_ll_spi.h
  • LL_I2S_Init() : stm32g4xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledAsyncStart() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32g4xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32g4xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32g4xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32g4xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32g4xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32g4xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32g4xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32g4xx_ll_spi.h
  • LL_I2S_StructInit() : stm32g4xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32g4xx_ll_spi.h
  • LL_Init1msTick() : stm32g4xx_ll_utils.c
  • LL_InitTick() : stm32g4xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32g4xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32g4xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32g4xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32g4xx_ll_cortex.h
  • LL_LPTIM_ClearFlag_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32g4xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32g4xx_ll_lptim.c
  • LL_LPTIM_TrigSw() : stm32g4xx_ll_lptim.h
  • LL_LPUART_ClearFlag_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_Disable() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32g4xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32g4xx_ll_lpuart.h
  • LL_mDelay() : stm32g4xx_ll_utils.c
  • LL_MPU_ConfigRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_Disable() : stm32g4xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_Enable() : stm32g4xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32g4xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32g4xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32g4xx_ll_opamp.c
  • LL_OPAMP_Disable() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInputsMuxMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetInternalOutput() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32g4xx_ll_opamp.c
  • LL_OPAMP_IsCalibrationOutputSet() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsLocked() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_IsTimerMuxLocked() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_Lock() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_LockTimerMux() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInvertingSecondary() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInputsMuxMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetInternalOutput() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32g4xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32g4xx_ll_opamp.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32g4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32g4xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32g4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32g4xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32g4xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32g4xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO2() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO4() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledRange1BoostMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUCPDDeadBattery() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUCPDStandbyMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32g4xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32g4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32g4xx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32g4xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32g4xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32g4xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetI2SClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetI2SClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32g4xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32g4xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_48M() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_ADC() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_SYS() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32g4xx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetI2SClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32g4xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32g4xx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_DeInit() : stm32g4xx_ll_rng.c
  • LL_RNG_Disable() : stm32g4xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32g4xx_ll_rng.h
  • LL_RNG_Enable() : stm32g4xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32g4xx_ll_rng.h
  • LL_RNG_Init() : stm32g4xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32g4xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32g4xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32g4xx_ll_rng.h
  • LL_RNG_StructInit() : stm32g4xx_ll_rng.c
  • LL_RTC_ALMA_ConfigTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_BKP_GetRegister() : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_SetRegister() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32g4xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32g4xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32g4xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32g4xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32g4xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32g4xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32g4xx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32g4xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP4() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP5() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP6() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32g4xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32g4xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_TAMPER_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32g4xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32g4xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32g4xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32g4xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32g4xx_ll_rtc.h
  • LL_SetFlashLatency() : stm32g4xx_ll_utils.c
  • LL_SetSystemCoreClock() : stm32g4xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32g4xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_SPI_DeInit() : stm32g4xx_ll_spi.c
  • LL_SPI_Disable() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32g4xx_ll_spi.h
  • LL_SPI_Enable() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32g4xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32g4xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32g4xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32g4xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_GetMode() : stm32g4xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32g4xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32g4xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32g4xx_ll_spi.h
  • LL_SPI_Init() : stm32g4xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32g4xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32g4xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32g4xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32g4xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32g4xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32g4xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32g4xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32g4xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32g4xx_ll_spi.h
  • LL_SPI_SetMode() : stm32g4xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32g4xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32g4xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32g4xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32g4xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32g4xx_ll_spi.h
  • LL_SPI_StructInit() : stm32g4xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32g4xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32g4xx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableCCMSRAMErase() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableCCMSRAMPageWRP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetFlashBankMode() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32g4xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsCCMSRAMEraseOngoing() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32g4xx_ll_system.h
  • LL_SYSCFG_LockCCMSRAMWRP() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetFlashBankMode() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32g4xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32g4xx_ll_system.h
  • LL_SYSCFG_UnlockCCMSRAMWRP() : stm32g4xx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32g4xx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32g4xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32g4xx_ll_tim.h
  • LL_TIM_ConfigIDX() : stm32g4xx_ll_tim.h
  • LL_TIM_DeInit() : stm32g4xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_DisarmBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_DisarmBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32g4xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32g4xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32g4xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_GetFallingDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_GetIndexDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_GetIndexPositionning() : stm32g4xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32g4xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_GetSMSPreloadSource() : stm32g4xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32g4xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsActiveUIFCPY() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAsymmetricalDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDeadTimePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDithering() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledEncoderIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledFirstIndex() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledHSE32() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_DIR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_IDX() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_IERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TERR() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledSMSPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPulseWidth() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_GetPulseWidthPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32g4xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPulseWidth() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_SetPulseWidthPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32g4xx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32g4xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32g4xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32g4xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetFallingDeadTime() : stm32g4xx_ll_tim.h
  • LL_TIM_SetIndexDirection() : stm32g4xx_ll_tim.h
  • LL_TIM_SetIndexPositionning() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32g4xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32g4xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32g4xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32g4xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32g4xx_ll_tim.h
  • LL_TIM_SetSMSPreloadSource() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32g4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32g4xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32g4xx_ll_tim.h
  • LL_TIM_StructInit() : stm32g4xx_ll_tim.c
  • LL_UCPD_ClearFlag_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DeInit() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ForceClockDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ForceClockEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_Init() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_IsActiveFlag_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabled() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabledRxDMA() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnabledTxDMA() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_FRS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxHRST() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxMsgEnd() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxNE() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOvr() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxIS() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGABT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGDISC() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGSENT() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxUND() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadData() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadRxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadRxPaySize() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDMADisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxDMAEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxFilterDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RxFilterEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SendHardReset() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SendMessage() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetccEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetCCPin() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetHbitClockDiv() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetIfrGap() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetPSCClk() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRpResistor() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxMode() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt1() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt2() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetSNKRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetSRCRole() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetTransWin() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SetTxMode() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SignalFRSTX() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_StructInit() : stm32g4xx_ll_ucpd.c
  • LL_UCPD_TxDMADisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TxDMAEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Disable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Enable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WakeUpDisable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WakeUpEnable() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteData() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteTxOrderSet() : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteTxPaySize() : stm32g4xx_ll_ucpd.h
  • LL_USART_ClearFlag_CM() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32g4xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_ClockInit() : stm32g4xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32g4xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32g4xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32g4xx_ll_usart.h
  • LL_USART_DeInit() : stm32g4xx_ll_usart.c
  • LL_USART_Disable() : stm32g4xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32g4xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32g4xx_ll_usart.h
  • LL_USART_Enable() : stm32g4xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32g4xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32g4xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32g4xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32g4xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32g4xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32g4xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32g4xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32g4xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32g4xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32g4xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32g4xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32g4xx_ll_usart.h
  • LL_USART_GetParity() : stm32g4xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32g4xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32g4xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32g4xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32g4xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32g4xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32g4xx_ll_usart.h
  • LL_USART_Init() : stm32g4xx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32g4xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32g4xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32g4xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32g4xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32g4xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32g4xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32g4xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32g4xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32g4xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32g4xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32g4xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32g4xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32g4xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32g4xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32g4xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32g4xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32g4xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32g4xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32g4xx_ll_usart.h
  • LL_USART_SetParity() : stm32g4xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32g4xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32g4xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32g4xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32g4xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32g4xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32g4xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32g4xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32g4xx_ll_usart.h
  • LL_USART_StructInit() : stm32g4xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32g4xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32g4xx_ll_usart.h
  • LL_VREFBUF_Disable() : stm32g4xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32g4xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32g4xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32g4xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32g4xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32g4xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32g4xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32g4xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32g4xx_ll_system.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32g4xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32g4xx_ll_wwdg.h
  • LPTIM_Disable() : stm32g4xx_hal_lptim.c
  • LPTIM_ResetCallback() : stm32g4xx_hal_lptim.c
  • LPTIM_WaitForFlag() : stm32g4xx_hal_lptim.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- o -

  • OC1Config() : stm32g4xx_ll_tim.c
  • OC2Config() : stm32g4xx_ll_tim.c
  • OC3Config() : stm32g4xx_ll_tim.c
  • OC4Config() : stm32g4xx_ll_tim.c
  • OC5Config() : stm32g4xx_ll_tim.c
  • OC6Config() : stm32g4xx_ll_tim.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- p -

  • PCD_EP_ISR_Handler() : stm32g4xx_hal_pcd.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- r -

  • RCC_GetHCLKClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_GetSysClockFreqFromPLLSource() : stm32g4xx_hal_rcc.c
  • RCC_GetSystemClockFreq() : stm32g4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_48M() : stm32g4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_ADC() : stm32g4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32g4xx_ll_rcc.c
  • RTC_Bcd2ToByte() : stm32g4xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32g4xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32g4xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32g4xx_hal_rtc.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- s -

  • SAI_Disable() : stm32g4xx_hal_sai.c
  • SAI_DMAAbort() : stm32g4xx_hal_sai.c
  • SAI_DMAError() : stm32g4xx_hal_sai.c
  • SAI_DMARxCplt() : stm32g4xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32g4xx_hal_sai.c
  • SAI_DMATxCplt() : stm32g4xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32g4xx_hal_sai.c
  • SAI_FillFifo() : stm32g4xx_hal_sai.c
  • SAI_InitI2S() : stm32g4xx_hal_sai.c
  • SAI_InitPCM() : stm32g4xx_hal_sai.c
  • SAI_InterruptFlag() : stm32g4xx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32g4xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32g4xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32g4xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32g4xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32g4xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32g4xx_hal_sai.c
  • SMARTCARD_AdvFeatureConfig() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_InitCallbacksToDefault() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_RxISR() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_TxISR() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32g4xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32g4xx_hal_smartcard.c
  • SMARTCARDEx_SetNbDataToProcess() : stm32g4xx_hal_smartcard_ex.c
  • SMBUS_ConvertOtherXferOptions() : stm32g4xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32g4xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32g4xx_hal_smbus.c
  • SMBUS_Flush_TXDR() : stm32g4xx_hal_smbus.c
  • SMBUS_ITErrorHandler() : stm32g4xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32g4xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32g4xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32g4xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32g4xx_hal_smbus.c
  • SPI_2linesRxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32g4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32g4xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32g4xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32g4xx_hal_spi.c
  • SPI_DMAError() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32g4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32g4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32g4xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32g4xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32g4xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32g4xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32g4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32g4xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32g4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32g4xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32g4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32g4xx_hal_spi.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- t -

  • TIM_Base_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32g4xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32g4xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32g4xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMADelayPulseNCplt() : stm32g4xx_hal_tim_ex.c
  • TIM_DMAError() : stm32g4xx_hal_tim.c
  • TIM_DMAErrorCCxN() : stm32g4xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32g4xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32g4xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32g4xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_ResetCallback() : stm32g4xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32g4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32g4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32g4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32g4xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32g4xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32g4xx_hal_tim_ex.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- u -

  • UART_AdvFeatureConfig() : stm32g4xx_hal_uart.c
  • UART_CheckIdleState() : stm32g4xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32g4xx_hal_uart.c
  • UART_DMAError() : stm32g4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32g4xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32g4xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32g4xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32g4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32g4xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32g4xx_hal_uart.c
  • UART_EndRxTransfer() : stm32g4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32g4xx_hal_uart.c
  • UART_EndTxTransfer() : stm32g4xx_hal_uart.c
  • UART_InitCallbacksToDefault() : stm32g4xx_hal_uart.c
  • UART_RxISR_16BIT() : stm32g4xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32g4xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_SetConfig() : stm32g4xx_hal_uart.c
  • UART_Start_Receive_DMA() : stm32g4xx_hal_uart.c
  • UART_Start_Receive_IT() : stm32g4xx_hal_uart.c
  • UART_TxISR_16BIT() : stm32g4xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32g4xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32g4xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32g4xx_hal_uart.c
  • UARTEx_SetNbDataToProcess() : stm32g4xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32g4xx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32g4xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32g4xx_hal_usart.c
  • USART_DMAError() : stm32g4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32g4xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32g4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32g4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32g4xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32g4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32g4xx_hal_usart.c
  • USART_EndTransfer() : stm32g4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32g4xx_hal_usart.c
  • USART_InitCallbacksToDefault() : stm32g4xx_hal_usart.c
  • USART_RxISR_16BIT() : stm32g4xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32g4xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_SetConfig() : stm32g4xx_hal_usart.c
  • USART_TxISR_16BIT() : stm32g4xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32g4xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32g4xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32g4xx_hal_usart.c
  • USARTEx_SetNbDataToProcess() : stm32g4xx_hal_usart_ex.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32g4xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32g4xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32g4xx_ll_utils.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • CHANNEL_OFFSET_TAB : stm32g4xx_ll_dma.h
  • DLCtoBytes : stm32g4xx_hal_fdcan.c
  • hopamp2 : stm32g4xx_hal_opamp_ex.c
  • LPUART_PRESCALER_TAB : stm32g4xx_ll_lpuart.h
  • OFFSET_TAB_CCMRx : stm32g4xx_ll_tim.h
  • pFlash : stm32g4xx_hal_flash.c , stm32g4xx_hal_flash.h
  • SHIFT_TAB_CCxP : stm32g4xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32g4xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32g4xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32g4xx_ll_tim.h
  • UARTPrescTable : stm32g4xx_hal_uart.c , stm32g4xx_hal_uart.h
  • USART_PRESCALER_TAB : stm32g4xx_ll_usart.h
  • uwTick : stm32g4xx_hal.c , stm32g4xx_hal.h
  • uwTickFreq : stm32g4xx_hal.h , stm32g4xx_hal.c
  • uwTickPrio : stm32g4xx_hal.h , stm32g4xx_hal.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u
  • w

- a -

  • ADC_HandleTypeDef : stm32g4xx_hal_adc.h

- c -

  • COMP_HandleTypeDef : stm32g4xx_hal_comp.h
  • CORDIC_HandleTypeDef : stm32g4xx_hal_cordic.h

- d -

  • DAC_HandleTypeDef : stm32g4xx_hal_dac.h
  • DMA_HandleTypeDef : stm32g4xx_hal_dma.h

- f -

  • FDCAN_HandleTypeDef : stm32g4xx_hal_fdcan.h
  • FMAC_HandleTypeDef : stm32g4xx_hal_fmac.h

- h -

  • HAL_IRDA_StateTypeDef : stm32g4xx_hal_irda.h
  • HAL_SMARTCARD_StateTypeDef : stm32g4xx_hal_smartcard.h
  • HAL_UART_RxEventTypeTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_RxTypeTypeDef : stm32g4xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32g4xx_hal_uart.h

- i -

  • I2C_HandleTypeDef : stm32g4xx_hal_i2c.h
  • I2S_HandleTypeDef : stm32g4xx_hal_i2s.h
  • IRDA_HandleTypeDef : stm32g4xx_hal_irda.h

- l -

  • LPTIM_HandleTypeDef : stm32g4xx_hal_lptim.h

- o -

  • OPAMP_HandleTypeDef : stm32g4xx_hal_opamp.h
  • OPAMP_TrimmingValueTypeDef : stm32g4xx_hal_opamp.h

- p -

  • pADC_CallbackTypeDef : stm32g4xx_hal_adc.h
  • PCD_EPTypeDef : stm32g4xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32g4xx_hal_pcd.h
  • PCD_InitTypeDef : stm32g4xx_hal_pcd.h
  • PCD_TypeDef : stm32g4xx_hal_pcd.h
  • pCOMP_CallbackTypeDef : stm32g4xx_hal_comp.h
  • pCORDIC_CallbackTypeDef : stm32g4xx_hal_cordic.h
  • pDAC_CallbackTypeDef : stm32g4xx_hal_dac.h
  • pFDCAN_CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32g4xx_hal_fdcan.h
  • pFMAC_CallbackTypeDef : stm32g4xx_hal_fmac.h
  • pI2C_AddrCallbackTypeDef : stm32g4xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32g4xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32g4xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32g4xx_hal_irda.h
  • pLPTIM_CallbackTypeDef : stm32g4xx_hal_lptim.h
  • pOPAMP_CallbackTypeDef : stm32g4xx_hal_opamp.h
  • pPCD_BcdCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32g4xx_hal_pcd.h
  • pRNG_CallbackTypeDef : stm32g4xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32g4xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32g4xx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32g4xx_hal_sai.h
  • pSMARTCARD_CallbackTypeDef : stm32g4xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32g4xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32g4xx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32g4xx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32g4xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32g4xx_hal_uart.h
  • pUART_RxEventCallbackTypeDef : stm32g4xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32g4xx_hal_usart.h
  • pWWDG_CallbackTypeDef : stm32g4xx_hal_wwdg.h

- r -

  • RNG_HandleTypeDef : stm32g4xx_hal_rng.h
  • RTC_HandleTypeDef : stm32g4xx_hal_rtc.h

- s -

  • SAI_HandleTypeDef : stm32g4xx_hal_sai.h
  • SAIcallback : stm32g4xx_hal_sai.h
  • SMARTCARD_HandleTypeDef : stm32g4xx_hal_smartcard.h
  • SMBUS_HandleTypeDef : stm32g4xx_hal_smbus.h
  • SPI_HandleTypeDef : stm32g4xx_hal_spi.h

- t -

  • TIM_HandleTypeDef : stm32g4xx_hal_tim.h

- u -

  • UART_HandleTypeDef : stm32g4xx_hal_uart.h
  • USART_HandleTypeDef : stm32g4xx_hal_usart.h

- w -

  • WWDG_HandleTypeDef : stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • e
  • f
  • g
  • h
  • i
  • p
  • s
  • u

- e -

  • EXTI_CallbackIDTypeDef : stm32g4xx_hal_exti.h

- f -

  • FLASH_CacheTypeDef : stm32g4xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32g4xx_hal_flash.h

- g -

  • GPIO_PinState : stm32g4xx_hal_gpio.h

- h -

  • HAL_ADC_CallbackIDTypeDef : stm32g4xx_hal_adc.h
  • HAL_COMP_CallbackIDTypeDef : stm32g4xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32g4xx_hal_comp.h
  • HAL_CORDIC_CallbackIDTypeDef : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_StateTypeDef : stm32g4xx_hal_cordic.h
  • HAL_CRC_StateTypeDef : stm32g4xx_hal_crc.h
  • HAL_DAC_CallbackIDTypeDef : stm32g4xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32g4xx_hal_dac.h
  • HAL_DMA_CallbackIDTypeDef : stm32g4xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32g4xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32g4xx_hal_dma.h
  • HAL_FDCAN_CallbackIDTypeDef : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32g4xx_hal_fdcan.h
  • HAL_FMAC_CallbackIDTypeDef : stm32g4xx_hal_fmac.h
  • HAL_FMAC_StateTypeDef : stm32g4xx_hal_fmac.h
  • HAL_I2C_CallbackIDTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32g4xx_hal_i2c.h
  • HAL_I2S_CallbackIDTypeDef : stm32g4xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32g4xx_hal_i2s.h
  • HAL_IRDA_CallbackIDTypeDef : stm32g4xx_hal_irda.h
  • HAL_LPTIM_CallbackIDTypeDef : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32g4xx_hal_lptim.h
  • HAL_OPAMP_CallbackIDTypeDef : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32g4xx_hal_opamp.h
  • HAL_PCD_CallbackIDTypeDef : stm32g4xx_hal_pcd.h
  • HAL_RNG_CallbackIDTypeDef : stm32g4xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32g4xx_hal_rng.h
  • HAL_RTC_CallbackIDTypeDef : stm32g4xx_hal_rtc.h
  • HAL_RTCStateTypeDef : stm32g4xx_hal_rtc.h
  • HAL_SAI_CallbackIDTypeDef : stm32g4xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32g4xx_hal_sai.h
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32g4xx_hal_smartcard.h
  • HAL_SMBUS_CallbackIDTypeDef : stm32g4xx_hal_smbus.h
  • HAL_SPI_CallbackIDTypeDef : stm32g4xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32g4xx_hal_spi.h
  • HAL_TIM_ActiveChannel : stm32g4xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_ChannelStateTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_DMABurstStateTypeDef : stm32g4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32g4xx_hal_tim.h
  • HAL_UART_CallbackIDTypeDef : stm32g4xx_hal_uart.h
  • HAL_USART_CallbackIDTypeDef : stm32g4xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32g4xx_hal_usart.h
  • HAL_WWDG_CallbackIDTypeDef : stm32g4xx_hal_wwdg.h

- i -

  • IRDA_ClockSourceTypeDef : stm32g4xx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32g4xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32g4xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32g4xx_hal_pcd.h
  • PCD_StateTypeDef : stm32g4xx_hal_pcd.h

- s -

  • SAI_ModeTypedef : stm32g4xx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32g4xx_hal_smartcard.h

- u -

  • UART_ClockSourceTypeDef : stm32g4xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32g4xx_hal_usart.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- f -

  • FLASH_CACHE_DCACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_DISABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_ICACHE_DCACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_CACHE_ICACHE_ENABLED : stm32g4xx_hal_flash.h
  • FLASH_PROC_MASS_ERASE : stm32g4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32g4xx_hal_flash.h
  • FLASH_PROC_PAGE_ERASE : stm32g4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32g4xx_hal_flash.h
  • FLASH_PROC_PROGRAM_LAST : stm32g4xx_hal_flash.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- g -

  • GPIO_PIN_RESET : stm32g4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- h -

  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_MSPDEINIT_CB_ID : stm32g4xx_hal_adc.h
  • HAL_ADC_MSPINIT_CB_ID : stm32g4xx_hal_adc.h
  • HAL_COMP_MSPDEINIT_CB_ID : stm32g4xx_hal_comp.h
  • HAL_COMP_MSPINIT_CB_ID : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_BUSY : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32g4xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32g4xx_hal_comp.h
  • HAL_COMP_TRIGGER_CB_ID : stm32g4xx_hal_comp.h
  • HAL_CORDIC_CALCULATE_CPLT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_MSPDEINIT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_MSPINIT_CB_ID : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_BUSY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_ERROR : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_READY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_STATE_RESET : stm32g4xx_hal_cordic.h
  • HAL_CRC_STATE_BUSY : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32g4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32g4xx_hal_crc.h
  • HAL_DAC_ALL_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_MSPDEINIT_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_MSPINIT_CB_ID : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_BUSY : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32g4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32g4xx_hal_dac.h
  • HAL_DMA_BURST_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_DMA_BURST_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_DMA_BURST_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_DMA_FULL_TRANSFER : stm32g4xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32g4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32g4xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32g4xx_hal_dma.h
  • HAL_EXTI_COMMON_CB_ID : stm32g4xx_hal_exti.h
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_MSPINIT_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_BUSY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_fdcan.h
  • HAL_FMAC_ERROR_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_FILTER_CONFIG_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_FILTER_PRELOAD_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_GET_DATA_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_HALF_GET_DATA_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_MSPDEINIT_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_MSPINIT_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_OUTPUT_DATA_READY_CB_ID : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_BUSY : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_BUSY_RD : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_BUSY_WR : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_ERROR : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_READY : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_RESET : stm32g4xx_hal_fmac.h
  • HAL_FMAC_STATE_TIMEOUT : stm32g4xx_hal_fmac.h
  • HAL_I2C_ABORT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_MASTER : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32g4xx_hal_i2c.h
  • HAL_I2C_MSPDEINIT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_MSPINIT_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32g4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32g4xx_hal_i2c.h
  • HAL_I2S_ERROR_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_MSPDEINIT_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_MSPINIT_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32g4xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32g4xx_hal_i2s.h
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_i2s.h
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_MSPINIT_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_irda.h
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_MSPINIT_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32g4xx_hal_lptim.h
  • HAL_LPTIM_TRIGGER_CB_ID : stm32g4xx_hal_lptim.h
  • HAL_OPAMP_ALL_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_MSPDEINIT_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_MSPINIT_CB_ID : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32g4xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32g4xx_hal_opamp.h
  • HAL_PCD_CONNECT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_DISCONNECT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_MSPDEINIT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_MSPINIT_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_RESET_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_RESUME_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_SOF_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_BUSY : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32g4xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32g4xx_hal_pcd.h
  • HAL_PCD_SUSPEND_CB_ID : stm32g4xx_hal_pcd.h
  • HAL_RNG_ERROR_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_MSPDEINIT_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_MSPINIT_CB_ID : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_BUSY : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32g4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32g4xx_hal_rng.h
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_MSPDEINIT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_MSPINIT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_BUSY : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32g4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32g4xx_hal_rtc.h
  • HAL_SAI_ERROR_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_MSPDEINIT_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_MSPINIT_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32g4xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32g4xx_hal_sai.h
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_sai.h
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MSPINIT_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32g4xx_hal_smbus.h
  • HAL_SPI_ABORT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_MSPDEINIT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_MSPINIT_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_ABORT : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32g4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32g4xx_hal_spi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32g4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32g4xx_hal_tim.h
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_BREAK2_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_DIRECTION_CHANGE_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ENCODER_INDEX_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_INDEX_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32g4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32g4xx_hal_tim.h
  • HAL_TIM_TRANSITION_ERROR_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32g4xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32g4xx_hal_tim.h
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_MSPDEINIT_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_MSPINIT_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RX_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TX_COMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_uart.h
  • HAL_UART_WAKEUP_CB_ID : stm32g4xx_hal_uart.h
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_MSPDEINIT_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_MSPINIT_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32g4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32g4xx_hal_usart.h
  • HAL_USART_TX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32g4xx_hal_usart.h
  • HAL_WWDG_EWI_CB_ID : stm32g4xx_hal_wwdg.h
  • HAL_WWDG_MSPINIT_CB_ID : stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- i -

  • IRDA_CLOCKSOURCE_HSI : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_irda.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- l -

  • LPM_L0 : stm32g4xx_hal_pcd.h
  • LPM_L1 : stm32g4xx_hal_pcd.h
  • LPM_L2 : stm32g4xx_hal_pcd.h
  • LPM_L3 : stm32g4xx_hal_pcd.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32g4xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32g4xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32g4xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32g4xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32g4xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32g4xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32g4xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32g4xx_hal_pcd.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- s -

  • SAI_MODE_DMA : stm32g4xx_hal_sai.c
  • SAI_MODE_IT : stm32g4xx_hal_sai.c
  • SMARTCARD_CLOCKSOURCE_HSI : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_smartcard.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • f
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- u -

  • UART_CLOCKSOURCE_HSI : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32g4xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32g4xx_hal_usart.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- _ -

  • __ADC_PTR_REG_OFFSET : stm32g4xx_ll_adc.h
  • __DAC_PTR_REG_OFFSET : stm32g4xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g4xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g4xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32g4xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32g4xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32g4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32g4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32g4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32g4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g4xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g4xx_hal_adc.h
  • __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32g4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32g4xx_hal_adc.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_CLEAR_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_EVENT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_IT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_GENERATE_SWIT : stm32g4xx_hal_comp.h
  • __HAL_COMP_COMP4_EXTI_GET_FLAG : stm32g4xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32g4xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32g4xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32g4xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32g4xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32g4xx_hal_comp.h
  • __HAL_CORDIC_CLEAR_FLAG : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_CLEAR_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_DISABLE_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_ENABLE_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_FLAG : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_IT : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_GET_IT_SOURCE : stm32g4xx_hal_cordic.h
  • __HAL_CORDIC_RESET_HANDLE_STATE : stm32g4xx_hal_cordic.h
  • __HAL_CRC_DR_RESET : stm32g4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32g4xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32g4xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32g4xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32g4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32g4xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32g4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32g4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32g4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32g4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32g4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32g4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32g4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32g4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32g4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32g4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32g4xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32g4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32g4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32g4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32g4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32g4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32g4xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32g4xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32g4xx_hal_fdcan.h
  • __HAL_FLASH_CLEAR_FLAG : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32g4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32g4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32g4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32g4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32g4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_DISABLE : stm32g4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_ENABLE : stm32g4xx_hal_flash.h
  • __HAL_FMAC_CLEAR_FLAG : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_CLEAR_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_DISABLE_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_ENABLE_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_FLAG : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_IT : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_GET_IT_SOURCE : stm32g4xx_hal_fmac.h
  • __HAL_FMAC_RESET_HANDLE_STATE : stm32g4xx_hal_fmac.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32g4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32g4xx_hal_gpio.h
  • __HAL_I2C_CLEAR_FLAG : stm32g4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32g4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32g4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32g4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32g4xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32g4xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32g4xx_hal_i2s.h
  • __HAL_I2S_FLUSH_RX_DR : stm32g4xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32g4xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32g4xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32g4xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32g4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32g4xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32g4xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32g4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32g4xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g4xx_hal_lptim.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32g4xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32g4xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32g4xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32g4xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32g4xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32g4xx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_CLEAR_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_EVENT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_IT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GENERATE_SWIT : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GET_FLAG : stm32g4xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32g4xx_hal_pwr_ex.h
  • __HAL_RCC_ADC12_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_ADC12_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ADC12_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CORDIC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DAC3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_FMAC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_ADC12_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_I2S_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_UCPD1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32g4xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32g4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32g4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32g4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32g4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32g4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32g4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32g4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32g4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_FALLING_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_RISING_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32g4xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32g4xx_hal_rtc.h
  • __HAL_RTC_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_IS_CALENDAR_INITIALIZED : stm32g4xx_hal_rtc.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32g4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32g4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32g4xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32g4xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32g4xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32g4xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32g4xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32g4xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32g4xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32g4xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32g4xx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32g4xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32g4xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32g4xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32g4xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32g4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32g4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32g4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32g4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32g4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32g4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32g4xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_ERASE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK : stm32g4xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32g4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32g4xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32g4xx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32g4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32g4xx_hal.h
  • __HAL_TIM_CALC_PERIOD : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_BY_DELAY : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_DITHER : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PSC : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PULSE : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CALC_PULSE_DITHER : stm32g4xx_hal_tim_ex.h
  • __HAL_TIM_CLEAR_FLAG : stm32g4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32g4xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32g4xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32g4xx_hal_tim.h
  • __HAL_TIM_GET_UIFCPY : stm32g4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32g4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32g4xx_hal_tim.h
  • __HAL_TIM_SELECT_CCDMAREQUEST : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32g4xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32g4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32g4xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32g4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32g4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32g4xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32g4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32g4xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32g4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32g4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32g4xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32g4xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32g4xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32g4xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32g4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32g4xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g4xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g4xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32g4xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g4xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32g4xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32g4xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g4xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g4xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32g4xx_ll_adc.h
  • __LL_ADC_MULTI_INSTANCE_MASTER : stm32g4xx_ll_adc.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32g4xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32g4xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32g4xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32g4xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32g4xx_ll_dac.h
  • __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG : stm32g4xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32g4xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32g4xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32g4xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32g4xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32g4xx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32g4xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32g4xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32g4xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32g4xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_ARR_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32g4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE_DITHER : stm32g4xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32g4xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32g4xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32g4xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32g4xx_ll_usart.h
  • __LSCO_CLK_ENABLE : stm32g4xx_hal_rcc_ex.c
  • __OPAMP_PTR_REG_OFFSET : stm32g4xx_ll_opamp.h
  • __STM32G4xx_HAL_VERSION : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_MAIN : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_RC : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_SUB1 : stm32g4xx_hal.c
  • __STM32G4xx_HAL_VERSION_SUB2 : stm32g4xx_hal.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- a -

  • ADC_ANALOGWATCHDOG_1 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32g4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32g4xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32g4xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_AWD_EVENT : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_2SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_3SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_4SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_5SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_6SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_7SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_8SAMPLES : stm32g4xx_hal_adc.h
  • ADC_AWD_FILTERING_NONE : stm32g4xx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32g4xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32g4xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_AUTOWAIT : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32g4xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32g4xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR_ADC1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR_ADC5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP1 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP3_ADC2 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP3_ADC3 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP4 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP5 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VOPAMP6 : stm32g4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32g4xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32g4xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32g4xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g4xx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32g4xx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32g4xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32g4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32g4xx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32g4xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32g4xx_hal_adc.c
  • ADC_DMAACCESSMODE_12_10_BITS : stm32g4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_8_6_BITS : stm32g4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_ALTERTRIG : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32g4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32g4xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32g4xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32g4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32g4xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG10 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG5 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG6 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG7 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG8 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_HRTIM_TRG9 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_LPTIM_OUT : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T20_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC3 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T7_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_CC1 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32g4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_LPTIM_OUT : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T16_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_CC2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T20_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_CC3 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T7_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32g4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32g4xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32g4xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32g4xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOC : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOS : stm32g4xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32g4xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32g4xx_hal_adc.h
  • ADC_FLAG_JEOS : stm32g4xx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32g4xx_hal_adc.h
  • ADC_FLAG_OVR : stm32g4xx_hal_adc.h
  • ADC_FLAG_RDY : stm32g4xx_hal_adc.h
  • ADC_FORCE_MODE_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32g4xx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32g4xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32g4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32g4xx_hal_adc_ex.h
  • ADC_IS_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32g4xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32g4xx_hal_adc.h
  • ADC_IT_AWD2 : stm32g4xx_hal_adc.h
  • ADC_IT_AWD3 : stm32g4xx_hal_adc.h
  • ADC_IT_EOC : stm32g4xx_hal_adc.h
  • ADC_IT_EOS : stm32g4xx_hal_adc.h
  • ADC_IT_EOSMP : stm32g4xx_hal_adc.h
  • ADC_IT_JEOC : stm32g4xx_hal_adc.h
  • ADC_IT_JEOS : stm32g4xx_hal_adc.h
  • ADC_IT_JQOVF : stm32g4xx_hal_adc.h
  • ADC_IT_OVR : stm32g4xx_hal_adc.h
  • ADC_IT_RDY : stm32g4xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32g4xx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32g4xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32g4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32g4xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SIGN_NEGATIVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFFSET_SIGN_POSITIVE : stm32g4xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_OFRx_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32g4xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32g4xx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32g4xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32g4xx_hal_adc.h
  • ADC_OVR_EVENT : stm32g4xx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32g4xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32g4xx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32g4xx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32g4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32g4xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32g4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32g4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_BULB : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_NORMAL : stm32g4xx_hal_adc.h
  • ADC_SAMPLING_MODE_TRIGGER_CONTROLED : stm32g4xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32g4xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32g4xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32g4xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32g4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32g4xx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32g4xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32g4xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32g4xx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_STATE_CLR_SET : stm32g4xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32g4xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32g4xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32g4xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32g4xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32g4xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32g4xx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32g4xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32g4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32g4xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32g4xx_hal_adc_ex.h
  • assert_param : stm32g4xx_ll_usart.c , stm32g4xx_ll_lpuart.c , stm32g4xx_ll_hrtim.c , stm32g4xx_ll_tim.c , stm32g4xx_ll_ucpd.c , stm32g4xx_ll_dma.c , stm32g4xx_ll_comp.c , stm32g4xx_ll_lptim.c , stm32g4xx_hal_conf.h , stm32g4xx_ll_spi.c , stm32g4xx_ll_cordic.c , stm32g4xx_ll_rtc.c , stm32g4xx_ll_rcc.c , stm32g4xx_ll_crc.c , stm32g4xx_ll_i2c.c , stm32g4xx_ll_dac.c , stm32g4xx_ll_utils.c , stm32g4xx_ll_rng.c , stm32g4xx_ll_opamp.c , stm32g4xx_ll_fmac.c , stm32g4xx_ll_gpio.c , stm32g4xx_ll_adc.c , stm32g4xx_ll_exti.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- b -

  • BDCR_REG_INDEX : stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- c -

  • CCMER_BitNumber : stm32g4xx_hal.c
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM20_OC5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC4_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC4_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP7 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM4_OC3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP1 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP3 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP4 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP5 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP6 : stm32g4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP7 : stm32g4xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32g4xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32g4xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g4xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32g4xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32g4xx_hal_comp.h
  • COMP_EXTI_IT : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP3 : stm32g4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP4 : stm32g4xx_hal_comp.h
  • COMP_EXTI_RISING : stm32g4xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_10MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_20MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_30MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_40MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_50MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_60MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_70MV : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32g4xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC2_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC3_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC3_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC4_CH1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC4_CH2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32g4xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32g4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32g4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32g4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g4xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32g4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32g4xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32g4xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32g4xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32g4xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32g4xx_hal_comp.h
  • CORDIC_DMA_DIR_IN : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_IN_OUT : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_NONE : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_DIR_OUT : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_REN : stm32g4xx_hal_cordic.h
  • CORDIC_DMA_WEN : stm32g4xx_hal_cordic.h
  • CORDIC_FLAG_RRDY : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_ARCTANGENT : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_COSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HARCTANGENT : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HCOSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_HSINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_MODULUS : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_NATURALLOG : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_PHASE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_SINE : stm32g4xx_hal_cordic.h
  • CORDIC_FUNCTION_SQUAREROOT : stm32g4xx_hal_cordic.h
  • CORDIC_INSIZE_16BITS : stm32g4xx_hal_cordic.h
  • CORDIC_INSIZE_32BITS : stm32g4xx_hal_cordic.h
  • CORDIC_IT_IEN : stm32g4xx_hal_cordic.h
  • CORDIC_NBREAD_1 : stm32g4xx_hal_cordic.h
  • CORDIC_NBREAD_2 : stm32g4xx_hal_cordic.h
  • CORDIC_NBWRITE_1 : stm32g4xx_hal_cordic.h
  • CORDIC_NBWRITE_2 : stm32g4xx_hal_cordic.h
  • CORDIC_OUTSIZE_16BITS : stm32g4xx_hal_cordic.h
  • CORDIC_OUTSIZE_32BITS : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_10CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_11CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_12CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_13CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_14CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_15CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_1CYCLE : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_2CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_3CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_4CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_5CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_6CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_7CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_8CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_PRECISION_9CYCLES : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_0 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_1 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_2 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_3 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_4 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_5 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_6 : stm32g4xx_hal_cordic.h
  • CORDIC_SCALE_7 : stm32g4xx_hal_cordic.h
  • CR_REG_INDEX : stm32g4xx_hal_rcc.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32g4xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32g4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32g4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32g4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32g4xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32g4xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32g4xx_hal_crc.h
  • CRRCR_REG_INDEX : stm32g4xx_hal_rcc.h
  • CSR_REG_INDEX : stm32g4xx_hal_rcc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- d -

  • DAC_ALIGN_12B_L : stm32g4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32g4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32g4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32g4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_BOTH : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_EXTERNAL : stm32g4xx_hal_dac.h
  • DAC_CHIPCONNECT_INTERNAL : stm32g4xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32g4xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32g4xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_DELAY_STARTUP_US : stm32g4xx_hal_dac.h
  • DAC_DELAY_TRIM_US : stm32g4xx_hal_dac_ex.c
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32g4xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32g4xx_ll_dac.h
  • DAC_FLAG_DAC1RDY : stm32g4xx_hal_dac.h
  • DAC_FLAG_DAC2RDY : stm32g4xx_hal_dac.h
  • DAC_FLAG_DMAUDR1 : stm32g4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC : stm32g4xx_hal_dac.h
  • DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE : stm32g4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32g4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32g4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32g4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32g4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32g4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32g4xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_REG_STR1_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_STR2_REGOFFSET : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_BITOFFSET_POS : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_MASK : stm32g4xx_ll_dac.h
  • DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 : stm32g4xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32g4xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32g4xx_hal_dac.h
  • DAC_SAWTOOTH_POLARITY_DECREMENT : stm32g4xx_hal_dac_ex.h
  • DAC_SAWTOOTH_POLARITY_INCREMENT : stm32g4xx_hal_dac_ex.h
  • DAC_SWTR_CH1 : stm32g4xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32g4xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CH1 : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CH2 : stm32g4xx_ll_dac.h
  • DAC_SWTRB_CHX_MASK : stm32g4xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32g4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT10 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_EXT_IT9 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG1 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG2 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG3 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG4 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG5 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_RST_TRG6 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG1 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG2 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG3 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG4 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG5 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_STEP_TRG6 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG01 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG02 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_HRTIM_TRG03 : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T3_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32g4xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32g4xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32g4xx_hal_dac.h
  • DATA_CACHE_ENABLE : stm32g4xx_hal_conf.h
  • DBGMCU_REVID_POSITION : stm32g4xx_ll_system.h
  • DEFAULT_CRC32_POLY : stm32g4xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32g4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32g4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32g4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32g4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32g4xx_hal_crc.h
  • DIVIDER_P_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32g4xx_hal_rcc_ex.c
  • DMA_CIRCULAR : stm32g4xx_hal_dma.h
  • DMA_CSELR_OFFSET : stm32g4xx_ll_dma.h
  • DMA_FLAG_GL1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32g4xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32g4xx_hal_dma.h
  • DMA_IT_HT : stm32g4xx_hal_dma.h
  • DMA_IT_TC : stm32g4xx_hal_dma.h
  • DMA_IT_TE : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32g4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32g4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32g4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32g4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32g4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32g4xx_hal_dma.h
  • DMA_NORMAL : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32g4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32g4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32g4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32g4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32g4xx_hal_dma.h
  • DMA_POSITION_CSELR_CXS : stm32g4xx_ll_dma.h
  • DMA_PRIORITY_HIGH : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32g4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32g4xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_ADC2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_AES_IN : stm32g4xx_hal_dma.h
  • DMA_REQUEST_AES_OUT : stm32g4xx_hal_dma.h
  • DMA_REQUEST_CORDIC_READ : stm32g4xx_hal_dma.h
  • DMA_REQUEST_CORDIC_WRITE : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC1_CHANNEL1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC1_CHANNEL2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC3_CHANNEL1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_DAC3_CHANNEL2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_FMAC_READ : stm32g4xx_hal_dma.h
  • DMA_REQUEST_FMAC_WRITE : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH1 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH2 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH3 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_CH4 : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_COM : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_TRIG : stm32g4xx_hal_dma.h
  • DMA_REQUEST_TIM8_UP : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UART4_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UART4_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UCPD1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_UCPD1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32g4xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32g4xx_hal_dma.h
  • DMAMUX_CCR_SIZE : stm32g4xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32g4xx_ll_dmamux.h
  • DT_DELAY_1 : stm32g4xx_ll_tim.h
  • DT_DELAY_2 : stm32g4xx_ll_tim.h
  • DT_DELAY_3 : stm32g4xx_ll_tim.h
  • DT_DELAY_4 : stm32g4xx_ll_tim.h
  • DT_RANGE_1 : stm32g4xx_ll_tim.h
  • DT_RANGE_2 : stm32g4xx_ll_tim.h
  • DT_RANGE_3 : stm32g4xx_ll_tim.h
  • DT_RANGE_4 : stm32g4xx_ll_tim.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- e -

  • EXTERNAL_CLOCK_VALUE : stm32g4xx_hal_conf.h
  • EXTI_CONFIG : stm32g4xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32g4xx_hal_exti.c
  • EXTI_DIRECT : stm32g4xx_hal_exti.h
  • EXTI_EVT : stm32g4xx_hal_gpio.h
  • EXTI_GPIO : stm32g4xx_hal_exti.h
  • EXTI_GPIOA : stm32g4xx_hal_exti.h
  • EXTI_GPIOB : stm32g4xx_hal_exti.h
  • EXTI_GPIOC : stm32g4xx_hal_exti.h
  • EXTI_GPIOD : stm32g4xx_hal_exti.h
  • EXTI_GPIOE : stm32g4xx_hal_exti.h
  • EXTI_GPIOF : stm32g4xx_hal_exti.h
  • EXTI_GPIOG : stm32g4xx_hal_exti.h
  • EXTI_IT : stm32g4xx_hal_gpio.h
  • EXTI_LINE_0 : stm32g4xx_hal_exti.h
  • EXTI_LINE_1 : stm32g4xx_hal_exti.h
  • EXTI_LINE_10 : stm32g4xx_hal_exti.h
  • EXTI_LINE_11 : stm32g4xx_hal_exti.h
  • EXTI_LINE_12 : stm32g4xx_hal_exti.h
  • EXTI_LINE_13 : stm32g4xx_hal_exti.h
  • EXTI_LINE_14 : stm32g4xx_hal_exti.h
  • EXTI_LINE_15 : stm32g4xx_hal_exti.h
  • EXTI_LINE_16 : stm32g4xx_hal_exti.h
  • EXTI_LINE_17 : stm32g4xx_hal_exti.h
  • EXTI_LINE_18 : stm32g4xx_hal_exti.h
  • EXTI_LINE_19 : stm32g4xx_hal_exti.h
  • EXTI_LINE_2 : stm32g4xx_hal_exti.h
  • EXTI_LINE_20 : stm32g4xx_hal_exti.h
  • EXTI_LINE_21 : stm32g4xx_hal_exti.h
  • EXTI_LINE_22 : stm32g4xx_hal_exti.h
  • EXTI_LINE_23 : stm32g4xx_hal_exti.h
  • EXTI_LINE_24 : stm32g4xx_hal_exti.h
  • EXTI_LINE_25 : stm32g4xx_hal_exti.h
  • EXTI_LINE_26 : stm32g4xx_hal_exti.h
  • EXTI_LINE_27 : stm32g4xx_hal_exti.h
  • EXTI_LINE_28 : stm32g4xx_hal_exti.h
  • EXTI_LINE_29 : stm32g4xx_hal_exti.h
  • EXTI_LINE_3 : stm32g4xx_hal_exti.h
  • EXTI_LINE_30 : stm32g4xx_hal_exti.h
  • EXTI_LINE_31 : stm32g4xx_hal_exti.h
  • EXTI_LINE_32 : stm32g4xx_hal_exti.h
  • EXTI_LINE_33 : stm32g4xx_hal_exti.h
  • EXTI_LINE_34 : stm32g4xx_hal_exti.h
  • EXTI_LINE_35 : stm32g4xx_hal_exti.h
  • EXTI_LINE_36 : stm32g4xx_hal_exti.h
  • EXTI_LINE_37 : stm32g4xx_hal_exti.h
  • EXTI_LINE_38 : stm32g4xx_hal_exti.h
  • EXTI_LINE_39 : stm32g4xx_hal_exti.h
  • EXTI_LINE_4 : stm32g4xx_hal_exti.h
  • EXTI_LINE_40 : stm32g4xx_hal_exti.h
  • EXTI_LINE_41 : stm32g4xx_hal_exti.h
  • EXTI_LINE_42 : stm32g4xx_hal_exti.h
  • EXTI_LINE_43 : stm32g4xx_hal_exti.h
  • EXTI_LINE_5 : stm32g4xx_hal_exti.h
  • EXTI_LINE_6 : stm32g4xx_hal_exti.h
  • EXTI_LINE_7 : stm32g4xx_hal_exti.h
  • EXTI_LINE_8 : stm32g4xx_hal_exti.h
  • EXTI_LINE_9 : stm32g4xx_hal_exti.h
  • EXTI_LINE_NB : stm32g4xx_hal_exti.h
  • EXTI_MODE : stm32g4xx_hal_gpio.h
  • EXTI_MODE_EVENT : stm32g4xx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32g4xx_hal_exti.h
  • EXTI_MODE_MASK : stm32g4xx_hal_exti.h
  • EXTI_MODE_NONE : stm32g4xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32g4xx_hal_exti.c
  • EXTI_MODE_Pos : stm32g4xx_hal_gpio.h
  • EXTI_PIN_MASK : stm32g4xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32g4xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32g4xx_hal_exti.h
  • EXTI_REG1 : stm32g4xx_hal_exti.h
  • EXTI_REG2 : stm32g4xx_hal_exti.h
  • EXTI_REG_MASK : stm32g4xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32g4xx_hal_exti.h
  • EXTI_RESERVED : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32g4xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32g4xx_hal_exti.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- f -

  • FB_MODE_BB : stm32g4xx_hal.c
  • FB_MODE_BitNumber : stm32g4xx_hal.c
  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32g4xx_hal_fdcan.h
  • FDCAN_CHECK_FLAG : stm32g4xx_hal_fdcan.h
  • FDCAN_CHECK_IT_SOURCE : stm32g4xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32g4xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32g4xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32g4xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32g4xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32g4xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32g4xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32g4xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32g4xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32g4xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32g4xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_ILS_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32g4xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_BIT_LINE_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_MISC : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_SMSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_GROUP_TX_FIFO_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_BIT_LINE_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_MISC : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_PROTOCOL_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_SMSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_LIST_TX_FIFO_ERROR : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32g4xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32g4xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32g4xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32g4xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32g4xx_hal_fdcan.h
  • FDCAN_REJECT : stm32g4xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32g4xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32g4xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32g4xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32g4xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32g4xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32g4xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32g4xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32g4xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32g4xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32g4xx_hal_flash.h
  • FLASH_BANK_BOTH : stm32g4xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32g4xx_hal_flash.h
  • FLASH_FLAG_ECCR_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32g4xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32g4xx_hal_flash.h
  • FLASH_FLAG_SR_ERRORS : stm32g4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32g4xx_hal_flash.h
  • FLASH_IT_ECCC : stm32g4xx_hal_flash.h
  • FLASH_IT_EOP : stm32g4xx_hal_flash.h
  • FLASH_IT_OPERR : stm32g4xx_hal_flash.h
  • FLASH_IT_RDERR : stm32g4xx_hal_flash.h
  • FLASH_KEY1 : stm32g4xx_hal_flash.h
  • FLASH_KEY2 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_10 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_11 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_12 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_13 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_14 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_15 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_3 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_4 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_5 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_6 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_7 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_8 : stm32g4xx_hal_flash.h
  • FLASH_LATENCY_9 : stm32g4xx_hal_flash.h
  • FLASH_NB_DOUBLE_WORDS_IN_ROW : stm32g4xx_hal_flash.c
  • FLASH_OPTKEY1 : stm32g4xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32g4xx_hal_flash.h
  • FLASH_PAGE_NB : stm32g4xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32g4xx_hal_flash.h
  • FLASH_PDKEY1 : stm32g4xx_ll_system.h , stm32g4xx_hal_flash.h
  • FLASH_PDKEY2 : stm32g4xx_ll_system.h , stm32g4xx_hal_flash.h
  • FLASH_SIZE : stm32g4xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32g4xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32g4xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32g4xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32g4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST_AND_LAST : stm32g4xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • FMAC_BUFFER_ACCESS_DMA : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_IT : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_NONE : stm32g4xx_hal_fmac.h
  • FMAC_BUFFER_ACCESS_POLLING : stm32g4xx_hal_fmac.h
  • FMAC_CLIP_DISABLED : stm32g4xx_hal_fmac.h
  • FMAC_CLIP_ENABLED : stm32g4xx_hal_fmac.h
  • FMAC_DMA_REN : stm32g4xx_hal_fmac.c
  • FMAC_DMA_WEN : stm32g4xx_hal_fmac.c
  • FMAC_FLAG_OVFL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_SAT : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_UNFL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_X1FULL : stm32g4xx_hal_fmac.h
  • FMAC_FLAG_YEMPTY : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_CONVO_FIR : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_IIR_DIRECT_FORM_1 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_X1 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_X2 : stm32g4xx_hal_fmac.h
  • FMAC_FUNC_LOAD_Y : stm32g4xx_hal_fmac.h
  • FMAC_GET_START_BIT : stm32g4xx_hal_fmac.c
  • FMAC_GET_THRESHOLD_FROM_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_X1_FULL_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_X1_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_GET_X2_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_GET_Y_EMPTY_WM : stm32g4xx_hal_fmac.c
  • FMAC_GET_Y_SIZE : stm32g4xx_hal_fmac.c
  • FMAC_IT_OVFLIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_RIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_SATIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_UNFLIEN : stm32g4xx_hal_fmac.h
  • FMAC_IT_WIEN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MAX_FIR : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MAX_IIR : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_P_MIN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_Q_MAX : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_Q_MIN : stm32g4xx_hal_fmac.h
  • FMAC_PARAM_R_MAX : stm32g4xx_hal_fmac.h
  • FMAC_START : stm32g4xx_hal_fmac.c
  • FMAC_THRESHOLD_1 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_2 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_4 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_8 : stm32g4xx_hal_fmac.h
  • FMAC_THRESHOLD_NO_VALUE : stm32g4xx_hal_fmac.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- g -

  • GPIO_AF0_MCO : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM17_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF10_TIM8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_FDCAN1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_LPTIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF11_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_LPUART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF12_TIM1_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF14_UCPD1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM17_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_COMP3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_SAI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF3_UCPD1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM16 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM17 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF4_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_I2S2ext : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF5_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_I2S3ext : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_IR : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM1_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF6_TIM8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP2 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_COMP4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_I2C3 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_FDCAN1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM15_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM1_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM8 : stm32g4xx_hal_gpio_ex.h
  • GPIO_AF9_TIM8_COMP1 : stm32g4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32g4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32g4xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32g4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32g4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32g4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32g4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32g4xx_hal_gpio.h
  • GPIO_MODE_Pos : stm32g4xx_hal_gpio.h
  • GPIO_NOPULL : stm32g4xx_hal_gpio.h
  • GPIO_NUMBER : stm32g4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32g4xx_hal_gpio.h
  • GPIO_PIN_All : stm32g4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32g4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32g4xx_hal_gpio.h
  • GPIO_PULLUP : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32g4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- h -

  • HAL_ADC_ERROR_DMA : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32g4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32g4xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32g4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32g4xx_hal_adc.h
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32g4xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32g4xx_hal_comp.h
  • HAL_COMP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CORDIC_ERROR_DMA : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_NONE : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_NOT_READY : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_PARAM : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_ERROR_TIMEOUT : stm32g4xx_hal_cordic.h
  • HAL_CORDIC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CRC_LENGTH_16B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32g4xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32g4xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_CRYP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32g4xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32g4xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DMA_ERROR_NO_XFER : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32g4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32g4xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32g4xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32g4xx_hal_dma_ex.h
  • HAL_EXTI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32g4xx_hal_fdcan.h
  • HAL_FDCAN_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FLASH_ERROR_ECCC : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_ECCD : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32g4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32g4xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FMAC_ERROR_DMA : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_INVALID_CALLBACK : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_NONE : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_OVFL : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_PARAM : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_RESET : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_SAT : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_TIMEOUT : stm32g4xx_hal_fmac.h
  • HAL_FMAC_ERROR_UNFL : stm32g4xx_hal_fmac.h
  • HAL_FMAC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_FMAC_RESET_TIMEOUT_VALUE : stm32g4xx_hal_fmac.c
  • HAL_FMAC_TIMEOUT_VALUE : stm32g4xx_hal_fmac.c
  • HAL_GPIO_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_HRTIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32g4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32g4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_I2S_ERROR_BUSY_LINE_RX : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_DMA : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32g4xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32g4xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_IRDA_ERROR_BUSY : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32g4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32g4xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_IRDA_STATE_BUSY : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32g4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32g4xx_hal_irda.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32g4xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_OPAMP_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32g4xx_hal_pcd.h
  • HAL_PCD_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_QSPI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RNG_ERROR_BUSY : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32g4xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32g4xx_hal_rng.h
  • HAL_RNG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32g4xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32g4xx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SMARTCARD_STATE_BUSY : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32g4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32g4xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_ACKF : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32g4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32g4xx_hal_smbus.h
  • HAL_SPI_ERROR_ABORT : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32g4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32g4xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_TICK_FREQ_100HZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32g4xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32g4xx_hal.h
  • HAL_TIM_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32g4xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32g4xx_hal_smbus.c
  • HAL_UART_ERROR_DMA : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32g4xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32g4xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_UART_RECEPTION_STANDARD : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TOCHARMATCH : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TOIDLE : stm32g4xx_hal_uart.h
  • HAL_UART_RECEPTION_TORTO : stm32g4xx_hal_uart.h
  • HAL_UART_RXEVENT_HT : stm32g4xx_hal_uart.h
  • HAL_UART_RXEVENT_IDLE : stm32g4xx_hal_uart.h
  • HAL_UART_RXEVENT_TC : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32g4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32g4xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32g4xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_RTO : stm32g4xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32g4xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32g4xx_hal_conf.h
  • HFSEL_ENABLE_THRESHOLD_160MHZ : stm32g4xx_hal_dac.c
  • HFSEL_ENABLE_THRESHOLD_80MHZ : stm32g4xx_hal_dac.c
  • HSE_STARTUP_TIMEOUT : stm32g4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSE_VALUE : stm32g4xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSI48_VALUE : stm32g4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • HSI_VALUE : stm32g4xx_hal_conf.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32g4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32g4xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32g4xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32g4xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32g4xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32g4xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32g4xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32g4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32g4xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C4 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32g4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32g4xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32g4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32g4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32g4xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32g4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32g4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TC : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32g4xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32g4xx_hal_i2c.h
  • I2C_FMP_NOT_SUPPORTED : stm32g4xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32g4xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32g4xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32g4xx_hal_i2c.h
  • I2C_GET_DIR : stm32g4xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32g4xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32g4xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32g4xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32g4xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32g4xx_hal_i2c.h
  • I2C_IT_ERRI : stm32g4xx_hal_i2c.h
  • I2C_IT_NACKI : stm32g4xx_hal_i2c.h
  • I2C_IT_RXI : stm32g4xx_hal_i2c.h
  • I2C_IT_STOPI : stm32g4xx_hal_i2c.h
  • I2C_IT_TCI : stm32g4xx_hal_i2c.h
  • I2C_IT_TXI : stm32g4xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32g4xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32g4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32g4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32g4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32g4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32g4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32g4xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32g4xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32g4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32g4xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32g4xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32g4xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32g4xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32g4xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32g4xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32g4xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32g4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32g4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32g4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32g4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32g4xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32g4xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32g4xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32g4xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32g4xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32g4xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32g4xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32g4xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32g4xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32g4xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32g4xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32g4xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32g4xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32g4xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32g4xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32g4xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32g4xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32g4xx_ll_spi.c
  • I2S_IT_ERR : stm32g4xx_hal_i2s.h
  • I2S_IT_RXNE : stm32g4xx_hal_i2s.h
  • I2S_IT_TXE : stm32g4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32g4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32g4xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32g4xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32g4xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32g4xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32g4xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32g4xx_hal_i2s.h
  • I2S_TIMEOUT_FLAG : stm32g4xx_hal_i2s.c
  • INSTRUCTION_CACHE_ENABLE : stm32g4xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32g4xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32g4xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32g4xx_hal_irda.c
  • IRDA_CR_MASK : stm32g4xx_hal_irda.h
  • IRDA_CR_POS : stm32g4xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32g4xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32g4xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32g4xx_hal_irda.h
  • IRDA_FLAG_FE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32g4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32g4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32g4xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32g4xx_hal_irda_ex.h
  • IRDA_ISR_MASK : stm32g4xx_hal_irda.h
  • IRDA_ISR_POS : stm32g4xx_hal_irda.h
  • IRDA_IT_ERR : stm32g4xx_hal_irda.h
  • IRDA_IT_FE : stm32g4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32g4xx_hal_irda.h
  • IRDA_IT_MASK : stm32g4xx_hal_irda.h
  • IRDA_IT_NE : stm32g4xx_hal_irda.h
  • IRDA_IT_ORE : stm32g4xx_hal_irda.h
  • IRDA_IT_PE : stm32g4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32g4xx_hal_irda.h
  • IRDA_IT_TC : stm32g4xx_hal_irda.h
  • IRDA_IT_TXE : stm32g4xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32g4xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_MODE_RX : stm32g4xx_hal_irda.h
  • IRDA_MODE_TX : stm32g4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32g4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32g4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32g4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32g4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32g4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32g4xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32g4xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32g4xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32g4xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32g4xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32g4xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32g4xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32g4xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32g4xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32g4xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_DMA_ACCESS_MULTIMODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32g4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32g4xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32g4xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32g4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_GAIN_COMPENSATION : stm32g4xx_hal_adc.h
  • IS_ADC_INJECTED_NB_CONV : stm32g4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32g4xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_SIGN : stm32g4xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32g4xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32g4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32g4xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32g4xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32g4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32g4xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32g4xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32g4xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32g4xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32g4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32g4xx_hal_adc_ex.h
  • IS_ADC_SAMPLINGMODE : stm32g4xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32g4xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32g4xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32g4xx_hal_adc_ex.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32g4xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32g4xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32g4xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32g4xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32g4xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32g4xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32g4xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32g4xx_hal_comp.h
  • IS_CORDIC_DMA_DIRECTION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_FUNCTION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_INSIZE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_NBREAD : stm32g4xx_hal_cordic.h
  • IS_CORDIC_NBWRITE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_OUTSIZE : stm32g4xx_hal_cordic.h
  • IS_CORDIC_PRECISION : stm32g4xx_hal_cordic.h
  • IS_CORDIC_SCALE : stm32g4xx_hal_cordic.h
  • IS_CRC_INPUTDATA_FORMAT : stm32g4xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32g4xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32g4xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32g4xx_hal_crc.h
  • IS_DAC_ALIGN : stm32g4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32g4xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32g4xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32g4xx_hal_dac.h
  • IS_DAC_HIGH_FREQUENCY_MODE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_HOLDTIME : stm32g4xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32g4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32g4xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32g4xx_hal_dac.h
  • IS_DAC_RESET_DATA : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAMPLEANDHOLD : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32g4xx_hal_dac_ex.h
  • IS_DAC_SAWTOOTH_POLARITY : stm32g4xx_hal_dac_ex.h
  • IS_DAC_STEP_DATA : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER2 : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32g4xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32g4xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32g4xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32g4xx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32g4xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32g4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32g4xx_hal_dma.h
  • IS_DMA_MODE : stm32g4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32g4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32g4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32g4xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32g4xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32g4xx_hal_dma_ex.h
  • IS_EXTI_CB : stm32g4xx_hal_exti.h
  • IS_EXTI_CONFIG_LINE : stm32g4xx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32g4xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32g4xx_hal_exti.h
  • IS_EXTI_LINE : stm32g4xx_hal_exti.h
  • IS_EXTI_MODE : stm32g4xx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32g4xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32g4xx_hal_exti.h
  • IS_FDCAN_BRS : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT_GROUP : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32g4xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION_LIST : stm32g4xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32g4xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32g4xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32g4xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_OTP_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_PAGE : stm32g4xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32g4xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32g4xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32g4xx_hal_flash.h
  • IS_FMAC_BUFFER_ACCESS : stm32g4xx_hal_fmac.h
  • IS_FMAC_CLIP_STATE : stm32g4xx_hal_fmac.h
  • IS_FMAC_FILTER_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_N_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_N_M_LOAD_FUNCTION : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_P : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_Q : stm32g4xx_hal_fmac.h
  • IS_FMAC_PARAM_R : stm32g4xx_hal_fmac.h
  • IS_FMAC_THRESHOLD : stm32g4xx_hal_fmac.h
  • IS_FMAC_THRESHOLD_APPLICABLE : stm32g4xx_hal_fmac.h
  • IS_GPIO_AF : stm32g4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32g4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32g4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32g4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32g4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32g4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32g4xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32g4xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32g4xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32g4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32g4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32g4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32g4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32g4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g4xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32g4xx_hal_i2s.h
  • IS_I2S_CPOL : stm32g4xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32g4xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32g4xx_hal_i2s.h
  • IS_I2S_MODE : stm32g4xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32g4xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32g4xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32g4xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32g4xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32g4xx_hal_irda.h
  • IS_IRDA_MODE : stm32g4xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32g4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32g4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32g4xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32g4xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32g4xx_hal_irda.h
  • IS_IRDA_STATE : stm32g4xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32g4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32g4xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32g4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32g4xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32g4xx_hal_iwdg.h
  • IS_LL_ADC_COMMON_CLOCK : stm32g4xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32g4xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32g4xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32g4xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32g4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32g4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32g4xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32g4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32g4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32g4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE2 : stm32g4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32g4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32g4xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32g4xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32g4xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32g4xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32g4xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32g4xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32g4xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32g4xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32g4xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32g4xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32g4xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32g4xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32g4xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32g4xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32g4xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32g4xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32g4xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32g4xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32g4xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32g4xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32g4xx_ll_lpuart.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32g4xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32g4xx_ll_opamp.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_FDCAN_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_UART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32g4xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32g4xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32g4xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32g4xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32g4xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32g4xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32g4xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32g4xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32g4xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32g4xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32g4xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32g4xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32g4xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_AFMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_AFMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32g4xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32g4xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32g4xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32g4xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32g4xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32g4xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32g4xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32g4xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32g4xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32g4xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32g4xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32g4xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32g4xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32g4xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32g4xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32g4xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32g4xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32g4xx_ll_utils.c
  • IS_LPTIM_CLOCK_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32g4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32g4xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32g4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32g4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32g4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32g4xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32g4xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32g4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32g4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32g4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32g4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32g4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32g4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32g4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32g4xx_hal_cortex.h
  • IS_OB_BOOT_LOCK : stm32g4xx_hal_flash.h
  • IS_OB_PCROP_RDP : stm32g4xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32g4xx_hal_flash.h
  • IS_OB_SECMEM_SIZE : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOOT0 : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOOT1 : stm32g4xx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32g4xx_hal_flash.h
  • IS_OB_USER_CCMSRAM_RST : stm32g4xx_hal_flash.h
  • IS_OB_USER_IRHEN : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG_STDBY : stm32g4xx_hal_flash.h
  • IS_OB_USER_IWDG_STOP : stm32g4xx_hal_flash.h
  • IS_OB_USER_NRST_MODE : stm32g4xx_hal_flash.h
  • IS_OB_USER_SHUTDOWN : stm32g4xx_hal_flash.h
  • IS_OB_USER_SRAM_PARITY : stm32g4xx_hal_flash.h
  • IS_OB_USER_STANDBY : stm32g4xx_hal_flash.h
  • IS_OB_USER_STOP : stm32g4xx_hal_flash.h
  • IS_OB_USER_SWBOOT0 : stm32g4xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32g4xx_hal_flash.h
  • IS_OB_USER_WWDG : stm32g4xx_hal_flash.h
  • IS_OB_WRPAREA : stm32g4xx_hal_flash.h
  • IS_OPAMP_FACTORYTRIMMING : stm32g4xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32g4xx_hal_opamp.h
  • IS_OPAMP_PGACONNECT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_SEC_INVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_SEC_NONINVERTING_INPUT : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TIMERCONTROLLED_MUXMODE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32g4xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32g4xx_hal_opamp.h
  • IS_OPAMP_VREF : stm32g4xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32g4xx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32g4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32g4xx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32g4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32g4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32g4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32g4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32g4xx_hal_pwr_ex.h
  • IS_RCC_ADC12CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32g4xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32g4xx_hal_rcc.h
  • IS_RCC_HSE : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32g4xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_I2SCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32g4xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32g4xx_hal_rcc.h
  • IS_RCC_LSI : stm32g4xx_hal_rcc.h
  • IS_RCC_MCO : stm32g4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32g4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32g4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32g4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32g4xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_SAI1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32g4xx_hal_rcc.h
  • IS_RCC_UART4CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32g4xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32g4xx_hal_rng.h
  • IS_RNG_FLAG : stm32g4xx_hal_rng.h
  • IS_RNG_IT : stm32g4xx_hal_rng.h
  • IS_RTC_ALARM : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32g4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32g4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32g4xx_hal_rtc.h
  • IS_RTC_BKP : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32g4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32g4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32g4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32g4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32g4xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_LOW_POWER_CALIB : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32g4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32g4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32g4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32g4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32g4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32g4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMPONTAMPER_DETECTION : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32g4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32g4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32g4xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32g4xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32g4xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32g4xx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32g4xx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32g4xx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32g4xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32g4xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32g4xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32g4xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32g4xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32g4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32g4xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32g4xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32g4xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32g4xx_hal_smbus.h
  • IS_SMBUS_FASTMODEPLUS : stm32g4xx_hal_smbus_ex.h
  • IS_SMBUS_GENERAL_CALL : stm32g4xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32g4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32g4xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32g4xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32g4xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32g4xx_hal_spi.h
  • IS_SPI_CPHA : stm32g4xx_hal_spi.h
  • IS_SPI_CPOL : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32g4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32g4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32g4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32g4xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32g4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32g4xx_hal_spi.h
  • IS_SPI_MODE : stm32g4xx_hal_spi.h
  • IS_SPI_NSS : stm32g4xx_hal_spi.h
  • IS_SPI_NSSP : stm32g4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32g4xx_hal_spi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32g4xx_hal.h
  • IS_SYSCFG_CCMSRAMWRP_PAGE : stm32g4xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32g4xx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32g4xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32g4xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32g4xx_hal_cortex.h
  • IS_TICKFREQ : stm32g4xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_AFMODE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_AFMODE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32g4xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32g4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_CCX_CHANNEL : stm32g4xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32g4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_ENCODERINDEX_DIRECTION : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_FILTER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_POLARITY : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_POSITION : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINDEX_PRESCALER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32g4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32g4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32g4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_LOCK_LEVEL : stm32g4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OC_CHANNEL_MODE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_OC_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32g4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32g4xx_hal_tim.h
  • IS_TIM_PERIOD : stm32g4xx_hal_tim.h
  • IS_TIM_PULSEONCOMPARE_CHANNEL : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_WIDTH : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER : stm32g4xx_hal_tim_ex.h
  • IS_TIM_PWM_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_REMAP : stm32g4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32g4xx_hal_tim.h
  • IS_TIM_SLAVE_PRELOAD_SOURCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32g4xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32g4xx_hal_tim.h
  • IS_TIM_TISEL : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TISEL_TIX_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGER_INSTANCE : stm32g4xx_hal_tim_ex.h
  • IS_TIM_TRIGGERFILTER : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32g4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32g4xx_hal_tim.h
  • IS_TIM_UIFREMAP_MODE : stm32g4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32g4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32g4xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32g4xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32g4xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32g4xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32g4xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32g4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32g4xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32g4xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32g4xx_hal_uart.h
  • IS_UART_DMA_RX : stm32g4xx_hal_uart.h
  • IS_UART_DMA_TX : stm32g4xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32g4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32g4xx_hal_uart.h
  • IS_UART_LIN : stm32g4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32g4xx_hal_uart.h
  • IS_UART_MODE : stm32g4xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32g4xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32g4xx_hal_uart.h
  • IS_UART_OVERRUN : stm32g4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32g4xx_hal_uart.h
  • IS_UART_PARITY : stm32g4xx_hal_uart.h
  • IS_UART_PRESCALER : stm32g4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32g4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32g4xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32g4xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32g4xx_hal_uart_ex.h
  • IS_UART_STATE : stm32g4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32g4xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32g4xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32g4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32g4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32g4xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32g4xx_hal_usart.h
  • IS_USART_CLOCK : stm32g4xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32g4xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32g4xx_hal_usart.h
  • IS_USART_MODE : stm32g4xx_hal_usart.h
  • IS_USART_NSS : stm32g4xx_hal_usart_ex.h
  • IS_USART_PARITY : stm32g4xx_hal_usart.h
  • IS_USART_PHASE : stm32g4xx_hal_usart.h
  • IS_USART_POLARITY : stm32g4xx_hal_usart.h
  • IS_USART_PRESCALER : stm32g4xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32g4xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32g4xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32g4xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32g4xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32g4xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32g4xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32g4xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32g4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32g4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32g4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32g4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32g4xx_hal_iwdg.h
  • IWDG_KERNEL_UPDATE_FLAGS : stm32g4xx_hal_iwdg.c
  • IWDG_KEY_ENABLE : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32g4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32g4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32g4xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32g4xx_hal_iwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- l -

  • LL_ADC_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP4_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VOPAMP6_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_2SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_3SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_4SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_5SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_6SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_7SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_8SAMPLES : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_FILTERING_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32g4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32g4xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR_ADC5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP1 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP3_ADC2 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP3_ADC3 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP4 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP5 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VOPAMP6 : stm32g4xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32g4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32g4xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32g4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32g4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32g4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_LPTIM_OUT : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM16_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32g4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32g4xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32g4xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32g4xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32g4xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32g4xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32g4xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SATURATION_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SATURATION_ENABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SIGN_NEGATIVE : stm32g4xx_ll_adc.h
  • LL_ADC_OFFSET_SIGN_POSITIVE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32g4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32g4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32g4xx_ll_adc.h
  • LL_ADC_ReadReg : stm32g4xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32g4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_BULB : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_NORMAL : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_LPTIM_OUT : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32g4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32g4xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 : stm32g4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_DEFAULT : stm32g4xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32g4xx_ll_adc.h
  • LL_ADC_TEMPERATURE_CALC_ERROR : stm32g4xx_ll_adc.h
  • LL_ADC_WriteReg : stm32g4xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CORDIC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FMAC : stm32g4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC12 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_CCM : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DAC1 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_DAC3 : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOF : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOG : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32g4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SRAM2 : stm32g4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_FDCAN : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTCAPB : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32g4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32g4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_UCPD1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32g4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32g4xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM20_OC5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM4_OC3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 : stm32g4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 : stm32g4xx_ll_comp.h
  • LL_COMP_DELAY_STARTUP_US : stm32g4xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_10MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_20MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_30MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_40MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_50MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_60MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_70MV : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32g4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC2_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC3_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC3_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC4_CH1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC4_CH2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32g4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32g4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32g4xx_ll_comp.h
  • LL_COMP_ReadReg : stm32g4xx_ll_comp.h
  • LL_COMP_WriteReg : stm32g4xx_ll_comp.h
  • LL_CORDIC_DMA_REG_DATA_IN : stm32g4xx_ll_cordic.h
  • LL_CORDIC_DMA_REG_DATA_OUT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FLAG_RRDY : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_ARCTANGENT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_COSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HARCTANGENT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HCOSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_HSINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_MODULUS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_NATURALLOG : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_PHASE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_SINE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_FUNCTION_SQUAREROOT : stm32g4xx_ll_cordic.h
  • LL_CORDIC_INSIZE_16BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_INSIZE_32BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_IT_IEN : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBREAD_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBREAD_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBWRITE_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_NBWRITE_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_OUTSIZE_16BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_OUTSIZE_32BITS : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_10CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_11CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_12CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_13CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_14CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_15CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_1CYCLE : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_2CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_3CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_4CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_5CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_6CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_7CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_8CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_PRECISION_9CYCLES : stm32g4xx_ll_cordic.h
  • LL_CORDIC_ReadReg : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_0 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_1 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_2 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_3 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_4 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_5 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_6 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_SCALE_7 : stm32g4xx_ll_cordic.h
  • LL_CORDIC_WriteReg : stm32g4xx_ll_cordic.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32g4xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32g4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32g4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32g4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32g4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32g4xx_ll_crc.h
  • LL_CRC_ReadReg : stm32g4xx_ll_crc.h
  • LL_CRC_WriteReg : stm32g4xx_ll_crc.h
  • LL_CRS_CR_ERRIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32g4xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32g4xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32g4xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32g4xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32g4xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32g4xx_ll_crs.h
  • LL_CRS_ReadReg : stm32g4xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32g4xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32g4xx_ll_crs.h
  • LL_CRS_WriteReg : stm32g4xx_ll_crs.h
  • LL_DAC_CHANNEL_1 : stm32g4xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32g4xx_ll_dac.h
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32g4xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DAC1RDY : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DAC2RDY : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DORSTAT1 : stm32g4xx_ll_dac.h
  • LL_DAC_FLAG_DORSTAT2 : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ : stm32g4xx_ll_dac.h
  • LL_DAC_HIGH_FREQ_MODE_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32g4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32g4xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32g4xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32g4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32g4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32g4xx_ll_dac.h
  • LL_DAC_ReadReg : stm32g4xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32g4xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32g4xx_ll_dac.h
  • LL_DAC_SAWTOOTH_POLARITY_DECREMENT : stm32g4xx_ll_dac.h
  • LL_DAC_SAWTOOTH_POLARITY_INCREMENT : stm32g4xx_ll_dac.h
  • LL_DAC_SIGNED_FORMAT_DISABLE : stm32g4xx_ll_dac.h
  • LL_DAC_SIGNED_FORMAT_ENABLE : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE10 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO1 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO2 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_HRTIM_TRGO3 : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32g4xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH : stm32g4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32g4xx_ll_dac.h
  • LL_DAC_WriteReg : stm32g4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32g4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32g4xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32g4xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32g4xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32g4xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32g4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32g4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32g4xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32g4xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32g4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32g4xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32g4xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32g4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32g4xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32g4xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32g4xx_ll_dma.h
  • LL_DMA_ReadReg : stm32g4xx_ll_dma.h
  • LL_DMA_WriteReg : stm32g4xx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_IN : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_CORDIC_READ : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_CORDIC_WRITE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC2_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC3_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC3_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC4_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC4_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_FMAC_READ : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_FMAC_WRITE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_A : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_B : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_C : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_D : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_E : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_F : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_HRTIM1_M : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_QSPI : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_A : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_B : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM20_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM5_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM6_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM7_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_CH4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_COM : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_TRIG : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM8_UP : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART4_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART4_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART5_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UART5_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_RX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_TX : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32g4xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32g4xx_ll_dmamux.h
  • LL_EXTI_LINE_0 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32g4xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32g4xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32g4xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32g4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32g4xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32g4xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_10 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_11 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_12 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_13 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_14 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_15 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_5 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_6 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_7 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_8 : stm32g4xx_ll_system.h
  • LL_FLASH_LATENCY_9 : stm32g4xx_ll_system.h
  • LL_FMAC_CR_OVFLIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_RIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_SATIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_UNFLIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_CR_WIEN : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_CONVO_FIR : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_IIR_DIRECT_FORM_1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_X1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_X2 : stm32g4xx_ll_fmac.h
  • LL_FMAC_FUNC_LOAD_Y : stm32g4xx_ll_fmac.h
  • LL_FMAC_PROCESSING_START : stm32g4xx_ll_fmac.h
  • LL_FMAC_PROCESSING_STOP : stm32g4xx_ll_fmac.h
  • LL_FMAC_ReadReg : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_OVFL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_SAT : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_UNFL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_X1FULL : stm32g4xx_ll_fmac.h
  • LL_FMAC_SR_YEMPTY : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_0_THRESHOLD_1 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_1_THRESHOLD_2 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_2_THRESHOLD_4 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WM_3_THRESHOLD_8 : stm32g4xx_ll_fmac.h
  • LL_FMAC_WriteReg : stm32g4xx_ll_fmac.h
  • LL_GPIO_AF_0 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32g4xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32g4xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32g4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32g4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32g4xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32g4xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32g4xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32g4xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32g4xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32g4xx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32g4xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32g4xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32g4xx_ll_cortex.h
  • LL_I2C_ACK : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32g4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32g4xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32g4xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32g4xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32g4xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32g4xx_ll_i2c.h
  • LL_I2C_NACK : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32g4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32g4xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32g4xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32g4xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32g4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32g4xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32g4xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32g4xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32g4xx_ll_spi.h
  • LL_I2S_CR2_ERRIE : stm32g4xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32g4xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32g4xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32g4xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32g4xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32g4xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32g4xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32g4xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32g4xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32g4xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32g4xx_ll_spi.h
  • LL_I2S_ReadReg : stm32g4xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32g4xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32g4xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32g4xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32g4xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32g4xx_ll_spi.h
  • LL_I2S_WriteReg : stm32g4xx_ll_spi.h
  • LL_IWDG_KEY_ENABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32g4xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32g4xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32g4xx_ll_iwdg.h
  • LL_LPTIM_CLK_FILTER_2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32g4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP4 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32g4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32g4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32g4xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32g4xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32g4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32g4xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32g4xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32g4xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32g4xx_ll_utils.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32g4xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32g4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32g4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32g4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32g4xx_ll_cortex.h
  • LL_OPAMP_DELAY_STARTUP_US : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_PGA_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_DISABLE : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM1_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM20_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_MUX_TIM8_CH6 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO1_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO2 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO2_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO3 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO3_SEC : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INTERNAL_OUPUT_DISABLED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_INTERNAL_OUPUT_ENABLED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_BIAS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA_IO0_IO1_BIAS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_HIGHSPEED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32g4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMALSPEED : stm32g4xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_FACTORY : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA : stm32g4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32g4xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32g4xx_ll_opamp.h
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32g4xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableDeadBatteryPD : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_DisableUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableDeadBatteryPD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_EnableUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32g4xx_ll_pwr.h
  • LL_PWR_GPIO_G : stm32g4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOSF : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBDeadBattery : stm32g4xx_ll_pwr.h
  • LL_PWR_IsEnabledUSBStandByModePD : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32g4xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_ADC : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_COMP : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_FASTDAC : stm32g4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_OPAMP_DAC : stm32g4xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32g4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32g4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO2 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO4 : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32g4xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32g4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32g4xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32g4xx_ll_pwr.h
  • LL_RCC_ADC12_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_ADC12_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_PIN : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_I2S_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32g4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32g4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_10 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_11 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_12 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_13 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_14 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_15 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_9 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_QUADSPI_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32g4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32g4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32g4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32g4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32g4xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32g4xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32g4xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32g4xx_ll_rng.h
  • LL_RNG_CR_IE : stm32g4xx_ll_rng.h
  • LL_RNG_ReadReg : stm32g4xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32g4xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32g4xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32g4xx_ll_rng.h
  • LL_RNG_WriteReg : stm32g4xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32g4xx_ll_rtc.h
  • LL_RTC_BKP_NUMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32g4xx_ll_rtc.h
  • LL_RTC_CSR_ALRAF : stm32g4xx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32g4xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32g4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32g4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_ALRAWF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_ALRBWF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32g4xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32g4xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32g4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32g4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32g4xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32g4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32g4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP4 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP5 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP6 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32g4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32g4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32g4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32g4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32g4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32g4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32g4xx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32g4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32g4xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32g4xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32g4xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32g4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32g4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32g4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32g4xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32g4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32g4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32g4xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32g4xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32g4xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32g4xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32g4xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32g4xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32g4xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32g4xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32g4xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32g4xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32g4xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32g4xx_ll_spi.h
  • LL_SPI_ReadReg : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32g4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32g4xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32g4xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32g4xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32g4xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32g4xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32g4xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32g4xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32g4xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32g4xx_ll_spi.h
  • LL_SPI_WriteReg : stm32g4xx_ll_spi.h
  • LL_SYSCFG_BANKMODE_BANK1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_BANKMODE_BANK2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE0 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE4 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE5 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_CCMSRAMWRP_PAGE9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32g4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32g4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32g4xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32g4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32g4xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32g4xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g4xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32g4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32g4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32g4xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_INPUT : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_INPUT : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32g4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32g4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4N : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32g4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32g4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_DIRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_IDXIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_IERRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_TERRIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32g4xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DTR2 : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ECR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_19TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_20TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_21TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_22TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_23TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_24TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_25TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_26TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X1_TI1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X1_TI2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32g4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32g4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32g4xx_ll_tim.h
  • LL_TIM_HSE_32_NOT_REQUEST : stm32g4xx_ll_tim.h
  • LL_TIM_HSE_32_REQUEST : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32g4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_ALL : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_FIRST_ONLY : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_DOWN_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_POSITION_UP_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_UP : stm32g4xx_ll_tim.h
  • LL_TIM_INDEX_UP_DOWN : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32g4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32g4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ASYMMETRIC_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_ASYMMETRIC_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_DIRECTION_OUTPUT : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PULSE_ON_COMPARE : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32g4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32g4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32g4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32g4xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X1 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X128 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X16 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X2 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X32 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X4 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X64 : stm32g4xx_ll_tim.h
  • LL_TIM_PWPRSC_X8 : stm32g4xx_ll_tim.h
  • LL_TIM_ReadReg : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_GATEDRESET : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32g4xx_ll_tim.h
  • LL_TIM_SMSPS_INDEX : stm32g4xx_ll_tim.h
  • LL_TIM_SMSPS_TIMUPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_DIRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_IDXF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_IERRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_TERRF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32g4xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_HSE_32 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC_WK : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_LSI : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_RTC_WK : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_LSE : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_TIM3_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_ETRSOURCE_TIM4_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_TIM2_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_ETRSOURCE_TIM4_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_ETRSOURCE_TIM3_ETR : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM4_TI4_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_ETRSOURCE_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP2 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP3 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP4 : stm32g4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_GPIO : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_ENCODERCLK : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32g4xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR10 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR11 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR4 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR5 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR6 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR8 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_ITR9 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32g4xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32g4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32g4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32g4xx_ll_tim.h
  • LL_TIM_WriteReg : stm32g4xx_ll_tim.h
  • LL_UCPD_CCENABLE_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC1CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_NONE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_EOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_FRSEVT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXHRSTDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXMSGEND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXNE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXORDDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_RXOVR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXIS : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGABT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TXUND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_HARD_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_CABLERST : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_HARDRST : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV16 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV4 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV8 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ReadReg : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_1_5A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_3_0A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_DEFAULT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_NONE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ROLE_SNK : stm32g4xx_ll_ucpd.h
  • LL_UCPD_ROLE_SRC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RST1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RST2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXMODE_BIST_TEST_DATA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXMODE_NORMAL : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2_DEBUG : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VOPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP15A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP30A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VOPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP15A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP30A : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_FRSEVT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXERR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXHRSTDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXMSGEND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXNE : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXORDDET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_RXOVR : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXIS : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGABT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGDISC : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGSENT : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TXUND : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_OPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRD : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_OPEN : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRA : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRD : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SYNC1 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SYNC2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_SYNC3 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_BIST_CARRIER2 : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_CABLE_RESET : stm32g4xx_ll_ucpd.h
  • LL_UCPD_TXMODE_NORMAL : stm32g4xx_ll_ucpd.h
  • LL_UCPD_WriteReg : stm32g4xx_ll_ucpd.h
  • LL_USART_ADDRESS_DETECT_4B : stm32g4xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32g4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32g4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32g4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32g4xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32g4xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32g4xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32g4xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32g4xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32g4xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32g4xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32g4xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32g4xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32g4xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32g4xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32g4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32g4xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32g4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32g4xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32g4xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32g4xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32g4xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32g4xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_FE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_NE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_PE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TC : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32g4xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32g4xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32g4xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32g4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32g4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32g4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32g4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32g4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32g4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32g4xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32g4xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32g4xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32g4xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32g4xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32g4xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32g4xx_ll_usart.h
  • LL_USART_ReadReg : stm32g4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32g4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32g4xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32g4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32g4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32g4xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32g4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32g4xx_ll_usart.h
  • LL_USART_WriteReg : stm32g4xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32g4xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP128 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP32 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48_EBIKE : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_TFBGA100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA100 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN32 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN48 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP49 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP64 : stm32g4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP81 : stm32g4xx_ll_utils.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32g4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32g4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE2 : stm32g4xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32g4xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32g4xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32g4xx_ll_wwdg.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32g4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32g4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32g4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32g4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32g4xx_hal_lptim.h
  • LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32g4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP3 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP4 : stm32g4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32g4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32g4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32g4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32g4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32g4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32g4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32g4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32g4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32g4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32g4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_10 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_11 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_12 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_8 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_9 : stm32g4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32g4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32g4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32g4xx_hal_lptim.h
  • LPUART_BRR_MASK : stm32g4xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32g4xx_hal_uart.c
  • LPUART_BRR_MIN : stm32g4xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32g4xx_ll_lpuart.h
  • LPUART_DEFAULT_BAUDRATE : stm32g4xx_ll_lpuart.c
  • LPUART_LPUARTDIV_FREQ_MUL : stm32g4xx_ll_lpuart.h
  • LSCO_GPIO_PORT : stm32g4xx_hal_rcc_ex.c
  • LSCO_PIN : stm32g4xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32g4xx_hal_conf.h
  • LSE_VALUE : stm32g4xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c
  • LSI_VALUE : stm32g4xx_hal_conf.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- m -

  • MAX_FILTER_DATA_SIZE_TO_HANDLE : stm32g4xx_hal_fmac.c
  • MAX_NBYTE_SIZE : stm32g4xx_hal_i2c.c , stm32g4xx_hal_smbus.c
  • MAX_PRELOAD_INDEX : stm32g4xx_hal_fmac.c
  • MEMRMP_OFFSET : stm32g4xx_hal.c
  • MODE_AF : stm32g4xx_hal_gpio.h
  • MODE_ANALOG : stm32g4xx_hal_gpio.h
  • MODE_INPUT : stm32g4xx_hal_gpio.h
  • MODE_OUTPUT : stm32g4xx_hal_gpio.h
  • MPU_ACCESS_BUFFERABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32g4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32g4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32g4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32g4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32g4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32g4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32g4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32g4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32g4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32g4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32g4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32g4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32g4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32g4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32g4xx_hal_cortex.h
  • MPU_TEX_LEVEL4 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- n -

  • NVIC_PRIORITYGROUP_0 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32g4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- o -

  • OB_BOOT0_FROM_OB : stm32g4xx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32g4xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32g4xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32g4xx_hal_flash.h
  • OB_BOOT_LOCK_DISABLE : stm32g4xx_hal_flash.h
  • OB_BOOT_LOCK_ENABLE : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32g4xx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32g4xx_hal_flash.h
  • OB_CCMSRAM_RST_ERASE : stm32g4xx_hal_flash.h
  • OB_CCMSRAM_RST_NOT_ERASE : stm32g4xx_hal_flash.h
  • OB_IRH_DISABLE : stm32g4xx_hal_flash.h
  • OB_IRH_ENABLE : stm32g4xx_hal_flash.h
  • OB_IWDG_HW : stm32g4xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32g4xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32g4xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32g4xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32g4xx_hal_flash.h
  • OB_IWDG_SW : stm32g4xx_hal_flash.h
  • OB_nBOOT0_RESET : stm32g4xx_hal_flash.h
  • OB_nBOOT0_SET : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_GPIO : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_INPUT_ONLY : stm32g4xx_hal_flash.h
  • OB_NRST_MODE_INPUT_OUTPUT : stm32g4xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32g4xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32g4xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32g4xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32g4xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32g4xx_hal_flash.h
  • OB_SRAM_PARITY_DISABLE : stm32g4xx_hal_flash.h
  • OB_SRAM_PARITY_ENABLE : stm32g4xx_hal_flash.h
  • OB_STANDBY_NORST : stm32g4xx_hal_flash.h
  • OB_STANDBY_RST : stm32g4xx_hal_flash.h
  • OB_STOP_NORST : stm32g4xx_hal_flash.h
  • OB_STOP_RST : stm32g4xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32g4xx_hal_flash.h
  • OB_USER_CCMSRAM_RST : stm32g4xx_hal_flash.h
  • OB_USER_IRHEN : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32g4xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32g4xx_hal_flash.h
  • OB_USER_nBOOT0 : stm32g4xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32g4xx_hal_flash.h
  • OB_USER_NRST_MODE : stm32g4xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32g4xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32g4xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32g4xx_hal_flash.h
  • OB_USER_nSWBOOT0 : stm32g4xx_hal_flash.h
  • OB_USER_SRAM_PE : stm32g4xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32g4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32g4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32g4xx_hal_flash.h
  • OB_WWDG_HW : stm32g4xx_hal_flash.h
  • OB_WWDG_SW : stm32g4xx_hal_flash.h
  • OCREF_CLEAR_SELECT_Msk : stm32g4xx_ll_tim.h
  • OCREF_CLEAR_SELECT_Pos : stm32g4xx_ll_tim.h
  • OPAMP_CSR_RESET_CHECK_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32g4xx_hal_opamp.c
  • OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32g4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32g4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32g4xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_INPUT_INVERTING : stm32g4xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32g4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO2 : stm32g4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO3 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_CONNECT_INVERTINGINPUT_NO : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16_OR_MINUS_15 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2_OR_MINUS_1 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_32_OR_MINUS_31 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4_OR_MINUS_3 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_64_OR_MINUS_63 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8_OR_MINUS_7 : stm32g4xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_POWERMODE_HIGHSPEED : stm32g4xx_hal_opamp.h
  • OPAMP_POWERMODE_NORMALSPEED : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_FOLLOWER : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_INVERTINGINPUT_PGA : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_DAC : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO0 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO1 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO2 : stm32g4xx_hal_opamp.h
  • OPAMP_SEC_NONINVERTINGINPUT_IO3 : stm32g4xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32g4xx_hal_opamp.h
  • OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK : stm32g4xx_hal_opamp.c
  • OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE : stm32g4xx_hal_opamp.h
  • OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 : stm32g4xx_hal_opamp.h
  • OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32g4xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32g4xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32g4xx_ll_opamp.h
  • OPAMP_VREF_10VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_3VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_50VDDA : stm32g4xx_hal_opamp.h
  • OPAMP_VREF_90VDDA : stm32g4xx_hal_opamp.h
  • OPTIONBYTE_BOOT_LOCK : stm32g4xx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32g4xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32g4xx_hal_flash.h
  • OPTIONBYTE_SEC : stm32g4xx_hal_flash.h
  • OPTIONBYTE_USER : stm32g4xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32g4xx_hal_flash.h
  • OUTPUT_OD : stm32g4xx_hal_gpio.h
  • OUTPUT_PP : stm32g4xx_hal_gpio.h
  • OUTPUT_TYPE : stm32g4xx_hal_gpio.h
  • OUTPUT_TYPE_Pos : stm32g4xx_hal_gpio.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- p -

  • PACKAGE_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • PCD_CALC_BLK2 : stm32g4xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_BULK_EP_DBUF : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32g4xx_hal_pcd.h
  • PCD_DBL_BUF : stm32g4xx_hal_pcd.h
  • PCD_ENDP0 : stm32g4xx_hal_pcd.h
  • PCD_ENDP1 : stm32g4xx_hal_pcd.h
  • PCD_ENDP2 : stm32g4xx_hal_pcd.h
  • PCD_ENDP3 : stm32g4xx_hal_pcd.h
  • PCD_ENDP4 : stm32g4xx_hal_pcd.h
  • PCD_ENDP5 : stm32g4xx_hal_pcd.h
  • PCD_ENDP6 : stm32g4xx_hal_pcd.h
  • PCD_ENDP7 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32g4xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32g4xx_hal_pcd.h
  • PCD_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_FREE_USER_BUFFER : stm32g4xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32g4xx_hal_pcd.h
  • PCD_MAX : stm32g4xx_hal_pcd.c
  • PCD_MIN : stm32g4xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32g4xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32g4xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32g4xx_hal_pcd.h
  • PCD_RX_DTOG : stm32g4xx_hal_pcd.h
  • PCD_SET_BULK_EP_DBUF : stm32g4xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32g4xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32g4xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32g4xx_hal_pcd.h
  • PCD_SNG_BUF : stm32g4xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32g4xx_hal_pcd.h
  • PCD_TX_DTOG : stm32g4xx_hal_pcd.h
  • PLL_TIMEOUT_VALUE : stm32g4xx_hal_rcc.c , stm32g4xx_hal_rcc_ex.c
  • POLLING_DISABLED : stm32g4xx_hal_fmac.c
  • POLLING_ENABLED : stm32g4xx_hal_fmac.c
  • POLLING_NOT_STOPPED : stm32g4xx_hal_fmac.c
  • POLLING_STOPPED : stm32g4xx_hal_fmac.c
  • PREFETCH_ENABLE : stm32g4xx_hal_conf.h
  • PRELOAD_ACCESS_DMA : stm32g4xx_hal_fmac.c
  • PRELOAD_ACCESS_POLLING : stm32g4xx_hal_fmac.c
  • PVD_FALLING_EDGE : stm32g4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32g4xx_hal_pwr.c
  • PVD_MODE_IT : stm32g4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32g4xx_hal_pwr.c
  • PVM_FALLING_EDGE : stm32g4xx_hal_pwr_ex.c
  • PVM_MODE_EVT : stm32g4xx_hal_pwr_ex.c
  • PVM_MODE_IT : stm32g4xx_hal_pwr_ex.c
  • PVM_RISING_EDGE : stm32g4xx_hal_pwr_ex.c
  • PWR_BATTERY_CHARGING_DISABLE : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32g4xx_hal_pwr.h
  • PWR_EVENT_LINE_PVM1 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM2 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM3 : stm32g4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM4 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32g4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM2 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32g4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO2 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32g4xx_hal_pwr_ex.c
  • PWR_FLAG_VOSF : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32g4xx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32g4xx_hal_pwr_ex.h
  • PWR_GPIO_G : stm32g4xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32g4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32g4xx_hal_pwr.h
  • PWR_PORTF_AVAILABLE_PINS : stm32g4xx_hal_pwr_ex.c
  • PWR_PORTG_AVAILABLE_PINS : stm32g4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32g4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32g4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32g4xx_hal_pwr.h
  • PWR_PVM_1 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_2 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_4 : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32g4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1_BOOST : stm32g4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32g4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32g4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32g4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32g4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32g4xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32g4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32g4xx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32g4xx_hal_pwr_ex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- r -

  • RCC_ADC12CLKSOURCE_NONE : stm32g4xx_hal_rcc_ex.h
  • RCC_ADC12CLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_ADC12CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_ALL : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32g4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32g4xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32g4xx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32g4xx_hal_rcc.h
  • RCC_EXTI_LINE_LSECSS : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_HSE : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32g4xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32g4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32g4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32g4xx_hal_rcc.h
  • RCC_GET_MCO_GPIO_AF : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_INDEX : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_PIN : stm32g4xx_hal_rcc.c
  • RCC_GET_MCO_GPIO_PORT : stm32g4xx_hal_rcc.c
  • RCC_HCLK_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32g4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSE_ON : stm32g4xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSI48_ON : stm32g4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32g4xx_hal_rcc.h
  • RCC_HSI_ON : stm32g4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32g4xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_EXT : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_I2SCLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32g4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32g4xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32g4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32g4xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32g4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32g4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32g4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32g4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32g4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32g4xx_hal_rcc.h
  • RCC_LSE_OFF : stm32g4xx_hal_rcc.h
  • RCC_LSE_ON : stm32g4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32g4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32g4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32g4xx_hal_rcc.h
  • RCC_LSI_ON : stm32g4xx_hal_rcc.h
  • RCC_MCO : stm32g4xx_hal_rcc.h
  • RCC_MCO1 : stm32g4xx_hal_rcc.h
  • RCC_MCO1_INDEX : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOAF_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOAF_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOPORT_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_GPIOPORT_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_INDEX_MASK : stm32g4xx_hal_rcc.h
  • RCC_MCO_INDEX_POS : stm32g4xx_hal_rcc.h
  • RCC_MCO_PA8 : stm32g4xx_hal_rcc.h
  • RCC_MCO_PG10 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32g4xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32g4xx_hal_rcc.h
  • RCC_OFFSET_CCIPR : stm32g4xx_ll_rcc.h
  • RCC_OFFSET_CCIPR2 : stm32g4xx_ll_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32g4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32g4xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC12 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32g4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32g4xx_hal_rcc_ex.h
  • RCC_PLL_48M1CLK : stm32g4xx_hal_rcc.h
  • RCC_PLL_ADCCLK : stm32g4xx_hal_rcc.h
  • RCC_PLL_NONE : stm32g4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32g4xx_hal_rcc.h
  • RCC_PLL_ON : stm32g4xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32g4xx_hal_rcc.c
  • RCC_PLL_SYSCLK : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV10 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV11 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV12 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV13 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV14 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV15 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLM_DIV9 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32g4xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32g4xx_hal_rcc.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32g4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32g4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32g4xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_EXT : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32g4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32g4xx_hal_rcc.h
  • RCC_UART4CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32g4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32g4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32g4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32g4xx_hal_rcc_ex.h
  • RNG_CED_DISABLE : stm32g4xx_hal_rng.h
  • RNG_CED_ENABLE : stm32g4xx_hal_rng.h
  • RNG_FLAG_CECS : stm32g4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32g4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32g4xx_hal_rng.h
  • RNG_IT_CEI : stm32g4xx_hal_rng.h
  • RNG_IT_DRDY : stm32g4xx_hal_rng.h
  • RNG_IT_SEI : stm32g4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32g4xx_hal_rng.c
  • RTC_ALARM_A : stm32g4xx_hal_rtc.h
  • RTC_ALARM_B : stm32g4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32g4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32g4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32g4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32g4xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32g4xx_ll_rtc.c
  • RTC_BKP_DR0 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32g4xx_hal_rtc_ex.h
  • RTC_BKP_NUMBER : stm32g4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32g4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32g4xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32g4xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32g4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32g4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TAMPER_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TIMESTAMP_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32g4xx_hal_rtc.h
  • RTC_FLAG_INT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_ITSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_MASK : stm32g4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32g4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32g4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32g4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32g4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32g4xx_hal_rtc.h
  • RTC_ICSR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32g4xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32g4xx_ll_rtc.c
  • RTC_INT_TAMPER_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32g4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32g4xx_hal_rtc.h
  • RTC_IT_INT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_4 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_5 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_6 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_7 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_8 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TAMP_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32g4xx_hal_rtc.h
  • RTC_IT_WUT : stm32g4xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32g4xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32g4xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32g4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32g4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32g4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32g4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32g4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32g4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32g4xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32g4xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32g4xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32g4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32g4xx_hal_rtc.h
  • RTC_RSF_MASK : stm32g4xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32g4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32g4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32g4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32g4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32g4xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32g4xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32g4xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32g4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32g4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32g4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32g4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32g4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32g4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32g4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32g4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32g4xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32g4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32g4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32g4xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32g4xx_hal_usart_ex.c , stm32g4xx_hal_smartcard_ex.c , stm32g4xx_hal_uart_ex.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- s -

  • SAI_AC97_FRAME_LENGTH : stm32g4xx_hal_sai.c
  • SAI_AC97_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32g4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32g4xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32g4xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32g4xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32g4xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32g4xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32g4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32g4xx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32g4xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32g4xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32g4xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32g4xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32g4xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32g4xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32g4xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32g4xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32g4xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32g4xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32g4xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32g4xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32g4xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32g4xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32g4xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32g4xx_hal_sai.h
  • SAI_IT_AFSDET : stm32g4xx_hal_sai.h
  • SAI_IT_CNRDY : stm32g4xx_hal_sai.h
  • SAI_IT_FREQ : stm32g4xx_hal_sai.h
  • SAI_IT_LFSDET : stm32g4xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32g4xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32g4xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32g4xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32g4xx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32g4xx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32g4xx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32g4xx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32g4xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32g4xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32g4xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32g4xx_hal_sai.h
  • SAI_MONOMODE : stm32g4xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32g4xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32g4xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32g4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32g4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PCM_LONG : stm32g4xx_hal_sai.h
  • SAI_PCM_SHORT : stm32g4xx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32g4xx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32g4xx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32g4xx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32g4xx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32g4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32g4xx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32g4xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32g4xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32g4xx_hal_sai.h
  • SAI_SPDIF_FRAME_LENGTH : stm32g4xx_hal_sai.c
  • SAI_SPDIF_PROTOCOL : stm32g4xx_hal_sai.h
  • SAI_STEREOMODE : stm32g4xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32g4xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32g4xx_hal_sai.h
  • SAI_ULAW_1CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32g4xx_hal_sai.h
  • SAI_ZERO_VALUE : stm32g4xx_hal_sai.h
  • SCSR_CCMER_BB : stm32g4xx_hal.c
  • SCSR_OFFSET : stm32g4xx_hal.c
  • SLAVE_ADDR_MSK : stm32g4xx_hal_i2c.c
  • SLAVE_ADDR_SHIFT : stm32g4xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_CR_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32g4xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_DISABLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ISR_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32g4xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32g4xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32g4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32g4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_STOPBITS_0_5 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TC : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32g4xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_smartcard_ex.h
  • SMARTCARD_WORDLENGTH_9B : stm32g4xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32g4xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32g4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32g4xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32g4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_FASTMODEPLUS_I2C1 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C2 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C3 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C4 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB6 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB7 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB8 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB9 : stm32g4xx_hal_smbus_ex.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32g4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32g4xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32g4xx_hal_smbus.h
  • SMBUS_FMP_NOT_SUPPORTED : stm32g4xx_hal_smbus_ex.h
  • SMBUS_GENERALCALL_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32g4xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32g4xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32g4xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32g4xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32g4xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32g4xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_RX : stm32g4xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TX : stm32g4xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32g4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32g4xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32g4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32g4xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32g4xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32g4xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32g4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32g4xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32g4xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32g4xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32g4xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32g4xx_hal_smbus.h
  • SPI_1LINE_RX : stm32g4xx_hal_spi.h
  • SPI_1LINE_TX : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32g4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32g4xx_hal_spi.h
  • SPI_CHECK_FLAG : stm32g4xx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32g4xx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32g4xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32g4xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32g4xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32g4xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32g4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32g4xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32g4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32g4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32g4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32g4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32g4xx_hal_spi.h
  • SPI_FIFO_SIZE : stm32g4xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32g4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32g4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32g4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32g4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32g4xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32g4xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32g4xx_hal_spi.h
  • SPI_FLAG_MASK : stm32g4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32g4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32g4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32g4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32g4xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32g4xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32g4xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32g4xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32g4xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32g4xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32g4xx_hal_spi.h
  • SPI_IT_ERR : stm32g4xx_hal_spi.h
  • SPI_IT_RXNE : stm32g4xx_hal_spi.h
  • SPI_IT_TXE : stm32g4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32g4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32g4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32g4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32g4xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32g4xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32g4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32g4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32g4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32g4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32g4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32g4xx_hal_spi.h
  • SPI_RESET_CRC : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32g4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32g4xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32g4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32g4xx_hal_spi.h
  • SRAMCAN_FLE_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLE_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLESA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLS_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLS_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_FLSSA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF0SA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_RF1SA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEF_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEF_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TEFSA : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQ_NBR : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQ_SIZE : stm32g4xx_hal_fdcan.c
  • SRAMCAN_TFQSA : stm32g4xx_hal_fdcan.c
  • SYSCFG_BOOT_MAINFLASH : stm32g4xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32g4xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE0 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE1 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE10 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE11 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE12 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE13 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE14 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE15 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE16 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE17 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE18 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE19 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE2 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE20 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE21 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE22 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE23 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE24 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE25 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE26 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE27 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE28 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE29 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE3 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE30 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE31 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE4 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE5 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE6 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE7 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE8 : stm32g4xx_hal.h
  • SYSCFG_CCMSRAMWRP_PAGE9 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32g4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32g4xx_hal.h
  • SYSCFG_FLAG_CCMSRAM_BUSY : stm32g4xx_hal.h
  • SYSCFG_FLAG_SRAM_PE : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32g4xx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32g4xx_hal.h
  • SYSCFG_OFFSET : stm32g4xx_hal.c
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32g4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE2 : stm32g4xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32g4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g4xx_hal_cortex.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32g4xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32g4xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32g4xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32g4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32g4xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32g4xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g4xx_hal_tim.h
  • TIM_BREAK2_AFMODE_INPUT : stm32g4xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g4xx_hal_tim.h
  • TIM_BREAK_AFMODE_INPUT : stm32g4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32g4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32g4xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_REARM_TIMEOUT : stm32g4xx_hal_tim_ex.c
  • TIM_BREAKINPUTSOURCE_BKIN : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32g4xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_CALC_DTS : stm32g4xx_ll_tim.h
  • TIM_CCDMAREQUEST_CC : stm32g4xx_hal_tim.h
  • TIM_CCDMAREQUEST_UPDATE : stm32g4xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32g4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32g4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32g4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32g4xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32g4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_GET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET_ALL : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_GET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET : stm32g4xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET_ALL : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP3 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP4 : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32g4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR10 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR11 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR5 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR6 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR8 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32g4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32g4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32g4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32g4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32g4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32g4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32g4xx_hal_tim.h
  • TIM_DMA_COM : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32g4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32g4xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32g4xx_hal_tim.h
  • TIM_DMABASE_DTR2 : stm32g4xx_hal_tim.h
  • TIM_DMABASE_ECR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_OR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32g4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32g4xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_19TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_20TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_21TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_22TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_23TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_24TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_25TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_26TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32g4xx_hal_tim.h
  • TIM_ENCODERINDEX_DIRECTION_DOWN : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_DIRECTION_UP : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_DIRECTION_UP_DOWN : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POLARITY_INVERTED : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POLARITY_NONINVERTED : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_0 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_00 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_01 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_1 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_10 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_POSITION_11 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV1 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV2 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV4 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINDEX_PRESCALER_DIV8 : stm32g4xx_hal_tim_ex.h
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_X1_TI1 : stm32g4xx_hal_tim.h
  • TIM_ENCODERMODE_X1_TI2 : stm32g4xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32g4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32g4xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32g4xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32g4xx_hal_tim.h
  • TIM_FLAG_COM : stm32g4xx_hal_tim.h
  • TIM_FLAG_DIR : stm32g4xx_hal_tim.h
  • TIM_FLAG_IDX : stm32g4xx_hal_tim.h
  • TIM_FLAG_IERR : stm32g4xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32g4xx_hal_tim.h
  • TIM_FLAG_TERR : stm32g4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32g4xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32g4xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32g4xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32g4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32g4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_IT_BREAK : stm32g4xx_hal_tim.h
  • TIM_IT_CC1 : stm32g4xx_hal_tim.h
  • TIM_IT_CC2 : stm32g4xx_hal_tim.h
  • TIM_IT_CC3 : stm32g4xx_hal_tim.h
  • TIM_IT_CC4 : stm32g4xx_hal_tim.h
  • TIM_IT_COM : stm32g4xx_hal_tim.h
  • TIM_IT_DIR : stm32g4xx_hal_tim.h
  • TIM_IT_IDX : stm32g4xx_hal_tim.h
  • TIM_IT_IERR : stm32g4xx_hal_tim.h
  • TIM_IT_TERR : stm32g4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32g4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32g4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32g4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ASYMMETRIC_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_ASYMMETRIC_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_DIRECTION_OUTPUT : stm32g4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PULSE_ON_COMPARE : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32g4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32g4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32g4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32g4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32g4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32g4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32g4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32g4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32g4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32g4xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32g4xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32g4xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32g4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_GATEDRESET : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32g4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32g4xx_hal_tim.h
  • TIM_SMS_PRELOAD_SOURCE_INDEX : stm32g4xx_hal_tim_ex.h
  • TIM_SMS_PRELOAD_SOURCE_UPDATE : stm32g4xx_hal_tim_ex.h
  • TIM_TI1SELECTION_CH1 : stm32g4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32g4xx_hal_tim.h
  • TIM_TIM15_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_HSE_32 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_MCO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC_WK : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_LSI : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_RTC_WK : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_TIM3_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_TIM4_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI3_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_ADC2_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_TIM2_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_TIM4_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI3_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM3_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_ETR_TIM3_ETR : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI2_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI3_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM4_TI4_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP1 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP3 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP4 : stm32g4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32g4xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32g4xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32g4xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32g4xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32g4xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32g4xx_hal_tim.h
  • TIM_TRGO_ENCODER_CLK : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32g4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32g4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32g4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32g4xx_hal_tim.h
  • TIM_TS_ETRF : stm32g4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR10 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR11 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR5 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR6 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR7 : stm32g4xx_hal_tim.h
  • TIM_TS_ITR8 : stm32g4xx_hal_tim.h
  • TIM_TS_NONE : stm32g4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32g4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32g4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32g4xx_hal_tim.h
  • TIM_UIFREMAP_DISABLE : stm32g4xx_hal_tim.h
  • TIM_UIFREMAP_ENABLE : stm32g4xx_hal_tim.h
  • TIMEOUT : stm32g4xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32g4xx_hal_dac.c
  • TIMING_CLEAR_MASK : stm32g4xx_hal_smbus.c , stm32g4xx_hal_i2c.c
  • TIMx_AF1_BKINP : stm32g4xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32g4xx_ll_tim.h
  • TIMx_AF2_OCRSEL : stm32g4xx_hal_tim.c
  • TRIGGER_FALLING : stm32g4xx_hal_gpio.h
  • TRIGGER_MODE : stm32g4xx_hal_gpio.h
  • TRIGGER_MODE_Pos : stm32g4xx_hal_gpio.h
  • TRIGGER_RISING : stm32g4xx_hal_gpio.h
  • TX_FIFO_DEPTH : stm32g4xx_hal_uart_ex.c , stm32g4xx_hal_smartcard_ex.c , stm32g4xx_hal_usart_ex.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- u -

  • UART_ADDRESS_DETECT_4B : stm32g4xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32g4xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32g4xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32g4xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32g4xx_hal_uart.h
  • UART_BRR_MAX : stm32g4xx_hal_uart.c
  • UART_BRR_MIN : stm32g4xx_hal_uart.c
  • UART_CLEAR_CMF : stm32g4xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32g4xx_hal_uart.h
  • UART_CLEAR_FEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32g4xx_hal_uart.h
  • UART_CLEAR_NEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_OREF : stm32g4xx_hal_uart.h
  • UART_CLEAR_PEF : stm32g4xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32g4xx_hal_uart.h
  • UART_CLEAR_TCF : stm32g4xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32g4xx_hal_uart.h
  • UART_CLEAR_WUF : stm32g4xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32g4xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32g4xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32g4xx_hal_uart.h
  • UART_DIV_LPUART : stm32g4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32g4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32g4xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32g4xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32g4xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32g4xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32g4xx_hal_uart.h
  • UART_FIFOMODE_DISABLE : stm32g4xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32g4xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32g4xx_hal_uart.h
  • UART_FLAG_ABRF : stm32g4xx_hal_uart.h
  • UART_FLAG_BUSY : stm32g4xx_hal_uart.h
  • UART_FLAG_CMF : stm32g4xx_hal_uart.h
  • UART_FLAG_CTS : stm32g4xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32g4xx_hal_uart.h
  • UART_FLAG_FE : stm32g4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32g4xx_hal_uart.h
  • UART_FLAG_LBDF : stm32g4xx_hal_uart.h
  • UART_FLAG_NE : stm32g4xx_hal_uart.h
  • UART_FLAG_ORE : stm32g4xx_hal_uart.h
  • UART_FLAG_PE : stm32g4xx_hal_uart.h
  • UART_FLAG_REACK : stm32g4xx_hal_uart.h
  • UART_FLAG_RTOF : stm32g4xx_hal_uart.h
  • UART_FLAG_RWU : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFF : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32g4xx_hal_uart.h
  • UART_FLAG_RXFT : stm32g4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32g4xx_hal_uart.h
  • UART_FLAG_SBKF : stm32g4xx_hal_uart.h
  • UART_FLAG_TC : stm32g4xx_hal_uart.h
  • UART_FLAG_TEACK : stm32g4xx_hal_uart.h
  • UART_FLAG_TXE : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFE : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32g4xx_hal_uart.h
  • UART_FLAG_TXFT : stm32g4xx_hal_uart.h
  • UART_FLAG_WUF : stm32g4xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32g4xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32g4xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32g4xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32g4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32g4xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32g4xx_hal_uart.h
  • UART_IT_CM : stm32g4xx_hal_uart.h
  • UART_IT_CTS : stm32g4xx_hal_uart.h
  • UART_IT_ERR : stm32g4xx_hal_uart.h
  • UART_IT_FE : stm32g4xx_hal_uart.h
  • UART_IT_IDLE : stm32g4xx_hal_uart.h
  • UART_IT_LBD : stm32g4xx_hal_uart.h
  • UART_IT_MASK : stm32g4xx_hal_uart.h
  • UART_IT_NE : stm32g4xx_hal_uart.h
  • UART_IT_ORE : stm32g4xx_hal_uart.h
  • UART_IT_PE : stm32g4xx_hal_uart.h
  • UART_IT_RTO : stm32g4xx_hal_uart.h
  • UART_IT_RXFF : stm32g4xx_hal_uart.h
  • UART_IT_RXFNE : stm32g4xx_hal_uart.h
  • UART_IT_RXFT : stm32g4xx_hal_uart.h
  • UART_IT_RXNE : stm32g4xx_hal_uart.h
  • UART_IT_TC : stm32g4xx_hal_uart.h
  • UART_IT_TXE : stm32g4xx_hal_uart.h
  • UART_IT_TXFE : stm32g4xx_hal_uart.h
  • UART_IT_TXFNF : stm32g4xx_hal_uart.h
  • UART_IT_TXFT : stm32g4xx_hal_uart.h
  • UART_IT_WUF : stm32g4xx_hal_uart.h
  • UART_LIN_DISABLE : stm32g4xx_hal_uart.h
  • UART_LIN_ENABLE : stm32g4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32g4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32g4xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32g4xx_hal_uart_ex.h
  • UART_MODE_RX : stm32g4xx_hal_uart.h
  • UART_MODE_TX : stm32g4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32g4xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32g4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32g4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32g4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32g4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32g4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32g4xx_hal_uart.h
  • UART_PARITY_NONE : stm32g4xx_hal_uart.h
  • UART_PARITY_ODD : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32g4xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32g4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32g4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32g4xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_uart_ex.h
  • UART_SENDBREAK_REQUEST : stm32g4xx_hal_uart.h
  • UART_STATE_DISABLE : stm32g4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32g4xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32g4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32g4xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_uart_ex.h
  • UART_WAKEUP_ON_ADDRESS : stm32g4xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32g4xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32g4xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32g4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32g4xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32g4xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32g4xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32g4xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32g4xx_ll_utils.h
  • UNUSED : stm32g4xx_ll_dmamux.h
  • USART_BRR_MAX : stm32g4xx_hal_irda.c , stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_BRR_MIN : stm32g4xx_hal_smartcard.c , stm32g4xx_hal_irda.c , stm32g4xx_hal_usart.c
  • USART_CLEAR_FEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_NEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_OREF : stm32g4xx_hal_usart.h
  • USART_CLEAR_PEF : stm32g4xx_hal_usart.h
  • USART_CLEAR_RTOF : stm32g4xx_hal_usart.h
  • USART_CLEAR_TCF : stm32g4xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32g4xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32g4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32g4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32g4xx_hal_usart.h
  • USART_CR1_FIELDS : stm32g4xx_hal_smartcard.c , stm32g4xx_hal_uart.c , stm32g4xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32g4xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_CR3_FIELDS : stm32g4xx_hal_uart.c , stm32g4xx_hal_smartcard.c , stm32g4xx_hal_usart.c
  • USART_CR_MASK : stm32g4xx_hal_usart.h
  • USART_CR_POS : stm32g4xx_hal_usart.h
  • USART_DEFAULT_BAUDRATE : stm32g4xx_ll_usart.c
  • USART_DIV_SAMPLING8 : stm32g4xx_hal_usart.h
  • USART_DUMMY_DATA : stm32g4xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32g4xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32g4xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32g4xx_hal_usart.h
  • USART_FLAG_FE : stm32g4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32g4xx_hal_usart.h
  • USART_FLAG_NE : stm32g4xx_hal_usart.h
  • USART_FLAG_ORE : stm32g4xx_hal_usart.h
  • USART_FLAG_PE : stm32g4xx_hal_usart.h
  • USART_FLAG_REACK : stm32g4xx_hal_usart.h
  • USART_FLAG_RTOF : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFF : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32g4xx_hal_usart.h
  • USART_FLAG_RXFT : stm32g4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32g4xx_hal_usart.h
  • USART_FLAG_TC : stm32g4xx_hal_usart.h
  • USART_FLAG_TEACK : stm32g4xx_hal_usart.h
  • USART_FLAG_TXE : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFE : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32g4xx_hal_usart.h
  • USART_FLAG_TXFT : stm32g4xx_hal_usart.h
  • USART_FLAG_UDR : stm32g4xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32g4xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32g4xx_hal_usart.h
  • USART_ISR_MASK : stm32g4xx_hal_usart.h
  • USART_ISR_POS : stm32g4xx_hal_usart.h
  • USART_IT_ERR : stm32g4xx_hal_usart.h
  • USART_IT_FE : stm32g4xx_hal_usart.h
  • USART_IT_IDLE : stm32g4xx_hal_usart.h
  • USART_IT_MASK : stm32g4xx_hal_usart.h
  • USART_IT_NE : stm32g4xx_hal_usart.h
  • USART_IT_ORE : stm32g4xx_hal_usart.h
  • USART_IT_PE : stm32g4xx_hal_usart.h
  • USART_IT_RXFF : stm32g4xx_hal_usart.h
  • USART_IT_RXFNE : stm32g4xx_hal_usart.h
  • USART_IT_RXFT : stm32g4xx_hal_usart.h
  • USART_IT_RXNE : stm32g4xx_hal_usart.h
  • USART_IT_TC : stm32g4xx_hal_usart.h
  • USART_IT_TXE : stm32g4xx_hal_usart.h
  • USART_IT_TXFE : stm32g4xx_hal_usart.h
  • USART_IT_TXFNF : stm32g4xx_hal_usart.h
  • USART_IT_TXFT : stm32g4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32g4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32g4xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32g4xx_hal_usart_ex.h
  • USART_MODE_RX : stm32g4xx_hal_usart.h
  • USART_MODE_TX : stm32g4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32g4xx_hal_usart.h
  • USART_NSS_HARD : stm32g4xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32g4xx_hal_usart_ex.h
  • USART_PARITY_EVEN : stm32g4xx_hal_usart.h
  • USART_PARITY_NONE : stm32g4xx_hal_usart.h
  • USART_PARITY_ODD : stm32g4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32g4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32g4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32g4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32g4xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32g4xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32g4xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_usart_ex.h
  • USART_SLAVEMODE_DISABLE : stm32g4xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32g4xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32g4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32g4xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32g4xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32g4xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32g4xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32g4xx_hal_usart_ex.h
  • USART_WORDLENGTH_7B : stm32g4xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32g4xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32g4xx_hal_usart_ex.h
  • USB_CNTRX_BLSIZE : stm32g4xx_hal_pcd.h
  • USB_CNTRX_NBLK_MSK : stm32g4xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32g4xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_CORDIC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_EXTI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_FMAC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_HRTIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_NAND_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_NOR_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_OPAMP_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_SRAM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32g4xx_hal_conf.h
  • USE_RTOS : stm32g4xx_hal_conf.h
  • USE_SPI_CRC : stm32g4xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32g4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32g4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32g4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32g4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY5_BOOST_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY5_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32g4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32g4xx_ll_utils.c
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- v -

  • VDD_VALUE : stm32g4xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32g4xx_hal.c
  • VREFINT_CAL_ADDR : stm32g4xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32g4xx_ll_adc.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- w -

  • WWDG_EWI_DISABLE : stm32g4xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32g4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32g4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32g4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32g4xx_hal_wwdg.h
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions | Variables
stm32g4xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32g4xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | HAL_TICK_FREQ_10HZ 100U
#define | HAL_TICK_FREQ_100HZ 10U
#define | HAL_TICK_FREQ_1KHZ 1U
#define | HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
#define | SYSCFG_BOOT_MAINFLASH 0x00000000U
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
#define | SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5
#define | SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY
#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
CCMSRAM page write protection enable macro.
#define | __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__)
#define | __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK()
CCMSRAM page write protection unlock prior to erase.
#define | __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
CCMSRAM erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | IS_TICKFREQ(FREQ)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Returns tick frequency.
__weak void | HAL_SuspendTick (void)
Suspends Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_CCMSRAMErase (void)
Start a hardware CCMSRAM erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOSwitchVDD (void)
Enable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_DisableIOSwitchVDD (void)
Disable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_CCMSRAM_WriteProtectionEnable (uint32_t Page)
CCMSRAM page write protection enable.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio
uint32_t | uwTickFreq

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_ll_adc.h"
#include "stm32g4xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)
#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)
#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)
#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1)
#define | ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)
#define | ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)
#define | ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1)
#define | ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2)
#define | ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3)
#define | ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)
#define | ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)
#define | ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)
#define | ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)
#define | ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)
#define | ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)
#define | ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
#define | ADC_SAMPLING_MODE_NORMAL (0x00000000UL)
#define | ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)
#define | ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)
#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)
#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)
#define | ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)
#define | ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)
#define | ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)
#define | ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)
#define | ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1)
#define | ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1)
#define | ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2)
#define | ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2)
#define | ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3)
#define | ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4)
#define | ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5)
#define | ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6)
#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
#define | ADC_AWD_FILTERING_NONE (0x00000000UL)
#define | ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1))
#define | ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2))
#define | ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0))
#define | ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1))
#define | ADC_AWD_FILTERING_8SAMPLES
#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)
#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)
#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
Verify the ADC gain compensation.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.
#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (const ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
HAL_StatusTypeDef | HAL_ADC_StartSampling (ADC_HandleTypeDef *hadc)
Start ADC conversion sampling phase of regular group.
HAL_StatusTypeDef | HAL_ADC_StopSampling (ADC_HandleTypeDef *hadc)
Stop ADC conversion sampling phase of regular group and start conversion.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (const ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (const ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_adc.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)
#define | ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)
#define | ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)
#define | ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)
#define | ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
#define | ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)
#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)
#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)
#define | ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
#define | ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)
#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)
#define | ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
#define | ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
#define | ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
#define | ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
#define | ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)
#define | ADC_DMAACCESSMODE_DISABLED (0x00000000UL)
#define | ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1)
#define | ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA)
#define | ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)
#define | ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)
#define | ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)
#define | ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
#define | ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)
#define | ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)
#define | ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)
#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)
#define | ADC_CFGR_FIELDS
#define | ADC_SMPR1_FIELDS
#define | ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
#define | ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
Force ADC instance in multimode mode independent (multimode disable).
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
Check whether or not ADC is independent.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__)
Set the selected injected Channel rank.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
Configure the ADC DMA continuous request.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)
Verify the ADC offset sign setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__)
Verify the ADC multimode DMA access setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__)
Verify the ADC analog watchdog filtering setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
Return the DFSDM configuration mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (const ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_adc_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_comp.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_ll_exti.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.
#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)
#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)
#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )
#define | COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_LOW COMP_HYSTERESIS_10MV
#define | COMP_HYSTERESIS_MEDIUM COMP_HYSTERESIS_40MV
#define | COMP_HYSTERESIS_HIGH COMP_HYSTERESIS_70MV
#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )
#define | COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )
#define | COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
Generate a software interrupt on the COMP3 EXTI line.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI flag.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP4 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP4 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
Generate a software interrupt on the COMP4 EXTI line.
#define | __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
Enable the COMP4 EXTI line in event mode.
#define | __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
Disable the COMP4 EXTI line in event mode.
#define | __HAL_COMP_COMP4_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
Check whether the COMP4 EXTI line flag is set.
#define | __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
Clear the COMP4 EXTI flag.
#define | COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21)
#define | COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22)
#define | COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29)
#define | COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (const COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (const COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (const COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_comp.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cordic.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_cordic.h File Reference

This file contains all the functions prototypes for the CORDIC firmware library. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | __CORDIC_HandleTypeDef
CORDIC Handle Structure definition. More...
struct | CORDIC_ConfigTypeDef
CORDIC Config Structure definition. More...

Defines

#define | HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U)
#define | HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U)
#define | HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U)
#define | HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)
#define | CORDIC_FUNCTION_COSINE (0x00000000U)
#define | CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))
#define | CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))
#define | CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))
#define | CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))
#define | CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))
#define | CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define | CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_7CYCLES
#define | CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define | CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define | CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define | CORDIC_PRECISION_11CYCLES
#define | CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define | CORDIC_PRECISION_13CYCLES
#define | CORDIC_PRECISION_14CYCLES
#define | CORDIC_PRECISION_15CYCLES
#define | CORDIC_SCALE_0 (0x00000000U)
#define | CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define | CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define | CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define | CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define | CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | CORDIC_IT_IEN CORDIC_CSR_IEN
#define | CORDIC_DMA_REN CORDIC_CSR_DMAREN
#define | CORDIC_DMA_WEN CORDIC_CSR_DMAWEN
#define | CORDIC_NBWRITE_1 (0x00000000U)
#define | CORDIC_NBWRITE_2 CORDIC_CSR_NARGS
#define | CORDIC_NBREAD_1 (0x00000000U)
#define | CORDIC_NBREAD_2 CORDIC_CSR_NRES
#define | CORDIC_INSIZE_32BITS (0x00000000U)
#define | CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE
#define | CORDIC_OUTSIZE_32BITS (0x00000000U)
#define | CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE
#define | CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
#define | CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U)
#define | CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U)
#define | CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U)
#define | CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U)
#define | __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__)
Reset CORDIC handle state.
#define | __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
Enable the CORDIC interrupt when result is ready.
#define | __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
Disable the CORDIC interrupt.
#define | __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Check whether the specified CORDIC interrupt occurred or not.
#define | __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Clear specified CORDIC interrupt status.
#define | __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
Check whether the specified CORDIC status flag is set or not.
#define | __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
Clear specified CORDIC status flag.
#define | __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
Check whether the specified CORDIC interrupt is enabled or not.
#define | IS_CORDIC_FUNCTION(__FUNCTION__)
Verify the CORDIC function.
#define | IS_CORDIC_PRECISION(__PRECISION__)
Verify the CORDIC precision.
#define | IS_CORDIC_SCALE(__SCALE__)
Verify the CORDIC scaling factor.
#define | IS_CORDIC_NBWRITE(__NBWRITE__)
Verify the CORDIC number of 32-bits write expected for one calculation.
#define | IS_CORDIC_NBREAD(__NBREAD__)
Verify the CORDIC number of 32-bits read expected after one calculation.
#define | IS_CORDIC_INSIZE(__INSIZE__)
Verify the CORDIC input data size for one calculation.
#define | IS_CORDIC_OUTSIZE(__OUTSIZE__)
Verify the CORDIC output data size for one calculation.
#define | IS_CORDIC_DMA_DIRECTION(__DMADIR__)
Verify the CORDIC DMA transfer Direction.

Typedefs

typedef struct
__CORDIC_HandleTypeDef 		CORDIC_HandleTypeDef
CORDIC Handle Structure definition.
typedef void(* | pCORDIC_CallbackTypeDef )(CORDIC_HandleTypeDef *hcordic)
HAL CORDIC Callback pointer definition.

Enumerations

enum | HAL_CORDIC_StateTypeDef { HAL_CORDIC_STATE_RESET = 0x00U, HAL_CORDIC_STATE_READY = 0x01U, HAL_CORDIC_STATE_BUSY = 0x02U, HAL_CORDIC_STATE_ERROR = 0x03U }
CORDIC HAL State Structure definition. More...
enum | HAL_CORDIC_CallbackIDTypeDef { HAL_CORDIC_ERROR_CB_ID = 0x00U, HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, HAL_CORDIC_MSPINIT_CB_ID = 0x02U, HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U }
HAL CORDIC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_CORDIC_Init (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_CORDIC_DeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC peripheral.
__weak void | HAL_CORDIC_MspInit (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC MSP.
__weak void | HAL_CORDIC_MspDeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC MSP.
HAL_StatusTypeDef | HAL_CORDIC_RegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback)
HAL_StatusTypeDef | HAL_CORDIC_UnRegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
Unregister a CORDIC CallBack.
HAL_StatusTypeDef | HAL_CORDIC_Configure (CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
Configure the CORDIC processing according to the specified parameters in the CORDIC_ConfigTypeDef structure.
HAL_StatusTypeDef | HAL_CORDIC_Calculate (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in polling mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_CalculateZO (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in Zero-Overhead mode (output data being read soon as input data are written), according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_IT (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
Carry out data of CORDIC processing in interrupt mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_DMA (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
Carry out input and/or output data of CORDIC processing in DMA mode, according to the existing CORDIC configuration.
__weak void | HAL_CORDIC_ErrorCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC error callback.
__weak void | HAL_CORDIC_CalculateCpltCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC calculate complete callback.
void | HAL_CORDIC_IRQHandler (CORDIC_HandleTypeDef *hcordic)
Handle CORDIC interrupt request.
HAL_CORDIC_StateTypeDef | HAL_CORDIC_GetState (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC handle state.
uint32_t | HAL_CORDIC_GetError (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC peripheral error.

Detailed Description

This file contains all the functions prototypes for the CORDIC firmware library.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_cordic.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cortex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 0x00000007U
#define | NVIC_PRIORITYGROUP_1 0x00000006U
#define | NVIC_PRIORITYGROUP_2 0x00000005U
#define | NVIC_PRIORITYGROUP_3 0x00000004U
#define | NVIC_PRIORITYGROUP_4 0x00000003U
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U
#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_TEX_LEVEL4 ((uint8_t)0x04)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_cortex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32g4xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7U
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE
#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U
#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (const CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_crc.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_crc_ex.h File Reference

Header file of CRC HAL extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN
#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_crc_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U
#define | DAC_TRIGGER_NONE 0x00000000UL
#define | DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U
#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U
#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define | DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define | DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define | DAC_CHIPCONNECT_BOTH (1UL << 2)
#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)
#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)
#define | DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL
#define | DAC_DELAY_STARTUP_US (15UL)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(DACX, CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.
uint32_t | HAL_DAC_GetValue (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (const DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (const DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_dac.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL
#define | DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)
#define | IS_DAC_TRIGGER(DACX, TRIGGER)
#define | IS_DAC_TRIGGER2(DACX, TRIGGER)
#define | IS_DAC_HIGH_FREQUENCY_MODE(MODE)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_SAWTOOTH_POLARITY(POLARITY)
#define | IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
#define | IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL)

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData)
Enable or disable the selected DAC channel sawtooth wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataReset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave reset.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataStep (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave step.
HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
uint32_t | HAL_DACEx_DualGetValue (const DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_dac_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U
#define | DMA_REQUEST_MEM2MEM 0U
#define | DMA_REQUEST_GENERATOR0 1U
#define | DMA_REQUEST_GENERATOR1 2U
#define | DMA_REQUEST_GENERATOR2 3U
#define | DMA_REQUEST_GENERATOR3 4U
#define | DMA_REQUEST_ADC1 5U
#define | DMA_REQUEST_DAC1_CHANNEL1 6U
#define | DMA_REQUEST_DAC1_CHANNEL2 7U
#define | DMA_REQUEST_TIM6_UP 8U
#define | DMA_REQUEST_TIM7_UP 9U
#define | DMA_REQUEST_SPI1_RX 10U
#define | DMA_REQUEST_SPI1_TX 11U
#define | DMA_REQUEST_SPI2_RX 12U
#define | DMA_REQUEST_SPI2_TX 13U
#define | DMA_REQUEST_SPI3_RX 14U
#define | DMA_REQUEST_SPI3_TX 15U
#define | DMA_REQUEST_I2C1_RX 16U
#define | DMA_REQUEST_I2C1_TX 17U
#define | DMA_REQUEST_I2C2_RX 18U
#define | DMA_REQUEST_I2C2_TX 19U
#define | DMA_REQUEST_I2C3_RX 20U
#define | DMA_REQUEST_I2C3_TX 21U
#define | DMA_REQUEST_USART1_RX 24U
#define | DMA_REQUEST_USART1_TX 25U
#define | DMA_REQUEST_USART2_RX 26U
#define | DMA_REQUEST_USART2_TX 27U
#define | DMA_REQUEST_USART3_RX 28U
#define | DMA_REQUEST_USART3_TX 29U
#define | DMA_REQUEST_UART4_RX 30U
#define | DMA_REQUEST_UART4_TX 31U
#define | DMA_REQUEST_LPUART1_RX 34U
#define | DMA_REQUEST_LPUART1_TX 35U
#define | DMA_REQUEST_ADC2 36U
#define | DMA_REQUEST_TIM1_CH1 42U
#define | DMA_REQUEST_TIM1_CH2 43U
#define | DMA_REQUEST_TIM1_CH3 44U
#define | DMA_REQUEST_TIM1_CH4 45U
#define | DMA_REQUEST_TIM1_UP 46U
#define | DMA_REQUEST_TIM1_TRIG 47U
#define | DMA_REQUEST_TIM1_COM 48U
#define | DMA_REQUEST_TIM8_CH1 49U
#define | DMA_REQUEST_TIM8_CH2 50U
#define | DMA_REQUEST_TIM8_CH3 51U
#define | DMA_REQUEST_TIM8_CH4 52U
#define | DMA_REQUEST_TIM8_UP 53U
#define | DMA_REQUEST_TIM8_TRIG 54U
#define | DMA_REQUEST_TIM8_COM 55U
#define | DMA_REQUEST_TIM2_CH1 56U
#define | DMA_REQUEST_TIM2_CH2 57U
#define | DMA_REQUEST_TIM2_CH3 58U
#define | DMA_REQUEST_TIM2_CH4 59U
#define | DMA_REQUEST_TIM2_UP 60U
#define | DMA_REQUEST_TIM3_CH1 61U
#define | DMA_REQUEST_TIM3_CH2 62U
#define | DMA_REQUEST_TIM3_CH3 63U
#define | DMA_REQUEST_TIM3_CH4 64U
#define | DMA_REQUEST_TIM3_UP 65U
#define | DMA_REQUEST_TIM3_TRIG 66U
#define | DMA_REQUEST_TIM4_CH1 67U
#define | DMA_REQUEST_TIM4_CH2 68U
#define | DMA_REQUEST_TIM4_CH3 69U
#define | DMA_REQUEST_TIM4_CH4 70U
#define | DMA_REQUEST_TIM4_UP 71U
#define | DMA_REQUEST_TIM15_CH1 78U
#define | DMA_REQUEST_TIM15_UP 79U
#define | DMA_REQUEST_TIM15_TRIG 80U
#define | DMA_REQUEST_TIM15_COM 81U
#define | DMA_REQUEST_TIM16_CH1 82U
#define | DMA_REQUEST_TIM16_UP 83U
#define | DMA_REQUEST_TIM17_CH1 84U
#define | DMA_REQUEST_TIM17_UP 85U
#define | DMA_REQUEST_AES_IN 91U
#define | DMA_REQUEST_AES_OUT 92U
#define | DMA_REQUEST_DAC3_CHANNEL1 102U
#define | DMA_REQUEST_DAC3_CHANNEL2 103U
#define | DMA_REQUEST_SAI1_A 108U
#define | DMA_REQUEST_SAI1_B 109U
#define | DMA_REQUEST_FMAC_READ 110U
#define | DMA_REQUEST_FMAC_WRITE 111U
#define | DMA_REQUEST_CORDIC_READ 112U
#define | DMA_REQUEST_CORDIC_WRITE 113U
#define | DMA_REQUEST_UCPD1_RX 114U
#define | DMA_REQUEST_UCPD1_TX 115U
#define | DMA_PERIPH_TO_MEMORY 0x00000000U
#define | DMA_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | DMA_PINC_ENABLE DMA_CCR_PINC
#define | DMA_PINC_DISABLE 0x00000000U
#define | DMA_MINC_ENABLE DMA_CCR_MINC
#define | DMA_MINC_DISABLE 0x00000000U
#define | DMA_PDATAALIGN_BYTE 0x00000000U
#define | DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | DMA_MDATAALIGN_BYTE 0x00000000U
#define | DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | DMA_NORMAL 0x00000000U
#define | DMA_CIRCULAR DMA_CCR_CIRC
#define | DMA_PRIORITY_LOW 0x00000000U
#define | DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | DMA_PRIORITY_VERY_HIGH DMA_CCR_PL
#define | DMA_IT_TC DMA_CCR_TCIE
#define | DMA_IT_HT DMA_CCR_HTIE
#define | DMA_IT_TE DMA_CCR_TEIE
#define | DMA_FLAG_GL1 0x00000001U
#define | DMA_FLAG_TC1 0x00000002U
#define | DMA_FLAG_HT1 0x00000004U
#define | DMA_FLAG_TE1 0x00000008U
#define | DMA_FLAG_GL2 0x00000010U
#define | DMA_FLAG_TC2 0x00000020U
#define | DMA_FLAG_HT2 0x00000040U
#define | DMA_FLAG_TE2 0x00000080U
#define | DMA_FLAG_GL3 0x00000100U
#define | DMA_FLAG_TC3 0x00000200U
#define | DMA_FLAG_HT3 0x00000400U
#define | DMA_FLAG_TE3 0x00000800U
#define | DMA_FLAG_GL4 0x00001000U
#define | DMA_FLAG_TC4 0x00002000U
#define | DMA_FLAG_HT4 0x00004000U
#define | DMA_FLAG_TE4 0x00008000U
#define | DMA_FLAG_GL5 0x00010000U
#define | DMA_FLAG_TC5 0x00020000U
#define | DMA_FLAG_HT5 0x00040000U
#define | DMA_FLAG_TE5 0x00080000U
#define | DMA_FLAG_GL6 0x00100000U
#define | DMA_FLAG_TC6 0x00200000U
#define | DMA_FLAG_HT6 0x00400000U
#define | DMA_FLAG_TE6 0x00800000U
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_dma.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMA Synchro definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 0U
#define | HAL_DMAMUX1_SYNC_EXTI1 1U
#define | HAL_DMAMUX1_SYNC_EXTI2 2U
#define | HAL_DMAMUX1_SYNC_EXTI3 3U
#define | HAL_DMAMUX1_SYNC_EXTI4 4U
#define | HAL_DMAMUX1_SYNC_EXTI5 5U
#define | HAL_DMAMUX1_SYNC_EXTI6 6U
#define | HAL_DMAMUX1_SYNC_EXTI7 7U
#define | HAL_DMAMUX1_SYNC_EXTI8 8U
#define | HAL_DMAMUX1_SYNC_EXTI9 9U
#define | HAL_DMAMUX1_SYNC_EXTI10 10U
#define | HAL_DMAMUX1_SYNC_EXTI11 11U
#define | HAL_DMAMUX1_SYNC_EXTI12 12U
#define | HAL_DMAMUX1_SYNC_EXTI13 13U
#define | HAL_DMAMUX1_SYNC_EXTI14 14U
#define | HAL_DMAMUX1_SYNC_EXTI15 15U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U
#define | HAL_DMAMUX_SYNC_NO_EVENT 0U
#define | HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0)
#define | HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1)
#define | HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)
#define | HAL_DMAMUX1_REQ_GEN_EXTI0 0U
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 1U
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 2U
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 3U
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 4U
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 5U
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 6U
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 7U
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 8U
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 9U
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 10U
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 11U
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 12U
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 13U
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 14U
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 15U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U
#define | HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0
#define | HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL
#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_dma_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_exti.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32g4xx_hal_exti.h File Reference

Header file of EXTI HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define | EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
#define | EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
#define | EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
#define | EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#define | EXTI_MODE_NONE 0x00000000U
#define | EXTI_MODE_INTERRUPT 0x00000001U
#define | EXTI_MODE_EVENT 0x00000002U
#define | EXTI_TRIGGER_NONE 0x00000000U
#define | EXTI_TRIGGER_RISING 0x00000001U
#define | EXTI_TRIGGER_FALLING 0x00000002U
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
#define | EXTI_GPIOA 0x00000000U
#define | EXTI_GPIOB 0x00000001U
#define | EXTI_GPIOC 0x00000002U
#define | EXTI_GPIOD 0x00000003U
#define | EXTI_GPIOE 0x00000004U
#define | EXTI_GPIOF 0x00000005U
#define | EXTI_GPIOG 0x00000006U
#define | EXTI_PROPERTY_SHIFT 24U
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_REG_SHIFT 16U
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001FU
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 44UL
EXTI Line number.
#define | IS_EXTI_LINE(__EXTI_LINE__)
#define | IS_EXTI_MODE(__EXTI_LINE__)
#define | IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define | IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
#define | IS_EXTI_PENDING_EDGE(__EDGE__)
#define | IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00UL }

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

Header file of EXTI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_exti.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fdcan.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_fdcan.h File Reference

Header file of FDCAN HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)
#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))
#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)
#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)
#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)
#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)
#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU)
#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)
#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)
#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)
#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)
#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)
#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)
#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)
#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)
#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)
#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)
#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)
#define | FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)
#define | FDCAN_ILS_MASK ((uint32_t)0x0000007FU)
#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE
#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE
#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE
#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE
#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE
#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE
#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE
#define | FDCAN_IT_LIST_RX_FIFO0
#define | FDCAN_IT_LIST_RX_FIFO1
#define | FDCAN_IT_LIST_SMSG
#define | FDCAN_IT_LIST_TX_FIFO_ERROR
#define | FDCAN_IT_LIST_MISC
#define | FDCAN_IT_LIST_BIT_LINE_ERROR
#define | FDCAN_IT_LIST_PROTOCOL_ERROR
#define | FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0
#define | FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1
#define | FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG
#define | FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR
#define | FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC
#define | FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR
#define | FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR
#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR) = (__FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
#define | IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_TX_LOCATION_LIST(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
#define | IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U,
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, HAL_FDCAN_MSPINIT_CB_ID = 0x05U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U
}
HAL FDCAN common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (const FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (const FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (const FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
uint32_t | HAL_FDCAN_GetError (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.

Detailed Description

Header file of FDCAN HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_fdcan.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions | Variables
stm32g4xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_flash_ex.h"
#include "stm32g4xx_hal_flash_ramfunc.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define | HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
#define | HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
#define | FLASH_TYPEERASE_PAGES 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x01U
#define | FLASH_BANK_1 0x00000001U
#define | FLASH_BANK_BOTH FLASH_BANK_1
#define | FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U
#define | FLASH_TYPEPROGRAM_FAST 0x01U
#define | FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U
#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_PCROP 0x08U
#define | OPTIONBYTE_BOOT_LOCK 0x10U
#define | OPTIONBYTE_SEC 0x20U
#define | OB_WRPAREA_BANK1_AREAA 0x00U
#define | OB_WRPAREA_BANK1_AREAB 0x01U
#define | OB_BOOT_LOCK_DISABLE 0x00000000U
#define | OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK
#define | OB_RDP_LEVEL_0 0xAAU
#define | OB_RDP_LEVEL_1 0xBBU
#define | OB_RDP_LEVEL_2 0xCCU
#define | OB_USER_BOR_LEV 0x00000001U
#define | OB_USER_nRST_STOP 0x00000002U
#define | OB_USER_nRST_STDBY 0x00000004U
#define | OB_USER_IWDG_SW 0x00000008U
#define | OB_USER_IWDG_STOP 0x00000010U
#define | OB_USER_IWDG_STDBY 0x00000020U
#define | OB_USER_WWDG_SW 0x00000040U
#define | OB_USER_nBOOT1 0x00000200U
#define | OB_USER_SRAM_PE 0x00000400U
#define | OB_USER_CCMSRAM_RST 0x00000800U
#define | OB_USER_nRST_SHDW 0x00001000U
#define | OB_USER_nSWBOOT0 0x00002000U
#define | OB_USER_nBOOT0 0x00004000U
#define | OB_USER_NRST_MODE 0x00008000U
#define | OB_USER_IRHEN 0x00010000U
#define | OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0
#define | OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1
#define | OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2
#define | OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3
#define | OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4
#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP
#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY
#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW
#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP
#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY
#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1
#define | OB_SRAM_PARITY_ENABLE 0x00000000U
#define | OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE
#define | OB_CCMSRAM_RST_ERASE 0x00000000U
#define | OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST
#define | OB_BOOT0_FROM_OB 0x00000000U
#define | OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0
#define | OB_nBOOT0_RESET 0x00000000U
#define | OB_nBOOT0_SET FLASH_OPTR_nBOOT0
#define | OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0
#define | OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1
#define | OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE
#define | OB_IRH_DISABLE 0x00000000U
#define | OB_IRH_ENABLE FLASH_OPTR_IRHEN
#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_PDKEY1 0x04152637U
#define | FLASH_PDKEY2 0xFAFBFCFDU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_SR_ERRORS
#define | FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define | FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U)
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.
#define | __HAL_FLASH_POWER_DOWN_ENABLE()
Enable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_POWER_DOWN_DISABLE()
Disable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Enable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Disable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.
#define | FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#define | FLASH_SIZE
#define | FLASH_BANK_SIZE (FLASH_SIZE)
#define | FLASH_PAGE_NB
#define | FLASH_PAGE_SIZE 0x800U /* 2 KB */
#define | FLASH_TIMEOUT_VALUE 1000U /* 1 s */
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
#define | IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#define | IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
#define | IS_OPTIONBYTE(VALUE)
#define | IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
#define | IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
#define | IS_OB_USER_BOR_LEVEL(LEVEL)
#define | IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define | IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define | IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define | IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define | IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#define | IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define | IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
#define | IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
#define | IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
#define | IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
#define | IS_OB_USER_NRST_MODE(VALUE)
#define | IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
#define | IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
#define | IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
#define | IS_FLASH_LATENCY(LATENCY)

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM,
FLASH_PROC_PROGRAM_LAST
}
FLASH Procedure structure definition. More...
enum | FLASH_CacheTypeDef { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED }
FLASH Cache structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Functions
stm32g4xx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
HAL_StatusTypeDef | HAL_FLASHEx_EnableSecMemProtection (uint32_t Bank)
Enable the FLASH Securable Memory protection.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Detailed Description

Header file of FLASH HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ramfunc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Functions
stm32g4xx_hal_flash_ramfunc.h File Reference

Header file of FLASH RAMFUNC driver. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Functions

__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

Header file of FLASH RAMFUNC driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash_ramfunc.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fmac.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_fmac.h File Reference

Header for stm32g4xx_hal_fmac.c module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | __FMAC_HandleTypeDef
FMAC Handle Structure definition. More...
struct | FMAC_FilterConfigTypeDef
FMAC Filter Configuration Structure definition. More...

Defines

#define | HAL_FMAC_ERROR_NONE 0x00000000U
#define | HAL_FMAC_ERROR_SAT 0x00000001U
#define | HAL_FMAC_ERROR_UNFL 0x00000002U
#define | HAL_FMAC_ERROR_OVFL 0x00000004U
#define | HAL_FMAC_ERROR_DMA 0x00000008U
#define | HAL_FMAC_ERROR_RESET 0x00000010U
#define | HAL_FMAC_ERROR_PARAM 0x00000020U
#define | HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U
#define | HAL_FMAC_ERROR_TIMEOUT 0x00000080U
#define | FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)
#define | FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)
#define | FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)
#define | FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)
#define | FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)
#define | FMAC_THRESHOLD_1 0x00000000U
#define | FMAC_THRESHOLD_2 0x01000000U
#define | FMAC_THRESHOLD_4 0x02000000U
#define | FMAC_THRESHOLD_8 0x03000000U
#define | FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU
#define | FMAC_BUFFER_ACCESS_NONE 0x00U
#define | FMAC_BUFFER_ACCESS_DMA 0x01U
#define | FMAC_BUFFER_ACCESS_POLLING 0x02U
#define | FMAC_BUFFER_ACCESS_IT 0x03U
#define | FMAC_CLIP_DISABLED 0x00000000U
#define | FMAC_CLIP_ENABLED FMAC_CR_CLIPEN
#define | FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY
#define | FMAC_FLAG_X1FULL FMAC_SR_X1FULL
#define | FMAC_FLAG_OVFL FMAC_SR_OVFL
#define | FMAC_FLAG_UNFL FMAC_SR_UNFL
#define | FMAC_FLAG_SAT FMAC_SR_SAT
#define | FMAC_IT_RIEN FMAC_CR_RIEN
#define | FMAC_IT_WIEN FMAC_CR_WIEN
#define | FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN
#define | FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN
#define | FMAC_IT_SATIEN FMAC_CR_SATIEN
#define | __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__)
Reset FMAC handle state.
#define | __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the specified FMAC interrupt.
#define | __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the FMAC interrupt.
#define | __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
Check whether the specified FMAC interrupt occurred or not.
#define | __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
Clear specified FMAC interrupt status.
#define | __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified FMAC status flag is set or not.
#define | __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
Clear specified FMAC status flag.
#define | __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
Check whether the specified FMAC interrupt is enabled or not.
#define | FMAC_PARAM_P_MAX_IIR 64U
#define | FMAC_PARAM_P_MAX_FIR 127U
#define | FMAC_PARAM_P_MIN 2U
#define | FMAC_PARAM_Q_MAX 63U
#define | FMAC_PARAM_Q_MIN 1U
#define | FMAC_PARAM_R_MAX 7U
#define | IS_FMAC_FUNCTION(__FUNCTION__)
Verify the FMAC function.
#define | IS_FMAC_LOAD_FUNCTION(__FUNCTION__)
Verify the FMAC load function used for input data, output data or coefficients.
#define | IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__)
Verify the FMAC load function used with N values as input or output data.
#define | IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
Verify the FMAC load function used with N + M values as coefficients.
#define | IS_FMAC_FILTER_FUNCTION(__FUNCTION__)
Verify the FMAC filter function.
#define | IS_FMAC_THRESHOLD(__THRESHOLD__)
Verify the FMAC threshold.
#define | IS_FMAC_PARAM_P(__FUNCTION__, __P__)
Verify the FMAC filter parameter P.
#define | IS_FMAC_PARAM_Q(__FUNCTION__, __Q__)
Verify the FMAC filter parameter Q.
#define | IS_FMAC_PARAM_R(__FUNCTION__, __R__)
Verify the FMAC filter parameter R.
#define | IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__)
Verify the FMAC buffer access.
#define | IS_FMAC_CLIP_STATE(__CLIP_STATE__)
Verify the FMAC clip feature.
#define | IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__)
Check whether the threshold is applicable.

Typedefs

typedef struct __FMAC_HandleTypeDef | FMAC_HandleTypeDef
FMAC Handle Structure definition.
typedef void(* | pFMAC_CallbackTypeDef )(FMAC_HandleTypeDef *hfmac)
HAL FMAC Callback pointer definition.

Enumerations

enum HAL_FMAC_StateTypeDef {
HAL_FMAC_STATE_RESET = 0x00U, HAL_FMAC_STATE_READY = 0x20U, HAL_FMAC_STATE_BUSY = 0x24U, HAL_FMAC_STATE_BUSY_RD = 0x25U,
HAL_FMAC_STATE_BUSY_WR = 0x26U, HAL_FMAC_STATE_TIMEOUT = 0xA0U, HAL_FMAC_STATE_ERROR = 0xE0U
}
FMAC HAL State Structure definition. More...
enum HAL_FMAC_CallbackIDTypeDef {
HAL_FMAC_ERROR_CB_ID = 0x00U, HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, HAL_FMAC_GET_DATA_CB_ID = 0x02U, HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U,
HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, HAL_FMAC_MSPINIT_CB_ID = 0x07U,
HAL_FMAC_MSPDEINIT_CB_ID = 0x08U
}
FMAC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_FMAC_Init (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_FMAC_DeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC peripheral.
__weak void | HAL_FMAC_MspInit (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC MSP.
__weak void | HAL_FMAC_MspDeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC MSP.
HAL_StatusTypeDef | HAL_FMAC_RegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID, pFMAC_CallbackTypeDef pCallback)
Register a User FMAC Callback.
HAL_StatusTypeDef | HAL_FMAC_UnRegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
Unregister a FMAC CallBack.
HAL_StatusTypeDef | HAL_FMAC_FilterConfig (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterConfig_DMA (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload_DMA (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterStart (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Start the FMAC processing according to the existing FMAC configuration.
HAL_StatusTypeDef | HAL_FMAC_AppendFilterData (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
Provide a new input buffer that will be loaded into the FMAC input memory area.
HAL_StatusTypeDef | HAL_FMAC_ConfigFilterOutputBuffer (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Provide a new output buffer to be filled with the data computed by FMAC unit.
HAL_StatusTypeDef | HAL_FMAC_PollFilterData (FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
Handle the input and/or output data in polling mode.
HAL_StatusTypeDef | HAL_FMAC_FilterStop (FMAC_HandleTypeDef *hfmac)
Stop the FMAC processing.
__weak void | HAL_FMAC_ErrorCallback (FMAC_HandleTypeDef *hfmac)
FMAC error callback.
__weak void | HAL_FMAC_HalfGetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get half data callback.
__weak void | HAL_FMAC_GetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get data callback.
__weak void | HAL_FMAC_HalfOutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC half output data ready callback.
__weak void | HAL_FMAC_OutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC output data ready callback.
__weak void | HAL_FMAC_FilterConfigCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter configuration callback.
__weak void | HAL_FMAC_FilterPreloadCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter preload callback.
void | HAL_FMAC_IRQHandler (FMAC_HandleTypeDef *hfmac)
Handle FMAC interrupt request.
HAL_FMAC_StateTypeDef | HAL_FMAC_GetState (const FMAC_HandleTypeDef *hfmac)
Return the FMAC state.
uint32_t | HAL_FMAC_GetError (const FMAC_HandleTypeDef *hfmac)
Return the FMAC peripheral error.

Detailed Description

Header for stm32g4xx_hal_fmac.c module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_fmac.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32g4xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT MODE_INPUT
#define | GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
#define | GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
#define | GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
#define | GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
#define | GPIO_MODE_ANALOG MODE_ANALOG
#define | GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
#define | GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
#define | GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
#define | GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U)
#define | GPIO_NOPULL (0x00000000U)
#define | GPIO_PULLUP (0x00000001U)
#define | GPIO_PULLDOWN (0x00000002U)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | GPIO_MODE_Pos 0U
#define | GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define | MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define | MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define | MODE_AF (0x2UL << GPIO_MODE_Pos)
#define | MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define | OUTPUT_TYPE_Pos 4U
#define | OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define | OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define | OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define | EXTI_MODE_Pos 16U
#define | EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define | EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define | EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define | TRIGGER_MODE_Pos 20U
#define | TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define | TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define | TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_gpio.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines
stm32g4xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define | GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define | GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
#define | GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#define | GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
#define | GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
#define | GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
#define | GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
#define | GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
#define | GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define | GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define | GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
#define | GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
#define | GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
#define | GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
#define | GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
#define | GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
#define | GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
#define | GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
#define | GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define | GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
#define | GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
#define | GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
#define | GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
#define | GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
#define | GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
#define | GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define | GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
#define | GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
#define | GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define | GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
#define | GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
#define | GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define | GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
#define | GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define | GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define | GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define | GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
#define | GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define | GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
#define | GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
#define | GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_gpio_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__)
#define | I2C_GET_ADDR_MATCH(__HANDLE__)
#define | I2C_GET_DIR(__HANDLE__)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (const I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (const I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (const I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_i2c.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED)
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_i2c_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2s.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010U)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)
#define | HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)
#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define | I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define | I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)
#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE
#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | I2S_FLAG_MASK
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_FLUSH_RX_DR(__HANDLE__)
Flush the I2S DR Register.
#define | I2S_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
Checks if I2S Serial clock steady state parameter is in allowed range.

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U,
HAL_I2S_ERROR_CB_ID = 0x06U, HAL_I2S_MSPINIT_CB_ID = 0x07U, HAL_I2S_MSPDEINIT_CB_ID = 0x08U
}
HAL I2S Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_i2s.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U
#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)
#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP
#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU
#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE
#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN
#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT
#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR
#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE
#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U,
IRDA_CLOCKSOURCE_LSE = 0x10U, IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_irda.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines
stm32g4xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0
#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_irda_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_iwdg.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_iwdg.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_lptim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM37
#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3
#define | LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0
#define | LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0
#define | LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()
Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()
Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()
Enable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()
Disable event on the LPTIM Wake-up Timer associated Exti line.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (const LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_lptim.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_opamp.h File Reference

Header file of OPAMP HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_opamp_ex.h"

Go to the source code of this file.

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | __OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Defines

#define | OPAMP_STANDALONE_MODE (0x00000000UL)
#define | OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1
#define | OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL
#define | OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0
#define | OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1
#define | OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL
#define | OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL
#define | OPAMP_INVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0
#define | OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000UL)
#define | OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 OPAMP_TCMR_T1CMEN
#define | OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN
#define | OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0
#define | OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1
#define | OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL
#define | OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL
#define | OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000UL)
#define | OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL
#define | OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL)
#define | OPAMP_SEC_INVERTINGINPUT_FOLLOWER OPAMP_TCMR_VMSSEL
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000UL)
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_4
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3
#define | OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3)
#define | OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)
#define | OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)
#define | OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )
#define | OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)
#define | OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)
#define | OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN
#define | OPAMP_TRIMMING_FACTORY (0x00000000UL)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFUL)
#define | OPAMP_FACTORYTRIMMING_N (0x00000000UL)
#define | OPAMP_FACTORYTRIMMING_P (0x00000001UL)
#define | OPAMP_VREF_3VDDA (0x00000000UL)
#define | OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0
#define | OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1
#define | OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL
#define | OPAMP_INPUT_INVERTING ( 24UL)
#define | OPAMP_INPUT_NONINVERTING ( 19UL)
#define | IS_OPAMP_INPUT(INPUT)
#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_INVERTING_INPUT(INPUT)
#define | IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE)
#define | IS_OPAMP_SEC_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_SEC_INVERTING_INPUT(INPUT)
#define | IS_OPAMP_PGACONNECT(CONNECT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_POWERMODE(POWERMODE)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FUL)
#define | IS_OPAMP_VREF(VREF)
#define | __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.

Typedefs

typedef struct
__OPAMP_HandleTypeDef 		OPAMP_HandleTypeDef
OPAMP Handle Structure definition.
typedef uint32_t | OPAMP_TrimmingValueTypeDef
OPAMP_TrimmingValueTypeDef definition.
typedef void(* | pOPAMP_CallbackTypeDef )(OPAMP_HandleTypeDef *hopamp)
HAL OPAMP Callback pointer definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000UL, HAL_OPAMP_STATE_READY = 0x00000001UL, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002UL, HAL_OPAMP_STATE_BUSY = 0x00000004UL,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005UL
}
HAL State structures definition. More...
enum | HAL_OPAMP_CallbackIDTypeDef { HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, HAL_OPAMP_ALL_CB_ID = 0x03UL }
HAL OPAMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitializes the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the opamp.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the opamp.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp configuration.
HAL_StatusTypeDef | HAL_OPAMP_LockTimerMux (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp timer controlled mux configuration.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP state.
OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.

Detailed Description

Header file of OPAMP HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_opamp.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Functions
stm32g4xx_hal_opamp_ex.h File Reference

Header file of OPAMP HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3)

Detailed Description

Header file of OPAMP HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_opamp_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32g4xx_ll_usb.h"
#include "stm32g4xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_FULL USBD_FS_SPEED
#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U
#define | HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
#define | USB_WAKEUP_EXTI_LINE (0x1U << 18)
#define | PCD_EP0MPS_64 EP_MPS_64
#define | PCD_EP0MPS_32 EP_MPS_32
#define | PCD_EP0MPS_16 EP_MPS_16
#define | PCD_EP0MPS_08 EP_MPS_8
#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U
#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U
#define | USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define | USB_CNTRX_BLSIZE (0x1U << 15)
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum)
#define | PCD_EP_RX_CNT(USBx, bEpNum)
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr)
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr)
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(pdwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(pdwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount)
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr)
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr)
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.
typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}
enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
Get Received Data Size.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef const *hpcd)
Return the PCD handle state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pcd.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Functions
stm32g4xx_hal_pcd_ex.h File Reference

Header file of PCD HAL Extension module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL Extension module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pcd_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7
#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)
#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define | PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)
#define | PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pwr.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...

Defines

#define | PWR_WUP_POLARITY_SHIFT 0x05U
#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)
#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_2 PWR_CR2_PVME2
#define | PWR_PVM_3 PWR_CR2_PVME3
#define | PWR_PVM_4 PWR_CR2_PVME4
#define | PWR_PVM_MODE_NORMAL 0x00000000U
#define | PWR_PVM_MODE_IT_RISING 0x00010001U
#define | PWR_PVM_MODE_IT_FALLING 0x00010002U
#define | PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U
#define | PWR_PVM_MODE_EVENT_RISING 0x00020001U
#define | PWR_PVM_MODE_EVENT_FALLING 0x00020002U
#define | PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U
#define | PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS
#define | PWR_BATTERY_CHARGING_DISABLE 0x00000000U
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRA_PA14
#define | PWR_GPIO_BIT_15 PWR_PUCRA_PA15
#define | PWR_GPIO_A 0x00000000U
#define | PWR_GPIO_B 0x00000001U
#define | PWR_GPIO_C 0x00000002U
#define | PWR_GPIO_D 0x00000003U
#define | PWR_GPIO_E 0x00000004U
#define | PWR_GPIO_F 0x00000005U
#define | PWR_GPIO_G 0x00000006U
#define | PWR_EXTI_LINE_PVM1 0x00000008U
#define | PWR_EXTI_LINE_PVM2 0x00000010U
#define | PWR_EXTI_LINE_PVM3 0x00000020U
#define | PWR_EXTI_LINE_PVM4 0x00000040U
#define | PWR_EVENT_LINE_PVM1 0x00000008U
#define | PWR_EVENT_LINE_PVM2 0x00000010U
#define | PWR_EVENT_LINE_PVM3 0x00000020U
#define | PWR_EVENT_LINE_PVM4 0x00000040U
#define | PWR_FLAG_WUF1 0x0020U
#define | PWR_FLAG_WUF2 0x0021U
#define | PWR_FLAG_WUF3 0x0022U
#define | PWR_FLAG_WUF4 0x0023U
#define | PWR_FLAG_WUF5 0x0024U
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_SB 0x0028U
#define | PWR_FLAG_WUFI 0x002FU
#define | PWR_FLAG_REGLPS 0x0048U
#define | PWR_FLAG_REGLPF 0x0049U
#define | PWR_FLAG_VOSF 0x004AU
#define | PWR_FLAG_PVDO 0x004BU
#define | PWR_FLAG_PVMO1 0x004CU
#define | PWR_FLAG_PVMO2 0x004DU
#define | PWR_FLAG_PVMO3 0x004EU
#define | PWR_FLAG_PVMO4 0x004FU
#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Enable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Disable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Enable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Disable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM2 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
Check whether the specified PVM2 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
Clear the PVM2 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Enable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Disable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Enable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Disable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM4 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
Check whether or not the specified PVM4 EXTI interrupt flag is set.
#define | __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
Clear the PVM4 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
#define | IS_PWR_GPIO(GPIO)

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.
void | HAL_PWREx_EnableUCPDStandbyMode (void)
Enable UCPD configuration memorization in Standby.
void | HAL_PWREx_DisableUCPDStandbyMode (void)
Disable UCPD configuration memorization in Standby.
void | HAL_PWREx_EnableUCPDDeadBattery (void)
Enable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.
void | HAL_PWREx_DisableUCPDDeadBattery (void)
Disable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.

Detailed Description

Header file of PWR HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pwr_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000020U
#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)
#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CRRCR_HSI48ON
#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U
#define | RCC_PLLM_DIV1 0x00000001U
#define | RCC_PLLM_DIV2 0x00000002U
#define | RCC_PLLM_DIV3 0x00000003U
#define | RCC_PLLM_DIV4 0x00000004U
#define | RCC_PLLM_DIV5 0x00000005U
#define | RCC_PLLM_DIV6 0x00000006U
#define | RCC_PLLM_DIV7 0x00000007U
#define | RCC_PLLM_DIV8 0x00000008U
#define | RCC_PLLM_DIV9 0x00000009U
#define | RCC_PLLM_DIV10 0x0000000AU
#define | RCC_PLLM_DIV11 0x0000000BU
#define | RCC_PLLM_DIV12 0x0000000CU
#define | RCC_PLLM_DIV13 0x0000000DU
#define | RCC_PLLM_DIV14 0x0000000EU
#define | RCC_PLLM_DIV15 0x0000000FU
#define | RCC_PLLM_DIV16 0x00000010U
#define | RCC_PLLP_DIV2 0x00000002U
#define | RCC_PLLP_DIV3 0x00000003U
#define | RCC_PLLP_DIV4 0x00000004U
#define | RCC_PLLP_DIV5 0x00000005U
#define | RCC_PLLP_DIV6 0x00000006U
#define | RCC_PLLP_DIV7 0x00000007U
#define | RCC_PLLP_DIV8 0x00000008U
#define | RCC_PLLP_DIV9 0x00000009U
#define | RCC_PLLP_DIV10 0x0000000AU
#define | RCC_PLLP_DIV11 0x0000000BU
#define | RCC_PLLP_DIV12 0x0000000CU
#define | RCC_PLLP_DIV13 0x0000000DU
#define | RCC_PLLP_DIV14 0x0000000EU
#define | RCC_PLLP_DIV15 0x0000000FU
#define | RCC_PLLP_DIV16 0x00000010U
#define | RCC_PLLP_DIV17 0x00000011U
#define | RCC_PLLP_DIV18 0x00000012U
#define | RCC_PLLP_DIV19 0x00000013U
#define | RCC_PLLP_DIV20 0x00000014U
#define | RCC_PLLP_DIV21 0x00000015U
#define | RCC_PLLP_DIV22 0x00000016U
#define | RCC_PLLP_DIV23 0x00000017U
#define | RCC_PLLP_DIV24 0x00000018U
#define | RCC_PLLP_DIV25 0x00000019U
#define | RCC_PLLP_DIV26 0x0000001AU
#define | RCC_PLLP_DIV27 0x0000001BU
#define | RCC_PLLP_DIV28 0x0000001CU
#define | RCC_PLLP_DIV29 0x0000001DU
#define | RCC_PLLP_DIV30 0x0000001EU
#define | RCC_PLLP_DIV31 0x0000001FU
#define | RCC_PLLQ_DIV2 0x00000002U
#define | RCC_PLLQ_DIV4 0x00000004U
#define | RCC_PLLQ_DIV6 0x00000006U
#define | RCC_PLLQ_DIV8 0x00000008U
#define | RCC_PLLR_DIV2 0x00000002U
#define | RCC_PLLR_DIV4 0x00000004U
#define | RCC_PLLR_DIV6 0x00000006U
#define | RCC_PLLR_DIV8 0x00000008U
#define | RCC_PLLSOURCE_NONE 0x00000000U
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN
#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_NONE 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | RCC_MCO_GPIOPORT_POS 16U
#define | RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
#define | RCC_MCO_GPIOAF_POS 20U
#define | RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
#define | RCC_MCO_INDEX_POS 28U
#define | RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
#define | RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS)
#define | RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
#define | RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
#define | RCC_MCO1 RCC_MCO_PA8
#define | RCC_MCO RCC_MCO1
#define | RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3
#define | RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4
#define | RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16
#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
#define | RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)
#define | RCC_LSEDRIVE_LOW 0x00000000U
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_DMAMUX1_CLK_ENABLE()
#define | __HAL_RCC_CORDIC_CLK_ENABLE()
#define | __HAL_RCC_FMAC_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
#define | __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
#define | __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
#define | __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_ADC12_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_DAC3_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
#define | __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
#define | __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_UCPD1_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
#define | __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
#define | __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
#define | __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
#define | __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
#define | __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
#define | __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
#define | __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
#define | __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define | __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define | __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define | __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define | __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#define | __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#define | __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define | __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define | __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define | __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define | __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define | __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#define | __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define | __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#define | __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
#define | __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
#define | __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
#define | __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
#define | __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
#define | __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
#define | __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
#define | __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
#define | __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
Macro to configure the PLL source division factor M.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.
#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
#define | IS_RCC_PLLQ_VALUE(__VALUE__)
#define | IS_RCC_PLLR_VALUE(__VALUE__)
#define | IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8/PG10).
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rcc.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...

Defines

#define | RCC_LSCOSOURCE_LSI 0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL
#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_USART2 0x00000002U
#define | RCC_PERIPHCLK_USART3 0x00000004U
#define | RCC_PERIPHCLK_UART4 0x00000008U
#define | RCC_PERIPHCLK_LPUART1 0x00000020U
#define | RCC_PERIPHCLK_I2C1 0x00000040U
#define | RCC_PERIPHCLK_I2C2 0x00000080U
#define | RCC_PERIPHCLK_I2C3 0x00000100U
#define | RCC_PERIPHCLK_LPTIM1 0x00000200U
#define | RCC_PERIPHCLK_SAI1 0x00000400U
#define | RCC_PERIPHCLK_I2S 0x00000800U
#define | RCC_PERIPHCLK_FDCAN 0x00001000U
#define | RCC_PERIPHCLK_USB 0x00002000U
#define | RCC_PERIPHCLK_RNG 0x00004000U
#define | RCC_PERIPHCLK_ADC12 0x00008000U
#define | RCC_PERIPHCLK_RTC 0x00080000U
#define | RCC_USART1CLKSOURCE_PCLK2 0x00000000U
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
#define | RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
#define | RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
#define | RCC_UART4CLKSOURCE_PCLK1 0x00000000U
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
#define | RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
#define | RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
#define | RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
#define | RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
#define | RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
#define | RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
#define | RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
#define | RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
#define | RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
#define | RCC_FDCANCLKSOURCE_HSE 0x00000000U
#define | RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
#define | RCC_RNGCLKSOURCE_HSI48 0x00000000U
#define | RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_USBCLKSOURCE_HSI48 0x00000000U
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_ADC12CLKSOURCE_NONE 0x00000000U
#define | RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
#define | RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1
#define | RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19
#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U
#define | RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | RCC_CRS_SYNC_DIV1 0x00000000U
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
#define | RCC_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
#define | RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U
#define | RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
#define | RCC_CRS_FREQERRORDIR_UP 0x00000000U
#define | RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR
#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
Macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
Macro to get the UART4 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
Macro to get the I2C3 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
Macro to configure the I2S clock source.
#define | __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
Macro to get the I2S clock source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
Macro to configure the FDCAN clock source.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
Macro to get the FDCAN clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
Macro to get the RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
Macro to configure the ADC12 interface clock.
#define | __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
Macro to get the ADC12 clock source.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.
#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART4CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2SCLKSOURCE(__SOURCE__)
#define | IS_RCC_FDCANCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADC12CLKSOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Header file of RCC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rcc_ex.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rng.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_InitTypeDef
struct | __RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED
#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}
enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (const RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (const RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (const RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rng.h.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 0x00000000U
#define | RTC_HOURFORMAT_12 RTC_CR_FMT
#define | RTC_OUTPUT_DISABLE 0x00000000U
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000U
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | RTC_OUTPUT_PULLUP_NONE 0x00000000U
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
#define | RTC_OUTPUT_REMAP_NONE 0x00000000U
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
#define | RTC_HOURFORMAT12_AM 0x0U
#define | RTC_HOURFORMAT12_PM 0x1U
#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000U
#define | RTC_STOREOPERATION_RESET 0x00000000U
#define | RTC_STOREOPERATION_SET RTC_CR_BKP
#define | RTC_FORMAT_BIN 0x00000000U
#define | RTC_FORMAT_BCD 0x00000001U
#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | RTC_ALARMMASK_NONE 0x00000000U
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE
#define | RTC_FLAG_MASK 0x001FU
#define | RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)
#define | RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)
#define | RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)
#define | RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)
#define | RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)
#define | RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)
#define | RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)
#define | RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)
#define | RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)
#define | RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)
#define | RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)
#define | RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)
#define | RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)
#define | RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)
#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
Check whether the RTC Calendar is initialized.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC Alarms flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the RTC Alarms pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
set rising edge interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)
set rising edge interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
clear interrupt on the RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_ICSR_RESERVED_MASK
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_INIT_MASK 0xFFFFFFFFU
#define | RTC_TIMEOUT_VALUE 1000U
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 0x07U,
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 0x08U, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU,
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 0x0DU, HAL_RTC_MSPINIT_CB_ID = 0x0EU, HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rtc.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
struct | RTC_InternalTamperTypeDef

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
#define | RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U
#define | RTC_CALIBOUTPUT_512HZ 0x00000000U
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
#define | RTC_SHIFTADD1S_RESET 0x00000000U
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )
#define | RTC_INT_TAMPER_1 0U
#define | RTC_INT_TAMPER_2 0U
#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_7 0U
#define | RTC_INT_TAMPER_8 0U
#define | RTC_INT_TAMPER_ALL
#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00U
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x01U
#define | RTC_TAMPERTRIGGER_LOWLEVEL 0x02U
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x03U
#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00U
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01U
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00U
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01U
#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)
#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000U
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS
#define | RTC_IT_TAMP_1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP_2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP_3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )
#define | RTC_IT_INT_TAMP_1 0U
#define | RTC_IT_INT_TAMP_2 0U
#define | RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE
#define | RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE
#define | RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE
#define | RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE
#define | RTC_IT_INT_TAMP_7 0U
#define | RTC_IT_INT_TAMP_8 0U
#define | RTC_IT_INT_TAMP_ALL
#define | RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
#define | RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)
#define | RTC_FLAG_INT_TAMP_1 0U
#define | RTC_FLAG_INT_TAMP_2 0U
#define | RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F
#define | RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F
#define | RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F
#define | RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F
#define | RTC_FLAG_INT_TAMP_7 0U
#define | RTC_FLAG_INT_TAMP_8 0U
#define | RTC_FLAG_INT_TAMP_ALL
#define | RTC_BKP_NUMBER RTC_BACKUP_NB
#define | RTC_BKP_DR0 0x00U
#define | RTC_BKP_DR1 0x01U
#define | RTC_BKP_DR2 0x02U
#define | RTC_BKP_DR3 0x03U
#define | RTC_BKP_DR4 0x04U
#define | RTC_BKP_DR5 0x05U
#define | RTC_BKP_DR6 0x06U
#define | RTC_BKP_DR7 0x07U
#define | RTC_BKP_DR8 0x08U
#define | RTC_BKP_DR9 0x09U
#define | RTC_BKP_DR10 0x0AU
#define | RTC_BKP_DR11 0x0BU
#define | RTC_BKP_DR12 0x0CU
#define | RTC_BKP_DR13 0x0DU
#define | RTC_BKP_DR14 0x0EU
#define | RTC_BKP_DR15 0x0FU
#define | __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__))
Clear the specified RTC pending flag.
#define | __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified RTC flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC WakeUpTimers flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
Clear the RTC Wake Up timers pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC TimeStamps flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
Clear the RTC Time Stamps pending flags.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
Clear the interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC Internal Time Stamps flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
Clear the RTC Internal Time Stamps pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC shift operations flag status.
#define | __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__))
Enable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
Disable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__))
Enable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
Disable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified TAMP Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TAMP Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0UL)
Get the selected TAMP Tampers flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__))
Clear the TAMP Tampers pending flags.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable interrupt on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)
Clear the interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable event on the RTC Tamper associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable event on the RTC Tamper associated Exti line.
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17
#define | RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_LOW_POWER_CALIB(LPCAL)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified TAMP Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified TAMP Backup data Register.

Detailed Description

Header file of RTC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rtc_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_sai_ex.h"

Go to the source code of this file.

Data Structures

struct | SAI_PdmInitTypeDef
struct | SAI_InitTypeDef
struct | SAI_FrameInitTypeDef
struct | SAI_SlotInitTypeDef
struct | __SAI_HandleTypeDef

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U
#define | SAI_SYNCEXT_DISABLE 0U
#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U
#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U
#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U
#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U
#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U
#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU
#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO
#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE
#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET
#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.
#define | IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (const SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (const SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_sai.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_sai_ex.h File Reference

Header file of SAI HAL extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...

Defines

#define | IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (const SAI_HandleTypeDef *hsai, const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

Header file of SAI HAL extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_sai_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initialization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U
#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)
#define | SMARTCARD_WORDLENGTH_9B USART_CR1_M0
#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP
#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL
#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA
#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK
#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9375001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U,
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_smartcard.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U
#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_smartcard_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_smbus_ex.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | __SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX
#define | SMBUS_IT_RX
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__)
#define | SMBUS_RESET_CR2(__HANDLE__)
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_smbus.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_smbus_ex.h File Reference

Header file of SMBUS HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED)
#define | IS_SMBUS_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).
void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

Header file of SMBUS HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_smbus_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)
#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)
#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK
#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)
#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__)
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_spi.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Functions
stm32g4xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (const SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_spi_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_COMP1 0x00000000U
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0
#define | TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1
#define | TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)
#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_CCR5 0x00000012U
#define | TIM_DMABASE_CCR6 0x00000013U
#define | TIM_DMABASE_CCMR3 0x00000014U
#define | TIM_DMABASE_DTR2 0x00000015U
#define | TIM_DMABASE_ECR 0x00000016U
#define | TIM_DMABASE_TISEL 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_OR 0x0000001AU
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U
#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_UIFREMAP_DISABLE 0x00000000U
#define | TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP
#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U
#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U
#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)
#define | TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE
#define | TIM_IT_IDX TIM_DIER_IDXIE
#define | TIM_IT_DIR TIM_DIER_DIRIE
#define | TIM_IT_IERR TIM_DIER_IERRIE
#define | TIM_IT_TERR TIM_DIER_TERRIE
#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U
#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE
#define | TIM_CCDMAREQUEST_CC 0x00000000U
#define | TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF
#define | TIM_FLAG_IDX TIM_SR_IDXF
#define | TIM_FLAG_DIR TIM_SR_DIRF
#define | TIM_FLAG_IERR TIM_SR_IERRF
#define | TIM_FLAG_TERR TIM_SR_TERRF
#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
#define | TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
#define | TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8
#define | TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10
#define | TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U
#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U
#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U
#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
#define | TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID
#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
#define | TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | TIM_GROUPCH5_NONE 0x00000000U
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3
#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)
#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M
#define | TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)
#define | TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)
#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U
#define | TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U
#define | TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U
#define | TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U
#define | TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U
#define | TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U
#define | TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U
#define | TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U
#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
#define | __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
Disable update interrupt flag (UIF) remapping.
#define | __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
Get update interrupt flag (UIF) copy status.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
Select the Capture/compare DMA request source.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_UIFREMAP_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_PERIOD(__HANDLE__, __PERIOD__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK_AFMODE(__AFMODE__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_AFMODE(__AFMODE__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum | HAL_TIM_ChannelStateTypeDef { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
TIM Channel States definition. More...
enum | HAL_TIM_DMABurstStateTypeDef { HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
DMA Burst States definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU,
HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU, HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU, HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU, HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU
}
HAL TIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_tim.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
struct | TIMEx_EncoderIndexConfigTypeDef
TIM Encoder index configuration. More...

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)
#define | TIM_TIM2_ETR_GPIO 0x00000000U
#define | TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_GPIO 0x00000000U
#define | TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)
#define | TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM4_ETR_GPIO 0x00000000U
#define | TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | TIM_TIM8_ETR_GPIO 0x00000000U
#define | TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2
#define | TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)
#define | TIM_BREAKINPUT_BRK 0x00000001U
#define | TIM_BREAKINPUT_BRK2 0x00000002U
#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U
#define | TIM_BREAKINPUTSOURCE_COMP3 0x00000008U
#define | TIM_BREAKINPUTSOURCE_COMP4 0x00000010U
#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U
#define | TIM_TIM1_TI1_GPIO 0x00000000U
#define | TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM2_TI1_GPIO 0x00000000U
#define | TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM2_TI2_GPIO 0x00000000U
#define | TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM2_TI3_GPIO 0x00000000U
#define | TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0
#define | TIM_TIM2_TI4_GPIO 0x00000000U
#define | TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0
#define | TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1
#define | TIM_TIM3_TI1_GPIO 0x00000000U
#define | TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM3_TI2_GPIO 0x00000000U
#define | TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM3_TI3_GPIO 0x00000000U
#define | TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0
#define | TIM_TIM4_TI1_GPIO 0x00000000U
#define | TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM4_TI2_GPIO 0x00000000U
#define | TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0
#define | TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1
#define | TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2
#define | TIM_TIM4_TI3_GPIO 0x00000000U
#define | TIM_TIM4_TI4_GPIO 0x00000000U
#define | TIM_TIM8_TI1_GPIO 0x00000000U
#define | TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0
#define | TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1
#define | TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2
#define | TIM_TIM15_TI1_GPIO 0x00000000U
#define | TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0
#define | TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1
#define | TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM15_TI2_GPIO 0x00000000U
#define | TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0
#define | TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1
#define | TIM_TIM16_TI1_GPIO 0x00000000U
#define | TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1
#define | TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2
#define | TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
#define | TIM_TIM17_TI1_GPIO 0x00000000U
#define | TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1
#define | TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2
#define | TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
#define | TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U
#define | TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS
#define | TIM_ENCODERINDEX_POSITION_00 0x00000000U
#define | TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0
#define | TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1
#define | TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)
#define | TIM_ENCODERINDEX_POSITION_0 0x00000000U
#define | TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0
#define | TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U
#define | TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0
#define | TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1
#define | TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.
#define | __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.
#define | __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
#define | IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
#define | IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__)
#define | IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__)
#define | IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__)
#define | IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__)
#define | IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
#define | IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
#define | IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U)
#define | IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__)
#define | IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__)
#define | IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__)
#define | IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
#define | IS_TIM_ENCODERINDEX_POSITION(__POSITION__)
#define | IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (const TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_DitheringEnable (TIM_HandleTypeDef *htim)
Enable dithering.
HAL_StatusTypeDef | HAL_TIMEx_DitheringDisable (TIM_HandleTypeDef *htim)
Disable dithering.
HAL_StatusTypeDef | HAL_TIMEx_OC_ConfigPulseOnCompare (TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth)
Initializes the pulse on compare pulse width and pulse prescaler.
HAL_StatusTypeDef | HAL_TIMEx_ConfigSlaveModePreload (TIM_HandleTypeDef *htim, uint32_t Source)
Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableSlaveModePreload (TIM_HandleTypeDef *htim)
Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_DisableSlaveModePreload (TIM_HandleTypeDef *htim)
Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableDeadTimePreload (TIM_HandleTypeDef *htim)
Enable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_DisableDeadTimePreload (TIM_HandleTypeDef *htim)
Disable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_ConfigDeadTime (TIM_HandleTypeDef *htim, uint32_t Deadtime)
Configure deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigAsymmetricalDeadTime (TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
Configure asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_EnableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Enable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_DisableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Disable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigEncoderIndex (TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
Configures the encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderIndex (TIM_HandleTypeDef *htim)
Enable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderIndex (TIM_HandleTypeDef *htim)
Disable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Enable encoder first index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Disable encoder first index.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Commutation callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Commutation half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Break2 detection callback in non blocking mode.
__weak void | HAL_TIMEx_EncoderIndexCallback (TIM_HandleTypeDef *htim)
Encoder index callback in non-blocking mode.
__weak void | HAL_TIMEx_DirectionChangeCallback (TIM_HandleTypeDef *htim)
Direction change callback in non-blocking mode.
__weak void | HAL_TIMEx_IndexErrorCallback (TIM_HandleTypeDef *htim)
Index error callback in non-blocking mode.
__weak void | HAL_TIMEx_TransitionErrorCallback (TIM_HandleTypeDef *htim)
Transition error callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_tim_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions | Variables
stm32g4xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U
#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_RTO (0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE
#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8
#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE
#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN
#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL
#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT
#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR
#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL
#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE
#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM
#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME
#define | UART_CR2_ADDRESS_LSB_POS 24U
#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS
#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP
#define | UART_CR1_DEAT_ADDRESS_LSB_POS 21U
#define | UART_CR1_DEDT_ADDRESS_LSB_POS 16U
#define | UART_IT_MASK 0x001FU
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE
#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | HAL_UART_RECEPTION_STANDARD (0x00000000U)
#define | HAL_UART_RECEPTION_TOIDLE (0x00000001U)
#define | HAL_UART_RECEPTION_TORTO (0x00000002U)
#define | HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)
#define | HAL_UART_RXEVENT_TC (0x00000000U)
#define | HAL_UART_RXEVENT_HT (0x00000001U)
#define | HAL_UART_RXEVENT_IDLE (0x00000002U)
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef uint32_t | HAL_UART_RxTypeTypeDef
HAL UART Reception type definition.
typedef uint32_t | HAL_UART_RxEventTypeTypeDef
HAL UART Rx Event type definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.
typedef void(* | pUART_RxEventCallbackTypeDef )(struct __UART_HandleTypeDef *huart, uint16_t Pos)

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Variables

const uint16_t | UARTPrescTable [12]

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_uart.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0
#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (const UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_uart_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)
#define | HAL_USART_ERROR_UDR (0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | HAL_USART_ERROR_RTO (0x00000080U)
#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1
#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL
#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA
#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL
#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU
#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_RTOF USART_ISR_RTOF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE
#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_CLEAR_RTOF USART_ICR_RTOCF
#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U,
USART_CLOCKSOURCE_LSE = 0x08U, USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_usart.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B (USART_CR1_M1)
#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B (USART_CR1_M0)
#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS
#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN
#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_usart_ex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_wwdg.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g4xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32g4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00U, HAL_WWDG_MSPINIT_CB_ID = 0x01U }
HAL WWDG common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_wwdg.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_adc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
#define | ADC_CHANNEL_ID_MASK
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
#define | ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
#define | ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
#define | ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_15_NUMBER
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS
#define | ADC_AWD_TRX_BIT_HIGH_MASK
#define | ADC_AWD_TRX_BIT_HIGH_POS
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK
#define | ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define | ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
#define | ADC_CR_BITS_PROPERTY_RS
#define | VREFINT_CAL_ADDR
#define | VREFINT_CAL_VREF
#define | TEMPSENSOR_CAL1_ADDR
#define | TEMPSENSOR_CAL2_ADDR
#define | TEMPSENSOR_CAL1_TEMP
#define | TEMPSENSOR_CAL2_TEMP
#define | TEMPSENSOR_CAL_VREFANALOG
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_DMA_REG_REGULAR_DATA
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV16
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256
#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL)
#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)
#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
#define | LL_ADC_OFFSET_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)
#define | LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
#define | LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)
#define | LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN)
#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
#define | LL_ADC_CHANNEL_0
#define | LL_ADC_CHANNEL_1
#define | LL_ADC_CHANNEL_2
#define | LL_ADC_CHANNEL_3
#define | LL_ADC_CHANNEL_4
#define | LL_ADC_CHANNEL_5
#define | LL_ADC_CHANNEL_6
#define | LL_ADC_CHANNEL_7
#define | LL_ADC_CHANNEL_8
#define | LL_ADC_CHANNEL_9
#define | LL_ADC_CHANNEL_10
#define | LL_ADC_CHANNEL_11
#define | LL_ADC_CHANNEL_12
#define | LL_ADC_CHANNEL_13
#define | LL_ADC_CHANNEL_14
#define | LL_ADC_CHANNEL_15
#define | LL_ADC_CHANNEL_16
#define | LL_ADC_CHANNEL_17
#define | LL_ADC_CHANNEL_18
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP2
#define | LL_ADC_CHANNEL_VOPAMP3_ADC2
#define | LL_ADC_CHANNEL_VOPAMP3_ADC3
#define | LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VOPAMP6
#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM7_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO
#define | LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH1
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH2
#define | LL_ADC_REG_TRIG_EXT_TIM20_CH3
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG2
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG4
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
#define | LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE2
#define | LL_ADC_REG_TRIG_EXT_LPTIM_OUT
#define | LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1)
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL)
#define | LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)
#define | LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)
#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
#define | LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS)
#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS
#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH3
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_CH4
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH2
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
#define | LL_ADC_INJ_TRIG_EXT_TIM16_CH1
#define | LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
#define | LL_ADC_INJ_TRIG_EXT_TIM20_CH2
#define | LL_ADC_INJ_TRIG_EXT_TIM20_CH4
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
#define | LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE3
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
#define | LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
#define | LL_ADC_INJ_QUEUE_DISABLE
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
#define | LL_ADC_INJ_RANK_1
#define | LL_ADC_INJ_RANK_2
#define | LL_ADC_INJ_RANK_3
#define | LL_ADC_INJ_RANK_4
#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1)
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2)
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5
#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
#define | LL_ADC_AWD1
#define | LL_ADC_AWD2
#define | LL_ADC_AWD3
#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG
#define | LL_ADC_AWD_ALL_CHANNELS_INJ
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ
#define | LL_ADC_AWD_CHANNEL_0_REG
#define | LL_ADC_AWD_CHANNEL_0_INJ
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ
#define | LL_ADC_AWD_CHANNEL_1_REG
#define | LL_ADC_AWD_CHANNEL_1_INJ
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ
#define | LL_ADC_AWD_CHANNEL_2_REG
#define | LL_ADC_AWD_CHANNEL_2_INJ
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ
#define | LL_ADC_AWD_CHANNEL_3_REG
#define | LL_ADC_AWD_CHANNEL_3_INJ
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ
#define | LL_ADC_AWD_CHANNEL_4_REG
#define | LL_ADC_AWD_CHANNEL_4_INJ
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ
#define | LL_ADC_AWD_CHANNEL_5_REG
#define | LL_ADC_AWD_CHANNEL_5_INJ
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ
#define | LL_ADC_AWD_CHANNEL_6_REG
#define | LL_ADC_AWD_CHANNEL_6_INJ
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ
#define | LL_ADC_AWD_CHANNEL_7_REG
#define | LL_ADC_AWD_CHANNEL_7_INJ
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ
#define | LL_ADC_AWD_CHANNEL_8_REG
#define | LL_ADC_AWD_CHANNEL_8_INJ
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ
#define | LL_ADC_AWD_CHANNEL_9_REG
#define | LL_ADC_AWD_CHANNEL_9_INJ
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ
#define | LL_ADC_AWD_CHANNEL_10_REG
#define | LL_ADC_AWD_CHANNEL_10_INJ
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ
#define | LL_ADC_AWD_CHANNEL_11_REG
#define | LL_ADC_AWD_CHANNEL_11_INJ
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ
#define | LL_ADC_AWD_CHANNEL_12_REG
#define | LL_ADC_AWD_CHANNEL_12_INJ
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ
#define | LL_ADC_AWD_CHANNEL_13_REG
#define | LL_ADC_AWD_CHANNEL_13_INJ
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ
#define | LL_ADC_AWD_CHANNEL_14_REG
#define | LL_ADC_AWD_CHANNEL_14_INJ
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ
#define | LL_ADC_AWD_CHANNEL_15_REG
#define | LL_ADC_AWD_CHANNEL_15_INJ
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ
#define | LL_ADC_AWD_CHANNEL_16_REG
#define | LL_ADC_AWD_CHANNEL_16_INJ
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ
#define | LL_ADC_AWD_CHANNEL_17_REG
#define | LL_ADC_AWD_CHANNEL_17_INJ
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ
#define | LL_ADC_AWD_CHANNEL_18_REG
#define | LL_ADC_AWD_CHANNEL_18_INJ
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ
#define | LL_ADC_AWD_CH_VREFINT_REG
#define | LL_ADC_AWD_CH_VREFINT_INJ
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ
#define | LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ
#define | LL_ADC_AWD_CH_VBAT_REG
#define | LL_ADC_AWD_CH_VBAT_INJ
#define | LL_ADC_AWD_CH_VBAT_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP1_REG
#define | LL_ADC_AWD_CH_VOPAMP1_INJ
#define | LL_ADC_AWD_CH_VOPAMP1_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP2_REG
#define | LL_ADC_AWD_CH_VOPAMP2_INJ
#define | LL_ADC_AWD_CH_VOPAMP2_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_REG
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_REG
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ
#define | LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP4_REG
#define | LL_ADC_AWD_CH_VOPAMP4_INJ
#define | LL_ADC_AWD_CH_VOPAMP4_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP5_REG
#define | LL_ADC_AWD_CH_VOPAMP5_INJ
#define | LL_ADC_AWD_CH_VOPAMP5_REG_INJ
#define | LL_ADC_AWD_CH_VOPAMP6_REG
#define | LL_ADC_AWD_CH_VOPAMP6_INJ
#define | LL_ADC_AWD_CH_VOPAMP6_REG_INJ
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW
#define | LL_ADC_AWD_FILTERING_NONE (0x00000000UL)
#define | LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1)
#define | LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2)
#define | LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)
#define | LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)
#define | LL_ADC_AWD_FILTERING_8SAMPLES
#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE)
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1)
#define | LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2)
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)
#define | LL_ADC_OVS_RATIO_256
#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1)
#define | LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2)
#define | LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)
#define | LL_ADC_OVS_SHIFT_RIGHT_7
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3)
#define | LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)
#define | LL_ADC_MULTI_DUAL_REG_INTERL
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1)
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2)
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3)
#define | LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)
#define | LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
#define | LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV)
#define | LL_ADC_MULTI_MASTER_SLAVE
#define | LL_ADC_TEMPERATURE_CALC_ERROR
#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__)
Helper macro to select, from a ADC instance, to which ADC instance it has a dependence in multimode (ADC master of the corresponding ADC common instance).
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value) in differential ended mode.
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (const ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (const ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChAdd (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChRem (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (const ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (const ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (const ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (const ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (const ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset instance 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset instance 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void | LL_ADC_SetOffsetSign (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset sign.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSign (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset sign if positive or negative.
__STATIC_INLINE void | LL_ADC_SetOffsetSaturation (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
Set for the ADC selected offset instance 1, 2, 3 or 4: choose offset saturation mode.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetSaturation (const ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset instance 1, 2, 3 or 4: offset saturation if enabled or disabled.
__STATIC_INLINE void | LL_ADC_SetGainCompensation (ADC_TypeDef *ADCx, uint32_t GainCompensation)
Set ADC gain compensation.
__STATIC_INLINE uint32_t | LL_ADC_GetGainCompensation (const ADC_TypeDef *ADCx)
Get the ADC gain compensation value.
__STATIC_INLINE void | LL_ADC_SetSamplingTimeCommonConfig (ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
Set ADC sampling time common configuration impacting settings of sampling time channel wise.
__STATIC_INLINE uint32_t | LL_ADC_GetSamplingTimeCommonConfig (const ADC_TypeDef *ADCx)
Get ADC sampling time common configuration impacting settings of sampling time channel wise.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (const ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSamplingMode (ADC_TypeDef *ADCx, uint32_t SamplingMode)
Set ADC sampling mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSamplingMode (const ADC_TypeDef *ADCx)
Get the ADC sampling mode.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (const ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (const ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (const ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (const ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (const ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (const ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (const ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (const ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (const ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (const ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (const ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetAWDFilteringConfiguration (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
Set ADC analog watchdog filtering configuration.
__STATIC_INLINE uint32_t | LL_ADC_GetAWDFilteringConfiguration (const ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog filtering configuration.
__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (const ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 series).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (const ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (const ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (const ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)
__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (const ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.
__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (const ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (const ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (const ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE void | LL_ADC_REG_StartSamplingPhase (ADC_TypeDef *ADCx)
Start ADC sampling phase for sampling time trigger mode.
__STATIC_INLINE void | LL_ADC_REG_StopSamplingPhase (ADC_TypeDef *ADCx)
Stop ADC sampling phase for sampling time trigger mode and start conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (const ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (const ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (const ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (const ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (const ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (const ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (const ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (const ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (const ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (const ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (const ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.
__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (const ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (const ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (const ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (const ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (const ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (const ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (const ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_adc.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_bus.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
#define | LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
#define | LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
#define | LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
#define | LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
#define | LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
#define | LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
#define | LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
#define | LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define | LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
#define | LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
#define | LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_bus.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_comp.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 )
#define | LL_COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_LOW LL_COMP_HYSTERESIS_10MV
#define | LL_COMP_HYSTERESIS_MEDIUM LL_COMP_HYSTERESIS_40MV
#define | LL_COMP_HYSTERESIS_HIGH LL_COMP_HYSTERESIS_70MV
#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 )
#define | LL_COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 )
#define | LL_COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)
#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | LL_COMP_DELAY_STARTUP_US ( 5UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (const COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (const COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (const COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (const COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (const COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (const COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (const COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (const COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_comp.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cordic.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_cordic.h File Reference

Header file of CORDIC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
#define | LL_CORDIC_IT_IEN CORDIC_CSR_IEN
#define | LL_CORDIC_FUNCTION_COSINE (0x00000000U)
#define | LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1))
#define | LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2))
#define | LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))
#define | LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3))
#define | LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))
#define | LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define | LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_7CYCLES
#define | LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define | LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define | LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define | LL_CORDIC_PRECISION_11CYCLES
#define | LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define | LL_CORDIC_PRECISION_13CYCLES
#define | LL_CORDIC_PRECISION_14CYCLES
#define | LL_CORDIC_PRECISION_15CYCLES
#define | LL_CORDIC_SCALE_0 (0x00000000U)
#define | LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define | LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define | LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define | LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define | LL_CORDIC_NBWRITE_1 (0x00000000U)
#define | LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS
#define | LL_CORDIC_NBREAD_1 (0x00000000U)
#define | LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES
#define | LL_CORDIC_INSIZE_32BITS (0x00000000U)
#define | LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE
#define | LL_CORDIC_OUTSIZE_32BITS (0x00000000U)
#define | LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE
#define | LL_CORDIC_DMA_REG_DATA_IN (0x00000000U)
#define | LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U)
#define | LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CORDIC register.
#define | LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CORDIC register.

Functions

__STATIC_INLINE void | LL_CORDIC_Config (CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
Configure the CORDIC processing.
__STATIC_INLINE void | LL_CORDIC_SetFunction (CORDIC_TypeDef *CORDICx, uint32_t Function)
Configure function.
__STATIC_INLINE uint32_t | LL_CORDIC_GetFunction (const CORDIC_TypeDef *CORDICx)
Return function.
__STATIC_INLINE void | LL_CORDIC_SetPrecision (CORDIC_TypeDef *CORDICx, uint32_t Precision)
Configure precision in cycles number.
__STATIC_INLINE uint32_t | LL_CORDIC_GetPrecision (const CORDIC_TypeDef *CORDICx)
Return precision in cycles number.
__STATIC_INLINE void | LL_CORDIC_SetScale (CORDIC_TypeDef *CORDICx, uint32_t Scale)
Configure scaling factor.
__STATIC_INLINE uint32_t | LL_CORDIC_GetScale (const CORDIC_TypeDef *CORDICx)
Return scaling factor.
__STATIC_INLINE void | LL_CORDIC_SetNbWrite (CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
Configure number of 32-bit write expected for one calculation.
__STATIC_INLINE uint32_t | LL_CORDIC_GetNbWrite (const CORDIC_TypeDef *CORDICx)
Return number of 32-bit write expected for one calculation.
__STATIC_INLINE void | LL_CORDIC_SetNbRead (CORDIC_TypeDef *CORDICx, uint32_t NbRead)
Configure number of 32-bit read expected after one calculation.
__STATIC_INLINE uint32_t | LL_CORDIC_GetNbRead (const CORDIC_TypeDef *CORDICx)
Return number of 32-bit read expected after one calculation.
__STATIC_INLINE void | LL_CORDIC_SetInSize (CORDIC_TypeDef *CORDICx, uint32_t InSize)
Configure width of input data.
__STATIC_INLINE uint32_t | LL_CORDIC_GetInSize (const CORDIC_TypeDef *CORDICx)
Return width of input data.
__STATIC_INLINE void | LL_CORDIC_SetOutSize (CORDIC_TypeDef *CORDICx, uint32_t OutSize)
Configure width of output data.
__STATIC_INLINE uint32_t | LL_CORDIC_GetOutSize (const CORDIC_TypeDef *CORDICx)
Return width of output data.
__STATIC_INLINE void | LL_CORDIC_EnableIT (CORDIC_TypeDef *CORDICx)
Enable CORDIC result ready interrupt.
__STATIC_INLINE void | LL_CORDIC_DisableIT (CORDIC_TypeDef *CORDICx)
Disable CORDIC result ready interrupt.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledIT (const CORDIC_TypeDef *CORDICx)
Check CORDIC result ready interrupt state.
__STATIC_INLINE void | LL_CORDIC_EnableDMAReq_RD (CORDIC_TypeDef *CORDICx)
Enable CORDIC DMA read channel request.
__STATIC_INLINE void | LL_CORDIC_DisableDMAReq_RD (CORDIC_TypeDef *CORDICx)
Disable CORDIC DMA read channel request.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledDMAReq_RD (const CORDIC_TypeDef *CORDICx)
Check CORDIC DMA read channel request state.
__STATIC_INLINE void | LL_CORDIC_EnableDMAReq_WR (CORDIC_TypeDef *CORDICx)
Enable CORDIC DMA write channel request.
__STATIC_INLINE void | LL_CORDIC_DisableDMAReq_WR (CORDIC_TypeDef *CORDICx)
Disable CORDIC DMA write channel request.
__STATIC_INLINE uint32_t | LL_CORDIC_IsEnabledDMAReq_WR (const CORDIC_TypeDef *CORDICx)
Check CORDIC DMA write channel request state.
__STATIC_INLINE uint32_t | LL_CORDIC_DMA_GetRegAddr (const CORDIC_TypeDef *CORDICx, uint32_t Direction)
Get the CORDIC data register address used for DMA transfer.
__STATIC_INLINE uint32_t | LL_CORDIC_IsActiveFlag_RRDY (const CORDIC_TypeDef *CORDICx)
Check CORDIC result ready flag state.
__STATIC_INLINE void | LL_CORDIC_WriteData (CORDIC_TypeDef *CORDICx, uint32_t InData)
Write 32-bit input data for the CORDIC processing.
__STATIC_INLINE uint32_t | LL_CORDIC_ReadData (const CORDIC_TypeDef *CORDICx)
Return 32-bit output data of CORDIC processing.
ErrorStatus | LL_CORDIC_DeInit (const CORDIC_TypeDef *CORDICx)
De-Initialize CORDIC peripheral registers to their default reset values.

Detailed Description

Header file of CORDIC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_cordic.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cortex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U
#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetArchitecture (void)
Get Architecture number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)

Definition in file stm32g4xx_ll_cortex.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (const CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (const CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (const CRC_TypeDef *CRCx)
Return type of reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (const CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (const CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (const CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (const CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (const CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_crc.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crs.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_crs.h File Reference

CRS LL module driver. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
#define | LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U)
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV
#define | LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U)
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U)
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U)
#define | LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR)
#define | LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
Reset value of the HSI48 Calibration field.
#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.
#define | __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.
__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.
ErrorStatus | LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Detailed Description

CRS LL module driver.

Header file of CRS LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_crs.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dac.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...

Defines

#define | DAC_CR_CH1_BITOFFSET
#define | DAC_CR_CH2_BITOFFSET
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
#define | DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
#define | DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET
#define | DAC_REG_DHR8R1_REGOFFSET
#define | DAC_REG_DHR12R2_REGOFFSET
#define | DAC_REG_DHR12L2_REGOFFSET
#define | DAC_REG_DHR8R2_REGOFFSET
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
#define | DAC_REG_STR2_REGOFFSET
#define | DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_STRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_STRX_REGOFFSET_BITOFFSET_POS
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define | LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
#define | LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
#define | LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2)
#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
#define | LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2)
#define | LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL
#define | LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0)
#define | LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1)
#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
#define | LL_DAC_TRIG_SOFTWARE 0x00000000UL
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
#define | LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL
#define | LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1)
#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
#define | LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL
#define | LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1)
#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL
#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL
#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.
#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).
#define | __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__)
Helper macro to format sawtooth wave generation configuration value to be filled into WaveAutoGenerationConfig parameter of LL_DAC_InitTypeDef.

Functions

__STATIC_INLINE void | LL_DAC_SetHighFrequencyMode (DAC_TypeDef *DACx, uint32_t HighFreqMode)
Set the high frequency interface mode for the selected DAC instance.
__STATIC_INLINE uint32_t | LL_DAC_GetHighFrequencyMode (const DAC_TypeDef *DACx)
Get the high frequency interface mode for the selected DAC instance.
__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothPolarity (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
Set the swatooth waveform generation polarity.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothPolarity (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation polarity.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothResetData (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
Set the swatooth waveform generation reset data.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothResetData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation reset data.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothStepData (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
Set the sawtooth waveform generation step data.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothStepData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation step data.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothResetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the sawtooth waveform generation reset trigger source.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothResetTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation reset trigger source.
__STATIC_INLINE void | LL_DAC_SetWaveSawtoothStepTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the swatooth waveform generation step trigger source.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveSawtoothStepTriggerSource (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sawtooth waveform generation step trigger source.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE void | LL_DAC_SetSignedFormat (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
Set the signed format for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetSignedFormat (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the signed format state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableDMADoubleDataMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA Double data mode of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMADoubleDataMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA Double data mode of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMADoubleDataModeEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA double data mode state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsReady (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC ready for conversion state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion2 (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by secondary software trigger for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (const DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (const DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (const DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (const DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (const DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DAC1RDY (const DAC_TypeDef *DACx)
Get DAC ready status flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DAC2RDY (const DAC_TypeDef *DACx)
Get DAC ready status flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DORSTAT1 (const DAC_TypeDef *DACx)
Get DAC output register status flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DORSTAT2 (const DAC_TypeDef *DACx)
Get DAC output register status flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (const DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (const DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (const DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (const DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.
ErrorStatus | LL_DAC_DeInit (const DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_dac.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dma.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions | Variables
stm32g4xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32g4xx.h"
#include "stm32g4xx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
#define | DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 0x00000000U
#define | LL_DMA_CHANNEL_2 0x00000001U
#define | LL_DMA_CHANNEL_3 0x00000002U
#define | LL_DMA_CHANNEL_4 0x00000003U
#define | LL_DMA_CHANNEL_5 0x00000004U
#define | LL_DMA_CHANNEL_6 0x00000005U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
Set DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | CHANNEL_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_dma.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dmamux.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_dmamux.h File Reference

Header file of DMAMUX LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | DMAMUX_CCR_SIZE 0x00000004U
#define | DMAMUX_RGCR_SIZE 0x00000004U
#define | UNUSED(X) (void)X
#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14
#define | LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3
#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14
#define | LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3
#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE
#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_DAC1_CH1 0x00000006U
#define | LL_DMAMUX_REQ_DAC1_CH2 0x00000007U
#define | LL_DMAMUX_REQ_TIM6_UP 0x00000008U
#define | LL_DMAMUX_REQ_TIM7_UP 0x00000009U
#define | LL_DMAMUX_REQ_SPI1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_SPI1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_SPI2_RX 0x0000000CU
#define | LL_DMAMUX_REQ_SPI2_TX 0x0000000DU
#define | LL_DMAMUX_REQ_SPI3_RX 0x0000000EU
#define | LL_DMAMUX_REQ_SPI3_TX 0x0000000FU
#define | LL_DMAMUX_REQ_I2C1_RX 0x00000010U
#define | LL_DMAMUX_REQ_I2C1_TX 0x00000011U
#define | LL_DMAMUX_REQ_I2C2_RX 0x00000012U
#define | LL_DMAMUX_REQ_I2C2_TX 0x00000013U
#define | LL_DMAMUX_REQ_I2C3_RX 0x00000014U
#define | LL_DMAMUX_REQ_I2C3_TX 0x00000015U
#define | LL_DMAMUX_REQ_I2C4_RX 0x00000016U
#define | LL_DMAMUX_REQ_I2C4_TX 0x00000017U
#define | LL_DMAMUX_REQ_USART1_RX 0x00000018U
#define | LL_DMAMUX_REQ_USART1_TX 0x00000019U
#define | LL_DMAMUX_REQ_USART2_RX 0x0000001AU
#define | LL_DMAMUX_REQ_USART2_TX 0x0000001BU
#define | LL_DMAMUX_REQ_USART3_RX 0x0000001CU
#define | LL_DMAMUX_REQ_USART3_TX 0x0000001DU
#define | LL_DMAMUX_REQ_UART4_RX 0x0000001EU
#define | LL_DMAMUX_REQ_UART4_TX 0x0000001FU
#define | LL_DMAMUX_REQ_UART5_RX 0x00000020U
#define | LL_DMAMUX_REQ_UART5_TX 0x00000021U
#define | LL_DMAMUX_REQ_LPUART1_RX 0x00000022U
#define | LL_DMAMUX_REQ_LPUART1_TX 0x00000023U
#define | LL_DMAMUX_REQ_ADC2 0x00000024U
#define | LL_DMAMUX_REQ_ADC3 0x00000025U
#define | LL_DMAMUX_REQ_ADC4 0x00000026U
#define | LL_DMAMUX_REQ_ADC5 0x00000027U
#define | LL_DMAMUX_REQ_QSPI 0x00000028U
#define | LL_DMAMUX_REQ_DAC2_CH1 0x00000029U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU
#define | LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU
#define | LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU
#define | LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU
#define | LL_DMAMUX_REQ_TIM1_UP 0x0000002EU
#define | LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU
#define | LL_DMAMUX_REQ_TIM1_COM 0x00000030U
#define | LL_DMAMUX_REQ_TIM8_CH1 0x00000031U
#define | LL_DMAMUX_REQ_TIM8_CH2 0x00000032U
#define | LL_DMAMUX_REQ_TIM8_CH3 0x00000033U
#define | LL_DMAMUX_REQ_TIM8_CH4 0x00000034U
#define | LL_DMAMUX_REQ_TIM8_UP 0x00000035U
#define | LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U
#define | LL_DMAMUX_REQ_TIM8_COM 0x00000037U
#define | LL_DMAMUX_REQ_TIM2_CH1 0x00000038U
#define | LL_DMAMUX_REQ_TIM2_CH2 0x00000039U
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU
#define | LL_DMAMUX_REQ_TIM2_UP 0x0000003CU
#define | LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU
#define | LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU
#define | LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU
#define | LL_DMAMUX_REQ_TIM3_CH4 0x00000040U
#define | LL_DMAMUX_REQ_TIM3_UP 0x00000041U
#define | LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U
#define | LL_DMAMUX_REQ_TIM4_CH1 0x00000043U
#define | LL_DMAMUX_REQ_TIM4_CH2 0x00000044U
#define | LL_DMAMUX_REQ_TIM4_CH3 0x00000045U
#define | LL_DMAMUX_REQ_TIM4_CH4 0x00000046U
#define | LL_DMAMUX_REQ_TIM4_UP 0x00000047U
#define | LL_DMAMUX_REQ_TIM5_CH1 0x00000048U
#define | LL_DMAMUX_REQ_TIM5_CH2 0x00000049U
#define | LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU
#define | LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU
#define | LL_DMAMUX_REQ_TIM5_UP 0x0000004CU
#define | LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU
#define | LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU
#define | LL_DMAMUX_REQ_TIM15_UP 0x0000004FU
#define | LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U
#define | LL_DMAMUX_REQ_TIM15_COM 0x00000051U
#define | LL_DMAMUX_REQ_TIM16_CH1 0x00000052U
#define | LL_DMAMUX_REQ_TIM16_UP 0x00000053U
#define | LL_DMAMUX_REQ_TIM17_CH1 0x00000054U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000055U
#define | LL_DMAMUX_REQ_TIM20_CH1 0x00000056U
#define | LL_DMAMUX_REQ_TIM20_CH2 0x00000057U
#define | LL_DMAMUX_REQ_TIM20_CH3 0x00000058U
#define | LL_DMAMUX_REQ_TIM20_CH4 0x00000059U
#define | LL_DMAMUX_REQ_TIM20_UP 0x0000005AU
#define | LL_DMAMUX_REQ_AES_IN 0x0000005BU
#define | LL_DMAMUX_REQ_AES_OUT 0x0000005CU
#define | LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU
#define | LL_DMAMUX_REQ_TIM20_COM 0x0000005EU
#define | LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU
#define | LL_DMAMUX_REQ_HRTIM1_A 0x00000060U
#define | LL_DMAMUX_REQ_HRTIM1_B 0x00000061U
#define | LL_DMAMUX_REQ_HRTIM1_C 0x00000062U
#define | LL_DMAMUX_REQ_HRTIM1_D 0x00000063U
#define | LL_DMAMUX_REQ_HRTIM1_E 0x00000064U
#define | LL_DMAMUX_REQ_HRTIM1_F 0x00000065U
#define | LL_DMAMUX_REQ_DAC3_CH1 0x00000066U
#define | LL_DMAMUX_REQ_DAC3_CH2 0x00000067U
#define | LL_DMAMUX_REQ_DAC4_CH1 0x00000068U
#define | LL_DMAMUX_REQ_DAC4_CH2 0x00000069U
#define | LL_DMAMUX_REQ_SPI4_RX 0x0000006AU
#define | LL_DMAMUX_REQ_SPI4_TX 0x0000006BU
#define | LL_DMAMUX_REQ_SAI1_A 0x0000006CU
#define | LL_DMAMUX_REQ_SAI1_B 0x0000006DU
#define | LL_DMAMUX_REQ_FMAC_READ 0x0000006EU
#define | LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU
#define | LL_DMAMUX_REQ_CORDIC_READ 0x00000070U
#define | LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U
#define | LL_DMAMUX_REQ_UCPD1_RX 0x00000072U
#define | LL_DMAMUX_REQ_UCPD1_TX 0x00000073U
#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU
#define | LL_DMAMUX_CHANNEL_14 0x0000000EU
#define | LL_DMAMUX_CHANNEL_15 0x0000000FU
#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U
#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Detailed Description

Header file of DMAMUX LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_dmamux.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_exti.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE 0x00000000U
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_exti.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_fmac.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_fmac.h File Reference

Header file of FMAC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_FMAC_SR_SAT FMAC_SR_SAT
#define | LL_FMAC_SR_UNFL FMAC_SR_UNFL
#define | LL_FMAC_SR_OVFL FMAC_SR_OVFL
#define | LL_FMAC_SR_X1FULL FMAC_SR_X1FULL
#define | LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY
#define | LL_FMAC_CR_SATIEN FMAC_CR_SATIEN
#define | LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN
#define | LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN
#define | LL_FMAC_CR_WIEN FMAC_CR_WIEN
#define | LL_FMAC_CR_RIEN FMAC_CR_RIEN
#define | LL_FMAC_WM_0_THRESHOLD_1 0x00000000U
#define | LL_FMAC_WM_1_THRESHOLD_2 0x01000000U
#define | LL_FMAC_WM_2_THRESHOLD_4 0x02000000U
#define | LL_FMAC_WM_3_THRESHOLD_8 0x03000000U
#define | LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)
#define | LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)
#define | LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)
#define | LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)
#define | LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)
#define | LL_FMAC_PROCESSING_STOP 0x00U
#define | LL_FMAC_PROCESSING_START 0x01U
#define | LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in FMAC register.
#define | LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in FMAC register.

Functions

__STATIC_INLINE void | LL_FMAC_SetX1FullWatermark (FMAC_TypeDef *FMACx, uint32_t Watermark)
Configure X1 full watermark.
__STATIC_INLINE uint32_t | LL_FMAC_GetX1FullWatermark (const FMAC_TypeDef *FMACx)
Return X1 full watermark.
__STATIC_INLINE void | LL_FMAC_SetX1BufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure X1 buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetX1BufferSize (const FMAC_TypeDef *FMACx)
Return X1 buffer size.
__STATIC_INLINE void | LL_FMAC_SetX1Base (FMAC_TypeDef *FMACx, uint8_t Base)
Configure X1 base.
__STATIC_INLINE uint8_t | LL_FMAC_GetX1Base (const FMAC_TypeDef *FMACx)
Return X1 base.
__STATIC_INLINE void | LL_FMAC_SetX2BufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure X2 buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetX2BufferSize (const FMAC_TypeDef *FMACx)
Return X2 buffer size.
__STATIC_INLINE void | LL_FMAC_SetX2Base (FMAC_TypeDef *FMACx, uint8_t Base)
Configure X2 base.
__STATIC_INLINE uint8_t | LL_FMAC_GetX2Base (const FMAC_TypeDef *FMACx)
Return X2 base.
__STATIC_INLINE void | LL_FMAC_SetYEmptyWatermark (FMAC_TypeDef *FMACx, uint32_t Watermark)
Configure Y empty watermark.
__STATIC_INLINE uint32_t | LL_FMAC_GetYEmptyWatermark (const FMAC_TypeDef *FMACx)
Return Y empty watermark.
__STATIC_INLINE void | LL_FMAC_SetYBufferSize (FMAC_TypeDef *FMACx, uint8_t BufferSize)
Configure Y buffer size.
__STATIC_INLINE uint8_t | LL_FMAC_GetYBufferSize (const FMAC_TypeDef *FMACx)
Return Y buffer size.
__STATIC_INLINE void | LL_FMAC_SetYBase (FMAC_TypeDef *FMACx, uint8_t Base)
Configure Y base.
__STATIC_INLINE uint8_t | LL_FMAC_GetYBase (const FMAC_TypeDef *FMACx)
Return Y base.
__STATIC_INLINE void | LL_FMAC_EnableStart (FMAC_TypeDef *FMACx)
Start FMAC processing.
__STATIC_INLINE void | LL_FMAC_DisableStart (FMAC_TypeDef *FMACx)
Stop FMAC processing.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledStart (const FMAC_TypeDef *FMACx)
Check the state of FMAC processing.
__STATIC_INLINE void | LL_FMAC_SetFunction (FMAC_TypeDef *FMACx, uint32_t Function)
Configure function.
__STATIC_INLINE uint32_t | LL_FMAC_GetFunction (const FMAC_TypeDef *FMACx)
Return function.
__STATIC_INLINE void | LL_FMAC_SetParamR (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter R.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamR (const FMAC_TypeDef *FMACx)
Return input parameter R.
__STATIC_INLINE void | LL_FMAC_SetParamQ (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter Q.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamQ (const FMAC_TypeDef *FMACx)
Return input parameter Q.
__STATIC_INLINE void | LL_FMAC_SetParamP (FMAC_TypeDef *FMACx, uint8_t Param)
Configure input parameter P.
__STATIC_INLINE uint8_t | LL_FMAC_GetParamP (const FMAC_TypeDef *FMACx)
Return input parameter P.
__STATIC_INLINE void | LL_FMAC_EnableReset (FMAC_TypeDef *FMACx)
Start the FMAC reset.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledReset (const FMAC_TypeDef *FMACx)
Check the state of the FMAC reset.
__STATIC_INLINE void | LL_FMAC_EnableClipping (FMAC_TypeDef *FMACx)
Enable Clipping.
__STATIC_INLINE void | LL_FMAC_DisableClipping (FMAC_TypeDef *FMACx)
Disable Clipping.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledClipping (const FMAC_TypeDef *FMACx)
Check Clipping State.
__STATIC_INLINE void | LL_FMAC_EnableDMAReq_WRITE (FMAC_TypeDef *FMACx)
Enable FMAC DMA write channel request.
__STATIC_INLINE void | LL_FMAC_DisableDMAReq_WRITE (FMAC_TypeDef *FMACx)
Disable FMAC DMA write channel request.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledDMAReq_WRITE (const FMAC_TypeDef *FMACx)
Check FMAC DMA write channel request state.
__STATIC_INLINE void | LL_FMAC_EnableDMAReq_READ (FMAC_TypeDef *FMACx)
Enable FMAC DMA read channel request.
__STATIC_INLINE void | LL_FMAC_DisableDMAReq_READ (FMAC_TypeDef *FMACx)
Disable FMAC DMA read channel request.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledDMAReq_READ (const FMAC_TypeDef *FMACx)
Check FMAC DMA read channel request state.
__STATIC_INLINE void | LL_FMAC_EnableIT_SAT (FMAC_TypeDef *FMACx)
Enable FMAC saturation error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_SAT (FMAC_TypeDef *FMACx)
Disable FMAC saturation error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_SAT (const FMAC_TypeDef *FMACx)
Check FMAC saturation error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_UNFL (FMAC_TypeDef *FMACx)
Enable FMAC underflow error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_UNFL (FMAC_TypeDef *FMACx)
Disable FMAC underflow error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_UNFL (const FMAC_TypeDef *FMACx)
Check FMAC underflow error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_OVFL (FMAC_TypeDef *FMACx)
Enable FMAC overflow error interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_OVFL (FMAC_TypeDef *FMACx)
Disable FMAC overflow error interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_OVFL (const FMAC_TypeDef *FMACx)
Check FMAC overflow error interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_WR (FMAC_TypeDef *FMACx)
Enable FMAC write interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_WR (FMAC_TypeDef *FMACx)
Disable FMAC write interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_WR (const FMAC_TypeDef *FMACx)
Check FMAC write interrupt state.
__STATIC_INLINE void | LL_FMAC_EnableIT_RD (FMAC_TypeDef *FMACx)
Enable FMAC read interrupt.
__STATIC_INLINE void | LL_FMAC_DisableIT_RD (FMAC_TypeDef *FMACx)
Disable FMAC read interrupt.
__STATIC_INLINE uint32_t | LL_FMAC_IsEnabledIT_RD (const FMAC_TypeDef *FMACx)
Check FMAC read interrupt state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_SAT (const FMAC_TypeDef *FMACx)
Check FMAC saturation error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_UNFL (const FMAC_TypeDef *FMACx)
Check FMAC underflow error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_OVFL (const FMAC_TypeDef *FMACx)
Check FMAC overflow error flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_X1FULL (const FMAC_TypeDef *FMACx)
Check FMAC X1 buffer full flag state.
__STATIC_INLINE uint32_t | LL_FMAC_IsActiveFlag_YEMPTY (const FMAC_TypeDef *FMACx)
Check FMAC Y buffer empty flag state.
__STATIC_INLINE void | LL_FMAC_WriteData (FMAC_TypeDef *FMACx, uint16_t InData)
Write 16-bit input data for the FMAC processing.
__STATIC_INLINE uint16_t | LL_FMAC_ReadData (const FMAC_TypeDef *FMACx)
Return 16-bit output data of FMAC processing.
__STATIC_INLINE void | LL_FMAC_ConfigX1 (FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
Configure memory for X1 buffer.
__STATIC_INLINE void | LL_FMAC_ConfigX2 (FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
Configure memory for X2 buffer.
__STATIC_INLINE void | LL_FMAC_ConfigY (FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
Configure memory for Y buffer.
__STATIC_INLINE void | LL_FMAC_ConfigFunc (FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP, uint8_t ParamQ, uint8_t ParamR)
Configure the FMAC processing.
ErrorStatus | LL_FMAC_Init (FMAC_TypeDef *FMACx)
Initialize FMAC peripheral registers to their default reset values.
ErrorStatus | LL_FMAC_DeInit (const FMAC_TypeDef *FMACx)
De-Initialize FMAC peripheral registers to their default reset values.

Detailed Description

Header file of FMAC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_fmac.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_gpio.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0
#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0
#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0
#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1
#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_gpio.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_i2c.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (const I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (const I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (const I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (const I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (const I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (const I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (const I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (const I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (const I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (const I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (const I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (const I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (const I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (const I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (const I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (const I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (const I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (const I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (const I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (const I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (const I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (const I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (const I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (const I2C_TypeDef *I2Cx)
Get the SMBus Extended Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (const I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (const I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (const I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (const I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (const I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (const I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (const I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (const I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (const I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (const I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (const I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (const I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (const I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (const I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (const I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (const I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (const I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (const I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (const I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (const I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (const I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (const I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (const I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (const I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (const I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (const I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (const I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (const I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (const I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (const I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (const I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
ErrorStatus | LL_I2C_DeInit (const I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_i2c.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_iwdg.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (const IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (const IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (const IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (const IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (const IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (const IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_iwdg.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lptim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_lptim.h File Reference

Header file of LPTIM LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN
#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE
#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT
#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE
#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL
#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3
#define | LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT
#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL
#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT
#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
#define | LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
#define | LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Functions

ErrorStatus | LL_LPTIM_DeInit (const LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (const LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (const LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (const LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (const LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (const LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (const LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (const LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (const LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (const LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.
__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (const LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (const LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.
__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (const LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Detailed Description

Header file of LPTIM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_lptim.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lpuart.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions | Variables
stm32g4xx_ll_lpuart.h File Reference

Header file of LPUART LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U
#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF
#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT
#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0
#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10
#define | LL_LPUART_PRESCALER_DIV12
#define | LL_LPUART_PRESCALER_DIV16
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64
#define | LL_LPUART_PRESCALER_DIV128
#define | LL_LPUART_PRESCALER_DIV256
#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.
#define | __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)
#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (const USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (const USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (const USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (const USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (const USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (const USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (const USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (const USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (const USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (const USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (const USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (const USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (const USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (const USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (const USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (const USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.
__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (const USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (const USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (const USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (const USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (const USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (const USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (const USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (const USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (const USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (const USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (const USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (const USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (const USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (const USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.
ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Variables

static const uint16_t | LPUART_PRESCALER_TAB []

Detailed Description

Header file of LPUART LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_lpuart.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_opamp.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_opamp.h File Reference

Header file of OPAMP LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...

Defines

#define | OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_OPAMP_MODE_FUNCTIONAL (0x00000000UL)
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON)
#define | LL_OPAMP_MODE_STANDALONE (0x00000000UL)
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)
#define | LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL)
#define | LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 )
#define | LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 )
#define | LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000UL)
#define | LL_OPAMP_INPUT_NONINVERT_IO1 OPAMP_CSR_VPSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_IO2 OPAMP_CSR_VPSEL_1
#define | LL_OPAMP_INPUT_NONINVERT_IO3 OPAMP_CSR_VPSEL
#define | LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL
#define | LL_OPAMP_INPUT_INVERT_IO0 (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1
#define | LL_OPAMP_INPUT_NONINVERT_IO0_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_NONINVERT_IO1_SEC OPAMP_TCMR_VPSSEL_0
#define | LL_OPAMP_INPUT_NONINVERT_IO2_SEC OPAMP_TCMR_VPSSEL_1
#define | LL_OPAMP_INPUT_NONINVERT_IO3_SEC OPAMP_TCMR_VPSSEL
#define | LL_OPAMP_INPUT_NONINVERT_DAC_SEC OPAMP_TCMR_VPSSEL
#define | LL_OPAMP_INPUT_INVERT_IO0_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_IO1_SEC OPAMP_TCMR_VMSSEL
#define | LL_OPAMP_INPUT_INVERT_PGA_SEC (0x00000000UL)
#define | LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC OPAMP_TCMR_VMSSEL
#define | LL_OPAMP_INTERNAL_OUPUT_DISABLED (0x00000000UL)
#define | LL_OPAMP_INTERNAL_OUPUT_ENABLED OPAMP_CSR_OPAMPINTEN
#define | LL_OPAMP_INPUT_MUX_DISABLE (0x00000000UL)
#define | LL_OPAMP_INPUT_MUX_TIM1_CH6 OPAMP_TCMR_T1CMEN
#define | LL_OPAMP_INPUT_MUX_TIM8_CH6 OPAMP_TCMR_T8CMEN
#define | LL_OPAMP_INPUT_MUX_TIM20_CH6 OPAMP_TCMR_T20CMEN
#define | LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL)
#define | LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN
#define | LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED
#define | LL_OPAMP_TRIMMING_FACTORY (0x00000000UL)
#define | LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0)
#define | LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 )
#define | LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0)
#define | LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP )
#define | LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)
#define | LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)
#define | LL_OPAMP_DELAY_STARTUP_US (6)
#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in OPAMP register.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in OPAMP register.

Functions

__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.
__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode normal or highspeed.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode normal or highspeed.
__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputNonInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input secondary connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInvertingSecondary (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input secondary connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input secondary connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input secondary connection.
__STATIC_INLINE void | LL_OPAMP_SetInputsMuxMode (OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
Set OPAMP inputs multiplexer mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputsMuxMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP inputs multiplexer mode.
__STATIC_INLINE void | LL_OPAMP_SetInternalOutput (OPAMP_TypeDef *OPAMPx, uint32_t InternalOutput)
Set OPAMP internal output.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInternalOutput (OPAMP_TypeDef *OPAMPx)
Get OPAMP internal output state.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)
__STATIC_INLINE void | LL_OPAMP_Lock (OPAMP_TypeDef *OPAMPx)
Lock OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsLocked (OPAMP_TypeDef *OPAMPx)
Get OPAMP lock state (0: OPAMP is unlocked, 1: OPAMP is locked).
__STATIC_INLINE void | LL_OPAMP_LockTimerMux (OPAMP_TypeDef *OPAMPx)
Lock OPAMP instance timer controlled mux.
__STATIC_INLINE uint32_t | LL_OPAMP_IsTimerMuxLocked (OPAMP_TypeDef *OPAMPx)
Get OPAMP timer controlled mux lock state (0: OPAMP timer controlled mux is unlocked, 1: OPAMP timer controlled mux is locked).
ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

Header file of OPAMP LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_opamp.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_pwr.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
#define | LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
#define | LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
#define | LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
#define | LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#define | LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
#define | LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
#define | LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define | LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
#define | LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
#define | LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
#define | LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
#define | LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
#define | LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
#define | LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
#define | LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
#define | LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
#define | LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
#define | LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
#define | LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
#define | LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
#define | LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
#define | LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
#define | LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
#define | LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.
#define | LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
#define | LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
#define | LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
#define | LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
#define | LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
#define | LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
#define | LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
#define | LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
#define | LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
#define | LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
#define | LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode

Functions

__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableRange1BoostMode (void)
Enable main regulator voltage range 1 boost mode.
__STATIC_INLINE void | LL_PWR_DisableRange1BoostMode (void)
Disable main regulator voltage range 1 boost mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledRange1BoostMode (void)
Check if the main regulator voltage range 1 boost mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_EnableUCPDStandbyMode (void)
Enable the USB Type-C and Power Delivery memorization in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableUCPDStandbyMode (void)
Disable the USB Type-C and Power Delivery memorization in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUCPDStandbyMode (void)
Check the USB Type-C and Power Delivery Standby mode memorization state.
__STATIC_INLINE void | LL_PWR_EnableUCPDDeadBattery (void)
Enable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE void | LL_PWR_DisableUCPDDeadBattery (void)
Disable the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledUCPDDeadBattery (void)
Check the USB Type-C and power delivery dead battery pull-down behavior on UCPD CC1 and CC2 pins.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO4 (void)
Indicate whether VDDA voltage is below or above PVM4 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO2 (void)
Indicate whether VDDIO2 voltage is below or above PVM2 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_pwr.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rcc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | RCC_OFFSET_CCIPR 0U
#define | RCC_OFFSET_CCIPR2 0x14U
#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3
#define | LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
#define | LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)
#define | LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U)
#define | LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)
#define | LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)
#define | LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U))
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))
#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1
#define | LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1)
#define | LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
#define | LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1
#define | LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1)
#define | LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U
#define | LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
#define | LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
#define | LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | LL_RCC_ADC12_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U))
#define | LL_RCC_ADC12_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos))
#define | LL_RCC_ADC12_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos))
#define | LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
#define | LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
#define | LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL
#define | LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos))
#define | LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos))
#define | LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos))
#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
#define | LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL
#define | LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL
#define | LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_ADC12_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos))
#define | LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0
#define | LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1
#define | LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2
#define | LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3
#define | LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLR_DIV_2 0x00000000U
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
#define | LL_RCC_PLLQ_DIV_2 0x00000000U
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
Helper macro to calculate the PCLK2 frequency (ABP2)

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetUARTClockSource (uint32_t UARTxSource)
Configure UARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetI2SClockSource (uint32_t I2SxSource)
Configure I2S clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t FDCANxSource)
Configure FDCAN clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUARTClockSource (uint32_t UARTx)
Get UARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2SClockSource (uint32_t I2Sx)
Get I2Sx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t FDCANx)
Get FDCANx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_ADC (void)
Check if PLL output mapped on ADC domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_48M (void)
Check if PLL output mapped on 48MHz domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_SYS (void)
Check if PLL output mapped on SYSCLK domain clock is enabled.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCAN kernel clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rcc.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rng.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_rng.h File Reference

Header file of RNG LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED
#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS
#define | LL_RNG_CR_IE RNG_CR_IE
#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (const RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (const RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (const RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (const RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (const RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (const RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (const RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.
__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (const RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_ReadRandData32 (const RNG_TypeDef *RNGx)
Return32-bit Random Number value.
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.
ErrorStatus | LL_RNG_DeInit (const RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

Header file of RNG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rng.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rtc.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF
#define | RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
#define | RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
#define | RTC_OFFSET_WEEKDAY 24U
#define | RTC_OFFSET_DAY 16U
#define | RTC_OFFSET_MONTH 8U
#define | RTC_OFFSET_HOUR 16U
#define | RTC_OFFSET_MINUTE 8U
#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_CSR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define | LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF
#define | LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
#define | LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
#define | LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
#define | LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
#define | LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
#define | LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
#define | LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07
#define | LL_RTC_MONTH_JANUARY (uint8_t)0x01
#define | LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
#define | LL_RTC_MONTH_MARCH (uint8_t)0x03
#define | LL_RTC_MONTH_APRIL (uint8_t)0x04
#define | LL_RTC_MONTH_MAY (uint8_t)0x05
#define | LL_RTC_MONTH_JUNE (uint8_t)0x06
#define | LL_RTC_MONTH_JULY (uint8_t)0x07
#define | LL_RTC_MONTH_AUGUST (uint8_t)0x08
#define | LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
#define | LL_RTC_MONTH_OCTOBER (uint8_t)0x10
#define | LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
#define | LL_RTC_MONTH_DECEMBER (uint8_t)0x12
#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
#define | LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E
#define | LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E
#define | LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E
#define | LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E
#define | LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E
#define | LL_RTC_BKP_NUMBER RTC_BACKUP_NB
#define | LL_RTC_BKP_DR0 0x00U
#define | LL_RTC_BKP_DR1 0x01U
#define | LL_RTC_BKP_DR2 0x02U
#define | LL_RTC_BKP_DR3 0x03U
#define | LL_RTC_BKP_DR4 0x04U
#define | LL_RTC_BKP_DR5 0x05U
#define | LL_RTC_BKP_DR6 0x06U
#define | LL_RTC_BKP_DR7 0x07U
#define | LL_RTC_BKP_DR8 0x08U
#define | LL_RTC_BKP_DR9 0x09U
#define | LL_RTC_BKP_DR10 0x0AU
#define | LL_RTC_BKP_DR11 0x0BU
#define | LL_RTC_BKP_DR12 0x0CU
#define | LL_RTC_BKP_DR13 0x0DU
#define | LL_RTC_BKP_DR14 0x0EU
#define | LL_RTC_BKP_DR15 0x0FU
#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Enable (RTC_TypeDef *RTCx, uint32_t InternalTamper)
Enable internal tamper detection.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Disable (RTC_TypeDef *RTCx, uint32_t InternalTamper)
Disable internal tamper detection.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_BKP_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BKP_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3 (RTC_TypeDef *RTCx)
Get internal tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4 (RTC_TypeDef *RTCx)
Get internal tamper 4 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5 (RTC_TypeDef *RTCx)
Get internal tamper 5 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6 (RTC_TypeDef *RTCx)
Get internal tamper 6 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (RTC_TypeDef *RTCx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (RTC_TypeDef *RTCx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (RTC_TypeDef *RTCx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3M (RTC_TypeDef *RTCx)
Get internal tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4M (RTC_TypeDef *RTCx)
Get internal tamper 4 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5M (RTC_TypeDef *RTCx)
Get internal tamper 5 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6M (RTC_TypeDef *RTCx)
Get internal tamper 6 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP3 (RTC_TypeDef *RTCx)
Clear internal tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP4 (RTC_TypeDef *RTCx)
Clear internal tamper 4 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP5 (RTC_TypeDef *RTCx)
Clear internal tamper 5 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP6 (RTC_TypeDef *RTCx)
Clear internal tamper 6 detection flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP3 (RTC_TypeDef *RTCx)
Enable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP3 (RTC_TypeDef *RTCx)
Disable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP4 (RTC_TypeDef *RTCx)
Enable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP4 (RTC_TypeDef *RTCx)
Disable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP5 (RTC_TypeDef *RTCx)
Enable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP5 (RTC_TypeDef *RTCx)
Disable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP6 (RTC_TypeDef *RTCx)
Enable internal tamper 6 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP6 (RTC_TypeDef *RTCx)
Disable internal tamper 6 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP3 (RTC_TypeDef *RTCx)
Check if internal tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP4 (RTC_TypeDef *RTCx)
Check if internal tamper 4 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP5 (RTC_TypeDef *RTCx)
Check if internal tamper 5 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP6 (RTC_TypeDef *RTCx)
Check if internal tamper 6 interrupt is enabled or not.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMB field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_rtc.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_spi.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...
struct | LL_I2S_InitTypeDef
I2S Init structure definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U
#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U
#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)
#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)
#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)
#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)
#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.
#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)
#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U
#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock output (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.
__STATIC_INLINE void | LL_I2S_EnableAsyncStart (SPI_TypeDef *SPIx)
Enable asynchronous start.
__STATIC_INLINE void | LL_I2S_DisableAsyncStart (SPI_TypeDef *SPIx)
Disable asynchronous start.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledAsyncStart (SPI_TypeDef *SPIx)
Check if asynchronous start is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_spi.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_system.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
#define | FLASH_PDKEY1 0x04152637U
Power-down in Run mode Flash key.
#define | FLASH_PDKEY2 0xFAFBFCFDU
#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#define | LL_SYSCFG_BANKMODE_BANK1 0x00000000U
#define | LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTF 5U
#define | LL_SYSCFG_EXTI_PORTG 6U
#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP
#define | LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
#define | LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1
#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
#define | LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
#define | LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
#define | LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
#define | LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
#define | LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
#define | LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
#define | LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetFlashBankMode (uint32_t Bank)
Select Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashBankMode (void)
Get Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableCCMSRAMErase (void)
Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsCCMSRAMEraseOngoing (void)
Check if CCMSRAM erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableCCMSRAMPageWRP (uint32_t CCMSRAMWRP)
Enable CCMSRAM page write protection.
__STATIC_INLINE void | LL_SYSCFG_LockCCMSRAMWRP (void)
CCMSRAM page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockCCMSRAMWRP (void)
CCMSRAM page write protection unlock prior to erase.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_EnableRunPowerDown (void)
Enable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_DisableRunPowerDown (void)
Disable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_EnableSleepPowerDown (void)
Enable Flash Power-down mode during Sleep or Low-power sleep mode.
__STATIC_INLINE void | LL_FLASH_DisableSleepPowerDown (void)
Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
      (+) Access to VREFBUF registers

Definition in file stm32g4xx_ll_system.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_tim.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions | Variables
stm32g4xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | OCREF_CLEAR_SELECT_Pos (28U)
Legacy definitions for compatibility purpose.
#define | OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_SR_IDXF TIM_SR_IDXF
#define | LL_TIM_SR_DIRF TIM_SR_DIRF
#define | LL_TIM_SR_IERRF TIM_SR_IERRF
#define | LL_TIM_SR_TERRF TIM_SR_TERRF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_DIER_IDXIE TIM_DIER_IDXIE
#define | LL_TIM_DIER_DIRIE TIM_DIER_DIRIE
#define | LL_TIM_DIER_IERRIE TIM_DIER_IERRIE
#define | LL_TIM_DIER_TERRIE TIM_DIER_TERRIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)
#define | LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)
#define | LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)
#define | LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3
#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)
#define | LL_TIM_SMSPS_TIMUPDATE 0x00000000U
#define | LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR4 TIM_SMCR_TS_3
#define | LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)
#define | LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)
#define | LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)
#define | LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U
#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P
#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U
#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E
#define | LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E
#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U
#define | LL_TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID
#define | LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)
#define | LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2
#define | LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0
#define | LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1
#define | LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2
#define | LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)
#define | LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2
#define | LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1
#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
#define | LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk
#define | LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0
#define | LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1
#define | LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)
#define | LL_TIM_INDEX_UP_DOWN 0x00000000U
#define | LL_TIM_INDEX_UP TIM_ECR_IDIR_0
#define | LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1
#define | LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U
#define | LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0
#define | LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1
#define | LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)
#define | LL_TIM_INDEX_POSITION_DOWN 0x00000000U
#define | LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0
#define | LL_TIM_INDEX_ALL 0x00000000U
#define | LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX
#define | LL_TIM_PWPRSC_X1 0x00000000U
#define | LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0
#define | LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1
#define | LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)
#define | LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2
#define | LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)
#define | LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)
#define | LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)
#define | LL_TIM_HSE_32_NOT_REQUEST 0x00000000U
#define | LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (const TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (const TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (const TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (const TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (const TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (const TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (const TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (const TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (const TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (const TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (const TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (const TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE uint32_t | LL_TIM_IsActiveUIFCPY (const uint32_t Counter)
Indicate whether update interrupt flag (UIF) copy is set.
__STATIC_INLINE void | LL_TIM_EnableDithering (TIM_TypeDef *TIMx)
Enable dithering.
__STATIC_INLINE void | LL_TIM_DisableDithering (TIM_TypeDef *TIMx)
Disable dithering.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDithering (const TIM_TypeDef *TIMx)
Indicates whether dithering is activated.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledPreload (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (const TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (const TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (const TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_OC_SetPulseWidthPrescaler (TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
Set the pulse on compare pulse width prescaler.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPulseWidthPrescaler (const TIM_TypeDef *TIMx)
Get the pulse on compare pulse width prescaler.
__STATIC_INLINE void | LL_TIM_OC_SetPulseWidth (TIM_TypeDef *TIMx, uint32_t PulseWidth)
Set the pulse on compare pulse width duration.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPulseWidth (const TIM_TypeDef *TIMx)
Get the pulse on compare pulse width duration.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (const TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (const TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (const TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (const TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (const TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (const TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (const TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableSMSPreload (TIM_TypeDef *TIMx)
Enable SMS preload.
__STATIC_INLINE void | LL_TIM_DisableSMSPreload (TIM_TypeDef *TIMx)
Disable SMS preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledSMSPreload (const TIM_TypeDef *TIMx)
Indicate whether SMS preload is enabled.
__STATIC_INLINE void | LL_TIM_SetSMSPreloadSource (TIM_TypeDef *TIMx, uint32_t PreloadSource)
Set the preload source of SMS.
__STATIC_INLINE uint32_t | LL_TIM_GetSMSPreloadSource (const TIM_TypeDef *TIMx)
Get the preload source of SMS.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode)
Configure the break input.
__STATIC_INLINE void | LL_TIM_DisarmBRK (TIM_TypeDef *TIMx)
Disarm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_DisarmBRK2 (TIM_TypeDef *TIMx)
Disarm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (const TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (const TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_EnableAsymmetricalDeadTime (TIM_TypeDef *TIMx)
Enable asymmetrical deadtime.
__STATIC_INLINE void | LL_TIM_DisableAsymmetricalDeadTime (TIM_TypeDef *TIMx)
Disable asymmetrical dead-time.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAsymmetricalDeadTime (const TIM_TypeDef *TIMx)
Indicates whether asymmetrical deadtime is activated.
__STATIC_INLINE void | LL_TIM_SetFallingDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
__STATIC_INLINE uint32_t | LL_TIM_GetFallingDeadTime (const TIM_TypeDef *TIMx)
Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
__STATIC_INLINE void | LL_TIM_EnableDeadTimePreload (TIM_TypeDef *TIMx)
Enable deadtime preload.
__STATIC_INLINE void | LL_TIM_DisableDeadTimePreload (TIM_TypeDef *TIMx)
Disable dead-time preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDeadTimePreload (const TIM_TypeDef *TIMx)
Indicates whether deadtime preload is activated.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_EnableEncoderIndex (TIM_TypeDef *TIMx)
Enable encoder index.
__STATIC_INLINE void | LL_TIM_DisableEncoderIndex (TIM_TypeDef *TIMx)
Disable encoder index.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledEncoderIndex (const TIM_TypeDef *TIMx)
Indicate whether encoder index is enabled.
__STATIC_INLINE void | LL_TIM_SetIndexDirection (TIM_TypeDef *TIMx, uint32_t IndexDirection)
Set index direction.
__STATIC_INLINE uint32_t | LL_TIM_GetIndexDirection (const TIM_TypeDef *TIMx)
Get actual index direction.
__STATIC_INLINE void | LL_TIM_EnableFirstIndex (TIM_TypeDef *TIMx)
Enable first index.
__STATIC_INLINE void | LL_TIM_DisableFirstIndex (TIM_TypeDef *TIMx)
Disable first index.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledFirstIndex (const TIM_TypeDef *TIMx)
Indicates whether first index is enabled.
__STATIC_INLINE void | LL_TIM_SetIndexPositionning (TIM_TypeDef *TIMx, uint32_t IndexPositionning)
Set index positioning.
__STATIC_INLINE uint32_t | LL_TIM_GetIndexPositionning (const TIM_TypeDef *TIMx)
Get actual index positioning.
__STATIC_INLINE void | LL_TIM_ConfigIDX (TIM_TypeDef *TIMx, uint32_t Configuration)
Configure encoder index.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_EnableHSE32 (TIM_TypeDef *TIMx)
Enable request for HSE/32 clock used for TISEL remap.
__STATIC_INLINE void | LL_TIM_DisableHSE32 (TIM_TypeDef *TIMx)
Disable request for HSE/32 clock used for TISEL remap.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledHSE32 (const TIM_TypeDef *TIMx)
Indicate whether request for HSE/32 clock is enabled.
__STATIC_INLINE void | LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (const TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (const TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (const TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (const TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (const TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (const TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TERR (TIM_TypeDef *TIMx)
Clear the transition error interrupt flag (TERRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TERR (const TIM_TypeDef *TIMx)
Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_IERR (TIM_TypeDef *TIMx)
Clear the index error interrupt flag (IERRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_IERR (const TIM_TypeDef *TIMx)
Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_DIR (TIM_TypeDef *TIMx)
Clear the direction change interrupt flag (DIRF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_DIR (const TIM_TypeDef *TIMx)
Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_IDX (TIM_TypeDef *TIMx)
Clear the index interrupt flag (IDXF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_IDX (const TIM_TypeDef *TIMx)
Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (const TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TERR (TIM_TypeDef *TIMx)
Enable transition error interrupt (TERRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TERR (TIM_TypeDef *TIMx)
Disable transition error interrupt (TERRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TERR (const TIM_TypeDef *TIMx)
Indicates whether the transition error interrupt (TERRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_IERR (TIM_TypeDef *TIMx)
Enable index error interrupt (IERRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_IERR (TIM_TypeDef *TIMx)
Disable index error interrupt (IERRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_IERR (const TIM_TypeDef *TIMx)
Indicates whether the index error interrupt (IERRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_DIR (TIM_TypeDef *TIMx)
Enable direction change interrupt (DIRIE).
__STATIC_INLINE void | LL_TIM_DisableIT_DIR (TIM_TypeDef *TIMx)
Disable direction change interrupt (DIRIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_DIR (const TIM_TypeDef *TIMx)
Indicates whether the direction change interrupt (DIRIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_IDX (TIM_TypeDef *TIMx)
Enable index interrupt (IDXIE).
__STATIC_INLINE void | LL_TIM_DisableIT_IDX (TIM_TypeDef *TIMx)
Disable index interrupt (IDXIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_IDX (const TIM_TypeDef *TIMx)
Indicates whether the index interrupt (IDXIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.
ErrorStatus | LL_TIM_DeInit (const TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_tim.h.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_ucpd.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_ucpd.h File Reference

Header file of UCPD LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UCPD_InitTypeDef
UCPD Init structures definition. More...

Defines

#define | LL_UCPD_SR_TXIS UCPD_SR_TXIS
#define | LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC
#define | LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT
#define | LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT
#define | LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC
#define | LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT
#define | LL_UCPD_SR_TXUND UCPD_SR_TXUND
#define | LL_UCPD_SR_RXNE UCPD_SR_RXNE
#define | LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET
#define | LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET
#define | LL_UCPD_SR_RXOVR UCPD_SR_RXOVR
#define | LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND
#define | LL_UCPD_SR_RXERR UCPD_SR_RXERR
#define | LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1
#define | LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2
#define | LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1
#define | LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2
#define | LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT
#define | LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE
#define | LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE
#define | LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE
#define | LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE
#define | LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE
#define | LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE
#define | LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE
#define | LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE
#define | LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE
#define | LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE
#define | LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE
#define | LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE
#define | LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE
#define | LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE
#define | LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE
#define | LL_UCPD_SYNC1 0x18u
#define | LL_UCPD_SYNC2 0x11u
#define | LL_UCPD_SYNC3 0x06u
#define | LL_UCPD_RST1 0x07u
#define | LL_UCPD_RST2 0x19u
#define | LL_UCPD_EOP 0x0Du
#define | LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
#define | LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE
#define | LL_UCPD_ROLE_SRC 0x0U
#define | LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0
#define | LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1
#define | LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE
#define | LL_UCPD_RESISTOR_NONE 0x0U
#define | LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
#define | LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
#define | LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
#define | LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
#define | LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
#define | LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
#define | LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
#define | LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
#define | LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8
#define | LL_UCPD_SNK_CC1_VOPEN 0x00u
#define | LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
#define | LL_UCPD_SNK_CC2_VOPEN 0x00u
#define | LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
#define | LL_UCPD_SRC_CC1_VRA 0x0U
#define | LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SRC_CC2_VRA 0x0U
#define | LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_PSC_DIV1 0x0u
#define | LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
#define | LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
#define | LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
#define | LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2
#define | LL_UCPD_CCENABLE_NONE 0x0U
#define | LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
#define | LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
#define | LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)
#define | LL_UCPD_CCPIN_CC1 0x0U
#define | LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL
#define | LL_UCPD_RXMODE_NORMAL 0x0U
#define | LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE
#define | LL_UCPD_TXMODE_NORMAL 0x0U
#define | LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
#define | LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1
#define | LL_UCPD_RXORDSET_SOP 0x0U
#define | LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
#define | LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
#define | LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
#define | LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in UCPD register.
#define | LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in UCPD register.

Functions

__STATIC_INLINE void | LL_UCPD_Enable (UCPD_TypeDef *UCPDx)
Enable UCPD peripheral.
__STATIC_INLINE void | LL_UCPD_Disable (UCPD_TypeDef *UCPDx)
Disable UCPD peripheral.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabled (UCPD_TypeDef const *const UCPDx)
Check if UCPD peripheral is enabled.
__STATIC_INLINE void | LL_UCPD_SetRxOrderSet (UCPD_TypeDef *UCPDx, uint32_t OrderSet)
Set the receiver ordered set detection enable.
__STATIC_INLINE void | LL_UCPD_SetPSCClk (UCPD_TypeDef *UCPDx, uint32_t Psc)
Set the prescaler for ucpd clock.
__STATIC_INLINE void | LL_UCPD_SetTransWin (UCPD_TypeDef *UCPDx, uint32_t TransWin)
Set the number of cycles (minus 1) of the half bit clock.
__STATIC_INLINE void | LL_UCPD_SetIfrGap (UCPD_TypeDef *UCPDx, uint32_t IfrGap)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_SetHbitClockDiv (UCPD_TypeDef *UCPDx, uint32_t HbitClock)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_WakeUpEnable (UCPD_TypeDef *UCPDx)
Enable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_WakeUpDisable (UCPD_TypeDef *UCPDx)
Disable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_ForceClockEnable (UCPD_TypeDef *UCPDx)
Force clock enable.
__STATIC_INLINE void | LL_UCPD_ForceClockDisable (UCPD_TypeDef *UCPDx)
Force clock disable.
__STATIC_INLINE void | LL_UCPD_RxFilterEnable (UCPD_TypeDef *UCPDx)
RxFilter enable.
__STATIC_INLINE void | LL_UCPD_RxFilterDisable (UCPD_TypeDef *UCPDx)
RxFilter disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 disable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeEnable (UCPD_TypeDef *UCPDx)
Source Vconn discharge enable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeDisable (UCPD_TypeDef *UCPDx)
Source Vconn discharge disable.
__STATIC_INLINE void | LL_UCPD_SignalFRSTX (UCPD_TypeDef *UCPDx)
Signal Fast Role Swap request.
__STATIC_INLINE void | LL_UCPD_FRSDetectionEnable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection enable.
__STATIC_INLINE void | LL_UCPD_FRSDetectionDisable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection disable.
__STATIC_INLINE void | LL_UCPD_SetccEnable (UCPD_TypeDef *UCPDx, uint32_t CCEnable)
Set cc enable.
__STATIC_INLINE void | LL_UCPD_SetSNKRole (UCPD_TypeDef *UCPDx)
Set UCPD SNK role.
__STATIC_INLINE void | LL_UCPD_SetSRCRole (UCPD_TypeDef *UCPDx)
Set UCPD SRC role.
__STATIC_INLINE uint32_t | LL_UCPD_GetRole (UCPD_TypeDef const *const UCPDx)
Get UCPD Role.
__STATIC_INLINE void | LL_UCPD_SetRpResistor (UCPD_TypeDef *UCPDx, uint32_t Resistor)
Set Rp resistor.
__STATIC_INLINE void | LL_UCPD_SetCCPin (UCPD_TypeDef *UCPDx, uint32_t CCPin)
Set CC pin.
__STATIC_INLINE void | LL_UCPD_RxEnable (UCPD_TypeDef *UCPDx)
Rx enable.
__STATIC_INLINE void | LL_UCPD_RxDisable (UCPD_TypeDef *UCPDx)
Rx disable.
__STATIC_INLINE void | LL_UCPD_SetRxMode (UCPD_TypeDef *UCPDx, uint32_t RxMode)
Set Rx mode.
__STATIC_INLINE void | LL_UCPD_SendHardReset (UCPD_TypeDef *UCPDx)
Send Hard Reset.
__STATIC_INLINE void | LL_UCPD_SendMessage (UCPD_TypeDef *UCPDx)
Send message.
__STATIC_INLINE void | LL_UCPD_SetTxMode (UCPD_TypeDef *UCPDx, uint32_t TxMode)
Set Tx mode.
__STATIC_INLINE void | LL_UCPD_EnableIT_FRS (UCPD_TypeDef *UCPDx)
Enable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Enable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Enable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Enable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOvr (UCPD_TypeDef *UCPDx)
Enable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxHRST (UCPD_TypeDef *UCPDx)
Enable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Enable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxNE (UCPD_TypeDef *UCPDx)
Enable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxUND (UCPD_TypeDef *UCPDx)
Enable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Enable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Enable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Enable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Enable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Enable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxIS (UCPD_TypeDef *UCPDx)
Enable Tx data receive interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_FRS (UCPD_TypeDef *UCPDx)
Disable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Disable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Disable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Disable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOvr (UCPD_TypeDef *UCPDx)
Disable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxHRST (UCPD_TypeDef *UCPDx)
Disable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Disable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxNE (UCPD_TypeDef *UCPDx)
Disable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxUND (UCPD_TypeDef *UCPDx)
Disable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Disable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Disable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Disable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Disable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Disable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxIS (UCPD_TypeDef *UCPDx)
Disable Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt enabled.
__STATIC_INLINE void | LL_UCPD_ClearFlag_FRS (UCPD_TypeDef *UCPDx)
Clear FRS interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Clear type c event on CC2.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Clear type c event on CC1.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxMsgEnd (UCPD_TypeDef *UCPDx)
Clear Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOvr (UCPD_TypeDef *UCPDx)
Clear Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxHRST (UCPD_TypeDef *UCPDx)
Clear Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOrderSet (UCPD_TypeDef *UCPDx)
Clear Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxUND (UCPD_TypeDef *UCPDx)
Clear TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Clear hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Clear hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGABT (UCPD_TypeDef *UCPDx)
Clear Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGSENT (UCPD_TypeDef *UCPDx)
Clear Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGDISC (UCPD_TypeDef *UCPDx)
Clear Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC2 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC2
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC1 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC1
__STATIC_INLINE void | LL_UCPD_RxDMAEnable (UCPD_TypeDef *UCPDx)
Rx DMA Enable.
__STATIC_INLINE void | LL_UCPD_RxDMADisable (UCPD_TypeDef *UCPDx)
Rx DMA Disable.
__STATIC_INLINE void | LL_UCPD_TxDMAEnable (UCPD_TypeDef *UCPDx)
Tx DMA Enable.
__STATIC_INLINE void | LL_UCPD_TxDMADisable (UCPD_TypeDef *UCPDx)
Tx DMA Disable.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledTxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledRxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_UCPD_WriteTxOrderSet (UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
write the orderset for Tx message
__STATIC_INLINE void | LL_UCPD_WriteTxPaySize (UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
write the Tx paysize
__STATIC_INLINE void | LL_UCPD_WriteData (UCPD_TypeDef *UCPDx, uint8_t Data)
Write data.
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxOrderSet (UCPD_TypeDef const *const UCPDx)
read RX the orderset
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxPaySize (UCPD_TypeDef const *const UCPDx)
Read the Rx paysize.
__STATIC_INLINE uint32_t | LL_UCPD_ReadData (UCPD_TypeDef const *const UCPDx)
Read data.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt1 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext1.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt2 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext2.
ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Detailed Description

Header file of UCPD LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_ucpd.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_usart.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions | Variables
stm32g4xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0
#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (const USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (const USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (const USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (const USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (const USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (const USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (const USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (const USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (const USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (const USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (const USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (const USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (const USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (const USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (const USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (const USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (const USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (const USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (const USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (const USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (const USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (const USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (const USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (const USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (const USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (const USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (const USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (const USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (const USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (const USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (const USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (const USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (const USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (const USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (const USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (const USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (const USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (const USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (const USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (const USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (const USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (const USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (const USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (const USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (const USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (const USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (const USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (const USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (const USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (const USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (const USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (const USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (const USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (const USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (const USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (const USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (const USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (const USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (const USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (const USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (const USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (const USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (const USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (const USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.
ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Variables

static const uint32_t | USART_PRESCALER_TAB []

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_usart.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_utils.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32g4xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U
#define | LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U
#define | LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80
#define | LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U
#define | LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U
#define | LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121
#define | LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U
#define | LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U
#define | LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU
#define | LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU
#define | LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU
#define | LL_UTILS_PACKAGETYPE_TFBGA100 0x0000000EU
#define | LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100
#define | LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions

Definition in file stm32g4xx_ll_utils.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_wwdg.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Defines | Functions
stm32g4xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32g4xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (const WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (const WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (const WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (const WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (const WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (const WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_wwdg.h.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions | Variables
stm32g4xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32G4xx_HAL_VERSION_MAIN (0x01U)
STM32G4xx HAL Driver version number V1.2.2.
#define | __STM32G4xx_HAL_VERSION_SUB1 (0x02U)
#define | __STM32G4xx_HAL_VERSION_SUB2 (0x03U)
#define | __STM32G4xx_HAL_VERSION_RC (0x00U)
#define | __STM32G4xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | FB_MODE_BitNumber ((uint8_t)0x8)
#define | FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
#define | SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
#define | CCMER_BitNumber ((uint8_t)0x0)
#define | SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Returns tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspends Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_CCMSRAMErase (void)
Start a hardware CCMSRAM erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOSwitchVDD (void)
Enable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_DisableIOSwitchVDD (void)
Disable the I/O analog switch voltage by VDD.
void | HAL_SYSCFG_CCMSRAM_WriteProtectionEnable (uint32_t Page)
CCMSRAM page write protection enable.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
uint32_t | uwTickFreq = HAL_TICK_FREQ_DEFAULT

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs

Definition in file stm32g4xx_hal.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g4xx_hal_adc_ex.c". More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (const ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
HAL_StatusTypeDef | HAL_ADC_StartSampling (ADC_HandleTypeDef *hadc)
Start ADC conversion sampling phase of regular group.
HAL_StatusTypeDef | HAL_ADC_StopSampling (ADC_HandleTypeDef *hadc)
Stop ADC conversion sampling phase of regular group and start conversion.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (const ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (const ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g4xx_hal_adc_ex.c".

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.

  (+) Interrupt generation at the end of regular conversion and in case of
      analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) External trigger (timer or EXTI) with configurable polarity

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Configurable delay between conversions in Dual interleaved mode.

  (+) ADC channels selectable single/differential input.

  (+) ADC offset shared on 4 offset instances.
  (+) ADC gain compensation

  (+) ADC calibration

  (+) ADC conversion of regular group.

  (+) ADC supply requirements: 1.62 V to 3.6 V.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
        (++) As prerequisite, ADC clock must be configured at RCC top level.

        (++) Two clock settings are mandatory:
             (+++) ADC clock (core clock, also possibly conversion clock).

             (+++) ADC clock (conversions clock).
                   Two possible clock sources: synchronous clock derived from AHB clock
                   or asynchronous clock derived from system clock or PLL (output divider P)
                   running up to 75MHz.

             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)

               RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

        (++) ADC clock source and clock prescaler are configured at ADC level with
             parameter "ClockPrescaler" using function HAL_ADC_Init().

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, group regular, channels parameters ***
     ================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_ADC_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     [..]

     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
     or @ref HAL_ADC_Init() function.
     [..]

     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_adc.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g4xx_hal_adc.c". More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (318978UL)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (const ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g4xx_hal_adc.c".

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32g4xx_hal_adc.c".
  [..]

Definition in file stm32g4xx_hal_adc_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_comp.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US (5UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (const COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (const COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (const COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
          ##### COMP Peripheral features #####
  ==============================================================================

  [..]
      The STM32G4xx device family integrates seven analog comparators instances:
      COMP1, COMP2, COMP3, COMP4, COMP5, COMP6 and COMP7.
      (#) Comparators input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes.

          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().

            ##### How to use this driver #####
  ==============================================================================
  [..]
      This driver provides functions to configure and program the comparator instances
      of STM32G4xx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity

      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy. In future STM32 families,
          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".

      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() function.

      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
          to manage comparator outputs (events and output level).

      (#) Disable the comparator using HAL_COMP_Stop() function.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_COMP_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function HAL_COMP_RegisterCallback() allows to register following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     [..]

     By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     example HAL_COMP_TriggerCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
     or HAL_COMP_Init() function.
     [..]

     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_comp.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cordic.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_cordic.c File Reference

CORDIC HAL module driver. This file provides firmware functions to manage the following functionalities of the CORDIC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

static void | CORDIC_WriteInDataIncrementPtr (const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
Write input data for CORDIC processing, and increment input buffer pointer.
static void | CORDIC_ReadOutDataIncrementPtr (const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
Read output data of CORDIC processing, and increment output buffer pointer.
static void | CORDIC_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CORDIC Input Data process complete callback.
static void | CORDIC_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CORDIC Output Data process complete callback.
static void | CORDIC_DMAError (DMA_HandleTypeDef *hdma)
DMA CORDIC communication error callback.
HAL_StatusTypeDef | HAL_CORDIC_Init (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_CORDIC_DeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC peripheral.
__weak void | HAL_CORDIC_MspInit (CORDIC_HandleTypeDef *hcordic)
Initialize the CORDIC MSP.
__weak void | HAL_CORDIC_MspDeInit (CORDIC_HandleTypeDef *hcordic)
DeInitialize the CORDIC MSP.
HAL_StatusTypeDef | HAL_CORDIC_RegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void(*pCallback)(CORDIC_HandleTypeDef *_hcordic))
Register a CORDIC CallBack.
HAL_StatusTypeDef | HAL_CORDIC_UnRegisterCallback (CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
Unregister a CORDIC CallBack.
HAL_StatusTypeDef | HAL_CORDIC_Configure (CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
Configure the CORDIC processing according to the specified parameters in the CORDIC_ConfigTypeDef structure.
HAL_StatusTypeDef | HAL_CORDIC_Calculate (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in polling mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_CalculateZO (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
Carry out data of CORDIC processing in Zero-Overhead mode (output data being read soon as input data are written), according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_IT (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
Carry out data of CORDIC processing in interrupt mode, according to the existing CORDIC configuration.
HAL_StatusTypeDef | HAL_CORDIC_Calculate_DMA (CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
Carry out input and/or output data of CORDIC processing in DMA mode, according to the existing CORDIC configuration.
__weak void | HAL_CORDIC_ErrorCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC error callback.
__weak void | HAL_CORDIC_CalculateCpltCallback (CORDIC_HandleTypeDef *hcordic)
CORDIC calculate complete callback.
void | HAL_CORDIC_IRQHandler (CORDIC_HandleTypeDef *hcordic)
Handle CORDIC interrupt request.
HAL_CORDIC_StateTypeDef | HAL_CORDIC_GetState (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC handle state.
uint32_t | HAL_CORDIC_GetError (const CORDIC_HandleTypeDef *hcordic)
Return the CORDIC peripheral error.

Detailed Description

CORDIC HAL module driver. This file provides firmware functions to manage the following functionalities of the CORDIC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ================================================================================
            ##### How to use this driver #####
  ================================================================================
    [..]
      The CORDIC HAL driver can be used as follows:

      (#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit():
         (++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE()
         (++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT())
             (+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler()
         (++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA())
             (+++) Enable the DMA2 interface clock using
                 __HAL_RCC_DMA2_CLK_ENABLE()
             (+++) Configure and enable two DMA channels one for managing data transfer from
                 memory to peripheral (input channel) and another channel for managing data
                 transfer from peripheral to memory (output channel)
             (+++) Associate the initialized DMA handle to the CORDIC DMA handle
                 using __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA channels.
                 Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function
         (++) resorts to HAL_CORDIC_MspInit() for low-level initialization,

      (#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure().
          This function configures:
         (++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent,
              Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent,
              Natural log, Square root
         (++) Scaling factor: 1 to 2exp(-7)
         (++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits
              input data size (Q1.15 format)
         (++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits
              output data size (Q1.15 format)
         (++) Number of 32-bit write expected for one calculation: One 32-bits write
              or Two 32-bit write
         (++) Number of 32-bit read expected after one calculation: One 32-bits read
              or Two 32-bit read
         (++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision)

      (#) Four processing (calculation) functions are available:
         (++) Polling mode: processing API is blocking function
              i.e. it processes the data and wait till the processing is finished
              API is HAL_CORDIC_Calculate
         (++) Polling Zero-overhead mode: processing API is blocking function
              i.e. it processes the data and wait till the processing is finished
              A bit faster than standard polling mode, but blocking also AHB bus
              API is HAL_CORDIC_CalculateZO
         (++) Interrupt mode: processing API is not blocking functions
              i.e. it processes the data under interrupt
              API is HAL_CORDIC_Calculate_IT
         (++) DMA mode: processing API is not blocking functions and the CPU is
              not used for data transfer,
              i.e. the data transfer is ensured by DMA
              API is HAL_CORDIC_Calculate_DMA

      (#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function
         (++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization,

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.

  Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
    (+) ErrorCallback             : Error Callback.
    (+) CalculateCpltCallback     : Calculate complete Callback.
    (+) MspInitCallback           : CORDIC MspInit.
    (+) MspDeInitCallback         : CORDIC MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) ErrorCallback             : Error Callback.
    (+) CalculateCpltCallback     : Calculate complete Callback.
    (+) MspInitCallback           : CORDIC MspInit.
    (+) MspDeInitCallback         : CORDIC MspDeInit.

  By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
  all callbacks are set to the corresponding weak functions:
  examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
  or HAL_CORDIC_Init() function.

  When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_cordic.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cortex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M4 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest pre-emption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure SysTick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32g4xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF

The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.

========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bit for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bit for subpriority ==========================================================================================================================

Definition in file stm32g4xx_hal_cortex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (const CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++) specify generating polynomial (peripheral default or non-default one)
             (++) specify initialization value (peripheral default or non-default one)
             (++) specify input data format
             (++) specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation

Definition in file stm32g4xx_hal_crc.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion

Definition in file stm32g4xx_hal_crc_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
#define | HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
#define | HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (const DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (const DAC_HandleTypeDef *hdac)
Return the DAC error code.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (overridden) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (overridden) predefined callback.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    STM32G4 devices integrate up to seven 12-bit Digital Analog Converters,
    up to six of them grouped by pair forming a DAC instance.

    The 2 converters of an single instance (i.e. channel1 & channel2)
    can be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip
          peripherals (ex. comparators, operational amplifier).
      (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip
          peripherals (ex. comparators, operational amplifier).
    Note: when an instance only includes one converter, only independent mode is
        supported by this converter.

    STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx):
    ----------------------------------------------------------------------------
                           |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
    ----------------------------------------------------------------------------
    Channel 1  |           |    YES     |    YES     |    YES     |    YES
               | DAC_OUT1  |    PA4     |    PA6     |     -      |     -
    ----------------------------------------------------------------------------
    Channel 2  |           |    YES     |    NO      |    YES     |    YES
               | DAC_OUT2  |    PA5     |     -      |     -      |     -
    ----------------------------------------------------------------------------
    Note: On this STM32 series, all devices do not include each DAC instances listed
          above. Refer to device datasheet for DACx instance availability.

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      (#) HRTimer TRGO: HRTIM1 (1)
          (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...)

    [..]
    Specific triggers for sawtooth generation:
      (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10.
          The used pin (GPIOx_PIN_10) must be configured in input mode.

      (#) HRTimer Step & Reset: HRTIM1 (1)
          (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...)

      Note: On this STM32 series, parameter only available if HRTIM feature is
            supported (refer to device datasheet for supported features list)

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** DAC connect feature ***
      ===============================
      [..]
      Each DAC channel can be connected internally.
      To connect, use
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
      or
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

      *** DAC Sample and Hold feature ***
      ========================
      [..]
      For each converter, 2 modes are supported: normal mode and
      "sample and hold" mode (i.e. low power mode).
      In the sample and hold mode, the DAC core converts data, then holds the
      converted voltage on a capacitor. When not converting, the DAC cores and
      buffer are completely turned off between samples and the DAC output is
      tri-stated, therefore  reducing the overall power consumption. A new
      stabilization period is needed before each new conversion.

      The sample and hold allow setting internal or external voltage @
      low power consumption cost (output value can be at any given rate either
      by CPU or DMA).

      The Sample and hold block and registers uses either LSI & run in
      several power modes: run mode, sleep mode, low power run, low power sleep
      mode & stop1 mode.

      Low power stop1 mode allows only static conversion.

      To enable Sample and Hold mode
      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
      RCC_LSI_ON parameters.

      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
           DAC_HoldTime & DAC_RefreshTime;

       *** DAC calibration feature ***
       ===================================
      [..]
       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
       (++) Calibration aims at correcting some offset of output buffer.
       (++) The DAC uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_DACEx_SelfCalibrate.
       (++) HAL_DACEx_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates a structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave
         (#) Triangle wave
         (#) Sawtooth wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VREF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests ***
       =====================
       [..]
       A DMAMUX request can be generated when an external trigger (but not a software trigger)
       occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA().
       DMAMUX requests are mapped as following:
        ----------------------------------------------------------------------------
                               |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
        ----------------------------------------------------------------------------
        Channel 1  |           |     6      |     41     |    102     |    104
        ----------------------------------------------------------------------------
        Channel 2  |           |     7      |     -      |    103     |    105
        ----------------------------------------------------------------------------
        Note: On this STM32 series, all devices do not include each DAC instances listed
              above. Refer to device datasheet for DACx instance availability.

       *** High frequency interface mode ***
       =====================================
       [..]
       The high frequency interface informs DAC instance about the bus frequency in use.
       It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
       provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
       Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
       function figured out the correct setting.
       The high frequency mode is same for all converters of a same DAC instance. Either same
       parameter DAC_HighFrequency is used for all DAC converters or again self
       DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.

     [..]
    (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation
        please refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.

     *** Calibration mode IO operation ***
     ======================================
     [..]
       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

    Use Functions HAL_DAC_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

    Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
      weak (overridden) function. It allows to reset following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      (+) All Callbacks
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (overridden) functions in the HAL_DAC_Init
      and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
      or HAL_DAC_Init function.

      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (overridden) callbacks are used.

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros

Definition in file stm32g4xx_hal_dac.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_dac_ex.c File Reference

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | DAC_DELAY_TRIM_US (50UL)

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStart_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
HAL_StatusTypeDef | HAL_DACEx_DualStop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion both channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData)
Enable or disable the selected DAC channel sawtooth wave generation.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataReset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave reset.
HAL_StatusTypeDef | HAL_DACEx_SawtoothWaveDataStep (DAC_HandleTypeDef *hdac, uint32_t Channel)
Trig sawtooth wave step.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (const DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (const DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
     *** Dual mode IO operation ***
     ==============================
     [..]
      (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
          for dual mode operation.
          If software trigger is selected, using HAL_DACEx_DualStart() will start
          the conversion of the value previously set by HAL_DACEx_DualSetValue().
      (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
          for dual mode operation.
      (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
          for dual mode operation using DMA to feed DAC converters.
          First issued trigger will start the conversion of the value previously
          set by HAL_DACEx_DualSetValue().
          The same callbacks that are used in single mode are called in dual mode to notify
          transfer completion (half complete or complete), errors or underrun.
      (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
          for dual mode operation using DMA to feed DAC converters.
      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
          Channel 1 and Channel 2.
     *** Signal generation operation ***
     ===================================
     [..]
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.

      (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal.
      (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave.
      (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave.

      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
          at least one time after reset).

Definition in file stm32g4xx_hal_dac_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on stream number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
       thanks to:
      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
      (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred.
              In this case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function to register callbacks with HAL_DMA_RegisterCallback().

     *** DMA HAL driver macros list ***
     =============================================
      [..]
       Below the list of macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros

Definition in file stm32g4xx_hal_dma.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:

   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)

Definition in file stm32g4xx_hal_dma_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_exti.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_exti.c File Reference

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the Extended Interrupts and events controller (EXTI) peripheral: functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the Extended Interrupts and events controller (EXTI) peripheral: functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### EXTI Peripheral features #####
  ==============================================================================
  [..]
    (+) Each Exti line can be configured within this driver.

    (+) Exti line can be configured in 3 different modes
        (++) Interrupt
        (++) Event
        (++) Both of them

    (+) Configurable Exti lines can be configured with 3 different triggers
        (++) Rising
        (++) Falling
        (++) Both of them

    (+) When set in interrupt mode, configurable Exti lines have two different
        interrupt pending registers which allow to distinguish which transition
        occurs:
        (++) Rising edge pending interrupt
        (++) Falling

    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
        be selected through multiplexer.

                     ##### How to use this driver #####
  ==============================================================================
  [..]

    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
        (++) Choose the interrupt line number by setting "Line" member from
             EXTI_ConfigTypeDef structure.
        (++) Configure the interrupt and/or event mode using "Mode" member from
             EXTI_ConfigTypeDef structure.
        (++) For configurable lines, configure rising and/or falling trigger
             "Trigger" member from EXTI_ConfigTypeDef structure.
        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
             member from GPIO_InitTypeDef structure.

    (#) Get current Exti configuration of a dedicated line using
        HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.
        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.

    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
        (++) Provide exiting handle as parameter.

    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
        (++) Provide exiting handle as first parameter.
        (++) Provide which callback will be registered using one value from
             EXTI_CallbackIDTypeDef.
        (++) Provide callback function pointer.

    (#) Get interrupt pending bit using HAL_EXTI_GetPending().

    (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().

    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().

Definition in file stm32g4xx_hal_exti.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fdcan.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions | Variables
stm32g4xx_hal_fdcan.c File Reference

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define | SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define | SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define | SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define | SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define | SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define | SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define | SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define | SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define | SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define | SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define | SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define | SRAMCAN_FLSSA
#define | SRAMCAN_FLESA
#define | SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define | SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define | SRAMCAN_TEFSA
#define | SRAMCAN_TFQSA
#define | SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Functions

static void | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (const FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (const FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (const FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (const FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (const FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (const FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Variables

static const uint8_t | DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Detailed Description

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.

      (#) If needed , configure the reception filters and optional features using
          the following configuration functions:
            (++) HAL_FDCAN_ConfigFilter
            (++) HAL_FDCAN_ConfigGlobalFilter
            (++) HAL_FDCAN_ConfigExtendedIdMask
            (++) HAL_FDCAN_ConfigRxFifoOverwrite
            (++) HAL_FDCAN_ConfigRamWatchdog
            (++) HAL_FDCAN_ConfigTimestampCounter
            (++) HAL_FDCAN_EnableTimestampCounter
            (++) HAL_FDCAN_DisableTimestampCounter
            (++) HAL_FDCAN_ConfigTimeoutCounter
            (++) HAL_FDCAN_EnableTimeoutCounter
            (++) HAL_FDCAN_DisableTimeoutCounter
            (++) HAL_FDCAN_ConfigTxDelayCompensation
            (++) HAL_FDCAN_EnableTxDelayCompensation
            (++) HAL_FDCAN_DisableTxDelayCompensation
            (++) HAL_FDCAN_EnableISOMode
            (++) HAL_FDCAN_DisableISOMode
            (++) HAL_FDCAN_EnableEdgeFiltering
            (++) HAL_FDCAN_DisableEdgeFiltering

      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
          the node is active on the bus: it can send and receive messages.

      (#) The following Tx control functions can only be called when the FDCAN
          module is started:
            (++) HAL_FDCAN_AddMessageToTxFifoQ
            (++) HAL_FDCAN_AbortTxRequest

      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
          get Tx buffer location used to place the Tx request thanks to
          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
          It is then possible to abort later on the corresponding Tx Request using
          HAL_FDCAN_AbortTxRequest API.

      (#) When a message is received into the FDCAN message RAM, it can be
          retrieved using the HAL_FDCAN_GetRxMessage function.

      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
          it to initialization mode and re-enabling access to configuration
          registers through the configuration functions listed here above.

      (#) All other control functions can be called any time after initialization
          phase, no matter if the FDCAN module is started or stopped.

      *** Polling mode operation ***
      ==============================
    [..]
        (#) Reception and transmission states can be monitored via the following
            functions:
              (++) HAL_FDCAN_IsTxBufferMessagePending
              (++) HAL_FDCAN_GetRxFifoFillLevel
              (++) HAL_FDCAN_GetTxFifoFreeLevel

      *** Interrupt mode operation ***
      ================================
      [..]
        (#) There are two interrupt lines: line 0 and 1.
            By default, all interrupts are assigned to line 0. Interrupt lines
            can be configured using HAL_FDCAN_ConfigInterruptLines function.

        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
            function. Then, the process can be controlled through one of the
            available user callbacks: HAL_FDCAN_xxxCallback.

  *** Callback registration ***
  =============================================

  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
  to register an interrupt callback.

  Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
  TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
  register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
  HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
  HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
  and HAL_FDCAN_RegisterErrorStatusCallback().

  Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.

  For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
  TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
  unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
  HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
  HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
  and HAL_FDCAN_UnRegisterErrorStatusCallback().

  By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
  all callbacks are set to the corresponding weak functions:
  examples HAL_FDCAN_ErrorCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
  or HAL_FDCAN_Init() function.

  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_fdcan.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions | Variables
stm32g4xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_NB_DOUBLE_WORDS_IN_ROW 32

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Option bytes programming
      (+) Prefetch on I-Code
      (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
      (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
      (+) Error code correction (ECC) : Data in flash are 72-bits word
          (8 bits added per double word)

                        ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32G4xx devices.

      (#) Flash Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: double word and fast program (full row programming)
           (++) There are two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions:
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_GetError()

      (#) Option bytes management functions:
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
                In this case, a reset is generated

    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the Instruction cache and the Data cache
       (+) Reset the Instruction cache and the Data cache
       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
       (+) Enable/Disable the Flash interrupts
       (+) Monitor the Flash flags status
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
static HAL_StatusTypeDef | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection area into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
Configure the Proprietary code readout protection area into Option Bytes.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the Write Protection configuration into Option Bytes.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level into Option Bytes.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
Return the FLASH PCROP configuration into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_SecMemConfig (uint32_t SecBank, uint32_t SecSize)
Configure the Securable memory area into Option Bytes.
static void | FLASH_OB_GetSecMem (uint32_t SecBank, uint32_t *SecSize)
Return the Securable memory area configuration into Option Bytes.
static HAL_StatusTypeDef | FLASH_OB_BootLockConfig (uint32_t BootLockConfig)
Configure the Boot Lock into Option Bytes.
static uint32_t | FLASH_OB_GetBootLock (void)
Return the Boot Lock configuration into Option Byte.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
HAL_StatusTypeDef | HAL_FLASHEx_EnableSecMemProtection (uint32_t Bank)
Enable the FLASH Securable Memory protection.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

Author:
MCD Application Team
  ==============================================================================
                   ##### Flash Extended features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
       devices contains the following additional features

       (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits
       (+) Protected areas including WRP, PCROP and Securable memory

                        ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32G4xx devices. It includes
      (#) Flash Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase pages, or mass erase banks
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
        (++) Configure the write protection areas (WRP)
        (++) Set the Read protection Level (RDP)
        (++) Program the user Option Bytes
        (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
        (++) Configure the Securable memory areas
        (++) Configure the Boot Lock

      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
        (++) Get the configuration of write protection areas (WRP)
        (++) Get the level of read protection (RDP)
        (++) Get the value of the user Option Bytes
        (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP)
        (++) Get the configuration of Securable memory areas
        (++) Get the status of Boot Lock

      (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection()
        (++) Deny the access to securable memory area

      (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
          HAL_FLASHEx_DisableDebugger()
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ramfunc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_flash_ramfunc.c File Reference

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH Power Down in Run mode + FLASH DBANK User Option Byte. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC HAL_StatusTypeDef | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH Power Down in Run mode + FLASH DBANK User Option Byte.

Author:
MCD Application Team
  ==============================================================================
                   ##### Flash RAM functions #####
  ==============================================================================

    *** ARM Compiler ***
    --------------------
    [..] RAM functions are defined using the toolchain options.
         Functions that are executed in RAM should reside in a separate
         source module. Using the 'Options for File' dialog you can simply change
         the 'Code / Const' area of a module to a memory space in physical RAM.
         Available memory areas are declared in the 'Target' tab of the
         Options for Target' dialog.

    *** ICCARM Compiler ***
    -----------------------
    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".

    *** GNU Compiler ***
    --------------------
    [..] RAM functions are defined using a specific toolchain attribute
         "__attribute__((section(".RamFunc")))".
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_flash_ramfunc.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fmac.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_fmac.c File Reference

FMAC HAL module driver. This file provides firmware functions to manage the following functionalities of the FMAC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State and Error functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
#define | MAX_PRELOAD_INDEX 0xFFU
#define | PRELOAD_ACCESS_DMA 0x00U
#define | PRELOAD_ACCESS_POLLING 0x01U
#define | POLLING_DISABLED 0U
#define | POLLING_ENABLED 1U
#define | POLLING_NOT_STOPPED 0U
#define | POLLING_STOPPED 1U
#define | HAL_FMAC_TIMEOUT_VALUE 1000U
#define | HAL_FMAC_RESET_TIMEOUT_VALUE 500U
#define | FMAC_DMA_REN FMAC_CR_DMAREN
#define | FMAC_DMA_WEN FMAC_CR_DMAWEN
#define | FMAC_START FMAC_PARAM_START
#define | FMAC_GET_X1_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
Get the X1 memory area size.
#define | FMAC_GET_X1_FULL_WM(__HANDLE__) (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
Get the X1 watermark.
#define | FMAC_GET_X2_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
Get the X2 memory area size.
#define | FMAC_GET_Y_SIZE(__HANDLE__) ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
Get the Y memory area size.
#define | FMAC_GET_Y_EMPTY_WM(__HANDLE__) (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
Get the Y watermark.
#define | FMAC_GET_START_BIT(__HANDLE__) ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
Get the start bit state.
#define | FMAC_GET_THRESHOLD_FROM_WM(__WM__)
Get the threshold matching the watermark.

Functions

static HAL_StatusTypeDef | FMAC_Reset (FMAC_HandleTypeDef *hfmac)
============================================================================== ##### FMAC Private Functions ##### ==============================================================================
static void | FMAC_ResetDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the data pointers of the FMAC unit.
static void | FMAC_ResetOutputStateAndDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the output data pointers of the FMAC unit.
static void | FMAC_ResetInputStateAndDataPointers (FMAC_HandleTypeDef *hfmac)
Reset the input data pointers of the FMAC unit.
static HAL_StatusTypeDef | FMAC_FilterConfig (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess)
Configure the FMAC filter.
static HAL_StatusTypeDef | FMAC_FilterPreload (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
static void | FMAC_WritePreloadDataIncrementPtr (FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
Write data into FMAC internal memory through WDATA and increment input buffer pointer.
static HAL_StatusTypeDef | FMAC_WaitOnStartUntilTimeout (FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
Handle FMAC Function Timeout.
static HAL_StatusTypeDef | FMAC_AppendFilterDataUpdateState (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
Register the new input buffer, update DMA configuration if needed and change the FMAC state.
static HAL_StatusTypeDef | FMAC_ConfigFilterOutputBufferUpdateState (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Register the new output buffer, update DMA configuration if needed and change the FMAC state.
static void | FMAC_WriteDataIncrementPtr (FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
Write available input data until X1 FULL is set.
static void | FMAC_ReadDataIncrementPtr (FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
Read available output data until Y EMPTY is set.
static void | FMAC_DMAHalfGetData (DMA_HandleTypeDef *hdma)
DMA FMAC Input Data process half complete callback.
static void | FMAC_DMAGetData (DMA_HandleTypeDef *hdma)
DMA FMAC Input Data process complete callback.
static void | FMAC_DMAHalfOutputDataReady (DMA_HandleTypeDef *hdma)
DMA FMAC Output Data process half complete callback.
static void | FMAC_DMAOutputDataReady (DMA_HandleTypeDef *hdma)
DMA FMAC Output Data process complete callback.
static void | FMAC_DMAFilterConfig (DMA_HandleTypeDef *hdma)
DMA FMAC Filter Configuration process complete callback.
static void | FMAC_DMAFilterPreload (DMA_HandleTypeDef *hdma)
DMA FMAC Filter Configuration process complete callback.
static void | FMAC_DMAError (DMA_HandleTypeDef *hdma)
DMA FMAC communication error callback.
HAL_StatusTypeDef | HAL_FMAC_Init (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC peripheral and the associated handle.
HAL_StatusTypeDef | HAL_FMAC_DeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC peripheral.
__weak void | HAL_FMAC_MspInit (FMAC_HandleTypeDef *hfmac)
Initialize the FMAC MSP.
__weak void | HAL_FMAC_MspDeInit (FMAC_HandleTypeDef *hfmac)
De-initialize the FMAC MSP.
HAL_StatusTypeDef | HAL_FMAC_RegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID, pFMAC_CallbackTypeDef pCallback)
Register a User FMAC Callback.
HAL_StatusTypeDef | HAL_FMAC_UnRegisterCallback (FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
Unregister a FMAC CallBack.
HAL_StatusTypeDef | HAL_FMAC_FilterConfig (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterConfig_DMA (FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
Configure the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterPreload_DMA (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize)
Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
HAL_StatusTypeDef | HAL_FMAC_FilterStart (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Start the FMAC processing according to the existing FMAC configuration.
HAL_StatusTypeDef | HAL_FMAC_AppendFilterData (FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
Provide a new input buffer that will be loaded into the FMAC input memory area.
HAL_StatusTypeDef | HAL_FMAC_ConfigFilterOutputBuffer (FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
Provide a new output buffer to be filled with the data computed by FMAC unit.
HAL_StatusTypeDef | HAL_FMAC_PollFilterData (FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
Handle the input and/or output data in polling mode.
HAL_StatusTypeDef | HAL_FMAC_FilterStop (FMAC_HandleTypeDef *hfmac)
Stop the FMAC processing.
__weak void | HAL_FMAC_ErrorCallback (FMAC_HandleTypeDef *hfmac)
FMAC error callback.
__weak void | HAL_FMAC_HalfGetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get half data callback.
__weak void | HAL_FMAC_GetDataCallback (FMAC_HandleTypeDef *hfmac)
FMAC get data callback.
__weak void | HAL_FMAC_HalfOutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC half output data ready callback.
__weak void | HAL_FMAC_OutputDataReadyCallback (FMAC_HandleTypeDef *hfmac)
FMAC output data ready callback.
__weak void | HAL_FMAC_FilterConfigCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter configuration callback.
__weak void | HAL_FMAC_FilterPreloadCallback (FMAC_HandleTypeDef *hfmac)
FMAC filter preload callback.
void | HAL_FMAC_IRQHandler (FMAC_HandleTypeDef *hfmac)
Handle FMAC interrupt request.
HAL_FMAC_StateTypeDef | HAL_FMAC_GetState (const FMAC_HandleTypeDef *hfmac)
Return the FMAC state.
uint32_t | HAL_FMAC_GetError (const FMAC_HandleTypeDef *hfmac)
Return the FMAC peripheral error.

Detailed Description

FMAC HAL module driver. This file provides firmware functions to manage the following functionalities of the FMAC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
      The FMAC HAL driver can be used as follows:

      (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
          (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
          (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
               (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
               (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
               (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
          (++) In case of using DMA to control data transfer (e.g. access configured
               as FMAC_BUFFER_ACCESS_DMA):
               (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
                     or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
               (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
               (+++) If the initialization of the internal buffers (coefficients, input,
                     output) is done via DMA, configure and enable one DMA channel for
                     managing data transfer from memory to memory (preload channel).
               (+++) If the input buffer is accessed via DMA, configure and enable one
                     DMA channel for managing data transfer from memory to peripheral
                     (input channel).
               (+++) If the output buffer is accessed via DMA, configure and enable
                     one DMA channel for managing data transfer from peripheral to
                     memory (output channel).
               (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
                     using __HAL_LINKDMA().
               (+++) Configure the priority and enable the NVIC for the transfer complete
                     interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
                     and HAL_NVIC_EnableIRQ().

      (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
          resorts to HAL_FMAC_MspInit() for low-level initialization.

      (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
          or HAL_FMAC_FilterConfig_DMA().
          This function:
          (++) Defines the memory area within the FMAC internal memory
               (input, coefficients, output) and the associated threshold (input, output).
          (++) Configures the filter and its parameters:
               (+++) Finite Impulse Response (FIR) filter (also known as convolution).
               (+++) Infinite Impulse Response (IIR) filter (direct form 1).
          (++) Choose the way to access to the input and output buffers: none, polling,
               DMA, IT. "none" means the input and/or output data will be handled by
               another IP (ADC, DAC, etc.).
          (++) Enable the error interruptions in the input access and/or the output
               access is done through IT/DMA. If an error occurs, the interruption
               will be triggered in loop. In order to recover, the user will have
               to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
               Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
               the error status will be kept, but no more interrupt will be triggered.
          (++) Write the provided coefficients into the internal memory using polling
               mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
               In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
               the handling is over.

       (#) Optionally, the user can enable the error interruption related to
           saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
           filter. If a saturation occurs, the interruption will be triggered in loop.
           In order to recover, the user will have to:
           (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
                the user wishes to continue all the same.
           (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.

       (#) Optionally, preload input (FIR, IIR) and output (IIR) data using
           HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
           In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
           the handling is over.
           This step is optional as the filter can be started without preloaded
           data.

       (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
           This function also configures the output buffer that will be filled from
           the circular internal output buffer. The function returns immediately
           without updating the provided buffer. The IP processing will be active until
           HAL_FMAC_FilterStop() is called.

       (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
           will be called to indicate that half of the input buffer has been handled.

       (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
           will be called to require new input data. It will be provided through
           HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.

       (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
           will be called to indicate that half of the output buffer has been handled.

       (#) If the output internal buffer is accessed via DMA or interrupt,
           HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
           buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
           if the DMA isn't in circular mode.

       (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
           This function should only be called once the previous input data has been handled
           (the preloaded input data isn't concerned).

       (#) In all modes except none, provide a new output buffer to be filled via
           HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
           user's output buffer has been filled.

       (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
           This function:
           (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
                into the FMAC input memory area.
           (++) Read the FMAC output memory area and write it into the user's output buffer.
           It will return either when:
           (++) the user's output buffer is filled.
           (++) the user's input buffer has been handled.
           The unused data (unread input data or free output data) will not be saved.
           The user will have to use the updated input and output sizes to keep track
           of them.

       (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().

       (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
           resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.

  ##### Callback registration #####
  ==================================

    [..]
      The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

    [..]
      Use Function HAL_FMAC_RegisterCallback() to register a user callback.
      Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
      (+) ErrorCallback               : Error Callback.
      (+) HalfGetDataCallback         : Get Half Data Callback.
      (+) GetDataCallback             : Get Data Callback.
      (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
      (+) OutputDataReadyCallback     : Output Data Ready Callback.
      (+) FilterConfigCallback        : Filter Configuration Callback.
      (+) FilterPreloadCallback       : Filter Preload Callback.
      (+) MspInitCallback             : FMAC MspInit.
      (+) MspDeInitCallback           : FMAC MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

    [..]
      Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
      weak function.
      HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
      and the Callback ID.
      This function allows to reset following callbacks:
      (+) ErrorCallback               : Error Callback.
      (+) HalfGetDataCallback         : Get Half Data Callback.
      (+) GetDataCallback             : Get Data Callback.
      (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
      (+) OutputDataReadyCallback     : Output Data Ready Callback.
      (+) FilterConfigCallback        : Filter Configuration Callback.
      (+) FilterPreloadCallback       : Filter Preload Callback.
      (+) MspInitCallback             : FMAC MspInit.
      (+) MspDeInitCallback           : FMAC MspDeInit.

    [..]
      By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
      all callbacks are set to the corresponding weak functions:
      examples GetDataCallback(), OutputDataReadyCallback().
      Exception done for MspInit and MspDeInit functions that are respectively
      reset to the legacy weak functions in the HAL_FMAC_Init()
      and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
      Callbacks can be registered/unregistered in HAL_FMAC_STATE_READY state only.
      Exception done MspInit/MspDeInit that can be registered/unregistered
      in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
      MspInit/DeInit callbacks can be used during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
      or HAL_FMAC_Init() function.

    [..]
      When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available
      and weak callbacks are used.

Definition in file stm32g4xx_hal_fmac.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_NUMBER (16U)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

    (+) The external interrupt/event controller consists of up to 44 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.

Definition in file stm32g4xx_hal_gpio.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SLAVE_ADDR_SHIFT 7U
#define | SLAVE_ADDR_MSK 0x06U
#define | I2C_STATE_MSK
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX
#define | I2C_STATE_MASTER_BUSY_RX
#define | I2C_STATE_SLAVE_BUSY_TX
#define | I2C_STATE_SLAVE_BUSY_RX
#define | I2C_STATE_MEM_BUSY_TX
#define | I2C_STATE_MEM_BUSY_RX
#define | I2C_XFER_TX_IT (uint16_t)(0x0001U)
#define | I2C_XFER_RX_IT (uint16_t)(0x0002U)
#define | I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)
#define | I2C_XFER_ERROR_IT (uint16_t)(0x0010U)
#define | I2C_XFER_CPLT_IT (uint16_t)(0x0020U)
#define | I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Mem_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Mem_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsErrorOccurred (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles errors detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_TreatErrorCallback (I2C_HandleTypeDef *hi2c)
I2C Error callback treatment.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (const I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (const I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (const I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for
                  the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode or DMA mode IO sequential operation ***
    ==========================================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
           no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
                            start condition, address and data to transfer without a final stop condition,
                            an then permit a call the same master sequential interface several times
                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to
                            transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to
                            transfer
                            if no direction change and with a final stop condition in both cases
      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
                            after several call of the same master sequential interface several times
                            (link with option I2C_FIRST_AND_NEXT_FRAME).
                            Usage can, transfer several bytes one by one using
                              HAL_I2C_Master_Seq_Transmit_IT
                              or HAL_I2C_Master_Seq_Receive_IT
                              or HAL_I2C_Master_Seq_Transmit_DMA
                              or HAL_I2C_Master_Seq_Receive_DMA
                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
                              Receive sequence permit to call the opposite interface Receive or Transmit
                              without stopping the communication and so generate a restart condition.
      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
                            each call of the same master sequential
                            interface.
                            Usage can, transfer several bytes one by one with a restart with slave address between
                            each bytes using
                              HAL_I2C_Master_Seq_Transmit_IT
                              or HAL_I2C_Master_Seq_Receive_IT
                              or HAL_I2C_Master_Seq_Transmit_DMA
                              or HAL_I2C_Master_Seq_Receive_DMA
                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
                            generation of STOP condition.

      (+) Different sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
            HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
           add their own code to check the Address Match Code and the transmission direction request by master
           (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
    [..]
     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
     weak function.
     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
    [..]
     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
     or HAL_I2C_Init() function.
    [..]
     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros

Definition in file stm32g4xx_hal_i2c.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32G4xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()

Definition in file stm32g4xx_hal_i2c_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2s.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | I2S_TIMEOUT_FLAG 100U

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream/Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                  DMA Tx/Rx Stream/Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
        (+@) SYSCLK is configured or
        (+@) PLLADCCLK output is configured or
        (+@) HSI is enabled or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32g4xx_hal_conf.h file.

    (#) Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
         In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
         HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
         In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
         inside DR register and avoid using DeInit/Init process for the next transfer.

   *** I2S HAL driver macros list ***
   ===================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
      (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros

   *** I2S HAL driver macros list ***
   ===================================
   [..]
       Callback registration:

      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.

          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
            (++) TxCpltCallback        : I2S Tx Completed callback
            (++) RxCpltCallback        : I2S Rx Completed callback
            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (++) ErrorCallback         : I2S Error callback
            (++) MspInitCallback       : I2S Msp Init callback
            (++) MspDeInitCallback     : I2S Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (++) TxCpltCallback        : I2S Tx Completed callback
            (++) RxCpltCallback        : I2S Rx Completed callback
            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (++) ErrorCallback         : I2S Error callback
            (++) MspInitCallback       : I2S Msp Init callback
            (++) MspDeInitCallback     : I2S Msp DeInit callback

       [..]
       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       [..]
       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
       or HAL_I2S_Init() function.

       [..]
       When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

Definition in file stm32g4xx_hal_i2s.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU
#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer
                  complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_IRDA_RegisterCallback() to register a user callback.
    Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.

    [..]
    By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
    all callbacks are set to the corresponding weak functions:
    examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak functions in the HAL_IRDA_Init()
    and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
    or HAL_IRDA_Init() function.

    [..]
    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak callbacks are used.

Definition in file stm32g4xx_hal_irda.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_iwdg.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define | IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
        active even if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded into the counter and the watchdog reset
        is prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode: When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI clock frequency dispersion.
         STM32G4xx devices provide the capability to measure the LSI clock
         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
         The measured value can be used to have an IWDG timeout with an
         acceptable accuracy.

    [..] Default timeout value (necessary for IWDG_SR status register update):
         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
         This frequency being subject to variations as mentioned above, the
         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
         below) may become too short or too long.
         In such cases, this default timeout value can be tuned by redefining
         the constant LSI_VALUE at user-application level (based, for instance,
         on the measured LSI clock frequency as explained above).

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts counting down.
      (++) Enable write access to configuration registers:
          IWDG_PR, IWDG_RLR and IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) Depending on window parameter:
        (+++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function with exact time base.
        (+++) Else modify Window register. This will automatically reload
             watchdog counter.
      (++) Wait for status flags to be reset.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register

Definition in file stm32g4xx_hal_iwdg.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_lptim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT 1000UL /* Timeout is 1s */

Functions

static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.
HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (const LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1.
         (++) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE or LSI).
             (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possible.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().

    *** Callback registration ***
  =============================================
  [..]
  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  [..]
  Use Function HAL_LPTIM_RegisterCallback() to register a callback.
  HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.
  [..]
  Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
  default weak function.
  HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  [..]
  These functions allow to register/unregister following callbacks:

    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
    (+) CompareMatchCallback    : Compare match Callback.
    (+) AutoReloadMatchCallback : Auto-reload match Callback.
    (+) TriggerCallback         : External trigger event detection Callback.
    (+) CompareWriteCallback    : Compare register write complete Callback.
    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
    (+) DirectionUpCallback     : Up-counting direction change Callback.
    (+) DirectionDownCallback   : Down-counting direction change Callback.

  [..]
  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
  all interrupt callbacks are set to the corresponding weak functions:
  examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init/DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.

  [..]
  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_lptim.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_opamp.c File Reference

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | OPAMP_CSR_RESET_VALUE (0x00000000UL)
#define | OPAMP_CSR_RESET_CHECK_MASK (~(OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP))
#define | OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK
#define | OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitializes the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the opamp.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the opamp.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp configuration.
HAL_StatusTypeDef | HAL_OPAMP_LockTimerMux (OPAMP_HandleTypeDef *hopamp)
Lock the selected opamp timer controlled mux configuration.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP state.
OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_StatusTypeDef | HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
Register a User OPAMP Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
Unregister a User OPAMP Callback OPAMP Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

================================================================================
          ##### OPAMP Peripheral Features #####
================================================================================

  [..] The device integrates up to 6 operational amplifiers OPAMP1, OPAMP2,
       OPAMP3, OPAMP4, OPAMP5 and OPAMP6:

       (#) The OPAMP(s) provides several exclusive running modes.
       (++) Standalone mode
       (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
       (++) Follower mode

       (#) The OPAMP(s) provide(s) calibration capabilities.
       (++) Calibration aims at correcting some offset for running mode.
       (++) The OPAMP uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
       (++) HAL_OPAMP_SelfCalibrate:
       (++) Runs automatically the calibration in 2 steps.
            (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
            appropriate and enough in most cases).
       (++) Enables the user trimming mode
       (++) Updates the init structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)
       (++) for STM32G4 devices having 6 OPAMPs
            HAL_OPAMPEx_SelfCalibrateAll
            runs calibration of 6 OPAMPs in parallel.

       (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
           mode can be set on top.
       (++) Timer-controlled Mux mode allows Automatic switching of inputs
           configuration (inverting and non inverting).
       (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
           the user shall select secondary inverting and non inverting inputs.
       (++) TIM1 OC6, TIM8 OC6 and TIM20 OC6 provides the alternate switching
           tempo between defaults (primary) and secondary inputs.
       (++) These 3 timers (TIM1, TIM8 and TIM20) can be combined to design a more
           complex switching scheme. So that any of the selected channel can initiate
           the configuration switch.

       (#) Running mode: Standalone mode
       (++) Gain is set externally (gain depends on external loads).
       (++) Follower mode also possible externally by connecting the inverting input to
           the output.

       (#) Running mode: Follower mode
       (++) Inverting Input is not connected.

       (#) Running mode: Programmable Gain Amplifier (PGA) mode
           (Resistor feedback output)
       (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
           output.
       (++) The OPAMP inverting input can be "not" connected, signal to amplify is
           connected to non inverting input and gain is positive (2,4,8,16,32 or 64)
       (++) The OPAMP inverting input can be connected to VINM0:
           If signal is applied to non inverting input, gain is positive (2,4,8,16,32 or 64).
           If signal is applied to inverting input, gain is negative (-1,-3,-7,-15-,31 or -63).
           In both cases, the other input can be used as bias.

            ##### How to use this driver #####
================================================================================
  [..]

    *** High speed / normal power mode ***
    ============================================
    [..]  To run in high speed mode:

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select OPAMP_POWERMODE_HIGHSPEED
      (++) Otherwise select OPAMP_POWERMODE_NORMALSPEED

    *** Calibration ***
    ============================================
    [..]  To run the OPAMP calibration self calibration:

      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
           Store the calibration results.

    *** Running mode ***
    ============================================
    [..]  To use the OPAMP, perform the following steps:

      (#) Fill in the HAL_OPAMP_MspInit() to
      (++) Configure the OPAMP input AND output in analog mode using
          HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.

      (#) Registrate Callbacks
      (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
           allows the user to configure dynamically the driver callbacks.

      (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
           it allows to register following callbacks:
      (+++) MspInitCallback         : OPAMP MspInit.
      (+++) MspDeInitCallback       : OPAMP MspDeInit.
           This function takes as parameters the HAL peripheral handle, the Callback ID
           and a pointer to the user callback function.

      (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
           weak (surcharged) function. It allows to reset following callbacks:
      (+++) MspInitCallback         : OPAMP MspInit.
      (+++) MspDeInitCallback       : OPAMP MspDeInit.
      (+++) All Callbacks

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select the mode
      (++) Select the inverting input
      (++) Select the non-inverting input
      (++) Select if the internal output should be enabled/disabled (if enabled, regular I/O output is disabled)
      (++) Select if the Timer controlled Mux is disabled or enabled and controlled by specified timer(s)
      (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
      (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
      (++) If PGA mode is enabled, Select if inverting input is connected.
      (++) If PGA mode is enabled, Select PGA gain to be used.
      (++) Select either factory or user defined trimming mode.
      (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
          (typ. settings returned by HAL_OPAMP_SelfCalibrate function).

      (#) Enable the OPAMP using HAL_OPAMP_Start() function.

      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.

      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() & HAL_OPAMP_TimerMuxLock functions.
          From then the configuration can only be modified
      (++) After HW reset
      (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.

    *** Running mode: change of configuration while OPAMP ON  ***
    ============================================
    [..]    To Re-configure OPAMP when OPAMP is ON (change on the fly)
      (#) If needed, fill in the HAL_OPAMP_MspInit()
      (++) This is the case for instance if you wish to use new OPAMP I/O

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) As in configure case, selects first the parameters you wish to modify.
      (++) If OPAMP control register is locked, it is not possible to modify any values
          on the fly (even the timer controlled mux parameters).
      (++) If OPAMP timer controlled mux mode register is locked, it is possible to modify any values
          of the control register but none on the timer controlled mux mode one.

      (#) Change from high speed mode to normal power mode (& vice versa) requires
          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
          alone.

Definition in file stm32g4xx_hal_opamp.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
static HAL_StatusTypeDef | HAL_PCD_EP_DB_Transmit (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk IN transaction from ISR.
static uint16_t | HAL_PCD_EP_DB_Receive (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk out transaction from ISR.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef const *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();

Definition in file stm32g4xx_hal_pcd.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_pcd_ex.c File Reference

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pcd_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pwr.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
#define | PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */
#define | PVM_MODE_IT 0x00010000U
#define | PVM_MODE_EVT 0x00020000U
#define | PVM_RISING_EDGE 0x00000001U
#define | PVM_FALLING_EDGE 0x00000002U
#define | PWR_FLAG_SETTING_DELAY_US 50UL

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.
void | HAL_PWREx_EnableUCPDStandbyMode (void)
Enable UCPD configuration memorization in Standby.
void | HAL_PWREx_DisableUCPDStandbyMode (void)
Disable UCPD configuration memorization in Standby.
void | HAL_PWREx_EnableUCPDDeadBattery (void)
Enable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.
void | HAL_PWREx_DisableUCPDDeadBattery (void)
Disable the USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_pwr_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
#define | RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
#define | RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
#define | RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
#define | RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))

Functions

static uint32_t | RCC_GetSysClockFreqFromPLLSource (void)
Compute SYSCLK frequency based on PLL SYSCLK source.
HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8/PG10).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from High Speed Internal oscillator
      (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analog mode, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs,
          UCPD, I2S, I2C, LPTIM, ADC, QSPI)
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rcc.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U
#define | __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_rcc_ex.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rng.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (const RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (const RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (const RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_RNG_RegisterCallback() to register a user callback.
    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
    weak (overridden) function.
    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.

    [..]
    For specific callback ReadyDataCallback, use dedicated register callbacks:
    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().

    [..]
    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
    all callbacks are set to the corresponding weak (overridden) functions:
    example HAL_RNG_ErrorCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
    or HAL_RNG_Init() function.

    [..]
    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (overridden) callbacks are used.

Definition in file stm32g4xx_hal_rng.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.
    (#) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
  ==================================================================
  [..] After reset, the backup domain (RTC registers and RTC backup data registers)
       is protected against possible unwanted write accesses.
  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Enable the Power Controller (PWR) APB1 interface clock using the
        __HAL_RCC_PWR_CLK_ENABLE() function.
    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.

  *** Callback registration ***
  =============================================
  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions. This is the recommended configuration
  in order to optimize memory/code consumption footprint/performances.

  [..]
  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.

  [..]
  Function HAL_RTC_RegisterCallback() allows to register following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) Tamper4EventCallback         : RTC Tamper 4 Event callback.
    (+) Tamper5EventCallback         : RTC Tamper 5 Event callback.
    (+) Tamper6EventCallback         : RTC Tamper 6 Event callback.
    (+) Tamper7EventCallback         : RTC Tamper 7 Event callback.
    (+) Tamper8EventCallback         : RTC Tamper 8 Event callback.
    (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback.
    (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback.
    (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback.
    (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback.
    (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback.
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
    (+) AlarmAEventCallback_S          : RTC Alarm A Event callback_S
    (+) AlarmBEventCallback_S          : RTC Alarm B Event callback_S.
    (+) TimeStampEventCallback_S       : RTC TimeStampEvent callback_S.
    (+) WakeUpTimerEventCallback_S     : RTC WakeUpTimerEvent callback_S.
    (+) Tamper1EventCallback_S         : RTC Tamper 1 Event callback_S.
    (+) Tamper2EventCallback_S         : RTC Tamper 2 Event callback_S.
    (+) Tamper3EventCallback_S         : RTC Tamper 3 Event callback_S.
    (+) Tamper4EventCallback_S         : RTC Tamper 4 Event callback_S.
    (+) Tamper5EventCallback_S         : RTC Tamper 5 Event callback_S.
    (+) Tamper6EventCallback_S         : RTC Tamper 6 Event callback_S.
    (+) Tamper7EventCallback_S         : RTC Tamper 7 Event callback_S.
    (+) Tamper8EventCallback_S         : RTC Tamper 8 Event callback_S.
    (+) InternalTamper1EventCallback_S : RTC InternalTamper 1 Event callback_S.
    (+) InternalTamper2EventCallback_S : RTC InternalTamper 2 Event callback_S.
    (+) InternalTamper3EventCallback_S : RTC InternalTamper 3 Event callback_S.
    (+) InternalTamper5EventCallback_S : RTC InternalTamper 5 Event callback_S.
    (+) InternalTamper8EventCallback_S : RTC InternalTamper 8 Event callback_S.
#endif
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.
  [..]
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) Tamper4EventCallback         : RTC Tamper 4 Event callback.
    (+) Tamper5EventCallback         : RTC Tamper 5 Event callback.
    (+) Tamper6EventCallback         : RTC Tamper 6 Event callback.
    (+) Tamper7EventCallback         : RTC Tamper 7 Event callback.
    (+) Tamper8EventCallback         : RTC Tamper 8 Event callback.
    (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Event callback.
    (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Event callback.
    (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback.
    (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback.
    (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback.
    (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback.
    (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Event callback.
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
    (+) AlarmAEventCallback_S          : RTC Alarm A Event callback secure.
    (+) AlarmBEventCallback_S          : RTC Alarm B Event callback secure.
    (+) TimeStampEventCallback_S       : RTC TimeStamp Event callback secure.
    (+) WakeUpTimerEventCallback_S     : RTC WakeUpTimer Event callback secure.
    (+) Tamper1EventCallback_S         : RTC Tamper 1 Event callback secure.
    (+) Tamper2EventCallback_S         : RTC Tamper 2 Event callback secure.
    (+) Tamper3EventCallback_S         : RTC Tamper 3 Event callback secure.
    (+) Tamper4EventCallback_S         : RTC Tamper 4 Event callback secure.
    (+) Tamper5EventCallback_S         : RTC Tamper 5 Event callback secure.
    (+) Tamper6EventCallback_S         : RTC Tamper 6 Event callback secure.
    (+) Tamper7EventCallback_S         : RTC Tamper 7 Event callback secure.
    (+) Tamper8EventCallback_S         : RTC Tamper 8 Event callback secure.
    (+) InternalTamper1EventCallback_S : RTC Internal Tamper 1 Event callback secure.
    (+) InternalTamper2EventCallback_S : RTC Internal Tamper 2 Event callback secure.
    (+) InternalTamper3EventCallback_S : RTC Internal Tamper 3 Event callback secure.
    (+) InternalTamper4EventCallback_S : RTC Internal Tamper 4 Event callback secure.
    (+) InternalTamper5EventCallback_S : RTC Internal Tamper 5 Event callback secure.
    (+) InternalTamper6EventCallback_S : RTC Internal Tamper 6 Event callback secure.
    (+) InternalTamper8EventCallback_S : RTC Internal Tamper 8 Event callback secure.
#endif
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.

  [..]
  By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
  all callbacks are set to the corresponding weak functions :
  examples AlarmAEventCallback(), TimeStampEventCallback().
  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
  in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
  (not registered beforehand).
  If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
  or HAL_RTC_Init() function.

  [..]
  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_rtc.c.

Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified TAMP Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified TAMP Backup data Register.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

   *** Tamper configuration ***
   ============================
   [..]
     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
         or Level according to the Tamper filter (if equal to 0 Edge else Level)
         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
     (+) The default configuration of the Tamper erases the backup registers. To avoid
         erase, enable the NoErase field on the RTC_TAMPCR register.
     (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization
         by setting ClockEnable init field to RTC_CLOCK_DISABLE.
     (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
         setting Interrupt field.

   *** Backup Data Registers configuration ***
   ===========================================
   [..]
     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
         function.
     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
         function.

Definition in file stm32g4xx_hal_rtc_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Enumerations | Functions
stm32g4xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U
#define | SAI_SPDIF_FRAME_LENGTH 64U
#define | SAI_AC97_FRAME_LENGTH 256U

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (const SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (const SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

    (#) The initialization can be done by two ways
        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().

  [..]
    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
        inside the transmit and receive process.
  [..]
    (@) Make sure that SAI clock source is configured:
        (+@) SYSCLK or
        (+@) PLLQ output or
        (+@) HSI or
        (+@) External clock source which is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32g4xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@) First bit Offset <= (SLOT size - Data size)
        (+@) Data size <= SLOT size
        (+@) Number of SLOT x SLOT size = Frame length
        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
    (@) PDM interface can be activated through HAL_SAI_Init function.
        Please note that PDM interface is only available for SAI1 sub-block A.
        PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

    *** SAI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SAI HAL driver :

      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
      (+) HAL_SAI_Abort(): Abort the current transfer

    *** SAI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SAI HAL driver :

      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not

    *** Callback registration ***
    =============================
    [..]
    The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.
    Use functions HAL_SAI_RegisterCallback() to register a user callback.

    [..]
    Function HAL_SAI_RegisterCallback() allows to register following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.

    [..]
    By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
    all callbacks are reset to the corresponding legacy weak functions:
    examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak functions in the HAL_SAI_Init
    and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
    or HAL_SAI_Init function.

    [..]
    When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak callbacks are used.

Definition in file stm32g4xx_hal_sai.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_sai_ex.c File Reference

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (const SAI_HandleTypeDef *hsai, const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_sai_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete
                   interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
    Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.

    [..]
    By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
    all callbacks are set to the corresponding weak functions:
    examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak functions in the HAL_SMARTCARD_Init()
    and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
    or HAL_SMARTCARD_Init() function.

    [..]
    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak callbacks are used.

Definition in file stm32g4xx_hal_smartcard.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.
void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

Definition in file stm32g4xx_hal_smartcard_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static void | SMBUS_Flush_TXDR (SMBUS_HandleTypeDef *hsmbus)
SMBUS Tx data register flush process.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (const SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
        (##) Enable the SMBUSx interface clock
        (##) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
           add their own code to check the Address Match Code and the transmission direction
           request by master/host (Write/Read).
      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using
          HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Error Code using function HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
    [..]
     Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
     weak function.
     HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
    [..]
     By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
     or HAL_SMBUS_Init() function.
    [..]
     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros

Definition in file stm32g4xx_hal_smbus.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_smbus_ex.c File Reference

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).
void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### SMBUS peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the SMBUS interface for STM32G4xx
       devices contains the following additional features

       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
          (++) HAL_SMBUSEx_EnableWakeUp()
          (++) HAL_SMBUSEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_SMBUSEx_EnableFastModePlus()
          (++) HAL_SMBUSEx_DisableFastModePlus()

Definition in file stm32g4xx_hal_smbus_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()
     [..]
       Callback registration:

      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.

          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback

       [..]
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       [..]
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
       or HAL_SPI_Init() function.

       [..]
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

     [..]
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.

Additional table :

DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

Note:
The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()

Definition in file stm32g4xx_hal_spi.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_FIFO_SIZE 4UL

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (const SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_hal_spi_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output
       (#) Synchronization circuit to control the timer with external signals and to interconnect
            several timers together.
       (#) Supports incremental encoder for positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
            to use the Timer to generate an Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
            in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()

    *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.

  [..]
  Use Function HAL_TIM_RegisterCallback() to register a callback.
  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.

  [..]
  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.

  [..]
  These functions allow to register/unregister following callbacks:
    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
    (+) TriggerCallback                   : TIM Trigger Callback.
    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
    (+) IC_CaptureCallback                : TIM Input Capture Callback.
    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
    (+) ErrorCallback                     : TIM Error Callback.
    (+) CommutationCallback               : TIM Commutation Callback.
    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
    (+) BreakCallback                     : TIM Break Callback.
    (+) Break2Callback                    : TIM Break2 Callback.
    (+) EncoderIndexCallback              : TIM Encoder Index Callback.
    (+) DirectionChangeCallback           : TIM Direction Change Callback
    (+) IndexErrorCallback                : TIM Index Error Callback.
    (+) TransitionErrorCallback           : TIM Transition Error Callback

  [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init / DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)

  [..]
    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
    Exception done MspInit / MspDeInit that can be registered / unregistered
    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.

  [..]
      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.

Definition in file stm32g4xx_hal_tim.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration + Timer encoder index configuration. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Functions

static void | TIM_DMADelayPulseNCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback (complementary channel).
static void | TIM_DMAErrorCCxN (DMA_HandleTypeDef *hdma)
TIM DMA error callback (complementary channel)
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (const TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_DitheringEnable (TIM_HandleTypeDef *htim)
Enable dithering.
HAL_StatusTypeDef | HAL_TIMEx_DitheringDisable (TIM_HandleTypeDef *htim)
Disable dithering.
HAL_StatusTypeDef | HAL_TIMEx_OC_ConfigPulseOnCompare (TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth)
Initializes the pulse on compare pulse width and pulse prescaler.
HAL_StatusTypeDef | HAL_TIMEx_ConfigSlaveModePreload (TIM_HandleTypeDef *htim, uint32_t Source)
Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableSlaveModePreload (TIM_HandleTypeDef *htim)
Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_DisableSlaveModePreload (TIM_HandleTypeDef *htim)
Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
HAL_StatusTypeDef | HAL_TIMEx_EnableDeadTimePreload (TIM_HandleTypeDef *htim)
Enable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_DisableDeadTimePreload (TIM_HandleTypeDef *htim)
Disable deadtime preload.
HAL_StatusTypeDef | HAL_TIMEx_ConfigDeadTime (TIM_HandleTypeDef *htim, uint32_t Deadtime)
Configure deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigAsymmetricalDeadTime (TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
Configure asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_EnableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Enable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_DisableAsymmetricalDeadTime (TIM_HandleTypeDef *htim)
Disable asymmetrical deadtime.
HAL_StatusTypeDef | HAL_TIMEx_ConfigEncoderIndex (TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
Configures the encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderIndex (TIM_HandleTypeDef *htim)
Enable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderIndex (TIM_HandleTypeDef *htim)
Disable encoder index.
HAL_StatusTypeDef | HAL_TIMEx_EnableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Enable encoder first index.
HAL_StatusTypeDef | HAL_TIMEx_DisableEncoderFirstIndex (TIM_HandleTypeDef *htim)
Disable encoder first index.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Commutation callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Commutation half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Break2 detection callback in non blocking mode.
__weak void | HAL_TIMEx_EncoderIndexCallback (TIM_HandleTypeDef *htim)
Encoder index callback in non-blocking mode.
__weak void | HAL_TIMEx_DirectionChangeCallback (TIM_HandleTypeDef *htim)
Direction change callback in non-blocking mode.
__weak void | HAL_TIMEx_IndexErrorCallback (TIM_HandleTypeDef *htim)
Index error callback in non-blocking mode.
__weak void | HAL_TIMEx_TransitionErrorCallback (TIM_HandleTypeDef *htim)
Transition error callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration + Timer encoder index configuration.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes
    (#) In case of Pulse on compare, configure pulse length and delay
    (#) Encoder index configuration

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
               Timer Hall Sensor Interface and the commutation event with the corresponding
               Interrupt and DMA request if needed (Note that One Timer is used to interface
               with the Hall sensor Interface and another Timer should be used to use
               the commutation event).
     (#) In case of Pulse On Compare:
           (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
                HAL_TIMEx_OCN_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
                HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
                HAL_TIMEx_HallSensor_Start_IT().

Definition in file stm32g4xx_hal_tim_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions | Variables
stm32g4xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Functions

static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Variables

const uint16_t | UARTPrescTable [12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
                inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_UART_RegisterCallback() to register a user callback.
    Function HAL_UART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.

    [..]
    For specific callback RxEventCallback, use dedicated registration/reset functions:
    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().

    [..]
    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
    all callbacks are set to the corresponding weak functions:
    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak functions in the HAL_UART_Init()
    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
    or HAL_UART_Init() function.

    [..]
    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak callbacks are used.

Definition in file stm32g4xx_hal_uart.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (const UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

Definition in file stm32g4xx_hal_uart_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used to override the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer
                  complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
          (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_USART_RegisterCallback() to register a user callback.
    Function HAL_USART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
    weak function.
    HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.

    [..]
    By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
    all callbacks are set to the corresponding weak functions:
    examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak functions in the HAL_USART_Init()
    and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
    or HAL_USART_Init() function.

    [..]
    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak callbacks are used.

Definition in file stm32g4xx_hal_usart.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Defines | Functions
stm32g4xx_hal_usart_ex.c File Reference

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.
__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### USART peripheral extended features  #####
  ==============================================================================

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

    (#) Slave mode enabling/disabling and NSS pin configuration.

        -@- When USART operates in Slave mode, Slave mode must be enabled prior
            starting RX/TX transfers.

Definition in file stm32g4xx_hal_usart_ex.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions. More...

#include "stm32g4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### WWDG Specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls down from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) If required by application, an Early Wakeup Interrupt can be triggered
        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
        (EWI) can be used if specific safety operations or data logging must
        be performed before the actual reset is generated. When the downcounter
        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
        disabled except by a system reset.
    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
        where T[5;0] are the lowest 6 bits of Counter.
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
    (+) Typical values:
        (++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler:
             max timeout before reset: approximately 24.09us
        (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler
             dividing by 128:
             max timeout before reset: approximately 197.38ms

                     ##### How to use this driver #####
  ==============================================================================

    *** Common driver usage ***
    ===========================

  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Configure the WWDG prescaler, refresh window value, counter value and early
        interrupt status using HAL_WWDG_Init() function. This will automatically
        enable WWDG and start its downcounter. Time reference can be taken from
        function exit. Care must be taken to provide a counter value
        greater than 0x40 to prevent generation of immediate reset.
    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
        triggered by the interrupt service routine, flag will be automatically
        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

    *** Callback registration ***
    =============================

  [..]
    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
    the user to configure dynamically the driver callbacks. Use Functions
    HAL_WWDG_RegisterCallback() to register a user callback.

    (+) Function HAL_WWDG_RegisterCallback() allows to register following
        callbacks:
        (++) EwiCallback : callback for Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
    takes as parameters the HAL peripheral handle and the Callback ID.
    This function allows to reset following callbacks:
        (++) EwiCallback : callback for  Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.

    [..]
    When calling HAL_WWDG_Init function, callbacks are reset to the
    corresponding legacy weak (surcharged) functions:
    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
    not been registered before.

    [..]
    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.

    *** WWDG HAL driver macros list ***
    ===================================
    [..]
      Below the list of available macros in WWDG HAL driver.
      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt

Definition in file stm32g4xx_hal_wwdg.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crs.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_ll_crs.c File Reference
#include "stm32g4xx_ll_crs.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.
Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_pwr.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Functions
stm32g4xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32g4xx_ll_pwr.h"
#include "stm32g4xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g4xx_ll_pwr.c.

Generated on Wed Dec 6 2023 15:11:30 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__ADC_HandleTypeDef | ADC handle Structure definition
__COMP_HandleTypeDef | COMP Handle Structure definition
__CORDIC_HandleTypeDef | CORDIC Handle Structure definition
__DAC_HandleTypeDef | DAC handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__FDCAN_HandleTypeDef | FDCAN handle structure definition
__FMAC_HandleTypeDef | FMAC Handle Structure definition
__I2C_HandleTypeDef |
__I2S_HandleTypeDef | I2S handle Structure definition
__IRDA_HandleTypeDef | IRDA handle Structure definition
__LPTIM_HandleTypeDef | LPTIM handle Structure definition
__OPAMP_HandleTypeDef | OPAMP Handle Structure definition
__PCD_HandleTypeDef | PCD Handle Structure definition
__RNG_HandleTypeDef |
__RTC_HandleTypeDef | RTC Handle Structure definition
__SAI_HandleTypeDef |
__SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
__SMBUS_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
__TIM_HandleTypeDef | TIM Time Base Handle Structure definition
__UART_HandleTypeDef | UART handle Structure definition
__USART_HandleTypeDef | USART handle Structure definition
__WWDG_HandleTypeDef | WWDG handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_InitTypeDef | Structure definition of ADC instance and ADC group regular
ADC_InjectionConfigTypeDef | ADC group injected contexts queue configuration
ADC_InjectionConfTypeDef | Structure definition of ADC group injected and ADC channel affected to ADC group injected
ADC_InjOversamplingTypeDef | ADC Injected Conversion Oversampling structure definition
ADC_MultiModeTypeDef | Structure definition of ADC multimode
ADC_OversamplingTypeDef | ADC group regular oversampling structure definition
COMP_InitTypeDef | COMP Init structure definition
CORDIC_ConfigTypeDef | CORDIC Config Structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_SampleAndHoldConfTypeDef | DAC Configuration sample and hold Channel structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
EXTI_ConfigTypeDef | EXTI Configuration structure definition
EXTI_HandleTypeDef | EXTI Handle structure definition
FDCAN_ErrorCountersTypeDef | FDCAN Error Counters structure definition
FDCAN_FilterTypeDef | FDCAN filter structure definition
FDCAN_HpMsgStatusTypeDef | FDCAN High Priority Message Status structure definition
FDCAN_InitTypeDef | FDCAN Init structure definition
FDCAN_MsgRamAddressTypeDef | FDCAN Message RAM blocks
FDCAN_ProtocolStatusTypeDef | FDCAN Protocol Status structure definition
FDCAN_RxHeaderTypeDef | FDCAN Rx header structure definition
FDCAN_TxEventFifoTypeDef | FDCAN Tx event FIFO structure definition
FDCAN_TxHeaderTypeDef | FDCAN Tx header structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
FMAC_FilterConfigTypeDef | FMAC Filter Configuration Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_DMA_MuxRequestGeneratorConfigTypeDef | HAL DMAMUX request generator parameters structure definition
HAL_DMA_MuxSyncConfigTypeDef | HAL DMA Synchro definition
I2C_InitTypeDef |
I2S_InitTypeDef | I2S Init structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DAC_InitTypeDef | Structure definition of some features of DAC instance
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_I2S_InitTypeDef | I2S Init structure definition
LL_LPTIM_InitTypeDef | LPTIM Init structure definition
LL_LPUART_InitTypeDef | LL LPUART Init Structure definition
LL_OPAMP_InitTypeDef | Structure definition of some features of OPAMP instance
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RNG_InitTypeDef | LL RNG Init Structure Definition
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_UCPD_InitTypeDef | UCPD Init structures definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
OPAMP_InitTypeDef | OPAMP Init structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWR_PVMTypeDef | PWR PVM configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_CRSInitTypeDef | RCC_CRS Init structure definition
RCC_CRSSynchroInfoTypeDef | RCC_CRS Synchronization structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RNG_InitTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_InternalTamperTypeDef |
RTC_TamperTypeDef |
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef |
SAI_InitTypeDef |
SAI_PdmInitTypeDef |
SAI_SlotInitTypeDef |
SAIEx_PdmMicDelayParamTypeDef | PDM microphone delay structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initialization structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_InitTypeDef |
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
TIMEx_EncoderIndexConfigTypeDef | TIM Encoder index configuration
UART_AdvFeatureInitTypeDef | UART Advanced Features initialization structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_InitTypeDef | USART Init Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | E | F | G | H | I | L | M | O | P | R | S | T | U | W | _
A
FLASH_EraseInitTypeDef LL_RTC_AlarmTypeDef RCC_PeriphCLKInitTypeDef UART_InitTypeDef
FLASH_OBProgramInitTypeDef LL_RTC_DateTypeDef RCC_PLLInitTypeDef UART_WakeUpTypeDef
ADC_AnalogWDGConfTypeDef FLASH_ProcessTypeDef LL_RTC_InitTypeDef RNG_InitTypeDef USART_InitTypeDef
ADC_ChannelConfTypeDef FMAC_FilterConfigTypeDef LL_RTC_TimeTypeDef RTC_AlarmTypeDef
W
ADC_InitTypeDef
G
LL_SPI_InitTypeDef RTC_DateTypeDef
ADC_InjectionConfigTypeDef LL_TIM_BDTR_InitTypeDef RTC_InitTypeDef WWDG_InitTypeDef
ADC_InjectionConfTypeDef GPIO_InitTypeDef LL_TIM_ENCODER_InitTypeDef RTC_InternalTamperTypeDef
_
ADC_InjOversamplingTypeDef
H
LL_TIM_HALLSENSOR_InitTypeDef RTC_TamperTypeDef
ADC_MultiModeTypeDef LL_TIM_IC_InitTypeDef RTC_TimeTypeDef __ADC_HandleTypeDef
ADC_OversamplingTypeDef HAL_DMA_MuxRequestGeneratorConfigTypeDef LL_TIM_InitTypeDef
S
__COMP_HandleTypeDef
C
HAL_DMA_MuxSyncConfigTypeDef LL_TIM_OC_InitTypeDef __CORDIC_HandleTypeDef
I
LL_UCPD_InitTypeDef SAI_FrameInitTypeDef __DAC_HandleTypeDef
COMP_InitTypeDef LL_USART_ClockInitTypeDef SAI_InitTypeDef __DMA_HandleTypeDef
CORDIC_ConfigTypeDef I2C_InitTypeDef LL_USART_InitTypeDef SAI_PdmInitTypeDef __FDCAN_HandleTypeDef
CRC_HandleTypeDef I2S_InitTypeDef LL_UTILS_ClkInitTypeDef SAI_SlotInitTypeDef __FMAC_HandleTypeDef
CRC_InitTypeDef IRDA_InitTypeDef LL_UTILS_PLLInitTypeDef SAIEx_PdmMicDelayParamTypeDef __I2C_HandleTypeDef
D
IWDG_HandleTypeDef LPTIM_ClockConfigTypeDef SMARTCARD_AdvFeatureInitTypeDef __I2S_HandleTypeDef
IWDG_InitTypeDef LPTIM_InitTypeDef SMARTCARD_InitTypeDef __IRDA_HandleTypeDef
DAC_ChannelConfTypeDef
L
LPTIM_TriggerConfigTypeDef SMBUS_InitTypeDef __LPTIM_HandleTypeDef
DAC_SampleAndHoldConfTypeDef LPTIM_ULPClockConfigTypeDef SPI_InitTypeDef __OPAMP_HandleTypeDef
DMA_InitTypeDef LL_ADC_CommonInitTypeDef
M
T
__PCD_HandleTypeDef
E
LL_ADC_InitTypeDef __RNG_HandleTypeDef
LL_ADC_INJ_InitTypeDef MPU_Region_InitTypeDef TIM_Base_InitTypeDef __RTC_HandleTypeDef
EXTI_ConfigTypeDef LL_ADC_REG_InitTypeDef
O
TIM_BreakDeadTimeConfigTypeDef __SAI_HandleTypeDef
EXTI_HandleTypeDef LL_COMP_InitTypeDef TIM_ClearInputConfigTypeDef __SMARTCARD_HandleTypeDef
F
LL_DAC_InitTypeDef OPAMP_InitTypeDef TIM_ClockConfigTypeDef __SMBUS_HandleTypeDef
LL_DMA_InitTypeDef
P
TIM_Encoder_InitTypeDef __SPI_HandleTypeDef
FDCAN_ErrorCountersTypeDef LL_EXTI_InitTypeDef TIM_HallSensor_InitTypeDef __TIM_HandleTypeDef
FDCAN_FilterTypeDef LL_GPIO_InitTypeDef PWR_PVDTypeDef TIM_IC_InitTypeDef __UART_HandleTypeDef
FDCAN_HpMsgStatusTypeDef LL_I2C_InitTypeDef PWR_PVMTypeDef TIM_MasterConfigTypeDef __USART_HandleTypeDef
FDCAN_InitTypeDef LL_I2S_InitTypeDef
R
TIM_OC_InitTypeDef __WWDG_HandleTypeDef
FDCAN_MsgRamAddressTypeDef LL_LPTIM_InitTypeDef TIM_OnePulse_InitTypeDef
FDCAN_ProtocolStatusTypeDef LL_LPUART_InitTypeDef RCC_ClkInitTypeDef TIM_SlaveConfigTypeDef
FDCAN_RxHeaderTypeDef LL_OPAMP_InitTypeDef RCC_CRSInitTypeDef TIMEx_BreakInputConfigTypeDef
FDCAN_TxEventFifoTypeDef LL_RCC_ClocksTypeDef RCC_CRSSynchroInfoTypeDef TIMEx_EncoderIndexConfigTypeDef
FDCAN_TxHeaderTypeDef LL_RNG_InitTypeDef RCC_OscInitTypeDef
U
UART_AdvFeatureInitTypeDef
A | C | D | E | F | G | H | I | L | M | O | P | R | S | T | U | W | _
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: C:/git/g4_release_v1.5.2/Firmware/ Directory Reference

  • Firmware
Firmware Directory Reference

Directories

directory Drivers
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: C:/git/g4_release_v1.5.2/Firmware/Drivers/STM32G4xx_HAL_Driver/Inc/ Directory Reference

  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32g4xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32g4xx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32g4xx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32g4xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32g4xx_hal_cordic.h [code]

This file contains all the functions prototypes for the CORDIC firmware library.

file | stm32g4xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32g4xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32g4xx_hal_crc_ex.h [code]

Header file of CRC HAL extended module.

file | stm32g4xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32g4xx_hal_cryp_ex.h [code]

Header file of CRYPEx HAL module.

file | stm32g4xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32g4xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32g4xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32g4xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32g4xx_hal_exti.h [code]

Header file of EXTI HAL module.

file | stm32g4xx_hal_fdcan.h [code]

Header file of FDCAN HAL module.

file | stm32g4xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32g4xx_hal_flash_ex.h [code]

Header file of FLASH HAL Extended module.

file | stm32g4xx_hal_flash_ramfunc.h [code]

Header file of FLASH RAMFUNC driver.

file | stm32g4xx_hal_fmac.h [code]

Header for stm32g4xx_hal_fmac.c module.

file | stm32g4xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32g4xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extended module.

file | stm32g4xx_hal_hrtim.h [code]

Header file of HRTIM HAL module.

file | stm32g4xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32g4xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32g4xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32g4xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32g4xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32g4xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32g4xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32g4xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32g4xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32g4xx_hal_opamp.h [code]

Header file of OPAMP HAL module.

file | stm32g4xx_hal_opamp_ex.h [code]

Header file of OPAMP HAL Extended module.

file | stm32g4xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32g4xx_hal_pcd_ex.h [code]

Header file of PCD HAL Extension module.

file | stm32g4xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32g4xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extended module.

file | stm32g4xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32g4xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32g4xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extended module.

file | stm32g4xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32g4xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32g4xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extended module.

file | stm32g4xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32g4xx_hal_sai_ex.h [code]

Header file of SAI HAL extended module.

file | stm32g4xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32g4xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32g4xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32g4xx_hal_smbus_ex.h [code]

Header file of SMBUS HAL Extended module.

file | stm32g4xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32g4xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32g4xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32g4xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32g4xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32g4xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32g4xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32g4xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32g4xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32g4xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32g4xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32g4xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32g4xx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32g4xx_ll_cordic.h [code]

Header file of CORDIC LL module.

file | stm32g4xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32g4xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32g4xx_ll_crs.h [code]

CRS LL module driver.

file | stm32g4xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32g4xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32g4xx_ll_dmamux.h [code]

Header file of DMAMUX LL module.

file | stm32g4xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32g4xx_ll_fmac.h [code]

Header file of FMAC LL module.

file | stm32g4xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32g4xx_ll_hrtim.h [code]

Header file of HRTIM LL module.

file | stm32g4xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32g4xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32g4xx_ll_lptim.h [code]

Header file of LPTIM LL module.

file | stm32g4xx_ll_lpuart.h [code]

Header file of LPUART LL module.

file | stm32g4xx_ll_opamp.h [code]

Header file of OPAMP LL module.

file | stm32g4xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32g4xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32g4xx_ll_rng.h [code]

Header file of RNG LL module.

file | stm32g4xx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32g4xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32g4xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32g4xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32g4xx_ll_ucpd.h [code]

Header file of UCPD LL module.

file | stm32g4xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32g4xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32g4xx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: C:/git/g4_release_v1.5.2/Firmware/Drivers/STM32G4xx_HAL_Driver/Src/ Directory Reference

  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32g4xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32g4xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g4xx_hal_adc_ex.c".

file | stm32g4xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g4xx_hal_adc.c".

file | stm32g4xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions.

file | stm32g4xx_hal_cordic.c [code]

CORDIC HAL module driver. This file provides firmware functions to manage the following functionalities of the CORDIC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State functions.

file | stm32g4xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

file | stm32g4xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32g4xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32g4xx_hal_cryp_ex.c [code]

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

file | stm32g4xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32g4xx_hal_dac_ex.c [code]

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

file | stm32g4xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32g4xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32g4xx_hal_exti.c [code]

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the Extended Interrupts and events controller (EXTI) peripheral: functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32g4xx_hal_fdcan.c [code]

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

file | stm32g4xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32g4xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

file | stm32g4xx_hal_flash_ramfunc.c [code]

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH Power Down in Run mode + FLASH DBANK User Option Byte.

file | stm32g4xx_hal_fmac.c [code]

FMAC HAL module driver. This file provides firmware functions to manage the following functionalities of the FMAC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State and Error functions.

file | stm32g4xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32g4xx_hal_hrtim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get.

file | stm32g4xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g4xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions.

file | stm32g4xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g4xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32g4xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32g4xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32g4xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32g4xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32g4xx_hal_opamp.c [code]

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_opamp_ex.c [code]

Extended OPAMP HAL module driver.

file | stm32g4xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_pcd_ex.c [code]

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32g4xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

file | stm32g4xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32g4xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32g4xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g4xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

file | stm32g4xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32g4xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32g4xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_sai_ex.c [code]

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

file | stm32g4xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32g4xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g4xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g4xx_hal_smbus_ex.c [code]

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions.

file | stm32g4xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g4xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

file | stm32g4xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32g4xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

file | stm32g4xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration + Timer encoder index configuration.

file | stm32g4xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32g4xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g4xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32g4xx_hal_usart_ex.c [code]

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

file | stm32g4xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

file | stm32g4xx_ll_adc.c [code]

ADC LL module driver.

file | stm32g4xx_ll_comp.c [code]

COMP LL module driver.

file | stm32g4xx_ll_cordic.c [code]

CORDIC LL module driver.

file | stm32g4xx_ll_crc.c [code]

CRC LL module driver.

file | stm32g4xx_ll_crs.c [code]
file | stm32g4xx_ll_dac.c [code]

DAC LL module driver.

file | stm32g4xx_ll_dma.c [code]

DMA LL module driver.

file | stm32g4xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32g4xx_ll_fmac.c [code]

Header for stm32g4xx_ll_fmac.c module.

file | stm32g4xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32g4xx_ll_hrtim.c [code]

HRTIM LL module driver.

file | stm32g4xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32g4xx_ll_lptim.c [code]

LPTIM LL module driver.

file | stm32g4xx_ll_lpuart.c [code]

LPUART LL module driver.

file | stm32g4xx_ll_opamp.c [code]

OPAMP LL module driver.

file | stm32g4xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32g4xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32g4xx_ll_rng.c [code]

RNG LL module driver.

file | stm32g4xx_ll_rtc.c [code]

RTC LL module driver.

file | stm32g4xx_ll_spi.c [code]

SPI LL module driver.

file | stm32g4xx_ll_tim.c [code]

TIM LL module driver.

file | stm32g4xx_ll_ucpd.c [code]

UCPD LL module driver.

file | stm32g4xx_ll_usart.c [code]

USART LL module driver.

file | stm32g4xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: C:/git/g4_release_v1.5.2/Firmware/Drivers/STM32G4xx_HAL_Driver/ Directory Reference

  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
STM32G4xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: C:/git/g4_release_v1.5.2/Firmware/Drivers/ Directory Reference

  • Firmware
  • Drivers
Drivers Directory Reference

Directories

directory STM32G4xx_HAL_Driver
Generated on Wed Dec 6 2023 15:11:42 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Firmware
    • Drivers
      • STM32G4xx_HAL_Driver
        • Inc
        • Src
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32g4xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32g4xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32g4xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g4xx_hal_adc_ex.c"
stm32g4xx_hal_adc.h [code] | Header file of ADC HAL module
stm32g4xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g4xx_hal_adc.c"
stm32g4xx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32g4xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions
stm32g4xx_hal_comp.h [code] | Header file of COMP HAL module
stm32g4xx_hal_conf.h [code] | HAL configuration template file. This file should be copied to the application folder and renamed to stm32g4xx_hal_conf.h
stm32g4xx_hal_cordic.c [code] | CORDIC HAL module driver. This file provides firmware functions to manage the following functionalities of the CORDIC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State functions
stm32g4xx_hal_cordic.h [code] | This file contains all the functions prototypes for the CORDIC firmware library
stm32g4xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions
stm32g4xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32g4xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_crc.h [code] | Header file of CRC HAL module
stm32g4xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32g4xx_hal_crc_ex.h [code] | Header file of CRC HAL extended module
stm32g4xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32g4xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32g4xx_hal_cryp_ex.c [code] | CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral
stm32g4xx_hal_cryp_ex.h [code] | Header file of CRYPEx HAL module
stm32g4xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32g4xx_hal_dac.h [code] | Header file of DAC HAL module
stm32g4xx_hal_dac_ex.c [code] | Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral
stm32g4xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32g4xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32g4xx_hal_dma.h [code] | Header file of DMA HAL module
stm32g4xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32g4xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32g4xx_hal_exti.c [code] | EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the Extended Interrupts and events controller (EXTI) peripheral: functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32g4xx_hal_exti.h [code] | Header file of EXTI HAL module
stm32g4xx_hal_fdcan.c [code] | FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions
stm32g4xx_hal_fdcan.h [code] | Header file of FDCAN HAL module
stm32g4xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32g4xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32g4xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions
stm32g4xx_hal_flash_ex.h [code] | Header file of FLASH HAL Extended module
stm32g4xx_hal_flash_ramfunc.c [code] | FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH Power Down in Run mode + FLASH DBANK User Option Byte
stm32g4xx_hal_flash_ramfunc.h [code] | Header file of FLASH RAMFUNC driver
stm32g4xx_hal_fmac.c [code] | FMAC HAL module driver. This file provides firmware functions to manage the following functionalities of the FMAC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Callback functions + IRQ handler management + Peripheral State and Error functions
stm32g4xx_hal_fmac.h [code] | Header for stm32g4xx_hal_fmac.c module
stm32g4xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32g4xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32g4xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extended module
stm32g4xx_hal_hrtim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the High Resolution Timer (HRTIM) peripheral: + HRTIM Initialization + DLL Calibration Start + Timer Time Base Unit Configuration + Simple Time Base Start/Stop + Simple Time Base Start/Stop Interrupt + Simple Time Base Start/Stop DMA Request + Simple Output Compare/PWM Channel Configuration + Simple Output Compare/PWM Channel Start/Stop Interrupt + Simple Output Compare/PWM Channel Start/Stop DMA Request + Simple Input Capture Channel Configuration + Simple Input Capture Channel Start/Stop Interrupt + Simple Input Capture Channel Start/Stop DMA Request + Simple One Pulse Channel Configuration + Simple One Pulse Channel Start/Stop Interrupt + HRTIM External Synchronization Configuration + HRTIM Burst Mode Controller Configuration + HRTIM Burst Mode Controller Enabling + HRTIM External Events Conditioning Configuration + HRTIM Faults Conditioning Configuration + HRTIM Faults Enabling + HRTIM ADC trigger Configuration + Waveform Timer Configuration + Waveform Event Filtering Configuration + Waveform Dead Time Insertion Configuration + Waveform Chopper Mode Configuration + Waveform Compare Unit Configuration + Waveform Capture Unit Configuration + Waveform Output Configuration + Waveform Counter Start/Stop + Waveform Counter Start/Stop Interrupt + Waveform Counter Start/Stop DMA Request + Waveform Output Enabling + Waveform Output Level Set/Get + Waveform Output State Get + Waveform Burst DMA Operation Configuration + Waveform Burst DMA Operation Start + Waveform Timer Counter Software Reset + Waveform Capture Software Trigger + Waveform Burst Mode Controller Software Trigger + Waveform Timer Pre-loadable Registers Update Enabling + Waveform Timer Pre-loadable Registers Software Update + Waveform Timer Delayed Protection Status Get + Waveform Timer Burst Status Get + Waveform Timer Push-Pull Status Get + Peripheral State Get
stm32g4xx_hal_hrtim.h [code] | Header file of HRTIM HAL module
stm32g4xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g4xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32g4xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions
stm32g4xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32g4xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g4xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32g4xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32g4xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32g4xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32g4xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32g4xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32g4xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32g4xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32g4xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32g4xx_hal_nand.h [code] | Header file of NAND HAL module
stm32g4xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32g4xx_hal_nor.h [code] | Header file of NOR HAL module
stm32g4xx_hal_opamp.c [code] | OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifiers peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_opamp.h [code] | Header file of OPAMP HAL module
stm32g4xx_hal_opamp_ex.c [code] | Extended OPAMP HAL module driver
stm32g4xx_hal_opamp_ex.h [code] | Header file of OPAMP HAL Extended module
stm32g4xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32g4xx_hal_pcd_ex.c [code] | PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32g4xx_hal_pcd_ex.h [code] | Header file of PCD HAL Extension module
stm32g4xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
stm32g4xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32g4xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32g4xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extended module
stm32g4xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32g4xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32g4xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32g4xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32g4xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions
stm32g4xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extended module
stm32g4xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_rng.h [code] | Header file of RNG HAL module
stm32g4xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32g4xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32g4xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32g4xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extended module
stm32g4xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_sai.h [code] | Header file of SAI HAL module
stm32g4xx_hal_sai_ex.c [code] | SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays
stm32g4xx_hal_sai_ex.h [code] | Header file of SAI HAL extended module
stm32g4xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32g4xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32g4xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32g4xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32g4xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g4xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32g4xx_hal_smbus_ex.c [code] | SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions
stm32g4xx_hal_smbus_ex.h [code] | Header file of SMBUS HAL Extended module
stm32g4xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32g4xx_hal_spi.h [code] | Header file of SPI HAL module
stm32g4xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions
stm32g4xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32g4xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32g4xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32g4xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration
stm32g4xx_hal_tim.h [code] | Header file of TIM HAL module
stm32g4xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration + Timer encoder index configuration
stm32g4xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32g4xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32g4xx_hal_uart.h [code] | Header file of UART HAL module
stm32g4xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32g4xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32g4xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32g4xx_hal_usart.h [code] | Header file of USART HAL module
stm32g4xx_hal_usart_ex.c [code] | Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions
stm32g4xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32g4xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions
stm32g4xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32g4xx_ll_adc.c [code] | ADC LL module driver
stm32g4xx_ll_adc.h [code] | Header file of ADC LL module
stm32g4xx_ll_bus.h [code] | Header file of BUS LL module
stm32g4xx_ll_comp.c [code] | COMP LL module driver
stm32g4xx_ll_comp.h [code] | Header file of COMP LL module
stm32g4xx_ll_cordic.c [code] | CORDIC LL module driver
stm32g4xx_ll_cordic.h [code] | Header file of CORDIC LL module
stm32g4xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32g4xx_ll_crc.c [code] | CRC LL module driver
stm32g4xx_ll_crc.h [code] | Header file of CRC LL module
stm32g4xx_ll_crs.c [code]
stm32g4xx_ll_crs.h [code] | CRS LL module driver
stm32g4xx_ll_dac.c [code] | DAC LL module driver
stm32g4xx_ll_dac.h [code] | Header file of DAC LL module
stm32g4xx_ll_dma.c [code] | DMA LL module driver
stm32g4xx_ll_dma.h [code] | Header file of DMA LL module
stm32g4xx_ll_dmamux.h [code] | Header file of DMAMUX LL module
stm32g4xx_ll_exti.c [code] | EXTI LL module driver
stm32g4xx_ll_exti.h [code] | Header file of EXTI LL module
stm32g4xx_ll_fmac.c [code] | Header for stm32g4xx_ll_fmac.c module
stm32g4xx_ll_fmac.h [code] | Header file of FMAC LL module
stm32g4xx_ll_gpio.c [code] | GPIO LL module driver
stm32g4xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32g4xx_ll_hrtim.c [code] | HRTIM LL module driver
stm32g4xx_ll_hrtim.h [code] | Header file of HRTIM LL module
stm32g4xx_ll_i2c.c [code] | I2C LL module driver
stm32g4xx_ll_i2c.h [code] | Header file of I2C LL module
stm32g4xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32g4xx_ll_lptim.c [code] | LPTIM LL module driver
stm32g4xx_ll_lptim.h [code] | Header file of LPTIM LL module
stm32g4xx_ll_lpuart.c [code] | LPUART LL module driver
stm32g4xx_ll_lpuart.h [code] | Header file of LPUART LL module
stm32g4xx_ll_opamp.c [code] | OPAMP LL module driver
stm32g4xx_ll_opamp.h [code] | Header file of OPAMP LL module
stm32g4xx_ll_pwr.c [code] | PWR LL module driver
stm32g4xx_ll_pwr.h [code] | Header file of PWR LL module
stm32g4xx_ll_rcc.c [code] | RCC LL module driver
stm32g4xx_ll_rcc.h [code] | Header file of RCC LL module
stm32g4xx_ll_rng.c [code] | RNG LL module driver
stm32g4xx_ll_rng.h [code] | Header file of RNG LL module
stm32g4xx_ll_rtc.c [code] | RTC LL module driver
stm32g4xx_ll_rtc.h [code] | Header file of RTC LL module
stm32g4xx_ll_spi.c [code] | SPI LL module driver
stm32g4xx_ll_spi.h [code] | Header file of SPI LL module
stm32g4xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32g4xx_ll_tim.c [code] | TIM LL module driver
stm32g4xx_ll_tim.h [code] | Header file of TIM LL module
stm32g4xx_ll_ucpd.c [code] | UCPD LL module driver
stm32g4xx_ll_ucpd.h [code] | Header file of UCPD LL module
stm32g4xx_ll_usart.c [code] | USART LL module driver
stm32g4xx_ll_usart.h [code] | Header file of USART LL module
stm32g4xx_ll_utils.c [code] | UTILS LL module driver
stm32g4xx_ll_utils.h [code] | Header file of UTILS LL module
stm32g4xx_ll_wwdg.h [code] | Header file of WWDG LL module
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC

Modules
ADC
STM32G4xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros
ADC Exported Macros

Detailed Description

ADC HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

ADC Initialization and Configuration functions.

ADC Input and Output operation functions

ADC IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

HAL ADC macro to manage HAL ADC handle, IT and flags.
HAL ADC helper macro
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC

Modules
ADC
STM32G4xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Clock source
ADC common - Measurement path to internal channels
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Low power mode
ADC instance - Offset instance
ADC instance - Offset state
ADC instance - Offset sign
ADC instance - Offset saturation mode
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Sampling mode
ADC group regular - Continuous mode
ADC group regular - DMA transfer of ADC conversion data
ADC instance - ADC sampling time common configuration
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Context queue mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Channel - Single or differential ending
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Analog watchdog - filtering config
Oversampling - Oversampling scope
Oversampling - Discontinuous mode
Oversampling - Ratio
Oversampling - Data right shift
Multimode - Mode
Multimode - DMA transfer
Multimode - Delay between two sampling phases
Multimode - ADC master or slave
Definitions of constants used by helper macro
Definitions of ADC hardware constraints delays
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several

ADC instances.

Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC transversal scope: oversampling
Configuration of ADC hierarchical scope: multimode
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADCEx

Modules
ADCEx
STM32G4xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Exported Macros
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Exported Constants

Modules
ADC Extended Exported Constants
ADCEx

Modules

ADC group injected trigger source
ADC group injected trigger edge (when external trigger is selected)
Channel - Single or differential ending
ADC instance - Offset number
ADC Extended Offset Sign
ADC group injected - Sequencer ranks
Multimode - Mode
ADC instance - Groups
ADCx CFGR fields
ADCx SMPR1 fields
ADCx CFGR sub fields
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Exported Functions

Modules
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

ADC Extended Peripheral Control functions

ADC Extended Peripheral Control functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: ADC Extended Exported Types

Data Structures
ADC Extended Exported Types
ADCEx

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BUS

Modules
BUS
STM32G4xx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
AHB2 GRP1 PERIPH
AHB3 GRP1 PERIPH
APB1 GRP1 PERIPH
APB1 GRP2 PERIPH
APB2 GRP1 PERIPH
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
AHB2
AHB3
APB1
APB2
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP

Modules
COMP
STM32G4xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Error Code
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP output Polarity
COMP blanking source
COMP Output Level
COMP output to EXTI
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP

Modules
COMP
STM32G4xx_LL_Driver

Modules

COMP Private Macros
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator input - Hysteresis
Comparator output - Output polarity
Comparator output - Blanking source
Comparator output - Output level
Definitions of COMP hardware constraints delays
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of comparator inputs
Configuration of comparator output
Operation on comparator instance
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP private macros to get EXTI line associated with comparators
COMP private macros to check input parameters
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC

Modules
CORDIC
STM32G4xx_HAL_Driver

CORDIC HAL driver modules. More...

Modules

CORDIC Private Functions
CORDIC Exported Functions
CORDIC Exported Types
CORDIC Exported Constants
CORDIC Exported Macros
CORDIC Private Macros

Detailed Description

CORDIC HAL driver modules.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Constants

Modules
CORDIC Exported Constants
CORDIC

Modules

CORDIC Error code
CORDIC Function
CORDIC Precision in Cycles Number
CORDIC Scaling factor
CORDIC Interrupts Enable bit
DMA Read Request Enable bit
DMA Write Request Enable bit
CORDIC Number of 32-bit write required for one calculation
CORDIC Number of 32-bit read required after one calculation
CORDIC input data size
CORDIC Results Size
CORDIC status flags
CORDIC DMA direction
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Functions

Modules
CORDIC Exported Functions
CORDIC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Control functions.

Callback functions

Callback functions.

IRQ handler management

IRQ handler.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC

Modules
CORDIC
STM32G4xx_LL_Driver

Modules

CORDIC Exported Constants
CORDIC Exported Macros
CORDIC Exported Functions
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Constants

Modules
CORDIC Exported Constants
CORDIC

Modules

Get Flags Defines

Flags defines which can be used with LL_CORDIC_ReadReg function.

IT Defines

IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.

FUNCTION
PRECISION
SCALE
NBWRITE
NBREAD
INSIZE
OUTSIZE
DMA register data
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Functions

Modules
CORDIC Exported Functions
CORDIC

Modules

CORDIC Configuration functions
IT_Management
DMA_Management
FLAG_Management
Data_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORDIC Exported Macros

Modules
CORDIC Exported Macros
CORDIC

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX

Modules
CORTEX
STM32G4xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX Exported Functions
CORTEX Private Macros

Detailed Description

CORTEX HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX SysTick clock source
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
CORTEX MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Types

Modules
CORTEX Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX

Modules
CORTEX
STM32G4xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
MPU
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
CORTEX Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC

Modules
CRC
STM32G4xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC Private Macros

Detailed Description

CRC HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the peripheral
CRC polynomial possible sizes actual definitions
Input Buffer Format
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC

Modules
CRC
STM32G4xx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRCEx

Modules
CRCEx
STM32G4xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRC Extended Exported Constants
CRC Extended Exported Macros
CRC Extended Private Macros

Detailed Description

CRC Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Extended Exported Constants

Modules
CRC Extended Exported Constants
CRCEx

Modules

Input Data Inversion Modes
Output Data Inversion Modes
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended Initialization/de-initialization functions

Extended Initialization and Configuration functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRS

Modules
CRS
STM32G4xx_LL_Driver

Modules

CRS Exported Constants
CRS Exported Macros
CRS Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRS Exported Constants

Modules
CRS Exported Constants
CRS

Modules

Get Flags Defines

Flags defines which can be used with LL_CRS_ReadReg function.

IT Defines

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Synchronization Signal Divider
Synchronization Signal Source
Synchronization Signal Polarity
Frequency Error Direction
Default Values
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRS Exported Functions

Modules
CRS Exported Functions
CRS

Modules

Configuration
CRS_Management
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: CRS Exported Macros

Modules
CRS Exported Macros
CRS

Modules

Common Write and read registers Macros
Exported_Macros_Calculate_Reload
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC trigger selection
DAC output buffer
DAC Channel selection
DAC data alignment
DAC flags definition
DAC IT definition
DAC ConnectOnChipPeripheral
DAC User Trimming
DAC power mode
DAC high frequency interface mode
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC

Modules
DAC
STM32G4xx_LL_Driver

Modules

DAC Private Constants
DAC Private Macros
DAC Exported Init structure
DAC Exported Constants
DAC Exported Macros
DAC Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Init structure

Data Structures
DAC Exported Init structure
DAC

Data Structures

struct LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC flags

Flags defines which can be used with LL_DAC_ReadReg function.

DAC interruptions

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

DAC channels
DAC high frequency interface mode

High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode.

DAC operating mode
DAC trigger source
DAC waveform automatic generation mode
DAC wave generation - Noise LFSR unmask bits
DAC wave generation - Triangle amplitude
DAC wave generation - Sawtooth polarity mode
DAC channel output mode
DAC channel output buffer
DAC channel output connection
DAC channel signed format
DAC channel output resolution
DAC registers compliant with specific purpose
Definitions of DAC hardware constraints delays
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Configuration of DAC instance
Configuration of DAC channels
DMA Management
Operation on DAC channels
FLAG Management
IT management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DAC Exported Macros

Modules
DAC Exported Macros
DAC

Modules

Common write and read registers macros
DAC helper macro
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

HAL State structures definition. More...

Modules

DACEx lfsrunmask triangle amplitude
DAC Sawtooth polarity mode

Detailed Description

HAL State structures definition.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DACEx Exported Functions

Modules
DACEx Exported Functions
DACEx

Modules

IO operation functions

Extended IO operation functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA

Modules
DMA
STM32G4xx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

Detailed Description

DMA HAL module driver.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA request
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA

Modules
DMA
STM32G4xx_LL_Driver

Modules

DMA Private Variables
DMA Private Constants
DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx

Modules
DMAEx
STM32G4xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Functions
DMAEx Exported Types
DMAEx Exported Constants
DMAEx Private Macros

DMAEx private macros.

Detailed Description

DMA Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx Exported Constants

Modules
DMAEx Exported Constants
DMAEx

Modules

DMAMUX SyncSignalID selection
DMAMUX SyncPolarity selection
DMAMUX SignalGeneratorID selection
DMAMUX RequestGeneneratorPolarity selection
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

Modules

DMAEx Extended features functions

Extended features functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAEx Exported Types

Data Structures
DMAEx Exported Types
DMAEx

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMA Synchro definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX

Modules
DMAMUX
STM32G4xx_LL_Driver

Modules

DMAMUX Private Constants
DMAMUX Private Macros
DMAMUX Exported Constants
DMAMUX Exported Macros
DMAMUX Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Exported Constants

Modules
DMAMUX Exported Constants
DMAMUX

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMAMUX_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Transfer request
DMAMUX Channel
Synchronization Signal Polarity
Synchronization Signal Event
Request Generator Channel
External Request Signal Generation Polarity
External Request Signal Generation
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Exported Functions

Modules
DMAMUX Exported Functions
DMAMUX

Modules

Configuration
FLAG_Management
IT_Management
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: DMAMUX Exported Macros

Modules
DMAMUX Exported Macros
DMAMUX

Modules

Common Write and read registers macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI

Modules
EXTI
STM32G4xx_HAL_Driver

EXTI HAL module driver. More...

Modules

EXTI Private Constants

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

EXTI Exported Types
EXTI Exported Constants
EXTI Exported Macros
EXTI Private Macros
EXTI Exported Functions

EXTI Exported Functions.

Detailed Description

EXTI HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

EXTI Line
EXTI Mode
EXTI Trigger
EXTI GPIOSel
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

EXTI Exported Functions. More...

Modules

Configuration functions

Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

EXTI Exported Functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI

Modules
EXTI
STM32G4xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN

Modules
FDCAN
STM32G4xx_HAL_Driver

FDCAN HAL module driver. More...

Modules

FDCAN Exported Functions
FDCAN Private Functions
FDCAN Exported Types
FDCAN Exported Constants
FDCAN Exported Macros
FDCAN Private Variables
FDCAN Private Constants
FDCAN Private Macros
FDCAN_Private_Functions_Prototypes

Detailed Description

FDCAN HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Exported Constants

Modules
FDCAN Exported Constants
FDCAN

Modules

HAL FDCAN Error Code
FDCAN Frame Format
FDCAN Operating Mode
FDCAN Clock Divider
FDCAN Tx FIFO/Queue Mode
FDCAN ID Type
FDCAN Frame Type
FDCAN Data Length Code
FDCAN Error State Indicator
FDCAN Bit Rate Switching
FDCAN format
FDCAN Event FIFO control
FDCAN Filter Type
FDCAN Filter Configuration
FDCAN Tx Location
FDCAN Rx Location
FDCAN Event Type
FDCAN High Priority Message Storage
FDCAN protocol error code
FDCAN communication state
FDCAN FIFO operation mode
FDCAN non-matching frames
FDCAN reject remote frames
FDCAN interrupt line
FDCAN timestamp
FDCAN timestamp prescaler
FDCAN timeout operation
Interrupt masks
FDCAN Flags
FDCAN Interrupts
FDCAN Interrupts List
FDCAN Interrupts Group
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Exported Functions

Modules
FDCAN Exported Functions
FDCAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Configuration functions

FDCAN Configuration functions.

Control functions

Control functions.

Interrupts management

Interrupts management.

Callback functions

FDCAN Callback functions.

Peripheral State functions

FDCAN Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FDCAN Interrupts

Modules
FDCAN Interrupts
FDCAN Exported Constants

Modules

FDCAN Tx Interrupts
FDCAN Rx Interrupts
FDCAN Counter Interrupts
FDCAN Tx Event FIFO Interrupts
FDCAN Rx FIFO 0 Interrupts
FDCAN Rx FIFO 1 Interrupts
FDCAN Error Interrupts
FDCAN Error Status Interrupts
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH

Modules
FLASH
STM32G4xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Constants
FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

FLASH Interrupts Macros

macros to handle FLASH interrupts

FLASH Exported Variables
FLASH Private Macros

Detailed Description

FLASH HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error
FLASH Erase Type
FLASH Banks
FLASH Program Type
FLASH Option Bytes Type
FLASH WRP Area
FLASH Boot Lock
FLASH Option Bytes Read Protection
FLASH Option Bytes User Type
FLASH Option Bytes User BOR Level
FLASH Option Bytes User Reset On Stop
FLASH Option Bytes User Reset On Standby
FLASH Option Bytes User Reset On Shutdown
FLASH Option Bytes User IWDG Type
FLASH Option Bytes User IWDG Mode On Stop
FLASH Option Bytes User IWDG Mode On Standby
FLASH Option Bytes User WWDG Type
FLASH Option Bytes User BOOT1 Type
FLASH Option Bytes User SRAM Parity Check Type
FLASH Option Bytes User CCMSRAM Erase On Reset Type
FLASH Option Bytes User Software BOOT0
FLASH Option Bytes User nBOOT0 option bit
FLASH Option Bytes User NRST mode bit
FLASH Option Bytes User internal reset holder bit
FLASH Option Bytes PCROP On RDP Level Type
FLASH Latency
FLASH Keys
FLASH Flags Definition
FLASH Interrupts Definition

FLASH Interrupt definition.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

Management functions.

Peripheral State and Errors functions

Peripheral Errors functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH_RAMFUNC

Modules
FLASH_RAMFUNC
STM32G4xx_HAL_Driver

FLASH functions executed from RAM. More...

Modules

FLASH_RAMFUNC Exported Functions

Detailed Description

FLASH functions executed from RAM.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASH_RAMFUNC Exported Functions

Modules
FLASH_RAMFUNC Exported Functions
FLASH_RAMFUNC

Modules

Peripheral features functions

Data transfers functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32G4xx_HAL_Driver

FLASH Extended HAL module driver. More...

Modules

FLASHEx Private Functions
FLASHEx Exported Functions

Detailed Description

FLASH Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FLASHEx Exported Functions

Modules
FLASHEx Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC

Modules
FMAC
STM32G4xx_HAL_Driver

FMAC HAL driver module. More...

Modules

FMAC Private Constants
FMAC Private Macros
FMAC Exported Functions
FMAC Private Functions
FMAC Exported Types
FMAC Exported Constants
FMAC Exported variables
FMAC Exported Macros

Detailed Description

FMAC HAL driver module.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Constants

Modules
FMAC Exported Constants
FMAC

Modules

FMAC Error code
FMAC Functions
FMAC Data Buffer Threshold
FMAC Buffer Access
FMAC Clip State
FMAC status flags
FMAC Interrupts Enable bit
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Functions

Modules
FMAC Exported Functions
FMAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Control functions.

Callback functions

Callback functions.

IRQ handler management

IRQ handler.

Peripheral State and Error functions

Peripheral State and Error functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC

Modules
FMAC
STM32G4xx_LL_Driver

Modules

FMAC Exported Constants
FMAC Exported Macros
FMAC Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Constants

Modules
FMAC Exported Constants
FMAC

Modules

Get Flag Defines

Flag defines which can be used with LL_FMAC_ReadReg function.

IT Defines

IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions.

FMAC watermarks

Watermark defines that can be used for buffer full (input) or buffer empty (output)

FMAC functions
FMAC processing
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Functions

Modules
FMAC Exported Functions
FMAC

Modules

FMAC Configuration functions
Reset_Management
DMA_Management
IT_Management
FLAG_Management
Data_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: FMAC Exported Macros

Modules
FMAC Exported Macros
FMAC

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO

Modules
GPIO
STM32G4xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

GPIO Private Macros
GPIO Exported Functions

GPIO Exported Functions.

Detailed Description

GPIO HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins
GPIO mode

GPIO Configuration Mode Elements values convention: 0x00WX00YZ.

GPIO speed

GPIO Output Maximum frequency.

GPIO pull

GPIO Pull-Up or Pull-Down Activation.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

GPIO Exported Functions. More...

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

GPIO Exported Functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO

Modules
GPIO
STM32G4xx_LL_Driver

Modules

GPIO Private Macros

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:37 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32G4xx_HAL_Driver

GPIO Extended HAL module driver. More...

Modules

GPIOEx Exported Constants
GPIOEx Exported Macros

Detailed Description

GPIO Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

GPIOEx Alternate function selection
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: GPIOEx Exported Macros

Modules
GPIOEx Exported Macros
GPIOEx

Modules

GPIOEx Get Port Index
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Exported Constants

Modules
HAL Exported Constants
HAL

Modules

Tick Frequency
SYSCFG Exported Constants
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

HAL Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

HAL Debug functions

HAL Debug functions.

HAL SYSCFG configuration functions

HAL SYSCFG configuration functions.

HAL Exported Variables
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C

Modules
I2C
STM32G4xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Detailed Description

I2C HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction Master Point of View
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C

Modules
I2C
STM32G4xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2CEx

Modules
I2CEx
STM32G4xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants
I2C Extended Exported Macros
I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Detailed Description

I2C Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Filter Mode Functions

Filter Mode Functions.

WakeUp Mode Functions

WakeUp Mode Functions.

Fast Mode Plus Functions

Fast Mode Plus Functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error
I2S Mode
I2S Standard
I2S Data Format
I2S MCLK Output
I2S Audio Frequency
I2S Clock Polarity
I2S Interrupts Definition
I2S Flags Definition
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S

Modules
I2S
STM32G4xx_LL_Driver

Modules

I2S Private Constants
I2S Private Macros
I2S Exported Init structure
I2S Exported Constants
I2S Exported Macros
I2S Exported Functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Init structure

Data Structures
I2S Exported Init structure
I2S

Data Structures

struct LL_I2S_InitTypeDef
I2S Init structure definition. More...
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

Get Flags Defines

Flags defines which can be used with LL_I2S_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Data format
Clock Polarity
I2s Standard
Operation Mode
Prescaler Factor
MCLK Output
Audio Frequency
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Configuration
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: I2S Exported Macros

Modules
I2S Exported Macros
I2S

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA

Modules
IRDA
STM32G4xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Private Macros
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros

Detailed Description

HAL IRDA module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA State Code Definition
IRDA Error Code Definition
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA Clock Prescaler
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32G4xx_HAL_Driver

IRDA Extended HAL module driver. More...

Modules

IRDAEx Extended Exported Constants
IRDAEx Private Macros

Detailed Description

IRDA Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IRDAEx Extended Exported Constants

Modules
IRDAEx Extended Exported Constants
IRDAEx

Modules

IRDAEx Word Length
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG

Modules
IWDG
STM32G4xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
Generated on Wed Dec 6 2023 15:11:32 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG

Modules
IWDG
STM32G4xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM

Modules
LPTIM
STM32G4xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Private Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros

Detailed Description

LPTIM HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM

Modules
LPTIM
STM32G4xx_LL_Driver

Modules

LPTIM Private Functions
LPTIM Private Macros
LPTIM Exported Init structure
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Exported Functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Init structure

Data Structures
LPTIM Exported Init structure
LPTIM

Data Structures

struct LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

Get Flags Defines

Flags defines which can be used with LL_LPTIM_ReadReg function.

IT Defines

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Operating Mode
Update Mode
Counter Mode
Output Waveform Type
Output Polarity
Prescaler Value
Trigger Source
Trigger Filter
Trigger Polarity
Clock Source
Clock Filter
Clock Polarity
Encoder Mode
Input1 Source
Input2 Source
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialisation and deinitialisation functions

Legacy definitions for compatibility purpose.

LPTIM Configuration
Trigger Configuration
Clock Configuration
Encoder Mode
FLAG Management
Interrupt Management
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPTIM Exported Macros

Modules
LPTIM Exported Macros
LPTIM

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART

Modules
LPUART
STM32G4xx_LL_Driver

Modules

LPUART Private Variables
LPUART Private Constants
LPUART Private Macros
LPUART Exported Init structures
LPUART Exported Constants
LPUART Exported Macros
LPUART Exported Functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Exported Init structures

Data Structures
LPUART Exported Init structures
LPUART

Data Structures

struct LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Exported Constants

Modules
LPUART Exported Constants
LPUART

Modules

Clear Flags Defines

Flags defines which can be used with LL_LPUART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_LPUART_ReadReg function.

IT Defines

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

FIFO Threshold
Direction
Parity Control
Wakeup
Datawidth
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Address Length Detection
Hardware Control
Wakeup Activation
Driver Enable Polarity
DMA Register Data
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Exported Functions

Modules
LPUART Exported Functions
LPUART

Modules

Configuration functions
Configuration functions related to Half Duplex feature
Configuration functions related to Driver Enable feature
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: LPUART Exported Macros

Modules
LPUART Exported Macros
LPUART

Modules

Common Write and read registers Macros
Helper Macros
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP Mode
OPAMP Non Inverting Input
OPAMP Inverting Input
OPAMP Timer Controlled Mux mode
OPAMP Non Inverting Input Secondary
OPAMP Inverting Input Secondary
OPAMP Pga Connect
OPAMP Pga Gain
OPAMP PowerMode
OPAMP User Trimming
OPAMP Factory Trimming
OPAMP VREF
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP

Modules
OPAMP
STM32G4xx_LL_Driver

Modules

OPAMP Private Constants
OPAMP Private Macros
OPAMP Exported Init structure
OPAMP Exported Constants
OPAMP Exported Macros
OPAMP Exported Functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Init structure

Data Structures
OPAMP Exported Init structure
OPAMP

Data Structures

struct LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP mode calibration or functional.
OPAMP functional mode
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP input non-inverting
OPAMP input inverting
OPAMP input non-inverting secondary
OPAMP input inverting secondary
OPAMP internal output mode
OPAMP inputs multiplexer mode
OPAMP PowerMode
OPAMP trimming mode
OPAMP trimming of transistors differential pair NMOS or PMOS
Definitions of OPAMP hardware constraints delays
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Functions

Modules
OPAMP Exported Functions
OPAMP

Modules

Configuration of OPAMP hierarchical scope: OPAMP instance
Configuration of OPAMP inputs
Configuration and operation of OPAMP trimming
Operation on OPAMP instance
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Exported Macros

Modules
OPAMP Exported Macros
OPAMP

Modules

Common write and read registers macro
Generated on Wed Dec 6 2023 15:11:38 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Private Constants

Modules
OPAMP Private Constants
OPAMP

OPAMP Private constants and defines. More...

Modules

OPAMP Input

Detailed Description

OPAMP Private constants and defines.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMPEx

Modules
OPAMPEx
STM32G4xx_HAL_Driver

Modules

OPAMP Extended Exported Functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: OPAMP Extended Exported Functions

Modules
OPAMP Extended Exported Functions
OPAMPEx

Modules

Extended Input and Output operation functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD

Modules
PCD
STM32G4xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
PCD Error Code definition

PCD Error Code definition.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
PCD EP0 MPS
PCD ENDP
PCD Endpoint Kind
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCDEx

Modules
PCDEx
STM32G4xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Detailed Description

PCD Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR

Modules
PWR
STM32G4xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Private Defines
PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macros
PWR Private Macros

Detailed Description

PWR HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Programmable Voltage Detection levels
PWR PVD interrupt and event mode
PWR regulator mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR PVD external interrupt line
PWR PVD event line
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Private Defines

Modules
PWR Extended Private Defines
PWREx

Modules

PWR PVM Mode Mask
PWR Extended Flag Setting Time Out Value
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR

Modules
PWR
STM32G4xx_LL_Driver

Modules

PWR Exported Constants
PWR Exported Macros
PWR Exported Functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

REGU VOLTAGE
MODE PWR
Peripheral voltage monitoring
PVDLEVEL
WAKEUP
BATT CHARG RESISTOR
GPIO
GPIO BIT
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
Legacy functions name
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Private Defines

Modules
PWR Private Defines
PWR

Modules

PWR PVD Mode Mask
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Exported Constants

Modules
PWR Extended Exported Constants
PWREx

Modules

Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR wake-up pins
Peripheral Voltage Monitoring type
PWR PVM interrupt and event mode
PWR Regulator voltage scale
PWR battery charging resistor selection
PWR battery charging
GPIO bit number for I/O setting in standby/shutdown mode
GPIO port
PWR PVM external interrupts lines
PWR PVM event lines
PWR Status Flags

Elements values convention: 0000 0000 0XXY YYYYb.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Exported Functions

Modules
PWR Extended Exported Functions
PWREx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: PWR Extended Exported Types

Data Structures
PWR Extended Exported Types
PWREx

Data Structures

struct PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC

Modules
RCC
STM32G4xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Functions
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Timeout Values
Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
HSI48 Config
PLL Config
PLLM Clock Divider
PLLP Clock Divider
PLLQ Clock Divider
PLLR Clock Divider
PLL Clock Source
PLL Clock Output
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1 APB2 Clock Source
RTC Clock Source
MCO Index
MCO1 Clock Source
MCO1 Clock Prescaler
Interrupts
Flags

Elements values convention: XXXYYYYYb.

LSE Drive Config
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC

Modules
RCC
STM32G4xx_LL_Driver

Modules

RCC Private functions
RCC Private Variables
RCC Private Constants
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

LSE oscillator drive capability
LSCO Selection
System clock switch
System clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
APB high-speed prescaler (APB2)
MCO1 SOURCE selection
MCO1 prescaler
Peripheral clock frequency
Peripheral USART clock source selection
Peripheral UART clock source selection
Peripheral LPUART clock source selection
Peripheral I2C clock source selection
Peripheral LPTIM clock source selection
Peripheral SAI clock source selection
Peripheral I2S clock source selection
Peripheral FDCAN clock source selection
Peripheral RNG clock source selection
Peripheral USB clock source selection
Peripheral ADC clock source selection
Peripheral QUADSPI get clock source
Peripheral USART get clock source
Peripheral UART get clock source
Peripheral LPUART get clock source
Peripheral I2C get clock source
Peripheral LPTIM get clock source
Peripheral SAI get clock source
Peripheral I2S get clock source
Peripheral FDCAN get clock source
Peripheral RNG get clock source
Peripheral USB get clock source
Peripheral ADC get clock source
RTC clock source selection
PLL entry clock source
PLL division factor
PLL division factor (PLLR)
PLL division factor (PLLP)
PLL division factor (PLLQ)
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
HSI48
LSE
LSI
LSCO
System
MCO
Peripheral Clock Source
RTC
PLL
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx

Modules
RCCEx
STM32G4xx_HAL_Driver

RCC Extended HAL module driver. More...

Modules

RCCEx Private Constants
RCCEx Private Functions
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
RCCEx_Private_Macros

Detailed Description

RCC Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

Low Speed Clock Source
Periph Clock Selection
USART1 Clock Source
USART2 Clock Source
USART3 Clock Source
UART4 Clock Source
LPUART1 Clock Source
I2C1 Clock Source
I2C2 Clock Source
I2C3 Clock Source
LPTIM1 Clock Source
SAI1 Clock Source
I2S Clock Source
FDCAN Clock Source
RNG Clock Source
USB Clock Source
ADC12 Clock Source
RCC LSE CSS external interrupt line
RCCEx CRS Status
RCCEx CRS SynchroSource
RCCEx CRS SynchroDivider
RCCEx CRS SynchroPolarity
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCCEx CRS Interrupt Sources
RCCEx CRS Flags
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended Clock management functions

Extended Clock management functions.

Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...
Generated on Wed Dec 6 2023 15:11:33 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG

Modules
RNG
STM32G4xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Private Constants
RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Macros

Detailed Description

RNG HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
RNG Clock Error Detection
RNG Error Definition
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and configuration functions

Initialization and configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG Init Structure definition
RNG State Structure definition
RNG Handle Structure definition
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Init Structure definition

Data Structures
RNG Init Structure definition
RNG Exported Types

Data Structures

struct RNG_InitTypeDef
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG

Modules
RNG
STM32G4xx_LL_Driver

Modules

RNG Private Macros
RNG Exported Init structures
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Init structures

Data Structures
RNG Exported Init structures
RNG

Data Structures

struct LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

Clock Error Detection
Get Flags Defines

Flags defines which can be used with LL_RNG_ReadReg function.

IT Defines

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

RNG Configuration functions
FLAG Management
IT Management
Data Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RNG Exported Macros

Modules
RNG Exported Macros
RNG

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC

Modules
RTC
STM32G4xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTCEx Output Selection Definition
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output Pull-Up ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLightSaving Definitions
RTC StoreOperation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC AlarmDateWeekDay Definitions
RTC AlarmMask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
RTC Flags Definitions

Elements values convention: 000000XX000YYYYYb.

RTC Clear Flags Definitions
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC

Modules
RTC
STM32G4xx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
Convert helper Macros
Date helper Macros
Time helper Macros
RTC Exported Functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
INTERNAL TAMPER
BACKUP
WAKEUP CLOCK DIV
Calibration output
Calibration pulse insertion
Calibration period
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
STM32G4xx_LL_Driver | RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Tamper
Internal Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:39 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx

Modules
RTCEx
STM32G4xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Exported Functions
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTCEx Time Stamp Edges definition
RTCEx TimeStamp Pin Selection
RTCEx Wakeup Timer Definitions
RTCEx Smooth calib period Definitions
RTCEx Smooth calib Plus pulses Definitions
RTCEx Calib Output selection Definitions
RTCEx Add 1 Second Parameter Definitions
RTCEx Tamper Pins Definition
RTCEx Internal Tamper Pins Definition
RTCEx Tamper Trigger
RTCEx Tamper MaskFlag
RTCEx Tamper EraseBackUp
RTCEx Tamper Filter
RTCEx Tamper Sampling Frequencies
RTCEx Tamper Pin Precharge Duration
RTCEx Tamper Pull UP
RTCEx Tamper TimeStamp On Tamper Detection
RTCEx Internal Tamper Interrupt
RTCEx Flags
RTCEx Backup Registers Definition
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

Extended RTC TimeStamp functions

RTC TimeStamp and Tamper functions.

Extended RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

Extended RTC Tamper functions

Extended RTC Tamper functions.

Extended RTC Backup register functions

Extended RTC Backup register functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Exported Types

Modules
RTCEx Exported Types
RTCEx

Modules

RTCEx Tamper structure definition
RTCEx Internal Tamper structure definition
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Internal Tamper structure definition

Data Structures
RTCEx Internal Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_InternalTamperTypeDef
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: RTCEx Tamper structure definition

Data Structures
RTCEx Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_TamperTypeDef
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI

Modules
SAI
STM32G4xx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Private Functions

Private functions.

SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI Private Macros

Detailed Description

SAI HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Block Master Clock Output
SAI Supported protocol
SAI protocol data size
SAI Audio Frequency
SAI Block Master Clock OverSampling
SAI PDM Clock Enable
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Exported Functions

Modules
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Frame Structure definition

Data Structures
SAI Frame Structure definition
SAI Exported Types

SAI Frame Init structure definition. More...

Data Structures

struct SAI_FrameInitTypeDef

Detailed Description

SAI Frame Init structure definition.

Note:
For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Init Structure definition

Data Structures
SAI Init Structure definition
SAI Exported Types

SAI Init Structure definition. More...

Data Structures

struct SAI_InitTypeDef

Detailed Description

SAI Init Structure definition.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI PDM Structure definition

Data Structures
SAI PDM Structure definition
SAI Exported Types

SAI PDM Init structure definition. More...

Data Structures

struct SAI_PdmInitTypeDef

Detailed Description

SAI PDM Init structure definition.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAI Slot Structure definition

Data Structures
SAI Slot Structure definition
SAI Exported Types

SAI Block Slot Init Structure definition. More...

Data Structures

struct SAI_SlotInitTypeDef

Detailed Description

SAI Block Slot Init Structure definition.

Note:
For SPDIF protocol, these parameters are not used (set by hardware).
For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx

Modules
SAIEx
STM32G4xx_HAL_Driver

SAI Extended HAL module driver. More...

Modules

SAIEx Extended Private Defines
SAIEx Extended Exported Functions
SAIEx Exported Types
SAIEx Extended Private Macros

Detailed Description

SAI Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx Extended Exported Functions

Modules
SAIEx Extended Exported Functions
SAIEx

Modules

Peripheral Control functions

SAIEx control functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SAIEx Exported Types

Data Structures
SAIEx Exported Types
SAIEx

Data Structures

struct SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32G4xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD State Code Definition
SMARTCARD Error Code Definition
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD Clock Prescaler
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD interruptions flags mask
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32G4xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Private Constants
SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Detailed Description

SMARTCARD Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARD FIFO mode

SMARTCARD FIFO mode.

SMARTCARD TXFIFO threshold level

SMARTCARD TXFIFO level.

SMARTCARD RXFIFO threshold level

SMARTCARD RXFIFO level.

SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Extended Peripheral IO operation functions

SMARTCARD Transmit and Receive functions.

Extended Peripheral FIFO Control functions

SMARTCARD control functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS

Modules
SMBUS
STM32G4xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS ownaddress2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUSEx

Modules
SMBUSEx
STM32G4xx_HAL_Driver

SMBUS Extended HAL module driver. More...

Modules

SMBUS Extended Exported Functions
SMBUS Extended Exported Constants
SMBUS Extended Exported Macros
SMBUS Extended Private Constants
SMBUS Extended Private Macros
SMBUS Extended Private Functions

Detailed Description

SMBUS Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Exported Constants

Modules
SMBUS Extended Exported Constants
SMBUSEx

Modules

SMBUS Extended Fast Mode Plus
Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SMBUS Extended Exported Functions

Modules
SMBUS Extended Exported Functions
SMBUSEx

Modules

WakeUp Mode Functions

WakeUp Mode Functions.

Fast Mode Plus Functions

Fast Mode Plus Functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI

Modules
SPI
STM32G4xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI Interrupt Definition
SPI Flags Definition
SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Wed Dec 6 2023 15:11:34 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI

Modules
SPI
STM32G4xx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Serial Protocol
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
CRC Length
RX FIFO Threshold
RX FIFO Level
TX FIFO Level
DMA Parity
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPIEx

Modules
SPIEx
STM32G4xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Private Constants
SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: STM32G4xx_HAL_Driver

Modules
STM32G4xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

COMP

COMP HAL module driver.

CORDIC

CORDIC HAL driver modules.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

DAC

DAC driver modules.

DACEx

DAC Extended HAL module driver.

DMA

DMA HAL module driver.

DMAEx

DMA Extended HAL module driver.

EXTI

EXTI HAL module driver.

FDCAN

FDCAN HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH Extended HAL module driver.

FLASH_RAMFUNC

FLASH functions executed from RAM.

FMAC

FMAC HAL driver module.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO Extended HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

I2S

I2S HAL module driver.

IRDA

HAL IRDA module driver.

IRDAEx

IRDA Extended HAL module driver.

IWDG

IWDG HAL module driver.

LPTIM

LPTIM HAL module driver.

OPAMP

OPAMP HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extended HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extended HAL module driver.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SMBUSEx

SMBUS Extended HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

USARTEx

USART Extended HAL module driver.

WWDG

WWDG HAL module driver.

CRYP
CRYPEx
OPAMPEx
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: STM32G4xx_LL_Driver

Modules
STM32G4xx_LL_Driver

Modules

ADC
BUS
COMP
CORDIC
CORTEX
CRC
CRS
DAC
DMA
DMAMUX
EXTI
FMAC
GPIO
I2C
IWDG
LPTIM
LPUART
OPAMP
PWR
RCC
RNG
RTC
RTC Exported Functions
SPI
I2S
SYSTEM
TIM
UCPD
USART
UTILS
WWDG
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSCFG Exported Constants

Modules
SYSCFG Exported Constants
HAL Exported Constants

Modules

Boot Mode
FPU Interrupts
CCM Write protection
VREFBUF Voltage Scale
VREFBUF High Impedance
Flags
Fast-mode Plus on GPIO
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTEM

Modules
SYSTEM
STM32G4xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG REMAP
SYSCFG BANK MODE
SYSCFG I2C FASTMODEPLUS
SYSCFG EXTI PORT
SYSCFG EXTI LINE
SYSCFG TIMER BREAK
SYSCFG CCMSRAM WRP
DBGMCU TRACE Pin Assignment
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB1 GRP2 STOP IP
DBGMCU APB2 GRP1 STOP IP
VREFBUF VOLTAGE
FLASH LATENCY
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
VREFBUF
FLASH
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM

Modules
TIM
STM32G4xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Private Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros

Detailed Description

TIM HAL module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Clear Input Source
TIM DMA Base Address
TIM Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Update Interrupt Flag Remap
TIM Clock Division
TIM Output Compare State
TIM Auto-Reload Preload
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Encoder Input Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
CCx DMA request selection
TIM Flag Definition
TIM Channel
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input Enable
TIM Break Input Polarity
TIM Break Input Alternate Function Mode
TIM Break input 2 Enable
TIM Break Input 2 Polarity
TIM Break2 Input Alternate Function Mode
TIM Automatic Output Enable
TIM Group Channel 5 and Channel 1, 2 or 3
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Output Compare and PWM Modes
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
TIM Break System
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

TIM Time Base functions

Time Base functions.

TIM Output Compare functions

TIM Output Compare functions.

TIM PWM functions

TIM PWM functions.

TIM Input Capture functions

TIM Input Capture functions.

TIM One Pulse functions

TIM One Pulse functions.

TIM Encoder functions

TIM Encoder functions.

TIM IRQ handler management

TIM IRQ handler management.

TIM Peripheral Control functions

TIM Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

TIM Peripheral State functions

TIM Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM

Modules
TIM
STM32G4xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Break2 Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode

Legacy definitions for compatibility purpose.

Output Configuration Polarity
Output Configuration Idle State
GROUPCH5
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Trigger Output 2
Slave Mode
SMS Preload Source
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
External Trigger Source TIM1
External Trigger Source TIM2
External Trigger Source TIM3
External Trigger Source TIM4
External Trigger Source TIM8
break polarity
break filter
BREAK2 POLARITY
BREAK2 FILTER
OSSI
OSSR
BREAK INPUT
BKIN SOURCE
BKIN POLARITY
BREAK AF MODE
BREAK2 AF MODE
DMA Burst Base Address

Legacy definitions for compatibility purpose.

DMA Burst Length
TIM1 Timer Input Ch1 Remap
TIM2 Timer Input Ch1 Remap
TIM2 Timer Input Ch2 Remap
TIM2 Timer Input Ch3 Remap
TIM2 Timer Input Ch4 Remap
TIM3 Timer Input Ch1 Remap
TIM3 Timer Input Ch2 Remap
TIM3 Timer Input Ch3 Remap
TIM4 Timer Input Ch1 Remap
TIM4 Timer Input Ch2 Remap
TIM4 Timer Input Ch3 Remap
TIM4 Timer Input Ch4 Remap
TIM8 Timer Input Ch1 Remap
TIM15 Timer Input Ch1 Remap
TIM15 Timer Input Ch2 Remap
TIM16 Timer Input Ch1 Remap
TIM17 Timer Input Ch1 Remap
OCREF clear input selection
index direction selection
index positioning selection
first index selection
Pulse on compare pulse width prescaler
Clock HSE/32 request
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Encoder configuration
Timer input remapping
OCREF_Clear_Management
FLAG-Management
IT-Management
DMA Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Wed Dec 6 2023 15:11:40 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIMEx

Modules
TIMEx
STM32G4xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Private Constants
TIM Extended Exported Functions
TIM Extended Private Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros
TIM Extended Private Macros

Detailed Description

TIM Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Remapping
TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity
TIM Extended Timer input selection
TIM Extended Bitfield SMS preload enabling
TIM Extended Encoder index position
TIM Extended Encoder index direction
TIM Extended Encoder index polarity
TIM Extended Encodder index prescaler
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Exported Functions

Modules
TIM Extended Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
struct | TIMEx_EncoderIndexConfigTypeDef
TIM Encoder index configuration. More...
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART

Modules
UART
STM32G4xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros
UART Private variables

Detailed Description

HAL UART module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART State Code Definition
UART Error Definition
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Clock Prescaler
UART Advanced Feature AutoBaud Rate Mode
UART Receiver Timeout
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
UART Reception type values
UART RxEvent type values
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx

Modules
UARTEx
STM32G4xx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Constants
UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
UARTEx WakeUp Address Length
UARTEx FIFO mode

UART FIFO mode.

UARTEx TXFIFO threshold level

UART TXFIFO threshold level.

UARTEx RXFIFO threshold level

UART RXFIFO threshold level.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

IO operation functions

Extended functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD

Modules
UCPD
STM32G4xx_LL_Driver

Modules

UCPD Private Constants
UCPD Private Macros
UCPD Exported Init structure
UCPD Exported Constants
UCPD Exported Macros
UCPD Exported Functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Configuration

Modules
Configuration
UCPD Exported Functions

Modules

CFG1 register
CFG2 register
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Exported Init structure

Data Structures
UCPD Exported Init structure
UCPD

Data Structures

struct LL_UCPD_InitTypeDef
UCPD Init structures definition. More...
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Exported Constants

Modules
UCPD Exported Constants
UCPD

Modules

Get Flags Defines

Flags defines which can be used with LL_ucpd_ReadReg function.

IT Defines

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions.

Ordered sets value

definition of the usual Ordered sets

Role Mode
Resistor value
ordered set configuration
CCx event
prescaler for UCPDCLK
CC pin enable
CC pin selection
Receiver mode
Type of Tx packet
Rx ordered set code detected
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Exported Functions

Modules
UCPD Exported Functions
UCPD

Modules

Configuration
CR register
Interrupt Management
Interrupt Clear
FLAG Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UCPD Exported Macros

Modules
UCPD Exported Macros
UCPD

Modules

Common Write and read registers Macros
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART

Modules
USART
STM32G4xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Definition
USART Number of Stop Bits
USART Parity
USART Mode
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Clock Prescaler
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Wed Dec 6 2023 15:11:35 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART

Modules
USART
STM32G4xx_LL_Driver

Modules

USART Private Variables
USART Private Constants
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

FIFO Threshold
Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to SPI Slave feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx

Modules
USARTEx
STM32G4xx_HAL_Driver

USART Extended HAL module driver. More...

Modules

USARTEx Private Constants
USARTEx Private Functions
USARTEx Exported Functions
USARTEx Exported Constants
USARTEx Private Macros

Detailed Description

USART Extended HAL module driver.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
USARTEx Slave Select Management
USARTEx Synchronous Slave mode enable

USART SLAVE mode.

USARTEx FIFO mode

USART FIFO mode.

USARTEx TXFIFO threshold level

USART TXFIFO level.

USARTEx RXFIFO threshold level

USART RXFIFO level.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: USARTEx Exported Functions

Modules
USARTEx Exported Functions
USARTEx

Modules

IO operation functions

Extended USART Transmit/Receive functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS

Modules
UTILS
STM32G4xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
PACKAGE TYPE
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG

Modules
WWDG
STM32G4xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Generated on Wed Dec 6 2023 15:11:36 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG

Modules
WWDG
STM32G4xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
Generated on Wed Dec 6 2023 15:11:41 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32G4xx_HAL_Driver
    • HAL
      • HAL Exported Variables
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
        • HAL Debug functions
        • HAL SYSCFG configuration functions
        • HAL Exported Variables
      • HAL Exported Constants
        • Tick Frequency
        • SYSCFG Exported Constants
          • Boot Mode
          • FPU Interrupts
          • CCM Write protection
          • VREFBUF Voltage Scale
          • VREFBUF High Impedance
          • Flags
          • Fast-mode Plus on GPIO
      • DBGMCU Exported Macros
      • SYSCFG Exported Macros
      • SYSCFG Private Macros
      • HAL Private Macros
    • ADC
      • ADC Private Constants
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • ADC Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Private Functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC common - Clock source
        • ADC instance - Resolution
        • ADC conversion data alignment
        • ADC sequencer scan mode
        • ADC group regular trigger source
        • ADC group regular trigger edge (when external trigger is selected)
        • ADC group regular sampling mode
        • ADC sequencer end of unitary conversion or sequence conversions
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer ranks
        • Channel - Sampling time
        • ADC instance - Channel number
        • Analog watchdog - ADC analog watchdog (AWD) number
        • ADC analog watchdog (AWD) filtering configuration
        • ADC analog watchdog (AWD) mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Oversampling - Discontinuous mode
        • Oversampling - Oversampling scope for ADC group regular
        • ADC Event type
        • ADC interrupts definition
        • ADC flags definition
      • ADC Private Macros
      • ADC Exported Macros
        • HAL ADC macro to manage HAL ADC handle, IT and flags.
        • HAL ADC helper macro
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • ADC Extended Peripheral Control functions
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC group injected trigger source
        • ADC group injected trigger edge (when external trigger is selected)
        • Channel - Single or differential ending
        • ADC instance - Offset number
        • ADC Extended Offset Sign
        • ADC group injected - Sequencer ranks
        • Multimode - Mode
          • Multimode - DMA transfer mode depending on ADC resolution
          • Multimode - Delay between two sampling phases
        • ADC instance - Groups
        • ADCx CFGR fields
        • ADCx SMPR1 fields
        • ADCx CFGR sub fields
      • ADC Extended Exported Macros
      • ADC Extended Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Error Code
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP output Polarity
        • COMP blanking source
        • COMP Output Level
        • COMP output to EXTI
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP private macros to get EXTI line associated with comparators
        • COMP private macros to check input parameters
    • CORDIC
      • CORDIC Private Functions
      • CORDIC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Callback functions
        • IRQ handler management
        • Peripheral State functions
      • CORDIC Exported Types
      • CORDIC Exported Constants
        • CORDIC Error code
        • CORDIC Function
        • CORDIC Precision in Cycles Number
        • CORDIC Scaling factor
        • CORDIC Interrupts Enable bit
        • DMA Read Request Enable bit
        • DMA Write Request Enable bit
        • CORDIC Number of 32-bit write required for one calculation
        • CORDIC Number of 32-bit read required after one calculation
        • CORDIC input data size
        • CORDIC Results Size
        • CORDIC status flags
        • CORDIC DMA direction
      • CORDIC Exported Macros
      • CORDIC Private Macros
    • CORTEX
      • CORTEX Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX SysTick clock source
        • CORTEX MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • CORTEX MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX Exported Functions
        • Initialization and Configuration functions
        • Peripheral Control functions
      • CORTEX Private Macros
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the peripheral
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
      • CRC Exported Macros
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • Extended Initialization/de-initialization functions
      • CRC Extended Exported Constants
        • Input Data Inversion Modes
        • Output Data Inversion Modes
      • CRC Extended Exported Macros
      • CRC Extended Private Macros
    • DAC
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC trigger selection
        • DAC output buffer
        • DAC Channel selection
        • DAC data alignment
        • DAC flags definition
        • DAC IT definition
        • DAC ConnectOnChipPeripheral
        • DAC User Trimming
        • DAC power mode
        • DAC high frequency interface mode
      • DAC Exported Macros
      • DAC Private Macros
      • DAC Private Functions
      • DAC Private Constants
    • DACEx
      • DACEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • DACEx private functions
      • DACEx Exported Constants
        • DACEx lfsrunmask triangle amplitude
        • DAC Sawtooth polarity mode
      • DACEx Private Macros
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA request
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • DMAEx
      • DMAEx Exported Functions
        • DMAEx Extended features functions
      • DMAEx Exported Types
      • DMAEx Exported Constants
        • DMAMUX SyncSignalID selection
        • DMAMUX SyncPolarity selection
        • DMAMUX SignalGeneratorID selection
        • DMAMUX RequestGeneneratorPolarity selection
      • DMAEx Private Macros
    • EXTI
      • EXTI Private Constants
      • EXTI Exported Types
      • EXTI Exported Constants
        • EXTI Line
        • EXTI Mode
        • EXTI Trigger
        • EXTI GPIOSel
      • EXTI Exported Macros
      • EXTI Private Macros
      • EXTI Exported Functions
        • Configuration functions
        • IO operation functions
    • FDCAN
      • FDCAN Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • Control functions
        • Interrupts management
        • Callback functions
        • Peripheral State functions
      • FDCAN Private Functions
      • FDCAN Exported Types
      • FDCAN Exported Constants
        • HAL FDCAN Error Code
        • FDCAN Frame Format
        • FDCAN Operating Mode
        • FDCAN Clock Divider
        • FDCAN Tx FIFO/Queue Mode
        • FDCAN ID Type
        • FDCAN Frame Type
        • FDCAN Data Length Code
        • FDCAN Error State Indicator
        • FDCAN Bit Rate Switching
        • FDCAN format
        • FDCAN Event FIFO control
        • FDCAN Filter Type
        • FDCAN Filter Configuration
        • FDCAN Tx Location
        • FDCAN Rx Location
        • FDCAN Event Type
        • FDCAN High Priority Message Storage
        • FDCAN protocol error code
        • FDCAN communication state
        • FDCAN FIFO operation mode
        • FDCAN non-matching frames
        • FDCAN reject remote frames
        • FDCAN interrupt line
        • FDCAN timestamp
        • FDCAN timestamp prescaler
        • FDCAN timeout operation
        • Interrupt masks
        • FDCAN Flags
        • FDCAN Interrupts
          • FDCAN Tx Interrupts
          • FDCAN Rx Interrupts
          • FDCAN Counter Interrupts
          • FDCAN Tx Event FIFO Interrupts
          • FDCAN Rx FIFO 0 Interrupts
          • FDCAN Rx FIFO 1 Interrupts
          • FDCAN Error Interrupts
          • FDCAN Error Status Interrupts
        • FDCAN Interrupts List
        • FDCAN Interrupts Group
      • FDCAN Exported Macros
      • FDCAN Private Variables
      • FDCAN Private Constants
      • FDCAN Private Macros
      • FDCAN_Private_Functions_Prototypes
    • FLASH
      • FLASH Private Constants
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error
        • FLASH Erase Type
        • FLASH Banks
        • FLASH Program Type
        • FLASH Option Bytes Type
        • FLASH WRP Area
        • FLASH Boot Lock
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes User Type
        • FLASH Option Bytes User BOR Level
        • FLASH Option Bytes User Reset On Stop
        • FLASH Option Bytes User Reset On Standby
        • FLASH Option Bytes User Reset On Shutdown
        • FLASH Option Bytes User IWDG Type
        • FLASH Option Bytes User IWDG Mode On Stop
        • FLASH Option Bytes User IWDG Mode On Standby
        • FLASH Option Bytes User WWDG Type
        • FLASH Option Bytes User BOOT1 Type
        • FLASH Option Bytes User SRAM Parity Check Type
        • FLASH Option Bytes User CCMSRAM Erase On Reset Type
        • FLASH Option Bytes User Software BOOT0
        • FLASH Option Bytes User nBOOT0 option bit
        • FLASH Option Bytes User NRST mode bit
        • FLASH Option Bytes User internal reset holder bit
        • FLASH Option Bytes PCROP On RDP Level Type
        • FLASH Latency
        • FLASH Keys
        • FLASH Flags Definition
        • FLASH Interrupts Definition
      • FLASH Exported Macros
      • FLASH Interrupts Macros
      • FLASH Exported Variables
      • FLASH Private Macros
    • FLASHEx
      • FLASHEx Private Functions
      • FLASHEx Exported Functions
        • Extended IO operation functions
    • FLASH_RAMFUNC
      • FLASH_RAMFUNC Exported Functions
        • Peripheral features functions
    • FMAC
      • FMAC Private Constants
      • FMAC Private Macros
      • FMAC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Callback functions
        • IRQ handler management
        • Peripheral State and Error functions
      • FMAC Private Functions
      • FMAC Exported Types
      • FMAC Exported Constants
        • FMAC Error code
        • FMAC Functions
        • FMAC Data Buffer Threshold
        • FMAC Buffer Access
        • FMAC Clip State
        • FMAC status flags
        • FMAC Interrupts Enable bit
      • FMAC Exported variables
      • FMAC Exported Macros
    • GPIO
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins
        • GPIO mode
        • GPIO speed
        • GPIO pull
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
    • GPIOEx
      • GPIOEx Exported Constants
        • GPIOEx Alternate function selection
      • GPIOEx Exported Macros
        • GPIOEx Get Port Index
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction Master Point of View
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Filter Mode Functions
        • WakeUp Mode Functions
        • Fast Mode Plus Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
      • I2C Extended Exported Macros
      • I2C Extended Private Constants
      • I2C Extended Private Macros
      • I2C Extended Private Functions
    • I2S
      • I2S Private Functions
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S MCLK Output
        • I2S Audio Frequency
        • I2S Clock Polarity
        • I2S Interrupts Definition
        • I2S Flags Definition
      • I2S Exported Macros
      • I2S Private Macros
    • IRDA
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA State Code Definition
        • IRDA Error Code Definition
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA Clock Prescaler
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
    • IRDAEx
      • IRDAEx Extended Exported Constants
        • IRDAEx Word Length
      • IRDAEx Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Private Functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Types
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
    • OPAMP
      • OPAMP Private Define
      • OPAMP Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • Peripheral State functions
      • OPAMP Exported Types
      • OPAMP Exported Constants
        • OPAMP Mode
        • OPAMP Non Inverting Input
        • OPAMP Inverting Input
        • OPAMP Timer Controlled Mux mode
        • OPAMP Non Inverting Input Secondary
        • OPAMP Inverting Input Secondary
        • OPAMP Pga Connect
        • OPAMP Pga Gain
        • OPAMP PowerMode
        • OPAMP User Trimming
        • OPAMP Factory Trimming
        • OPAMP VREF
      • OPAMP Private Constants
        • OPAMP Input
      • OPAMP Private Macros
      • OPAMP Exported Macros
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG PCD Callback ID enumeration definition
          • HAL USB OTG PCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • PCD Error Code definition
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
        • PCD EP0 MPS
        • PCD ENDP
        • PCD Endpoint Kind
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PWR
      • PWR Private Defines
        • PWR PVD Mode Mask
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • Programmable Voltage Detection levels
        • PWR PVD interrupt and event mode
        • PWR regulator mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR PVD external interrupt line
        • PWR PVD event line
      • PWR Exported Macros
      • PWR Private Macros
    • PWREx
      • PWR Extended Private Defines
        • PWR PVM Mode Mask
        • PWR Extended Flag Setting Time Out Value
      • PWR Extended Exported Functions
        • Extended Peripheral Control functions
      • PWR Extended Exported Types
      • PWR Extended Exported Constants
        • Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
        • PWR wake-up pins
        • Peripheral Voltage Monitoring type
        • PWR PVM interrupt and event mode
        • PWR Regulator voltage scale
        • PWR battery charging resistor selection
        • PWR battery charging
        • GPIO bit number for I/O setting in standby/shutdown mode
        • GPIO port
        • PWR PVM external interrupts lines
        • PWR PVM event lines
        • PWR Status Flags
      • PWR Extended Exported Macros
      • PWR Extended Private Macros
    • RCC
      • RCC Private Constants
      • RCC Private Macros
      • RCC Private Functions
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Timeout Values
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • HSI48 Config
        • PLL Config
        • PLLM Clock Divider
        • PLLP Clock Divider
        • PLLQ Clock Divider
        • PLLR Clock Divider
        • PLL Clock Source
        • PLL Clock Output
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1 APB2 Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO1 Clock Source
        • MCO1 Clock Prescaler
        • Interrupts
        • Flags
        • LSE Drive Config
      • RCC Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • AHB2 Peripheral Clock Enable Disable
        • AHB3 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enabled or Disabled Status
        • AHB2 Peripheral Clock Enabled or Disabled Status
        • AHB3 Peripheral Clock Enabled or Disabled Status
        • APB1 Peripheral Clock Enabled or Disabled Status
        • APB2 Peripheral Clock Enabled or Disabled Status
        • AHB1 Peripheral Force Release Reset
        • AHB2 Peripheral Force Release Reset
        • AHB3 Peripheral Force Release Reset
        • APB1 Peripheral Force Release Reset
        • APB2 Peripheral Force Release Reset
        • AHB1 Peripheral Clock Sleep Enable Disable
        • AHB2 Peripheral Clock Sleep Enable Disable
        • AHB3 Peripheral Clock Sleep Enable Disable
        • APB1 Peripheral Clock Sleep Enable Disable
        • APB2 Peripheral Clock Sleep Enable Disable
        • AHB1 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB2 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB3 Peripheral Clock Sleep Enabled or Disabled Status
        • APB1 Peripheral Clock Sleep Enabled or Disabled Status
        • APB2 Peripheral Clock Sleep Enabled or Disabled Status
        • RCC Backup Domain Reset
        • RCC RTC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Constants
      • RCCEx Private Functions
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
        • Extended Clock management functions
        • Extended Clock Recovery System Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • Low Speed Clock Source
        • Periph Clock Selection
        • USART1 Clock Source
        • USART2 Clock Source
        • USART3 Clock Source
        • UART4 Clock Source
        • LPUART1 Clock Source
        • I2C1 Clock Source
        • I2C2 Clock Source
        • I2C3 Clock Source
        • LPTIM1 Clock Source
        • SAI1 Clock Source
        • I2S Clock Source
        • FDCAN Clock Source
        • RNG Clock Source
        • USB Clock Source
        • ADC12 Clock Source
        • RCC LSE CSS external interrupt line
        • RCCEx CRS Status
        • RCCEx CRS SynchroSource
        • RCCEx CRS SynchroDivider
        • RCCEx CRS SynchroPolarity
        • RCCEx CRS ReloadValueDefault
        • RCCEx CRS ErrorLimitDefault
        • RCCEx CRS HSI48CalibrationDefault
        • RCCEx CRS FreqErrorDirection
        • RCCEx CRS Interrupt Sources
        • RCCEx CRS Flags
      • RCCEx Exported Macros
        • Flags Interrupts Management
        • RCCEx CRS Extended Features
      • RCCEx_Private_Macros
    • RNG
      • RNG Private Constants
      • RNG Exported Types
        • RNG Init Structure definition
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
        • RNG Clock Error Detection
        • RNG Error Definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and configuration functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Macros
    • RTC
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTCEx Output Selection Definition
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output Pull-Up ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLightSaving Definitions
        • RTC StoreOperation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC AlarmDateWeekDay Definitions
        • RTC AlarmMask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
        • RTC Flags Definitions
        • RTC Clear Flags Definitions
      • RTC Exported Macros
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Exported Types
        • RTCEx Tamper structure definition
        • RTCEx Internal Tamper structure definition
      • RTCEx Exported Constants
        • RTCEx Time Stamp Edges definition
        • RTCEx TimeStamp Pin Selection
        • RTCEx Wakeup Timer Definitions
        • RTCEx Smooth calib period Definitions
        • RTCEx Smooth calib Plus pulses Definitions
        • RTCEx Calib Output selection Definitions
        • RTCEx Add 1 Second Parameter Definitions
        • RTCEx Tamper Pins Definition
        • RTCEx Internal Tamper Pins Definition
        • RTCEx Tamper Trigger
        • RTCEx Tamper MaskFlag
        • RTCEx Tamper EraseBackUp
        • RTCEx Tamper Filter
        • RTCEx Tamper Sampling Frequencies
        • RTCEx Tamper Pin Precharge Duration
        • RTCEx Tamper Pull UP
        • RTCEx Tamper TimeStamp On Tamper Detection
        • RTCEx Internal Tamper Interrupt
        • RTCEx Flags
        • RTCEx Backup Registers Definition
      • RTCEx Exported Macros
        • RTC WakeUp Timer
        • RTC Timestamp
        • RTC Calibration
        • RTCEx tamper
      • RTCEx Exported Functions
        • Extended RTC TimeStamp functions
        • Extended RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
        • Extended RTC Tamper functions
        • Extended RTC Backup register functions
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Private Functions
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
        • SAI PDM Structure definition
        • SAI Init Structure definition
        • SAI Frame Structure definition
        • SAI Slot Structure definition
        • SAI Handle Structure definition
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Block Master Clock Output
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Audio Frequency
        • SAI Block Master Clock OverSampling
        • SAI PDM Clock Enable
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI Private Macros
    • SAIEx
      • SAIEx Extended Private Defines
      • SAIEx Extended Exported Functions
        • Peripheral Control functions
      • SAIEx Exported Types
      • SAIEx Extended Private Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD State Code Definition
        • SMARTCARD Error Code Definition
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD Clock Prescaler
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Private Constants
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
        • Extended Peripheral IO operation functions
        • Extended Peripheral FIFO Control functions
      • SMARTCARD Extended Private Functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARD FIFO mode
        • SMARTCARD TXFIFO threshold level
        • SMARTCARD RXFIFO threshold level
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS ownaddress2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SMBUSEx
      • SMBUS Extended Exported Functions
        • WakeUp Mode Functions
        • Fast Mode Plus Functions
      • SMBUS Extended Exported Constants
        • SMBUS Extended Fast Mode Plus
      • SMBUS Extended Exported Macros
      • SMBUS Extended Private Constants
      • SMBUS Extended Private Macros
      • SMBUS Extended Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Private Constants
      • SPIEx Exported Functions
        • IO operation functions
    • TIM
      • TIM Exported Functions
        • TIM Time Base functions
        • TIM Output Compare functions
        • TIM PWM functions
        • TIM Input Capture functions
        • TIM One Pulse functions
        • TIM Encoder functions
        • TIM IRQ handler management
        • TIM Peripheral Control functions
        • TIM Callbacks functions
        • TIM Peripheral State functions
      • TIM Private Functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Clear Input Source
        • TIM DMA Base Address
        • TIM Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Update Interrupt Flag Remap
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Encoder Input Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • CCx DMA request selection
        • TIM Flag Definition
        • TIM Channel
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Break Input Alternate Function Mode
        • TIM Break input 2 Enable
        • TIM Break Input 2 Polarity
        • TIM Break2 Input Alternate Function Mode
        • TIM Automatic Output Enable
        • TIM Group Channel 5 and Channel 1, 2 or 3
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Output Compare and PWM Modes
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
        • TIM Break System
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
    • TIMEx
      • TIM Extended Private Constants
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIM Extended Private Functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Remapping
        • TIM Extended Break input
        • TIM Extended Break input source
        • TIM Extended Break input source enabling
        • TIM Extended Break input polarity
        • TIM Extended Timer input selection
        • TIM Extended Bitfield SMS preload enabling
        • TIM Extended Encoder index position
        • TIM Extended Encoder index direction
        • TIM Extended Encoder index polarity
        • TIM Extended Encodder index prescaler
      • TIM Extended Exported Macros
      • TIM Extended Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART State Code Definition
        • UART Error Definition
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Clock Prescaler
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver Timeout
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
        • UART Reception type values
        • UART RxEvent type values
      • UART Exported Macros
      • UART Private Macros
      • UART Private variables
    • UARTEx
      • UARTEx Private Constants
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UARTEx Word Length
        • UARTEx WakeUp Address Length
        • UARTEx FIFO mode
        • UARTEx TXFIFO threshold level
        • UARTEx RXFIFO threshold level
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Definition
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Clock Prescaler
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • USARTEx
      • USARTEx Private Constants
      • USARTEx Private Functions
      • USARTEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • USARTEx Exported Constants
        • USARTEx Word Length
        • USARTEx Slave Select Management
        • USARTEx Synchronous Slave mode enable
        • USARTEx FIFO mode
        • USARTEx TXFIFO threshold level
        • USARTEx RXFIFO threshold level
      • USARTEx Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
    • CRYP
    • CRYPEx
    • OPAMPEx
      • OPAMP Extended Exported Functions
        • Extended Input and Output operation functions
  • STM32G4xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Clock source
        • ADC common - Measurement path to internal channels
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Low power mode
        • ADC instance - Offset instance
        • ADC instance - Offset state
        • ADC instance - Offset sign
        • ADC instance - Offset saturation mode
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Sampling mode
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer of ADC conversion data
        • ADC instance - ADC sampling time common configuration
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Context queue mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Channel - Single or differential ending
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Analog watchdog - filtering config
        • Oversampling - Oversampling scope
        • Oversampling - Discontinuous mode
        • Oversampling - Ratio
        • Oversampling - Data right shift
        • Multimode - Mode
        • Multimode - DMA transfer
        • Multimode - Delay between two sampling phases
        • Multimode - ADC master or slave
        • Definitions of constants used by helper macro
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC transversal scope: oversampling
        • Configuration of ADC hierarchical scope: multimode
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • AHB2 GRP1 PERIPH
        • AHB3 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB1 GRP2 PERIPH
        • APB2 GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • AHB2
        • AHB3
        • APB1
        • APB2
    • COMP
      • COMP Private Macros
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator input - Hysteresis
        • Comparator output - Output polarity
        • Comparator output - Blanking source
        • Comparator output - Output level
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Operation on comparator instance
        • Initialization and de-initialization functions
    • CORDIC
      • CORDIC Exported Constants
        • Get Flags Defines
        • IT Defines
        • FUNCTION
        • PRECISION
        • SCALE
        • NBWRITE
        • NBREAD
        • INSIZE
        • OUTSIZE
        • DMA register data
      • CORDIC Exported Macros
        • Common Write and read registers Macros
      • CORDIC Exported Functions
        • CORDIC Configuration functions
        • IT_Management
        • DMA_Management
        • FLAG_Management
        • Data_Management
        • Initialization and de-initialization functions
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • CRS
      • CRS Exported Constants
        • Get Flags Defines
        • IT Defines
        • Synchronization Signal Divider
        • Synchronization Signal Source
        • Synchronization Signal Polarity
        • Frequency Error Direction
        • Default Values
      • CRS Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Calculate_Reload
      • CRS Exported Functions
        • Configuration
        • CRS_Management
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DAC
      • DAC Private Constants
      • DAC Private Macros
      • DAC Exported Init structure
      • DAC Exported Constants
        • DAC flags
        • DAC interruptions
        • DAC channels
        • DAC high frequency interface mode
        • DAC operating mode
        • DAC trigger source
        • DAC waveform automatic generation mode
        • DAC wave generation - Noise LFSR unmask bits
        • DAC wave generation - Triangle amplitude
        • DAC wave generation - Sawtooth polarity mode
        • DAC channel output mode
        • DAC channel output buffer
        • DAC channel output connection
        • DAC channel signed format
        • DAC channel output resolution
        • DAC registers compliant with specific purpose
        • Definitions of DAC hardware constraints delays
      • DAC Exported Macros
        • Common write and read registers macros
        • DAC helper macro
      • DAC Exported Functions
        • Configuration of DAC instance
        • Configuration of DAC channels
        • DMA Management
        • Operation on DAC channels
        • FLAG Management
        • IT management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Private Constants
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DMAMUX
      • DMAMUX Private Constants
      • DMAMUX Private Macros
      • DMAMUX Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Transfer request
        • DMAMUX Channel
        • Synchronization Signal Polarity
        • Synchronization Signal Event
        • Request Generator Channel
        • External Request Signal Generation Polarity
        • External Request Signal Generation
      • DMAMUX Exported Macros
        • Common Write and read registers macros
      • DMAMUX Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • FMAC
      • FMAC Exported Constants
        • Get Flag Defines
        • IT Defines
        • FMAC watermarks
        • FMAC functions
        • FMAC processing
      • FMAC Exported Macros
        • Common Write and read registers Macros
      • FMAC Exported Functions
        • FMAC Configuration functions
        • Reset_Management
        • DMA_Management
        • IT_Management
        • FLAG_Management
        • Data_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • LPTIM
      • LPTIM Private Functions
      • LPTIM Private Macros
      • LPTIM Exported Init structure
      • LPTIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operating Mode
        • Update Mode
        • Counter Mode
        • Output Waveform Type
        • Output Polarity
        • Prescaler Value
        • Trigger Source
        • Trigger Filter
        • Trigger Polarity
        • Clock Source
        • Clock Filter
        • Clock Polarity
        • Encoder Mode
        • Input1 Source
        • Input2 Source
      • LPTIM Exported Macros
        • Common Write and read registers Macros
      • LPTIM Exported Functions
        • Initialisation and deinitialisation functions
        • LPTIM Configuration
        • Trigger Configuration
        • Clock Configuration
        • Encoder Mode
        • FLAG Management
        • Interrupt Management
    • LPUART
      • LPUART Private Variables
      • LPUART Private Constants
      • LPUART Private Macros
      • LPUART Exported Init structures
      • LPUART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • Driver Enable Polarity
        • DMA Register Data
      • LPUART Exported Macros
        • Common Write and read registers Macros
        • Helper Macros
      • LPUART Exported Functions
        • Configuration functions
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to Driver Enable feature
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • OPAMP
      • OPAMP Private Constants
      • OPAMP Private Macros
      • OPAMP Exported Init structure
      • OPAMP Exported Constants
        • OPAMP mode calibration or functional.
        • OPAMP functional mode
        • OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
        • OPAMP input non-inverting
        • OPAMP input inverting
        • OPAMP input non-inverting secondary
        • OPAMP input inverting secondary
        • OPAMP internal output mode
        • OPAMP inputs multiplexer mode
        • OPAMP PowerMode
        • OPAMP trimming mode
        • OPAMP trimming of transistors differential pair NMOS or PMOS
        • Definitions of OPAMP hardware constraints delays
      • OPAMP Exported Macros
        • Common write and read registers macro
      • OPAMP Exported Functions
        • Configuration of OPAMP hierarchical scope: OPAMP instance
        • Configuration of OPAMP inputs
        • Configuration and operation of OPAMP trimming
        • Operation on OPAMP instance
        • Initialization and de-initialization functions
    • PWR
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • REGU VOLTAGE
        • MODE PWR
        • Peripheral voltage monitoring
        • PVDLEVEL
        • WAKEUP
        • BATT CHARG RESISTOR
        • GPIO
        • GPIO BIT
      • PWR Exported Macros
        • Common Write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
        • De-initialization function
        • Legacy functions name
    • RCC
      • RCC Private functions
      • RCC Private Variables
      • RCC Private Constants
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • LSE oscillator drive capability
        • LSCO Selection
        • System clock switch
        • System clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB high-speed prescaler (APB2)
        • MCO1 SOURCE selection
        • MCO1 prescaler
        • Peripheral clock frequency
        • Peripheral USART clock source selection
        • Peripheral UART clock source selection
        • Peripheral LPUART clock source selection
        • Peripheral I2C clock source selection
        • Peripheral LPTIM clock source selection
        • Peripheral SAI clock source selection
        • Peripheral I2S clock source selection
        • Peripheral FDCAN clock source selection
        • Peripheral RNG clock source selection
        • Peripheral USB clock source selection
        • Peripheral ADC clock source selection
        • Peripheral QUADSPI get clock source
        • Peripheral USART get clock source
        • Peripheral UART get clock source
        • Peripheral LPUART get clock source
        • Peripheral I2C get clock source
        • Peripheral LPTIM get clock source
        • Peripheral SAI get clock source
        • Peripheral I2S get clock source
        • Peripheral FDCAN get clock source
        • Peripheral RNG get clock source
        • Peripheral USB get clock source
        • Peripheral ADC get clock source
        • RTC clock source selection
        • PLL entry clock source
        • PLL division factor
        • PLL division factor (PLLR)
        • PLL division factor (PLLP)
        • PLL division factor (PLLQ)
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • HSI48
        • LSE
        • LSI
        • LSCO
        • System
        • MCO
        • Peripheral Clock Source
        • RTC
        • PLL
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • RNG
      • RNG Private Macros
      • RNG Exported Init structures
      • RNG Exported Constants
        • Clock Error Detection
        • Get Flags Defines
        • IT Defines
      • RNG Exported Macros
        • Common Write and read registers Macros
      • RNG Exported Functions
        • RNG Configuration functions
        • FLAG Management
        • IT Management
        • Data Management
        • Initialization and de-initialization functions
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • INTERNAL TAMPER
        • BACKUP
        • WAKEUP CLOCK DIV
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • Convert helper Macros
      • Date helper Macros
      • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Tamper
        • Internal Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • RTC Exported Functions
      • Configuration
      • Time
      • Date
      • ALARMA
      • ALARMB
      • Timestamp
      • Tamper
      • Internal Tamper
      • Wakeup
      • Backup_Registers
      • Calibration
      • FLAG_Management
      • IT_Management
      • Initialization and de-initialization functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Serial Protocol
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
        • CRC Length
        • RX FIFO Threshold
        • RX FIFO Level
        • TX FIFO Level
        • DMA Parity
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • I2S
      • I2S Private Constants
      • I2S Private Macros
      • I2S Exported Init structure
      • I2S Exported Constants
        • Get Flags Defines
        • IT Defines
        • Data format
        • Clock Polarity
        • I2s Standard
        • Operation Mode
        • Prescaler Factor
        • MCLK Output
        • Audio Frequency
      • I2S Exported Macros
        • Common Write and read registers Macros
      • I2S Exported Functions
        • Configuration
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • SYSCFG REMAP
        • SYSCFG BANK MODE
        • SYSCFG I2C FASTMODEPLUS
        • SYSCFG EXTI PORT
        • SYSCFG EXTI LINE
        • SYSCFG TIMER BREAK
        • SYSCFG CCMSRAM WRP
        • DBGMCU TRACE Pin Assignment
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB1 GRP2 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • VREFBUF VOLTAGE
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • VREFBUF
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Break2 Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • GROUPCH5
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Trigger Output 2
        • Slave Mode
        • SMS Preload Source
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • External Trigger Source TIM1
        • External Trigger Source TIM2
        • External Trigger Source TIM3
        • External Trigger Source TIM4
        • External Trigger Source TIM8
        • break polarity
        • break filter
        • BREAK2 POLARITY
        • BREAK2 FILTER
        • OSSI
        • OSSR
        • BREAK INPUT
        • BKIN SOURCE
        • BKIN POLARITY
        • BREAK AF MODE
        • BREAK2 AF MODE
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM1 Timer Input Ch1 Remap
        • TIM2 Timer Input Ch1 Remap
        • TIM2 Timer Input Ch2 Remap
        • TIM2 Timer Input Ch3 Remap
        • TIM2 Timer Input Ch4 Remap
        • TIM3 Timer Input Ch1 Remap
        • TIM3 Timer Input Ch2 Remap
        • TIM3 Timer Input Ch3 Remap
        • TIM4 Timer Input Ch1 Remap
        • TIM4 Timer Input Ch2 Remap
        • TIM4 Timer Input Ch3 Remap
        • TIM4 Timer Input Ch4 Remap
        • TIM8 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch2 Remap
        • TIM16 Timer Input Ch1 Remap
        • TIM17 Timer Input Ch1 Remap
        • OCREF clear input selection
        • index direction selection
        • index positioning selection
        • first index selection
        • Pulse on compare pulse width prescaler
        • Clock HSE/32 request
      • TIM Exported Macros
        • Common Write and read registers Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Encoder configuration
        • Timer input remapping
        • OCREF_Clear_Management
        • FLAG-Management
        • IT-Management
        • DMA Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • UCPD
      • UCPD Private Constants
      • UCPD Private Macros
      • UCPD Exported Init structure
      • UCPD Exported Constants
        • Get Flags Defines
        • IT Defines
        • Ordered sets value
        • Role Mode
        • Resistor value
        • ordered set configuration
        • CCx event
        • prescaler for UCPDCLK
        • CC pin enable
        • CC pin selection
        • Receiver mode
        • Type of Tx packet
        • Rx ordered set code detected
      • UCPD Exported Macros
        • Common Write and read registers Macros
      • UCPD Exported Functions
        • Configuration
          • CFG1 register
          • CFG2 register
        • CR register
        • Interrupt Management
        • Interrupt Clear
        • FLAG Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • USART
      • USART Private Variables
      • USART Private Constants
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to SPI Slave feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
        • PACKAGE TYPE
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
Generated on Wed Dec 6 2023 15:11:43 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal.c
00004   * @author  MCD Application Team
00005   * @brief   HAL module driver.
00006   *          This is the common part of the HAL initialization
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * Copyright (c) 2019 STMicroelectronics.
00011   * All rights reserved.
00012   *
00013   * This software is licensed under terms that can be found in the LICENSE file
00014   * in the root directory of this software component.
00015   * If no LICENSE file comes with this software, it is provided AS-IS.
00016   *
00017   ******************************************************************************
00018   @verbatim
00019   ==============================================================================
00020                      ##### How to use this driver #####
00021   ==============================================================================
00022     [..]
00023     The common HAL driver contains a set of generic and common APIs that can be
00024     used by the PPP peripheral drivers and the user to start using the HAL.
00025     [..]
00026     The HAL contains two APIs' categories:
00027          (+) Common HAL APIs
00028          (+) Services HAL APIs
00029
00030   @endverbatim
00031   ******************************************************************************
00032   */
00033
00034 /* Includes ------------------------------------------------------------------*/
00035 #include "stm32g4xx_hal.h"
00036
00037 /** @addtogroup STM32G4xx_HAL_Driver
00038   * @{
00039   */
00040
00041 /** @defgroup HAL HAL
00042   * @brief HAL module driver
00043   * @{
00044   */
00045
00046 #ifdef HAL_MODULE_ENABLED
00047
00048 /* Private typedef -----------------------------------------------------------*/
00049 /* Private define ------------------------------------------------------------*/
00050 /**
00051   * @brief STM32G4xx HAL Driver version number V1.2.2
00052   */
00053 #define __STM32G4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
00054 #define __STM32G4xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
00055 #define __STM32G4xx_HAL_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
00056 #define __STM32G4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
00057 #define __STM32G4xx_HAL_VERSION         ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
00058                                          |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
00059                                          |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\
00060                                          |(__STM32G4xx_HAL_VERSION_RC))
00061
00062 #if defined(VREFBUF)
00063 #define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms */
00064 #endif /* VREFBUF */
00065
00066 /* ------------ SYSCFG registers bit address in the alias region ------------ */
00067 #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
00068 /* ---  MEMRMP Register ---*/
00069 /* Alias word address of FB_MODE bit */
00070 #define MEMRMP_OFFSET           SYSCFG_OFFSET
00071 #define FB_MODE_BitNumber       ((uint8_t)0x8)
00072 #define FB_MODE_BB              (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
00073
00074 /* --- GPC Register ---*/
00075 /* Alias word address of CCMER bit */
00076 #define SCSR_OFFSET             (SYSCFG_OFFSET + 0x18)
00077 #define CCMER_BitNumber         ((uint8_t)0x0)
00078 #define SCSR_CCMER_BB           (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
00079
00080 /* Private macro -------------------------------------------------------------*/
00081 /* Exported variables ---------------------------------------------------------*/
00082 /** @defgroup HAL_Exported_Variables HAL Exported Variables
00083   * @{
00084   */
00085 __IO uint32_t uwTick;
00086 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
00087 uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
00088 /**
00089   * @}
00090   */
00091
00092 /* Private function prototypes -----------------------------------------------*/
00093 /* Exported functions --------------------------------------------------------*/
00094
00095 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00096   * @{
00097   */
00098
00099 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00100   *  @brief    HAL Initialization and de-initialization functions
00101   *
00102 @verbatim
00103  ===============================================================================
00104               ##### Initialization and Configuration functions #####
00105  ===============================================================================
00106     [..]  This section provides functions allowing to:
00107       (+) Initialize the Flash interface the NVIC allocation and initial time base
00108           clock configuration.
00109       (+) De-Initialize common part of the HAL.
00110       (+) Configure the time base source to have 1ms time base with a dedicated
00111           Tick interrupt priority.
00112         (++) SysTick timer is used by default as source of time base, but user
00113              can eventually implement his proper time base source (a general purpose
00114              timer for example or other time source), keeping in mind that Time base
00115              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00116              handled in milliseconds basis.
00117         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00118              at the beginning of the program after reset by HAL_Init() or at any time
00119              when clock is configured, by HAL_RCC_ClockConfig().
00120         (++) Source of time base is configured  to generate interrupts at regular
00121              time intervals. Care must be taken if HAL_Delay() is called from a
00122              peripheral ISR process, the Tick interrupt line must have higher priority
00123             (numerically lower) than the peripheral interrupt. Otherwise the caller
00124             ISR process will be blocked.
00125        (++) functions affecting time base configurations are declared as __weak
00126              to make  override possible  in case of other  implementations in user file.
00127 @endverbatim
00128   * @{
00129   */
00130
00131 /**
00132   * @brief  This function is used to configure the Flash prefetch, the Instruction and Data caches,
00133   *         the time base source, NVIC and any required global low level hardware
00134   *         by calling the HAL_MspInit() callback function to be optionally defined in user file
00135   *         stm32g4xx_hal_msp.c.
00136   *
00137   * @note   HAL_Init() function is called at the beginning of program after reset and before
00138   *         the clock configuration.
00139   *
00140   * @note   In the default implementation the System Timer (Systick) is used as source of time base.
00141   *         The Systick configuration is based on HSI clock, as HSI is the clock
00142   *         used after a system Reset and the NVIC configuration is set to Priority group 4.
00143   *         Once done, time base tick starts incrementing: the tick variable counter is incremented
00144   *         each 1ms in the SysTick_Handler() interrupt handler.
00145   *
00146   * @retval HAL status
00147   */
00148 HAL_StatusTypeDef HAL_Init(void)
00149 {
00150   HAL_StatusTypeDef  status = HAL_OK;
00151   /* Configure Flash prefetch, Instruction cache, Data cache */
00152   /* Default configuration at reset is:                      */
00153   /* - Prefetch disabled                                     */
00154   /* - Instruction cache enabled                             */
00155   /* - Data cache enabled                                    */
00156 #if (INSTRUCTION_CACHE_ENABLE == 0U)
00157   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00158 #endif /* INSTRUCTION_CACHE_ENABLE */
00159
00160 #if (DATA_CACHE_ENABLE == 0U)
00161   __HAL_FLASH_DATA_CACHE_DISABLE();
00162 #endif /* DATA_CACHE_ENABLE */
00163
00164 #if (PREFETCH_ENABLE != 0U)
00165   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00166 #endif /* PREFETCH_ENABLE */
00167
00168   /* Set Interrupt Group Priority */
00169   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00170
00171   /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00172   if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
00173   {
00174     status = HAL_ERROR;
00175   }
00176   else
00177   {
00178     /* Init the low level hardware */
00179     HAL_MspInit();
00180   }
00181
00182   /* Return function status */
00183   return status;
00184
00185 }
00186
00187 /**
00188   * @brief  This function de-initializes common part of the HAL and stops the source of time base.
00189   * @note   This function is optional.
00190   * @retval HAL status
00191   */
00192 HAL_StatusTypeDef HAL_DeInit(void)
00193 {
00194   /* Reset of all peripherals */
00195   __HAL_RCC_APB1_FORCE_RESET();
00196   __HAL_RCC_APB1_RELEASE_RESET();
00197
00198   __HAL_RCC_APB2_FORCE_RESET();
00199   __HAL_RCC_APB2_RELEASE_RESET();
00200
00201   __HAL_RCC_AHB1_FORCE_RESET();
00202   __HAL_RCC_AHB1_RELEASE_RESET();
00203
00204   __HAL_RCC_AHB2_FORCE_RESET();
00205   __HAL_RCC_AHB2_RELEASE_RESET();
00206
00207   __HAL_RCC_AHB3_FORCE_RESET();
00208   __HAL_RCC_AHB3_RELEASE_RESET();
00209
00210   /* De-Init the low level hardware */
00211   HAL_MspDeInit();
00212
00213   /* Return function status */
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Initialize the MSP.
00219   * @retval None
00220   */
00221 __weak void HAL_MspInit(void)
00222 {
00223   /* NOTE : This function should not be modified, when the callback is needed,
00224             the HAL_MspInit could be implemented in the user file
00225    */
00226 }
00227
00228 /**
00229   * @brief  DeInitializes the MSP.
00230   * @retval None
00231   */
00232 __weak void HAL_MspDeInit(void)
00233 {
00234   /* NOTE : This function should not be modified, when the callback is needed,
00235             the HAL_MspDeInit could be implemented in the user file
00236    */
00237 }
00238
00239 /**
00240   * @brief This function configures the source of the time base:
00241   *        The time source is configured to have 1ms time base with a dedicated
00242   *        Tick interrupt priority.
00243   * @note This function is called  automatically at the beginning of program after
00244   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00245   * @note In the default implementation, SysTick timer is the source of time base.
00246   *       It is used to generate interrupts at regular time intervals.
00247   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00248   *       The SysTick interrupt must have higher priority (numerically lower)
00249   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00250   *       The function is declared as __weak  to be overwritten  in case of other
00251   *       implementation  in user file.
00252   * @param TickPriority: Tick interrupt priority.
00253   * @retval HAL status
00254   */
00255 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00256 {
00257   HAL_StatusTypeDef  status = HAL_OK;
00258
00259   if (uwTickFreq != 0U)
00260   {
00261     /* Configure the SysTick to have interrupt in 1ms time basis*/
00262     if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
00263     {
00264       /* Configure the SysTick IRQ priority */
00265       if (TickPriority < (1UL << __NVIC_PRIO_BITS))
00266       {
00267         HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
00268         uwTickPrio = TickPriority;
00269       }
00270       else
00271       {
00272         status = HAL_ERROR;
00273       }
00274     }
00275     else
00276     {
00277       status = HAL_ERROR;
00278     }
00279   }
00280   else
00281   {
00282     status = HAL_ERROR;
00283   }
00284
00285   /* Return function status */
00286   return status;
00287 }
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00294   *  @brief    HAL Control functions
00295   *
00296 @verbatim
00297  ===============================================================================
00298                       ##### HAL Control functions #####
00299  ===============================================================================
00300     [..]  This section provides functions allowing to:
00301       (+) Provide a tick value in millisecond
00302       (+) Provide a blocking delay in millisecond
00303       (+) Suspend the time base source interrupt
00304       (+) Resume the time base source interrupt
00305       (+) Get the HAL API driver version
00306       (+) Get the device identifier
00307       (+) Get the device revision identifier
00308
00309 @endverbatim
00310   * @{
00311   */
00312
00313 /**
00314   * @brief This function is called to increment a global variable "uwTick"
00315   *        used as application time base.
00316   * @note In the default implementation, this variable is incremented each 1ms
00317   *       in SysTick ISR.
00318   * @note This function is declared as __weak to be overwritten in case of other
00319   *      implementations in user file.
00320   * @retval None
00321   */
00322 __weak void HAL_IncTick(void)
00323 {
00324   uwTick += uwTickFreq;
00325 }
00326
00327 /**
00328   * @brief Provides a tick value in millisecond.
00329   * @note This function is declared as __weak to be overwritten in case of other
00330   *       implementations in user file.
00331   * @retval tick value
00332   */
00333 __weak uint32_t HAL_GetTick(void)
00334 {
00335   return uwTick;
00336 }
00337
00338 /**
00339   * @brief This function returns a tick priority.
00340   * @retval tick priority
00341   */
00342 uint32_t HAL_GetTickPrio(void)
00343 {
00344   return uwTickPrio;
00345 }
00346
00347 /**
00348   * @brief Set new tick Freq.
00349   * @retval status
00350   */
00351 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
00352 {
00353   HAL_StatusTypeDef status  = HAL_OK;
00354   uint32_t prevTickFreq;
00355
00356   assert_param(IS_TICKFREQ(Freq));
00357
00358   if (uwTickFreq != Freq)
00359   {
00360     /* Back up uwTickFreq frequency */
00361     prevTickFreq = uwTickFreq;
00362
00363     /* Update uwTickFreq global variable used by HAL_InitTick() */
00364     uwTickFreq = Freq;
00365
00366     /* Apply the new tick Freq  */
00367     status = HAL_InitTick(uwTickPrio);
00368
00369     if (status != HAL_OK)
00370     {
00371       /* Restore previous tick frequency */
00372       uwTickFreq = prevTickFreq;
00373     }
00374   }
00375
00376   return status;
00377 }
00378
00379 /**
00380   * @brief Returns tick frequency.
00381   * @retval Tick frequency.
00382   *         Value of @ref HAL_TickFreqTypeDef.
00383   */
00384 uint32_t HAL_GetTickFreq(void)
00385 {
00386   return uwTickFreq;
00387 }
00388
00389 /**
00390   * @brief This function provides minimum delay (in milliseconds) based
00391   *        on variable incremented.
00392   * @note In the default implementation , SysTick timer is the source of time base.
00393   *       It is used to generate interrupts at regular time intervals where uwTick
00394   *       is incremented.
00395   * @note This function is declared as __weak to be overwritten in case of other
00396   *       implementations in user file.
00397   * @param Delay specifies the delay time length, in milliseconds.
00398   * @retval None
00399   */
00400 __weak void HAL_Delay(uint32_t Delay)
00401 {
00402   uint32_t tickstart = HAL_GetTick();
00403   uint32_t wait = Delay;
00404
00405   /* Add a freq to guarantee minimum wait */
00406   if (wait < HAL_MAX_DELAY)
00407   {
00408     wait += (uint32_t)(uwTickFreq);
00409   }
00410
00411   while ((HAL_GetTick() - tickstart) < wait)
00412   {
00413   }
00414 }
00415
00416 /**
00417   * @brief Suspends Tick increment.
00418   * @note In the default implementation , SysTick timer is the source of time base. It is
00419   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00420   *       is called, the SysTick interrupt will be disabled and so Tick increment
00421   *       is suspended.
00422   * @note This function is declared as __weak to be overwritten in case of other
00423   *       implementations in user file.
00424   * @retval None
00425   */
00426 __weak void HAL_SuspendTick(void)
00427 {
00428   /* Disable SysTick Interrupt */
00429   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00430 }
00431
00432 /**
00433   * @brief Resume Tick increment.
00434   * @note In the default implementation , SysTick timer is the source of time base. It is
00435   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00436   *       is called, the SysTick interrupt will be enabled and so Tick increment
00437   *       is resumed.
00438   * @note This function is declared as __weak to be overwritten in case of other
00439   *       implementations in user file.
00440   * @retval None
00441   */
00442 __weak void HAL_ResumeTick(void)
00443 {
00444   /* Enable SysTick Interrupt */
00445   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00446 }
00447
00448 /**
00449   * @brief  Returns the HAL revision.
00450   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00451   */
00452 uint32_t HAL_GetHalVersion(void)
00453 {
00454   return __STM32G4xx_HAL_VERSION;
00455 }
00456
00457 /**
00458   * @brief  Returns the device revision identifier.
00459   * @retval Device revision identifier
00460   */
00461 uint32_t HAL_GetREVID(void)
00462 {
00463   return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
00464 }
00465
00466 /**
00467   * @brief  Returns the device identifier.
00468   * @retval Device identifier
00469   */
00470 uint32_t HAL_GetDEVID(void)
00471 {
00472   return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
00473 }
00474
00475 /**
00476   * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
00477   * @retval Device identifier
00478   */
00479 uint32_t HAL_GetUIDw0(void)
00480 {
00481   return (READ_REG(*((uint32_t *)UID_BASE)));
00482 }
00483
00484 /**
00485   * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
00486   * @retval Device identifier
00487   */
00488 uint32_t HAL_GetUIDw1(void)
00489 {
00490   return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00491 }
00492
00493 /**
00494   * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
00495   * @retval Device identifier
00496   */
00497 uint32_t HAL_GetUIDw2(void)
00498 {
00499   return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00500 }
00501
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
00507   *  @brief    HAL Debug functions
00508   *
00509 @verbatim
00510  ===============================================================================
00511                       ##### HAL Debug functions #####
00512  ===============================================================================
00513     [..]  This section provides functions allowing to:
00514       (+) Enable/Disable Debug module during SLEEP mode
00515       (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
00516       (+) Enable/Disable Debug module during STANDBY mode
00517
00518 @endverbatim
00519   * @{
00520   */
00521
00522 /**
00523   * @brief  Enable the Debug Module during SLEEP mode.
00524   * @retval None
00525   */
00526 void HAL_DBGMCU_EnableDBGSleepMode(void)
00527 {
00528   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00529 }
00530
00531 /**
00532   * @brief  Disable the Debug Module during SLEEP mode.
00533   * @retval None
00534   */
00535 void HAL_DBGMCU_DisableDBGSleepMode(void)
00536 {
00537   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00538 }
00539
00540 /**
00541   * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
00542   * @retval None
00543   */
00544 void HAL_DBGMCU_EnableDBGStopMode(void)
00545 {
00546   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00547 }
00548
00549 /**
00550   * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
00551   * @retval None
00552   */
00553 void HAL_DBGMCU_DisableDBGStopMode(void)
00554 {
00555   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00556 }
00557
00558 /**
00559   * @brief  Enable the Debug Module during STANDBY mode.
00560   * @retval None
00561   */
00562 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00563 {
00564   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00565 }
00566
00567 /**
00568   * @brief  Disable the Debug Module during STANDBY mode.
00569   * @retval None
00570   */
00571 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00572 {
00573   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00574 }
00575
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
00581   *  @brief    HAL SYSCFG configuration functions
00582   *
00583 @verbatim
00584  ===============================================================================
00585                       ##### HAL SYSCFG configuration functions #####
00586  ===============================================================================
00587     [..]  This section provides functions allowing to:
00588       (+) Start a hardware CCMSRAM erase operation
00589       (+) Enable/Disable the Internal FLASH Bank Swapping
00590       (+) Configure the Voltage reference buffer
00591       (+) Enable/Disable the Voltage reference buffer
00592       (+) Enable/Disable the I/O analog switch voltage booster
00593
00594 @endverbatim
00595   * @{
00596   */
00597
00598 /**
00599   * @brief  Start a hardware CCMSRAM erase operation.
00600   * @note   As long as CCMSRAM is not erased the CCMER bit will be set.
00601   *         This bit is automatically reset at the end of the CCMSRAM erase operation.
00602   * @retval None
00603   */
00604 void HAL_SYSCFG_CCMSRAMErase(void)
00605 {
00606   /* unlock the write protection of the CCMER bit */
00607   SYSCFG->SKR = 0xCA;
00608   SYSCFG->SKR = 0x53;
00609   /* Starts a hardware CCMSRAM erase operation*/
00610   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
00611 }
00612
00613 /**
00614   * @brief  Enable the Internal FLASH Bank Swapping.
00615   *
00616   * @note   This function can be used only for STM32G4xx devices.
00617   *
00618   * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
00619   *         and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
00620   *
00621   * @retval None
00622   */
00623 void HAL_SYSCFG_EnableMemorySwappingBank(void)
00624 {
00625   SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
00626 }
00627
00628 /**
00629   * @brief  Disable the Internal FLASH Bank Swapping.
00630   *
00631   * @note   This function can be used only for STM32G4xx devices.
00632   *
00633   * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
00634   *         and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000)
00635   *
00636   * @retval None
00637   */
00638 void HAL_SYSCFG_DisableMemorySwappingBank(void)
00639 {
00640   CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
00641 }
00642
00643 #if defined(VREFBUF)
00644 /**
00645   * @brief Configure the internal voltage reference buffer voltage scale.
00646   * @param  VoltageScaling: specifies the output voltage to achieve
00647   *          This parameter can be one of the following values:
00648   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
00649   *                                                This requires VDDA equal to or higher than 2.4 V.
00650   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
00651   *                                                This requires VDDA equal to or higher than 2.8 V.
00652   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
00653   *                                                This requires VDDA equal to or higher than 3.15 V.
00654   * @retval None
00655   */
00656 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00657 {
00658   /* Check the parameters */
00659   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00660
00661   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
00662 }
00663
00664 /**
00665   * @brief Configure the internal voltage reference buffer high impedance mode.
00666   * @param  Mode: specifies the high impedance mode
00667   *          This parameter can be one of the following values:
00668   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
00669   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
00670   * @retval None
00671   */
00672 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00673 {
00674   /* Check the parameters */
00675   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00676
00677   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00678 }
00679
00680 /**
00681   * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
00682   * @param TrimmingValue specifies trimming code for VREFBUF calibration
00683   *        This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
00684   * @retval None
00685   */
00686 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00687 {
00688   /* Check the parameters */
00689   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00690
00691   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
00692 }
00693
00694 /**
00695   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00696   * @retval HAL_OK/HAL_TIMEOUT
00697   */
00698 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00699 {
00700   uint32_t tickstart;
00701
00702   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00703
00704   /* Get Start Tick*/
00705   tickstart = HAL_GetTick();
00706
00707   /* Wait for VRR bit  */
00708   while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
00709   {
00710     if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00711     {
00712       return HAL_TIMEOUT;
00713     }
00714   }
00715
00716   return HAL_OK;
00717 }
00718
00719 /**
00720   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00721   *
00722   * @retval None
00723   */
00724 void HAL_SYSCFG_DisableVREFBUF(void)
00725 {
00726   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00727 }
00728 #endif /* VREFBUF */
00729
00730 /**
00731   * @brief  Enable the I/O analog switch voltage booster
00732   *
00733   * @retval None
00734   */
00735 void HAL_SYSCFG_EnableIOSwitchBooster(void)
00736 {
00737   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00738 }
00739
00740 /**
00741   * @brief  Disable the I/O analog switch voltage booster
00742   *
00743   * @retval None
00744   */
00745 void HAL_SYSCFG_DisableIOSwitchBooster(void)
00746 {
00747   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00748 }
00749
00750 /**
00751   * @brief  Enable the I/O analog switch voltage by VDD
00752   *
00753   * @retval None
00754   */
00755 void HAL_SYSCFG_EnableIOSwitchVDD(void)
00756 {
00757   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
00758 }
00759
00760 /**
00761   * @brief  Disable the I/O analog switch voltage by VDD
00762   *
00763   * @retval None
00764   */
00765 void HAL_SYSCFG_DisableIOSwitchVDD(void)
00766 {
00767   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
00768 }
00769
00770
00771 /** @brief  CCMSRAM page write protection enable
00772   * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP
00773   * @note   write protection can only be disabled by a system reset
00774   * @retval None
00775   */
00776 void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page)
00777 {
00778   assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
00779
00780   SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
00781 }
00782
00783
00784 /**
00785   * @}
00786   */
00787
00788 /**
00789   * @}
00790   */
00791
00792 #endif /* HAL_MODULE_ENABLED */
00793 /**
00794   * @}
00795   */
00796
00797 /**
00798   * @}
00799   */
00800
Generated on Wed Dec 6 2023 15:11:26 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the HAL
00006   *          module driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * Copyright (c) 2019 STMicroelectronics.
00011   * All rights reserved.
00012   *
00013   * This software is licensed under terms that can be found in the LICENSE file
00014   * in the root directory of this software component.
00015   * If no LICENSE file comes with this software, it is provided AS-IS.
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32G4xx_HAL_H
00022 #define STM32G4xx_HAL_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32g4xx_hal_conf.h"
00030
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup HAL HAL
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /** @defgroup HAL_Exported_Constants HAL Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup HAL_TICK_FREQ Tick Frequency
00047   * @{
00048   */
00049 #define HAL_TICK_FREQ_10HZ         100U
00050 #define HAL_TICK_FREQ_100HZ        10U
00051 #define HAL_TICK_FREQ_1KHZ         1U
00052 #define HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
00059   * @{
00060   */
00061
00062 /** @defgroup SYSCFG_BootMode Boot Mode
00063   * @{
00064   */
00065 #define SYSCFG_BOOT_MAINFLASH          0x00000000U
00066 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMMEMRMP_MODE_0
00067
00068 #if defined (FMC_BANK1)
00069 #define SYSCFG_BOOT_FMC                SYSCFG_MEMMEMRMP_MODE_1
00070 #endif /* FMC_BANK1 */
00071
00072 #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
00073
00074 #if defined (QUADSPI)
00075 #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
00076 #endif /* QUADSPI */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
00083   * @{
00084   */
00085 #define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
00086 #define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
00087 #define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
00088 #define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
00089 #define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
00090 #define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
00097   * @{
00098   */
00099 #define SYSCFG_CCMSRAMWRP_PAGE0          SYSCFG_SWPR_PAGE0  /*!< CCMSRAM Write protection page 0 */
00100 #define SYSCFG_CCMSRAMWRP_PAGE1          SYSCFG_SWPR_PAGE1  /*!< CCMSRAM Write protection page 1 */
00101 #define SYSCFG_CCMSRAMWRP_PAGE2          SYSCFG_SWPR_PAGE2  /*!< CCMSRAM Write protection page 2 */
00102 #define SYSCFG_CCMSRAMWRP_PAGE3          SYSCFG_SWPR_PAGE3  /*!< CCMSRAM Write protection page 3 */
00103 #define SYSCFG_CCMSRAMWRP_PAGE4          SYSCFG_SWPR_PAGE4  /*!< CCMSRAM Write protection page 4 */
00104 #define SYSCFG_CCMSRAMWRP_PAGE5          SYSCFG_SWPR_PAGE5  /*!< CCMSRAM Write protection page 5 */
00105 #define SYSCFG_CCMSRAMWRP_PAGE6          SYSCFG_SWPR_PAGE6  /*!< CCMSRAM Write protection page 6 */
00106 #define SYSCFG_CCMSRAMWRP_PAGE7          SYSCFG_SWPR_PAGE7  /*!< CCMSRAM Write protection page 7 */
00107 #define SYSCFG_CCMSRAMWRP_PAGE8          SYSCFG_SWPR_PAGE8  /*!< CCMSRAM Write protection page 8 */
00108 #define SYSCFG_CCMSRAMWRP_PAGE9          SYSCFG_SWPR_PAGE9  /*!< CCMSRAM Write protection page 9 */
00109 #define SYSCFG_CCMSRAMWRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
00110 #define SYSCFG_CCMSRAMWRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
00111 #define SYSCFG_CCMSRAMWRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
00112 #define SYSCFG_CCMSRAMWRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
00113 #define SYSCFG_CCMSRAMWRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
00114 #define SYSCFG_CCMSRAMWRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
00115 #define SYSCFG_CCMSRAMWRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
00116 #define SYSCFG_CCMSRAMWRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
00117 #define SYSCFG_CCMSRAMWRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
00118 #define SYSCFG_CCMSRAMWRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
00119 #define SYSCFG_CCMSRAMWRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
00120 #define SYSCFG_CCMSRAMWRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
00121 #define SYSCFG_CCMSRAMWRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
00122 #define SYSCFG_CCMSRAMWRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
00123 #define SYSCFG_CCMSRAMWRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
00124 #define SYSCFG_CCMSRAMWRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
00125 #define SYSCFG_CCMSRAMWRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
00126 #define SYSCFG_CCMSRAMWRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
00127 #define SYSCFG_CCMSRAMWRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
00128 #define SYSCFG_CCMSRAMWRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
00129 #define SYSCFG_CCMSRAMWRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
00130 #define SYSCFG_CCMSRAMWRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
00131
00132 /**
00133   * @}
00134   */
00135
00136 #if defined(VREFBUF)
00137 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00138   * @{
00139   */
00140 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
00141 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS_0      /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V)   */
00142 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2  VREFBUF_CSR_VRS_1      /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V)   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00149   * @{
00150   */
00151 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U       /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00152 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ       /*!< VREF_plus pin is high impedance */
00153
00154 /**
00155   * @}
00156   */
00157 #endif /* VREFBUF */
00158
00159 /** @defgroup SYSCFG_flags_definition Flags
00160   * @{
00161   */
00162
00163 #define SYSCFG_FLAG_SRAM_PE             SYSCFG_CFGR2_SPF       /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
00164 #define SYSCFG_FLAG_CCMSRAM_BUSY        SYSCFG_SCSR_CCMBSY     /*!< CCMSRAM busy by erase operation */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00171   * @{
00172   */
00173
00174 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00175   */
00176 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
00177 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
00178 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00179 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
00180 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00181 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00182 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
00183 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported macros -----------------------------------------------------------*/
00198
00199 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
00200   * @{
00201   */
00202
00203 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00204   */
00205 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00206 #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00207 #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00208 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
00209
00210 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00211 #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00212 #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00213 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
00214
00215 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00216 #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00217 #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00218 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
00219
00220 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00221 #define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00222 #define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00223 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
00224
00225 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00226 #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00227 #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00228 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
00229
00230 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00231 #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00232 #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00233 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
00234
00235 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
00236 #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00237 #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00238 #endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
00239
00240 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00241 #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00242 #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00243 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
00244
00245 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00246 #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00247 #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00248 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
00249
00250 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00251 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00252 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00253 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
00254
00255 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00256 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00257 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00258 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
00259
00260 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00261 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00262 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00263 #endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
00264
00265 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00266 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00267 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00268 #endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
00269
00270 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
00271 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
00272 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
00273 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
00274
00275 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
00276 #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00277 #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00278 #endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
00279
00280 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
00281 #define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00282 #define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00283 #endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
00284
00285 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
00286 #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00287 #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00288 #endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
00289
00290 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
00291 #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00292 #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00293 #endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
00294
00295 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
00296 #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00297 #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00298 #endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
00299
00300 #if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
00301 #define __HAL_DBGMCU_FREEZE_TIM20()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
00302 #define __HAL_DBGMCU_UNFREEZE_TIM20()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
00303 #endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
00304
00305 #if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
00306 #define __HAL_DBGMCU_FREEZE_HRTIM1()         SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
00307 #define __HAL_DBGMCU_UNFREEZE_HRTIM1()       CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
00308 #endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00315   * @{
00316   */
00317
00318 /** @brief  Main Flash memory mapped at 0x00000000.
00319   */
00320 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00321
00322 /** @brief  System Flash memory mapped at 0x00000000.
00323   */
00324 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
00325
00326 /** @brief  Embedded SRAM mapped at 0x00000000.
00327   */
00328 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
00329
00330 #if defined (FMC_BANK1)
00331 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
00332   */
00333 #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
00334 #endif /* FMC_BANK1 */
00335
00336 #if defined (QUADSPI)
00337 /** @brief  QUADSPI mapped at 0x00000000.
00338   */
00339 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
00340 #endif /* QUADSPI */
00341
00342 /**
00343   * @brief  Return the boot mode as configured by user.
00344   * @retval The boot mode as configured by user. The returned value can be one
00345   *         of the following values:
00346   *           @arg @ref SYSCFG_BOOT_MAINFLASH
00347   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
00348   *           @arg @ref SYSCFG_BOOT_FMC (*)
00349   *           @arg @ref SYSCFG_BOOT_QUADSPI (*)
00350   *           @arg @ref SYSCFG_BOOT_SRAM
00351   * @note   (*) availability depends on devices
00352   */
00353 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00354
00355 /** @brief  CCMSRAM page write protection enable macro
00356   * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
00357   * @note   write protection can only be disabled by a system reset
00358   * @retval None
00359   */
00360 /* Legacy define */
00361 #define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE   __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
00362 #define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__)    do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
00363                                                                      SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
00364                                                                    }while(0)
00365
00366 /** @brief  CCMSRAM page write protection unlock prior to erase
00367   * @note   Writing a wrong key reactivates the write protection
00368   */
00369 #define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK()    do {SYSCFG->SKR = 0xCA;\
00370                                                   SYSCFG->SKR = 0x53;\
00371                                                 }while(0)
00372
00373 /** @brief  CCMSRAM erase
00374   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
00375   */
00376 #define __HAL_SYSCFG_CCMSRAM_ERASE()         SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
00377
00378 /** @brief  Floating Point Unit interrupt enable/disable macros
00379   * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
00380   */
00381 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00382                                                                  SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00383                                                                }while(0)
00384
00385 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00386                                                                  CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00387                                                                }while(0)
00388
00389 /** @brief  SYSCFG Break ECC lock.
00390   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
00391   * @note   The selected configuration is locked and can be unlocked only by system reset.
00392   */
00393 #define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
00394
00395 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
00396   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
00397   * @note   The selected configuration is locked and can be unlocked only by system reset.
00398   */
00399 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
00400
00401 /** @brief  SYSCFG Break PVD lock.
00402   *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
00403   * @note   The selected configuration is locked and can be unlocked only by system reset.
00404   */
00405 #define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
00406
00407 /** @brief  SYSCFG Break SRAM parity lock.
00408   *         Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
00409   * @note   The selected configuration is locked and can be unlocked by system reset.
00410   */
00411 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
00412
00413 /** @brief  Check SYSCFG flag is set or not.
00414   * @param  __FLAG__: specifies the flag to check.
00415   *         This parameter can be one of the following values:
00416   *            @arg @ref SYSCFG_FLAG_SRAM_PE   SRAM Parity Error Flag
00417   *            @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
00418   * @retval The new state of __FLAG__ (TRUE or FALSE).
00419   */
00420 #define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
00421                                                 & (__FLAG__))!= 0U) ? 1U : 0U)
00422
00423 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
00424   */
00425 #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
00426
00427 /** @brief  Fast-mode Plus driving capability enable/disable macros
00428   * @param __FASTMODEPLUS__: This parameter can be a value of :
00429   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
00430   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
00431   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
00432   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
00433   */
00434 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00435                                                                  SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00436                                                                }while(0)
00437
00438 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00439                                                                  CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00440                                                                }while(0)
00441
00442 /**
00443   * @}
00444   */
00445
00446 /* Private macros ------------------------------------------------------------*/
00447 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
00448   * @{
00449   */
00450
00451 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
00452                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
00453                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
00454                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
00455                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
00456                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
00457
00458 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
00459                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
00460                                             ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY)    || \
00461                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
00462
00463 #if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL)
00464 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  ((__PAGE__) > 0U)
00465 #elif (CCMSRAM_SIZE == 0x00002800UL)
00466 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
00467 #endif /* CCMSRAM_SIZE */
00468
00469 #if defined(VREFBUF)
00470 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00471                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
00472                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
00473
00474 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00475                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00476
00477 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00478 #endif /* VREFBUF */
00479
00480 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
00481 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00482                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00483                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
00484                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00485 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
00486 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00487                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00488                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
00489 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
00490 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00491                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00492                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00493 #else
00494 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00495                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
00496 #endif /* SYSCFG_FASTMODEPLUS_PB */
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup HAL_Private_Macros HAL Private Macros
00502   * @{
00503   */
00504 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
00505                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
00506                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
00507 /**
00508   * @}
00509   */
00510
00511 /* Exported functions --------------------------------------------------------*/
00512
00513 /** @addtogroup HAL_Exported_Functions
00514   * @{
00515   */
00516
00517 /** @addtogroup HAL_Exported_Functions_Group1
00518   * @{
00519   */
00520 /* Initialization and Configuration functions  ******************************/
00521 HAL_StatusTypeDef HAL_Init(void);
00522 HAL_StatusTypeDef HAL_DeInit(void);
00523 void HAL_MspInit(void);
00524 void HAL_MspDeInit(void);
00525 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
00526
00527 /**
00528   * @}
00529   */
00530
00531 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
00532   * @{
00533   */
00534
00535 /* Peripheral Control functions  ************************************************/
00536 void HAL_IncTick(void);
00537 void HAL_Delay(uint32_t Delay);
00538 uint32_t HAL_GetTick(void);
00539 uint32_t HAL_GetTickPrio(void);
00540 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
00541 uint32_t HAL_GetTickFreq(void);
00542 void HAL_SuspendTick(void);
00543 void HAL_ResumeTick(void);
00544 uint32_t HAL_GetHalVersion(void);
00545 uint32_t HAL_GetREVID(void);
00546 uint32_t HAL_GetDEVID(void);
00547 uint32_t HAL_GetUIDw0(void);
00548 uint32_t HAL_GetUIDw1(void);
00549 uint32_t HAL_GetUIDw2(void);
00550
00551 /**
00552   * @}
00553   */
00554
00555 /** @addtogroup HAL_Exported_Functions_Group3
00556   * @{
00557   */
00558
00559 /* DBGMCU Peripheral Control functions  *****************************************/
00560 void HAL_DBGMCU_EnableDBGSleepMode(void);
00561 void HAL_DBGMCU_DisableDBGSleepMode(void);
00562 void HAL_DBGMCU_EnableDBGStopMode(void);
00563 void HAL_DBGMCU_DisableDBGStopMode(void);
00564 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00565 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00566
00567 /**
00568   * @}
00569   */
00570
00571 /* Exported variables ---------------------------------------------------------*/
00572 /** @addtogroup HAL_Exported_Variables
00573   * @{
00574   */
00575 extern __IO uint32_t uwTick;
00576 extern uint32_t uwTickPrio;
00577 extern uint32_t uwTickFreq;
00578 /**
00579   * @}
00580   */
00581
00582 /** @addtogroup HAL_Exported_Functions_Group4
00583   * @{
00584   */
00585
00586 /* SYSCFG Control functions  ****************************************************/
00587 void HAL_SYSCFG_CCMSRAMErase(void);
00588 void HAL_SYSCFG_EnableMemorySwappingBank(void);
00589 void HAL_SYSCFG_DisableMemorySwappingBank(void);
00590
00591 #if defined(VREFBUF)
00592 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00593 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00594 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00595 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00596 void HAL_SYSCFG_DisableVREFBUF(void);
00597 #endif /* VREFBUF */
00598
00599 void HAL_SYSCFG_EnableIOSwitchBooster(void);
00600 void HAL_SYSCFG_DisableIOSwitchBooster(void);
00601 void HAL_SYSCFG_EnableIOSwitchVDD(void);
00602 void HAL_SYSCFG_DisableIOSwitchVDD(void);
00603
00604 void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
00605
00606 /**
00607   * @}
00608   */
00609
00610 /**
00611   * @}
00612   */
00613
00614 /**
00615   * @}
00616   */
00617
00618 /**
00619   * @}
00620   */
00621
00622 #ifdef __cplusplus
00623 }
00624 #endif
00625
00626 #endif /* STM32G4xx_HAL_H */
00627
Generated on Wed Dec 6 2023 15:11:26 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_adc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Converter (ADC)
00007   *          peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *          Other functions (extended functions) are available in file
00012   *          "stm32g4xx_hal_adc_ex.c".
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### ADC peripheral features #####
00028   ==============================================================================
00029   [..]
00030   (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00031
00032   (+) Interrupt generation at the end of regular conversion and in case of
00033       analog watchdog or overrun events.
00034
00035   (+) Single and continuous conversion modes.
00036
00037   (+) Scan mode for conversion of several channels sequentially.
00038
00039   (+) Data alignment with in-built data coherency.
00040
00041   (+) Programmable sampling time (channel wise)
00042
00043   (+) External trigger (timer or EXTI) with configurable polarity
00044
00045   (+) DMA request generation for transfer of conversions data of regular group.
00046
00047   (+) Configurable delay between conversions in Dual interleaved mode.
00048
00049   (+) ADC channels selectable single/differential input.
00050
00051   (+) ADC offset shared on 4 offset instances.
00052   (+) ADC gain compensation
00053
00054   (+) ADC calibration
00055
00056   (+) ADC conversion of regular group.
00057
00058   (+) ADC supply requirements: 1.62 V to 3.6 V.
00059
00060   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00061       Vdda or to an external voltage reference).
00062
00063
00064                      ##### How to use this driver #####
00065   ==============================================================================
00066     [..]
00067
00068      *** Configuration of top level parameters related to ADC ***
00069      ============================================================
00070      [..]
00071
00072     (#) Enable the ADC interface
00073         (++) As prerequisite, ADC clock must be configured at RCC top level.
00074
00075         (++) Two clock settings are mandatory:
00076              (+++) ADC clock (core clock, also possibly conversion clock).
00077
00078              (+++) ADC clock (conversions clock).
00079                    Two possible clock sources: synchronous clock derived from AHB clock
00080                    or asynchronous clock derived from system clock or PLL (output divider P)
00081                    running up to 75MHz.
00082
00083              (+++) Example:
00084                    Into HAL_ADC_MspInit() (recommended code location) or with
00085                    other device clock parameters configuration:
00086                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
00087
00088                RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
00089                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00090                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00091                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
00092                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00093
00094         (++) ADC clock source and clock prescaler are configured at ADC level with
00095              parameter "ClockPrescaler" using function HAL_ADC_Init().
00096
00097     (#) ADC pins configuration
00098          (++) Enable the clock for the ADC GPIOs
00099               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00100          (++) Configure these ADC pins in analog mode
00101               using function HAL_GPIO_Init()
00102
00103     (#) Optionally, in case of usage of ADC with interruptions:
00104          (++) Configure the NVIC for ADC
00105               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00106          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00107               into the function of corresponding ADC interruption vector
00108               ADCx_IRQHandler().
00109
00110     (#) Optionally, in case of usage of DMA:
00111          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00112               using function HAL_DMA_Init().
00113          (++) Configure the NVIC for DMA
00114               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00115          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00116               into the function of corresponding DMA interruption vector
00117               DMAx_Channelx_IRQHandler().
00118
00119      *** Configuration of ADC, group regular, channels parameters ***
00120      ================================================================
00121      [..]
00122
00123     (#) Configure the ADC parameters (resolution, data alignment, ...)
00124         and regular group parameters (conversion trigger, sequencer, ...)
00125         using function HAL_ADC_Init().
00126
00127     (#) Configure the channels for regular group parameters (channel number,
00128         channel rank into sequencer, ..., into regular group)
00129         using function HAL_ADC_ConfigChannel().
00130
00131     (#) Optionally, configure the analog watchdog parameters (channels
00132         monitored, thresholds, ...)
00133         using function HAL_ADC_AnalogWDGConfig().
00134
00135      *** Execution of ADC conversions ***
00136      ====================================
00137      [..]
00138
00139     (#) Optionally, perform an automatic ADC calibration to improve the
00140         conversion accuracy
00141         using function HAL_ADCEx_Calibration_Start().
00142
00143     (#) ADC driver can be used among three modes: polling, interruption,
00144         transfer by DMA.
00145
00146         (++) ADC conversion by polling:
00147           (+++) Activate the ADC peripheral and start conversions
00148                 using function HAL_ADC_Start()
00149           (+++) Wait for ADC conversion completion
00150                 using function HAL_ADC_PollForConversion()
00151           (+++) Retrieve conversion results
00152                 using function HAL_ADC_GetValue()
00153           (+++) Stop conversion and disable the ADC peripheral
00154                 using function HAL_ADC_Stop()
00155
00156         (++) ADC conversion by interruption:
00157           (+++) Activate the ADC peripheral and start conversions
00158                 using function HAL_ADC_Start_IT()
00159           (+++) Wait for ADC conversion completion by call of function
00160                 HAL_ADC_ConvCpltCallback()
00161                 (this function must be implemented in user program)
00162           (+++) Retrieve conversion results
00163                 using function HAL_ADC_GetValue()
00164           (+++) Stop conversion and disable the ADC peripheral
00165                 using function HAL_ADC_Stop_IT()
00166
00167         (++) ADC conversion with transfer by DMA:
00168           (+++) Activate the ADC peripheral and start conversions
00169                 using function HAL_ADC_Start_DMA()
00170           (+++) Wait for ADC conversion completion by call of function
00171                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00172                 (these functions must be implemented in user program)
00173           (+++) Conversion results are automatically transferred by DMA into
00174                 destination variable address.
00175           (+++) Stop conversion and disable the ADC peripheral
00176                 using function HAL_ADC_Stop_DMA()
00177
00178      [..]
00179
00180     (@) Callback functions must be implemented in user program:
00181       (+@) HAL_ADC_ErrorCallback()
00182       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00183       (+@) HAL_ADC_ConvCpltCallback()
00184       (+@) HAL_ADC_ConvHalfCpltCallback
00185
00186      *** Deinitialization of ADC ***
00187      ============================================================
00188      [..]
00189
00190     (#) Disable the ADC interface
00191       (++) ADC clock can be hard reset and disabled at RCC top level.
00192         (++) Hard reset of ADC peripherals
00193              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
00194         (++) ADC clock disable
00195              using the equivalent macro/functions as configuration step.
00196              (+++) Example:
00197                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00198                    other device clock parameters configuration:
00199                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
00200                (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
00201                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
00202
00203     (#) ADC pins configuration
00204          (++) Disable the clock for the ADC GPIOs
00205               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00206
00207     (#) Optionally, in case of usage of ADC with interruptions:
00208          (++) Disable the NVIC for ADC
00209               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00210
00211     (#) Optionally, in case of usage of DMA:
00212          (++) Deinitialize the DMA
00213               using function HAL_DMA_Init().
00214          (++) Disable the NVIC for DMA
00215               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00216
00217     [..]
00218
00219     *** Callback registration ***
00220     =============================================
00221     [..]
00222
00223      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
00224      allows the user to configure dynamically the driver callbacks.
00225      Use Functions @ref HAL_ADC_RegisterCallback()
00226      to register an interrupt callback.
00227     [..]
00228
00229      Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
00230        (+) ConvCpltCallback               : ADC conversion complete callback
00231        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00232        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00233        (+) ErrorCallback                  : ADC error callback
00234        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00235        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00236        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00237        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00238        (+) EndOfSamplingCallback          : ADC end of sampling callback
00239        (+) MspInitCallback                : ADC Msp Init callback
00240        (+) MspDeInitCallback              : ADC Msp DeInit callback
00241      This function takes as parameters the HAL peripheral handle, the Callback ID
00242      and a pointer to the user callback function.
00243     [..]
00244
00245      Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
00246      weak function.
00247     [..]
00248
00249      @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00250      and the Callback ID.
00251      This function allows to reset following callbacks:
00252        (+) ConvCpltCallback               : ADC conversion complete callback
00253        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00254        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00255        (+) ErrorCallback                  : ADC error callback
00256        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00257        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00258        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00259        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00260        (+) EndOfSamplingCallback          : ADC end of sampling callback
00261        (+) MspInitCallback                : ADC Msp Init callback
00262        (+) MspDeInitCallback              : ADC Msp DeInit callback
00263      [..]
00264
00265      By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
00266      all callbacks are set to the corresponding weak functions:
00267      examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
00268      Exception done for MspInit and MspDeInit functions that are
00269      reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
00270      these callbacks are null (not registered beforehand).
00271     [..]
00272
00273      If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
00274      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00275      [..]
00276
00277      Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
00278      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00279      in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
00280      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00281     [..]
00282
00283      Then, the user first registers the MspInit/MspDeInit user callbacks
00284      using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
00285      or @ref HAL_ADC_Init() function.
00286      [..]
00287
00288      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
00289      not defined, the callback registration feature is not available and all callbacks
00290      are set to the corresponding weak functions.
00291
00292   @endverbatim
00293   ******************************************************************************
00294   */
00295
00296 /* Includes ------------------------------------------------------------------*/
00297 #include "stm32g4xx_hal.h"
00298
00299 /** @addtogroup STM32G4xx_HAL_Driver
00300   * @{
00301   */
00302
00303 /** @defgroup ADC ADC
00304   * @brief ADC HAL module driver
00305   * @{
00306   */
00307
00308 #ifdef HAL_ADC_MODULE_ENABLED
00309
00310 /* Private typedef -----------------------------------------------------------*/
00311 /* Private define ------------------------------------------------------------*/
00312
00313 /** @defgroup ADC_Private_Constants ADC Private Constants
00314   * @{
00315   */
00316
00317 #define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
00318                            ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00319                            ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00320                            ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)              /*!< ADC_CFGR fields of parameters that can
00321                           be updated when no regular conversion is on-going */
00322
00323 /* Timeout values for ADC operations (enable settling time,                   */
00324 /*   disable settling time, ...).                                             */
00325 /*   Values defined to be higher than worst cases: low clock frequency,       */
00326 /*   maximum prescalers.                                                      */
00327 #define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
00328 #define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
00329
00330 /* Timeout to wait for current conversion on going to be completed.           */
00331 /* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
00332 /*   - maximum sampling time (640.5 adc_clk)                                  */
00333 /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
00334 /*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
00335 /*   - ADC oversampling ratio 256                                             */
00336 /*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
00337 /* Unit: cycles of CPU clock.                                                 */
00338 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion time-out value */
00339
00340
00341 /**
00342   * @}
00343   */
00344
00345 /* Private macro -------------------------------------------------------------*/
00346 /* Private variables ---------------------------------------------------------*/
00347 /* Private function prototypes -----------------------------------------------*/
00348 /* Exported functions --------------------------------------------------------*/
00349
00350 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00351   * @{
00352   */
00353
00354 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00355   * @brief    ADC Initialization and Configuration functions
00356   *
00357 @verbatim
00358  ===============================================================================
00359               ##### Initialization and de-initialization functions #####
00360  ===============================================================================
00361     [..]  This section provides functions allowing to:
00362       (+) Initialize and configure the ADC.
00363       (+) De-initialize the ADC.
00364 @endverbatim
00365   * @{
00366   */
00367
00368 /**
00369   * @brief  Initialize the ADC peripheral and regular group according to
00370   *         parameters specified in structure "ADC_InitTypeDef".
00371   * @note   As prerequisite, ADC clock must be configured at RCC top level
00372   *         (refer to description of RCC configuration for ADC
00373   *         in header of this file).
00374   * @note   Possibility to update parameters on the fly:
00375   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00376   *         coming from ADC state reset. Following calls to this function can
00377   *         be used to reconfigure some parameters of ADC_InitTypeDef
00378   *         structure on the fly, without modifying MSP configuration. If ADC
00379   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00380   *         before HAL_ADC_Init().
00381   *         The setting of these parameters is conditioned to ADC state.
00382   *         For parameters constraints, see comments of structure
00383   *         "ADC_InitTypeDef".
00384   * @note   This function configures the ADC within 2 scopes: scope of entire
00385   *         ADC and scope of regular group. For parameters details, see comments
00386   *         of structure "ADC_InitTypeDef".
00387   * @note   Parameters related to common ADC registers (ADC clock mode) are set
00388   *         only if all ADCs are disabled.
00389   *         If this is not the case, these common parameters setting are
00390   *         bypassed without error reporting: it can be the intended behaviour in
00391   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00392   *         without  disabling the other ADCs.
00393   * @param hadc ADC handle
00394   * @retval HAL status
00395   */
00396 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
00397 {
00398   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00399   uint32_t tmp_cfgr;
00400   uint32_t tmp_adc_is_conversion_on_going_regular;
00401   uint32_t tmp_adc_is_conversion_on_going_injected;
00402   __IO uint32_t wait_loop_index = 0UL;
00403
00404   /* Check ADC handle */
00405   if (hadc == NULL)
00406   {
00407     return HAL_ERROR;
00408   }
00409
00410   /* Check the parameters */
00411   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00412   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00413   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00414   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00415   assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
00416   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00417   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00418   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00419   assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
00420   assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
00421   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00422   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00423   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00424   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00425   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00426
00427   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00428   {
00429     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00430     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00431
00432     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00433     {
00434       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00435     }
00436   }
00437
00438   /* DISCEN and CONT bits cannot be set at the same time */
00439   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00440
00441   /* Actions performed only if ADC is coming from state reset:                */
00442   /* - Initialization of ADC MSP                                              */
00443   if (hadc->State == HAL_ADC_STATE_RESET)
00444   {
00445 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00446     /* Init the ADC Callback settings */
00447     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
00448     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
00449     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
00450     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
00451     hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
00452     hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak callback */
00453     hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
00454     hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
00455     hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
00456
00457     if (hadc->MspInitCallback == NULL)
00458     {
00459       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
00460     }
00461
00462     /* Init the low level hardware */
00463     hadc->MspInitCallback(hadc);
00464 #else
00465     /* Init the low level hardware */
00466     HAL_ADC_MspInit(hadc);
00467 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00468
00469     /* Set ADC error code to none */
00470     ADC_CLEAR_ERRORCODE(hadc);
00471
00472     /* Initialize Lock */
00473     hadc->Lock = HAL_UNLOCKED;
00474   }
00475
00476   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00477   if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
00478   {
00479     /* Disable ADC deep power down mode */
00480     LL_ADC_DisableDeepPowerDown(hadc->Instance);
00481
00482     /* System was in deep power down mode, calibration must
00483      be relaunched or a previously saved calibration factor
00484      re-applied once the ADC voltage regulator is enabled */
00485   }
00486
00487   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00488   {
00489     /* Enable ADC internal voltage regulator */
00490     LL_ADC_EnableInternalRegulator(hadc->Instance);
00491
00492     /* Note: Variable divided by 2 to compensate partially              */
00493     /*       CPU processing cycles, scaling in us split to not          */
00494     /*       exceed 32 bits register capacity and handle low frequency. */
00495     wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00496     while (wait_loop_index != 0UL)
00497     {
00498       wait_loop_index--;
00499     }
00500   }
00501
00502   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00503   /* or not ADC is coming from state reset (if any potential problem of       */
00504   /* clocking, voltage regulator would not be enabled).                       */
00505   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00506   {
00507     /* Update ADC state machine to error */
00508     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00509
00510     /* Set ADC error code to ADC peripheral internal error */
00511     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00512
00513     tmp_hal_status = HAL_ERROR;
00514   }
00515
00516   /* Configuration of ADC parameters if previous preliminary actions are      */
00517   /* correctly completed and if there is no conversion on going on regular    */
00518   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00519   /* called to update a parameter on the fly).                                */
00520   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00521
00522   if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
00523       && (tmp_adc_is_conversion_on_going_regular == 0UL)
00524      )
00525   {
00526     /* Set ADC state */
00527     ADC_STATE_CLR_SET(hadc->State,
00528                       HAL_ADC_STATE_REG_BUSY,
00529                       HAL_ADC_STATE_BUSY_INTERNAL);
00530
00531     /* Configuration of common ADC parameters                                 */
00532
00533     /* Parameters update conditioned to ADC state:                            */
00534     /* Parameters that can be updated only when ADC is disabled:              */
00535     /*  - clock configuration                                                 */
00536     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00537     {
00538       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00539       {
00540         /* Reset configuration of ADC common register CCR:                      */
00541         /*                                                                      */
00542         /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00543         /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00544         /*    source and sets the clock division factor.                        */
00545         /*                                                                      */
00546         /* Some parameters of this register are not reset, since they are set   */
00547         /* by other functions and must be kept in case of usage of this         */
00548         /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00549         /* without needing to reconfigure all other ADC groups/channels         */
00550         /* parameters):                                                         */
00551         /*   - when multimode feature is available, multimode-related           */
00552         /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
00553         /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
00554         /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00555         /*     (set into HAL_ADC_ConfigChannel() or                             */
00556         /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00557         LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
00558       }
00559     }
00560
00561     /* Configuration of ADC:                                                  */
00562     /*  - resolution                               Init.Resolution            */
00563     /*  - data alignment                           Init.DataAlign             */
00564     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00565     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00566     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00567     /*  - overrun                                  Init.Overrun               */
00568     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00569     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
00570     tmp_cfgr  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)           |
00571                  hadc->Init.Overrun                                                     |
00572                  hadc->Init.DataAlign                                                   |
00573                  hadc->Init.Resolution                                                  |
00574                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
00575
00576     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00577     {
00578       tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
00579     }
00580
00581     /* Enable external trigger if trigger selection is different of software  */
00582     /* start.                                                                 */
00583     /* Note: This configuration keeps the hardware feature of parameter       */
00584     /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00585     /*       software start.                                                  */
00586     if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00587     {
00588       tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
00589                    | hadc->Init.ExternalTrigConvEdge
00590                   );
00591     }
00592
00593     /* Update Configuration Register CFGR */
00594     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
00595
00596     /* Configuration of sampling mode */
00597     MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
00598
00599     /* Parameters update conditioned to ADC state:                            */
00600     /* Parameters that can be updated when ADC is disabled or enabled without */
00601     /* conversion on going on regular and injected groups:                    */
00602     /*  - Gain Compensation               Init.GainCompensation               */
00603     /*  - DMA continuous request          Init.DMAContinuousRequests          */
00604     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00605     /*  - Oversampling parameters         Init.Oversampling                   */
00606     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00607     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
00608         && (tmp_adc_is_conversion_on_going_injected == 0UL)
00609        )
00610     {
00611       tmp_cfgr = (ADC_CFGR_DFSDM(hadc)                                            |
00612                    ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
00613                    ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
00614
00615       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
00616
00617       if (hadc->Init.GainCompensation != 0UL)
00618       {
00619         SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
00620         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
00621       }
00622       else
00623       {
00624         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
00625         MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
00626       }
00627
00628       if (hadc->Init.OversamplingMode == ENABLE)
00629       {
00630         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00631         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00632         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00633         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00634
00635         /* Configuration of Oversampler:                                      */
00636         /*  - Oversampling Ratio                                              */
00637         /*  - Right bit shift                                                 */
00638         /*  - Triggered mode                                                  */
00639         /*  - Oversampling mode (continued/resumed)                           */
00640         MODIFY_REG(hadc->Instance->CFGR2,
00641                    ADC_CFGR2_OVSR  |
00642                    ADC_CFGR2_OVSS  |
00643                    ADC_CFGR2_TROVS |
00644                    ADC_CFGR2_ROVSM,
00645                    ADC_CFGR2_ROVSE                       |
00646                    hadc->Init.Oversampling.Ratio         |
00647                    hadc->Init.Oversampling.RightBitShift |
00648                    hadc->Init.Oversampling.TriggeredMode |
00649                    hadc->Init.Oversampling.OversamplingStopReset
00650                   );
00651       }
00652       else
00653       {
00654         /* Disable ADC oversampling scope on ADC group regular */
00655         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00656       }
00657
00658     }
00659
00660     /* Configuration of regular group sequencer:                              */
00661     /* - if scan mode is disabled, regular channels sequence length is set to */
00662     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00663     /*   Parameter "NbrOfConversion" is discarded.                            */
00664     /*   Note: Scan mode is not present by hardware on this device, but       */
00665     /*   emulated by software for alignment over all STM32 devices.           */
00666     /* - if scan mode is enabled, regular channels sequence length is set to  */
00667     /*   parameter "NbrOfConversion".                                         */
00668
00669     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00670     {
00671       /* Set number of ranks in regular group sequencer */
00672       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
00673     }
00674     else
00675     {
00676       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00677     }
00678
00679     /* Initialize the ADC state */
00680     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00681     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00682   }
00683   else
00684   {
00685     /* Update ADC state machine to error */
00686     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00687
00688     tmp_hal_status = HAL_ERROR;
00689   }
00690
00691   /* Return function status */
00692   return tmp_hal_status;
00693 }
00694
00695 /**
00696   * @brief  Deinitialize the ADC peripheral registers to their default reset
00697   *         values, with deinitialization of the ADC MSP.
00698   * @note   For devices with several ADCs: reset of ADC common registers is done
00699   *         only if all ADCs sharing the same common group are disabled.
00700   *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
00701   *         all ADC instances use the same core clock at RCC level, disabling
00702   *         the core clock reset all ADC instances).
00703   *         If this is not the case, reset of these common parameters reset is
00704   *         bypassed without error reporting: it can be the intended behavior in
00705   *         case of reset of a single ADC while the other ADCs sharing the same
00706   *         common group is still running.
00707   * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
00708   *         this saves more power by reducing leakage currents
00709   *         and is particularly interesting before entering MCU low-power modes.
00710   * @param hadc ADC handle
00711   * @retval HAL status
00712   */
00713 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
00714 {
00715   HAL_StatusTypeDef tmp_hal_status;
00716
00717   /* Check ADC handle */
00718   if (hadc == NULL)
00719   {
00720     return HAL_ERROR;
00721   }
00722
00723   /* Check the parameters */
00724   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00725
00726   /* Set ADC state */
00727   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00728
00729   /* Stop potential conversion on going */
00730   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00731
00732   /* Disable ADC peripheral if conversions are effectively stopped            */
00733   /* Flush register JSQR: reset the queue sequencer when injected             */
00734   /* queue sequencer is enabled and ADC disabled.                             */
00735   /* The software and hardware triggers of the injected sequence are both     */
00736   /* internally disabled just after the completion of the last valid          */
00737   /* injected sequence.                                                       */
00738   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00739
00740   /* Disable ADC peripheral if conversions are effectively stopped */
00741   if (tmp_hal_status == HAL_OK)
00742   {
00743     /* Disable the ADC peripheral */
00744     tmp_hal_status = ADC_Disable(hadc);
00745
00746     /* Check if ADC is effectively disabled */
00747     if (tmp_hal_status == HAL_OK)
00748     {
00749       /* Change ADC state */
00750       hadc->State = HAL_ADC_STATE_READY;
00751     }
00752   }
00753
00754   /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
00755   /*       and disable return status. In case of status fail, attempt to      */
00756   /*       perform deinitialization anyway and it is up user code in          */
00757   /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
00758   /*       system RCC hard reset.                                             */
00759
00760   /* ========== Reset ADC registers ========== */
00761   /* Reset register IER */
00762   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00763                               ADC_IT_JQOVF | ADC_IT_OVR  |
00764                               ADC_IT_JEOS  | ADC_IT_JEOC |
00765                               ADC_IT_EOS   | ADC_IT_EOC  |
00766                               ADC_IT_EOSMP | ADC_IT_RDY));
00767
00768   /* Reset register ISR */
00769   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00770                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00771                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00772                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00773                               ADC_FLAG_EOSMP | ADC_FLAG_RDY));
00774
00775   /* Reset register CR */
00776   /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
00777      ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
00778      no direct reset applicable.
00779      Update CR register to reset value where doable by software */
00780   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00781   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00782
00783   /* Reset register CFGR */
00784   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
00785   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00786
00787   /* Reset register CFGR2 */
00788   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
00789             ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
00790
00791   /* Reset register SMPR1 */
00792   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
00793
00794   /* Reset register SMPR2 */
00795   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00796             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00797             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
00798
00799   /* Reset register TR1 */
00800   CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
00801
00802   /* Reset register TR2 */
00803   CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
00804
00805   /* Reset register TR3 */
00806   CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
00807
00808   /* Reset register SQR1 */
00809   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00810             ADC_SQR1_SQ1 | ADC_SQR1_L);
00811
00812   /* Reset register SQR2 */
00813   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00814             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00815
00816   /* Reset register SQR3 */
00817   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00818             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00819
00820   /* Reset register SQR4 */
00821   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00822
00823   /* Register JSQR was reset when the ADC was disabled */
00824
00825   /* Reset register DR */
00826   /* bits in access mode read only, no direct reset applicable*/
00827
00828   /* Reset register OFR1 */
00829   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00830   /* Reset register OFR2 */
00831   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00832   /* Reset register OFR3 */
00833   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00834   /* Reset register OFR4 */
00835   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00836
00837   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00838   /* bits in access mode read only, no direct reset applicable*/
00839
00840   /* Reset register AWD2CR */
00841   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00842
00843   /* Reset register AWD3CR */
00844   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00845
00846   /* Reset register DIFSEL */
00847   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00848
00849   /* Reset register CALFACT */
00850   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00851
00852
00853   /* ========== Reset common ADC registers ========== */
00854
00855   /* Software is allowed to change common parameters only when all the other
00856      ADCs are disabled.   */
00857   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00858   {
00859     /* Reset configuration of ADC common register CCR:
00860       - clock mode: CKMODE, PRESCEN
00861       - multimode related parameters (when this feature is available): MDMA,
00862         DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
00863       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00864         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00865     */
00866     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
00867
00868     /* ========== Hard reset ADC peripheral ========== */
00869     /* Performs a global reset of the entire ADC peripherals instances        */
00870     /* sharing the same common ADC instance: ADC state is forced to           */
00871     /* a similar state as after device power-on.                              */
00872     /* Note: A possible implementation is to add RCC bus reset of ADC         */
00873     /* (for example, using macro                                              */
00874     /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
00875     /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
00876 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00877     if (hadc->MspDeInitCallback == NULL)
00878     {
00879       hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
00880     }
00881
00882     /* DeInit the low level hardware */
00883     hadc->MspDeInitCallback(hadc);
00884 #else
00885     /* DeInit the low level hardware */
00886     HAL_ADC_MspDeInit(hadc);
00887 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00888   }
00889
00890   /* Set ADC error code to none */
00891   ADC_CLEAR_ERRORCODE(hadc);
00892
00893   /* Reset injected channel configuration parameters */
00894   hadc->InjectionConfig.ContextQueue = 0;
00895   hadc->InjectionConfig.ChannelCount = 0;
00896
00897   /* Set ADC state */
00898   hadc->State = HAL_ADC_STATE_RESET;
00899
00900   /* Process unlocked */
00901   __HAL_UNLOCK(hadc);
00902
00903   /* Return function status */
00904   return tmp_hal_status;
00905 }
00906
00907 /**
00908   * @brief  Initialize the ADC MSP.
00909   * @param hadc ADC handle
00910   * @retval None
00911   */
00912 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
00913 {
00914   /* Prevent unused argument(s) compilation warning */
00915   UNUSED(hadc);
00916
00917   /* NOTE : This function should not be modified. When the callback is needed,
00918             function HAL_ADC_MspInit must be implemented in the user file.
00919    */
00920 }
00921
00922 /**
00923   * @brief  DeInitialize the ADC MSP.
00924   * @param hadc ADC handle
00925   * @note   All ADC instances use the same core clock at RCC level, disabling
00926   *         the core clock reset all ADC instances).
00927   * @retval None
00928   */
00929 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
00930 {
00931   /* Prevent unused argument(s) compilation warning */
00932   UNUSED(hadc);
00933
00934   /* NOTE : This function should not be modified. When the callback is needed,
00935             function HAL_ADC_MspDeInit must be implemented in the user file.
00936    */
00937 }
00938
00939 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00940 /**
00941   * @brief  Register a User ADC Callback
00942   *         To be used instead of the weak predefined callback
00943   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
00944   *                the configuration information for the specified ADC.
00945   * @param  CallbackID ID of the callback to be registered
00946   *         This parameter can be one of the following values:
00947   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
00948   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
00949   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
00950   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
00951   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
00952   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
00953   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
00954   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
00955   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
00956   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
00957   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
00958   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
00959   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
00960   * @param  pCallback pointer to the Callback function
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
00964                                            pADC_CallbackTypeDef pCallback)
00965 {
00966   HAL_StatusTypeDef status = HAL_OK;
00967
00968   if (pCallback == NULL)
00969   {
00970     /* Update the error code */
00971     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00972
00973     return HAL_ERROR;
00974   }
00975
00976   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
00977   {
00978     switch (CallbackID)
00979     {
00980       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
00981         hadc->ConvCpltCallback = pCallback;
00982         break;
00983
00984       case HAL_ADC_CONVERSION_HALF_CB_ID :
00985         hadc->ConvHalfCpltCallback = pCallback;
00986         break;
00987
00988       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
00989         hadc->LevelOutOfWindowCallback = pCallback;
00990         break;
00991
00992       case HAL_ADC_ERROR_CB_ID :
00993         hadc->ErrorCallback = pCallback;
00994         break;
00995
00996       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
00997         hadc->InjectedConvCpltCallback = pCallback;
00998         break;
00999
01000       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
01001         hadc->InjectedQueueOverflowCallback = pCallback;
01002         break;
01003
01004       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01005         hadc->LevelOutOfWindow2Callback = pCallback;
01006         break;
01007
01008       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01009         hadc->LevelOutOfWindow3Callback = pCallback;
01010         break;
01011
01012       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01013         hadc->EndOfSamplingCallback = pCallback;
01014         break;
01015
01016       case HAL_ADC_MSPINIT_CB_ID :
01017         hadc->MspInitCallback = pCallback;
01018         break;
01019
01020       case HAL_ADC_MSPDEINIT_CB_ID :
01021         hadc->MspDeInitCallback = pCallback;
01022         break;
01023
01024       default :
01025         /* Update the error code */
01026         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01027
01028         /* Return error status */
01029         status = HAL_ERROR;
01030         break;
01031     }
01032   }
01033   else if (HAL_ADC_STATE_RESET == hadc->State)
01034   {
01035     switch (CallbackID)
01036     {
01037       case HAL_ADC_MSPINIT_CB_ID :
01038         hadc->MspInitCallback = pCallback;
01039         break;
01040
01041       case HAL_ADC_MSPDEINIT_CB_ID :
01042         hadc->MspDeInitCallback = pCallback;
01043         break;
01044
01045       default :
01046         /* Update the error code */
01047         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01048
01049         /* Return error status */
01050         status = HAL_ERROR;
01051         break;
01052     }
01053   }
01054   else
01055   {
01056     /* Update the error code */
01057     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01058
01059     /* Return error status */
01060     status =  HAL_ERROR;
01061   }
01062
01063   return status;
01064 }
01065
01066 /**
01067   * @brief  Unregister a ADC Callback
01068   *         ADC callback is redirected to the weak predefined callback
01069   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
01070   *                the configuration information for the specified ADC.
01071   * @param  CallbackID ID of the callback to be unregistered
01072   *         This parameter can be one of the following values:
01073   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
01074   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
01075   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
01076   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
01077   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
01078   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
01079   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
01080   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
01081   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
01082   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
01083   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
01084   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
01085   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
01086   * @retval HAL status
01087   */
01088 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
01089 {
01090   HAL_StatusTypeDef status = HAL_OK;
01091
01092   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
01093   {
01094     switch (CallbackID)
01095     {
01096       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
01097         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
01098         break;
01099
01100       case HAL_ADC_CONVERSION_HALF_CB_ID :
01101         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
01102         break;
01103
01104       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
01105         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
01106         break;
01107
01108       case HAL_ADC_ERROR_CB_ID :
01109         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
01110         break;
01111
01112       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
01113         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
01114         break;
01115
01116       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
01117         hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
01118         break;
01119
01120       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01121         hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
01122         break;
01123
01124       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01125         hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
01126         break;
01127
01128       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01129         hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
01130         break;
01131
01132       case HAL_ADC_MSPINIT_CB_ID :
01133         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
01134         break;
01135
01136       case HAL_ADC_MSPDEINIT_CB_ID :
01137         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
01138         break;
01139
01140       default :
01141         /* Update the error code */
01142         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01143
01144         /* Return error status */
01145         status =  HAL_ERROR;
01146         break;
01147     }
01148   }
01149   else if (HAL_ADC_STATE_RESET == hadc->State)
01150   {
01151     switch (CallbackID)
01152     {
01153       case HAL_ADC_MSPINIT_CB_ID :
01154         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
01155         break;
01156
01157       case HAL_ADC_MSPDEINIT_CB_ID :
01158         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
01159         break;
01160
01161       default :
01162         /* Update the error code */
01163         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01164
01165         /* Return error status */
01166         status =  HAL_ERROR;
01167         break;
01168     }
01169   }
01170   else
01171   {
01172     /* Update the error code */
01173     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01174
01175     /* Return error status */
01176     status =  HAL_ERROR;
01177   }
01178
01179   return status;
01180 }
01181
01182 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01183
01184 /**
01185   * @}
01186   */
01187
01188 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
01189   * @brief    ADC IO operation functions
01190   *
01191 @verbatim
01192  ===============================================================================
01193                       ##### IO operation functions #####
01194  ===============================================================================
01195     [..]  This section provides functions allowing to:
01196       (+) Start conversion of regular group.
01197       (+) Stop conversion of regular group.
01198       (+) Poll for conversion complete on regular group.
01199       (+) Poll for conversion event.
01200       (+) Get result of regular channel conversion.
01201       (+) Start conversion of regular group and enable interruptions.
01202       (+) Stop conversion of regular group and disable interruptions.
01203       (+) Handle ADC interrupt request
01204       (+) Start conversion of regular group and enable DMA transfer.
01205       (+) Stop conversion of regular group and disable ADC DMA transfer.
01206 @endverbatim
01207   * @{
01208   */
01209
01210 /**
01211   * @brief  Enable ADC, start conversion of regular group.
01212   * @note   Interruptions enabled in this function: None.
01213   * @note   Case of multimode enabled (when multimode feature is available):
01214   *           if ADC is Slave, ADC is enabled but conversion is not started,
01215   *           if ADC is master, ADC is enabled and multimode conversion is started.
01216   * @param hadc ADC handle
01217   * @retval HAL status
01218   */
01219 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
01220 {
01221   HAL_StatusTypeDef tmp_hal_status;
01222 #if defined(ADC_MULTIMODE_SUPPORT)
01223   const ADC_TypeDef *tmpADC_Master;
01224   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01225 #endif /* ADC_MULTIMODE_SUPPORT */
01226
01227   /* Check the parameters */
01228   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01229
01230   /* Perform ADC enable and conversion start if no conversion is on going */
01231   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01232   {
01233     /* Process locked */
01234     __HAL_LOCK(hadc);
01235
01236     /* Enable the ADC peripheral */
01237     tmp_hal_status = ADC_Enable(hadc);
01238
01239     /* Start conversion if ADC is effectively enabled */
01240     if (tmp_hal_status == HAL_OK)
01241     {
01242       /* Set ADC state                                                        */
01243       /* - Clear state bitfield related to regular group conversion results   */
01244       /* - Set state bitfield related to regular operation                    */
01245       ADC_STATE_CLR_SET(hadc->State,
01246                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01247                         HAL_ADC_STATE_REG_BUSY);
01248
01249 #if defined(ADC_MULTIMODE_SUPPORT)
01250       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01251         - if ADC instance is master or if multimode feature is not available
01252         - if multimode setting is disabled (ADC instance slave in independent mode) */
01253       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01254           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01255          )
01256       {
01257         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01258       }
01259 #endif /* ADC_MULTIMODE_SUPPORT */
01260
01261       /* Set ADC error code */
01262       /* Check if a conversion is on going on ADC group injected */
01263       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01264       {
01265         /* Reset ADC error code fields related to regular conversions only */
01266         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01267       }
01268       else
01269       {
01270         /* Reset all ADC error code fields */
01271         ADC_CLEAR_ERRORCODE(hadc);
01272       }
01273
01274       /* Clear ADC group regular conversion flag and overrun flag               */
01275       /* (To ensure of no unknown state from potential previous ADC operations) */
01276       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01277
01278       /* Process unlocked */
01279       /* Unlock before starting ADC conversions: in case of potential         */
01280       /* interruption, to let the process to ADC IRQ Handler.                 */
01281       __HAL_UNLOCK(hadc);
01282
01283       /* Enable conversion of regular group.                                  */
01284       /* If software start has been selected, conversion starts immediately.  */
01285       /* If external trigger has been selected, conversion will start at next */
01286       /* trigger event.                                                       */
01287       /* Case of multimode enabled (when multimode feature is available):     */
01288       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01289       /*    enabled only (conversion is not started),                         */
01290       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01291 #if defined(ADC_MULTIMODE_SUPPORT)
01292       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01293           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01294           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01295           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01296          )
01297       {
01298         /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
01299         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01300         {
01301           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01302         }
01303
01304         /* Start ADC group regular conversion */
01305         LL_ADC_REG_StartConversion(hadc->Instance);
01306       }
01307       else
01308       {
01309         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
01310         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01311         /* if Master ADC JAUTO bit is set, update Slave State in setting
01312            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
01313         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01314         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
01315         {
01316           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01317         }
01318
01319       }
01320 #else
01321       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01322       {
01323         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01324       }
01325
01326       /* Start ADC group regular conversion */
01327       LL_ADC_REG_StartConversion(hadc->Instance);
01328 #endif /* ADC_MULTIMODE_SUPPORT */
01329     }
01330     else
01331     {
01332       /* Process unlocked */
01333       __HAL_UNLOCK(hadc);
01334     }
01335   }
01336   else
01337   {
01338     tmp_hal_status = HAL_BUSY;
01339   }
01340
01341   /* Return function status */
01342   return tmp_hal_status;
01343 }
01344
01345 /**
01346   * @brief  Stop ADC conversion of regular group (and injected channels in
01347   *         case of auto_injection mode), disable ADC peripheral.
01348   * @note:  ADC peripheral disable is forcing stop of potential
01349   *         conversion on injected group. If injected group is under use, it
01350   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01351   * @param hadc ADC handle
01352   * @retval HAL status.
01353   */
01354 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
01355 {
01356   HAL_StatusTypeDef tmp_hal_status;
01357
01358   /* Check the parameters */
01359   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01360
01361   /* Process locked */
01362   __HAL_LOCK(hadc);
01363
01364   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01365   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01366
01367   /* Disable ADC peripheral if conversions are effectively stopped */
01368   if (tmp_hal_status == HAL_OK)
01369   {
01370     /* 2. Disable the ADC peripheral */
01371     tmp_hal_status = ADC_Disable(hadc);
01372
01373     /* Check if ADC is effectively disabled */
01374     if (tmp_hal_status == HAL_OK)
01375     {
01376       /* Set ADC state */
01377       ADC_STATE_CLR_SET(hadc->State,
01378                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01379                         HAL_ADC_STATE_READY);
01380     }
01381   }
01382
01383   /* Process unlocked */
01384   __HAL_UNLOCK(hadc);
01385
01386   /* Return function status */
01387   return tmp_hal_status;
01388 }
01389
01390 /**
01391   * @brief  Wait for regular group conversion to be completed.
01392   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
01393   *         conversion) are cleared by this function, with an exception:
01394   *         if low power feature "LowPowerAutoWait" is enabled, flags are
01395   *         not cleared to not interfere with this feature until data register
01396   *         is read using function HAL_ADC_GetValue().
01397   * @note   This function cannot be used in a particular setup: ADC configured
01398   *         in DMA mode and polling for end of each conversion (ADC init
01399   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
01400   *         In this case, DMA resets the flag EOC and polling cannot be
01401   *         performed on each conversion. Nevertheless, polling can still
01402   *         be performed on the complete sequence (ADC init
01403   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
01404   * @param hadc ADC handle
01405   * @param Timeout Timeout value in millisecond.
01406   * @retval HAL status
01407   */
01408 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
01409 {
01410   uint32_t tickstart;
01411   uint32_t tmp_Flag_End;
01412   uint32_t tmp_cfgr;
01413 #if defined(ADC_MULTIMODE_SUPPORT)
01414   const ADC_TypeDef *tmpADC_Master;
01415   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01416 #endif /* ADC_MULTIMODE_SUPPORT */
01417
01418   /* Check the parameters */
01419   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01420
01421   /* If end of conversion selected to end of sequence conversions */
01422   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01423   {
01424     tmp_Flag_End = ADC_FLAG_EOS;
01425   }
01426   /* If end of conversion selected to end of unitary conversion */
01427   else /* ADC_EOC_SINGLE_CONV */
01428   {
01429     /* Verification that ADC configuration is compliant with polling for      */
01430     /* each conversion:                                                       */
01431     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
01432     /* several ranks and polling for end of each conversion.                  */
01433     /* For code simplicity sake, this particular case is generalized to       */
01434     /* ADC configured in DMA mode and and polling for end of each conversion. */
01435 #if defined(ADC_MULTIMODE_SUPPORT)
01436     if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01437         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01438         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01439        )
01440     {
01441       /* Check ADC DMA mode in independent mode on ADC group regular */
01442       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
01443       {
01444         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01445         return HAL_ERROR;
01446       }
01447       else
01448       {
01449         tmp_Flag_End = (ADC_FLAG_EOC);
01450       }
01451     }
01452     else
01453     {
01454       /* Check ADC DMA mode in multimode on ADC group regular */
01455       if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
01456       {
01457         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01458         return HAL_ERROR;
01459       }
01460       else
01461       {
01462         tmp_Flag_End = (ADC_FLAG_EOC);
01463       }
01464     }
01465 #else
01466     /* Check ADC DMA mode */
01467     if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
01468     {
01469       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01470       return HAL_ERROR;
01471     }
01472     else
01473     {
01474       tmp_Flag_End = (ADC_FLAG_EOC);
01475     }
01476 #endif /* ADC_MULTIMODE_SUPPORT */
01477   }
01478
01479   /* Get tick count */
01480   tickstart = HAL_GetTick();
01481
01482   /* Wait until End of unitary conversion or sequence conversions flag is raised */
01483   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
01484   {
01485     /* Check if timeout is disabled (set to infinite wait) */
01486     if (Timeout != HAL_MAX_DELAY)
01487     {
01488       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01489       {
01490         /* New check to avoid false timeout detection in case of preemption */
01491         if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
01492         {
01493           /* Update ADC state machine to timeout */
01494           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01495
01496           /* Process unlocked */
01497           __HAL_UNLOCK(hadc);
01498
01499           return HAL_TIMEOUT;
01500         }
01501       }
01502     }
01503   }
01504
01505   /* Update ADC state machine */
01506   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01507
01508   /* Determine whether any further conversion upcoming on group regular       */
01509   /* by external trigger, continuous mode or scan sequence on going.          */
01510   if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
01511       && (hadc->Init.ContinuousConvMode == DISABLE)
01512      )
01513   {
01514     /* Check whether end of sequence is reached */
01515     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
01516     {
01517       /* Set ADC state */
01518       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01519
01520       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
01521       {
01522         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01523       }
01524     }
01525   }
01526
01527   /* Get relevant register CFGR in ADC instance of ADC master or slave        */
01528   /* in function of multimode state (for devices with multimode               */
01529   /* available).                                                              */
01530 #if defined(ADC_MULTIMODE_SUPPORT)
01531   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01532       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01533       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01534       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01535      )
01536   {
01537     /* Retrieve handle ADC CFGR register */
01538     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01539   }
01540   else
01541   {
01542     /* Retrieve Master ADC CFGR register */
01543     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01544     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01545   }
01546 #else
01547   /* Retrieve handle ADC CFGR register */
01548   tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01549 #endif /* ADC_MULTIMODE_SUPPORT */
01550
01551   /* Clear polled flag */
01552   if (tmp_Flag_End == ADC_FLAG_EOS)
01553   {
01554     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
01555   }
01556   else
01557   {
01558     /* Clear end of conversion EOC flag of regular group if low power feature */
01559     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01560     /* until data register is read using function HAL_ADC_GetValue().         */
01561     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
01562     {
01563       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
01564     }
01565   }
01566
01567   /* Return function status */
01568   return HAL_OK;
01569 }
01570
01571 /**
01572   * @brief  Poll for ADC event.
01573   * @param hadc ADC handle
01574   * @param EventType the ADC event type.
01575   *          This parameter can be one of the following values:
01576   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01577   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on
01578   *                                       all STM32 series)
01579   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on
01580   *                                       all STM32 series)
01581   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on
01582   *                                       all STM32 series)
01583   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01584   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01585   * @param Timeout Timeout value in millisecond.
01586   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01587   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01588   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
01589   *         by a new converted data as soon as OVR is cleared.
01590   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01591   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01592   * @retval HAL status
01593   */
01594 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
01595 {
01596   uint32_t tickstart;
01597
01598   /* Check the parameters */
01599   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01600   assert_param(IS_ADC_EVENT_TYPE(EventType));
01601
01602   /* Get tick count */
01603   tickstart = HAL_GetTick();
01604
01605   /* Check selected event flag */
01606   while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01607   {
01608     /* Check if timeout is disabled (set to infinite wait) */
01609     if (Timeout != HAL_MAX_DELAY)
01610     {
01611       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01612       {
01613         /* New check to avoid false timeout detection in case of preemption */
01614         if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01615         {
01616           /* Update ADC state machine to timeout */
01617           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01618
01619           /* Process unlocked */
01620           __HAL_UNLOCK(hadc);
01621
01622           return HAL_TIMEOUT;
01623         }
01624       }
01625     }
01626   }
01627
01628   switch (EventType)
01629   {
01630     /* End Of Sampling event */
01631     case ADC_EOSMP_EVENT:
01632       /* Set ADC state */
01633       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01634
01635       /* Clear the End Of Sampling flag */
01636       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01637
01638       break;
01639
01640     /* Analog watchdog (level out of window) event */
01641     /* Note: In case of several analog watchdog enabled, if needed to know      */
01642     /* which one triggered and on which ADCx, test ADC state of analog watchdog */
01643     /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
01644     /* For example:                                                             */
01645     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
01646     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
01647     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
01648
01649     /* Check analog watchdog 1 flag */
01650     case ADC_AWD_EVENT:
01651       /* Set ADC state */
01652       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01653
01654       /* Clear ADC analog watchdog flag */
01655       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01656
01657       break;
01658
01659     /* Check analog watchdog 2 flag */
01660     case ADC_AWD2_EVENT:
01661       /* Set ADC state */
01662       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01663
01664       /* Clear ADC analog watchdog flag */
01665       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01666
01667       break;
01668
01669     /* Check analog watchdog 3 flag */
01670     case ADC_AWD3_EVENT:
01671       /* Set ADC state */
01672       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01673
01674       /* Clear ADC analog watchdog flag */
01675       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01676
01677       break;
01678
01679     /* Injected context queue overflow event */
01680     case ADC_JQOVF_EVENT:
01681       /* Set ADC state */
01682       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01683
01684       /* Set ADC error code to Injected context queue overflow */
01685       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01686
01687       /* Clear ADC Injected context queue overflow flag */
01688       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01689
01690       break;
01691
01692     /* Overrun event */
01693     default: /* Case ADC_OVR_EVENT */
01694       /* If overrun is set to overwrite previous data, overrun event is not     */
01695       /* considered as an error.                                                */
01696       /* (cf ref manual "Managing conversions without using the DMA and without */
01697       /* overrun ")                                                             */
01698       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01699       {
01700         /* Set ADC state */
01701         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01702
01703         /* Set ADC error code to overrun */
01704         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01705       }
01706       else
01707       {
01708         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01709            otherwise, data register is potentially overwritten by new converted data as soon
01710            as OVR is cleared. */
01711         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01712       }
01713       break;
01714   }
01715
01716   /* Return function status */
01717   return HAL_OK;
01718 }
01719
01720 /**
01721   * @brief  Enable ADC, start conversion of regular group with interruption.
01722   * @note   Interruptions enabled in this function according to initialization
01723   *         setting : EOC (end of conversion), EOS (end of sequence),
01724   *         OVR overrun.
01725   *         Each of these interruptions has its dedicated callback function.
01726   * @note   Case of multimode enabled (when multimode feature is available):
01727   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
01728   *         ADC Master.
01729   *         For ADC Slave, ADC is enabled only (conversion is not started).
01730   *         For ADC Master, ADC is enabled and multimode conversion is started.
01731   * @note   To guarantee a proper reset of all interruptions once all the needed
01732   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01733   *         a correct stop of the IT-based conversions.
01734   * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
01735   *         interruption. If required (e.g. in case of oversampling with trigger
01736   *         mode), the user must:
01737   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
01738   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
01739   *          before calling HAL_ADC_Start_IT().
01740   * @param hadc ADC handle
01741   * @retval HAL status
01742   */
01743 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
01744 {
01745   HAL_StatusTypeDef tmp_hal_status;
01746 #if defined(ADC_MULTIMODE_SUPPORT)
01747   const ADC_TypeDef *tmpADC_Master;
01748   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01749 #endif /* ADC_MULTIMODE_SUPPORT */
01750
01751   /* Check the parameters */
01752   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01753
01754   /* Perform ADC enable and conversion start if no conversion is on going */
01755   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01756   {
01757     /* Process locked */
01758     __HAL_LOCK(hadc);
01759
01760     /* Enable the ADC peripheral */
01761     tmp_hal_status = ADC_Enable(hadc);
01762
01763     /* Start conversion if ADC is effectively enabled */
01764     if (tmp_hal_status == HAL_OK)
01765     {
01766       /* Set ADC state                                                        */
01767       /* - Clear state bitfield related to regular group conversion results   */
01768       /* - Set state bitfield related to regular operation                    */
01769       ADC_STATE_CLR_SET(hadc->State,
01770                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01771                         HAL_ADC_STATE_REG_BUSY);
01772
01773 #if defined(ADC_MULTIMODE_SUPPORT)
01774       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01775         - if ADC instance is master or if multimode feature is not available
01776         - if multimode setting is disabled (ADC instance slave in independent mode) */
01777       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01778           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01779          )
01780       {
01781         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01782       }
01783 #endif /* ADC_MULTIMODE_SUPPORT */
01784
01785       /* Set ADC error code */
01786       /* Check if a conversion is on going on ADC group injected */
01787       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
01788       {
01789         /* Reset ADC error code fields related to regular conversions only */
01790         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01791       }
01792       else
01793       {
01794         /* Reset all ADC error code fields */
01795         ADC_CLEAR_ERRORCODE(hadc);
01796       }
01797
01798       /* Clear ADC group regular conversion flag and overrun flag               */
01799       /* (To ensure of no unknown state from potential previous ADC operations) */
01800       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01801
01802       /* Process unlocked */
01803       /* Unlock before starting ADC conversions: in case of potential         */
01804       /* interruption, to let the process to ADC IRQ Handler.                 */
01805       __HAL_UNLOCK(hadc);
01806
01807       /* Disable all interruptions before enabling the desired ones */
01808       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01809
01810       /* Enable ADC end of conversion interrupt */
01811       switch (hadc->Init.EOCSelection)
01812       {
01813         case ADC_EOC_SEQ_CONV:
01814           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01815           break;
01816         /* case ADC_EOC_SINGLE_CONV */
01817         default:
01818           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01819           break;
01820       }
01821
01822       /* Enable ADC overrun interrupt */
01823       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01824          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01825          behavior and no CPU time is lost for a non-processed interruption */
01826       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01827       {
01828         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01829       }
01830
01831       /* Enable conversion of regular group.                                  */
01832       /* If software start has been selected, conversion starts immediately.  */
01833       /* If external trigger has been selected, conversion will start at next */
01834       /* trigger event.                                                       */
01835       /* Case of multimode enabled (when multimode feature is available):     */
01836       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01837       /*    enabled only (conversion is not started),                         */
01838       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01839 #if defined(ADC_MULTIMODE_SUPPORT)
01840       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
01841           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
01842           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
01843           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
01844          )
01845       {
01846         /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
01847         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01848         {
01849           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01850
01851           /* Enable as well injected interruptions in case
01852            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01853            allows to start regular and injected conversions when JAUTO is
01854            set with a single call to HAL_ADC_Start_IT() */
01855           switch (hadc->Init.EOCSelection)
01856           {
01857             case ADC_EOC_SEQ_CONV:
01858               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01859               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01860               break;
01861             /* case ADC_EOC_SINGLE_CONV */
01862             default:
01863               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01864               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01865               break;
01866           }
01867         }
01868
01869         /* Start ADC group regular conversion */
01870         LL_ADC_REG_StartConversion(hadc->Instance);
01871       }
01872       else
01873       {
01874         /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
01875         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01876         /* if Master ADC JAUTO bit is set, Slave injected interruptions
01877            are enabled nevertheless (for same reason as above) */
01878         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
01879         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
01880         {
01881           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
01882              and in resetting HAL_ADC_STATE_INJ_EOC bit */
01883           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01884           /* Next, set Slave injected interruptions */
01885           switch (hadc->Init.EOCSelection)
01886           {
01887             case ADC_EOC_SEQ_CONV:
01888               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01889               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01890               break;
01891             /* case ADC_EOC_SINGLE_CONV */
01892             default:
01893               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01894               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01895               break;
01896           }
01897         }
01898       }
01899 #else
01900       /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
01901       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
01902       {
01903         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01904
01905         /* Enable as well injected interruptions in case
01906          HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01907          allows to start regular and injected conversions when JAUTO is
01908          set with a single call to HAL_ADC_Start_IT() */
01909         switch (hadc->Init.EOCSelection)
01910         {
01911           case ADC_EOC_SEQ_CONV:
01912             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01913             __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01914             break;
01915           /* case ADC_EOC_SINGLE_CONV */
01916           default:
01917             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01918             __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01919             break;
01920         }
01921       }
01922
01923       /* Start ADC group regular conversion */
01924       LL_ADC_REG_StartConversion(hadc->Instance);
01925 #endif /* ADC_MULTIMODE_SUPPORT */
01926     }
01927     else
01928     {
01929       /* Process unlocked */
01930       __HAL_UNLOCK(hadc);
01931     }
01932
01933   }
01934   else
01935   {
01936     tmp_hal_status = HAL_BUSY;
01937   }
01938
01939   /* Return function status */
01940   return tmp_hal_status;
01941 }
01942
01943 /**
01944   * @brief  Stop ADC conversion of regular group (and injected group in
01945   *         case of auto_injection mode), disable interrution of
01946   *         end-of-conversion, disable ADC peripheral.
01947   * @param hadc ADC handle
01948   * @retval HAL status.
01949   */
01950 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
01951 {
01952   HAL_StatusTypeDef tmp_hal_status;
01953
01954   /* Check the parameters */
01955   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01956
01957   /* Process locked */
01958   __HAL_LOCK(hadc);
01959
01960   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01961   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01962
01963   /* Disable ADC peripheral if conversions are effectively stopped */
01964   if (tmp_hal_status == HAL_OK)
01965   {
01966     /* Disable ADC end of conversion interrupt for regular group */
01967     /* Disable ADC overrun interrupt */
01968     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01969
01970     /* 2. Disable the ADC peripheral */
01971     tmp_hal_status = ADC_Disable(hadc);
01972
01973     /* Check if ADC is effectively disabled */
01974     if (tmp_hal_status == HAL_OK)
01975     {
01976       /* Set ADC state */
01977       ADC_STATE_CLR_SET(hadc->State,
01978                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01979                         HAL_ADC_STATE_READY);
01980     }
01981   }
01982
01983   /* Process unlocked */
01984   __HAL_UNLOCK(hadc);
01985
01986   /* Return function status */
01987   return tmp_hal_status;
01988 }
01989
01990 /**
01991   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01992   * @note   Interruptions enabled in this function:
01993   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01994   *         Each of these interruptions has its dedicated callback function.
01995   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
01996   *         is designed for single-ADC mode only. For multimode, the dedicated
01997   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
01998   * @param hadc ADC handle
01999   * @param pData Destination Buffer address.
02000   * @param Length Number of data to be transferred from ADC peripheral to memory
02001   * @retval HAL status.
02002   */
02003 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
02004 {
02005   HAL_StatusTypeDef tmp_hal_status;
02006 #if defined(ADC_MULTIMODE_SUPPORT)
02007   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02008 #endif /* ADC_MULTIMODE_SUPPORT */
02009
02010   /* Check the parameters */
02011   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02012
02013   /* Perform ADC enable and conversion start if no conversion is on going */
02014   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02015   {
02016     /* Process locked */
02017     __HAL_LOCK(hadc);
02018
02019 #if defined(ADC_MULTIMODE_SUPPORT)
02020     /* Ensure that multimode regular conversions are not enabled.   */
02021     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
02022     if ((ADC_IS_INDEPENDENT(hadc) != RESET)
02023         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02024         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
02025         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
02026        )
02027 #endif /* ADC_MULTIMODE_SUPPORT */
02028     {
02029       /* Enable the ADC peripheral */
02030       tmp_hal_status = ADC_Enable(hadc);
02031
02032       /* Start conversion if ADC is effectively enabled */
02033       if (tmp_hal_status == HAL_OK)
02034       {
02035         /* Set ADC state                                                        */
02036         /* - Clear state bitfield related to regular group conversion results   */
02037         /* - Set state bitfield related to regular operation                    */
02038         ADC_STATE_CLR_SET(hadc->State,
02039                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
02040                           HAL_ADC_STATE_REG_BUSY);
02041
02042 #if defined(ADC_MULTIMODE_SUPPORT)
02043         /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
02044           - if ADC instance is master or if multimode feature is not available
02045           - if multimode setting is disabled (ADC instance slave in independent mode) */
02046         if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
02047             || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02048            )
02049         {
02050           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
02051         }
02052 #endif /* ADC_MULTIMODE_SUPPORT */
02053
02054         /* Check if a conversion is on going on ADC group injected */
02055         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
02056         {
02057           /* Reset ADC error code fields related to regular conversions only */
02058           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
02059         }
02060         else
02061         {
02062           /* Reset all ADC error code fields */
02063           ADC_CLEAR_ERRORCODE(hadc);
02064         }
02065
02066         /* Set the DMA transfer complete callback */
02067         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
02068
02069         /* Set the DMA half transfer complete callback */
02070         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
02071
02072         /* Set the DMA error callback */
02073         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
02074
02075
02076         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
02077         /* ADC start (in case of SW start):                                   */
02078
02079         /* Clear regular group conversion flag and overrun flag               */
02080         /* (To ensure of no unknown state from potential previous ADC         */
02081         /* operations)                                                        */
02082         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
02083
02084         /* Process unlocked */
02085         /* Unlock before starting ADC conversions: in case of potential         */
02086         /* interruption, to let the process to ADC IRQ Handler.                 */
02087         __HAL_UNLOCK(hadc);
02088
02089         /* With DMA, overrun event is always considered as an error even if
02090            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
02091            ADC_IT_OVR is enabled. */
02092         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
02093
02094         /* Enable ADC DMA mode */
02095         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
02096
02097         /* Start the DMA channel */
02098         tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
02099
02100         /* Enable conversion of regular group.                                  */
02101         /* If software start has been selected, conversion starts immediately.  */
02102         /* If external trigger has been selected, conversion will start at next */
02103         /* trigger event.                                                       */
02104         /* Start ADC group regular conversion */
02105         LL_ADC_REG_StartConversion(hadc->Instance);
02106       }
02107       else
02108       {
02109         /* Process unlocked */
02110         __HAL_UNLOCK(hadc);
02111       }
02112
02113     }
02114 #if defined(ADC_MULTIMODE_SUPPORT)
02115     else
02116     {
02117       tmp_hal_status = HAL_ERROR;
02118       /* Process unlocked */
02119       __HAL_UNLOCK(hadc);
02120     }
02121 #endif /* ADC_MULTIMODE_SUPPORT */
02122   }
02123   else
02124   {
02125     tmp_hal_status = HAL_BUSY;
02126   }
02127
02128   /* Return function status */
02129   return tmp_hal_status;
02130 }
02131
02132 /**
02133   * @brief  Stop ADC conversion of regular group (and injected group in
02134   *         case of auto_injection mode), disable ADC DMA transfer, disable
02135   *         ADC peripheral.
02136   * @note:  ADC peripheral disable is forcing stop of potential
02137   *         conversion on ADC group injected. If ADC group injected is under use, it
02138   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
02139   * @note   Case of multimode enabled (when multimode feature is available):
02140   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
02141   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
02142   * @param hadc ADC handle
02143   * @retval HAL status.
02144   */
02145 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
02146 {
02147   HAL_StatusTypeDef tmp_hal_status;
02148
02149   /* Check the parameters */
02150   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02151
02152   /* Process locked */
02153   __HAL_LOCK(hadc);
02154
02155   /* 1. Stop potential ADC group regular conversion on going */
02156   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
02157
02158   /* Disable ADC peripheral if conversions are effectively stopped */
02159   if (tmp_hal_status == HAL_OK)
02160   {
02161     /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
02162     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
02163
02164     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
02165     /* while DMA transfer is on going)                                        */
02166     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
02167     {
02168       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
02169
02170       /* Check if DMA channel effectively disabled */
02171       if (tmp_hal_status != HAL_OK)
02172       {
02173         /* Update ADC state machine to error */
02174         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02175       }
02176     }
02177
02178     /* Disable ADC overrun interrupt */
02179     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
02180
02181     /* 2. Disable the ADC peripheral */
02182     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
02183     /* to keep in memory a potential failing status.                          */
02184     if (tmp_hal_status == HAL_OK)
02185     {
02186       tmp_hal_status = ADC_Disable(hadc);
02187     }
02188     else
02189     {
02190       (void)ADC_Disable(hadc);
02191     }
02192
02193     /* Check if ADC is effectively disabled */
02194     if (tmp_hal_status == HAL_OK)
02195     {
02196       /* Set ADC state */
02197       ADC_STATE_CLR_SET(hadc->State,
02198                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
02199                         HAL_ADC_STATE_READY);
02200     }
02201
02202   }
02203
02204   /* Process unlocked */
02205   __HAL_UNLOCK(hadc);
02206
02207   /* Return function status */
02208   return tmp_hal_status;
02209 }
02210
02211 /**
02212   * @brief  Get ADC regular group conversion result.
02213   * @note   Reading register DR automatically clears ADC flag EOC
02214   *         (ADC group regular end of unitary conversion).
02215   * @note   This function does not clear ADC flag EOS
02216   *         (ADC group regular end of sequence conversion).
02217   *         Occurrence of flag EOS rising:
02218   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
02219   *            to flag EOC.
02220   *          - If sequencer is composed of several ranks, during the scan
02221   *            sequence flag EOC only is raised, at the end of the scan sequence
02222   *            both flags EOC and EOS are raised.
02223   *         To clear this flag, either use function:
02224   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
02225   *         model polling: @ref HAL_ADC_PollForConversion()
02226   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
02227   * @param hadc ADC handle
02228   * @retval ADC group regular conversion data
02229   */
02230 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
02231 {
02232   /* Check the parameters */
02233   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02234
02235   /* Note: EOC flag is not cleared here by software because automatically     */
02236   /*       cleared by hardware when reading register DR.                      */
02237
02238   /* Return ADC converted value */
02239   return hadc->Instance->DR;
02240 }
02241
02242 /**
02243   * @brief  Start ADC conversion sampling phase of regular group
02244   * @note:  This function should only be called to start sampling when
02245   *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
02246   *         mode has been selected
02247   *         - @ref ADC_SOFTWARE_START has been selected as trigger source
02248   * @param hadc ADC handle
02249   * @retval HAL status.
02250   */
02251 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
02252 {
02253   /* Check the parameters */
02254   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02255
02256   /* Start sampling */
02257   SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
02258
02259   /* Return function status */
02260   return HAL_OK;
02261 }
02262
02263 /**
02264   * @brief  Stop ADC conversion sampling phase of regular group and start conversion
02265   * @note:  This function should only be called to stop sampling when
02266   *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
02267   *         mode has been selected
02268   *         - @ref ADC_SOFTWARE_START has been selected as trigger source
02269   *         - after sampling has been started using @ref HAL_ADC_StartSampling.
02270   * @param hadc ADC handle
02271   * @retval HAL status.
02272   */
02273 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
02274 {
02275   /* Check the parameters */
02276   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02277
02278   /* Start sampling */
02279   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
02280
02281   /* Return function status */
02282   return HAL_OK;
02283 }
02284
02285 /**
02286   * @brief  Handle ADC interrupt request.
02287   * @param hadc ADC handle
02288   * @retval None
02289   */
02290 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
02291 {
02292   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
02293   uint32_t tmp_isr = hadc->Instance->ISR;
02294   uint32_t tmp_ier = hadc->Instance->IER;
02295   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
02296   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
02297   uint32_t tmp_cfgr;
02298 #if defined(ADC_MULTIMODE_SUPPORT)
02299   const ADC_TypeDef *tmpADC_Master;
02300   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02301 #endif /* ADC_MULTIMODE_SUPPORT */
02302
02303   /* Check the parameters */
02304   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02305   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
02306
02307   /* ========== Check End of Sampling flag for ADC group regular ========== */
02308   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
02309   {
02310     /* Update state machine on end of sampling status if not in error state */
02311     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02312     {
02313       /* Set ADC state */
02314       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
02315     }
02316
02317     /* End Of Sampling callback */
02318 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02319     hadc->EndOfSamplingCallback(hadc);
02320 #else
02321     HAL_ADCEx_EndOfSamplingCallback(hadc);
02322 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02323
02324     /* Clear regular group conversion flag */
02325     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
02326   }
02327
02328   /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
02329   if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
02330       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
02331   {
02332     /* Update state machine on conversion status if not in error state */
02333     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02334     {
02335       /* Set ADC state */
02336       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02337     }
02338
02339     /* Determine whether any further conversion upcoming on group regular     */
02340     /* by external trigger, continuous mode or scan sequence on going         */
02341     /* to disable interruption.                                               */
02342     if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
02343     {
02344       /* Get relevant register CFGR in ADC instance of ADC master or slave    */
02345       /* in function of multimode state (for devices with multimode           */
02346       /* available).                                                          */
02347 #if defined(ADC_MULTIMODE_SUPPORT)
02348       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
02349           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02350           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
02351           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
02352          )
02353       {
02354         /* check CONT bit directly in handle ADC CFGR register */
02355         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02356       }
02357       else
02358       {
02359         /* else need to check Master ADC CONT bit */
02360         tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
02361         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
02362       }
02363 #else
02364       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02365 #endif /* ADC_MULTIMODE_SUPPORT */
02366
02367       /* Carry on if continuous mode is disabled */
02368       if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
02369       {
02370         /* If End of Sequence is reached, disable interrupts */
02371         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
02372         {
02373           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
02374           /* ADSTART==0 (no conversion on going)                              */
02375           if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02376           {
02377             /* Disable ADC end of sequence conversion interrupt */
02378             /* Note: Overrun interrupt was enabled with EOC interrupt in      */
02379             /* HAL_Start_IT(), but is not disabled here because can be used   */
02380             /* by overrun IRQ process below.                                  */
02381             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
02382
02383             /* Set ADC state */
02384             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02385
02386             if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
02387             {
02388               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02389             }
02390           }
02391           else
02392           {
02393             /* Change ADC state to error state */
02394             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02395
02396             /* Set ADC error code to ADC peripheral internal error */
02397             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02398           }
02399         }
02400       }
02401     }
02402
02403     /* Conversion complete callback */
02404     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
02405     /*       to determine if conversion has been triggered from EOC or EOS,   */
02406     /*       possibility to use:                                              */
02407     /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
02408 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02409     hadc->ConvCpltCallback(hadc);
02410 #else
02411     HAL_ADC_ConvCpltCallback(hadc);
02412 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02413
02414     /* Clear regular group conversion flag */
02415     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
02416     /*       conversion flags clear induces the release of the preserved data.*/
02417     /*       Therefore, if the preserved data value is needed, it must be     */
02418     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
02419     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
02420   }
02421
02422   /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
02423   if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
02424       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
02425   {
02426     /* Update state machine on conversion status if not in error state */
02427     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02428     {
02429       /* Set ADC state */
02430       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
02431     }
02432
02433     /* Retrieve ADC configuration */
02434     tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
02435     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
02436     /* Get relevant register CFGR in ADC instance of ADC master or slave  */
02437     /* in function of multimode state (for devices with multimode         */
02438     /* available).                                                        */
02439 #if defined(ADC_MULTIMODE_SUPPORT)
02440     if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
02441         || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
02442         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
02443         || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
02444        )
02445     {
02446       tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02447     }
02448     else
02449     {
02450       tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
02451       tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
02452     }
02453 #else
02454     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02455 #endif /* ADC_MULTIMODE_SUPPORT */
02456
02457     /* Disable interruption if no further conversion upcoming by injected     */
02458     /* external trigger or by automatic injected conversion with regular      */
02459     /* group having no further conversion upcoming (same conditions as        */
02460     /* regular group interruption disabling above),                           */
02461     /* and if injected scan sequence is completed.                            */
02462     if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
02463     {
02464       if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
02465           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
02466            (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
02467       {
02468         /* If End of Sequence is reached, disable interrupts */
02469         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
02470         {
02471           /* Particular case if injected contexts queue is enabled:             */
02472           /* when the last context has been fully processed, JSQR is reset      */
02473           /* by the hardware. Even if no injected conversion is planned to come */
02474           /* (queue empty, triggers are ignored), it can start again            */
02475           /* immediately after setting a new context (JADSTART is still set).   */
02476           /* Therefore, state of HAL ADC injected group is kept to busy.        */
02477           if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
02478           {
02479             /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
02480             /* JADSTART==0 (no conversion on going)                             */
02481             if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
02482             {
02483               /* Disable ADC end of sequence conversion interrupt  */
02484               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
02485
02486               /* Set ADC state */
02487               CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
02488
02489               if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
02490               {
02491                 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02492               }
02493             }
02494             else
02495             {
02496               /* Update ADC state machine to error */
02497               SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02498
02499               /* Set ADC error code to ADC peripheral internal error */
02500               SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02501             }
02502           }
02503         }
02504       }
02505     }
02506
02507     /* Injected Conversion complete callback */
02508     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
02509               if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
02510               if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
02511               interruption has been triggered by end of conversion or end of
02512               sequence.    */
02513 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02514     hadc->InjectedConvCpltCallback(hadc);
02515 #else
02516     HAL_ADCEx_InjectedConvCpltCallback(hadc);
02517 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02518
02519     /* Clear injected group conversion flag */
02520     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
02521   }
02522
02523   /* ========== Check Analog watchdog 1 flag ========== */
02524   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
02525   {
02526     /* Set ADC state */
02527     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02528
02529     /* Level out of window 1 callback */
02530 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02531     hadc->LevelOutOfWindowCallback(hadc);
02532 #else
02533     HAL_ADC_LevelOutOfWindowCallback(hadc);
02534 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02535
02536     /* Clear ADC analog watchdog flag */
02537     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
02538   }
02539
02540   /* ========== Check analog watchdog 2 flag ========== */
02541   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
02542   {
02543     /* Set ADC state */
02544     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02545
02546     /* Level out of window 2 callback */
02547 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02548     hadc->LevelOutOfWindow2Callback(hadc);
02549 #else
02550     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
02551 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02552
02553     /* Clear ADC analog watchdog flag */
02554     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
02555   }
02556
02557   /* ========== Check analog watchdog 3 flag ========== */
02558   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
02559   {
02560     /* Set ADC state */
02561     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02562
02563     /* Level out of window 3 callback */
02564 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02565     hadc->LevelOutOfWindow3Callback(hadc);
02566 #else
02567     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
02568 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02569
02570     /* Clear ADC analog watchdog flag */
02571     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
02572   }
02573
02574   /* ========== Check Overrun flag ========== */
02575   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
02576   {
02577     /* If overrun is set to overwrite previous data (default setting),        */
02578     /* overrun event is not considered as an error.                           */
02579     /* (cf ref manual "Managing conversions without using the DMA and without */
02580     /* overrun ")                                                             */
02581     /* Exception for usage with DMA overrun event always considered as an     */
02582     /* error.                                                                 */
02583     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02584     {
02585       overrun_error = 1UL;
02586     }
02587     else
02588     {
02589       /* Check DMA configuration */
02590 #if defined(ADC_MULTIMODE_SUPPORT)
02591       if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
02592       {
02593         /* Multimode (when feature is available) is enabled,
02594            Common Control Register MDMA bits must be checked. */
02595         if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
02596         {
02597           overrun_error = 1UL;
02598         }
02599       }
02600       else
02601 #endif /* ADC_MULTIMODE_SUPPORT */
02602       {
02603         /* Multimode not set or feature not available or ADC independent */
02604         if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
02605         {
02606           overrun_error = 1UL;
02607         }
02608       }
02609     }
02610
02611     if (overrun_error == 1UL)
02612     {
02613       /* Change ADC state to error state */
02614       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
02615
02616       /* Set ADC error code to overrun */
02617       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
02618
02619       /* Error callback */
02620       /* Note: In case of overrun, ADC conversion data is preserved until     */
02621       /*       flag OVR is reset.                                             */
02622       /*       Therefore, old ADC conversion data can be retrieved in         */
02623       /*       function "HAL_ADC_ErrorCallback()".                            */
02624 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02625       hadc->ErrorCallback(hadc);
02626 #else
02627       HAL_ADC_ErrorCallback(hadc);
02628 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02629     }
02630
02631     /* Clear ADC overrun flag */
02632     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
02633   }
02634
02635   /* ========== Check Injected context queue overflow flag ========== */
02636   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
02637   {
02638     /* Change ADC state to overrun state */
02639     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02640
02641     /* Set ADC error code to Injected context queue overflow */
02642     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
02643
02644     /* Clear the Injected context queue overflow flag */
02645     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
02646
02647     /* Injected context queue overflow callback */
02648 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02649     hadc->InjectedQueueOverflowCallback(hadc);
02650 #else
02651     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
02652 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02653   }
02654
02655 }
02656
02657 /**
02658   * @brief  Conversion complete callback in non-blocking mode.
02659   * @param hadc ADC handle
02660   * @retval None
02661   */
02662 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
02663 {
02664   /* Prevent unused argument(s) compilation warning */
02665   UNUSED(hadc);
02666
02667   /* NOTE : This function should not be modified. When the callback is needed,
02668             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02669    */
02670 }
02671
02672 /**
02673   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02674   * @param hadc ADC handle
02675   * @retval None
02676   */
02677 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
02678 {
02679   /* Prevent unused argument(s) compilation warning */
02680   UNUSED(hadc);
02681
02682   /* NOTE : This function should not be modified. When the callback is needed,
02683             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02684   */
02685 }
02686
02687 /**
02688   * @brief  Analog watchdog 1 callback in non-blocking mode.
02689   * @param hadc ADC handle
02690   * @retval None
02691   */
02692 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
02693 {
02694   /* Prevent unused argument(s) compilation warning */
02695   UNUSED(hadc);
02696
02697   /* NOTE : This function should not be modified. When the callback is needed,
02698             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02699   */
02700 }
02701
02702 /**
02703   * @brief  ADC error callback in non-blocking mode
02704   *         (ADC conversion with interruption or transfer by DMA).
02705   * @note   In case of error due to overrun when using ADC with DMA transfer
02706   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
02707   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
02708   *         - If needed, restart a new ADC conversion using function
02709   *           "HAL_ADC_Start_DMA()"
02710   *           (this function is also clearing overrun flag)
02711   * @param hadc ADC handle
02712   * @retval None
02713   */
02714 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02715 {
02716   /* Prevent unused argument(s) compilation warning */
02717   UNUSED(hadc);
02718
02719   /* NOTE : This function should not be modified. When the callback is needed,
02720             function HAL_ADC_ErrorCallback must be implemented in the user file.
02721   */
02722 }
02723
02724 /**
02725   * @}
02726   */
02727
02728 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02729   * @brief    Peripheral Control functions
02730   *
02731 @verbatim
02732  ===============================================================================
02733              ##### Peripheral Control functions #####
02734  ===============================================================================
02735     [..]  This section provides functions allowing to:
02736       (+) Configure channels on regular group
02737       (+) Configure the analog watchdog
02738
02739 @endverbatim
02740   * @{
02741   */
02742
02743 /**
02744   * @brief  Configure a channel to be assigned to ADC group regular.
02745   * @note   In case of usage of internal measurement channels:
02746   *         Vbat/VrefInt/TempSensor.
02747   *         These internal paths can be disabled using function
02748   *         HAL_ADC_DeInit().
02749   * @note   Possibility to update parameters on the fly:
02750   *         This function initializes channel into ADC group regular,
02751   *         following calls to this function can be used to reconfigure
02752   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
02753   *         without resetting the ADC.
02754   *         The setting of these parameters is conditioned to ADC state:
02755   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
02756   * @param hadc ADC handle
02757   * @param pConfig Structure of ADC channel assigned to ADC group regular.
02758   * @retval HAL status
02759   */
02760 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
02761 {
02762   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02763   uint32_t tmpOffsetShifted;
02764   uint32_t tmp_config_internal_channel;
02765   __IO uint32_t wait_loop_index = 0UL;
02766   uint32_t tmp_adc_is_conversion_on_going_regular;
02767   uint32_t tmp_adc_is_conversion_on_going_injected;
02768
02769   /* Check the parameters */
02770   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02771   assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
02772   assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
02773   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
02774   assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
02775   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
02776
02777   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
02778      ignored (considered as reset) */
02779   assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
02780
02781   /* Verification of channel number */
02782   if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02783   {
02784     assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
02785   }
02786   else
02787   {
02788     assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
02789   }
02790
02791   /* Process locked */
02792   __HAL_LOCK(hadc);
02793
02794   /* Parameters update conditioned to ADC state:                              */
02795   /* Parameters that can be updated when ADC is disabled or enabled without   */
02796   /* conversion on going on regular group:                                    */
02797   /*  - Channel number                                                        */
02798   /*  - Channel rank                                                          */
02799   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02800   {
02801     /* Set ADC group regular sequence: channel on the selected scan sequence rank */
02802     LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
02803
02804     /* Parameters update conditioned to ADC state:                              */
02805     /* Parameters that can be updated when ADC is disabled or enabled without   */
02806     /* conversion on going on regular group:                                    */
02807     /*  - Channel sampling time                                                 */
02808     /*  - Channel offset                                                        */
02809     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02810     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02811     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02812         && (tmp_adc_is_conversion_on_going_injected == 0UL)
02813        )
02814     {
02815       /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
02816       if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
02817       {
02818         /* Set sampling time of the selected ADC channel */
02819         LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
02820
02821         /* Set ADC sampling time common configuration */
02822         LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
02823       }
02824       else
02825       {
02826         /* Set sampling time of the selected ADC channel */
02827         LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
02828
02829         /* Set ADC sampling time common configuration */
02830         LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
02831       }
02832
02833       /* Configure the offset: offset enable/disable, channel, offset value */
02834
02835       /* Shift the offset with respect to the selected ADC resolution. */
02836       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02837       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
02838
02839       if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
02840       {
02841         /* Set ADC selected offset number */
02842         LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
02843
02844         assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
02845         assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
02846         /* Set ADC selected offset sign & saturation */
02847         LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
02848         LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
02849                                    (pConfig->OffsetSaturation == ENABLE) ?
02850                                    LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
02851       }
02852       else
02853       {
02854         /* Scan each offset register to check if the selected channel is targeted. */
02855         /* If this is the case, the corresponding offset number is disabled.       */
02856         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
02857             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
02858         {
02859           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
02860         }
02861         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
02862             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
02863         {
02864           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
02865         }
02866         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
02867             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
02868         {
02869           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
02870         }
02871         if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
02872             == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
02873         {
02874           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
02875         }
02876       }
02877     }
02878
02879     /* Parameters update conditioned to ADC state:                              */
02880     /* Parameters that can be updated only when ADC is disabled:                */
02881     /*  - Single or differential mode                                           */
02882     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02883     {
02884       /* Set mode single-ended or differential input of the selected ADC channel */
02885       LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
02886
02887       /* Configuration of differential mode */
02888       if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
02889       {
02890         /* Set sampling time of the selected ADC channel */
02891         /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
02892         LL_ADC_SetChannelSamplingTime(hadc->Instance,
02893                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
02894                                                    (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
02895                                                     + 1UL) & 0x1FUL)),
02896                                       pConfig->SamplingTime);
02897       }
02898
02899     }
02900
02901     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02902     /* If internal channel selected, enable dedicated internal buffers and    */
02903     /* paths.                                                                 */
02904     /* Note: these internal measurement paths can be disabled using           */
02905     /* HAL_ADC_DeInit().                                                      */
02906
02907     if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
02908     {
02909       tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02910
02911       /* If the requested internal measurement path has already been enabled, */
02912       /* bypass the configuration processing.                                 */
02913       if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
02914           && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02915       {
02916         if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02917         {
02918           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02919                                          LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02920
02921           /* Delay for temperature sensor stabilization time */
02922           /* Wait loop initialization and execution */
02923           /* Note: Variable divided by 2 to compensate partially              */
02924           /*       CPU processing cycles, scaling in us split to not          */
02925           /*       exceed 32 bits register capacity and handle low frequency. */
02926           wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
02927           while (wait_loop_index != 0UL)
02928           {
02929             wait_loop_index--;
02930           }
02931         }
02932       }
02933       else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
02934                && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02935       {
02936         if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02937         {
02938           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02939                                          LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02940         }
02941       }
02942       else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
02943                && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02944       {
02945         if (ADC_VREFINT_INSTANCE(hadc))
02946         {
02947           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02948                                          LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02949         }
02950       }
02951       else
02952       {
02953         /* nothing to do */
02954       }
02955     }
02956   }
02957
02958   /* If a conversion is on going on regular group, no update on regular       */
02959   /* channel could be done on neither of the channel configuration structure  */
02960   /* parameters.                                                              */
02961   else
02962   {
02963     /* Update ADC state machine to error */
02964     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02965
02966     tmp_hal_status = HAL_ERROR;
02967   }
02968
02969   /* Process unlocked */
02970   __HAL_UNLOCK(hadc);
02971
02972   /* Return function status */
02973   return tmp_hal_status;
02974 }
02975
02976 /**
02977   * @brief  Configure the analog watchdog.
02978   * @note   Possibility to update parameters on the fly:
02979   *         This function initializes the selected analog watchdog, successive
02980   *         calls to this function can be used to reconfigure some parameters
02981   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02982   *         the ADC.
02983   *         The setting of these parameters is conditioned to ADC state.
02984   *         For parameters constraints, see comments of structure
02985   *         "ADC_AnalogWDGConfTypeDef".
02986   * @note   On this STM32 series, analog watchdog thresholds can be modified
02987   *         while ADC conversion is on going.
02988   *         In this case, some constraints must be taken into account:
02989   *         the programmed threshold values are effective from the next
02990   *         ADC EOC (end of unitary conversion).
02991   *         Considering that registers write delay may happen due to
02992   *         bus activity, this might cause an uncertainty on the
02993   *         effective timing of the new programmed threshold values.
02994   * @param hadc ADC handle
02995   * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
02996   * @retval HAL status
02997   */
02998 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
02999 {
03000   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
03001   uint32_t tmp_awd_high_threshold_shifted;
03002   uint32_t tmp_awd_low_threshold_shifted;
03003   uint32_t tmp_adc_is_conversion_on_going_regular;
03004   uint32_t tmp_adc_is_conversion_on_going_injected;
03005
03006   /* Check the parameters */
03007   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03008   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
03009   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
03010   assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
03011   assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
03012
03013   if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
03014       (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
03015       (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
03016   {
03017     assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
03018   }
03019
03020   /* Verify thresholds range */
03021   if (hadc->Init.OversamplingMode == ENABLE)
03022   {
03023     /* Case of oversampling enabled: depending on ratio and shift configuration,
03024        analog watchdog thresholds can be higher than ADC resolution.
03025        Verify if thresholds are within maximum thresholds range. */
03026     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
03027     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
03028   }
03029   else
03030   {
03031     /* Verify if thresholds are within the selected ADC resolution */
03032     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
03033     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
03034   }
03035
03036   /* Process locked */
03037   __HAL_LOCK(hadc);
03038
03039   /* Parameters update conditioned to ADC state:                              */
03040   /* Parameters that can be updated when ADC is disabled or enabled without   */
03041   /* conversion on going on ADC groups regular and injected:                  */
03042   /*  - Analog watchdog channels                                              */
03043   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
03044   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
03045   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
03046       && (tmp_adc_is_conversion_on_going_injected == 0UL)
03047      )
03048   {
03049     /* Analog watchdog configuration */
03050     if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
03051     {
03052       /* Configuration of analog watchdog:                                    */
03053       /*  - Set the analog watchdog enable mode: one or overall group of      */
03054       /*    channels, on groups regular and-or injected.                      */
03055       switch (pAnalogWDGConfig->WatchdogMode)
03056       {
03057         case ADC_ANALOGWATCHDOG_SINGLE_REG:
03058           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
03059                                           __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
03060                                                                           LL_ADC_GROUP_REGULAR));
03061           break;
03062
03063         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
03064           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
03065                                           __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
03066                                                                           LL_ADC_GROUP_INJECTED));
03067           break;
03068
03069         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
03070           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
03071                                           __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
03072                                                                           LL_ADC_GROUP_REGULAR_INJECTED));
03073           break;
03074
03075         case ADC_ANALOGWATCHDOG_ALL_REG:
03076           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
03077           break;
03078
03079         case ADC_ANALOGWATCHDOG_ALL_INJEC:
03080           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
03081           break;
03082
03083         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
03084           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
03085           break;
03086
03087         default: /* ADC_ANALOGWATCHDOG_NONE */
03088           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
03089           break;
03090       }
03091
03092       /* Set the filtering configuration */
03093       MODIFY_REG(hadc->Instance->TR1,
03094                  ADC_TR1_AWDFILT,
03095                  pAnalogWDGConfig->FilteringConfig);
03096
03097       /* Update state, clear previous result related to AWD1 */
03098       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
03099
03100       /* Clear flag ADC analog watchdog */
03101       /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
03102       /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
03103       /* (in case left enabled by previous ADC operations).                 */
03104       LL_ADC_ClearFlag_AWD1(hadc->Instance);
03105
03106       /* Configure ADC analog watchdog interrupt */
03107       if (pAnalogWDGConfig->ITMode == ENABLE)
03108       {
03109         LL_ADC_EnableIT_AWD1(hadc->Instance);
03110       }
03111       else
03112       {
03113         LL_ADC_DisableIT_AWD1(hadc->Instance);
03114       }
03115     }
03116     /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
03117     else
03118     {
03119       switch (pAnalogWDGConfig->WatchdogMode)
03120       {
03121         case ADC_ANALOGWATCHDOG_SINGLE_REG:
03122         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
03123         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
03124           /* Update AWD by bitfield to keep the possibility to monitor        */
03125           /* several channels by successive calls of this function.           */
03126           if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03127           {
03128             SET_BIT(hadc->Instance->AWD2CR,
03129                     (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
03130           }
03131           else
03132           {
03133             SET_BIT(hadc->Instance->AWD3CR,
03134                     (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
03135           }
03136           break;
03137
03138         case ADC_ANALOGWATCHDOG_ALL_REG:
03139         case ADC_ANALOGWATCHDOG_ALL_INJEC:
03140         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
03141           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
03142                                           pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
03143           break;
03144
03145         default: /* ADC_ANALOGWATCHDOG_NONE */
03146           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
03147           break;
03148       }
03149
03150       if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
03151       {
03152         /* Update state, clear previous result related to AWD2 */
03153         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
03154
03155         /* Clear flag ADC analog watchdog */
03156         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
03157         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
03158         /* (in case left enabled by previous ADC operations).                 */
03159         LL_ADC_ClearFlag_AWD2(hadc->Instance);
03160
03161         /* Configure ADC analog watchdog interrupt */
03162         if (pAnalogWDGConfig->ITMode == ENABLE)
03163         {
03164           LL_ADC_EnableIT_AWD2(hadc->Instance);
03165         }
03166         else
03167         {
03168           LL_ADC_DisableIT_AWD2(hadc->Instance);
03169         }
03170       }
03171       /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
03172       else
03173       {
03174         /* Update state, clear previous result related to AWD3 */
03175         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
03176
03177         /* Clear flag ADC analog watchdog */
03178         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
03179         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
03180         /* (in case left enabled by previous ADC operations).                 */
03181         LL_ADC_ClearFlag_AWD3(hadc->Instance);
03182
03183         /* Configure ADC analog watchdog interrupt */
03184         if (pAnalogWDGConfig->ITMode == ENABLE)
03185         {
03186           LL_ADC_EnableIT_AWD3(hadc->Instance);
03187         }
03188         else
03189         {
03190           LL_ADC_DisableIT_AWD3(hadc->Instance);
03191         }
03192       }
03193     }
03194
03195   }
03196
03197   /* Analog watchdog thresholds configuration */
03198   if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
03199   {
03200     /* Shift the offset with respect to the selected ADC resolution:        */
03201     /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
03202     /* are set to 0.                                                        */
03203     tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
03204     tmp_awd_low_threshold_shifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
03205   }
03206   /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
03207   else
03208   {
03209     /* Shift the offset with respect to the selected ADC resolution:        */
03210     /* Thresholds have to be left-aligned on bit 7, the LSB (right bits)    */
03211     /* are set to 0.                                                        */
03212     tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
03213     tmp_awd_low_threshold_shifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
03214   }
03215
03216   /* Set ADC analog watchdog thresholds value of both thresholds high and low */
03217   LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
03218                                   tmp_awd_low_threshold_shifted);
03219
03220   /* Process unlocked */
03221   __HAL_UNLOCK(hadc);
03222
03223   /* Return function status */
03224   return tmp_hal_status;
03225 }
03226
03227
03228 /**
03229   * @}
03230   */
03231
03232 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
03233   *  @brief    ADC Peripheral State functions
03234   *
03235 @verbatim
03236  ===============================================================================
03237             ##### Peripheral state and errors functions #####
03238  ===============================================================================
03239     [..]
03240     This subsection provides functions to get in run-time the status of the
03241     peripheral.
03242       (+) Check the ADC state
03243       (+) Check the ADC error code
03244
03245 @endverbatim
03246   * @{
03247   */
03248
03249 /**
03250   * @brief  Return the ADC handle state.
03251   * @note   ADC state machine is managed by bitfields, ADC status must be
03252   *         compared with states bits.
03253   *         For example:
03254   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
03255   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
03256   * @param hadc ADC handle
03257   * @retval ADC handle state (bitfield on 32 bits)
03258   */
03259 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
03260 {
03261   /* Check the parameters */
03262   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03263
03264   /* Return ADC handle state */
03265   return hadc->State;
03266 }
03267
03268 /**
03269   * @brief  Return the ADC error code.
03270   * @param hadc ADC handle
03271   * @retval ADC error code (bitfield on 32 bits)
03272   */
03273 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
03274 {
03275   /* Check the parameters */
03276   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03277
03278   return hadc->ErrorCode;
03279 }
03280
03281 /**
03282   * @}
03283   */
03284
03285 /**
03286   * @}
03287   */
03288
03289 /** @defgroup ADC_Private_Functions ADC Private Functions
03290   * @{
03291   */
03292
03293 /**
03294   * @brief  Stop ADC conversion.
03295   * @param hadc ADC handle
03296   * @param ConversionGroup ADC group regular and/or injected.
03297   *          This parameter can be one of the following values:
03298   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
03299   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
03300   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
03301   * @retval HAL status.
03302   */
03303 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
03304 {
03305   uint32_t tickstart;
03306   uint32_t Conversion_Timeout_CPU_cycles = 0UL;
03307   uint32_t conversion_group_reassigned = ConversionGroup;
03308   uint32_t tmp_ADC_CR_ADSTART_JADSTART;
03309   uint32_t tmp_adc_is_conversion_on_going_regular;
03310   uint32_t tmp_adc_is_conversion_on_going_injected;
03311
03312   /* Check the parameters */
03313   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
03314   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
03315
03316   /* Verification if ADC is not already stopped (on regular and injected      */
03317   /* groups) to bypass this function if not needed.                           */
03318   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
03319   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
03320   if ((tmp_adc_is_conversion_on_going_regular != 0UL)
03321       || (tmp_adc_is_conversion_on_going_injected != 0UL)
03322      )
03323   {
03324     /* Particular case of continuous auto-injection mode combined with        */
03325     /* auto-delay mode.                                                       */
03326     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
03327     /* injected group stop ADC_CR_JADSTP).                                    */
03328     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
03329     /* (see reference manual).                                                */
03330     if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
03331         && (hadc->Init.ContinuousConvMode == ENABLE)
03332         && (hadc->Init.LowPowerAutoWait == ENABLE)
03333        )
03334     {
03335       /* Use stop of regular group */
03336       conversion_group_reassigned = ADC_REGULAR_GROUP;
03337
03338       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
03339       while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
03340       {
03341         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
03342         {
03343           /* Update ADC state machine to error */
03344           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03345
03346           /* Set ADC error code to ADC peripheral internal error */
03347           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03348
03349           return HAL_ERROR;
03350         }
03351         Conversion_Timeout_CPU_cycles ++;
03352       }
03353
03354       /* Clear JEOS */
03355       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
03356     }
03357
03358     /* Stop potential conversion on going on ADC group regular */
03359     if (conversion_group_reassigned != ADC_INJECTED_GROUP)
03360     {
03361       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
03362       if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
03363       {
03364         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
03365         {
03366           /* Stop ADC group regular conversion */
03367           LL_ADC_REG_StopConversion(hadc->Instance);
03368         }
03369       }
03370     }
03371
03372     /* Stop potential conversion on going on ADC group injected */
03373     if (conversion_group_reassigned != ADC_REGULAR_GROUP)
03374     {
03375       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
03376       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
03377       {
03378         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
03379         {
03380           /* Stop ADC group injected conversion */
03381           LL_ADC_INJ_StopConversion(hadc->Instance);
03382         }
03383       }
03384     }
03385
03386     /* Selection of start and stop bits with respect to the regular or injected group */
03387     switch (conversion_group_reassigned)
03388     {
03389       case ADC_REGULAR_INJECTED_GROUP:
03390         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
03391         break;
03392       case ADC_INJECTED_GROUP:
03393         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
03394         break;
03395       /* Case ADC_REGULAR_GROUP only*/
03396       default:
03397         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
03398         break;
03399     }
03400
03401     /* Wait for conversion effectively stopped */
03402     tickstart = HAL_GetTick();
03403
03404     while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
03405     {
03406       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
03407       {
03408         /* New check to avoid false timeout detection in case of preemption */
03409         if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
03410         {
03411           /* Update ADC state machine to error */
03412           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03413
03414           /* Set ADC error code to ADC peripheral internal error */
03415           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03416
03417           return HAL_ERROR;
03418         }
03419       }
03420     }
03421
03422   }
03423
03424   /* Return HAL status */
03425   return HAL_OK;
03426 }
03427
03428 /**
03429   * @brief  Enable the selected ADC.
03430   * @note   Prerequisite condition to use this function: ADC must be disabled
03431   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
03432   * @param hadc ADC handle
03433   * @retval HAL status.
03434   */
03435 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
03436 {
03437   uint32_t tickstart;
03438   __IO uint32_t wait_loop_index = 0UL;
03439
03440   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
03441   /* enabling phase not yet completed: flag ADC ready not yet set).           */
03442   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
03443   /* causes: ADC clock not running, ...).                                     */
03444   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03445   {
03446     /* Check if conditions to enable the ADC are fulfilled */
03447     if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
03448                                | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
03449     {
03450       /* Update ADC state machine to error */
03451       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03452
03453       /* Set ADC error code to ADC peripheral internal error */
03454       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03455
03456       return HAL_ERROR;
03457     }
03458
03459     /* Enable the ADC peripheral */
03460     LL_ADC_Enable(hadc->Instance);
03461
03462     if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
03463          & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
03464     {
03465       /* Delay for temperature sensor buffer stabilization time */
03466       /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of      */
03467       /*       LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed      */
03468       /*       in case of ADC enable after a system wake up               */
03469       /*       from low power mode.                                       */
03470
03471       /* Wait loop initialization and execution */
03472       /* Note: Variable divided by 2 to compensate partially              */
03473       /*       CPU processing cycles, scaling in us split to not          */
03474       /*       exceed 32 bits register capacity and handle low frequency. */
03475       wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
03476       while (wait_loop_index != 0UL)
03477       {
03478         wait_loop_index--;
03479       }
03480     }
03481
03482     /* Wait for ADC effectively enabled */
03483     tickstart = HAL_GetTick();
03484
03485     while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
03486     {
03487       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
03488           has been cleared (after a calibration), ADEN bit is reset by the
03489           calibration logic.
03490           The workaround is to continue setting ADEN until ADRDY is becomes 1.
03491           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
03492           4 ADC clock cycle duration */
03493       /* Note: Test of ADC enabled required due to hardware constraint to     */
03494       /*       not enable ADC if already enabled.                             */
03495       if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03496       {
03497         LL_ADC_Enable(hadc->Instance);
03498       }
03499
03500       if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
03501       {
03502         /* New check to avoid false timeout detection in case of preemption */
03503         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
03504         {
03505           /* Update ADC state machine to error */
03506           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03507
03508           /* Set ADC error code to ADC peripheral internal error */
03509           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03510
03511           return HAL_ERROR;
03512         }
03513       }
03514     }
03515   }
03516
03517   /* Return HAL status */
03518   return HAL_OK;
03519 }
03520
03521 /**
03522   * @brief  Disable the selected ADC.
03523   * @note   Prerequisite condition to use this function: ADC conversions must be
03524   *         stopped.
03525   * @param hadc ADC handle
03526   * @retval HAL status.
03527   */
03528 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
03529 {
03530   uint32_t tickstart;
03531   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
03532
03533   /* Verification if ADC is not already disabled:                             */
03534   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
03535   /*       disabled.                                                          */
03536   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
03537       && (tmp_adc_is_disable_on_going == 0UL)
03538      )
03539   {
03540     /* Check if conditions to disable the ADC are fulfilled */
03541     if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
03542     {
03543       /* Disable the ADC peripheral */
03544       LL_ADC_Disable(hadc->Instance);
03545       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
03546     }
03547     else
03548     {
03549       /* Update ADC state machine to error */
03550       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03551
03552       /* Set ADC error code to ADC peripheral internal error */
03553       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03554
03555       return HAL_ERROR;
03556     }
03557
03558     /* Wait for ADC effectively disabled */
03559     /* Get tick count */
03560     tickstart = HAL_GetTick();
03561
03562     while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
03563     {
03564       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
03565       {
03566         /* New check to avoid false timeout detection in case of preemption */
03567         if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
03568         {
03569           /* Update ADC state machine to error */
03570           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03571
03572           /* Set ADC error code to ADC peripheral internal error */
03573           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03574
03575           return HAL_ERROR;
03576         }
03577       }
03578     }
03579   }
03580
03581   /* Return HAL status */
03582   return HAL_OK;
03583 }
03584
03585 /**
03586   * @brief  DMA transfer complete callback.
03587   * @param hdma pointer to DMA handle.
03588   * @retval None
03589   */
03590 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
03591 {
03592   /* Retrieve ADC handle corresponding to current DMA handle */
03593   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03594
03595   /* Update state machine on conversion status if not in error state */
03596   if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
03597   {
03598     /* Set ADC state */
03599     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
03600
03601     /* Determine whether any further conversion upcoming on group regular     */
03602     /* by external trigger, continuous mode or scan sequence on going         */
03603     /* to disable interruption.                                               */
03604     /* Is it the end of the regular sequence ? */
03605     if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
03606     {
03607       /* Are conversions software-triggered ? */
03608       if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
03609       {
03610         /* Is CONT bit set ? */
03611         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
03612         {
03613           /* CONT bit is not set, no more conversions expected */
03614           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03615           if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03616           {
03617             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03618           }
03619         }
03620       }
03621     }
03622     else
03623     {
03624       /* DMA End of Transfer interrupt was triggered but conversions sequence
03625          is not over. If DMACFG is set to 0, conversions are stopped. */
03626       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
03627       {
03628         /* DMACFG bit is not set, conversions are stopped. */
03629         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03630         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03631         {
03632           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03633         }
03634       }
03635     }
03636
03637     /* Conversion complete callback */
03638 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03639     hadc->ConvCpltCallback(hadc);
03640 #else
03641     HAL_ADC_ConvCpltCallback(hadc);
03642 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03643   }
03644   else /* DMA and-or internal error occurred */
03645   {
03646     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
03647     {
03648       /* Call HAL ADC Error Callback function */
03649 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03650       hadc->ErrorCallback(hadc);
03651 #else
03652       HAL_ADC_ErrorCallback(hadc);
03653 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03654     }
03655     else
03656     {
03657       /* Call ADC DMA error callback */
03658       hadc->DMA_Handle->XferErrorCallback(hdma);
03659     }
03660   }
03661 }
03662
03663 /**
03664   * @brief  DMA half transfer complete callback.
03665   * @param hdma pointer to DMA handle.
03666   * @retval None
03667   */
03668 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
03669 {
03670   /* Retrieve ADC handle corresponding to current DMA handle */
03671   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03672
03673   /* Half conversion callback */
03674 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03675   hadc->ConvHalfCpltCallback(hadc);
03676 #else
03677   HAL_ADC_ConvHalfCpltCallback(hadc);
03678 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03679 }
03680
03681 /**
03682   * @brief  DMA error callback.
03683   * @param hdma pointer to DMA handle.
03684   * @retval None
03685   */
03686 void ADC_DMAError(DMA_HandleTypeDef *hdma)
03687 {
03688   /* Retrieve ADC handle corresponding to current DMA handle */
03689   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03690
03691   /* Set ADC state */
03692   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
03693
03694   /* Set ADC error code to DMA error */
03695   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
03696
03697   /* Error callback */
03698 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03699   hadc->ErrorCallback(hadc);
03700 #else
03701   HAL_ADC_ErrorCallback(hadc);
03702 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03703 }
03704
03705 /**
03706   * @}
03707   */
03708
03709 #endif /* HAL_ADC_MODULE_ENABLED */
03710 /**
03711   * @}
03712   */
03713
03714 /**
03715   * @}
03716   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_adc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_ADC_H
00021 #define STM32G4xx_HAL_ADC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /* Include low level driver */
00031 #include "stm32g4xx_ll_adc.h"
00032
00033 /** @addtogroup STM32G4xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup ADC
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup ADC_Exported_Types ADC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  ADC group regular oversampling structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00052                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
00053
00054   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00055                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00056
00057   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00058                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
00059
00060   uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
00061                                                The oversampling is either temporary stopped or reset upon an injected
00062                                                sequence interruption.
00063                                                If oversampling is enabled on both regular and injected groups, this
00064                                                parameter is discarded and forced to setting
00065                                                "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
00066                                                during injection sequence).
00067                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
00068
00069 } ADC_OversamplingTypeDef;
00070
00071 /**
00072   * @brief  Structure definition of ADC instance and ADC group regular.
00073   * @note   Parameters of this structure are shared within 2 scopes:
00074   *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
00075   *            GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
00076   *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
00077   *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling,
00078   *            SamplingMode.
00079   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
00080   *         ADC state can be either:
00081   *          - For all parameters: ADC disabled
00082   *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled
00083   *            without conversion on going on group regular.
00084   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
00085   *            on groups regular and injected.
00086   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00087   *         without error reporting (as it can be the expected behavior in case of intended action to update another
00088   *         parameter (which fulfills the ADC state condition) on the fly).
00089   */
00090 typedef struct
00091 {
00092   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
00093                                        clock derived from system clock or PLL (Refer to reference manual for list of
00094                                        clocks available)) and clock prescaler.
00095                                        This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
00096                                        Note: The ADC clock configuration is common to all ADC instances.
00097                                        Note: In case of usage of channels on injected group, ADC frequency should be
00098                                              lower than AHB clock frequency /4 for resolution 12 or 10 bits,
00099                                                         AHB clock frequency /3 for resolution 8 bits,
00100                                                         AHB clock frequency /2 for resolution 6 bits.
00101                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must
00102                                              be enabled only if the system clock has a 50% duty clock cycle (APB
00103                                              prescaler configured inside RCC  must be bypassed and PCLK clock must have
00104                                              50% duty cycle). Refer to reference manual for details.
00105                                        Note: In case of usage of asynchronous clock, the selected clock must be
00106                                              preliminarily enabled at RCC top level.
00107                                        Note: This parameter can be modified only if all ADC instances are disabled. */
00108
00109   uint32_t Resolution;            /*!< Configure the ADC resolution.
00110                                        This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
00111
00112   uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
00113                                        Refer to reference manual for alignments formats versus resolutions.
00114                                        This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
00115
00116   uint32_t GainCompensation;      /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion
00117                                        data, based on following formula:
00118                                          DATA = DATA(raw) * (gain compensation coef) / 4096
00119                                        "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa
00120                                        Gain step is 1/4096 = 0.000244
00121                                        Gain range is 0.0000 to 3.999756
00122                                        This parameter value can be
00123                                         0           Gain compensation will be disabled and coefficient set to 0
00124                                         1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified
00125                                                     value
00126                                        Note: Gain compensation when enabled is applied to all channels. */
00127
00128   uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
00129                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have
00130                                        main sequence subdivided in successive parts.
00131                                        If disabled: Conversion is performed in single mode (one channel converted, the
00132                                                     one defined in rank 1). Parameters 'NbrOfConversion' and
00133                                                     'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00134                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined
00135                                                     by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each
00136                                                     channel in sequencer). Scan direction is upward: from rank 1 to
00137                                                     rank 'n'.
00138                                        This parameter can be a value of @ref ADC_Scan_mode */
00139
00140   uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
00141                                        interruption: end of unitary conversion or end of sequence conversions.
00142                                        This parameter can be a value of @ref ADC_EOCSelection. */
00143
00144   FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
00145                                        previous conversion (for ADC group regular) or previous sequence (for ADC group
00146                                        injected) has been retrieved by user software, using function HAL_ADC_GetValue()
00147                                        or HAL_ADCEx_InjectedGetValue().
00148                                        This feature automatically adapts the frequency of ADC conversions triggers to
00149                                        the speed of the system that reads the data. Moreover, this avoids risk of
00150                                        overrun for low frequency applications.
00151                                        This parameter can be set to ENABLE or DISABLE.
00152                                        Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
00153                                              HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
00154                                              flag (by CPU to free the IRQ pending event or by DMA).
00155                                              Auto wait will work but fort a very short time, discarding its intended
00156                                              benefit (except specific case of high load of CPU or DMA transfers which
00157                                              can justify usage of auto wait).
00158                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
00159                                              when ADC conversion data is needed:
00160                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and
00161                                              HAL_ADC_GetValue() to retrieve conversion result and trig another
00162                                              conversion start. (in case of usage of ADC group injected, use the
00163                                              equivalent functions HAL_ADCExInjected_Start(),
00164                                              HAL_ADCEx_InjectedGetValue(), ...). */
00165
00166   FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
00167                                            or continuous mode for ADC group regular, after the first ADC conversion
00168                                            start trigger occurred (software start or external trigger). This parameter
00169                                            can be set to ENABLE or DISABLE. */
00170
00171   uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group
00172                                        sequencer.
00173                                        This parameter is dependent on ScanConvMode:
00174                                         - sequencer configured to fully configurable:
00175                                           Number of ranks in the scan sequence is configurable using this parameter.
00176                                           Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
00177                                                 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
00178                                                 Afterwards, when all needed sequencer ranks are set, parameter
00179                                                 'NbrOfConversion' can be updated without modifying configuration of
00180                                                 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
00181                                         - sequencer configured to not fully configurable:
00182                                           Number of ranks in the scan sequence is defined by number of channels set in
00183                                           the sequence. This parameter is discarded.
00184                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8.
00185                                        Note: This parameter must be modified when no conversion is on going on regular
00186                                              group (ADC disabled, or ADC enabled without continuous mode or external
00187                                              trigger that could launch a conversion). */
00188
00189   FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
00190                                               in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
00191                                               successive parts).
00192                                               Discontinuous mode is used only if sequencer is enabled (parameter
00193                                               'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00194                                               Discontinuous mode can be enabled only if continuous mode is disabled.
00195                                               If continuous mode is enabled, this parameter setting is discarded.
00196                                               This parameter can be set to ENABLE or DISABLE.
00197                                               Note: On this STM32 series, ADC group regular number of discontinuous
00198                                                     ranks increment is fixed to one-by-one. */
00199
00200   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence
00201                                        of ADC group regular (parameter NbrOfConversion) will be subdivided.
00202                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00203                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00204
00205   uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion
00206                                        start.
00207                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
00208                                        is used instead.
00209                                        This parameter can be a value of @ref ADC_regular_external_trigger_source.
00210                                        Caution: external trigger source is common to all ADC instances. */
00211
00212   uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start
00213                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
00214                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
00215
00216   uint32_t SamplingMode;          /*!< Select the sampling mode to be used for ADC group regular conversion.
00217                                        This parameter can be a value of @ref ADC_regular_sampling_mode */
00218
00219   FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
00220                                               transfer stops when number of conversions is reached) or in continuous
00221                                               mode (DMA transfer unlimited, whatever number of conversions).
00222                                               This parameter can be set to ENABLE or DISABLE.
00223                                               Note: In continuous mode, DMA must be configured in circular mode.
00224                                                     Otherwise an overrun will be triggered when DMA buffer maximum
00225                                                     pointer is reached. */
00226
00227   uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
00228                                        This parameter applies to ADC group regular only.
00229                                        This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
00230                                        Note: In case of overrun set to data preserved and usage with programming model
00231                                              with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
00232                                              conversion flags, this induces the release of the preserved data. If
00233                                              needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
00234                                              placed in user program code (called before end of conversion flags clear)
00235                                        Note: Error reporting with respect to the conversion mode:
00236                                              - Usage with ADC conversion by polling for event or interruption: Error is
00237                                                reported only if overrun is set to data preserved. If overrun is set to
00238                                                data overwritten, user can willingly not read all the converted data,
00239                                                this is not considered as an erroneous case.
00240                                              - Usage with ADC conversion by DMA: Error is reported whatever overrun
00241                                                setting (DMA is expected to process all data from data register). */
00242
00243   FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
00244                                                This parameter can be set to ENABLE or DISABLE.
00245                                                Note: This parameter can be modified only if there is no conversion is
00246                                                      ongoing on ADC groups regular and injected */
00247
00248   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
00249                                                Caution: this setting overwrites the previous oversampling configuration
00250                                                         if oversampling is already enabled. */
00251
00252 } ADC_InitTypeDef;
00253
00254 /**
00255   * @brief  Structure definition of ADC channel for regular group
00256   * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00257   *         ADC state can be either:
00258   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00259   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
00260   *            on going on regular group.
00261   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
00262   *            regular and injected groups.
00263   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00264   *         without error reporting (as it can be the expected behavior in case of intended action to update another
00265   *         parameter (which fulfills the ADC state condition) on the fly).
00266   */
00267 typedef struct
00268 {
00269   uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
00270                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00271                                         Note: Depending on devices and ADC instances, some channels may not be available
00272                                               on device package pins. Refer to device datasheet for channels
00273                                               availability. */
00274
00275   uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
00276                                         This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
00277                                         Note: to disable a channel or change order of conversion sequencer, rank
00278                                         containing a previous channel setting can be overwritten by the new channel
00279                                         setting (or parameter number of conversions adjusted) */
00280
00281   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00282                                         Unit: ADC clock cycles
00283                                         Conversion time is the addition of sampling time and processing time
00284                                         (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
00285                                         8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00286                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
00287                                         Caution: This parameter applies to a channel that can be used into regular
00288                                                  and/or injected group. It overwrites the last setting.
00289                                         Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...),
00290                                               sampling time constraints must be respected (sampling time can be adjusted
00291                                               in function of ADC clock frequency and sampling time setting).
00292                                               Refer to device datasheet for timings values. */
00293
00294   uint32_t SingleDiff;             /*!< Select single-ended or differential input.
00295                                         In differential mode: Differential measurement is carried out between the
00296                                         selected channel 'i' (positive input) and channel 'i+1' (negative input).
00297                                         Only channel 'i' has to be configured, channel 'i+1' is configured automatically
00298                                         This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
00299                                         Caution: This parameter applies to a channel that can be used in a regular
00300                                                  and/or injected group.
00301                                                  It overwrites the last setting.
00302                                         Note: Refer to Reference Manual to ensure the selected channel is available in
00303                                               differential mode.
00304                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is
00305                                               not usable separately.
00306                                         Note: This parameter must be modified when ADC is disabled (before ADC start
00307                                               conversion or after ADC stop conversion).
00308                                               If ADC is enabled, this parameter setting is bypassed without error
00309                                               reporting (as it can be the expected behavior in case of another parameter
00310                                               update on the fly) */
00311
00312   uint32_t OffsetNumber;           /*!< Select the offset number
00313                                         This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
00314                                         Caution: Only one offset is allowed per channel. This parameter overwrites the
00315                                                  last setting. */
00316
00317   uint32_t Offset;                 /*!< Define the offset to be applied on the raw converted data.
00318                                         Offset value must be a positive number.
00319                                         Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
00320                                         must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00321                                         0x3FF, 0xFF or 0x3F respectively.
00322                                         Note: This parameter must be modified when no conversion is on going on both
00323                                               regular and injected groups (ADC disabled, or ADC enabled without
00324                                               continuous mode or external trigger that could launch a conversion). */
00325
00326   uint32_t OffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive
00327                                             sign) from or to the raw converted data.
00328                                             This parameter can be a value of @ref ADCEx_OffsetSign.
00329                                             Note: This parameter must be modified when no conversion is on going on both
00330                                                   regular and injected groups (ADC disabled, or ADC enabled without
00331                                                   continuous mode or external trigger that could launch a conversion).*/
00332   FunctionalState OffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
00333                                         This parameter value can be ENABLE or DISABLE.
00334                                         Note: This parameter must be modified when no conversion is on going on both
00335                                               regular and injected groups (ADC disabled, or ADC enabled without
00336                                               continuous mode or external trigger that could launch a conversion). */
00337
00338 } ADC_ChannelConfTypeDef;
00339
00340 /**
00341   * @brief  Structure definition of ADC analog watchdog
00342   * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00343   *         ADC state can be either:
00344   *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
00345                on going on ADC groups regular and injected.
00346   *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and
00347                injected groups.
00348   */
00349 typedef struct
00350 {
00351   uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
00352                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
00353                                                           by setting parameter 'WatchdogMode')
00354                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
00355                                                                 of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00356                                    This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
00357
00358   uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
00359                                    For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
00360                                                           channels, ADC groups regular and-or injected.
00361                                    For Analog Watchdog 2 and 3: Several channels can be monitored by applying
00362                                                                 successively the AWD init structure. Channels on ADC
00363                                                                 group regular and injected are not differentiated: Set
00364                                                                 value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
00365                                                                 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
00366                                                                 all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
00367                                                                 channel.
00368                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
00369
00370   uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
00371                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
00372                                                           is configured on single channel (only 1 channel can be
00373                                                           monitored).
00374                                    For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
00375                                                                 call successively the function HAL_ADC_AnalogWDGConfig()
00376                                                                 for each channel to be added (or removed with value
00377                                                                 'ADC_ANALOGWATCHDOG_NONE').
00378                                    This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
00379
00380   FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
00381                                    This parameter can be set to ENABLE or DISABLE */
00382
00383   uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
00384                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
00385                                    number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
00386                                    respectively.
00387                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
00388                                          resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
00389                                          LSB are ignored.
00390                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00391                                          impacted: the comparison of analog watchdog thresholds is done on
00392                                          oversampling final computation (after ratio and shift application):
00393                                          ADC data register bitfield [15:4] (12 most significant bits). */
00394
00395   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00396                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
00397                                    number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
00398                                    respectively.
00399                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
00400                                          resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
00401                                          LSB are ignored.
00402                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00403                                          impacted: the comparison of analog watchdog thresholds is done on
00404                                          oversampling final computation (after ratio and shift application):
00405                                          ADC data register bitfield [15:4] (12 most significant bits).*/
00406
00407   uint32_t FilteringConfig;   /*!< Specify whether filtering should be use and the number of samples to consider.
00408                                    Before setting flag or raising interrupt, analog watchdog can wait to have several
00409                                    consecutive out-of-window samples. This parameter allows to configure this number.
00410                                    This parameter only applies to Analog watchdog 1. For others, use value
00411                                    ADC_AWD_FILTERING_NONE.
00412                                    This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
00413 } ADC_AnalogWDGConfTypeDef;
00414
00415 /**
00416   * @brief  ADC group injected contexts queue configuration
00417   * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"
00418   */
00419 typedef struct
00420 {
00421   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00422                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00423                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00424
00425   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00426 } ADC_InjectionConfigTypeDef;
00427
00428 /** @defgroup ADC_States ADC States
00429   * @{
00430   */
00431
00432 /**
00433   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00434   * @note   ADC state machine is managed by bitfields, state must be compared
00435   *         with bit by bit.
00436   *         For example:
00437   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
00438   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
00439   */
00440 /* States of ADC global scope */
00441 #define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
00442 #define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
00443 #define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization,
00444                                                               calibration, ...) */
00445 #define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
00446
00447 /* States of ADC errors */
00448 #define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
00449 #define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
00450 #define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
00451
00452 /* States of ADC group regular */
00453 #define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur
00454                                                               (either by continuous mode, external trigger, low power
00455                                                               auto power-on (if feature available), multimode ADC master
00456                                                               control (if feature available)) */
00457 #define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
00458 #define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
00459 #define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag
00460                                                               raised  */
00461
00462 /* States of ADC group injected */
00463 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur
00464                                                               (either by auto-injection mode, external trigger, low
00465                                                               power auto power-on (if feature available), multimode
00466                                                               ADC master control (if feature available)) */
00467 #define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
00468 #define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */
00469
00470 /* States of ADC analog watchdogs */
00471 #define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
00472 #define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
00473 #define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
00474
00475 /* States of ADC multi-mode */
00476 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another ADC
00477                                                               master (when feature available) */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @brief  ADC handle Structure definition
00485   */
00486 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00487 typedef struct __ADC_HandleTypeDef
00488 #else
00489 typedef struct
00490 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00491 {
00492   ADC_TypeDef                   *Instance;                     /*!< Register base address */
00493   ADC_InitTypeDef               Init;                          /*!< ADC initialization parameters and regular
00494                                                                     conversions setting */
00495   DMA_HandleTypeDef             *DMA_Handle;                   /*!< Pointer DMA Handler */
00496   HAL_LockTypeDef               Lock;                          /*!< ADC locking object */
00497   __IO uint32_t                 State;                         /*!< ADC communication state (bitmap of ADC states) */
00498   __IO uint32_t                 ErrorCode;                     /*!< ADC Error code */
00499   ADC_InjectionConfigTypeDef    InjectionConfig ;              /*!< ADC injected channel configuration build-up
00500                                                                   structure */
00501 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00502   void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
00503   void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer
00504                                                                                  callback */
00505   void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
00506   void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
00507   void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete
00508                                                                                  callback */
00509   void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
00510                                                                                  overflow callback */
00511   void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
00512   void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
00513   void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
00514   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
00515   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
00516 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00517 } ADC_HandleTypeDef;
00518
00519 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00520 /**
00521   * @brief  HAL ADC Callback ID enumeration definition
00522   */
00523 typedef enum
00524 {
00525   HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
00526   HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
00527   HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
00528   HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
00529   HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
00530   HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */
00531   HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
00532   HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
00533   HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
00534   HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
00535   HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
00536 } HAL_ADC_CallbackIDTypeDef;
00537
00538 /**
00539   * @brief  HAL ADC Callback pointer definition
00540   */
00541 typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
00542
00543 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00544
00545 /**
00546   * @}
00547   */
00548
00549
00550 /* Exported constants --------------------------------------------------------*/
00551
00552 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00553   * @{
00554   */
00555
00556 /** @defgroup ADC_Error_Code ADC Error Code
00557   * @{
00558   */
00559 #define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
00560 #define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
00561                                                        enable/disable, erroneous state, ...)       */
00562 #define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
00563 #define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
00564 #define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */
00565 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00566 #define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
00567 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00573   * @{
00574   */
00575
00576 #define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock from AHB clock
00577                                            without prescaler */
00578 #define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock from AHB clock
00579                                            with prescaler division by 2 */
00580 #define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock from AHB clock
00581                                            with prescaler division by 4 */
00582 #define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without
00583                                            prescaler */
00584 #define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler
00585                                            division by 2   */
00586 #define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler
00587                                            division by 4   */
00588 #define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler
00589                                            division by 6   */
00590 #define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler
00591                                            division by 8   */
00592 #define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler
00593                                            division by 10  */
00594 #define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler
00595                                            division by 12  */
00596 #define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler
00597                                            division by 16  */
00598 #define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler
00599                                            division by 32  */
00600 #define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler
00601                                            division by 64  */
00602 #define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler
00603                                            division by 128 */
00604 #define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler
00605                                            division by 256 */
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
00611   * @{
00612   */
00613 #define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
00614 #define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
00615 #define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
00616 #define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
00617 /**
00618   * @}
00619   */
00620
00621 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
00622   * @{
00623   */
00624 #define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
00625                                            (alignment on data register LSB bit 0)*/
00626 #define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)  /*!< ADC conversion data alignment: left aligned
00627                                            (alignment on data register MSB bit 15)*/
00628 /**
00629   * @}
00630   */
00631
00632 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
00633   * @{
00634   */
00635 #define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
00636 #define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
00642   * @{
00643   */
00644 /* ADC group regular trigger sources for all ADC instances */
00645 #define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                  /*!< ADC group regular conversion
00646                                       trigger software start */
00647 #define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             /*!< ADC group regular conversion
00648                                       trigger from external peripheral: TIM1 TRGO. */
00649 #define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            /*!< ADC group regular conversion
00650                                       trigger from external peripheral: TIM1 TRGO2. */
00651 #define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)              /*!< ADC group regular conversion
00652                                       trigger from external peripheral: TIM1 channel 1 event (capture compare). */
00653 #define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)              /*!< ADC group regular conversion
00654                                       trigger from external peripheral: TIM1 channel 2 event (capture compare). */
00655 #define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)              /*!< ADC group regular conversion
00656                                       trigger from external peripheral: TIM1 channel 3 event (capture compare). */
00657 #define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)             /*!< ADC group regular conversion
00658                                       trigger from external peripheral: TIM2 TRGO. */
00659 #define ADC_EXTERNALTRIG_T2_CC1       (LL_ADC_REG_TRIG_EXT_TIM2_CH1)              /*!< ADC group regular conversion
00660                                       trigger from external peripheral: TIM2 channel 1 event (capture compare). */
00661 #define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)              /*!< ADC group regular conversion
00662                                       trigger from external peripheral: TIM2 channel 2 event (capture compare). */
00663 #define ADC_EXTERNALTRIG_T2_CC3       (LL_ADC_REG_TRIG_EXT_TIM2_CH3)              /*!< ADC group regular conversion
00664                                       trigger from external peripheral: TIM2 channel 3 event (capture compare). */
00665 #define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)             /*!< ADC group regular conversion
00666                                       trigger from external peripheral: TIM3 TRGO. */
00667 #define ADC_EXTERNALTRIG_T3_CC1       (LL_ADC_REG_TRIG_EXT_TIM3_CH1)              /*!< ADC group regular conversion
00668                                       trigger from external peripheral: TIM3 channel 1 event (capture compare). */
00669 #define ADC_EXTERNALTRIG_T3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)              /*!< ADC group regular conversion
00670                                       trigger from external peripheral: TIM3 channel 4 event (capture compare). */
00671 #define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             /*!< ADC group regular conversion
00672                                       trigger from external peripheral: TIM4 TRGO. */
00673 #define ADC_EXTERNALTRIG_T4_CC1       (LL_ADC_REG_TRIG_EXT_TIM4_CH1)              /*!< ADC group regular conversion
00674                                       trigger from external peripheral: TIM4 channel 1 event (capture compare). */
00675 #define ADC_EXTERNALTRIG_T4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)              /*!< ADC group regular conversion
00676                                       trigger from external peripheral: TIM4 channel 4 event (capture compare). */
00677 #define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)             /*!< ADC group regular conversion
00678                                       trigger from external peripheral: TIM6 TRGO. */
00679 #define ADC_EXTERNALTRIG_T7_TRGO      (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)             /*!< ADC group regular conversion
00680                                       trigger from external peripheral: TIM7 TRGO. */
00681 #define ADC_EXTERNALTRIG_T8_TRGO      (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)             /*!< ADC group regular conversion
00682                                       trigger from external peripheral: TIM8 TRGO. */
00683 #define ADC_EXTERNALTRIG_T8_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            /*!< ADC group regular conversion
00684                                       trigger from external peripheral: TIM8 TRGO2. */
00685 #define ADC_EXTERNALTRIG_T8_CC1       (LL_ADC_REG_TRIG_EXT_TIM8_CH1)              /*!< ADC group regular conversion
00686                                       trigger from external peripheral: TIM8 channel 1 event (capture compare). */
00687 #define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            /*!< ADC group regular conversion
00688                                       trigger from external peripheral: TIM15 TRGO. */
00689 #define ADC_EXTERNALTRIG_T20_TRGO     (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)            /*!< ADC group regular conversion
00690                                       trigger from external peripheral: TIM20 TRGO. */
00691 #define ADC_EXTERNALTRIG_T20_TRGO2    (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)           /*!< ADC group regular conversion
00692                                       trigger from external peripheral: TIM20 TRGO2. */
00693 #define ADC_EXTERNALTRIG_T20_CC1      (LL_ADC_REG_TRIG_EXT_TIM20_CH1)             /*!< ADC group regular conversion
00694                                       trigger from external peripheral: TIM20 channel 1 event (capture compare). */
00695 #define ADC_EXTERNALTRIG_T20_CC2      (LL_ADC_REG_TRIG_EXT_TIM20_CH2)             /*!< ADC group regular conversion
00696                                       trigger from external peripheral: TIM20 channel 2 event (capture compare). */
00697 #define ADC_EXTERNALTRIG_T20_CC3      (LL_ADC_REG_TRIG_EXT_TIM20_CH3)             /*!< ADC group regular conversion
00698                                       trigger from external peripheral: TIM20 channel 3 event (capture compare). */
00699 #define ADC_EXTERNALTRIG_HRTIM_TRG1   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)            /*!< ADC group regular conversion
00700                                       trigger from external peripheral: HRTIMER ADC trigger 1 event. */
00701 #define ADC_EXTERNALTRIG_HRTIM_TRG2   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)            /*!< ADC group regular conversion
00702                                       trigger from external peripheral: HRTIMER ADC trigger 2 event. */
00703 #define ADC_EXTERNALTRIG_HRTIM_TRG3   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)            /*!< ADC group regular conversion
00704                                       trigger from external peripheral: HRTIMER ADC trigger 3 event. */
00705 #define ADC_EXTERNALTRIG_HRTIM_TRG4   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)            /*!< ADC group regular conversion
00706                                       trigger from external peripheral: HRTIMER ADC trigger 4 event. */
00707 #define ADC_EXTERNALTRIG_HRTIM_TRG5   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)            /*!< ADC group regular conversion
00708                                       trigger from external peripheral: HRTIMER ADC trigger 5 event. */
00709 #define ADC_EXTERNALTRIG_HRTIM_TRG6   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)            /*!< ADC group regular conversion
00710                                       trigger from external peripheral: HRTIMER ADC trigger 6 event. */
00711 #define ADC_EXTERNALTRIG_HRTIM_TRG7   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)            /*!< ADC group regular conversion
00712                                       trigger from external peripheral: HRTIMER ADC trigger 7 event. */
00713 #define ADC_EXTERNALTRIG_HRTIM_TRG8   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)            /*!< ADC group regular conversion
00714                                       trigger from external peripheral: HRTIMER ADC trigger 8 event. */
00715 #define ADC_EXTERNALTRIG_HRTIM_TRG9   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)            /*!< ADC group regular conversion
00716                                       trigger from external peripheral: HRTIMER ADC trigger 9 event. */
00717 #define ADC_EXTERNALTRIG_HRTIM_TRG10  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)           /*!< ADC group regular conversion
00718                                       trigger from external peripheral: HRTIMER ADC trigger 10 event. */
00719 #define ADC_EXTERNALTRIG_EXT_IT2      (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)            /*!< ADC group regular conversion
00720                                       trigger from external peripheral: external interrupt line 2. */
00721 #define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)           /*!< ADC group regular conversion
00722                                       trigger from external peripheral: external interrupt line 11. */
00723 #define ADC_EXTERNALTRIG_LPTIM_OUT    (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)             /*!< ADC group regular conversion
00724                                       trigger from external peripheral: LPTIMER OUT event. */
00725 /**
00726   * @}
00727   */
00728
00729 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
00730   * @{
00731   */
00732 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< ADC group regular trigger
00733                                                 disabled (SW start)*/
00734 #define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion
00735                                                 trigger polarity set to rising edge */
00736 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion
00737                                                 trigger polarity set to falling edge */
00738 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
00739                                                 trigger polarity set to both rising and falling edges */
00740 /**
00741   * @}
00742   */
00743
00744 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
00745   * @{
00746   */
00747 #define ADC_SAMPLING_MODE_NORMAL                (0x00000000UL)      /*!< ADC conversions sampling phase duration is
00748                                                 defined using  @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
00749 #define ADC_SAMPLING_MODE_BULB                  (ADC_CFGR2_BULB)    /*!< ADC conversions sampling phase starts
00750                                                 immediately after end of conversion, and stops upon trigger event.
00751                                                 Note: First conversion is using minimal sampling time
00752                                                       (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
00753 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED     (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled
00754                                                 by trigger events:
00755                                                 Trigger rising edge  = start sampling
00756                                                 Trigger falling edge = stop sampling and start conversion */
00757 /**
00758   * @}
00759   */
00760
00761 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
00762   * @{
00763   */
00764 #define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
00765 #define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00771   * @{
00772   */
00773 #define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case
00774                                            of overrun: data preserved */
00775 #define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case
00776                                            of overrun: data overwritten */
00777 /**
00778   * @}
00779   */
00780
00781 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00782   * @{
00783   */
00784 #define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
00785 #define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
00786 #define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
00787 #define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
00788 #define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
00789 #define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
00790 #define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
00791 #define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
00792 #define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
00793 #define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
00794 #define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
00795 #define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
00796 #define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
00797 #define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
00798 #define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
00799 #define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
00800 /**
00801   * @}
00802   */
00803
00804 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00805   * @{
00806   */
00807 #define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
00808 #define ADC_SAMPLETIME_6CYCLES_5         (LL_ADC_SAMPLINGTIME_6CYCLES_5)    /*!< Sampling time 6.5 ADC clock cycles */
00809 #define ADC_SAMPLETIME_12CYCLES_5        (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
00810 #define ADC_SAMPLETIME_24CYCLES_5        (LL_ADC_SAMPLINGTIME_24CYCLES_5)   /*!< Sampling time 24.5 ADC clock cycles */
00811 #define ADC_SAMPLETIME_47CYCLES_5        (LL_ADC_SAMPLINGTIME_47CYCLES_5)   /*!< Sampling time 47.5 ADC clock cycles */
00812 #define ADC_SAMPLETIME_92CYCLES_5        (LL_ADC_SAMPLINGTIME_92CYCLES_5)   /*!< Sampling time 92.5 ADC clock cycles */
00813 #define ADC_SAMPLETIME_247CYCLES_5       (LL_ADC_SAMPLINGTIME_247CYCLES_5)  /*!< Sampling time 247.5 ADC clock cycles */
00814 #define ADC_SAMPLETIME_640CYCLES_5       (LL_ADC_SAMPLINGTIME_640CYCLES_5)  /*!< Sampling time 640.5 ADC clock cycles */
00815 #define ADC_SAMPLETIME_3CYCLES_5         (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5
00816                                          ADC clock cycles. If selected, this sampling time replaces sampling time
00817                                          2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
00818 /**
00819   * @}
00820   */
00821
00822 /** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
00823   * @{
00824   */
00825 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
00826 /*        all ADC instances (refer to Reference Manual).                      */
00827 #define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)              /*!< External channel (GPIO pin) ADCx_IN0  */
00828 #define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)              /*!< External channel (GPIO pin) ADCx_IN1  */
00829 #define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)              /*!< External channel (GPIO pin) ADCx_IN2  */
00830 #define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)              /*!< External channel (GPIO pin) ADCx_IN3  */
00831 #define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)              /*!< External channel (GPIO pin) ADCx_IN4  */
00832 #define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)              /*!< External channel (GPIO pin) ADCx_IN5  */
00833 #define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)              /*!< External channel (GPIO pin) ADCx_IN6  */
00834 #define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)              /*!< External channel (GPIO pin) ADCx_IN7  */
00835 #define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)              /*!< External channel (GPIO pin) ADCx_IN8  */
00836 #define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)              /*!< External channel (GPIO pin) ADCx_IN9  */
00837 #define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)             /*!< External channel (GPIO pin) ADCx_IN10 */
00838 #define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)             /*!< External channel (GPIO pin) ADCx_IN11 */
00839 #define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)             /*!< External channel (GPIO pin) ADCx_IN12 */
00840 #define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)             /*!< External channel (GPIO pin) ADCx_IN13 */
00841 #define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)             /*!< External channel (GPIO pin) ADCx_IN14 */
00842 #define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)             /*!< External channel (GPIO pin) ADCx_IN15 */
00843 #define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)             /*!< External channel (GPIO pin) ADCx_IN16 */
00844 #define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)             /*!< External channel (GPIO pin) ADCx_IN17 */
00845 #define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)             /*!< External channel (GPIO pin) ADCx_IN18 */
00846 #define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)        /*!< Internal channel VrefInt: Internal
00847                                            voltage reference. On this STM32 series, ADC channel available on all
00848                                            instances but ADC2. */
00849 #define ADC_CHANNEL_TEMPSENSOR_ADC1        (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor.
00850                                            On this STM32 series, ADC channel available only on ADC1 instance. */
00851 #define ADC_CHANNEL_TEMPSENSOR_ADC5        (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor.
00852                                            On this STM32 series, ADC channel available only on ADC5 instance.
00853                                            Refer to device datasheet for ADC5 availaibility */
00854 #define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)           /*!< Internal channel Vbat/3: Vbat voltage
00855                                            through a divider ladder of factor 1/3 to have channel voltage always below
00856                                            Vdda.
00857                                            On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4.
00858                                            Refer to device datasheet for ADC4 availaibility */
00859 #define ADC_CHANNEL_VOPAMP1                (LL_ADC_CHANNEL_VOPAMP1)        /*!< Internal channel OPAMP1 output.
00860                                            On this STM32 series, ADC channel available only on ADC1 instance. */
00861 #define ADC_CHANNEL_VOPAMP2                (LL_ADC_CHANNEL_VOPAMP2)        /*!< Internal channel OPAMP2 output.
00862                                            On this STM32 series, ADC channel available only on ADC2 instance. */
00863 #define ADC_CHANNEL_VOPAMP3_ADC2           (LL_ADC_CHANNEL_VOPAMP3_ADC2)   /*!< Internal channel OPAMP3 output.
00864                                            On this STM32 series, ADC channel available only on ADC2 instance. */
00865 #define ADC_CHANNEL_VOPAMP3_ADC3           (LL_ADC_CHANNEL_VOPAMP3_ADC3)   /*!< Internal channel OPAMP3 output.
00866                                            On this STM32 series, ADC channel available only on ADC3 instance.
00867                                            Refer to device datasheet for ADC3 availability */
00868 #define ADC_CHANNEL_VOPAMP4                (LL_ADC_CHANNEL_VOPAMP4)        /*!< Internal channel OPAMP4 output.
00869                                            On this STM32 series, ADC channel available only on ADC5 instance.
00870                                            Refer to device datasheet for ADC5 availability */
00871 #define ADC_CHANNEL_VOPAMP5                (LL_ADC_CHANNEL_VOPAMP5)        /*!< Internal channel OPAMP5 output.
00872                                            On this STM32 series, ADC channel available only on ADC5 instance.
00873                                            Refer to device datasheet for ADC5 availability */
00874 #define ADC_CHANNEL_VOPAMP6                (LL_ADC_CHANNEL_VOPAMP6)        /*!< Internal channel OPAMP6 output.
00875                                            On this STM32 series, ADC channel available only on ADC4 instance.
00876                                            Refer to device datasheet for ADC4 availability */
00877 /**
00878   * @}
00879   */
00880
00881 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
00882   * @{
00883   */
00884 #define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
00885 #define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
00886 #define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
00887 /**
00888   * @}
00889   */
00890
00891 /** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration
00892   * @{
00893   */
00894 #define ADC_AWD_FILTERING_NONE          (0x00000000UL)                            /*!< ADC AWD no filtering, one
00895 out-of-window sample to raise flag or interrupt */
00896 #define ADC_AWD_FILTERING_2SAMPLES      ((ADC_TR1_AWDFILT_0))                     /*!< ADC AWD 2 consecutives
00897                                         out-of-window samples to raise flag or interrupt */
00898 #define ADC_AWD_FILTERING_3SAMPLES      ((ADC_TR1_AWDFILT_1))                     /*!< ADC AWD 3 consecutives
00899                                         out-of-window samples to raise flag or interrupt */
00900 #define ADC_AWD_FILTERING_4SAMPLES      ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives
00901                                         out-of-window samples to raise flag or interrupt */
00902 #define ADC_AWD_FILTERING_5SAMPLES      ((ADC_TR1_AWDFILT_2))                     /*!< ADC AWD 5 consecutives
00903                                         out-of-window samples to raise flag or interrupt */
00904 #define ADC_AWD_FILTERING_6SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives
00905                                         out-of-window samples to raise flag or interrupt */
00906 #define ADC_AWD_FILTERING_7SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives
00907                                         out-of-window samples to raise flag or interrupt */
00908 #define ADC_AWD_FILTERING_8SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
00909                                           | ADC_TR1_AWDFILT_0))                     /*!< ADC AWD 8 consecutives
00910                                         out-of-window samples to raise flag or interrupt */
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
00916   * @{
00917   */
00918 #define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                         /*!< ADC AWD not selected */
00919 #define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)   /*!< ADC AWD applied to a regular
00920                                                 group single channel */
00921 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)  /*!< ADC AWD applied to an
00922                                                 injected group single channel */
00923 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
00924                                                  | ADC_CFGR_JAWD1EN)                    /*!< ADC AWD applied to a regular
00925                                                 and injected groups single channel */
00926 #define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                      /*!< ADC AWD applied to regular
00927                                                 group all channels */
00928 #define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                     /*!< ADC AWD applied to injected
00929                                                 group all channels */
00930 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)   /*!< ADC AWD applied to regular
00931                                                 and injected groups all channels */
00932 /**
00933   * @}
00934   */
00935
00936 /** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
00937   * @{
00938   */
00939 /**
00940   * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
00941   *       to result as the ADC oversampling conversion data (before potential shift)
00942   */
00943 #define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)    /*!< ADC oversampling ratio    2 */
00944 #define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)    /*!< ADC oversampling ratio    4 */
00945 #define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)    /*!< ADC oversampling ratio    8 */
00946 #define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)   /*!< ADC oversampling ratio   16 */
00947 #define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)   /*!< ADC oversampling ratio   32 */
00948 #define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)   /*!< ADC oversampling ratio   64 */
00949 #define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128)  /*!< ADC oversampling ratio  128 */
00950 #define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256)  /*!< ADC oversampling ratio  256 */
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
00956   * @{
00957   */
00958 /**
00959   * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
00960   *       conversion data)
00961   */
00962 #define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift   */
00963 #define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
00964 #define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
00965 #define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
00966 #define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
00967 #define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
00968 #define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
00969 #define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
00970 #define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
00971 /**
00972   * @}
00973   */
00974
00975 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
00976   * @{
00977   */
00978 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode:
00979                                            continuous mode (all conversions of OVS ratio are done from 1 trigger) */
00980 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode:
00981                                            discontinuous mode (each conversion of OVS ratio needs a trigger) */
00982 /**
00983   * @}
00984   */
00985
00986 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
00987   * @{
00988   */
00989 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
00990                                            during injection sequence */
00991 #define ADC_REGOVERSAMPLING_RESUMED_MODE   (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during
00992                                            injection sequence */
00993 /**
00994   * @}
00995   */
00996
00997 /** @defgroup ADC_Event_type ADC Event type
00998   * @{
00999   */
01000 /**
01001   * @note Analog watchdog 1 is available on all stm32 series
01002   *       Analog watchdog 2 and 3 are not available on all series
01003   */
01004 #define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
01005 #define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
01006 #define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
01007 #define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
01008 #define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
01009 #define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
01010 /**
01011   * @}
01012   */
01013 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility
01014                                                           with other STM32 devices having only one analog watchdog */
01015
01016 /** @defgroup ADC_interrupts_definition ADC interrupts definition
01017   * @{
01018   */
01019 #define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
01020 #define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
01021 #define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
01022 #define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
01023 #define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
01024 #define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
01025 #define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
01026 #define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
01027 #define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog
01028                              watchdog) */
01029 #define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog
01030                              watchdog) */
01031 #define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */
01032
01033 /**
01034   * @}
01035   */
01036
01037 /** @defgroup ADC_flags_definition ADC flags definition
01038   * @{
01039   */
01040 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
01041 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
01042 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
01043 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
01044 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
01045 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
01046 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
01047 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
01048 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
01049 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
01050 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
01051
01052 /**
01053   * @}
01054   */
01055
01056 /**
01057   * @}
01058   */
01059
01060 /* Private macro -------------------------------------------------------------*/
01061
01062 /** @defgroup ADC_Private_Macros ADC Private Macros
01063   * @{
01064   */
01065 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
01066 /* code of final user.                                                        */
01067
01068 /**
01069   * @brief Return resolution bits in CFGR register RES[1:0] field.
01070   * @param __HANDLE__ ADC handle
01071   * @retval Value of bitfield RES in CFGR register.
01072   */
01073 #define ADC_GET_RESOLUTION(__HANDLE__)                                         \
01074   (LL_ADC_GetResolution((__HANDLE__)->Instance))
01075
01076 /**
01077   * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
01078   * @param __HANDLE__ ADC handle
01079   * @retval None
01080   */
01081 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
01082
01083 /**
01084   * @brief Simultaneously clear and set specific bits of the handle State.
01085   * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
01086   *        the first parameter is the ADC handle State, the second parameter is the
01087   *        bit field to clear, the third and last parameter is the bit field to set.
01088   * @retval None
01089   */
01090 #define ADC_STATE_CLR_SET MODIFY_REG
01091
01092 /**
01093   * @brief Verify that a given value is aligned with the ADC resolution range.
01094   * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
01095   * @param __ADC_VALUE__ value checked against the resolution.
01096   * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
01097   */
01098 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
01099   ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
01100
01101 /**
01102   * @brief Verify the length of the scheduled regular conversions group.
01103   * @param __LENGTH__ number of programmed conversions.
01104   * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
01105   *         or RESET (__LENGTH__ is null or too large)
01106   */
01107 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
01108
01109
01110 /**
01111   * @brief Verify the number of scheduled regular conversions in discontinuous mode.
01112   * @param NUMBER number of scheduled regular conversions in discontinuous mode.
01113   * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
01114   *         or RESET (NUMBER is null or too large)
01115   */
01116 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
01117
01118
01119 /**
01120   * @brief Verify the ADC clock setting.
01121   * @param __ADC_CLOCK__ programmed ADC clock.
01122   * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
01123   */
01124 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
01125                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
01126                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
01127                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
01128                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
01129                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
01130                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
01131                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
01132                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
01133                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
01134                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
01135                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
01136                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
01137                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
01138                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
01139
01140 /**
01141   * @brief Verify the ADC resolution setting.
01142   * @param __RESOLUTION__ programmed ADC resolution.
01143   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
01144   */
01145 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
01146                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
01147                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
01148                                            ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
01149
01150 /**
01151   * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
01152   * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
01153   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
01154   */
01155 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
01156                                                     ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
01157
01158 /**
01159   * @brief Verify the ADC converted data alignment.
01160   * @param __ALIGN__ programmed ADC converted data alignment.
01161   * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
01162   */
01163 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
01164                                       ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
01165
01166 /**
01167   * @brief Verify the ADC gain compensation.
01168   * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
01169   * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
01170   */
01171 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
01172
01173 /**
01174   * @brief Verify the ADC scan mode.
01175   * @param __SCAN_MODE__ programmed ADC scan mode.
01176   * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
01177   */
01178 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
01179                                          ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
01180
01181 /**
01182   * @brief Verify the ADC edge trigger setting for regular group.
01183   * @param __EDGE__ programmed ADC edge trigger setting.
01184   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
01185   */
01186 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
01187                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
01188                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
01189                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
01190
01191 /**
01192   * @brief Verify the ADC regular conversions external trigger.
01193   * @param __HANDLE__ ADC handle
01194   * @param __REGTRIG__ programmed ADC regular conversions external trigger.
01195   * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
01196   */
01197 #if defined(STM32G474xx) || defined(STM32G484xx)
01198 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
01199                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
01200                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
01201                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
01202                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
01203                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
01204                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
01205                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
01206                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
01207                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
01208                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
01209                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
01210                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
01211                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
01212                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1)      || \
01213                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3)      || \
01214                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5)      || \
01215                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6)      || \
01216                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7)      || \
01217                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8)      || \
01218                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9)      || \
01219                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10)     || \
01220                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
01221                                                  ((((__HANDLE__)->Instance == ADC1) || \
01222                                                    ((__HANDLE__)->Instance == ADC2)) && \
01223                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
01224                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
01225                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
01226                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
01227                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
01228                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
01229                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
01230                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
01231                                                  ((((__HANDLE__)->Instance == ADC3) || \
01232                                                    ((__HANDLE__)->Instance == ADC4) || \
01233                                                    ((__HANDLE__)->Instance == ADC5)) && \
01234                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
01235                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
01236                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
01237                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
01238                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
01239                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2)    || \
01240                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4)    || \
01241                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
01242                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
01243 #elif defined(STM32G473xx) || defined(STM32G483xx)
01244 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
01245                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
01246                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
01247                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
01248                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
01249                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
01250                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
01251                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
01252                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
01253                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
01254                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
01255                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
01256                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
01257                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
01258                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
01259                                                  ((((__HANDLE__)->Instance == ADC1) || \
01260                                                    ((__HANDLE__)->Instance == ADC2)) && \
01261                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
01262                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
01263                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
01264                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
01265                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
01266                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
01267                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
01268                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
01269                                                  ((((__HANDLE__)->Instance == ADC3) || \
01270                                                    ((__HANDLE__)->Instance == ADC4) || \
01271                                                    ((__HANDLE__)->Instance == ADC5)) && \
01272                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
01273                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
01274                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
01275                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
01276                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
01277                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
01278                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
01279 #elif defined(STM32G471xx)
01280 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
01281                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
01282                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
01283                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
01284                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
01285                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
01286                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
01287                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
01288                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
01289                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
01290                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
01291                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
01292                                                  ((((__HANDLE__)->Instance == ADC1) || \
01293                                                    ((__HANDLE__)->Instance == ADC2)) && \
01294                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
01295                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
01296                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
01297                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
01298                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
01299                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
01300                                                  ((((__HANDLE__)->Instance == ADC3)) && \
01301                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
01302                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
01303                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
01304                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
01305                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
01306                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
01307                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
01308 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
01309 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
01310                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
01311                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)          || \
01312                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)          || \
01313                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
01314                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
01315                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)          || \
01316                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
01317                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)          || \
01318                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
01319                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)          || \
01320                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
01321                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
01322                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
01323                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
01324                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
01325                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
01326                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)        || \
01327                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
01328 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
01329 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
01330                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
01331                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
01332                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
01333                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
01334                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
01335                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
01336                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
01337                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
01338                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
01339                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
01340                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
01341                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
01342                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
01343                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
01344                                                  ((((__HANDLE__)->Instance == ADC1) || \
01345                                                    ((__HANDLE__)->Instance == ADC2)) && \
01346                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
01347                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
01348                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
01349                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
01350                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
01351                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
01352                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
01353                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
01354                                                  (((__HANDLE__)->Instance == ADC3) && \
01355                                                   (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
01356                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
01357                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
01358                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
01359                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
01360                                                    ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
01361                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
01362 #endif /* STM32G4xx */
01363
01364 /**
01365   * @brief Verify the ADC regular conversions external trigger.
01366   * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
01367   * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
01368   */
01369 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL)          || \
01370                                                ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB)            || \
01371                                                ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)  )
01372
01373 /**
01374   * @brief Verify the ADC regular conversions check for converted data availability.
01375   * @param __EOC_SELECTION__ converted data availability check.
01376   * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
01377   */
01378 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
01379                                                  ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
01380
01381 /**
01382   * @brief Verify the ADC regular conversions overrun handling.
01383   * @param __OVR__ ADC regular conversions overrun handling.
01384   * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
01385   */
01386 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
01387                                  ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
01388
01389 /**
01390   * @brief Verify the ADC conversions sampling time.
01391   * @param __TIME__ ADC conversions sampling time.
01392   * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
01393   */
01394 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
01395                                       ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
01396                                       ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
01397                                       ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
01398                                       ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
01399                                       ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
01400                                       ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
01401                                       ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
01402                                       ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
01403
01404 /**
01405   * @brief Verify the ADC regular channel setting.
01406   * @param  __CHANNEL__ programmed ADC regular channel.
01407   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01408   */
01409 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
01410                                           ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
01411                                           ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
01412                                           ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
01413                                           ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
01414                                           ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
01415                                           ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
01416                                           ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
01417                                           ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
01418                                           ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
01419                                           ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
01420                                           ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
01421                                           ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
01422                                           ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
01423                                           ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
01424                                           ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
01425
01426 /**
01427   * @}
01428   */
01429
01430
01431 /* Private constants ---------------------------------------------------------*/
01432
01433 /** @defgroup ADC_Private_Constants ADC Private Constants
01434   * @{
01435   */
01436
01437 /* Fixed timeout values for ADC conversion (including sampling time)        */
01438 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
01439 /* Maximum conversion time is 12.5 + Maximum sampling time                  */
01440 /*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
01441 /* Minimum ADC Clock frequency is 0.14 MHz                                  */
01442 /* Maximum conversion time is                                               */
01443 /*              653 / 0.14 MHz = 4.66 ms                                    */
01444 #define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */
01445
01446 /* Delay for temperature sensor stabilization time.                         */
01447 /* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
01448 /* Unit: us                                                                 */
01449 #define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
01450
01451 /**
01452   * @}
01453   */
01454
01455 /* Exported macro ------------------------------------------------------------*/
01456
01457 /** @defgroup ADC_Exported_Macros ADC Exported Macros
01458   * @{
01459   */
01460 /* Macro for internal HAL driver usage, and possibly can be used into code of */
01461 /* final user.                                                                */
01462
01463 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
01464   * @{
01465   */
01466
01467 /** @brief  Reset ADC handle state.
01468   * @param __HANDLE__ ADC handle
01469   * @retval None
01470   */
01471 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01472 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01473   do{                                                                          \
01474     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
01475     (__HANDLE__)->MspInitCallback = NULL;                                      \
01476     (__HANDLE__)->MspDeInitCallback = NULL;                                    \
01477   } while(0)
01478 #else
01479 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01480   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
01481 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01482
01483 /**
01484   * @brief Enable ADC interrupt.
01485   * @param __HANDLE__ ADC handle
01486   * @param __INTERRUPT__ ADC Interrupt
01487   *        This parameter can be one of the following values:
01488   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01489   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01490   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01491   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01492   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01493   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01494   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01495   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01496   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01497   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01498   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01499   * @retval None
01500   */
01501 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
01502   (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
01503
01504 /**
01505   * @brief Disable ADC interrupt.
01506   * @param __HANDLE__ ADC handle
01507   * @param __INTERRUPT__ ADC Interrupt
01508   *        This parameter can be one of the following values:
01509   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01510   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01511   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01512   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01513   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01514   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01515   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01516   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01517   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01518   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01519   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01520   * @retval None
01521   */
01522 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
01523   (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
01524
01525 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
01526   * @param __HANDLE__ ADC handle
01527   * @param __INTERRUPT__ ADC interrupt source to check
01528   *          This parameter can be one of the following values:
01529   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01530   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01531   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01532   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01533   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01534   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01535   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01536   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01537   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01538   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01539   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01540   * @retval State of interruption (SET or RESET)
01541   */
01542 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
01543   (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
01544
01545 /**
01546   * @brief Check whether the specified ADC flag is set or not.
01547   * @param __HANDLE__ ADC handle
01548   * @param __FLAG__ ADC flag
01549   *        This parameter can be one of the following values:
01550   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01551   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01552   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01553   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01554   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01555   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01556   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01557   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01558   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01559   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01560   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01561   * @retval State of flag (TRUE or FALSE).
01562   */
01563 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
01564   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
01565
01566 /**
01567   * @brief Clear the specified ADC flag.
01568   * @param __HANDLE__ ADC handle
01569   * @param __FLAG__ ADC flag
01570   *        This parameter can be one of the following values:
01571   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01572   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01573   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01574   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01575   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01576   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01577   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01578   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01579   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01580   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01581   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01582   * @retval None
01583   */
01584 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
01585 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
01586   (((__HANDLE__)->Instance->ISR) = (__FLAG__))
01587
01588 /**
01589   * @}
01590   */
01591
01592 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
01593   * @{
01594   */
01595
01596 /**
01597   * @brief  Helper macro to get ADC channel number in decimal format
01598   *         from literals ADC_CHANNEL_x.
01599   * @note   Example:
01600   *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
01601   *           will return decimal number "4".
01602   * @note   The input can be a value from functions where a channel
01603   *         number is returned, either defined with number
01604   *         or with bitfield (only one bit must be set).
01605   * @param  __CHANNEL__ This parameter can be one of the following values:
01606   *         @arg @ref ADC_CHANNEL_0
01607   *         @arg @ref ADC_CHANNEL_1                 (8)
01608   *         @arg @ref ADC_CHANNEL_2                 (8)
01609   *         @arg @ref ADC_CHANNEL_3                 (8)
01610   *         @arg @ref ADC_CHANNEL_4                 (8)
01611   *         @arg @ref ADC_CHANNEL_5                 (8)
01612   *         @arg @ref ADC_CHANNEL_6
01613   *         @arg @ref ADC_CHANNEL_7
01614   *         @arg @ref ADC_CHANNEL_8
01615   *         @arg @ref ADC_CHANNEL_9
01616   *         @arg @ref ADC_CHANNEL_10
01617   *         @arg @ref ADC_CHANNEL_11
01618   *         @arg @ref ADC_CHANNEL_12
01619   *         @arg @ref ADC_CHANNEL_13
01620   *         @arg @ref ADC_CHANNEL_14
01621   *         @arg @ref ADC_CHANNEL_15
01622   *         @arg @ref ADC_CHANNEL_16
01623   *         @arg @ref ADC_CHANNEL_17
01624   *         @arg @ref ADC_CHANNEL_18
01625   *         @arg @ref ADC_CHANNEL_VREFINT           (7)
01626   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
01627   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
01628   *         @arg @ref ADC_CHANNEL_VBAT              (6)
01629   *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
01630   *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
01631   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
01632   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
01633   *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
01634   *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
01635   *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
01636   *
01637   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
01638   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
01639   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
01640   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
01641   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
01642   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
01643   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
01644   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
01645   *             for more details.
01646   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
01647   *             convert in 12-bit resolution.
01648   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
01649   *            (fADC) to convert in 12-bit resolution.\n
01650   * @retval Value between Min_Data=0 and Max_Data=18
01651   */
01652 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
01653   __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
01654
01655 /**
01656   * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
01657   *         from number in decimal format.
01658   * @note   Example:
01659   *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01660   *           will return a data equivalent to "ADC_CHANNEL_4".
01661   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01662   * @retval Returned value can be one of the following values:
01663   *         @arg @ref ADC_CHANNEL_0
01664   *         @arg @ref ADC_CHANNEL_1                 (8)
01665   *         @arg @ref ADC_CHANNEL_2                 (8)
01666   *         @arg @ref ADC_CHANNEL_3                 (8)
01667   *         @arg @ref ADC_CHANNEL_4                 (8)
01668   *         @arg @ref ADC_CHANNEL_5                 (8)
01669   *         @arg @ref ADC_CHANNEL_6
01670   *         @arg @ref ADC_CHANNEL_7
01671   *         @arg @ref ADC_CHANNEL_8
01672   *         @arg @ref ADC_CHANNEL_9
01673   *         @arg @ref ADC_CHANNEL_10
01674   *         @arg @ref ADC_CHANNEL_11
01675   *         @arg @ref ADC_CHANNEL_12
01676   *         @arg @ref ADC_CHANNEL_13
01677   *         @arg @ref ADC_CHANNEL_14
01678   *         @arg @ref ADC_CHANNEL_15
01679   *         @arg @ref ADC_CHANNEL_16
01680   *         @arg @ref ADC_CHANNEL_17
01681   *         @arg @ref ADC_CHANNEL_18
01682   *         @arg @ref ADC_CHANNEL_VREFINT           (7)
01683   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
01684   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
01685   *         @arg @ref ADC_CHANNEL_VBAT              (6)
01686   *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
01687   *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
01688   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
01689   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
01690   *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
01691   *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
01692   *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
01693   *
01694   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
01695   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
01696   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
01697   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
01698   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
01699   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
01700   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
01701   *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
01702   *             more details.
01703   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC)
01704   *             to convert in 12-bit resolution.
01705   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
01706   *             (fADC) to convert in 12-bit resolution.\n
01707   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
01708   *                      comparison with internal channel parameter to be done
01709   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01710   */
01711 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
01712   __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
01713
01714 /**
01715   * @brief  Helper macro to determine whether the selected channel
01716   *         corresponds to literal definitions of driver.
01717   * @note   The different literal definitions of ADC channels are:
01718   *         - ADC internal channel:
01719   *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
01720   *         - ADC external channel (channel connected to a GPIO pin):
01721   *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
01722   * @note   The channel parameter must be a value defined from literal
01723   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01724   *         ADC_CHANNEL_TEMPSENSOR, ...),
01725   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
01726   *         must not be a value from functions where a channel number is
01727   *         returned from ADC registers,
01728   *         because internal and external channels share the same channel
01729   *         number in ADC registers. The differentiation is made only with
01730   *         parameters definitions of driver.
01731   * @param  __CHANNEL__ This parameter can be one of the following values:
01732   *         @arg @ref ADC_CHANNEL_0
01733   *         @arg @ref ADC_CHANNEL_1                 (8)
01734   *         @arg @ref ADC_CHANNEL_2                 (8)
01735   *         @arg @ref ADC_CHANNEL_3                 (8)
01736   *         @arg @ref ADC_CHANNEL_4                 (8)
01737   *         @arg @ref ADC_CHANNEL_5                 (8)
01738   *         @arg @ref ADC_CHANNEL_6
01739   *         @arg @ref ADC_CHANNEL_7
01740   *         @arg @ref ADC_CHANNEL_8
01741   *         @arg @ref ADC_CHANNEL_9
01742   *         @arg @ref ADC_CHANNEL_10
01743   *         @arg @ref ADC_CHANNEL_11
01744   *         @arg @ref ADC_CHANNEL_12
01745   *         @arg @ref ADC_CHANNEL_13
01746   *         @arg @ref ADC_CHANNEL_14
01747   *         @arg @ref ADC_CHANNEL_15
01748   *         @arg @ref ADC_CHANNEL_16
01749   *         @arg @ref ADC_CHANNEL_17
01750   *         @arg @ref ADC_CHANNEL_18
01751   *         @arg @ref ADC_CHANNEL_VREFINT           (7)
01752   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
01753   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
01754   *         @arg @ref ADC_CHANNEL_VBAT              (6)
01755   *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
01756   *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
01757   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
01758   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
01759   *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
01760   *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
01761   *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
01762   *
01763   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
01764   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
01765   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
01766   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
01767   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
01768   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
01769   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
01770   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
01771   *             for more details.
01772   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
01773   *             convert in 12-bit resolution.
01774   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
01775   *            (fADC) to convert in 12-bit resolution.\n
01776   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
01777   *         connected to a GPIO pin).
01778   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01779   */
01780 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
01781   __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
01782
01783 /**
01784   * @brief  Helper macro to convert a channel defined from parameter
01785   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01786   *         ADC_CHANNEL_TEMPSENSOR, ...),
01787   *         to its equivalent parameter definition of a ADC external channel
01788   *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
01789   * @note   The channel parameter can be, additionally to a value
01790   *         defined from parameter definition of a ADC internal channel
01791   *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
01792   *         a value defined from parameter definition of
01793   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01794   *         or a value from functions where a channel number is returned
01795   *         from ADC registers.
01796   * @param  __CHANNEL__ This parameter can be one of the following values:
01797   *         @arg @ref ADC_CHANNEL_0
01798   *         @arg @ref ADC_CHANNEL_1                 (8)
01799   *         @arg @ref ADC_CHANNEL_2                 (8)
01800   *         @arg @ref ADC_CHANNEL_3                 (8)
01801   *         @arg @ref ADC_CHANNEL_4                 (8)
01802   *         @arg @ref ADC_CHANNEL_5                 (8)
01803   *         @arg @ref ADC_CHANNEL_6
01804   *         @arg @ref ADC_CHANNEL_7
01805   *         @arg @ref ADC_CHANNEL_8
01806   *         @arg @ref ADC_CHANNEL_9
01807   *         @arg @ref ADC_CHANNEL_10
01808   *         @arg @ref ADC_CHANNEL_11
01809   *         @arg @ref ADC_CHANNEL_12
01810   *         @arg @ref ADC_CHANNEL_13
01811   *         @arg @ref ADC_CHANNEL_14
01812   *         @arg @ref ADC_CHANNEL_15
01813   *         @arg @ref ADC_CHANNEL_16
01814   *         @arg @ref ADC_CHANNEL_17
01815   *         @arg @ref ADC_CHANNEL_18
01816   *         @arg @ref ADC_CHANNEL_VREFINT           (7)
01817   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
01818   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
01819   *         @arg @ref ADC_CHANNEL_VBAT              (6)
01820   *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
01821   *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
01822   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
01823   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
01824   *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
01825   *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
01826   *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
01827   *
01828   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
01829   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
01830   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
01831   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
01832   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
01833   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
01834   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
01835   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
01836   *             for more details.
01837   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
01838   *             convert in 12-bit resolution.
01839   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
01840   *            (fADC) to convert in 12-bit resolution.\n
01841   * @retval Returned value can be one of the following values:
01842   *         @arg @ref ADC_CHANNEL_0
01843   *         @arg @ref ADC_CHANNEL_1
01844   *         @arg @ref ADC_CHANNEL_2
01845   *         @arg @ref ADC_CHANNEL_3
01846   *         @arg @ref ADC_CHANNEL_4
01847   *         @arg @ref ADC_CHANNEL_5
01848   *         @arg @ref ADC_CHANNEL_6
01849   *         @arg @ref ADC_CHANNEL_7
01850   *         @arg @ref ADC_CHANNEL_8
01851   *         @arg @ref ADC_CHANNEL_9
01852   *         @arg @ref ADC_CHANNEL_10
01853   *         @arg @ref ADC_CHANNEL_11
01854   *         @arg @ref ADC_CHANNEL_12
01855   *         @arg @ref ADC_CHANNEL_13
01856   *         @arg @ref ADC_CHANNEL_14
01857   *         @arg @ref ADC_CHANNEL_15
01858   *         @arg @ref ADC_CHANNEL_16
01859   *         @arg @ref ADC_CHANNEL_17
01860   *         @arg @ref ADC_CHANNEL_18
01861   */
01862 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
01863   __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
01864
01865 /**
01866   * @brief  Helper macro to determine whether the internal channel
01867   *         selected is available on the ADC instance selected.
01868   * @note   The channel parameter must be a value defined from parameter
01869   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01870   *         ADC_CHANNEL_TEMPSENSOR, ...),
01871   *         must not be a value defined from parameter definition of
01872   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01873   *         or a value from functions where a channel number is
01874   *         returned from ADC registers,
01875   *         because internal and external channels share the same channel
01876   *         number in ADC registers. The differentiation is made only with
01877   *         parameters definitions of driver.
01878   * @param  __ADC_INSTANCE__ ADC instance
01879   * @param  __CHANNEL__ This parameter can be one of the following values:
01880   *         @arg @ref ADC_CHANNEL_VREFINT           (7)
01881   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
01882   *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
01883   *         @arg @ref ADC_CHANNEL_VBAT              (6)
01884   *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
01885   *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
01886   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
01887   *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
01888   *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
01889   *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
01890   *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
01891   *
01892   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
01893   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
01894   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
01895   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
01896   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
01897   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
01898   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
01899   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
01900   *             for more details.
01901   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01902   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01903   */
01904 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01905   __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
01906
01907 #if defined(ADC_MULTIMODE_SUPPORT)
01908 /**
01909   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01910   *         or ADC slave from raw value with both ADC conversion data concatenated.
01911   * @note   This macro is intended to be used when multimode transfer by DMA
01912   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
01913   *         In this case the transferred data need to processed with this macro
01914   *         to separate the conversion data of ADC master and ADC slave.
01915   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
01916   *         @arg @ref LL_ADC_MULTI_MASTER
01917   *         @arg @ref LL_ADC_MULTI_SLAVE
01918   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
01919   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01920   */
01921 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
01922   __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
01923 #endif /* ADC_MULTIMODE_SUPPORT */
01924
01925 /**
01926   * @brief  Helper macro to select the ADC common instance
01927   *         to which is belonging the selected ADC instance.
01928   * @note   ADC common register instance can be used for:
01929   *         - Set parameters common to several ADC instances
01930   *         - Multimode (for devices with several ADC instances)
01931   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01932   * @param  __ADCx__ ADC instance
01933   * @retval ADC common register instance
01934   */
01935 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
01936   __LL_ADC_COMMON_INSTANCE((__ADCx__))
01937
01938 /**
01939   * @brief  Helper macro to check if all ADC instances sharing the same
01940   *         ADC common instance are disabled.
01941   * @note   This check is required by functions with setting conditioned to
01942   *         ADC state:
01943   *         All ADC instances of the ADC common group must be disabled.
01944   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01945   * @note   On devices with only 1 ADC common instance, parameter of this macro
01946   *         is useless and can be ignored (parameter kept for compatibility
01947   *         with devices featuring several ADC common instances).
01948   * @param  __ADCXY_COMMON__ ADC common instance
01949   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01950   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01951   *         are disabled.
01952   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01953   *         is enabled.
01954   */
01955 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01956   __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
01957
01958 /**
01959   * @brief  Helper macro to define the ADC conversion data full-scale digital
01960   *         value corresponding to the selected ADC resolution.
01961   * @note   ADC conversion data full-scale corresponds to voltage range
01962   *         determined by analog voltage references Vref+ and Vref-
01963   *         (refer to reference manual).
01964   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01965   *         @arg @ref ADC_RESOLUTION_12B
01966   *         @arg @ref ADC_RESOLUTION_10B
01967   *         @arg @ref ADC_RESOLUTION_8B
01968   *         @arg @ref ADC_RESOLUTION_6B
01969   * @retval ADC conversion data full-scale digital value
01970   */
01971 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01972   __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
01973
01974 /**
01975   * @brief  Helper macro to convert the ADC conversion data from
01976   *         a resolution to another resolution.
01977   * @param  __DATA__ ADC conversion data to be converted
01978   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
01979   *         This parameter can be one of the following values:
01980   *         @arg @ref ADC_RESOLUTION_12B
01981   *         @arg @ref ADC_RESOLUTION_10B
01982   *         @arg @ref ADC_RESOLUTION_8B
01983   *         @arg @ref ADC_RESOLUTION_6B
01984   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01985   *         This parameter can be one of the following values:
01986   *         @arg @ref ADC_RESOLUTION_12B
01987   *         @arg @ref ADC_RESOLUTION_10B
01988   *         @arg @ref ADC_RESOLUTION_8B
01989   *         @arg @ref ADC_RESOLUTION_6B
01990   * @retval ADC conversion data to the requested resolution
01991   */
01992 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01993                                           __ADC_RESOLUTION_CURRENT__,\
01994                                           __ADC_RESOLUTION_TARGET__) \
01995 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
01996                                  (__ADC_RESOLUTION_CURRENT__),\
01997                                  (__ADC_RESOLUTION_TARGET__))
01998
01999 /**
02000   * @brief  Helper macro to calculate the voltage (unit: mVolt)
02001   *         corresponding to a ADC conversion data (unit: digital value).
02002   * @note   Analog reference voltage (Vref+) must be either known from
02003   *         user board environment or can be calculated using ADC measurement
02004   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02005   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
02006   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
02007   *                       (unit: digital value).
02008   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02009   *         @arg @ref ADC_RESOLUTION_12B
02010   *         @arg @ref ADC_RESOLUTION_10B
02011   *         @arg @ref ADC_RESOLUTION_8B
02012   *         @arg @ref ADC_RESOLUTION_6B
02013   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02014   */
02015 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
02016                                        __ADC_DATA__,\
02017                                        __ADC_RESOLUTION__) \
02018 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
02019                               (__ADC_DATA__),\
02020                               (__ADC_RESOLUTION__))
02021
02022 /**
02023   * @brief  Helper macro to calculate the voltage (unit: mVolt)
02024   *         corresponding to a ADC conversion data (unit: digital value)
02025   *         in differential ended mode.
02026   * @note   Analog reference voltage (Vref+) must be either known from
02027   *         user board environment or can be calculated using ADC measurement
02028   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02029   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
02030   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
02031   *                       (unit: digital value).
02032   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02033   *         @arg @ref ADC_RESOLUTION_12B
02034   *         @arg @ref ADC_RESOLUTION_10B
02035   *         @arg @ref ADC_RESOLUTION_8B
02036   *         @arg @ref ADC_RESOLUTION_6B
02037   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02038   */
02039 #define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
02040                                             __ADC_DATA__,\
02041                                             __ADC_RESOLUTION__) \
02042 __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
02043                                    (__ADC_DATA__),\
02044                                    (__ADC_RESOLUTION__))
02045
02046 /**
02047   * @brief  Helper macro to calculate analog reference voltage (Vref+)
02048   *         (unit: mVolt) from ADC conversion data of internal voltage
02049   *         reference VrefInt.
02050   * @note   Computation is using VrefInt calibration value
02051   *         stored in system memory for each device during production.
02052   * @note   This voltage depends on user board environment: voltage level
02053   *         connected to pin Vref+.
02054   *         On devices with small package, the pin Vref+ is not present
02055   *         and internally bonded to pin Vdda.
02056   * @note   On this STM32 series, calibration data of internal voltage reference
02057   *         VrefInt corresponds to a resolution of 12 bits,
02058   *         this is the recommended ADC resolution to convert voltage of
02059   *         internal voltage reference VrefInt.
02060   *         Otherwise, this macro performs the processing to scale
02061   *         ADC conversion data to 12 bits.
02062   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
02063   *         of internal voltage reference VrefInt (unit: digital value).
02064   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02065   *         @arg @ref ADC_RESOLUTION_12B
02066   *         @arg @ref ADC_RESOLUTION_10B
02067   *         @arg @ref ADC_RESOLUTION_8B
02068   *         @arg @ref ADC_RESOLUTION_6B
02069   * @retval Analog reference voltage (unit: mV)
02070   */
02071 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
02072                                           __ADC_RESOLUTION__) \
02073 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
02074                                  (__ADC_RESOLUTION__))
02075
02076 /**
02077   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02078   *         from ADC conversion data of internal temperature sensor.
02079   * @note   Computation is using temperature sensor calibration values
02080   *         stored in system memory for each device during production.
02081   * @note   Calculation formula:
02082   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
02083   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
02084   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
02085   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
02086   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
02087   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
02088   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
02089   *                            TEMP_DEGC_CAL1 (calibrated in factory)
02090   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
02091   *                            TEMP_DEGC_CAL2 (calibrated in factory)
02092   *         Caution: Calculation relevancy under reserve that calibration
02093   *                  parameters are correct (address and data).
02094   *                  To calculate temperature using temperature sensor
02095   *                  datasheet typical values (generic values less, therefore
02096   *                  less accurate than calibrated values),
02097   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
02098   * @note   As calculation input, the analog reference voltage (Vref+) must be
02099   *         defined as it impacts the ADC LSB equivalent voltage.
02100   * @note   Analog reference voltage (Vref+) must be either known from
02101   *         user board environment or can be calculated using ADC measurement
02102   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02103   * @note   On this STM32 series, calibration data of temperature sensor
02104   *         corresponds to a resolution of 12 bits,
02105   *         this is the recommended ADC resolution to convert voltage of
02106   *         temperature sensor.
02107   *         Otherwise, this macro performs the processing to scale
02108   *         ADC conversion data to 12 bits.
02109   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
02110   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
02111   *                                 temperature sensor (unit: digital value).
02112   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
02113   *                                 sensor voltage has been measured.
02114   *         This parameter can be one of the following values:
02115   *         @arg @ref ADC_RESOLUTION_12B
02116   *         @arg @ref ADC_RESOLUTION_10B
02117   *         @arg @ref ADC_RESOLUTION_8B
02118   *         @arg @ref ADC_RESOLUTION_6B
02119   * @retval Temperature (unit: degree Celsius)
02120   */
02121 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
02122                                    __TEMPSENSOR_ADC_DATA__,\
02123                                    __ADC_RESOLUTION__) \
02124 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
02125                           (__TEMPSENSOR_ADC_DATA__),\
02126                           (__ADC_RESOLUTION__))
02127
02128 /**
02129   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02130   *         from ADC conversion data of internal temperature sensor.
02131   * @note   Computation is using temperature sensor typical values
02132   *         (refer to device datasheet).
02133   * @note   Calculation formula:
02134   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
02135   *                         / Avg_Slope + CALx_TEMP
02136   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
02137   *                                   (unit: digital value)
02138   *                Avg_Slope        = temperature sensor slope
02139   *                                   (unit: uV/Degree Celsius)
02140   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
02141   *                                   temperature CALx_TEMP (unit: mV)
02142   *         Caution: Calculation relevancy under reserve the temperature sensor
02143   *                  of the current device has characteristics in line with
02144   *                  datasheet typical values.
02145   *                  If temperature sensor calibration values are available on
02146   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
02147   *                  temperature calculation will be more accurate using
02148   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
02149   * @note   As calculation input, the analog reference voltage (Vref+) must be
02150   *         defined as it impacts the ADC LSB equivalent voltage.
02151   * @note   Analog reference voltage (Vref+) must be either known from
02152   *         user board environment or can be calculated using ADC measurement
02153   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02154   * @note   ADC measurement data must correspond to a resolution of 12bits
02155   *         (full scale digital value 4095). If not the case, the data must be
02156   *         preliminarily rescaled to an equivalent resolution of 12 bits.
02157   * @param  __TEMPSENSOR_TYP_AVGSLOPE__    Device datasheet data: Temperature sensor slope typical value
02158                                            (unit: uV/DegCelsius).
02159   *                                        On STM32G4, refer to device datasheet parameter "Avg_Slope".
02160   * @param  __TEMPSENSOR_TYP_CALX_V__      Device datasheet data: Temperature sensor voltage typical value (at
02161                                            temperature and Vref+ defined in parameters below) (unit: mV).
02162   *                                        On STM32G4, refer to device datasheet parameter "V30"
02163                                            (corresponding to TS_CAL1).
02164   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see
02165                                                                  parameter above) is corresponding (unit: mV)
02166   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
02167   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
02168   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
02169   *         This parameter can be one of the following values:
02170   *         @arg @ref ADC_RESOLUTION_12B
02171   *         @arg @ref ADC_RESOLUTION_10B
02172   *         @arg @ref ADC_RESOLUTION_8B
02173   *         @arg @ref ADC_RESOLUTION_6B
02174   * @retval Temperature (unit: degree Celsius)
02175   */
02176 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
02177                                               __TEMPSENSOR_TYP_CALX_V__,\
02178                                               __TEMPSENSOR_CALX_TEMP__,\
02179                                               __VREFANALOG_VOLTAGE__,\
02180                                               __TEMPSENSOR_ADC_DATA__,\
02181                                               __ADC_RESOLUTION__) \
02182 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
02183                                      (__TEMPSENSOR_TYP_CALX_V__),\
02184                                      (__TEMPSENSOR_CALX_TEMP__),\
02185                                      (__VREFANALOG_VOLTAGE__),\
02186                                      (__TEMPSENSOR_ADC_DATA__),\
02187                                      (__ADC_RESOLUTION__))
02188
02189 /**
02190   * @}
02191   */
02192
02193 /**
02194   * @}
02195   */
02196
02197 /* Include ADC HAL Extended module */
02198 #include "stm32g4xx_hal_adc_ex.h"
02199
02200 /* Exported functions --------------------------------------------------------*/
02201 /** @addtogroup ADC_Exported_Functions
02202   * @{
02203   */
02204
02205 /** @addtogroup ADC_Exported_Functions_Group1
02206   * @brief    Initialization and Configuration functions
02207   * @{
02208   */
02209 /* Initialization and de-initialization functions  ****************************/
02210 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
02211 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
02212 void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
02213 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
02214
02215 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02216 /* Callbacks Register/UnRegister functions  ***********************************/
02217 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
02218                                            pADC_CallbackTypeDef pCallback);
02219 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
02220 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02221 /**
02222   * @}
02223   */
02224
02225 /** @addtogroup ADC_Exported_Functions_Group2
02226   * @brief    IO operation functions
02227   * @{
02228   */
02229 /* IO operation functions  *****************************************************/
02230
02231 /* Blocking mode: Polling */
02232 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
02233 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
02234 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
02235 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
02236
02237 /* Non-blocking mode: Interruption */
02238 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
02239 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
02240
02241 /* Non-blocking mode: DMA */
02242 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
02243 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
02244
02245 /* ADC retrieve conversion value intended to be used with polling or interruption */
02246 uint32_t                HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
02247
02248 /* ADC sampling control */
02249 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
02250 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
02251
02252 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
02253 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
02254 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
02255 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
02256 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
02257 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
02258 /**
02259   * @}
02260   */
02261
02262 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
02263   *  @brief    Peripheral Control functions
02264   * @{
02265   */
02266 /* Peripheral Control functions ***********************************************/
02267 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
02268 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
02269                                                 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
02270
02271 /**
02272   * @}
02273   */
02274
02275 /* Peripheral State functions *************************************************/
02276 /** @addtogroup ADC_Exported_Functions_Group4
02277   * @{
02278   */
02279 uint32_t                HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
02280 uint32_t                HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
02281
02282 /**
02283   * @}
02284   */
02285
02286 /**
02287   * @}
02288   */
02289
02290 /* Private functions ---------------------------------------------------------*/
02291 /** @addtogroup ADC_Private_Functions ADC Private Functions
02292   * @{
02293   */
02294 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
02295 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
02296 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
02297 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
02298 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
02299 void ADC_DMAError(DMA_HandleTypeDef *hdma);
02300
02301 /**
02302   * @}
02303   */
02304
02305 /**
02306   * @}
02307   */
02308
02309 /**
02310   * @}
02311   */
02312
02313 #ifdef __cplusplus
02314 }
02315 #endif
02316
02317
02318 #endif /* STM32G4xx_HAL_ADC_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_adc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Converter (ADC)
00007   *          peripheral:
00008   *           + Peripheral Control functions
00009   *          Other functions (generic functions) are available in file
00010   *          "stm32g4xx_hal_adc.c".
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   [..]
00025   (@) Sections "ADC peripheral features" and "How to use this driver" are
00026       available in file of generic functions "stm32g4xx_hal_adc.c".
00027   [..]
00028   @endverbatim
00029   ******************************************************************************
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32g4xx_hal.h"
00034
00035 /** @addtogroup STM32G4xx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup ADCEx ADCEx
00040   * @brief ADC Extended HAL module driver
00041   * @{
00042   */
00043
00044 #ifdef HAL_ADC_MODULE_ENABLED
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 /* Private define ------------------------------------------------------------*/
00048
00049 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00050   * @{
00051   */
00052
00053 #define ADC_JSQR_FIELDS      ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00054                                ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
00055                                ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))           /*!< ADC_JSQR fields of parameters that can
00056                              be updated anytime once the ADC is enabled */
00057
00058 /* Fixed timeout value for ADC calibration.                                   */
00059 /* Values defined to be higher than worst cases: low clock frequency,         */
00060 /* maximum prescalers.                                                        */
00061 /* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value           */
00062 /* considering both possible ADC clocking scheme:                             */
00063 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00064 /*          ADC prescaler 4.                                                  */
00065 /*           Ratio max = 512 *4 = 2048                                        */
00066 /*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
00067 /*          Highest CPU clock PLL (PLLR).                                     */
00068 /*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
00069 /*                     = 3968 )                                               */
00070 /* Calibration_time MAX = 81 / f_ADC                                          */
00071 /*                      = 81 / (f_CPU/3938) = 318978 CPU cycles               */
00072 #define ADC_CALIBRATION_TIMEOUT         (318978UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Private macro -------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private function prototypes -----------------------------------------------*/
00081 /* Exported functions --------------------------------------------------------*/
00082
00083 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00088   * @brief    Extended IO operation functions
00089   *
00090 @verbatim
00091  ===============================================================================
00092                       ##### IO operation functions #####
00093  ===============================================================================
00094     [..]  This section provides functions allowing to:
00095
00096       (+) Perform the ADC self-calibration for single or differential ending.
00097       (+) Get calibration factors for single or differential ending.
00098       (+) Set calibration factors for single or differential ending.
00099
00100       (+) Start conversion of ADC group injected.
00101       (+) Stop conversion of ADC group injected.
00102       (+) Poll for conversion complete on ADC group injected.
00103       (+) Get result of ADC group injected channel conversion.
00104       (+) Start conversion of ADC group injected and enable interruptions.
00105       (+) Stop conversion of ADC group injected and disable interruptions.
00106
00107       (+) When multimode feature is available, start multimode and enable DMA transfer.
00108       (+) Stop multimode and disable ADC DMA transfer.
00109       (+) Get result of multimode conversion.
00110
00111 @endverbatim
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  Perform an ADC automatic self-calibration
00117   *         Calibration prerequisite: ADC must be disabled (execute this
00118   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00119   * @param  hadc       ADC handle
00120   * @param  SingleDiff Selection of single-ended or differential input
00121   *         This parameter can be one of the following values:
00122   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00123   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00124   * @retval HAL status
00125   */
00126 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
00127 {
00128   HAL_StatusTypeDef tmp_hal_status;
00129   __IO uint32_t wait_loop_index = 0UL;
00130
00131   /* Check the parameters */
00132   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00133   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00134
00135   /* Process locked */
00136   __HAL_LOCK(hadc);
00137
00138   /* Calibration prerequisite: ADC must be disabled. */
00139
00140   /* Disable the ADC (if not already disabled) */
00141   tmp_hal_status = ADC_Disable(hadc);
00142
00143   /* Check if ADC is effectively disabled */
00144   if (tmp_hal_status == HAL_OK)
00145   {
00146     /* Set ADC state */
00147     ADC_STATE_CLR_SET(hadc->State,
00148                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00149                       HAL_ADC_STATE_BUSY_INTERNAL);
00150
00151     /* Start ADC calibration in mode single-ended or differential */
00152     LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
00153
00154     /* Wait for calibration completion */
00155     while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
00156     {
00157       wait_loop_index++;
00158       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
00159       {
00160         /* Update ADC state machine to error */
00161         ADC_STATE_CLR_SET(hadc->State,
00162                           HAL_ADC_STATE_BUSY_INTERNAL,
00163                           HAL_ADC_STATE_ERROR_INTERNAL);
00164
00165         /* Process unlocked */
00166         __HAL_UNLOCK(hadc);
00167
00168         return HAL_ERROR;
00169       }
00170     }
00171
00172     /* Set ADC state */
00173     ADC_STATE_CLR_SET(hadc->State,
00174                       HAL_ADC_STATE_BUSY_INTERNAL,
00175                       HAL_ADC_STATE_READY);
00176   }
00177   else
00178   {
00179     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00180
00181     /* Note: No need to update variable "tmp_hal_status" here: already set    */
00182     /*       to state "HAL_ERROR" by function disabling the ADC.              */
00183   }
00184
00185   /* Process unlocked */
00186   __HAL_UNLOCK(hadc);
00187
00188   /* Return function status */
00189   return tmp_hal_status;
00190 }
00191
00192 /**
00193   * @brief  Get the calibration factor.
00194   * @param hadc ADC handle.
00195   * @param SingleDiff This parameter can be only:
00196   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00197   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00198   * @retval Calibration value.
00199   */
00200 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
00201 {
00202   /* Check the parameters */
00203   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00204   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00205
00206   /* Return the selected ADC calibration value */
00207   return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
00208 }
00209
00210 /**
00211   * @brief  Set the calibration factor to overwrite automatic conversion result.
00212   *         ADC must be enabled and no conversion is ongoing.
00213   * @param hadc ADC handle
00214   * @param SingleDiff This parameter can be only:
00215   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00216   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00217   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
00218   * @retval HAL state
00219   */
00220 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
00221                                                  uint32_t CalibrationFactor)
00222 {
00223   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00224   uint32_t tmp_adc_is_conversion_on_going_regular;
00225   uint32_t tmp_adc_is_conversion_on_going_injected;
00226
00227   /* Check the parameters */
00228   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00229   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00230   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00231
00232   /* Process locked */
00233   __HAL_LOCK(hadc);
00234
00235   /* Verification of hardware constraints before modifying the calibration    */
00236   /* factors register: ADC must be enabled, no conversion on going.           */
00237   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00238   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00239
00240   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00241       && (tmp_adc_is_conversion_on_going_regular == 0UL)
00242       && (tmp_adc_is_conversion_on_going_injected == 0UL)
00243      )
00244   {
00245     /* Set the selected ADC calibration value */
00246     LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
00247   }
00248   else
00249   {
00250     /* Update ADC state machine */
00251     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00252     /* Update ADC error code */
00253     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00254
00255     /* Update ADC state machine to error */
00256     tmp_hal_status = HAL_ERROR;
00257   }
00258
00259   /* Process unlocked */
00260   __HAL_UNLOCK(hadc);
00261
00262   /* Return function status */
00263   return tmp_hal_status;
00264 }
00265
00266 /**
00267   * @brief  Enable ADC, start conversion of injected group.
00268   * @note   Interruptions enabled in this function: None.
00269   * @note   Case of multimode enabled when multimode feature is available:
00270   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
00271   *         then for ADC master.
00272   *         For ADC slave, ADC is enabled only (conversion is not started).
00273   *         For ADC master, ADC is enabled and multimode conversion is started.
00274   * @param hadc ADC handle.
00275   * @retval HAL status
00276   */
00277 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
00278 {
00279   HAL_StatusTypeDef tmp_hal_status;
00280   uint32_t tmp_config_injected_queue;
00281 #if defined(ADC_MULTIMODE_SUPPORT)
00282   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00283 #endif /* ADC_MULTIMODE_SUPPORT */
00284
00285   /* Check the parameters */
00286   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00287
00288   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00289   {
00290     return HAL_BUSY;
00291   }
00292   else
00293   {
00294     /* In case of software trigger detection enabled, JQDIS must be set
00295       (which can be done only if ADSTART and JADSTART are both cleared).
00296        If JQDIS is not set at that point, returns an error
00297        - since software trigger detection is disabled. User needs to
00298        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00299        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00300          the queue is empty */
00301     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00302
00303     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00304         && (tmp_config_injected_queue == 0UL)
00305        )
00306     {
00307       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00308       return HAL_ERROR;
00309     }
00310
00311     /* Process locked */
00312     __HAL_LOCK(hadc);
00313
00314     /* Enable the ADC peripheral */
00315     tmp_hal_status = ADC_Enable(hadc);
00316
00317     /* Start conversion if ADC is effectively enabled */
00318     if (tmp_hal_status == HAL_OK)
00319     {
00320       /* Check if a regular conversion is ongoing */
00321       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00322       {
00323         /* Reset ADC error code field related to injected conversions only */
00324         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00325       }
00326       else
00327       {
00328         /* Set ADC error code to none */
00329         ADC_CLEAR_ERRORCODE(hadc);
00330       }
00331
00332       /* Set ADC state                                                        */
00333       /* - Clear state bitfield related to injected group conversion results  */
00334       /* - Set state bitfield related to injected operation                   */
00335       ADC_STATE_CLR_SET(hadc->State,
00336                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00337                         HAL_ADC_STATE_INJ_BUSY);
00338
00339 #if defined(ADC_MULTIMODE_SUPPORT)
00340       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00341         - if ADC instance is master or if multimode feature is not available
00342         - if multimode setting is disabled (ADC instance slave in independent mode) */
00343       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00344           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00345          )
00346       {
00347         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00348       }
00349 #endif /* ADC_MULTIMODE_SUPPORT */
00350
00351       /* Clear ADC group injected group conversion flag */
00352       /* (To ensure of no unknown state from potential previous ADC operations) */
00353       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00354
00355       /* Process unlocked */
00356       /* Unlock before starting ADC conversions: in case of potential         */
00357       /* interruption, to let the process to ADC IRQ Handler.                 */
00358       __HAL_UNLOCK(hadc);
00359
00360       /* Enable conversion of injected group, if automatic injected conversion  */
00361       /* is disabled.                                                           */
00362       /* If software start has been selected, conversion starts immediately.    */
00363       /* If external trigger has been selected, conversion will start at next   */
00364       /* trigger event.                                                         */
00365       /* Case of multimode enabled (when multimode feature is available):       */
00366       /* if ADC is slave,                                                       */
00367       /*    - ADC is enabled only (conversion is not started),                  */
00368       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00369       /*     and conversion is started.                                         */
00370       /* If ADC is master or independent,                                       */
00371       /*    - ADC is enabled and conversion is started.                         */
00372 #if defined(ADC_MULTIMODE_SUPPORT)
00373       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00374           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00375           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00376           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00377          )
00378       {
00379         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00380         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00381         {
00382           LL_ADC_INJ_StartConversion(hadc->Instance);
00383         }
00384       }
00385       else
00386       {
00387         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00388         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00389       }
00390 #else
00391       if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00392       {
00393         /* Start ADC group injected conversion */
00394         LL_ADC_INJ_StartConversion(hadc->Instance);
00395       }
00396 #endif /* ADC_MULTIMODE_SUPPORT */
00397
00398     }
00399     else
00400     {
00401       /* Process unlocked */
00402       __HAL_UNLOCK(hadc);
00403     }
00404
00405     /* Return function status */
00406     return tmp_hal_status;
00407   }
00408 }
00409
00410 /**
00411   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00412   *         no regular conversion is on going.
00413   * @note   If ADC must be disabled and if conversion is on going on
00414   *         regular group, function HAL_ADC_Stop must be used to stop both
00415   *         injected and regular groups, and disable the ADC.
00416   * @note   If injected group mode auto-injection is enabled,
00417   *         function HAL_ADC_Stop must be used.
00418   * @note   In case of multimode enabled (when multimode feature is available),
00419   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
00420   *         For ADC master, conversion is stopped and ADC is disabled.
00421   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00422   *         has already stopped conversion of ADC slave).
00423   * @param hadc ADC handle.
00424   * @retval HAL status
00425   */
00426 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
00427 {
00428   HAL_StatusTypeDef tmp_hal_status;
00429
00430   /* Check the parameters */
00431   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00432
00433   /* Process locked */
00434   __HAL_LOCK(hadc);
00435
00436   /* 1. Stop potential conversion on going on injected group only. */
00437   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00438
00439   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00440   /* and if no conversion on regular group is on-going                       */
00441   if (tmp_hal_status == HAL_OK)
00442   {
00443     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00444     {
00445       /* 2. Disable the ADC peripheral */
00446       tmp_hal_status = ADC_Disable(hadc);
00447
00448       /* Check if ADC is effectively disabled */
00449       if (tmp_hal_status == HAL_OK)
00450       {
00451         /* Set ADC state */
00452         ADC_STATE_CLR_SET(hadc->State,
00453                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00454                           HAL_ADC_STATE_READY);
00455       }
00456     }
00457     /* Conversion on injected group is stopped, but ADC not disabled since    */
00458     /* conversion on regular group is still running.                          */
00459     else
00460     {
00461       /* Set ADC state */
00462       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00463     }
00464   }
00465
00466   /* Process unlocked */
00467   __HAL_UNLOCK(hadc);
00468
00469   /* Return function status */
00470   return tmp_hal_status;
00471 }
00472
00473 /**
00474   * @brief  Wait for injected group conversion to be completed.
00475   * @param hadc ADC handle
00476   * @param Timeout Timeout value in millisecond.
00477   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
00478   *         checked and cleared depending on AUTDLY bit status.
00479   * @retval HAL status
00480   */
00481 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
00482 {
00483   uint32_t tickstart;
00484   uint32_t tmp_flag_end;
00485   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
00486   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
00487   uint32_t tmp_cfgr;
00488 #if defined(ADC_MULTIMODE_SUPPORT)
00489   const ADC_TypeDef *tmpADC_Master;
00490   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00491 #endif /* ADC_MULTIMODE_SUPPORT */
00492
00493   /* Check the parameters */
00494   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00495
00496   /* If end of sequence selected */
00497   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00498   {
00499     tmp_flag_end = ADC_FLAG_JEOS;
00500   }
00501   else /* end of conversion selected */
00502   {
00503     tmp_flag_end = ADC_FLAG_JEOC;
00504   }
00505
00506   /* Get timeout */
00507   tickstart = HAL_GetTick();
00508
00509   /* Wait until End of Conversion or Sequence flag is raised */
00510   while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
00511   {
00512     /* Check if timeout is disabled (set to infinite wait) */
00513     if (Timeout != HAL_MAX_DELAY)
00514     {
00515       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
00516       {
00517         /* New check to avoid false timeout detection in case of preemption */
00518         if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
00519         {
00520           /* Update ADC state machine to timeout */
00521           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00522
00523           /* Process unlocked */
00524           __HAL_UNLOCK(hadc);
00525
00526           return HAL_TIMEOUT;
00527         }
00528       }
00529     }
00530   }
00531
00532   /* Retrieve ADC configuration */
00533   tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
00534   tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
00535   /* Get relevant register CFGR in ADC instance of ADC master or slave  */
00536   /* in function of multimode state (for devices with multimode         */
00537   /* available).                                                        */
00538 #if defined(ADC_MULTIMODE_SUPPORT)
00539   if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00540       || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00541       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00542       || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00543      )
00544   {
00545     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00546   }
00547   else
00548   {
00549     tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
00550     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
00551   }
00552 #else
00553   tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00554 #endif /* ADC_MULTIMODE_SUPPORT */
00555
00556   /* Update ADC state machine */
00557   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00558
00559   /* Determine whether any further conversion upcoming on group injected      */
00560   /* by external trigger or by automatic injected conversion                  */
00561   /* from group regular.                                                      */
00562   if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
00563       ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
00564        ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
00565         (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
00566   {
00567     /* Check whether end of sequence is reached */
00568     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
00569     {
00570       /* Particular case if injected contexts queue is enabled:             */
00571       /* when the last context has been fully processed, JSQR is reset      */
00572       /* by the hardware. Even if no injected conversion is planned to come */
00573       /* (queue empty, triggers are ignored), it can start again            */
00574       /* immediately after setting a new context (JADSTART is still set).   */
00575       /* Therefore, state of HAL ADC injected group is kept to busy.        */
00576       if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
00577       {
00578         /* Set ADC state */
00579         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00580
00581         if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
00582         {
00583           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00584         }
00585       }
00586     }
00587   }
00588
00589   /* Clear polled flag */
00590   if (tmp_flag_end == ADC_FLAG_JEOS)
00591   {
00592     /* Clear end of sequence JEOS flag of injected group if low power feature */
00593     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00594     /* For injected groups, no new conversion will start before JEOS is       */
00595     /* cleared.                                                               */
00596     if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
00597     {
00598       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00599     }
00600   }
00601   else
00602   {
00603     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00604   }
00605
00606   /* Return API HAL status */
00607   return HAL_OK;
00608 }
00609
00610 /**
00611   * @brief  Enable ADC, start conversion of injected group with interruption.
00612   * @note   Interruptions enabled in this function according to initialization
00613   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
00614   * @note   Case of multimode enabled (when multimode feature is enabled):
00615   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
00616   *         then for ADC master.
00617   *         For ADC slave, ADC is enabled only (conversion is not started).
00618   *         For ADC master, ADC is enabled and multimode conversion is started.
00619   * @param hadc ADC handle.
00620   * @retval HAL status.
00621   */
00622 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
00623 {
00624   HAL_StatusTypeDef tmp_hal_status;
00625   uint32_t tmp_config_injected_queue;
00626 #if defined(ADC_MULTIMODE_SUPPORT)
00627   uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
00628 #endif /* ADC_MULTIMODE_SUPPORT */
00629
00630   /* Check the parameters */
00631   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00632
00633   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00634   {
00635     return HAL_BUSY;
00636   }
00637   else
00638   {
00639     /* In case of software trigger detection enabled, JQDIS must be set
00640       (which can be done only if ADSTART and JADSTART are both cleared).
00641        If JQDIS is not set at that point, returns an error
00642        - since software trigger detection is disabled. User needs to
00643        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00644        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00645          the queue is empty */
00646     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00647
00648     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00649         && (tmp_config_injected_queue == 0UL)
00650        )
00651     {
00652       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00653       return HAL_ERROR;
00654     }
00655
00656     /* Process locked */
00657     __HAL_LOCK(hadc);
00658
00659     /* Enable the ADC peripheral */
00660     tmp_hal_status = ADC_Enable(hadc);
00661
00662     /* Start conversion if ADC is effectively enabled */
00663     if (tmp_hal_status == HAL_OK)
00664     {
00665       /* Check if a regular conversion is ongoing */
00666       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00667       {
00668         /* Reset ADC error code field related to injected conversions only */
00669         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00670       }
00671       else
00672       {
00673         /* Set ADC error code to none */
00674         ADC_CLEAR_ERRORCODE(hadc);
00675       }
00676
00677       /* Set ADC state                                                        */
00678       /* - Clear state bitfield related to injected group conversion results  */
00679       /* - Set state bitfield related to injected operation                   */
00680       ADC_STATE_CLR_SET(hadc->State,
00681                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00682                         HAL_ADC_STATE_INJ_BUSY);
00683
00684 #if defined(ADC_MULTIMODE_SUPPORT)
00685       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00686         - if ADC instance is master or if multimode feature is not available
00687         - if multimode setting is disabled (ADC instance slave in independent mode) */
00688       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00689           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00690          )
00691       {
00692         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00693       }
00694 #endif /* ADC_MULTIMODE_SUPPORT */
00695
00696       /* Clear ADC group injected group conversion flag */
00697       /* (To ensure of no unknown state from potential previous ADC operations) */
00698       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00699
00700       /* Process unlocked */
00701       /* Unlock before starting ADC conversions: in case of potential         */
00702       /* interruption, to let the process to ADC IRQ Handler.                 */
00703       __HAL_UNLOCK(hadc);
00704
00705       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00706       /* is enabled.                                                            */
00707       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
00708       {
00709         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00710       }
00711
00712       /* Enable ADC end of conversion interrupt */
00713       switch (hadc->Init.EOCSelection)
00714       {
00715         case ADC_EOC_SEQ_CONV:
00716           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00717           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00718           break;
00719         /* case ADC_EOC_SINGLE_CONV */
00720         default:
00721           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
00722           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00723           break;
00724       }
00725
00726       /* Enable conversion of injected group, if automatic injected conversion  */
00727       /* is disabled.                                                           */
00728       /* If software start has been selected, conversion starts immediately.    */
00729       /* If external trigger has been selected, conversion will start at next   */
00730       /* trigger event.                                                         */
00731       /* Case of multimode enabled (when multimode feature is available):       */
00732       /* if ADC is slave,                                                       */
00733       /*    - ADC is enabled only (conversion is not started),                  */
00734       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00735       /*     and conversion is started.                                         */
00736       /* If ADC is master or independent,                                       */
00737       /*    - ADC is enabled and conversion is started.                         */
00738 #if defined(ADC_MULTIMODE_SUPPORT)
00739       if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
00740           || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
00741           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
00742           || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
00743          )
00744       {
00745         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00746         if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00747         {
00748           LL_ADC_INJ_StartConversion(hadc->Instance);
00749         }
00750       }
00751       else
00752       {
00753         /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
00754         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00755       }
00756 #else
00757       if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00758       {
00759         /* Start ADC group injected conversion */
00760         LL_ADC_INJ_StartConversion(hadc->Instance);
00761       }
00762 #endif /* ADC_MULTIMODE_SUPPORT */
00763
00764     }
00765     else
00766     {
00767       /* Process unlocked */
00768       __HAL_UNLOCK(hadc);
00769     }
00770
00771     /* Return function status */
00772     return tmp_hal_status;
00773   }
00774 }
00775
00776 /**
00777   * @brief  Stop conversion of injected channels, disable interruption of
00778   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00779   *         is on going.
00780   * @note   If ADC must be disabled and if conversion is on going on
00781   *         regular group, function HAL_ADC_Stop must be used to stop both
00782   *         injected and regular groups, and disable the ADC.
00783   * @note   If injected group mode auto-injection is enabled,
00784   *         function HAL_ADC_Stop must be used.
00785   * @note   Case of multimode enabled (when multimode feature is available):
00786   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
00787   *         then for ADC slave.
00788   *         For ADC master, conversion is stopped and ADC is disabled.
00789   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00790   *         has already stopped conversion of ADC slave).
00791   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00792   * @param hadc ADC handle
00793   * @retval HAL status
00794   */
00795 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
00796 {
00797   HAL_StatusTypeDef tmp_hal_status;
00798
00799   /* Check the parameters */
00800   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00801
00802   /* Process locked */
00803   __HAL_LOCK(hadc);
00804
00805   /* 1. Stop potential conversion on going on injected group only. */
00806   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00807
00808   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00809   /* and if no conversion on the other group (regular group) is intended to   */
00810   /* continue.                                                                */
00811   if (tmp_hal_status == HAL_OK)
00812   {
00813     /* Disable ADC end of conversion interrupt for injected channels */
00814     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00815
00816     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00817     {
00818       /* 2. Disable the ADC peripheral */
00819       tmp_hal_status = ADC_Disable(hadc);
00820
00821       /* Check if ADC is effectively disabled */
00822       if (tmp_hal_status == HAL_OK)
00823       {
00824         /* Set ADC state */
00825         ADC_STATE_CLR_SET(hadc->State,
00826                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00827                           HAL_ADC_STATE_READY);
00828       }
00829     }
00830     /* Conversion on injected group is stopped, but ADC not disabled since    */
00831     /* conversion on regular group is still running.                          */
00832     else
00833     {
00834       /* Set ADC state */
00835       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00836     }
00837   }
00838
00839   /* Process unlocked */
00840   __HAL_UNLOCK(hadc);
00841
00842   /* Return function status */
00843   return tmp_hal_status;
00844 }
00845
00846 #if defined(ADC_MULTIMODE_SUPPORT)
00847 /**
00848   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
00849   * @note   Multimode must have been previously configured using
00850   *         HAL_ADCEx_MultiModeConfigChannel() function.
00851   *         Interruptions enabled in this function:
00852   *          overrun, DMA half transfer, DMA transfer complete.
00853   *         Each of these interruptions has its dedicated callback function.
00854   * @note   State field of Slave ADC handle is not updated in this configuration:
00855   *          user should not rely on it for information related to Slave regular
00856   *         conversions.
00857   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
00858   * @param pData Destination Buffer address.
00859   * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
00860   * @retval HAL status
00861   */
00862 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
00863 {
00864   HAL_StatusTypeDef tmp_hal_status;
00865   ADC_HandleTypeDef tmp_hadc_slave;
00866   ADC_Common_TypeDef *tmpADC_Common;
00867
00868   /* Check the parameters */
00869   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00870   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00871   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00872   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00873
00874   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
00875   {
00876     return HAL_BUSY;
00877   }
00878   else
00879   {
00880     /* Process locked */
00881     __HAL_LOCK(hadc);
00882
00883     /* Temporary handle minimum initialization */
00884     __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
00885     ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
00886
00887     /* Set a temporary handle of the ADC slave associated to the ADC master   */
00888     ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
00889
00890     if (tmp_hadc_slave.Instance == NULL)
00891     {
00892       /* Set ADC state */
00893       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00894
00895       /* Process unlocked */
00896       __HAL_UNLOCK(hadc);
00897
00898       return HAL_ERROR;
00899     }
00900
00901     /* Enable the ADC peripherals: master and slave (in case if not already   */
00902     /* enabled previously)                                                    */
00903     tmp_hal_status = ADC_Enable(hadc);
00904     if (tmp_hal_status == HAL_OK)
00905     {
00906       tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
00907     }
00908
00909     /* Start multimode conversion of ADCs pair */
00910     if (tmp_hal_status == HAL_OK)
00911     {
00912       /* Set ADC state */
00913       ADC_STATE_CLR_SET(hadc->State,
00914                         (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
00915                         HAL_ADC_STATE_REG_BUSY);
00916
00917       /* Set ADC error code to none */
00918       ADC_CLEAR_ERRORCODE(hadc);
00919
00920       /* Set the DMA transfer complete callback */
00921       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
00922
00923       /* Set the DMA half transfer complete callback */
00924       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
00925
00926       /* Set the DMA error callback */
00927       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
00928
00929       /* Pointer to the common control register  */
00930       tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
00931
00932       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
00933       /* start (in case of SW start):                                           */
00934
00935       /* Clear regular group conversion flag and overrun flag */
00936       /* (To ensure of no unknown state from potential previous ADC operations) */
00937       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
00938
00939       /* Process unlocked */
00940       /* Unlock before starting ADC conversions: in case of potential         */
00941       /* interruption, to let the process to ADC IRQ Handler.                 */
00942       __HAL_UNLOCK(hadc);
00943
00944       /* Enable ADC overrun interrupt */
00945       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
00946
00947       /* Start the DMA channel */
00948       tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
00949
00950       /* Enable conversion of regular group.                                    */
00951       /* If software start has been selected, conversion starts immediately.    */
00952       /* If external trigger has been selected, conversion will start at next   */
00953       /* trigger event.                                                         */
00954       /* Start ADC group regular conversion */
00955       LL_ADC_REG_StartConversion(hadc->Instance);
00956     }
00957     else
00958     {
00959       /* Process unlocked */
00960       __HAL_UNLOCK(hadc);
00961     }
00962
00963     /* Return function status */
00964     return tmp_hal_status;
00965   }
00966 }
00967
00968 /**
00969   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
00970   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
00971   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
00972   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
00973   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
00974   *         resort to HAL_ADCEx_DisableMultiMode() API.
00975   * @note   In case of DMA configured in circular mode, function
00976   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
00977   *         ADC slave, to properly disable the DMA channel.
00978   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
00982 {
00983   HAL_StatusTypeDef tmp_hal_status;
00984   uint32_t tickstart;
00985   ADC_HandleTypeDef tmp_hadc_slave;
00986   uint32_t tmp_hadc_slave_conversion_on_going;
00987   HAL_StatusTypeDef tmp_hadc_slave_disable_status;
00988
00989   /* Check the parameters */
00990   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00991
00992   /* Process locked */
00993   __HAL_LOCK(hadc);
00994
00995   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
00996   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00997
00998   /* Disable ADC peripheral if conversions are effectively stopped */
00999   if (tmp_hal_status == HAL_OK)
01000   {
01001     /* Temporary handle minimum initialization */
01002     __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
01003     ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
01004
01005     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01006     ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
01007
01008     if (tmp_hadc_slave.Instance == NULL)
01009     {
01010       /* Update ADC state machine to error */
01011       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01012
01013       /* Process unlocked */
01014       __HAL_UNLOCK(hadc);
01015
01016       return HAL_ERROR;
01017     }
01018
01019     /* Procedure to disable the ADC peripheral: wait for conversions          */
01020     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01021
01022     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
01023     tickstart = HAL_GetTick();
01024
01025     tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01026     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01027            || (tmp_hadc_slave_conversion_on_going == 1UL)
01028           )
01029     {
01030       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01031       {
01032         /* New check to avoid false timeout detection in case of preemption */
01033         tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01034         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01035             || (tmp_hadc_slave_conversion_on_going == 1UL)
01036            )
01037         {
01038           /* Update ADC state machine to error */
01039           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01040
01041           /* Process unlocked */
01042           __HAL_UNLOCK(hadc);
01043
01044           return HAL_ERROR;
01045         }
01046       }
01047
01048       tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01049     }
01050
01051     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01052     /* while DMA transfer is on going)                                        */
01053     /* Note: DMA channel of ADC slave should be stopped after this function   */
01054     /*       with HAL_ADC_Stop_DMA() API.                                     */
01055     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01056
01057     /* Check if DMA channel effectively disabled */
01058     if (tmp_hal_status == HAL_ERROR)
01059     {
01060       /* Update ADC state machine to error */
01061       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01062     }
01063
01064     /* Disable ADC overrun interrupt */
01065     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01066
01067     /* 2. Disable the ADC peripherals: master and slave */
01068     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
01069     /* memory a potential failing status.                                     */
01070     if (tmp_hal_status == HAL_OK)
01071     {
01072       tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
01073       if ((ADC_Disable(hadc) == HAL_OK)           &&
01074           (tmp_hadc_slave_disable_status == HAL_OK))
01075       {
01076         tmp_hal_status = HAL_OK;
01077       }
01078     }
01079     else
01080     {
01081       /* In case of error, attempt to disable ADC master and slave without status assert */
01082       (void) ADC_Disable(hadc);
01083       (void) ADC_Disable(&tmp_hadc_slave);
01084     }
01085
01086     /* Set ADC state (ADC master) */
01087     ADC_STATE_CLR_SET(hadc->State,
01088                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01089                       HAL_ADC_STATE_READY);
01090   }
01091
01092   /* Process unlocked */
01093   __HAL_UNLOCK(hadc);
01094
01095   /* Return function status */
01096   return tmp_hal_status;
01097 }
01098
01099 /**
01100   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
01101   * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
01102   * @retval The converted data values.
01103   */
01104 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
01105 {
01106   const ADC_Common_TypeDef *tmpADC_Common;
01107
01108   /* Check the parameters */
01109   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01110
01111   /* Prevent unused argument(s) compilation warning if no assert_param check */
01112   /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
01113   UNUSED(hadc);
01114
01115   /* Pointer to the common control register  */
01116   tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
01117
01118   /* Return the multi mode conversion value */
01119   return tmpADC_Common->CDR;
01120 }
01121 #endif /* ADC_MULTIMODE_SUPPORT */
01122
01123 /**
01124   * @brief  Get ADC injected group conversion result.
01125   * @note   Reading register JDRx automatically clears ADC flag JEOC
01126   *         (ADC group injected end of unitary conversion).
01127   * @note   This function does not clear ADC flag JEOS
01128   *         (ADC group injected end of sequence conversion)
01129   *         Occurrence of flag JEOS rising:
01130   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
01131   *            to flag JEOC.
01132   *          - If sequencer is composed of several ranks, during the scan
01133   *            sequence flag JEOC only is raised, at the end of the scan sequence
01134   *            both flags JEOC and EOS are raised.
01135   *         Flag JEOS must not be cleared by this function because
01136   *         it would not be compliant with low power features
01137   *         (feature low power auto-wait, not available on all STM32 series).
01138   *         To clear this flag, either use function:
01139   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01140   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
01141   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
01142   * @param hadc ADC handle
01143   * @param InjectedRank the converted ADC injected rank.
01144   *          This parameter can be one of the following values:
01145   *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
01146   *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
01147   *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
01148   *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
01149   * @retval ADC group injected conversion data
01150   */
01151 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
01152 {
01153   uint32_t tmp_jdr;
01154
01155   /* Check the parameters */
01156   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01157   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
01158
01159   /* Get ADC converted value */
01160   switch (InjectedRank)
01161   {
01162     case ADC_INJECTED_RANK_4:
01163       tmp_jdr = hadc->Instance->JDR4;
01164       break;
01165     case ADC_INJECTED_RANK_3:
01166       tmp_jdr = hadc->Instance->JDR3;
01167       break;
01168     case ADC_INJECTED_RANK_2:
01169       tmp_jdr = hadc->Instance->JDR2;
01170       break;
01171     case ADC_INJECTED_RANK_1:
01172     default:
01173       tmp_jdr = hadc->Instance->JDR1;
01174       break;
01175   }
01176
01177   /* Return ADC converted value */
01178   return tmp_jdr;
01179 }
01180
01181 /**
01182   * @brief  Injected conversion complete callback in non-blocking mode.
01183   * @param hadc ADC handle
01184   * @retval None
01185   */
01186 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
01187 {
01188   /* Prevent unused argument(s) compilation warning */
01189   UNUSED(hadc);
01190
01191   /* NOTE : This function should not be modified. When the callback is needed,
01192             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
01193   */
01194 }
01195
01196 /**
01197   * @brief  Injected context queue overflow callback.
01198   * @note   This callback is called if injected context queue is enabled
01199             (parameter "QueueInjectedContext" in injected channel configuration)
01200             and if a new injected context is set when queue is full (maximum 2
01201             contexts).
01202   * @param hadc ADC handle
01203   * @retval None
01204   */
01205 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
01206 {
01207   /* Prevent unused argument(s) compilation warning */
01208   UNUSED(hadc);
01209
01210   /* NOTE : This function should not be modified. When the callback is needed,
01211             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
01212   */
01213 }
01214
01215 /**
01216   * @brief  Analog watchdog 2 callback in non-blocking mode.
01217   * @param hadc ADC handle
01218   * @retval None
01219   */
01220 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
01221 {
01222   /* Prevent unused argument(s) compilation warning */
01223   UNUSED(hadc);
01224
01225   /* NOTE : This function should not be modified. When the callback is needed,
01226             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
01227   */
01228 }
01229
01230 /**
01231   * @brief  Analog watchdog 3 callback in non-blocking mode.
01232   * @param hadc ADC handle
01233   * @retval None
01234   */
01235 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
01236 {
01237   /* Prevent unused argument(s) compilation warning */
01238   UNUSED(hadc);
01239
01240   /* NOTE : This function should not be modified. When the callback is needed,
01241             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
01242   */
01243 }
01244
01245
01246 /**
01247   * @brief  End Of Sampling callback in non-blocking mode.
01248   * @param hadc ADC handle
01249   * @retval None
01250   */
01251 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
01252 {
01253   /* Prevent unused argument(s) compilation warning */
01254   UNUSED(hadc);
01255
01256   /* NOTE : This function should not be modified. When the callback is needed,
01257             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
01258   */
01259 }
01260
01261 /**
01262   * @brief  Stop ADC conversion of regular group (and injected channels in
01263   *         case of auto_injection mode), disable ADC peripheral if no
01264   *         conversion is on going on injected group.
01265   * @param hadc ADC handle
01266   * @retval HAL status.
01267   */
01268 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
01269 {
01270   HAL_StatusTypeDef tmp_hal_status;
01271
01272   /* Check the parameters */
01273   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01274
01275   /* Process locked */
01276   __HAL_LOCK(hadc);
01277
01278   /* 1. Stop potential regular conversion on going */
01279   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01280
01281   /* Disable ADC peripheral if regular conversions are effectively stopped
01282      and if no injected conversions are on-going */
01283   if (tmp_hal_status == HAL_OK)
01284   {
01285     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01286     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01287
01288     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01289     {
01290       /* 2. Disable the ADC peripheral */
01291       tmp_hal_status = ADC_Disable(hadc);
01292
01293       /* Check if ADC is effectively disabled */
01294       if (tmp_hal_status == HAL_OK)
01295       {
01296         /* Set ADC state */
01297         ADC_STATE_CLR_SET(hadc->State,
01298                           HAL_ADC_STATE_INJ_BUSY,
01299                           HAL_ADC_STATE_READY);
01300       }
01301     }
01302     /* Conversion on injected group is stopped, but ADC not disabled since    */
01303     /* conversion on regular group is still running.                          */
01304     else
01305     {
01306       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01307     }
01308   }
01309
01310   /* Process unlocked */
01311   __HAL_UNLOCK(hadc);
01312
01313   /* Return function status */
01314   return tmp_hal_status;
01315 }
01316
01317
01318 /**
01319   * @brief  Stop ADC conversion of ADC groups regular and injected,
01320   *         disable interrution of end-of-conversion,
01321   *         disable ADC peripheral if no conversion is on going
01322   *         on injected group.
01323   * @param hadc ADC handle
01324   * @retval HAL status.
01325   */
01326 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
01327 {
01328   HAL_StatusTypeDef tmp_hal_status;
01329
01330   /* Check the parameters */
01331   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01332
01333   /* Process locked */
01334   __HAL_LOCK(hadc);
01335
01336   /* 1. Stop potential regular conversion on going */
01337   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01338
01339   /* Disable ADC peripheral if conversions are effectively stopped
01340     and if no injected conversion is on-going */
01341   if (tmp_hal_status == HAL_OK)
01342   {
01343     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01344     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01345
01346     /* Disable all regular-related interrupts */
01347     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01348
01349     /* 2. Disable ADC peripheral if no injected conversions are on-going */
01350     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01351     {
01352       tmp_hal_status = ADC_Disable(hadc);
01353       /* if no issue reported */
01354       if (tmp_hal_status == HAL_OK)
01355       {
01356         /* Set ADC state */
01357         ADC_STATE_CLR_SET(hadc->State,
01358                           HAL_ADC_STATE_INJ_BUSY,
01359                           HAL_ADC_STATE_READY);
01360       }
01361     }
01362     else
01363     {
01364       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01365     }
01366   }
01367
01368   /* Process unlocked */
01369   __HAL_UNLOCK(hadc);
01370
01371   /* Return function status */
01372   return tmp_hal_status;
01373 }
01374
01375 /**
01376   * @brief  Stop ADC conversion of regular group (and injected group in
01377   *         case of auto_injection mode), disable ADC DMA transfer, disable
01378   *         ADC peripheral if no conversion is on going
01379   *         on injected group.
01380   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
01381   *         For multimode (when multimode feature is available),
01382   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
01383   * @param hadc ADC handle
01384   * @retval HAL status.
01385   */
01386 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
01387 {
01388   HAL_StatusTypeDef tmp_hal_status;
01389
01390   /* Check the parameters */
01391   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01392
01393   /* Process locked */
01394   __HAL_LOCK(hadc);
01395
01396   /* 1. Stop potential regular conversion on going */
01397   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01398
01399   /* Disable ADC peripheral if conversions are effectively stopped
01400      and if no injected conversion is on-going */
01401   if (tmp_hal_status == HAL_OK)
01402   {
01403     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01404     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01405
01406     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01407     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01408
01409     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01410     /* while DMA transfer is on going)                                        */
01411     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01412
01413     /* Check if DMA channel effectively disabled */
01414     if (tmp_hal_status != HAL_OK)
01415     {
01416       /* Update ADC state machine to error */
01417       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01418     }
01419
01420     /* Disable ADC overrun interrupt */
01421     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01422
01423     /* 2. Disable the ADC peripheral */
01424     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
01425     /* to keep in memory a potential failing status.                          */
01426     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01427     {
01428       if (tmp_hal_status == HAL_OK)
01429       {
01430         tmp_hal_status = ADC_Disable(hadc);
01431       }
01432       else
01433       {
01434         (void)ADC_Disable(hadc);
01435       }
01436
01437       /* Check if ADC is effectively disabled */
01438       if (tmp_hal_status == HAL_OK)
01439       {
01440         /* Set ADC state */
01441         ADC_STATE_CLR_SET(hadc->State,
01442                           HAL_ADC_STATE_INJ_BUSY,
01443                           HAL_ADC_STATE_READY);
01444       }
01445     }
01446     else
01447     {
01448       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01449     }
01450   }
01451
01452   /* Process unlocked */
01453   __HAL_UNLOCK(hadc);
01454
01455   /* Return function status */
01456   return tmp_hal_status;
01457 }
01458
01459 #if defined(ADC_MULTIMODE_SUPPORT)
01460 /**
01461   * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
01462   *         conversion is on-going.
01463   * @note   Multimode is kept enabled after this function. Multimode DMA bits
01464   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01465   *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01466   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01467   *         resort to HAL_ADCEx_DisableMultiMode() API.
01468   * @note   In case of DMA configured in circular mode, function
01469   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
01470   *         ADC slave, to properly disable the DMA channel.
01471   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
01472   * @retval HAL status
01473   */
01474 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
01475 {
01476   HAL_StatusTypeDef tmp_hal_status;
01477   uint32_t tickstart;
01478   ADC_HandleTypeDef tmp_hadc_slave;
01479   uint32_t tmp_hadc_slave_conversion_on_going;
01480
01481   /* Check the parameters */
01482   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01483
01484   /* Process locked */
01485   __HAL_LOCK(hadc);
01486
01487
01488   /* 1. Stop potential multimode conversion on going, on regular groups */
01489   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01490
01491   /* Disable ADC peripheral if conversions are effectively stopped */
01492   if (tmp_hal_status == HAL_OK)
01493   {
01494     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01495     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01496
01497     /* Temporary handle minimum initialization */
01498     __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
01499     ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
01500
01501     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01502     ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
01503
01504     if (tmp_hadc_slave.Instance == NULL)
01505     {
01506       /* Update ADC state machine to error */
01507       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01508
01509       /* Process unlocked */
01510       __HAL_UNLOCK(hadc);
01511
01512       return HAL_ERROR;
01513     }
01514
01515     /* Procedure to disable the ADC peripheral: wait for conversions          */
01516     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01517
01518     /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
01519     tickstart = HAL_GetTick();
01520
01521     tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01522     while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01523            || (tmp_hadc_slave_conversion_on_going == 1UL)
01524           )
01525     {
01526       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01527       {
01528         /* New check to avoid false timeout detection in case of preemption */
01529         tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01530         if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
01531             || (tmp_hadc_slave_conversion_on_going == 1UL)
01532            )
01533         {
01534           /* Update ADC state machine to error */
01535           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01536
01537           /* Process unlocked */
01538           __HAL_UNLOCK(hadc);
01539
01540           return HAL_ERROR;
01541         }
01542       }
01543
01544       tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
01545     }
01546
01547     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01548     /* while DMA transfer is on going)                                        */
01549     /* Note: DMA channel of ADC slave should be stopped after this function   */
01550     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
01551     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01552
01553     /* Check if DMA channel effectively disabled */
01554     if (tmp_hal_status != HAL_OK)
01555     {
01556       /* Update ADC state machine to error */
01557       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01558     }
01559
01560     /* Disable ADC overrun interrupt */
01561     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01562
01563     /* 2. Disable the ADC peripherals: master and slave if no injected        */
01564     /*   conversion is on-going.                                              */
01565     /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
01566     /* memory a potential failing status.                                     */
01567     if (tmp_hal_status == HAL_OK)
01568     {
01569       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01570       {
01571         tmp_hal_status =  ADC_Disable(hadc);
01572         if (tmp_hal_status == HAL_OK)
01573         {
01574           if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
01575           {
01576             tmp_hal_status =  ADC_Disable(&tmp_hadc_slave);
01577           }
01578         }
01579       }
01580
01581       if (tmp_hal_status == HAL_OK)
01582       {
01583         /* Both Master and Slave ADC's could be disabled. Update Master State */
01584         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01585         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01586       }
01587       else
01588       {
01589         /* injected (Master or Slave) conversions are still on-going,
01590            no Master State change */
01591       }
01592     }
01593   }
01594
01595   /* Process unlocked */
01596   __HAL_UNLOCK(hadc);
01597
01598   /* Return function status */
01599   return tmp_hal_status;
01600 }
01601 #endif /* ADC_MULTIMODE_SUPPORT */
01602
01603 /**
01604   * @}
01605   */
01606
01607 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
01608   * @brief    ADC Extended Peripheral Control functions
01609   *
01610 @verbatim
01611  ===============================================================================
01612              ##### Peripheral Control functions #####
01613  ===============================================================================
01614     [..]  This section provides functions allowing to:
01615       (+) Configure channels on injected group
01616       (+) Configure multimode when multimode feature is available
01617       (+) Enable or Disable Injected Queue
01618       (+) Disable ADC voltage regulator
01619       (+) Enter ADC deep-power-down mode
01620
01621 @endverbatim
01622   * @{
01623   */
01624
01625 /**
01626   * @brief  Configure a channel to be assigned to ADC group injected.
01627   * @note   Possibility to update parameters on the fly:
01628   *         This function initializes injected group, following calls to this
01629   *         function can be used to reconfigure some parameters of structure
01630   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01631   *         The setting of these parameters is conditioned to ADC state:
01632   *         Refer to comments of structure "ADC_InjectionConfTypeDef".
01633   * @note   In case of usage of internal measurement channels:
01634   *         Vbat/VrefInt/TempSensor.
01635   *         These internal paths can be disabled using function
01636   *         HAL_ADC_DeInit().
01637   * @note   Caution: For Injected Context Queue use, a context must be fully
01638   *         defined before start of injected conversion. All channels are configured
01639   *         consecutively for the same ADC instance. Therefore, the number of calls to
01640   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
01641   *         InjectedNbrOfConversion for each context.
01642   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
01643   *    Injected Queue Context feature) and if the context contains 3 injected ranks
01644   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
01645   *    called once for each channel (i.e. 3 times) before starting a conversion.
01646   *    This function must not be called to configure a 4th injected channel:
01647   *    it would start a new context into context queue.
01648   *  - Example 2: If 2 contexts are intended to be used and each of them contains
01649   *    3 injected ranks (InjectedNbrOfConversion = 3),
01650   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
01651   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
01652   *    start once the 1st context is set, that is after the first three
01653   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01654   * @param hadc ADC handle
01655   * @param pConfigInjected Structure of ADC injected group and ADC channel for
01656   *         injected group.
01657   * @retval HAL status
01658   */
01659 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
01660                                                   const ADC_InjectionConfTypeDef *pConfigInjected)
01661 {
01662   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01663   uint32_t tmp_offset_shifted;
01664   uint32_t tmp_config_internal_channel;
01665   uint32_t tmp_adc_is_conversion_on_going_regular;
01666   uint32_t tmp_adc_is_conversion_on_going_injected;
01667   __IO uint32_t wait_loop_index = 0;
01668
01669   uint32_t tmp_jsqr_context_queue_being_built = 0U;
01670
01671   /* Check the parameters */
01672   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01673   assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
01674   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
01675   assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
01676   assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
01677   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
01678   assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
01679   assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
01680   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
01681   assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
01682   assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
01683   assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
01684
01685   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01686   {
01687     assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
01688     assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
01689     assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
01690   }
01691
01692
01693   /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
01694      ignored (considered as reset) */
01695   assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
01696                  && (pConfigInjected->InjecOversamplingMode == ENABLE)));
01697
01698   /* JDISCEN and JAUTO bits can't be set at the same time  */
01699   assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
01700                  && (pConfigInjected->AutoInjectedConv == ENABLE)));
01701
01702   /*  DISCEN and JAUTO bits can't be set at the same time */
01703   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
01704
01705   /* Verification of channel number */
01706   if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01707   {
01708     assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
01709   }
01710   else
01711   {
01712     assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
01713   }
01714
01715   /* Process locked */
01716   __HAL_LOCK(hadc);
01717
01718   /* Configuration of injected group sequencer:                               */
01719   /* Hardware constraint: Must fully define injected context register JSQR    */
01720   /* before make it entering into injected sequencer queue.                   */
01721   /*                                                                          */
01722   /* - if scan mode is disabled:                                              */
01723   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01724   /*      converted (channel on injected rank 1)                              */
01725   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01726   /*    * Injected context register JSQR setting is simple: register is fully */
01727   /*      defined on one call of this function (for injected rank 1) and can  */
01728   /*      be entered into queue directly.                                     */
01729   /* - if scan mode is enabled:                                               */
01730   /*    * Injected channels sequence length is set to parameter               */
01731   /*      "InjectedNbrOfConversion".                                          */
01732   /*    * Injected context register JSQR setting more complex: register is    */
01733   /*      fully defined over successive calls of this function, for each      */
01734   /*      injected channel rank. It is entered into queue only when all       */
01735   /*      injected ranks have been set.                                       */
01736   /*   Note: Scan mode is not present by hardware on this device, but used    */
01737   /*   by software for alignment over all STM32 devices.                      */
01738
01739   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01740       (pConfigInjected->InjectedNbrOfConversion == 1U))
01741   {
01742     /* Configuration of context register JSQR:                                */
01743     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01744     /*    (scan mode disabled, only rank 1 used)                              */
01745     /*  - external trigger to start conversion                                */
01746     /*  - external trigger polarity                                           */
01747     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01748
01749     if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01750     {
01751       /* Enable external trigger if trigger selection is different of         */
01752       /* software start.                                                      */
01753       /* Note: This configuration keeps the hardware feature of parameter     */
01754       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01755       /*       software start.                                                */
01756       if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01757       {
01758         tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
01759                                               | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01760                                               | pConfigInjected->ExternalTrigInjecConvEdge
01761                                              );
01762       }
01763       else
01764       {
01765         tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
01766       }
01767
01768       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
01769       /* For debug and informative reasons, hadc handle saves JSQR setting */
01770       hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
01771
01772     }
01773   }
01774   else
01775   {
01776     /* Case of scan mode enabled, several channels to set into injected group */
01777     /* sequencer.                                                             */
01778     /*                                                                        */
01779     /* Procedure to define injected context register JSQR over successive     */
01780     /* calls of this function, for each injected channel rank:                */
01781     /* 1. Start new context and set parameters related to all injected        */
01782     /*    channels: injected sequence length and trigger.                     */
01783
01784     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01785     /*   call of the context under setting                                    */
01786     if (hadc->InjectionConfig.ChannelCount == 0U)
01787     {
01788       /* Initialize number of channels that will be configured on the context */
01789       /*  being built                                                         */
01790       hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
01791       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01792          call, this context will be written in JSQR register at the last call.
01793          At this point, the context is merely reset  */
01794       hadc->InjectionConfig.ContextQueue = 0x00000000U;
01795
01796       /* Configuration of context register JSQR:                              */
01797       /*  - number of ranks in injected group sequencer                       */
01798       /*  - external trigger to start conversion                              */
01799       /*  - external trigger polarity                                         */
01800
01801       /* Enable external trigger if trigger selection is different of         */
01802       /* software start.                                                      */
01803       /* Note: This configuration keeps the hardware feature of parameter     */
01804       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01805       /*       software start.                                                */
01806       if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01807       {
01808         tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
01809                                               | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01810                                               | pConfigInjected->ExternalTrigInjecConvEdge
01811                                              );
01812       }
01813       else
01814       {
01815         tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
01816       }
01817
01818     }
01819
01820     /* 2. Continue setting of context under definition with parameter       */
01821     /*    related to each channel: channel rank sequence                    */
01822     /* Clear the old JSQx bits for the selected rank */
01823     tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
01824
01825     /* Set the JSQx bits for the selected rank */
01826     tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
01827
01828     /* Decrease channel count  */
01829     hadc->InjectionConfig.ChannelCount--;
01830
01831     /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
01832           call, aggregate the setting to those already built during the previous
01833           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01834     hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
01835
01836     /* 4. End of context setting: if this is the last channel set, then write context
01837         into register JSQR and make it enter into queue                   */
01838     if (hadc->InjectionConfig.ChannelCount == 0U)
01839     {
01840       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
01841     }
01842   }
01843
01844   /* Parameters update conditioned to ADC state:                              */
01845   /* Parameters that can be updated when ADC is disabled or enabled without   */
01846   /* conversion on going on injected group:                                   */
01847   /*  - Injected context queue: Queue disable (active context is kept) or     */
01848   /*    enable (context decremented, up to 2 contexts queued)                 */
01849   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01850   /*    mode is disabled.                                                     */
01851   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01852   {
01853     /* If auto-injected mode is disabled: no constraint                       */
01854     if (pConfigInjected->AutoInjectedConv == DISABLE)
01855     {
01856       MODIFY_REG(hadc->Instance->CFGR,
01857                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01858                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)           |
01859                  ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
01860     }
01861     /* If auto-injected mode is enabled: Injected discontinuous setting is    */
01862     /* discarded.                                                             */
01863     else
01864     {
01865       MODIFY_REG(hadc->Instance->CFGR,
01866                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01867                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
01868     }
01869
01870   }
01871
01872   /* Parameters update conditioned to ADC state:                              */
01873   /* Parameters that can be updated when ADC is disabled or enabled without   */
01874   /* conversion on going on regular and injected groups:                      */
01875   /*  - Automatic injected conversion: can be enabled if injected group       */
01876   /*    external triggers are disabled.                                       */
01877   /*  - Channel sampling time                                                 */
01878   /*  - Channel offset                                                        */
01879   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
01880   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
01881
01882   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
01883       && (tmp_adc_is_conversion_on_going_injected == 0UL)
01884      )
01885   {
01886     /* If injected group external triggers are disabled (set to injected      */
01887     /* software start): no constraint                                         */
01888     if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
01889         || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01890     {
01891       if (pConfigInjected->AutoInjectedConv == ENABLE)
01892       {
01893         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01894       }
01895       else
01896       {
01897         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01898       }
01899     }
01900     /* If Automatic injected conversion was intended to be set and could not  */
01901     /* due to injected group external triggers enabled, error is reported.    */
01902     else
01903     {
01904       if (pConfigInjected->AutoInjectedConv == ENABLE)
01905       {
01906         /* Update ADC state machine to error */
01907         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01908
01909         tmp_hal_status = HAL_ERROR;
01910       }
01911       else
01912       {
01913         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01914       }
01915     }
01916
01917     if (pConfigInjected->InjecOversamplingMode == ENABLE)
01918     {
01919       assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
01920       assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
01921
01922       /*  JOVSE must be reset in case of triggered regular mode  */
01923       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
01924                      == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
01925
01926       /* Configuration of Injected Oversampler:                                 */
01927       /*  - Oversampling Ratio                                                  */
01928       /*  - Right bit shift                                                     */
01929
01930       /* Enable OverSampling mode */
01931       MODIFY_REG(hadc->Instance->CFGR2,
01932                  ADC_CFGR2_JOVSE |
01933                  ADC_CFGR2_OVSR  |
01934                  ADC_CFGR2_OVSS,
01935                  ADC_CFGR2_JOVSE                                  |
01936                  pConfigInjected->InjecOversampling.Ratio         |
01937                  pConfigInjected->InjecOversampling.RightBitShift
01938                 );
01939     }
01940     else
01941     {
01942       /* Disable Regular OverSampling */
01943       CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
01944     }
01945
01946     /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
01947     if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
01948     {
01949       /* Set sampling time of the selected ADC channel */
01950       LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
01951
01952       /* Set ADC sampling time common configuration */
01953       LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
01954     }
01955     else
01956     {
01957       /* Set sampling time of the selected ADC channel */
01958       LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
01959                                     pConfigInjected->InjectedSamplingTime);
01960
01961       /* Set ADC sampling time common configuration */
01962       LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
01963     }
01964
01965     /* Configure the offset: offset enable/disable, channel, offset value */
01966
01967     /* Shift the offset with respect to the selected ADC resolution. */
01968     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
01969     tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
01970
01971     if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
01972     {
01973       /* Set ADC selected offset number */
01974       LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
01975                        tmp_offset_shifted);
01976
01977       /* Set ADC selected offset sign & saturation */
01978       LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
01979       LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
01980                                  (pConfigInjected->InjectedOffsetSaturation == ENABLE) ?
01981                                  LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
01982     }
01983     else
01984     {
01985       /* Scan each offset register to check if the selected channel is targeted. */
01986       /* If this is the case, the corresponding offset number is disabled.       */
01987       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
01988           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
01989       {
01990         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
01991       }
01992       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
01993           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
01994       {
01995         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
01996       }
01997       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
01998           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
01999       {
02000         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
02001       }
02002       if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
02003           == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
02004       {
02005         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
02006       }
02007     }
02008
02009   }
02010
02011   /* Parameters update conditioned to ADC state:                              */
02012   /* Parameters that can be updated only when ADC is disabled:                */
02013   /*  - Single or differential mode                                           */
02014   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02015   {
02016     /* Set mode single-ended or differential input of the selected ADC channel */
02017     LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
02018
02019     /* Configuration of differential mode */
02020     /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
02021     if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
02022     {
02023       /* Set sampling time of the selected ADC channel */
02024       LL_ADC_SetChannelSamplingTime(hadc->Instance,
02025                                     (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
02026                                                  (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
02027                                                     (uint32_t)pConfigInjected->InjectedChannel)
02028                                                   + 1UL) & 0x1FUL)),
02029                                     pConfigInjected->InjectedSamplingTime);
02030     }
02031
02032   }
02033
02034   /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
02035   /* internal measurement paths enable: If internal channel selected,       */
02036   /* enable dedicated internal buffers and path.                            */
02037   /* Note: these internal measurement paths can be disabled using           */
02038   /* HAL_ADC_DeInit().                                                      */
02039
02040   if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
02041   {
02042     tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02043
02044     /* If the requested internal measurement path has already been enabled,   */
02045     /* bypass the configuration processing.                                   */
02046     if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1)
02047          || (pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5))
02048         && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02049     {
02050       if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02051       {
02052         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02053                                        LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02054
02055         /* Delay for temperature sensor stabilization time */
02056         /* Wait loop initialization and execution */
02057         /* Note: Variable divided by 2 to compensate partially              */
02058         /*       CPU processing cycles, scaling in us split to not          */
02059         /*       exceed 32 bits register capacity and handle low frequency. */
02060         wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
02061                            * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
02062         while (wait_loop_index != 0UL)
02063         {
02064           wait_loop_index--;
02065         }
02066       }
02067     }
02068     else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
02069              && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02070     {
02071       if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02072       {
02073         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02074                                        LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02075       }
02076     }
02077     else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
02078              && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02079     {
02080       if (ADC_VREFINT_INSTANCE(hadc))
02081       {
02082         LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02083                                        LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02084       }
02085     }
02086     else
02087     {
02088       /* nothing to do */
02089     }
02090   }
02091
02092   /* Process unlocked */
02093   __HAL_UNLOCK(hadc);
02094
02095   /* Return function status */
02096   return tmp_hal_status;
02097 }
02098
02099 #if defined(ADC_MULTIMODE_SUPPORT)
02100 /**
02101   * @brief  Enable ADC multimode and configure multimode parameters
02102   * @note   Possibility to update parameters on the fly:
02103   *         This function initializes multimode parameters, following
02104   *         calls to this function can be used to reconfigure some parameters
02105   *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
02106   *         the ADCs.
02107   *         The setting of these parameters is conditioned to ADC state.
02108   *         For parameters constraints, see comments of structure
02109   *         "ADC_MultiModeTypeDef".
02110   * @note   To move back configuration from multimode to single mode, ADC must
02111   *         be reset (using function HAL_ADC_Init() ).
02112   * @param hadc Master ADC handle
02113   * @param pMultimode Structure of ADC multimode configuration
02114   * @retval HAL status
02115   */
02116 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
02117 {
02118   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02119   ADC_Common_TypeDef *tmpADC_Common;
02120   ADC_HandleTypeDef tmp_hadc_slave;
02121   uint32_t tmp_hadc_slave_conversion_on_going;
02122
02123   /* Check the parameters */
02124   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
02125   assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
02126   if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
02127   {
02128     assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
02129     assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
02130   }
02131
02132   /* Process locked */
02133   __HAL_LOCK(hadc);
02134
02135   /* Temporary handle minimum initialization */
02136   __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
02137   ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
02138
02139   ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
02140
02141   if (tmp_hadc_slave.Instance == NULL)
02142   {
02143     /* Update ADC state machine to error */
02144     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02145
02146     /* Process unlocked */
02147     __HAL_UNLOCK(hadc);
02148
02149     return HAL_ERROR;
02150   }
02151
02152   /* Parameters update conditioned to ADC state:                              */
02153   /* Parameters that can be updated when ADC is disabled or enabled without   */
02154   /* conversion on going on regular group:                                    */
02155   /*  - Multimode DMA configuration                                           */
02156   /*  - Multimode DMA mode                                                    */
02157   tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
02158   if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02159       && (tmp_hadc_slave_conversion_on_going == 0UL))
02160   {
02161     /* Pointer to the common control register */
02162     tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
02163
02164     /* If multimode is selected, configure all multimode parameters.          */
02165     /* Otherwise, reset multimode parameters (can be used in case of          */
02166     /* transition from multimode to independent mode).                        */
02167     if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
02168     {
02169       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
02170                  pMultimode->DMAAccessMode |
02171                  ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
02172
02173       /* Parameters that can be updated only when ADC is disabled:                */
02174       /*  - Multimode mode selection                                              */
02175       /*  - Multimode delay                                                       */
02176       /*    Note: Delay range depends on selected resolution:                     */
02177       /*      from 1 to 12 clock cycles for 12 bits                               */
02178       /*      from 1 to 10 clock cycles for 10 bits,                              */
02179       /*      from 1 to 8 clock cycles for 8 bits                                 */
02180       /*      from 1 to 6 clock cycles for 6 bits                                 */
02181       /*    If a higher delay is selected, it will be clipped to maximum delay    */
02182       /*    range                                                                 */
02183       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02184       {
02185         MODIFY_REG(tmpADC_Common->CCR,
02186                    ADC_CCR_DUAL |
02187                    ADC_CCR_DELAY,
02188                    pMultimode->Mode |
02189                    pMultimode->TwoSamplingDelay
02190                   );
02191       }
02192     }
02193     else /* ADC_MODE_INDEPENDENT */
02194     {
02195       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
02196
02197       /* Parameters that can be updated only when ADC is disabled:                */
02198       /*  - Multimode mode selection                                              */
02199       /*  - Multimode delay                                                       */
02200       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02201       {
02202         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
02203       }
02204     }
02205   }
02206   /* If one of the ADC sharing the same common group is enabled, no update    */
02207   /* could be done on neither of the multimode structure parameters.          */
02208   else
02209   {
02210     /* Update ADC state machine to error */
02211     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02212
02213     tmp_hal_status = HAL_ERROR;
02214   }
02215
02216   /* Process unlocked */
02217   __HAL_UNLOCK(hadc);
02218
02219   /* Return function status */
02220   return tmp_hal_status;
02221 }
02222 #endif /* ADC_MULTIMODE_SUPPORT */
02223
02224 /**
02225   * @brief  Enable Injected Queue
02226   * @note   This function resets CFGR register JQDIS bit in order to enable the
02227   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02228   *         are both equal to 0 to ensure that no regular nor injected
02229   *         conversion is ongoing.
02230   * @param hadc ADC handle
02231   * @retval HAL status
02232   */
02233 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
02234 {
02235   HAL_StatusTypeDef tmp_hal_status;
02236   uint32_t tmp_adc_is_conversion_on_going_regular;
02237   uint32_t tmp_adc_is_conversion_on_going_injected;
02238
02239   /* Check the parameters */
02240   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02241
02242   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02243   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02244
02245   /* Parameter can be set only if no conversion is on-going */
02246   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02247       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02248      )
02249   {
02250     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02251
02252     /* Update state, clear previous result related to injected queue overflow */
02253     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02254
02255     tmp_hal_status = HAL_OK;
02256   }
02257   else
02258   {
02259     tmp_hal_status = HAL_ERROR;
02260   }
02261
02262   return tmp_hal_status;
02263 }
02264
02265 /**
02266   * @brief  Disable Injected Queue
02267   * @note   This function sets CFGR register JQDIS bit in order to disable the
02268   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02269   *         are both equal to 0 to ensure that no regular nor injected
02270   *         conversion is ongoing.
02271   * @param hadc ADC handle
02272   * @retval HAL status
02273   */
02274 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
02275 {
02276   HAL_StatusTypeDef tmp_hal_status;
02277   uint32_t tmp_adc_is_conversion_on_going_regular;
02278   uint32_t tmp_adc_is_conversion_on_going_injected;
02279
02280   /* Check the parameters */
02281   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02282
02283   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02284   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02285
02286   /* Parameter can be set only if no conversion is on-going */
02287   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02288       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02289      )
02290   {
02291     LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
02292     tmp_hal_status = HAL_OK;
02293   }
02294   else
02295   {
02296     tmp_hal_status = HAL_ERROR;
02297   }
02298
02299   return tmp_hal_status;
02300 }
02301
02302 /**
02303   * @brief  Disable ADC voltage regulator.
02304   * @note   Disabling voltage regulator allows to save power. This operation can
02305   *         be carried out only when ADC is disabled.
02306   * @note   To enable again the voltage regulator, the user is expected to
02307   *         resort to HAL_ADC_Init() API.
02308   * @param hadc ADC handle
02309   * @retval HAL status
02310   */
02311 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
02312 {
02313   HAL_StatusTypeDef tmp_hal_status;
02314
02315   /* Check the parameters */
02316   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02317
02318   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
02319   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02320   {
02321     LL_ADC_DisableInternalRegulator(hadc->Instance);
02322     tmp_hal_status = HAL_OK;
02323   }
02324   else
02325   {
02326     tmp_hal_status = HAL_ERROR;
02327   }
02328
02329   return tmp_hal_status;
02330 }
02331
02332 /**
02333   * @brief  Enter ADC deep-power-down mode
02334   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
02335   *         in reducing leakage currents. It is particularly interesting before
02336   *         entering stop modes.
02337   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
02338   *         ADC voltage regulator. This means that this API encompasses
02339   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
02340   *         calibration is lost.
02341   * @note   To exit the ADC deep-power-down mode, the user is expected to
02342   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
02343   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
02344   *         saved calibration factor.
02345   * @param hadc ADC handle
02346   * @retval HAL status
02347   */
02348 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
02349 {
02350   HAL_StatusTypeDef tmp_hal_status;
02351
02352   /* Check the parameters */
02353   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02354
02355   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
02356   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02357   {
02358     LL_ADC_EnableDeepPowerDown(hadc->Instance);
02359     tmp_hal_status = HAL_OK;
02360   }
02361   else
02362   {
02363     tmp_hal_status = HAL_ERROR;
02364   }
02365
02366   return tmp_hal_status;
02367 }
02368
02369 /**
02370   * @}
02371   */
02372
02373 /**
02374   * @}
02375   */
02376
02377 #endif /* HAL_ADC_MODULE_ENABLED */
02378 /**
02379   * @}
02380   */
02381
02382 /**
02383   * @}
02384   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_adc_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_adc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_ADC_EX_H
00021 #define STM32G4xx_HAL_ADC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup ADCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  ADC Injected Conversion Oversampling structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00049                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
00050
00051   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00052                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00053 } ADC_InjOversamplingTypeDef;
00054
00055 /**
00056   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
00057   * @note   Parameters of this structure are shared within 2 scopes:
00058   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
00059   *            InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
00060   *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
00061   *            InjectedDiscontinuousConvMode,
00062   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
00063   *            InjecOversamplingMode, InjecOversampling.
00064   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00065   *         ADC state can be either:
00066   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
00067   *            'InjectedSingleDiff')
00068   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
00069   *            without conversion on going on injected group.
00070   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign',
00071   *            'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and
00072   *            injected groups.
00073   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
00074   *            'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
00075   *            on ADC groups regular and injected.
00076   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00077   *         without error reporting (as it can be the expected behavior in case of intended action to update another
00078   *         parameter (which fulfills the ADC state condition) on the fly).
00079   */
00080 typedef struct
00081 {
00082   uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
00083                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00084                                                Note: Depending on devices and ADC instances, some channels may not be
00085                                                      available on device package pins. Refer to device datasheet for
00086                                                      channels availability. */
00087
00088   uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
00089                                                This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
00090                                                Note: to disable a channel or change order of conversion sequencer,
00091                                                      rank containing a previous channel setting can be overwritten by
00092                                                      the new channel setting (or parameter number of conversions
00093                                                      adjusted) */
00094
00095   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00096                                                Unit: ADC clock cycles.
00097                                                Conversion time is the addition of sampling time and processing time
00098                                                (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
00099                                                8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00100                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
00101                                                Caution: This parameter applies to a channel that can be used in a
00102                                                         regular and/or injected group. It overwrites the last setting.
00103                                                Note: In case of usage of internal measurement channels (VrefInt, ...),
00104                                                      sampling time constraints must be respected (sampling time can be
00105                                                      adjusted in function of ADC clock frequency and sampling time
00106                                                      setting). Refer to device datasheet for timings values. */
00107
00108   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00109                                                In differential mode: Differential measurement is between the selected
00110                                                channel 'i' (positive input) and channel 'i+1' (negative input).
00111                                                Only channel 'i' has to be configured, channel 'i+1' is configured
00112                                                automatically.
00113                                                This parameter must be a value of
00114                                                @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
00115                                                Caution: This parameter applies to a channel that can be used in a
00116                                                regular and/or injected group. It overwrites the last setting.
00117                                                Note: Refer to Reference Manual to ensure the selected channel is
00118                                                      available in differential mode.
00119                                                Note: When configuring a channel 'i' in differential mode, the channel
00120                                                      'i+1' is not usable separately.
00121                                                Note: This parameter must be modified when ADC is disabled (before ADC
00122                                                      start conversion or after ADC stop conversion).
00123                                                If ADC is enabled, this parameter setting is bypassed without error
00124                                                reporting (as it can be the expected behavior in case of another
00125                                                parameter update on the fly) */
00126
00127   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
00128                                                This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
00129                                                Caution: Only one offset is allowed per channel. This parameter
00130                                                         overwrites the last setting. */
00131
00132   uint32_t InjectedOffset;                /*!< Defines the offset to be applied on the raw converted data.
00133                                                Offset value must be a positive number.
00134                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
00135                                                parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00136                                                0x3FF, 0xFF or 0x3F respectively.
00137                                                Note: This parameter must be modified when no conversion is on going
00138                                                      on both regular and injected groups (ADC disabled, or ADC enabled
00139                                                      without continuous mode or external trigger that could launch a
00140                                                      conversion). */
00141
00142   uint32_t InjectedOffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added
00143                                                   (positive sign) from or to the raw converted data.
00144                                                   This parameter can be a value of @ref ADCEx_OffsetSign.
00145                                                   Note: This parameter must be modified when no conversion is on going
00146                                                         on both regular and injected groups (ADC disabled, or ADC
00147                                                         enabled without continuous mode or external trigger that could
00148                                                         launch a conversion). */
00149   FunctionalState InjectedOffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
00150                                                This parameter value can be ENABLE or DISABLE.
00151                                                Note: This parameter must be modified when no conversion is on going
00152                                                      on both regular and injected groups (ADC disabled, or ADC enabled
00153                                                      without continuous mode or external trigger that could launch a
00154                                                      conversion). */
00155
00156   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group
00157                                                injected sequencer.
00158                                                To use the injected group sequencer and convert several ranks, parameter
00159                                                'ScanConvMode' must be enabled.
00160                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00161                                                Caution: this setting impacts the entire injected group. Therefore,
00162                                                call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
00163                                                injected group can impact the configuration of other channels previously
00164                                                set. */
00165
00166   FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
00167                                                is performed in Complete-sequence/Discontinuous-sequence
00168                                                (main sequence subdivided in successive parts).
00169                                                Discontinuous mode is used only if sequencer is enabled (parameter
00170                                                'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00171                                                Discontinuous mode can be enabled only if continuous mode is disabled.
00172                                                This parameter can be set to ENABLE or DISABLE.
00173                                                Note: This parameter must be modified when ADC is disabled (before ADC
00174                                                start conversion or after ADC stop conversion).
00175                                                Note: For injected group, discontinuous mode converts the sequence
00176                                                channel by channel (discontinuous length fixed to 1 rank).
00177                                                Caution: this setting impacts the entire injected group. Therefore,
00178                                                         call of HAL_ADCEx_InjectedConfigChannel() to
00179                                                         configure a channel on injected group can impact the
00180                                                         configuration of other channels previously set. */
00181
00182   FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion
00183                                                after regular one
00184                                                This parameter can be set to ENABLE or DISABLE.
00185                                                Note: To use Automatic injected conversion, discontinuous mode must
00186                                                      be disabled ('DiscontinuousConvMode' and
00187                                                      'InjectedDiscontinuousConvMode' set to DISABLE)
00188                                                Note: To use Automatic injected conversion, injected group external
00189                                                      triggers must be disabled ('ExternalTrigInjecConv' set to
00190                                                      ADC_INJECTED_SOFTWARE_START)
00191                                                Note: In case of DMA used with regular group: if DMA configured in
00192                                                      normal mode (single shot) JAUTO will be stopped upon DMA transfer
00193                                                      complete.
00194                                                      To maintain JAUTO always enabled, DMA must be configured in
00195                                                      circular mode.
00196                                                Caution: this setting impacts the entire injected group. Therefore,
00197                                                         call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
00198                                                         on injected group can impact the configuration of other channels
00199                                                         previously set. */
00200
00201   FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
00202                                                This parameter can be set to ENABLE or DISABLE.
00203                                                If context queue is enabled, injected sequencer&channels configurations
00204                                                are queued on up to 2 contexts. If a
00205                                                new injected context is set when queue is full, error is triggered by
00206                                                interruption and through function
00207                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
00208                                                Caution: This feature request that the sequence is fully configured
00209                                                         before injected conversion start.
00210                                                         Therefore, configure channels with as many calls to
00211                                                         HAL_ADCEx_InjectedConfigChannel() as the
00212                                                         'InjectedNbrOfConversion' parameter.
00213                                                Caution: this setting impacts the entire injected group. Therefore,
00214                                                         call of HAL_ADCEx_InjectedConfigChannel() to
00215                                                         configure a channel on injected group can impact the
00216                                                         configuration of other channels previously set.
00217                                                Note: This parameter must be modified when ADC is disabled (before ADC
00218                                                      start conversion or after ADC stop conversion). */
00219
00220   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of
00221                                                injected group.
00222                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
00223                                                and software trigger is used instead.
00224                                                This parameter can be a value of
00225                                                @ref ADC_injected_external_trigger_source.
00226                                                Caution: this setting impacts the entire injected group. Therefore,
00227                                                         call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
00228                                                         on injected group can impact the configuration of other channels
00229                                                         previously set. */
00230
00231   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00232                                                This parameter can be a value of @ref ADC_injected_external_trigger_edge.
00233                                                If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
00234                                                is discarded.
00235                                                Caution: this setting impacts the entire injected group. Therefore,
00236                                                         call of HAL_ADCEx_InjectedConfigChannel() to
00237                                                         configure a channel on injected group can impact the
00238                                                         configuration of other channels previously set. */
00239
00240   FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
00241                                                       This parameter can be set to ENABLE or DISABLE.
00242                                                       Note: This parameter can be modified only if there is no
00243                                                       conversion is ongoing (both ADSTART and JADSTART cleared). */
00244
00245   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
00246                                                       Caution: this setting overwrites the previous oversampling
00247                                                                configuration if oversampling already enabled.
00248                                                       Note: This parameter can be modified only if there is no
00249                                                             conversion is ongoing (both ADSTART and JADSTART cleared).*/
00250 } ADC_InjectionConfTypeDef;
00251
00252 #if defined(ADC_MULTIMODE_SUPPORT)
00253 /**
00254   * @brief  Structure definition of ADC multimode
00255   * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
00256   *         (both Master and Slave ADCs).
00257   *         Both Master and Slave ADCs must be disabled.
00258   */
00259 typedef struct
00260 {
00261   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
00262                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
00263
00264   uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
00265                                    selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
00266                                    (one DMA channel for both ADC, DMA of ADC master).
00267                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
00268
00269   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00270                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
00271                                    Delay range depends on selected resolution:
00272                                     from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
00273                                     from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
00274 } ADC_MultiModeTypeDef;
00275 #endif /* ADC_MULTIMODE_SUPPORT */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /* Exported constants --------------------------------------------------------*/
00282
00283 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00284   * @{
00285   */
00286
00287 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
00288   * @{
00289   */
00290 /* ADC group regular trigger sources for all ADC instances */
00291 #define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< ADC group injected conversion
00292                                            trigger software start */
00293 #define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion
00294                                            trigger from external peripheral: TIM1 TRGO. */
00295 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion
00296                                            trigger from external peripheral: TIM1 TRGO2. */
00297 #define ADC_EXTERNALTRIGINJEC_T1_CC3       (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)        /*!< ADC group injected conversion
00298                                            trigger from external peripheral: TIM1 channel 3 event (capture compare). */
00299 #define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion
00300                                            trigger from external peripheral: TIM1 channel 4 event (capture compare). */
00301 #define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion
00302                                            trigger from external peripheral: TIM2 TRGO. */
00303 #define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion
00304                                            trigger from external peripheral: TIM2 channel 1 event (capture compare). */
00305 #define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion
00306                                            trigger from external peripheral: TIM3 TRGO. */
00307 #define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion
00308                                            trigger from external peripheral: TIM3 channel 1 event (capture compare). */
00309 #define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion
00310                                            trigger from external peripheral: TIM3 channel 3 event (capture compare). */
00311 #define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion
00312                                            trigger from external peripheral: TIM3 channel 4 event (capture compare). */
00313 #define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion
00314                                            trigger from external peripheral: TIM4 TRGO. */
00315 #define ADC_EXTERNALTRIGINJEC_T4_CC3       (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)        /*!< ADC group injected conversion
00316                                            trigger from external peripheral: TIM4 channel 3 event (capture compare). */
00317 #define ADC_EXTERNALTRIGINJEC_T4_CC4       (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)        /*!< ADC group injected conversion
00318                                            trigger from external peripheral: TIM4 channel 4 event (capture compare). */
00319 #define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion
00320                                            trigger from external peripheral: TIM6 TRGO. */
00321 #define ADC_EXTERNALTRIGINJEC_T7_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)       /*!< ADC group injected conversion
00322                                            trigger from external peripheral: TIM7 TRGO. */
00323 #define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)       /*!< ADC group injected conversion
00324                                            trigger from external peripheral: TIM8 TRGO. */
00325 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)      /*!< ADC group injected conversion
00326                                            trigger from external peripheral: TIM8 TRGO2. */
00327 #define ADC_EXTERNALTRIGINJEC_T8_CC2       (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)        /*!< ADC group injected conversion
00328                                            trigger from external peripheral: TIM8 channel 2 event (capture compare). */
00329 #define ADC_EXTERNALTRIGINJEC_T8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)        /*!< ADC group injected conversion
00330                                            trigger from external peripheral: TIM8 channel 4 event (capture compare). */
00331 #define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion
00332                                            trigger from external peripheral: TIM15 TRGO. */
00333 #define ADC_EXTERNALTRIGINJEC_T16_CC1      (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)       /*!< ADC group injected conversion
00334                                            trigger from external peripheral: TIM8 channel 4 event (capture compare). */
00335 #define ADC_EXTERNALTRIGINJEC_T20_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)      /*!< ADC group injected conversion
00336                                            trigger from external peripheral: TIM20 TRGO. */
00337 #define ADC_EXTERNALTRIGINJEC_T20_TRGO2    (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)     /*!< ADC group injected conversion
00338                                            trigger from external peripheral: TIM20 TRGO2. */
00339 #define ADC_EXTERNALTRIGINJEC_T20_CC2      (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)       /*!< ADC group injected conversion
00340                                            trigger from external peripheral: TIM20 channel 2 event (capture compare). */
00341 #define ADC_EXTERNALTRIGINJEC_T20_CC4      (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)       /*!< ADC group injected conversion
00342                                            trigger from external peripheral: TIM20 channel 4 event (capture compare). */
00343 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)      /*!< ADC group injected conversion
00344                                            trigger from external peripheral: HRTIMER ADC trigger 1 event. */
00345 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion
00346                                            trigger from external peripheral: HRTIMER ADC trigger 2 event. */
00347 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)      /*!< ADC group injected conversion
00348                                            trigger from external peripheral: HRTIMER ADC trigger 3 event. */
00349 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion
00350                                            trigger from external peripheral: HRTIMER ADC trigger 4 event. */
00351 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)      /*!< ADC group injected conversion
00352                                            trigger from external peripheral: HRTIMER ADC trigger 5 event. */
00353 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)      /*!< ADC group injected conversion
00354                                            trigger from external peripheral: HRTIMER ADC trigger 6 event. */
00355 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)      /*!< ADC group injected conversion
00356                                            trigger from external peripheral: HRTIMER ADC trigger 7 event. */
00357 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)      /*!< ADC group injected conversion
00358                                            trigger from external peripheral: HRTIMER ADC trigger 8 event. */
00359 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)      /*!< ADC group injected conversion
00360                                            trigger from external peripheral: HRTIMER ADC trigger 9 event. */
00361 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)     /*!< ADC group injected conversion
00362                                            trigger from external peripheral: HRTIMER ADC trigger 10 event. */
00363 #define ADC_EXTERNALTRIGINJEC_EXT_IT3      (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)      /*!< ADC group injected conversion
00364                                            trigger from external peripheral: external interrupt line 3. */
00365 #define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion
00366                                            trigger from external peripheral: external interrupt line 15. */
00367 #define ADC_EXTERNALTRIGINJEC_LPTIM_OUT    (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)       /*!< ADC group injected conversion
00368                                            trigger from external peripheral: LPTIMER OUT event. */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
00374   * @{
00375   */
00376 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions trigger
00377                                                       disabled (SW start)*/
00378 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions trigger
00379                                                       polarity set to rising edge */
00380 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions trigger
00381                                                       polarity set to falling edge */
00382 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions trigger
00383                                                       polarity set to both rising and falling edges */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
00389   * @{
00390   */
00391 #define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended */
00392 #define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
00398   * @{
00399   */
00400 #define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
00401                                      ADC channel */
00402 #define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
00403                                      the offset programmed will be applied (independently of channel mapped
00404                                      on ADC group regular or group injected) */
00405 #define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
00406                                      the offset programmed will be applied (independently of channel mapped
00407                                      on ADC group regular or group injected) */
00408 #define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
00409                                      the offset programmed will be applied (independently of channel mapped
00410                                      on ADC group regular or group injected) */
00411 #define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
00412                                      the offset programmed will be applied (independently of channel mapped
00413                                      on ADC group regular or group injected) */
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
00419   * @{
00420   */
00421 #define ADC_OFFSET_SIGN_NEGATIVE      (0x00000000UL)         /*!< Offset sign negative, offset is subtracted */
00422 #define ADC_OFFSET_SIGN_POSITIVE      (ADC_OFR1_OFFSETPOS)   /*!< Offset sign positive, offset is added  */
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
00428   * @{
00429   */
00430 #define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
00431 #define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
00432 #define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
00433 #define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
00434 /**
00435   * @}
00436   */
00437
00438 #if defined(ADC_MULTIMODE_SUPPORT)
00439 /** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
00440   * @{
00441   */
00442 #define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)          /*!< ADC dual mode disabled
00443                                            (ADC independent mode) */
00444 #define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT)      /*!< ADC dual mode enabled: group regular
00445                                            simultaneous */
00446 #define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL)      /*!< ADC dual mode enabled: Combined
00447                                            group regular interleaved */
00448 #define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT)      /*!< ADC dual mode enabled: group
00449                                            injected simultaneous */
00450 #define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN)      /*!< ADC dual mode enabled: group
00451                                            injected alternate trigger. Works only with external triggers (not internal
00452                                            SW start) */
00453 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
00454                                            group regular simultaneous + group injected simultaneous */
00455 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
00456                                            group regular simultaneous + group injected alternate trigger */
00457 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
00458                                            group regular interleaved + group injected simultaneous */
00459
00460 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION  Multimode - DMA transfer mode depending on ADC resolution
00461   * @{
00462   */
00463 #define ADC_DMAACCESSMODE_DISABLED         (0x00000000UL)     /*!< DMA multimode disabled: each ADC uses its own
00464                                            DMA channel */
00465 #define ADC_DMAACCESSMODE_12_10_BITS       (ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC,
00466                                            DMA of ADC master) for 12 and 10 bits resolution */
00467 #define ADC_DMAACCESSMODE_8_6_BITS         (ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC,
00468                                            DMA of ADC master) for 8 and 6 bits resolution */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
00474   * @{
00475   */
00476 #define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)    /*!< ADC multimode delay between two
00477                                            sampling phases: 1 ADC clock cycle */
00478 #define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)   /*!< ADC multimode delay between two
00479                                            sampling phases: 2 ADC clock cycles */
00480 #define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)   /*!< ADC multimode delay between two
00481                                            sampling phases: 3 ADC clock cycles */
00482 #define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)   /*!< ADC multimode delay between two
00483                                            sampling phases: 4 ADC clock cycles */
00484 #define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)   /*!< ADC multimode delay between two
00485                                            sampling phases: 5 ADC clock cycles */
00486 #define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)   /*!< ADC multimode delay between two
00487                                            sampling phases: 6 ADC clock cycles */
00488 #define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)   /*!< ADC multimode delay between two
00489                                            sampling phases: 7 ADC clock cycles */
00490 #define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two
00491                                            sampling phases: 8 ADC clock cycles */
00492 #define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two
00493                                            sampling phases: 9 ADC clock cycles */
00494 #define ADC_TWOSAMPLINGDELAY_10CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)  /*!< ADC multimode delay between two
00495                                            sampling phases: 10 ADC clock cycles */
00496 #define ADC_TWOSAMPLINGDELAY_11CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)  /*!< ADC multimode delay between two
00497                                            sampling phases: 11 ADC clock cycles */
00498 #define ADC_TWOSAMPLINGDELAY_12CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)  /*!< ADC multimode delay between two
00499                                            sampling phases: 12 ADC clock cycles */
00500 /**
00501   * @}
00502   */
00503
00504 /**
00505   * @}
00506   */
00507 #endif /* ADC_MULTIMODE_SUPPORT */
00508
00509 /** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
00510   * @{
00511   */
00512 #define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)          /*!< ADC group regular (available on
00513                                                                                 all STM32 devices) */
00514 #define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)         /*!< ADC group injected (not available on
00515                                                                                 all STM32 devices) */
00516 #define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
00522   * @{
00523   */
00524 #define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
00525                             ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
00526                             ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
00527                             ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
00528                             ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
00529                             ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
00535   * @{
00536   */
00537 #if defined(ADC_SMPR1_SMPPLUS)
00538 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
00539                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
00540                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
00541                              ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
00542 #else
00543 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
00544                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
00545                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
00546                              ADC_SMPR1_SMP0)
00547 #endif /* ADC_SMPR1_SMPPLUS */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
00553   * @{
00554   */
00555 /* ADC_CFGR fields of parameters that can be updated when no conversion
00556    (neither regular nor injected) is on-going  */
00557 #define ADC_CFGR_FIELDS_2  ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
00558 /**
00559   * @}
00560   */
00561
00562 /**
00563   * @}
00564   */
00565
00566 /* Exported macros -----------------------------------------------------------*/
00567
00568 #if defined(ADC_MULTIMODE_SUPPORT)
00569 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
00570   * @{
00571   */
00572
00573 /** @brief  Force ADC instance in multimode mode independent (multimode disable).
00574   * @note   This macro must be used only in case of transition from multimode
00575   *         to mode independent and in case of unknown previous state,
00576   *         to ensure ADC configuration is in mode independent.
00577   * @note   Standard way of multimode configuration change is done from
00578   *         HAL ADC handle of ADC master using function
00579   *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
00580   *         Usage of this macro is not the Standard way of multimode
00581   *         configuration and can lead to have HAL ADC handles status
00582   *         misaligned. Usage of this macro must be limited to cases
00583   *         mentioned above.
00584   * @param __HANDLE__ ADC handle.
00585   * @retval None
00586   */
00587 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
00588   LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
00589
00590 /**
00591   * @}
00592   */
00593 #endif /* ADC_MULTIMODE_SUPPORT */
00594
00595 /* Private macros ------------------------------------------------------------*/
00596
00597 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00598   * @{
00599   */
00600 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00601 /* code of final user.                                                        */
00602
00603 /**
00604   * @brief Test if conversion trigger of injected group is software start
00605   *        or external trigger.
00606   * @param __HANDLE__ ADC handle.
00607   * @retval SET (software start) or RESET (external trigger).
00608   */
00609 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00610   (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
00611
00612 /**
00613   * @brief Check whether or not ADC is independent.
00614   * @param __HANDLE__ ADC handle.
00615   * @note  When multimode feature is not available, the macro always returns SET.
00616   * @retval SET (ADC is independent) or RESET (ADC is not).
00617   */
00618 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00619 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
00620   ( ( ( ((__HANDLE__)->Instance) == ADC5) \
00621     )?                                    \
00622     SET                                   \
00623     :                                     \
00624     RESET                                 \
00625   )
00626 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00627 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
00628   ( ( ( ((__HANDLE__)->Instance) == ADC3) \
00629     )?                                    \
00630     SET                                   \
00631     :                                     \
00632     RESET                                 \
00633   )
00634 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
00635 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
00636 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
00637
00638 /**
00639   * @brief Set the selected injected Channel rank.
00640   * @param __CHANNELNB__ Channel number.
00641   * @param __RANKNB__ Rank number.
00642   * @retval None
00643   */
00644 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
00645   ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
00646    << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
00647
00648 /**
00649   * @brief Configure ADC injected context queue
00650   * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
00651   * @retval None
00652   */
00653 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
00654   ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
00655
00656 /**
00657   * @brief Configure ADC discontinuous conversion mode for injected group
00658   * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
00659   * @retval None
00660   */
00661 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
00662   ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
00663
00664 /**
00665   * @brief Configure ADC discontinuous conversion mode for regular group
00666   * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
00667   * @retval None
00668   */
00669 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
00670   ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
00671
00672 /**
00673   * @brief Configure the number of discontinuous conversions for regular group.
00674   * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
00675   * @retval None
00676   */
00677 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
00678   (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
00679
00680 /**
00681   * @brief Configure the ADC auto delay mode.
00682   * @param __AUTOWAIT__ Auto delay bit enable or disable.
00683   * @retval None
00684   */
00685 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
00686
00687 /**
00688   * @brief Configure ADC continuous conversion mode.
00689   * @param __CONTINUOUS_MODE__ Continuous mode.
00690   * @retval None
00691   */
00692 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
00693
00694 /**
00695   * @brief Configure the ADC DMA continuous request.
00696   * @param __DMACONTREQ_MODE__ DMA continuous request mode.
00697   * @retval None
00698   */
00699 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  ADC_CFGR_DMACFG_Pos)
00700
00701 #if defined(ADC_MULTIMODE_SUPPORT)
00702 /**
00703   * @brief Configure the ADC DMA continuous request for ADC multimode.
00704   * @param __DMACONTREQ_MODE__ DMA continuous request mode.
00705   * @retval None
00706   */
00707 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
00708 #endif /* ADC_MULTIMODE_SUPPORT */
00709
00710 /**
00711   * @brief Shift the offset with respect to the selected ADC resolution.
00712   * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
00713   *         If resolution 12 bits, no shift.
00714   *         If resolution 10 bits, shift of 2 ranks on the left.
00715   *         If resolution 8 bits, shift of 4 ranks on the left.
00716   *         If resolution 6 bits, shift of 6 ranks on the left.
00717   *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
00718   * @param __HANDLE__ ADC handle
00719   * @param __OFFSET__ Value to be shifted
00720   * @retval None
00721   */
00722 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
00723   ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
00724
00725 /**
00726   * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
00727   * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
00728   *        If resolution 12 bits, no shift.
00729   *        If resolution 10 bits, shift of 2 ranks on the left.
00730   *        If resolution 8 bits, shift of 4 ranks on the left.
00731   *        If resolution 6 bits, shift of 6 ranks on the left.
00732   *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
00733   * @param __HANDLE__ ADC handle
00734   * @param __THRESHOLD__ Value to be shifted
00735   * @retval None
00736   */
00737 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
00738   ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
00739
00740 /**
00741   * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
00742   * @note  Thresholds have to be left-aligned on bit 7.
00743   *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
00744   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
00745   *        If resolution 8 bits, no shift.
00746   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
00747   * @param __HANDLE__ ADC handle
00748   * @param __THRESHOLD__ Value to be shifted
00749   * @retval None
00750   */
00751 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                       \
00752   ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
00753    ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
00754    ((__THRESHOLD__) << 2UL)                                                                                 \
00755   )
00756
00757 /**
00758   * @brief Clear Common Control Register.
00759   * @param __HANDLE__ ADC handle.
00760   * @retval None
00761   */
00762 #if defined(ADC_MULTIMODE_SUPPORT)
00763 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
00764                                                                 ADC_CCR_CKMODE    | \
00765                                                                 ADC_CCR_PRESC     | \
00766                                                                 ADC_CCR_VBATSEL   | \
00767                                                                 ADC_CCR_VSENSESEL | \
00768                                                                 ADC_CCR_VREFEN    | \
00769                                                                 ADC_CCR_MDMA      | \
00770                                                                 ADC_CCR_DMACFG    | \
00771                                                                 ADC_CCR_DELAY     | \
00772                                                                 ADC_CCR_DUAL)
00773 #endif /* ADC_MULTIMODE_SUPPORT */
00774
00775 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00776 /**
00777   * @brief Set handle instance of the ADC slave associated to the ADC master.
00778   * @param __HANDLE_MASTER__ ADC master handle.
00779   * @param __HANDLE_SLAVE__ ADC slave handle.
00780   * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is
00781   *       set to NULL.
00782   * @retval None
00783   */
00784 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
00785   ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
00786     ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
00787     :                                                                    \
00788     ((__HANDLE_MASTER__)->Instance == ADC3) ?                            \
00789     ((__HANDLE_SLAVE__)->Instance = ADC4)                                \
00790     :                                                                    \
00791     ((__HANDLE_SLAVE__)->Instance = NULL)                                \
00792   )
00793 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
00794 /**
00795   * @brief Set handle instance of the ADC slave associated to the ADC master.
00796   * @param __HANDLE_MASTER__ ADC master handle.
00797   * @param __HANDLE_SLAVE__ ADC slave handle.
00798   * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set
00799   *       to NULL.
00800   * @retval None
00801   */
00802 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
00803   ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
00804     ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
00805     :                                                                    \
00806     ((__HANDLE_SLAVE__)->Instance = NULL)                                \
00807   )
00808 #endif /* STM32G4xx */
00809
00810
00811 /**
00812   * @brief Verify the ADC instance connected to the temperature sensor.
00813   * @param __HANDLE__ ADC handle.
00814   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00815   */
00816 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00817 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
00818   ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
00819 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
00820 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
00821 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
00822
00823 /**
00824   * @brief Verify the ADC instance connected to the battery voltage VBAT.
00825   * @param __HANDLE__ ADC handle.
00826   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00827   */
00828 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00829 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
00830   ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
00831 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
00832 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
00833 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00834 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
00835 #endif /* STM32G4xx */
00836
00837 /**
00838   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
00839   * @param __HANDLE__ ADC handle.
00840   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00841   */
00842 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
00843
00844 /**
00845   * @brief Verify the length of scheduled injected conversions group.
00846   * @param __LENGTH__ number of programmed conversions.
00847   * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
00848   *         or RESET (__LENGTH__ is null or too large)
00849   */
00850 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
00851
00852 /**
00853   * @brief Calibration factor size verification (7 bits maximum).
00854   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00855   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
00856   */
00857 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
00858
00859
00860 /**
00861   * @brief Verify the ADC channel setting.
00862   * @param __HANDLE__ ADC handle.
00863   * @param __CHANNEL__ programmed ADC channel.
00864   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00865   */
00866 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00867 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
00868                                                           ((__CHANNEL__) == ADC_CHANNEL_1)                || \
00869                                                           ((__CHANNEL__) == ADC_CHANNEL_2)                || \
00870                                                           ((__CHANNEL__) == ADC_CHANNEL_6)                || \
00871                                                           ((__CHANNEL__) == ADC_CHANNEL_7)                || \
00872                                                           ((__CHANNEL__) == ADC_CHANNEL_8)                || \
00873                                                           ((__CHANNEL__) == ADC_CHANNEL_9)                || \
00874                                                           ((__CHANNEL__) == ADC_CHANNEL_10)               || \
00875                                                           ((__CHANNEL__) == ADC_CHANNEL_11)               || \
00876                                                           ((__CHANNEL__) == ADC_CHANNEL_12)               || \
00877                                                           ((__CHANNEL__) == ADC_CHANNEL_14)               || \
00878                                                           ((__CHANNEL__) == ADC_CHANNEL_15))              || \
00879                                                         ((((__HANDLE__)->Instance) == ADC1)  && \
00880                                                          (((__CHANNEL__) == ADC_CHANNEL_3)                || \
00881                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00882                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00883                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
00884                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
00885                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00886                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00887                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
00888                                                          (((__CHANNEL__) == ADC_CHANNEL_3)                || \
00889                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00890                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00891                                                           ((__CHANNEL__) == ADC_CHANNEL_13)               || \
00892                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
00893                                                           ((__CHANNEL__) == ADC_CHANNEL_17)               || \
00894                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
00895                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
00896                                                          (((__CHANNEL__) == ADC_CHANNEL_3)                || \
00897                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00898                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00899                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
00900                                                           ((__CHANNEL__) == ADC_CHANNEL_16)               || \
00901                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00902                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00903                                                         ((((__HANDLE__)->Instance) == ADC4)  && \
00904                                                          (((__CHANNEL__) == ADC_CHANNEL_3)                || \
00905                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00906                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00907                                                           ((__CHANNEL__) == ADC_CHANNEL_13)               || \
00908                                                           ((__CHANNEL__) == ADC_CHANNEL_16)               || \
00909                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
00910                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00911                                                         ((((__HANDLE__)->Instance) == ADC5)  && \
00912                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5)          || \
00913                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5)  || \
00914                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4)          || \
00915                                                           ((__CHANNEL__) == ADC_CHANNEL_13)               || \
00916                                                           ((__CHANNEL__) == ADC_CHANNEL_16)               || \
00917                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00918                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
00919 #elif defined(STM32G471xx)
00920 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
00921                                                           ((__CHANNEL__) == ADC_CHANNEL_1)                || \
00922                                                           ((__CHANNEL__) == ADC_CHANNEL_2)                || \
00923                                                           ((__CHANNEL__) == ADC_CHANNEL_3)                || \
00924                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00925                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00926                                                           ((__CHANNEL__) == ADC_CHANNEL_6)                || \
00927                                                           ((__CHANNEL__) == ADC_CHANNEL_7)                || \
00928                                                           ((__CHANNEL__) == ADC_CHANNEL_8)                || \
00929                                                           ((__CHANNEL__) == ADC_CHANNEL_9)                || \
00930                                                           ((__CHANNEL__) == ADC_CHANNEL_10)               || \
00931                                                           ((__CHANNEL__) == ADC_CHANNEL_11)               || \
00932                                                           ((__CHANNEL__) == ADC_CHANNEL_12)               || \
00933                                                           ((__CHANNEL__) == ADC_CHANNEL_14)               || \
00934                                                           ((__CHANNEL__) == ADC_CHANNEL_15))              || \
00935                                                         ((((__HANDLE__)->Instance) == ADC1)  && \
00936                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
00937                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
00938                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00939                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00940                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
00941                                                          (((__CHANNEL__) == ADC_CHANNEL_13)               || \
00942                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
00943                                                           ((__CHANNEL__) == ADC_CHANNEL_17)               || \
00944                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
00945                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
00946                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
00947                                                           ((__CHANNEL__) == ADC_CHANNEL_16)               || \
00948                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00949                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
00950 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
00951 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
00952                                                           ((__CHANNEL__) == ADC_CHANNEL_1)                || \
00953                                                           ((__CHANNEL__) == ADC_CHANNEL_2)                || \
00954                                                           ((__CHANNEL__) == ADC_CHANNEL_3)                || \
00955                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00956                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00957                                                           ((__CHANNEL__) == ADC_CHANNEL_6)                || \
00958                                                           ((__CHANNEL__) == ADC_CHANNEL_7)                || \
00959                                                           ((__CHANNEL__) == ADC_CHANNEL_8)                || \
00960                                                           ((__CHANNEL__) == ADC_CHANNEL_9)                || \
00961                                                           ((__CHANNEL__) == ADC_CHANNEL_10)               || \
00962                                                           ((__CHANNEL__) == ADC_CHANNEL_11)               || \
00963                                                           ((__CHANNEL__) == ADC_CHANNEL_12)               || \
00964                                                           ((__CHANNEL__) == ADC_CHANNEL_14)               || \
00965                                                           ((__CHANNEL__) == ADC_CHANNEL_15))              || \
00966                                                         ((((__HANDLE__)->Instance) == ADC1)  && \
00967                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
00968                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
00969                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00970                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00971                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
00972                                                          (((__CHANNEL__) == ADC_CHANNEL_13)               || \
00973                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
00974                                                           ((__CHANNEL__) == ADC_CHANNEL_17)               || \
00975                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
00976 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00977 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
00978                                                           ((__CHANNEL__) == ADC_CHANNEL_1)                || \
00979                                                           ((__CHANNEL__) == ADC_CHANNEL_2)                || \
00980                                                           ((__CHANNEL__) == ADC_CHANNEL_3)                || \
00981                                                           ((__CHANNEL__) == ADC_CHANNEL_4)                || \
00982                                                           ((__CHANNEL__) == ADC_CHANNEL_5)                || \
00983                                                           ((__CHANNEL__) == ADC_CHANNEL_6)                || \
00984                                                           ((__CHANNEL__) == ADC_CHANNEL_7)                || \
00985                                                           ((__CHANNEL__) == ADC_CHANNEL_8)                || \
00986                                                           ((__CHANNEL__) == ADC_CHANNEL_9)                || \
00987                                                           ((__CHANNEL__) == ADC_CHANNEL_10)               || \
00988                                                           ((__CHANNEL__) == ADC_CHANNEL_11)               || \
00989                                                           ((__CHANNEL__) == ADC_CHANNEL_12)               || \
00990                                                           ((__CHANNEL__) == ADC_CHANNEL_14)               || \
00991                                                           ((__CHANNEL__) == ADC_CHANNEL_15))              || \
00992                                                         ((((__HANDLE__)->Instance) == ADC1)  && \
00993                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
00994                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
00995                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
00996                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
00997                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
00998                                                          (((__CHANNEL__) == ADC_CHANNEL_13)               || \
00999                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
01000                                                           ((__CHANNEL__) == ADC_CHANNEL_17)               || \
01001                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
01002                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
01003                                                          (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
01004                                                           ((__CHANNEL__) == ADC_CHANNEL_16)               || \
01005                                                           ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
01006                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
01007 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
01008
01009 /**
01010   * @brief Verify the ADC channel setting in differential mode.
01011   * @param __HANDLE__ ADC handle.
01012   * @param __CHANNEL__ programmed ADC channel.
01013   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01014   */
01015 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
01016 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
01017                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01018                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01019                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01020                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01021                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01022                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01023                                                           ((__CHANNEL__) == ADC_CHANNEL_14))         || \
01024                                                         ((((__HANDLE__)->Instance) == ADC1)  && \
01025                                                          (((__CHANNEL__) == ADC_CHANNEL_2)           || \
01026                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01027                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01028                                                           ((__CHANNEL__) == ADC_CHANNEL_5)))         || \
01029                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
01030                                                          (((__CHANNEL__) == ADC_CHANNEL_2)           || \
01031                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01032                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01033                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01034                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01035                                                           ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
01036                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
01037                                                          (((__CHANNEL__) == ADC_CHANNEL_2)           || \
01038                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01039                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01040                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01041                                                           ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
01042                                                         ((((__HANDLE__)->Instance) == ADC4)  && \
01043                                                          (((__CHANNEL__) == ADC_CHANNEL_2)           || \
01044                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01045                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01046                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01047                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01048                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01049                                                           ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
01050                                                         ((((__HANDLE__)->Instance) == ADC5)  && \
01051                                                          (((__CHANNEL__) == ADC_CHANNEL_12)          || \
01052                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01053                                                           ((__CHANNEL__) == ADC_CHANNEL_15))) )
01054 #elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
01055 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
01056                                                          (((__CHANNEL__) == ADC_CHANNEL_2)           || \
01057                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01058                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01059                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01060                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01061                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01062                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01063                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01064                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01065                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01066                                                           ((__CHANNEL__) == ADC_CHANNEL_14))         || \
01067                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
01068                                                          (((__CHANNEL__) == ADC_CHANNEL_12)          || \
01069                                                           ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
01070                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
01071                                                           ((__CHANNEL__) == ADC_CHANNEL_15))) )
01072 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
01073 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
01074                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
01075                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01076                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01077                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01078                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01079                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01080                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01081                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01082                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01083                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01084                                                           ((__CHANNEL__) == ADC_CHANNEL_14))         || \
01085                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
01086                                                          (((__CHANNEL__) == ADC_CHANNEL_12)          || \
01087                                                           ((__CHANNEL__) == ADC_CHANNEL_13))) )
01088 #endif /* STM32G4xx */
01089
01090 /**
01091   * @brief Verify the ADC single-ended input or differential mode setting.
01092   * @param __SING_DIFF__ programmed channel setting.
01093   * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
01094   */
01095 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
01096                                                    ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
01097
01098 /**
01099   * @brief Verify the ADC offset management setting.
01100   * @param __OFFSET_NUMBER__ ADC offset management.
01101   * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
01102   */
01103 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
01104                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
01105                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
01106                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
01107                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
01108
01109 /**
01110   * @brief Verify the ADC offset sign setting.
01111   * @param __OFFSET_SIGN__ ADC offset sign.
01112   * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
01113   */
01114 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)     (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
01115                                                  ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )
01116
01117 /**
01118   * @brief Verify the ADC injected channel setting.
01119   * @param __CHANNEL__ programmed ADC injected channel.
01120   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01121   */
01122 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
01123                                            ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
01124                                            ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
01125                                            ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
01126
01127 /**
01128   * @brief Verify the ADC injected conversions external trigger.
01129   * @param __HANDLE__ ADC handle.
01130   * @param __INJTRIG__ programmed ADC injected conversions external trigger.
01131   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
01132   */
01133 #if defined(STM32G474xx) || defined(STM32G484xx)
01134 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
01135                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
01136                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
01137                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
01138                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
01139                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
01140                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
01141                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
01142                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
01143                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
01144                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
01145                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
01146                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
01147                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
01148                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2)     || \
01149                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4)     || \
01150                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5)     || \
01151                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6)     || \
01152                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7)     || \
01153                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8)     || \
01154                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9)     || \
01155                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10)    || \
01156                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
01157                                                        ((((__HANDLE__)->Instance == ADC1) || \
01158                                                          ((__HANDLE__)->Instance == ADC2)) && \
01159                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
01160                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
01161                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
01162                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
01163                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
01164                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
01165                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
01166                                                        ((((__HANDLE__)->Instance == ADC3) || \
01167                                                          ((__HANDLE__)->Instance == ADC4) || \
01168                                                          ((__HANDLE__)->Instance == ADC5)) && \
01169                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
01170                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
01171                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
01172                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
01173                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
01174                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1)   || \
01175                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3)   || \
01176                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
01177                                                        ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
01178 #elif defined(STM32G473xx) || defined(STM32G483xx)
01179 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
01180                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
01181                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
01182                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
01183                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
01184                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
01185                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
01186                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
01187                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
01188                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
01189                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
01190                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
01191                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
01192                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
01193                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
01194                                                        ((((__HANDLE__)->Instance == ADC1) || \
01195                                                          ((__HANDLE__)->Instance == ADC2)) && \
01196                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
01197                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
01198                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
01199                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
01200                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
01201                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
01202                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
01203                                                        ((((__HANDLE__)->Instance == ADC3) || \
01204                                                          ((__HANDLE__)->Instance == ADC4) || \
01205                                                          ((__HANDLE__)->Instance == ADC5)) && \
01206                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
01207                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
01208                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
01209                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
01210                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
01211                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
01212                                                        ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
01213 #elif defined(STM32G471xx)
01214 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
01215                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
01216                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
01217                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
01218                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
01219                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
01220                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
01221                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
01222                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
01223                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
01224                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
01225                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
01226                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
01227                                                        ((((__HANDLE__)->Instance == ADC1) || \
01228                                                          ((__HANDLE__)->Instance == ADC2)) && \
01229                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
01230                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
01231                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
01232                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
01233                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
01234                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
01235                                                        ((((__HANDLE__)->Instance == ADC3)) && \
01236                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
01237                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
01238                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
01239                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
01240                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
01241                                                        ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
01242 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
01243 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
01244                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
01245                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
01246                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
01247                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)         || \
01248                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
01249                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)         || \
01250                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)         || \
01251                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)         || \
01252                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
01253                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
01254                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
01255                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
01256                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
01257                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
01258                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
01259                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)        || \
01260                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)       || \
01261                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
01262                                                        ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
01263 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
01264 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
01265                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
01266                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
01267                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
01268                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
01269                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
01270                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
01271                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
01272                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
01273                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
01274                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
01275                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
01276                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
01277                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
01278                                                        ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
01279                                                        ((((__HANDLE__)->Instance == ADC1) || \
01280                                                          ((__HANDLE__)->Instance == ADC2)) && \
01281                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
01282                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
01283                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
01284                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
01285                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
01286                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
01287                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
01288                                                        (((__HANDLE__)->Instance == ADC3) && \
01289                                                         (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
01290                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
01291                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
01292                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
01293                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
01294                                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
01295                                                        ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
01296 #endif /* STM32G4xx */
01297
01298 /**
01299   * @brief Verify the ADC edge trigger setting for injected group.
01300   * @param __EDGE__ programmed ADC edge trigger setting.
01301   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
01302   */
01303 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
01304                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
01305                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
01306                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
01307
01308 #if defined(ADC_MULTIMODE_SUPPORT)
01309 /**
01310   * @brief Verify the ADC multimode setting.
01311   * @param __MODE__ programmed ADC multimode setting.
01312   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01313   */
01314 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
01315                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
01316                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
01317                                     ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
01318                                     ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
01319                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
01320                                     ((__MODE__) == ADC_DUALMODE_INTERL)                || \
01321                                     ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
01322
01323 /**
01324   * @brief Verify the ADC multimode DMA access setting.
01325   * @param __MODE__ programmed ADC multimode DMA access setting.
01326   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01327   */
01328 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
01329                                                ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
01330                                                ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )
01331
01332 /**
01333   * @brief Verify the ADC multimode delay setting.
01334   * @param __DELAY__ programmed ADC multimode delay setting.
01335   * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
01336   */
01337 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
01338                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
01339                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
01340                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
01341                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
01342                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
01343                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
01344                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
01345                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
01346                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
01347                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
01348                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
01349 #endif /* ADC_MULTIMODE_SUPPORT */
01350
01351 /**
01352   * @brief Verify the ADC analog watchdog setting.
01353   * @param __WATCHDOG__ programmed ADC analog watchdog setting.
01354   * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
01355   */
01356 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
01357                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
01358                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
01359
01360 /**
01361   * @brief Verify the ADC analog watchdog mode setting.
01362   * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
01363   * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
01364   */
01365 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)            || \
01366                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)      || \
01367                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)    || \
01368                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
01369                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)         || \
01370                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)       || \
01371                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      )
01372
01373 /**
01374   * @brief Verify the ADC analog watchdog filtering setting.
01375   * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
01376   * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
01377   */
01378 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
01379   (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)            || \
01380    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)        || \
01381    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)        || \
01382    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)        || \
01383    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)        || \
01384    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)        || \
01385    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)        || \
01386    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)           )
01387
01388
01389 /**
01390   * @brief Verify the ADC conversion (regular or injected or both).
01391   * @param __CONVERSION__ ADC conversion group.
01392   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
01393   */
01394 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
01395                                                  ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
01396                                                  ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
01397
01398 /**
01399   * @brief Verify the ADC event type.
01400   * @param __EVENT__ ADC event.
01401   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
01402   */
01403 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
01404                                       ((__EVENT__) == ADC_AWD_EVENT)    || \
01405                                       ((__EVENT__) == ADC_AWD2_EVENT)   || \
01406                                       ((__EVENT__) == ADC_AWD3_EVENT)   || \
01407                                       ((__EVENT__) == ADC_OVR_EVENT)    || \
01408                                       ((__EVENT__) == ADC_JQOVF_EVENT)  )
01409
01410 /**
01411   * @brief Verify the ADC oversampling ratio.
01412   * @param __RATIO__ programmed ADC oversampling ratio.
01413   * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
01414   */
01415 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
01416                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
01417                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
01418                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
01419                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
01420                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
01421                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
01422                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
01423
01424 /**
01425   * @brief Verify the ADC oversampling shift.
01426   * @param __SHIFT__ programmed ADC oversampling shift.
01427   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
01428   */
01429 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
01430                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
01431                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
01432                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
01433                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
01434                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
01435                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
01436                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
01437                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
01438
01439 /**
01440   * @brief Verify the ADC oversampling triggered mode.
01441   * @param __MODE__ programmed ADC oversampling triggered mode.
01442   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01443   */
01444 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
01445                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
01446
01447 /**
01448   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
01449   * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
01450   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01451   */
01452 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
01453                                                ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
01454
01455 /**
01456   * @brief Verify the DFSDM mode configuration.
01457   * @param __HANDLE__ ADC handle.
01458   * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
01459   *      this reason, the input parameter is the ADC handle and not the configuration parameter
01460   *      directly.
01461   * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
01462   */
01463 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
01464
01465 /**
01466   * @brief Return the DFSDM configuration mode.
01467   * @param __HANDLE__ ADC handle.
01468   * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
01469   *       For this reason, the input parameter is the ADC handle and not the configuration parameter
01470   *       directly.
01471   * @retval DFSDM configuration mode
01472   */
01473 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
01474
01475 /**
01476   * @}
01477   */
01478
01479
01480 /* Exported functions --------------------------------------------------------*/
01481 /** @addtogroup ADCEx_Exported_Functions
01482   * @{
01483   */
01484
01485 /** @addtogroup ADCEx_Exported_Functions_Group1
01486   * @{
01487   */
01488 /* IO operation functions *****************************************************/
01489
01490 /* ADC calibration */
01491 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
01492 uint32_t                HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
01493 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
01494                                                        uint32_t CalibrationFactor);
01495
01496 /* Blocking mode: Polling */
01497 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
01498 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
01499 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
01500
01501 /* Non-blocking mode: Interruption */
01502 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
01503 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
01504
01505 #if defined(ADC_MULTIMODE_SUPPORT)
01506 /* ADC multimode */
01507 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01508 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01509 uint32_t                HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
01510 #endif /* ADC_MULTIMODE_SUPPORT */
01511
01512 /* ADC retrieve conversion value intended to be used with polling or interruption */
01513 uint32_t                HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
01514
01515 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
01516 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
01517 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
01518 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
01519 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
01520 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
01521
01522 /* ADC group regular conversions stop */
01523 HAL_StatusTypeDef       HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
01524 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
01525 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
01526 #if defined(ADC_MULTIMODE_SUPPORT)
01527 HAL_StatusTypeDef       HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01528 #endif /* ADC_MULTIMODE_SUPPORT */
01529
01530 /**
01531   * @}
01532   */
01533
01534 /** @addtogroup ADCEx_Exported_Functions_Group2
01535   * @{
01536   */
01537 /* Peripheral Control functions ***********************************************/
01538 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
01539                                                         const ADC_InjectionConfTypeDef *pConfigInjected);
01540 #if defined(ADC_MULTIMODE_SUPPORT)
01541 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
01542                                                          const ADC_MultiModeTypeDef *pMultimode);
01543 #endif /* ADC_MULTIMODE_SUPPORT */
01544
01545 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
01546 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
01547 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
01548 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
01549
01550 /**
01551   * @}
01552   */
01553
01554 /**
01555   * @}
01556   */
01557
01558 /**
01559   * @}
01560   */
01561
01562 /**
01563   * @}
01564   */
01565
01566 #ifdef __cplusplus
01567 }
01568 #endif
01569
01570 #endif /* STM32G4xx_HAL_ADC_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_comp.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_comp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the COMP peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral control functions
00010   *           + Peripheral state functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025           ##### COMP Peripheral features #####
00026   ==============================================================================
00027
00028   [..]
00029       The STM32G4xx device family integrates seven analog comparators instances:
00030       COMP1, COMP2, COMP3, COMP4, COMP5, COMP6 and COMP7.
00031       (#) Comparators input minus (inverting input) and input plus (non inverting input)
00032           can be set to internal references or to GPIO pins
00033           (refer to GPIO list in reference manual).
00034
00035       (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
00036           and can be redirected to other peripherals: GPIO pins (in mode
00037           alternate functions for comparator), timers.
00038           (refer to GPIO list in reference manual).
00039
00040       (#) The comparators have interrupt capability through the EXTI controller
00041           with wake-up from sleep and stop modes.
00042
00043           From the corresponding IRQ handler, the right interrupt source can be retrieved
00044           using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
00045
00046             ##### How to use this driver #####
00047   ==============================================================================
00048   [..]
00049       This driver provides functions to configure and program the comparator instances
00050       of STM32G4xx devices.
00051
00052       To use the comparator, perform the following steps:
00053
00054       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00055       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00056            using HAL_GPIO_Init().
00057       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00058            using HAL_GPIO_Init().
00059       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00060            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00061            interrupt vector using HAL_NVIC_EnableIRQ() function.
00062
00063       (#) Configure the comparator using HAL_COMP_Init() function:
00064       (++) Select the input minus (inverting input)
00065       (++) Select the input plus (non-inverting input)
00066       (++) Select the hysteresis
00067       (++) Select the blanking source
00068       (++) Select the output polarity
00069
00070       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00071           to enable internal control clock of the comparators.
00072           However, this is a legacy strategy. In future STM32 families,
00073           COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
00074           Therefore, for compatibility anticipation, it is recommended to
00075           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00076
00077       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00078           function HAL_COMP_Init() with new input structure parameters values.
00079
00080       (#) Enable the comparator using HAL_COMP_Start() function.
00081
00082       (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
00083           to manage comparator outputs (events and output level).
00084
00085       (#) Disable the comparator using HAL_COMP_Stop() function.
00086
00087       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00088
00089       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00090           The only way to unlock the comparator is a device hardware reset.
00091
00092     *** Callback registration ***
00093     =============================================
00094     [..]
00095
00096      The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
00097      allows the user to configure dynamically the driver callbacks.
00098      Use Functions HAL_COMP_RegisterCallback()
00099      to register an interrupt callback.
00100     [..]
00101
00102      Function HAL_COMP_RegisterCallback() allows to register following callbacks:
00103        (+) TriggerCallback       : callback for COMP trigger.
00104        (+) MspInitCallback       : callback for Msp Init.
00105        (+) MspDeInitCallback     : callback for Msp DeInit.
00106      This function takes as parameters the HAL peripheral handle, the Callback ID
00107      and a pointer to the user callback function.
00108     [..]
00109
00110      Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
00111      weak function.
00112     [..]
00113
00114      HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
00115      and the Callback ID.
00116      This function allows to reset following callbacks:
00117        (+) TriggerCallback       : callback for COMP trigger.
00118        (+) MspInitCallback       : callback for Msp Init.
00119        (+) MspDeInitCallback     : callback for Msp DeInit.
00120      [..]
00121
00122      By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
00123      all callbacks are set to the corresponding weak functions:
00124      example HAL_COMP_TriggerCallback().
00125      Exception done for MspInit and MspDeInit functions that are
00126      reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
00127      these callbacks are null (not registered beforehand).
00128     [..]
00129
00130      If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
00131      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00132      [..]
00133
00134      Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
00135      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00136      in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
00137      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00138     [..]
00139
00140      Then, the user first registers the MspInit/MspDeInit user callbacks
00141      using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
00142      or HAL_COMP_Init() function.
00143      [..]
00144
00145      When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
00146      not defined, the callback registration feature is not available and all callbacks
00147      are set to the corresponding weak functions.
00148
00149   @endverbatim
00150   ******************************************************************************
00151   */
00152
00153 /* Includes ------------------------------------------------------------------*/
00154 #include "stm32g4xx_hal.h"
00155
00156 /** @addtogroup STM32G4xx_HAL_Driver
00157   * @{
00158   */
00159
00160 #ifdef HAL_COMP_MODULE_ENABLED
00161
00162
00163
00164 /** @defgroup COMP COMP
00165   * @brief COMP HAL module driver
00166   * @{
00167   */
00168
00169 /* Private typedef -----------------------------------------------------------*/
00170 /* Private define ------------------------------------------------------------*/
00171 /** @addtogroup COMP_Private_Constants
00172   * @{
00173   */
00174
00175 /* Delay for COMP startup time.                                               */
00176 /* Note: Delay required to reach propagation delay specification.             */
00177 /* Literal set to maximum value (refer to device datasheet,                   */
00178 /* parameter "tSTART").                                                       */
00179 /* Unit: us                                                                   */
00180 #define COMP_DELAY_STARTUP_US           (5UL)      /*!< Delay for COMP startup time */
00181
00182 /* Delay for COMP voltage scaler stabilization time.                          */
00183 /* Literal set to maximum value (refer to device datasheet,                   */
00184 /* parameter "tSTART_SCALER").                                                */
00185 /* Unit: us                                                                   */
00186 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)  /*!< Delay for COMP voltage scaler stabilization time */
00187
00188 #define COMP_OUTPUT_LEVEL_BITOFFSET_POS    (30UL)
00189
00190 /**
00191   * @}
00192   */
00193
00194 /* Private macro -------------------------------------------------------------*/
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /* Exported functions --------------------------------------------------------*/
00198
00199 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00200   * @{
00201   */
00202
00203 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00204   *  @brief    Initialization and de-initialization functions.
00205   *
00206 @verbatim
00207  ===============================================================================
00208               ##### Initialization and de-initialization functions #####
00209  ===============================================================================
00210     [..]  This section provides functions to initialize and de-initialize comparators
00211
00212 @endverbatim
00213   * @{
00214   */
00215
00216 /**
00217   * @brief  Initialize the COMP according to the specified
00218   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00219   * @note   If the selected comparator is locked, initialization can't be performed.
00220   *         To unlock the configuration, perform a system reset.
00221   * @param  hcomp  COMP handle
00222   * @retval HAL status
00223   */
00224 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00225 {
00226   uint32_t tmp_csr;
00227   uint32_t exti_line;
00228   uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
00229   __IO uint32_t wait_loop_index = 0UL;
00230   HAL_StatusTypeDef status = HAL_OK;
00231
00232   /* Check the COMP handle allocation and lock status */
00233   if (hcomp == NULL)
00234   {
00235     status = HAL_ERROR;
00236   }
00237   else if (__HAL_COMP_IS_LOCKED(hcomp))
00238   {
00239     status = HAL_ERROR;
00240   }
00241   else
00242   {
00243     /* Check the parameters */
00244     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00245     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
00246     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
00247     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00248     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00249     assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
00250     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00251
00252     if (hcomp->State == HAL_COMP_STATE_RESET)
00253     {
00254       /* Allocate lock resource and initialize it */
00255       hcomp->Lock = HAL_UNLOCKED;
00256
00257       /* Set COMP error code to none */
00258       COMP_CLEAR_ERRORCODE(hcomp);
00259
00260 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00261       /* Init the COMP Callback settings */
00262       hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
00263
00264       if (hcomp->MspInitCallback == NULL)
00265       {
00266         hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
00267       }
00268
00269       /* Init the low level hardware */
00270       /* Note: Internal control clock of the comparators must                 */
00271       /*       be enabled in "HAL_COMP_MspInit()"                             */
00272       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00273       hcomp->MspInitCallback(hcomp);
00274 #else
00275       /* Init the low level hardware */
00276       /* Note: Internal control clock of the comparators must                 */
00277       /*       be enabled in "HAL_COMP_MspInit()"                             */
00278       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00279       HAL_COMP_MspInit(hcomp);
00280 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00281     }
00282
00283     /* Memorize voltage scaler state before initialization */
00284     comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
00285
00286     /* Set COMP parameters */
00287     tmp_csr = (hcomp->Init.InputMinus
00288                | hcomp->Init.InputPlus
00289                | hcomp->Init.BlankingSrce
00290                | hcomp->Init.Hysteresis
00291                | hcomp->Init.OutputPol
00292               );
00293
00294     /* Set parameters in COMP register */
00295     /* Note: Update all bits except read-only, lock and enable bits */
00296     MODIFY_REG(hcomp->Instance->CSR,
00297                COMP_CSR_INMSEL   | COMP_CSR_INPSEL |
00298                COMP_CSR_POLARITY | COMP_CSR_HYST   |
00299                COMP_CSR_BLANKING | COMP_CSR_BRGEN  | COMP_CSR_SCALEN,
00300                tmp_csr
00301               );
00302
00303     /* Delay for COMP scaler bridge voltage stabilization */
00304     /* Apply the delay if voltage scaler bridge is required and not already enabled */
00305     if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
00306         (comp_voltage_scaler_initialized == 0UL))
00307     {
00308       /* Wait loop initialization and execution */
00309       /* Note: Variable divided by 2 to compensate partially              */
00310       /*       CPU processing cycles, scaling in us split to not          */
00311       /*       exceed 32 bits register capacity and handle low frequency. */
00312       wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00313       while (wait_loop_index != 0UL)
00314       {
00315         wait_loop_index--;
00316       }
00317     }
00318
00319     /* Get the EXTI line corresponding to the selected COMP instance */
00320     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00321
00322     /* Manage EXTI settings */
00323     if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
00324     {
00325       /* Configure EXTI rising edge */
00326       if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
00327       {
00328 #if defined(COMP7)
00329         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00330         {
00331           LL_EXTI_EnableRisingTrig_32_63(exti_line);
00332         }
00333         else
00334         {
00335           LL_EXTI_EnableRisingTrig_0_31(exti_line);
00336         }
00337 #else
00338         LL_EXTI_EnableRisingTrig_0_31(exti_line);
00339 #endif /* COMP7 */
00340       }
00341       else
00342       {
00343 #if defined(COMP7)
00344         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00345         {
00346           LL_EXTI_DisableRisingTrig_32_63(exti_line);
00347         }
00348         else
00349         {
00350           LL_EXTI_DisableRisingTrig_0_31(exti_line);
00351         }
00352 #else
00353         LL_EXTI_DisableRisingTrig_0_31(exti_line);
00354 #endif /* COMP7 */
00355       }
00356
00357       /* Configure EXTI falling edge */
00358       if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
00359       {
00360 #if defined(COMP7)
00361         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00362         {
00363           LL_EXTI_EnableFallingTrig_32_63(exti_line);
00364         }
00365         else
00366         {
00367           LL_EXTI_EnableFallingTrig_0_31(exti_line);
00368         }
00369 #else
00370         LL_EXTI_EnableFallingTrig_0_31(exti_line);
00371 #endif /* COMP7 */
00372       }
00373       else
00374       {
00375 #if defined(COMP7)
00376         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00377         {
00378           LL_EXTI_DisableFallingTrig_32_63(exti_line);
00379         }
00380         else
00381         {
00382           LL_EXTI_DisableFallingTrig_0_31(exti_line);
00383         }
00384 #else
00385         LL_EXTI_DisableFallingTrig_0_31(exti_line);
00386 #endif /* COMP7 */
00387       }
00388
00389       /* Clear COMP EXTI pending bit (if any) */
00390 #if defined(COMP7)
00391       if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00392       {
00393         LL_EXTI_ClearFlag_32_63(exti_line);
00394       }
00395       else
00396       {
00397         LL_EXTI_ClearFlag_0_31(exti_line);
00398       }
00399 #else
00400       LL_EXTI_ClearFlag_0_31(exti_line);
00401 #endif /* COMP7 */
00402
00403       /* Configure EXTI event mode */
00404       if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
00405       {
00406 #if defined(COMP7)
00407         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00408         {
00409           LL_EXTI_EnableEvent_32_63(exti_line);
00410         }
00411         else
00412         {
00413           LL_EXTI_EnableEvent_0_31(exti_line);
00414         }
00415 #else
00416         LL_EXTI_EnableEvent_0_31(exti_line);
00417 #endif /* COMP7 */
00418       }
00419       else
00420       {
00421 #if defined(COMP7)
00422         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00423         {
00424           LL_EXTI_DisableEvent_32_63(exti_line);
00425         }
00426         else
00427         {
00428           LL_EXTI_DisableEvent_0_31(exti_line);
00429         }
00430 #else
00431         LL_EXTI_DisableEvent_0_31(exti_line);
00432 #endif /* COMP7 */
00433       }
00434
00435       /* Configure EXTI interrupt mode */
00436       if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
00437       {
00438 #if defined(COMP7)
00439         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00440         {
00441           LL_EXTI_EnableIT_32_63(exti_line);
00442         }
00443         else
00444         {
00445           LL_EXTI_EnableIT_0_31(exti_line);
00446         }
00447 #else
00448         LL_EXTI_EnableIT_0_31(exti_line);
00449 #endif /* COMP7 */
00450       }
00451       else
00452       {
00453 #if defined(COMP7)
00454         if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00455         {
00456           LL_EXTI_DisableIT_32_63(exti_line);
00457         }
00458         else
00459         {
00460           LL_EXTI_DisableIT_0_31(exti_line);
00461         }
00462 #else
00463         LL_EXTI_DisableIT_0_31(exti_line);
00464 #endif /* COMP7 */
00465       }
00466     }
00467     else
00468     {
00469       /* Disable EXTI event mode */
00470 #if defined(COMP7)
00471       if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00472       {
00473         LL_EXTI_DisableEvent_32_63(exti_line);
00474       }
00475       else
00476       {
00477         LL_EXTI_DisableEvent_0_31(exti_line);
00478       }
00479 #else
00480       LL_EXTI_DisableEvent_0_31(exti_line);
00481 #endif /* COMP7 */
00482
00483       /* Disable EXTI interrupt mode */
00484 #if defined(COMP7)
00485       if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00486       {
00487         LL_EXTI_DisableIT_32_63(exti_line);
00488       }
00489       else
00490       {
00491         LL_EXTI_DisableIT_0_31(exti_line);
00492       }
00493 #else
00494       LL_EXTI_DisableIT_0_31(exti_line);
00495 #endif /* COMP7 */
00496     }
00497
00498     /* Set HAL COMP handle state */
00499     /* Note: Transition from state reset to state ready,                      */
00500     /*       otherwise (coming from state ready or busy) no state update.     */
00501     if (hcomp->State == HAL_COMP_STATE_RESET)
00502     {
00503       hcomp->State = HAL_COMP_STATE_READY;
00504     }
00505   }
00506
00507   return status;
00508 }
00509
00510 /**
00511   * @brief  DeInitialize the COMP peripheral.
00512   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00513   *         To unlock the configuration, perform a system reset.
00514   * @param  hcomp  COMP handle
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00518 {
00519   HAL_StatusTypeDef status = HAL_OK;
00520
00521   /* Check the COMP handle allocation and lock status */
00522   if (hcomp == NULL)
00523   {
00524     status = HAL_ERROR;
00525   }
00526   else if (__HAL_COMP_IS_LOCKED(hcomp))
00527   {
00528     status = HAL_ERROR;
00529   }
00530   else
00531   {
00532     /* Check the parameter */
00533     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00534
00535     /* Set COMP_CSR register to reset value */
00536     WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
00537
00538 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00539     if (hcomp->MspDeInitCallback == NULL)
00540     {
00541       hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
00542     }
00543
00544     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00545     hcomp->MspDeInitCallback(hcomp);
00546 #else
00547     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00548     HAL_COMP_MspDeInit(hcomp);
00549 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00550
00551     /* Set HAL COMP handle state */
00552     hcomp->State = HAL_COMP_STATE_RESET;
00553
00554     /* Release Lock */
00555     __HAL_UNLOCK(hcomp);
00556   }
00557
00558   return status;
00559 }
00560
00561 /**
00562   * @brief  Initialize the COMP MSP.
00563   * @param  hcomp  COMP handle
00564   * @retval None
00565   */
00566 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00567 {
00568   /* Prevent unused argument(s) compilation warning */
00569   UNUSED(hcomp);
00570
00571   /* NOTE : This function should not be modified, when the callback is needed,
00572             the HAL_COMP_MspInit could be implemented in the user file
00573    */
00574 }
00575
00576 /**
00577   * @brief  DeInitialize the COMP MSP.
00578   * @param  hcomp  COMP handle
00579   * @retval None
00580   */
00581 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00582 {
00583   /* Prevent unused argument(s) compilation warning */
00584   UNUSED(hcomp);
00585
00586   /* NOTE : This function should not be modified, when the callback is needed,
00587             the HAL_COMP_MspDeInit could be implemented in the user file
00588    */
00589 }
00590
00591 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00592 /**
00593   * @brief  Register a User COMP Callback
00594   *         To be used instead of the weak predefined callback
00595   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00596   *                the configuration information for the specified COMP.
00597   * @param  CallbackID ID of the callback to be registered
00598   *         This parameter can be one of the following values:
00599   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00600   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00601   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00602   * @param  pCallback pointer to the Callback function
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
00606                                             pCOMP_CallbackTypeDef pCallback)
00607 {
00608   HAL_StatusTypeDef status = HAL_OK;
00609
00610   if (pCallback == NULL)
00611   {
00612     /* Update the error code */
00613     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00614
00615     return HAL_ERROR;
00616   }
00617
00618   if (HAL_COMP_STATE_READY == hcomp->State)
00619   {
00620     switch (CallbackID)
00621     {
00622       case HAL_COMP_TRIGGER_CB_ID :
00623         hcomp->TriggerCallback = pCallback;
00624         break;
00625
00626       case HAL_COMP_MSPINIT_CB_ID :
00627         hcomp->MspInitCallback = pCallback;
00628         break;
00629
00630       case HAL_COMP_MSPDEINIT_CB_ID :
00631         hcomp->MspDeInitCallback = pCallback;
00632         break;
00633
00634       default :
00635         /* Update the error code */
00636         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00637
00638         /* Return error status */
00639         status = HAL_ERROR;
00640         break;
00641     }
00642   }
00643   else if (HAL_COMP_STATE_RESET == hcomp->State)
00644   {
00645     switch (CallbackID)
00646     {
00647       case HAL_COMP_MSPINIT_CB_ID :
00648         hcomp->MspInitCallback = pCallback;
00649         break;
00650
00651       case HAL_COMP_MSPDEINIT_CB_ID :
00652         hcomp->MspDeInitCallback = pCallback;
00653         break;
00654
00655       default :
00656         /* Update the error code */
00657         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00658
00659         /* Return error status */
00660         status = HAL_ERROR;
00661         break;
00662     }
00663   }
00664   else
00665   {
00666     /* Update the error code */
00667     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00668
00669     /* Return error status */
00670     status =  HAL_ERROR;
00671   }
00672
00673   return status;
00674 }
00675
00676 /**
00677   * @brief  Unregister a COMP Callback
00678   *         COMP callback is redirected to the weak predefined callback
00679   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00680   *                the configuration information for the specified COMP.
00681   * @param  CallbackID ID of the callback to be unregistered
00682   *         This parameter can be one of the following values:
00683   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00684   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00685   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00686   * @retval HAL status
00687   */
00688 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
00689 {
00690   HAL_StatusTypeDef status = HAL_OK;
00691
00692   if (HAL_COMP_STATE_READY == hcomp->State)
00693   {
00694     switch (CallbackID)
00695     {
00696       case HAL_COMP_TRIGGER_CB_ID :
00697         hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
00698         break;
00699
00700       case HAL_COMP_MSPINIT_CB_ID :
00701         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00702         break;
00703
00704       case HAL_COMP_MSPDEINIT_CB_ID :
00705         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00706         break;
00707
00708       default :
00709         /* Update the error code */
00710         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00711
00712         /* Return error status */
00713         status =  HAL_ERROR;
00714         break;
00715     }
00716   }
00717   else if (HAL_COMP_STATE_RESET == hcomp->State)
00718   {
00719     switch (CallbackID)
00720     {
00721       case HAL_COMP_MSPINIT_CB_ID :
00722         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00723         break;
00724
00725       case HAL_COMP_MSPDEINIT_CB_ID :
00726         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00727         break;
00728
00729       default :
00730         /* Update the error code */
00731         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00732
00733         /* Return error status */
00734         status =  HAL_ERROR;
00735         break;
00736     }
00737   }
00738   else
00739   {
00740     /* Update the error code */
00741     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00742
00743     /* Return error status */
00744     status =  HAL_ERROR;
00745   }
00746
00747   return status;
00748 }
00749
00750 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00751
00752 /**
00753   * @}
00754   */
00755
00756 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00757   *  @brief   Start-Stop operation functions.
00758   *
00759 @verbatim
00760  ===============================================================================
00761                       ##### IO operation functions #####
00762  ===============================================================================
00763     [..]  This section provides functions allowing to:
00764       (+) Start a comparator instance.
00765       (+) Stop a comparator instance.
00766
00767 @endverbatim
00768   * @{
00769   */
00770
00771 /**
00772   * @brief  Start the comparator.
00773   * @param  hcomp  COMP handle
00774   * @retval HAL status
00775   */
00776 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00777 {
00778   __IO uint32_t wait_loop_index = 0UL;
00779   HAL_StatusTypeDef status = HAL_OK;
00780
00781   /* Check the COMP handle allocation and lock status */
00782   if (hcomp == NULL)
00783   {
00784     status = HAL_ERROR;
00785   }
00786   else if (__HAL_COMP_IS_LOCKED(hcomp))
00787   {
00788     status = HAL_ERROR;
00789   }
00790   else
00791   {
00792     /* Check the parameter */
00793     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00794
00795     if (hcomp->State == HAL_COMP_STATE_READY)
00796     {
00797       /* Enable the selected comparator */
00798       SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00799
00800       /* Set HAL COMP handle state */
00801       hcomp->State = HAL_COMP_STATE_BUSY;
00802
00803       /* Delay for COMP startup time */
00804       /* Wait loop initialization and execution */
00805       /* Note: Variable divided by 2 to compensate partially                  */
00806       /*       CPU processing cycles.                                         */
00807       /* Note: In case of system low frequency (below 1Mhz), short delay      */
00808       /*       of startup time (few us) is within CPU processing cycles       */
00809       /*       of following instructions.                                     */
00810       wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
00811       while (wait_loop_index != 0UL)
00812       {
00813         wait_loop_index--;
00814       }
00815     }
00816     else
00817     {
00818       status = HAL_ERROR;
00819     }
00820   }
00821
00822   return status;
00823 }
00824
00825 /**
00826   * @brief  Stop the comparator.
00827   * @param  hcomp  COMP handle
00828   * @retval HAL status
00829   */
00830 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00831 {
00832   HAL_StatusTypeDef status = HAL_OK;
00833
00834   /* Check the COMP handle allocation and lock status */
00835   if (hcomp == NULL)
00836   {
00837     status = HAL_ERROR;
00838   }
00839   else if (__HAL_COMP_IS_LOCKED(hcomp))
00840   {
00841     status = HAL_ERROR;
00842   }
00843   else
00844   {
00845     /* Check the parameter */
00846     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00847
00848     /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY    */
00849     /* (all states except HAL_COMP_STATE_RESET and except locked status.      */
00850     if (hcomp->State != HAL_COMP_STATE_RESET)
00851     {
00852       /* Disable the selected comparator */
00853       CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00854
00855       /* Set HAL COMP handle state */
00856       hcomp->State = HAL_COMP_STATE_READY;
00857     }
00858     else
00859     {
00860       status = HAL_ERROR;
00861     }
00862   }
00863
00864   return status;
00865 }
00866
00867 /**
00868   * @brief  Comparator IRQ handler.
00869   * @param  hcomp  COMP handle
00870   * @retval None
00871   */
00872 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00873 {
00874   /* Get the EXTI line corresponding to the selected COMP instance */
00875   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00876   uint32_t tmp_comp_exti_flag_set = 0UL;
00877
00878   /* Check COMP EXTI flag */
00879 #if defined(COMP7)
00880   if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
00881   {
00882     if (LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL)
00883     {
00884       tmp_comp_exti_flag_set = 2UL;
00885     }
00886   }
00887   else
00888   {
00889     if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
00890     {
00891       tmp_comp_exti_flag_set = 1UL;
00892     }
00893   }
00894 #else
00895   if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
00896   {
00897     tmp_comp_exti_flag_set = 1UL;
00898   }
00899 #endif /* COMP7 */
00900
00901   if (tmp_comp_exti_flag_set != 0UL)
00902   {
00903     /* Clear COMP EXTI line pending bit */
00904 #if defined(COMP7)
00905     if (tmp_comp_exti_flag_set == 2UL)
00906     {
00907       LL_EXTI_ClearFlag_32_63(exti_line);
00908     }
00909     else
00910     {
00911       LL_EXTI_ClearFlag_0_31(exti_line);
00912     }
00913 #else
00914     LL_EXTI_ClearFlag_0_31(exti_line);
00915 #endif /* COMP7 */
00916
00917     /* COMP trigger user callback */
00918 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00919     hcomp->TriggerCallback(hcomp);
00920 #else
00921     HAL_COMP_TriggerCallback(hcomp);
00922 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00923   }
00924 }
00925
00926 /**
00927   * @}
00928   */
00929
00930 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00931   *  @brief   Management functions.
00932   *
00933 @verbatim
00934  ===============================================================================
00935                       ##### Peripheral Control functions #####
00936  ===============================================================================
00937     [..]
00938     This subsection provides a set of functions allowing to control the comparators.
00939
00940 @endverbatim
00941   * @{
00942   */
00943
00944 /**
00945   * @brief  Lock the selected comparator configuration.
00946   * @note   A system reset is required to unlock the comparator configuration.
00947   * @note   Locking the comparator from reset state is possible
00948   *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
00949   * @param  hcomp  COMP handle
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00953 {
00954   HAL_StatusTypeDef status = HAL_OK;
00955
00956   /* Check the COMP handle allocation and lock status */
00957   if (hcomp == NULL)
00958   {
00959     status = HAL_ERROR;
00960   }
00961   else if (__HAL_COMP_IS_LOCKED(hcomp))
00962   {
00963     status = HAL_ERROR;
00964   }
00965   else
00966   {
00967     /* Check the parameter */
00968     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00969
00970     /* Set HAL COMP handle state */
00971     switch (hcomp->State)
00972     {
00973       case HAL_COMP_STATE_RESET:
00974         hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
00975         break;
00976       case HAL_COMP_STATE_READY:
00977         hcomp->State = HAL_COMP_STATE_READY_LOCKED;
00978         break;
00979       default: /* HAL_COMP_STATE_BUSY */
00980         hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
00981         break;
00982     }
00983
00984     /* Set the lock bit corresponding to selected comparator */
00985     __HAL_COMP_LOCK(hcomp);
00986   }
00987
00988   return status;
00989 }
00990
00991 /**
00992   * @brief  Return the output level (high or low) of the selected comparator.
00993   *         On this STM32 series, comparator 'value' is taken before
00994   *         polarity and blanking are applied, thus:
00995   *           - Comparator output is low when the input plus is at a lower
00996   *             voltage than the input minus
00997   *           - Comparator output is high when the input plus is at a higher
00998   *             voltage than the input minus
00999   * @param  hcomp  COMP handle
01000   * @retval Returns the selected comparator output level:
01001   *         @arg COMP_OUTPUT_LEVEL_LOW
01002   *         @arg COMP_OUTPUT_LEVEL_HIGH
01003   *
01004   */
01005 uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp)
01006 {
01007   /* Check the parameter */
01008   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01009
01010   return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
01011                     >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
01012 }
01013
01014 /**
01015   * @brief  Comparator trigger callback.
01016   * @param  hcomp  COMP handle
01017   * @retval None
01018   */
01019 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
01020 {
01021   /* Prevent unused argument(s) compilation warning */
01022   UNUSED(hcomp);
01023
01024   /* NOTE : This function should not be modified, when the callback is needed,
01025             the HAL_COMP_TriggerCallback should be implemented in the user file
01026    */
01027 }
01028
01029
01030 /**
01031   * @}
01032   */
01033
01034 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
01035   *  @brief   Peripheral State functions.
01036   *
01037 @verbatim
01038  ===============================================================================
01039                       ##### Peripheral State functions #####
01040  ===============================================================================
01041     [..]
01042     This subsection permit to get in run-time the status of the peripheral.
01043
01044 @endverbatim
01045   * @{
01046   */
01047
01048 /**
01049   * @brief  Return the COMP handle state.
01050   * @param  hcomp  COMP handle
01051   * @retval HAL state
01052   */
01053 HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
01054 {
01055   /* Check the COMP handle allocation */
01056   if (hcomp == NULL)
01057   {
01058     return HAL_COMP_STATE_RESET;
01059   }
01060
01061   /* Check the parameter */
01062   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01063
01064   /* Return HAL COMP handle state */
01065   return hcomp->State;
01066 }
01067
01068 /**
01069   * @brief  Return the COMP error code.
01070   * @param hcomp COMP handle
01071   * @retval COMP error code
01072   */
01073 uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp)
01074 {
01075   /* Check the parameters */
01076   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01077
01078   return hcomp->ErrorCode;
01079 }
01080
01081 /**
01082   * @}
01083   */
01084
01085 /**
01086   * @}
01087   */
01088
01089 /**
01090   * @}
01091   */
01092
01093
01094
01095 #endif /* HAL_COMP_MODULE_ENABLED */
01096
01097 /**
01098   * @}
01099   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_comp.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_comp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_COMP_H
00021 #define STM32G4xx_HAL_COMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029 #include "stm32g4xx_ll_exti.h"
00030
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035
00036 /** @addtogroup COMP
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup COMP_Exported_Types COMP Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  COMP Init structure definition
00047   */
00048 typedef struct
00049 {
00050
00051   uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
00052                                     This parameter can be a value of @ref COMP_InputPlus */
00053
00054   uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
00055                                     This parameter can be a value of @ref COMP_InputMinus */
00056
00057   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00058                                     This parameter can be a value of @ref COMP_Hysteresis */
00059
00060   uint32_t OutputPol;          /*!< Set comparator output polarity.
00061                                     This parameter can be a value of @ref COMP_OutputPolarity */
00062
00063   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00064                                     This parameter can be a value of @ref COMP_BlankingSrce */
00065
00066   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00067                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00068
00069 } COMP_InitTypeDef;
00070
00071 /**
00072   * @brief  HAL COMP state machine: HAL COMP states definition
00073   */
00074 #define COMP_STATE_BITFIELD_LOCK  (0x10U)
00075 typedef enum
00076 {
00077   HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
00078   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00079   HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
00080   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00081   HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
00082   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00083 } HAL_COMP_StateTypeDef;
00084
00085 /**
00086   * @brief  COMP Handle Structure definition
00087   */
00088 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00089 typedef struct __COMP_HandleTypeDef
00090 #else
00091 typedef struct
00092 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00093 {
00094   COMP_TypeDef       *Instance;       /*!< Register base address    */
00095   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00096   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00097   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00098   __IO uint32_t      ErrorCode;       /*!< COMP error code */
00099 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00100   void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
00101   void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
00102   void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
00103 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00104 } COMP_HandleTypeDef;
00105
00106 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00107 /**
00108   * @brief  HAL COMP Callback ID enumeration definition
00109   */
00110 typedef enum
00111 {
00112   HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
00113   HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
00114   HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
00115 } HAL_COMP_CallbackIDTypeDef;
00116
00117 /**
00118   * @brief  HAL COMP Callback pointer definition
00119   */
00120 typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
00121
00122 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported constants --------------------------------------------------------*/
00129 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00130   * @{
00131   */
00132
00133 /** @defgroup COMP_Error_Code COMP Error Code
00134   * @{
00135   */
00136 #define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
00137 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00138 #define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
00139 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00145   * @{
00146   */
00147 #define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00148 #define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL)      /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00154   * @{
00155   */
00156 #define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
00157 #define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
00158 #define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
00159 #define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00160 #define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
00161 #define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
00162 #define COMP_INPUT_MINUS_DAC2_CH1      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
00163 #define COMP_INPUT_MINUS_DAC3_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
00164 #define COMP_INPUT_MINUS_DAC3_CH2      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
00165 #define COMP_INPUT_MINUS_DAC4_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
00166 #define COMP_INPUT_MINUS_DAC4_CH2      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
00167 #define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00168 #define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup COMP_Hysteresis COMP hysteresis
00174   * @{
00175   */
00176 #define COMP_HYSTERESIS_NONE           (0x00000000UL)                                        /*!< No hysteresis */
00177 #define COMP_HYSTERESIS_10MV           (                                    COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
00178 #define COMP_HYSTERESIS_20MV           (                  COMP_CSR_HYST_1                  ) /*!< Hysteresis level 20mV */
00179 #define COMP_HYSTERESIS_30MV           (                  COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
00180 #define COMP_HYSTERESIS_40MV           (COMP_CSR_HYST_2                                    ) /*!< Hysteresis level 40mV */
00181 #define COMP_HYSTERESIS_50MV           (COMP_CSR_HYST_2                   | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
00182 #define COMP_HYSTERESIS_60MV           (COMP_CSR_HYST_2 | COMP_CSR_HYST_1                  ) /*!< Hysteresis level 60mV */
00183 #define COMP_HYSTERESIS_70MV           (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
00184 #define COMP_HYSTERESIS_LOW            COMP_HYSTERESIS_10MV  /*!< Hysteresis level low */
00185 #define COMP_HYSTERESIS_MEDIUM         COMP_HYSTERESIS_40MV  /*!< Hysteresis level medium */
00186 #define COMP_HYSTERESIS_HIGH           COMP_HYSTERESIS_70MV  /*!< Hysteresis level high */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup COMP_OutputPolarity COMP output Polarity
00192   * @{
00193   */
00194 #define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00195 #define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup COMP_BlankingSrce  COMP blanking source
00201   * @{
00202   */
00203 #define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00204 #define COMP_BLANKINGSRC_TIM1_OC5_COMP1  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00205 #define COMP_BLANKINGSRC_TIM1_OC5_COMP2  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00206 #define COMP_BLANKINGSRC_TIM1_OC5_COMP3  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00207 #define COMP_BLANKINGSRC_TIM1_OC5_COMP4  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00208 #define COMP_BLANKINGSRC_TIM1_OC5_COMP5  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00209 #define COMP_BLANKINGSRC_TIM1_OC5_COMP6  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00210 #define COMP_BLANKINGSRC_TIM1_OC5_COMP7  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00211 #define COMP_BLANKINGSRC_TIM2_OC3_COMP1  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00212 #define COMP_BLANKINGSRC_TIM2_OC3_COMP2  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00213 #define COMP_BLANKINGSRC_TIM2_OC3_COMP5  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00214 #define COMP_BLANKINGSRC_TIM2_OC4_COMP3  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00215 #define COMP_BLANKINGSRC_TIM2_OC4_COMP6  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00216 #define COMP_BLANKINGSRC_TIM3_OC3_COMP1  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00217 #define COMP_BLANKINGSRC_TIM3_OC3_COMP2  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00218 #define COMP_BLANKINGSRC_TIM3_OC3_COMP3  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00219 #define COMP_BLANKINGSRC_TIM3_OC3_COMP5  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00220 #define COMP_BLANKINGSRC_TIM3_OC3_COMP7  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00221 #define COMP_BLANKINGSRC_TIM3_OC4_COMP4  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00222 #define COMP_BLANKINGSRC_TIM8_OC5_COMP1  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00223 #define COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00224 #define COMP_BLANKINGSRC_TIM8_OC5_COMP3  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00225 #define COMP_BLANKINGSRC_TIM8_OC5_COMP4  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00226 #define COMP_BLANKINGSRC_TIM8_OC5_COMP5  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00227 #define COMP_BLANKINGSRC_TIM8_OC5_COMP6  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00228 #define COMP_BLANKINGSRC_TIM8_OC5_COMP7  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00229 #define COMP_BLANKINGSRC_TIM15_OC1_COMP4 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00230 #define COMP_BLANKINGSRC_TIM15_OC2_COMP6 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00231 #define COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
00232 #define COMP_BLANKINGSRC_TIM20_OC5       (COMP_CSR_BLANKING_2 |                       COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances) */
00233 #define COMP_BLANKINGSRC_TIM15_OC1       (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances) */
00234 #define COMP_BLANKINGSRC_TIM4_OC3        (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances) */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup COMP_OutputLevel COMP Output Level
00241   * @{
00242   */
00243 /* Note: Comparator output level values are fixed to "0" and "1",             */
00244 /* corresponding COMP register bit is managed by HAL function to match        */
00245 /* with these values (independently of bit position in register).             */
00246
00247 /* When output polarity is not inverted, comparator output is low when
00248    the input plus is at a lower voltage than the input minus */
00249 #define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
00250 /* When output polarity is not inverted, comparator output is high when
00251    the input plus is at a higher voltage than the input minus */
00252 #define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00258   * @{
00259   */
00260 #define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
00261 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00262 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00263 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00264 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00265 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00266 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /* Exported macro ------------------------------------------------------------*/
00276 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00277   * @{
00278   */
00279
00280 /** @defgroup COMP_Handle_Management  COMP Handle Management
00281   * @{
00282   */
00283
00284 /** @brief  Reset COMP handle state.
00285   * @param  __HANDLE__  COMP handle
00286   * @retval None
00287   */
00288 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00289 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
00290                                                       (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
00291                                                       (__HANDLE__)->MspInitCallback = NULL;            \
00292                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
00293                                                     } while(0)
00294 #else
00295 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00296 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00297
00298 /**
00299   * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
00300   * @param __HANDLE__ COMP handle
00301   * @retval None
00302   */
00303 #define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
00304
00305 /**
00306   * @brief  Enable the specified comparator.
00307   * @param  __HANDLE__  COMP handle
00308   * @retval None
00309   */
00310 #define __HAL_COMP_ENABLE(__HANDLE__)       SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00311
00312 /**
00313   * @brief  Disable the specified comparator.
00314   * @param  __HANDLE__  COMP handle
00315   * @retval None
00316   */
00317 #define __HAL_COMP_DISABLE(__HANDLE__)      CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00318
00319 /**
00320   * @brief  Lock the specified comparator configuration.
00321   * @note   Using this macro induce HAL COMP handle state machine being no
00322   *         more in line with COMP instance state.
00323   *         To keep HAL COMP handle state machine updated, it is recommended
00324   *         to use function "HAL_COMP_Lock')".
00325   * @param  __HANDLE__  COMP handle
00326   * @retval None
00327   */
00328 #define __HAL_COMP_LOCK(__HANDLE__)         SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
00329
00330 /**
00331   * @brief  Check whether the specified comparator is locked.
00332   * @param  __HANDLE__  COMP handle
00333   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00334   */
00335 #define __HAL_COMP_IS_LOCKED(__HANDLE__)    (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
00336
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00342   * @{
00343   */
00344 /**
00345   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00346   * @retval None
00347   */
00348 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00349
00350 /**
00351   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00352   * @retval None
00353   */
00354 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00355
00356 /**
00357   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00358   * @retval None
00359   */
00360 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00361
00362 /**
00363   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00364   * @retval None
00365   */
00366 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00367
00368 /**
00369   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00370   * @retval None
00371   */
00372 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
00373                                                                 LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00374                                                                 LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
00375                                                               } while(0)
00376
00377 /**
00378   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00379   * @retval None
00380   */
00381 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00382                                                                  LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00383                                                                  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
00384                                                                } while(0)
00385
00386 /**
00387   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00388   * @retval None
00389   */
00390 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
00391
00392 /**
00393   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00394   * @retval None
00395   */
00396 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
00397
00398 /**
00399   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00400   * @retval None
00401   */
00402 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
00403
00404 /**
00405   * @brief  Enable the COMP1 EXTI line in event mode.
00406   * @retval None
00407   */
00408 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
00409
00410 /**
00411   * @brief  Disable the COMP1 EXTI line in event mode.
00412   * @retval None
00413   */
00414 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
00415
00416 /**
00417   * @brief  Check whether the COMP1 EXTI line flag is set.
00418   * @retval RESET or SET
00419   */
00420 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
00421
00422 /**
00423   * @brief  Clear the COMP1 EXTI flag.
00424   * @retval None
00425   */
00426 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
00427
00428 /**
00429   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00430   * @retval None
00431   */
00432 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00433
00434 /**
00435   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00436   * @retval None
00437   */
00438 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00439
00440 /**
00441   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00442   * @retval None
00443   */
00444 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00445
00446 /**
00447   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00448   * @retval None
00449   */
00450 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00451
00452 /**
00453   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00454   * @retval None
00455   */
00456 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
00457                                                                 LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
00458                                                                 LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
00459                                                               } while(0)
00460
00461 /**
00462   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00463   * @retval None
00464   */
00465 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00466                                                                  LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
00467                                                                  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
00468                                                                } while(0)
00469
00470 /**
00471   * @brief  Enable the COMP2 EXTI line in interrupt mode.
00472   * @retval None
00473   */
00474 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
00475
00476 /**
00477   * @brief  Disable the COMP2 EXTI line in interrupt mode.
00478   * @retval None
00479   */
00480 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
00481
00482 /**
00483   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00484   * @retval None
00485   */
00486 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
00487
00488 /**
00489   * @brief  Enable the COMP2 EXTI line in event mode.
00490   * @retval None
00491   */
00492 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
00493
00494 /**
00495   * @brief  Disable the COMP2 EXTI line in event mode.
00496   * @retval None
00497   */
00498 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
00499
00500 /**
00501   * @brief  Check whether the COMP2 EXTI line flag is set.
00502   * @retval RESET or SET
00503   */
00504 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
00505
00506 /**
00507   * @brief  Clear the COMP2 EXTI flag.
00508   * @retval None
00509   */
00510 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
00511
00512 /**
00513   * @brief  Enable the COMP3 EXTI line rising edge trigger.
00514   * @retval None
00515   */
00516 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
00517
00518 /**
00519   * @brief  Disable the COMP3 EXTI line rising edge trigger.
00520   * @retval None
00521   */
00522 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
00523
00524 /**
00525   * @brief  Enable the COMP3 EXTI line falling edge trigger.
00526   * @retval None
00527   */
00528 #define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
00529
00530 /**
00531   * @brief  Disable the COMP3 EXTI line falling edge trigger.
00532   * @retval None
00533   */
00534 #define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
00535
00536 /**
00537   * @brief  Enable the COMP3 EXTI line rising & falling edge trigger.
00538   * @retval None
00539   */
00540 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00541                                                                   LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00542                                                                   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00543                                                                 } while(0)
00544
00545 /**
00546   * @brief  Disable the COMP3 EXTI line rising & falling edge trigger.
00547   * @retval None
00548   */
00549 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00550                                                                   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00551                                                                   LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00552                                                                 } while(0)
00553
00554 /**
00555   * @brief  Enable the COMP3 EXTI line in interrupt mode.
00556   * @retval None
00557   */
00558 #define __HAL_COMP_COMP3_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
00559
00560 /**
00561   * @brief  Disable the COMP3 EXTI line in interrupt mode.
00562   * @retval None
00563   */
00564 #define __HAL_COMP_COMP3_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
00565
00566 /**
00567   * @brief  Generate a software interrupt on the COMP3 EXTI line.
00568   * @retval None
00569   */
00570 #define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
00571
00572 /**
00573   * @brief  Enable the COMP3 EXTI line in event mode.
00574   * @retval None
00575   */
00576 #define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
00577
00578 /**
00579   * @brief  Disable the COMP3 EXTI line in event mode.
00580   * @retval None
00581   */
00582 #define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
00583
00584 /**
00585   * @brief  Check whether the COMP3 EXTI line flag is set.
00586   * @retval RESET or SET
00587   */
00588 #define __HAL_COMP_COMP3_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
00589
00590 /**
00591   * @brief  Clear the COMP3 EXTI flag.
00592   * @retval None
00593   */
00594 #define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
00595
00596 /**
00597   * @brief  Enable the COMP4 EXTI line rising edge trigger.
00598   * @retval None
00599   */
00600 #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
00601
00602 /**
00603   * @brief  Disable the COMP4 EXTI line rising edge trigger.
00604   * @retval None
00605   */
00606 #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
00607
00608 /**
00609   * @brief  Enable the COMP4 EXTI line falling edge trigger.
00610   * @retval None
00611   */
00612 #define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
00613
00614 /**
00615   * @brief  Disable the COMP4 EXTI line falling edge trigger.
00616   * @retval None
00617   */
00618 #define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
00619
00620 /**
00621   * @brief  Enable the COMP4 EXTI line rising & falling edge trigger.
00622   * @retval None
00623   */
00624 #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00625                                                                   LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
00626                                                                   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
00627                                                                 } while(0)
00628
00629 /**
00630   * @brief  Disable the COMP4 EXTI line rising & falling edge trigger.
00631   * @retval None
00632   */
00633 #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00634                                                                   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
00635                                                                   LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
00636                                                                 } while(0)
00637
00638 /**
00639   * @brief  Enable the COMP4 EXTI line in interrupt mode.
00640   * @retval None
00641   */
00642 #define __HAL_COMP_COMP4_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
00643
00644 /**
00645   * @brief  Disable the COMP4 EXTI line in interrupt mode.
00646   * @retval None
00647   */
00648 #define __HAL_COMP_COMP4_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
00649
00650 /**
00651   * @brief  Generate a software interrupt on the COMP4 EXTI line.
00652   * @retval None
00653   */
00654 #define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
00655
00656 /**
00657   * @brief  Enable the COMP4 EXTI line in event mode.
00658   * @retval None
00659   */
00660 #define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
00661
00662 /**
00663   * @brief  Disable the COMP4 EXTI line in event mode.
00664   * @retval None
00665   */
00666 #define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
00667
00668 /**
00669   * @brief  Check whether the COMP4 EXTI line flag is set.
00670   * @retval RESET or SET
00671   */
00672 #define __HAL_COMP_COMP4_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
00673
00674 /**
00675   * @brief  Clear the COMP4 EXTI flag.
00676   * @retval None
00677   */
00678 #define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
00679
00680 #if  defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00681 /**
00682   * @brief  Enable the COMP5 EXTI line rising edge trigger.
00683   * @retval None
00684   */
00685 #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
00686
00687 /**
00688   * @brief  Disable the COMP5 EXTI line rising edge trigger.
00689   * @retval None
00690   */
00691 #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
00692
00693 /**
00694   * @brief  Enable the COMP5 EXTI line falling edge trigger.
00695   * @retval None
00696   */
00697 #define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
00698
00699 /**
00700   * @brief  Disable the COMP5 EXTI line falling edge trigger.
00701   * @retval None
00702   */
00703 #define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
00704
00705 /**
00706   * @brief  Enable the COMP5 EXTI line rising & falling edge trigger.
00707   * @retval None
00708   */
00709 #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00710                                                                   LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
00711                                                                   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
00712                                                                 } while(0)
00713
00714 /**
00715   * @brief  Disable the COMP5 EXTI line rising & falling edge trigger.
00716   * @retval None
00717   */
00718 #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00719                                                                   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
00720                                                                   LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
00721                                                                 } while(0)
00722
00723 /**
00724   * @brief  Enable the COMP5 EXTI line in interrupt mode.
00725   * @retval None
00726   */
00727 #define __HAL_COMP_COMP5_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP5)
00728
00729 /**
00730   * @brief  Disable the COMP5 EXTI line in interrupt mode.
00731   * @retval None
00732   */
00733 #define __HAL_COMP_COMP5_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP5)
00734
00735 /**
00736   * @brief  Generate a software interrupt on the COMP5 EXTI line.
00737   * @retval None
00738   */
00739 #define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP5)
00740
00741 /**
00742   * @brief  Enable the COMP5 EXTI line in event mode.
00743   * @retval None
00744   */
00745 #define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP5)
00746
00747 /**
00748   * @brief  Disable the COMP5 EXTI line in event mode.
00749   * @retval None
00750   */
00751 #define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP5)
00752
00753 /**
00754   * @brief  Check whether the COMP5 EXTI line flag is set.
00755   * @retval RESET or SET
00756   */
00757 #define __HAL_COMP_COMP5_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP5)
00758
00759 /**
00760   * @brief  Clear the COMP5 EXTI flag.
00761   * @retval None
00762   */
00763 #define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
00764
00765 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
00766 #if  defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00767 /**
00768   * @brief  Enable the COMP6 EXTI line rising edge trigger.
00769   * @retval None
00770   */
00771 #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
00772
00773 /**
00774   * @brief  Disable the COMP6 EXTI line rising edge trigger.
00775   * @retval None
00776   */
00777 #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
00778
00779 /**
00780   * @brief  Enable the COMP6 EXTI line falling edge trigger.
00781   * @retval None
00782   */
00783 #define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
00784
00785 /**
00786   * @brief  Disable the COMP6 EXTI line falling edge trigger.
00787   * @retval None
00788   */
00789 #define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
00790
00791 /**
00792   * @brief  Enable the COMP6 EXTI line rising & falling edge trigger.
00793   * @retval None
00794   */
00795 #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00796                                                                   LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
00797                                                                   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
00798                                                                 } while(0)
00799
00800 /**
00801   * @brief  Disable the COMP6 EXTI line rising & falling edge trigger.
00802   * @retval None
00803   */
00804 #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00805                                                                   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
00806                                                                   LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
00807                                                                 } while(0)
00808
00809 /**
00810   * @brief  Enable the COMP6 EXTI line in interrupt mode.
00811   * @retval None
00812   */
00813 #define __HAL_COMP_COMP6_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP6)
00814
00815 /**
00816   * @brief  Disable the COMP6 EXTI line in interrupt mode.
00817   * @retval None
00818   */
00819 #define __HAL_COMP_COMP6_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP6)
00820
00821 /**
00822   * @brief  Generate a software interrupt on the COMP6 EXTI line.
00823   * @retval None
00824   */
00825 #define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP6)
00826
00827 /**
00828   * @brief  Enable the COMP6 EXTI line in event mode.
00829   * @retval None
00830   */
00831 #define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP6)
00832
00833 /**
00834   * @brief  Disable the COMP6 EXTI line in event mode.
00835   * @retval None
00836   */
00837 #define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP6)
00838
00839 /**
00840   * @brief  Check whether the COMP6 EXTI line flag is set.
00841   * @retval RESET or SET
00842   */
00843 #define __HAL_COMP_COMP6_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP6)
00844
00845 /**
00846   * @brief  Clear the COMP6 EXTI flag.
00847   * @retval None
00848   */
00849 #define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
00850
00851 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
00852 #if  defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00853 /**
00854   * @brief  Enable the COMP7 EXTI line rising edge trigger.
00855   * @retval None
00856   */
00857 #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
00858
00859 /**
00860   * @brief  Disable the COMP7 EXTI line rising edge trigger.
00861   * @retval None
00862   */
00863 #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
00864
00865 /**
00866   * @brief  Enable the COMP7 EXTI line falling edge trigger.
00867   * @retval None
00868   */
00869 #define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
00870
00871 /**
00872   * @brief  Disable the COMP7 EXTI line falling edge trigger.
00873   * @retval None
00874   */
00875 #define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
00876
00877 /**
00878   * @brief  Enable the COMP7 EXTI line rising & falling edge trigger.
00879   * @retval None
00880   */
00881 #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00882                                                                   LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
00883                                                                   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
00884                                                                 } while(0)
00885
00886 /**
00887   * @brief  Disable the COMP7 EXTI line rising & falling edge trigger.
00888   * @retval None
00889   */
00890 #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00891                                                                   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
00892                                                                   LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
00893                                                                 } while(0)
00894
00895 /**
00896   * @brief  Enable the COMP7 EXTI line in interrupt mode.
00897   * @retval None
00898   */
00899 #define __HAL_COMP_COMP7_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP7)
00900
00901 /**
00902   * @brief  Disable the COMP7 EXTI line in interrupt mode.
00903   * @retval None
00904   */
00905 #define __HAL_COMP_COMP7_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP7)
00906
00907 /**
00908   * @brief  Generate a software interrupt on the COMP7 EXTI line.
00909   * @retval None
00910   */
00911 #define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP7)
00912
00913 /**
00914   * @brief  Enable the COMP7 EXTI line in event mode.
00915   * @retval None
00916   */
00917 #define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP7)
00918
00919 /**
00920   * @brief  Disable the COMP7 EXTI line in event mode.
00921   * @retval None
00922   */
00923 #define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP7)
00924
00925 /**
00926   * @brief  Check whether the COMP7 EXTI line flag is set.
00927   * @retval RESET or SET
00928   */
00929 #define __HAL_COMP_COMP7_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP7)
00930
00931 /**
00932   * @brief  Clear the COMP7 EXTI flag.
00933   * @retval None
00934   */
00935 #define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
00936
00937 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
00938 /**
00939   * @}
00940   */
00941
00942 /**
00943   * @}
00944   */
00945
00946
00947 /* Private types -------------------------------------------------------------*/
00948 /* Private constants ---------------------------------------------------------*/
00949 /** @defgroup COMP_Private_Constants COMP Private Constants
00950   * @{
00951   */
00952
00953 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00954   * @{
00955   */
00956 #define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
00957 #define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_22)  /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
00958 #define COMP_EXTI_LINE_COMP3           (LL_EXTI_LINE_29)  /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
00959 #define COMP_EXTI_LINE_COMP4           (LL_EXTI_LINE_30)  /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
00960 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00961 #define COMP_EXTI_LINE_COMP5           (LL_EXTI_LINE_31)  /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
00962 #define COMP_EXTI_LINE_COMP6           (LL_EXTI_LINE_32)  /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
00963 #define COMP_EXTI_LINE_COMP7           (LL_EXTI_LINE_33)  /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
00964 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
00965 /**
00966   * @}
00967   */
00968
00969 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00970   * @{
00971   */
00972 #define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
00973 #define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
00974 #define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
00975 #define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
00976 /**
00977   * @}
00978   */
00979
00980 /**
00981   * @}
00982   */
00983
00984 /* Private macros ------------------------------------------------------------*/
00985 /** @defgroup COMP_Private_Macros COMP Private Macros
00986   * @{
00987   */
00988
00989 /** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
00990   * @{
00991   */
00992 /**
00993   * @brief  Get the specified EXTI line for a comparator instance.
00994   * @param  __INSTANCE__  specifies the COMP instance.
00995   * @retval value of @ref COMP_ExtiLine
00996   */
00997 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00998 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
00999                                              :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
01000                                              :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
01001                                              :((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 \
01002                                              :((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 \
01003                                              :((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 \
01004                                              : COMP_EXTI_LINE_COMP7)
01005 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
01006 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
01007                                              :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
01008                                              :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
01009                                              : COMP_EXTI_LINE_COMP4)
01010 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
01011 /**
01012   * @}
01013   */
01014
01015 /** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
01016   * @{
01017   */
01018 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
01019                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
01020
01021 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
01022 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  ||\
01023                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  ||\
01024                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  ||\
01025                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     ||\
01026                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         ||\
01027                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         ||\
01028                                                                  (((__COMP_INSTANCE__) == COMP1)                        && \
01029                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
01030                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
01031                                                                  )                                                      || \
01032                                                                  (((__COMP_INSTANCE__) == COMP2)                        && \
01033                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  ||\
01034                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
01035                                                                  )                                                      || \
01036                                                                  (((__COMP_INSTANCE__) == COMP3)                        && \
01037                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
01038                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))   \
01039                                                                  )                                                      || \
01040                                                                  (((__COMP_INSTANCE__) == COMP4)                        && \
01041                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
01042                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
01043                                                                  )                                                      || \
01044                                                                  (((__COMP_INSTANCE__) == COMP5)                        && \
01045                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  ||\
01046                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1))   \
01047                                                                  )                                                      || \
01048                                                                  (((__COMP_INSTANCE__) == COMP6)                        && \
01049                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1)  ||\
01050                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2))   \
01051                                                                  )                                                      || \
01052                                                                  (((__COMP_INSTANCE__) == COMP7)                        && \
01053                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1)  ||\
01054                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1))   \
01055                                                                  ))
01056 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
01057 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  ||\
01058                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  ||\
01059                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  ||\
01060                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     ||\
01061                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         ||\
01062                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         ||\
01063                                                                  (((__COMP_INSTANCE__) == COMP1)                        && \
01064                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
01065                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))   \
01066                                                                  )                                                      || \
01067                                                                  (((__COMP_INSTANCE__) == COMP2)                        && \
01068                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  ||\
01069                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
01070                                                                  )                                                      || \
01071                                                                  (((__COMP_INSTANCE__) == COMP3)                        && \
01072                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
01073                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))   \
01074                                                                  )                                                      || \
01075                                                                  (((__COMP_INSTANCE__) == COMP4)                        && \
01076                                                                   (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  ||\
01077                                                                    ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))   \
01078                                                                  ))
01079 #endif
01080
01081
01082 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
01083                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_10MV)   || \
01084                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_20MV)   || \
01085                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_30MV)   || \
01086                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_40MV)   || \
01087                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_50MV)   || \
01088                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_60MV)   || \
01089                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_70MV)   || \
01090                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
01091                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
01092                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
01093
01094 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
01095                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
01096
01097 /* Note: Output blanking source depends on COMP instances     */
01098 /*       Better use IS_COMP_BLANKINGSRC_INSTANCE instead      */
01099 /*       Macro kept for compatibility with other STM32 series */
01100 #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
01101   (   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
01102       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
01103       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)     \
01104       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)     \
01105       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)     \
01106       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5)     \
01107       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6)     \
01108       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7)     \
01109       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
01110       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)     \
01111       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5)     \
01112       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)     \
01113       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6)     \
01114       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
01115       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)     \
01116       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)     \
01117       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5)     \
01118       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7)     \
01119       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)     \
01120       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)     \
01121       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
01122       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)     \
01123       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)     \
01124       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5)     \
01125       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6)     \
01126       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7)     \
01127       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)    \
01128       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6)    \
01129       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7)    \
01130       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)          \
01131       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)          \
01132       || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)           \
01133   )
01134 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
01135 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
01136   ((((__INSTANCE__) == COMP1) &&                                               \
01137     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01138      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
01139      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
01140      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
01141      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
01142    ||                                                                          \
01143    (((__INSTANCE__) == COMP2) &&                                               \
01144     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01145      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
01146      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
01147      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
01148      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
01149    ||                                                                          \
01150    (((__INSTANCE__) == COMP3) &&                                               \
01151     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01152      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
01153      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
01154      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
01155      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
01156    ||                                                                          \
01157    (((__INSTANCE__) == COMP4) &&                                               \
01158     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01159      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
01160      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
01161      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
01162      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
01163    ||                                                                          \
01164    (((__INSTANCE__) == COMP5) &&                                               \
01165     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01166      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5)  ||      \
01167      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5)  ||      \
01168      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5)  ||      \
01169      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5)))        \
01170    ||                                                                          \
01171    (((__INSTANCE__) == COMP6) &&                                               \
01172     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01173      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6)  ||      \
01174      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6)  ||      \
01175      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6)  ||      \
01176      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6)))       \
01177    ||                                                                          \
01178    (((__INSTANCE__) == COMP7) &&                                               \
01179     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01180      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7)  ||      \
01181      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7)  ||      \
01182      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7)  ||      \
01183      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7)))       \
01184    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)             \
01185    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)             \
01186    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)              \
01187   )
01188 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
01189 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
01190   ((((__INSTANCE__) == COMP1) &&                                               \
01191     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01192      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
01193      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
01194      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
01195      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
01196    ||                                                                          \
01197    (((__INSTANCE__) == COMP2) &&                                               \
01198     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01199      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
01200      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
01201      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
01202      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
01203    ||                                                                          \
01204    (((__INSTANCE__) == COMP3) &&                                               \
01205     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01206      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
01207      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
01208      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
01209      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
01210    ||                                                                          \
01211    (((__INSTANCE__) == COMP4) &&                                               \
01212     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01213      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
01214      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
01215      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
01216      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
01217    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)             \
01218    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)              \
01219   )
01220 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
01221 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
01222   ((((__INSTANCE__) == COMP1) &&                                               \
01223     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01224      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
01225      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
01226      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
01227      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
01228    ||                                                                          \
01229    (((__INSTANCE__) == COMP2) &&                                               \
01230     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01231      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
01232      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
01233      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
01234      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
01235    ||                                                                          \
01236    (((__INSTANCE__) == COMP3) &&                                               \
01237     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01238      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
01239      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
01240      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
01241      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
01242    ||                                                                          \
01243    (((__INSTANCE__) == COMP4) &&                                               \
01244     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
01245      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
01246      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
01247      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
01248      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
01249    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)             \
01250    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)             \
01251    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)              \
01252   )
01253 #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
01254
01255 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
01256                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
01257                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
01258                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
01259                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
01260                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
01261                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
01262
01263 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
01264                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
01265
01266 /**
01267   * @}
01268   */
01269
01270 /**
01271   * @}
01272   */
01273
01274
01275 /* Exported functions --------------------------------------------------------*/
01276 /** @addtogroup COMP_Exported_Functions
01277   * @{
01278   */
01279
01280 /** @addtogroup COMP_Exported_Functions_Group1
01281   * @{
01282   */
01283
01284 /* Initialization and de-initialization functions  **********************************/
01285 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
01286 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
01287 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
01288 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
01289
01290 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
01291 /* Callbacks Register/UnRegister functions  ***********************************/
01292 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
01293                                             pCOMP_CallbackTypeDef pCallback);
01294 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
01295 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
01296 /**
01297   * @}
01298   */
01299
01300 /* IO operation functions  *****************************************************/
01301 /** @addtogroup COMP_Exported_Functions_Group2
01302   * @{
01303   */
01304 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
01305 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
01306 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
01307 /**
01308   * @}
01309   */
01310
01311 /* Peripheral Control functions  ************************************************/
01312 /** @addtogroup COMP_Exported_Functions_Group3
01313   * @{
01314   */
01315 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
01316 uint32_t          HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
01317 /* Callback in interrupt mode */
01318 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
01319 /**
01320   * @}
01321   */
01322
01323 /* Peripheral State functions  **************************************************/
01324 /** @addtogroup COMP_Exported_Functions_Group4
01325   * @{
01326   */
01327 HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
01328 uint32_t              HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
01329 /**
01330   * @}
01331   */
01332
01333 /**
01334   * @}
01335   */
01336
01337 /**
01338   * @}
01339   */
01340
01341 /**
01342   * @}
01343   */
01344
01345 #ifdef __cplusplus
01346 }
01347 #endif
01348
01349 #endif /* STM32G4xx_HAL_COMP_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_conf.h Source File

  • File List
  • Globals
stm32g4xx_hal_conf.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @brief   HAL configuration template file.
00006   *          This file should be copied to the application folder and renamed
00007   *          to stm32g4xx_hal_conf.h.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * Copyright (c) 2019 STMicroelectronics.
00012   * All rights reserved.
00013   *
00014   * This software is licensed under terms that can be found in the LICENSE file
00015   * in the root directory of this software component.
00016   * If no LICENSE file comes with this software, it is provided AS-IS.
00017   *
00018   ******************************************************************************
00019   */
00020
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef STM32G4xx_HAL_CONF_H
00023 #define STM32G4xx_HAL_CONF_H
00024
00025 #ifdef __cplusplus
00026 extern "C" {
00027 #endif
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031
00032 /* ########################## Module Selection ############################## */
00033 /**
00034   * @brief This is the list of modules to be used in the HAL driver
00035   */
00036 #define HAL_MODULE_ENABLED
00037 #define HAL_ADC_MODULE_ENABLED
00038 #define HAL_COMP_MODULE_ENABLED
00039 #define HAL_CORDIC_MODULE_ENABLED
00040 #define HAL_CORTEX_MODULE_ENABLED
00041 #define HAL_CRC_MODULE_ENABLED
00042 #define HAL_CRYP_MODULE_ENABLED
00043 #define HAL_DAC_MODULE_ENABLED
00044 #define HAL_DMA_MODULE_ENABLED
00045 #define HAL_EXTI_MODULE_ENABLED
00046 #define HAL_FDCAN_MODULE_ENABLED
00047 #define HAL_FLASH_MODULE_ENABLED
00048 #define HAL_FMAC_MODULE_ENABLED
00049 #define HAL_GPIO_MODULE_ENABLED
00050 #define HAL_HRTIM_MODULE_ENABLED
00051 #define HAL_IRDA_MODULE_ENABLED
00052 #define HAL_IWDG_MODULE_ENABLED
00053 #define HAL_I2C_MODULE_ENABLED
00054 #define HAL_I2S_MODULE_ENABLED
00055 #define HAL_LPTIM_MODULE_ENABLED
00056 #define HAL_NAND_MODULE_ENABLED
00057 #define HAL_NOR_MODULE_ENABLED
00058 #define HAL_OPAMP_MODULE_ENABLED
00059 #define HAL_PCD_MODULE_ENABLED
00060 #define HAL_PWR_MODULE_ENABLED
00061 #define HAL_QSPI_MODULE_ENABLED
00062 #define HAL_RCC_MODULE_ENABLED
00063 #define HAL_RNG_MODULE_ENABLED
00064 #define HAL_RTC_MODULE_ENABLED
00065 #define HAL_SAI_MODULE_ENABLED
00066 #define HAL_SMARTCARD_MODULE_ENABLED
00067 #define HAL_SMBUS_MODULE_ENABLED
00068 #define HAL_SPI_MODULE_ENABLED
00069 #define HAL_SRAM_MODULE_ENABLED
00070 #define HAL_TIM_MODULE_ENABLED
00071 #define HAL_UART_MODULE_ENABLED
00072 #define HAL_USART_MODULE_ENABLED
00073 #define HAL_WWDG_MODULE_ENABLED
00074
00075 /* ########################## Register Callbacks selection ############################## */
00076 /**
00077   * @brief This is the list of modules where register callback can be used
00078   */
00079
00080 #define USE_HAL_ADC_REGISTER_CALLBACKS 1U
00081 #define USE_HAL_COMP_REGISTER_CALLBACKS 1U
00082 #define USE_HAL_CORDIC_REGISTER_CALLBACKS 1U
00083 #define USE_HAL_CRYP_REGISTER_CALLBACKS 1U
00084 #define USE_HAL_DAC_REGISTER_CALLBACKS 1U
00085 #define USE_HAL_EXTI_REGISTER_CALLBACKS 1U
00086 #define USE_HAL_FDCAN_REGISTER_CALLBACKS 1U
00087 #define USE_HAL_FMAC_REGISTER_CALLBACKS 1U
00088 #define USE_HAL_HRTIM_REGISTER_CALLBACKS 1U
00089 #define USE_HAL_I2C_REGISTER_CALLBACKS 1U
00090 #define USE_HAL_I2S_REGISTER_CALLBACKS 1U
00091 #define USE_HAL_IRDA_REGISTER_CALLBACKS 1U
00092 #define USE_HAL_LPTIM_REGISTER_CALLBACKS 1U
00093 #define USE_HAL_NAND_REGISTER_CALLBACKS 1U
00094 #define USE_HAL_NOR_REGISTER_CALLBACKS 1U
00095 #define USE_HAL_OPAMP_REGISTER_CALLBACKS 1U
00096 #define USE_HAL_PCD_REGISTER_CALLBACKS 1U
00097 #define USE_HAL_QSPI_REGISTER_CALLBACKS 1U
00098 #define USE_HAL_RNG_REGISTER_CALLBACKS 1U
00099 #define USE_HAL_RTC_REGISTER_CALLBACKS 1U
00100 #define USE_HAL_SAI_REGISTER_CALLBACKS 1U
00101 #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1U
00102 #define USE_HAL_SMBUS_REGISTER_CALLBACKS 1U
00103 #define USE_HAL_SPI_REGISTER_CALLBACKS 1U
00104 #define USE_HAL_SRAM_REGISTER_CALLBACKS 1U
00105 #define USE_HAL_TIM_REGISTER_CALLBACKS 1U
00106 #define USE_HAL_UART_REGISTER_CALLBACKS 1U
00107 #define USE_HAL_USART_REGISTER_CALLBACKS 1U
00108 #define USE_HAL_WWDG_REGISTER_CALLBACKS 1U
00109
00110 /* ########################## Oscillator Values adaptation ####################*/
00111 /**
00112   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00113   *        This value is used by the RCC HAL module to compute the system frequency
00114   *        (when HSE is used as system clock source, directly or through the PLL).
00115   */
00116 #if !defined  (HSE_VALUE)
00117 #define HSE_VALUE    (8000000UL) /*!< Value of the External oscillator in Hz */
00118 #endif /* HSE_VALUE */
00119
00120 #if !defined  (HSE_STARTUP_TIMEOUT)
00121 #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
00122 #endif /* HSE_STARTUP_TIMEOUT */
00123
00124 /**
00125   * @brief Internal High Speed oscillator (HSI) value.
00126   *        This value is used by the RCC HAL module to compute the system frequency
00127   *        (when HSI is used as system clock source, directly or through the PLL).
00128   */
00129 #if !defined  (HSI_VALUE)
00130 #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
00131 #endif /* HSI_VALUE */
00132
00133 /**
00134   * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
00135   *        This internal oscillator is mainly dedicated to provide a high precision clock to
00136   *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
00137   *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
00138   *        which is subject to manufacturing process variations.
00139   */
00140 #if !defined  (HSI48_VALUE)
00141 #define HSI48_VALUE   (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
00142                                           The real value my vary depending on manufacturing process variations.*/
00143 #endif /* HSI48_VALUE */
00144
00145 /**
00146   * @brief Internal Low Speed oscillator (LSI) value.
00147   */
00148 #if !defined  (LSI_VALUE)
00149 /*!< Value of the Internal Low Speed oscillator in Hz
00150 The real value may vary depending on the variations in voltage and temperature.*/
00151 #define LSI_VALUE  (32000UL)      /*!< LSI Typical Value in Hz*/
00152 #endif /* LSI_VALUE */
00153 /**
00154   * @brief External Low Speed oscillator (LSE) value.
00155   *        This value is used by the UART, RTC HAL module to compute the system frequency
00156   */
00157 #if !defined  (LSE_VALUE)
00158 #define LSE_VALUE    (32768UL) /*!< Value of the External oscillator in Hz*/
00159 #endif /* LSE_VALUE */
00160
00161 #if !defined  (LSE_STARTUP_TIMEOUT)
00162 #define LSE_STARTUP_TIMEOUT    (5000UL)  /*!< Time out for LSE start up, in ms */
00163 #endif /* LSE_STARTUP_TIMEOUT */
00164
00165 /**
00166   * @brief External clock source for I2S and SAI peripherals
00167   *        This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
00168   *        frequency, this source is inserted directly through I2S_CKIN pad.
00169   */
00170 #if !defined  (EXTERNAL_CLOCK_VALUE)
00171 #define EXTERNAL_CLOCK_VALUE    (48000UL) /*!< Value of the External clock source in Hz*/
00172 #endif /* EXTERNAL_CLOCK_VALUE */
00173
00174 /* Tip: To avoid modifying this file each time you need to use different HSE,
00175    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00176
00177 /* ########################### System Configuration ######################### */
00178 /**
00179   * @brief This is the HAL system configuration section
00180   */
00181 #define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
00182 #define  TICK_INT_PRIORITY            (0x0FUL) /*!< tick interrupt priority */
00183 #define  USE_RTOS                     0U
00184 #define  PREFETCH_ENABLE              0U
00185 #define  INSTRUCTION_CACHE_ENABLE     1U
00186 #define  DATA_CACHE_ENABLE            1U
00187
00188 /* ########################## Assert Selection ############################## */
00189 /**
00190   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00191   *        HAL drivers code
00192   */
00193 /* #define USE_FULL_ASSERT               1U */
00194
00195 /* ################## SPI peripheral configuration ########################## */
00196
00197 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
00198  * Activated: CRC code is present inside driver
00199  * Deactivated: CRC code cleaned from driver
00200  */
00201
00202 #define USE_SPI_CRC                   1U
00203
00204 /* Includes ------------------------------------------------------------------*/
00205 /**
00206   * @brief Include module's header file
00207   */
00208
00209 #ifdef HAL_RCC_MODULE_ENABLED
00210 #include "stm32g4xx_hal_rcc.h"
00211 #endif /* HAL_RCC_MODULE_ENABLED */
00212
00213 #ifdef HAL_GPIO_MODULE_ENABLED
00214 #include "stm32g4xx_hal_gpio.h"
00215 #endif /* HAL_GPIO_MODULE_ENABLED */
00216
00217 #ifdef HAL_DMA_MODULE_ENABLED
00218 #include "stm32g4xx_hal_dma.h"
00219 #endif /* HAL_DMA_MODULE_ENABLED */
00220
00221 #ifdef HAL_CORTEX_MODULE_ENABLED
00222 #include "stm32g4xx_hal_cortex.h"
00223 #endif /* HAL_CORTEX_MODULE_ENABLED */
00224
00225 #ifdef HAL_ADC_MODULE_ENABLED
00226 #include "stm32g4xx_hal_adc.h"
00227 #endif /* HAL_ADC_MODULE_ENABLED */
00228
00229 #ifdef HAL_COMP_MODULE_ENABLED
00230 #include "stm32g4xx_hal_comp.h"
00231 #endif /* HAL_COMP_MODULE_ENABLED */
00232
00233 #ifdef HAL_CORDIC_MODULE_ENABLED
00234 #include "stm32g4xx_hal_cordic.h"
00235 #endif /* HAL_CORDIC_MODULE_ENABLED */
00236
00237 #ifdef HAL_CRC_MODULE_ENABLED
00238 #include "stm32g4xx_hal_crc.h"
00239 #endif /* HAL_CRC_MODULE_ENABLED */
00240
00241 #ifdef HAL_CRYP_MODULE_ENABLED
00242 #include "stm32g4xx_hal_cryp.h"
00243 #endif /* HAL_CRYP_MODULE_ENABLED */
00244
00245 #ifdef HAL_DAC_MODULE_ENABLED
00246 #include "stm32g4xx_hal_dac.h"
00247 #endif /* HAL_DAC_MODULE_ENABLED */
00248
00249 #ifdef HAL_EXTI_MODULE_ENABLED
00250 #include "stm32g4xx_hal_exti.h"
00251 #endif /* HAL_EXTI_MODULE_ENABLED */
00252
00253 #ifdef HAL_FDCAN_MODULE_ENABLED
00254 #include "stm32g4xx_hal_fdcan.h"
00255 #endif /* HAL_FDCAN_MODULE_ENABLED */
00256
00257 #ifdef HAL_FLASH_MODULE_ENABLED
00258 #include "stm32g4xx_hal_flash.h"
00259 #endif /* HAL_FLASH_MODULE_ENABLED */
00260
00261 #ifdef HAL_FMAC_MODULE_ENABLED
00262 #include "stm32g4xx_hal_fmac.h"
00263 #endif /* HAL_FMAC_MODULE_ENABLED */
00264
00265 #ifdef HAL_HRTIM_MODULE_ENABLED
00266 #include "stm32g4xx_hal_hrtim.h"
00267 #endif /* HAL_HRTIM_MODULE_ENABLED */
00268
00269 #ifdef HAL_IRDA_MODULE_ENABLED
00270 #include "stm32g4xx_hal_irda.h"
00271 #endif /* HAL_IRDA_MODULE_ENABLED */
00272
00273 #ifdef HAL_IWDG_MODULE_ENABLED
00274 #include "stm32g4xx_hal_iwdg.h"
00275 #endif /* HAL_IWDG_MODULE_ENABLED */
00276
00277 #ifdef HAL_I2C_MODULE_ENABLED
00278 #include "stm32g4xx_hal_i2c.h"
00279 #endif /* HAL_I2C_MODULE_ENABLED */
00280
00281 #ifdef HAL_I2S_MODULE_ENABLED
00282 #include "stm32g4xx_hal_i2s.h"
00283 #endif /* HAL_I2S_MODULE_ENABLED */
00284
00285 #ifdef HAL_LPTIM_MODULE_ENABLED
00286 #include "stm32g4xx_hal_lptim.h"
00287 #endif /* HAL_LPTIM_MODULE_ENABLED */
00288
00289 #ifdef HAL_NAND_MODULE_ENABLED
00290 #include "stm32g4xx_hal_nand.h"
00291 #endif /* HAL_NAND_MODULE_ENABLED */
00292
00293 #ifdef HAL_NOR_MODULE_ENABLED
00294 #include "stm32g4xx_hal_nor.h"
00295 #endif /* HAL_NOR_MODULE_ENABLED */
00296
00297 #ifdef HAL_OPAMP_MODULE_ENABLED
00298 #include "stm32g4xx_hal_opamp.h"
00299 #endif /* HAL_OPAMP_MODULE_ENABLED */
00300
00301 #ifdef HAL_PCD_MODULE_ENABLED
00302 #include "stm32g4xx_hal_pcd.h"
00303 #endif /* HAL_PCD_MODULE_ENABLED */
00304
00305 #ifdef HAL_PWR_MODULE_ENABLED
00306 #include "stm32g4xx_hal_pwr.h"
00307 #endif /* HAL_PWR_MODULE_ENABLED */
00308
00309 #ifdef HAL_QSPI_MODULE_ENABLED
00310 #include "stm32g4xx_hal_qspi.h"
00311 #endif /* HAL_QSPI_MODULE_ENABLED */
00312
00313 #ifdef HAL_RNG_MODULE_ENABLED
00314 #include "stm32g4xx_hal_rng.h"
00315 #endif /* HAL_RNG_MODULE_ENABLED */
00316
00317 #ifdef HAL_RTC_MODULE_ENABLED
00318 #include "stm32g4xx_hal_rtc.h"
00319 #endif /* HAL_RTC_MODULE_ENABLED */
00320
00321 #ifdef HAL_SAI_MODULE_ENABLED
00322 #include "stm32g4xx_hal_sai.h"
00323 #endif /* HAL_SAI_MODULE_ENABLED */
00324
00325 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00326 #include "stm32g4xx_hal_smartcard.h"
00327 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00328
00329 #ifdef HAL_SMBUS_MODULE_ENABLED
00330 #include "stm32g4xx_hal_smbus.h"
00331 #endif /* HAL_SMBUS_MODULE_ENABLED */
00332
00333 #ifdef HAL_SPI_MODULE_ENABLED
00334 #include "stm32g4xx_hal_spi.h"
00335 #endif /* HAL_SPI_MODULE_ENABLED */
00336
00337 #ifdef HAL_SRAM_MODULE_ENABLED
00338 #include "stm32g4xx_hal_sram.h"
00339 #endif /* HAL_SRAM_MODULE_ENABLED */
00340
00341 #ifdef HAL_TIM_MODULE_ENABLED
00342 #include "stm32g4xx_hal_tim.h"
00343 #endif /* HAL_TIM_MODULE_ENABLED */
00344
00345 #ifdef HAL_UART_MODULE_ENABLED
00346 #include "stm32g4xx_hal_uart.h"
00347 #endif /* HAL_UART_MODULE_ENABLED */
00348
00349 #ifdef HAL_USART_MODULE_ENABLED
00350 #include "stm32g4xx_hal_usart.h"
00351 #endif /* HAL_USART_MODULE_ENABLED */
00352
00353 #ifdef HAL_WWDG_MODULE_ENABLED
00354 #include "stm32g4xx_hal_wwdg.h"
00355 #endif /* HAL_WWDG_MODULE_ENABLED */
00356
00357 /* Exported macro ------------------------------------------------------------*/
00358 #ifdef  USE_FULL_ASSERT
00359 /**
00360   * @brief  The assert_param macro is used for function's parameters check.
00361   * @param  expr: If expr is false, it calls assert_failed function
00362   *         which reports the name of the source file and the source
00363   *         line number of the call that failed.
00364   *         If expr is true, it returns no value.
00365   * @retval None
00366   */
00367 #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00368 /* Exported functions ------------------------------------------------------- */
00369 void assert_failed(uint8_t *file, uint32_t line);
00370 #else
00371 #define assert_param(expr) ((void)0U)
00372 #endif /* USE_FULL_ASSERT */
00373
00374 #ifdef __cplusplus
00375 }
00376 #endif
00377
00378 #endif /* STM32G4xx_HAL_CONF_H */
00379
00380
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cordic.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cordic.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cordic.c
00004   * @author  MCD Application Team
00005   * @brief   CORDIC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORDIC peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Callback functions
00011   *           + IRQ handler management
00012   *           + Peripheral State functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ================================================================================
00027             ##### How to use this driver #####
00028   ================================================================================
00029     [..]
00030       The CORDIC HAL driver can be used as follows:
00031
00032       (#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit():
00033          (++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE()
00034          (++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT())
00035              (+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority()
00036              (+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ()
00037              (+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler()
00038          (++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA())
00039              (+++) Enable the DMA2 interface clock using
00040                  __HAL_RCC_DMA2_CLK_ENABLE()
00041              (+++) Configure and enable two DMA channels one for managing data transfer from
00042                  memory to peripheral (input channel) and another channel for managing data
00043                  transfer from peripheral to memory (output channel)
00044              (+++) Associate the initialized DMA handle to the CORDIC DMA handle
00045                  using __HAL_LINKDMA()
00046              (+++) Configure the priority and enable the NVIC for the transfer complete
00047                  interrupt on the two DMA channels.
00048                  Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00049
00050       (#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function
00051          (++) resorts to HAL_CORDIC_MspInit() for low-level initialization,
00052
00053       (#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure().
00054           This function configures:
00055          (++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent,
00056               Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent,
00057               Natural log, Square root
00058          (++) Scaling factor: 1 to 2exp(-7)
00059          (++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits
00060               input data size (Q1.15 format)
00061          (++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits
00062               output data size (Q1.15 format)
00063          (++) Number of 32-bit write expected for one calculation: One 32-bits write
00064               or Two 32-bit write
00065          (++) Number of 32-bit read expected after one calculation: One 32-bits read
00066               or Two 32-bit read
00067          (++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision)
00068
00069       (#) Four processing (calculation) functions are available:
00070          (++) Polling mode: processing API is blocking function
00071               i.e. it processes the data and wait till the processing is finished
00072               API is HAL_CORDIC_Calculate
00073          (++) Polling Zero-overhead mode: processing API is blocking function
00074               i.e. it processes the data and wait till the processing is finished
00075               A bit faster than standard polling mode, but blocking also AHB bus
00076               API is HAL_CORDIC_CalculateZO
00077          (++) Interrupt mode: processing API is not blocking functions
00078               i.e. it processes the data under interrupt
00079               API is HAL_CORDIC_Calculate_IT
00080          (++) DMA mode: processing API is not blocking functions and the CPU is
00081               not used for data transfer,
00082               i.e. the data transfer is ensured by DMA
00083               API is HAL_CORDIC_Calculate_DMA
00084
00085       (#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function
00086          (++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization,
00087
00088   *** Callback registration ***
00089   =============================================
00090
00091   The compilation define  USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
00092   allows the user to configure dynamically the driver callbacks.
00093   Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
00094
00095   Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
00096     (+) ErrorCallback             : Error Callback.
00097     (+) CalculateCpltCallback     : Calculate complete Callback.
00098     (+) MspInitCallback           : CORDIC MspInit.
00099     (+) MspDeInitCallback         : CORDIC MspDeInit.
00100   This function takes as parameters the HAL peripheral handle, the Callback ID
00101   and a pointer to the user callback function.
00102
00103   Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
00104   weak function.
00105   HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00106   and the Callback ID.
00107   This function allows to reset following callbacks:
00108     (+) ErrorCallback             : Error Callback.
00109     (+) CalculateCpltCallback     : Calculate complete Callback.
00110     (+) MspInitCallback           : CORDIC MspInit.
00111     (+) MspDeInitCallback         : CORDIC MspDeInit.
00112
00113   By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
00114   all callbacks are set to the corresponding weak functions:
00115   examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
00116   Exception done for MspInit and MspDeInit functions that are
00117   reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
00118   these callbacks are null (not registered beforehand).
00119   if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
00120   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00121
00122   Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
00123   Exception done MspInit/MspDeInit that can be registered/unregistered
00124   in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
00125   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00126   In that case first register the MspInit/MspDeInit user callbacks
00127   using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
00128   or HAL_CORDIC_Init() function.
00129
00130   When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
00131   not defined, the callback registration feature is not available and all callbacks
00132   are set to the corresponding weak functions.
00133
00134   @endverbatim
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32g4xx_hal.h"
00140
00141 #if defined(CORDIC)
00142 #ifdef HAL_CORDIC_MODULE_ENABLED
00143
00144 /** @addtogroup STM32G4xx_HAL_Driver
00145   * @{
00146   */
00147
00148 /** @defgroup CORDIC CORDIC
00149   * @brief CORDIC HAL driver modules.
00150   * @{
00151   */
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /* Private macro -------------------------------------------------------------*/
00156 /* Private variables ---------------------------------------------------------*/
00157 /* Private function prototypes -----------------------------------------------*/
00158
00159 /** @defgroup CORDIC_Private_Functions CORDIC Private Functions
00160   * @{
00161   */
00162 static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff);
00163 static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
00164 static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
00165 static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
00166 static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported functions --------------------------------------------------------*/
00172
00173 /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
00174   * @{
00175   */
00176
00177 /** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions
00178   *  @brief    Initialization and Configuration functions.
00179   *
00180 @verbatim
00181   ==============================================================================
00182               ##### Initialization and de-initialization functions #####
00183   ==============================================================================
00184     [..]  This section provides functions allowing to:
00185       (+) Initialize the CORDIC peripheral and the associated handle
00186       (+) DeInitialize the CORDIC peripheral
00187       (+) Initialize the CORDIC MSP (MCU Specific Package)
00188       (+) De-Initialize the CORDIC MSP
00189
00190     [..]
00191
00192 @endverbatim
00193   * @{
00194   */
00195
00196 /**
00197   * @brief  Initialize the CORDIC peripheral and the associated handle.
00198   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure.
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic)
00202 {
00203   /* Check the CORDIC handle allocation */
00204   if (hcordic == NULL)
00205   {
00206     /* Return error status */
00207     return HAL_ERROR;
00208   }
00209
00210   /* Check the instance */
00211   assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
00212
00213 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00214   if (hcordic->State == HAL_CORDIC_STATE_RESET)
00215   {
00216     /* Allocate lock resource and initialize it */
00217     hcordic->Lock = HAL_UNLOCKED;
00218
00219     /* Reset callbacks to legacy functions */
00220     hcordic->ErrorCallback         = HAL_CORDIC_ErrorCallback;         /* Legacy weak ErrorCallback */
00221     hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; /* Legacy weak CalculateCpltCallback */
00222
00223     if (hcordic->MspInitCallback == NULL)
00224     {
00225       hcordic->MspInitCallback = HAL_CORDIC_MspInit;                   /* Legacy weak MspInit */
00226     }
00227
00228     /* Initialize the low level hardware */
00229     hcordic->MspInitCallback(hcordic);
00230   }
00231 #else
00232   if (hcordic->State == HAL_CORDIC_STATE_RESET)
00233   {
00234     /* Allocate lock resource and initialize it */
00235     hcordic->Lock = HAL_UNLOCKED;
00236
00237     /* Initialize the low level hardware */
00238     HAL_CORDIC_MspInit(hcordic);
00239   }
00240 #endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
00241
00242   /* Set CORDIC error code to none */
00243   hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00244
00245   /* Reset pInBuff and pOutBuff */
00246   hcordic->pInBuff = NULL;
00247   hcordic->pOutBuff = NULL;
00248
00249   /* Reset NbCalcToOrder and NbCalcToGet */
00250   hcordic->NbCalcToOrder = 0U;
00251   hcordic->NbCalcToGet = 0U;
00252
00253   /* Reset DMADirection */
00254   hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
00255
00256   /* Change CORDIC peripheral state */
00257   hcordic->State = HAL_CORDIC_STATE_READY;
00258
00259   /* Return function status */
00260   return HAL_OK;
00261 }
00262
00263 /**
00264   * @brief  DeInitialize the CORDIC peripheral.
00265   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure.
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic)
00269 {
00270   /* Check the CORDIC handle allocation */
00271   if (hcordic == NULL)
00272   {
00273     /* Return error status */
00274     return HAL_ERROR;
00275   }
00276
00277   /* Check the parameters */
00278   assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
00279
00280   /* Change CORDIC peripheral state */
00281   hcordic->State = HAL_CORDIC_STATE_BUSY;
00282
00283 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00284   if (hcordic->MspDeInitCallback == NULL)
00285   {
00286     hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
00287   }
00288
00289   /* De-Initialize the low level hardware */
00290   hcordic->MspDeInitCallback(hcordic);
00291 #else
00292   /* De-Initialize the low level hardware: CLOCK, NVIC, DMA */
00293   HAL_CORDIC_MspDeInit(hcordic);
00294 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00295
00296   /* Set CORDIC error code to none */
00297   hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00298
00299   /* Reset pInBuff and pOutBuff */
00300   hcordic->pInBuff = NULL;
00301   hcordic->pOutBuff = NULL;
00302
00303   /* Reset NbCalcToOrder and NbCalcToGet */
00304   hcordic->NbCalcToOrder = 0U;
00305   hcordic->NbCalcToGet = 0U;
00306
00307   /* Reset DMADirection */
00308   hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
00309
00310   /* Change CORDIC peripheral state */
00311   hcordic->State = HAL_CORDIC_STATE_RESET;
00312
00313   /* Reset Lock */
00314   hcordic->Lock = HAL_UNLOCKED;
00315
00316   /* Return function status */
00317   return HAL_OK;
00318 }
00319
00320 /**
00321   * @brief  Initialize the CORDIC MSP.
00322   * @param  hcordic CORDIC handle
00323   * @retval None
00324   */
00325 __weak void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic)
00326 {
00327   /* Prevent unused argument(s) compilation warning */
00328   UNUSED(hcordic);
00329
00330   /* NOTE : This function should not be modified, when the callback is needed,
00331             the HAL_CORDIC_MspInit can be implemented in the user file
00332    */
00333 }
00334
00335 /**
00336   * @brief  DeInitialize the CORDIC MSP.
00337   * @param  hcordic CORDIC handle
00338   * @retval None
00339   */
00340 __weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic)
00341 {
00342   /* Prevent unused argument(s) compilation warning */
00343   UNUSED(hcordic);
00344
00345   /* NOTE : This function should not be modified, when the callback is needed,
00346             the HAL_CORDIC_MspDeInit can be implemented in the user file
00347    */
00348 }
00349
00350 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00351 /**
00352   * @brief  Register a CORDIC CallBack.
00353   *         To be used instead of the weak predefined callback.
00354   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00355   *         the configuration information for CORDIC module
00356   * @param  CallbackID ID of the callback to be registered
00357   *         This parameter can be one of the following values:
00358   *           @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
00359   *           @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
00360   *           @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
00361   *           @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
00362   * @param  pCallback pointer to the Callback function
00363   * @retval HAL status
00364   */
00365 HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
00366                                               void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
00367 {
00368   HAL_StatusTypeDef status = HAL_OK;
00369
00370   if (pCallback == NULL)
00371   {
00372     /* Update the error code */
00373     hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00374
00375     /* Return error status */
00376     return HAL_ERROR;
00377   }
00378
00379   if (hcordic->State == HAL_CORDIC_STATE_READY)
00380   {
00381     switch (CallbackID)
00382     {
00383       case HAL_CORDIC_ERROR_CB_ID :
00384         hcordic->ErrorCallback = pCallback;
00385         break;
00386
00387       case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
00388         hcordic->CalculateCpltCallback = pCallback;
00389         break;
00390
00391       case HAL_CORDIC_MSPINIT_CB_ID :
00392         hcordic->MspInitCallback = pCallback;
00393         break;
00394
00395       case HAL_CORDIC_MSPDEINIT_CB_ID :
00396         hcordic->MspDeInitCallback = pCallback;
00397         break;
00398
00399       default :
00400         /* Update the error code */
00401         hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00402
00403         /* Return error status */
00404         status = HAL_ERROR;
00405         break;
00406     }
00407   }
00408   else if (hcordic->State == HAL_CORDIC_STATE_RESET)
00409   {
00410     switch (CallbackID)
00411     {
00412       case HAL_CORDIC_MSPINIT_CB_ID :
00413         hcordic->MspInitCallback = pCallback;
00414         break;
00415
00416       case HAL_CORDIC_MSPDEINIT_CB_ID :
00417         hcordic->MspDeInitCallback = pCallback;
00418         break;
00419
00420       default :
00421         /* Update the error code */
00422         hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00423
00424         /* Return error status */
00425         status = HAL_ERROR;
00426         break;
00427     }
00428   }
00429   else
00430   {
00431     /* Update the error code */
00432     hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00433
00434     /* Return error status */
00435     status = HAL_ERROR;
00436   }
00437
00438   return status;
00439 }
00440 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00441
00442 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00443 /**
00444   * @brief  Unregister a CORDIC CallBack.
00445   *         CORDIC callback is redirected to the weak predefined callback.
00446   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00447   *         the configuration information for CORDIC module
00448   * @param  CallbackID ID of the callback to be unregistered
00449   *         This parameter can be one of the following values:
00450   *           @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
00451   *           @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
00452   *           @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
00453   *           @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
00454   * @retval HAL status
00455   */
00456 HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
00457 {
00458   HAL_StatusTypeDef status = HAL_OK;
00459
00460   if (hcordic->State == HAL_CORDIC_STATE_READY)
00461   {
00462     switch (CallbackID)
00463     {
00464       case HAL_CORDIC_ERROR_CB_ID :
00465         hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback;
00466         break;
00467
00468       case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
00469         hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback;
00470         break;
00471
00472       case HAL_CORDIC_MSPINIT_CB_ID :
00473         hcordic->MspInitCallback = HAL_CORDIC_MspInit;
00474         break;
00475
00476       case HAL_CORDIC_MSPDEINIT_CB_ID :
00477         hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
00478         break;
00479
00480       default :
00481         /* Update the error code */
00482         hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00483
00484         /* Return error status */
00485         status = HAL_ERROR;
00486         break;
00487     }
00488   }
00489   else if (hcordic->State == HAL_CORDIC_STATE_RESET)
00490   {
00491     switch (CallbackID)
00492     {
00493       case HAL_CORDIC_MSPINIT_CB_ID :
00494         hcordic->MspInitCallback = HAL_CORDIC_MspInit;
00495         break;
00496
00497       case HAL_CORDIC_MSPDEINIT_CB_ID :
00498         hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
00499         break;
00500
00501       default :
00502         /* Update the error code */
00503         hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00504
00505         /* Return error status */
00506         status = HAL_ERROR;
00507         break;
00508     }
00509   }
00510   else
00511   {
00512     /* Update the error code */
00513     hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
00514
00515     /* Return error status */
00516     status = HAL_ERROR;
00517   }
00518
00519   return status;
00520 }
00521 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00522
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
00528   *  @brief    Control functions.
00529   *
00530 @verbatim
00531   ==============================================================================
00532                       ##### Peripheral Control functions #####
00533   ==============================================================================
00534     [..]  This section provides functions allowing to:
00535       (+) Configure the CORDIC peripheral: function, precision, scaling factor,
00536           number of input data and output data, size of input data and output data.
00537       (+) Calculate output data of CORDIC processing on input date, using the
00538           existing CORDIC configuration
00539     [..]  Four processing functions are available for calculation:
00540       (+) Polling mode
00541       (+) Polling mode, with Zero-Overhead register access
00542       (+) Interrupt mode
00543       (+) DMA mode
00544
00545 @endverbatim
00546   * @{
00547   */
00548
00549 /**
00550   * @brief  Configure the CORDIC processing according to the specified
00551             parameters in the CORDIC_ConfigTypeDef structure.
00552   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00553   *         the configuration information for CORDIC module
00554   * @param  sConfig pointer to a CORDIC_ConfigTypeDef structure that
00555   *         contains the CORDIC configuration information.
00556   * @retval HAL status
00557   */
00558 HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
00559 {
00560   HAL_StatusTypeDef status = HAL_OK;
00561
00562   /* Check the parameters */
00563   assert_param(IS_CORDIC_FUNCTION(sConfig->Function));
00564   assert_param(IS_CORDIC_PRECISION(sConfig->Precision));
00565   assert_param(IS_CORDIC_SCALE(sConfig->Scale));
00566   assert_param(IS_CORDIC_NBWRITE(sConfig->NbWrite));
00567   assert_param(IS_CORDIC_NBREAD(sConfig->NbRead));
00568   assert_param(IS_CORDIC_INSIZE(sConfig->InSize));
00569   assert_param(IS_CORDIC_OUTSIZE(sConfig->OutSize));
00570
00571   /* Check handle state is ready */
00572   if (hcordic->State == HAL_CORDIC_STATE_READY)
00573   {
00574     /* Apply all configuration parameters in CORDIC control register */
00575     MODIFY_REG(hcordic->Instance->CSR,                                                         \
00576                (CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |                    \
00577                 CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE), \
00578                (sConfig->Function | sConfig->Precision | sConfig->Scale |                      \
00579                 sConfig->NbWrite | sConfig->NbRead | sConfig->InSize | sConfig->OutSize));
00580   }
00581   else
00582   {
00583     /* Set CORDIC error code */
00584     hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
00585
00586     /* Return error status */
00587     status = HAL_ERROR;
00588   }
00589
00590   /* Return function status */
00591   return status;
00592 }
00593
00594 /**
00595   * @brief  Carry out data of CORDIC processing in polling mode,
00596   *         according to the existing CORDIC configuration.
00597   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00598   *         the configuration information for CORDIC module.
00599   * @param  pInBuff Pointer to buffer containing input data for CORDIC processing.
00600   * @param  pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
00601   * @param  NbCalc Number of CORDIC calculation to process.
00602   * @param  Timeout Specify Timeout value
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00606                                        uint32_t NbCalc, uint32_t Timeout)
00607 {
00608   uint32_t tickstart;
00609   uint32_t index;
00610   const int32_t *p_tmp_in_buff = pInBuff;
00611   int32_t *p_tmp_out_buff = pOutBuff;
00612
00613   /* Check parameters setting */
00614   if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
00615   {
00616     /* Update the error code */
00617     hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00618
00619     /* Return error status */
00620     return HAL_ERROR;
00621   }
00622
00623   /* Check handle state is ready */
00624   if (hcordic->State == HAL_CORDIC_STATE_READY)
00625   {
00626     /* Reset CORDIC error code */
00627     hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00628
00629     /* Change the CORDIC state */
00630     hcordic->State = HAL_CORDIC_STATE_BUSY;
00631
00632     /* Get tick */
00633     tickstart = HAL_GetTick();
00634
00635     /* Write of input data in Write Data register, and increment input buffer pointer */
00636     CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
00637
00638     /* Calculation is started.
00639        Provide next set of input data, until number of calculation is achieved */
00640     for (index = (NbCalc - 1U); index > 0U; index--)
00641     {
00642       /* Write of input data in Write Data register, and increment input buffer pointer */
00643       CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
00644
00645       /* Wait for RRDY flag to be raised */
00646       do
00647       {
00648         /* Check for the Timeout */
00649         if (Timeout != HAL_MAX_DELAY)
00650         {
00651           if ((HAL_GetTick() - tickstart) > Timeout)
00652           {
00653             /* Set CORDIC error code */
00654             hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
00655
00656             /* Change the CORDIC state */
00657             hcordic->State = HAL_CORDIC_STATE_READY;
00658
00659             /* Return function status */
00660             return HAL_ERROR;
00661           }
00662         }
00663       } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
00664
00665       /* Read output data from Read Data register, and increment output buffer pointer */
00666       CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
00667     }
00668
00669     /* Read output data from Read Data register, and increment output buffer pointer */
00670     CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
00671
00672     /* Change the CORDIC state */
00673     hcordic->State = HAL_CORDIC_STATE_READY;
00674
00675     /* Return function status */
00676     return HAL_OK;
00677   }
00678   else
00679   {
00680     /* Set CORDIC error code */
00681     hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
00682
00683     /* Return function status */
00684     return HAL_ERROR;
00685   }
00686 }
00687
00688 /**
00689   * @brief  Carry out data of CORDIC processing in Zero-Overhead mode (output data being read
00690   *         soon as input data are written), according to the existing CORDIC configuration.
00691   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00692   *         the configuration information for CORDIC module.
00693   * @param  pInBuff Pointer to buffer containing input data for CORDIC processing.
00694   * @param  pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
00695   * @param  NbCalc Number of CORDIC calculation to process.
00696   * @param  Timeout Specify Timeout value
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00700                                          uint32_t NbCalc, uint32_t Timeout)
00701 {
00702   uint32_t tickstart;
00703   uint32_t index;
00704   const int32_t *p_tmp_in_buff = pInBuff;
00705   int32_t *p_tmp_out_buff = pOutBuff;
00706
00707   /* Check parameters setting */
00708   if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
00709   {
00710     /* Update the error code */
00711     hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00712
00713     /* Return error status */
00714     return HAL_ERROR;
00715   }
00716
00717   /* Check handle state is ready */
00718   if (hcordic->State == HAL_CORDIC_STATE_READY)
00719   {
00720     /* Reset CORDIC error code */
00721     hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00722
00723     /* Change the CORDIC state */
00724     hcordic->State = HAL_CORDIC_STATE_BUSY;
00725
00726     /* Get tick */
00727     tickstart = HAL_GetTick();
00728
00729     /* Write of input data in Write Data register, and increment input buffer pointer */
00730     CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
00731
00732     /* Calculation is started.
00733        Provide next set of input data, until number of calculation is achieved */
00734     for (index = (NbCalc - 1U); index > 0U; index--)
00735     {
00736       /* Write of input data in Write Data register, and increment input buffer pointer */
00737       CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
00738
00739       /* Read output data from Read Data register, and increment output buffer pointer
00740          The reading is performed in Zero-Overhead mode:
00741          reading is ordered immediately without waiting result ready flag */
00742       CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
00743
00744       /* Check for the Timeout */
00745       if (Timeout != HAL_MAX_DELAY)
00746       {
00747         if ((HAL_GetTick() - tickstart) > Timeout)
00748         {
00749           /* Set CORDIC error code */
00750           hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
00751
00752           /* Change the CORDIC state */
00753           hcordic->State = HAL_CORDIC_STATE_READY;
00754
00755           /* Return function status */
00756           return HAL_ERROR;
00757         }
00758       }
00759     }
00760
00761     /* Read output data from Read Data register, and increment output buffer pointer
00762        The reading is performed in Zero-Overhead mode:
00763        reading is ordered immediately without waiting result ready flag */
00764     CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
00765
00766     /* Change the CORDIC state */
00767     hcordic->State = HAL_CORDIC_STATE_READY;
00768
00769     /* Return function status */
00770     return HAL_OK;
00771   }
00772   else
00773   {
00774     /* Set CORDIC error code */
00775     hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
00776
00777     /* Return function status */
00778     return HAL_ERROR;
00779   }
00780 }
00781
00782 /**
00783   * @brief  Carry out data of CORDIC processing in interrupt mode,
00784   *         according to the existing CORDIC configuration.
00785   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00786   *         the configuration information for CORDIC module.
00787   * @param  pInBuff Pointer to buffer containing input data for CORDIC processing.
00788   * @param  pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
00789   * @param  NbCalc Number of CORDIC calculation to process.
00790   * @retval HAL status
00791   */
00792 HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00793                                           uint32_t NbCalc)
00794 {
00795   const int32_t *tmp_pInBuff = pInBuff;
00796
00797   /* Check parameters setting */
00798   if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
00799   {
00800     /* Update the error code */
00801     hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00802
00803     /* Return error status */
00804     return HAL_ERROR;
00805   }
00806
00807   /* Check handle state is ready */
00808   if (hcordic->State == HAL_CORDIC_STATE_READY)
00809   {
00810     /* Reset CORDIC error code */
00811     hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00812
00813     /* Change the CORDIC state */
00814     hcordic->State = HAL_CORDIC_STATE_BUSY;
00815
00816     /* Store the buffers addresses and number of calculations in handle,
00817        provisioning initial write of input data that will be done */
00818     if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
00819     {
00820       /* Two writes of input data are expected */
00821       tmp_pInBuff++;
00822       tmp_pInBuff++;
00823     }
00824     else
00825     {
00826       /* One write of input data is expected */
00827       tmp_pInBuff++;
00828     }
00829     hcordic->pInBuff = tmp_pInBuff;
00830     hcordic->pOutBuff = pOutBuff;
00831     hcordic->NbCalcToOrder = NbCalc - 1U;
00832     hcordic->NbCalcToGet = NbCalc;
00833
00834     /* Enable Result Ready Interrupt */
00835     __HAL_CORDIC_ENABLE_IT(hcordic, CORDIC_IT_IEN);
00836
00837     /* Set back pointer to start of input data buffer */
00838     tmp_pInBuff = pInBuff;
00839
00840     /* Initiate the processing by providing input data
00841        in the Write Data register */
00842     WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
00843
00844     /* Check if second write of input data is expected */
00845     if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
00846     {
00847       /* Increment pointer to input data */
00848       tmp_pInBuff++;
00849
00850       /* Perform second write of input data */
00851       WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
00852     }
00853
00854     /* Return function status */
00855     return HAL_OK;
00856   }
00857   else
00858   {
00859     /* Set CORDIC error code */
00860     hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
00861
00862     /* Return function status */
00863     return HAL_ERROR;
00864   }
00865 }
00866
00867 /**
00868   * @brief  Carry out input and/or output data of CORDIC processing in DMA mode,
00869   *         according to the existing CORDIC configuration.
00870   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
00871   *         the configuration information for CORDIC module.
00872   * @param  pInBuff Pointer to buffer containing input data for CORDIC processing.
00873   * @param  pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
00874   * @param  NbCalc Number of CORDIC calculation to process.
00875   * @param  DMADirection Direction of DMA transfers.
00876   *         This parameter can be one of the following values:
00877   *            @arg @ref CORDIC_DMA_Direction CORDIC DMA direction
00878   * @note   pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can
00879   *         be set to NULL value in this case.
00880   * @note   pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct
00881   *         DMA transfer to and from the Peripheral.
00882   * @retval HAL status
00883   */
00884 HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00885                                            uint32_t NbCalc, uint32_t DMADirection)
00886 {
00887   uint32_t sizeinbuff;
00888   uint32_t sizeoutbuff;
00889
00890   /* Check the parameters */
00891   assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
00892
00893   /* Check parameters setting */
00894   if (NbCalc == 0U)
00895   {
00896     /* Update the error code */
00897     hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00898
00899     /* Return error status */
00900     return HAL_ERROR;
00901   }
00902
00903   /* Check if CORDIC DMA direction "Out" is requested */
00904   if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
00905   {
00906     /* Check parameters setting */
00907     if (pOutBuff == NULL)
00908     {
00909       /* Update the error code */
00910       hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00911
00912       /* Return error status */
00913       return HAL_ERROR;
00914     }
00915   }
00916
00917   /* Check if CORDIC DMA direction "In" is requested */
00918   if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
00919   {
00920     /* Check parameters setting */
00921     if (pInBuff == NULL)
00922     {
00923       /* Update the error code */
00924       hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
00925
00926       /* Return error status */
00927       return HAL_ERROR;
00928     }
00929   }
00930
00931   if (hcordic->State == HAL_CORDIC_STATE_READY)
00932   {
00933     /* Reset CORDIC error code */
00934     hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
00935
00936     /* Change the CORDIC state */
00937     hcordic->State = HAL_CORDIC_STATE_BUSY;
00938
00939     /* Get DMA direction */
00940     hcordic->DMADirection = DMADirection;
00941
00942     /* Check if CORDIC DMA direction "Out" is requested */
00943     if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
00944     {
00945       /* Set the CORDIC DMA transfer complete callback */
00946       hcordic->hdmaOut->XferCpltCallback = CORDIC_DMAOutCplt;
00947       /* Set the DMA error callback */
00948       hcordic->hdmaOut->XferErrorCallback = CORDIC_DMAError;
00949
00950       /* Check number of output data at each calculation,
00951          to retrieve the size of output data buffer */
00952       if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
00953       {
00954         sizeoutbuff = 2U * NbCalc;
00955       }
00956       else
00957       {
00958         sizeoutbuff = NbCalc;
00959       }
00960
00961       /* Enable the DMA stream managing CORDIC output data read */
00962       if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff)
00963           != HAL_OK)
00964       {
00965         /* Update the error code */
00966         hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
00967
00968         /* Return error status */
00969         return HAL_ERROR;
00970       }
00971
00972       /* Enable output data Read DMA requests */
00973       SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
00974     }
00975
00976     /* Check if CORDIC DMA direction "In" is requested */
00977     if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
00978     {
00979       /* Set the CORDIC DMA transfer complete callback */
00980       hcordic->hdmaIn->XferCpltCallback = CORDIC_DMAInCplt;
00981       /* Set the DMA error callback */
00982       hcordic->hdmaIn->XferErrorCallback = CORDIC_DMAError;
00983
00984       /* Check number of input data expected for each calculation,
00985          to retrieve the size of input data buffer */
00986       if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
00987       {
00988         sizeinbuff = 2U * NbCalc;
00989       }
00990       else
00991       {
00992         sizeinbuff = NbCalc;
00993       }
00994
00995       /* Enable the DMA stream managing CORDIC input data write */
00996       if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff)
00997           != HAL_OK)
00998       {
00999         /* Update the error code */
01000         hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
01001
01002         /* Return error status */
01003         return HAL_ERROR;
01004       }
01005
01006       /* Enable input data Write DMA request */
01007       SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
01008     }
01009
01010     /* Return function status */
01011     return HAL_OK;
01012   }
01013   else
01014   {
01015     /* Set CORDIC error code */
01016     hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
01017
01018     /* Return function status */
01019     return HAL_ERROR;
01020   }
01021 }
01022
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
01028   *  @brief    Callback functions.
01029   *
01030 @verbatim
01031   ==============================================================================
01032                       ##### Callback functions  #####
01033   ==============================================================================
01034     [..]  This section provides Interruption and DMA callback functions:
01035       (+) DMA or Interrupt calculate complete
01036       (+) DMA or Interrupt error
01037
01038 @endverbatim
01039   * @{
01040   */
01041
01042 /**
01043   * @brief  CORDIC error callback.
01044   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01045   *         the configuration information for CORDIC module
01046   * @retval None
01047   */
01048 __weak void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic)
01049 {
01050   /* Prevent unused argument(s) compilation warning */
01051   UNUSED(hcordic);
01052
01053   /* NOTE : This function should not be modified; when the callback is needed,
01054             the HAL_CORDIC_ErrorCallback can be implemented in the user file
01055    */
01056 }
01057
01058 /**
01059   * @brief  CORDIC calculate complete callback.
01060   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01061   *         the configuration information for CORDIC module
01062   * @retval None
01063   */
01064 __weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic)
01065 {
01066   /* Prevent unused argument(s) compilation warning */
01067   UNUSED(hcordic);
01068
01069   /* NOTE : This function should not be modified; when the callback is needed,
01070             the HAL_CORDIC_CalculateCpltCallback can be implemented in the user file
01071    */
01072 }
01073
01074 /**
01075   * @}
01076   */
01077
01078 /** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
01079   *  @brief    IRQ handler.
01080   *
01081 @verbatim
01082   ==============================================================================
01083                 ##### IRQ handler management #####
01084   ==============================================================================
01085 [..]  This section provides IRQ handler function.
01086
01087 @endverbatim
01088   * @{
01089   */
01090
01091 /**
01092   * @brief  Handle CORDIC interrupt request.
01093   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01094   *         the configuration information for CORDIC module
01095   * @retval None
01096   */
01097 void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
01098 {
01099   /* Check if calculation complete interrupt is enabled and if result ready
01100      flag is raised */
01101   if (__HAL_CORDIC_GET_IT_SOURCE(hcordic, CORDIC_IT_IEN) != 0U)
01102   {
01103     if (__HAL_CORDIC_GET_FLAG(hcordic, CORDIC_FLAG_RRDY) != 0U)
01104     {
01105       /* Decrement number of calculations to get */
01106       hcordic->NbCalcToGet--;
01107
01108       /* Read output data from Read Data register, and increment output buffer pointer */
01109       CORDIC_ReadOutDataIncrementPtr(hcordic, &(hcordic->pOutBuff));
01110
01111       /* Check if calculations are still to be ordered */
01112       if (hcordic->NbCalcToOrder > 0U)
01113       {
01114         /* Decrement number of calculations to order */
01115         hcordic->NbCalcToOrder--;
01116
01117         /* Continue the processing by providing another write of input data
01118            in the Write Data register, and increment input buffer pointer */
01119         CORDIC_WriteInDataIncrementPtr(hcordic, &(hcordic->pInBuff));
01120       }
01121
01122       /* Check if all calculations results are got */
01123       if (hcordic->NbCalcToGet == 0U)
01124       {
01125         /* Disable Result Ready Interrupt */
01126         __HAL_CORDIC_DISABLE_IT(hcordic, CORDIC_IT_IEN);
01127
01128         /* Change the CORDIC state */
01129         hcordic->State = HAL_CORDIC_STATE_READY;
01130
01131         /* Call calculation complete callback */
01132 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
01133         /*Call registered callback*/
01134         hcordic->CalculateCpltCallback(hcordic);
01135 #else
01136         /*Call legacy weak callback*/
01137         HAL_CORDIC_CalculateCpltCallback(hcordic);
01138 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
01139       }
01140     }
01141   }
01142 }
01143
01144 /**
01145   * @}
01146   */
01147
01148 /** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
01149   *  @brief   Peripheral State functions.
01150   *
01151 @verbatim
01152   ==============================================================================
01153                       ##### Peripheral State functions #####
01154   ==============================================================================
01155     [..]
01156     This subsection permits to get in run-time the status of the peripheral.
01157
01158 @endverbatim
01159   * @{
01160   */
01161
01162 /**
01163   * @brief  Return the CORDIC handle state.
01164   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01165   *         the configuration information for CORDIC module
01166   * @retval HAL state
01167   */
01168 HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic)
01169 {
01170   /* Return CORDIC handle state */
01171   return hcordic->State;
01172 }
01173
01174 /**
01175   * @brief  Return the CORDIC peripheral error.
01176   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01177   *         the configuration information for CORDIC module
01178   * @note   The returned error is a bit-map combination of possible errors
01179   * @retval Error bit-map
01180   */
01181 uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic)
01182 {
01183   /* Return CORDIC error code */
01184   return hcordic->ErrorCode;
01185 }
01186
01187 /**
01188   * @}
01189   */
01190
01191 /**
01192   * @}
01193   */
01194
01195 /** @addtogroup CORDIC_Private_Functions
01196   * @{
01197   */
01198
01199 /**
01200   * @brief  Write input data for CORDIC processing, and increment input buffer pointer.
01201   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01202   *         the configuration information for CORDIC module.
01203   * @param  ppInBuff Pointer to pointer to input buffer.
01204   * @retval none
01205   */
01206 static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
01207 {
01208   /* First write of input data in the Write Data register */
01209   WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
01210
01211   /* Increment input data pointer */
01212   (*ppInBuff)++;
01213
01214   /* Check if second write of input data is expected */
01215   if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
01216   {
01217     /* Second write of input data in the Write Data register */
01218     WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
01219
01220     /* Increment input data pointer */
01221     (*ppInBuff)++;
01222   }
01223 }
01224
01225 /**
01226   * @brief  Read output data of CORDIC processing, and increment output buffer pointer.
01227   * @param  hcordic pointer to a CORDIC_HandleTypeDef structure that contains
01228   *         the configuration information for CORDIC module.
01229   * @param  ppOutBuff Pointer to pointer to output buffer.
01230   * @retval none
01231   */
01232 static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
01233 {
01234   /* First read of output data from the Read Data register */
01235   **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
01236
01237   /* Increment output data pointer */
01238   (*ppOutBuff)++;
01239
01240   /* Check if second read of output data is expected */
01241   if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
01242   {
01243     /* Second read of output data from the Read Data register */
01244     **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
01245
01246     /* Increment output data pointer */
01247     (*ppOutBuff)++;
01248   }
01249 }
01250
01251 /**
01252   * @brief  DMA CORDIC Input Data process complete callback.
01253   * @param  hdma DMA handle.
01254   * @retval None
01255   */
01256 static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
01257 {
01258   CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01259
01260   /* Disable the DMA transfer for input request */
01261   CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
01262
01263   /* Check if DMA direction is CORDIC Input only (no DMA for CORDIC Output) */
01264   if (hcordic->DMADirection == CORDIC_DMA_DIR_IN)
01265   {
01266     /* Change the CORDIC DMA direction to none */
01267     hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
01268
01269     /* Change the CORDIC state to ready */
01270     hcordic->State = HAL_CORDIC_STATE_READY;
01271
01272     /* Call calculation complete callback */
01273 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
01274     /*Call registered callback*/
01275     hcordic->CalculateCpltCallback(hcordic);
01276 #else
01277     /*Call legacy weak callback*/
01278     HAL_CORDIC_CalculateCpltCallback(hcordic);
01279 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
01280   }
01281 }
01282
01283 /**
01284   * @brief  DMA CORDIC Output Data process complete callback.
01285   * @param  hdma DMA handle.
01286   * @retval None
01287   */
01288 static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
01289 {
01290   CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01291
01292   /* Disable the DMA transfer for output request */
01293   CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
01294
01295   /* Change the CORDIC DMA direction to none */
01296   hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
01297
01298   /* Change the CORDIC state to ready */
01299   hcordic->State = HAL_CORDIC_STATE_READY;
01300
01301   /* Call calculation complete callback */
01302 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
01303   /*Call registered callback*/
01304   hcordic->CalculateCpltCallback(hcordic);
01305 #else
01306   /*Call legacy weak callback*/
01307   HAL_CORDIC_CalculateCpltCallback(hcordic);
01308 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
01309 }
01310
01311 /**
01312   * @brief  DMA CORDIC communication error callback.
01313   * @param  hdma DMA handle.
01314   * @retval None
01315   */
01316 static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
01317 {
01318   CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01319
01320   /* Set CORDIC handle state to error */
01321   hcordic->State = HAL_CORDIC_STATE_READY;
01322
01323   /* Set CORDIC handle error code to DMA error */
01324   hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
01325
01326   /* Call user callback */
01327 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
01328   /*Call registered callback*/
01329   hcordic->ErrorCallback(hcordic);
01330 #else
01331   /*Call legacy weak callback*/
01332   HAL_CORDIC_ErrorCallback(hcordic);
01333 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
01334 }
01335
01336 /**
01337   * @}
01338   */
01339
01340 /**
01341   * @}
01342   */
01343
01344 /**
01345   * @}
01346   */
01347
01348 #endif /* HAL_CORDIC_MODULE_ENABLED */
01349 #endif /* CORDIC */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cordic.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cordic.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cordic.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the CORDIC firmware
00006   *          library.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * Copyright (c) 2019 STMicroelectronics.
00011   * All rights reserved.
00012   *
00013   * This software is licensed under terms that can be found in the LICENSE file
00014   * in the root directory of this software component.
00015   * If no LICENSE file comes with this software, it is provided AS-IS.
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32G4xx_HAL_CORDIC_H
00022 #define STM32G4xx_HAL_CORDIC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32g4xx_hal_def.h"
00030
00031 #if defined(CORDIC)
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup CORDIC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup CORDIC_Exported_Types CORDIC Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  CORDIC HAL State Structure definition
00047   */
00048 typedef enum
00049 {
00050   HAL_CORDIC_STATE_RESET     = 0x00U,  /*!< CORDIC not yet initialized or disabled */
00051   HAL_CORDIC_STATE_READY     = 0x01U,  /*!< CORDIC initialized and ready for use   */
00052   HAL_CORDIC_STATE_BUSY      = 0x02U,  /*!< CORDIC internal process is ongoing     */
00053   HAL_CORDIC_STATE_ERROR     = 0x03U   /*!< CORDIC error state                     */
00054 } HAL_CORDIC_StateTypeDef;
00055
00056 /**
00057   * @brief  CORDIC Handle Structure definition
00058   */
00059 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00060 typedef struct __CORDIC_HandleTypeDef
00061 #else
00062 typedef struct
00063 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00064 {
00065   CORDIC_TypeDef                *Instance;   /*!< Register base address */
00066
00067   const int32_t                 *pInBuff;    /*!< Pointer to CORDIC input data buffer */
00068
00069   int32_t                       *pOutBuff;   /*!< Pointer to CORDIC output data buffer */
00070
00071   uint32_t                      NbCalcToOrder; /*!< Remaining number of calculation to order */
00072
00073   uint32_t                      NbCalcToGet; /*!< Remaining number of calculation result to get */
00074
00075   uint32_t                      DMADirection; /*!< Direction of CORDIC DMA transfers */
00076
00077   DMA_HandleTypeDef             *hdmaIn;     /*!< CORDIC peripheral input data DMA handle parameters */
00078
00079   DMA_HandleTypeDef             *hdmaOut;    /*!< CORDIC peripheral output data DMA handle parameters */
00080
00081   HAL_LockTypeDef               Lock;        /*!< CORDIC locking object */
00082
00083   __IO HAL_CORDIC_StateTypeDef  State;       /*!< CORDIC state */
00084
00085   __IO uint32_t                 ErrorCode;   /*!< CORDIC peripheral error code
00086                                                   This parameter can be a value of @ref CORDIC_Error_Code */
00087
00088 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00089   void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic);          /*!< CORDIC error callback */
00090   void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic);  /*!< CORDIC calculate complete callback */
00091
00092   void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic);        /*!< CORDIC Msp Init callback */
00093   void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic);      /*!< CORDIC Msp DeInit callback */
00094
00095 #endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
00096
00097 } CORDIC_HandleTypeDef;
00098
00099 /**
00100   * @brief  CORDIC Config Structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t   Function;     /*!< Function
00105                                 This parameter can be a value of @ref CORDIC_Function */
00106
00107   uint32_t   Scale;        /*!< Scaling factor
00108                                 This parameter can be a value of @ref CORDIC_Scale */
00109
00110   uint32_t   InSize;       /*!< Width of input data
00111                                 This parameter can be a value of @ref CORDIC_In_Size */
00112
00113   uint32_t   OutSize;      /*!< Width of output data
00114                                 This parameter can be a value of @ref CORDIC_Out_Size */
00115
00116   uint32_t   NbWrite;      /*!< Number of 32-bit write expected for one calculation
00117                                 This parameter can be a value of @ref CORDIC_Nb_Write */
00118
00119   uint32_t   NbRead;       /*!< Number of 32-bit read expected after one calculation
00120                                 This parameter can be a value of @ref CORDIC_Nb_Read */
00121
00122   uint32_t   Precision;    /*!< Number of cycles for calculation
00123                                 This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
00124
00125 } CORDIC_ConfigTypeDef;
00126
00127 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00128 /**
00129   * @brief  HAL CORDIC Callback ID enumeration definition
00130   */
00131 typedef enum
00132 {
00133   HAL_CORDIC_ERROR_CB_ID             = 0x00U,    /*!< CORDIC error callback ID */
00134   HAL_CORDIC_CALCULATE_CPLT_CB_ID    = 0x01U,    /*!< CORDIC calculate complete callback ID */
00135
00136   HAL_CORDIC_MSPINIT_CB_ID           = 0x02U,    /*!< CORDIC MspInit callback ID */
00137   HAL_CORDIC_MSPDEINIT_CB_ID         = 0x03U,    /*!< CORDIC MspDeInit callback ID */
00138
00139 } HAL_CORDIC_CallbackIDTypeDef;
00140
00141 /**
00142   * @brief  HAL CORDIC Callback pointer definition
00143   */
00144 typedef  void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic);  /*!< pointer to a CORDIC callback function */
00145
00146 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00147
00148 /**
00149   * @}
00150   */
00151
00152
00153 /* Exported constants --------------------------------------------------------*/
00154 /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
00155   * @{
00156   */
00157
00158 /** @defgroup CORDIC_Error_Code CORDIC Error code
00159   * @{
00160   */
00161 #define HAL_CORDIC_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error                */
00162 #define HAL_CORDIC_ERROR_PARAM             ((uint32_t)0x00000001U)   /*!< Wrong parameter error   */
00163 #define HAL_CORDIC_ERROR_NOT_READY         ((uint32_t)0x00000002U)   /*!< Peripheral not ready    */
00164 #define HAL_CORDIC_ERROR_TIMEOUT           ((uint32_t)0x00000004U)   /*!< Timeout error           */
00165 #define HAL_CORDIC_ERROR_DMA               ((uint32_t)0x00000008U)   /*!< DMA error               */
00166 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00167 #define HAL_CORDIC_ERROR_INVALID_CALLBACK  ((uint32_t)0x00000010U)   /*!< Invalid Callback error  */
00168 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup CORDIC_Function CORDIC Function
00174   * @{
00175   */
00176 #define CORDIC_FUNCTION_COSINE      (0x00000000U)                                                          /*!< Cosine */
00177 #define CORDIC_FUNCTION_SINE        ((uint32_t)(CORDIC_CSR_FUNC_0))                                        /*!< Sine */
00178 #define CORDIC_FUNCTION_PHASE       ((uint32_t)(CORDIC_CSR_FUNC_1))                                        /*!< Phase */
00179 #define CORDIC_FUNCTION_MODULUS     ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))                    /*!< Modulus */
00180 #define CORDIC_FUNCTION_ARCTANGENT  ((uint32_t)(CORDIC_CSR_FUNC_2))                                        /*!< Arctangent */
00181 #define CORDIC_FUNCTION_HCOSINE     ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))                    /*!< Hyperbolic Cosine */
00182 #define CORDIC_FUNCTION_HSINE       ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))                    /*!< Hyperbolic Sine */
00183 #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
00184 #define CORDIC_FUNCTION_NATURALLOG  ((uint32_t)(CORDIC_CSR_FUNC_3))                                        /*!< Natural Logarithm */
00185 #define CORDIC_FUNCTION_SQUAREROOT  ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))                    /*!< Square Root */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
00191   * @{
00192   */
00193 /* Note: 1 cycle corresponds to 4 algorithm iterations */
00194 #define CORDIC_PRECISION_1CYCLE     ((uint32_t)(CORDIC_CSR_PRECISION_0))
00195 #define CORDIC_PRECISION_2CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_1))
00196 #define CORDIC_PRECISION_3CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00197 #define CORDIC_PRECISION_4CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_2))
00198 #define CORDIC_PRECISION_5CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
00199 #define CORDIC_PRECISION_6CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
00200 #define CORDIC_PRECISION_7CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_2\
00201                                                 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00202 #define CORDIC_PRECISION_8CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_3))
00203 #define CORDIC_PRECISION_9CYCLES    ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
00204 #define CORDIC_PRECISION_10CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
00205 #define CORDIC_PRECISION_11CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3\
00206                                                 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00207 #define CORDIC_PRECISION_12CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
00208 #define CORDIC_PRECISION_13CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3\
00209                                                 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
00210 #define CORDIC_PRECISION_14CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3\
00211                                                 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
00212 #define CORDIC_PRECISION_15CYCLES   ((uint32_t)(CORDIC_CSR_PRECISION_3\
00213                                                 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
00214                                                 |CORDIC_CSR_PRECISION_0))
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup CORDIC_Scale CORDIC Scaling factor
00220   * @{
00221   */
00222 /* Scale factor value 'n' implies that the input data have been multiplied
00223    by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
00224 #define CORDIC_SCALE_0              (0x00000000U)
00225 #define CORDIC_SCALE_1              ((uint32_t)(CORDIC_CSR_SCALE_0))
00226 #define CORDIC_SCALE_2              ((uint32_t)(CORDIC_CSR_SCALE_1))
00227 #define CORDIC_SCALE_3              ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
00228 #define CORDIC_SCALE_4              ((uint32_t)(CORDIC_CSR_SCALE_2))
00229 #define CORDIC_SCALE_5              ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
00230 #define CORDIC_SCALE_6              ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
00231 #define CORDIC_SCALE_7              ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
00237   * @{
00238   */
00239 #define CORDIC_IT_IEN              CORDIC_CSR_IEN            /*!< Result ready interrupt enable */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup CORDIC_DMAR DMA Read Request Enable bit
00245   * @{
00246   */
00247 #define CORDIC_DMA_REN             CORDIC_CSR_DMAREN         /*!< DMA Read requests enable */
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CORDIC_DMAW DMA Write Request Enable bit
00253   * @{
00254   */
00255 #define CORDIC_DMA_WEN             CORDIC_CSR_DMAWEN         /*!< DMA Write channel enable */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
00261   * @{
00262   */
00263 #define CORDIC_NBWRITE_1           (0x00000000U)             /*!< One 32-bits write containing either only one
00264                                                                   32-bit data input (Q1.31 format), or two 16-bit
00265                                                                   data input (Q1.15 format) packed in one 32 bits
00266                                                                   Data */
00267 #define CORDIC_NBWRITE_2           CORDIC_CSR_NARGS          /*!< Two 32-bit write containing two 32-bits data input
00268                                                                   (Q1.31 format) */
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
00274   * @{
00275   */
00276 #define CORDIC_NBREAD_1            (0x00000000U)             /*!< One 32-bits read containing either only one
00277                                                                   32-bit data output (Q1.31 format), or two 16-bit
00278                                                                   data output (Q1.15 format) packed in one 32 bits
00279                                                                   Data */
00280 #define CORDIC_NBREAD_2            CORDIC_CSR_NRES           /*!< Two 32-bit Data containing two 32-bits data output
00281                                                                   (Q1.31 format) */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup CORDIC_In_Size CORDIC input data size
00287   * @{
00288   */
00289 #define CORDIC_INSIZE_32BITS       (0x00000000U)             /*!< 32 bits input data size (Q1.31 format) */
00290 #define CORDIC_INSIZE_16BITS       CORDIC_CSR_ARGSIZE        /*!< 16 bits input data size (Q1.15 format) */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup CORDIC_Out_Size CORDIC Results Size
00296   * @{
00297   */
00298 #define CORDIC_OUTSIZE_32BITS      (0x00000000U)             /*!< 32 bits output data size (Q1.31 format) */
00299 #define CORDIC_OUTSIZE_16BITS      CORDIC_CSR_RESSIZE        /*!< 16 bits output data size (Q1.15 format) */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup CORDIC_Flags  CORDIC status flags
00305   * @{
00306   */
00307 #define CORDIC_FLAG_RRDY           CORDIC_CSR_RRDY           /*!< Result Ready Flag */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
00313   * @{
00314   */
00315 #define CORDIC_DMA_DIR_NONE        ((uint32_t)0x00000000U)   /*!< DMA direction : none */
00316 #define CORDIC_DMA_DIR_IN          ((uint32_t)0x00000001U)   /*!< DMA direction : Input of CORDIC */
00317 #define CORDIC_DMA_DIR_OUT         ((uint32_t)0x00000002U)   /*!< DMA direction : Output of CORDIC */
00318 #define CORDIC_DMA_DIR_IN_OUT      ((uint32_t)0x00000003U)   /*!< DMA direction : Input and Output of CORDIC */
00319 /**
00320   * @}
00321   */
00322
00323 /**
00324   * @}
00325   */
00326
00327
00328 /* Exported macro ------------------------------------------------------------*/
00329 /** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
00330   * @{
00331   */
00332
00333 /** @brief  Reset CORDIC handle state.
00334   * @param  __HANDLE__ CORDIC handle
00335   * @retval None
00336   */
00337 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00338 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
00339                                                         (__HANDLE__)->State = HAL_CORDIC_STATE_RESET;   \
00340                                                         (__HANDLE__)->MspInitCallback = NULL;           \
00341                                                         (__HANDLE__)->MspDeInitCallback = NULL;         \
00342                                                       } while(0)
00343 #else
00344 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
00345 #endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
00346
00347 /**
00348   * @brief  Enable the CORDIC interrupt when result is ready
00349   * @param  __HANDLE__ CORDIC handle.
00350   * @param  __INTERRUPT__ CORDIC Interrupt.
00351   *         This parameter can be one of the following values:
00352   *            @arg @ref CORDIC_IT_IEN Enable Interrupt
00353   * @retval None
00354   */
00355 #define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                     \
00356   (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
00357
00358 /**
00359   * @brief  Disable the CORDIC interrupt
00360   * @param  __HANDLE__ CORDIC handle.
00361   * @param  __INTERRUPT__ CORDIC Interrupt.
00362   *         This parameter can be one of the following values:
00363   *            @arg @ref CORDIC_IT_IEN Enable Interrupt
00364   * @retval None
00365   */
00366 #define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                    \
00367   (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
00368
00369 /** @brief  Check whether the specified CORDIC interrupt occurred or not.
00370             Dummy macro as no interrupt status flag.
00371   * @param  __HANDLE__ CORDIC handle.
00372   * @param  __INTERRUPT__ CORDIC interrupt to check
00373   * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
00374   */
00375 #define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__)     /* Dummy macro */
00376
00377 /** @brief  Clear specified CORDIC interrupt status. Dummy macro as no
00378             interrupt status flag.
00379   * @param  __HANDLE__ CORDIC handle.
00380   * @param  __INTERRUPT__ CORDIC interrupt to clear
00381   * @retval None
00382   */
00383 #define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__)   /* Dummy macro */
00384
00385 /** @brief  Check whether the specified CORDIC status flag is set or not.
00386   * @param  __HANDLE__ CORDIC handle.
00387   * @param  __FLAG__ CORDIC flag to check
00388   *         This parameter can be one of the following values:
00389   *            @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
00390   * @retval SET (flag is set) or RESET (flag is reset)
00391   */
00392 #define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__)                           \
00393   ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
00394
00395 /** @brief  Clear specified CORDIC status flag. Dummy macro as no
00396             flag can be cleared.
00397   * @param  __HANDLE__ CORDIC handle.
00398   * @param  __FLAG__ CORDIC flag to clear
00399   *         This parameter can be one of the following values:
00400   *            @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
00401   * @retval None
00402   */
00403 #define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__)     /* Dummy macro */
00404
00405 /** @brief  Check whether the specified CORDIC interrupt is enabled or not.
00406   * @param  __HANDLE__ CORDIC handle.
00407   * @param  __INTERRUPT__ CORDIC interrupt to check
00408   *         This parameter can be one of the following values:
00409   *            @arg @ref CORDIC_IT_IEN Enable Interrupt
00410   * @retval FlagStatus
00411   */
00412 #define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                 \
00413   (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
00414
00415 /**
00416   * @}
00417   */
00418
00419 /* Private macros --------------------------------------------------------*/
00420 /** @defgroup  CORDIC_Private_Macros   CORDIC Private Macros
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Verify the CORDIC function.
00426   * @param  __FUNCTION__ Name of the function.
00427   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00428   */
00429 #define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE)       || \
00430                                           ((__FUNCTION__) == CORDIC_FUNCTION_SINE)         || \
00431                                           ((__FUNCTION__) == CORDIC_FUNCTION_PHASE)        || \
00432                                           ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS)      || \
00433                                           ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT)   || \
00434                                           ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE)      || \
00435                                           ((__FUNCTION__) == CORDIC_FUNCTION_HSINE)        || \
00436                                           ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT)  || \
00437                                           ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG)   || \
00438                                           ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
00439
00440
00441 /**
00442   * @brief  Verify the CORDIC precision.
00443   * @param  __PRECISION__ CORDIC Precision in Cycles Number.
00444   * @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
00445   */
00446 #define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE)   || \
00447                                             ((__PRECISION__) == CORDIC_PRECISION_2CYCLES)  || \
00448                                             ((__PRECISION__) == CORDIC_PRECISION_3CYCLES)  || \
00449                                             ((__PRECISION__) == CORDIC_PRECISION_4CYCLES)  || \
00450                                             ((__PRECISION__) == CORDIC_PRECISION_5CYCLES)  || \
00451                                             ((__PRECISION__) == CORDIC_PRECISION_6CYCLES)  || \
00452                                             ((__PRECISION__) == CORDIC_PRECISION_7CYCLES)  || \
00453                                             ((__PRECISION__) == CORDIC_PRECISION_8CYCLES)  || \
00454                                             ((__PRECISION__) == CORDIC_PRECISION_9CYCLES)  || \
00455                                             ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
00456                                             ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
00457                                             ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
00458                                             ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
00459                                             ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
00460                                             ((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
00461
00462 /**
00463   * @brief  Verify the CORDIC scaling factor.
00464   * @param  __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
00465   * @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
00466   */
00467 #define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0)  || \
00468                                     ((__SCALE__) == CORDIC_SCALE_1)  || \
00469                                     ((__SCALE__) == CORDIC_SCALE_2)  || \
00470                                     ((__SCALE__) == CORDIC_SCALE_3)  || \
00471                                     ((__SCALE__) == CORDIC_SCALE_4)  || \
00472                                     ((__SCALE__) == CORDIC_SCALE_5)  || \
00473                                     ((__SCALE__) == CORDIC_SCALE_6)  || \
00474                                     ((__SCALE__) == CORDIC_SCALE_7))
00475
00476 /**
00477   * @brief  Verify the CORDIC number of 32-bits write expected for one calculation.
00478   * @param  __NBWRITE__ Number of 32-bits write expected for one calculation.
00479   * @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
00480   */
00481 #define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1)  || \
00482                                         ((__NBWRITE__) == CORDIC_NBWRITE_2))
00483
00484 /**
00485   * @brief  Verify the CORDIC number of 32-bits read expected after one calculation.
00486   * @param  __NBREAD__ Number of 32-bits read expected after one calculation.
00487   * @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
00488   */
00489 #define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1)  || \
00490                                       ((__NBREAD__) == CORDIC_NBREAD_2))
00491
00492 /**
00493   * @brief  Verify the CORDIC input data size for one calculation.
00494   * @param  __INSIZE__ input data size for one calculation.
00495   * @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
00496   */
00497 #define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS)  || \
00498                                       ((__INSIZE__) == CORDIC_INSIZE_16BITS))
00499
00500 /**
00501   * @brief  Verify the CORDIC output data size for one calculation.
00502   * @param  __OUTSIZE__ output data size for one calculation.
00503   * @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
00504   */
00505 #define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS)  || \
00506                                         ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
00507
00508 /**
00509   * @brief  Verify the CORDIC DMA transfer Direction.
00510   * @param  __DMADIR__ DMA transfer direction.
00511   * @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
00512   */
00513 #define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN)  || \
00514                                              ((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
00515                                              ((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
00516
00517 /**
00518   * @}
00519   */
00520
00521 /** @addtogroup CORDIC_Exported_Functions
00522   * @{
00523   */
00524 /* Exported functions ------------------------------------------------------- */
00525
00526 /** @addtogroup CORDIC_Exported_Functions_Group1
00527   * @{
00528   */
00529 /* Initialization and de-initialization functions ******************************/
00530 HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
00531 HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
00532 void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
00533 void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
00534
00535 #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
00536 /* Callbacks Register/UnRegister functions  ***********************************/
00537 HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
00538                                               pCORDIC_CallbackTypeDef pCallback);
00539 HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
00540 /**
00541   * @}
00542   */
00543
00544 /** @addtogroup CORDIC_Exported_Functions_Group2
00545   * @{
00546   */
00547 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
00548 /* Peripheral Control functions ***********************************************/
00549 HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
00550 HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00551                                        uint32_t NbCalc, uint32_t Timeout);
00552 HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00553                                          uint32_t NbCalc, uint32_t Timeout);
00554 HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00555                                           uint32_t NbCalc);
00556 HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
00557                                            uint32_t NbCalc, uint32_t DMADirection);
00558 /**
00559   * @}
00560   */
00561
00562 /** @addtogroup CORDIC_Exported_Functions_Group3
00563   * @{
00564   */
00565 /* Callback functions *********************************************************/
00566 void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
00567 void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
00568 /**
00569   * @}
00570   */
00571
00572 /** @addtogroup CORDIC_Exported_Functions_Group4
00573   * @{
00574   */
00575 /* IRQ handler management *****************************************************/
00576 void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
00577 /**
00578   * @}
00579   */
00580
00581 /** @addtogroup CORDIC_Exported_Functions_Group5
00582   * @{
00583   */
00584 /* Peripheral State functions *************************************************/
00585 HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
00586 uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
00587 /**
00588   * @}
00589   */
00590
00591 /**
00592   * @}
00593   */
00594
00595 /**
00596   * @}
00597   */
00598
00599 /**
00600   * @}
00601   */
00602
00603 #endif /* CORDIC */
00604
00605 #ifdef __cplusplus
00606 }
00607 #endif
00608
00609 #endif /* STM32G4xx_HAL_CORDIC_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cortex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cortex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @brief   CORTEX HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORTEX:
00008   *           + Initialization and Configuration functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                         ##### How to use this driver #####
00025   ==============================================================================
00026
00027     [..]
00028     *** How to configure Interrupts using CORTEX HAL driver ***
00029     ===========================================================
00030     [..]
00031     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00032     The Cortex-M4 exceptions are managed by CMSIS functions.
00033
00034     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
00035     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00036     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00037
00038      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
00039          The pending IRQ priority will be managed only by the sub priority.
00040
00041      -@- IRQ priority order (sorted by highest to lowest priority):
00042         (+@) Lowest pre-emption priority
00043         (+@) Lowest sub priority
00044         (+@) Lowest hardware priority (IRQ number)
00045
00046     [..]
00047     *** How to configure SysTick using CORTEX HAL driver ***
00048     ========================================================
00049     [..]
00050     Setup SysTick Timer for time base.
00051
00052    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00053        is a CMSIS function that:
00054         (++) Configures the SysTick Reload register with value passed as function parameter.
00055         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
00056         (++) Resets the SysTick Counter register.
00057         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00058         (++) Enables the SysTick Interrupt.
00059         (++) Starts the SysTick Counter.
00060
00061    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00062        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00063        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00064        inside the stm32g4xx_hal_cortex.h file.
00065
00066    (+) You can change the SysTick IRQ priority by calling the
00067        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00068        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00069
00070    (+) To adjust the SysTick time base, use the following formula:
00071
00072        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00073        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00074        (++) Reload Value should not exceed 0xFFFFFF
00075
00076   @endverbatim
00077   ******************************************************************************
00078
00079   The table below gives the allowed values of the pre-emption priority and subpriority according
00080   to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
00081
00082     ==========================================================================================================================
00083       NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
00084     ==========================================================================================================================
00085      NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
00086                            |                                   |                             | 4 bits for subpriority
00087     --------------------------------------------------------------------------------------------------------------------------
00088      NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
00089                            |                                   |                             | 3 bits for subpriority
00090     --------------------------------------------------------------------------------------------------------------------------
00091      NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
00092                            |                                   |                             | 2 bits for subpriority
00093     --------------------------------------------------------------------------------------------------------------------------
00094      NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
00095                            |                                   |                             | 1 bit for subpriority
00096     --------------------------------------------------------------------------------------------------------------------------
00097      NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
00098                            |                                   |                             | 0 bit for subpriority
00099     ==========================================================================================================================
00100
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32g4xx_hal.h"
00105
00106 /** @addtogroup STM32G4xx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @addtogroup CORTEX
00111   * @{
00112   */
00113
00114 #ifdef HAL_CORTEX_MODULE_ENABLED
00115
00116 /* Private types -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private constants ---------------------------------------------------------*/
00119 /* Private macros ------------------------------------------------------------*/
00120 /* Private functions ---------------------------------------------------------*/
00121 /* Exported functions --------------------------------------------------------*/
00122
00123 /** @addtogroup CORTEX_Exported_Functions
00124   * @{
00125   */
00126
00127
00128 /** @addtogroup CORTEX_Exported_Functions_Group1
00129  *  @brief    Initialization and Configuration functions
00130  *
00131 @verbatim
00132   ==============================================================================
00133               ##### Initialization and Configuration functions #####
00134   ==============================================================================
00135     [..]
00136       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00137       SysTick functionalities
00138
00139 @endverbatim
00140   * @{
00141   */
00142
00143
00144 /**
00145   * @brief  Set the priority grouping field (pre-emption priority and subpriority)
00146   *         using the required unlock sequence.
00147   * @param  PriorityGroup: The priority grouping bits length.
00148   *         This parameter can be one of the following values:
00149   *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
00150   *                                    4 bits for subpriority
00151   *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
00152   *                                    3 bits for subpriority
00153   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00154   *                                    2 bits for subpriority
00155   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00156   *                                    1 bit  for subpriority
00157   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00158   *                                    0 bit  for subpriority
00159   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
00160   *         The pending IRQ priority will be managed only by the subpriority.
00161   * @retval None
00162   */
00163 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00164 {
00165   /* Check the parameters */
00166   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00167
00168   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00169   NVIC_SetPriorityGrouping(PriorityGroup);
00170 }
00171
00172 /**
00173   * @brief  Set the priority of an interrupt.
00174   * @param  IRQn: External interrupt number.
00175   *         This parameter can be an enumerator of IRQn_Type enumeration
00176   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00177   * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
00178   *         This parameter can be a value between 0 and 15
00179   *         A lower priority value indicates a higher priority
00180   * @param  SubPriority: the subpriority level for the IRQ channel.
00181   *         This parameter can be a value between 0 and 15
00182   *         A lower priority value indicates a higher priority.
00183   * @retval None
00184   */
00185 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00186 {
00187   uint32_t prioritygroup;
00188
00189   /* Check the parameters */
00190   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00191   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00192
00193   prioritygroup = NVIC_GetPriorityGrouping();
00194
00195   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00196 }
00197
00198 /**
00199   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
00200   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00201   *         function should be called before.
00202   * @param  IRQn External interrupt number.
00203   *         This parameter can be an enumerator of IRQn_Type enumeration
00204   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00205   * @retval None
00206   */
00207 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00208 {
00209   /* Check the parameters */
00210   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00211
00212   /* Enable interrupt */
00213   NVIC_EnableIRQ(IRQn);
00214 }
00215
00216 /**
00217   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
00218   * @param  IRQn External interrupt number.
00219   *         This parameter can be an enumerator of IRQn_Type enumeration
00220   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00221   * @retval None
00222   */
00223 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00224 {
00225   /* Check the parameters */
00226   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00227
00228   /* Disable interrupt */
00229   NVIC_DisableIRQ(IRQn);
00230 }
00231
00232 /**
00233   * @brief  Initiate a system reset request to reset the MCU.
00234   * @retval None
00235   */
00236 void HAL_NVIC_SystemReset(void)
00237 {
00238   /* System Reset */
00239   NVIC_SystemReset();
00240 }
00241
00242 /**
00243   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
00244   *         Counter is in free running mode to generate periodic interrupts.
00245   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00246   * @retval status:  - 0  Function succeeded.
00247   *                  - 1  Function failed.
00248   */
00249 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00250 {
00251    return SysTick_Config(TicksNumb);
00252 }
00253 /**
00254   * @}
00255   */
00256
00257 /** @addtogroup CORTEX_Exported_Functions_Group2
00258  *  @brief   Cortex control functions
00259  *
00260 @verbatim
00261   ==============================================================================
00262                       ##### Peripheral Control functions #####
00263   ==============================================================================
00264     [..]
00265       This subsection provides a set of functions allowing to control the CORTEX
00266       (NVIC, SYSTICK, MPU) functionalities.
00267
00268
00269 @endverbatim
00270   * @{
00271   */
00272
00273 /**
00274   * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
00275   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00276   */
00277 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00278 {
00279   /* Get the PRIGROUP[10:8] field value */
00280   return NVIC_GetPriorityGrouping();
00281 }
00282
00283 /**
00284   * @brief  Get the priority of an interrupt.
00285   * @param  IRQn: External interrupt number.
00286   *         This parameter can be an enumerator of IRQn_Type enumeration
00287   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00288   * @param   PriorityGroup: the priority grouping bits length.
00289   *         This parameter can be one of the following values:
00290   *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
00291   *                                      4 bits for subpriority
00292   *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
00293   *                                      3 bits for subpriority
00294   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00295   *                                      2 bits for subpriority
00296   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00297   *                                      1 bit for subpriority
00298   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00299   *                                      0 bit for subpriority
00300   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00301   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00302   * @retval None
00303   */
00304 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00305 {
00306   /* Check the parameters */
00307   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00308  /* Get priority for Cortex-M system or device specific interrupts */
00309   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00310 }
00311
00312 /**
00313   * @brief  Set Pending bit of an external interrupt.
00314   * @param  IRQn External interrupt number
00315   *         This parameter can be an enumerator of IRQn_Type enumeration
00316   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00317   * @retval None
00318   */
00319 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00320 {
00321   /* Check the parameters */
00322   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00323
00324   /* Set interrupt pending */
00325   NVIC_SetPendingIRQ(IRQn);
00326 }
00327
00328 /**
00329   * @brief  Get Pending Interrupt (read the pending register in the NVIC
00330   *         and return the pending bit for the specified interrupt).
00331   * @param  IRQn External interrupt number.
00332   *          This parameter can be an enumerator of IRQn_Type enumeration
00333   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00334   * @retval status: - 0  Interrupt status is not pending.
00335   *                 - 1  Interrupt status is pending.
00336   */
00337 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00338 {
00339   /* Check the parameters */
00340   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00341
00342   /* Return 1 if pending else 0 */
00343   return NVIC_GetPendingIRQ(IRQn);
00344 }
00345
00346 /**
00347   * @brief  Clear the pending bit of an external interrupt.
00348   * @param  IRQn External interrupt number.
00349   *         This parameter can be an enumerator of IRQn_Type enumeration
00350   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00351   * @retval None
00352   */
00353 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00354 {
00355   /* Check the parameters */
00356   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00357
00358   /* Clear pending interrupt */
00359   NVIC_ClearPendingIRQ(IRQn);
00360 }
00361
00362 /**
00363   * @brief Get active interrupt (read the active register in NVIC and return the active bit).
00364   * @param IRQn External interrupt number
00365   *         This parameter can be an enumerator of IRQn_Type enumeration
00366   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
00367   * @retval status: - 0  Interrupt status is not pending.
00368   *                 - 1  Interrupt status is pending.
00369   */
00370 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00371 {
00372   /* Return 1 if active else 0 */
00373   return NVIC_GetActive(IRQn);
00374 }
00375
00376 /**
00377   * @brief  Configure the SysTick clock source.
00378   * @param  CLKSource: specifies the SysTick clock source.
00379   *          This parameter can be one of the following values:
00380   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00381   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00382   * @retval None
00383   */
00384 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00385 {
00386   /* Check the parameters */
00387   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00388   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00389   {
00390     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00391   }
00392   else
00393   {
00394     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00395   }
00396 }
00397
00398 /**
00399   * @brief  Handle SYSTICK interrupt request.
00400   * @retval None
00401   */
00402 void HAL_SYSTICK_IRQHandler(void)
00403 {
00404   HAL_SYSTICK_Callback();
00405 }
00406
00407 /**
00408   * @brief  SYSTICK callback.
00409   * @retval None
00410   */
00411 __weak void HAL_SYSTICK_Callback(void)
00412 {
00413   /* NOTE : This function should not be modified, when the callback is needed,
00414             the HAL_SYSTICK_Callback could be implemented in the user file
00415    */
00416 }
00417
00418 #if (__MPU_PRESENT == 1)
00419 /**
00420   * @brief  Enable the MPU.
00421   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00422   *          NMI, FAULTMASK and privileged accessto the default memory
00423   *          This parameter can be one of the following values:
00424   *            @arg MPU_HFNMI_PRIVDEF_NONE
00425   *            @arg MPU_HARDFAULT_NMI
00426   *            @arg MPU_PRIVILEGED_DEFAULT
00427   *            @arg MPU_HFNMI_PRIVDEF
00428   * @retval None
00429   */
00430 void HAL_MPU_Enable(uint32_t MPU_Control)
00431 {
00432   /* Enable the MPU */
00433   MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
00434
00435   /* Ensure MPU setting take effects */
00436   __DSB();
00437   __ISB();
00438 }
00439
00440
00441 /**
00442   * @brief  Disable the MPU.
00443   * @retval None
00444   */
00445 void HAL_MPU_Disable(void)
00446 {
00447   /* Make sure outstanding transfers are done */
00448   __DMB();
00449
00450   /* Disable the MPU and clear the control register*/
00451   MPU->CTRL  = 0;
00452 }
00453
00454
00455 /**
00456   * @brief  Initialize and configure the Region and the memory to be protected.
00457   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00458   *                the initialization and configuration information.
00459   * @retval None
00460   */
00461 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00462 {
00463   /* Check the parameters */
00464   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00465   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00466
00467   /* Set the Region number */
00468   MPU->RNR = MPU_Init->Number;
00469
00470   if ((MPU_Init->Enable) != 0U)
00471   {
00472     /* Check the parameters */
00473     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00474     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00475     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00476     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00477     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00478     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00479     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00480     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00481
00482     MPU->RBAR = MPU_Init->BaseAddress;
00483     MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
00484                 ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
00485                 ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
00486                 ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
00487                 ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
00488                 ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
00489                 ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
00490                 ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
00491                 ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
00492   }
00493   else
00494   {
00495     MPU->RBAR = 0x00;
00496     MPU->RASR = 0x00;
00497   }
00498 }
00499 #endif /* __MPU_PRESENT */
00500
00501 /**
00502   * @}
00503   */
00504
00505 /**
00506   * @}
00507   */
00508
00509 #endif /* HAL_CORTEX_MODULE_ENABLED */
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cortex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cortex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef __STM32G4xx_HAL_CORTEX_H
00020 #define __STM32G4xx_HAL_CORTEX_H
00021
00022 #ifdef __cplusplus
00023  extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @defgroup CORTEX CORTEX
00034   * @brief CORTEX HAL module driver
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
00040   * @{
00041   */
00042
00043 #if (__MPU_PRESENT == 1)
00044 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00045   * @brief  MPU Region initialization structure
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint8_t                Enable;                /*!< Specifies the status of the region.
00051                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00052   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00053                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00054   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00055   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00056                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00057   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00058                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00059   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00060                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00061   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00062                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00063   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00064                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00065   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00066                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00067   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00068                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00069   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00070                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00071 }MPU_Region_InitTypeDef;
00072 /**
00073   * @}
00074   */
00075 #endif /* __MPU_PRESENT */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported constants --------------------------------------------------------*/
00082
00083 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00088   * @{
00089   */
00090 #define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bit  for pre-emption priority,
00091                                                       4 bits for subpriority */
00092 #define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bit  for pre-emption priority,
00093                                                       3 bits for subpriority */
00094 #define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority,
00095                                                       2 bits for subpriority */
00096 #define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority,
00097                                                       1 bit  for subpriority */
00098 #define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority,
00099                                                       0 bit  for subpriority */
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00105   * @{
00106   */
00107 #define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
00108 #define SYSTICK_CLKSOURCE_HCLK            0x00000004U
00109
00110 /**
00111   * @}
00112   */
00113
00114 #if (__MPU_PRESENT == 1)
00115 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
00116   * @{
00117   */
00118 #define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
00119 #define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
00120 #define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
00121 #define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00127   * @{
00128   */
00129 #define  MPU_REGION_ENABLE           ((uint8_t)0x01)
00130 #define  MPU_REGION_DISABLE          ((uint8_t)0x00)
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00136   * @{
00137   */
00138 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00139 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00145   * @{
00146   */
00147 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00148 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00154   * @{
00155   */
00156 #define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
00157 #define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00163   * @{
00164   */
00165 #define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
00166 #define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
00172   * @{
00173   */
00174 #define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
00175 #define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
00176 #define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
00177 #define  MPU_TEX_LEVEL4              ((uint8_t)0x04)
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00183   * @{
00184   */
00185 #define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
00186 #define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
00187 #define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
00188 #define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
00189 #define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
00190 #define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
00191 #define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
00192 #define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
00193 #define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
00194 #define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
00195 #define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
00196 #define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
00197 #define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
00198 #define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
00199 #define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
00200 #define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
00201 #define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
00202 #define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
00203 #define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
00204 #define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
00205 #define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
00206 #define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
00207 #define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
00208 #define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
00209 #define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
00210 #define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
00211 #define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
00212 #define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00218   * @{
00219   */
00220 #define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
00221 #define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
00222 #define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
00223 #define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
00224 #define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
00225 #define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00231   * @{
00232   */
00233 #define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
00234 #define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
00235 #define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
00236 #define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
00237 #define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
00238 #define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
00239 #define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
00240 #define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
00241 /**
00242   * @}
00243   */
00244 #endif /* __MPU_PRESENT */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /* Exported macros -----------------------------------------------------------*/
00251 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00252   * @{
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 /* Exported functions --------------------------------------------------------*/
00260 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00261   * @{
00262   */
00263
00264 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
00265   * @brief    Initialization and Configuration functions
00266   * @{
00267   */
00268 /* Initialization and Configuration functions *****************************/
00269 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00270 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00271 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00272 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00273 void HAL_NVIC_SystemReset(void);
00274 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00281   * @brief   Cortex control functions
00282   * @{
00283   */
00284 /* Peripheral Control functions ***********************************************/
00285 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00286 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00287 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00288 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00289 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00290 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00291 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00292 void HAL_SYSTICK_IRQHandler(void);
00293 void HAL_SYSTICK_Callback(void);
00294
00295 #if (__MPU_PRESENT == 1)
00296 void HAL_MPU_Enable(uint32_t MPU_Control);
00297 void HAL_MPU_Disable(void);
00298 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00299 #endif /* __MPU_PRESENT */
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /* Private types -------------------------------------------------------------*/
00309 /* Private variables ---------------------------------------------------------*/
00310 /* Private constants ---------------------------------------------------------*/
00311 /* Private macros ------------------------------------------------------------*/
00312 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00313   * @{
00314   */
00315 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00316                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00317                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00318                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00319                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00320
00321 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00322
00323 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
00324
00325 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) > SysTick_IRQn)
00326
00327 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00328                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00329
00330 #if (__MPU_PRESENT == 1)
00331 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00332                                      ((STATE) == MPU_REGION_DISABLE))
00333
00334 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00335                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00336
00337 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00338                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00339
00340 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00341                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00342
00343 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00344                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00345
00346 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00347                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00348                                 ((TYPE) == MPU_TEX_LEVEL2)  || \
00349                                 ((TYPE) == MPU_TEX_LEVEL4))
00350
00351 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00352                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00353                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00354                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00355                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00356                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00357
00358 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00359                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00360                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00361                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00362                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00363                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00364                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00365                                          ((NUMBER) == MPU_REGION_NUMBER7))
00366
00367 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00368                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00369                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00370                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00371                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00372                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00373                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00374                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00375                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00376                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00377                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00378                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00379                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00380                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00381                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00382                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00383                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00384                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00385                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00386                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00387                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00388                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00389                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00390                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00391                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00392                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00393                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00394                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00395
00396 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00397 #endif /* __MPU_PRESENT */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /* Private functions ---------------------------------------------------------*/
00404
00405 /**
00406   * @}
00407   */
00408
00409 /**
00410   * @}
00411   */
00412
00413 #ifdef __cplusplus
00414 }
00415 #endif
00416
00417 #endif /* __STM32G4xx_HAL_CORTEX_H */
00418
00419
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_crc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024  ===============================================================================
00025                      ##### How to use this driver #####
00026  ===============================================================================
00027     [..]
00028          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00029          (+) Initialize CRC calculator
00030              (++) specify generating polynomial (peripheral default or non-default one)
00031              (++) specify initialization value (peripheral default or non-default one)
00032              (++) specify input data format
00033              (++) specify input or output data inversion mode if any
00034          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00035              input data buffer starting with the previously computed CRC as
00036              initialization value
00037          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00038              input data buffer starting with the defined initialization value
00039              (default or non-default) to initiate CRC calculation
00040
00041   @endverbatim
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32g4xx_hal.h"
00047
00048 /** @addtogroup STM32G4xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup CRC CRC
00053   * @brief CRC HAL module driver.
00054   * @{
00055   */
00056
00057 #ifdef HAL_CRC_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /** @defgroup CRC_Private_Functions CRC Private Functions
00065   * @{
00066   */
00067 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00068 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00069 /**
00070   * @}
00071   */
00072
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00080   *  @brief    Initialization and Configuration functions.
00081   *
00082 @verbatim
00083  ===============================================================================
00084             ##### Initialization and de-initialization functions #####
00085  ===============================================================================
00086     [..]  This section provides functions allowing to:
00087       (+) Initialize the CRC according to the specified parameters
00088           in the CRC_InitTypeDef and create the associated handle
00089       (+) DeInitialize the CRC peripheral
00090       (+) Initialize the CRC MSP (MCU Specific Package)
00091       (+) DeInitialize the CRC MSP
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Initialize the CRC according to the specified
00099   *         parameters in the CRC_InitTypeDef and create the associated handle.
00100   * @param  hcrc CRC handle
00101   * @retval HAL status
00102   */
00103 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00104 {
00105   /* Check the CRC handle allocation */
00106   if (hcrc == NULL)
00107   {
00108     return HAL_ERROR;
00109   }
00110
00111   /* Check the parameters */
00112   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00113
00114   if (hcrc->State == HAL_CRC_STATE_RESET)
00115   {
00116     /* Allocate lock resource and initialize it */
00117     hcrc->Lock = HAL_UNLOCKED;
00118     /* Init the low level hardware */
00119     HAL_CRC_MspInit(hcrc);
00120   }
00121
00122   hcrc->State = HAL_CRC_STATE_BUSY;
00123
00124   /* check whether or not non-default generating polynomial has been
00125    * picked up by user */
00126   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00127   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00128   {
00129     /* initialize peripheral with default generating polynomial */
00130     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00131     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00132   }
00133   else
00134   {
00135     /* initialize CRC peripheral with generating polynomial defined by user */
00136     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00137     {
00138       return HAL_ERROR;
00139     }
00140   }
00141
00142   /* check whether or not non-default CRC initial value has been
00143    * picked up by user */
00144   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00145   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00146   {
00147     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00148   }
00149   else
00150   {
00151     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00152   }
00153
00154
00155   /* set input data inversion mode */
00156   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00157   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00158
00159   /* set output data inversion mode */
00160   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00161   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00162
00163   /* makes sure the input data format (bytes, halfwords or words stream)
00164    * is properly specified by user */
00165   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00166
00167   /* Change CRC peripheral state */
00168   hcrc->State = HAL_CRC_STATE_READY;
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  DeInitialize the CRC peripheral.
00176   * @param  hcrc CRC handle
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00180 {
00181   /* Check the CRC handle allocation */
00182   if (hcrc == NULL)
00183   {
00184     return HAL_ERROR;
00185   }
00186
00187   /* Check the parameters */
00188   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00189
00190   /* Check the CRC peripheral state */
00191   if (hcrc->State == HAL_CRC_STATE_BUSY)
00192   {
00193     return HAL_BUSY;
00194   }
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_BUSY;
00198
00199   /* Reset CRC calculation unit */
00200   __HAL_CRC_DR_RESET(hcrc);
00201
00202   /* Reset IDR register content */
00203   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00204
00205   /* DeInit the low level hardware */
00206   HAL_CRC_MspDeInit(hcrc);
00207
00208   /* Change CRC peripheral state */
00209   hcrc->State = HAL_CRC_STATE_RESET;
00210
00211   /* Process unlocked */
00212   __HAL_UNLOCK(hcrc);
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Initializes the CRC MSP.
00220   * @param  hcrc CRC handle
00221   * @retval None
00222   */
00223 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hcrc);
00227
00228   /* NOTE : This function should not be modified, when the callback is needed,
00229             the HAL_CRC_MspInit can be implemented in the user file
00230    */
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the CRC MSP.
00235   * @param  hcrc CRC handle
00236   * @retval None
00237   */
00238 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00239 {
00240   /* Prevent unused argument(s) compilation warning */
00241   UNUSED(hcrc);
00242
00243   /* NOTE : This function should not be modified, when the callback is needed,
00244             the HAL_CRC_MspDeInit can be implemented in the user file
00245    */
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00253   *  @brief    management functions.
00254   *
00255 @verbatim
00256  ===============================================================================
00257                       ##### Peripheral Control functions #####
00258  ===============================================================================
00259     [..]  This section provides functions allowing to:
00260       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00261           using combination of the previous CRC value and the new one.
00262
00263        [..]  or
00264
00265       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00266           independently of the previous CRC value.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00274   *         starting with the previously computed CRC as initialization value.
00275   * @param  hcrc CRC handle
00276   * @param  pBuffer pointer to the input data buffer, exact input data format is
00277   *         provided by hcrc->InputDataFormat.
00278   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00279   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00280   *         number of words if pBuffer type is * uint32_t).
00281   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00282   *        Input buffer pointers with other types simply need to be cast in uint32_t
00283   *        and the API will internally adjust its input data processing based on the
00284   *        handle field hcrc->InputDataFormat.
00285   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00286   */
00287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00288 {
00289   uint32_t index;      /* CRC input data buffer index */
00290   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00291
00292   /* Change CRC peripheral state */
00293   hcrc->State = HAL_CRC_STATE_BUSY;
00294
00295   switch (hcrc->InputDataFormat)
00296   {
00297     case CRC_INPUTDATA_FORMAT_WORDS:
00298       /* Enter Data to the CRC calculator */
00299       for (index = 0U; index < BufferLength; index++)
00300       {
00301         hcrc->Instance->DR = pBuffer[index];
00302       }
00303       temp = hcrc->Instance->DR;
00304       break;
00305
00306     case CRC_INPUTDATA_FORMAT_BYTES:
00307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00308       break;
00309
00310     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00312       break;
00313     default:
00314       break;
00315   }
00316
00317   /* Change CRC peripheral state */
00318   hcrc->State = HAL_CRC_STATE_READY;
00319
00320   /* Return the CRC computed value */
00321   return temp;
00322 }
00323
00324 /**
00325   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00326   *         starting with hcrc->Instance->INIT as initialization value.
00327   * @param  hcrc CRC handle
00328   * @param  pBuffer pointer to the input data buffer, exact input data format is
00329   *         provided by hcrc->InputDataFormat.
00330   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00331   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00332   *         number of words if pBuffer type is * uint32_t).
00333   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00334   *        Input buffer pointers with other types simply need to be cast in uint32_t
00335   *        and the API will internally adjust its input data processing based on the
00336   *        handle field hcrc->InputDataFormat.
00337   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00338   */
00339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00340 {
00341   uint32_t index;      /* CRC input data buffer index */
00342   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00343
00344   /* Change CRC peripheral state */
00345   hcrc->State = HAL_CRC_STATE_BUSY;
00346
00347   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00348   *  written in hcrc->Instance->DR) */
00349   __HAL_CRC_DR_RESET(hcrc);
00350
00351   switch (hcrc->InputDataFormat)
00352   {
00353     case CRC_INPUTDATA_FORMAT_WORDS:
00354       /* Enter 32-bit input data to the CRC calculator */
00355       for (index = 0U; index < BufferLength; index++)
00356       {
00357         hcrc->Instance->DR = pBuffer[index];
00358       }
00359       temp = hcrc->Instance->DR;
00360       break;
00361
00362     case CRC_INPUTDATA_FORMAT_BYTES:
00363       /* Specific 8-bit input data handling  */
00364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00365       break;
00366
00367     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00368       /* Specific 16-bit input data handling  */
00369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00370       break;
00371
00372     default:
00373       break;
00374   }
00375
00376   /* Change CRC peripheral state */
00377   hcrc->State = HAL_CRC_STATE_READY;
00378
00379   /* Return the CRC computed value */
00380   return temp;
00381 }
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00388   *  @brief    Peripheral State functions.
00389   *
00390 @verbatim
00391  ===============================================================================
00392                       ##### Peripheral State functions #####
00393  ===============================================================================
00394     [..]
00395     This subsection permits to get in run-time the status of the peripheral.
00396
00397 @endverbatim
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Return the CRC handle state.
00403   * @param  hcrc CRC handle
00404   * @retval HAL state
00405   */
00406 HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
00407 {
00408   /* Return CRC handle state */
00409   return hcrc->State;
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup CRC_Private_Functions
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Enter 8-bit input data to the CRC calculator.
00426   *         Specific data handling to optimize processing time.
00427   * @param  hcrc CRC handle
00428   * @param  pBuffer pointer to the input data buffer
00429   * @param  BufferLength input data buffer length
00430   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00431   */
00432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00433 {
00434   uint32_t i; /* input data buffer index */
00435   uint16_t data;
00436   __IO uint16_t *pReg;
00437
00438   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00439    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00440    * handling by the peripheral */
00441   for (i = 0U; i < (BufferLength / 4U); i++)
00442   {
00443     hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
00444                          ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
00445                          ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
00446                          (uint32_t)pBuffer[(4U * i) + 3U];
00447   }
00448   /* last bytes specific handling */
00449   if ((BufferLength % 4U) != 0U)
00450   {
00451     if ((BufferLength % 4U) == 1U)
00452     {
00453       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
00454     }
00455     if ((BufferLength % 4U) == 2U)
00456     {
00457       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00458       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00459       *pReg = data;
00460     }
00461     if ((BufferLength % 4U) == 3U)
00462     {
00463       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00464       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00465       *pReg = data;
00466
00467       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
00468     }
00469   }
00470
00471   /* Return the CRC computed value */
00472   return hcrc->Instance->DR;
00473 }
00474
00475 /**
00476   * @brief  Enter 16-bit input data to the CRC calculator.
00477   *         Specific data handling to optimize processing time.
00478   * @param  hcrc CRC handle
00479   * @param  pBuffer pointer to the input data buffer
00480   * @param  BufferLength input data buffer length
00481   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00482   */
00483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00484 {
00485   uint32_t i;  /* input data buffer index */
00486   __IO uint16_t *pReg;
00487
00488   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00489    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00490    * a correct type handling by the peripheral */
00491   for (i = 0U; i < (BufferLength / 2U); i++)
00492   {
00493     hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
00494   }
00495   if ((BufferLength % 2U) != 0U)
00496   {
00497     pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
00498     *pReg = pBuffer[2U * i];
00499   }
00500
00501   /* Return the CRC computed value */
00502   return hcrc->Instance->DR;
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 #endif /* HAL_CRC_MODULE_ENABLED */
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_CRC_H
00021 #define STM32G4xx_HAL_CRC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup CRC
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup CRC_Exported_Types CRC Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  CRC HAL State Structure definition
00045   */
00046 typedef enum
00047 {
00048   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00049   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00050   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00051   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00052   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00053 } HAL_CRC_StateTypeDef;
00054
00055 /**
00056   * @brief CRC Init Structure definition
00057   */
00058 typedef struct
00059 {
00060   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00061                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00062                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
00063                                             X^4 + X^2+ X +1.
00064                                             In that case, there is no need to set GeneratingPolynomial field.
00065                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
00066                                             CRCLength fields must be set. */
00067
00068   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00069                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00070                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
00071                                            otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
00072
00073   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
00074                                            respectively equal to 7, 8, 16 or 32. This field is written in normal,
00075                                            representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
00076                                            is written 0x65. No need to specify it if DefaultPolynomialUse is set to
00077                                             DEFAULT_POLYNOMIAL_ENABLE.   */
00078
00079   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00080                                            Value can be either one of
00081                                            @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
00082                                            @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
00083                                            @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
00084                                            @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
00085
00086   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00087                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00088
00089   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00090                                            Can be either one of the following values
00091                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
00092                                            @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D
00093                                            becomes 0x58D43CB2
00094                                            @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion,
00095                                            0x1A2B3C4D becomes 0xD458B23C
00096                                            @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D
00097                                            becomes 0xB23CD458 */
00098
00099   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00100                                             Can be either
00101                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
00102                                             @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted
00103                                              into 0x22CC4488 */
00104 } CRC_InitTypeDef;
00105
00106 /**
00107   * @brief  CRC Handle Structure definition
00108   */
00109 typedef struct
00110 {
00111   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00112
00113   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00114
00115   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00116
00117   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00118
00119   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00120                                             Can be either
00121                                             @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes
00122                                             (8-bit data)
00123                                             @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of
00124                                             half-words (16-bit data)
00125                                             @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words
00126                                             (32-bit data)
00127
00128                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
00129                                           error must occur if InputBufferFormat is not one of the three values listed
00130                                           above  */
00131 } CRC_HandleTypeDef;
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00142   * @{
00143   */
00144 #define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00150   * @{
00151   */
00152 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00158   * @{
00159   */
00160 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
00161 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00167   * @{
00168   */
00169 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
00170 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
00176   * @{
00177   */
00178 #define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
00179 #define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
00180 #define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
00181 #define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00187   * @{
00188   */
00189 #define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
00190 #define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
00191 #define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
00192 #define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00198   * @{
00199   */
00200 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00201  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00202  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00203  * the CRC APIs to provide a correct result */
00204 #define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
00205 #define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
00206 #define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
00207 #define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /* Exported macros -----------------------------------------------------------*/
00217 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00218   * @{
00219   */
00220
00221 /** @brief Reset CRC handle state.
00222   * @param  __HANDLE__ CRC handle.
00223   * @retval None
00224   */
00225 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00226
00227 /**
00228   * @brief  Reset CRC Data Register.
00229   * @param  __HANDLE__ CRC handle
00230   * @retval None
00231   */
00232 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00233
00234 /**
00235   * @brief  Set CRC INIT non-default value
00236   * @param  __HANDLE__ CRC handle
00237   * @param  __INIT__ 32-bit initial value
00238   * @retval None
00239   */
00240 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00241
00242 /**
00243   * @brief Store data in the Independent Data (ID) register.
00244   * @param __HANDLE__ CRC handle
00245   * @param __VALUE__  Value to be stored in the ID register
00246   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00247   * @retval None
00248   */
00249 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00250
00251 /**
00252   * @brief Return the data stored in the Independent Data (ID) register.
00253   * @param __HANDLE__ CRC handle
00254   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00255   * @retval Value of the ID register
00256   */
00257 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00258 /**
00259   * @}
00260   */
00261
00262
00263 /* Private macros --------------------------------------------------------*/
00264 /** @defgroup  CRC_Private_Macros CRC Private Macros
00265   * @{
00266   */
00267
00268 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00269                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00270
00271 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00272                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00273
00274 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00275                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00276                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00277                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00278
00279 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
00280                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00281                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Include CRC HAL Extended module */
00288 #include "stm32g4xx_hal_crc_ex.h"
00289
00290 /* Exported functions --------------------------------------------------------*/
00291 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00292   * @{
00293   */
00294
00295 /* Initialization and de-initialization functions  ****************************/
00296 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00297   * @{
00298   */
00299 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00300 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
00301 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00302 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00303 /**
00304   * @}
00305   */
00306
00307 /* Peripheral Control functions ***********************************************/
00308 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00309   * @{
00310   */
00311 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00312 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00313 /**
00314   * @}
00315   */
00316
00317 /* Peripheral State and Error functions ***************************************/
00318 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00319   * @{
00320   */
00321 HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* STM32G4xx_HAL_CRC_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_crc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the CRC peripheral.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   @verbatim
00021 ================================================================================
00022             ##### How to use this driver #####
00023 ================================================================================
00024     [..]
00025          (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
00026          (+) Configure Input or Output data inversion
00027
00028   @endverbatim
00029   ******************************************************************************
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32g4xx_hal.h"
00034
00035 /** @addtogroup STM32G4xx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup CRCEx CRCEx
00040   * @brief CRC Extended HAL module driver
00041   * @{
00042   */
00043
00044 #ifdef HAL_CRC_MODULE_ENABLED
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 /* Private define ------------------------------------------------------------*/
00048 /* Private macro -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private function prototypes -----------------------------------------------*/
00051 /* Exported functions --------------------------------------------------------*/
00052
00053 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00054   * @{
00055   */
00056
00057 /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00058   * @brief    Extended Initialization and Configuration functions.
00059   *
00060 @verbatim
00061  ===============================================================================
00062             ##### Extended configuration functions #####
00063  ===============================================================================
00064     [..]  This section provides functions allowing to:
00065       (+) Configure the generating polynomial
00066       (+) Configure the input data inversion
00067       (+) Configure the output data inversion
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073
00074 /**
00075   * @brief  Initialize the CRC polynomial if different from default one.
00076   * @param  hcrc CRC handle
00077   * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
00078   *         This parameter is written in normal representation, e.g.
00079   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00080   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00081   * @param  PolyLength CRC polynomial length.
00082   *         This parameter can be one of the following values:
00083   *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
00084   *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
00085   *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
00086   *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
00087   * @retval HAL status
00088   */
00089 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00090 {
00091   HAL_StatusTypeDef status = HAL_OK;
00092   uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
00093
00094   /* Check the parameters */
00095   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00096
00097   /* Ensure that the generating polynomial is odd */
00098   if ((Pol & (uint32_t)(0x1U)) ==  0U)
00099   {
00100     status =  HAL_ERROR;
00101   }
00102   else
00103   {
00104     /* check polynomial definition vs polynomial size:
00105      * polynomial length must be aligned with polynomial
00106      * definition. HAL_ERROR is reported if Pol degree is
00107      * larger than that indicated by PolyLength.
00108      * Look for MSB position: msb will contain the degree of
00109      *  the second to the largest polynomial member. E.g., for
00110      *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00111     while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
00112     {
00113     }
00114
00115     switch (PolyLength)
00116     {
00117
00118       case CRC_POLYLENGTH_7B:
00119         if (msb >= HAL_CRC_LENGTH_7B)
00120         {
00121           status =   HAL_ERROR;
00122         }
00123         break;
00124       case CRC_POLYLENGTH_8B:
00125         if (msb >= HAL_CRC_LENGTH_8B)
00126         {
00127           status =   HAL_ERROR;
00128         }
00129         break;
00130       case CRC_POLYLENGTH_16B:
00131         if (msb >= HAL_CRC_LENGTH_16B)
00132         {
00133           status =   HAL_ERROR;
00134         }
00135         break;
00136
00137       case CRC_POLYLENGTH_32B:
00138         /* no polynomial definition vs. polynomial length issue possible */
00139         break;
00140       default:
00141         status =  HAL_ERROR;
00142         break;
00143     }
00144   }
00145   if (status == HAL_OK)
00146   {
00147     /* set generating polynomial */
00148     WRITE_REG(hcrc->Instance->POL, Pol);
00149
00150     /* set generating polynomial size */
00151     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00152   }
00153   /* Return function status */
00154   return status;
00155 }
00156
00157 /**
00158   * @brief  Set the Reverse Input data mode.
00159   * @param  hcrc CRC handle
00160   * @param  InputReverseMode Input Data inversion mode.
00161   *         This parameter can be one of the following values:
00162   *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
00163   *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
00164   *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
00165   *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00169 {
00170   /* Check the parameters */
00171   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00172
00173   /* Change CRC peripheral state */
00174   hcrc->State = HAL_CRC_STATE_BUSY;
00175
00176   /* set input data inversion mode */
00177   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00178   /* Change CRC peripheral state */
00179   hcrc->State = HAL_CRC_STATE_READY;
00180
00181   /* Return function status */
00182   return HAL_OK;
00183 }
00184
00185 /**
00186   * @brief  Set the Reverse Output data mode.
00187   * @param  hcrc CRC handle
00188   * @param  OutputReverseMode Output Data inversion mode.
00189   *         This parameter can be one of the following values:
00190   *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
00191   *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00192   * @retval HAL status
00193   */
00194 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00195 {
00196   /* Check the parameters */
00197   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00198
00199   /* Change CRC peripheral state */
00200   hcrc->State = HAL_CRC_STATE_BUSY;
00201
00202   /* set output data inversion mode */
00203   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00204
00205   /* Change CRC peripheral state */
00206   hcrc->State = HAL_CRC_STATE_READY;
00207
00208   /* Return function status */
00209   return HAL_OK;
00210 }
00211
00212
00213
00214
00215 /**
00216   * @}
00217   */
00218
00219
00220 /**
00221   * @}
00222   */
00223
00224
00225 #endif /* HAL_CRC_MODULE_ENABLED */
00226 /**
00227   * @}
00228   */
00229
00230 /**
00231   * @}
00232   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_crc_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_crc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_CRC_EX_H
00021 #define STM32G4xx_HAL_CRC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup CRCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
00045   * @{
00046   */
00047 #define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
00048 #define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
00049 #define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
00050 #define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
00056   * @{
00057   */
00058 #define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
00059 #define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Exported macro ------------------------------------------------------------*/
00069 /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  Set CRC output reversal
00075   * @param  __HANDLE__ CRC handle
00076   * @retval None
00077   */
00078 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00079
00080 /**
00081   * @brief  Unset CRC output reversal
00082   * @param  __HANDLE__ CRC handle
00083   * @retval None
00084   */
00085 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00086
00087 /**
00088   * @brief  Set CRC non-default polynomial
00089   * @param  __HANDLE__ CRC handle
00090   * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
00091   * @retval None
00092   */
00093 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Private macros --------------------------------------------------------*/
00100 /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
00101   * @{
00102   */
00103
00104 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
00105                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
00106                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00107                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00108
00109 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00110                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported functions --------------------------------------------------------*/
00117
00118 /** @addtogroup CRCEx_Exported_Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup CRCEx_Exported_Functions_Group1
00123   * @{
00124   */
00125 /* Initialization and de-initialization functions  ****************************/
00126 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00127 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00128 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 #ifdef __cplusplus
00147 }
00148 #endif
00149
00150 #endif /* STM32G4xx_HAL_CRC_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cryp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @brief   CRYP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cryptography (CRYP) peripheral:
00008   *           + Initialization, de-initialization, set config and get config  functions
00009   *           + AES processing functions
00010   *           + DMA callback functions
00011   *           + CRYP IRQ handler management
00012   *           + Peripheral State functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### How to use this driver #####
00028   ==============================================================================
00029     [..]
00030       The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:
00031
00032       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00033          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00034               or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
00035          (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
00036              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00037              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00038              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00039          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
00040              (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
00041              (+++) Configure and enable two DMA streams one for managing data transfer from
00042                  memory to peripheral (input stream) and another stream for managing data
00043                  transfer from peripheral to memory (output stream)
00044              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00045                  using  __HAL_LINKDMA()
00046              (+++) Configure the priority and enable the NVIC for the transfer complete
00047                  interrupt on the two DMA channels. The output channel should have higher
00048                  priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00049
00050       (#)Initialize the CRYP according to the specified parameters :
00051          (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
00052          (##) The key size: 128, 192 or 256.
00053          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
00054          (##) The initialization vector (counter). It is not used in ECB mode.
00055          (##) The key buffer used for encryption/decryption.
00056              (+++) In some specific configurations, the key is written by the application
00057                    code out of the HAL scope. In that case, user can still resort to the
00058                    HAL APIs as usual but must make sure that pKey pointer is set to NULL.
00059          (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
00060                algorithms) is in words or bytes.
00061          (##) The Header used only in AES GCM and CCM Algorithm for authentication.
00062          (##) The HeaderSize providing the size of the header buffer in words or bytes,
00063               depending upon HeaderWidthUnit field.
00064          (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms)
00065               is in words or bytes.
00066          (##) The B0 block is the first authentication block used only in AES CCM mode.
00067          (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
00068
00069       (#)Three processing (encryption/decryption) functions are available:
00070          (##) Polling mode: encryption and decryption APIs are blocking functions
00071               i.e. they process the data and wait till the processing is finished,
00072               e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00073          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00074               i.e. they process the data under interrupt,
00075               e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00076          (##) DMA mode: encryption and decryption APIs are not blocking functions
00077               i.e. the data transfer is ensured by DMA,
00078               e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00079
00080       (#)When the processing function is called at first time after HAL_CRYP_Init()
00081          the CRYP peripheral is configured and processes the buffer in input.
00082          At second call, no need to Initialize the CRYP, user have to get current configuration via
00083          HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
00084          new parameters, finally user can  start encryption/decryption.
00085
00086        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00087
00088        (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
00089           without having to configure again the Key or the Initialization Vector between each API call,
00090           the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
00091           Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
00092           or HAL_CRYP_Decrypt_DMA().
00093
00094     [..]
00095       The cryptographic processor supports following standards:
00096       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
00097          (##)64-bit data block processing
00098          (##) chaining modes supported :
00099              (+++)  Electronic Code Book(ECB)
00100              (+++)  Cipher Block Chaining (CBC)
00101          (##) keys length supported :64-bit, 128-bit and 192-bit.
00102       (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
00103          (##)128-bit data block processing
00104          (##) chaining modes supported :
00105              (+++)  Electronic Code Book(ECB)
00106              (+++)  Cipher Block Chaining (CBC)
00107              (+++)  Counter mode (CTR)
00108              (+++)  Galois/counter mode (GCM/GMAC)
00109              (+++)  Counter with Cipher Block Chaining-Message(CCM)
00110          (##) keys length Supported :
00111              (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
00112              (+++) for TinyAES peripheral:  128-bit and 256-bit
00113
00114     [..]
00115     (@) Specific care must be taken to format the key and the Initialization Vector IV!
00116
00117     [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
00118          b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
00119          (+) as a sequence of words where the MSB word comes first (occupies the
00120            lowest memory address)
00121           (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
00122           (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
00123           (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
00124           (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
00125      [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
00126          The 4 32-bit words that make the key must be stored as follows in MCU memory:
00127           (+)    address n+0 : 0x B15 B14 B13 B12
00128           (+)    address n+4 : 0x B11 B10 B9 B8
00129           (+)    address n+8 : 0x B7 B6 B5 B4
00130           (+)    address n+C : 0x B3 B2 B1 B0
00131      [..]  which leads to the expected setting
00132        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00133        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00134        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00135        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00136
00137     [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
00138           The 8 32-bit words that make the key must be stored as follows in MCU memory:
00139           (+)    address n+00 : 0x B31 B30 B29 B28
00140           (+)    address n+04 : 0x B27 B26 B25 B24
00141           (+)    address n+08 : 0x B23 B22 B21 B20
00142           (+)    address n+0C : 0x B19 B18 B17 B16
00143           (+)    address n+10 : 0x B15 B14 B13 B12
00144           (+)    address n+14 : 0x B11 B10 B9 B8
00145           (+)    address n+18 : 0x B7 B6 B5 B4
00146           (+)    address n+1C : 0x B3 B2 B1 B0
00147      [..]  which leads to the expected setting
00148        (+)       AES_KEYR7 = 0x B31 B30 B29 B28
00149        (+)       AES_KEYR6 = 0x B27 B26 B25 B24
00150        (+)       AES_KEYR5 = 0x B23 B22 B21 B20
00151        (+)       AES_KEYR4 = 0x B19 B18 B17 B16
00152        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00153        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00154        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00155        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00156
00157     [..] Initialization Vector IV (4 32-bit words) format must follow the same as
00158          that of a 128-bit long key.
00159
00160     [..] Note that key and IV registers are not sensitive to swap mode selection.
00161
00162     [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
00163       (#)  Algorithm supported :
00164          (##) Galois/counter mode (GCM)
00165          (##) Galois message authentication code (GMAC) :is exactly the same as
00166               GCM algorithm composed only by an header.
00167       (#)  Four phases are performed in GCM :
00168          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00169          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00170           computation only.
00171          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00172           encryption + data XORing. It works in a similar way for ciphertext (C).
00173          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00174       (#)  structure of message construction in GCM is defined as below  :
00175          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
00176          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
00177           this part of the message is only authenticated, not encrypted.
00178          (##) The plaintext message P is both authenticated and encrypted as ciphertext.
00179           GCM standard specifies that ciphertext has same bit length as the plaintext.
00180          (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
00181           (on 64 bits)
00182
00183     [..]  A more detailed description of the GCM message structure is available below.
00184
00185     [..]  This section describe The AES Counter with Cipher Block Chaining-Message
00186           Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
00187       (#)  Specific parameters for CCM  :
00188
00189          (##) B0 block  : follows NIST Special Publication 800-38C,
00190          (##) B1 block (header)
00191          (##) CTRx block  : control blocks
00192
00193     [..]  A detailed description of the CCM message structure is available below.
00194
00195       (#)  Four phases are performed in CCM for CRYP1 peripheral:
00196          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00197          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00198           computation only.
00199          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00200           encryption + data XORing. It works in a similar way for ciphertext (C).
00201          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00202       (#)    CCM in TinyAES peripheral:
00203          (##) To perform message payload encryption or decryption AES is configured in CTR mode.
00204          (##) For authentication two phases are performed :
00205           - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
00206           only cleartext payload (not the ciphertext payload) is used and no output.
00207          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00208
00209   *** Callback registration ***
00210   =============================
00211
00212   [..]
00213   The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
00214   allows the user to configure dynamically the driver callbacks.
00215   Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
00216   to register an interrupt callback.
00217
00218   [..]
00219   Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
00220     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00221     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00222     (+) ErrorCallback      : callback for error detection.
00223     (+) MspInitCallback    : CRYP MspInit.
00224     (+) MspDeInitCallback  : CRYP MspDeInit.
00225   This function takes as parameters the HAL peripheral handle, the Callback ID
00226   and a pointer to the user callback function.
00227
00228   [..]
00229   Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
00230   weak function.
00231   HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00232   and the Callback ID.
00233   This function allows to reset following callbacks:
00234     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00235     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00236     (+) ErrorCallback      : callback for error detection.
00237     (+) MspInitCallback    : CRYP MspInit.
00238     (+) MspDeInitCallback  : CRYP MspDeInit.
00239
00240   [..]
00241   By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
00242   all callbacks are set to the corresponding weak functions :
00243   examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
00244   Exception done for MspInit and MspDeInit functions that are
00245   reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
00246   these callbacks are null (not registered beforehand).
00247   if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
00248   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00249
00250   [..]
00251   Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
00252   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00253   in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
00254   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00255   In that case first register the MspInit/MspDeInit user callbacks
00256   using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
00257   or HAL_CRYP_Init() function.
00258
00259   [..]
00260   When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
00261   not defined, the callback registration feature is not available and all callbacks
00262   are set to the corresponding weak functions.
00263
00264
00265   *** Suspend/Resume feature ***
00266   ==============================
00267
00268   [..]
00269   The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
00270   allows the user to resort to the suspend/resume feature.
00271   A low priority block processing can be suspended to process a high priority block
00272   instead. When the high priority block processing is over, the low priority block
00273   processing can be resumed, restarting from the point where it was suspended. This
00274   feature is applicable only in non-blocking interrupt mode.
00275
00276   [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
00277   processing. This API manages the hardware block processing suspension and saves all the
00278   internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
00279   the user can launch the processing of any other block (high priority block processing).
00280
00281   [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
00282   to resume the low priority block processing. Ciphering (or deciphering) restarts from
00283   the suspension point and ends as usual.
00284
00285   [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
00286   (i.e when the low priority block processing is about to end). There is no use to
00287   suspend the tag generation processing for authentication algorithms.
00288
00289     [..]
00290     (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
00291         the block processing suspension/resumption mechanism is NOT applicable.
00292
00293     [..]
00294     (@) If the Key and Initialization Vector are configured only once and configuration is
00295         skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
00296         the block processing suspension/resumption mechanism is NOT applicable.
00297
00298   @endverbatim
00299   ******************************************************************************
00300   */
00301
00302 /* Includes ------------------------------------------------------------------*/
00303 #include "stm32g4xx_hal.h"
00304
00305 /** @addtogroup STM32G4xx_HAL_Driver
00306   * @{
00307   */
00308
00309 /** @addtogroup CRYP
00310   * @{
00311   */
00312
00313 #if defined(AES)
00314 #ifdef HAL_CRYP_MODULE_ENABLED
00315
00316 /* Private typedef -----------------------------------------------------------*/
00317 /* Private define ------------------------------------------------------------*/
00318 /** @addtogroup CRYP_Private_Defines
00319   * @{
00320   */
00321 #define CRYP_TIMEOUT_KEYPREPARATION      82U         /* The latency of key preparation operation is 82 clock cycles.*/
00322 #define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /* The latency of  GCM/CCM init phase to prepare hash subkey
00323                                                         is 299 clock cycles.*/
00324 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /* The latency of  GCM/CCM header phase is 290 clock cycles.*/
00325
00326 #define CRYP_PHASE_READY                 0x00000001U /*!< CRYP peripheral is ready for initialization. */
00327 #define CRYP_PHASE_PROCESS               0x00000002U /*!< CRYP peripheral is in processing phase */
00328 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00329 #define  CRYP_PHASE_HEADER_SUSPENDED     0x00000004U    /*!< GCM/GMAC/CCM header phase is suspended */
00330 #define  CRYP_PHASE_PAYLOAD_SUSPENDED    0x00000005U    /*!< GCM/CCM payload phase is suspended     */
00331 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00332 #define  CRYP_PHASE_HEADER_DMA_FEED      0x00000006U    /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
00333
00334 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U     /*!< Encryption mode(Mode 1)  */
00335 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0   /*!< Key derivation mode  only used when performing ECB and CBC decryptions (Mode 2) */
00336 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1   /*!< Decryption    (Mode 3)    */
00337 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE     /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
00338 #define CRYP_PHASE_INIT                              0x00000000U     /*!< GCM/GMAC (or CCM) init phase */
00339 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0  /*!< GCM/GMAC or CCM header phase */
00340 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1  /*!< GCM(/CCM) payload phase      */
00341 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH    /*!< GCM/GMAC or CCM  final phase */
00342
00343 /*  CTR1 information to use in CCM algorithm */
00344 #define CRYP_CCM_CTR1_0                  0x07FFFFFFU
00345 #define CRYP_CCM_CTR1_1                  0xFFFFFF00U
00346 #define CRYP_CCM_CTR1_2                  0x00000001U
00347
00348 /**
00349   * @}
00350   */
00351
00352 /* Private macro -------------------------------------------------------------*/
00353 /** @addtogroup CRYP_Private_Macros
00354   * @{
00355   */
00356
00357 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__)   MODIFY_REG((__HANDLE__)->Instance->CR,\
00358                                                            AES_CR_GCMPH, (uint32_t)(__PHASE__))
00359
00360 /**
00361   * @}
00362   */
00363
00364 /* Private struct -------------------------------------------------------------*/
00365 /* Private variables ---------------------------------------------------------*/
00366 /* Private function prototypes -----------------------------------------------*/
00367 /** @addtogroup CRYP_Private_Functions
00368   * @{
00369   */
00370
00371 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00372 static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
00373 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00374 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00375 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00376 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
00377 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00378 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00379 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
00380 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
00381 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
00382 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
00383 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00384 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00385 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00386 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00387 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00388 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00389 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
00390 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00391 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00392 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
00393 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
00394 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
00395 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00396 static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00397 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00398 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
00399 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
00400 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
00401 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
00402 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize);
00403 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize);
00404 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
00405 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00406
00407
00408 /**
00409   * @}
00410   */
00411
00412 /* Exported functions ---------------------------------------------------------*/
00413
00414 /** @addtogroup CRYP_Exported_Functions
00415   * @{
00416   */
00417
00418 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00419   * @brief    Initialization and Configuration functions.
00420   *
00421 @verbatim
00422   ========================================================================================
00423      ##### Initialization, de-initialization and Set and Get configuration functions #####
00424   ========================================================================================
00425     [..]  This section provides functions allowing to:
00426       (+) Initialize the CRYP
00427       (+) DeInitialize the CRYP
00428       (+) Initialize the CRYP MSP
00429       (+) DeInitialize the CRYP MSP
00430       (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
00431           Parameters which are configured in This section are :
00432           (++) Key size
00433           (++) Data Type : 32,16, 8 or 1bit
00434           (++) AlgoMode :
00435               (+++) for CRYP1 peripheral :
00436                  ECB and CBC in DES/TDES Standard
00437                  ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
00438               (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
00439       (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
00440
00441 @endverbatim
00442   * @{
00443   */
00444
00445 /**
00446   * @brief  Initializes the CRYP according to the specified
00447   *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
00448   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00449   *         the configuration information for CRYP module
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00453 {
00454   /* Check the CRYP handle allocation */
00455   if (hcryp == NULL)
00456   {
00457     return HAL_ERROR;
00458   }
00459
00460   /* Check parameters */
00461   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00462   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00463   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
00464   assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
00465
00466 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00467   if (hcryp->State == HAL_CRYP_STATE_RESET)
00468   {
00469     /* Allocate lock resource and initialize it */
00470     hcryp->Lock = HAL_UNLOCKED;
00471
00472     hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy weak InCpltCallback   */
00473     hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback  */
00474     hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy weak ErrorCallback    */
00475
00476     if (hcryp->MspInitCallback == NULL)
00477     {
00478       hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit  */
00479     }
00480
00481     /* Init the low level hardware */
00482     hcryp->MspInitCallback(hcryp);
00483   }
00484 #else
00485   if (hcryp->State == HAL_CRYP_STATE_RESET)
00486   {
00487     /* Allocate lock resource and initialize it */
00488     hcryp->Lock = HAL_UNLOCKED;
00489
00490     /* Init the low level hardware */
00491     HAL_CRYP_MspInit(hcryp);
00492   }
00493 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00494
00495   /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */
00496   MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
00497              hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00498
00499   /* Reset Error Code field */
00500   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00501
00502   /* Reset peripheral Key and IV configuration flag */
00503   hcryp->KeyIVConfig = 0U;
00504
00505   /* Change the CRYP state */
00506   hcryp->State = HAL_CRYP_STATE_READY;
00507
00508   /* Set the default CRYP phase */
00509   hcryp->Phase = CRYP_PHASE_READY;
00510
00511   /* Return function status */
00512   return HAL_OK;
00513 }
00514
00515 /**
00516   * @brief  De-Initializes the CRYP peripheral.
00517   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00518   *         the configuration information for CRYP module
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00522 {
00523   /* Check the CRYP handle allocation */
00524   if (hcryp == NULL)
00525   {
00526     return HAL_ERROR;
00527   }
00528
00529   /* Set the default CRYP phase */
00530   hcryp->Phase = CRYP_PHASE_READY;
00531
00532   /* Reset CrypInCount and CrypOutCount */
00533   hcryp->CrypInCount = 0;
00534   hcryp->CrypOutCount = 0;
00535   hcryp->CrypHeaderCount = 0;
00536
00537   /* Disable the CRYP peripheral clock */
00538   __HAL_CRYP_DISABLE(hcryp);
00539
00540 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00541
00542   if (hcryp->MspDeInitCallback == NULL)
00543   {
00544     hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit  */
00545   }
00546   /* DeInit the low level hardware */
00547   hcryp->MspDeInitCallback(hcryp);
00548
00549 #else
00550
00551   /* DeInit the low level hardware: CLOCK, NVIC.*/
00552   HAL_CRYP_MspDeInit(hcryp);
00553
00554 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00555
00556   /* Change the CRYP state */
00557   hcryp->State = HAL_CRYP_STATE_RESET;
00558
00559   /* Release Lock */
00560   __HAL_UNLOCK(hcryp);
00561
00562   /* Return function status */
00563   return HAL_OK;
00564 }
00565
00566 /**
00567   * @brief  Configure the CRYP according to the specified
00568   *         parameters in the CRYP_ConfigTypeDef
00569   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
00570   * @param  pConf pointer to a CRYP_ConfigTypeDef structure that contains
00571   *         the configuration information for CRYP module
00572   * @retval HAL status
00573   */
00574 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00575 {
00576   /* Check the CRYP handle allocation */
00577   if ((hcryp == NULL) || (pConf == NULL))
00578   {
00579     return HAL_ERROR;
00580   }
00581
00582   /* Check parameters */
00583   assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
00584   assert_param(IS_CRYP_DATATYPE(pConf->DataType));
00585   assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
00586
00587   if (hcryp->State == HAL_CRYP_STATE_READY)
00588   {
00589     /* Change the CRYP state */
00590     hcryp->State = HAL_CRYP_STATE_BUSY;
00591
00592     /* Process locked */
00593     __HAL_LOCK(hcryp);
00594
00595     /* Set  CRYP parameters  */
00596     hcryp->Init.DataType        = pConf->DataType;
00597     hcryp->Init.pKey            = pConf->pKey;
00598     hcryp->Init.Algorithm       = pConf->Algorithm;
00599     hcryp->Init.KeySize         = pConf->KeySize;
00600     hcryp->Init.pInitVect       = pConf->pInitVect;
00601     hcryp->Init.Header          = pConf->Header;
00602     hcryp->Init.HeaderSize      = pConf->HeaderSize;
00603     hcryp->Init.B0              = pConf->B0;
00604     hcryp->Init.DataWidthUnit   = pConf->DataWidthUnit;
00605     hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
00606     hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
00607
00608     /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
00609     MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
00610                hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00611
00612     /*clear error flags*/
00613     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
00614
00615     /* Process Unlocked */
00616     __HAL_UNLOCK(hcryp);
00617
00618     /* Reset Error Code field */
00619     hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00620
00621     /* Change the CRYP state */
00622     hcryp->State = HAL_CRYP_STATE_READY;
00623
00624     /* Set the default CRYP phase */
00625     hcryp->Phase = CRYP_PHASE_READY;
00626
00627     /* Return function status */
00628     return HAL_OK;
00629   }
00630   else
00631   {
00632     /* Process Unlocked */
00633     __HAL_UNLOCK(hcryp);
00634
00635     /* Busy error code field */
00636     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00637     return HAL_ERROR;
00638   }
00639 }
00640
00641 /**
00642   * @brief  Get CRYP Configuration parameters in associated handle.
00643   * @param  pConf pointer to a CRYP_ConfigTypeDef structure
00644   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00645   *         the configuration information for CRYP module
00646   * @retval HAL status
00647   */
00648 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00649 {
00650   /* Check the CRYP handle allocation */
00651   if ((hcryp == NULL) || (pConf == NULL))
00652   {
00653     return HAL_ERROR;
00654   }
00655
00656   if (hcryp->State == HAL_CRYP_STATE_READY)
00657   {
00658     /* Change the CRYP state */
00659     hcryp->State = HAL_CRYP_STATE_BUSY;
00660
00661     /* Process locked */
00662     __HAL_LOCK(hcryp);
00663
00664     /* Get  CRYP parameters  */
00665     pConf->DataType        = hcryp->Init.DataType;
00666     pConf->pKey            = hcryp->Init.pKey;
00667     pConf->Algorithm       = hcryp->Init.Algorithm;
00668     pConf->KeySize         = hcryp->Init.KeySize ;
00669     pConf->pInitVect       = hcryp->Init.pInitVect;
00670     pConf->Header          = hcryp->Init.Header ;
00671     pConf->HeaderSize      = hcryp->Init.HeaderSize;
00672     pConf->B0              = hcryp->Init.B0;
00673     pConf->DataWidthUnit   = hcryp->Init.DataWidthUnit;
00674     pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
00675     pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(hcryp);
00679
00680     /* Change the CRYP state */
00681     hcryp->State = HAL_CRYP_STATE_READY;
00682
00683     /* Return function status */
00684     return HAL_OK;
00685   }
00686   else
00687   {
00688     /* Process Unlocked */
00689     __HAL_UNLOCK(hcryp);
00690
00691     /* Busy error code field */
00692     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00693     return HAL_ERROR;
00694   }
00695 }
00696 /**
00697   * @brief  Initializes the CRYP MSP.
00698   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00699   *         the configuration information for CRYP module
00700   * @retval None
00701   */
00702 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00703 {
00704   /* Prevent unused argument(s) compilation warning */
00705   UNUSED(hcryp);
00706
00707   /* NOTE : This function should not be modified; when the callback is needed,
00708             the HAL_CRYP_MspInit can be implemented in the user file
00709    */
00710 }
00711
00712 /**
00713   * @brief  DeInitializes CRYP MSP.
00714   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00715   *         the configuration information for CRYP module
00716   * @retval None
00717   */
00718 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00719 {
00720   /* Prevent unused argument(s) compilation warning */
00721   UNUSED(hcryp);
00722
00723   /* NOTE : This function should not be modified; when the callback is needed,
00724             the HAL_CRYP_MspDeInit can be implemented in the user file
00725    */
00726 }
00727
00728 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00729 /**
00730   * @brief  Register a User CRYP Callback
00731   *         To be used instead of the weak predefined callback
00732   * @param hcryp cryp handle
00733   * @param CallbackID ID of the callback to be registered
00734   *        This parameter can be one of the following values:
00735   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00736   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00737   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00738   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00739   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00740   * @param pCallback pointer to the Callback function
00741   * @retval status
00742   */
00743 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
00744                                             pCRYP_CallbackTypeDef pCallback)
00745 {
00746   HAL_StatusTypeDef status = HAL_OK;
00747
00748   if (pCallback == NULL)
00749   {
00750     /* Update the error code */
00751     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00752
00753     return HAL_ERROR;
00754   }
00755   /* Process locked */
00756   __HAL_LOCK(hcryp);
00757
00758   if (hcryp->State == HAL_CRYP_STATE_READY)
00759   {
00760     switch (CallbackID)
00761     {
00762       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00763         hcryp->InCpltCallback = pCallback;
00764         break;
00765
00766       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00767         hcryp->OutCpltCallback = pCallback;
00768         break;
00769
00770       case HAL_CRYP_ERROR_CB_ID :
00771         hcryp->ErrorCallback = pCallback;
00772         break;
00773
00774       case HAL_CRYP_MSPINIT_CB_ID :
00775         hcryp->MspInitCallback = pCallback;
00776         break;
00777
00778       case HAL_CRYP_MSPDEINIT_CB_ID :
00779         hcryp->MspDeInitCallback = pCallback;
00780         break;
00781
00782       default :
00783         /* Update the error code */
00784         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00785         /* Return error status */
00786         status =  HAL_ERROR;
00787         break;
00788     }
00789   }
00790   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00791   {
00792     switch (CallbackID)
00793     {
00794       case HAL_CRYP_MSPINIT_CB_ID :
00795         hcryp->MspInitCallback = pCallback;
00796         break;
00797
00798       case HAL_CRYP_MSPDEINIT_CB_ID :
00799         hcryp->MspDeInitCallback = pCallback;
00800         break;
00801
00802       default :
00803         /* Update the error code */
00804         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00805         /* Return error status */
00806         status =  HAL_ERROR;
00807         break;
00808     }
00809   }
00810   else
00811   {
00812     /* Update the error code */
00813     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00814     /* Return error status */
00815     status =  HAL_ERROR;
00816   }
00817
00818   /* Release Lock */
00819   __HAL_UNLOCK(hcryp);
00820
00821   return status;
00822 }
00823
00824 /**
00825   * @brief  Unregister an CRYP Callback
00826   *         CRYP callback is redirected to the weak predefined callback
00827   * @param hcryp cryp handle
00828   * @param CallbackID ID of the callback to be unregistered
00829   *        This parameter can be one of the following values:
00830   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00831   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00832   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00833   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00834   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00835   * @retval status
00836   */
00837 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
00838 {
00839   HAL_StatusTypeDef status = HAL_OK;
00840
00841   /* Process locked */
00842   __HAL_LOCK(hcryp);
00843
00844   if (hcryp->State == HAL_CRYP_STATE_READY)
00845   {
00846     switch (CallbackID)
00847     {
00848       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00849         hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
00850         break;
00851
00852       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00853         hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;         /* Legacy weak OutCpltCallback       */
00854         break;
00855
00856       case HAL_CRYP_ERROR_CB_ID :
00857         hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;           /* Legacy weak ErrorCallback        */
00858         break;
00859
00860       case HAL_CRYP_MSPINIT_CB_ID :
00861         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00862         break;
00863
00864       case HAL_CRYP_MSPDEINIT_CB_ID :
00865         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00866         break;
00867
00868       default :
00869         /* Update the error code */
00870         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00871         /* Return error status */
00872         status =  HAL_ERROR;
00873         break;
00874     }
00875   }
00876   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00877   {
00878     switch (CallbackID)
00879     {
00880       case HAL_CRYP_MSPINIT_CB_ID :
00881         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00882         break;
00883
00884       case HAL_CRYP_MSPDEINIT_CB_ID :
00885         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00886         break;
00887
00888       default :
00889         /* Update the error code */
00890         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00891         /* Return error status */
00892         status =  HAL_ERROR;
00893         break;
00894     }
00895   }
00896   else
00897   {
00898     /* Update the error code */
00899     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
00900     /* Return error status */
00901     status =  HAL_ERROR;
00902   }
00903
00904   /* Release Lock */
00905   __HAL_UNLOCK(hcryp);
00906
00907   return status;
00908 }
00909 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00910
00911 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00912 /**
00913   * @brief  Request CRYP processing suspension when in interruption mode.
00914   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00915   *         the configuration information for CRYP module.
00916   * @note   Set the handle field SuspendRequest to the appropriate value so that
00917   *         the on-going CRYP processing is suspended as soon as the required
00918   *         conditions are met.
00919   * @note   HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
00920   *         in non-blocking interrupt mode.
00921   * @note   It is advised not to suspend the CRYP processing when the DMA controller
00922   *         is managing the data transfer.
00923   * @retval None
00924   */
00925 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
00926 {
00927   /* Set Handle SuspendRequest field */
00928   hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
00929 }
00930
00931
00932
00933 /**
00934   * @brief  CRYP processing suspension and peripheral internal parameters storage.
00935   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00936   *         the configuration information for CRYP module
00937   * @note   peripheral internal parameters are stored to be readily available when
00938   *         suspended processing is resumed later on.
00939   * @retval HAL status
00940   */
00941 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
00942 {
00943   HAL_CRYP_STATETypeDef state;
00944
00945   /* Request suspension */
00946   HAL_CRYP_ProcessSuspend(hcryp);
00947
00948   do
00949   {
00950     state = HAL_CRYP_GetState(hcryp);
00951   } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
00952
00953   if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
00954   {
00955     /* Processing was already over or was about to end. No suspension done */
00956     return HAL_ERROR;
00957   }
00958   else
00959   {
00960     /* Suspend Processing */
00961
00962     /* If authentication algorithms on-going, carry out first saving steps
00963        before disable the peripheral */
00964     if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
00965         (hcryp->Init.Algorithm == CRYP_AES_CCM))
00966     {
00967       /* Save Suspension registers */
00968       CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
00969       /* Save Key */
00970       CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
00971       /* Save IV */
00972       CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00973     }
00974     /* Disable AES */
00975     __HAL_CRYP_DISABLE(hcryp);
00976
00977     /* Save low-priority block CRYP handle parameters */
00978     hcryp->Init_saved              = hcryp->Init;
00979     hcryp->pCrypInBuffPtr_saved    = hcryp->pCrypInBuffPtr;
00980     hcryp->pCrypOutBuffPtr_saved   = hcryp->pCrypOutBuffPtr;
00981     hcryp->CrypInCount_saved       = hcryp->CrypInCount;
00982     hcryp->CrypOutCount_saved      = hcryp->CrypOutCount;
00983     hcryp->Phase_saved             = hcryp->Phase;
00984     hcryp->State_saved             = hcryp->State;
00985     hcryp->Size_saved              = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
00986                                       (hcryp->Size / 4U) : hcryp->Size);
00987     hcryp->SizesSum_saved          = hcryp->SizesSum;
00988     hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
00989     hcryp->CrypHeaderCount_saved   = hcryp->CrypHeaderCount;
00990     hcryp->SuspendRequest          = HAL_CRYP_SUSPEND_NONE;
00991
00992     if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
00993         (hcryp->Init.Algorithm == CRYP_AES_CTR))
00994     {
00995       /* Save Initialisation Vector registers */
00996       CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00997     }
00998
00999     /* Save Control register */
01000     hcryp->CR_saved = hcryp->Instance->CR;
01001
01002   }
01003   return HAL_OK;
01004 }
01005
01006
01007 /**
01008   * @brief  CRYP processing resumption.
01009   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01010   *         the configuration information for CRYP module
01011   * @note   Processing restarts at the exact point where it was suspended, based
01012   *         on the parameters saved at suspension time.
01013   * @retval HAL status
01014   */
01015 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
01016 {
01017   /* Check the CRYP handle allocation */
01018   if (hcryp == NULL)
01019   {
01020     return HAL_ERROR;
01021   }
01022
01023   if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
01024   {
01025     /* CRYP was not suspended */
01026     return HAL_ERROR;
01027   }
01028   else
01029   {
01030
01031     /* Restore low-priority block CRYP handle parameters */
01032     hcryp->Init            = hcryp->Init_saved;
01033     hcryp->State           = hcryp->State_saved;
01034
01035     /* Chaining algorithms case */
01036     if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \
01037         (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \
01038         (hcryp->Init_saved.Algorithm == CRYP_AES_CTR))
01039     {
01040       /* Restore low-priority block CRYP handle parameters */
01041       hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved;
01042
01043       if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
01044           (hcryp->Init.Algorithm == CRYP_AES_CTR))
01045       {
01046         hcryp->Init.pInitVect     = hcryp->IV_saved;
01047       }
01048       __HAL_CRYP_DISABLE(hcryp);
01049       (void) HAL_CRYP_Init(hcryp);
01050     }
01051     else    /* Authentication algorithms case */
01052     {
01053       /* Restore low-priority block CRYP handle parameters */
01054       hcryp->Phase           = hcryp->Phase_saved;
01055       hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
01056       hcryp->SizesSum        = hcryp->SizesSum_saved;
01057
01058       /* Disable AES and write-back SUSPxR registers */;
01059       __HAL_CRYP_DISABLE(hcryp);
01060       /* Restore AES Suspend Registers */
01061       CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
01062       /* Restore Control,  Key and IV Registers, then enable AES */
01063       hcryp->Instance->CR = hcryp->CR_saved;
01064       CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
01065       CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
01066
01067       /* At the same time, set handle state back to READY to be able to resume the AES calculations
01068       without the processing APIs returning HAL_BUSY when called. */
01069       hcryp->State        = HAL_CRYP_STATE_READY;
01070     }
01071
01072
01073     /* Resume low-priority block processing under IT */
01074     hcryp->ResumingFlag = 1U;
01075     if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
01076     {
01077       if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
01078                               hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01079       {
01080         return HAL_ERROR;
01081       }
01082     }
01083     else
01084     {
01085       if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
01086                               hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01087       {
01088         return HAL_ERROR;
01089       }
01090     }
01091   }
01092   return HAL_OK;
01093 }
01094 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
01095
01096 /**
01097   * @}
01098   */
01099
01100 /** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions
01101   * @brief    Encryption Decryption functions.
01102   *
01103 @verbatim
01104   ==============================================================================
01105                       ##### Encrypt Decrypt  functions #####
01106   ==============================================================================
01107     [..]  This section provides API allowing to Encrypt/Decrypt Data following
01108           Standard DES/TDES or AES, and Algorithm configured by the user:
01109       (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported :
01110            - Electronic Code Book(ECB)
01111            - Cipher Block Chaining (CBC)
01112       (+) Standard AES  supported by CRYP1 peripheral & TinyAES, list of Algorithm supported:
01113            - Electronic Code Book(ECB)
01114            - Cipher Block Chaining (CBC)
01115            - Counter mode (CTR)
01116            - Cipher Block Chaining (CBC)
01117            - Counter mode (CTR)
01118            - Galois/counter mode (GCM)
01119            - Counter with Cipher Block Chaining-Message(CCM)
01120     [..]  Three processing functions are available:
01121       (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
01122       (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
01123       (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
01124
01125 @endverbatim
01126   * @{
01127   */
01128
01129 /* GCM message structure additional details
01130
01131                                   ICB
01132           +-------------------------------------------------------+
01133           |       Initialization vector (IV)      |  Counter      |
01134           |----------------|----------------|-----------|---------|
01135          127              95                63            31       0
01136
01137
01138               Bit Number    Register           Contents
01139               ----------   ---------------       -----------
01140               127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
01141               95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01142               63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
01143               31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
01144
01145
01146
01147                                  GCM last block definition
01148           +-------------------------------------------------------------------+
01149           |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
01150           |-----------|--------------------|-----------|----------------------|
01151           |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
01152           |-----------|--------------------|-----------|----------------------|
01153
01154 */
01155
01156 /* CCM message blocks description
01157
01158          (##) B0 block  : According to NIST Special Publication 800-38C,
01159             The first block B0 is formatted as follows, where l(m) is encoded in
01160             most-significant-byte first order:
01161
01162                 Octet Number   Contents
01163                 ------------   ---------
01164                 0              Flags
01165                 1 ... 15-q     Nonce N
01166                 16-q ... 15    Q
01167
01168             the Flags field is formatted as follows:
01169
01170                 Bit Number   Contents
01171                 ----------   ----------------------
01172                 7            Reserved (always zero)
01173                 6            Adata
01174                 5 ... 3      (t-2)/2
01175                 2 ... 0      [q-1]3
01176
01177               - Q: a bit string representation of the octet length of P (plaintext)
01178               - q The octet length of the binary representation of the octet length of the payload
01179               - A nonce (N), n The octet length of the where n+q=15.
01180               - Flags: most significant octet containing four flags for control information,
01181               - t The octet length of the MAC.
01182          (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
01183               the associated data length expressed in bytes (a) defined as below:
01184             - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
01185             - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
01186             - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
01187          (##) CTRx block  : control blocks
01188             - Generation of CTR1 from first block B0 information :
01189               equal to B0 with first 5 bits zeroed and most significant bits storing octet
01190               length of P also zeroed, then incremented by one
01191
01192                 Bit Number    Register           Contents
01193                 ----------   ---------------       -----------
01194                 127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
01195                                                  bit 0 that is set to 1
01196                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01197                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
01198                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
01199
01200             - Generation of CTR0: same as CTR1 with bit[0] set to zero.
01201
01202 */
01203
01204 /**
01205   * @brief  Encryption mode.
01206   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01207   *         the configuration information for CRYP module
01208   * @param  Input Pointer to the input buffer (plaintext)
01209   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01210   * @param  Output Pointer to the output buffer(ciphertext)
01211   * @param  Timeout Specify Timeout value
01212   * @retval HAL status
01213   */
01214 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
01215                                    uint32_t Timeout)
01216 {
01217   uint32_t algo;
01218   HAL_StatusTypeDef status;
01219 #ifdef  USE_FULL_ASSERT
01220   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01221
01222   /* Check input buffer size */
01223   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01224 #endif /* USE_FULL_ASSERT */
01225
01226   if (hcryp->State == HAL_CRYP_STATE_READY)
01227   {
01228     /* Change state Busy */
01229     hcryp->State = HAL_CRYP_STATE_BUSY;
01230
01231     /* Process locked */
01232     __HAL_LOCK(hcryp);
01233
01234     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01235     hcryp->CrypInCount = 0U;
01236     hcryp->CrypOutCount = 0U;
01237     hcryp->pCrypInBuffPtr = Input;
01238     hcryp->pCrypOutBuffPtr = Output;
01239
01240     /*  Calculate Size parameter in Byte*/
01241     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01242     {
01243       hcryp->Size = Size * 4U;
01244     }
01245     else
01246     {
01247       hcryp->Size = Size;
01248     }
01249
01250     /* Set the operating mode*/
01251     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01252
01253     /* algo get algorithm selected */
01254     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01255
01256     switch (algo)
01257     {
01258
01259       case CRYP_AES_ECB:
01260       case CRYP_AES_CBC:
01261       case CRYP_AES_CTR:
01262
01263         /* AES encryption */
01264         status = CRYP_AES_Encrypt(hcryp, Timeout);
01265         break;
01266
01267       case CRYP_AES_GCM_GMAC:
01268
01269         /* AES GCM encryption */
01270         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01271         break;
01272
01273       case CRYP_AES_CCM:
01274
01275         /* AES CCM encryption */
01276         status = CRYP_AESCCM_Process(hcryp, Timeout);
01277         break;
01278
01279       default:
01280         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01281         status = HAL_ERROR;
01282         break;
01283     }
01284
01285     if (status == HAL_OK)
01286     {
01287       /* Change the CRYP peripheral state */
01288       hcryp->State = HAL_CRYP_STATE_READY;
01289
01290       /* Process unlocked */
01291       __HAL_UNLOCK(hcryp);
01292     }
01293   }
01294   else
01295   {
01296     /* Busy error code field */
01297     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01298     status = HAL_ERROR;
01299   }
01300
01301   /* Return function status */
01302   return status;
01303 }
01304
01305 /**
01306   * @brief  Decryption mode.
01307   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01308   *         the configuration information for CRYP module
01309   * @param  Input Pointer to the input buffer (ciphertext )
01310   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01311   * @param  Output Pointer to the output buffer(plaintext)
01312   * @param  Timeout Specify Timeout value
01313   * @retval HAL status
01314   */
01315 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
01316                                    uint32_t Timeout)
01317 {
01318   HAL_StatusTypeDef status;
01319   uint32_t algo;
01320 #ifdef  USE_FULL_ASSERT
01321   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01322
01323   /* Check input buffer size */
01324   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01325 #endif /* USE_FULL_ASSERT */
01326
01327   if (hcryp->State == HAL_CRYP_STATE_READY)
01328   {
01329     /* Change state Busy */
01330     hcryp->State = HAL_CRYP_STATE_BUSY;
01331
01332     /* Process locked */
01333     __HAL_LOCK(hcryp);
01334
01335     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr  parameters*/
01336     hcryp->CrypInCount = 0U;
01337     hcryp->CrypOutCount = 0U;
01338     hcryp->pCrypInBuffPtr = Input;
01339     hcryp->pCrypOutBuffPtr = Output;
01340
01341     /*  Calculate Size parameter in Byte*/
01342     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01343     {
01344       hcryp->Size = Size * 4U;
01345     }
01346     else
01347     {
01348       hcryp->Size = Size;
01349     }
01350
01351     /* Set Decryption operating mode*/
01352     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01353
01354     /* algo get algorithm selected */
01355     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01356
01357     switch (algo)
01358     {
01359
01360       case CRYP_AES_ECB:
01361       case CRYP_AES_CBC:
01362       case CRYP_AES_CTR:
01363
01364         /* AES decryption */
01365         status = CRYP_AES_Decrypt(hcryp, Timeout);
01366         break;
01367
01368       case CRYP_AES_GCM_GMAC:
01369
01370         /* AES GCM decryption */
01371         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01372         break;
01373
01374       case CRYP_AES_CCM:
01375
01376         /* AES CCM decryption */
01377         status = CRYP_AESCCM_Process(hcryp, Timeout);
01378         break;
01379
01380       default:
01381         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01382         status = HAL_ERROR;
01383         break;
01384     }
01385
01386     if (status == HAL_OK)
01387     {
01388       /* Change the CRYP peripheral state */
01389       hcryp->State = HAL_CRYP_STATE_READY;
01390
01391       /* Process unlocked */
01392       __HAL_UNLOCK(hcryp);
01393     }
01394   }
01395   else
01396   {
01397     /* Busy error code field */
01398     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01399     status = HAL_ERROR;
01400   }
01401
01402   /* Return function status */
01403   return status;
01404 }
01405
01406 /**
01407   * @brief  Encryption in interrupt mode.
01408   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01409   *         the configuration information for CRYP module
01410   * @param  Input Pointer to the input buffer (plaintext)
01411   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01412   * @param  Output Pointer to the output buffer(ciphertext)
01413   * @retval HAL status
01414   */
01415 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01416 {
01417   HAL_StatusTypeDef status;
01418   uint32_t algo;
01419 #ifdef  USE_FULL_ASSERT
01420   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01421
01422   /* Check input buffer size */
01423   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01424 #endif /* USE_FULL_ASSERT */
01425
01426   if (hcryp->State == HAL_CRYP_STATE_READY)
01427   {
01428     /* Change state Busy */
01429     hcryp->State = HAL_CRYP_STATE_BUSY;
01430
01431     /* Process locked */
01432     __HAL_LOCK(hcryp);
01433
01434     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01435 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01436     if (hcryp->ResumingFlag == 1U)
01437     {
01438       hcryp->ResumingFlag = 0U;
01439       if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01440       {
01441         hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01442         hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01443       }
01444       else
01445       {
01446         hcryp->CrypInCount = 0U;
01447         hcryp->CrypOutCount = 0U;
01448       }
01449     }
01450     else
01451 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01452     {
01453       hcryp->CrypInCount = 0U;
01454       hcryp->CrypOutCount = 0U;
01455     }
01456
01457     hcryp->pCrypInBuffPtr = Input;
01458     hcryp->pCrypOutBuffPtr = Output;
01459
01460     /*  Calculate Size parameter in Byte*/
01461     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01462     {
01463       hcryp->Size = Size * 4U;
01464     }
01465     else
01466     {
01467       hcryp->Size = Size;
01468     }
01469
01470     /* Set encryption operating mode*/
01471     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01472
01473     /* algo get algorithm selected */
01474     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01475
01476     switch (algo)
01477     {
01478
01479       case CRYP_AES_ECB:
01480       case CRYP_AES_CBC:
01481       case CRYP_AES_CTR:
01482
01483         /* AES encryption */
01484         status = CRYP_AES_Encrypt_IT(hcryp);
01485         break;
01486
01487       case CRYP_AES_GCM_GMAC:
01488
01489         /* AES GCM encryption */
01490         status = CRYP_AESGCM_Process_IT(hcryp) ;
01491         break;
01492
01493       case CRYP_AES_CCM:
01494
01495         /* AES CCM encryption */
01496         status = CRYP_AESCCM_Process_IT(hcryp);
01497         break;
01498
01499       default:
01500         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01501         status = HAL_ERROR;
01502         break;
01503     }
01504   }
01505   else
01506   {
01507     /* Busy error code field */
01508     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01509     status = HAL_ERROR;
01510   }
01511
01512   /* Return function status */
01513   return status;
01514 }
01515
01516 /**
01517   * @brief  Decryption in interrupt mode.
01518   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01519   *         the configuration information for CRYP module
01520   * @param  Input Pointer to the input buffer (ciphertext )
01521   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01522   * @param  Output Pointer to the output buffer(plaintext)
01523   * @retval HAL status
01524   */
01525 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01526 {
01527   HAL_StatusTypeDef status;
01528   uint32_t algo;
01529 #ifdef  USE_FULL_ASSERT
01530   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01531
01532   /* Check input buffer size */
01533   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01534 #endif /* USE_FULL_ASSERT */
01535
01536   if (hcryp->State == HAL_CRYP_STATE_READY)
01537   {
01538     /* Change state Busy */
01539     hcryp->State = HAL_CRYP_STATE_BUSY;
01540
01541     /* Process locked */
01542     __HAL_LOCK(hcryp);
01543
01544     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01545 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01546     if (hcryp->ResumingFlag == 1U)
01547     {
01548       hcryp->ResumingFlag = 0U;
01549       if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01550       {
01551         hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01552         hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01553       }
01554       else
01555       {
01556         hcryp->CrypInCount = 0U;
01557         hcryp->CrypOutCount = 0U;
01558       }
01559     }
01560     else
01561 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01562     {
01563       hcryp->CrypInCount = 0U;
01564       hcryp->CrypOutCount = 0U;
01565     }
01566     hcryp->pCrypInBuffPtr = Input;
01567     hcryp->pCrypOutBuffPtr = Output;
01568
01569     /*  Calculate Size parameter in Byte*/
01570     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01571     {
01572       hcryp->Size = Size * 4U;
01573     }
01574     else
01575     {
01576       hcryp->Size = Size;
01577     }
01578
01579     /* Set decryption operating mode*/
01580     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01581
01582     /* algo get algorithm selected */
01583     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01584
01585     switch (algo)
01586     {
01587
01588       case CRYP_AES_ECB:
01589       case CRYP_AES_CBC:
01590       case CRYP_AES_CTR:
01591
01592         /* AES decryption */
01593         status = CRYP_AES_Decrypt_IT(hcryp);
01594         break;
01595
01596       case CRYP_AES_GCM_GMAC:
01597
01598         /* AES GCM decryption */
01599         status = CRYP_AESGCM_Process_IT(hcryp) ;
01600         break;
01601
01602       case CRYP_AES_CCM:
01603
01604         /* AES CCM decryption */
01605         status = CRYP_AESCCM_Process_IT(hcryp);
01606         break;
01607
01608       default:
01609         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01610         status = HAL_ERROR;
01611         break;
01612     }
01613   }
01614   else
01615   {
01616     /* Busy error code field */
01617     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01618     status = HAL_ERROR;
01619   }
01620
01621   /* Return function status */
01622   return status;
01623 }
01624
01625 /**
01626   * @brief  Encryption in DMA mode.
01627   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01628   *         the configuration information for CRYP module
01629   * @param  Input Pointer to the input buffer (plaintext)
01630   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01631   * @param  Output Pointer to the output buffer(ciphertext)
01632   * @retval HAL status
01633   */
01634 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01635 {
01636   HAL_StatusTypeDef status;
01637   uint32_t algo;
01638   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
01639 #ifdef  USE_FULL_ASSERT
01640   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01641
01642   /* Check input buffer size */
01643   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01644 #endif /* USE_FULL_ASSERT */
01645
01646   if (hcryp->State == HAL_CRYP_STATE_READY)
01647   {
01648     /* Change state Busy */
01649     hcryp->State = HAL_CRYP_STATE_BUSY;
01650
01651     /* Process locked */
01652     __HAL_LOCK(hcryp);
01653
01654     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01655     hcryp->CrypInCount = 0U;
01656     hcryp->CrypOutCount = 0U;
01657     hcryp->pCrypInBuffPtr = Input;
01658     hcryp->pCrypOutBuffPtr = Output;
01659
01660     /*  Calculate Size parameter in Byte*/
01661     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01662     {
01663       hcryp->Size = Size * 4U;
01664     }
01665     else
01666     {
01667       hcryp->Size = Size;
01668     }
01669
01670     /* Set encryption operating mode*/
01671     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01672
01673     /* algo get algorithm selected */
01674     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01675
01676     switch (algo)
01677     {
01678
01679       case CRYP_AES_ECB:
01680       case CRYP_AES_CBC:
01681       case CRYP_AES_CTR:
01682
01683         if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
01684         {
01685           if (hcryp->KeyIVConfig == 1U)
01686           {
01687             /* If the Key and IV configuration has to be done only once
01688                and if it has already been done, skip it */
01689             DoKeyIVConfig = 0U;
01690           }
01691           else
01692           {
01693             /* If the Key and IV configuration has to be done only once
01694                and if it has not been done already, do it and set KeyIVConfig
01695                to keep track it won't have to be done again next time */
01696             hcryp->KeyIVConfig = 1U;
01697           }
01698         }
01699
01700         if (DoKeyIVConfig == 1U)
01701         {
01702           /*  Set the Key*/
01703           CRYP_SetKey(hcryp, hcryp->Init.KeySize);
01704
01705           /* Set the Initialization Vector*/
01706           if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01707           {
01708             hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
01709             hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
01710             hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
01711             hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
01712           }
01713         } /* if (DoKeyIVConfig == 1U) */
01714
01715         /* Set the phase */
01716         hcryp->Phase = CRYP_PHASE_PROCESS;
01717
01718         /* Start DMA process transfer for AES */
01719         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \
01720                           (uint32_t)(hcryp->pCrypOutBuffPtr));
01721         status = HAL_OK;
01722         break;
01723
01724       case CRYP_AES_GCM_GMAC:
01725
01726         /* AES GCM encryption */
01727         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01728         break;
01729
01730       case CRYP_AES_CCM:
01731
01732         /* AES CCM encryption */
01733         status = CRYP_AESCCM_Process_DMA(hcryp);
01734         break;
01735
01736       default:
01737         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01738         status = HAL_ERROR;
01739         break;
01740     }
01741   }
01742   else
01743   {
01744     /* Busy error code field */
01745     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01746     status = HAL_ERROR;
01747   }
01748
01749   /* Return function status */
01750   return status;
01751 }
01752
01753 /**
01754   * @brief  Decryption in DMA mode.
01755   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01756   *         the configuration information for CRYP module
01757   * @param  Input Pointer to the input buffer (ciphertext )
01758   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01759   * @param  Output Pointer to the output buffer(plaintext)
01760   * @retval HAL status
01761   */
01762 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01763 {
01764   HAL_StatusTypeDef status;
01765   uint32_t algo;
01766 #ifdef  USE_FULL_ASSERT
01767   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01768
01769   /* Check input buffer size */
01770   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01771 #endif /* USE_FULL_ASSERT */
01772
01773   if (hcryp->State == HAL_CRYP_STATE_READY)
01774   {
01775
01776     /* Change state Busy */
01777     hcryp->State = HAL_CRYP_STATE_BUSY;
01778
01779     /* Process locked */
01780     __HAL_LOCK(hcryp);
01781
01782     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01783     hcryp->CrypInCount = 0U;
01784     hcryp->CrypOutCount = 0U;
01785     hcryp->pCrypInBuffPtr = Input;
01786     hcryp->pCrypOutBuffPtr = Output;
01787
01788     /*  Calculate Size parameter in Byte*/
01789     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01790     {
01791       hcryp->Size = Size * 4U;
01792     }
01793     else
01794     {
01795       hcryp->Size = Size;
01796     }
01797
01798     /* Set decryption operating mode*/
01799     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01800
01801     /* algo get algorithm selected */
01802     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01803
01804     switch (algo)
01805     {
01806
01807       case CRYP_AES_ECB:
01808       case CRYP_AES_CBC:
01809       case CRYP_AES_CTR:
01810
01811         /* AES decryption */
01812         status = CRYP_AES_Decrypt_DMA(hcryp);
01813         break;
01814
01815       case CRYP_AES_GCM_GMAC:
01816
01817         /* AES GCM decryption */
01818         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01819         break;
01820
01821       case CRYP_AES_CCM:
01822
01823         /* AES CCM decryption */
01824         status = CRYP_AESCCM_Process_DMA(hcryp);
01825         break;
01826
01827       default:
01828         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01829         status = HAL_ERROR;
01830         break;
01831     }
01832   }
01833   else
01834   {
01835     /* Busy error code field */
01836     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01837     status = HAL_ERROR;
01838   }
01839   /* Return function status */
01840   return status;
01841 }
01842
01843 /**
01844   * @}
01845   */
01846
01847 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
01848   * @brief    CRYP IRQ handler.
01849   *
01850 @verbatim
01851   ==============================================================================
01852                 ##### CRYP IRQ handler management #####
01853   ==============================================================================
01854 [..]  This section provides CRYP IRQ handler and callback functions.
01855       (+) HAL_CRYP_IRQHandler CRYP interrupt request
01856       (+) HAL_CRYP_InCpltCallback input data transfer complete callback
01857       (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
01858       (+) HAL_CRYP_ErrorCallback  CRYP error callback
01859       (+) HAL_CRYP_GetState return the CRYP state
01860       (+) HAL_CRYP_GetError return the CRYP error code
01861 @endverbatim
01862   * @{
01863   */
01864
01865 /**
01866   * @brief  This function handles cryptographic interrupt request.
01867   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01868   *         the configuration information for CRYP module
01869   * @retval None
01870   */
01871 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01872 {
01873   uint32_t itsource = hcryp->Instance->CR;
01874   uint32_t itflag   = hcryp->Instance->SR;
01875
01876   /* Check if error occurred */
01877   if ((itsource & CRYP_IT_ERRIE) != RESET)
01878   {
01879     /* If write Error occurred */
01880     if ((itflag & CRYP_IT_WRERR) != RESET)
01881     {
01882       hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
01883     }
01884     /* If read Error occurred */
01885     if ((itflag & CRYP_IT_RDERR) != RESET)
01886     {
01887       hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
01888     }
01889   }
01890
01891   if ((itflag & CRYP_IT_CCF) != RESET)
01892   {
01893     if ((itsource & CRYP_IT_CCFIE) != RESET)
01894     {
01895       /* Clear computation complete flag */
01896       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
01897
01898       if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
01899       {
01900
01901         /* if header phase */
01902         if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
01903         {
01904           CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01905         }
01906         else  /* if payload phase */
01907         {
01908           CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01909         }
01910       }
01911       else  /* AES Algorithm ECB,CBC or CTR*/
01912       {
01913         CRYP_AES_IT(hcryp);
01914       }
01915     }
01916   }
01917 }
01918
01919 /**
01920   * @brief  Return the CRYP error code.
01921   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01922   *                 the configuration information for the  CRYP peripheral
01923   * @retval CRYP error code
01924   */
01925 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01926 {
01927   return hcryp->ErrorCode;
01928 }
01929
01930 /**
01931   * @brief  Returns the CRYP state.
01932   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01933   *         the configuration information for CRYP module.
01934   * @retval HAL state
01935   */
01936 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01937 {
01938   return hcryp->State;
01939 }
01940
01941 /**
01942   * @brief  Input FIFO transfer completed callback.
01943   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01944   *         the configuration information for CRYP module.
01945   * @retval None
01946   */
01947 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01948 {
01949   /* Prevent unused argument(s) compilation warning */
01950   UNUSED(hcryp);
01951
01952   /* NOTE : This function should not be modified; when the callback is needed,
01953             the HAL_CRYP_InCpltCallback can be implemented in the user file
01954    */
01955 }
01956
01957 /**
01958   * @brief  Output FIFO transfer completed callback.
01959   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01960   *         the configuration information for CRYP module.
01961   * @retval None
01962   */
01963 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01964 {
01965   /* Prevent unused argument(s) compilation warning */
01966   UNUSED(hcryp);
01967
01968   /* NOTE : This function should not be modified; when the callback is needed,
01969             the HAL_CRYP_OutCpltCallback can be implemented in the user file
01970    */
01971 }
01972
01973 /**
01974   * @brief  CRYP error callback.
01975   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01976   *         the configuration information for CRYP module.
01977   * @retval None
01978   */
01979 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01980 {
01981   /* Prevent unused argument(s) compilation warning */
01982   UNUSED(hcryp);
01983
01984   /* NOTE : This function should not be modified; when the callback is needed,
01985             the HAL_CRYP_ErrorCallback can be implemented in the user file
01986    */
01987 }
01988 /**
01989   * @}
01990   */
01991
01992 /**
01993   * @}
01994   */
01995
01996 /* Private functions ---------------------------------------------------------*/
01997 /** @addtogroup CRYP_Private_Functions
01998   * @{
01999   */
02000
02001 /**
02002   * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
02003   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
02004   * @param  Timeout specify Timeout value
02005   * @retval HAL status
02006   */
02007 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02008 {
02009   uint16_t incount;  /* Temporary CrypInCount Value */
02010   uint16_t outcount;  /* Temporary CrypOutCount Value */
02011   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02012
02013   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02014   {
02015     if (hcryp->KeyIVConfig == 1U)
02016     {
02017       /* If the Key and IV configuration has to be done only once
02018          and if it has already been done, skip it */
02019       DoKeyIVConfig = 0U;
02020     }
02021     else
02022     {
02023       /* If the Key and IV configuration has to be done only once
02024          and if it has not been done already, do it and set KeyIVConfig
02025          to keep track it won't have to be done again next time */
02026       hcryp->KeyIVConfig = 1U;
02027     }
02028   }
02029
02030   if (DoKeyIVConfig == 1U)
02031   {
02032     /*  Set the Key*/
02033     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02034
02035     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02036     {
02037       /* Set the Initialization Vector*/
02038       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02039       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02040       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02041       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02042     }
02043   } /* if (DoKeyIVConfig == 1U) */
02044
02045   /* Set the phase */
02046   hcryp->Phase = CRYP_PHASE_PROCESS;
02047
02048   /* Enable CRYP */
02049   __HAL_CRYP_ENABLE(hcryp);
02050
02051   incount = hcryp->CrypInCount;
02052   outcount = hcryp->CrypOutCount;
02053   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02054   {
02055     /* Write plain Ddta and get cipher data */
02056     CRYP_AES_ProcessData(hcryp, Timeout);
02057     incount = hcryp->CrypInCount;
02058     outcount = hcryp->CrypOutCount;
02059   }
02060
02061   /* Disable CRYP */
02062   __HAL_CRYP_DISABLE(hcryp);
02063
02064   /* Change the CRYP state */
02065   hcryp->State = HAL_CRYP_STATE_READY;
02066
02067   /* Return function status */
02068   return HAL_OK;
02069 }
02070
02071 /**
02072   * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02073   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02074   *         the configuration information for CRYP module
02075   * @retval HAL status
02076   */
02077 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
02078 {
02079   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02080
02081   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02082   {
02083     if (hcryp->KeyIVConfig == 1U)
02084     {
02085       /* If the Key and IV configuration has to be done only once
02086          and if it has already been done, skip it */
02087       DoKeyIVConfig = 0U;
02088     }
02089     else
02090     {
02091       /* If the Key and IV configuration has to be done only once
02092          and if it has not been done already, do it and set KeyIVConfig
02093          to keep track it won't have to be done again next time */
02094       hcryp->KeyIVConfig = 1U;
02095     }
02096   }
02097
02098   if (DoKeyIVConfig == 1U)
02099   {
02100     /*  Set the Key*/
02101     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02102
02103     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02104     {
02105       /* Set the Initialization Vector*/
02106       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02107       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02108       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02109       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02110     }
02111   } /* if (DoKeyIVConfig == 1U) */
02112
02113   /* Set the phase */
02114   hcryp->Phase = CRYP_PHASE_PROCESS;
02115
02116   if (hcryp->Size != 0U)
02117   {
02118
02119     /* Enable computation complete flag and error interrupts */
02120     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02121
02122     /* Enable CRYP */
02123     __HAL_CRYP_ENABLE(hcryp);
02124
02125     /* Increment the pointer before writing the input block in the IN FIFO to make sure that
02126        when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
02127        and it is ready for the next operation. */
02128     hcryp->CrypInCount++;
02129     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02130     hcryp->CrypInCount++;
02131     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02132     hcryp->CrypInCount++;
02133     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02134     hcryp->CrypInCount++;
02135     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02136   }
02137   else
02138   {
02139     /* Change the CRYP state */
02140     hcryp->State = HAL_CRYP_STATE_READY;
02141
02142     /* Process unlocked */
02143     __HAL_UNLOCK(hcryp);
02144   }
02145
02146   /* Return function status */
02147   return HAL_OK;
02148 }
02149
02150 /**
02151   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
02152   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
02153   * @param  Timeout Specify Timeout value
02154   * @retval HAL status
02155   */
02156 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02157 {
02158   uint16_t incount;  /* Temporary CrypInCount Value */
02159   uint16_t outcount;  /* Temporary CrypOutCount Value */
02160   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02161
02162   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02163   {
02164     if (hcryp->KeyIVConfig == 1U)
02165     {
02166       /* If the Key and IV configuration has to be done only once
02167          and if it has already been done, skip it */
02168       DoKeyIVConfig = 0U;
02169     }
02170     else
02171     {
02172       /* If the Key and IV configuration has to be done only once
02173          and if it has not been done already, do it and set KeyIVConfig
02174          to keep track it won't have to be done again next time */
02175       hcryp->KeyIVConfig = 1U;
02176     }
02177   }
02178
02179   if (DoKeyIVConfig == 1U)
02180   {
02181     /*  Key preparation for ECB/CBC */
02182     if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
02183     {
02184       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02185       {
02186         /* Set key preparation for decryption operating mode*/
02187         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02188
02189         /*  Set the Key*/
02190         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02191
02192         /* Enable CRYP */
02193         __HAL_CRYP_ENABLE(hcryp);
02194
02195         /* Wait for CCF flag to be raised */
02196         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02197         {
02198           /* Disable the CRYP peripheral clock */
02199           __HAL_CRYP_DISABLE(hcryp);
02200
02201           /* Change state & error code*/
02202           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02203           hcryp->State = HAL_CRYP_STATE_READY;
02204
02205           /* Process unlocked */
02206           __HAL_UNLOCK(hcryp);
02207           return HAL_ERROR;
02208         }
02209         /* Clear CCF Flag */
02210         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02211
02212         /* Return to decryption operating mode(Mode 3)*/
02213         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02214       }
02215       else /*Mode 4 : decryption & Key preparation*/
02216       {
02217         /*  Set the Key*/
02218         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02219
02220         /* Set decryption & Key preparation operating mode*/
02221         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02222       }
02223     }
02224     else  /*Algorithm CTR */
02225     {
02226       /*  Set the Key*/
02227       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02228     }
02229
02230     /* Set IV */
02231     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02232     {
02233       /* Set the Initialization Vector*/
02234       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02235       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02236       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02237       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02238     }
02239   } /* if (DoKeyIVConfig == 1U) */
02240
02241   /* Set the phase */
02242   hcryp->Phase = CRYP_PHASE_PROCESS;
02243
02244   /* Enable CRYP */
02245   __HAL_CRYP_ENABLE(hcryp);
02246
02247   incount = hcryp->CrypInCount;
02248   outcount = hcryp->CrypOutCount;
02249   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02250   {
02251     /* Write plain data and get cipher data */
02252     CRYP_AES_ProcessData(hcryp, Timeout);
02253     incount = hcryp->CrypInCount;
02254     outcount = hcryp->CrypOutCount;
02255   }
02256
02257   /* Disable CRYP */
02258   __HAL_CRYP_DISABLE(hcryp);
02259
02260   /* Change the CRYP state */
02261   hcryp->State = HAL_CRYP_STATE_READY;
02262
02263   /* Return function status */
02264   return HAL_OK;
02265 }
02266 /**
02267   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02268   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02269   *         the configuration information for CRYP module
02270   * @retval HAL status
02271   */
02272 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
02273 {
02274   __IO uint32_t count = 0U;
02275   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02276
02277   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02278   {
02279     if (hcryp->KeyIVConfig == 1U)
02280     {
02281       /* If the Key and IV configuration has to be done only once
02282          and if it has already been done, skip it */
02283       DoKeyIVConfig = 0U;
02284     }
02285     else
02286     {
02287       /* If the Key and IV configuration has to be done only once
02288          and if it has not been done already, do it and set KeyIVConfig
02289          to keep track it won't have to be done again next time */
02290       hcryp->KeyIVConfig = 1U;
02291     }
02292   }
02293
02294   if (DoKeyIVConfig == 1U)
02295   {
02296     /*  Key preparation for ECB/CBC */
02297     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02298     {
02299       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02300       {
02301         /* Set key preparation for decryption operating mode*/
02302         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02303
02304         /*  Set the Key*/
02305         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02306
02307         /* Enable CRYP */
02308         __HAL_CRYP_ENABLE(hcryp);
02309
02310         /* Wait for CCF flag to be raised */
02311         count = CRYP_TIMEOUT_KEYPREPARATION;
02312         do
02313         {
02314           count-- ;
02315           if (count == 0U)
02316           {
02317             /* Disable the CRYP peripheral clock */
02318             __HAL_CRYP_DISABLE(hcryp);
02319
02320             /* Change state */
02321             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02322             hcryp->State = HAL_CRYP_STATE_READY;
02323
02324             /* Process unlocked */
02325             __HAL_UNLOCK(hcryp);
02326             return HAL_ERROR;
02327           }
02328         } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02329
02330         /* Clear CCF Flag */
02331         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02332
02333         /* Return to decryption operating mode(Mode 3)*/
02334         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02335       }
02336       else /*Mode 4 : decryption & key preparation*/
02337       {
02338         /*  Set the Key*/
02339         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02340
02341         /* Set decryption & key preparation operating mode*/
02342         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02343       }
02344     }
02345     else  /*Algorithm CTR */
02346     {
02347       /*  Set the Key*/
02348       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02349     }
02350
02351     /* Set IV */
02352     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02353     {
02354       /* Set the Initialization Vector*/
02355       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02356       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02357       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02358       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02359     }
02360   } /* if (DoKeyIVConfig == 1U) */
02361
02362   /* Set the phase */
02363   hcryp->Phase = CRYP_PHASE_PROCESS;
02364   if (hcryp->Size != 0U)
02365   {
02366     /* Enable computation complete flag and error interrupts */
02367     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02368
02369     /* Enable CRYP */
02370     __HAL_CRYP_ENABLE(hcryp);
02371
02372     /* Increment the pointer before writing the input block in the IN FIFO to make sure that
02373        when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
02374        and it is ready for the next operation. */
02375     hcryp->CrypInCount++;
02376     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02377     hcryp->CrypInCount++;
02378     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02379     hcryp->CrypInCount++;
02380     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02381     hcryp->CrypInCount++;
02382     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
02383   }
02384   else
02385   {
02386     /* Process locked */
02387     __HAL_UNLOCK(hcryp);
02388
02389     /* Change the CRYP state */
02390     hcryp->State = HAL_CRYP_STATE_READY;
02391   }
02392
02393   /* Return function status */
02394   return HAL_OK;
02395 }
02396 /**
02397   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
02398   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02399   *         the configuration information for CRYP module
02400   * @retval HAL status
02401   */
02402 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
02403 {
02404   __IO uint32_t count = 0U;
02405   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02406
02407   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02408   {
02409     if (hcryp->KeyIVConfig == 1U)
02410     {
02411       /* If the Key and IV configuration has to be done only once
02412          and if it has already been done, skip it */
02413       DoKeyIVConfig = 0U;
02414     }
02415     else
02416     {
02417       /* If the Key and IV configuration has to be done only once
02418          and if it has not been done already, do it and set KeyIVConfig
02419          to keep track it won't have to be done again next time */
02420       hcryp->KeyIVConfig = 1U;
02421     }
02422   }
02423
02424   if (DoKeyIVConfig == 1U)
02425   {
02426     /*  Key preparation for ECB/CBC */
02427     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02428     {
02429       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
02430       {
02431         /* Set key preparation for decryption operating mode*/
02432         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02433
02434         /*  Set the Key*/
02435         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02436
02437         /* Enable CRYP */
02438         __HAL_CRYP_ENABLE(hcryp);
02439
02440         /* Wait for CCF flag to be raised */
02441         count = CRYP_TIMEOUT_KEYPREPARATION;
02442         do
02443         {
02444           count-- ;
02445           if (count == 0U)
02446           {
02447             /* Disable the CRYP peripheral clock */
02448             __HAL_CRYP_DISABLE(hcryp);
02449
02450             /* Change state */
02451             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02452             hcryp->State = HAL_CRYP_STATE_READY;
02453
02454             /* Process unlocked */
02455             __HAL_UNLOCK(hcryp);
02456             return HAL_ERROR;
02457           }
02458         } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02459
02460         /* Clear CCF Flag */
02461         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02462
02463         /* Return to decryption operating mode(Mode 3)*/
02464         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02465       }
02466       else /*Mode 4 : decryption & key preparation*/
02467       {
02468         /*  Set the Key*/
02469         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02470
02471         /* Set decryption & Key preparation operating mode*/
02472         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02473       }
02474     }
02475     else  /*Algorithm CTR */
02476     {
02477       /*  Set the Key*/
02478       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02479     }
02480
02481     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02482     {
02483       /* Set the Initialization Vector*/
02484       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02485       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02486       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02487       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02488     }
02489   } /* if (DoKeyIVConfig == 1U) */
02490
02491   /* Set the phase */
02492   hcryp->Phase = CRYP_PHASE_PROCESS;
02493
02494   if (hcryp->Size != 0U)
02495   {
02496     /* Set the input and output addresses and start DMA transfer */
02497     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
02498   }
02499   else
02500   {
02501     /* Process unlocked */
02502     __HAL_UNLOCK(hcryp);
02503
02504     /* Change the CRYP state */
02505     hcryp->State = HAL_CRYP_STATE_READY;
02506   }
02507
02508   /* Return function status */
02509   return HAL_OK;
02510 }
02511
02512
02513 /**
02514   * @brief  DMA CRYP input data process complete callback.
02515   * @param  hdma DMA handle
02516   * @retval None
02517   */
02518 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
02519 {
02520   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02521   uint32_t loopcounter;
02522   uint32_t headersize_in_bytes;
02523   uint32_t tmp;
02524   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
02525                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
02526                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
02527                                     }; /*  8-bit data type */
02528
02529   /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
02530   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02531
02532   if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
02533   {
02534     /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
02535     CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02536
02537     /* Set the phase */
02538     hcryp->Phase = CRYP_PHASE_PROCESS;
02539
02540     if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
02541     {
02542       headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
02543     }
02544     else
02545     {
02546       headersize_in_bytes = hcryp->Init.HeaderSize;
02547     }
02548
02549     if ((headersize_in_bytes % 16U) != 0U)
02550     {
02551       /* Write last words that couldn't be fed by DMA */
02552       hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
02553       for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
02554       {
02555         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
02556         hcryp->CrypHeaderCount++ ;
02557       }
02558       /* If the header size is a multiple of words */
02559       if ((headersize_in_bytes % 4U) == 0U)
02560       {
02561         /* Pad the data with zeros to have a complete block */
02562         while (loopcounter < 4U)
02563         {
02564           hcryp->Instance->DINR = 0x0U;
02565           loopcounter++;
02566         }
02567       }
02568       else
02569       {
02570         /* Enter last bytes, padded with zeros */
02571         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
02572         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
02573         hcryp->Instance->DINR = tmp;
02574         loopcounter++;
02575         /* Pad the data with zeros to have a complete block */
02576         while (loopcounter < 4U)
02577         {
02578           hcryp->Instance->DINR = 0x0U;
02579           loopcounter++;
02580         }
02581       }
02582
02583       /* Wait for computation completion before moving forward */
02584       CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02585     } /* if ((headersize_in_bytes % 16U) != 0U) */
02586
02587     /* Set to 0 the number of non-valid bytes using NPBLB register*/
02588     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
02589
02590     /* Select payload phase once the header phase is performed */
02591     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02592
02593     /* Initiate payload DMA IN and processed data DMA OUT transfers */
02594     (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
02595   }
02596   else
02597   {
02598     uint32_t algo;
02599     /* ECB, CBC or CTR end of input data feeding
02600        or
02601        end of GCM/CCM payload data feeding through DMA */
02602     algo = hcryp->Instance->CR & AES_CR_CHMOD;
02603
02604     /* Don't call input data transfer complete callback only if
02605        it remains some input data to write to the peripheral.
02606        This case can only occur for GCM and CCM with a payload length
02607        not a multiple of 16 bytes */
02608     if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
02609           (((hcryp->Size) % 16U) != 0U)))
02610     {
02611       /* Call input data transfer complete callback */
02612 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02613       /*Call registered Input complete callback*/
02614       hcryp->InCpltCallback(hcryp);
02615 #else
02616       /*Call legacy weak Input complete callback*/
02617       HAL_CRYP_InCpltCallback(hcryp);
02618 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02619     }
02620   } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
02621 }
02622
02623 /**
02624   * @brief  DMA CRYP output data process complete callback.
02625   * @param  hdma DMA handle
02626   * @retval None
02627   */
02628 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
02629 {
02630   uint32_t count;
02631   uint32_t npblb;
02632   uint32_t lastwordsize;
02633   uint32_t temp[4];  /* Temporary CrypOutBuff */
02634   uint32_t mode;
02635
02636   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02637
02638   /* Stop the DMA transfers to the OUT FIFO by clearing to "0" the DMAOUTEN */
02639   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
02640
02641   /* Clear CCF flag */
02642   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02643
02644   /* Last block transfer in case of GCM or CCM with Size not %16*/
02645   if (((hcryp->Size) % 16U) != 0U)
02646   {
02647     /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
02648     hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
02649     hcryp->CrypOutCount = hcryp->CrypInCount;
02650
02651     /* Compute the number of padding bytes in last block of payload */
02652     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
02653
02654     mode = hcryp->Instance->CR & AES_CR_MODE;
02655     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
02656         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
02657     {
02658       /* Specify the number of non-valid bytes using NPBLB register*/
02659       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
02660     }
02661
02662     /* Number of valid words (lastwordsize) in last block */
02663     if ((npblb % 4U) == 0U)
02664     {
02665       lastwordsize = (16U - npblb) / 4U;
02666     }
02667     else
02668     {
02669       lastwordsize = ((16U - npblb) / 4U) + 1U;
02670     }
02671
02672     /*  Last block optionally pad the data with zeros*/
02673     for (count = 0U; count < lastwordsize; count++)
02674     {
02675       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02676       hcryp->CrypInCount++;
02677     }
02678     while (count < 4U)
02679     {
02680       /* Pad the data with zeros to have a complete block */
02681       hcryp->Instance->DINR = 0x0U;
02682       count++;
02683     }
02684     /* Call input data transfer complete callback */
02685 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02686     /*Call registered Input complete callback*/
02687     hcryp->InCpltCallback(hcryp);
02688 #else
02689     /*Call legacy weak Input complete callback*/
02690     HAL_CRYP_InCpltCallback(hcryp);
02691 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02692
02693     /*Wait on CCF flag*/
02694     CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02695
02696     /*Read the output block from the output FIFO */
02697     for (count = 0U; count < 4U; count++)
02698     {
02699       /* Read the output block from the output FIFO and put them in temporary buffer
02700          then get CrypOutBuff from temporary buffer */
02701       temp[count] = hcryp->Instance->DOUTR;
02702     }
02703
02704     count = 0U;
02705     while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
02706     {
02707       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
02708       hcryp->CrypOutCount++;
02709       count++;
02710     }
02711   }
02712
02713   if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
02714       && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
02715   {
02716     /* Disable CRYP (not allowed in  GCM)*/
02717     __HAL_CRYP_DISABLE(hcryp);
02718   }
02719
02720   /* Change the CRYP state to ready */
02721   hcryp->State = HAL_CRYP_STATE_READY;
02722
02723   /* Process unlocked */
02724   __HAL_UNLOCK(hcryp);
02725
02726   /* Call output data transfer complete callback */
02727 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02728   /*Call registered Output complete callback*/
02729   hcryp->OutCpltCallback(hcryp);
02730 #else
02731   /*Call legacy weak Output complete callback*/
02732   HAL_CRYP_OutCpltCallback(hcryp);
02733 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02734 }
02735
02736 /**
02737   * @brief  DMA CRYP communication error callback.
02738   * @param  hdma DMA handle
02739   * @retval None
02740   */
02741 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
02742 {
02743   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02744
02745   /* Change the CRYP peripheral state */
02746   hcryp->State = HAL_CRYP_STATE_READY;
02747
02748   /* DMA error code field */
02749   hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02750
02751   /* Clear CCF flag */
02752   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02753
02754   /* Call error callback */
02755 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02756   /*Call registered error callback*/
02757   hcryp->ErrorCallback(hcryp);
02758 #else
02759   /*Call legacy weak error callback*/
02760   HAL_CRYP_ErrorCallback(hcryp);
02761 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02762 }
02763
02764 /**
02765   * @brief  Set the DMA configuration and start the DMA transfer
02766   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02767   *         the configuration information for CRYP module
02768   * @param  inputaddr address of the input buffer
02769   * @param  Size size of the input and output buffers in words, must be a multiple of 4
02770   * @param  outputaddr address of the output buffer
02771   * @retval None
02772   */
02773 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02774 {
02775   /* Set the CRYP DMA transfer complete callback */
02776   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02777
02778   /* Set the DMA input error callback */
02779   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02780
02781   /* Set the CRYP DMA transfer complete callback */
02782   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
02783
02784   /* Set the DMA output error callback */
02785   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
02786
02787   if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
02788   {
02789     /* Enable CRYP (not allowed in  GCM & CCM)*/
02790     __HAL_CRYP_ENABLE(hcryp);
02791   }
02792
02793   /* Enable the DMA input stream */
02794   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
02795   {
02796     /* DMA error code field */
02797     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02798
02799     /* Call error callback */
02800 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02801     /*Call registered error callback*/
02802     hcryp->ErrorCallback(hcryp);
02803 #else
02804     /*Call legacy weak error callback*/
02805     HAL_CRYP_ErrorCallback(hcryp);
02806 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02807   }
02808   /* Enable the DMA output stream */
02809   if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
02810   {
02811     /* DMA error code field */
02812     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02813
02814     /* Call error callback */
02815 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02816     /*Call registered error callback*/
02817     hcryp->ErrorCallback(hcryp);
02818 #else
02819     /*Call legacy weak error callback*/
02820     HAL_CRYP_ErrorCallback(hcryp);
02821 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02822   }
02823   /* Enable In and Out DMA requests */
02824   SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
02825 }
02826
02827 /**
02828   * @brief  Set the DMA configuration and start the header DMA transfer
02829   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02830   *         the configuration information for CRYP module
02831   * @param  inputaddr address of the input buffer
02832   * @param  Size size of the input buffer in words, must be a multiple of 4
02833   * @retval None
02834   */
02835 static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
02836 {
02837   /* Set the CRYP DMA transfer complete callback */
02838   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02839
02840   /* Set the DMA input error callback */
02841   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02842
02843   /* Mark that header is fed to the peripheral in DMA mode */
02844   hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
02845   /* Enable the DMA input stream */
02846   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
02847   {
02848     /* DMA error code field */
02849     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02850     hcryp->State = HAL_CRYP_STATE_READY;
02851
02852     /* Process unlocked */
02853     __HAL_UNLOCK(hcryp);
02854     return HAL_ERROR;
02855     /* Call error callback */
02856   }
02857
02858   /* Enable IN DMA requests */
02859   SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02860
02861   return HAL_OK;
02862 }
02863
02864 /**
02865   * @brief  Process Data: Write Input data in polling mode and used in AES functions.
02866   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02867   *         the configuration information for CRYP module
02868   * @param  Timeout Specify Timeout value
02869   * @retval None
02870   */
02871 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02872 {
02873
02874   uint32_t temp[4];  /* Temporary CrypOutBuff */
02875   uint32_t i;
02876
02877   /* Write the input block in the IN FIFO */
02878   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02879   hcryp->CrypInCount++;
02880   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02881   hcryp->CrypInCount++;
02882   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02883   hcryp->CrypInCount++;
02884   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02885   hcryp->CrypInCount++;
02886
02887   /* Wait for CCF flag to be raised */
02888   if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02889   {
02890     /* Disable the CRYP peripheral clock */
02891     __HAL_CRYP_DISABLE(hcryp);
02892
02893     /* Change state */
02894     hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02895     hcryp->State = HAL_CRYP_STATE_READY;
02896
02897     /* Process unlocked */
02898     __HAL_UNLOCK(hcryp);
02899     /*Call registered error callback*/
02900 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02901     hcryp->ErrorCallback(hcryp);
02902 #else
02903     /*Call legacy weak error callback*/
02904     HAL_CRYP_ErrorCallback(hcryp);
02905 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02906   }
02907
02908   /* Clear CCF Flag */
02909   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02910
02911   /* Read the output block from the output FIFO and put them in temporary buffer
02912      then get CrypOutBuff from temporary buffer*/
02913   for (i = 0U; i < 4U; i++)
02914   {
02915     temp[i] = hcryp->Instance->DOUTR;
02916   }
02917   i = 0U;
02918   while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
02919   {
02920     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
02921     hcryp->CrypOutCount++;
02922     i++;
02923   }
02924 }
02925
02926 /**
02927   * @brief  Handle CRYP block input/output data handling under interruption.
02928   * @note   The function is called under interruption only, once
02929   *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
02930   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02931   *         the configuration information for CRYP module.
02932   * @retval HAL status
02933   */
02934 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
02935 {
02936   uint32_t temp[4];  /* Temporary CrypOutBuff */
02937   uint32_t i;
02938
02939   if (hcryp->State == HAL_CRYP_STATE_BUSY)
02940   {
02941     /* Read the output block from the output FIFO and put them in temporary buffer
02942        then get CrypOutBuff from temporary buffer*/
02943     for (i = 0U; i < 4U; i++)
02944     {
02945       temp[i] = hcryp->Instance->DOUTR;
02946     }
02947     i = 0U;
02948     while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
02949     {
02950       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
02951       hcryp->CrypOutCount++;
02952       i++;
02953     }
02954     if (hcryp->CrypOutCount == (hcryp->Size / 4U))
02955     {
02956       /* Disable Computation Complete flag and errors interrupts */
02957       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02958
02959       /* Change the CRYP state */
02960       hcryp->State = HAL_CRYP_STATE_READY;
02961
02962       /* Disable CRYP */
02963       __HAL_CRYP_DISABLE(hcryp);
02964
02965       /* Process Unlocked */
02966       __HAL_UNLOCK(hcryp);
02967
02968       /* Call Output transfer complete callback */
02969 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02970       /*Call registered Output complete callback*/
02971       hcryp->OutCpltCallback(hcryp);
02972 #else
02973       /*Call legacy weak Output complete callback*/
02974       HAL_CRYP_OutCpltCallback(hcryp);
02975 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02976     }
02977     else
02978     {
02979 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
02980       /* If suspension flag has been raised, suspend processing
02981          only if not already at the end of the payload */
02982       if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
02983       {
02984         /* Clear CCF Flag */
02985         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02986
02987         /* reset SuspendRequest */
02988         hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02989         /* Disable Computation Complete Flag and Errors Interrupts */
02990         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02991         /* Change the CRYP state */
02992         hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02993         /* Mark that the payload phase is suspended */
02994         hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
02995
02996         /* Process Unlocked */
02997         __HAL_UNLOCK(hcryp);
02998       }
02999       else
03000 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03001       {
03002         /* Write the input block in the IN FIFO */
03003         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03004         hcryp->CrypInCount++;
03005         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03006         hcryp->CrypInCount++;
03007         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03008         hcryp->CrypInCount++;
03009         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03010         hcryp->CrypInCount++;
03011
03012         if (hcryp->CrypInCount == (hcryp->Size / 4U))
03013         {
03014           /* Call Input transfer complete callback */
03015 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03016           /*Call registered Input complete callback*/
03017           hcryp->InCpltCallback(hcryp);
03018 #else
03019           /*Call legacy weak Input complete callback*/
03020           HAL_CRYP_InCpltCallback(hcryp);
03021 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03022         }
03023       }
03024     }
03025   }
03026   else
03027   {
03028     /* Busy error code field */
03029     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
03030 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03031     /*Call registered error callback*/
03032     hcryp->ErrorCallback(hcryp);
03033 #else
03034     /*Call legacy weak error callback*/
03035     HAL_CRYP_ErrorCallback(hcryp);
03036 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03037   }
03038 }
03039
03040 /**
03041   * @brief  Writes Key in Key registers.
03042   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03043   *         the configuration information for CRYP module
03044   * @param  KeySize Size of Key
03045   * @note   If pKey is NULL, the Key registers are not written. This configuration
03046   *         occurs when the key is written out of HAL scope.
03047   * @retval None
03048   */
03049 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
03050 {
03051   if (hcryp->Init.pKey != NULL)
03052   {
03053     switch (KeySize)
03054     {
03055       case CRYP_KEYSIZE_256B:
03056         hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
03057         hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
03058         hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
03059         hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
03060         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
03061         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
03062         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
03063         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
03064         break;
03065       case CRYP_KEYSIZE_128B:
03066         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
03067         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
03068         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
03069         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
03070
03071         break;
03072       default:
03073         break;
03074     }
03075   }
03076 }
03077
03078 /**
03079   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
03080   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03081   *         the configuration information for CRYP module
03082   * @param  Timeout Timeout duration
03083   * @retval HAL status
03084   */
03085 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03086 {
03087   uint32_t tickstart;
03088   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
03089   uint32_t npblb;
03090   uint32_t temp[4];  /* Temporary CrypOutBuff */
03091   uint32_t index;
03092   uint32_t lastwordsize;
03093   uint32_t incount;  /* Temporary CrypInCount Value */
03094   uint32_t outcount;  /* Temporary CrypOutCount Value */
03095   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03096
03097   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03098   {
03099     if (hcryp->KeyIVConfig == 1U)
03100     {
03101       /* If the Key and IV configuration has to be done only once
03102          and if it has already been done, skip it */
03103       DoKeyIVConfig = 0U;
03104       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03105     }
03106     else
03107     {
03108       /* If the Key and IV configuration has to be done only once
03109          and if it has not been done already, do it and set KeyIVConfig
03110          to keep track it won't have to be done again next time */
03111       hcryp->KeyIVConfig = 1U;
03112       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03113     }
03114   }
03115   else
03116   {
03117     hcryp->SizesSum = hcryp->Size;
03118   }
03119
03120   if (DoKeyIVConfig == 1U)
03121   {
03122
03123     /*  Reset CrypHeaderCount */
03124     hcryp->CrypHeaderCount = 0U;
03125
03126     /****************************** Init phase **********************************/
03127
03128     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03129
03130     /* Set the key */
03131     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03132
03133     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03134     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03135     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03136     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03137     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03138
03139     /* Enable the CRYP peripheral */
03140     __HAL_CRYP_ENABLE(hcryp);
03141
03142     /* just wait for hash computation */
03143     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03144     {
03145       /* Change state */
03146       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03147       hcryp->State = HAL_CRYP_STATE_READY;
03148
03149       /* Process unlocked & return error */
03150       __HAL_UNLOCK(hcryp);
03151       return HAL_ERROR;
03152     }
03153     /* Clear CCF flag */
03154     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03155
03156     /************************ Header phase *************************************/
03157
03158     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03159     {
03160       return HAL_ERROR;
03161     }
03162
03163     /*************************Payload phase ************************************/
03164
03165     /* Set the phase */
03166     hcryp->Phase = CRYP_PHASE_PROCESS;
03167
03168     /* Select payload phase once the header phase is performed */
03169     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03170
03171     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03172     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03173
03174   } /* if (DoKeyIVConfig == 1U) */
03175
03176   if ((hcryp->Size % 16U) != 0U)
03177   {
03178     /* recalculate  wordsize */
03179     wordsize = ((wordsize / 4U) * 4U) ;
03180   }
03181
03182   /* Get tick */
03183   tickstart = HAL_GetTick();
03184
03185   /* Write input data and get output Data */
03186   incount = hcryp->CrypInCount;
03187   outcount = hcryp->CrypOutCount;
03188   while ((incount < wordsize) && (outcount < wordsize))
03189   {
03190     /* Write plain data and get cipher data */
03191     CRYP_AES_ProcessData(hcryp, Timeout);
03192
03193     /* Check for the Timeout */
03194     if (Timeout != HAL_MAX_DELAY)
03195     {
03196       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03197       {
03198         /* Disable the CRYP peripheral clock */
03199         __HAL_CRYP_DISABLE(hcryp);
03200
03201         /* Change state & error code */
03202         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03203         hcryp->State = HAL_CRYP_STATE_READY;
03204
03205         /* Process unlocked */
03206         __HAL_UNLOCK(hcryp);
03207         return HAL_ERROR;
03208       }
03209     }
03210     incount = hcryp->CrypInCount;
03211     outcount = hcryp->CrypOutCount;
03212   }
03213
03214   if ((hcryp->Size % 16U) != 0U)
03215   {
03216     /* Compute the number of padding bytes in last block of payload */
03217     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03218
03219     /*  Set Npblb in case of AES GCM payload encryption to get right tag*/
03220     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03221     {
03222       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03223       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03224     }
03225     /* Number of valid words (lastwordsize) in last block */
03226     if ((npblb % 4U) == 0U)
03227     {
03228       lastwordsize = (16U - npblb) / 4U;
03229     }
03230     else
03231     {
03232       lastwordsize = ((16U - npblb) / 4U) + 1U;
03233     }
03234     /*  last block optionally pad the data with zeros*/
03235     for (index = 0U; index < lastwordsize; index ++)
03236     {
03237       /* Write the last Input block in the IN FIFO */
03238       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03239       hcryp->CrypInCount++;
03240     }
03241     while (index < 4U)
03242     {
03243       /* pad the data with zeros to have a complete block */
03244       hcryp->Instance->DINR  = 0U;
03245       index++;
03246     }
03247     /* Wait for CCF flag to be raised */
03248     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03249     {
03250       hcryp->State = HAL_CRYP_STATE_READY;
03251       __HAL_UNLOCK(hcryp);
03252
03253 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03254       /*Call registered error callback*/
03255       hcryp->ErrorCallback(hcryp);
03256 #else
03257       /*Call legacy weak error callback*/
03258       HAL_CRYP_ErrorCallback(hcryp);
03259 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03260     }
03261
03262     /* Clear CCF Flag */
03263     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03264
03265     /*Read the output block from the output FIFO */
03266     for (index = 0U; index < 4U; index++)
03267     {
03268       /* Read the output block from the output FIFO and put them in temporary buffer
03269          then get CrypOutBuff from temporary buffer */
03270       temp[index] = hcryp->Instance->DOUTR;
03271     }
03272     for (index = 0U; index < lastwordsize; index++)
03273     {
03274       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
03275       hcryp->CrypOutCount++;
03276     }
03277   }
03278
03279   /* Return function status */
03280   return HAL_OK;
03281 }
03282
03283 /**
03284   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
03285   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03286   *         the configuration information for CRYP module
03287   * @retval HAL status
03288   */
03289 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03290 {
03291   __IO uint32_t count = 0U;
03292   uint32_t loopcounter;
03293   uint32_t lastwordsize;
03294   uint32_t npblb;
03295   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03296   uint32_t headersize_in_bytes;
03297   uint32_t tmp;
03298   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
03299                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
03300                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
03301                                     }; /*  8-bit data type */
03302
03303
03304 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03305   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03306   {
03307     CRYP_PhaseProcessingResume(hcryp);
03308     return HAL_OK;
03309   }
03310 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03311
03312   /* Manage header size given in bytes to handle cases where
03313      header size is not a multiple of 4 bytes */
03314   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
03315   {
03316     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
03317   }
03318   else
03319   {
03320     headersize_in_bytes = hcryp->Init.HeaderSize;
03321   }
03322
03323   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03324   {
03325     if (hcryp->KeyIVConfig == 1U)
03326     {
03327       /* If the Key and IV configuration has to be done only once
03328          and if it has already been done, skip it */
03329       DoKeyIVConfig = 0U;
03330       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03331     }
03332     else
03333     {
03334       /* If the Key and IV configuration has to be done only once
03335          and if it has not been done already, do it and set KeyIVConfig
03336          to keep track it won't have to be done again next time */
03337       hcryp->KeyIVConfig = 1U;
03338       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03339     }
03340   }
03341   else
03342   {
03343     hcryp->SizesSum = hcryp->Size;
03344   }
03345
03346   /* Configure Key, IV and process message (header and payload) */
03347   if (DoKeyIVConfig == 1U)
03348   {
03349     /*  Reset CrypHeaderCount */
03350     hcryp->CrypHeaderCount = 0U;
03351
03352     /******************************* Init phase *********************************/
03353
03354     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03355
03356     /* Set the key */
03357     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03358
03359     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03360     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03361     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03362     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03363     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03364
03365     /* Enable the CRYP peripheral */
03366     __HAL_CRYP_ENABLE(hcryp);
03367
03368     /* just wait for hash computation */
03369     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03370     do
03371     {
03372       count-- ;
03373       if (count == 0U)
03374       {
03375         /* Disable the CRYP peripheral clock */
03376         __HAL_CRYP_DISABLE(hcryp);
03377
03378         /* Change state */
03379         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03380         hcryp->State = HAL_CRYP_STATE_READY;
03381
03382         /* Process unlocked */
03383         __HAL_UNLOCK(hcryp);
03384         return HAL_ERROR;
03385       }
03386     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03387
03388     /* Clear CCF flag */
03389     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03390
03391     /***************************** Header phase *********************************/
03392
03393     /* Select header phase */
03394     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03395
03396     /* Enable computation complete flag and error interrupts */
03397     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03398
03399     /* Enable the CRYP peripheral */
03400     __HAL_CRYP_ENABLE(hcryp);
03401
03402     if (hcryp->Init.HeaderSize == 0U) /*header phase is  skipped*/
03403     {
03404       /* Set the phase */
03405       hcryp->Phase = CRYP_PHASE_PROCESS;
03406
03407       /* Select payload phase once the header phase is performed */
03408       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03409
03410       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03411       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03412
03413       /* Write the payload Input block in the IN FIFO */
03414       if (hcryp->Size == 0U)
03415       {
03416         /* Disable interrupts */
03417         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03418
03419         /* Change the CRYP state */
03420         hcryp->State = HAL_CRYP_STATE_READY;
03421
03422         /* Process unlocked */
03423         __HAL_UNLOCK(hcryp);
03424       }
03425       else if (hcryp->Size >= 16U)
03426       {
03427         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03428         hcryp->CrypInCount++;
03429         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03430         hcryp->CrypInCount++;
03431         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03432         hcryp->CrypInCount++;
03433         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03434         hcryp->CrypInCount++;
03435         if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
03436         {
03437           /* Call Input transfer complete callback */
03438 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03439           /*Call registered Input complete callback*/
03440           hcryp->InCpltCallback(hcryp);
03441 #else
03442           /*Call legacy weak Input complete callback*/
03443           HAL_CRYP_InCpltCallback(hcryp);
03444 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03445         }
03446       }
03447       else /* Size < 16Bytes  : first block is the last block*/
03448       {
03449         /* Workaround not implemented for TinyAES2*/
03450         /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03451         Workaround is implemented in polling mode, so if last block of
03452         payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03453
03454
03455         /* Compute the number of padding bytes in last block of payload */
03456         npblb = 16U - ((uint32_t)hcryp->Size);
03457
03458         if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03459         {
03460           /* Set to 0 the number of non-valid bytes using NPBLB register*/
03461           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03462         }
03463
03464         /* Number of valid words (lastwordsize) in last block */
03465         if ((npblb % 4U) == 0U)
03466         {
03467           lastwordsize = (16U - npblb) / 4U;
03468         }
03469         else
03470         {
03471           lastwordsize = ((16U - npblb) / 4U) + 1U;
03472         }
03473
03474         /*  last block optionally pad the data with zeros*/
03475         for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03476         {
03477           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03478           hcryp->CrypInCount++;
03479         }
03480         while (loopcounter < 4U)
03481         {
03482           /* pad the data with zeros to have a complete block */
03483           hcryp->Instance->DINR = 0x0U;
03484           loopcounter++;
03485         }
03486         /* Call Input transfer complete callback */
03487 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03488         /*Call registered Input complete callback*/
03489         hcryp->InCpltCallback(hcryp);
03490 #else
03491         /*Call legacy weak Input complete callback*/
03492         HAL_CRYP_InCpltCallback(hcryp);
03493 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03494       }
03495     }
03496     /* Enter header data */
03497     /* Cher first whether header length is small enough to enter the full header in one shot */
03498     else if (headersize_in_bytes <= 16U)
03499     {
03500       /* Write header data, padded with zeros if need be */
03501       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
03502       {
03503         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03504         hcryp->CrypHeaderCount++ ;
03505       }
03506       /* If the header size is a multiple of words */
03507       if ((headersize_in_bytes % 4U) == 0U)
03508       {
03509         /* Pad the data with zeros to have a complete block */
03510         while (loopcounter < 4U)
03511         {
03512           hcryp->Instance->DINR = 0x0U;
03513           loopcounter++;
03514           hcryp->CrypHeaderCount++;
03515         }
03516       }
03517       else
03518       {
03519         /* Enter last bytes, padded with zeros */
03520         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03521         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
03522         hcryp->Instance->DINR = tmp;
03523         loopcounter++;
03524         hcryp->CrypHeaderCount++ ;
03525         /* Pad the data with zeros to have a complete block */
03526         while (loopcounter < 4U)
03527         {
03528           hcryp->Instance->DINR = 0x0U;
03529           loopcounter++;
03530           hcryp->CrypHeaderCount++;
03531         }
03532       }
03533     }
03534     else
03535     {
03536       /* Write the first input header block in the Input FIFO,
03537          the following header data will be fed after interrupt occurrence */
03538       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03539       hcryp->CrypHeaderCount++;
03540       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03541       hcryp->CrypHeaderCount++;
03542       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03543       hcryp->CrypHeaderCount++;
03544       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03545       hcryp->CrypHeaderCount++;
03546     }
03547
03548   } /* end of if (DoKeyIVConfig == 1U) */
03549   else  /* Key and IV have already been configured,
03550           header has already been processed;
03551           only process here message payload */
03552   {
03553     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03554     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03555
03556     /* Write the payload Input block in the IN FIFO */
03557     if (hcryp->Size == 0U)
03558     {
03559       /* Disable interrupts */
03560       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03561
03562       /* Change the CRYP state */
03563       hcryp->State = HAL_CRYP_STATE_READY;
03564
03565       /* Process unlocked */
03566       __HAL_UNLOCK(hcryp);
03567     }
03568     else if (hcryp->Size >= 16U)
03569     {
03570       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03571       hcryp->CrypInCount++;
03572       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03573       hcryp->CrypInCount++;
03574       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03575       hcryp->CrypInCount++;
03576       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03577       hcryp->CrypInCount++;
03578       if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
03579       {
03580         /* Call Input transfer complete callback */
03581 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03582         /*Call registered Input complete callback*/
03583         hcryp->InCpltCallback(hcryp);
03584 #else
03585         /*Call legacy weak Input complete callback*/
03586         HAL_CRYP_InCpltCallback(hcryp);
03587 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03588       }
03589
03590       /* Enable computation complete flag and error interrupts */
03591       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03592     }
03593     else /* Size < 16Bytes  : first block is the last block*/
03594     {
03595       /* Workaround not implemented for TinyAES2*/
03596       /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03597       Workaround is implemented in polling mode, so if last block of
03598       payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03599
03600
03601       /* Compute the number of padding bytes in last block of payload */
03602       npblb = 16U - ((uint32_t)hcryp->Size);
03603
03604       if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03605       {
03606         /* Set to 0 the number of non-valid bytes using NPBLB register*/
03607         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03608       }
03609
03610       /* Number of valid words (lastwordsize) in last block */
03611       if ((npblb % 4U) == 0U)
03612       {
03613         lastwordsize = (16U - npblb) / 4U;
03614       }
03615       else
03616       {
03617         lastwordsize = ((16U - npblb) / 4U) + 1U;
03618       }
03619
03620       /*  last block optionally pad the data with zeros*/
03621       for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03622       {
03623         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03624         hcryp->CrypInCount++;
03625       }
03626       while (loopcounter < 4U)
03627       {
03628         /* pad the data with zeros to have a complete block */
03629         hcryp->Instance->DINR = 0x0U;
03630         loopcounter++;
03631       }
03632       /* Call Input transfer complete callback */
03633 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03634       /*Call registered Input complete callback*/
03635       hcryp->InCpltCallback(hcryp);
03636 #else
03637       /*Call legacy weak Input complete callback*/
03638       HAL_CRYP_InCpltCallback(hcryp);
03639 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03640
03641       /* Enable computation complete flag and error interrupts */
03642       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03643     }
03644   }
03645
03646   /* Return function status */
03647   return HAL_OK;
03648 }
03649
03650
03651 /**
03652   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
03653   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03654   *         the configuration information for CRYP module
03655   * @retval HAL status
03656   */
03657 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
03658 {
03659   uint32_t count;
03660   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03661
03662   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03663   {
03664     if (hcryp->KeyIVConfig == 1U)
03665     {
03666       /* If the Key and IV configuration has to be done only once
03667          and if it has already been done, skip it */
03668       DoKeyIVConfig = 0U;
03669       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03670     }
03671     else
03672     {
03673       /* If the Key and IV configuration has to be done only once
03674          and if it has not been done already, do it and set KeyIVConfig
03675          to keep track it won't have to be done again next time */
03676       hcryp->KeyIVConfig = 1U;
03677       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03678     }
03679   }
03680   else
03681   {
03682     hcryp->SizesSum = hcryp->Size;
03683   }
03684
03685   if (DoKeyIVConfig == 1U)
03686   {
03687
03688     /*  Reset CrypHeaderCount */
03689     hcryp->CrypHeaderCount = 0U;
03690
03691     /*************************** Init phase ************************************/
03692
03693     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03694
03695     /* Set the key */
03696     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03697
03698     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03699     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03700     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03701     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03702     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03703
03704     /* Enable the CRYP peripheral */
03705     __HAL_CRYP_ENABLE(hcryp);
03706
03707     /* just wait for hash computation */
03708     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03709     do
03710     {
03711       count-- ;
03712       if (count == 0U)
03713       {
03714         /* Disable the CRYP peripheral clock */
03715         __HAL_CRYP_DISABLE(hcryp);
03716
03717         /* Change state */
03718         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03719         hcryp->State = HAL_CRYP_STATE_READY;
03720
03721         /* Process unlocked */
03722         __HAL_UNLOCK(hcryp);
03723         return HAL_ERROR;
03724       }
03725     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03726
03727     /* Clear CCF flag */
03728     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03729
03730     /************************ Header phase *************************************/
03731
03732     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
03733     {
03734       return HAL_ERROR;
03735     }
03736
03737   }
03738   else
03739   {
03740     /* Initialization and header phases already done, only do payload phase */
03741     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
03742     {
03743       return HAL_ERROR;
03744     }
03745   } /* if (DoKeyIVConfig == 1U) */
03746
03747   /* Return function status */
03748   return HAL_OK;
03749 }
03750
03751
03752 /**
03753   * @brief  AES CCM encryption/decryption processing in polling mode
03754   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03755   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03756   *         the configuration information for CRYP module
03757   * @param  Timeout Timeout duration
03758   * @retval HAL status
03759   */
03760 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03761 {
03762   uint32_t tickstart;
03763   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
03764   uint32_t loopcounter;
03765   uint32_t npblb;
03766   uint32_t lastwordsize;
03767   uint32_t temp[4] ;  /* Temporary CrypOutBuff */
03768   uint32_t incount;  /* Temporary CrypInCount Value */
03769   uint32_t outcount;  /* Temporary CrypOutCount Value */
03770   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03771
03772   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03773   {
03774     if (hcryp->KeyIVConfig == 1U)
03775     {
03776       /* If the Key and IV configuration has to be done only once
03777          and if it has already been done, skip it */
03778       DoKeyIVConfig = 0U;
03779       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03780     }
03781     else
03782     {
03783       /* If the Key and IV configuration has to be done only once
03784          and if it has not been done already, do it and set KeyIVConfig
03785          to keep track it won't have to be done again next time */
03786       hcryp->KeyIVConfig = 1U;
03787       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03788     }
03789   }
03790   else
03791   {
03792     hcryp->SizesSum = hcryp->Size;
03793   }
03794
03795   if (DoKeyIVConfig == 1U)
03796   {
03797     /*  Reset CrypHeaderCount */
03798     hcryp->CrypHeaderCount = 0U;
03799
03800     /********************** Init phase ******************************************/
03801
03802     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03803
03804     /* Set the key */
03805     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03806
03807     /* Set the initialization vector (IV) with B0 */
03808     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
03809     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
03810     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
03811     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
03812
03813     /* Enable the CRYP peripheral */
03814     __HAL_CRYP_ENABLE(hcryp);
03815
03816     /* just wait for hash computation */
03817     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03818     {
03819       /* Change state */
03820       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03821       hcryp->State = HAL_CRYP_STATE_READY;
03822
03823       /* Process unlocked & return error */
03824       __HAL_UNLOCK(hcryp);
03825       return HAL_ERROR;
03826     }
03827     /* Clear CCF flag */
03828     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03829
03830     /************************ Header phase *************************************/
03831     /* Header block(B1) : associated data length expressed in bytes concatenated
03832     with Associated Data (A)*/
03833     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03834     {
03835       return HAL_ERROR;
03836     }
03837
03838     /*************************Payload phase ************************************/
03839
03840     /* Set the phase */
03841     hcryp->Phase = CRYP_PHASE_PROCESS;
03842
03843     /* Select payload phase once the header phase is performed */
03844     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03845
03846     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03847     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03848
03849   } /* if (DoKeyIVConfig == 1U) */
03850
03851   if ((hcryp->Size % 16U) != 0U)
03852   {
03853     /* recalculate  wordsize */
03854     wordsize = ((wordsize / 4U) * 4U) ;
03855   }
03856   /* Get tick */
03857   tickstart = HAL_GetTick();
03858
03859   /* Write input data and get output data */
03860   incount = hcryp->CrypInCount;
03861   outcount = hcryp->CrypOutCount;
03862   while ((incount < wordsize) && (outcount < wordsize))
03863   {
03864     /* Write plain data and get cipher data */
03865     CRYP_AES_ProcessData(hcryp, Timeout);
03866
03867     /* Check for the Timeout */
03868     if (Timeout != HAL_MAX_DELAY)
03869     {
03870       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03871       {
03872         /* Disable the CRYP peripheral clock */
03873         __HAL_CRYP_DISABLE(hcryp);
03874
03875         /* Change state */
03876         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03877         hcryp->State = HAL_CRYP_STATE_READY;
03878
03879         /* Process unlocked */
03880         __HAL_UNLOCK(hcryp);
03881         return HAL_ERROR;
03882       }
03883     }
03884     incount = hcryp->CrypInCount;
03885     outcount = hcryp->CrypOutCount;
03886   }
03887
03888   if ((hcryp->Size % 16U) != 0U)
03889   {
03890     /* Compute the number of padding bytes in last block of payload */
03891     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03892
03893     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
03894     {
03895       /* Set Npblb in case of AES CCM payload decryption to get right tag  */
03896       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20);
03897
03898     }
03899     /* Number of valid words (lastwordsize) in last block */
03900     if ((npblb % 4U) == 0U)
03901     {
03902       lastwordsize = (16U - npblb) / 4U;
03903     }
03904     else
03905     {
03906       lastwordsize = ((16U - npblb) / 4U) + 1U;
03907     }
03908
03909     /* Write the last input block in the IN FIFO */
03910     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
03911     {
03912       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03913       hcryp->CrypInCount++;
03914     }
03915
03916     /* Pad the data with zeros to have a complete block */
03917     while (loopcounter < 4U)
03918     {
03919       hcryp->Instance->DINR  = 0U;
03920       loopcounter++;
03921     }
03922     /* just wait for hash computation */
03923     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03924     {
03925       /* Change state */
03926       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03927       hcryp->State = HAL_CRYP_STATE_READY;
03928
03929       /* Process unlocked & return error */
03930       __HAL_UNLOCK(hcryp);
03931       return HAL_ERROR;
03932     }
03933     /* Clear CCF flag */
03934     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03935
03936     for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
03937     {
03938       /* Read the output block from the output FIFO and put them in temporary buffer
03939          then get CrypOutBuff from temporary buffer */
03940       temp[loopcounter] = hcryp->Instance->DOUTR;
03941     }
03942     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
03943     {
03944       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
03945       hcryp->CrypOutCount++;
03946     }
03947   }
03948
03949   /* Return function status */
03950   return HAL_OK;
03951 }
03952
03953 /**
03954   * @brief  AES CCM encryption/decryption process in interrupt mode
03955   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03956   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03957   *         the configuration information for CRYP module
03958   * @retval HAL status
03959   */
03960 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03961 {
03962   __IO uint32_t count = 0U;
03963   uint32_t loopcounter;
03964   uint32_t lastwordsize;
03965   uint32_t npblb;
03966   uint32_t mode;
03967   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03968   uint32_t headersize_in_bytes;
03969   uint32_t tmp;
03970   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
03971                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
03972                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
03973                                     }; /*  8-bit data type */
03974
03975 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03976   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03977   {
03978     CRYP_PhaseProcessingResume(hcryp);
03979     return HAL_OK;
03980   }
03981 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03982
03983   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03984   {
03985     if (hcryp->KeyIVConfig == 1U)
03986     {
03987       /* If the Key and IV configuration has to be done only once
03988          and if it has already been done, skip it */
03989       DoKeyIVConfig = 0U;
03990       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03991     }
03992     else
03993     {
03994       /* If the Key and IV configuration has to be done only once
03995          and if it has not been done already, do it and set KeyIVConfig
03996          to keep track it won't have to be done again next time */
03997       hcryp->KeyIVConfig = 1U;
03998       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03999     }
04000   }
04001   else
04002   {
04003     hcryp->SizesSum = hcryp->Size;
04004   }
04005
04006   /* Configure Key, IV and process message (header and payload) */
04007   if (DoKeyIVConfig == 1U)
04008   {
04009     /*  Reset CrypHeaderCount */
04010     hcryp->CrypHeaderCount = 0U;
04011
04012     /********************** Init phase ******************************************/
04013
04014     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
04015
04016     /* Set the key */
04017     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
04018
04019     /* Set the initialization vector (IV) with B0 */
04020     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
04021     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
04022     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
04023     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
04024
04025     /* Enable the CRYP peripheral */
04026     __HAL_CRYP_ENABLE(hcryp);
04027
04028     /* just wait for hash computation */
04029     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
04030     do
04031     {
04032       count-- ;
04033       if (count == 0U)
04034       {
04035         /* Disable the CRYP peripheral clock */
04036         __HAL_CRYP_DISABLE(hcryp);
04037
04038         /* Change state */
04039         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04040         hcryp->State = HAL_CRYP_STATE_READY;
04041
04042         /* Process unlocked */
04043         __HAL_UNLOCK(hcryp);
04044         return HAL_ERROR;
04045       }
04046     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04047
04048     /* Clear CCF flag */
04049     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04050
04051     /***************************** Header phase *********************************/
04052
04053     /* Select header phase */
04054     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04055
04056     /* Enable computation complete flag and error interrupts */
04057     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04058
04059     /* Enable the CRYP peripheral */
04060     __HAL_CRYP_ENABLE(hcryp);
04061
04062     if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04063     {
04064       headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
04065     }
04066     else
04067     {
04068       headersize_in_bytes = hcryp->Init.HeaderSize;
04069     }
04070
04071     if (headersize_in_bytes == 0U) /* Header phase is  skipped */
04072     {
04073       /* Set the phase */
04074       hcryp->Phase = CRYP_PHASE_PROCESS;
04075       /* Select payload phase once the header phase is performed */
04076       CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
04077       /* Set to 0 the number of non-valid bytes using NPBLB register*/
04078       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04079
04080       if (hcryp->Init.Algorithm == CRYP_AES_CCM)
04081       {
04082         /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
04083         hcryp->CrypHeaderCount++;
04084       }
04085       /* Write the payload Input block in the IN FIFO */
04086       if (hcryp->Size == 0U)
04087       {
04088         /* Disable interrupts */
04089         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04090
04091         /* Change the CRYP state */
04092         hcryp->State = HAL_CRYP_STATE_READY;
04093
04094         /* Process unlocked */
04095         __HAL_UNLOCK(hcryp);
04096       }
04097       else if (hcryp->Size >= 16U)
04098       {
04099         hcryp->CrypInCount++;
04100         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04101         hcryp->CrypInCount++;
04102         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04103         hcryp->CrypInCount++;
04104         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04105         hcryp->CrypInCount++;
04106         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04107
04108         if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04109         {
04110           /* Call Input transfer complete callback */
04111 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04112           /*Call registered Input complete callback*/
04113           hcryp->InCpltCallback(hcryp);
04114 #else
04115           /*Call legacy weak Input complete callback*/
04116           HAL_CRYP_InCpltCallback(hcryp);
04117 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04118         }
04119       }
04120       else /* Size < 4 words  : first block is the last block*/
04121       {
04122         /* Compute the number of padding bytes in last block of payload */
04123         npblb = 16U - (uint32_t)hcryp->Size;
04124
04125         mode = hcryp->Instance->CR & AES_CR_MODE;
04126         if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04127             ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04128         {
04129           /* Specify the number of non-valid bytes using NPBLB register*/
04130           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04131         }
04132
04133         /* Number of valid words (lastwordsize) in last block */
04134         if ((npblb % 4U) == 0U)
04135         {
04136           lastwordsize = (16U - npblb) / 4U;
04137         }
04138         else
04139         {
04140           lastwordsize = ((16U - npblb) / 4U) + 1U;
04141         }
04142
04143         /*  Last block optionally pad the data with zeros*/
04144         for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04145         {
04146           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04147           hcryp->CrypInCount++;
04148         }
04149         while (loopcounter < 4U)
04150         {
04151           /* Pad the data with zeros to have a complete block */
04152           hcryp->Instance->DINR = 0x0U;
04153           loopcounter++;
04154         }
04155         /* Call Input transfer complete callback */
04156 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04157         /*Call registered Input complete callback*/
04158         hcryp->InCpltCallback(hcryp);
04159 #else
04160         /*Call legacy weak Input complete callback*/
04161         HAL_CRYP_InCpltCallback(hcryp);
04162 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04163       }
04164     }
04165     /* Enter header data */
04166     /* Check first whether header length is small enough to enter the full header in one shot */
04167     else if (headersize_in_bytes <= 16U)
04168     {
04169       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
04170       {
04171         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04172         hcryp->CrypHeaderCount++ ;
04173       }
04174       /* If the header size is a multiple of words */
04175       if ((headersize_in_bytes % 4U) == 0U)
04176       {
04177         /* Pad the data with zeros to have a complete block */
04178         while (loopcounter < 4U)
04179         {
04180           hcryp->Instance->DINR = 0x0U;
04181           loopcounter++;
04182         }
04183       }
04184       else
04185       {
04186         /* Enter last bytes, padded with zeros */
04187         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04188         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
04189         hcryp->Instance->DINR = tmp;
04190         hcryp->CrypHeaderCount++;
04191         loopcounter++;
04192         /* Pad the data with zeros to have a complete block */
04193         while (loopcounter < 4U)
04194         {
04195           hcryp->Instance->DINR = 0x0U;
04196           loopcounter++;
04197         }
04198       }
04199       /* Call Input transfer complete callback */
04200 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04201       /*Call registered Input complete callback*/
04202       hcryp->InCpltCallback(hcryp);
04203 #else
04204       /*Call legacy weak Input complete callback*/
04205       HAL_CRYP_InCpltCallback(hcryp);
04206 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04207     }
04208     else
04209     {
04210       /* Write the first input header block in the Input FIFO,
04211          the following header data will be fed after interrupt occurrence */
04212       hcryp->CrypHeaderCount++;
04213       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
04214       hcryp->CrypHeaderCount++;
04215       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
04216       hcryp->CrypHeaderCount++;
04217       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
04218       hcryp->CrypHeaderCount++;
04219       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
04220     }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is  skipped*/
04221   } /* end of if (dokeyivconfig == 1U) */
04222   else  /* Key and IV have already been configured,
04223           header has already been processed;
04224           only process here message payload */
04225   {
04226     /* Write the payload Input block in the IN FIFO */
04227     if (hcryp->Size == 0U)
04228     {
04229       /* Disable interrupts */
04230       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04231
04232       /* Change the CRYP state */
04233       hcryp->State = HAL_CRYP_STATE_READY;
04234
04235       /* Process unlocked */
04236       __HAL_UNLOCK(hcryp);
04237     }
04238     else if (hcryp->Size >= 16U)
04239     {
04240       hcryp->CrypInCount++;
04241       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04242       hcryp->CrypInCount++;
04243       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04244       hcryp->CrypInCount++;
04245       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04246       hcryp->CrypInCount++;
04247       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
04248
04249       if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04250       {
04251         /* Call Input transfer complete callback */
04252 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04253         /*Call registered Input complete callback*/
04254         hcryp->InCpltCallback(hcryp);
04255 #else
04256         /*Call legacy weak Input complete callback*/
04257         HAL_CRYP_InCpltCallback(hcryp);
04258 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04259       }
04260     }
04261     else /* Size < 4 words  : first block is the last block*/
04262     {
04263       /* Compute the number of padding bytes in last block of payload */
04264       npblb = 16U - (uint32_t)hcryp->Size;
04265
04266       mode = hcryp->Instance->CR & AES_CR_MODE;
04267       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04268           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04269       {
04270         /* Specify the number of non-valid bytes using NPBLB register*/
04271         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04272       }
04273
04274       /* Number of valid words (lastwordsize) in last block */
04275       if ((npblb % 4U) == 0U)
04276       {
04277         lastwordsize = (16U - npblb) / 4U;
04278       }
04279       else
04280       {
04281         lastwordsize = ((16U - npblb) / 4U) + 1U;
04282       }
04283
04284       /*  Last block optionally pad the data with zeros*/
04285       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04286       {
04287         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04288         hcryp->CrypInCount++;
04289       }
04290       while (loopcounter < 4U)
04291       {
04292         /* Pad the data with zeros to have a complete block */
04293         hcryp->Instance->DINR = 0x0U;
04294         loopcounter++;
04295       }
04296       /* Call Input transfer complete callback */
04297 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04298       /*Call registered Input complete callback*/
04299       hcryp->InCpltCallback(hcryp);
04300 #else
04301       /*Call legacy weak Input complete callback*/
04302       HAL_CRYP_InCpltCallback(hcryp);
04303 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04304     }
04305   }
04306
04307   /* Return function status */
04308   return HAL_OK;
04309 }
04310
04311 /**
04312   * @brief  AES CCM encryption/decryption process in DMA mode
04313   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
04314   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04315   *         the configuration information for CRYP module
04316   * @retval HAL status
04317   */
04318 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
04319 {
04320   uint32_t count;
04321   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
04322
04323   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
04324   {
04325     if (hcryp->KeyIVConfig == 1U)
04326     {
04327       /* If the Key and IV configuration has to be done only once
04328          and if it has already been done, skip it */
04329       DoKeyIVConfig = 0U;
04330       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
04331     }
04332     else
04333     {
04334       /* If the Key and IV configuration has to be done only once
04335          and if it has not been done already, do it and set KeyIVConfig
04336          to keep track it won't have to be done again next time */
04337       hcryp->KeyIVConfig = 1U;
04338       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
04339     }
04340   }
04341   else
04342   {
04343     hcryp->SizesSum = hcryp->Size;
04344   }
04345
04346   if (DoKeyIVConfig == 1U)
04347   {
04348
04349     /*  Reset CrypHeaderCount */
04350     hcryp->CrypHeaderCount = 0U;
04351
04352
04353     /********************** Init phase ******************************************/
04354
04355     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
04356
04357     /* Set the key */
04358     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
04359
04360     /* Set the initialization vector (IV) with B0 */
04361     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
04362     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
04363     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
04364     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
04365
04366     /* Enable the CRYP peripheral */
04367     __HAL_CRYP_ENABLE(hcryp);
04368
04369     /* just wait for hash computation */
04370     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
04371     do
04372     {
04373       count-- ;
04374       if (count == 0U)
04375       {
04376         /* Disable the CRYP peripheral clock */
04377         __HAL_CRYP_DISABLE(hcryp);
04378
04379         /* Change state */
04380         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04381         hcryp->State = HAL_CRYP_STATE_READY;
04382
04383         /* Process unlocked */
04384         __HAL_UNLOCK(hcryp);
04385         return HAL_ERROR;
04386       }
04387     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04388
04389     /* Clear CCF flag */
04390     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04391
04392
04393     /********************* Header phase *****************************************/
04394
04395     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
04396     {
04397       return HAL_ERROR;
04398     }
04399
04400   }
04401   else
04402   {
04403     /* Initialization and header phases already done, only do payload phase */
04404     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
04405     {
04406       return HAL_ERROR;
04407     }
04408   } /* if (DoKeyIVConfig == 1U) */
04409
04410   /* Return function status */
04411   return HAL_OK;
04412 }
04413
04414 /**
04415   * @brief  Sets the payload phase in interrupt mode
04416   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04417   *         the configuration information for CRYP module
04418   * @retval state
04419   */
04420 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
04421 {
04422   uint32_t loopcounter;
04423   uint32_t temp[4];  /* Temporary CrypOutBuff */
04424   uint32_t lastwordsize;
04425   uint32_t npblb;
04426   uint32_t mode;
04427   uint16_t incount;  /* Temporary CrypInCount Value */
04428   uint16_t outcount;  /* Temporary CrypOutCount Value */
04429   uint32_t i;
04430
04431   /***************************** Payload phase *******************************/
04432
04433   /* Read the output block from the output FIFO and put them in temporary buffer
04434      then get CrypOutBuff from temporary buffer*/
04435   for (i = 0U; i < 4U; i++)
04436   {
04437     temp[i] = hcryp->Instance->DOUTR;
04438   }
04439   i = 0U;
04440   while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
04441   {
04442     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
04443     hcryp->CrypOutCount++;
04444     i++;
04445   }
04446   incount = hcryp->CrypInCount;
04447   outcount = hcryp->CrypOutCount;
04448   if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >=  hcryp->Size))
04449   {
04450
04451     /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
04452     if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
04453     {
04454       /* Disable computation complete flag and errors interrupts */
04455       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04456     }
04457
04458     /* Change the CRYP state */
04459     hcryp->State = HAL_CRYP_STATE_READY;
04460
04461     /* Process unlocked */
04462     __HAL_UNLOCK(hcryp);
04463
04464     /* Call output transfer complete callback */
04465 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04466     /*Call registered Output complete callback*/
04467     hcryp->OutCpltCallback(hcryp);
04468 #else
04469     /*Call legacy weak Output complete callback*/
04470     HAL_CRYP_OutCpltCallback(hcryp);
04471 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04472   }
04473
04474   else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
04475   {
04476
04477 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
04478     /* If suspension flag has been raised, suspend processing
04479        only if not already at the end of the payload */
04480     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
04481     {
04482       /* Clear CCF Flag */
04483       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04484
04485       /* reset SuspendRequest */
04486       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
04487       /* Disable Computation Complete Flag and Errors Interrupts */
04488       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04489       /* Change the CRYP state */
04490       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
04491       /* Mark that the payload phase is suspended */
04492       hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
04493
04494       /* Process Unlocked */
04495       __HAL_UNLOCK(hcryp);
04496     }
04497     else
04498 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
04499     {
04500       /* Write the input block in the IN FIFO */
04501       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04502       hcryp->CrypInCount++;
04503       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04504       hcryp->CrypInCount++;
04505       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04506       hcryp->CrypInCount++;
04507       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04508       hcryp->CrypInCount++;
04509       if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04510       {
04511         /* Call input transfer complete callback */
04512 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04513         /*Call registered Input complete callback*/
04514         hcryp->InCpltCallback(hcryp);
04515 #else
04516         /*Call legacy weak Input complete callback*/
04517         HAL_CRYP_InCpltCallback(hcryp);
04518 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04519       }
04520     }
04521   }
04522   else /* Last block of payload < 128bit*/
04523   {
04524     /* Compute the number of padding bytes in last block of payload */
04525     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
04526
04527     mode = hcryp->Instance->CR & AES_CR_MODE;
04528     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04529         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04530     {
04531       /* Specify the number of non-valid bytes using NPBLB register*/
04532       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04533     }
04534
04535     /* Number of valid words (lastwordsize) in last block */
04536     if ((npblb % 4U) == 0U)
04537     {
04538       lastwordsize = (16U - npblb) / 4U;
04539     }
04540     else
04541     {
04542       lastwordsize = ((16U - npblb) / 4U) + 1U;
04543     }
04544
04545     /*  Last block optionally pad the data with zeros*/
04546     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04547     {
04548       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04549       hcryp->CrypInCount++;
04550     }
04551     while (loopcounter < 4U)
04552     {
04553       /* pad the data with zeros to have a complete block */
04554       hcryp->Instance->DINR = 0x0U;
04555       loopcounter++;
04556     }
04557     /* Call input transfer complete callback */
04558 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04559     /*Call registered Input complete callback*/
04560     hcryp->InCpltCallback(hcryp);
04561 #else
04562     /*Call legacy weak Input complete callback*/
04563     HAL_CRYP_InCpltCallback(hcryp);
04564 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04565   }
04566 }
04567
04568
04569 /**
04570   * @brief  Sets the payload phase in DMA mode
04571   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04572   *         the configuration information for CRYP module
04573   * @retval state
04574   */
04575 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
04576 {
04577   uint16_t wordsize = hcryp->Size / 4U ;
04578   uint32_t index;
04579   uint32_t npblb;
04580   uint32_t lastwordsize;
04581   uint32_t temp[4];  /* Temporary CrypOutBuff */
04582   uint32_t count;
04583   uint32_t reg;
04584
04585   /************************ Payload phase ************************************/
04586   if (hcryp->Size == 0U)
04587   {
04588     /* Process unLocked */
04589     __HAL_UNLOCK(hcryp);
04590
04591     /* Change the CRYP state and phase */
04592     hcryp->State = HAL_CRYP_STATE_READY;
04593   }
04594   else if (hcryp->Size >= 16U)
04595   {
04596     /*DMA transfer must not include the last block in case of Size is not %16 */
04597     wordsize = wordsize - (wordsize % 4U);
04598
04599     /*DMA transfer */
04600     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
04601   }
04602   else /* length of input data is < 16 */
04603   {
04604     /* Compute the number of padding bytes in last block of payload */
04605     npblb = 16U - (uint32_t)hcryp->Size;
04606
04607     /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
04608     reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE);
04609     if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \
04610         (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT)))
04611     {
04612       /* Specify the number of non-valid bytes using NPBLB register*/
04613       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04614     }
04615
04616     /* Number of valid words (lastwordsize) in last block */
04617     if ((npblb % 4U) == 0U)
04618     {
04619       lastwordsize = (16U - npblb) / 4U;
04620     }
04621     else
04622     {
04623       lastwordsize = ((16U - npblb) / 4U) + 1U;
04624     }
04625
04626     /*  last block optionally pad the data with zeros*/
04627     for (index = 0U; index < lastwordsize; index ++)
04628     {
04629       /* Write the last Input block in the IN FIFO */
04630       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04631       hcryp->CrypInCount++;
04632     }
04633     while (index < 4U)
04634     {
04635       /* pad the data with zeros to have a complete block */
04636       hcryp->Instance->DINR  = 0U;
04637       index++;
04638     }
04639     /* Call the input data transfer complete callback */
04640 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04641     /*Call registered Input complete callback*/
04642     hcryp->InCpltCallback(hcryp);
04643 #else
04644     /*Call legacy weak Input complete callback*/
04645     HAL_CRYP_InCpltCallback(hcryp);
04646 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04647     /* Wait for CCF flag to be raised */
04648     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04649     do
04650     {
04651       count-- ;
04652       if (count == 0U)
04653       {
04654         /* Disable the CRYP peripheral clock */
04655         __HAL_CRYP_DISABLE(hcryp);
04656
04657         /* Change state */
04658         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04659         hcryp->State = HAL_CRYP_STATE_READY;
04660
04661         /* Process unlocked */
04662         __HAL_UNLOCK(hcryp);
04663         return HAL_ERROR;
04664       }
04665     } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04666
04667     /* Clear CCF Flag */
04668     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04669
04670     /*Read the output block from the output FIFO */
04671     for (index = 0U; index < 4U; index++)
04672     {
04673       /* Read the output block from the output FIFO and put them in temporary buffer
04674          then get CrypOutBuff from temporary buffer */
04675       temp[index] = hcryp->Instance->DOUTR;
04676     }
04677     for (index = 0U; index < lastwordsize; index++)
04678     {
04679       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
04680       hcryp->CrypOutCount++;
04681     }
04682
04683     /* Change the CRYP state to ready */
04684     hcryp->State = HAL_CRYP_STATE_READY;
04685
04686     /* Process unlocked */
04687     __HAL_UNLOCK(hcryp);
04688
04689     /* Call Output transfer complete callback */
04690 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04691     /*Call registered Output complete callback*/
04692     hcryp->OutCpltCallback(hcryp);
04693 #else
04694     /*Call legacy weak Output complete callback*/
04695     HAL_CRYP_OutCpltCallback(hcryp);
04696 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04697   }
04698
04699   return HAL_OK;
04700 }
04701
04702 /**
04703   * @brief  Sets the header phase in polling mode
04704   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04705   *         the configuration information for CRYP module(Header & HeaderSize)
04706   * @param  Timeout Timeout value
04707   * @retval state
04708   */
04709 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04710 {
04711   uint32_t loopcounter;
04712   uint32_t size_in_bytes;
04713   uint32_t tmp;
04714   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04715                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
04716                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
04717                                     }; /*  8-bit data type */
04718
04719   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04720   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04721   {
04722     size_in_bytes = hcryp->Init.HeaderSize * 4U;
04723   }
04724   else
04725   {
04726     size_in_bytes = hcryp->Init.HeaderSize;
04727   }
04728
04729   if ((size_in_bytes != 0U))
04730   {
04731     /* Select header phase */
04732     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04733
04734     /* Enable the CRYP peripheral */
04735     __HAL_CRYP_ENABLE(hcryp);
04736
04737     /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
04738     if ((size_in_bytes % 16U) == 0U)
04739     {
04740       /*  No padding */
04741       for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
04742       {
04743         /* Write the input block in the data input register */
04744         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04745         hcryp->CrypHeaderCount++ ;
04746         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04747         hcryp->CrypHeaderCount++ ;
04748         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04749         hcryp->CrypHeaderCount++ ;
04750         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04751         hcryp->CrypHeaderCount++ ;
04752
04753         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04754         {
04755           /* Disable the CRYP peripheral clock */
04756           __HAL_CRYP_DISABLE(hcryp);
04757
04758           /* Change state */
04759           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04760           hcryp->State = HAL_CRYP_STATE_READY;
04761
04762           /* Process unlocked */
04763           __HAL_UNLOCK(hcryp);
04764           return HAL_ERROR;
04765         }
04766         /* Clear CCF flag */
04767         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04768       }
04769     }
04770     else
04771     {
04772       /* Write header block in the IN FIFO without last block */
04773       for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
04774       {
04775         /* Write the input block in the data input register */
04776         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04777         hcryp->CrypHeaderCount++ ;
04778         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04779         hcryp->CrypHeaderCount++ ;
04780         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04781         hcryp->CrypHeaderCount++ ;
04782         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04783         hcryp->CrypHeaderCount++ ;
04784
04785         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04786         {
04787           /* Disable the CRYP peripheral clock */
04788           __HAL_CRYP_DISABLE(hcryp);
04789
04790           /* Change state */
04791           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04792           hcryp->State = HAL_CRYP_STATE_READY;
04793
04794           /* Process unlocked */
04795           __HAL_UNLOCK(hcryp);
04796           return HAL_ERROR;
04797         }
04798         /* Clear CCF flag */
04799         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04800       }
04801       /* Write last complete words */
04802       for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
04803       {
04804         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04805         hcryp->CrypHeaderCount++ ;
04806       }
04807       /* If the header size is a multiple of words */
04808       if ((size_in_bytes % 4U) == 0U)
04809       {
04810         /* Pad the data with zeros to have a complete block */
04811         while (loopcounter < 4U)
04812         {
04813           hcryp->Instance->DINR = 0x0U;
04814           loopcounter++;
04815         }
04816       }
04817       else
04818       {
04819         /* Enter last bytes, padded with zeros */
04820         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04821         tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
04822         hcryp->Instance->DINR = tmp;
04823         loopcounter++;
04824         /* Pad the data with zeros to have a complete block */
04825         while (loopcounter < 4U)
04826         {
04827           hcryp->Instance->DINR = 0x0U;
04828           loopcounter++;
04829         }
04830       }
04831
04832       if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04833       {
04834         /* Disable the CRYP peripheral clock */
04835         __HAL_CRYP_DISABLE(hcryp);
04836
04837         /* Change state */
04838         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04839         hcryp->State = HAL_CRYP_STATE_READY;
04840
04841         /* Process unlocked */
04842         __HAL_UNLOCK(hcryp);
04843         return HAL_ERROR;
04844       }
04845       /* Clear CCF flag */
04846       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04847     }
04848   }
04849   else
04850   {
04851     /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
04852     MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
04853
04854     /* Select header phase */
04855     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04856
04857     /* Enable the CRYP peripheral */
04858     __HAL_CRYP_ENABLE(hcryp);
04859   }
04860   /* Return function status */
04861   return HAL_OK;
04862 }
04863
04864 /**
04865   * @brief  Sets the header phase when using DMA in process
04866   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04867   *         the configuration information for CRYP module(Header & HeaderSize)
04868   * @retval None
04869   */
04870 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
04871 {
04872   uint32_t loopcounter;
04873   uint32_t headersize_in_bytes;
04874   uint32_t tmp;
04875   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04876                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
04877                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
04878                                     }; /*  8-bit data type */
04879
04880   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04881   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04882   {
04883     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
04884   }
04885   else
04886   {
04887     headersize_in_bytes = hcryp->Init.HeaderSize;
04888   }
04889
04890   /* Select header phase */
04891   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04892
04893   /* Enable the CRYP peripheral */
04894   __HAL_CRYP_ENABLE(hcryp);
04895
04896   /* Set the phase */
04897   hcryp->Phase = CRYP_PHASE_PROCESS;
04898
04899   /* If header size is at least equal to 16 bytes, feed the header through DMA.
04900      If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
04901      last bytes feeding and padding will be done in CRYP_DMAInCplt() */
04902   if (headersize_in_bytes >= 16U)
04903   {
04904     /* Initiate header DMA transfer */
04905     if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header),
04906                                 (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
04907     {
04908       return HAL_ERROR;
04909     }
04910   }
04911   else
04912   {
04913     if (headersize_in_bytes != 0U)
04914     {
04915       /* Header length is larger than 0 and strictly less than 16 bytes */
04916       /* Write last complete words */
04917       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
04918       {
04919         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04920         hcryp->CrypHeaderCount++ ;
04921       }
04922       /* If the header size is a multiple of words */
04923       if ((headersize_in_bytes % 4U) == 0U)
04924       {
04925         /* Pad the data with zeros to have a complete block */
04926         while (loopcounter < 4U)
04927         {
04928           hcryp->Instance->DINR = 0x0U;
04929           loopcounter++;
04930         }
04931       }
04932       else
04933       {
04934         /* Enter last bytes, padded with zeros */
04935         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04936         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
04937         hcryp->Instance->DINR = tmp;
04938         loopcounter++;
04939         /* Pad the data with zeros to have a complete block */
04940         while (loopcounter < 4U)
04941         {
04942           hcryp->Instance->DINR = 0x0U;
04943           loopcounter++;
04944         }
04945       }
04946
04947       if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
04948       {
04949         /* Disable the CRYP peripheral clock */
04950         __HAL_CRYP_DISABLE(hcryp);
04951
04952         /* Change state */
04953         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04954         hcryp->State = HAL_CRYP_STATE_READY;
04955
04956         /* Process unlocked */
04957         __HAL_UNLOCK(hcryp);
04958         return HAL_ERROR;
04959       }
04960       /* Clear CCF flag */
04961       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04962     } /* if (headersize_in_bytes != 0U) */
04963
04964     /* Move to payload phase if header length is null or
04965        if the header length was less than 16 and header written by software instead of DMA */
04966
04967     /* Set to 0 the number of non-valid bytes using NPBLB register*/
04968     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04969
04970     /* Select payload phase once the header phase is performed */
04971     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
04972
04973     /* Initiate payload DMA IN and processed data DMA OUT transfers */
04974     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
04975     {
04976       return HAL_ERROR;
04977     }
04978   } /* if (headersize_in_bytes >= 16U) */
04979
04980   /* Return function status */
04981   return HAL_OK;
04982 }
04983
04984 /**
04985   * @brief  Sets the header phase in interrupt mode
04986   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04987   *         the configuration information for CRYP module(Header & HeaderSize)
04988   * @retval None
04989   */
04990 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
04991 {
04992   uint32_t loopcounter;
04993   uint32_t lastwordsize;
04994   uint32_t npblb;
04995   uint32_t mode;
04996   uint32_t headersize_in_bytes;
04997   uint32_t tmp;
04998   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04999                                      0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
05000                                      0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
05001                                     }; /*  8-bit data type */
05002
05003   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
05004   {
05005     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
05006   }
05007   else
05008   {
05009     headersize_in_bytes = hcryp->Init.HeaderSize;
05010   }
05011
05012   /***************************** Header phase *********************************/
05013   /* Test whether or not the header phase is over.
05014      If the test below is true, move to payload phase */
05015   if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
05016   {
05017     /* Set the phase */
05018     hcryp->Phase = CRYP_PHASE_PROCESS;
05019     /* Select payload phase */
05020     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
05021     /* Set to 0 the number of non-valid bytes using NPBLB register*/
05022     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
05023
05024     if (hcryp->Init.Algorithm == CRYP_AES_CCM)
05025     {
05026       /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
05027       hcryp->CrypHeaderCount++;
05028     }
05029     /* Write the payload Input block in the IN FIFO */
05030     if (hcryp->Size == 0U)
05031     {
05032       /* Disable interrupts */
05033       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
05034
05035       /* Change the CRYP state */
05036       hcryp->State = HAL_CRYP_STATE_READY;
05037
05038       /* Process unlocked */
05039       __HAL_UNLOCK(hcryp);
05040     }
05041     else if (hcryp->Size >= 16U)
05042     {
05043       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05044       hcryp->CrypInCount++;
05045       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05046       hcryp->CrypInCount++;
05047       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05048       hcryp->CrypInCount++;
05049       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05050       hcryp->CrypInCount++;
05051
05052       if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
05053       {
05054         /* Call the input data transfer complete callback */
05055 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05056         /*Call registered Input complete callback*/
05057         hcryp->InCpltCallback(hcryp);
05058 #else
05059         /*Call legacy weak Input complete callback*/
05060         HAL_CRYP_InCpltCallback(hcryp);
05061 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05062       }
05063     }
05064     else /* Size < 4 words  : first block is the last block*/
05065     {
05066       /* Compute the number of padding bytes in last block of payload */
05067       npblb = 16U - ((uint32_t)hcryp->Size);
05068       mode = hcryp->Instance->CR & AES_CR_MODE;
05069       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
05070           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
05071       {
05072         /* Specify the number of non-valid bytes using NPBLB register*/
05073         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
05074       }
05075
05076       /* Number of valid words (lastwordsize) in last block */
05077       if ((npblb % 4U) == 0U)
05078       {
05079         lastwordsize = (16U - npblb) / 4U;
05080       }
05081       else
05082       {
05083         lastwordsize = ((16U - npblb) / 4U) + 1U;
05084       }
05085
05086       /*  Last block optionally pad the data with zeros*/
05087       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
05088       {
05089         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05090         hcryp->CrypInCount++;
05091       }
05092       while (loopcounter < 4U)
05093       {
05094         /* Pad the data with zeros to have a complete block */
05095         hcryp->Instance->DINR = 0x0U;
05096         loopcounter++;
05097       }
05098       /* Call the input data transfer complete callback */
05099 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05100       /*Call registered Input complete callback*/
05101       hcryp->InCpltCallback(hcryp);
05102 #else
05103       /*Call legacy weak Input complete callback*/
05104       HAL_CRYP_InCpltCallback(hcryp);
05105 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05106     }
05107   }
05108   else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
05109   {
05110     /* Can enter full 4 header words */
05111 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
05112     /* If suspension flag has been raised, suspend processing
05113        only if not already at the end of the header */
05114     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
05115     {
05116       /* Clear CCF Flag */
05117       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
05118
05119       /* reset SuspendRequest */
05120       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
05121       /* Disable Computation Complete Flag and Errors Interrupts */
05122       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
05123       /* Change the CRYP state */
05124       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
05125       /* Mark that the payload phase is suspended */
05126       hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
05127
05128       /* Process Unlocked */
05129       __HAL_UNLOCK(hcryp);
05130     }
05131     else
05132 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
05133     {
05134       /* Write the input block in the IN FIFO */
05135       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05136       hcryp->CrypHeaderCount++;
05137       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05138       hcryp->CrypHeaderCount++;
05139       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05140       hcryp->CrypHeaderCount++;
05141       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05142       hcryp->CrypHeaderCount++;
05143     }
05144   }
05145   else /* Write last header block (4 words), padded with zeros if needed */
05146   {
05147
05148     for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
05149     {
05150       hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05151       hcryp->CrypHeaderCount++ ;
05152     }
05153     /* If the header size is a multiple of words */
05154     if ((headersize_in_bytes % 4U) == 0U)
05155     {
05156       /* Pad the data with zeros to have a complete block */
05157       while (loopcounter < 4U)
05158       {
05159         hcryp->Instance->DINR = 0x0U;
05160         loopcounter++;
05161         hcryp->CrypHeaderCount++;
05162       }
05163     }
05164     else
05165     {
05166       /* Enter last bytes, padded with zeros */
05167       tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05168       tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
05169       hcryp->Instance->DINR = tmp;
05170       loopcounter++;
05171       hcryp->CrypHeaderCount++;
05172       /* Pad the data with zeros to have a complete block */
05173       while (loopcounter < 4U)
05174       {
05175         hcryp->Instance->DINR = 0x0U;
05176         loopcounter++;
05177         hcryp->CrypHeaderCount++;
05178       }
05179     }
05180   }
05181 }
05182
05183 /**
05184   * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
05185   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05186   *         the configuration information for CRYP module.
05187   * @param  Timeout Timeout duration.
05188   * @note   This function can only be used in thread mode.
05189   * @retval HAL status
05190   */
05191 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
05192 {
05193   uint32_t tickstart;
05194
05195   /* Get timeout */
05196   tickstart = HAL_GetTick();
05197
05198   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
05199   {
05200     /* Check for the Timeout */
05201     if (Timeout != HAL_MAX_DELAY)
05202     {
05203       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
05204       {
05205         return HAL_ERROR;
05206       }
05207     }
05208   }
05209   return HAL_OK;
05210 }
05211
05212 /**
05213   * @brief  Wait for Computation Complete Flag (CCF) to raise then clear it.
05214   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05215   *         the configuration information for CRYP module.
05216   * @param  Timeout Timeout duration.
05217   * @note   This function can be used in thread or handler mode.
05218   * @retval HAL status
05219   */
05220 static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
05221 {
05222   uint32_t count = Timeout;
05223
05224   do
05225   {
05226     count-- ;
05227     if (count == 0U)
05228     {
05229       /* Disable the CRYP peripheral clock */
05230       __HAL_CRYP_DISABLE(hcryp);
05231
05232       /* Change state */
05233       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
05234
05235       /* Process unlocked */
05236       __HAL_UNLOCK(hcryp);
05237       hcryp->State = HAL_CRYP_STATE_READY;
05238
05239 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05240       /*Call registered error callback*/
05241       hcryp->ErrorCallback(hcryp);
05242 #else
05243       /*Call legacy weak error callback*/
05244       HAL_CRYP_ErrorCallback(hcryp);
05245 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05246     }
05247   } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
05248
05249   /* Clear CCF flag */
05250   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
05251 }
05252
05253 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
05254 /**
05255   * @brief  In case of message processing suspension, read the Initialization Vector.
05256   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05257   *         the configuration information for CRYP module.
05258   * @param  Output Pointer to the buffer containing the saved Initialization Vector.
05259   * @note   This value has to be stored for reuse by writing the AES_IVRx registers
05260   *         as soon as the suspended processing has to be resumed.
05261   * @retval None
05262   */
05263 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
05264 {
05265   uint32_t outputaddr = (uint32_t)Output;
05266
05267   *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3;
05268   outputaddr += 4U;
05269   *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2;
05270   outputaddr += 4U;
05271   *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1;
05272   outputaddr += 4U;
05273   *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0;
05274 }
05275
05276 /**
05277   * @brief  In case of message processing resumption, rewrite the Initialization
05278   *         Vector in the AES_IVRx registers.
05279   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05280   *         the configuration information for CRYP module.
05281   * @param  Input Pointer to the buffer containing the saved Initialization Vector to
05282   *         write back in the CRYP hardware block.
05283   * @note   AES must be disabled when reconfiguring the IV values.
05284   * @retval None
05285   */
05286 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
05287 {
05288   uint32_t ivaddr = (uint32_t)Input;
05289
05290   hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr);
05291   ivaddr += 4U;
05292   hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr);
05293   ivaddr += 4U;
05294   hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr);
05295   ivaddr += 4U;
05296   hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr);
05297 }
05298
05299 /**
05300   * @brief  In case of message GCM/GMAC/CCM processing suspension,
05301   *         read the Suspend Registers.
05302   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05303   *         the configuration information for CRYP module.
05304   * @param  Output Pointer to the buffer containing the saved Suspend Registers.
05305   * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers
05306   *         as soon as the suspended processing has to be resumed.
05307   * @retval None
05308   */
05309 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
05310 {
05311   uint32_t outputaddr = (uint32_t)Output;
05312   __IO uint32_t count = 0U;
05313
05314   /* In case of GCM payload phase encryption, check that suspension can be carried out */
05315   if (READ_BIT(hcryp->Instance->CR,
05316                (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | AES_CR_GCMPH_1 | 0x0U))
05317   {
05318
05319     /* Wait for BUSY flag to be cleared */
05320     count = 0xFFF;
05321     do
05322     {
05323       count-- ;
05324       if (count == 0U)
05325       {
05326         /* Change state */
05327         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
05328         hcryp->State = HAL_CRYP_STATE_READY;
05329
05330         /* Process unlocked */
05331         __HAL_UNLOCK(hcryp);
05332         HAL_CRYP_ErrorCallback(hcryp);
05333         return;
05334       }
05335     } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
05336
05337   }
05338
05339
05340   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R;
05341   outputaddr += 4U;
05342   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R;
05343   outputaddr += 4U;
05344   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R;
05345   outputaddr += 4U;
05346   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R;
05347   outputaddr += 4U;
05348   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R;
05349   outputaddr += 4U;
05350   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R;
05351   outputaddr += 4U;
05352   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R;
05353   outputaddr += 4U;
05354   *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R;
05355 }
05356
05357 /**
05358   * @brief  In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend
05359   *         Registers in the AES_SUSPxR registers.
05360   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05361   *         the configuration information for CRYP module.
05362   * @param  Input Pointer to the buffer containing the saved suspend registers to
05363   *         write back in the CRYP hardware block.
05364   * @note   AES must be disabled when reconfiguring the suspend registers.
05365   * @retval None
05366   */
05367 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
05368 {
05369   uint32_t ivaddr = (uint32_t)Input;
05370
05371   hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr);
05372   ivaddr += 4U;
05373   hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr);
05374   ivaddr += 4U;
05375   hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr);
05376   ivaddr += 4U;
05377   hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr);
05378   ivaddr += 4U;
05379   hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr);
05380   ivaddr += 4U;
05381   hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr);
05382   ivaddr += 4U;
05383   hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr);
05384   ivaddr += 4U;
05385   hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr);
05386 }
05387
05388 /**
05389   * @brief  In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
05390   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05391   *         the configuration information for CRYP module.
05392   * @param  Output Pointer to the buffer containing the saved Key Registers.
05393   * @param  KeySize Indicates the key size (128 or 256 bits).
05394   * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers
05395   *         as soon as the suspended processing has to be resumed.
05396   * @retval None
05397   */
05398 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize)
05399 {
05400   uint32_t keyaddr = (uint32_t)Output;
05401
05402   switch (KeySize)
05403   {
05404     case CRYP_KEYSIZE_256B:
05405       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05406       keyaddr += 4U;
05407       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05408       keyaddr += 4U;
05409       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05410       keyaddr += 4U;
05411       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05412       keyaddr += 4U;
05413       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
05414       keyaddr += 4U;
05415       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
05416       keyaddr += 4U;
05417       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
05418       keyaddr += 4U;
05419       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
05420       break;
05421     case CRYP_KEYSIZE_128B:
05422       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05423       keyaddr += 4U;
05424       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05425       keyaddr += 4U;
05426       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05427       keyaddr += 4U;
05428       *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05429       break;
05430     default:
05431       break;
05432   }
05433 }
05434
05435 /**
05436   * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
05437   *         Registers in the AES_KEYRx registers.
05438   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05439   *         the configuration information for CRYP module.
05440   * @param  Input Pointer to the buffer containing the saved key registers to
05441   *         write back in the CRYP hardware block.
05442   * @param  KeySize Indicates the key size (128 or 256 bits)
05443   * @note   AES must be disabled when reconfiguring the Key registers.
05444   * @retval None
05445   */
05446 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize)
05447 {
05448   uint32_t keyaddr = (uint32_t)Input;
05449
05450   if (KeySize == CRYP_KEYSIZE_256B)
05451   {
05452     hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr);
05453     keyaddr += 4U;
05454     hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr);
05455     keyaddr += 4U;
05456     hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr);
05457     keyaddr += 4U;
05458     hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr);
05459     keyaddr += 4U;
05460   }
05461
05462   hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr);
05463   keyaddr += 4U;
05464   hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr);
05465   keyaddr += 4U;
05466   hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr);
05467   keyaddr += 4U;
05468   hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr);
05469 }
05470
05471 /**
05472   * @brief  Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
05473   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05474   *         the configuration information for CRYP module(Header & HeaderSize)
05475   * @retval None
05476   */
05477 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
05478 {
05479   uint32_t loopcounter;
05480   uint16_t lastwordsize;
05481   uint16_t npblb;
05482   uint32_t cr_temp;
05483
05484
05485   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR | CRYP_CCF_CLEAR);
05486
05487   /* Enable computation complete flag and error interrupts */
05488   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
05489
05490   /* Enable the CRYP peripheral */
05491   __HAL_CRYP_ENABLE(hcryp);
05492
05493   /* Case of header phase resumption =================================================*/
05494   if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
05495   {
05496     /* Set the phase */
05497     hcryp->Phase = CRYP_PHASE_PROCESS;
05498
05499     /* Select header phase */
05500     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
05501
05502     if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
05503     {
05504       /* Write the input block in the IN FIFO */
05505       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05506       hcryp->CrypHeaderCount++;
05507       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05508       hcryp->CrypHeaderCount++;
05509       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05510       hcryp->CrypHeaderCount++;
05511       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05512       hcryp->CrypHeaderCount++;
05513     }
05514     else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
05515     {
05516       /*  Last block optionally pad the data with zeros*/
05517       for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
05518       {
05519         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05520         hcryp->CrypHeaderCount++ ;
05521       }
05522       while (loopcounter < 4U)
05523       {
05524         /* pad the data with zeros to have a complete block */
05525         hcryp->Instance->DINR = 0x0U;
05526         loopcounter++;
05527       }
05528     }
05529   }
05530   /* Case of payload phase resumption =================================================*/
05531   else
05532   {
05533     if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
05534     {
05535
05536       /* Set the phase */
05537       hcryp->Phase = CRYP_PHASE_PROCESS;
05538
05539       /* Select payload phase once the header phase is performed */
05540       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
05541
05542       /* Set to 0 the number of non-valid bytes using NPBLB register*/
05543       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
05544
05545       if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
05546       {
05547         /* Write the input block in the IN FIFO */
05548         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05549         hcryp->CrypInCount++;
05550         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05551         hcryp->CrypInCount++;
05552         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05553         hcryp->CrypInCount++;
05554         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05555         hcryp->CrypInCount++;
05556         if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
05557         {
05558           /* Call input transfer complete callback */
05559 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
05560           /*Call registered Input complete callback*/
05561           hcryp->InCpltCallback(hcryp);
05562 #else
05563           /*Call legacy weak Input complete callback*/
05564           HAL_CRYP_InCpltCallback(hcryp);
05565 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05566         }
05567       }
05568       else /* Last block of payload < 128bit*/
05569       {
05570         /* Compute the number of padding bytes in last block of payload */
05571         npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size);
05572         cr_temp = hcryp->Instance->CR;
05573         if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
05574             (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
05575         {
05576           /* Specify the number of non-valid bytes using NPBLB register*/
05577           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U);
05578         }
05579
05580         /* Number of valid words (lastwordsize) in last block */
05581         if ((npblb % 4U) == 0U)
05582         {
05583           lastwordsize = (16U - npblb) / 4U;
05584         }
05585         else
05586         {
05587           lastwordsize = ((16U - npblb) / 4U) + 1U;
05588         }
05589
05590         /*  Last block optionally pad the data with zeros*/
05591         for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
05592         {
05593           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05594           hcryp->CrypInCount++;
05595         }
05596         while (loopcounter < 4U)
05597         {
05598           /* pad the data with zeros to have a complete block */
05599           hcryp->Instance->DINR = 0x0U;
05600           loopcounter++;
05601         }
05602       }
05603     }
05604   }
05605 }
05606 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
05607 /**
05608   * @}
05609   */
05610
05611
05612 #endif /* HAL_CRYP_MODULE_ENABLED */
05613
05614 #endif /* AES */
05615 /**
05616   * @}
05617   */
05618
05619 /**
05620   * @}
05621   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cryp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_CRYP_H
00021 #define STM32G4xx_HAL_CRYP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined(AES)
00035
00036 /** @defgroup CRYP CRYP
00037   * @brief CRYP HAL module driver.
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief CRYP Init Structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00054                                         This parameter can be a value of @ref CRYP_Data_Type */
00055   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
00056                                         128 or 256 bit key length in TinyAES
00057                                         This parameter can be a value of @ref CRYP_Key_Size */
00058   uint32_t *pKey;                      /*!< The key used for encryption/decryption */
00059   uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
00060                                          counter in CTR mode */
00061   uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
00062                                         AES Algorithm ECB/CBC/CTR/GCM or CCM
00063                                         This parameter can be a value of @ref CRYP_Algorithm_Mode */
00064   uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
00065                                         GCM : also known as Additional Authentication Data
00066                                         CCM : named B1 composed of the associated data length and Associated Data. */
00067   uint32_t HeaderSize;                 /*!< The size of header buffer */
00068   uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
00069   uint32_t DataWidthUnit;              /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
00070   uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
00071   uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
00072                                            Vector only once and to skip configuration for consecutive processings.
00073                                            This parameter can be a value of @ref CRYP_Configuration_Skip */
00074
00075 } CRYP_ConfigTypeDef;
00076
00077
00078 /**
00079   * @brief  CRYP State Structure definition
00080   */
00081
00082 typedef enum
00083 {
00084   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00085   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00086   HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
00087 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00088   HAL_CRYP_STATE_SUSPENDED         = 0x03U,   /*!< CRYP suspended                        */
00089 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00090 } HAL_CRYP_STATETypeDef;
00091
00092 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00093 /**
00094   * @brief HAL CRYP mode suspend definitions
00095   */
00096 typedef enum
00097 {
00098   HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
00099   HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
00100 } HAL_SuspendTypeDef;
00101 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00102
00103 /**
00104   * @brief  CRYP handle Structure definition
00105   */
00106 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00107 typedef struct __CRYP_HandleTypeDef
00108 #else
00109 typedef struct
00110 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00111 {
00112   AES_TypeDef                       *Instance;        /*!< AES Register base address */
00113
00114   CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
00115
00116   FunctionalState                   AutoKeyDerivation;   /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
00117                                                          This parameter can be a value of ENABLE/DISABLE */
00118
00119   uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00120
00121   uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00122
00123   __IO uint16_t                     CrypHeaderCount;  /*!< Counter of header data in words */
00124
00125   __IO uint16_t                     CrypInCount;      /*!< Counter of input data in words */
00126
00127   __IO uint16_t                     CrypOutCount;     /*!< Counter of output data in words */
00128
00129   uint16_t                          Size;             /*!< Length of input data */
00130
00131   uint32_t                          Phase;            /*!< CRYP peripheral phase */
00132
00133   DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
00134
00135   DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
00136
00137   HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
00138
00139   __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
00140
00141   __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
00142
00143   uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
00144                                                            configuration can be skipped */
00145
00146   uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
00147                                                            for a single signature computation after several
00148                                                            messages processing */
00149
00150 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00151   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
00152   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
00153   void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
00154
00155   void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
00156   void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
00157
00158 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00159
00160 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00161
00162   __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
00163
00164   CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing is suspended */
00165
00166   uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing is suspended */
00167
00168   uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing is suspended */
00169
00170   uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing is suspended */
00171
00172   uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing is suspended */
00173
00174   uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing is suspended */
00175
00176   __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing is suspended */
00177
00178   uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
00179
00180   uint32_t                    SUSPxR_saved[8];         /*!< copy of suspension registers */
00181
00182   uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing is suspended*/
00183
00184   uint32_t                    Key_saved[8];            /*!< copy of key registers */
00185
00186   uint16_t                    Size_saved;              /*!< copy of input buffer size */
00187
00188   uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing is suspended */
00189
00190   uint32_t                    SizesSum_saved;          /*!< copy of SizesSum when processing is suspended */
00191
00192   uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
00193
00194   FunctionalState             AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
00195
00196 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00197
00198 } CRYP_HandleTypeDef;
00199
00200 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00201 /** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
00202   * @brief  HAL CRYP Callback ID enumeration definition
00203   * @{
00204   */
00205 typedef enum
00206 {
00207   HAL_CRYP_MSPINIT_CB_ID           = 0x00U,    /*!< CRYP MspInit callback ID                        */
00208   HAL_CRYP_MSPDEINIT_CB_ID         = 0x01U,     /*!< CRYP MspDeInit callback ID                      */
00209   HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x02U,    /*!< CRYP Input FIFO transfer completed callback ID  */
00210   HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x03U,    /*!< CRYP Output FIFO transfer completed callback ID */
00211   HAL_CRYP_ERROR_CB_ID             = 0x04U,    /*!< CRYP Error callback ID                          */
00212 } HAL_CRYP_CallbackIDTypeDef;
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
00218   * @brief  HAL CRYP Callback pointer definition
00219   * @{
00220   */
00221
00222 typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
00223
00224 /**
00225   * @}
00226   */
00227
00228 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00229
00230 /**
00231   * @}
00232   */
00233
00234 /* Exported constants --------------------------------------------------------*/
00235 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00236   * @{
00237   */
00238
00239 /** @defgroup CRYP_Error_Definition   CRYP Error Definition
00240   * @{
00241   */
00242 #define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
00243 #define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
00244 #define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
00245 #define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
00246 #define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
00247 #define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
00248 #define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
00249 #define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
00250 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00251 #define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
00252 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
00259   * @{
00260   */
00261
00262 #define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
00263 #define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
00270   * @{
00271   */
00272
00273 #define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, header size unit is word */
00274 #define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, header size unit is byte */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
00281   * @{
00282   */
00283
00284 #define CRYP_AES_ECB            0x00000000U                       /*!< Electronic codebook chaining algorithm                   */
00285 #define CRYP_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
00286 #define CRYP_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
00287 #define CRYP_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
00288 #define CRYP_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup CRYP_Key_Size CRYP Key Size
00295   * @{
00296   */
00297
00298 #define CRYP_KEYSIZE_128B         0x00000000U          /*!< 128-bit long key */
00299 #define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE       /*!< 256-bit long key */
00300
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup CRYP_Data_Type CRYP Data Type
00306   * @{
00307   */
00308
00309 #define CRYP_DATATYPE_32B         0x00000000U  /*!< 32-bit data type (no swapping)        */
00310 #define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
00311 #define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
00312 #define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup CRYP_Interrupt  CRYP Interrupt
00319   * @{
00320   */
00321
00322 #define CRYP_IT_CCFIE     AES_CR_CCFIE /*!< Computation Complete interrupt enable */
00323 #define CRYP_IT_ERRIE     AES_CR_ERRIE /*!< Error interrupt enable                */
00324 #define CRYP_IT_WRERR     AES_SR_WRERR  /*!< Write Error           */
00325 #define CRYP_IT_RDERR     AES_SR_RDERR  /*!< Read Error            */
00326 #define CRYP_IT_CCF       AES_SR_CCF    /*!< Computation completed */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup CRYP_Flags CRYP Flags
00333   * @{
00334   */
00335
00336 /* status flags */
00337 #define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
00338 #define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
00339 #define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
00340 #define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
00341 /* clearing flags */
00342 #define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
00343 #define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear  */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
00350   * @{
00351   */
00352
00353 #define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
00354 #define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
00355
00356 /**
00357   * @}
00358   */
00359
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macros -----------------------------------------------------------*/
00366 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00367   * @{
00368   */
00369
00370 /** @brief Reset CRYP handle state
00371   * @param  __HANDLE__ specifies the CRYP handle.
00372   * @retval None
00373   */
00374 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00375 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
00376                                                       (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
00377                                                       (__HANDLE__)->MspInitCallback = NULL;\
00378                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00379                                                      }while(0U)
00380 #else
00381 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00382 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00383
00384 /**
00385   * @brief  Enable/Disable the CRYP peripheral.
00386   * @param  __HANDLE__ specifies the CRYP handle.
00387   * @retval None
00388   */
00389
00390 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
00391 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
00392
00393
00394 /** @brief  Check whether the specified CRYP status flag is set or not.
00395   * @param  __HANDLE__ specifies the CRYP handle.
00396   * @param  __FLAG__ specifies the flag to check.
00397   *         This parameter can be one of the following values for TinyAES:
00398   *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
00399   *            @arg @ref CRYP_IT_WRERR Write Error
00400   *            @arg @ref CRYP_IT_RDERR Read Error
00401   *            @arg @ref CRYP_IT_CCF Computation Complete
00402   *         This parameter can be one of the following values for CRYP:
00403   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00404   *                                 or a key preparation (for AES decryption).
00405   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00406   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00407   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00408   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00409   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00410   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00411   * @retval The state of __FLAG__ (TRUE or FALSE).
00412   */
00413
00414 #define CRYP_FLAG_MASK  0x0000001FU
00415 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00416
00417 /** @brief  Clear the CRYP pending status flag.
00418   * @param  __HANDLE__ specifies the CRYP handle.
00419   * @param  __FLAG__ specifies the flag to clear.
00420   *         This parameter can be one of the following values:
00421   *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
00422   *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
00423   * @retval None
00424   */
00425
00426 #define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
00427
00428
00429 /** @brief  Check whether the specified CRYP interrupt source is enabled or not.
00430   * @param  __HANDLE__ specifies the CRYP handle.
00431   * @param __INTERRUPT__ CRYP interrupt source to check
00432   *         This parameter can be one of the following values for TinyAES:
00433   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00434   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00435   * @retval State of interruption (TRUE or FALSE).
00436   */
00437
00438 #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\
00439                                                               (__INTERRUPT__)) == (__INTERRUPT__))
00440
00441 /** @brief  Check whether the specified CRYP interrupt is set or not.
00442   * @param  __HANDLE__ specifies the CRYP handle.
00443   * @param  __INTERRUPT__ specifies the interrupt to check.
00444   *         This parameter can be one of the following values for TinyAES:
00445   *            @arg @ref CRYP_IT_WRERR Write Error
00446   *            @arg @ref CRYP_IT_RDERR Read Error
00447   *            @arg @ref CRYP_IT_CCF  Computation Complete
00448   *         This parameter can be one of the following values for CRYP:
00449   *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
00450   *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
00451   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00452   */
00453
00454 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00455
00456 /**
00457   * @brief  Enable the CRYP interrupt.
00458   * @param  __HANDLE__ specifies the CRYP handle.
00459   * @param  __INTERRUPT__ CRYP Interrupt.
00460   *         This parameter can be one of the following values for TinyAES:
00461   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00462   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00463   *         This parameter can be one of the following values for CRYP:
00464   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00465   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00466   * @retval None
00467   */
00468
00469 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00470
00471 /**
00472   * @brief  Disable the CRYP interrupt.
00473   * @param  __HANDLE__ specifies the CRYP handle.
00474   * @param  __INTERRUPT__ CRYP Interrupt.
00475   *         This parameter can be one of the following values for TinyAES:
00476   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00477   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00478   *         This parameter can be one of the following values for CRYP:
00479   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00480   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00481   * @retval None
00482   */
00483
00484 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00485
00486 /**
00487   * @}
00488   */
00489
00490 /* Include CRYP HAL Extended module */
00491 #include "stm32g4xx_hal_cryp_ex.h"
00492
00493 /* Exported functions --------------------------------------------------------*/
00494 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00495   * @{
00496   */
00497
00498 /** @addtogroup CRYP_Exported_Functions_Group1
00499   * @{
00500   */
00501 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00502 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00503 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00504 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00505 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00506 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00507 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00508 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
00509                                             pCRYP_CallbackTypeDef pCallback);
00510 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
00511 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00512 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00513 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
00514 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
00515 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
00516 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
00517 /**
00518   * @}
00519   */
00520
00521 /** @addtogroup CRYP_Exported_Functions_Group2
00522   * @{
00523   */
00524
00525 /* encryption/decryption ***********************************/
00526 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
00527                                    uint32_t Timeout);
00528 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
00529                                    uint32_t Timeout);
00530 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00531 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00532 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00533 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00534
00535 /**
00536   * @}
00537   */
00538
00539
00540 /** @addtogroup CRYP_Exported_Functions_Group3
00541   * @{
00542   */
00543 /* Interrupt Handler functions  **********************************************/
00544 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00545 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00546 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00547 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00548 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00549 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00550
00551 /**
00552   * @}
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /* Private macros --------------------------------------------------------*/
00560 /** @defgroup CRYP_Private_Macros CRYP Private Macros
00561   * @{
00562   */
00563
00564 /** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
00565   * @{
00566   */
00567
00568 #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)      || \
00569                                       ((ALGORITHM)  == CRYP_AES_CBC)     || \
00570                                       ((ALGORITHM)  == CRYP_AES_CTR)     || \
00571                                       ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
00572                                       ((ALGORITHM)  == CRYP_AES_CCM))
00573
00574
00575 #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
00576                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
00577
00578 #define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
00579                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
00580                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
00581                                    ((DATATYPE) == CRYP_DATATYPE_1B))
00582
00583 #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
00584                              ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
00585
00586 #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)                                             \
00587   (((((ALGO) == CRYP_AES_CTR)) &&                                             \
00588     ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
00589      (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
00590    (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC)                  || \
00591     ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
00592
00593 /**
00594   * @}
00595   */
00596
00597 /**
00598   * @}
00599   */
00600
00601
00602 /* Private constants ---------------------------------------------------------*/
00603 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00604   * @{
00605   */
00606
00607 /**
00608   * @}
00609   */
00610 /* Private defines -----------------------------------------------------------*/
00611 /** @defgroup CRYP_Private_Defines CRYP Private Defines
00612   * @{
00613   */
00614
00615 /**
00616   * @}
00617   */
00618
00619 /* Private variables ---------------------------------------------------------*/
00620 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00621   * @{
00622   */
00623
00624 /**
00625   * @}
00626   */
00627
00628 /* Private functions ---------------------------------------------------------*/
00629 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00630   * @{
00631   */
00632
00633 /**
00634   * @}
00635   */
00636
00637 /**
00638   * @}
00639   */
00640
00641 #endif /* AES */
00642 /**
00643   * @}
00644   */
00645
00646 #ifdef __cplusplus
00647 }
00648 #endif
00649
00650 #endif /* STM32G4xx_HAL_CRYP_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_cryp_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   CRYPEx HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the Cryptography (CRYP) peripheral.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32g4xx_hal.h"
00024
00025 /** @addtogroup STM32G4xx_HAL_Driver
00026   * @{
00027   */
00028
00029 /** @addtogroup CRYPEx
00030   * @{
00031   */
00032
00033 #if defined(AES)
00034
00035 #ifdef HAL_CRYP_MODULE_ENABLED
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /** @addtogroup CRYPEx_Private_Defines
00040   * @{
00041   */
00042
00043 #define CRYP_PHASE_INIT                              0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
00044 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0          /*!< GCM/GMAC or CCM header phase */
00045 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase   */
00046 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH            /*!< GCM/GMAC or CCM  final phase  */
00047
00048 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U             /*!< Encryption mode   */
00049 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode  only used when performing ECB and CBC decryptions  */
00050 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption       */
00051 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption only used when performing ECB and CBC decryptions  */
00052
00053 #define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
00054 #define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
00055
00056 /*  CTR0 information to use in CCM algorithm */
00057 #define CRYP_CCM_CTR0_0            0x07FFFFFFU
00058 #define CRYP_CCM_CTR0_3            0xFFFFFF00U
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067
00068 /* Exported functions---------------------------------------------------------*/
00069 /** @addtogroup CRYPEx_Exported_Functions
00070   * @{
00071   */
00072
00073 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00074   *  @brief   Extended processing functions.
00075   *
00076 @verbatim
00077   ==============================================================================
00078               ##### Extended AES processing functions #####
00079   ==============================================================================
00080     [..]  This section provides functions allowing to generate the authentication
00081           TAG in Polling mode
00082       (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
00083       (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
00084          they should be used after Encrypt/Decrypt operation.
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  generate the GCM authentication TAG.
00092   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00093   *         the configuration information for CRYP module
00094   * @param  AuthTag Pointer to the authentication buffer
00095   * @param  Timeout Timeout duration
00096   * @retval HAL status
00097   */
00098 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00099 {
00100   uint32_t tickstart;
00101   /* Assume first Init.HeaderSize is in words */
00102   uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
00103   uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
00104   uint32_t tagaddr = (uint32_t)AuthTag;
00105
00106   /* Correct headerlength if Init.HeaderSize is actually in bytes */
00107   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
00108   {
00109     headerlength /= 4U;
00110   }
00111
00112   if (hcryp->State == HAL_CRYP_STATE_READY)
00113   {
00114     /* Process locked */
00115     __HAL_LOCK(hcryp);
00116
00117     /* Change the CRYP peripheral state */
00118     hcryp->State = HAL_CRYP_STATE_BUSY;
00119
00120     /* Check if initialization phase has already been performed */
00121     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00122     {
00123       /* Change the CRYP phase */
00124       hcryp->Phase = CRYPEx_PHASE_FINAL;
00125     }
00126     else /* Initialization phase has not been performed*/
00127     {
00128       /* Disable the Peripheral */
00129       __HAL_CRYP_DISABLE(hcryp);
00130
00131       /* Sequence error code field */
00132       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00133
00134       /* Change the CRYP peripheral state */
00135       hcryp->State = HAL_CRYP_STATE_READY;
00136
00137       /* Process unlocked */
00138       __HAL_UNLOCK(hcryp);
00139       return HAL_ERROR;
00140     }
00141
00142     /* Select final phase */
00143     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00144
00145     /* Set the encrypt operating mode*/
00146     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00147
00148     /*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
00149     /* Write into the AES_DINR register the number of bits in header (64 bits)
00150     followed by the number of bits in the payload */
00151
00152     hcryp->Instance->DINR = 0U;
00153     hcryp->Instance->DINR = (uint32_t)(headerlength);
00154     hcryp->Instance->DINR = 0U;
00155     hcryp->Instance->DINR = (uint32_t)(inputlength);
00156
00157     /* Wait for CCF flag to be raised */
00158     tickstart = HAL_GetTick();
00159     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00160     {
00161       /* Check for the Timeout */
00162       if (Timeout != HAL_MAX_DELAY)
00163       {
00164         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00165         {
00166           /* Disable the CRYP peripheral clock */
00167           __HAL_CRYP_DISABLE(hcryp);
00168
00169           /* Change state */
00170           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00171           hcryp->State = HAL_CRYP_STATE_READY;
00172
00173           /* Process unlocked */
00174           __HAL_UNLOCK(hcryp);
00175           return HAL_ERROR;
00176         }
00177       }
00178     }
00179
00180     /* Read the authentication TAG in the output FIFO */
00181     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00182     tagaddr += 4U;
00183     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00184     tagaddr += 4U;
00185     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00186     tagaddr += 4U;
00187     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00188
00189     /* Clear CCF flag */
00190     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00191
00192     /* Disable the peripheral */
00193     __HAL_CRYP_DISABLE(hcryp);
00194
00195     /* Change the CRYP peripheral state */
00196     hcryp->State = HAL_CRYP_STATE_READY;
00197
00198     /* Process unlocked */
00199     __HAL_UNLOCK(hcryp);
00200   }
00201   else
00202   {
00203     /* Busy error code field */
00204     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00205     return HAL_ERROR;
00206   }
00207   /* Return function status */
00208   return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief  AES CCM Authentication TAG generation.
00213   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00214   *         the configuration information for CRYP module
00215   * @param  AuthTag Pointer to the authentication buffer
00216   * @param  Timeout Timeout duration
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00220 {
00221   uint32_t tagaddr = (uint32_t)AuthTag;
00222   uint32_t tickstart;
00223
00224   if (hcryp->State == HAL_CRYP_STATE_READY)
00225   {
00226     /* Process locked */
00227     __HAL_LOCK(hcryp);
00228
00229     /* Disable interrupts in case they were kept enabled to proceed
00230        a single message in several iterations */
00231     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
00232
00233     /* Change the CRYP peripheral state */
00234     hcryp->State = HAL_CRYP_STATE_BUSY;
00235
00236     /* Check if initialization phase has already been performed */
00237     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00238     {
00239       /* Change the CRYP phase */
00240       hcryp->Phase = CRYPEx_PHASE_FINAL;
00241     }
00242     else /* Initialization phase has not been performed*/
00243     {
00244       /* Disable the peripheral */
00245       __HAL_CRYP_DISABLE(hcryp);
00246
00247       /* Sequence error code field */
00248       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00249
00250       /* Change the CRYP peripheral state */
00251       hcryp->State = HAL_CRYP_STATE_READY;
00252
00253       /* Process unlocked */
00254       __HAL_UNLOCK(hcryp);
00255       return HAL_ERROR;
00256     }
00257     /* Select final phase */
00258     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00259
00260     /* Set encrypt  operating mode*/
00261     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00262
00263     /* Wait for CCF flag to be raised */
00264     tickstart = HAL_GetTick();
00265     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00266     {
00267       /* Check for the Timeout */
00268       if (Timeout != HAL_MAX_DELAY)
00269       {
00270         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00271         {
00272           /* Disable the CRYP peripheral Clock */
00273           __HAL_CRYP_DISABLE(hcryp);
00274
00275           /* Change state */
00276           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00277           hcryp->State = HAL_CRYP_STATE_READY;
00278
00279           /* Process unlocked */
00280           __HAL_UNLOCK(hcryp);
00281           return HAL_ERROR;
00282         }
00283       }
00284     }
00285
00286     /* Read the authentication TAG in the output FIFO */
00287     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00288     tagaddr += 4U;
00289     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00290     tagaddr += 4U;
00291     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00292     tagaddr += 4U;
00293     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00294
00295     /* Clear CCF Flag */
00296     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00297
00298
00299     /* Change the CRYP peripheral state */
00300     hcryp->State = HAL_CRYP_STATE_READY;
00301
00302     /* Process unlocked */
00303     __HAL_UNLOCK(hcryp);
00304
00305     /* Disable CRYP  */
00306     __HAL_CRYP_DISABLE(hcryp);
00307   }
00308   else
00309   {
00310     /* Busy error code field */
00311     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00312     return HAL_ERROR;
00313   }
00314   /* Return function status */
00315   return HAL_OK;
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup CRYPEx_Exported_Functions_Group2 Extended AES Key Derivations functions
00323   * @brief   Extended Key Derivations functions.
00324   *
00325 @verbatim
00326   ==============================================================================
00327               ##### Key Derivation functions #####
00328   ==============================================================================
00329     [..]  This section provides functions allowing to Enable or Disable the
00330           the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
00331           These function are allowed only in TinyAES peripheral.
00332 @endverbatim
00333   * @{
00334   */
00335
00336 /**
00337   * @brief  AES enable key derivation functions
00338   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00339   */
00340 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00341 {
00342   if (hcryp->State == HAL_CRYP_STATE_READY)
00343   {
00344     hcryp->AutoKeyDerivation = ENABLE;
00345   }
00346   else
00347   {
00348     /* Busy error code field */
00349     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00350   }
00351 }
00352 /**
00353   * @brief  AES disable key derivation functions
00354   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00355   */
00356 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00357 {
00358   if (hcryp->State == HAL_CRYP_STATE_READY)
00359   {
00360     hcryp->AutoKeyDerivation = DISABLE;
00361   }
00362   else
00363   {
00364     /* Busy error code field */
00365     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00366   }
00367 }
00368
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376
00377 #endif /* HAL_CRYP_MODULE_ENABLED */
00378
00379 #endif /* AES */
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_cryp_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_cryp_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYPEx HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_CRYP_EX_H
00021 #define STM32G4xx_HAL_CRYP_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined(AES)
00035
00036 /** @defgroup CRYPEx CRYPEx
00037   * @brief CRYP Extension HAL module driver.
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /* Exported constants --------------------------------------------------------*/
00043 /* Private types -------------------------------------------------------------*/
00044 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052 /* Private variables ---------------------------------------------------------*/
00053 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00054   * @{
00055   */
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Private functions ---------------------------------------------------------*/
00080 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00081   * @{
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported functions --------------------------------------------------------*/
00089 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00090   * @{
00091   */
00092
00093 /** @addtogroup CRYPEx_Exported_Functions_Group1
00094   * @{
00095   */
00096 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00097 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @addtogroup CRYPEx_Exported_Functions_Group2
00104   * @{
00105   */
00106 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00107 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00108
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /**
00118   * @}
00119   */
00120 #endif /* AES */
00121
00122 /**
00123   * @}
00124   */
00125
00126 #ifdef __cplusplus
00127 }
00128 #endif
00129
00130 #endif /* STM32G4xx_HAL_CRYP_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_dac.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                       ##### DAC Peripheral features #####
00028   ==============================================================================
00029     [..]
00030       *** DAC Channels ***
00031       ====================
00032     [..]
00033     STM32G4 devices integrate up to seven 12-bit Digital Analog Converters,
00034     up to six of them grouped by pair forming a DAC instance.
00035
00036     The 2 converters of an single instance (i.e. channel1 & channel2)
00037     can be used independently or simultaneously (dual mode):
00038       (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip
00039           peripherals (ex. comparators, operational amplifier).
00040       (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip
00041           peripherals (ex. comparators, operational amplifier).
00042     Note: when an instance only includes one converter, only independent mode is
00043         supported by this converter.
00044
00045     STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx):
00046     ----------------------------------------------------------------------------
00047                            |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
00048     ----------------------------------------------------------------------------
00049     Channel 1  |           |    YES     |    YES     |    YES     |    YES
00050                | DAC_OUT1  |    PA4     |    PA6     |     -      |     -
00051     ----------------------------------------------------------------------------
00052     Channel 2  |           |    YES     |    NO      |    YES     |    YES
00053                | DAC_OUT2  |    PA5     |     -      |     -      |     -
00054     ----------------------------------------------------------------------------
00055     Note: On this STM32 series, all devices do not include each DAC instances listed
00056           above. Refer to device datasheet for DACx instance availability.
00057
00058       *** DAC Triggers ***
00059       ====================
00060     [..]
00061     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00062     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00063     [..]
00064     Digital to Analog conversion can be triggered by:
00065       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00066           The used pin (GPIOx_PIN_9) must be configured in input mode.
00067
00068       (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15
00069           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
00070
00071       (#) Software using DAC_TRIGGER_SOFTWARE
00072
00073       (#) HRTimer TRGO: HRTIM1 (1)
00074           (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...)
00075
00076     [..]
00077     Specific triggers for sawtooth generation:
00078       (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10.
00079           The used pin (GPIOx_PIN_10) must be configured in input mode.
00080
00081       (#) HRTimer Step & Reset: HRTIM1 (1)
00082           (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...)
00083
00084       Note: On this STM32 series, parameter only available if HRTIM feature is
00085             supported (refer to device datasheet for supported features list)
00086
00087       *** DAC Buffer mode feature ***
00088       ===============================
00089       [..]
00090       Each DAC channel integrates an output buffer that can be used to
00091       reduce the output impedance, and to drive external loads directly
00092       without having to add an external operational amplifier.
00093       To enable, the output buffer use
00094       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00095       [..]
00096       (@) Refer to the device datasheet for more details about output
00097           impedance value with and without output buffer.
00098
00099       *** DAC connect feature ***
00100       ===============================
00101       [..]
00102       Each DAC channel can be connected internally.
00103       To connect, use
00104       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
00105       or
00106       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
00107
00108       *** GPIO configurations guidelines ***
00109       =====================
00110       [..]
00111       When a DAC channel is used (ex channel1 on PA4) and the other is not
00112       (ex channel2 on PA5 is configured in Analog and disabled).
00113       Channel1 may disturb channel2 as coupling effect.
00114       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00115       Coupling on adjacent channel could be avoided as follows:
00116       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00117       PA5 is configured in ANALOG just before it is turned on.
00118
00119       *** DAC Sample and Hold feature ***
00120       ========================
00121       [..]
00122       For each converter, 2 modes are supported: normal mode and
00123       "sample and hold" mode (i.e. low power mode).
00124       In the sample and hold mode, the DAC core converts data, then holds the
00125       converted voltage on a capacitor. When not converting, the DAC cores and
00126       buffer are completely turned off between samples and the DAC output is
00127       tri-stated, therefore  reducing the overall power consumption. A new
00128       stabilization period is needed before each new conversion.
00129
00130       The sample and hold allow setting internal or external voltage @
00131       low power consumption cost (output value can be at any given rate either
00132       by CPU or DMA).
00133
00134       The Sample and hold block and registers uses either LSI & run in
00135       several power modes: run mode, sleep mode, low power run, low power sleep
00136       mode & stop1 mode.
00137
00138       Low power stop1 mode allows only static conversion.
00139
00140       To enable Sample and Hold mode
00141       Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
00142       RCC_LSI_ON parameters.
00143
00144       Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
00145          & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
00146            DAC_HoldTime & DAC_RefreshTime;
00147
00148        *** DAC calibration feature ***
00149        ===================================
00150       [..]
00151        (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
00152        (++) Calibration aims at correcting some offset of output buffer.
00153        (++) The DAC uses either factory calibration settings OR user defined
00154            calibration (trimming) settings (i.e. trimming mode).
00155        (++) The user defined settings can be figured out using self calibration
00156            handled by HAL_DACEx_SelfCalibrate.
00157        (++) HAL_DACEx_SelfCalibrate:
00158        (+++) Runs automatically the calibration.
00159        (+++) Enables the user trimming mode
00160        (+++) Updates a structure with trimming values with fresh calibration
00161             results.
00162             The user may store the calibration results for larger
00163             (ex monitoring the trimming as a function of temperature
00164             for instance)
00165
00166        *** DAC wave generation feature ***
00167        ===================================
00168        [..]
00169        Both DAC channels can be used to generate
00170          (#) Noise wave
00171          (#) Triangle wave
00172          (#) Sawtooth wave
00173
00174        *** DAC data format ***
00175        =======================
00176        [..]
00177        The DAC data format can be:
00178          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00179          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00180          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00181
00182        *** DAC data value to voltage correspondence ***
00183        ================================================
00184        [..]
00185        The analog output voltage on each DAC channel pin is determined
00186        by the following equation:
00187        [..]
00188        DAC_OUTx = VREF+ * DOR / 4095
00189        (+) with  DOR is the Data Output Register
00190        [..]
00191           VREF+ is the input voltage reference (refer to the device datasheet)
00192        [..]
00193         e.g. To set DAC_OUT1 to 0.7V, use
00194        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00195
00196        *** DMA requests ***
00197        =====================
00198        [..]
00199        A DMAMUX request can be generated when an external trigger (but not a software trigger)
00200        occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA().
00201        DMAMUX requests are mapped as following:
00202         ----------------------------------------------------------------------------
00203                                |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
00204         ----------------------------------------------------------------------------
00205         Channel 1  |           |     6      |     41     |    102     |    104
00206         ----------------------------------------------------------------------------
00207         Channel 2  |           |     7      |     -      |    103     |    105
00208         ----------------------------------------------------------------------------
00209         Note: On this STM32 series, all devices do not include each DAC instances listed
00210               above. Refer to device datasheet for DACx instance availability.
00211
00212        *** High frequency interface mode ***
00213        =====================================
00214        [..]
00215        The high frequency interface informs DAC instance about the bus frequency in use.
00216        It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
00217        provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
00218        Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
00219        function figured out the correct setting.
00220        The high frequency mode is same for all converters of a same DAC instance. Either same
00221        parameter DAC_HighFrequency is used for all DAC converters or again self
00222        DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
00223
00224      [..]
00225     (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation
00226         please refer to Extended Features Driver description
00227
00228                       ##### How to use this driver #####
00229   ==============================================================================
00230     [..]
00231       (+) DAC APB clock must be enabled to get write access to DAC
00232           registers using HAL_DAC_Init()
00233       (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode.
00234       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00235       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
00236
00237      *** Calibration mode IO operation ***
00238      ======================================
00239      [..]
00240        (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
00241        (+) Run the calibration using HAL_DACEx_SelfCalibrate()
00242        (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
00243
00244      *** Polling mode IO operation ***
00245      =================================
00246      [..]
00247        (+) Start the DAC peripheral using HAL_DAC_Start()
00248        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00249        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00250
00251      *** DMA mode IO operation ***
00252      ==============================
00253      [..]
00254        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00255            of data to be transferred at each end of conversion
00256            First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
00257        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00258            function is executed and user can add his own code by customization of function pointer
00259            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00260        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00261            function is executed and user can add his own code by customization of function pointer
00262            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00263        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00264             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00265        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00266            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
00267            function is executed and user can add his own code by customization of function pointer
00268            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
00269            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
00270        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00271
00272     *** Callback registration ***
00273     =============================================
00274     [..]
00275       The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
00276       allows the user to configure dynamically the driver callbacks.
00277
00278     Use Functions HAL_DAC_RegisterCallback() to register a user callback,
00279       it allows to register following callbacks:
00280       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00281       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00282       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00283       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00284       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00285       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00286       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00287       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00288       (+) MspInitCallback         : DAC MspInit.
00289       (+) MspDeInitCallback       : DAC MspdeInit.
00290       This function takes as parameters the HAL peripheral handle, the Callback ID
00291       and a pointer to the user callback function.
00292
00293     Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
00294       weak (overridden) function. It allows to reset following callbacks:
00295       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00296       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00297       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00298       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00299       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00300       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00301       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00302       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00303       (+) MspInitCallback         : DAC MspInit.
00304       (+) MspDeInitCallback       : DAC MspdeInit.
00305       (+) All Callbacks
00306       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00307
00308       By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
00309       all callbacks are reset to the corresponding legacy weak (overridden) functions.
00310       Exception done for MspInit and MspDeInit callbacks that are respectively
00311       reset to the legacy weak (overridden) functions in the HAL_DAC_Init
00312       and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
00313       If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
00314       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00315
00316       Callbacks can be registered/unregistered in READY state only.
00317       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00318       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00319       during the Init/DeInit.
00320       In that case first register the MspInit/MspDeInit user callbacks
00321       using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
00322       or HAL_DAC_Init function.
00323
00324       When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
00325       not defined, the callback registering feature is not available
00326       and weak (overridden) callbacks are used.
00327
00328      *** DAC HAL driver macros list ***
00329      =============================================
00330      [..]
00331        Below the list of most used macros in DAC HAL driver.
00332
00333       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00334       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00335       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00336       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00337
00338      [..]
00339       (@) You can refer to the DAC HAL driver header file for more useful macros
00340
00341 @endverbatim
00342   ******************************************************************************
00343   */
00344
00345 /* Includes ------------------------------------------------------------------*/
00346 #include "stm32g4xx_hal.h"
00347
00348 /** @addtogroup STM32G4xx_HAL_Driver
00349   * @{
00350   */
00351
00352 #ifdef HAL_DAC_MODULE_ENABLED
00353 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00354
00355 /** @defgroup DAC DAC
00356   * @brief DAC driver modules
00357   * @{
00358   */
00359
00360 /* Private typedef -----------------------------------------------------------*/
00361 /* Private define ------------------------------------------------------------*/
00362 /* Private constants ---------------------------------------------------------*/
00363 /** @addtogroup DAC_Private_Constants DAC Private Constants
00364   * @{
00365   */
00366 #define TIMEOUT_DAC_CALIBCONFIG        1U         /* 1   ms        */
00367 #define HFSEL_ENABLE_THRESHOLD_80MHZ   80000000U  /* 80 MHz        */
00368 #define HFSEL_ENABLE_THRESHOLD_160MHZ  160000000U /* 160 MHz       */
00369
00370 /**
00371   * @}
00372   */
00373
00374 /* Private macro -------------------------------------------------------------*/
00375 /* Private variables ---------------------------------------------------------*/
00376 /* Private function prototypes -----------------------------------------------*/
00377 /* Exported functions -------------------------------------------------------*/
00378
00379 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00380   * @{
00381   */
00382
00383 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00384   *  @brief    Initialization and Configuration functions
00385   *
00386 @verbatim
00387   ==============================================================================
00388               ##### Initialization and de-initialization functions #####
00389   ==============================================================================
00390     [..]  This section provides functions allowing to:
00391       (+) Initialize and configure the DAC.
00392       (+) De-initialize the DAC.
00393
00394 @endverbatim
00395   * @{
00396   */
00397
00398 /**
00399   * @brief  Initialize the DAC peripheral according to the specified parameters
00400   *         in the DAC_InitStruct and initialize the associated handle.
00401   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00402   *         the configuration information for the specified DAC.
00403   * @retval HAL status
00404   */
00405 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
00406 {
00407   /* Check the DAC peripheral handle */
00408   if (hdac == NULL)
00409   {
00410     return HAL_ERROR;
00411   }
00412   /* Check the parameters */
00413   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00414
00415   if (hdac->State == HAL_DAC_STATE_RESET)
00416   {
00417 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00418     /* Init the DAC Callback settings */
00419     hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
00420     hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
00421     hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
00422     hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
00423
00424     hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
00425     hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
00426     hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
00427     hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
00428
00429     if (hdac->MspInitCallback == NULL)
00430     {
00431       hdac->MspInitCallback             = HAL_DAC_MspInit;
00432     }
00433 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00434
00435     /* Allocate lock resource and initialize it */
00436     hdac->Lock = HAL_UNLOCKED;
00437
00438 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00439     /* Init the low level hardware */
00440     hdac->MspInitCallback(hdac);
00441 #else
00442     /* Init the low level hardware */
00443     HAL_DAC_MspInit(hdac);
00444 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00445   }
00446
00447   /* Initialize the DAC state*/
00448   hdac->State = HAL_DAC_STATE_BUSY;
00449
00450   /* Set DAC error code to none */
00451   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00452
00453   /* Initialize the DAC state*/
00454   hdac->State = HAL_DAC_STATE_READY;
00455
00456   /* Return function status */
00457   return HAL_OK;
00458 }
00459
00460 /**
00461   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00462   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00463   *         the configuration information for the specified DAC.
00464   * @retval HAL status
00465   */
00466 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
00467 {
00468   /* Check the DAC peripheral handle */
00469   if (hdac == NULL)
00470   {
00471     return HAL_ERROR;
00472   }
00473
00474   /* Check the parameters */
00475   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00476
00477   /* Change DAC state */
00478   hdac->State = HAL_DAC_STATE_BUSY;
00479
00480 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00481   if (hdac->MspDeInitCallback == NULL)
00482   {
00483     hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
00484   }
00485   /* DeInit the low level hardware */
00486   hdac->MspDeInitCallback(hdac);
00487 #else
00488   /* DeInit the low level hardware */
00489   HAL_DAC_MspDeInit(hdac);
00490 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00491
00492   /* Set DAC error code to none */
00493   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00494
00495   /* Change DAC state */
00496   hdac->State = HAL_DAC_STATE_RESET;
00497
00498   /* Release Lock */
00499   __HAL_UNLOCK(hdac);
00500
00501   /* Return function status */
00502   return HAL_OK;
00503 }
00504
00505 /**
00506   * @brief  Initialize the DAC MSP.
00507   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00508   *         the configuration information for the specified DAC.
00509   * @retval None
00510   */
00511 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
00512 {
00513   /* Prevent unused argument(s) compilation warning */
00514   UNUSED(hdac);
00515
00516   /* NOTE : This function should not be modified, when the callback is needed,
00517             the HAL_DAC_MspInit could be implemented in the user file
00518    */
00519 }
00520
00521 /**
00522   * @brief  DeInitialize the DAC MSP.
00523   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00524   *         the configuration information for the specified DAC.
00525   * @retval None
00526   */
00527 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
00528 {
00529   /* Prevent unused argument(s) compilation warning */
00530   UNUSED(hdac);
00531
00532   /* NOTE : This function should not be modified, when the callback is needed,
00533             the HAL_DAC_MspDeInit could be implemented in the user file
00534    */
00535 }
00536
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00542   *  @brief    IO operation functions
00543   *
00544 @verbatim
00545   ==============================================================================
00546              ##### IO operation functions #####
00547   ==============================================================================
00548     [..]  This section provides functions allowing to:
00549       (+) Start conversion.
00550       (+) Stop conversion.
00551       (+) Start conversion and enable DMA transfer.
00552       (+) Stop conversion and disable DMA transfer.
00553       (+) Get result of conversion.
00554
00555 @endverbatim
00556   * @{
00557   */
00558
00559 /**
00560   * @brief  Enables DAC and starts conversion of channel.
00561   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00562   *         the configuration information for the specified DAC.
00563   * @param  Channel The selected DAC channel.
00564   *          This parameter can be one of the following values:
00565   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00566   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00567   *
00568   *         (1) On this STM32 series, parameter not available on all instances.
00569   *             Refer to device datasheet for channels availability.
00570   * @retval HAL status
00571   */
00572 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
00573 {
00574   __IO uint32_t wait_loop_index;
00575
00576   /* Check the DAC peripheral handle */
00577   if (hdac == NULL)
00578   {
00579     return HAL_ERROR;
00580   }
00581
00582   /* Check the parameters */
00583   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00584
00585   /* Process locked */
00586   __HAL_LOCK(hdac);
00587
00588   /* Change DAC state */
00589   hdac->State = HAL_DAC_STATE_BUSY;
00590
00591   /* Enable the Peripheral */
00592   __HAL_DAC_ENABLE(hdac, Channel);
00593   /* Ensure minimum wait before using peripheral after enabling it */
00594   /* Wait loop initialization and execution */
00595   /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
00596   /*       bits register capacity and handle low frequency. */
00597   wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00598   while (wait_loop_index != 0UL)
00599   {
00600     wait_loop_index--;
00601   }
00602
00603   if (Channel == DAC_CHANNEL_1)
00604   {
00605     /* Check if software trigger enabled */
00606     if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
00607     {
00608       /* Enable the selected DAC software conversion */
00609       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00610     }
00611   }
00612
00613   else
00614   {
00615     /* Check if software trigger enabled */
00616     if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
00617     {
00618       /* Enable the selected DAC software conversion*/
00619       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00620     }
00621   }
00622
00623
00624   /* Change DAC state */
00625   hdac->State = HAL_DAC_STATE_READY;
00626
00627   /* Process unlocked */
00628   __HAL_UNLOCK(hdac);
00629
00630   /* Return function status */
00631   return HAL_OK;
00632 }
00633
00634 /**
00635   * @brief  Disables DAC and stop conversion of channel.
00636   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00637   *         the configuration information for the specified DAC.
00638   * @param  Channel The selected DAC channel.
00639   *          This parameter can be one of the following values:
00640   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00641   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00642   *
00643   *         (1) On this STM32 series, parameter not available on all instances.
00644   *             Refer to device datasheet for channels availability.
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
00648 {
00649   /* Check the DAC peripheral handle */
00650   if (hdac == NULL)
00651   {
00652     return HAL_ERROR;
00653   }
00654
00655   /* Check the parameters */
00656   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00657
00658   /* Disable the Peripheral */
00659   __HAL_DAC_DISABLE(hdac, Channel);
00660
00661   /* Change DAC state */
00662   hdac->State = HAL_DAC_STATE_READY;
00663
00664   /* Return function status */
00665   return HAL_OK;
00666 }
00667
00668 /**
00669   * @brief  Enables DAC and starts conversion of channel.
00670   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00671   *         the configuration information for the specified DAC.
00672   * @param  Channel The selected DAC channel.
00673   *          This parameter can be one of the following values:
00674   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00675   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00676   *
00677   *         (1) On this STM32 series, parameter not available on all instances.
00678   *             Refer to device datasheet for channels availability.
00679   * @param  pData The source Buffer address.
00680   * @param  Length The length of data to be transferred from memory to DAC peripheral
00681   * @param  Alignment Specifies the data alignment for DAC channel.
00682   *          This parameter can be one of the following values:
00683   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00684   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00685   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00686   * @retval HAL status
00687   */
00688 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
00689                                     uint32_t Alignment)
00690 {
00691   HAL_StatusTypeDef status;
00692   uint32_t tmpreg;
00693   __IO uint32_t wait_loop_index;
00694
00695   /* Check the DAC peripheral handle */
00696   if (hdac == NULL)
00697   {
00698     return HAL_ERROR;
00699   }
00700
00701   /* Check the parameters */
00702   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00703   assert_param(IS_DAC_ALIGN(Alignment));
00704
00705   /* Process locked */
00706   __HAL_LOCK(hdac);
00707
00708   /* Change DAC state */
00709   hdac->State = HAL_DAC_STATE_BUSY;
00710
00711   if (Channel == DAC_CHANNEL_1)
00712   {
00713     /* Set the DMA transfer complete callback for channel1 */
00714     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00715
00716     /* Set the DMA half transfer complete callback for channel1 */
00717     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00718
00719     /* Set the DMA error callback for channel1 */
00720     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00721
00722     /* Enable the selected DAC channel1 DMA request */
00723     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00724
00725     /* Case of use of channel 1 */
00726     switch (Alignment)
00727     {
00728       case DAC_ALIGN_12B_R:
00729         /* Get DHR12R1 address */
00730         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00731         break;
00732       case DAC_ALIGN_12B_L:
00733         /* Get DHR12L1 address */
00734         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00735         break;
00736       default: /* case DAC_ALIGN_8B_R */
00737         /* Get DHR8R1 address */
00738         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00739         break;
00740     }
00741   }
00742
00743   else
00744   {
00745     /* Set the DMA transfer complete callback for channel2 */
00746     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00747
00748     /* Set the DMA half transfer complete callback for channel2 */
00749     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00750
00751     /* Set the DMA error callback for channel2 */
00752     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00753
00754     /* Enable the selected DAC channel2 DMA request */
00755     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00756
00757     /* Case of use of channel 2 */
00758     switch (Alignment)
00759     {
00760       case DAC_ALIGN_12B_R:
00761         /* Get DHR12R2 address */
00762         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00763         break;
00764       case DAC_ALIGN_12B_L:
00765         /* Get DHR12L2 address */
00766         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00767         break;
00768       default: /* case DAC_ALIGN_8B_R */
00769         /* Get DHR8R2 address */
00770         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00771         break;
00772     }
00773   }
00774
00775   if (Channel == DAC_CHANNEL_1)
00776   {
00777     /* Enable the DAC DMA underrun interrupt */
00778     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00779
00780     /* Enable the DMA channel */
00781     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00782   }
00783
00784   else
00785   {
00786     /* Enable the DAC DMA underrun interrupt */
00787     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00788
00789     /* Enable the DMA channel */
00790     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00791   }
00792
00793
00794   /* Process Unlocked */
00795   __HAL_UNLOCK(hdac);
00796
00797   if (status == HAL_OK)
00798   {
00799     /* Enable the Peripheral */
00800     __HAL_DAC_ENABLE(hdac, Channel);
00801     /* Ensure minimum wait before using peripheral after enabling it */
00802     /* Wait loop initialization and execution */
00803     /* Note: Variable divided by 2 to compensate partially              */
00804     /*       CPU processing cycles, scaling in us split to not          */
00805     /*       exceed 32 bits register capacity and handle low frequency. */
00806     wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00807     while (wait_loop_index != 0UL)
00808     {
00809       wait_loop_index--;
00810     }
00811   }
00812   else
00813   {
00814     hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00815   }
00816
00817   /* Return function status */
00818   return status;
00819 }
00820
00821 /**
00822   * @brief  Disables DAC and stop conversion of channel.
00823   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00824   *         the configuration information for the specified DAC.
00825   * @param  Channel The selected DAC channel.
00826   *          This parameter can be one of the following values:
00827   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00828   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00829   *
00830   *         (1) On this STM32 series, parameter not available on all instances.
00831   *             Refer to device datasheet for channels availability.
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
00835 {
00836   /* Check the DAC peripheral handle */
00837   if (hdac == NULL)
00838   {
00839     return HAL_ERROR;
00840   }
00841
00842   /* Check the parameters */
00843   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00844
00845   /* Disable the selected DAC channel DMA request */
00846   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
00847
00848   /* Disable the Peripheral */
00849   __HAL_DAC_DISABLE(hdac, Channel);
00850
00851   /* Disable the DMA channel */
00852
00853   /* Channel1 is used */
00854   if (Channel == DAC_CHANNEL_1)
00855   {
00856     /* Disable the DMA channel */
00857     (void)HAL_DMA_Abort(hdac->DMA_Handle1);
00858
00859     /* Disable the DAC DMA underrun interrupt */
00860     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00861   }
00862
00863   else /* Channel2 is used for */
00864   {
00865     /* Disable the DMA channel */
00866     (void)HAL_DMA_Abort(hdac->DMA_Handle2);
00867
00868     /* Disable the DAC DMA underrun interrupt */
00869     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00870   }
00871
00872
00873   /* Change DAC state */
00874   hdac->State = HAL_DAC_STATE_READY;
00875
00876   /* Return function status */
00877   return HAL_OK;
00878 }
00879
00880 /**
00881   * @brief  Handles DAC interrupt request
00882   *         This function uses the interruption of DMA
00883   *         underrun.
00884   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00885   *         the configuration information for the specified DAC.
00886   * @retval None
00887   */
00888 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
00889 {
00890   uint32_t itsource = hdac->Instance->CR;
00891   uint32_t itflag   = hdac->Instance->SR;
00892
00893   if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
00894   {
00895     /* Check underrun flag of DAC channel 1 */
00896     if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
00897     {
00898       /* Change DAC state to error state */
00899       hdac->State = HAL_DAC_STATE_ERROR;
00900
00901       /* Set DAC error code to channel1 DMA underrun error */
00902       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00903
00904       /* Clear the underrun flag */
00905       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
00906
00907       /* Disable the selected DAC channel1 DMA request */
00908       __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
00909
00910       /* Error callback */
00911 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00912       hdac->DMAUnderrunCallbackCh1(hdac);
00913 #else
00914       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00915 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00916     }
00917   }
00918
00919
00920   if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
00921   {
00922     /* Check underrun flag of DAC channel 2 */
00923     if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
00924     {
00925       /* Change DAC state to error state */
00926       hdac->State = HAL_DAC_STATE_ERROR;
00927
00928       /* Set DAC error code to channel2 DMA underrun error */
00929       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00930
00931       /* Clear the underrun flag */
00932       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
00933
00934       /* Disable the selected DAC channel2 DMA request */
00935       __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
00936
00937       /* Error callback */
00938 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00939       hdac->DMAUnderrunCallbackCh2(hdac);
00940 #else
00941       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00942 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00943     }
00944   }
00945
00946 }
00947
00948 /**
00949   * @brief  Set the specified data holding register value for DAC channel.
00950   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00951   *         the configuration information for the specified DAC.
00952   * @param  Channel The selected DAC channel.
00953   *          This parameter can be one of the following values:
00954   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00955   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00956   *
00957   *         (1) On this STM32 series, parameter not available on all instances.
00958   *             Refer to device datasheet for channels availability.
00959   * @param  Alignment Specifies the data alignment.
00960   *          This parameter can be one of the following values:
00961   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00962   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00963   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00964   * @param  Data Data to be loaded in the selected data holding register.
00965   * @retval HAL status
00966   */
00967 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00968 {
00969   __IO uint32_t tmp = 0UL;
00970
00971   /* Check the DAC peripheral handle */
00972   if (hdac == NULL)
00973   {
00974     return HAL_ERROR;
00975   }
00976
00977   /* Check the parameters */
00978   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00979   assert_param(IS_DAC_ALIGN(Alignment));
00980   /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
00981   if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
00982   {
00983     assert_param(IS_DAC_DATA(Data));
00984   }
00985
00986   tmp = (uint32_t)hdac->Instance;
00987   if (Channel == DAC_CHANNEL_1)
00988   {
00989     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00990   }
00991
00992   else
00993   {
00994     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00995   }
00996
00997
00998   /* Set the DAC channel selected data holding register */
00999   *(__IO uint32_t *) tmp = Data;
01000
01001   /* Return function status */
01002   return HAL_OK;
01003 }
01004
01005 /**
01006   * @brief  Conversion complete callback in non-blocking mode for Channel1
01007   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01008   *         the configuration information for the specified DAC.
01009   * @retval None
01010   */
01011 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
01012 {
01013   /* Prevent unused argument(s) compilation warning */
01014   UNUSED(hdac);
01015
01016   /* NOTE : This function should not be modified, when the callback is needed,
01017             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
01018    */
01019 }
01020
01021 /**
01022   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
01023   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01024   *         the configuration information for the specified DAC.
01025   * @retval None
01026   */
01027 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
01028 {
01029   /* Prevent unused argument(s) compilation warning */
01030   UNUSED(hdac);
01031
01032   /* NOTE : This function should not be modified, when the callback is needed,
01033             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
01034    */
01035 }
01036
01037 /**
01038   * @brief  Error DAC callback for Channel1.
01039   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01040   *         the configuration information for the specified DAC.
01041   * @retval None
01042   */
01043 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
01044 {
01045   /* Prevent unused argument(s) compilation warning */
01046   UNUSED(hdac);
01047
01048   /* NOTE : This function should not be modified, when the callback is needed,
01049             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
01050    */
01051 }
01052
01053 /**
01054   * @brief  DMA underrun DAC callback for channel1.
01055   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01056   *         the configuration information for the specified DAC.
01057   * @retval None
01058   */
01059 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
01060 {
01061   /* Prevent unused argument(s) compilation warning */
01062   UNUSED(hdac);
01063
01064   /* NOTE : This function should not be modified, when the callback is needed,
01065             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
01066    */
01067 }
01068
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
01074   *  @brief    Peripheral Control functions
01075   *
01076 @verbatim
01077   ==============================================================================
01078              ##### Peripheral Control functions #####
01079   ==============================================================================
01080     [..]  This section provides functions allowing to:
01081       (+) Configure channels.
01082       (+) Set the specified data holding register value for DAC channel.
01083
01084 @endverbatim
01085   * @{
01086   */
01087
01088 /**
01089   * @brief  Returns the last data output value of the selected DAC channel.
01090   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01091   *         the configuration information for the specified DAC.
01092   * @param  Channel The selected DAC channel.
01093   *          This parameter can be one of the following values:
01094   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
01095   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
01096   *
01097   *         (1) On this STM32 series, parameter not available on all instances.
01098   *             Refer to device datasheet for channels availability.
01099   * @retval The selected DAC channel data output value.
01100   */
01101 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
01102 {
01103   uint32_t result;
01104
01105   /* Check the DAC peripheral handle */
01106   assert_param(hdac != NULL);
01107
01108   /* Check the parameters */
01109   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
01110
01111   if (Channel == DAC_CHANNEL_1)
01112   {
01113     result = hdac->Instance->DOR1;
01114   }
01115
01116   else
01117   {
01118     result = hdac->Instance->DOR2;
01119   }
01120
01121   /* Returns the DAC channel data output register value */
01122   return result;
01123 }
01124
01125 /**
01126   * @brief  Configures the selected DAC channel.
01127   * @note   By calling this function, the high frequency interface mode (HFSEL bits)
01128   *         will be set. This parameter scope is the DAC instance. As the function
01129   *         is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
01130   *         must be the same at each call.
01131   *         (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
01132   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01133   *         the configuration information for the specified DAC.
01134   * @param  sConfig DAC configuration structure.
01135   * @param  Channel The selected DAC channel.
01136   *          This parameter can be one of the following values:
01137   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
01138   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
01139   *
01140   *         (1) On this STM32 series, parameter not available on all instances.
01141   *             Refer to device datasheet for channels availability.
01142   * @retval HAL status
01143   */
01144 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
01145                                         const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
01146 {
01147   HAL_StatusTypeDef status = HAL_OK;
01148   uint32_t tmpreg1;
01149   uint32_t tmpreg2;
01150   uint32_t tickstart;
01151   uint32_t hclkfreq;
01152   uint32_t connectOnChip;
01153
01154   /* Check the DAC peripheral handle and channel configuration struct */
01155   if ((hdac == NULL) || (sConfig == NULL))
01156   {
01157     return HAL_ERROR;
01158   }
01159
01160   /* Check the DAC parameters */
01161   assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
01162   assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger));
01163   assert_param(IS_DAC_TRIGGER2(hdac->Instance, sConfig->DAC_Trigger2));
01164   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
01165   assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
01166   assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
01167   if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
01168   {
01169     assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
01170   }
01171   assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
01172   if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
01173   {
01174     assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
01175     assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
01176     assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
01177   }
01178   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
01179   assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
01180   assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
01181
01182   /* Process locked */
01183   __HAL_LOCK(hdac);
01184
01185   /* Change DAC state */
01186   hdac->State = HAL_DAC_STATE_BUSY;
01187
01188   /* Sample and hold configuration */
01189   if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
01190   {
01191     /* Get timeout */
01192     tickstart = HAL_GetTick();
01193
01194     if (Channel == DAC_CHANNEL_1)
01195     {
01196       /* SHSR1 can be written when BWST1 is cleared */
01197       while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
01198       {
01199         /* Check for the Timeout */
01200         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01201         {
01202           /* New check to avoid false timeout detection in case of preemption */
01203           if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
01204           {
01205             /* Update error code */
01206             SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01207
01208             /* Change the DMA state */
01209             hdac->State = HAL_DAC_STATE_TIMEOUT;
01210
01211             return HAL_TIMEOUT;
01212           }
01213         }
01214       }
01215       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01216     }
01217
01218     else /* Channel 2 */
01219     {
01220       /* SHSR2 can be written when BWST2 is cleared */
01221       while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
01222       {
01223         /* Check for the Timeout */
01224         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01225         {
01226           /* New check to avoid false timeout detection in case of preemption */
01227           if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
01228           {
01229             /* Update error code */
01230             SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01231
01232             /* Change the DMA state */
01233             hdac->State = HAL_DAC_STATE_TIMEOUT;
01234
01235             return HAL_TIMEOUT;
01236           }
01237         }
01238       }
01239       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01240     }
01241
01242
01243     /* HoldTime */
01244     MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
01245                (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
01246     /* RefreshTime */
01247     MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
01248                (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
01249   }
01250
01251   if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
01252     /* USER TRIMMING */
01253   {
01254     /* Get the DAC CCR value */
01255     tmpreg1 = hdac->Instance->CCR;
01256     /* Clear trimming value */
01257     tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
01258     /* Configure for the selected trimming offset */
01259     tmpreg2 = sConfig->DAC_TrimmingValue;
01260     /* Calculate CCR register value depending on DAC_Channel */
01261     tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01262     /* Write to DAC CCR */
01263     hdac->Instance->CCR = tmpreg1;
01264   }
01265   /* else factory trimming is used (factory setting are available at reset)*/
01266   /* SW Nothing has nothing to do */
01267
01268   /* Get the DAC MCR value */
01269   tmpreg1 = hdac->Instance->MCR;
01270   /* Clear DAC_MCR_MODEx bits */
01271   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
01272   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
01273
01274
01275   if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
01276   {
01277     connectOnChip = 0x00000000UL;
01278   }
01279   else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
01280   {
01281     connectOnChip = DAC_MCR_MODE1_0;
01282   }
01283   else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
01284   {
01285     if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
01286     {
01287       connectOnChip = DAC_MCR_MODE1_0;
01288     }
01289     else
01290     {
01291       connectOnChip = 0x00000000UL;
01292     }
01293   }
01294   tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
01295   /* Clear DAC_MCR_DMADOUBLEx */
01296   tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
01297   /* Configure for the selected DAC channel: DMA double data mode */
01298   tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
01299   /* Clear DAC_MCR_SINFORMATx */
01300   tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
01301   /* Configure for the selected DAC channel: Signed format */
01302   tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
01303   /* Clear DAC_MCR_HFSEL bits */
01304   tmpreg1 &= ~(DAC_MCR_HFSEL);
01305   /* Configure for both DAC channels: high frequency mode */
01306   if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
01307   {
01308     hclkfreq = HAL_RCC_GetHCLKFreq();
01309     if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
01310     {
01311       tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
01312     }
01313     else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
01314     {
01315       tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
01316     }
01317     else
01318     {
01319       tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
01320     }
01321   }
01322   else
01323   {
01324     tmpreg1 |= sConfig->DAC_HighFrequency;
01325   }
01326   /* Calculate MCR register value depending on DAC_Channel */
01327   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01328   /* Write to DAC MCR */
01329   hdac->Instance->MCR = tmpreg1;
01330
01331   /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
01332   CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
01333
01334   /* Get the DAC CR value */
01335   tmpreg1 = hdac->Instance->CR;
01336   /* Clear TENx, TSELx, WAVEx and MAMPx bits */
01337   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
01338   /* Configure for the selected DAC channel: trigger */
01339   /* Set TSELx and TENx bits according to DAC_Trigger value */
01340   tmpreg2 = sConfig->DAC_Trigger;
01341   /* Calculate CR register value depending on DAC_Channel */
01342   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01343   /* Write to DAC CR */
01344   hdac->Instance->CR = tmpreg1;
01345   /* Disable wave generation */
01346   CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
01347
01348   /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */
01349   tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos;
01350   tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos;
01351   /* Modify STMODR register value depending on DAC_Channel */
01352   MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1)
01353              << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL));
01354   /* Change DAC state */
01355   hdac->State = HAL_DAC_STATE_READY;
01356
01357   /* Process unlocked */
01358   __HAL_UNLOCK(hdac);
01359
01360   /* Return function status */
01361   return status;
01362 }
01363
01364 /**
01365   * @}
01366   */
01367
01368 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
01369   *  @brief   Peripheral State and Errors functions
01370   *
01371 @verbatim
01372   ==============================================================================
01373             ##### Peripheral State and Errors functions #####
01374   ==============================================================================
01375     [..]
01376     This subsection provides functions allowing to
01377       (+) Check the DAC state.
01378       (+) Check the DAC Errors.
01379
01380 @endverbatim
01381   * @{
01382   */
01383
01384 /**
01385   * @brief  return the DAC handle state
01386   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01387   *         the configuration information for the specified DAC.
01388   * @retval HAL state
01389   */
01390 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
01391 {
01392   /* Return DAC handle state */
01393   return hdac->State;
01394 }
01395
01396
01397 /**
01398   * @brief  Return the DAC error code
01399   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01400   *         the configuration information for the specified DAC.
01401   * @retval DAC Error Code
01402   */
01403 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
01404 {
01405   return hdac->ErrorCode;
01406 }
01407
01408 /**
01409   * @}
01410   */
01411
01412 /**
01413   * @}
01414   */
01415
01416 /** @addtogroup DAC_Exported_Functions
01417   * @{
01418   */
01419
01420 /** @addtogroup DAC_Exported_Functions_Group1
01421   * @{
01422   */
01423 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01424 /**
01425   * @brief  Register a User DAC Callback
01426   *         To be used instead of the weak (overridden) predefined callback
01427   * @note   The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
01428   *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
01429   * @param  hdac DAC handle
01430   * @param  CallbackID ID of the callback to be registered
01431   *         This parameter can be one of the following values:
01432   *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
01433   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
01434   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
01435   *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
01436   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
01437   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
01438   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
01439   *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
01440   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
01441   *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
01442   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
01443   *
01444   * @param  pCallback pointer to the Callback function
01445   * @retval status
01446   */
01447 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
01448                                            pDAC_CallbackTypeDef pCallback)
01449 {
01450   HAL_StatusTypeDef status = HAL_OK;
01451
01452   /* Check the DAC peripheral handle */
01453   if (hdac == NULL)
01454   {
01455     return HAL_ERROR;
01456   }
01457
01458   if (pCallback == NULL)
01459   {
01460     /* Update the error code */
01461     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01462     return HAL_ERROR;
01463   }
01464
01465   if (hdac->State == HAL_DAC_STATE_READY)
01466   {
01467     switch (CallbackID)
01468     {
01469       case HAL_DAC_CH1_COMPLETE_CB_ID :
01470         hdac->ConvCpltCallbackCh1 = pCallback;
01471         break;
01472       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01473         hdac->ConvHalfCpltCallbackCh1 = pCallback;
01474         break;
01475       case HAL_DAC_CH1_ERROR_ID :
01476         hdac->ErrorCallbackCh1 = pCallback;
01477         break;
01478       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01479         hdac->DMAUnderrunCallbackCh1 = pCallback;
01480         break;
01481
01482       case HAL_DAC_CH2_COMPLETE_CB_ID :
01483         hdac->ConvCpltCallbackCh2 = pCallback;
01484         break;
01485       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01486         hdac->ConvHalfCpltCallbackCh2 = pCallback;
01487         break;
01488       case HAL_DAC_CH2_ERROR_ID :
01489         hdac->ErrorCallbackCh2 = pCallback;
01490         break;
01491       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01492         hdac->DMAUnderrunCallbackCh2 = pCallback;
01493         break;
01494
01495       case HAL_DAC_MSPINIT_CB_ID :
01496         hdac->MspInitCallback = pCallback;
01497         break;
01498       case HAL_DAC_MSPDEINIT_CB_ID :
01499         hdac->MspDeInitCallback = pCallback;
01500         break;
01501       default :
01502         /* Update the error code */
01503         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01504         /* update return status */
01505         status =  HAL_ERROR;
01506         break;
01507     }
01508   }
01509   else if (hdac->State == HAL_DAC_STATE_RESET)
01510   {
01511     switch (CallbackID)
01512     {
01513       case HAL_DAC_MSPINIT_CB_ID :
01514         hdac->MspInitCallback = pCallback;
01515         break;
01516       case HAL_DAC_MSPDEINIT_CB_ID :
01517         hdac->MspDeInitCallback = pCallback;
01518         break;
01519       default :
01520         /* Update the error code */
01521         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01522         /* update return status */
01523         status =  HAL_ERROR;
01524         break;
01525     }
01526   }
01527   else
01528   {
01529     /* Update the error code */
01530     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01531     /* update return status */
01532     status =  HAL_ERROR;
01533   }
01534
01535   return status;
01536 }
01537
01538 /**
01539   * @brief  Unregister a User DAC Callback
01540   *         DAC Callback is redirected to the weak (overridden) predefined callback
01541   * @note   The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
01542   *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
01543   * @param  hdac DAC handle
01544   * @param  CallbackID ID of the callback to be unregistered
01545   *         This parameter can be one of the following values:
01546   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 transfer Complete Callback ID
01547   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
01548   *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
01549   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
01550   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
01551   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
01552   *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
01553   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
01554   *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
01555   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
01556   *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
01557   * @retval status
01558   */
01559 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
01560 {
01561   HAL_StatusTypeDef status = HAL_OK;
01562
01563   /* Check the DAC peripheral handle */
01564   if (hdac == NULL)
01565   {
01566     return HAL_ERROR;
01567   }
01568
01569   if (hdac->State == HAL_DAC_STATE_READY)
01570   {
01571     switch (CallbackID)
01572     {
01573       case HAL_DAC_CH1_COMPLETE_CB_ID :
01574         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01575         break;
01576       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01577         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01578         break;
01579       case HAL_DAC_CH1_ERROR_ID :
01580         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01581         break;
01582       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01583         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01584         break;
01585
01586       case HAL_DAC_CH2_COMPLETE_CB_ID :
01587         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01588         break;
01589       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01590         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01591         break;
01592       case HAL_DAC_CH2_ERROR_ID :
01593         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01594         break;
01595       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01596         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01597         break;
01598
01599       case HAL_DAC_MSPINIT_CB_ID :
01600         hdac->MspInitCallback = HAL_DAC_MspInit;
01601         break;
01602       case HAL_DAC_MSPDEINIT_CB_ID :
01603         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01604         break;
01605       case HAL_DAC_ALL_CB_ID :
01606         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01607         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01608         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01609         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01610
01611         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01612         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01613         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01614         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01615
01616         hdac->MspInitCallback = HAL_DAC_MspInit;
01617         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01618         break;
01619       default :
01620         /* Update the error code */
01621         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01622         /* update return status */
01623         status =  HAL_ERROR;
01624         break;
01625     }
01626   }
01627   else if (hdac->State == HAL_DAC_STATE_RESET)
01628   {
01629     switch (CallbackID)
01630     {
01631       case HAL_DAC_MSPINIT_CB_ID :
01632         hdac->MspInitCallback = HAL_DAC_MspInit;
01633         break;
01634       case HAL_DAC_MSPDEINIT_CB_ID :
01635         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01636         break;
01637       default :
01638         /* Update the error code */
01639         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01640         /* update return status */
01641         status =  HAL_ERROR;
01642         break;
01643     }
01644   }
01645   else
01646   {
01647     /* Update the error code */
01648     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01649     /* update return status */
01650     status =  HAL_ERROR;
01651   }
01652
01653   return status;
01654 }
01655 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01656
01657 /**
01658   * @}
01659   */
01660
01661 /**
01662   * @}
01663   */
01664
01665 /** @addtogroup DAC_Private_Functions
01666   * @{
01667   */
01668
01669 /**
01670   * @brief  DMA conversion complete callback.
01671   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01672   *                the configuration information for the specified DMA module.
01673   * @retval None
01674   */
01675 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01676 {
01677   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01678
01679 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01680   hdac->ConvCpltCallbackCh1(hdac);
01681 #else
01682   HAL_DAC_ConvCpltCallbackCh1(hdac);
01683 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01684
01685   hdac->State = HAL_DAC_STATE_READY;
01686 }
01687
01688 /**
01689   * @brief  DMA half transfer complete callback.
01690   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01691   *                the configuration information for the specified DMA module.
01692   * @retval None
01693   */
01694 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01695 {
01696   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01697   /* Conversion complete callback */
01698 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01699   hdac->ConvHalfCpltCallbackCh1(hdac);
01700 #else
01701   HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01702 #endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
01703 }
01704
01705 /**
01706   * @brief  DMA error callback
01707   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01708   *                the configuration information for the specified DMA module.
01709   * @retval None
01710   */
01711 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01712 {
01713   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01714
01715   /* Set DAC error code to DMA error */
01716   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01717
01718 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01719   hdac->ErrorCallbackCh1(hdac);
01720 #else
01721   HAL_DAC_ErrorCallbackCh1(hdac);
01722 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01723
01724   hdac->State = HAL_DAC_STATE_READY;
01725 }
01726
01727 /**
01728   * @}
01729   */
01730
01731 /**
01732   * @}
01733   */
01734
01735 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
01736
01737 #endif /* HAL_DAC_MODULE_ENABLED */
01738 /**
01739   * @}
01740   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_dac.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_DAC_H
00021 #define STM32G4xx_HAL_DAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /** @addtogroup STM32G4xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32g4xx_hal_def.h"
00033
00034 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00035
00036 /** @addtogroup DAC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup DAC_Exported_Types DAC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL State structures definition
00048   */
00049 typedef enum
00050 {
00051   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00052   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00053   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00054   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00055   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
00056
00057 } HAL_DAC_StateTypeDef;
00058
00059 /**
00060   * @brief  DAC handle Structure definition
00061   */
00062 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00063 typedef struct __DAC_HandleTypeDef
00064 #else
00065 typedef struct
00066 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00067 {
00068   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00069
00070   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00071
00072   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00073
00074   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00075
00076   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00077
00078   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00079
00080 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00081   void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
00082   void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
00083   void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
00084   void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
00085
00086   void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
00087   void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
00088   void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
00089   void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
00090
00091
00092   void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
00093   void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
00094 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00095
00096 } DAC_HandleTypeDef;
00097
00098 /**
00099   * @brief   DAC Configuration sample and hold Channel structure definition
00100   */
00101 typedef struct
00102 {
00103   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
00104                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00105                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00106
00107   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
00108                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00109                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00110
00111   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
00112                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00113                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
00114 } DAC_SampleAndHoldConfTypeDef;
00115
00116 /**
00117   * @brief   DAC Configuration regular Channel structure definition
00118   */
00119 typedef struct
00120 {
00121   uint32_t DAC_HighFrequency;            /*!< Specifies the frequency interface mode
00122                                               This parameter can be a value of @ref DAC_HighFrequency */
00123
00124   FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
00125                                               This parameter can be ENABLE or DISABLE */
00126
00127   FunctionalState DAC_SignedFormat;      /*!< Specifies if signed format should be used or not for the selected channel.
00128                                               This parameter can be ENABLE or DISABLE */
00129
00130   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
00131                                               This parameter can be a value of @ref DAC_SampleAndHold */
00132
00133   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
00134                                               This parameter can be a value of @ref DAC_trigger_selection.
00135                                               Note: In case of sawtooth wave generation, this
00136                                               trigger corresponds to the reset trigger. */
00137
00138   uint32_t DAC_Trigger2;                 /*!< Specifies the external secondary trigger for the selected DAC channel.
00139                                               This parameter can be a value of @ref DAC_trigger_selection.
00140                                               Note: In case of sawtooth wave generation, this
00141                                               trigger corresponds to the step trigger.*/
00142
00143   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00144                                                This parameter can be a value of @ref DAC_output_buffer */
00145
00146   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
00147                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
00148
00149   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
00150                                               This parameter must be a value of @ref DAC_UserTrimming
00151                                               DAC_UserTrimming is either factory or user trimming */
00152
00153   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
00154                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
00155                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00156   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
00157 } DAC_ChannelConfTypeDef;
00158
00159 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00160 /**
00161   * @brief  HAL DAC Callback ID enumeration definition
00162   */
00163 typedef enum
00164 {
00165   HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
00166   HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
00167   HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
00168   HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
00169
00170   HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
00171   HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
00172   HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
00173   HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
00174
00175   HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
00176   HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
00177   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
00178 } HAL_DAC_CallbackIDTypeDef;
00179
00180 /**
00181   * @brief  HAL DAC Callback pointer definition
00182   */
00183 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
00184 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported constants --------------------------------------------------------*/
00191
00192 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00193   * @{
00194   */
00195
00196 /** @defgroup DAC_Error_Code DAC Error Code
00197   * @{
00198   */
00199 #define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
00200 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
00201 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
00202 #define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
00203 #define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
00204 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00205 #define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
00206 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup DAC_trigger_selection DAC trigger selection
00213   * @{
00214   */
00215 #define DAC_TRIGGER_NONE                0x00000000UL                                                                      /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
00216 #define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
00217 #define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
00218 #define DAC_TRIGGER_T8_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
00219 #define DAC_TRIGGER_T7_TRGO             (                                  DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */
00220 #define DAC_TRIGGER_T15_TRGO            (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */
00221 #define DAC_TRIGGER_T2_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */
00222 #define DAC_TRIGGER_T4_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */
00223 #define DAC_TRIGGER_EXT_IT9             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */
00224 #define DAC_TRIGGER_EXT_IT10            (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */
00225 #define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */
00226 #define DAC_TRIGGER_T3_TRGO             (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */
00227 #define DAC_TRIGGER_HRTIM_RST_TRG1      (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00228 #define DAC_TRIGGER_HRTIM_STEP_TRG1     (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00229 #define DAC_TRIGGER_HRTIM_RST_TRG2      (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00230 #define DAC_TRIGGER_HRTIM_STEP_TRG2     (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00231 #define DAC_TRIGGER_HRTIM_RST_TRG3      (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00232 #define DAC_TRIGGER_HRTIM_STEP_TRG3     (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00233 #define DAC_TRIGGER_HRTIM_RST_TRG4      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00234 #define DAC_TRIGGER_HRTIM_STEP_TRG4     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00235 #define DAC_TRIGGER_HRTIM_RST_TRG5      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00236 #define DAC_TRIGGER_HRTIM_STEP_TRG5     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00237 #define DAC_TRIGGER_HRTIM_RST_TRG6      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00238 #define DAC_TRIGGER_HRTIM_STEP_TRG6     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00239 #define DAC_TRIGGER_HRTIM_TRG01         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00240 #define DAC_TRIGGER_HRTIM_TRG02         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
00241 #define DAC_TRIGGER_HRTIM_TRG03         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup DAC_output_buffer DAC output buffer
00248   * @{
00249   */
00250 #define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
00251 #define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup DAC_Channel_selection DAC Channel selection
00258   * @{
00259   */
00260 #define DAC_CHANNEL_1                      0x00000000U
00261
00262 #define DAC_CHANNEL_2                      0x00000010U
00263
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup DAC_data_alignment DAC data alignment
00269   * @{
00270   */
00271 #define DAC_ALIGN_12B_R                    0x00000000U
00272 #define DAC_ALIGN_12B_L                    0x00000004U
00273 #define DAC_ALIGN_8B_R                     0x00000008U
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup DAC_flags_definition DAC flags definition
00280   * @{
00281   */
00282 #define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
00283
00284 #define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
00285
00286 #define DAC_FLAG_DAC1RDY                   (DAC_SR_DAC1RDY)
00287
00288 #define DAC_FLAG_DAC2RDY                   (DAC_SR_DAC2RDY)
00289
00290
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup DAC_IT_definition  DAC IT definition
00296   * @{
00297   */
00298 #define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
00299
00300 #define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
00301
00302
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
00308   * @{
00309   */
00310 #define DAC_CHIPCONNECT_EXTERNAL       (1UL << 0)
00311 #define DAC_CHIPCONNECT_INTERNAL       (1UL << 1)
00312 #define DAC_CHIPCONNECT_BOTH           (1UL << 2)
00313
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup DAC_UserTrimming DAC User Trimming
00319   * @{
00320   */
00321 #define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
00322 #define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup DAC_SampleAndHold DAC power mode
00328   * @{
00329   */
00330 #define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
00331 #define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
00332
00333 /**
00334   * @}
00335   */
00336 /** @defgroup DAC_HighFrequency DAC high frequency interface mode
00337   * @{
00338   */
00339 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE        0x00000000UL       /*!< High frequency interface mode disabled */
00340 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ    (DAC_MCR_HFSEL_0)  /*!< High frequency interface mode compatible to AHB>80MHz enabled */
00341 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ   (DAC_MCR_HFSEL_1)  /*!< High frequency interface mode compatible to AHB>160MHz enabled */
00342 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC      0x00000002UL       /*!< High frequency interface mode automatic */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00353 /* (transition from disable to enable).                                       */
00354 /* Note: DAC channel startup time depends on board application environment:   */
00355 /*       impedance connected to DAC channel output.                           */
00356 /*       The delay below is specified under conditions:                       */
00357 /*        - voltage maximum transition (lowest to highest value)              */
00358 /*        - until voltage reaches final value +-1LSB                          */
00359 /*        - DAC channel output buffer enabled                                 */
00360 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00361 /* Literal set to maximum value (refer to device datasheet,                   */
00362 /* parameter "tWAKEUP").                                                      */
00363 /* Unit: us                                                                   */
00364 #define DAC_DELAY_STARTUP_US          (15UL)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00365
00366 /* Exported macro ------------------------------------------------------------*/
00367
00368 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00369   * @{
00370   */
00371
00372 /** @brief Reset DAC handle state.
00373   * @param  __HANDLE__ specifies the DAC handle.
00374   * @retval None
00375   */
00376 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00377 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00378                                                       (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
00379                                                       (__HANDLE__)->MspInitCallback   = NULL;                \
00380                                                       (__HANDLE__)->MspDeInitCallback = NULL;                \
00381                                                      } while(0)
00382 #else
00383 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00384 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00385
00386 /** @brief Enable the DAC channel.
00387   * @param  __HANDLE__ specifies the DAC handle.
00388   * @param  __DAC_Channel__ specifies the DAC channel
00389   * @retval None
00390   */
00391 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00392   ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00393
00394 /** @brief Disable the DAC channel.
00395   * @param  __HANDLE__ specifies the DAC handle
00396   * @param  __DAC_Channel__ specifies the DAC channel.
00397   * @retval None
00398   */
00399 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00400   ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00401
00402 /** @brief Set DHR12R1 alignment.
00403   * @param  __ALIGNMENT__ specifies the DAC alignment
00404   * @retval None
00405   */
00406 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
00407
00408
00409 /** @brief  Set DHR12R2 alignment.
00410   * @param  __ALIGNMENT__ specifies the DAC alignment
00411   * @retval None
00412   */
00413 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
00414
00415
00416 /** @brief  Set DHR12RD alignment.
00417   * @param  __ALIGNMENT__ specifies the DAC alignment
00418   * @retval None
00419   */
00420 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
00421
00422 /** @brief Enable the DAC interrupt.
00423   * @param  __HANDLE__ specifies the DAC handle
00424   * @param  __INTERRUPT__ specifies the DAC interrupt.
00425   *          This parameter can be any combination of the following values:
00426   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00427   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
00428   *
00429   *         (1) On this STM32 series, parameter not available on all instances.
00430   *             Refer to device datasheet for channels availability.
00431   * @retval None
00432   */
00433 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00434
00435 /** @brief Disable the DAC interrupt.
00436   * @param  __HANDLE__ specifies the DAC handle
00437   * @param  __INTERRUPT__ specifies the DAC interrupt.
00438   *          This parameter can be any combination of the following values:
00439   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00440   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
00441   *
00442   *         (1) On this STM32 series, parameter not available on all instances.
00443   *             Refer to device datasheet for channels availability.
00444   * @retval None
00445   */
00446 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00447
00448 /** @brief  Check whether the specified DAC interrupt source is enabled or not.
00449   * @param __HANDLE__ DAC handle
00450   * @param __INTERRUPT__ DAC interrupt source to check
00451   *          This parameter can be any combination of the following values:
00452   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00453   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
00454   *
00455   *         (1) On this STM32 series, parameter not available on all instances.
00456   *             Refer to device datasheet for channels availability.
00457   * @retval State of interruption (SET or RESET)
00458   */
00459 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
00460                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
00461
00462 /** @brief  Get the selected DAC's flag status.
00463   * @param  __HANDLE__ specifies the DAC handle.
00464   * @param  __FLAG__ specifies the DAC flag to get.
00465   *          This parameter can be any combination of the following values:
00466   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00467   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
00468   *            @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
00469   *            @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
00470   *
00471   *         (1) On this STM32 series, parameter not available on all instances.
00472   *             Refer to device datasheet for channels availability.
00473   * @retval None
00474   */
00475 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00476
00477 /** @brief  Clear the DAC's flag.
00478   * @param  __HANDLE__ specifies the DAC handle.
00479   * @param  __FLAG__ specifies the DAC flag to clear.
00480   *          This parameter can be any combination of the following values:
00481   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00482   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
00483   *
00484   *         (1) On this STM32 series, parameter not available on all instances.
00485   *             Refer to device datasheet for channels availability.
00486   * @retval None
00487   */
00488 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00489
00490 /**
00491   * @}
00492   */
00493
00494 /* Private macro -------------------------------------------------------------*/
00495
00496 /** @defgroup DAC_Private_Macros DAC Private Macros
00497   * @{
00498   */
00499 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00500                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00501
00502 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
00503 #define IS_DAC_CHANNEL(DACX, CHANNEL)        \
00504   (((DACX) == DAC2) ?                  \
00505    ((CHANNEL) == DAC_CHANNEL_1)        \
00506    :                                    \
00507    (((CHANNEL) == DAC_CHANNEL_1)    || \
00508     ((CHANNEL) == DAC_CHANNEL_2)))
00509 #else
00510 #define IS_DAC_CHANNEL(DACX, CHANNEL)        \
00511   (((CHANNEL) == DAC_CHANNEL_1)     || \
00512    ((CHANNEL) == DAC_CHANNEL_2))
00513 #endif /* STM32G474xx || STM32G484xx || STM32G473xx */
00514
00515 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00516                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00517                              ((ALIGN) == DAC_ALIGN_8B_R))
00518
00519 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
00520
00521 #define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
00522
00523 /**
00524   * @}
00525   */
00526
00527 /* Include DAC HAL Extended module */
00528 #include "stm32g4xx_hal_dac_ex.h"
00529
00530 /* Exported functions --------------------------------------------------------*/
00531
00532 /** @addtogroup DAC_Exported_Functions
00533   * @{
00534   */
00535
00536 /** @addtogroup DAC_Exported_Functions_Group1
00537   * @{
00538   */
00539 /* Initialization and de-initialization functions *****************************/
00540 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
00541 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
00542 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
00543 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
00544
00545 /**
00546   * @}
00547   */
00548
00549 /** @addtogroup DAC_Exported_Functions_Group2
00550   * @{
00551   */
00552 /* IO operation functions *****************************************************/
00553 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
00554 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
00555 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
00556                                     uint32_t Alignment);
00557 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
00558 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
00559 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00560
00561 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00562 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00563 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00564 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00565
00566 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00567 /* DAC callback registering/unregistering */
00568 HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
00569                                                pDAC_CallbackTypeDef pCallback);
00570 HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
00571 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00572
00573 /**
00574   * @}
00575   */
00576
00577 /** @addtogroup DAC_Exported_Functions_Group3
00578   * @{
00579   */
00580 /* Peripheral Control functions ***********************************************/
00581 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
00582 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
00583                                         const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00584 /**
00585   * @}
00586   */
00587
00588 /** @addtogroup DAC_Exported_Functions_Group4
00589   * @{
00590   */
00591 /* Peripheral State and Error functions ***************************************/
00592 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
00593 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
00594
00595 /**
00596   * @}
00597   */
00598
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup DAC_Private_Functions DAC Private Functions
00604   * @{
00605   */
00606 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00607 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00608 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00609 /**
00610   * @}
00611   */
00612
00613 /**
00614   * @}
00615   */
00616
00617 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
00618
00619 /**
00620   * @}
00621   */
00622
00623 #ifdef __cplusplus
00624 }
00625 #endif
00626
00627
00628 #endif /* STM32G4xx_HAL_DAC_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_dac_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended DAC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the DAC peripheral.
00008   *
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                       ##### How to use this driver #####
00024   ==============================================================================
00025     [..]
00026      *** Dual mode IO operation ***
00027      ==============================
00028      [..]
00029       (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
00030           for dual mode operation.
00031           If software trigger is selected, using HAL_DACEx_DualStart() will start
00032           the conversion of the value previously set by HAL_DACEx_DualSetValue().
00033       (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
00034           for dual mode operation.
00035       (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
00036           for dual mode operation using DMA to feed DAC converters.
00037           First issued trigger will start the conversion of the value previously
00038           set by HAL_DACEx_DualSetValue().
00039           The same callbacks that are used in single mode are called in dual mode to notify
00040           transfer completion (half complete or complete), errors or underrun.
00041       (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
00042           for dual mode operation using DMA to feed DAC converters.
00043       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
00044           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00045           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
00046           Channel 1 and Channel 2.
00047      *** Signal generation operation ***
00048      ===================================
00049      [..]
00050       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00051       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00052
00053       (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal.
00054       (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave.
00055       (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave.
00056
00057       (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
00058       (+) HAL_DACEx_SetUserTrimming to set user trimming value.
00059       (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
00060           after reset, user setting if HAL_DACEx_SetUserTrimming have been used
00061           at least one time after reset).
00062
00063  @endverbatim
00064   ******************************************************************************
00065   */
00066
00067
00068 /* Includes ------------------------------------------------------------------*/
00069 #include "stm32g4xx_hal.h"
00070
00071 /** @addtogroup STM32G4xx_HAL_Driver
00072   * @{
00073   */
00074
00075 #ifdef HAL_DAC_MODULE_ENABLED
00076
00077 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00078
00079 /** @defgroup DACEx DACEx
00080   * @brief DAC Extended HAL module driver
00081   * @{
00082   */
00083
00084 /* Private typedef -----------------------------------------------------------*/
00085 /* Private define ------------------------------------------------------------*/
00086
00087 /* Delay for DAC minimum trimming time.                                       */
00088 /* Note: minimum time needed between two calibration steps                    */
00089 /*       The delay below is specified under conditions:                       */
00090 /*        - DAC channel output buffer enabled                                 */
00091 /* Literal set to maximum value (refer to device datasheet,                   */
00092 /* electrical characteristics, parameter "tTRIM").                            */
00093 /* Unit: us                                                                   */
00094 #define DAC_DELAY_TRIM_US          (50UL)     /*!< Delay for DAC minimum trimming time */
00095
00096 /* Private macro -------------------------------------------------------------*/
00097 /* Private variables ---------------------------------------------------------*/
00098 /* Private function prototypes -----------------------------------------------*/
00099 /* Exported functions --------------------------------------------------------*/
00100
00101 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00102   * @{
00103   */
00104
00105 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
00106   *  @brief    Extended IO operation functions
00107   *
00108 @verbatim
00109   ==============================================================================
00110                  ##### Extended features functions #####
00111   ==============================================================================
00112     [..]  This section provides functions allowing to:
00113       (+) Start conversion.
00114       (+) Stop conversion.
00115       (+) Start conversion and enable DMA transfer.
00116       (+) Stop conversion and disable DMA transfer.
00117       (+) Get result of conversion.
00118       (+) Get result of dual mode conversion.
00119
00120 @endverbatim
00121   * @{
00122   */
00123
00124
00125 /**
00126   * @brief  Enables DAC and starts conversion of both channels.
00127   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00128   *         the configuration information for the specified DAC.
00129   * @retval HAL status
00130   */
00131 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
00132 {
00133   uint32_t tmp_swtrig = 0UL;
00134   __IO uint32_t wait_loop_index;
00135
00136   /* Check the DAC peripheral handle */
00137   if (hdac == NULL)
00138   {
00139     return HAL_ERROR;
00140   }
00141
00142   /* Check the parameters */
00143   assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
00144
00145   /* Process locked */
00146   __HAL_LOCK(hdac);
00147
00148   /* Change DAC state */
00149   hdac->State = HAL_DAC_STATE_BUSY;
00150
00151   /* Enable the Peripheral */
00152   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
00153   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
00154   /* Ensure minimum wait before using peripheral after enabling it */
00155   /* Wait loop initialization and execution */
00156   /* Note: Variable divided by 2 to compensate partially              */
00157   /*       CPU processing cycles, scaling in us split to not          */
00158   /*       exceed 32 bits register capacity and handle low frequency. */
00159   wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00160   while (wait_loop_index != 0UL)
00161   {
00162     wait_loop_index--;
00163   }
00164
00165   /* Check if software trigger enabled */
00166   if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
00167   {
00168     tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
00169   }
00170   if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
00171   {
00172     tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
00173   }
00174   /* Enable the selected DAC software conversion*/
00175   SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
00176
00177   /* Change DAC state */
00178   hdac->State = HAL_DAC_STATE_READY;
00179
00180   /* Process unlocked */
00181   __HAL_UNLOCK(hdac);
00182
00183   /* Return function status */
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  Disables DAC and stop conversion of both channels.
00189   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00190   *         the configuration information for the specified DAC.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
00194 {
00195   /* Check the DAC peripheral handle */
00196   if (hdac == NULL)
00197   {
00198     return HAL_ERROR;
00199   }
00200
00201   /* Check the parameters */
00202   assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
00203
00204   /* Disable the Peripheral */
00205   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
00206   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
00207
00208   /* Change DAC state */
00209   hdac->State = HAL_DAC_STATE_READY;
00210
00211   /* Return function status */
00212   return HAL_OK;
00213 }
00214
00215 /**
00216   * @brief  Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
00217   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00218   *         the configuration information for the specified DAC.
00219   * @param  Channel The DAC channel that will request data from DMA.
00220   *          This parameter can be one of the following values:
00221   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00222   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00223   * @param  pData The destination peripheral Buffer address.
00224   * @param  Length The length of data to be transferred from memory to DAC peripheral
00225   * @param  Alignment Specifies the data alignment for DAC channel.
00226   *          This parameter can be one of the following values:
00227   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00228   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00229   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
00233                                           const uint32_t *pData, uint32_t Length, uint32_t Alignment)
00234 {
00235   HAL_StatusTypeDef status;
00236   uint32_t tmpreg = 0UL;
00237   __IO uint32_t wait_loop_index;
00238
00239   /* Check the DAC peripheral handle */
00240   if (hdac == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   /* Check the parameters */
00246   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00247   /* Ensure Channel 2 exists for this particular DAC instance */
00248   assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
00249   assert_param(IS_DAC_ALIGN(Alignment));
00250
00251   /* Process locked */
00252   __HAL_LOCK(hdac);
00253
00254   /* Change DAC state */
00255   hdac->State = HAL_DAC_STATE_BUSY;
00256
00257   if (Channel == DAC_CHANNEL_1)
00258   {
00259     /* Set the DMA transfer complete callback for channel1 */
00260     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00261
00262     /* Set the DMA half transfer complete callback for channel1 */
00263     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00264
00265     /* Set the DMA error callback for channel1 */
00266     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00267
00268     /* Enable the selected DAC channel1 DMA request */
00269     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00270   }
00271   else
00272   {
00273     /* Set the DMA transfer complete callback for channel2 */
00274     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00275
00276     /* Set the DMA half transfer complete callback for channel2 */
00277     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00278
00279     /* Set the DMA error callback for channel2 */
00280     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00281
00282     /* Enable the selected DAC channel2 DMA request */
00283     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00284   }
00285
00286   switch (Alignment)
00287   {
00288     case DAC_ALIGN_12B_R:
00289       /* Get DHR12R1 address */
00290       tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
00291       break;
00292     case DAC_ALIGN_12B_L:
00293       /* Get DHR12L1 address */
00294       tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
00295       break;
00296     case DAC_ALIGN_8B_R:
00297       /* Get DHR8R1 address */
00298       tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
00299       break;
00300     default:
00301       break;
00302   }
00303
00304   /* Enable the DMA channel */
00305   if (Channel == DAC_CHANNEL_1)
00306   {
00307     /* Enable the DAC DMA underrun interrupt */
00308     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00309
00310     /* Enable the DMA channel */
00311     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00312   }
00313   else
00314   {
00315     /* Enable the DAC DMA underrun interrupt */
00316     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00317
00318     /* Enable the DMA channel */
00319     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00320   }
00321
00322   /* Process Unlocked */
00323   __HAL_UNLOCK(hdac);
00324
00325   if (status == HAL_OK)
00326   {
00327     /* Enable the Peripheral */
00328     __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
00329     __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
00330     /* Ensure minimum wait before using peripheral after enabling it */
00331     /* Wait loop initialization and execution */
00332     /* Note: Variable divided by 2 to compensate partially              */
00333     /*       CPU processing cycles, scaling in us split to not          */
00334     /*       exceed 32 bits register capacity and handle low frequency. */
00335     wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00336     while (wait_loop_index != 0UL)
00337     {
00338       wait_loop_index--;
00339     }
00340   }
00341   else
00342   {
00343     hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00344   }
00345
00346   /* Return function status */
00347   return status;
00348 }
00349
00350 /**
00351   * @brief  Disables DAC and stop conversion both channel.
00352   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00353   *         the configuration information for the specified DAC.
00354   * @param  Channel The DAC channel that requests data from DMA.
00355   *          This parameter can be one of the following values:
00356   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00357   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00358   * @retval HAL status
00359   */
00360 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
00361 {
00362   HAL_StatusTypeDef status;
00363
00364   /* Check the DAC peripheral handle */
00365   if (hdac == NULL)
00366   {
00367     return HAL_ERROR;
00368   }
00369
00370   /* Ensure Channel 2 exists for this particular DAC instance */
00371   assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
00372
00373   /* Disable the selected DAC channel DMA request */
00374   CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
00375
00376   /* Disable the Peripheral */
00377   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
00378   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
00379
00380   /* Disable the DMA channel */
00381
00382   /* Channel1 is used */
00383   if (Channel == DAC_CHANNEL_1)
00384   {
00385     /* Disable the DMA channel */
00386     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00387
00388     /* Disable the DAC DMA underrun interrupt */
00389     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00390   }
00391   else
00392   {
00393     /* Disable the DMA channel */
00394     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00395
00396     /* Disable the DAC DMA underrun interrupt */
00397     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00398   }
00399
00400   /* Check if DMA Channel effectively disabled */
00401   if (status != HAL_OK)
00402   {
00403     /* Update DAC state machine to error */
00404     hdac->State = HAL_DAC_STATE_ERROR;
00405   }
00406   else
00407   {
00408     /* Change DAC state */
00409     hdac->State = HAL_DAC_STATE_READY;
00410   }
00411
00412   /* Return function status */
00413   return status;
00414 }
00415
00416
00417 /**
00418   * @brief  Enable or disable the selected DAC channel wave generation.
00419   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00420   *         the configuration information for the specified DAC.
00421   * @param  Channel The selected DAC channel.
00422   *          This parameter can be one of the following values:
00423   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00424   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00425   *
00426   *         (1) On this STM32 series, parameter not available on all instances.
00427   *             Refer to device datasheet for channels availability.
00428   * @param  Amplitude Select max triangle amplitude.
00429   *          This parameter can be one of the following values:
00430   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00431   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00432   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00433   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00434   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00435   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00436   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00437   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00438   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00439   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00440   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00441   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00445 {
00446   /* Check the DAC peripheral handle */
00447   if (hdac == NULL)
00448   {
00449     return HAL_ERROR;
00450   }
00451
00452   /* Check the parameters */
00453   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00454   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00455
00456   /* Process locked */
00457   __HAL_LOCK(hdac);
00458
00459   /* Change DAC state */
00460   hdac->State = HAL_DAC_STATE_BUSY;
00461
00462   /* Enable the triangle wave generation for the selected DAC channel */
00463   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
00464              (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
00465
00466   /* Change DAC state */
00467   hdac->State = HAL_DAC_STATE_READY;
00468
00469   /* Process unlocked */
00470   __HAL_UNLOCK(hdac);
00471
00472   /* Return function status */
00473   return HAL_OK;
00474 }
00475
00476 /**
00477   * @brief  Enable or disable the selected DAC channel wave generation.
00478   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00479   *         the configuration information for the specified DAC.
00480   * @param  Channel The selected DAC channel.
00481   *          This parameter can be one of the following values:
00482   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00483   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00484   *
00485   *         (1) On this STM32 series, parameter not available on all instances.
00486   *             Refer to device datasheet for channels availability.
00487   * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
00488   *          This parameter can be one of the following values:
00489   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00490   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00491   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00492   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00493   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00494   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00495   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00496   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00497   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00498   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00499   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00500   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00501   * @retval HAL status
00502   */
00503 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00504 {
00505   /* Check the DAC peripheral handle */
00506   if (hdac == NULL)
00507   {
00508     return HAL_ERROR;
00509   }
00510
00511   /* Check the parameters */
00512   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00513   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00514
00515   /* Process locked */
00516   __HAL_LOCK(hdac);
00517
00518   /* Change DAC state */
00519   hdac->State = HAL_DAC_STATE_BUSY;
00520
00521   /* Enable the noise wave generation for the selected DAC channel */
00522   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
00523              (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
00524
00525   /* Change DAC state */
00526   hdac->State = HAL_DAC_STATE_READY;
00527
00528   /* Process unlocked */
00529   __HAL_UNLOCK(hdac);
00530
00531   /* Return function status */
00532   return HAL_OK;
00533 }
00534
00535 /**
00536   * @brief  Enable or disable the selected DAC channel sawtooth wave generation.
00537   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00538   *         the configuration information for the specified DAC.
00539   * @param  Channel The selected DAC channel.
00540   *          This parameter can be one of the following values:
00541   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00542   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00543   *
00544   *         (1) On this STM32 series, parameter not available on all instances.
00545   *             Refer to device datasheet for channels availability.
00546   * @param  Polarity polarity to be used for wave generation.
00547   *          This parameter can be one of the following values:
00548   *            @arg DAC_SAWTOOTH_POLARITY_DECREMENT
00549   *            @arg DAC_SAWTOOTH_POLARITY_INCREMENT
00550   * @param  ResetData Sawtooth wave reset value.
00551   *          Range is from 0 to DAC full range 4095 (0xFFF)
00552   * @param  StepData Sawtooth wave step value.
00553   *          12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
00554   *          Step value step is 1/16 = 0.0625
00555   *          Step value range is 0.0000 to 4095.9375 (0xFFF.F)
00556   * @note    Sawtooth reset and step triggers are configured by calling @ref HAL_DAC_ConfigChannel
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
00560                                                  uint32_t ResetData, uint32_t StepData)
00561 {
00562   /* Check the DAC peripheral handle */
00563   if (hdac == NULL)
00564   {
00565     return HAL_ERROR;
00566   }
00567
00568   /* Check the parameters */
00569   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00570   assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity));
00571   assert_param(IS_DAC_RESET_DATA(ResetData));
00572   assert_param(IS_DAC_STEP_DATA(StepData));
00573
00574   /* Process locked */
00575   __HAL_LOCK(hdac);
00576
00577   /* Change DAC state */
00578   hdac->State = HAL_DAC_STATE_BUSY;
00579
00580   if (Channel == DAC_CHANNEL_1)
00581   {
00582     /* Configure the sawtooth wave generation data parameters */
00583     MODIFY_REG(hdac->Instance->STR1,
00584                DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1,
00585                (StepData << DAC_STR1_STINCDATA1_Pos)
00586                | Polarity
00587                | (ResetData << DAC_STR1_STRSTDATA1_Pos));
00588   }
00589   else
00590   {
00591     /* Configure the sawtooth wave generation data parameters */
00592     MODIFY_REG(hdac->Instance->STR2,
00593                DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2,
00594                (StepData << DAC_STR2_STINCDATA2_Pos)
00595                | Polarity
00596                | (ResetData << DAC_STR2_STRSTDATA2_Pos));
00597   }
00598
00599   /* Enable the sawtooth wave generation for the selected DAC channel */
00600   MODIFY_REG(hdac->Instance->CR,
00601              (DAC_CR_WAVE1) << (Channel & 0x10UL),
00602              (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL));
00603
00604   /* Change DAC state */
00605   hdac->State = HAL_DAC_STATE_READY;
00606
00607   /* Process unlocked */
00608   __HAL_UNLOCK(hdac);
00609
00610   /* Return function status */
00611   return HAL_OK;
00612 }
00613
00614 /**
00615   * @brief  Trig sawtooth wave reset
00616   * @note   This function allows to reset sawtooth wave in case of SW trigger
00617   *         has been configured for this usage.
00618   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00619   *         the configuration information for the specified DAC.
00620   * @param  Channel The selected DAC channel.
00621   *          This parameter can be one of the following values:
00622   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00623   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00624   *
00625   *         (1) On this STM32 series, parameter not available on all instances.
00626   *             Refer to device datasheet for channels availability.
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel)
00630 {
00631   HAL_StatusTypeDef status = HAL_OK;
00632
00633   /* Check the DAC peripheral handle */
00634   if (hdac == NULL)
00635   {
00636     return HAL_ERROR;
00637   }
00638
00639   /* Check the parameters */
00640   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00641
00642   /* Process locked */
00643   __HAL_LOCK(hdac);
00644
00645   if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */)
00646   {
00647     /* Change DAC state */
00648     hdac->State = HAL_DAC_STATE_BUSY;
00649
00650     if (Channel == DAC_CHANNEL_1)
00651     {
00652       /* Enable the selected DAC software conversion */
00653       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00654     }
00655     else
00656     {
00657       /* Enable the selected DAC software conversion */
00658       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00659     }
00660
00661     /* Change DAC state */
00662     hdac->State = HAL_DAC_STATE_READY;
00663   }
00664   else
00665   {
00666     status = HAL_ERROR;
00667   }
00668
00669   /* Process unlocked */
00670   __HAL_UNLOCK(hdac);
00671
00672   /* Return function status */
00673   return status;
00674 }
00675
00676 /**
00677   * @brief  Trig sawtooth wave step
00678   * @note   This function allows to generate step  in sawtooth wave in case of
00679   *         SW trigger has been configured for this usage.
00680   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00681   *         the configuration information for the specified DAC.
00682   * @param  Channel The selected DAC channel.
00683   *          This parameter can be one of the following values:
00684   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00685   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00686   *
00687   *         (1) On this STM32 series, parameter not available on all instances.
00688   *             Refer to device datasheet for channels availability.
00689   * @retval HAL status
00690   */
00691 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel)
00692 {
00693   HAL_StatusTypeDef status = HAL_OK;
00694
00695   /* Check the DAC peripheral handle */
00696   if (hdac == NULL)
00697   {
00698     return HAL_ERROR;
00699   }
00700
00701   /* Check the parameters */
00702   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00703
00704   /* Process locked */
00705   __HAL_LOCK(hdac);
00706
00707   if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */)
00708   {
00709     /* Change DAC state */
00710     hdac->State = HAL_DAC_STATE_BUSY;
00711
00712     if (Channel == DAC_CHANNEL_1)
00713     {
00714       /* Enable the selected DAC software conversion */
00715       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1);
00716     }
00717     else
00718     {
00719       /* Enable the selected DAC software conversion */
00720       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2);
00721     }
00722
00723     /* Change DAC state */
00724     hdac->State = HAL_DAC_STATE_READY;
00725   }
00726   else
00727   {
00728     status = HAL_ERROR;
00729   }
00730
00731   /* Process unlocked */
00732   __HAL_UNLOCK(hdac);
00733
00734   /* Return function status */
00735   return status;
00736 }
00737
00738
00739 /**
00740   * @brief  Set the specified data holding register value for dual DAC channel.
00741   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00742   *               the configuration information for the specified DAC.
00743   * @param  Alignment Specifies the data alignment for dual channel DAC.
00744   *          This parameter can be one of the following values:
00745   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00746   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00747   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00748   * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
00749   * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
00750   * @note   In dual mode, a unique register access is required to write in both
00751   *          DAC channels at the same time.
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00755 {
00756   uint32_t data;
00757   uint32_t tmp;
00758
00759   /* Check the DAC peripheral handle */
00760   if (hdac == NULL)
00761   {
00762     return HAL_ERROR;
00763   }
00764
00765   /* Check the parameters */
00766   assert_param(IS_DAC_ALIGN(Alignment));
00767   assert_param(IS_DAC_DATA(Data1));
00768   assert_param(IS_DAC_DATA(Data2));
00769
00770   /* Calculate and set dual DAC data holding register value */
00771   if (Alignment == DAC_ALIGN_8B_R)
00772   {
00773     data = ((uint32_t)Data2 << 8U) | Data1;
00774   }
00775   else
00776   {
00777     data = ((uint32_t)Data2 << 16U) | Data1;
00778   }
00779
00780   tmp = (uint32_t)hdac->Instance;
00781   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00782
00783   /* Set the dual DAC selected data holding register */
00784   *(__IO uint32_t *)tmp = data;
00785
00786   /* Return function status */
00787   return HAL_OK;
00788 }
00789
00790 /**
00791   * @brief  Conversion complete callback in non-blocking mode for Channel2.
00792   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00793   *         the configuration information for the specified DAC.
00794   * @retval None
00795   */
00796 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00797 {
00798   /* Prevent unused argument(s) compilation warning */
00799   UNUSED(hdac);
00800
00801   /* NOTE : This function should not be modified, when the callback is needed,
00802             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00803    */
00804 }
00805
00806 /**
00807   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
00808   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00809   *         the configuration information for the specified DAC.
00810   * @retval None
00811   */
00812 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00813 {
00814   /* Prevent unused argument(s) compilation warning */
00815   UNUSED(hdac);
00816
00817   /* NOTE : This function should not be modified, when the callback is needed,
00818             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00819    */
00820 }
00821
00822 /**
00823   * @brief  Error DAC callback for Channel2.
00824   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00825   *         the configuration information for the specified DAC.
00826   * @retval None
00827   */
00828 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00829 {
00830   /* Prevent unused argument(s) compilation warning */
00831   UNUSED(hdac);
00832
00833   /* NOTE : This function should not be modified, when the callback is needed,
00834             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00835    */
00836 }
00837
00838 /**
00839   * @brief  DMA underrun DAC callback for Channel2.
00840   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00841   *         the configuration information for the specified DAC.
00842   * @retval None
00843   */
00844 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00845 {
00846   /* Prevent unused argument(s) compilation warning */
00847   UNUSED(hdac);
00848
00849   /* NOTE : This function should not be modified, when the callback is needed,
00850             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00851    */
00852 }
00853
00854
00855 /**
00856   * @brief  Run the self calibration of one DAC channel.
00857   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00858   *         the configuration information for the specified DAC.
00859   * @param  sConfig DAC channel configuration structure.
00860   * @param  Channel The selected DAC channel.
00861   *          This parameter can be one of the following values:
00862   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00863   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00864   *
00865   *         (1) On this STM32 series, parameter not available on all instances.
00866   *             Refer to device datasheet for channels availability.
00867   * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
00868   * @retval HAL status
00869   * @note   Calibration runs about 7 ms.
00870   */
00871 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
00872 {
00873   HAL_StatusTypeDef status = HAL_OK;
00874
00875   uint32_t trimmingvalue;
00876   uint32_t delta;
00877   __IO uint32_t wait_loop_index;
00878
00879   /* store/restore channel configuration structure purpose */
00880   uint32_t oldmodeconfiguration;
00881
00882   /* Check the parameters */
00883   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
00884
00885   /* Check the DAC handle allocation */
00886   /* Check if DAC running */
00887   if ((hdac == NULL) || (sConfig == NULL))
00888   {
00889     status = HAL_ERROR;
00890   }
00891   else if (hdac->State == HAL_DAC_STATE_BUSY)
00892   {
00893     status = HAL_ERROR;
00894   }
00895   else
00896   {
00897     /* Process locked */
00898     __HAL_LOCK(hdac);
00899
00900     /* Store configuration */
00901     oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
00902
00903     /* Disable the selected DAC channel */
00904     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
00905     /* Wait for ready bit to be de-asserted */
00906     HAL_Delay(1);
00907
00908     /* Set mode in MCR  for calibration */
00909     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
00910
00911     /* Enable the selected DAC channel calibration */
00912     /* i.e. set DAC_CR_CENx bit */
00913     SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00914
00915     /* Init trimming counter */
00916     /* Medium value */
00917     trimmingvalue = 16UL;
00918     delta = 8UL;
00919     while (delta != 0UL)
00920     {
00921       /* Set candidate trimming */
00922       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00923
00924       /* Wait minimum time needed between two calibration steps (OTRIM) */
00925       /* Wait loop initialization and execution */
00926       /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
00927       /*       32 bits register capacity and handle low frequency. */
00928       wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00929       while (wait_loop_index != 0UL)
00930       {
00931         wait_loop_index--;
00932       }
00933
00934       if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
00935       {
00936         /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
00937         trimmingvalue -= delta;
00938       }
00939       else
00940       {
00941         /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
00942         trimmingvalue += delta;
00943       }
00944       delta >>= 1UL;
00945     }
00946
00947     /* Still need to check if right calibration is current value or one step below */
00948     /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
00949     /* Set candidate trimming */
00950     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00951
00952     /* Wait minimum time needed between two calibration steps (OTRIM) */
00953     /* Wait loop initialization and execution */
00954     /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
00955     /*       32 bits register capacity and handle low frequency. */
00956     wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00957     while (wait_loop_index != 0UL)
00958     {
00959       wait_loop_index--;
00960     }
00961
00962     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
00963     {
00964       /* Trimming is actually one value more */
00965       trimmingvalue++;
00966       /* Set right trimming */
00967       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00968     }
00969
00970     /* Disable the selected DAC channel calibration */
00971     /* i.e. clear DAC_CR_CENx bit */
00972     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00973
00974     sConfig->DAC_TrimmingValue = trimmingvalue;
00975     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00976
00977     /* Restore configuration */
00978     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
00979
00980     /* Process unlocked */
00981     __HAL_UNLOCK(hdac);
00982   }
00983
00984   return status;
00985 }
00986
00987 /**
00988   * @brief  Set the trimming mode and trimming value (user trimming mode applied).
00989   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00990   *         the configuration information for the specified DAC.
00991   * @param  sConfig DAC configuration structure updated with new DAC trimming value.
00992   * @param  Channel The selected DAC channel.
00993   *          This parameter can be one of the following values:
00994   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00995   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
00996   *
00997   *         (1) On this STM32 series, parameter not available on all instances.
00998   *             Refer to device datasheet for channels availability.
00999   * @param  NewTrimmingValue DAC new trimming value
01000   * @retval HAL status
01001   */
01002 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
01003                                             uint32_t NewTrimmingValue)
01004 {
01005   HAL_StatusTypeDef status = HAL_OK;
01006
01007   /* Check the parameters */
01008   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
01009   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
01010
01011   /* Check the DAC handle and channel configuration struct allocation */
01012   if ((hdac == NULL) || (sConfig == NULL))
01013   {
01014     status = HAL_ERROR;
01015   }
01016   else
01017   {
01018     /* Process locked */
01019     __HAL_LOCK(hdac);
01020
01021     /* Set new trimming */
01022     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
01023
01024     /* Update trimming mode */
01025     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
01026     sConfig->DAC_TrimmingValue = NewTrimmingValue;
01027
01028     /* Process unlocked */
01029     __HAL_UNLOCK(hdac);
01030   }
01031   return status;
01032 }
01033
01034 /**
01035   * @brief  Return the DAC trimming value.
01036   * @param  hdac DAC handle
01037   * @param  Channel The selected DAC channel.
01038   *          This parameter can be one of the following values:
01039   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
01040   *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
01041   *
01042   *         (1) On this STM32 series, parameter not available on all instances.
01043   *             Refer to device datasheet for channels availability.
01044   * @retval Trimming value : range: 0->31
01045   *
01046  */
01047 uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
01048 {
01049   /* Check the parameter */
01050   assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
01051
01052   /* Retrieve trimming */
01053   return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
01054 }
01055
01056 /**
01057   * @}
01058   */
01059
01060 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
01061   *  @brief    Extended Peripheral Control functions
01062   *
01063 @verbatim
01064   ==============================================================================
01065              ##### Peripheral Control functions #####
01066   ==============================================================================
01067     [..]  This section provides functions allowing to:
01068       (+) Set the specified data holding register value for DAC channel.
01069
01070 @endverbatim
01071   * @{
01072   */
01073
01074
01075 /**
01076   * @brief  Return the last data output value of the selected DAC channel.
01077   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01078   *         the configuration information for the specified DAC.
01079   * @retval The selected DAC channel data output value.
01080   */
01081 uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
01082 {
01083   uint32_t tmp = 0UL;
01084
01085   tmp |= hdac->Instance->DOR1;
01086
01087   tmp |= hdac->Instance->DOR2 << 16UL;
01088
01089   /* Returns the DAC channel data output register value */
01090   return tmp;
01091 }
01092
01093
01094 /**
01095   * @}
01096   */
01097 /**
01098   * @}
01099   */
01100
01101 /* Private functions ---------------------------------------------------------*/
01102 /** @defgroup DACEx_Private_Functions DACEx private functions
01103   *  @brief    Extended private functions
01104   * @{
01105   */
01106
01107
01108 /**
01109   * @brief  DMA conversion complete callback.
01110   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01111   *                the configuration information for the specified DMA module.
01112   * @retval None
01113   */
01114 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
01115 {
01116   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01117
01118 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01119   hdac->ConvCpltCallbackCh2(hdac);
01120 #else
01121   HAL_DACEx_ConvCpltCallbackCh2(hdac);
01122 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01123
01124   hdac->State = HAL_DAC_STATE_READY;
01125 }
01126
01127 /**
01128   * @brief  DMA half transfer complete callback.
01129   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01130   *                the configuration information for the specified DMA module.
01131   * @retval None
01132   */
01133 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
01134 {
01135   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01136   /* Conversion complete callback */
01137 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01138   hdac->ConvHalfCpltCallbackCh2(hdac);
01139 #else
01140   HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
01141 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01142 }
01143
01144 /**
01145   * @brief  DMA error callback.
01146   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01147   *                the configuration information for the specified DMA module.
01148   * @retval None
01149   */
01150 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
01151 {
01152   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01153
01154   /* Set DAC error code to DMA error */
01155   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01156
01157 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01158   hdac->ErrorCallbackCh2(hdac);
01159 #else
01160   HAL_DACEx_ErrorCallbackCh2(hdac);
01161 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01162
01163   hdac->State = HAL_DAC_STATE_READY;
01164 }
01165
01166
01167 /**
01168   * @}
01169   */
01170
01171 /**
01172   * @}
01173   */
01174
01175 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
01176
01177 #endif /* HAL_DAC_MODULE_ENABLED */
01178
01179 /**
01180   * @}
01181   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dac_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_dac_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_DAC_EX_H
00021 #define STM32G4xx_HAL_DAC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /** @addtogroup STM32G4xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32g4xx_hal_def.h"
00033
00034 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00035
00036 /** @addtogroup DACEx
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /**
00043   * @brief  HAL State structures definition
00044   */
00045
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00049   * @{
00050   */
00051
00052 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
00053   * @{
00054   */
00055 #define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00056 #define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00057 #define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00058 #define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00059 #define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00060 #define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00061 #define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00062 #define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00063 #define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00064 #define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00065 #define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00066 #define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00067 #define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
00068 #define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00069 #define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
00070 #define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00071 #define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
00072 #define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00073 #define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
00074 #define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00075 #define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
00076 #define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00077 #define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
00078 #define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
00085   * @{
00086   */
00087 #define DAC_SAWTOOTH_POLARITY_DECREMENT        0x00000000UL            /*!< Sawtooth wave generation, polarity is decrement */
00088 #define DAC_SAWTOOTH_POLARITY_INCREMENT        (DAC_STR1_STDIR1)       /*!< Sawtooth wave generation, polarity is increment */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /**
00095   * @}
00096   */
00097
00098 /* Exported macro ------------------------------------------------------------*/
00099
00100
00101 /* Private macro -------------------------------------------------------------*/
00102
00103 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00104   * @{
00105   */
00106 #if defined(STM32G474xx) || defined(STM32G484xx)
00107 #define IS_DAC_TRIGGER(DACX, TRIGGER) \
00108   (((TRIGGER) == DAC_TRIGGER_NONE)           || \
00109    ((TRIGGER) == DAC_TRIGGER_SOFTWARE)       || \
00110    ((TRIGGER) == DAC_TRIGGER_T7_TRGO)        || \
00111    ((TRIGGER) == DAC_TRIGGER_T15_TRGO)       || \
00112    ((TRIGGER) == DAC_TRIGGER_T2_TRGO)        || \
00113    ((TRIGGER) == DAC_TRIGGER_T4_TRGO)        || \
00114    ((TRIGGER) == DAC_TRIGGER_EXT_IT9)        || \
00115    ((TRIGGER) == DAC_TRIGGER_T6_TRGO)        || \
00116    ((TRIGGER) == DAC_TRIGGER_T3_TRGO)        || \
00117    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \
00118    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \
00119    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \
00120    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \
00121    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \
00122    ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \
00123    (((DACX) == DAC1) &&                         \
00124     (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
00125      ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01))     \
00126    )                                         || \
00127    (((DACX) == DAC2) &&                         \
00128     (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
00129      ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02))     \
00130    )                                         || \
00131    (((DACX) == DAC3) &&                         \
00132     (((TRIGGER) == DAC_TRIGGER_T1_TRGO)      || \
00133      ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03))     \
00134    )                                         || \
00135    (((DACX) == DAC4) &&                         \
00136     (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
00137      ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01))     \
00138    )                                            \
00139   )
00140 #else
00141 #define IS_DAC_TRIGGER(DACX, TRIGGER) \
00142   (((TRIGGER) == DAC_TRIGGER_NONE)           || \
00143    ((TRIGGER) == DAC_TRIGGER_SOFTWARE)       || \
00144    ((TRIGGER) == DAC_TRIGGER_T7_TRGO)        || \
00145    ((TRIGGER) == DAC_TRIGGER_T15_TRGO)       || \
00146    ((TRIGGER) == DAC_TRIGGER_T2_TRGO)        || \
00147    ((TRIGGER) == DAC_TRIGGER_T4_TRGO)        || \
00148    ((TRIGGER) == DAC_TRIGGER_EXT_IT9)        || \
00149    ((TRIGGER) == DAC_TRIGGER_T6_TRGO)        || \
00150    ((TRIGGER) == DAC_TRIGGER_T3_TRGO)        || \
00151    (((DACX) == DAC3) ?                          \
00152     ((TRIGGER) == DAC_TRIGGER_T1_TRGO)          \
00153     : ((TRIGGER) == DAC_TRIGGER_T8_TRGO)        \
00154    )                                            \
00155   )
00156 #endif /* STM32G474xx || STM32G484xx */
00157
00158 #if defined(STM32G474xx) || defined(STM32G484xx)
00159 #define IS_DAC_TRIGGER2(DACX, TRIGGER) \
00160   (((TRIGGER) == DAC_TRIGGER_NONE)            || \
00161    ((TRIGGER) == DAC_TRIGGER_SOFTWARE)        || \
00162    ((TRIGGER) == DAC_TRIGGER_T7_TRGO)         || \
00163    ((TRIGGER) == DAC_TRIGGER_T15_TRGO)        || \
00164    ((TRIGGER) == DAC_TRIGGER_T2_TRGO)         || \
00165    ((TRIGGER) == DAC_TRIGGER_T4_TRGO)         || \
00166    ((TRIGGER) == DAC_TRIGGER_EXT_IT10)        || \
00167    ((TRIGGER) == DAC_TRIGGER_T6_TRGO)         || \
00168    ((TRIGGER) == DAC_TRIGGER_T3_TRGO)         || \
00169    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \
00170    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \
00171    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \
00172    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \
00173    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \
00174    ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \
00175    (((DACX) == DAC1) &&                          \
00176     ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
00177    ) ||                                          \
00178    (((DACX) == DAC2) &&                          \
00179     ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
00180    ) ||                                          \
00181    (((DACX) == DAC3) &&                          \
00182     ((TRIGGER) == DAC_TRIGGER_T1_TRGO)           \
00183    ) ||                                          \
00184    (((DACX) == DAC4) &&                          \
00185     ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
00186    )                                             \
00187   )
00188 #else
00189 #define IS_DAC_TRIGGER2(DACX, TRIGGER) \
00190   (((TRIGGER) == DAC_TRIGGER_NONE)            || \
00191    ((TRIGGER) == DAC_TRIGGER_SOFTWARE)        || \
00192    ((TRIGGER) == DAC_TRIGGER_T7_TRGO)         || \
00193    ((TRIGGER) == DAC_TRIGGER_T15_TRGO)        || \
00194    ((TRIGGER) == DAC_TRIGGER_T2_TRGO)         || \
00195    ((TRIGGER) == DAC_TRIGGER_T4_TRGO)         || \
00196    ((TRIGGER) == DAC_TRIGGER_EXT_IT10)        || \
00197    ((TRIGGER) == DAC_TRIGGER_T6_TRGO)         || \
00198    ((TRIGGER) == DAC_TRIGGER_T3_TRGO)         || \
00199    (((DACX) == DAC3) ?                           \
00200     ((TRIGGER) == DAC_TRIGGER_T1_TRGO)           \
00201     :((TRIGGER) == DAC_TRIGGER_T8_TRGO)          \
00202    )                                             \
00203   )
00204 #endif /* STM32G474xx || STM32G484xx */
00205 #define  IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE)         || \
00206                                            ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ)     || \
00207                                            ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ)    || \
00208                                            ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
00209
00210 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
00211
00212 #define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
00213
00214 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
00215                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
00216
00217 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00218
00219 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00220
00221 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
00222                                          ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
00223                                          ((CONNECT) == DAC_CHIPCONNECT_BOTH))
00224
00225 #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
00226                                    ((TRIMMING) == DAC_TRIMMING_USER))
00227
00228 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00229                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00230                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00231                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00232                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00233                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00234                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00235                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00236                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00237                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00238                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00239                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00240                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00241                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00242                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00243                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00244                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00245                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00246                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00247                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00248                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00249                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00250                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00251                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00252
00253 #define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
00254                                             ((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))
00255
00256 #define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
00257 #define IS_DAC_STEP_DATA(DATA)  ((DATA) <= 0x0000FFFFUL)
00258 /**
00259   * @}
00260   */
00261
00262 /* Exported functions --------------------------------------------------------*/
00263 /* Extended features functions ***********************************************/
00264
00265 /** @addtogroup DACEx_Exported_Functions
00266   * @{
00267   */
00268
00269 /** @addtogroup DACEx_Exported_Functions_Group2
00270   * @{
00271   */
00272 /* IO operation functions *****************************************************/
00273
00274 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00275 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00276 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
00277                                                  uint32_t ResetData, uint32_t StepData);
00278 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel);
00279 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel);
00280
00281 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
00282 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
00283 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
00284                                           const uint32_t *pData, uint32_t Length, uint32_t Alignment);
00285 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
00286 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00287 uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
00288
00289 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00290 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00291 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
00292 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
00293
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @addtogroup DACEx_Exported_Functions_Group3
00300   * @{
00301   */
00302 /* Peripheral Control functions ***********************************************/
00303
00304 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00305 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
00306                                             uint32_t NewTrimmingValue);
00307 uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @addtogroup DACEx_Private_Functions
00318   * @{
00319   */
00320
00321 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
00322 /* are called by HAL_DAC_Start_DMA */
00323 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00324 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00325 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
00336
00337 /**
00338   * @}
00339   */
00340
00341 #ifdef __cplusplus
00342 }
00343 #endif
00344
00345 #endif /* STM32G4xx_HAL_DAC_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_dma.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Direct Memory Access (DMA) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and errors functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027   [..]
00028    (#) Enable and configure the peripheral to be connected to the DMA Channel
00029        (except for internal SRAM / FLASH memories: no initialization is
00030        necessary). Please refer to the Reference manual for connection between peripherals
00031        and DMA requests.
00032
00033    (#) For a given Channel, program the required configuration through the following parameters:
00034        Channel request, Transfer Direction, Source and Destination data formats,
00035        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
00036        using HAL_DMA_Init() function.
00037
00038        Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
00039        thanks to:
00040       (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
00041       (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();
00042
00043    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00044        detection.
00045
00046    (#) Use HAL_DMA_Abort() function to abort the current transfer
00047
00048      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00049
00050      *** Polling mode IO operation ***
00051      =================================
00052     [..]
00053           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00054               address and destination address and the Length of data to be transferred
00055           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00056               case a fixed Timeout can be configured by User depending from his application.
00057
00058      *** Interrupt mode IO operation ***
00059      ===================================
00060     [..]
00061           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00062           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00063           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00064               Source address and destination address and the Length of data to be transferred.
00065               In this case the DMA interrupt is configured
00066           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00067           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00068               add his own function to register callbacks with HAL_DMA_RegisterCallback().
00069
00070      *** DMA HAL driver macros list ***
00071      =============================================
00072       [..]
00073        Below the list of macros in DMA HAL driver.
00074
00075        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
00076        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
00077        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
00078        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
00079        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
00080        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
00081        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
00082
00083      [..]
00084       (@) You can refer to the DMA HAL driver header file for more useful macros
00085
00086   @endverbatim
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32g4xx_hal.h"
00091
00092 /** @addtogroup STM32G4xx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup DMA DMA
00097   * @brief DMA HAL module driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_DMA_MODULE_ENABLED
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private define ------------------------------------------------------------*/
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /* Private function prototypes -----------------------------------------------*/
00108 /** @defgroup DMA_Private_Functions DMA Private Functions
00109   * @{
00110   */
00111 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00112
00113 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
00114 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Exported functions ---------------------------------------------------------*/
00121
00122 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00127   *  @brief   Initialization and de-initialization functions
00128   *
00129 @verbatim
00130  ===============================================================================
00131              ##### Initialization and de-initialization functions  #####
00132  ===============================================================================
00133     [..]
00134     This section provides functions allowing to initialize the DMA Channel source
00135     and destination addresses, incrementation and data sizes, transfer direction,
00136     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00137     [..]
00138     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00139     reference manual.
00140
00141 @endverbatim
00142   * @{
00143   */
00144
00145 /**
00146   * @brief  Initialize the DMA according to the specified
00147   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
00148   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00149   *               the configuration information for the specified DMA Channel.
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00153 {
00154   uint32_t tmp;
00155
00156   /* Check the DMA handle allocation */
00157   if (hdma == NULL)
00158   {
00159     return HAL_ERROR;
00160   }
00161
00162   /* Check the parameters */
00163   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00164   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00165   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00166   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00167   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00168   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00169   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00170   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00171
00172   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
00173
00174   /* Compute the channel index */
00175   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00176   {
00177     /* DMA1 */
00178     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00179     hdma->DmaBaseAddress = DMA1;
00180   }
00181   else
00182   {
00183     /* DMA2 */
00184     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00185     hdma->DmaBaseAddress = DMA2;
00186   }
00187
00188   /* Change DMA peripheral state */
00189   hdma->State = HAL_DMA_STATE_BUSY;
00190
00191   /* Get the CR register value */
00192   tmp = hdma->Instance->CCR;
00193
00194   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
00195   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
00196                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
00197                       DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
00198
00199   /* Prepare the DMA Channel configuration */
00200   tmp |=  hdma->Init.Direction        |
00201           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00202           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00203           hdma->Init.Mode                | hdma->Init.Priority;
00204
00205   /* Write to DMA Channel CR register */
00206   hdma->Instance->CCR = tmp;
00207
00208   /* Initialize parameters for DMAMUX channel :
00209      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
00210   */
00211   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00212
00213   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00214   {
00215     /* if memory to memory force the request to 0*/
00216     hdma->Init.Request = DMA_REQUEST_MEM2MEM;
00217   }
00218
00219   /* Set peripheral request  to DMAMUX channel */
00220   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
00221
00222   /* Clear the DMAMUX synchro overrun flag */
00223   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00224
00225   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00226   {
00227     /* Initialize parameters for DMAMUX request generator :
00228        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00229     */
00230     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00231
00232     /* Reset the DMAMUX request generator register*/
00233     hdma->DMAmuxRequestGen->RGCR = 0U;
00234
00235     /* Clear the DMAMUX request generator overrun flag */
00236     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00237   }
00238   else
00239   {
00240     hdma->DMAmuxRequestGen = 0U;
00241     hdma->DMAmuxRequestGenStatus = 0U;
00242     hdma->DMAmuxRequestGenStatusMask = 0U;
00243   }
00244
00245   /* Initialize the error code */
00246   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00247
00248   /* Initialize the DMA state*/
00249   hdma->State  = HAL_DMA_STATE_READY;
00250
00251   /* Allocate lock resource and initialize it */
00252   hdma->Lock = HAL_UNLOCKED;
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  DeInitialize the DMA peripheral.
00259   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00260   *               the configuration information for the specified DMA Channel.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00264 {
00265
00266   /* Check the DMA handle allocation */
00267   if (NULL == hdma)
00268   {
00269     return HAL_ERROR;
00270   }
00271
00272   /* Check the parameters */
00273   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00274
00275   /* Disable the selected DMA Channelx */
00276   __HAL_DMA_DISABLE(hdma);
00277
00278   /* Compute the channel index */
00279   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00280   {
00281     /* DMA1 */
00282     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00283     hdma->DmaBaseAddress = DMA1;
00284   }
00285   else
00286   {
00287     /* DMA2 */
00288     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00289     hdma->DmaBaseAddress = DMA2;
00290   }
00291
00292   /* Reset DMA Channel control register */
00293   hdma->Instance->CCR  = 0;
00294
00295   /* Clear all flags */
00296   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
00297
00298   /* Initialize parameters for DMAMUX channel :
00299      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
00300
00301   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00302
00303   /* Reset the DMAMUX channel that corresponds to the DMA channel */
00304   hdma->DMAmuxChannel->CCR = 0;
00305
00306   /* Clear the DMAMUX synchro overrun flag */
00307   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00308
00309   /* Reset Request generator parameters if any */
00310   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00311   {
00312     /* Initialize parameters for DMAMUX request generator :
00313        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00314     */
00315     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00316
00317     /* Reset the DMAMUX request generator register*/
00318     hdma->DMAmuxRequestGen->RGCR = 0U;
00319
00320     /* Clear the DMAMUX request generator overrun flag */
00321     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00322   }
00323
00324   hdma->DMAmuxRequestGen = 0U;
00325   hdma->DMAmuxRequestGenStatus = 0U;
00326   hdma->DMAmuxRequestGenStatusMask = 0U;
00327
00328   /* Clean callbacks */
00329   hdma->XferCpltCallback = NULL;
00330   hdma->XferHalfCpltCallback = NULL;
00331   hdma->XferErrorCallback = NULL;
00332   hdma->XferAbortCallback = NULL;
00333
00334   /* Initialize the error code */
00335   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00336
00337   /* Initialize the DMA state */
00338   hdma->State = HAL_DMA_STATE_RESET;
00339
00340   /* Release Lock */
00341   __HAL_UNLOCK(hdma);
00342
00343   return HAL_OK;
00344 }
00345
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00351   *  @brief   Input and Output operation functions
00352   *
00353 @verbatim
00354  ===============================================================================
00355                       #####  IO operation functions  #####
00356  ===============================================================================
00357     [..]  This section provides functions allowing to:
00358       (+) Configure the source, destination address and data length and Start DMA transfer
00359       (+) Configure the source, destination address and data length and
00360           Start DMA transfer with interrupt
00361       (+) Abort DMA transfer
00362       (+) Poll for transfer complete
00363       (+) Handle DMA interrupt request
00364
00365 @endverbatim
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Start the DMA Transfer.
00371   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00372   *               the configuration information for the specified DMA Channel.
00373   * @param  SrcAddress The source memory Buffer address
00374   * @param  DstAddress The destination memory Buffer address
00375   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
00376   * @retval HAL status
00377   */
00378 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00379 {
00380   HAL_StatusTypeDef status = HAL_OK;
00381
00382   /* Check the parameters */
00383   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00384
00385   /* Process locked */
00386   __HAL_LOCK(hdma);
00387
00388   if (HAL_DMA_STATE_READY == hdma->State)
00389   {
00390     /* Change DMA peripheral state */
00391     hdma->State = HAL_DMA_STATE_BUSY;
00392     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00393
00394     /* Disable the peripheral */
00395     __HAL_DMA_DISABLE(hdma);
00396
00397     /* Configure the source, destination address and the data length & clear flags*/
00398     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00399
00400     /* Enable the Peripheral */
00401     __HAL_DMA_ENABLE(hdma);
00402   }
00403   else
00404   {
00405     /* Process Unlocked */
00406     __HAL_UNLOCK(hdma);
00407     status = HAL_BUSY;
00408   }
00409   return status;
00410 }
00411
00412 /**
00413   * @brief  Start the DMA Transfer with interrupt enabled.
00414   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00415   *               the configuration information for the specified DMA Channel.
00416   * @param  SrcAddress The source memory Buffer address
00417   * @param  DstAddress The destination memory Buffer address
00418   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
00419   * @retval HAL status
00420   */
00421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
00422                                    uint32_t DataLength)
00423 {
00424   HAL_StatusTypeDef status = HAL_OK;
00425
00426   /* Check the parameters */
00427   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00428
00429   /* Process locked */
00430   __HAL_LOCK(hdma);
00431
00432   if (HAL_DMA_STATE_READY == hdma->State)
00433   {
00434     /* Change DMA peripheral state */
00435     hdma->State = HAL_DMA_STATE_BUSY;
00436     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00437
00438     /* Disable the peripheral */
00439     __HAL_DMA_DISABLE(hdma);
00440
00441     /* Configure the source, destination address and the data length & clear flags*/
00442     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00443
00444     /* Enable the transfer complete interrupt */
00445     /* Enable the transfer Error interrupt */
00446     if (NULL != hdma->XferHalfCpltCallback)
00447     {
00448       /* Enable the Half transfer complete interrupt as well */
00449       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00450     }
00451     else
00452     {
00453       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00454       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00455     }
00456
00457     /* Check if DMAMUX Synchronization is enabled*/
00458     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00459     {
00460       /* Enable DMAMUX sync overrun IT*/
00461       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00462     }
00463
00464     if (hdma->DMAmuxRequestGen != 0U)
00465     {
00466       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00467       /* enable the request gen overrun IT*/
00468       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00469     }
00470
00471     /* Enable the Peripheral */
00472     __HAL_DMA_ENABLE(hdma);
00473   }
00474   else
00475   {
00476     /* Process Unlocked */
00477     __HAL_UNLOCK(hdma);
00478
00479     /* Remain BUSY */
00480     status = HAL_BUSY;
00481   }
00482   return status;
00483 }
00484
00485 /**
00486   * @brief  Abort the DMA Transfer.
00487   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00488   *               the configuration information for the specified DMA Channel.
00489     * @retval HAL status
00490   */
00491 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00492 {
00493   HAL_StatusTypeDef status = HAL_OK;
00494
00495   if(hdma->State != HAL_DMA_STATE_BUSY)
00496   {
00497     /* no transfer ongoing */
00498     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00499
00500     status = HAL_ERROR;
00501   }
00502   else
00503   {
00504      /* Disable DMA IT */
00505      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00506
00507      /* disable the DMAMUX sync overrun IT*/
00508      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00509
00510      /* Disable the channel */
00511      __HAL_DMA_DISABLE(hdma);
00512
00513      /* Clear all flags */
00514      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
00515
00516      /* Clear the DMAMUX synchro overrun flag */
00517      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00518
00519      if (hdma->DMAmuxRequestGen != 0U)
00520      {
00521        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00522        /* disable the request gen overrun IT*/
00523        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00524
00525        /* Clear the DMAMUX request generator overrun flag */
00526        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00527      }
00528   }
00529   /* Change the DMA state */
00530   hdma->State = HAL_DMA_STATE_READY;
00531
00532   /* Process Unlocked */
00533   __HAL_UNLOCK(hdma);
00534
00535   return status;
00536 }
00537
00538 /**
00539   * @brief  Aborts the DMA Transfer in Interrupt mode.
00540   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00541   *              the configuration information for the specified DMA Channel.
00542   * @retval HAL status
00543   */
00544 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00545 {
00546   HAL_StatusTypeDef status = HAL_OK;
00547
00548   if (HAL_DMA_STATE_BUSY != hdma->State)
00549   {
00550     /* no transfer ongoing */
00551     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00552
00553     /* Change the DMA state */
00554     hdma->State = HAL_DMA_STATE_READY;
00555
00556     /* Process Unlocked */
00557     __HAL_UNLOCK(hdma);
00558
00559     status = HAL_ERROR;
00560   }
00561   else
00562   {
00563     /* Disable DMA IT */
00564     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00565
00566     /* Disable the channel */
00567     __HAL_DMA_DISABLE(hdma);
00568
00569     /* disable the DMAMUX sync overrun IT*/
00570     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00571
00572     /* Clear all flags */
00573     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
00574
00575     /* Clear the DMAMUX synchro overrun flag */
00576     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00577
00578     if (hdma->DMAmuxRequestGen != 0U)
00579     {
00580       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00581       /* disable the request gen overrun IT*/
00582       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00583
00584       /* Clear the DMAMUX request generator overrun flag */
00585       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00586     }
00587
00588     /* Change the DMA state */
00589     hdma->State = HAL_DMA_STATE_READY;
00590
00591     /* Process Unlocked */
00592     __HAL_UNLOCK(hdma);
00593
00594     /* Call User Abort callback */
00595     if (hdma->XferAbortCallback != NULL)
00596     {
00597       hdma->XferAbortCallback(hdma);
00598     }
00599   }
00600   return status;
00601 }
00602
00603 /**
00604   * @brief  Polling for transfer complete.
00605   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00606   *              the configuration information for the specified DMA Channel.
00607   * @param  CompleteLevel Specifies the DMA level complete.
00608   * @param  Timeout       Timeout duration.
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
00612                                           uint32_t Timeout)
00613 {
00614   uint32_t temp;
00615   uint32_t tickstart;
00616
00617   if (HAL_DMA_STATE_BUSY != hdma->State)
00618   {
00619     /* no transfer ongoing */
00620     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00621     __HAL_UNLOCK(hdma);
00622     return HAL_ERROR;
00623   }
00624
00625   /* Polling mode not supported in circular mode */
00626   if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
00627   {
00628     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00629     return HAL_ERROR;
00630   }
00631
00632   /* Get the level transfer complete flag */
00633   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00634   {
00635     /* Transfer Complete flag */
00636
00637     temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
00638   }
00639   else
00640   {
00641     /* Half Transfer Complete flag */
00642     temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
00643   }
00644
00645   /* Get tick */
00646   tickstart = HAL_GetTick();
00647
00648   while (0U == (hdma->DmaBaseAddress->ISR & temp))
00649   {
00650     if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))))
00651     {
00652       /* When a DMA transfer error occurs */
00653       /* A hardware clear of its EN bits is performed */
00654       /* Clear all flags */
00655       hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
00656
00657       /* Update error code */
00658       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00659
00660       /* Change the DMA state */
00661       hdma->State = HAL_DMA_STATE_READY;
00662
00663       /* Process Unlocked */
00664       __HAL_UNLOCK(hdma);
00665
00666       return HAL_ERROR;
00667     }
00668     /* Check for the Timeout */
00669     if (Timeout != HAL_MAX_DELAY)
00670     {
00671       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00672       {
00673         /* Update error code */
00674         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00675
00676         /* Change the DMA state */
00677         hdma->State = HAL_DMA_STATE_READY;
00678
00679         /* Process Unlocked */
00680         __HAL_UNLOCK(hdma);
00681
00682         return HAL_ERROR;
00683       }
00684     }
00685   }
00686
00687   /*Check for DMAMUX Request generator (if used) overrun status */
00688   if (hdma->DMAmuxRequestGen != 0U)
00689   {
00690     /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
00691     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00692     {
00693       /* Disable the request gen overrun interrupt */
00694       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00695
00696       /* Clear the DMAMUX request generator overrun flag */
00697       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00698
00699       /* Update error code */
00700       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00701     }
00702   }
00703
00704   /* Check for DMAMUX Synchronization overrun */
00705   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00706   {
00707     /* Clear the DMAMUX synchro overrun flag */
00708     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00709
00710     /* Update error code */
00711     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00712   }
00713
00714   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00715   {
00716     /* Clear the transfer complete flag */
00717     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
00718
00719     /* The selected Channelx EN bit is cleared (DMA is disabled and
00720     all transfers are complete) */
00721     hdma->State = HAL_DMA_STATE_READY;
00722   }
00723   else
00724   {
00725     /* Clear the half transfer complete flag */
00726     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
00727   }
00728
00729   /* Process unlocked */
00730   __HAL_UNLOCK(hdma);
00731
00732   return HAL_OK;
00733 }
00734
00735 /**
00736   * @brief  Handle DMA interrupt request.
00737   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00738   *               the configuration information for the specified DMA Channel.
00739   * @retval None
00740   */
00741 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00742 {
00743   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00744   uint32_t source_it = hdma->Instance->CCR;
00745
00746   /* Half Transfer Complete Interrupt management ******************************/
00747   if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT)))
00748   {
00749     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00750     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00751     {
00752       /* Disable the half transfer interrupt */
00753       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00754     }
00755     /* Clear the half transfer complete flag */
00756     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
00757
00758     /* DMA peripheral state is not updated in Half Transfer */
00759     /* but in Transfer Complete case */
00760
00761     if (hdma->XferHalfCpltCallback != NULL)
00762     {
00763       /* Half transfer callback */
00764       hdma->XferHalfCpltCallback(hdma);
00765     }
00766   }
00767   /* Transfer Complete Interrupt management ***********************************/
00768   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU))))
00769            && (0U != (source_it & DMA_IT_TC)))
00770   {
00771     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00772     {
00773       /* Disable the transfer complete and error interrupt */
00774       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
00775
00776       /* Change the DMA state */
00777       hdma->State = HAL_DMA_STATE_READY;
00778     }
00779     /* Clear the transfer complete flag */
00780     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
00781
00782     /* Process Unlocked */
00783     __HAL_UNLOCK(hdma);
00784
00785     if (hdma->XferCpltCallback != NULL)
00786     {
00787       /* Transfer complete callback */
00788       hdma->XferCpltCallback(hdma);
00789     }
00790   }
00791   /* Transfer Error Interrupt management **************************************/
00792   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))
00793            && (0U != (source_it & DMA_IT_TE)))
00794   {
00795     /* When a DMA transfer error occurs */
00796     /* A hardware clear of its EN bits is performed */
00797     /* Disable ALL DMA IT */
00798     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00799
00800     /* Clear all flags */
00801     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
00802
00803     /* Update error code */
00804     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00805
00806     /* Change the DMA state */
00807     hdma->State = HAL_DMA_STATE_READY;
00808
00809     /* Process Unlocked */
00810     __HAL_UNLOCK(hdma);
00811
00812     if (hdma->XferErrorCallback != NULL)
00813     {
00814       /* Transfer error callback */
00815       hdma->XferErrorCallback(hdma);
00816     }
00817   }
00818   else
00819   {
00820     /* Nothing To Do */
00821   }
00822   return;
00823 }
00824
00825 /**
00826   * @brief  Register callbacks
00827   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
00828   *                               the configuration information for the specified DMA Channel.
00829   * @param  CallbackID           User Callback identifier
00830   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00831   * @param  pCallback            pointer to private callbacsk function which has pointer to
00832   *                               a DMA_HandleTypeDef structure as parameter.
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
00836 {
00837   HAL_StatusTypeDef status = HAL_OK;
00838
00839   /* Process locked */
00840   __HAL_LOCK(hdma);
00841
00842   if (HAL_DMA_STATE_READY == hdma->State)
00843   {
00844     switch (CallbackID)
00845     {
00846       case  HAL_DMA_XFER_CPLT_CB_ID:
00847         hdma->XferCpltCallback = pCallback;
00848         break;
00849
00850       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00851         hdma->XferHalfCpltCallback = pCallback;
00852         break;
00853
00854       case  HAL_DMA_XFER_ERROR_CB_ID:
00855         hdma->XferErrorCallback = pCallback;
00856         break;
00857
00858       case  HAL_DMA_XFER_ABORT_CB_ID:
00859         hdma->XferAbortCallback = pCallback;
00860         break;
00861
00862       default:
00863         status = HAL_ERROR;
00864         break;
00865     }
00866   }
00867   else
00868   {
00869     status = HAL_ERROR;
00870   }
00871
00872   /* Release Lock */
00873   __HAL_UNLOCK(hdma);
00874
00875   return status;
00876 }
00877
00878 /**
00879   * @brief  UnRegister callbacks
00880   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
00881   *                               the configuration information for the specified DMA Channel.
00882   * @param  CallbackID           User Callback identifier
00883   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00884   * @retval HAL status
00885   */
00886 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00887 {
00888   HAL_StatusTypeDef status = HAL_OK;
00889
00890   /* Process locked */
00891   __HAL_LOCK(hdma);
00892
00893   if (HAL_DMA_STATE_READY == hdma->State)
00894   {
00895     switch (CallbackID)
00896     {
00897       case  HAL_DMA_XFER_CPLT_CB_ID:
00898         hdma->XferCpltCallback = NULL;
00899         break;
00900
00901       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00902         hdma->XferHalfCpltCallback = NULL;
00903         break;
00904
00905       case  HAL_DMA_XFER_ERROR_CB_ID:
00906         hdma->XferErrorCallback = NULL;
00907         break;
00908
00909       case  HAL_DMA_XFER_ABORT_CB_ID:
00910         hdma->XferAbortCallback = NULL;
00911         break;
00912
00913       case   HAL_DMA_XFER_ALL_CB_ID:
00914         hdma->XferCpltCallback = NULL;
00915         hdma->XferHalfCpltCallback = NULL;
00916         hdma->XferErrorCallback = NULL;
00917         hdma->XferAbortCallback = NULL;
00918         break;
00919
00920       default:
00921         status = HAL_ERROR;
00922         break;
00923     }
00924   }
00925   else
00926   {
00927     status = HAL_ERROR;
00928   }
00929
00930   /* Release Lock */
00931   __HAL_UNLOCK(hdma);
00932
00933   return status;
00934 }
00935
00936 /**
00937   * @}
00938   */
00939
00940
00941
00942 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
00943   *  @brief    Peripheral State and Errors functions
00944   *
00945 @verbatim
00946  ===============================================================================
00947             ##### Peripheral State and Errors functions #####
00948  ===============================================================================
00949     [..]
00950     This subsection provides functions allowing to
00951       (+) Check the DMA state
00952       (+) Get error code
00953
00954 @endverbatim
00955   * @{
00956   */
00957
00958 /**
00959   * @brief  Return the DMA hande state.
00960   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00961   *               the configuration information for the specified DMA Channel.
00962   * @retval HAL state
00963   */
00964 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00965 {
00966   /* Return DMA handle state */
00967   return hdma->State;
00968 }
00969
00970 /**
00971   * @brief  Return the DMA error code.
00972   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
00973   *              the configuration information for the specified DMA Channel.
00974   * @retval DMA Error Code
00975   */
00976 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00977 {
00978   return hdma->ErrorCode;
00979 }
00980
00981 /**
00982   * @}
00983   */
00984
00985 /**
00986   * @}
00987   */
00988
00989 /** @addtogroup DMA_Private_Functions
00990   * @{
00991   */
00992
00993 /**
00994   * @brief  Sets the DMA Transfer parameter.
00995   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
00996   *                     the configuration information for the specified DMA Channel.
00997   * @param  SrcAddress The source memory Buffer address
00998   * @param  DstAddress The destination memory Buffer address
00999   * @param  DataLength The length of data to be transferred from source to destination
01000   * @retval HAL status
01001   */
01002 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
01003 {
01004   /* Clear the DMAMUX synchro overrun flag */
01005   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
01006
01007   if (hdma->DMAmuxRequestGen != 0U)
01008   {
01009     /* Clear the DMAMUX request generator overrun flag */
01010     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
01011   }
01012
01013   /* Clear all flags */
01014   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
01015
01016   /* Configure DMA Channel data length */
01017   hdma->Instance->CNDTR = DataLength;
01018
01019   /* Memory to Peripheral */
01020   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01021   {
01022     /* Configure DMA Channel destination address */
01023     hdma->Instance->CPAR = DstAddress;
01024
01025     /* Configure DMA Channel source address */
01026     hdma->Instance->CMAR = SrcAddress;
01027   }
01028   /* Peripheral to Memory */
01029   else
01030   {
01031     /* Configure DMA Channel source address */
01032     hdma->Instance->CPAR = SrcAddress;
01033
01034     /* Configure DMA Channel destination address */
01035     hdma->Instance->CMAR = DstAddress;
01036   }
01037 }
01038
01039 /**
01040   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
01041   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
01042   *                     the configuration information for the specified DMA Stream.
01043   * @retval None
01044   */
01045 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
01046 {
01047   uint32_t dmamux_base_addr;
01048   uint32_t channel_number;
01049   DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
01050
01051   /* check if instance is not outside the DMA channel range */
01052   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
01053   {
01054     /* DMA1 */
01055     DMAMUX1_ChannelBase = DMAMUX1_Channel0;
01056   }
01057   else
01058   {
01059     /* DMA2 */
01060 #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx)
01061     DMAMUX1_ChannelBase = DMAMUX1_Channel8;
01062 #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
01063     DMAMUX1_ChannelBase = DMAMUX1_Channel6;
01064 #else
01065     DMAMUX1_ChannelBase = DMAMUX1_Channel7;
01066 #endif /* STM32G4x1xx) */
01067   }
01068   dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
01069   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
01070   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
01071   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
01072   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
01073 }
01074
01075 /**
01076   * @brief  Updates the DMA handle with the DMAMUX  request generator params
01077   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
01078   *                     the configuration information for the specified DMA Channel.
01079   * @retval None
01080   */
01081
01082 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
01083 {
01084   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
01085
01086   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
01087   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
01088
01089   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
01090
01091   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
01092 }
01093
01094 /**
01095   * @}
01096   */
01097
01098 /**
01099   * @}
01100   */
01101
01102 #endif /* HAL_DMA_MODULE_ENABLED */
01103 /**
01104   * @}
01105   */
01106
01107 /**
01108   * @}
01109   */
01110
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_dma.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_HAL_DMA_H
00021 #define __STM32G4xx_HAL_DMA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup DMA
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup DMA_Exported_Types DMA Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  DMA Configuration Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
00049                                            This parameter can be a value of @ref DMA_request */
00050
00051   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00052                                            from memory to memory or from peripheral to memory.
00053                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00054
00055   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00056                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00057
00058   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00059                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00060
00061   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00062                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00063
00064   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00065                                            This parameter can be a value of @ref DMA_Memory_data_size */
00066
00067   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00068                                            This parameter can be a value of @ref DMA_mode
00069                                            @note The circular buffer mode cannot be used if the memory-to-memory
00070                                                  data transfer is configured on the selected Channel */
00071
00072   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
00073                                            This parameter can be a value of @ref DMA_Priority_level */
00074 } DMA_InitTypeDef;
00075
00076 /**
00077   * @brief  HAL DMA State structures definition
00078   */
00079 typedef enum
00080 {
00081   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
00082   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
00083   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
00084   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                     */
00085 } HAL_DMA_StateTypeDef;
00086
00087 /**
00088   * @brief  HAL DMA Error Code structure definition
00089   */
00090 typedef enum
00091 {
00092   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00093   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
00094 } HAL_DMA_LevelCompleteTypeDef;
00095
00096
00097 /**
00098   * @brief  HAL DMA Callback ID structure definition
00099   */
00100 typedef enum
00101 {
00102   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00103   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
00104   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
00105   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
00106   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
00107
00108 } HAL_DMA_CallbackIDTypeDef;
00109
00110 /**
00111   * @brief  DMA handle Structure definition
00112   */
00113 typedef struct __DMA_HandleTypeDef
00114 {
00115   DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
00116
00117   DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
00118
00119   HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
00120
00121   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
00122
00123   void                  *Parent;                                                     /*!< Parent object state                  */
00124
00125   void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);                       /*!< DMA transfer complete callback       */
00126
00127   void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);                   /*!< DMA Half transfer complete callback  */
00128
00129   void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer error callback          */
00130
00131   void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer abort callback          */
00132
00133   __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
00134
00135   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
00136
00137   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
00138
00139   DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                   /*!< Register base address                */
00140
00141   DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                             /*!< DMAMUX Channels Status Base Address  */
00142
00143   uint32_t                         DMAmuxChannelStatusMask;                          /*!< DMAMUX Channel Status Mask           */
00144
00145   DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                /*!< DMAMUX request generator Base Address */
00146
00147   DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                          /*!< DMAMUX request generator Address     */
00148
00149   uint32_t                         DMAmuxRequestGenStatusMask;                       /*!< DMAMUX request generator Status mask */
00150
00151 } DMA_HandleTypeDef;
00152 /**
00153   * @}
00154   */
00155
00156 /* Exported constants --------------------------------------------------------*/
00157
00158 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00159   * @{
00160   */
00161
00162 /** @defgroup DMA_Error_Code DMA Error Code
00163   * @{
00164   */
00165 #define HAL_DMA_ERROR_NONE             0x00000000U    /*!< No error                              */
00166 #define HAL_DMA_ERROR_TE               0x00000001U    /*!< Transfer error                        */
00167 #define HAL_DMA_ERROR_NO_XFER          0x00000004U    /*!< Abort requested with no Xfer ongoing  */
00168 #define HAL_DMA_ERROR_TIMEOUT          0x00000020U    /*!< Timeout error                         */
00169 #define HAL_DMA_ERROR_NOT_SUPPORTED    0x00000100U    /*!< Not supported mode                    */
00170 #define HAL_DMA_ERROR_SYNC             0x00000200U    /*!< DMAMUX sync overrun  error              */
00171 #define HAL_DMA_ERROR_REQGEN           0x00000400U    /*!< DMAMUX request generator overrun  error */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup DMA_request DMA request
00177   * @{
00178   */
00179 #define DMA_REQUEST_MEM2MEM            0U  /*!< memory to memory transfer   */
00180
00181 #define DMA_REQUEST_GENERATOR0         1U
00182 #define DMA_REQUEST_GENERATOR1         2U
00183 #define DMA_REQUEST_GENERATOR2         3U
00184 #define DMA_REQUEST_GENERATOR3         4U
00185
00186 #define DMA_REQUEST_ADC1               5U
00187
00188 #define DMA_REQUEST_DAC1_CHANNEL1      6U
00189 #define DMA_REQUEST_DAC1_CHANNEL2      7U
00190
00191 #define DMA_REQUEST_TIM6_UP            8U
00192 #define DMA_REQUEST_TIM7_UP            9U
00193
00194 #define DMA_REQUEST_SPI1_RX           10U
00195 #define DMA_REQUEST_SPI1_TX           11U
00196 #define DMA_REQUEST_SPI2_RX           12U
00197 #define DMA_REQUEST_SPI2_TX           13U
00198 #define DMA_REQUEST_SPI3_RX           14U
00199 #define DMA_REQUEST_SPI3_TX           15U
00200
00201 #define DMA_REQUEST_I2C1_RX           16U
00202 #define DMA_REQUEST_I2C1_TX           17U
00203 #define DMA_REQUEST_I2C2_RX           18U
00204 #define DMA_REQUEST_I2C2_TX           19U
00205 #define DMA_REQUEST_I2C3_RX           20U
00206 #define DMA_REQUEST_I2C3_TX           21U
00207 #if defined (I2C4)
00208 #define DMA_REQUEST_I2C4_RX           22U
00209 #define DMA_REQUEST_I2C4_TX           23U
00210 #endif /* I2C4 */
00211
00212 #define DMA_REQUEST_USART1_RX         24U
00213 #define DMA_REQUEST_USART1_TX         25U
00214 #define DMA_REQUEST_USART2_RX         26U
00215 #define DMA_REQUEST_USART2_TX         27U
00216 #define DMA_REQUEST_USART3_RX         28U
00217 #define DMA_REQUEST_USART3_TX         29U
00218
00219 #define DMA_REQUEST_UART4_RX          30U
00220 #define DMA_REQUEST_UART4_TX          31U
00221 #if defined (UART5)
00222 #define DMA_REQUEST_UART5_RX          32U
00223 #define DMA_REQUEST_UART5_TX          33U
00224 #endif /* UART5 */
00225
00226 #define DMA_REQUEST_LPUART1_RX        34U
00227 #define DMA_REQUEST_LPUART1_TX        35U
00228
00229 #define DMA_REQUEST_ADC2              36U
00230 #if defined (ADC3)
00231 #define DMA_REQUEST_ADC3              37U
00232 #endif /* ADC3 */
00233 #if defined (ADC4)
00234 #define DMA_REQUEST_ADC4              38U
00235 #endif /* ADC4 */
00236 #if defined (ADC5)
00237 #define DMA_REQUEST_ADC5              39U
00238 #endif /* ADC5 */
00239
00240 #if defined (QUADSPI)
00241 #define DMA_REQUEST_QUADSPI           40U
00242 #endif /* QUADSPI */
00243
00244 #if defined (DAC2)
00245 #define DMA_REQUEST_DAC2_CHANNEL1     41U
00246 #endif /* DAC2 */
00247
00248 #define DMA_REQUEST_TIM1_CH1          42U
00249 #define DMA_REQUEST_TIM1_CH2          43U
00250 #define DMA_REQUEST_TIM1_CH3          44U
00251 #define DMA_REQUEST_TIM1_CH4          45U
00252 #define DMA_REQUEST_TIM1_UP           46U
00253 #define DMA_REQUEST_TIM1_TRIG         47U
00254 #define DMA_REQUEST_TIM1_COM          48U
00255
00256 #define DMA_REQUEST_TIM8_CH1          49U
00257 #define DMA_REQUEST_TIM8_CH2          50U
00258 #define DMA_REQUEST_TIM8_CH3          51U
00259 #define DMA_REQUEST_TIM8_CH4          52U
00260 #define DMA_REQUEST_TIM8_UP           53U
00261 #define DMA_REQUEST_TIM8_TRIG         54U
00262 #define DMA_REQUEST_TIM8_COM          55U
00263
00264 #define DMA_REQUEST_TIM2_CH1          56U
00265 #define DMA_REQUEST_TIM2_CH2          57U
00266 #define DMA_REQUEST_TIM2_CH3          58U
00267 #define DMA_REQUEST_TIM2_CH4          59U
00268 #define DMA_REQUEST_TIM2_UP           60U
00269
00270 #define DMA_REQUEST_TIM3_CH1          61U
00271 #define DMA_REQUEST_TIM3_CH2          62U
00272 #define DMA_REQUEST_TIM3_CH3          63U
00273 #define DMA_REQUEST_TIM3_CH4          64U
00274 #define DMA_REQUEST_TIM3_UP           65U
00275 #define DMA_REQUEST_TIM3_TRIG         66U
00276
00277 #define DMA_REQUEST_TIM4_CH1          67U
00278 #define DMA_REQUEST_TIM4_CH2          68U
00279 #define DMA_REQUEST_TIM4_CH3          69U
00280 #define DMA_REQUEST_TIM4_CH4          70U
00281 #define DMA_REQUEST_TIM4_UP           71U
00282
00283 #if defined (TIM5)
00284 #define DMA_REQUEST_TIM5_CH1          72U
00285 #define DMA_REQUEST_TIM5_CH2          73U
00286 #define DMA_REQUEST_TIM5_CH3          74U
00287 #define DMA_REQUEST_TIM5_CH4          75U
00288 #define DMA_REQUEST_TIM5_UP           76U
00289 #define DMA_REQUEST_TIM5_TRIG         77U
00290 #endif /* TIM5 */
00291
00292 #define DMA_REQUEST_TIM15_CH1         78U
00293 #define DMA_REQUEST_TIM15_UP          79U
00294 #define DMA_REQUEST_TIM15_TRIG        80U
00295 #define DMA_REQUEST_TIM15_COM         81U
00296
00297 #define DMA_REQUEST_TIM16_CH1         82U
00298 #define DMA_REQUEST_TIM16_UP          83U
00299 #define DMA_REQUEST_TIM17_CH1         84U
00300 #define DMA_REQUEST_TIM17_UP          85U
00301
00302 #if defined (TIM20)
00303 #define DMA_REQUEST_TIM20_CH1         86U
00304 #define DMA_REQUEST_TIM20_CH2         87U
00305 #define DMA_REQUEST_TIM20_CH3         88U
00306 #define DMA_REQUEST_TIM20_CH4         89U
00307 #define DMA_REQUEST_TIM20_UP          90U
00308 #endif /* TIM20 */
00309
00310 #define DMA_REQUEST_AES_IN            91U
00311 #define DMA_REQUEST_AES_OUT           92U
00312
00313 #if defined (TIM20)
00314 #define DMA_REQUEST_TIM20_TRIG        93U
00315 #define DMA_REQUEST_TIM20_COM         94U
00316 #endif /* TIM20 */
00317
00318 #if defined (HRTIM1)
00319 #define DMA_REQUEST_HRTIM1_M          95U
00320 #define DMA_REQUEST_HRTIM1_A          96U
00321 #define DMA_REQUEST_HRTIM1_B          97U
00322 #define DMA_REQUEST_HRTIM1_C          98U
00323 #define DMA_REQUEST_HRTIM1_D          99U
00324 #define DMA_REQUEST_HRTIM1_E          100U
00325 #define DMA_REQUEST_HRTIM1_F          101U
00326 #endif /* HRTIM1 */
00327
00328 #define DMA_REQUEST_DAC3_CHANNEL1     102U
00329 #define DMA_REQUEST_DAC3_CHANNEL2     103U
00330 #if defined (DAC4)
00331 #define DMA_REQUEST_DAC4_CHANNEL1     104U
00332 #define DMA_REQUEST_DAC4_CHANNEL2     105U
00333 #endif /* DAC4 */
00334
00335 #if defined (SPI4)
00336 #define DMA_REQUEST_SPI4_RX           106U
00337 #define DMA_REQUEST_SPI4_TX           107U
00338 #endif /* SPI4 */
00339
00340 #define DMA_REQUEST_SAI1_A            108U
00341 #define DMA_REQUEST_SAI1_B            109U
00342
00343 #define DMA_REQUEST_FMAC_READ         110U
00344 #define DMA_REQUEST_FMAC_WRITE        111U
00345
00346 #define DMA_REQUEST_CORDIC_READ       112U
00347 #define DMA_REQUEST_CORDIC_WRITE      113U
00348
00349 #define DMA_REQUEST_UCPD1_RX         114U
00350 #define DMA_REQUEST_UCPD1_TX         115U
00351
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00357   * @{
00358   */
00359 #define DMA_PERIPH_TO_MEMORY         0x00000000U                   /*!< Peripheral to memory direction */
00360 #define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR                   /*!< Memory to peripheral direction */
00361 #define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM               /*!< Memory to memory direction     */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00367   * @{
00368   */
00369 #define DMA_PINC_ENABLE        DMA_CCR_PINC              /*!< Peripheral increment mode Enable */
00370 #define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00376   * @{
00377   */
00378 #define DMA_MINC_ENABLE         DMA_CCR_MINC              /*!< Memory increment mode Enable  */
00379 #define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00385   * @{
00386   */
00387 #define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment : Byte     */
00388 #define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0              /*!< Peripheral data alignment : HalfWord */
00389 #define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1              /*!< Peripheral data alignment : Word     */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup DMA_Memory_data_size DMA Memory data size
00395   * @{
00396   */
00397 #define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment : Byte     */
00398 #define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0              /*!< Memory data alignment : HalfWord */
00399 #define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1              /*!< Memory data alignment : Word     */
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup DMA_mode DMA mode
00405   * @{
00406   */
00407 #define DMA_NORMAL         0x00000000U       /*!< Normal mode                  */
00408 #define DMA_CIRCULAR       DMA_CCR_CIRC      /*!< Circular mode                */
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup DMA_Priority_level DMA Priority level
00414   * @{
00415   */
00416 #define DMA_PRIORITY_LOW              0x00000000U              /*!< Priority level : Low       */
00417 #define DMA_PRIORITY_MEDIUM           DMA_CCR_PL_0             /*!< Priority level : Medium    */
00418 #define DMA_PRIORITY_HIGH             DMA_CCR_PL_1             /*!< Priority level : High      */
00419 #define DMA_PRIORITY_VERY_HIGH        DMA_CCR_PL               /*!< Priority level : Very_High */
00420 /**
00421   * @}
00422   */
00423
00424
00425 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00426   * @{
00427   */
00428 #define DMA_IT_TC                     DMA_CCR_TCIE
00429 #define DMA_IT_HT                     DMA_CCR_HTIE
00430 #define DMA_IT_TE                     DMA_CCR_TEIE
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup DMA_flag_definitions DMA flag definitions
00436   * @{
00437   */
00438 #define DMA_FLAG_GL1                      0x00000001U
00439 #define DMA_FLAG_TC1                      0x00000002U
00440 #define DMA_FLAG_HT1                      0x00000004U
00441 #define DMA_FLAG_TE1                      0x00000008U
00442 #define DMA_FLAG_GL2                      0x00000010U
00443 #define DMA_FLAG_TC2                      0x00000020U
00444 #define DMA_FLAG_HT2                      0x00000040U
00445 #define DMA_FLAG_TE2                      0x00000080U
00446 #define DMA_FLAG_GL3                      0x00000100U
00447 #define DMA_FLAG_TC3                      0x00000200U
00448 #define DMA_FLAG_HT3                      0x00000400U
00449 #define DMA_FLAG_TE3                      0x00000800U
00450 #define DMA_FLAG_GL4                      0x00001000U
00451 #define DMA_FLAG_TC4                      0x00002000U
00452 #define DMA_FLAG_HT4                      0x00004000U
00453 #define DMA_FLAG_TE4                      0x00008000U
00454 #define DMA_FLAG_GL5                      0x00010000U
00455 #define DMA_FLAG_TC5                      0x00020000U
00456 #define DMA_FLAG_HT5                      0x00040000U
00457 #define DMA_FLAG_TE5                      0x00080000U
00458 #define DMA_FLAG_GL6                      0x00100000U
00459 #define DMA_FLAG_TC6                      0x00200000U
00460 #define DMA_FLAG_HT6                      0x00400000U
00461 #define DMA_FLAG_TE6                      0x00800000U
00462 #if defined (DMA1_Channel7)
00463 #define DMA_FLAG_GL7                      0x01000000U
00464 #define DMA_FLAG_TC7                      0x02000000U
00465 #define DMA_FLAG_HT7                      0x04000000U
00466 #define DMA_FLAG_TE7                      0x08000000U
00467 #endif /* DMA1_Channel7 */
00468 #if defined (DMA1_Channel8)
00469 #define DMA_FLAG_GL8                      0x10000000U
00470 #define DMA_FLAG_TC8                      0x20000000U
00471 #define DMA_FLAG_HT8                      0x40000000U
00472 #define DMA_FLAG_TE8                      0x80000000U
00473 #endif /* DMA1_Channel8 */
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Exported macros -----------------------------------------------------------*/
00483 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00484   * @{
00485   */
00486
00487 /** @brief  Reset DMA handle state.
00488   * @param  __HANDLE__ DMA handle
00489   * @retval None
00490   */
00491 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00492
00493 /**
00494   * @brief  Enable the specified DMA Channel.
00495   * @param  __HANDLE__ DMA handle
00496   * @retval None
00497   */
00498 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
00499
00500 /**
00501   * @brief  Disable the specified DMA Channel.
00502   * @param  __HANDLE__ DMA handle
00503   * @retval None
00504   */
00505 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
00506
00507
00508 /* Interrupt & Flag management */
00509
00510 /**
00511   * @brief  Return the current DMA Channel transfer complete flag.
00512   * @param  __HANDLE__ DMA handle
00513   * @retval The specified transfer complete flag index.
00514   */
00515
00516 #if defined (DMA1_Channel8)
00517 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00518   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00519    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00520    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00521    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00522    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00523    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00524    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00525    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00526    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00527    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00528    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00529    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
00530    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
00531    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
00532    DMA_FLAG_TC8)
00533 #elif defined (DMA1_Channel6)
00534 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00535   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00536    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00537    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00538    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00539    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00540    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00541    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00542    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00543    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00544    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00545    DMA_FLAG_TC6)
00546 #endif /* DMA1_Channel8 */
00547
00548 /**
00549   * @brief  Return the current DMA Channel half transfer complete flag.
00550   * @param  __HANDLE__ DMA handle
00551   * @retval The specified half transfer complete flag index.
00552   */
00553 #if defined (DMA1_Channel8)
00554 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00555   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00556    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00557    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00558    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00559    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00560    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00561    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00562    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00563    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00564    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00565    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00566    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
00567    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
00568    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
00569    DMA_FLAG_HT8)
00570 #elif defined (DMA1_Channel6)
00571 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00572   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00573    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00574    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00575    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00576    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00577    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00578    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00579    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00580    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00581    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00582    DMA_FLAG_HT6)
00583 #endif /* DMA1_Channel8 */
00584
00585 /**
00586   * @brief  Return the current DMA Channel transfer error flag.
00587   * @param  __HANDLE__ DMA handle
00588   * @retval The specified transfer error flag index.
00589   */
00590 #if defined (DMA1_Channel8)
00591 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00592   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00593    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00594    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00595    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00596    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00597    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00598    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00599    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00600    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00601    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00602    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00603    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
00604    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
00605    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
00606    DMA_FLAG_TE8)
00607 #elif defined (DMA1_Channel6)
00608 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00609   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00610    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00611    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00612    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00613    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00614    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00615    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00616    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00617    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00618    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00619    DMA_FLAG_TE6)
00620 #endif /* DMA1_Channel8 */
00621
00622 /**
00623   * @brief  Return the current DMA Channel Global interrupt flag.
00624   * @param  __HANDLE__ DMA handle
00625   * @retval The specified transfer error flag index.
00626   */
00627 #if defined (DMA1_Channel8)
00628 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00629   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00630    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
00631    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00632    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
00633    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00634    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
00635    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00636    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
00637    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00638    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
00639    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
00640    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
00641    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
00642    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
00643    DMA_ISR_GIF8)
00644 #elif defined (DMA1_Channel6)
00645 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00646   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00647    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
00648    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00649    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
00650    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00651    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
00652    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00653    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
00654    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00655    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
00656    DMA_ISR_GIF6)
00657 #endif /* DMA1_Channel8 */
00658
00659 /**
00660   * @brief  Get the DMA Channel pending flags.
00661   * @param  __HANDLE__ DMA handle
00662   * @param  __FLAG__ Get the specified flag.
00663   *          This parameter can be any combination of the following values:
00664   *            @arg DMA_FLAG_TCx  Transfer complete flag
00665   *            @arg DMA_FLAG_HTx  Half transfer complete flag
00666   *            @arg DMA_FLAG_TEx  Transfer error flag
00667   *            @arg DMA_FLAG_GLx  Global interrupt flag
00668   *         Where x can be from 1 to 8 to select the DMA Channel x flag.
00669   * @retval The state of FLAG (SET or RESET).
00670   */
00671 #if defined (DMA1_Channel8)
00672 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
00673                                                   (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00674 #elif defined (DMA1_Channel6)
00675 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
00676                                                   (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00677 #endif /* DMA1_Channel8 */
00678
00679 /**
00680   * @brief  Clear the DMA Channel pending flags.
00681   * @param  __HANDLE__ DMA handle
00682   * @param  __FLAG__ specifies the flag to clear.
00683   *          This parameter can be any combination of the following values:
00684   *            @arg DMA_FLAG_TCx  Transfer complete flag
00685   *            @arg DMA_FLAG_HTx  Half transfer complete flag
00686   *            @arg DMA_FLAG_TEx  Transfer error flag
00687   *            @arg DMA_FLAG_GLx  Global interrupt flag
00688   *         Where x can be from 1 to 8 to select the DMA Channel x flag.
00689   * @retval None
00690   */
00691 #if defined (DMA1_Channel8)
00692 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
00693                                                     (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
00694 #else
00695 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
00696                                                     (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
00697 #endif /* DMA1_Channel8 */
00698
00699 /**
00700   * @brief  Enable the specified DMA Channel interrupts.
00701   * @param  __HANDLE__ DMA handle
00702   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00703   *          This parameter can be any combination of the following values:
00704   *            @arg DMA_IT_TC  Transfer complete interrupt mask
00705   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
00706   *            @arg DMA_IT_TE  Transfer error interrupt mask
00707   * @retval None
00708   */
00709 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00710
00711 /**
00712   * @brief  Disable the specified DMA Channel interrupts.
00713   * @param  __HANDLE__ DMA handle
00714   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00715   *          This parameter can be any combination of the following values:
00716   *            @arg DMA_IT_TC  Transfer complete interrupt mask
00717   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
00718   *            @arg DMA_IT_TE  Transfer error interrupt mask
00719   * @retval None
00720   */
00721 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00722
00723 /**
00724   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
00725   * @param  __HANDLE__ DMA handle
00726   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
00727   *          This parameter can be one of the following values:
00728   *            @arg DMA_IT_TC  Transfer complete interrupt mask
00729   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
00730   *            @arg DMA_IT_TE  Transfer error interrupt mask
00731   * @retval The state of DMA_IT (SET or RESET).
00732   */
00733 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00734
00735 /**
00736   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
00737   * @param  __HANDLE__ DMA handle
00738   * @retval The number of remaining data units in the current DMA Channel transfer.
00739   */
00740 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00741
00742 /**
00743   * @}
00744   */
00745
00746 /* Include DMA HAL Extension module */
00747 #include "stm32g4xx_hal_dma_ex.h"
00748
00749 /* Exported functions --------------------------------------------------------*/
00750
00751 /** @addtogroup DMA_Exported_Functions
00752   * @{
00753   */
00754
00755 /** @addtogroup DMA_Exported_Functions_Group1
00756   * @{
00757   */
00758 /* Initialization and de-initialization functions *****************************/
00759 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00760 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00761 /**
00762   * @}
00763   */
00764
00765 /** @addtogroup DMA_Exported_Functions_Group2
00766   * @{
00767   */
00768 /* IO operation functions *****************************************************/
00769 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00770 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
00771                                    uint32_t DataLength);
00772 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00773 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00774 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
00775                                           uint32_t Timeout);
00776 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00777 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
00778 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00779
00780 /**
00781   * @}
00782   */
00783
00784 /** @addtogroup DMA_Exported_Functions_Group3
00785   * @{
00786   */
00787 /* Peripheral State and Error functions ***************************************/
00788 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00789 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00790 /**
00791   * @}
00792   */
00793
00794 /**
00795   * @}
00796   */
00797
00798 /* Private macros ------------------------------------------------------------*/
00799 /** @defgroup DMA_Private_Macros DMA Private Macros
00800   * @{
00801   */
00802
00803 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00804                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00805                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00806
00807 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
00808
00809 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00810                                             ((STATE) == DMA_PINC_DISABLE))
00811
00812 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00813                                         ((STATE) == DMA_MINC_DISABLE))
00814
00815 #define IS_DMA_ALL_REQUEST(REQUEST)    ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
00816
00817 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00818                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00819                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00820
00821 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00822                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00823                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00824
00825 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00826                            ((MODE) == DMA_CIRCULAR))
00827
00828 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00829                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00830                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00831                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00832
00833 /**
00834   * @}
00835   */
00836
00837 /* Private functions ---------------------------------------------------------*/
00838
00839 /**
00840   * @}
00841   */
00842
00843 /**
00844   * @}
00845   */
00846
00847 #ifdef __cplusplus
00848 }
00849 #endif
00850
00851 #endif /* __STM32G4xx_HAL_DMA_H */
00852
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_dma_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DMA Extension HAL module driver
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the DMA Extension peripheral:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                         ##### How to use this driver #####
00024   ==============================================================================
00025   [..]
00026   The DMA Extension HAL driver can be used as follows:
00027
00028    (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00029    (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00030        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00031        to respectively enable/disable the request generator.
00032
00033    (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
00034        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
00035        As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
00036        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
00037       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
00038
00039   @endverbatim
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32g4xx_hal.h"
00044
00045 /** @addtogroup STM32G4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup DMAEx DMAEx
00050   * @brief DMA Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_DMA_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /* Private macro -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private Constants ---------------------------------------------------------*/
00061 /* Private function prototypes -----------------------------------------------*/
00062 /* Private functions ---------------------------------------------------------*/
00063
00064
00065 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00066   * @{
00067   */
00068
00069 /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
00070   *  @brief   Extended features functions
00071   *
00072 @verbatim
00073  ===============================================================================
00074                 #####  Extended features functions  #####
00075  ===============================================================================
00076     [..]  This section provides functions allowing to:
00077
00078     (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00079     (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00080        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00081        to respectively enable/disable the request generator.
00082
00083 @endverbatim
00084   * @{
00085   */
00086
00087
00088 /**
00089   * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
00090   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00091   *                     the configuration information for the specified DMA channel.
00092   * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
00093   * @retval HAL status
00094   */
00095 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
00096 {
00097   /* Check the parameters */
00098   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00099
00100   assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00101
00102   assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
00103   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
00104   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
00105   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
00106
00107   /*Check if the DMA state is ready */
00108   if (hdma->State == HAL_DMA_STATE_READY)
00109   {
00110     /* Process Locked */
00111     __HAL_LOCK(hdma);
00112
00113     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
00114     MODIFY_REG(hdma->DMAmuxChannel->CCR, \
00115                (~DMAMUX_CxCR_DMAREQ_ID), \
00116                ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
00117                pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
00118                ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
00119
00120     /* Process UnLocked */
00121     __HAL_UNLOCK(hdma);
00122
00123     return HAL_OK;
00124   }
00125   else
00126   {
00127     /*DMA State not Ready*/
00128     return HAL_ERROR;
00129   }
00130 }
00131
00132 /**
00133   * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).
00134   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00135   *                     the configuration information for the specified DMA channel.
00136   * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
00137   *         contains the request generator parameters.
00138   *
00139   * @retval HAL status
00140   */
00141 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
00142                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00146
00147   assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00148
00149   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
00150   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
00151
00152   /* check if the DMA state is ready
00153      and DMA is using a DMAMUX request generator block
00154   */
00155   if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
00156   {
00157     /* Process Locked */
00158     __HAL_LOCK(hdma);
00159
00160     /* Set the request generator new parameters */
00161     hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
00162                                    ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) | \
00163                                    pRequestGeneratorConfig->Polarity;
00164     /* Process UnLocked */
00165     __HAL_UNLOCK(hdma);
00166
00167     return HAL_OK;
00168   }
00169   else
00170   {
00171     return HAL_ERROR;
00172   }
00173 }
00174
00175 /**
00176   * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).
00177   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00178   *                     the configuration information for the specified DMA channel.
00179   * @retval HAL status
00180   */
00181 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00182 {
00183   /* Check the parameters */
00184   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00185
00186   /* check if the DMA state is ready
00187      and DMA is using a DMAMUX request generator block
00188   */
00189   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
00190   {
00191
00192     /* Enable the request generator*/
00193     hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
00194
00195     return HAL_OK;
00196   }
00197   else
00198   {
00199     return HAL_ERROR;
00200   }
00201 }
00202
00203 /**
00204   * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).
00205   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00206   *                     the configuration information for the specified DMA channel.
00207   * @retval HAL status
00208   */
00209 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00210 {
00211   /* Check the parameters */
00212   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00213
00214   /* check if the DMA state is ready
00215      and DMA is using a DMAMUX request generator block
00216   */
00217   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
00218   {
00219
00220     /* Disable the request generator*/
00221     hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
00222
00223     return HAL_OK;
00224   }
00225   else
00226   {
00227     return HAL_ERROR;
00228   }
00229 }
00230
00231 /**
00232   * @brief  Handles DMAMUX interrupt request.
00233   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00234   *               the configuration information for the specified DMA channel.
00235   * @retval None
00236   */
00237 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
00238 {
00239   /* Check for DMAMUX Synchronization overrun */
00240   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00241   {
00242     /* Disable the synchro overrun interrupt */
00243     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00244
00245     /* Clear the DMAMUX synchro overrun flag */
00246     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00247
00248     /* Update error code */
00249     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00250
00251     if (hdma->XferErrorCallback != NULL)
00252     {
00253       /* Transfer error callback */
00254       hdma->XferErrorCallback(hdma);
00255     }
00256   }
00257
00258   if (hdma->DMAmuxRequestGen != 0)
00259   {
00260     /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
00261     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00262     {
00263       /* Disable the request gen overrun interrupt */
00264       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00265
00266       /* Clear the DMAMUX request generator overrun flag */
00267       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00268
00269       /* Update error code */
00270       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00271
00272       if (hdma->XferErrorCallback != NULL)
00273       {
00274         /* Transfer error callback */
00275         hdma->XferErrorCallback(hdma);
00276       }
00277     }
00278   }
00279 }
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 #endif /* HAL_DMA_MODULE_ENABLED */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_dma_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_dma_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_HAL_DMA_EX_H
00021 #define __STM32G4xx_HAL_DMA_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup DMAEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  HAL DMA Synchro definition
00045   */
00046
00047
00048 /**
00049   * @brief  HAL DMAMUX Synchronization configuration structure definition
00050   */
00051 typedef struct
00052 {
00053   uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
00054                               This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
00055
00056   uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
00057                               This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
00058
00059   FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
00060                                     This parameter can take the value ENABLE or DISABLE*/
00061
00062
00063   FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
00064                                        This parameter can take the value ENABLE or DISABLE */
00065
00066   uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
00067                                This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00068
00069
00070 } HAL_DMA_MuxSyncConfigTypeDef;
00071
00072
00073 /**
00074   * @brief  HAL DMAMUX request generator parameters structure definition
00075   */
00076 typedef struct
00077 {
00078   uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
00079                               This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
00080
00081   uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
00082                              This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
00083
00084   uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event
00085                                 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00086
00087 } HAL_DMA_MuxRequestGeneratorConfigTypeDef;
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
00099   * @{
00100   */
00101 #define HAL_DMAMUX1_SYNC_EXTI0                      0U     /*!<  Synchronization Signal is EXTI0  IT   */
00102 #define HAL_DMAMUX1_SYNC_EXTI1                      1U     /*!<  Synchronization Signal is EXTI1  IT   */
00103 #define HAL_DMAMUX1_SYNC_EXTI2                      2U     /*!<  Synchronization Signal is EXTI2  IT   */
00104 #define HAL_DMAMUX1_SYNC_EXTI3                      3U     /*!<  Synchronization Signal is EXTI3  IT   */
00105 #define HAL_DMAMUX1_SYNC_EXTI4                      4U     /*!<  Synchronization Signal is EXTI4  IT   */
00106 #define HAL_DMAMUX1_SYNC_EXTI5                      5U     /*!<  Synchronization Signal is EXTI5  IT   */
00107 #define HAL_DMAMUX1_SYNC_EXTI6                      6U     /*!<  Synchronization Signal is EXTI6  IT   */
00108 #define HAL_DMAMUX1_SYNC_EXTI7                      7U     /*!<  Synchronization Signal is EXTI7  IT   */
00109 #define HAL_DMAMUX1_SYNC_EXTI8                      8U     /*!<  Synchronization Signal is EXTI8  IT   */
00110 #define HAL_DMAMUX1_SYNC_EXTI9                      9U     /*!<  Synchronization Signal is EXTI9  IT   */
00111 #define HAL_DMAMUX1_SYNC_EXTI10                    10U     /*!<  Synchronization Signal is EXTI10 IT   */
00112 #define HAL_DMAMUX1_SYNC_EXTI11                    11U     /*!<  Synchronization Signal is EXTI11 IT   */
00113 #define HAL_DMAMUX1_SYNC_EXTI12                    12U     /*!<  Synchronization Signal is EXTI12 IT   */
00114 #define HAL_DMAMUX1_SYNC_EXTI13                    13U     /*!<  Synchronization Signal is EXTI13 IT   */
00115 #define HAL_DMAMUX1_SYNC_EXTI14                    14U     /*!<  Synchronization Signal is EXTI14 IT   */
00116 #define HAL_DMAMUX1_SYNC_EXTI15                    15U     /*!<  Synchronization Signal is EXTI15 IT   */
00117 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT           16U     /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */
00118 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT           17U     /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */
00119 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT           18U     /*!<  Synchronization Signal is DMAMUX1 Channel2 Event  */
00120 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT           19U     /*!<  Synchronization Signal is DMAMUX1 Channel3 Event  */
00121 #define HAL_DMAMUX1_SYNC_LPTIM1_OUT                20U     /*!<  Synchronization Signal is LPTIM1 OUT */
00122
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
00128   * @{
00129   */
00130 #define HAL_DMAMUX_SYNC_NO_EVENT                               0U    /*!< block synchronization events        */
00131 #define HAL_DMAMUX_SYNC_RISING     ((uint32_t)DMAMUX_CxCR_SPOL_0)    /*!< synchronize with rising edge events */
00132 #define HAL_DMAMUX_SYNC_FALLING    ((uint32_t)DMAMUX_CxCR_SPOL_1)    /*!< synchronize with falling edge events */
00133 #define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL)  /*!< synchronize with rising and falling edge events */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
00140   * @{
00141   */
00142 #define HAL_DMAMUX1_REQ_GEN_EXTI0                0U        /*!< Request generator Signal is EXTI0 IT    */
00143 #define HAL_DMAMUX1_REQ_GEN_EXTI1                1U        /*!< Request generator Signal is EXTI1 IT    */
00144 #define HAL_DMAMUX1_REQ_GEN_EXTI2                2U        /*!< Request generator Signal is EXTI2 IT    */
00145 #define HAL_DMAMUX1_REQ_GEN_EXTI3                3U        /*!< Request generator Signal is EXTI3 IT    */
00146 #define HAL_DMAMUX1_REQ_GEN_EXTI4                4U        /*!< Request generator Signal is EXTI4 IT    */
00147 #define HAL_DMAMUX1_REQ_GEN_EXTI5                5U        /*!< Request generator Signal is EXTI5 IT    */
00148 #define HAL_DMAMUX1_REQ_GEN_EXTI6                6U        /*!< Request generator Signal is EXTI6 IT    */
00149 #define HAL_DMAMUX1_REQ_GEN_EXTI7                7U        /*!< Request generator Signal is EXTI7 IT    */
00150 #define HAL_DMAMUX1_REQ_GEN_EXTI8                8U        /*!< Request generator Signal is EXTI8 IT    */
00151 #define HAL_DMAMUX1_REQ_GEN_EXTI9                9U        /*!< Request generator Signal is EXTI9 IT    */
00152 #define HAL_DMAMUX1_REQ_GEN_EXTI10              10U        /*!< Request generator Signal is EXTI10 IT   */
00153 #define HAL_DMAMUX1_REQ_GEN_EXTI11              11U        /*!< Request generator Signal is EXTI11 IT   */
00154 #define HAL_DMAMUX1_REQ_GEN_EXTI12              12U        /*!< Request generator Signal is EXTI12 IT   */
00155 #define HAL_DMAMUX1_REQ_GEN_EXTI13              13U        /*!< Request generator Signal is EXTI13 IT   */
00156 #define HAL_DMAMUX1_REQ_GEN_EXTI14              14U        /*!< Request generator Signal is EXTI14 IT   */
00157 #define HAL_DMAMUX1_REQ_GEN_EXTI15              15U        /*!< Request generator Signal is EXTI15 IT   */
00158 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     16U        /*!< Request generator Signal is DMAMUX1 Channel0 Event */
00159 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     17U        /*!< Request generator Signal is DMAMUX1 Channel1 Event */
00160 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT     18U        /*!< Request generator Signal is DMAMUX1 Channel2 Event */
00161 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT     19U        /*!< Request generator Signal is DMAMUX1 Channel3 Event */
00162 #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          20U        /*!< Request generator Signal is LPTIM1 OUT  */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
00169   * @{
00170   */
00171 #define HAL_DMAMUX_REQ_GEN_NO_EVENT         0x00000000U           /*!< block request generator events        */
00172 #define HAL_DMAMUX_REQ_GEN_RISING           DMAMUX_RGxCR_GPOL_0   /*!< generate request on rising edge events */
00173 #define HAL_DMAMUX_REQ_GEN_FALLING          DMAMUX_RGxCR_GPOL_1   /*!< generate request on falling edge events */
00174 #define HAL_DMAMUX_REQ_GEN_RISING_FALLING   DMAMUX_RGxCR_GPOL     /*!< generate request on rising and falling edge events */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported macro ------------------------------------------------------------*/
00185
00186 /* Exported functions --------------------------------------------------------*/
00187 /** @addtogroup DMAEx_Exported_Functions
00188   * @{
00189   */
00190
00191 /* IO operation functions *****************************************************/
00192 /** @addtogroup DMAEx_Exported_Functions_Group1
00193   * @{
00194   */
00195
00196 /* ------------------------- REQUEST -----------------------------------------*/
00197 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
00198                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
00199 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00200 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00201 /* -------------------------------------------------------------------------- */
00202
00203 /* ------------------------- SYNCHRO -----------------------------------------*/
00204 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
00205 /* -------------------------------------------------------------------------- */
00206
00207 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
00208
00209 /**
00210   * @}
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /* Private macros ------------------------------------------------------------*/
00218 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros
00219   * @brief    DMAEx private macros
00220   * @{
00221   */
00222
00223 #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
00224
00225 #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00226
00227 #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
00228                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
00229                                            ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
00230                                            ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
00231
00232 #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
00233
00234 #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
00235                                      ((EVENT) == ENABLE))
00236
00237 #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
00238
00239 #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00240
00241 #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \
00242                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
00243                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
00244                                                   ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
00245
00246 /**
00247   * @}
00248   */
00249
00250
00251 /**
00252   * @}
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 #ifdef __cplusplus
00260 }
00261 #endif
00262
00263 #endif /* __STM32G4xx_HAL_DMA_EX_H */
00264
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_exti.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_exti.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
00008   *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                     ##### EXTI Peripheral features #####
00026   ==============================================================================
00027   [..]
00028     (+) Each Exti line can be configured within this driver.
00029
00030     (+) Exti line can be configured in 3 different modes
00031         (++) Interrupt
00032         (++) Event
00033         (++) Both of them
00034
00035     (+) Configurable Exti lines can be configured with 3 different triggers
00036         (++) Rising
00037         (++) Falling
00038         (++) Both of them
00039
00040     (+) When set in interrupt mode, configurable Exti lines have two different
00041         interrupt pending registers which allow to distinguish which transition
00042         occurs:
00043         (++) Rising edge pending interrupt
00044         (++) Falling
00045
00046     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
00047         be selected through multiplexer.
00048
00049                      ##### How to use this driver #####
00050   ==============================================================================
00051   [..]
00052
00053     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
00054         (++) Choose the interrupt line number by setting "Line" member from
00055              EXTI_ConfigTypeDef structure.
00056         (++) Configure the interrupt and/or event mode using "Mode" member from
00057              EXTI_ConfigTypeDef structure.
00058         (++) For configurable lines, configure rising and/or falling trigger
00059              "Trigger" member from EXTI_ConfigTypeDef structure.
00060         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
00061              member from GPIO_InitTypeDef structure.
00062
00063     (#) Get current Exti configuration of a dedicated line using
00064         HAL_EXTI_GetConfigLine().
00065         (++) Provide exiting handle as parameter.
00066         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
00067
00068     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
00069         (++) Provide exiting handle as parameter.
00070
00071     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
00072         (++) Provide exiting handle as first parameter.
00073         (++) Provide which callback will be registered using one value from
00074              EXTI_CallbackIDTypeDef.
00075         (++) Provide callback function pointer.
00076
00077     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
00078
00079     (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
00080
00081     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
00082
00083   @endverbatim
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32g4xx_hal.h"
00088
00089 /** @addtogroup STM32G4xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @addtogroup EXTI
00094   * @{
00095   */
00096 /** MISRA C:2012 deviation rule has been granted for following rule:
00097   * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
00098   * of bounds [0,3] in following API :
00099   * HAL_EXTI_SetConfigLine
00100   * HAL_EXTI_GetConfigLine
00101   * HAL_EXTI_ClearConfigLine
00102   */
00103
00104 #ifdef HAL_EXTI_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private defines ------------------------------------------------------------*/
00108 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00109   * @{
00110   */
00111 #define EXTI_MODE_OFFSET                    0x08U   /* 0x20: offset between MCU IMR/EMR registers */
00112 #define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between MCU Rising/Falling configuration registers */
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros ------------------------------------------------------------*/
00118 /* Private variables ---------------------------------------------------------*/
00119 /* Private function prototypes -----------------------------------------------*/
00120 /* Exported functions --------------------------------------------------------*/
00121
00122 /** @addtogroup EXTI_Exported_Functions
00123   * @{
00124   */
00125
00126 /** @addtogroup EXTI_Exported_Functions_Group1
00127   *  @brief    Configuration functions
00128   *
00129 @verbatim
00130  ===============================================================================
00131               ##### Configuration functions #####
00132  ===============================================================================
00133
00134 @endverbatim
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Set configuration of a dedicated Exti line.
00140   * @param  hexti Exti handle.
00141   * @param  pExtiConfig Pointer on EXTI configuration to be set.
00142   * @retval HAL Status.
00143   */
00144 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00145 {
00146   __IO uint32_t *regaddr;
00147   uint32_t regval;
00148   uint32_t linepos;
00149   uint32_t maskline;
00150   uint32_t offset;
00151
00152   /* Check null pointer */
00153   if ((hexti == NULL) || (pExtiConfig == NULL))
00154   {
00155     return HAL_ERROR;
00156   }
00157
00158   /* Check parameters */
00159   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
00160   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
00161
00162   /* Assign line number to handle */
00163   hexti->Line = pExtiConfig->Line;
00164
00165   /* Compute line register offset */
00166   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00167   /* Compute line position */
00168   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00169   /* Compute line mask */
00170   maskline = (1uL << linepos);
00171
00172   /* Configure triggers for configurable lines */
00173   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00174   {
00175     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
00176
00177     /* Configure rising trigger */
00178     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00179     regval = *regaddr;
00180
00181     /* Mask or set line */
00182     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
00183     {
00184       regval |= maskline;
00185     }
00186     else
00187     {
00188       regval &= ~maskline;
00189     }
00190
00191     /* Store rising trigger mode */
00192     *regaddr = regval;
00193
00194     /* Configure falling trigger */
00195     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00196     regval = *regaddr;
00197
00198     /* Mask or set line */
00199     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
00200     {
00201       regval |= maskline;
00202     }
00203     else
00204     {
00205       regval &= ~maskline;
00206     }
00207
00208     /* Store falling trigger mode */
00209     *regaddr = regval;
00210
00211     /* Configure gpio port selection in case of gpio exti line */
00212     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00213     {
00214       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
00215       assert_param(IS_EXTI_GPIO_PIN(linepos));
00216
00217       regval = SYSCFG->EXTICR[linepos >> 2u];
00218       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00219       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00220       SYSCFG->EXTICR[linepos >> 2u] = regval;
00221     }
00222   }
00223
00224   /* Configure interrupt mode : read current mode */
00225   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00226   regval = *regaddr;
00227
00228   /* Mask or set line */
00229   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
00230   {
00231     regval |= maskline;
00232   }
00233   else
00234   {
00235     regval &= ~maskline;
00236   }
00237
00238   /* Store interrupt mode */
00239   *regaddr = regval;
00240
00241   /* Configure event mode : read current mode */
00242   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00243   regval = *regaddr;
00244
00245   /* Mask or set line */
00246   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
00247   {
00248     regval |= maskline;
00249   }
00250   else
00251   {
00252     regval &= ~maskline;
00253   }
00254
00255   /* Store event mode */
00256   *regaddr = regval;
00257
00258   return HAL_OK;
00259 }
00260
00261
00262 /**
00263   * @brief  Get configuration of a dedicated Exti line.
00264   * @param  hexti Exti handle.
00265   * @param  pExtiConfig Pointer on structure to store Exti configuration.
00266   * @retval HAL Status.
00267   */
00268 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00269 {
00270   __IO uint32_t *regaddr;
00271   uint32_t regval;
00272   uint32_t linepos;
00273   uint32_t maskline;
00274   uint32_t offset;
00275
00276   /* Check null pointer */
00277   if ((hexti == NULL) || (pExtiConfig == NULL))
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameter */
00283   assert_param(IS_EXTI_LINE(hexti->Line));
00284
00285   /* Store handle line number to configuration structure */
00286   pExtiConfig->Line = hexti->Line;
00287
00288   /* Compute line register offset and line mask */
00289   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00290   /* Compute line position */
00291   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00292   /* Compute mask */
00293   maskline = (1uL << linepos);
00294
00295   /* 1] Get core mode : interrupt */
00296   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00297   regval = *regaddr;
00298
00299   /* Check if selected line is enable */
00300   if ((regval & maskline) != 0x00u)
00301   {
00302     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
00303   }
00304   else
00305   {
00306     pExtiConfig->Mode = EXTI_MODE_NONE;
00307   }
00308
00309   /* Get event mode */
00310   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00311   regval = *regaddr;
00312
00313   /* Check if selected line is enable */
00314   if ((regval & maskline) != 0x00u)
00315   {
00316     pExtiConfig->Mode |= EXTI_MODE_EVENT;
00317   }
00318
00319   /* Get default Trigger and GPIOSel configuration */
00320   pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00321   pExtiConfig->GPIOSel = 0x00u;
00322
00323   /* 2] Get trigger for configurable lines : rising */
00324   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00325   {
00326     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00327     regval = *regaddr;
00328
00329     /* Check if configuration of selected line is enable */
00330     if ((regval & maskline) != 0x00u)
00331     {
00332       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
00333     }
00334
00335     /* Get falling configuration */
00336     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00337     regval = *regaddr;
00338
00339     /* Check if configuration of selected line is enable */
00340     if ((regval & maskline) != 0x00u)
00341     {
00342       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
00343     }
00344
00345     /* Get Gpio port selection for gpio lines */
00346     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00347     {
00348       assert_param(IS_EXTI_GPIO_PIN(linepos));
00349
00350       regval = SYSCFG->EXTICR[linepos >> 2u];
00351       pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
00352     }
00353   }
00354
00355   return HAL_OK;
00356 }
00357
00358
00359 /**
00360   * @brief  Clear whole configuration of a dedicated Exti line.
00361   * @param  hexti Exti handle.
00362   * @retval HAL Status.
00363   */
00364 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
00365 {
00366   __IO uint32_t *regaddr;
00367   uint32_t regval;
00368   uint32_t linepos;
00369   uint32_t maskline;
00370   uint32_t offset;
00371
00372   /* Check null pointer */
00373   if (hexti == NULL)
00374   {
00375     return HAL_ERROR;
00376   }
00377
00378   /* Check the parameter */
00379   assert_param(IS_EXTI_LINE(hexti->Line));
00380
00381   /* compute line register offset and line mask */
00382   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00383   /* compute line position */
00384   linepos = (hexti->Line & EXTI_PIN_MASK);
00385   /* compute line mask */
00386   maskline = (1uL << linepos);
00387
00388   /* 1] Clear interrupt mode */
00389   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00390   regval = (*regaddr & ~maskline);
00391   *regaddr = regval;
00392
00393   /* 2] Clear event mode */
00394   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00395   regval = (*regaddr & ~maskline);
00396   *regaddr = regval;
00397
00398   /* 3] Clear triggers in case of configurable lines */
00399   if ((hexti->Line & EXTI_CONFIG) != 0x00u)
00400   {
00401     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00402     regval = (*regaddr & ~maskline);
00403     *regaddr = regval;
00404
00405     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00406     regval = (*regaddr & ~maskline);
00407     *regaddr = regval;
00408
00409     /* Get Gpio port selection for gpio lines */
00410     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
00411     {
00412       assert_param(IS_EXTI_GPIO_PIN(linepos));
00413
00414       regval = SYSCFG->EXTICR[linepos >> 2u];
00415       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00416       SYSCFG->EXTICR[linepos >> 2u] = regval;
00417     }
00418   }
00419
00420   return HAL_OK;
00421 }
00422
00423
00424 /**
00425   * @brief  Register callback for a dedicated Exti line.
00426   * @param  hexti Exti handle.
00427   * @param  CallbackID User callback identifier.
00428   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
00429   * @param  pPendingCbfn function pointer to be stored as callback.
00430   * @retval HAL Status.
00431   */
00432 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
00433 {
00434   HAL_StatusTypeDef status = HAL_OK;
00435
00436   /* Check the parameters */
00437   assert_param(IS_EXTI_CB(CallbackID));
00438
00439   switch (CallbackID)
00440   {
00441     /* set common callback */
00442     case  HAL_EXTI_COMMON_CB_ID:
00443       hexti->PendingCallback = pPendingCbfn;
00444       break;
00445
00446     default:
00447       hexti->PendingCallback = NULL;
00448       status = HAL_ERROR;
00449       break;
00450   }
00451
00452   return status;
00453 }
00454
00455
00456 /**
00457   * @brief  Store line number as handle private field.
00458   * @param  hexti Exti handle.
00459   * @param  ExtiLine Exti line number.
00460   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
00461   * @retval HAL Status.
00462   */
00463 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
00464 {
00465   /* Check the parameters */
00466   assert_param(IS_EXTI_LINE(ExtiLine));
00467
00468   /* Check null pointer */
00469   if (hexti == NULL)
00470   {
00471     return HAL_ERROR;
00472   }
00473   else
00474   {
00475     /* Store line number as handle private field */
00476     hexti->Line = ExtiLine;
00477
00478     return HAL_OK;
00479   }
00480 }
00481
00482
00483 /**
00484   * @}
00485   */
00486
00487 /** @addtogroup EXTI_Exported_Functions_Group2
00488   *  @brief EXTI IO functions.
00489   *
00490 @verbatim
00491  ===============================================================================
00492                        ##### IO operation functions #####
00493  ===============================================================================
00494
00495 @endverbatim
00496   * @{
00497   */
00498
00499 /**
00500   * @brief  Handle EXTI interrupt request.
00501   * @param  hexti Exti handle.
00502   * @retval none.
00503   */
00504 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
00505 {
00506   __IO uint32_t *regaddr;
00507   uint32_t regval;
00508   uint32_t maskline;
00509   uint32_t offset;
00510
00511   /* Compute line register offset */
00512   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00513   /* compute line mask */
00514   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00515
00516   /* Get pending bit  */
00517   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00518   regval = (*regaddr & maskline);
00519
00520   if (regval != 0x00u)
00521   {
00522     /* Clear pending bit */
00523     *regaddr = maskline;
00524
00525     /* Call pending callback */
00526     if (hexti->PendingCallback != NULL)
00527     {
00528       hexti->PendingCallback();
00529     }
00530   }
00531 }
00532
00533 /**
00534   * @brief  Get interrupt pending bit of a dedicated line.
00535   * @param  hexti Exti handle.
00536   * @param  Edge unused
00537   * @retval 1 if interrupt is pending else 0.
00538   */
00539 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00540 {
00541   __IO uint32_t *regaddr;
00542   uint32_t regval;
00543   uint32_t linepos;
00544   uint32_t maskline;
00545   uint32_t offset;
00546
00547   /* Check parameters */
00548   assert_param(IS_EXTI_LINE(hexti->Line));
00549   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00550   UNUSED(Edge);
00551
00552   /* Compute line register offset */
00553   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00554   /* Compute line position */
00555   linepos = (hexti->Line & EXTI_PIN_MASK);
00556   /* Compute line mask */
00557   maskline = (1uL << linepos);
00558
00559   /* Get pending bit */
00560   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00561
00562   /* return 1 if bit is set else 0 */
00563   regval = ((*regaddr & maskline) >> linepos);
00564   return regval;
00565 }
00566
00567
00568 /**
00569   * @brief  Clear interrupt pending bit of a dedicated line.
00570   * @param  hexti Exti handle.
00571   * @param  Edge unused
00572   * @retval None.
00573   */
00574 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00575 {
00576   __IO uint32_t *regaddr;
00577   uint32_t maskline;
00578   uint32_t offset;
00579
00580   /* Check parameters */
00581   assert_param(IS_EXTI_LINE(hexti->Line));
00582   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00583   UNUSED(Edge);
00584
00585   /* Compute line register offset */
00586   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00587   /* Compute line mask */
00588   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00589
00590   /* Get pending register address */
00591   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00592
00593   /* Clear Pending bit */
00594   *regaddr =  maskline;
00595 }
00596
00597
00598 /**
00599   * @brief  Generate a software interrupt for a dedicated line.
00600   * @param  hexti Exti handle.
00601   * @retval None.
00602   */
00603 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
00604 {
00605   __IO uint32_t *regaddr;
00606   uint32_t maskline;
00607   uint32_t offset;
00608
00609   /* Check parameter */
00610   assert_param(IS_EXTI_LINE(hexti->Line));
00611   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00612
00613   /* compute line register offset */
00614   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00615   /* compute line mask */
00616   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00617
00618   regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
00619   *regaddr = maskline;
00620 }
00621
00622
00623 /**
00624   * @}
00625   */
00626
00627 /**
00628   * @}
00629   */
00630
00631 #endif /* HAL_EXTI_MODULE_ENABLED */
00632 /**
00633   * @}
00634   */
00635
00636 /**
00637   * @}
00638   */
00639
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_exti.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_exti.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_EXTI_H
00021 #define STM32G4xx_HAL_EXTI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup EXTI EXTI
00035   * @brief EXTI HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup EXTI_Exported_Types EXTI Exported Types
00042   * @{
00043   */
00044 typedef enum
00045 {
00046   HAL_EXTI_COMMON_CB_ID         = 0x00UL
00047 } EXTI_CallbackIDTypeDef;
00048
00049
00050 /**
00051   * @brief  EXTI Handle structure definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t Line;                    /*!<  Exti line number */
00056   void (* PendingCallback)(void);   /*!<  Exti pending callback */
00057 } EXTI_HandleTypeDef;
00058
00059 /**
00060   * @brief  EXTI Configuration structure definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t Line;      /*!< The Exti line to be configured. This parameter
00065                            can be a value of @ref EXTI_Line */
00066   uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
00067                            This parameter can be a combination of @ref EXTI_Mode */
00068   uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
00069                            can be a value of @ref EXTI_Trigger */
00070   uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
00071                            This parameter is only possible for line 0 to 15. It
00072                            can be a value of @ref EXTI_GPIOSel */
00073 } EXTI_ConfigTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup EXTI_Line  EXTI Line
00085   * @{
00086   */
00087 #define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | 0x00u)
00088 #define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | 0x01u)
00089 #define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | 0x02u)
00090 #define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | 0x03u)
00091 #define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | 0x04u)
00092 #define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | 0x05u)
00093 #define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | 0x06u)
00094 #define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | 0x07u)
00095 #define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | 0x08u)
00096 #define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | 0x09u)
00097 #define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | 0x0Au)
00098 #define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | 0x0Bu)
00099 #define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | 0x0Cu)
00100 #define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | 0x0Du)
00101 #define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | 0x0Eu)
00102 #define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | 0x0Fu)
00103 #define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | 0x10u)
00104 #define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_REG1 | 0x11u)
00105 #define EXTI_LINE_18                        (EXTI_DIRECT   | EXTI_REG1 | 0x12u)
00106 #define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_REG1 | 0x13u)
00107 #define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | 0x14u)
00108 #define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | 0x15u)
00109 #define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | 0x16u)
00110 #define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | 0x17u)
00111 #define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | 0x18u)
00112 #define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | 0x19u)
00113 #define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Au)
00114 #define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Bu)
00115 #define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Cu)
00116 #define EXTI_LINE_29                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Du)
00117 #define EXTI_LINE_30                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Eu)
00118 #define EXTI_LINE_31                        (EXTI_CONFIG   | EXTI_REG1 | 0x1Fu)
00119 #define EXTI_LINE_32                        (EXTI_CONFIG   | EXTI_REG2 | 0x00u)
00120 #define EXTI_LINE_33                        (EXTI_CONFIG   | EXTI_REG2 | 0x01u)
00121 #define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | 0x02u)
00122 #define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_REG2 | 0x03u)
00123 #define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_REG2 | 0x04u)
00124 #define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_REG2 | 0x05u)
00125 #define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | 0x06u)
00126 #define EXTI_LINE_39                        (EXTI_CONFIG   | EXTI_REG2 | 0x07u)
00127 #define EXTI_LINE_40                        (EXTI_CONFIG   | EXTI_REG2 | 0x08u)
00128 #define EXTI_LINE_41                        (EXTI_CONFIG   | EXTI_REG2 | 0x09u)
00129 #define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_REG2 | 0x0Au)
00130 #define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_REG2 | 0x0Bu)
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup EXTI_Mode  EXTI Mode
00136   * @{
00137   */
00138 #define EXTI_MODE_NONE                      0x00000000U
00139 #define EXTI_MODE_INTERRUPT                 0x00000001U
00140 #define EXTI_MODE_EVENT                     0x00000002U
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup EXTI_Trigger  EXTI Trigger
00146   * @{
00147   */
00148 #define EXTI_TRIGGER_NONE                   0x00000000U
00149 #define EXTI_TRIGGER_RISING                 0x00000001U
00150 #define EXTI_TRIGGER_FALLING                0x00000002U
00151 #define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup EXTI_GPIOSel  EXTI GPIOSel
00157   * @brief
00158   * @{
00159   */
00160 #define EXTI_GPIOA                          0x00000000U
00161 #define EXTI_GPIOB                          0x00000001U
00162 #define EXTI_GPIOC                          0x00000002U
00163 #define EXTI_GPIOD                          0x00000003U
00164 #define EXTI_GPIOE                          0x00000004U
00165 #define EXTI_GPIOF                          0x00000005U
00166 #define EXTI_GPIOG                          0x00000006U
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported macro ------------------------------------------------------------*/
00176 /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
00177   * @{
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /* Private constants --------------------------------------------------------*/
00185 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00186   * @{
00187   */
00188 /**
00189   * @brief  EXTI Line property definition
00190   */
00191 #define EXTI_PROPERTY_SHIFT                 24U
00192 #define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
00193 #define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
00194 #define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
00195 #define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
00196 #define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
00197
00198 /**
00199   * @brief  EXTI Register and bit usage
00200   */
00201 #define EXTI_REG_SHIFT                      16U
00202 #define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
00203 #define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
00204 #define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
00205 #define EXTI_PIN_MASK                       0x0000001FU
00206
00207 /**
00208   * @brief  EXTI Mask for interrupt & event mode
00209   */
00210 #define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
00211
00212 /**
00213   * @brief  EXTI Mask for trigger possibilities
00214   */
00215 #define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00216
00217 /**
00218   * @brief  EXTI Line number
00219   */
00220 #define EXTI_LINE_NB                        44UL
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Private macros ------------------------------------------------------------*/
00227 /** @defgroup EXTI_Private_Macros EXTI Private Macros
00228   * @{
00229   */
00230 #define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
00231                                               ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
00232                                                (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
00233                                                (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
00234                                               (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
00235                                                (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
00236
00237 #define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
00238                                               (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
00239
00240 #define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
00241
00242 #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
00243
00244 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00245                                          ((__PORT__) == EXTI_GPIOB) || \
00246                                          ((__PORT__) == EXTI_GPIOC) || \
00247                                          ((__PORT__) == EXTI_GPIOD) || \
00248                                          ((__PORT__) == EXTI_GPIOE) || \
00249                                          ((__PORT__) == EXTI_GPIOF) || \
00250                                          ((__PORT__) == EXTI_GPIOG))
00251
00252 #define IS_EXTI_GPIO_PIN(__PIN__)        ((__PIN__) < 16u)
00253
00254 #define IS_EXTI_PENDING_EDGE(__EDGE__)   (((__EDGE__) == EXTI_TRIGGER_RISING)   || \
00255                                           ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
00256                                           ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
00257
00258 #define IS_EXTI_CB(__CB__)               ((__CB__) == HAL_EXTI_COMMON_CB_ID)
00259 /**
00260   * @}
00261   */
00262
00263
00264 /* Exported functions --------------------------------------------------------*/
00265 /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
00266   * @brief    EXTI Exported Functions
00267   * @{
00268   */
00269
00270 /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
00271   * @brief    Configuration functions
00272   * @{
00273   */
00274 /* Configuration functions ****************************************************/
00275 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00276 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00277 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
00278 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
00279 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
00285   * @brief    IO operation functions
00286   * @{
00287   */
00288 /* IO operation functions *****************************************************/
00289 void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
00290 uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00291 void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00292 void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 #ifdef __cplusplus
00311 }
00312 #endif
00313
00314 #endif /* STM32G4xx_HAL_EXTI_H */
00315
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fdcan.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_fdcan.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_fdcan.c
00004   * @author  MCD Application Team
00005   * @brief   FDCAN HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Flexible DataRate Controller Area Network
00008   *          (FDCAN) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Configuration and Control functions
00012   *           + Peripheral State and Error functions
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029       (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
00030
00031       (#) If needed , configure the reception filters and optional features using
00032           the following configuration functions:
00033             (++) HAL_FDCAN_ConfigFilter
00034             (++) HAL_FDCAN_ConfigGlobalFilter
00035             (++) HAL_FDCAN_ConfigExtendedIdMask
00036             (++) HAL_FDCAN_ConfigRxFifoOverwrite
00037             (++) HAL_FDCAN_ConfigRamWatchdog
00038             (++) HAL_FDCAN_ConfigTimestampCounter
00039             (++) HAL_FDCAN_EnableTimestampCounter
00040             (++) HAL_FDCAN_DisableTimestampCounter
00041             (++) HAL_FDCAN_ConfigTimeoutCounter
00042             (++) HAL_FDCAN_EnableTimeoutCounter
00043             (++) HAL_FDCAN_DisableTimeoutCounter
00044             (++) HAL_FDCAN_ConfigTxDelayCompensation
00045             (++) HAL_FDCAN_EnableTxDelayCompensation
00046             (++) HAL_FDCAN_DisableTxDelayCompensation
00047             (++) HAL_FDCAN_EnableISOMode
00048             (++) HAL_FDCAN_DisableISOMode
00049             (++) HAL_FDCAN_EnableEdgeFiltering
00050             (++) HAL_FDCAN_DisableEdgeFiltering
00051
00052       (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
00053           the node is active on the bus: it can send and receive messages.
00054
00055       (#) The following Tx control functions can only be called when the FDCAN
00056           module is started:
00057             (++) HAL_FDCAN_AddMessageToTxFifoQ
00058             (++) HAL_FDCAN_AbortTxRequest
00059
00060       (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
00061           get Tx buffer location used to place the Tx request thanks to
00062           HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
00063           It is then possible to abort later on the corresponding Tx Request using
00064           HAL_FDCAN_AbortTxRequest API.
00065
00066       (#) When a message is received into the FDCAN message RAM, it can be
00067           retrieved using the HAL_FDCAN_GetRxMessage function.
00068
00069       (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
00070           it to initialization mode and re-enabling access to configuration
00071           registers through the configuration functions listed here above.
00072
00073       (#) All other control functions can be called any time after initialization
00074           phase, no matter if the FDCAN module is started or stopped.
00075
00076       *** Polling mode operation ***
00077       ==============================
00078     [..]
00079         (#) Reception and transmission states can be monitored via the following
00080             functions:
00081               (++) HAL_FDCAN_IsTxBufferMessagePending
00082               (++) HAL_FDCAN_GetRxFifoFillLevel
00083               (++) HAL_FDCAN_GetTxFifoFreeLevel
00084
00085       *** Interrupt mode operation ***
00086       ================================
00087       [..]
00088         (#) There are two interrupt lines: line 0 and 1.
00089             By default, all interrupts are assigned to line 0. Interrupt lines
00090             can be configured using HAL_FDCAN_ConfigInterruptLines function.
00091
00092         (#) Notifications are activated using HAL_FDCAN_ActivateNotification
00093             function. Then, the process can be controlled through one of the
00094             available user callbacks: HAL_FDCAN_xxxCallback.
00095
00096   *** Callback registration ***
00097   =============================================
00098
00099   The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
00100   allows the user to configure dynamically the driver callbacks.
00101   Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
00102   to register an interrupt callback.
00103
00104   Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
00105     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00106     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00107     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00108     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00109     (+) ErrorCallback                : Error Callback.
00110     (+) MspInitCallback              : FDCAN MspInit.
00111     (+) MspDeInitCallback            : FDCAN MspDeInit.
00112   This function takes as parameters the HAL peripheral handle, the Callback ID
00113   and a pointer to the user callback function.
00114
00115   For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
00116   TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
00117   register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
00118   HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
00119   HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
00120   and HAL_FDCAN_RegisterErrorStatusCallback().
00121
00122   Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
00123   weak function.
00124   HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
00125   and the Callback ID.
00126   This function allows to reset following callbacks:
00127     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00128     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00129     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00130     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00131     (+) ErrorCallback                : Error Callback.
00132     (+) MspInitCallback              : FDCAN MspInit.
00133     (+) MspDeInitCallback            : FDCAN MspDeInit.
00134
00135   For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
00136   TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
00137   unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
00138   HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
00139   HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
00140   and HAL_FDCAN_UnRegisterErrorStatusCallback().
00141
00142   By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
00143   all callbacks are set to the corresponding weak functions:
00144   examples HAL_FDCAN_ErrorCallback().
00145   Exception done for MspInit and MspDeInit functions that are
00146   reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
00147   these callbacks are null (not registered beforehand).
00148   if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
00149   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00150
00151   Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
00152   Exception done MspInit/MspDeInit that can be registered/unregistered
00153   in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
00154   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00155   In that case first register the MspInit/MspDeInit user callbacks
00156   using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
00157   or HAL_FDCAN_Init() function.
00158
00159   When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
00160   not defined, the callback registration feature is not available and all callbacks
00161   are set to the corresponding weak functions.
00162
00163   @endverbatim
00164   ******************************************************************************
00165   */
00166
00167 /* Includes ------------------------------------------------------------------*/
00168 #include "stm32g4xx_hal.h"
00169
00170 #if defined(FDCAN1)
00171
00172 /** @addtogroup STM32G4xx_HAL_Driver
00173   * @{
00174   */
00175
00176 /** @defgroup FDCAN FDCAN
00177   * @brief FDCAN HAL module driver
00178   * @{
00179   */
00180
00181 #ifdef HAL_FDCAN_MODULE_ENABLED
00182
00183 /* Private typedef -----------------------------------------------------------*/
00184 /* Private define ------------------------------------------------------------*/
00185 /** @addtogroup FDCAN_Private_Constants
00186   * @{
00187   */
00188 #define FDCAN_TIMEOUT_VALUE 10U
00189
00190 #define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
00191 #define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
00192 #define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
00193 #define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
00194 #define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
00195
00196 #define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
00197 #define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
00198 #define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
00199 #define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
00200 #define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
00201 #define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
00202 #define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
00203 #define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
00204 #define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
00205 #define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
00206 #define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
00207 #define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
00208 #define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
00209 #define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
00210
00211 #define SRAMCAN_FLS_NBR                  (28U)         /* Max. Filter List Standard Number      */
00212 #define SRAMCAN_FLE_NBR                  ( 8U)         /* Max. Filter List Extended Number      */
00213 #define SRAMCAN_RF0_NBR                  ( 3U)         /* RX FIFO 0 Elements Number             */
00214 #define SRAMCAN_RF1_NBR                  ( 3U)         /* RX FIFO 1 Elements Number             */
00215 #define SRAMCAN_TEF_NBR                  ( 3U)         /* TX Event FIFO Elements Number         */
00216 #define SRAMCAN_TFQ_NBR                  ( 3U)         /* TX FIFO/Queue Elements Number         */
00217
00218 #define SRAMCAN_FLS_SIZE            ( 1U * 4U)         /* Filter Standard Element Size in bytes */
00219 #define SRAMCAN_FLE_SIZE            ( 2U * 4U)         /* Filter Extended Element Size in bytes */
00220 #define SRAMCAN_RF0_SIZE            (18U * 4U)         /* RX FIFO 0 Elements Size in bytes      */
00221 #define SRAMCAN_RF1_SIZE            (18U * 4U)         /* RX FIFO 1 Elements Size in bytes      */
00222 #define SRAMCAN_TEF_SIZE            ( 2U * 4U)         /* TX Event FIFO Elements Size in bytes  */
00223 #define SRAMCAN_TFQ_SIZE            (18U * 4U)         /* TX FIFO/Queue Elements Size in bytes  */
00224
00225 #define SRAMCAN_FLSSA ((uint32_t)0)                                                      /* Filter List Standard Start
00226                                                                                             Address                  */
00227 #define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
00228                                                                                             Address                  */
00229 #define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address  */
00230 #define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address  */
00231 #define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
00232                                                                                             Address */
00233 #define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
00234                                                                                             Address                  */
00235 #define SRAMCAN_SIZE  ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size         */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /* Private macro -------------------------------------------------------------*/
00242 /* Private variables ---------------------------------------------------------*/
00243 /** @addtogroup FDCAN_Private_Variables
00244   * @{
00245   */
00246 static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
00247 /**
00248   * @}
00249   */
00250
00251 /* Private function prototypes -----------------------------------------------*/
00252 /** @addtogroup FDCAN_Private_Functions_Prototypes
00253   * @{
00254   */
00255 static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
00256 static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
00257                                    const uint8_t *pTxData, uint32_t BufferIndex);
00258 /**
00259   * @}
00260   */
00261
00262 /* Exported functions --------------------------------------------------------*/
00263 /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
00264   * @{
00265   */
00266
00267 /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
00268   *  @brief    Initialization and Configuration functions
00269   *
00270 @verbatim
00271   ==============================================================================
00272               ##### Initialization and de-initialization functions #####
00273   ==============================================================================
00274     [..]  This section provides functions allowing to:
00275       (+) Initialize and configure the FDCAN.
00276       (+) De-initialize the FDCAN.
00277       (+) Enter FDCAN peripheral in power down mode.
00278       (+) Exit power down mode.
00279       (+) Register callbacks.
00280       (+) Unregister callbacks.
00281
00282 @endverbatim
00283   * @{
00284   */
00285
00286 /**
00287   * @brief  Initializes the FDCAN peripheral according to the specified
00288   *         parameters in the FDCAN_InitTypeDef structure.
00289   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00290   *         the configuration information for the specified FDCAN.
00291   * @retval HAL status
00292   */
00293 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
00294 {
00295   uint32_t tickstart;
00296
00297   /* Check FDCAN handle */
00298   if (hfdcan == NULL)
00299   {
00300     return HAL_ERROR;
00301   }
00302
00303   /* Check function parameters */
00304   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00305   if (hfdcan->Instance == FDCAN1)
00306   {
00307     assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
00308   }
00309   assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
00310   assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
00311   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
00312   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
00313   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
00314   assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
00315   assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
00316   assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
00317   assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
00318   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00319   {
00320     assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
00321     assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
00322     assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
00323     assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
00324   }
00325   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
00326   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
00327   assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
00328
00329 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00330   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00331   {
00332     /* Allocate lock resource and initialize it */
00333     hfdcan->Lock = HAL_UNLOCKED;
00334
00335     /* Reset callbacks to legacy functions */
00336     hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* TxEventFifoCallback */
00337     hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* RxFifo0Callback     */
00338     hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* RxFifo1Callback     */
00339     hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* TxFifoEmptyCallback */
00340     hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* TxBufferCompleteCallback        */
00341     hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* TxBufferAbortCallback           */
00342     hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback     */
00343     hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback     */
00344     hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* TimeoutOccurredCallback         */
00345     hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* ErrorCallback       */
00346     hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* ErrorStatusCallback */
00347
00348     if (hfdcan->MspInitCallback == NULL)
00349     {
00350       hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
00351     }
00352
00353     /* Init the low level hardware: CLOCK, NVIC */
00354     hfdcan->MspInitCallback(hfdcan);
00355   }
00356 #else
00357   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00358   {
00359     /* Allocate lock resource and initialize it */
00360     hfdcan->Lock = HAL_UNLOCKED;
00361
00362     /* Init the low level hardware: CLOCK, NVIC */
00363     HAL_FDCAN_MspInit(hfdcan);
00364   }
00365 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00366
00367   /* Exit from Sleep mode */
00368   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00369
00370   /* Get tick */
00371   tickstart = HAL_GetTick();
00372
00373   /* Check Sleep mode acknowledge */
00374   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00375   {
00376     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00377     {
00378       /* Update error code */
00379       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00380
00381       /* Change FDCAN state */
00382       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00383
00384       return HAL_ERROR;
00385     }
00386   }
00387
00388   /* Request initialisation */
00389   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00390
00391   /* Get tick */
00392   tickstart = HAL_GetTick();
00393
00394   /* Wait until the INIT bit into CCCR register is set */
00395   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
00396   {
00397     /* Check for the Timeout */
00398     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00399     {
00400       /* Update error code */
00401       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00402
00403       /* Change FDCAN state */
00404       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00405
00406       return HAL_ERROR;
00407     }
00408   }
00409
00410   /* Enable configuration change */
00411   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
00412
00413   /* Check FDCAN instance */
00414   if (hfdcan->Instance == FDCAN1)
00415   {
00416     /* Configure Clock divider */
00417     FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
00418   }
00419
00420   /* Set the no automatic retransmission */
00421   if (hfdcan->Init.AutoRetransmission == ENABLE)
00422   {
00423     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00424   }
00425   else
00426   {
00427     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00428   }
00429
00430   /* Set the transmit pause feature */
00431   if (hfdcan->Init.TransmitPause == ENABLE)
00432   {
00433     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00434   }
00435   else
00436   {
00437     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00438   }
00439
00440   /* Set the Protocol Exception Handling */
00441   if (hfdcan->Init.ProtocolException == ENABLE)
00442   {
00443     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00444   }
00445   else
00446   {
00447     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00448   }
00449
00450   /* Set FDCAN Frame Format */
00451   MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
00452
00453   /* Reset FDCAN Operation Mode */
00454   CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
00455   CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00456
00457   /* Set FDCAN Operating Mode:
00458                | Normal | Restricted |    Bus     | Internal | External
00459                |        | Operation  | Monitoring | LoopBack | LoopBack
00460      CCCR.TEST |   0    |     0      |     0      |    1     |    1
00461      CCCR.MON  |   0    |     0      |     1      |    1     |    0
00462      TEST.LBCK |   0    |     0      |     0      |    1     |    1
00463      CCCR.ASM  |   0    |     1      |     0      |    0     |    0
00464   */
00465   if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
00466   {
00467     /* Enable Restricted Operation mode */
00468     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
00469   }
00470   else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
00471   {
00472     if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
00473     {
00474       /* Enable write access to TEST register */
00475       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
00476
00477       /* Enable LoopBack mode */
00478       SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00479
00480       if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
00481       {
00482         SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00483       }
00484     }
00485     else
00486     {
00487       /* Enable bus monitoring mode */
00488       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00489     }
00490   }
00491   else
00492   {
00493     /* Nothing to do: normal mode */
00494   }
00495
00496   /* Set the nominal bit timing register */
00497   hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
00498                             (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
00499                             (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
00500                             (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
00501
00502   /* If FD operation with BRS is selected, set the data bit timing register */
00503   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00504   {
00505     hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
00506                               (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
00507                               (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
00508                               (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
00509   }
00510
00511   /* Select between Tx FIFO and Tx Queue operation modes */
00512   SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
00513
00514   /* Calculate each RAM block address */
00515   FDCAN_CalcultateRamBlockAddresses(hfdcan);
00516
00517   /* Initialize the Latest Tx request buffer index */
00518   hfdcan->LatestTxFifoQRequest = 0U;
00519
00520   /* Initialize the error code */
00521   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00522
00523   /* Initialize the FDCAN state */
00524   hfdcan->State = HAL_FDCAN_STATE_READY;
00525
00526   /* Return function status */
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
00532   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00533   *         the configuration information for the specified FDCAN.
00534   * @retval HAL status
00535   */
00536 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
00537 {
00538   /* Check FDCAN handle */
00539   if (hfdcan == NULL)
00540   {
00541     return HAL_ERROR;
00542   }
00543
00544   /* Check function parameters */
00545   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00546
00547   /* Stop the FDCAN module: return value is voluntary ignored */
00548   (void)HAL_FDCAN_Stop(hfdcan);
00549
00550   /* Disable Interrupt lines */
00551   CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
00552
00553 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00554   if (hfdcan->MspDeInitCallback == NULL)
00555   {
00556     hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
00557   }
00558
00559   /* DeInit the low level hardware: CLOCK, NVIC */
00560   hfdcan->MspDeInitCallback(hfdcan);
00561 #else
00562   /* DeInit the low level hardware: CLOCK, NVIC */
00563   HAL_FDCAN_MspDeInit(hfdcan);
00564 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00565
00566   /* Reset the FDCAN ErrorCode */
00567   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00568
00569   /* Change FDCAN state */
00570   hfdcan->State = HAL_FDCAN_STATE_RESET;
00571
00572   /* Return function status */
00573   return HAL_OK;
00574 }
00575
00576 /**
00577   * @brief  Initializes the FDCAN MSP.
00578   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00579   *         the configuration information for the specified FDCAN.
00580   * @retval None
00581   */
00582 __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
00583 {
00584   /* Prevent unused argument(s) compilation warning */
00585   UNUSED(hfdcan);
00586   /* NOTE: This function Should not be modified, when the callback is needed,
00587             the HAL_FDCAN_MspInit could be implemented in the user file
00588    */
00589 }
00590
00591 /**
00592   * @brief  DeInitializes the FDCAN MSP.
00593   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00594   *         the configuration information for the specified FDCAN.
00595   * @retval None
00596   */
00597 __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
00598 {
00599   /* Prevent unused argument(s) compilation warning */
00600   UNUSED(hfdcan);
00601   /* NOTE: This function Should not be modified, when the callback is needed,
00602             the HAL_FDCAN_MspDeInit could be implemented in the user file
00603    */
00604 }
00605
00606 /**
00607   * @brief  Enter FDCAN peripheral in sleep mode.
00608   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00609   *         the configuration information for the specified FDCAN.
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00613 {
00614   uint32_t tickstart;
00615
00616   /* Request clock stop */
00617   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00618
00619   /* Get tick */
00620   tickstart = HAL_GetTick();
00621
00622   /* Wait until FDCAN is ready for power down */
00623   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
00624   {
00625     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00626     {
00627       /* Update error code */
00628       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00629
00630       /* Change FDCAN state */
00631       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00632
00633       return HAL_ERROR;
00634     }
00635   }
00636
00637   /* Return function status */
00638   return HAL_OK;
00639 }
00640
00641 /**
00642   * @brief  Exit power down mode.
00643   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00644   *         the configuration information for the specified FDCAN.
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00648 {
00649   uint32_t tickstart;
00650
00651   /* Reset clock stop request */
00652   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00653
00654   /* Get tick */
00655   tickstart = HAL_GetTick();
00656
00657   /* Wait until FDCAN exits sleep mode */
00658   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00659   {
00660     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00661     {
00662       /* Update error code */
00663       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00664
00665       /* Change FDCAN state */
00666       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00667
00668       return HAL_ERROR;
00669     }
00670   }
00671
00672   /* Enter normal operation */
00673   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00674
00675   /* Return function status */
00676   return HAL_OK;
00677 }
00678
00679 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00680 /**
00681   * @brief  Register a FDCAN CallBack.
00682   *         To be used instead of the weak predefined callback
00683   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00684   *         the configuration information for FDCAN module
00685   * @param  CallbackID ID of the callback to be registered
00686   *         This parameter can be one of the following values:
00687   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00688   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00689   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00690   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00691   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00692   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00693   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00694   * @param  pCallback pointer to the Callback function
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
00698                                              void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
00699 {
00700   HAL_StatusTypeDef status = HAL_OK;
00701
00702   if (pCallback == NULL)
00703   {
00704     /* Update the error code */
00705     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00706
00707     return HAL_ERROR;
00708   }
00709
00710   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00711   {
00712     switch (CallbackID)
00713     {
00714       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00715         hfdcan->TxFifoEmptyCallback = pCallback;
00716         break;
00717
00718       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00719         hfdcan->HighPriorityMessageCallback = pCallback;
00720         break;
00721
00722       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00723         hfdcan->TimestampWraparoundCallback = pCallback;
00724         break;
00725
00726       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00727         hfdcan->TimeoutOccurredCallback = pCallback;
00728         break;
00729
00730       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00731         hfdcan->ErrorCallback = pCallback;
00732         break;
00733
00734       case HAL_FDCAN_MSPINIT_CB_ID :
00735         hfdcan->MspInitCallback = pCallback;
00736         break;
00737
00738       case HAL_FDCAN_MSPDEINIT_CB_ID :
00739         hfdcan->MspDeInitCallback = pCallback;
00740         break;
00741
00742       default :
00743         /* Update the error code */
00744         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00745
00746         /* Return error status */
00747         status =  HAL_ERROR;
00748         break;
00749     }
00750   }
00751   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00752   {
00753     switch (CallbackID)
00754     {
00755       case HAL_FDCAN_MSPINIT_CB_ID :
00756         hfdcan->MspInitCallback = pCallback;
00757         break;
00758
00759       case HAL_FDCAN_MSPDEINIT_CB_ID :
00760         hfdcan->MspDeInitCallback = pCallback;
00761         break;
00762
00763       default :
00764         /* Update the error code */
00765         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00766
00767         /* Return error status */
00768         status =  HAL_ERROR;
00769         break;
00770     }
00771   }
00772   else
00773   {
00774     /* Update the error code */
00775     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00776
00777     /* Return error status */
00778     status =  HAL_ERROR;
00779   }
00780
00781   return status;
00782 }
00783
00784 /**
00785   * @brief  Unregister a FDCAN CallBack.
00786   *         FDCAN callback is redirected to the weak predefined callback
00787   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00788   *         the configuration information for FDCAN module
00789   * @param  CallbackID ID of the callback to be unregistered
00790   *         This parameter can be one of the following values:
00791   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00792   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00793   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00794   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00795   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00796   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00797   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00798   * @retval HAL status
00799   */
00800 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
00801 {
00802   HAL_StatusTypeDef status = HAL_OK;
00803
00804   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00805   {
00806     switch (CallbackID)
00807     {
00808       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00809         hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
00810         break;
00811
00812       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00813         hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
00814         break;
00815
00816       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00817         hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
00818         break;
00819
00820       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00821         hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
00822         break;
00823
00824       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00825         hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
00826         break;
00827
00828       case HAL_FDCAN_MSPINIT_CB_ID :
00829         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00830         break;
00831
00832       case HAL_FDCAN_MSPDEINIT_CB_ID :
00833         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00834         break;
00835
00836       default :
00837         /* Update the error code */
00838         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00839
00840         /* Return error status */
00841         status =  HAL_ERROR;
00842         break;
00843     }
00844   }
00845   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00846   {
00847     switch (CallbackID)
00848     {
00849       case HAL_FDCAN_MSPINIT_CB_ID :
00850         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00851         break;
00852
00853       case HAL_FDCAN_MSPDEINIT_CB_ID :
00854         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00855         break;
00856
00857       default :
00858         /* Update the error code */
00859         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00860
00861         /* Return error status */
00862         status =  HAL_ERROR;
00863         break;
00864     }
00865   }
00866   else
00867   {
00868     /* Update the error code */
00869     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00870
00871     /* Return error status */
00872     status =  HAL_ERROR;
00873   }
00874
00875   return status;
00876 }
00877
00878 /**
00879   * @brief  Register Tx Event Fifo FDCAN Callback
00880   *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
00881   * @param  hfdcan FDCAN handle
00882   * @param  pCallback pointer to the Tx Event Fifo Callback function
00883   * @retval HAL status
00884   */
00885 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
00886                                                         pFDCAN_TxEventFifoCallbackTypeDef pCallback)
00887 {
00888   HAL_StatusTypeDef status = HAL_OK;
00889
00890   if (pCallback == NULL)
00891   {
00892     /* Update the error code */
00893     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00894     return HAL_ERROR;
00895   }
00896
00897   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00898   {
00899     hfdcan->TxEventFifoCallback = pCallback;
00900   }
00901   else
00902   {
00903     /* Update the error code */
00904     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00905
00906     /* Return error status */
00907     status =  HAL_ERROR;
00908   }
00909
00910   return status;
00911 }
00912
00913 /**
00914   * @brief  UnRegister the Tx Event Fifo FDCAN Callback
00915   *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
00916   * @param  hfdcan FDCAN handle
00917   * @retval HAL status
00918   */
00919 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
00920 {
00921   HAL_StatusTypeDef status = HAL_OK;
00922
00923   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00924   {
00925     hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
00926   }
00927   else
00928   {
00929     /* Update the error code */
00930     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00931
00932     /* Return error status */
00933     status =  HAL_ERROR;
00934   }
00935
00936   return status;
00937 }
00938
00939 /**
00940   * @brief  Register Rx Fifo 0 FDCAN Callback
00941   *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
00942   * @param  hfdcan FDCAN handle
00943   * @param  pCallback pointer to the Rx Fifo 0 Callback function
00944   * @retval HAL status
00945   */
00946 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
00947                                                     pFDCAN_RxFifo0CallbackTypeDef pCallback)
00948 {
00949   HAL_StatusTypeDef status = HAL_OK;
00950
00951   if (pCallback == NULL)
00952   {
00953     /* Update the error code */
00954     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00955     return HAL_ERROR;
00956   }
00957
00958   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00959   {
00960     hfdcan->RxFifo0Callback = pCallback;
00961   }
00962   else
00963   {
00964     /* Update the error code */
00965     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00966
00967     /* Return error status */
00968     status =  HAL_ERROR;
00969   }
00970
00971   return status;
00972 }
00973
00974 /**
00975   * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
00976   *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
00977   * @param  hfdcan FDCAN handle
00978   * @retval HAL status
00979   */
00980 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
00981 {
00982   HAL_StatusTypeDef status = HAL_OK;
00983
00984   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00985   {
00986     hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
00987   }
00988   else
00989   {
00990     /* Update the error code */
00991     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00992
00993     /* Return error status */
00994     status =  HAL_ERROR;
00995   }
00996
00997   return status;
00998 }
00999
01000 /**
01001   * @brief  Register Rx Fifo 1 FDCAN Callback
01002   *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01003   * @param  hfdcan FDCAN handle
01004   * @param  pCallback pointer to the Rx Fifo 1 Callback function
01005   * @retval HAL status
01006   */
01007 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
01008                                                     pFDCAN_RxFifo1CallbackTypeDef pCallback)
01009 {
01010   HAL_StatusTypeDef status = HAL_OK;
01011
01012   if (pCallback == NULL)
01013   {
01014     /* Update the error code */
01015     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01016     return HAL_ERROR;
01017   }
01018
01019   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01020   {
01021     hfdcan->RxFifo1Callback = pCallback;
01022   }
01023   else
01024   {
01025     /* Update the error code */
01026     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01027
01028     /* Return error status */
01029     status =  HAL_ERROR;
01030   }
01031
01032   return status;
01033 }
01034
01035 /**
01036   * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
01037   *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01038   * @param  hfdcan FDCAN handle
01039   * @retval HAL status
01040   */
01041 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
01042 {
01043   HAL_StatusTypeDef status = HAL_OK;
01044
01045   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01046   {
01047     hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
01048   }
01049   else
01050   {
01051     /* Update the error code */
01052     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01053
01054     /* Return error status */
01055     status =  HAL_ERROR;
01056   }
01057
01058   return status;
01059 }
01060
01061 /**
01062   * @brief  Register Tx Buffer Complete FDCAN Callback
01063   *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01064   * @param  hfdcan FDCAN handle
01065   * @param  pCallback pointer to the Tx Buffer Complete Callback function
01066   * @retval HAL status
01067   */
01068 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
01069                                                              pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
01070 {
01071   HAL_StatusTypeDef status = HAL_OK;
01072
01073   if (pCallback == NULL)
01074   {
01075     /* Update the error code */
01076     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01077     return HAL_ERROR;
01078   }
01079
01080   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01081   {
01082     hfdcan->TxBufferCompleteCallback = pCallback;
01083   }
01084   else
01085   {
01086     /* Update the error code */
01087     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01088
01089     /* Return error status */
01090     status =  HAL_ERROR;
01091   }
01092
01093   return status;
01094 }
01095
01096 /**
01097   * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
01098   *         Tx Buffer Complete FDCAN Callback is redirected to
01099   *         the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01100   * @param  hfdcan FDCAN handle
01101   * @retval HAL status
01102   */
01103 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
01104 {
01105   HAL_StatusTypeDef status = HAL_OK;
01106
01107   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01108   {
01109     hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
01110   }
01111   else
01112   {
01113     /* Update the error code */
01114     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01115
01116     /* Return error status */
01117     status =  HAL_ERROR;
01118   }
01119
01120   return status;
01121 }
01122
01123 /**
01124   * @brief  Register Tx Buffer Abort FDCAN Callback
01125   *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01126   * @param  hfdcan FDCAN handle
01127   * @param  pCallback pointer to the Tx Buffer Abort Callback function
01128   * @retval HAL status
01129   */
01130 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
01131                                                           pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
01132 {
01133   HAL_StatusTypeDef status = HAL_OK;
01134
01135   if (pCallback == NULL)
01136   {
01137     /* Update the error code */
01138     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01139     return HAL_ERROR;
01140   }
01141
01142   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01143   {
01144     hfdcan->TxBufferAbortCallback = pCallback;
01145   }
01146   else
01147   {
01148     /* Update the error code */
01149     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01150
01151     /* Return error status */
01152     status =  HAL_ERROR;
01153   }
01154
01155   return status;
01156 }
01157
01158 /**
01159   * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
01160   *         Tx Buffer Abort FDCAN Callback is redirected to
01161   *         the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01162   * @param  hfdcan FDCAN handle
01163   * @retval HAL status
01164   */
01165 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
01166 {
01167   HAL_StatusTypeDef status = HAL_OK;
01168
01169   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01170   {
01171     hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
01172   }
01173   else
01174   {
01175     /* Update the error code */
01176     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01177
01178     /* Return error status */
01179     status =  HAL_ERROR;
01180   }
01181
01182   return status;
01183 }
01184
01185 /**
01186   * @brief  Register Error Status FDCAN Callback
01187   *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01188   * @param  hfdcan FDCAN handle
01189   * @param  pCallback pointer to the Error Status Callback function
01190   * @retval HAL status
01191   */
01192 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
01193                                                         pFDCAN_ErrorStatusCallbackTypeDef pCallback)
01194 {
01195   HAL_StatusTypeDef status = HAL_OK;
01196
01197   if (pCallback == NULL)
01198   {
01199     /* Update the error code */
01200     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01201     return HAL_ERROR;
01202   }
01203
01204   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01205   {
01206     hfdcan->ErrorStatusCallback = pCallback;
01207   }
01208   else
01209   {
01210     /* Update the error code */
01211     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01212
01213     /* Return error status */
01214     status =  HAL_ERROR;
01215   }
01216
01217   return status;
01218 }
01219
01220 /**
01221   * @brief  UnRegister the Error Status FDCAN Callback
01222   *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01223   * @param  hfdcan FDCAN handle
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
01227 {
01228   HAL_StatusTypeDef status = HAL_OK;
01229
01230   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01231   {
01232     hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
01233   }
01234   else
01235   {
01236     /* Update the error code */
01237     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01238
01239     /* Return error status */
01240     status =  HAL_ERROR;
01241   }
01242
01243   return status;
01244 }
01245
01246 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01247
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
01253   *  @brief    FDCAN Configuration functions.
01254   *
01255 @verbatim
01256   ==============================================================================
01257               ##### Configuration functions #####
01258   ==============================================================================
01259     [..]  This section provides functions allowing to:
01260       (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
01261       (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
01262       (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
01263       (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
01264       (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
01265       (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
01266         (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
01267         (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
01268         (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
01269         (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
01270       (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
01271         (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
01272         (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
01273         (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
01274         (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
01275       (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
01276         (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
01277         (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
01278       (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
01279       (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
01280       (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
01281       (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
01282
01283 @endverbatim
01284   * @{
01285   */
01286
01287 /**
01288   * @brief  Configure the FDCAN reception filter according to the specified
01289   *         parameters in the FDCAN_FilterTypeDef structure.
01290   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01291   *         the configuration information for the specified FDCAN.
01292   * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
01293   *         contains the filter configuration information
01294   * @retval HAL status
01295   */
01296 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
01297 {
01298   uint32_t FilterElementW1;
01299   uint32_t FilterElementW2;
01300   uint32_t *FilterAddress;
01301   HAL_FDCAN_StateTypeDef state = hfdcan->State;
01302
01303   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
01304   {
01305     /* Check function parameters */
01306     assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
01307     assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
01308
01309     if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
01310     {
01311       /* Check function parameters */
01312       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
01313       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
01314       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
01315       assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
01316
01317       /* Build filter element */
01318       FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
01319                          (sFilterConfig->FilterConfig << 27U) |
01320                          (sFilterConfig->FilterID1 << 16U)    |
01321                          sFilterConfig->FilterID2);
01322
01323       /* Calculate filter address */
01324       FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
01325
01326       /* Write filter element to the message RAM */
01327       *FilterAddress = FilterElementW1;
01328     }
01329     else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
01330     {
01331       /* Check function parameters */
01332       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
01333       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
01334       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
01335       assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
01336
01337       /* Build first word of filter element */
01338       FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
01339
01340       /* Build second word of filter element */
01341       FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
01342
01343       /* Calculate filter address */
01344       FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
01345
01346       /* Write filter element to the message RAM */
01347       *FilterAddress = FilterElementW1;
01348       FilterAddress++;
01349       *FilterAddress = FilterElementW2;
01350     }
01351
01352     /* Return function status */
01353     return HAL_OK;
01354   }
01355   else
01356   {
01357     /* Update error code */
01358     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01359
01360     return HAL_ERROR;
01361   }
01362 }
01363
01364 /**
01365   * @brief  Configure the FDCAN global filter.
01366   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01367   *         the configuration information for the specified FDCAN.
01368   * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
01369   *         do not match any element of the filter list are treated.
01370   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01371   * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
01372   *         do not match any element of the filter list are treated.
01373   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01374   * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
01375   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01376   * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
01377   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
01381                                                uint32_t NonMatchingStd,
01382                                                uint32_t NonMatchingExt,
01383                                                uint32_t RejectRemoteStd,
01384                                                uint32_t RejectRemoteExt)
01385 {
01386   /* Check function parameters */
01387   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
01388   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
01389   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
01390   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
01391
01392   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01393   {
01394     /* Configure global filter */
01395     MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS |
01396                                          FDCAN_RXGFC_ANFE |
01397                                          FDCAN_RXGFC_RRFS |
01398                                          FDCAN_RXGFC_RRFE),
01399                ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos)  |
01400                 (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos)  |
01401                 (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
01402                 (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
01403
01404     /* Return function status */
01405     return HAL_OK;
01406   }
01407   else
01408   {
01409     /* Update error code */
01410     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01411
01412     return HAL_ERROR;
01413   }
01414 }
01415
01416 /**
01417   * @brief  Configure the extended ID mask.
01418   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01419   *         the configuration information for the specified FDCAN.
01420   * @param  Mask Extended ID Mask.
01421   *         This parameter must be a number between 0 and 0x1FFFFFFF.
01422   * @retval HAL status
01423   */
01424 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
01425 {
01426   /* Check function parameters */
01427   assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
01428
01429   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01430   {
01431     /* Configure the extended ID mask */
01432     hfdcan->Instance->XIDAM = Mask;
01433
01434     /* Return function status */
01435     return HAL_OK;
01436   }
01437   else
01438   {
01439     /* Update error code */
01440     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01441
01442     return HAL_ERROR;
01443   }
01444 }
01445
01446 /**
01447   * @brief  Configure the Rx FIFO operation mode.
01448   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01449   *         the configuration information for the specified FDCAN.
01450   * @param  RxFifo Rx FIFO.
01451   *         This parameter can be one of the following values:
01452   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
01453   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
01454   * @param  OperationMode operation mode.
01455   *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
01456   * @retval HAL status
01457   */
01458 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
01459 {
01460   /* Check function parameters */
01461   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
01462   assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
01463
01464   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01465   {
01466     if (RxFifo == FDCAN_RX_FIFO0)
01467     {
01468       /* Select FIFO 0 Operation Mode */
01469       MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos));
01470     }
01471     else /* RxFifo == FDCAN_RX_FIFO1 */
01472     {
01473       /* Select FIFO 1 Operation Mode */
01474       MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos));
01475     }
01476
01477     /* Return function status */
01478     return HAL_OK;
01479   }
01480   else
01481   {
01482     /* Update error code */
01483     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01484
01485     return HAL_ERROR;
01486   }
01487 }
01488
01489 /**
01490   * @brief  Configure the RAM watchdog.
01491   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01492   *         the configuration information for the specified FDCAN.
01493   * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
01494   *         This parameter must be a number between 0x00 and 0xFF,
01495   *         with the reset value of 0x00 the counter is disabled.
01496   * @retval HAL status
01497   */
01498 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
01499 {
01500   /* Check function parameters */
01501   assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
01502
01503   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01504   {
01505     /* Configure the RAM watchdog counter start value */
01506     MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
01507
01508     /* Return function status */
01509     return HAL_OK;
01510   }
01511   else
01512   {
01513     /* Update error code */
01514     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01515
01516     return HAL_ERROR;
01517   }
01518 }
01519
01520 /**
01521   * @brief  Configure the timestamp counter.
01522   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01523   *         the configuration information for the specified FDCAN.
01524   * @param  TimestampPrescaler Timestamp Counter Prescaler.
01525   *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
01526   * @retval HAL status
01527   */
01528 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
01529 {
01530   /* Check function parameters */
01531   assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
01532
01533   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01534   {
01535     /* Configure prescaler */
01536     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
01537
01538     /* Return function status */
01539     return HAL_OK;
01540   }
01541   else
01542   {
01543     /* Update error code */
01544     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01545
01546     return HAL_ERROR;
01547   }
01548 }
01549
01550 /**
01551   * @brief  Enable the timestamp counter.
01552   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01553   *         the configuration information for the specified FDCAN.
01554   * @param  TimestampOperation Timestamp counter operation.
01555   *         This parameter can be a value of @arg FDCAN_Timestamp.
01556   * @retval HAL status
01557   */
01558 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
01559 {
01560   /* Check function parameters */
01561   assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
01562
01563   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01564   {
01565     /* Enable timestamp counter */
01566     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
01567
01568     /* Return function status */
01569     return HAL_OK;
01570   }
01571   else
01572   {
01573     /* Update error code */
01574     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01575
01576     return HAL_ERROR;
01577   }
01578 }
01579
01580 /**
01581   * @brief  Disable the timestamp counter.
01582   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01583   *         the configuration information for the specified FDCAN.
01584   * @retval HAL status
01585   */
01586 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01587 {
01588   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01589   {
01590     /* Disable timestamp counter */
01591     CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
01592
01593     /* Return function status */
01594     return HAL_OK;
01595   }
01596   else
01597   {
01598     /* Update error code */
01599     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01600
01601     return HAL_ERROR;
01602   }
01603 }
01604
01605 /**
01606   * @brief  Get the timestamp counter value.
01607   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01608   *         the configuration information for the specified FDCAN.
01609   * @retval Timestamp counter value
01610   */
01611 uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
01612 {
01613   return (uint16_t)(hfdcan->Instance->TSCV);
01614 }
01615
01616 /**
01617   * @brief  Reset the timestamp counter to zero.
01618   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01619   *         the configuration information for the specified FDCAN.
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01623 {
01624   if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
01625   {
01626     /* Reset timestamp counter.
01627        Actually any write operation to TSCV clears the counter */
01628     CLEAR_REG(hfdcan->Instance->TSCV);
01629   }
01630   else
01631   {
01632     /* Update error code.
01633        Unable to reset external counter */
01634     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01635
01636     return HAL_ERROR;
01637   }
01638
01639   /* Return function status */
01640   return HAL_OK;
01641 }
01642
01643 /**
01644   * @brief  Configure the timeout counter.
01645   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01646   *         the configuration information for the specified FDCAN.
01647   * @param  TimeoutOperation Timeout counter operation.
01648   *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
01649   * @param  TimeoutPeriod Start value of the timeout down-counter.
01650   *         This parameter must be a number between 0x0000 and 0xFFFF
01651   * @retval HAL status
01652   */
01653 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
01654                                                  uint32_t TimeoutPeriod)
01655 {
01656   /* Check function parameters */
01657   assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
01658   assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
01659
01660   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01661   {
01662     /* Select timeout operation and configure period */
01663     MODIFY_REG(hfdcan->Instance->TOCC,
01664                (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
01665
01666     /* Return function status */
01667     return HAL_OK;
01668   }
01669   else
01670   {
01671     /* Update error code */
01672     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01673
01674     return HAL_ERROR;
01675   }
01676 }
01677
01678 /**
01679   * @brief  Enable the timeout counter.
01680   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01681   *         the configuration information for the specified FDCAN.
01682   * @retval HAL status
01683   */
01684 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01685 {
01686   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01687   {
01688     /* Enable timeout counter */
01689     SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01690
01691     /* Return function status */
01692     return HAL_OK;
01693   }
01694   else
01695   {
01696     /* Update error code */
01697     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01698
01699     return HAL_ERROR;
01700   }
01701 }
01702
01703 /**
01704   * @brief  Disable the timeout counter.
01705   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01706   *         the configuration information for the specified FDCAN.
01707   * @retval HAL status
01708   */
01709 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01710 {
01711   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01712   {
01713     /* Disable timeout counter */
01714     CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01715
01716     /* Return function status */
01717     return HAL_OK;
01718   }
01719   else
01720   {
01721     /* Update error code */
01722     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01723
01724     return HAL_ERROR;
01725   }
01726 }
01727
01728 /**
01729   * @brief  Get the timeout counter value.
01730   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01731   *         the configuration information for the specified FDCAN.
01732   * @retval Timeout counter value
01733   */
01734 uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
01735 {
01736   return (uint16_t)(hfdcan->Instance->TOCV);
01737 }
01738
01739 /**
01740   * @brief  Reset the timeout counter to its start value.
01741   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01742   *         the configuration information for the specified FDCAN.
01743   * @retval HAL status
01744   */
01745 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01746 {
01747   if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
01748   {
01749     /* Reset timeout counter to start value */
01750     CLEAR_REG(hfdcan->Instance->TOCV);
01751
01752     /* Return function status */
01753     return HAL_OK;
01754   }
01755   else
01756   {
01757     /* Update error code.
01758        Unable to reset counter: controlled only by FIFO empty state */
01759     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01760
01761     return HAL_ERROR;
01762   }
01763 }
01764
01765 /**
01766   * @brief  Configure the transmitter delay compensation.
01767   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01768   *         the configuration information for the specified FDCAN.
01769   * @param  TdcOffset Transmitter Delay Compensation Offset.
01770   *         This parameter must be a number between 0x00 and 0x7F.
01771   * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
01772   *         This parameter must be a number between 0x00 and 0x7F.
01773   * @retval HAL status
01774   */
01775 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
01776                                                       uint32_t TdcFilter)
01777 {
01778   /* Check function parameters */
01779   assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
01780   assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
01781
01782   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01783   {
01784     /* Configure TDC offset and filter window */
01785     hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
01786
01787     /* Return function status */
01788     return HAL_OK;
01789   }
01790   else
01791   {
01792     /* Update error code */
01793     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01794
01795     return HAL_ERROR;
01796   }
01797 }
01798
01799 /**
01800   * @brief  Enable the transmitter delay compensation.
01801   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01802   *         the configuration information for the specified FDCAN.
01803   * @retval HAL status
01804   */
01805 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01806 {
01807   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01808   {
01809     /* Enable transmitter delay compensation */
01810     SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01811
01812     /* Return function status */
01813     return HAL_OK;
01814   }
01815   else
01816   {
01817     /* Update error code */
01818     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01819
01820     return HAL_ERROR;
01821   }
01822 }
01823
01824 /**
01825   * @brief  Disable the transmitter delay compensation.
01826   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01827   *         the configuration information for the specified FDCAN.
01828   * @retval HAL status
01829   */
01830 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01831 {
01832   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01833   {
01834     /* Disable transmitter delay compensation */
01835     CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01836
01837     /* Return function status */
01838     return HAL_OK;
01839   }
01840   else
01841   {
01842     /* Update error code */
01843     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01844
01845     return HAL_ERROR;
01846   }
01847 }
01848
01849 /**
01850   * @brief  Enable ISO 11898-1 protocol mode.
01851   *         CAN FD frame format is according to ISO 11898-1 standard.
01852   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01853   *         the configuration information for the specified FDCAN.
01854   * @retval HAL status
01855   */
01856 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
01857 {
01858   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01859   {
01860     /* Disable Non ISO protocol mode */
01861     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
01862
01863     /* Return function status */
01864     return HAL_OK;
01865   }
01866   else
01867   {
01868     /* Update error code */
01869     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01870
01871     return HAL_ERROR;
01872   }
01873 }
01874
01875 /**
01876   * @brief  Disable ISO 11898-1 protocol mode.
01877   *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
01878   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01879   *         the configuration information for the specified FDCAN.
01880   * @retval HAL status
01881   */
01882 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
01883 {
01884   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01885   {
01886     /* Enable Non ISO protocol mode */
01887     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
01888
01889     /* Return function status */
01890     return HAL_OK;
01891   }
01892   else
01893   {
01894     /* Update error code */
01895     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01896
01897     return HAL_ERROR;
01898   }
01899 }
01900
01901 /**
01902   * @brief  Enable edge filtering during bus integration.
01903   *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
01904   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01905   *         the configuration information for the specified FDCAN.
01906   * @retval HAL status
01907   */
01908 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
01909 {
01910   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01911   {
01912     /* Enable edge filtering */
01913     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
01914
01915     /* Return function status */
01916     return HAL_OK;
01917   }
01918   else
01919   {
01920     /* Update error code */
01921     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01922
01923     return HAL_ERROR;
01924   }
01925 }
01926
01927 /**
01928   * @brief  Disable edge filtering during bus integration.
01929   *         One dominant tq is required to detect an edge for hard synchronization.
01930   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01931   *         the configuration information for the specified FDCAN.
01932   * @retval HAL status
01933   */
01934 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
01935 {
01936   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01937   {
01938     /* Disable edge filtering */
01939     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
01940
01941     /* Return function status */
01942     return HAL_OK;
01943   }
01944   else
01945   {
01946     /* Update error code */
01947     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01948
01949     return HAL_ERROR;
01950   }
01951 }
01952
01953 /**
01954   * @}
01955   */
01956
01957 /** @defgroup FDCAN_Exported_Functions_Group3 Control functions
01958   *  @brief    Control functions
01959   *
01960 @verbatim
01961   ==============================================================================
01962                           ##### Control functions #####
01963   ==============================================================================
01964     [..]  This section provides functions allowing to:
01965       (+) HAL_FDCAN_Start                         : Start the FDCAN module
01966       (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
01967       (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
01968                                                     transmission request
01969       (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
01970       (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
01971       (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx FIFO zone into the message RAM
01972       (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
01973                                                     into the message RAM
01974       (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
01975       (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
01976       (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
01977       (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
01978                                                     on the selected Tx buffer
01979       (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
01980       (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
01981       (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
01982       (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
01983
01984 @endverbatim
01985   * @{
01986   */
01987
01988 /**
01989   * @brief  Start the FDCAN module.
01990   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01991   *         the configuration information for the specified FDCAN.
01992   * @retval HAL status
01993   */
01994 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
01995 {
01996   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01997   {
01998     /* Change FDCAN peripheral state */
01999     hfdcan->State = HAL_FDCAN_STATE_BUSY;
02000
02001     /* Request leave initialisation */
02002     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02003
02004     /* Reset the FDCAN ErrorCode */
02005     hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
02006
02007     /* Return function status */
02008     return HAL_OK;
02009   }
02010   else
02011   {
02012     /* Update error code */
02013     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02014
02015     return HAL_ERROR;
02016   }
02017 }
02018
02019 /**
02020   * @brief  Stop the FDCAN module and enable access to configuration registers.
02021   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02022   *         the configuration information for the specified FDCAN.
02023   * @retval HAL status
02024   */
02025 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
02026 {
02027   uint32_t Counter = 0U;
02028
02029   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02030   {
02031     /* Request initialisation */
02032     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02033
02034     /* Wait until the INIT bit into CCCR register is set */
02035     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
02036     {
02037       /* Check for the Timeout */
02038       if (Counter > FDCAN_TIMEOUT_VALUE)
02039       {
02040         /* Update error code */
02041         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02042
02043         /* Change FDCAN state */
02044         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02045
02046         return HAL_ERROR;
02047       }
02048
02049       /* Increment counter */
02050       Counter++;
02051     }
02052
02053     /* Reset counter */
02054     Counter = 0U;
02055
02056     /* Exit from Sleep mode */
02057     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
02058
02059     /* Wait until FDCAN exits sleep mode */
02060     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
02061     {
02062       /* Check for the Timeout */
02063       if (Counter > FDCAN_TIMEOUT_VALUE)
02064       {
02065         /* Update error code */
02066         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02067
02068         /* Change FDCAN state */
02069         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02070
02071         return HAL_ERROR;
02072       }
02073
02074       /* Increment counter */
02075       Counter++;
02076     }
02077
02078     /* Enable configuration change */
02079     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
02080
02081     /* Reset Latest Tx FIFO/Queue Request Buffer Index */
02082     hfdcan->LatestTxFifoQRequest = 0U;
02083
02084     /* Change FDCAN peripheral state */
02085     hfdcan->State = HAL_FDCAN_STATE_READY;
02086
02087     /* Return function status */
02088     return HAL_OK;
02089   }
02090   else
02091   {
02092     /* Update error code */
02093     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02094
02095     return HAL_ERROR;
02096   }
02097 }
02098
02099 /**
02100   * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
02101   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02102   *         the configuration information for the specified FDCAN.
02103   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
02104   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
02105   * @retval HAL status
02106   */
02107 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
02108                                                 const uint8_t *pTxData)
02109 {
02110   uint32_t PutIndex;
02111
02112   /* Check function parameters */
02113   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
02114   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
02115   {
02116     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
02117   }
02118   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
02119   {
02120     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
02121   }
02122   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
02123   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
02124   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
02125   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
02126   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
02127   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
02128   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
02129
02130   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02131   {
02132     /* Check that the Tx FIFO/Queue is not full */
02133     if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
02134     {
02135       /* Update error code */
02136       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
02137
02138       return HAL_ERROR;
02139     }
02140     else
02141     {
02142       /* Retrieve the Tx FIFO PutIndex */
02143       PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
02144
02145       /* Add the message to the Tx FIFO/Queue */
02146       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
02147
02148       /* Activate the corresponding transmission request */
02149       hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
02150
02151       /* Store the Latest Tx FIFO/Queue Request Buffer Index */
02152       hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
02153     }
02154
02155     /* Return function status */
02156     return HAL_OK;
02157   }
02158   else
02159   {
02160     /* Update error code */
02161     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02162
02163     return HAL_ERROR;
02164   }
02165 }
02166
02167 /**
02168   * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
02169   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02170   *         the configuration information for the specified FDCAN.
02171   * @retval Tx buffer index of last Tx FIFO/Queue request
02172   *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
02173   *          - 0 if no Tx FIFO/Queue request have been submitted.
02174   */
02175 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan)
02176 {
02177   /* Return Last Tx FIFO/Queue Request Buffer */
02178   return hfdcan->LatestTxFifoQRequest;
02179 }
02180
02181 /**
02182   * @brief  Abort transmission request
02183   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02184   *         the configuration information for the specified FDCAN.
02185   * @param  BufferIndex buffer index.
02186   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02187   * @retval HAL status
02188   */
02189 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
02190 {
02191   /* Check function parameters */
02192   assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
02193
02194   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02195   {
02196     /* Add cancellation request */
02197     hfdcan->Instance->TXBCR = BufferIndex;
02198
02199     /* Return function status */
02200     return HAL_OK;
02201   }
02202   else
02203   {
02204     /* Update error code */
02205     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02206
02207     return HAL_ERROR;
02208   }
02209 }
02210
02211 /**
02212   * @brief  Get an FDCAN frame from the Rx FIFO zone into the message RAM.
02213   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02214   *         the configuration information for the specified FDCAN.
02215   * @param  RxLocation Location of the received message to be read.
02216   *         This parameter can be a value of @arg FDCAN_Rx_location.
02217   * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
02218   * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
02219   * @retval HAL status
02220   */
02221 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
02222                                          FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
02223 {
02224   uint32_t *RxAddress;
02225   uint8_t  *pData;
02226   uint32_t ByteCounter;
02227   uint32_t GetIndex = 0;
02228   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02229
02230   /* Check function parameters */
02231   assert_param(IS_FDCAN_RX_FIFO(RxLocation));
02232
02233   if (state == HAL_FDCAN_STATE_BUSY)
02234   {
02235     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
02236     {
02237       /* Check that the Rx FIFO 0 is not empty */
02238       if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
02239       {
02240         /* Update error code */
02241         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02242
02243         return HAL_ERROR;
02244       }
02245       else
02246       {
02247         /* Check that the Rx FIFO 0 is full & overwrite mode is on */
02248         if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
02249         {
02250           if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
02251           {
02252             /* When overwrite status is on discard first message in FIFO */
02253             GetIndex = 1U;
02254           }
02255         }
02256
02257         /* Calculate Rx FIFO 0 element index */
02258         GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
02259
02260         /* Calculate Rx FIFO 0 element address */
02261         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
02262       }
02263     }
02264     else /* Rx element is assigned to the Rx FIFO 1 */
02265     {
02266       /* Check that the Rx FIFO 1 is not empty */
02267       if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
02268       {
02269         /* Update error code */
02270         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02271
02272         return HAL_ERROR;
02273       }
02274       else
02275       {
02276         /* Check that the Rx FIFO 1 is full & overwrite mode is on */
02277         if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
02278         {
02279           if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
02280           {
02281             /* When overwrite status is on discard first message in FIFO */
02282             GetIndex = 1U;
02283           }
02284         }
02285
02286         /* Calculate Rx FIFO 1 element index */
02287         GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
02288         /* Calculate Rx FIFO 1 element address */
02289         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
02290       }
02291     }
02292
02293     /* Retrieve IdType */
02294     pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
02295
02296     /* Retrieve Identifier */
02297     if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
02298     {
02299       pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
02300     }
02301     else /* Extended ID element */
02302     {
02303       pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
02304     }
02305
02306     /* Retrieve RxFrameType */
02307     pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
02308
02309     /* Retrieve ErrorStateIndicator */
02310     pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
02311
02312     /* Increment RxAddress pointer to second word of Rx FIFO element */
02313     RxAddress++;
02314
02315     /* Retrieve RxTimestamp */
02316     pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
02317
02318     /* Retrieve DataLength */
02319     pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
02320
02321     /* Retrieve BitRateSwitch */
02322     pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
02323
02324     /* Retrieve FDFormat */
02325     pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
02326
02327     /* Retrieve FilterIndex */
02328     pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
02329
02330     /* Retrieve NonMatchingFrame */
02331     pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
02332
02333     /* Increment RxAddress pointer to payload of Rx FIFO element */
02334     RxAddress++;
02335
02336     /* Retrieve Rx payload */
02337     pData = (uint8_t *)RxAddress;
02338     for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
02339     {
02340       pRxData[ByteCounter] = pData[ByteCounter];
02341     }
02342
02343     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
02344     {
02345       /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
02346       hfdcan->Instance->RXF0A = GetIndex;
02347     }
02348     else /* Rx element is assigned to the Rx FIFO 1 */
02349     {
02350       /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
02351       hfdcan->Instance->RXF1A = GetIndex;
02352     }
02353
02354     /* Return function status */
02355     return HAL_OK;
02356   }
02357   else
02358   {
02359     /* Update error code */
02360     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02361
02362     return HAL_ERROR;
02363   }
02364 }
02365
02366 /**
02367   * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
02368   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02369   *         the configuration information for the specified FDCAN.
02370   * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
02371   * @retval HAL status
02372   */
02373 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
02374 {
02375   uint32_t *TxEventAddress;
02376   uint32_t GetIndex;
02377   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02378
02379   if (state == HAL_FDCAN_STATE_BUSY)
02380   {
02381     /* Check that the Tx event FIFO is not empty */
02382     if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
02383     {
02384       /* Update error code */
02385       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02386
02387       return HAL_ERROR;
02388     }
02389
02390     /* Calculate Tx event FIFO element address */
02391     GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
02392     TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE));
02393
02394     /* Retrieve IdType */
02395     pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
02396
02397     /* Retrieve Identifier */
02398     if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
02399     {
02400       pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
02401     }
02402     else /* Extended ID element */
02403     {
02404       pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
02405     }
02406
02407     /* Retrieve TxFrameType */
02408     pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
02409
02410     /* Retrieve ErrorStateIndicator */
02411     pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
02412
02413     /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
02414     TxEventAddress++;
02415
02416     /* Retrieve TxTimestamp */
02417     pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
02418
02419     /* Retrieve DataLength */
02420     pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
02421
02422     /* Retrieve BitRateSwitch */
02423     pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
02424
02425     /* Retrieve FDFormat */
02426     pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
02427
02428     /* Retrieve EventType */
02429     pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
02430
02431     /* Retrieve MessageMarker */
02432     pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
02433
02434     /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
02435     hfdcan->Instance->TXEFA = GetIndex;
02436
02437     /* Return function status */
02438     return HAL_OK;
02439   }
02440   else
02441   {
02442     /* Update error code */
02443     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02444
02445     return HAL_ERROR;
02446   }
02447 }
02448
02449 /**
02450   * @brief  Get high priority message status.
02451   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02452   *         the configuration information for the specified FDCAN.
02453   * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
02454   * @retval HAL status
02455   */
02456 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
02457                                                          FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
02458 {
02459   HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
02460   HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
02461   HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
02462   HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
02463
02464   /* Return function status */
02465   return HAL_OK;
02466 }
02467
02468 /**
02469   * @brief  Get protocol status.
02470   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02471   *         the configuration information for the specified FDCAN.
02472   * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
02473   * @retval HAL status
02474   */
02475 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
02476                                               FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
02477 {
02478   uint32_t StatusReg;
02479
02480   /* Read the protocol status register */
02481   StatusReg = READ_REG(hfdcan->Instance->PSR);
02482
02483   /* Fill the protocol status structure */
02484   ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
02485   ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
02486   ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
02487   ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
02488   ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
02489   ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
02490   ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
02491   ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
02492   ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
02493   ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
02494   ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
02495
02496   /* Return function status */
02497   return HAL_OK;
02498 }
02499
02500 /**
02501   * @brief  Get error counter values.
02502   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02503   *         the configuration information for the specified FDCAN.
02504   * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
02505   * @retval HAL status
02506   */
02507 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
02508                                              FDCAN_ErrorCountersTypeDef *ErrorCounters)
02509 {
02510   uint32_t CountersReg;
02511
02512   /* Read the error counters register */
02513   CountersReg = READ_REG(hfdcan->Instance->ECR);
02514
02515   /* Fill the error counters structure */
02516   ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
02517   ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
02518   ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
02519   ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
02520
02521   /* Return function status */
02522   return HAL_OK;
02523 }
02524
02525 /**
02526   * @brief  Check if a transmission request is pending on the selected Tx buffer.
02527   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02528   *         the configuration information for the specified FDCAN.
02529   * @param  TxBufferIndex Tx buffer index.
02530   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02531   * @retval Status
02532   *          - 0 : No pending transmission request on TxBufferIndex list.
02533   *          - 1 : Pending transmission request on TxBufferIndex.
02534   */
02535 uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
02536 {
02537   /* Check function parameters */
02538   assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
02539
02540   /* Check pending transmission request on the selected buffer */
02541   if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
02542   {
02543     return 0;
02544   }
02545   return 1;
02546 }
02547
02548 /**
02549   * @brief  Return Rx FIFO fill level.
02550   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02551   *         the configuration information for the specified FDCAN.
02552   * @param  RxFifo Rx FIFO.
02553   *         This parameter can be one of the following values:
02554   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
02555   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
02556   * @retval Rx FIFO fill level.
02557   */
02558 uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
02559 {
02560   uint32_t FillLevel;
02561
02562   /* Check function parameters */
02563   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
02564
02565   if (RxFifo == FDCAN_RX_FIFO0)
02566   {
02567     FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
02568   }
02569   else /* RxFifo == FDCAN_RX_FIFO1 */
02570   {
02571     FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
02572   }
02573
02574   /* Return Rx FIFO fill level */
02575   return FillLevel;
02576 }
02577
02578 /**
02579   * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
02580   *         elements starting from Tx FIFO GetIndex.
02581   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02582   *         the configuration information for the specified FDCAN.
02583   * @retval Tx FIFO free level.
02584   */
02585 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
02586 {
02587   uint32_t FreeLevel;
02588
02589   FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
02590
02591   /* Return Tx FIFO free level */
02592   return FreeLevel;
02593 }
02594
02595 /**
02596   * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
02597   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02598   *         the configuration information for the specified FDCAN.
02599   * @retval Status
02600   *          - 0 : Normal FDCAN operation.
02601   *          - 1 : Restricted Operation Mode active.
02602   */
02603 uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan)
02604 {
02605   uint32_t OperationMode;
02606
02607   /* Get Operation Mode */
02608   OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
02609
02610   return OperationMode;
02611 }
02612
02613 /**
02614   * @brief  Exit Restricted Operation Mode.
02615   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02616   *         the configuration information for the specified FDCAN.
02617   * @retval HAL status
02618   */
02619 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
02620 {
02621   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02622
02623   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02624   {
02625     /* Exit Restricted Operation mode */
02626     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
02627
02628     /* Return function status */
02629     return HAL_OK;
02630   }
02631   else
02632   {
02633     /* Update error code */
02634     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02635
02636     return HAL_ERROR;
02637   }
02638 }
02639
02640 /**
02641   * @}
02642   */
02643
02644 /** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
02645   *  @brief    Interrupts management
02646   *
02647 @verbatim
02648   ==============================================================================
02649                        ##### Interrupts management #####
02650   ==============================================================================
02651     [..]  This section provides functions allowing to:
02652       (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
02653       (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
02654       (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
02655       (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
02656
02657 @endverbatim
02658   * @{
02659   */
02660
02661 /**
02662   * @brief  Assign interrupts to either Interrupt line 0 or 1.
02663   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02664   *         the configuration information for the specified FDCAN.
02665   * @param  ITList indicates which interrupts group will be assigned to the selected interrupt line.
02666   *         This parameter can be any combination of @arg FDCAN_Interrupts_Group.
02667   * @param  InterruptLine Interrupt line.
02668   *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
02669   * @retval HAL status
02670   */
02671 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
02672 {
02673   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02674
02675   /* Check function parameters */
02676   assert_param(IS_FDCAN_IT_GROUP(ITList));
02677   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
02678
02679   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02680   {
02681     /* Assign list of interrupts to the selected line */
02682     if (InterruptLine == FDCAN_INTERRUPT_LINE0)
02683     {
02684       CLEAR_BIT(hfdcan->Instance->ILS, ITList);
02685     }
02686     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
02687     {
02688       SET_BIT(hfdcan->Instance->ILS, ITList);
02689     }
02690
02691     /* Return function status */
02692     return HAL_OK;
02693   }
02694   else
02695   {
02696     /* Update error code */
02697     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02698
02699     return HAL_ERROR;
02700   }
02701 }
02702
02703 /**
02704   * @brief  Enable interrupts.
02705   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02706   *         the configuration information for the specified FDCAN.
02707   * @param  ActiveITs indicates which interrupts will be enabled.
02708   *         This parameter can be any combination of @arg FDCAN_Interrupts.
02709   * @param  BufferIndexes Tx Buffer Indexes.
02710   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02711   *         This parameter is ignored if ActiveITs does not include one of the following:
02712   *           - FDCAN_IT_TX_COMPLETE
02713   *           - FDCAN_IT_TX_ABORT_COMPLETE
02714   * @retval HAL status
02715   */
02716 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
02717                                                  uint32_t BufferIndexes)
02718 {
02719   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02720   uint32_t ITs_lines_selection;
02721
02722   /* Check function parameters */
02723   assert_param(IS_FDCAN_IT(ActiveITs));
02724   if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U)
02725   {
02726     assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
02727   }
02728
02729   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02730   {
02731     /* Get interrupts line selection */
02732     ITs_lines_selection = hfdcan->Instance->ILS;
02733
02734     /* Enable Interrupt lines */
02735     if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
02736          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
02737         (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02738          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
02739         (((ActiveITs & FDCAN_IT_LIST_SMSG)           != 0U)
02740          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)     == 0U)) || \
02741         (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02742          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  == 0U)) || \
02743         (((ActiveITs & FDCAN_IT_LIST_MISC)           != 0U)
02744          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           == 0U)) || \
02745         (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02746          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
02747         (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02748          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
02749     {
02750       /* Enable Interrupt line 0 */
02751       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
02752     }
02753     if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02754          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)      != 0U)) || \
02755         (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02756          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       != 0U)) || \
02757         (((ActiveITs & FDCAN_IT_LIST_SMSG)           != 0U)
02758          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           != 0U)) || \
02759         (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02760          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  != 0U)) || \
02761         (((ActiveITs & FDCAN_IT_LIST_MISC)           != 0U)
02762          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           != 0U)) || \
02763         (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02764          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
02765         (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02766          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
02767     {
02768       /* Enable Interrupt line 1 */
02769       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
02770     }
02771
02772     if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
02773     {
02774       /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
02775          but interrupt will only occur if TC is enabled in IE register */
02776       SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
02777     }
02778
02779     if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
02780     {
02781       /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
02782          but interrupt will only occur if TCF is enabled in IE register */
02783       SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
02784     }
02785
02786     /* Enable the selected interrupts */
02787     __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
02788
02789     /* Return function status */
02790     return HAL_OK;
02791   }
02792   else
02793   {
02794     /* Update error code */
02795     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02796
02797     return HAL_ERROR;
02798   }
02799 }
02800
02801 /**
02802   * @brief  Disable interrupts.
02803   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02804   *         the configuration information for the specified FDCAN.
02805   * @param  InactiveITs indicates which interrupts will be disabled.
02806   *         This parameter can be any combination of @arg FDCAN_Interrupts.
02807   * @retval HAL status
02808   */
02809 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
02810 {
02811   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02812   uint32_t ITs_enabled;
02813   uint32_t ITs_lines_selection;
02814
02815   /* Check function parameters */
02816   assert_param(IS_FDCAN_IT(InactiveITs));
02817
02818   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02819   {
02820     /* Disable the selected interrupts */
02821     __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
02822
02823     if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
02824     {
02825       /* Disable Tx Buffer Transmission Interrupts */
02826       CLEAR_REG(hfdcan->Instance->TXBTIE);
02827     }
02828
02829     if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
02830     {
02831       /* Disable Tx Buffer Cancellation Finished Interrupt */
02832       CLEAR_REG(hfdcan->Instance->TXBCIE);
02833     }
02834
02835     /* Get interrupts enabled and interrupts line selection */
02836     ITs_enabled = hfdcan->Instance->IE;
02837     ITs_lines_selection = hfdcan->Instance->ILS;
02838
02839     /* Check if some interrupts are still enabled on interrupt line 0 */
02840     if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02841          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)       == 0U)) || \
02842         (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02843          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       == 0U)) || \
02844         (((ITs_enabled & FDCAN_IT_LIST_SMSG)           != 0U)
02845          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           == 0U)) || \
02846         (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02847          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  == 0U)) || \
02848         (((ITs_enabled & FDCAN_IT_LIST_MISC)           != 0U)
02849          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           == 0U)) || \
02850         (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02851          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
02852         (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02853          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
02854     {
02855       /* Do nothing */
02856     }
02857     else /* no more interrupts enabled on interrupt line 0 */
02858     {
02859       /* Disable interrupt line 0 */
02860       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
02861     }
02862
02863     /* Check if some interrupts are still enabled on interrupt line 1 */
02864     if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02865          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)       != 0U)) || \
02866         (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02867          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       != 0U)) || \
02868         (((ITs_enabled & FDCAN_IT_LIST_SMSG)           != 0U)
02869          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           != 0U)) || \
02870         (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02871          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  != 0U)) || \
02872         (((ITs_enabled & FDCAN_IT_LIST_MISC)           != 0U)
02873          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           != 0U)) || \
02874         (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02875          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
02876         (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02877          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
02878     {
02879       /* Do nothing */
02880     }
02881     else /* no more interrupts enabled on interrupt line 1 */
02882     {
02883       /* Disable interrupt line 1 */
02884       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
02885     }
02886
02887     /* Return function status */
02888     return HAL_OK;
02889   }
02890   else
02891   {
02892     /* Update error code */
02893     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02894
02895     return HAL_ERROR;
02896   }
02897 }
02898
02899 /**
02900   * @brief  Handles FDCAN interrupt request.
02901   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02902   *         the configuration information for the specified FDCAN.
02903   * @retval HAL status
02904   */
02905 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
02906 {
02907   uint32_t TxEventFifoITs;
02908   uint32_t RxFifo0ITs;
02909   uint32_t RxFifo1ITs;
02910   uint32_t Errors;
02911   uint32_t ErrorStatusITs;
02912   uint32_t TransmittedBuffers;
02913   uint32_t AbortedBuffers;
02914   uint32_t itsource;
02915   uint32_t itflag;
02916
02917   TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
02918   TxEventFifoITs &= hfdcan->Instance->IE;
02919   RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
02920   RxFifo0ITs &= hfdcan->Instance->IE;
02921   RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
02922   RxFifo1ITs &= hfdcan->Instance->IE;
02923   Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
02924   Errors &= hfdcan->Instance->IE;
02925   ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
02926   ErrorStatusITs &= hfdcan->Instance->IE;
02927   itsource = hfdcan->Instance->IE;
02928   itflag = hfdcan->Instance->IR;
02929
02930   /* High Priority Message interrupt management *******************************/
02931   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
02932   {
02933     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
02934     {
02935       /* Clear the High Priority Message flag */
02936       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
02937
02938 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02939       /* Call registered callback*/
02940       hfdcan->HighPriorityMessageCallback(hfdcan);
02941 #else
02942       /* High Priority Message Callback */
02943       HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
02944 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02945     }
02946   }
02947
02948   /* Transmission Abort interrupt management **********************************/
02949   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
02950   {
02951     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
02952     {
02953       /* List of aborted monitored buffers */
02954       AbortedBuffers = hfdcan->Instance->TXBCF;
02955       AbortedBuffers &= hfdcan->Instance->TXBCIE;
02956
02957       /* Clear the Transmission Cancellation flag */
02958       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
02959
02960 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02961       /* Call registered callback*/
02962       hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
02963 #else
02964       /* Transmission Cancellation Callback */
02965       HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
02966 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02967     }
02968   }
02969
02970   /* Tx event FIFO interrupts management **************************************/
02971   if (TxEventFifoITs != 0U)
02972   {
02973     /* Clear the Tx Event FIFO flags */
02974     __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
02975
02976 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02977     /* Call registered callback*/
02978     hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
02979 #else
02980     /* Tx Event FIFO Callback */
02981     HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
02982 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02983   }
02984
02985   /* Rx FIFO 0 interrupts management ******************************************/
02986   if (RxFifo0ITs != 0U)
02987   {
02988     /* Clear the Rx FIFO 0 flags */
02989     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
02990
02991 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02992     /* Call registered callback*/
02993     hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
02994 #else
02995     /* Rx FIFO 0 Callback */
02996     HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
02997 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02998   }
02999
03000   /* Rx FIFO 1 interrupts management ******************************************/
03001   if (RxFifo1ITs != 0U)
03002   {
03003     /* Clear the Rx FIFO 1 flags */
03004     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
03005
03006 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03007     /* Call registered callback*/
03008     hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
03009 #else
03010     /* Rx FIFO 1 Callback */
03011     HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
03012 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03013   }
03014
03015   /* Tx FIFO empty interrupt management ***************************************/
03016   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
03017   {
03018     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
03019     {
03020       /* Clear the Tx FIFO empty flag */
03021       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
03022
03023 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03024       /* Call registered callback*/
03025       hfdcan->TxFifoEmptyCallback(hfdcan);
03026 #else
03027       /* Tx FIFO empty Callback */
03028       HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
03029 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03030     }
03031   }
03032
03033   /* Transmission Complete interrupt management *******************************/
03034   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET)
03035   {
03036     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET)
03037     {
03038       /* List of transmitted monitored buffers */
03039       TransmittedBuffers = hfdcan->Instance->TXBTO;
03040       TransmittedBuffers &= hfdcan->Instance->TXBTIE;
03041
03042       /* Clear the Transmission Complete flag */
03043       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
03044
03045 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03046       /* Call registered callback*/
03047       hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
03048 #else
03049       /* Transmission Complete Callback */
03050       HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
03051 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03052     }
03053   }
03054
03055   /* Timestamp Wraparound interrupt management ********************************/
03056   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
03057   {
03058     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
03059     {
03060       /* Clear the Timestamp Wraparound flag */
03061       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
03062
03063 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03064       /* Call registered callback*/
03065       hfdcan->TimestampWraparoundCallback(hfdcan);
03066 #else
03067       /* Timestamp Wraparound Callback */
03068       HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
03069 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03070     }
03071   }
03072
03073   /* Timeout Occurred interrupt management ************************************/
03074   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
03075   {
03076     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
03077     {
03078       /* Clear the Timeout Occurred flag */
03079       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
03080
03081 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03082       /* Call registered callback*/
03083       hfdcan->TimeoutOccurredCallback(hfdcan);
03084 #else
03085       /* Timeout Occurred Callback */
03086       HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
03087 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03088     }
03089   }
03090
03091   /* Message RAM access failure interrupt management **************************/
03092   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
03093   {
03094     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
03095     {
03096       /* Clear the Message RAM access failure flag */
03097       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
03098
03099       /* Update error code */
03100       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
03101     }
03102   }
03103
03104   /* Error Status interrupts management ***************************************/
03105   if (ErrorStatusITs != 0U)
03106   {
03107     /* Clear the Error flags */
03108     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
03109
03110 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03111     /* Call registered callback*/
03112     hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
03113 #else
03114     /* Error Status Callback */
03115     HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
03116 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03117   }
03118
03119   /* Error interrupts management **********************************************/
03120   if (Errors != 0U)
03121   {
03122     /* Clear the Error flags */
03123     __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
03124
03125     /* Update error code */
03126     hfdcan->ErrorCode |= Errors;
03127   }
03128
03129   if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
03130   {
03131 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03132     /* Call registered callback*/
03133     hfdcan->ErrorCallback(hfdcan);
03134 #else
03135     /* Error Callback */
03136     HAL_FDCAN_ErrorCallback(hfdcan);
03137 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03138   }
03139 }
03140
03141 /**
03142   * @}
03143   */
03144
03145 /** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
03146   *  @brief   FDCAN Callback functions
03147   *
03148 @verbatim
03149   ==============================================================================
03150                           ##### Callback functions #####
03151   ==============================================================================
03152     [..]
03153     This subsection provides the following callback functions:
03154       (+) HAL_FDCAN_TxEventFifoCallback
03155       (+) HAL_FDCAN_RxFifo0Callback
03156       (+) HAL_FDCAN_RxFifo1Callback
03157       (+) HAL_FDCAN_TxFifoEmptyCallback
03158       (+) HAL_FDCAN_TxBufferCompleteCallback
03159       (+) HAL_FDCAN_TxBufferAbortCallback
03160       (+) HAL_FDCAN_HighPriorityMessageCallback
03161       (+) HAL_FDCAN_TimestampWraparoundCallback
03162       (+) HAL_FDCAN_TimeoutOccurredCallback
03163       (+) HAL_FDCAN_ErrorCallback
03164       (+) HAL_FDCAN_ErrorStatusCallback
03165
03166 @endverbatim
03167   * @{
03168   */
03169
03170 /**
03171   * @brief  Tx Event callback.
03172   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03173   *         the configuration information for the specified FDCAN.
03174   * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
03175   *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
03176   * @retval None
03177   */
03178 __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
03179 {
03180   /* Prevent unused argument(s) compilation warning */
03181   UNUSED(hfdcan);
03182   UNUSED(TxEventFifoITs);
03183
03184   /* NOTE: This function Should not be modified, when the callback is needed,
03185             the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
03186    */
03187 }
03188
03189 /**
03190   * @brief  Rx FIFO 0 callback.
03191   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03192   *         the configuration information for the specified FDCAN.
03193   * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
03194   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
03195   * @retval None
03196   */
03197 __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
03198 {
03199   /* Prevent unused argument(s) compilation warning */
03200   UNUSED(hfdcan);
03201   UNUSED(RxFifo0ITs);
03202
03203   /* NOTE: This function Should not be modified, when the callback is needed,
03204             the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
03205    */
03206 }
03207
03208 /**
03209   * @brief  Rx FIFO 1 callback.
03210   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03211   *         the configuration information for the specified FDCAN.
03212   * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
03213   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
03214   * @retval None
03215   */
03216 __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
03217 {
03218   /* Prevent unused argument(s) compilation warning */
03219   UNUSED(hfdcan);
03220   UNUSED(RxFifo1ITs);
03221
03222   /* NOTE: This function Should not be modified, when the callback is needed,
03223             the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
03224    */
03225 }
03226
03227 /**
03228   * @brief  Tx FIFO Empty callback.
03229   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03230   *         the configuration information for the specified FDCAN.
03231   * @retval None
03232   */
03233 __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
03234 {
03235   /* Prevent unused argument(s) compilation warning */
03236   UNUSED(hfdcan);
03237
03238   /* NOTE: This function Should not be modified, when the callback is needed,
03239             the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
03240    */
03241 }
03242
03243 /**
03244   * @brief  Transmission Complete callback.
03245   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03246   *         the configuration information for the specified FDCAN.
03247   * @param  BufferIndexes Indexes of the transmitted buffers.
03248   *         This parameter can be any combination of @arg FDCAN_Tx_location.
03249   * @retval None
03250   */
03251 __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
03252 {
03253   /* Prevent unused argument(s) compilation warning */
03254   UNUSED(hfdcan);
03255   UNUSED(BufferIndexes);
03256
03257   /* NOTE: This function Should not be modified, when the callback is needed,
03258             the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
03259    */
03260 }
03261
03262 /**
03263   * @brief  Transmission Cancellation callback.
03264   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03265   *         the configuration information for the specified FDCAN.
03266   * @param  BufferIndexes Indexes of the aborted buffers.
03267   *         This parameter can be any combination of @arg FDCAN_Tx_location.
03268   * @retval None
03269   */
03270 __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
03271 {
03272   /* Prevent unused argument(s) compilation warning */
03273   UNUSED(hfdcan);
03274   UNUSED(BufferIndexes);
03275
03276   /* NOTE: This function Should not be modified, when the callback is needed,
03277             the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
03278    */
03279 }
03280
03281 /**
03282   * @brief  Timestamp Wraparound callback.
03283   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03284   *         the configuration information for the specified FDCAN.
03285   * @retval None
03286   */
03287 __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
03288 {
03289   /* Prevent unused argument(s) compilation warning */
03290   UNUSED(hfdcan);
03291
03292   /* NOTE: This function Should not be modified, when the callback is needed,
03293             the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
03294    */
03295 }
03296
03297 /**
03298   * @brief  Timeout Occurred callback.
03299   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03300   *         the configuration information for the specified FDCAN.
03301   * @retval None
03302   */
03303 __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
03304 {
03305   /* Prevent unused argument(s) compilation warning */
03306   UNUSED(hfdcan);
03307
03308   /* NOTE: This function Should not be modified, when the callback is needed,
03309             the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
03310    */
03311 }
03312
03313 /**
03314   * @brief  High Priority Message callback.
03315   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03316   *         the configuration information for the specified FDCAN.
03317   * @retval None
03318   */
03319 __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
03320 {
03321   /* Prevent unused argument(s) compilation warning */
03322   UNUSED(hfdcan);
03323
03324   /* NOTE: This function Should not be modified, when the callback is needed,
03325             the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
03326    */
03327 }
03328
03329 /**
03330   * @brief  Error callback.
03331   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03332   *         the configuration information for the specified FDCAN.
03333   * @retval None
03334   */
03335 __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
03336 {
03337   /* Prevent unused argument(s) compilation warning */
03338   UNUSED(hfdcan);
03339
03340   /* NOTE: This function Should not be modified, when the callback is needed,
03341             the HAL_FDCAN_ErrorCallback could be implemented in the user file
03342    */
03343 }
03344
03345 /**
03346   * @brief  Error status callback.
03347   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03348   *         the configuration information for the specified FDCAN.
03349   * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
03350   *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
03351   * @retval None
03352   */
03353 __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
03354 {
03355   /* Prevent unused argument(s) compilation warning */
03356   UNUSED(hfdcan);
03357   UNUSED(ErrorStatusITs);
03358
03359   /* NOTE: This function Should not be modified, when the callback is needed,
03360             the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
03361    */
03362 }
03363
03364 /**
03365   * @}
03366   */
03367
03368 /** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
03369   *  @brief   FDCAN Peripheral State functions
03370   *
03371 @verbatim
03372   ==============================================================================
03373                       ##### Peripheral State functions #####
03374   ==============================================================================
03375     [..]
03376     This subsection provides functions allowing to :
03377       (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
03378       (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
03379
03380 @endverbatim
03381   * @{
03382   */
03383 /**
03384   * @brief  Return the FDCAN state
03385   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03386   *         the configuration information for the specified FDCAN.
03387   * @retval HAL state
03388   */
03389 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan)
03390 {
03391   /* Return FDCAN state */
03392   return hfdcan->State;
03393 }
03394
03395 /**
03396   * @brief  Return the FDCAN error code
03397   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03398   *         the configuration information for the specified FDCAN.
03399   * @retval FDCAN Error Code
03400   */
03401 uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan)
03402 {
03403   /* Return FDCAN error code */
03404   return hfdcan->ErrorCode;
03405 }
03406
03407 /**
03408   * @}
03409   */
03410
03411 /**
03412   * @}
03413   */
03414
03415 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
03416   * @{
03417   */
03418
03419 /**
03420   * @brief  Calculate each RAM block start address and size
03421   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03422   *         the configuration information for the specified FDCAN.
03423   * @retval none
03424  */
03425 static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
03426 {
03427   uint32_t RAMcounter;
03428   uint32_t SramCanInstanceBase = SRAMCAN_BASE;
03429 #if defined(FDCAN2)
03430
03431   if (hfdcan->Instance == FDCAN2)
03432   {
03433     SramCanInstanceBase += SRAMCAN_SIZE;
03434   }
03435 #endif /* FDCAN2 */
03436 #if defined(FDCAN3)
03437   if (hfdcan->Instance == FDCAN3)
03438   {
03439     SramCanInstanceBase += SRAMCAN_SIZE * 2U;
03440   }
03441 #endif /* FDCAN3 */
03442
03443   /* Standard filter list start address */
03444   hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
03445
03446   /* Standard filter elements number */
03447   MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
03448
03449   /* Extended filter list start address */
03450   hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
03451
03452   /* Extended filter elements number */
03453   MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
03454
03455   /* Rx FIFO 0 start address */
03456   hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
03457
03458   /* Rx FIFO 1 start address */
03459   hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
03460
03461   /* Tx event FIFO start address */
03462   hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
03463
03464   /* Tx FIFO/queue start address */
03465   hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
03466
03467   /* Flush the allocated Message RAM area */
03468   for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
03469   {
03470     *(uint32_t *)(RAMcounter) = 0x00000000U;
03471   }
03472 }
03473
03474 /**
03475   * @brief  Copy Tx message to the message RAM.
03476   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03477   *         the configuration information for the specified FDCAN.
03478   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
03479   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
03480   * @param  BufferIndex index of the buffer to be configured.
03481   * @retval none
03482  */
03483 static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
03484                                    const uint8_t *pTxData, uint32_t BufferIndex)
03485 {
03486   uint32_t TxElementW1;
03487   uint32_t TxElementW2;
03488   uint32_t *TxAddress;
03489   uint32_t ByteCounter;
03490
03491   /* Build first word of Tx header element */
03492   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
03493   {
03494     TxElementW1 = (pTxHeader->ErrorStateIndicator |
03495                    FDCAN_STANDARD_ID |
03496                    pTxHeader->TxFrameType |
03497                    (pTxHeader->Identifier << 18U));
03498   }
03499   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
03500   {
03501     TxElementW1 = (pTxHeader->ErrorStateIndicator |
03502                    FDCAN_EXTENDED_ID |
03503                    pTxHeader->TxFrameType |
03504                    pTxHeader->Identifier);
03505   }
03506
03507   /* Build second word of Tx header element */
03508   TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
03509                  pTxHeader->TxEventFifoControl |
03510                  pTxHeader->FDFormat |
03511                  pTxHeader->BitRateSwitch |
03512                  (pTxHeader->DataLength << 16U));
03513
03514   /* Calculate Tx element address */
03515   TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
03516
03517   /* Write Tx element header to the message RAM */
03518   *TxAddress = TxElementW1;
03519   TxAddress++;
03520   *TxAddress = TxElementW2;
03521   TxAddress++;
03522
03523   /* Write Tx payload to the message RAM */
03524   for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
03525   {
03526     *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
03527                   ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
03528                   ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
03529                   (uint32_t)pTxData[ByteCounter]);
03530     TxAddress++;
03531   }
03532 }
03533
03534 /**
03535   * @}
03536   */
03537 #endif /* HAL_FDCAN_MODULE_ENABLED */
03538 /**
03539   * @}
03540   */
03541
03542 /**
03543   * @}
03544   */
03545
03546 #endif /* FDCAN1 */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fdcan.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_fdcan.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_fdcan.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FDCAN HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_FDCAN_H
00021 #define STM32G4xx_HAL_FDCAN_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined(FDCAN1)
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup FDCAN
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief HAL State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
00051   HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
00052   HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
00053   HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
00054 } HAL_FDCAN_StateTypeDef;
00055
00056 /**
00057   * @brief FDCAN Init structure definition
00058   */
00059 typedef struct
00060 {
00061   uint32_t ClockDivider;                 /*!< Specifies the FDCAN kernel clock divider.
00062                                               The clock is common to all FDCAN instances.
00063                                               This parameter is applied only at initialisation of
00064                                               first FDCAN instance.
00065                                               This parameter can be a value of @ref FDCAN_clock_divider.   */
00066
00067   uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
00068                                               This parameter can be a value of @ref FDCAN_frame_format     */
00069
00070   uint32_t Mode;                         /*!< Specifies the FDCAN mode.
00071                                               This parameter can be a value of @ref FDCAN_operating_mode   */
00072
00073   FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
00074                                               This parameter can be set to ENABLE or DISABLE               */
00075
00076   FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
00077                                               This parameter can be set to ENABLE or DISABLE               */
00078
00079   FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
00080                                               This parameter can be set to ENABLE or DISABLE               */
00081
00082   uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
00083                                               divided for generating the nominal bit time quanta.
00084                                               This parameter must be a number between 1 and 512            */
00085
00086   uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
00087                                               hardware is allowed to lengthen or shorten a bit to perform
00088                                               resynchronization.
00089                                               This parameter must be a number between 1 and 128            */
00090
00091   uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
00092                                               This parameter must be a number between 2 and 256            */
00093
00094   uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
00095                                               This parameter must be a number between 2 and 128            */
00096
00097   uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
00098                                               divided for generating the data bit time quanta.
00099                                               This parameter must be a number between 1 and 32             */
00100
00101   uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
00102                                               hardware is allowed to lengthen or shorten a data bit to
00103                                               perform resynchronization.
00104                                               This parameter must be a number between 1 and 16             */
00105
00106   uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
00107                                               This parameter must be a number between 1 and 32             */
00108
00109   uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
00110                                               This parameter must be a number between 1 and 16             */
00111
00112   uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
00113                                               This parameter must be a number between 0 and 28             */
00114
00115   uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
00116                                               This parameter must be a number between 0 and 8             */
00117
00118   uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
00119                                               This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
00120
00121 } FDCAN_InitTypeDef;
00122
00123 /**
00124   * @brief  FDCAN filter structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t IdType;           /*!< Specifies the identifier type.
00129                                   This parameter can be a value of @ref FDCAN_id_type       */
00130
00131   uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
00132                                   This parameter must be a number between:
00133                                    - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
00134                                    - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
00135
00136   uint32_t FilterType;       /*!< Specifies the filter type.
00137                                   This parameter can be a value of @ref FDCAN_filter_type.
00138                                   The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
00139                                   only when IdType is FDCAN_EXTENDED_ID.                    */
00140
00141   uint32_t FilterConfig;     /*!< Specifies the filter configuration.
00142                                   This parameter can be a value of @ref FDCAN_filter_config */
00143
00144   uint32_t FilterID1;        /*!< Specifies the filter identification 1.
00145                                   This parameter must be a number between:
00146                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00147                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00148
00149   uint32_t FilterID2;        /*!< Specifies the filter identification 2.
00150                                   This parameter must be a number between:
00151                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00152                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00153
00154 } FDCAN_FilterTypeDef;
00155
00156 /**
00157   * @brief  FDCAN Tx header structure definition
00158   */
00159 typedef struct
00160 {
00161   uint32_t Identifier;          /*!< Specifies the identifier.
00162                                      This parameter must be a number between:
00163                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00164                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00165
00166   uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
00167                                      transmitted.
00168                                      This parameter can be a value of @ref FDCAN_id_type               */
00169
00170   uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
00171                                      This parameter can be a value of @ref FDCAN_frame_type            */
00172
00173   uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
00174                                       This parameter can be a value of @ref FDCAN_data_length_code     */
00175
00176   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00177                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00178
00179   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
00180                                      bit rate switching.
00181                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00182
00183   uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
00184                                      FD format.
00185                                      This parameter can be a value of @ref FDCAN_format                */
00186
00187   uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
00188                                      This parameter can be a value of @ref FDCAN_EFC                   */
00189
00190   uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
00191                                      element for identification of Tx message status.
00192                                      This parameter must be a number between 0 and 0xFF                */
00193
00194 } FDCAN_TxHeaderTypeDef;
00195
00196 /**
00197   * @brief  FDCAN Rx header structure definition
00198   */
00199 typedef struct
00200 {
00201   uint32_t Identifier;            /*!< Specifies the identifier.
00202                                        This parameter must be a number between:
00203                                         - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00204                                         - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00205
00206   uint32_t IdType;                /*!< Specifies the identifier type of the received message.
00207                                        This parameter can be a value of @ref FDCAN_id_type               */
00208
00209   uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
00210                                        This parameter can be a value of @ref FDCAN_frame_type            */
00211
00212   uint32_t DataLength;            /*!< Specifies the received frame length.
00213                                         This parameter can be a value of @ref FDCAN_data_length_code     */
00214
00215   uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
00216                                        This parameter can be a value of @ref FDCAN_error_state_indicator */
00217
00218   uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
00219                                        rate switching.
00220                                        This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00221
00222   uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
00223                                        format.
00224                                        This parameter can be a value of @ref FDCAN_format                */
00225
00226   uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
00227                                        reception.
00228                                        This parameter must be a number between 0 and 0xFFFF              */
00229
00230   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
00231                                        This parameter must be a number between:
00232                                         - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
00233                                         - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID
00234                                        When the frame is a Non-Filter matching frame, this parameter
00235                                        is unused.                                                        */
00236
00237   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
00238                                        Acceptance of non-matching frames may be enabled via
00239                                        HAL_FDCAN_ConfigGlobalFilter().
00240                                        This parameter takes 0 if the frame matched an Rx filter or
00241                                        1 if it did not match any Rx filter                               */
00242
00243 } FDCAN_RxHeaderTypeDef;
00244
00245 /**
00246   * @brief  FDCAN Tx event FIFO structure definition
00247   */
00248 typedef struct
00249 {
00250   uint32_t Identifier;          /*!< Specifies the identifier.
00251                                      This parameter must be a number between:
00252                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00253                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00254
00255   uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
00256                                      This parameter can be a value of @ref FDCAN_id_type               */
00257
00258   uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
00259                                      This parameter can be a value of @ref FDCAN_frame_type            */
00260
00261   uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
00262                                      This parameter can be a value of @ref FDCAN_data_length_code      */
00263
00264   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00265                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00266
00267   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
00268                                      rate switching.
00269                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00270
00271   uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
00272                                      format.
00273                                      This parameter can be a value of @ref FDCAN_format                */
00274
00275   uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
00276                                      transmission.
00277                                      This parameter must be a number between 0 and 0xFFFF              */
00278
00279   uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
00280                                      for identification of Tx message status.
00281                                      This parameter must be a number between 0 and 0xFF                */
00282
00283   uint32_t EventType;           /*!< Specifies the event type.
00284                                      This parameter can be a value of @ref FDCAN_event_type            */
00285
00286 } FDCAN_TxEventFifoTypeDef;
00287
00288 /**
00289   * @brief  FDCAN High Priority Message Status structure definition
00290   */
00291 typedef struct
00292 {
00293   uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
00294                                 This parameter can be:
00295                                  - 0 : Standard Filter List
00296                                  - 1 : Extended Filter List                                */
00297
00298   uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
00299                                 This parameter can be a number between:
00300                                 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
00301                                 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */
00302
00303   uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
00304                                 This parameter can be a value of @ref FDCAN_hp_msg_storage */
00305
00306   uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
00307                                 message was stored.
00308                                 This parameter is valid only when MessageStorage is:
00309                                   FDCAN_HP_STORAGE_RXFIFO0
00310                                  or
00311                                   FDCAN_HP_STORAGE_RXFIFO1                                 */
00312
00313 } FDCAN_HpMsgStatusTypeDef;
00314
00315 /**
00316   * @brief FDCAN Protocol Status structure definition
00317   */
00318 typedef struct
00319 {
00320   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
00321                                    This parameter can be a value of @ref FDCAN_protocol_error_code             */
00322
00323   uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
00324                                    of a CAN FD format frame with its BRS flag set.
00325                                    This parameter can be a value of @ref FDCAN_protocol_error_code             */
00326
00327   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
00328                                    This parameter can be a value of @ref FDCAN_communication_state             */
00329
00330   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
00331                                    This parameter can be:
00332                                     - 0 : The FDCAN is in Error_Active state
00333                                     - 1 : The FDCAN is in Error_Passive state                                  */
00334
00335   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
00336                                    This parameter can be:
00337                                     - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
00338                                           Error_Warning limit of 96
00339                                     - 1 : at least one of error counters has reached the Error_Warning
00340                                           limit of 96                                                          */
00341
00342   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
00343                                    This parameter can be:
00344                                     - 0 : The FDCAN is not in Bus_Off state
00345                                     - 1 : The FDCAN is in Bus_Off state                                        */
00346
00347   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
00348                                    This parameter can be:
00349                                     - 0 : Last received CAN FD message did not have its ESI flag set
00350                                     - 1 : Last received CAN FD message had its ESI flag set                    */
00351
00352   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
00353                                    This parameter can be:
00354                                     - 0 : Last received CAN FD message did not have its BRS flag set
00355                                     - 1 : Last received CAN FD message had its BRS flag set                    */
00356
00357   uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received
00358                                    since last protocol status.
00359                                    This parameter can be:
00360                                     - 0 : No CAN FD message received
00361                                     - 1 : CAN FD message received                                              */
00362
00363   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
00364                                    This parameter can be:
00365                                     - 0 : No protocol exception event occurred since last read access
00366                                     - 1 : Protocol exception event occurred                                    */
00367
00368   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
00369                                    This parameter can be a number between 0 and 127                            */
00370
00371 } FDCAN_ProtocolStatusTypeDef;
00372
00373 /**
00374   * @brief FDCAN Error Counters structure definition
00375   */
00376 typedef struct
00377 {
00378   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
00379                                 This parameter can be a number between 0 and 255                               */
00380
00381   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
00382                                 This parameter can be a number between 0 and 127                               */
00383
00384   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
00385                                 This parameter can be:
00386                                  - 0 : The Receive Error Counter (RxErrorCnt) is below the error
00387                                        passive level of 128
00388                                  - 1 : The Receive Error Counter (RxErrorCnt) has reached the error
00389                                        passive level of 128                                                    */
00390
00391   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
00392                                 This parameter can be a number between 0 and 255.
00393                                 This counter is incremented each time when a FDCAN protocol error causes
00394                                 the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
00395                                 the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
00396                                 FDCAN_FLAG_ERROR_LOGGING_OVERFLOW                                              */
00397
00398 } FDCAN_ErrorCountersTypeDef;
00399
00400 /**
00401   * @brief  FDCAN Message RAM blocks
00402   */
00403 typedef struct
00404 {
00405   uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
00406                                   This parameter must be a 32-bit word address      */
00407
00408   uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
00409                                   This parameter must be a 32-bit word address      */
00410
00411   uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
00412                                   This parameter must be a 32-bit word address      */
00413
00414   uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
00415                                   This parameter must be a 32-bit word address      */
00416
00417   uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
00418                                   This parameter must be a 32-bit word address      */
00419
00420   uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
00421                                   This parameter must be a 32-bit word address      */
00422
00423 } FDCAN_MsgRamAddressTypeDef;
00424
00425 /**
00426   * @brief  FDCAN handle structure definition
00427   */
00428 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00429 typedef struct __FDCAN_HandleTypeDef
00430 #else
00431 typedef struct
00432 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00433 {
00434   FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
00435
00436   FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
00437
00438   FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
00439
00440   uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
00441                                                of latest Tx FIFO/Queue request */
00442
00443   __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
00444
00445   HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
00446
00447   __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
00448
00449 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00450   void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);     /*!< FDCAN Tx Event Fifo callback         */
00451   void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);             /*!< FDCAN Rx Fifo 0 callback             */
00452   void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);             /*!< FDCAN Rx Fifo 1 callback             */
00453   void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                              /*!< FDCAN Tx Fifo Empty callback         */
00454   void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback    */
00455   void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);    /*!< FDCAN Tx Buffer abort callback       */
00456   void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                      /*!< FDCAN High priority message callback */
00457   void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                      /*!< FDCAN Timestamp wraparound callback  */
00458   void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                          /*!< FDCAN Timeout occurred callback      */
00459   void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                    /*!< FDCAN Error callback                 */
00460   void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);     /*!< FDCAN Error status callback          */
00461
00462   void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Msp Init callback              */
00463   void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                /*!< FDCAN Msp DeInit callback            */
00464
00465 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00466
00467 } FDCAN_HandleTypeDef;
00468
00469 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00470 /**
00471   * @brief  HAL FDCAN common Callback ID enumeration definition
00472   */
00473 typedef enum
00474 {
00475   HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U,    /*!< FDCAN Tx Fifo Empty callback ID         */
00476   HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x01U,    /*!< FDCAN High priority message callback ID */
00477   HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U,    /*!< FDCAN Timestamp wraparound callback ID  */
00478   HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x03U,    /*!< FDCAN Timeout occurred callback ID      */
00479   HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x04U,    /*!< FDCAN Error callback ID                 */
00480
00481   HAL_FDCAN_MSPINIT_CB_ID              = 0x05U,    /*!< FDCAN MspInit callback ID               */
00482   HAL_FDCAN_MSPDEINIT_CB_ID            = 0x06U,    /*!< FDCAN MspDeInit callback ID             */
00483
00484 } HAL_FDCAN_CallbackIDTypeDef;
00485
00486 /**
00487   * @brief  HAL FDCAN Callback pointer definition
00488   */
00489 typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                         /*!< pointer to a common FDCAN callback function           */
00490 typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);     /*!< pointer to Tx event Fifo FDCAN callback function      */
00491 typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);             /*!< pointer to Rx Fifo 0 FDCAN callback function          */
00492 typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);             /*!< pointer to Rx Fifo 1 FDCAN callback function          */
00493 typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
00494 typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);    /*!< pointer to Tx Buffer abort FDCAN callback function    */
00495 typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);     /*!< pointer to Error Status callback function             */
00496
00497 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00498
00499 /**
00500   * @}
00501   */
00502
00503 /* Exported constants --------------------------------------------------------*/
00504 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
00505   * @{
00506   */
00507
00508 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
00509   * @{
00510   */
00511 #define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
00512 #define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
00513 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
00514 #define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
00515 #define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
00516 #define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
00517 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
00518 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
00519 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
00520 #define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
00521 #define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
00522 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
00523 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
00524 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
00525 #define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
00526 #define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
00527
00528 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00529 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
00530 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup FDCAN_frame_format FDCAN Frame Format
00536   * @{
00537   */
00538 #define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
00539 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
00540 #define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
00546   * @{
00547   */
00548 #define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
00549 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
00550 #define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
00551 #define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
00552 #define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
00558   * @{
00559   */
00560 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
00561 #define FDCAN_CLOCK_DIV2  ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2  */
00562 #define FDCAN_CLOCK_DIV4  ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4  */
00563 #define FDCAN_CLOCK_DIV6  ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6  */
00564 #define FDCAN_CLOCK_DIV8  ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8  */
00565 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
00566 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
00567 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
00568 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
00569 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
00570 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
00571 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
00572 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
00573 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
00574 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
00575 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
00581   * @{
00582   */
00583 #define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
00584 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup FDCAN_id_type FDCAN ID Type
00590   * @{
00591   */
00592 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
00593 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
00594 /**
00595   * @}
00596   */
00597
00598 /** @defgroup FDCAN_frame_type FDCAN Frame Type
00599   * @{
00600   */
00601 #define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
00602 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
00603 /**
00604   * @}
00605   */
00606
00607 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
00608   * @{
00609   */
00610 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
00611 #define FDCAN_DLC_BYTES_1  ((uint32_t)0x00000001U) /*!< 1 bytes data field  */
00612 #define FDCAN_DLC_BYTES_2  ((uint32_t)0x00000002U) /*!< 2 bytes data field  */
00613 #define FDCAN_DLC_BYTES_3  ((uint32_t)0x00000003U) /*!< 3 bytes data field  */
00614 #define FDCAN_DLC_BYTES_4  ((uint32_t)0x00000004U) /*!< 4 bytes data field  */
00615 #define FDCAN_DLC_BYTES_5  ((uint32_t)0x00000005U) /*!< 5 bytes data field  */
00616 #define FDCAN_DLC_BYTES_6  ((uint32_t)0x00000006U) /*!< 6 bytes data field  */
00617 #define FDCAN_DLC_BYTES_7  ((uint32_t)0x00000007U) /*!< 7 bytes data field  */
00618 #define FDCAN_DLC_BYTES_8  ((uint32_t)0x00000008U) /*!< 8 bytes data field  */
00619 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
00620 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
00621 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
00622 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
00623 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
00624 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
00625 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
00631   * @{
00632   */
00633 #define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
00634 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
00640   * @{
00641   */
00642 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
00643 #define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup FDCAN_format FDCAN format
00649   * @{
00650   */
00651 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
00652 #define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
00653 /**
00654   * @}
00655   */
00656
00657 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
00658   * @{
00659   */
00660 #define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
00661 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
00662 /**
00663   * @}
00664   */
00665
00666 /** @defgroup FDCAN_filter_type FDCAN Filter Type
00667   * @{
00668   */
00669 #define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
00670 #define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
00671 #define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
00672 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
00678   * @{
00679   */
00680 #define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
00681 #define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
00682 #define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
00683 #define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
00684 #define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
00685 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
00686 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
00687 /**
00688   * @}
00689   */
00690
00691 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
00692   * @{
00693   */
00694 #define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
00695 #define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
00696 #define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
00702   * @{
00703   */
00704 #define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
00705 #define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
00706 /**
00707   * @}
00708   */
00709
00710 /** @defgroup FDCAN_event_type FDCAN Event Type
00711   * @{
00712   */
00713 #define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
00714 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
00720   * @{
00721   */
00722 #define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
00723 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
00724 #define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
00725 #define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
00731   * @{
00732   */
00733 #define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
00734 #define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
00735 #define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
00736 #define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
00737 #define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
00738 #define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
00739 #define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
00740 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
00741 /**
00742   * @}
00743   */
00744
00745 /** @defgroup FDCAN_communication_state FDCAN communication state
00746   * @{
00747   */
00748 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
00749 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
00750 #define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
00751 #define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
00752 /**
00753   * @}
00754   */
00755
00756 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
00757   * @{
00758   */
00759 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
00760 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
00761 /**
00762   * @}
00763   */
00764
00765 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
00766   * @{
00767   */
00768 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
00769 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
00770 #define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
00771 /**
00772   * @}
00773   */
00774
00775 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
00776   * @{
00777   */
00778 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
00779 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
00780 /**
00781   * @}
00782   */
00783
00784 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
00785   * @{
00786   */
00787 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
00788 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
00789 /**
00790   * @}
00791   */
00792
00793 /** @defgroup FDCAN_Timestamp FDCAN timestamp
00794   * @{
00795   */
00796 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
00797 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
00803   * @{
00804   */
00805 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
00806 #define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
00807 #define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
00808 #define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
00809 #define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
00810 #define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
00811 #define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
00812 #define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
00813 #define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
00814 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
00815 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
00816 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
00817 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
00818 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
00819 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
00820 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
00821 /**
00822   * @}
00823   */
00824
00825 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
00826   * @{
00827   */
00828 #define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
00829 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
00830 #define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
00831 #define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
00832 /**
00833   * @}
00834   */
00835
00836 /** @defgroup Interrupt_Masks Interrupt masks
00837   * @{
00838   */
00839 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
00840 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
00841 /**
00842   * @}
00843   */
00844
00845 /** @defgroup FDCAN_flags FDCAN Flags
00846   * @{
00847   */
00848 #define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
00849 #define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
00850 #define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
00851 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
00852 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
00853 #define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
00854 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
00855 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
00856 #define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
00857 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
00858 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
00859 #define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
00860 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
00861 #define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
00862 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
00863 #define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
00864 #define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
00865 #define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
00866 #define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
00867 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
00868 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
00869 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
00870 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
00871 #define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
00877   * @{
00878   */
00879
00880 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
00881   * @{
00882   */
00883 #define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
00884 #define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
00885 #define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
00891   * @{
00892   */
00893 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
00894 /**
00895   * @}
00896   */
00897
00898 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
00899   * @{
00900   */
00901 #define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
00902 #define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
00903 /**
00904   * @}
00905   */
00906
00907 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
00908   * @{
00909   */
00910 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
00911 #define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
00912 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
00913 /**
00914   * @}
00915   */
00916
00917 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
00918   * @{
00919   */
00920 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
00921 #define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
00922 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
00923 /**
00924   * @}
00925   */
00926
00927 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
00928   * @{
00929   */
00930 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
00931 #define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
00932 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
00938   * @{
00939   */
00940 #define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
00941 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
00942 #define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
00943 #define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
00944 #define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
00945 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
00951   * @{
00952   */
00953 #define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed      */
00954 #define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed      */
00955 #define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed            */
00956 /**
00957   * @}
00958   */
00959
00960 /**
00961   * @}
00962   */
00963
00964 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
00965   * @{
00966   */
00967 #define FDCAN_IT_LIST_RX_FIFO0         (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
00968                                         FDCAN_IT_RX_FIFO0_FULL         | \
00969                                         FDCAN_IT_RX_FIFO0_NEW_MESSAGE)       /*!< RX FIFO 0 Interrupts List          */
00970 #define FDCAN_IT_LIST_RX_FIFO1         (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
00971                                         FDCAN_IT_RX_FIFO1_FULL         | \
00972                                         FDCAN_IT_RX_FIFO1_NEW_MESSAGE)       /*!< RX FIFO 1 Interrupts List          */
00973 #define FDCAN_IT_LIST_SMSG             (FDCAN_IT_TX_ABORT_COMPLETE | \
00974                                         FDCAN_IT_TX_COMPLETE | \
00975                                         FDCAN_IT_RX_HIGH_PRIORITY_MSG)       /*!< Status Message Interrupts List     */
00976 #define FDCAN_IT_LIST_TX_FIFO_ERROR    (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
00977                                         FDCAN_IT_TX_EVT_FIFO_FULL | \
00978                                         FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
00979                                         FDCAN_IT_TX_FIFO_EMPTY)              /*!< TX FIFO Error Interrupts List      */
00980 #define FDCAN_IT_LIST_MISC             (FDCAN_IT_TIMEOUT_OCCURRED | \
00981                                         FDCAN_IT_RAM_ACCESS_FAILURE | \
00982                                         FDCAN_IT_TIMESTAMP_WRAPAROUND)       /*!< Misc. Interrupts List              */
00983 #define FDCAN_IT_LIST_BIT_LINE_ERROR   (FDCAN_IT_ERROR_PASSIVE | \
00984                                         FDCAN_IT_ERROR_LOGGING_OVERFLOW)     /*!< Bit and Line Error Interrupts List */
00985 #define FDCAN_IT_LIST_PROTOCOL_ERROR   (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
00986                                         FDCAN_IT_DATA_PROTOCOL_ERROR | \
00987                                         FDCAN_IT_ARB_PROTOCOL_ERROR | \
00988                                         FDCAN_IT_RAM_WATCHDOG | \
00989                                         FDCAN_IT_BUS_OFF | \
00990                                         FDCAN_IT_ERROR_WARNING)              /*!< Protocol Error Interrupts List     */
00991 /**
00992   * @}
00993   */
00994
00995 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
00996   * @{
00997   */
00998 #define FDCAN_IT_GROUP_RX_FIFO0          FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group:
00999                                                                   RF0LL: Rx FIFO 0 Message Lost
01000                                                                   RF0FL: Rx FIFO 0 is Full
01001                                                                   RF0NL: Rx FIFO 0 Has New Message            */
01002 #define FDCAN_IT_GROUP_RX_FIFO1          FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group:
01003                                                                   RF1LL: Rx FIFO 1 Message Lost
01004                                                                   RF1FL: Rx FIFO 1 is Full
01005                                                                   RF1NL: Rx FIFO 1 Has New Message            */
01006 #define FDCAN_IT_GROUP_SMSG              FDCAN_ILS_SMSG    /*!< Status Message Interrupts Group:
01007                                                                   TCFL: Transmission Cancellation Finished
01008                                                                   TCL: Transmission Completed
01009                                                                   HPML: High Priority Message                 */
01010 #define FDCAN_IT_GROUP_TX_FIFO_ERROR     FDCAN_ILS_TFERR   /*!< TX FIFO Error Interrupts Group:
01011                                                                   TEFLL: Tx Event FIFO Element Lost
01012                                                                   TEFFL: Tx Event FIFO Full
01013                                                                   TEFNL: Tx Event FIFO New Entry
01014                                                                   TFEL: Tx FIFO Empty Interrupt Line          */
01015 #define FDCAN_IT_GROUP_MISC              FDCAN_ILS_MISC    /*!< Misc. Interrupts Group:
01016                                                                   TOOL: Timeout Occurred
01017                                                                   MRAFL: Message RAM Access Failure
01018                                                                   TSWL: Timestamp Wraparound                  */
01019 #define FDCAN_IT_GROUP_BIT_LINE_ERROR    FDCAN_ILS_BERR    /*!< Bit and Line Error Interrupts Group:
01020                                                                   EPL: Error Passive
01021                                                                   ELOL: Error Logging Overflow                */
01022 #define FDCAN_IT_GROUP_PROTOCOL_ERROR    FDCAN_ILS_PERR    /*!< Protocol Error Group:
01023                                                                   ARAL: Access to Reserved Address Line
01024                                                                   PEDL: Protocol Error in Data Phase Line
01025                                                                   PEAL: Protocol Error in Arbitration Phase Line
01026                                                                   WDIL: Watchdog Interrupt Line
01027                                                                   BOL: Bus_Off Status
01028                                                                   EWL: Warning Status                         */
01029 /**
01030   * @}
01031   */
01032
01033 /**
01034   * @}
01035   */
01036
01037 /* Exported macro ------------------------------------------------------------*/
01038 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
01039   * @{
01040   */
01041
01042 /** @brief  Reset FDCAN handle state.
01043   * @param  __HANDLE__ FDCAN handle.
01044   * @retval None
01045   */
01046 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01047 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
01048                                                        (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
01049                                                        (__HANDLE__)->MspInitCallback = NULL;           \
01050                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
01051                                                      } while(0)
01052 #else
01053 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
01054 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01055
01056 /**
01057   * @brief  Enable the specified FDCAN interrupts.
01058   * @param  __HANDLE__ FDCAN handle.
01059   * @param  __INTERRUPT__ FDCAN interrupt.
01060   *         This parameter can be any combination of @arg FDCAN_Interrupts
01061   * @retval None
01062   */
01063 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
01064   (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
01065
01066 /**
01067   * @brief  Disable the specified FDCAN interrupts.
01068   * @param  __HANDLE__ FDCAN handle.
01069   * @param  __INTERRUPT__ FDCAN interrupt.
01070   *         This parameter can be any combination of @arg FDCAN_Interrupts
01071   * @retval None
01072   */
01073 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
01074   ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
01075
01076 /**
01077   * @brief  Check whether the specified FDCAN interrupt is set or not.
01078   * @param  __HANDLE__ FDCAN handle.
01079   * @param  __INTERRUPT__ FDCAN interrupt.
01080   *         This parameter can be one of @arg FDCAN_Interrupts
01081   * @retval ITStatus
01082   */
01083 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
01084
01085 /**
01086   * @brief  Clear the specified FDCAN interrupts.
01087   * @param  __HANDLE__ FDCAN handle.
01088   * @param  __INTERRUPT__ specifies the interrupts to clear.
01089   *         This parameter can be any combination of @arg FDCAN_Interrupts
01090   * @retval None
01091   */
01092 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)             \
01093   ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
01094
01095 /**
01096   * @brief  Check whether the specified FDCAN flag is set or not.
01097   * @param  __HANDLE__ FDCAN handle.
01098   * @param  __FLAG__ FDCAN flag.
01099   *         This parameter can be one of @arg FDCAN_flags
01100   * @retval FlagStatus
01101   */
01102 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
01103
01104 /**
01105   * @brief  Clear the specified FDCAN flags.
01106   * @param  __HANDLE__ FDCAN handle.
01107   * @param  __FLAG__ specifies the flags to clear.
01108   *         This parameter can be any combination of @arg FDCAN_flags
01109   * @retval None
01110   */
01111 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
01112   ((__HANDLE__)->Instance->IR) = (__FLAG__)
01113
01114 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
01115   * @param  __HANDLE__ FDCAN handle.
01116   * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
01117   *         This parameter can be a value of @arg FDCAN_Interrupts
01118   * @retval ITStatus
01119   */
01120 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
01121
01122 /**
01123   * @}
01124   */
01125
01126 /* Exported functions --------------------------------------------------------*/
01127 /** @addtogroup FDCAN_Exported_Functions
01128   * @{
01129   */
01130
01131 /** @addtogroup FDCAN_Exported_Functions_Group1
01132   * @{
01133   */
01134 /* Initialization and de-initialization functions *****************************/
01135 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
01136 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
01137 void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
01138 void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
01139 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01140 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01141
01142 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01143 /* Callbacks Register/UnRegister functions  ***********************************/
01144 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
01145                                              pFDCAN_CallbackTypeDef pCallback);
01146 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
01147 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
01148                                                         pFDCAN_TxEventFifoCallbackTypeDef pCallback);
01149 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
01150 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
01151                                                     pFDCAN_RxFifo0CallbackTypeDef pCallback);
01152 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
01153 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
01154                                                     pFDCAN_RxFifo1CallbackTypeDef pCallback);
01155 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
01156 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
01157                                                              pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
01158 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
01159 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
01160                                                           pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
01161 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
01162 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
01163                                                         pFDCAN_ErrorStatusCallbackTypeDef pCallback);
01164 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
01165 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01166 /**
01167   * @}
01168   */
01169
01170 /** @addtogroup FDCAN_Exported_Functions_Group2
01171   * @{
01172   */
01173 /* Configuration functions ****************************************************/
01174 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
01175 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
01176                                                uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
01177                                                uint32_t RejectRemoteExt);
01178 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
01179 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
01180 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
01181 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
01182 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
01183 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01184 uint16_t          HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
01185 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01186 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
01187                                                  uint32_t TimeoutPeriod);
01188 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01189 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01190 uint16_t          HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
01191 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01192 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
01193                                                       uint32_t TdcFilter);
01194 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01195 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01196 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
01197 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
01198 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
01199 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
01200 /**
01201   * @}
01202   */
01203
01204 /** @addtogroup FDCAN_Exported_Functions_Group3
01205   * @{
01206   */
01207 /* Control functions **********************************************************/
01208 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
01209 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
01210 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
01211                                                 const uint8_t *pTxData);
01212 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
01213 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
01214 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
01215                                          FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
01216 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
01217 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
01218                                                          FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
01219 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
01220                                               FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
01221 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
01222                                              FDCAN_ErrorCountersTypeDef *ErrorCounters);
01223 uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
01224 uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
01225 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
01226 uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
01227 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
01228 /**
01229   * @}
01230   */
01231
01232 /** @addtogroup FDCAN_Exported_Functions_Group4
01233   * @{
01234   */
01235 /* Interrupts management ******************************************************/
01236 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
01237 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
01238                                                  uint32_t BufferIndexes);
01239 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
01240 void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
01241 /**
01242   * @}
01243   */
01244
01245 /** @addtogroup FDCAN_Exported_Functions_Group5
01246   * @{
01247   */
01248 /* Callback functions *********************************************************/
01249 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
01250 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
01251 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
01252 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
01253 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01254 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01255 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
01256 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
01257 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
01258 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
01259 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
01260 /**
01261   * @}
01262   */
01263
01264 /** @addtogroup FDCAN_Exported_Functions_Group6
01265   * @{
01266   */
01267 /* Peripheral State functions *************************************************/
01268 uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
01269 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
01270 /**
01271   * @}
01272   */
01273
01274 /**
01275   * @}
01276   */
01277
01278 /* Private types -------------------------------------------------------------*/
01279 /* Private variables ---------------------------------------------------------*/
01280 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
01281   * @{
01282   */
01283
01284 /**
01285   * @}
01286   */
01287
01288 /* Private constants ---------------------------------------------------------*/
01289 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
01290   * @{
01291   */
01292
01293 /**
01294   * @}
01295   */
01296
01297 /* Private macros ------------------------------------------------------------*/
01298 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
01299   * @{
01300   */
01301 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
01302                                        ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
01303                                        ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
01304 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
01305                              ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
01306                              ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
01307                              ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
01308                              ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
01309 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
01310                                ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
01311                                ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
01312                                ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
01313                                ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
01314                                ((CKDIV) == FDCAN_CLOCK_DIV10) || \
01315                                ((CKDIV) == FDCAN_CLOCK_DIV12) || \
01316                                ((CKDIV) == FDCAN_CLOCK_DIV14) || \
01317                                ((CKDIV) == FDCAN_CLOCK_DIV16) || \
01318                                ((CKDIV) == FDCAN_CLOCK_DIV18) || \
01319                                ((CKDIV) == FDCAN_CLOCK_DIV20) || \
01320                                ((CKDIV) == FDCAN_CLOCK_DIV22) || \
01321                                ((CKDIV) == FDCAN_CLOCK_DIV24) || \
01322                                ((CKDIV) == FDCAN_CLOCK_DIV26) || \
01323                                ((CKDIV) == FDCAN_CLOCK_DIV28) || \
01324                                ((CKDIV) == FDCAN_CLOCK_DIV30))
01325 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
01326 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
01327 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
01328 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
01329 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
01330 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
01331 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
01332 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
01333 #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
01334 #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
01335 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
01336                                            ((MODE) == FDCAN_TX_QUEUE_OPERATION))
01337 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
01338                                    ((ID_TYPE) == FDCAN_EXTENDED_ID))
01339 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
01340                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
01341                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
01342                                      ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
01343                                      ((CONFIG) == FDCAN_FILTER_HP           ) || \
01344                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
01345                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
01346 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
01347                                         ((LOCATION) == FDCAN_TX_BUFFER2 ))
01348 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \
01349                                              ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
01350 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
01351                                 ((FIFO) == FDCAN_RX_FIFO1))
01352 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
01353                                      ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
01354 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
01355                                         ((TYPE) == FDCAN_FILTER_DUAL ) || \
01356                                         ((TYPE) == FDCAN_FILTER_MASK ))
01357 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
01358                                         ((TYPE) == FDCAN_FILTER_DUAL         ) || \
01359                                         ((TYPE) == FDCAN_FILTER_MASK         ) || \
01360                                         ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
01361 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
01362                                    ((TYPE) == FDCAN_REMOTE_FRAME))
01363 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
01364                            ((DLC) == FDCAN_DLC_BYTES_1 ) || \
01365                            ((DLC) == FDCAN_DLC_BYTES_2 ) || \
01366                            ((DLC) == FDCAN_DLC_BYTES_3 ) || \
01367                            ((DLC) == FDCAN_DLC_BYTES_4 ) || \
01368                            ((DLC) == FDCAN_DLC_BYTES_5 ) || \
01369                            ((DLC) == FDCAN_DLC_BYTES_6 ) || \
01370                            ((DLC) == FDCAN_DLC_BYTES_7 ) || \
01371                            ((DLC) == FDCAN_DLC_BYTES_8 ) || \
01372                            ((DLC) == FDCAN_DLC_BYTES_12) || \
01373                            ((DLC) == FDCAN_DLC_BYTES_16) || \
01374                            ((DLC) == FDCAN_DLC_BYTES_20) || \
01375                            ((DLC) == FDCAN_DLC_BYTES_24) || \
01376                            ((DLC) == FDCAN_DLC_BYTES_32) || \
01377                            ((DLC) == FDCAN_DLC_BYTES_48) || \
01378                            ((DLC) == FDCAN_DLC_BYTES_64))
01379 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
01380                            ((ESI) == FDCAN_ESI_PASSIVE))
01381 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
01382                            ((BRS) == FDCAN_BRS_ON ))
01383 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
01384                            ((FDF) == FDCAN_FD_CAN     ))
01385 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
01386                            ((EFC) == FDCAN_STORE_TX_EVENTS))
01387 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
01388 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
01389 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
01390                                             ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
01391                                             ((DESTINATION) == FDCAN_REJECT            ))
01392 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
01393                                              ((DESTINATION) == FDCAN_REJECT_REMOTE))
01394 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
01395                                    ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
01396 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
01397                                        ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
01398 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
01399                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
01400                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
01401                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
01402                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
01403                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
01404                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
01405                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
01406                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
01407                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
01408                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
01409                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
01410                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
01411                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
01412                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
01413                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
01414 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
01415                                      ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
01416                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
01417                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
01418
01419 #define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
01420
01421 #define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
01422 /**
01423   * @}
01424   */
01425
01426 /* Private functions prototypes ----------------------------------------------*/
01427 /* Private functions ---------------------------------------------------------*/
01428
01429 /**
01430   * @}
01431   */
01432
01433 /**
01434   * @}
01435   */
01436 #endif /* FDCAN1 */
01437
01438 #ifdef __cplusplus
01439 }
01440 #endif
01441
01442 #endif /* STM32G4xx_HAL_FDCAN_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_flash.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the internal FLASH memory:
00008   *           + Program operations functions
00009   *           + Memory Control functions
00010   *           + Peripheral Errors functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### FLASH peripheral features #####
00015   ==============================================================================
00016
00017   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00018        to the Flash memory. It implements the erase and program Flash memory operations
00019        and the read and write protection mechanisms.
00020
00021   [..] The Flash memory interface accelerates code execution with a system of instruction
00022        prefetch and cache lines.
00023
00024   [..] The FLASH main features are:
00025       (+) Flash memory read operations
00026       (+) Flash memory program/erase operations
00027       (+) Read / write protections
00028       (+) Option bytes programming
00029       (+) Prefetch on I-Code
00030       (+) 32 cache lines of 4*64 or 2*128 bits on I-Code
00031       (+) 8 cache lines of 4*64 or 2*128 bits on D-Code
00032       (+) Error code correction (ECC) : Data in flash are 72-bits word
00033           (8 bits added per double word)
00034
00035
00036                         ##### How to use this driver #####
00037   ==============================================================================
00038     [..]
00039       This driver provides functions and macros to configure and program the FLASH
00040       memory of all STM32G4xx devices.
00041
00042       (#) Flash Memory IO Programming functions:
00043            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00044                 HAL_FLASH_Lock() functions
00045            (++) Program functions: double word and fast program (full row programming)
00046            (++) There are two modes of programming :
00047             (+++) Polling mode using HAL_FLASH_Program() function
00048             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00049
00050       (#) Interrupts and flags management functions:
00051            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00052            (++) Callback functions are called when the flash operations are finished :
00053                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00054                 HAL_FLASH_OperationErrorCallback()
00055            (++) Get error flag status by calling HAL_GetError()
00056
00057       (#) Option bytes management functions:
00058            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00059                 HAL_FLASH_OB_Lock() functions
00060            (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
00061                 In this case, a reset is generated
00062
00063     [..]
00064       In addition to these functions, this driver includes a set of macros allowing
00065       to handle the following operations:
00066        (+) Set the latency
00067        (+) Enable/Disable the prefetch buffer
00068        (+) Enable/Disable the Instruction cache and the Data cache
00069        (+) Reset the Instruction cache and the Data cache
00070        (+) Enable/Disable the Flash power-down during low-power run and sleep modes
00071        (+) Enable/Disable the Flash interrupts
00072        (+) Monitor the Flash flags status
00073
00074   @endverbatim
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * Copyright (c) 2019 STMicroelectronics.
00079   * All rights reserved.
00080   *
00081   * This software is licensed under terms that can be found in the LICENSE file in
00082   * the root directory of this software component.
00083   * If no LICENSE file comes with this software, it is provided AS-IS.
00084   ******************************************************************************
00085   */
00086
00087 /* Includes ------------------------------------------------------------------*/
00088 #include "stm32g4xx_hal.h"
00089
00090 /** @addtogroup STM32G4xx_HAL_Driver
00091   * @{
00092   */
00093
00094 /** @defgroup FLASH FLASH
00095   * @brief FLASH HAL module driver
00096   * @{
00097   */
00098
00099 #ifdef HAL_FLASH_MODULE_ENABLED
00100
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private defines -----------------------------------------------------------*/
00103 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00104   * @{
00105   */
00106 #define FLASH_NB_DOUBLE_WORDS_IN_ROW  32
00107 /**
00108   * @}
00109   */
00110
00111 /* Private macros ------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Variable used for Program/Erase sectors under interruption
00119   */
00120 FLASH_ProcessTypeDef pFlash  = {.Lock = HAL_UNLOCKED,
00121                                 .ErrorCode = HAL_FLASH_ERROR_NONE,
00122                                 .ProcedureOnGoing = FLASH_PROC_NONE,
00123                                 .Address = 0U,
00124                                 .Bank = FLASH_BANK_1,
00125                                 .Page = 0U,
00126                                 .NbPagesToErase = 0U,
00127                                 .CacheToReactivate = FLASH_CACHE_DISABLED};
00128 /**
00129   * @}
00130   */
00131
00132 /* Private function prototypes -----------------------------------------------*/
00133 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00134   * @{
00135   */
00136 static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00137 static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
00138 /**
00139   * @}
00140   */
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00144   * @{
00145   */
00146
00147 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00148   *  @brief   Programming operation functions
00149   *
00150 @verbatim
00151  ===============================================================================
00152                   ##### Programming operation functions #####
00153  ===============================================================================
00154     [..]
00155     This subsection provides a set of functions allowing to manage the FLASH
00156     program operations.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Program double word or fast program of a row at a specified address.
00164   * @param  TypeProgram Indicate the way to program at a specified address.
00165   *         This parameter can be a value of @ref FLASH_Type_Program.
00166   * @param  Address specifies the address to be programmed.
00167   * @param  Data specifies the data to be programmed.
00168   *         This parameter is the data for the double word program and the address where
00169   *         are stored the data for the row fast program.
00170   *
00171   * @retval HAL_Status
00172   */
00173 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00174 {
00175   HAL_StatusTypeDef status;
00176   uint32_t prog_bit = 0;
00177
00178   /* Check the parameters */
00179   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00180
00181   /* Process Locked */
00182   __HAL_LOCK(&pFlash);
00183
00184   /* Wait for last operation to be completed */
00185   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00186
00187   if (status == HAL_OK)
00188   {
00189     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00190
00191     /* Deactivate the data cache if they are activated to avoid data misbehavior */
00192     if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00193     {
00194       /* Disable data cache  */
00195       __HAL_FLASH_DATA_CACHE_DISABLE();
00196       pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
00197     }
00198     else
00199     {
00200       pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
00201     }
00202     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00203     {
00204       /* Program double-word (64-bit) at a specified address */
00205       FLASH_Program_DoubleWord(Address, Data);
00206       prog_bit = FLASH_CR_PG;
00207     }
00208     else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00209     {
00210       /* Fast program a 32 row double-word (64-bit) at a specified address */
00211       FLASH_Program_Fast(Address, (uint32_t)Data);
00212
00213       /* If it is the last row, the bit will be cleared at the end of the operation */
00214       if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
00215       {
00216         prog_bit = FLASH_CR_FSTPG;
00217       }
00218     }
00219     else
00220     {
00221       /* Nothing to do */
00222     }
00223
00224     /* Wait for last operation to be completed */
00225     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00226
00227     /* If the program operation is completed, disable the PG or FSTPG Bit */
00228     if (prog_bit != 0U)
00229     {
00230       CLEAR_BIT(FLASH->CR, prog_bit);
00231     }
00232
00233     /* Flush the caches to be sure of the data consistency */
00234     FLASH_FlushCaches();
00235   }
00236
00237   /* Process Unlocked */
00238   __HAL_UNLOCK(&pFlash);
00239
00240   /* return status */
00241   return status;
00242 }
00243
00244 /**
00245   * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
00246   * @param  TypeProgram Indicate the way to program at a specified address.
00247   *         This parameter can be a value of @ref FLASH_Type_Program.
00248   * @param  Address specifies the address to be programmed.
00249   * @param  Data specifies the data to be programmed.
00250   *         This parameter is the data for the double word program and the address where
00251   *         are stored the data for the row fast program.
00252   *
00253   * @retval HAL_Status
00254   */
00255 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00256 {
00257   HAL_StatusTypeDef status;
00258
00259   /* Check the parameters */
00260   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00261
00262   /* Process Locked */
00263   __HAL_LOCK(&pFlash);
00264
00265   /* Reset error code */
00266   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00267
00268   /* Deactivate the data cache if they are activated to avoid data misbehavior */
00269   if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00270   {
00271     /* Disable data cache  */
00272     __HAL_FLASH_DATA_CACHE_DISABLE();
00273     pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
00274   }
00275   else
00276   {
00277     pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
00278   }
00279
00280   /* Wait for last operation to be completed */
00281   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00282
00283   if (status != HAL_OK)
00284   {
00285     /* Process Unlocked */
00286     __HAL_UNLOCK(&pFlash);
00287   }
00288   else
00289   {
00290     /* Set internal variables used by the IRQ handler */
00291     if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
00292     {
00293       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
00294     }
00295     else
00296     {
00297       pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
00298     }
00299     pFlash.Address = Address;
00300
00301     /* Enable End of Operation and Error interrupts */
00302     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00303
00304     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00305     {
00306       /* Program double-word (64-bit) at a specified address */
00307       FLASH_Program_DoubleWord(Address, Data);
00308     }
00309     else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00310     {
00311       /* Fast program a 32 row double-word (64-bit) at a specified address */
00312       FLASH_Program_Fast(Address, (uint32_t)Data);
00313     }
00314     else
00315     {
00316       /* Nothing to do */
00317     }
00318   }
00319
00320   return status;
00321 }
00322
00323 /**
00324   * @brief  Handle FLASH interrupt request.
00325   * @retval None
00326   */
00327 void HAL_FLASH_IRQHandler(void)
00328 {
00329   uint32_t tmp_page;
00330   uint32_t error;
00331   FLASH_ProcedureTypeDef procedure;
00332
00333   /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
00334   CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
00335 #if defined (FLASH_OPTR_DBANK)
00336   CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
00337 #endif
00338
00339   /* Disable the FSTPG Bit only if it is the last row programmed */
00340   if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
00341   {
00342     CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
00343   }
00344
00345   /* Check FLASH operation error flags */
00346   error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
00347
00348   if (error != 0U)
00349   {
00350     /* Save the error code */
00351     pFlash.ErrorCode |= error;
00352
00353     /* Clear error programming flags */
00354     __HAL_FLASH_CLEAR_FLAG(error);
00355
00356     /* Flush the caches to be sure of the data consistency */
00357     FLASH_FlushCaches();
00358
00359     /* FLASH error interrupt user callback */
00360     procedure = pFlash.ProcedureOnGoing;
00361     if (procedure == FLASH_PROC_PAGE_ERASE)
00362     {
00363       HAL_FLASH_OperationErrorCallback(pFlash.Page);
00364     }
00365     else if (procedure == FLASH_PROC_MASS_ERASE)
00366     {
00367       HAL_FLASH_OperationErrorCallback(pFlash.Bank);
00368     }
00369     else if ((procedure == FLASH_PROC_PROGRAM) ||
00370              (procedure == FLASH_PROC_PROGRAM_LAST))
00371     {
00372       HAL_FLASH_OperationErrorCallback(pFlash.Address);
00373     }
00374     else
00375     {
00376       /* Nothing to do */
00377     }
00378
00379     /*Stop the procedure ongoing*/
00380     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00381   }
00382
00383   /* Check FLASH End of Operation flag  */
00384   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00385   {
00386     /* Clear FLASH End of Operation pending bit */
00387     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00388
00389     if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
00390     {
00391       /* Nb of pages to erased can be decreased */
00392       pFlash.NbPagesToErase--;
00393
00394       /* Check if there are still pages to erase*/
00395       if (pFlash.NbPagesToErase != 0U)
00396       {
00397         /* Indicate user which page has been erased*/
00398         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
00399
00400         /* Increment page number */
00401         pFlash.Page++;
00402         tmp_page = pFlash.Page;
00403         FLASH_PageErase(tmp_page, pFlash.Bank);
00404       }
00405       else
00406       {
00407         /* No more pages to Erase */
00408         /* Reset Address and stop Erase pages procedure */
00409         pFlash.Page = 0xFFFFFFFFU;
00410         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00411
00412         /* Flush the caches to be sure of the data consistency */
00413         FLASH_FlushCaches();
00414
00415         /* FLASH EOP interrupt user callback */
00416         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
00417       }
00418     }
00419     else
00420     {
00421       /* Flush the caches to be sure of the data consistency */
00422       FLASH_FlushCaches();
00423
00424       procedure = pFlash.ProcedureOnGoing;
00425       if (procedure == FLASH_PROC_MASS_ERASE)
00426       {
00427         /* MassErase ended. Return the selected bank */
00428         /* FLASH EOP interrupt user callback */
00429         HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
00430       }
00431       else if ((procedure == FLASH_PROC_PROGRAM) ||
00432                (procedure == FLASH_PROC_PROGRAM_LAST))
00433       {
00434         /* Program ended. Return the selected address */
00435         /* FLASH EOP interrupt user callback */
00436         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00437       }
00438       else
00439       {
00440         /* Nothing to do */
00441       }
00442
00443       /*Clear the procedure ongoing*/
00444       pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00445     }
00446   }
00447
00448   if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00449   {
00450     /* Disable End of Operation and Error interrupts */
00451     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00452
00453     /* Process Unlocked */
00454     __HAL_UNLOCK(&pFlash);
00455   }
00456 }
00457
00458 /**
00459   * @brief  FLASH end of operation interrupt callback.
00460   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
00461   *           @arg Mass Erase: Bank number which has been requested to erase
00462   *           @arg Page Erase: Page which has been erased
00463   *                            (if 0xFFFFFFFF, it means that all the selected pages have been erased)
00464   *           @arg Program: Address which was selected for data program
00465   * @retval None
00466   */
00467 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00468 {
00469   /* Prevent unused argument(s) compilation warning */
00470   UNUSED(ReturnValue);
00471
00472   /* NOTE : This function should not be modified, when the callback is needed,
00473             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00474    */
00475 }
00476
00477 /**
00478   * @brief  FLASH operation error interrupt callback.
00479   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure:
00480   *           @arg Mass Erase: Bank number which has been requested to erase
00481   *           @arg Page Erase: Page number which returned an error
00482   *           @arg Program: Address which was selected for data program
00483   * @retval None
00484   */
00485 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00486 {
00487   /* Prevent unused argument(s) compilation warning */
00488   UNUSED(ReturnValue);
00489
00490   /* NOTE : This function should not be modified, when the callback is needed,
00491             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00492    */
00493 }
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00500   * @brief   Management functions
00501   *
00502 @verbatim
00503  ===============================================================================
00504                       ##### Peripheral Control functions #####
00505  ===============================================================================
00506     [..]
00507     This subsection provides a set of functions allowing to control the FLASH
00508     memory operations.
00509
00510 @endverbatim
00511   * @{
00512   */
00513
00514 /**
00515   * @brief  Unlock the FLASH control register access.
00516   * @retval HAL_Status
00517   */
00518 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00519 {
00520   HAL_StatusTypeDef status = HAL_OK;
00521
00522   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
00523   {
00524     /* Authorize the FLASH Registers access */
00525     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00526     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00527
00528     /* verify Flash is unlocked */
00529     if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
00530     {
00531       status = HAL_ERROR;
00532     }
00533   }
00534
00535   return status;
00536 }
00537
00538 /**
00539   * @brief  Lock the FLASH control register access.
00540   * @retval HAL_Status
00541   */
00542 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00543 {
00544   HAL_StatusTypeDef status = HAL_ERROR;
00545
00546   /* Set the LOCK Bit to lock the FLASH Registers access */
00547   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00548
00549   /* verify Flash is locked */
00550   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
00551   {
00552     status = HAL_OK;
00553   }
00554
00555   return status;
00556 }
00557
00558 /**
00559   * @brief  Unlock the FLASH Option Bytes Registers access.
00560   * @retval HAL_Status
00561   */
00562 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00563 {
00564   HAL_StatusTypeDef status = HAL_OK;
00565
00566   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
00567   {
00568     /* Authorizes the Option Byte register programming */
00569     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00570     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00571
00572     /* verify option bytes are unlocked */
00573     if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
00574     {
00575       status = HAL_ERROR;
00576     }
00577   }
00578
00579   return status;
00580 }
00581
00582 /**
00583   * @brief  Lock the FLASH Option Bytes Registers access.
00584   * @retval HAL_Status
00585   */
00586 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00587 {
00588   HAL_StatusTypeDef status = HAL_ERROR;
00589
00590   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00591   SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
00592
00593   /* Verify option bytes are locked */
00594   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
00595   {
00596     status = HAL_OK;
00597   }
00598
00599   return status;
00600 }
00601
00602 /**
00603   * @brief  Launch the option byte loading.
00604   * @retval HAL_Status
00605   */
00606 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00607 {
00608   /* Set the bit to force the option byte reloading */
00609   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00610
00611   /* Wait for last operation to be completed */
00612   return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
00613 }
00614
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00620   * @brief   Peripheral Errors functions
00621   *
00622 @verbatim
00623  ===============================================================================
00624                 ##### Peripheral Errors functions #####
00625  ===============================================================================
00626     [..]
00627     This subsection permits to get in run-time Errors of the FLASH peripheral.
00628
00629 @endverbatim
00630   * @{
00631   */
00632
00633 /**
00634   * @brief  Get the specific FLASH error flag.
00635   * @retval FLASH_ErrorCode. The returned value can be:
00636   *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
00637   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
00638   *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
00639   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
00640   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
00641   *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
00642   *            @arg HAL_FLASH_ERROR_NONE: No error set
00643   *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
00644   *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
00645   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
00646   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
00647   *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
00648   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
00649   *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
00650   *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
00651   *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
00652   *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
00653   */
00654 uint32_t HAL_FLASH_GetError(void)
00655 {
00656   return pFlash.ErrorCode;
00657 }
00658
00659 /**
00660   * @}
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 /* Private functions ---------------------------------------------------------*/
00668
00669 /** @addtogroup FLASH_Private_Functions
00670   * @{
00671   */
00672
00673 /**
00674   * @brief  Wait for a FLASH operation to complete.
00675   * @param  Timeout maximum flash operation timeout.
00676   * @retval HAL_Status
00677   */
00678 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00679 {
00680   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00681      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00682      flag will be set */
00683
00684   uint32_t tickstart = HAL_GetTick();
00685   uint32_t error;
00686
00687   while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
00688   {
00689     if ((HAL_GetTick() - tickstart) > Timeout)
00690     {
00691       return HAL_TIMEOUT;
00692     }
00693   }
00694
00695   /* Check FLASH operation error flags */
00696   error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
00697   if (error != 0u)
00698   {
00699     /* Save the error code */
00700     pFlash.ErrorCode |= error;
00701
00702     /* Clear error programming flags */
00703     __HAL_FLASH_CLEAR_FLAG(error);
00704
00705     return HAL_ERROR;
00706   }
00707
00708   /* Check FLASH End of Operation flag  */
00709   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00710   {
00711     /* Clear FLASH End of Operation pending bit */
00712     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00713   }
00714
00715   /* If there is an error flag set */
00716   return HAL_OK;
00717 }
00718
00719 /**
00720   * @brief  Program double-word (64-bit) at a specified address.
00721   * @param  Address specifies the address to be programmed.
00722   * @param  Data specifies the data to be programmed.
00723   * @retval None
00724   */
00725 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00726 {
00727   /* Check the parameters */
00728   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00729
00730   /* Set PG bit */
00731   SET_BIT(FLASH->CR, FLASH_CR_PG);
00732
00733   /* Program first word */
00734   *(uint32_t *)Address = (uint32_t)Data;
00735
00736   /* Barrier to ensure programming is performed in 2 steps, in right order
00737     (independently of compiler optimization behavior) */
00738   __ISB();
00739
00740   /* Program second word */
00741   *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
00742 }
00743
00744 /**
00745   * @brief  Fast program a row double-word (64-bit) at a specified address.
00746   * @param  Address specifies the address to be programmed.
00747   * @param  DataAddress specifies the address where the data are stored.
00748   * @retval None
00749   */
00750 static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
00751 {
00752   uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
00753   uint32_t *dest_addr = (uint32_t *)Address;
00754   uint32_t *src_addr = (uint32_t *)DataAddress;
00755   uint32_t primask_bit;
00756
00757   /* Check the parameters */
00758   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
00759
00760   /* Set FSTPG bit */
00761   SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
00762
00763   /* Enter critical section: Disable interrupts to avoid any interruption during the loop */
00764   primask_bit = __get_PRIMASK();
00765   __disable_irq();
00766
00767   /* Program the double words of the row */
00768   do
00769   {
00770     *dest_addr = *src_addr;
00771     dest_addr++;
00772     src_addr++;
00773     row_index--;
00774   }
00775   while (row_index != 0U);
00776
00777   /* Exit critical section: restore previous priority mask */
00778   __set_PRIMASK(primask_bit);
00779 }
00780
00781 /**
00782   * @}
00783   */
00784
00785 #endif /* HAL_FLASH_MODULE_ENABLED */
00786
00787 /**
00788   * @}
00789   */
00790
00791 /**
00792   * @}
00793   */
00794
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_flash.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_HAL_FLASH_H
00020 #define STM32G4xx_HAL_FLASH_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup FLASH
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  FLASH Erase structure definition
00044   */
00045 typedef struct
00046 {
00047   uint32_t TypeErase;   /*!< Mass erase or page erase.
00048                              This parameter can be a value of @ref FLASH_Type_Erase */
00049   uint32_t Banks;       /*!< Select bank to erase.
00050                              This parameter must be a value of @ref FLASH_Banks
00051                              (FLASH_BANK_BOTH should be used only for mass erase) */
00052   uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled.
00053                              This parameter must be a value between 0 and (max number of pages in the bank - 1)
00054                              (eg : 127 for 512KB dual bank) */
00055   uint32_t NbPages;     /*!< Number of pages to be erased.
00056                              This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
00057 } FLASH_EraseInitTypeDef;
00058
00059 /**
00060   * @brief  FLASH Option Bytes Program structure definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t OptionType;     /*!< Option byte to be configured.
00065                                 This parameter can be a combination of the values of @ref FLASH_OB_Type */
00066   uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
00067                                 Only one WRP area could be programmed at the same time.
00068                                 This parameter can be value of @ref FLASH_OB_WRP_Area */
00069   uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
00070                                 This parameter must be a value between 0 and (max number of pages in the bank - 1) */
00071   uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
00072                                 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
00073   uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
00074                                 This parameter can be a value of @ref FLASH_OB_Read_Protection */
00075   uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00076                                 This parameter can be a combination of @ref FLASH_OB_USER_Type */
00077   uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
00078                                 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
00079                                 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
00080                                 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
00081                                 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
00082                                 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
00083                                 @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
00084                                 @ref FLASH_OB_USER_CCMSRAM_RST
00085                                 @note (*) availability depends on devices */
00086   uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
00087                                 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
00088                                 and @ref FLASH_OB_PCROP_RDP */
00089   uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
00090                                 This parameter must be a value between begin and end of bank
00091                                 => Be careful of the bank swapping for the address */
00092   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
00093                                 This parameter must be a value between PCROP Start address and end of bank */
00094   uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK).
00095                                 This parameter can be a value of @ref FLASH_OB_Boot_Lock */
00096   uint32_t SecBank;        /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC).
00097                                 Only one securable memory area could be programmed at the same time.
00098                                 This parameter can be one of the following values:
00099                                 FLASH_BANK_1: Securable memory area to be programmed in bank 1
00100                                 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)
00101                                 @note (*) availability depends on devices */
00102   uint32_t SecSize;        /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC),
00103                                 in number of pages. Securable memory area is starting from first page of the bank.
00104                                 Only one securable memory could be programmed at the same time.
00105                                 This parameter must be a value between 0 and (max number of pages in the bank - 1) */
00106 } FLASH_OBProgramInitTypeDef;
00107
00108 /**
00109   * @brief  FLASH Procedure structure definition
00110   */
00111 typedef enum
00112 {
00113   FLASH_PROC_NONE = 0,
00114   FLASH_PROC_PAGE_ERASE,
00115   FLASH_PROC_MASS_ERASE,
00116   FLASH_PROC_PROGRAM,
00117   FLASH_PROC_PROGRAM_LAST
00118 } FLASH_ProcedureTypeDef;
00119
00120 /**
00121   * @brief  FLASH Cache structure definition
00122   */
00123 typedef enum
00124 {
00125   FLASH_CACHE_DISABLED = 0,
00126   FLASH_CACHE_ICACHE_ENABLED,
00127   FLASH_CACHE_DCACHE_ENABLED,
00128   FLASH_CACHE_ICACHE_DCACHE_ENABLED
00129 } FLASH_CacheTypeDef;
00130
00131 /**
00132   * @brief  FLASH handle Structure definition
00133   */
00134 typedef struct
00135 {
00136   HAL_LockTypeDef             Lock;              /* FLASH locking object */
00137   __IO uint32_t               ErrorCode;         /* FLASH error code */
00138   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
00139   __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
00140   __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
00141   __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
00142   __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
00143   __IO FLASH_CacheTypeDef     CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
00144 } FLASH_ProcessTypeDef;
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00152   * @{
00153   */
00154
00155 /** @defgroup FLASH_Error FLASH Error
00156   * @{
00157   */
00158 #define HAL_FLASH_ERROR_NONE      0x00000000U
00159 #define HAL_FLASH_ERROR_OP        FLASH_FLAG_OPERR
00160 #define HAL_FLASH_ERROR_PROG      FLASH_FLAG_PROGERR
00161 #define HAL_FLASH_ERROR_WRP       FLASH_FLAG_WRPERR
00162 #define HAL_FLASH_ERROR_PGA       FLASH_FLAG_PGAERR
00163 #define HAL_FLASH_ERROR_SIZ       FLASH_FLAG_SIZERR
00164 #define HAL_FLASH_ERROR_PGS       FLASH_FLAG_PGSERR
00165 #define HAL_FLASH_ERROR_MIS       FLASH_FLAG_MISERR
00166 #define HAL_FLASH_ERROR_FAST      FLASH_FLAG_FASTERR
00167 #define HAL_FLASH_ERROR_RD        FLASH_FLAG_RDERR
00168 #define HAL_FLASH_ERROR_OPTV      FLASH_FLAG_OPTVERR
00169 #define HAL_FLASH_ERROR_ECCC      FLASH_FLAG_ECCC
00170 #define HAL_FLASH_ERROR_ECCD      FLASH_FLAG_ECCD
00171 #if defined (FLASH_OPTR_DBANK)
00172 #define HAL_FLASH_ERROR_ECCC2     FLASH_FLAG_ECCC2
00173 #define HAL_FLASH_ERROR_ECCD2     FLASH_FLAG_ECCD2
00174 #endif
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup FLASH_Type_Erase FLASH Erase Type
00180   * @{
00181   */
00182 #define FLASH_TYPEERASE_PAGES     0x00U                    /*!<Pages erase only*/
00183 #define FLASH_TYPEERASE_MASSERASE 0x01U                    /*!<Flash mass erase activation*/
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup FLASH_Banks FLASH Banks
00189   * @{
00190   */
00191 #define FLASH_BANK_1              0x00000001U              /*!< Bank 1   */
00192 #if defined (FLASH_OPTR_DBANK)
00193 #define FLASH_BANK_2              0x00000002U              /*!< Bank 2   */
00194 #define FLASH_BANK_BOTH           (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
00195 #else
00196 #define FLASH_BANK_BOTH           FLASH_BANK_1             /*!< Bank 1   */
00197 #endif
00198 /**
00199   * @}
00200   */
00201
00202
00203 /** @defgroup FLASH_Type_Program FLASH Program Type
00204   * @{
00205   */
00206 #define FLASH_TYPEPROGRAM_DOUBLEWORD    0x00U              /*!< Program a double-word (64-bit) at a specified address.*/
00207 #define FLASH_TYPEPROGRAM_FAST          0x01U              /*!< Fast program a 32 row double-word (64-bit) at a specified address.
00208                                                                 And another 32 row double-word (64-bit) will be programmed */
00209 #define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U              /*!< Fast program a 32 row double-word (64-bit) at a specified address.
00210                                                                 And this is the last 32 row double-word (64-bit) programmed */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
00216   * @{
00217   */
00218 #define OPTIONBYTE_WRP            0x01U                    /*!< WRP option byte configuration */
00219 #define OPTIONBYTE_RDP            0x02U                    /*!< RDP option byte configuration */
00220 #define OPTIONBYTE_USER           0x04U                    /*!< USER option byte configuration */
00221 #define OPTIONBYTE_PCROP          0x08U                    /*!< PCROP option byte configuration */
00222 #define OPTIONBYTE_BOOT_LOCK      0x10U                    /*!< Boot lock option byte configuration */
00223 #define OPTIONBYTE_SEC            0x20U                    /*!< Securable memory option byte configuration */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
00229   * @{
00230   */
00231 #define OB_WRPAREA_BANK1_AREAA    0x00U                    /*!< Flash Bank 1 Area A */
00232 #define OB_WRPAREA_BANK1_AREAB    0x01U                    /*!< Flash Bank 1 Area B */
00233 #if defined (FLASH_OPTR_DBANK)
00234 #define OB_WRPAREA_BANK2_AREAA    0x02U                    /*!< Flash Bank 2 Area A */
00235 #define OB_WRPAREA_BANK2_AREAB    0x04U                    /*!< Flash Bank 2 Area B */
00236 #endif
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
00242   * @{
00243   */
00244 #define OB_BOOT_LOCK_DISABLE      0x00000000U              /*!< Boot Lock Disable */
00245 #define OB_BOOT_LOCK_ENABLE       FLASH_SEC1R_BOOT_LOCK    /*!< Boot Lock Enable */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
00251   * @{
00252   */
00253 #define OB_RDP_LEVEL_0            0xAAU
00254 #define OB_RDP_LEVEL_1            0xBBU
00255 #define OB_RDP_LEVEL_2            0xCCU                    /*!< Warning: When enabling read protection level 2
00256                                                                 it's no more possible to go back to level 1 or 0 */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
00262   * @{
00263   */
00264 #define OB_USER_BOR_LEV           0x00000001U              /*!< BOR reset Level */
00265 #define OB_USER_nRST_STOP         0x00000002U              /*!< Reset generated when entering the stop mode */
00266 #define OB_USER_nRST_STDBY        0x00000004U              /*!< Reset generated when entering the standby mode */
00267 #define OB_USER_IWDG_SW           0x00000008U              /*!< Independent watchdog selection */
00268 #define OB_USER_IWDG_STOP         0x00000010U              /*!< Independent watchdog counter freeze in stop mode */
00269 #define OB_USER_IWDG_STDBY        0x00000020U              /*!< Independent watchdog counter freeze in standby mode */
00270 #define OB_USER_WWDG_SW           0x00000040U              /*!< Window watchdog selection */
00271 #if defined (FLASH_OPTR_DBANK)
00272 #define OB_USER_BFB2              0x00000080U              /*!< Dual-bank boot */
00273 #define OB_USER_DBANK             0x00000100U              /*!< Single bank with 128-bits data or two banks with 64-bits data */
00274 #endif
00275 #if defined (FLASH_OPTR_PB4_PUPEN)
00276 #define OB_USER_PB4_PUPEN         0x00000100U              /*!< USB power delivery dead-battery/TDI pull-up */
00277 #endif
00278 #define OB_USER_nBOOT1            0x00000200U              /*!< Boot configuration */
00279 #define OB_USER_SRAM_PE           0x00000400U              /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
00280 #define OB_USER_CCMSRAM_RST       0x00000800U              /*!< CCMSRAM Erase when system reset */
00281 #define OB_USER_nRST_SHDW         0x00001000U              /*!< Reset generated when entering the shutdown mode */
00282 #define OB_USER_nSWBOOT0          0x00002000U              /*!< Software BOOT0 */
00283 #define OB_USER_nBOOT0            0x00004000U              /*!< nBOOT0 option bit */
00284 #define OB_USER_NRST_MODE         0x00008000U              /*!< Reset pin configuration */
00285 #define OB_USER_IRHEN             0x00010000U              /*!< Internal Reset Holder enable */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
00291   * @{
00292   */
00293 #define OB_BOR_LEVEL_0            FLASH_OPTR_BOR_LEV_0     /*!< Reset level threshold is around 1.7V */
00294 #define OB_BOR_LEVEL_1            FLASH_OPTR_BOR_LEV_1     /*!< Reset level threshold is around 2.0V */
00295 #define OB_BOR_LEVEL_2            FLASH_OPTR_BOR_LEV_2     /*!< Reset level threshold is around 2.2V */
00296 #define OB_BOR_LEVEL_3            FLASH_OPTR_BOR_LEV_3     /*!< Reset level threshold is around 2.5V */
00297 #define OB_BOR_LEVEL_4            FLASH_OPTR_BOR_LEV_4     /*!< Reset level threshold is around 2.8V */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
00303   * @{
00304   */
00305 #define OB_STOP_RST               0x00000000U              /*!< Reset generated when entering the stop mode */
00306 #define OB_STOP_NORST             FLASH_OPTR_nRST_STOP     /*!< No reset generated when entering the stop mode */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
00312   * @{
00313   */
00314 #define OB_STANDBY_RST            0x00000000U              /*!< Reset generated when entering the standby mode */
00315 #define OB_STANDBY_NORST          FLASH_OPTR_nRST_STDBY    /*!< No reset generated when entering the standby mode */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
00321   * @{
00322   */
00323 #define OB_SHUTDOWN_RST           0x00000000U              /*!< Reset generated when entering the shutdown mode */
00324 #define OB_SHUTDOWN_NORST         FLASH_OPTR_nRST_SHDW     /*!< No reset generated when entering the shutdown mode */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
00330   * @{
00331   */
00332 #define OB_IWDG_HW                0x00000000U              /*!< Hardware independent watchdog */
00333 #define OB_IWDG_SW                FLASH_OPTR_IWDG_SW       /*!< Software independent watchdog */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
00339   * @{
00340   */
00341 #define OB_IWDG_STOP_FREEZE       0x00000000U              /*!< Independent watchdog counter is frozen in Stop mode */
00342 #define OB_IWDG_STOP_RUN          FLASH_OPTR_IWDG_STOP     /*!< Independent watchdog counter is running in Stop mode */
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
00348   * @{
00349   */
00350 #define OB_IWDG_STDBY_FREEZE      0x00000000U              /*!< Independent watchdog counter is frozen in Standby mode */
00351 #define OB_IWDG_STDBY_RUN         FLASH_OPTR_IWDG_STDBY    /*!< Independent watchdog counter is running in Standby mode */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
00357   * @{
00358   */
00359 #define OB_WWDG_HW                0x00000000U              /*!< Hardware window watchdog */
00360 #define OB_WWDG_SW                FLASH_OPTR_WWDG_SW       /*!< Software window watchdog */
00361 /**
00362   * @}
00363   */
00364
00365 #if defined (FLASH_OPTR_DBANK)
00366 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
00367   * @{
00368   */
00369 #define OB_BFB2_DISABLE           0x00000000U              /*!< Dual-bank boot disable */
00370 #define OB_BFB2_ENABLE            FLASH_OPTR_BFB2          /*!< Dual-bank boot enable */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
00376   * @{
00377   */
00378 #define OB_DBANK_128_BITS         0x00000000U              /*!< Single-bank with 128-bits data */
00379 #define OB_DBANK_64_BITS          FLASH_OPTR_DBANK         /*!< Dual-bank with 64-bits data */
00380 /**
00381   * @}
00382   */
00383 #endif
00384
00385 #if defined (FLASH_OPTR_PB4_PUPEN)
00386 /** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
00387   * @{
00388   */
00389 #define OB_PB4_PUPEN_DISABLE      0x00000000U              /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */
00390 #define OB_PB4_PUPEN_ENABLE       FLASH_OPTR_PB4_PUPEN     /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */
00391 /**
00392   * @}
00393   */
00394 #endif
00395
00396 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
00397   * @{
00398   */
00399 #define OB_BOOT1_SRAM             0x00000000U              /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
00400 #define OB_BOOT1_SYSTEM           FLASH_OPTR_nBOOT1        /*!< System memory is selected as boot space (if BOOT0=1) */
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type
00406   * @{
00407   */
00408 #define OB_SRAM_PARITY_ENABLE     0x00000000U              /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
00409 #define OB_SRAM_PARITY_DISABLE    FLASH_OPTR_SRAM_PE       /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type
00415   * @{
00416   */
00417 #define OB_CCMSRAM_RST_ERASE      0x00000000U              /*!< CCMSRAM erased when a system reset occurs */
00418 #define OB_CCMSRAM_RST_NOT_ERASE  FLASH_OPTR_CCMSRAM_RST   /*!< CCMSRAM is not erased when a system reset occurs */
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
00424   * @{
00425   */
00426 #define OB_BOOT0_FROM_OB          0x00000000U              /*!< BOOT0 taken from the option bit nBOOT0 */
00427 #define OB_BOOT0_FROM_PIN         FLASH_OPTR_nSWBOOT0      /*!< BOOT0 taken from PB8/BOOT0 pin */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
00433   * @{
00434   */
00435 #define OB_nBOOT0_RESET           0x00000000U              /*!< nBOOT0 = 0 */
00436 #define OB_nBOOT0_SET             FLASH_OPTR_nBOOT0        /*!< nBOOT0 = 1 */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
00442   * @{
00443   */
00444 #define OB_NRST_MODE_INPUT_ONLY   FLASH_OPTR_NRST_MODE_0   /*!< Reset pin is in Reset input mode only */
00445 #define OB_NRST_MODE_GPIO         FLASH_OPTR_NRST_MODE_1   /*!< Reset pin is in GPIO mode only */
00446 #define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE     /*!< Reset pin is in reset input and output mode */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit
00452   * @{
00453   */
00454 #define OB_IRH_DISABLE            0x00000000U              /*!< Internal Reset holder disable */
00455 #define OB_IRH_ENABLE             FLASH_OPTR_IRHEN         /*!< Internal Reset holder enable */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
00461   * @{
00462   */
00463 #define OB_PCROP_RDP_NOT_ERASE    0x00000000U              /*!< PCROP area is not erased when the RDP level
00464                                                                 is decreased from Level 1 to Level 0 */
00465 #define OB_PCROP_RDP_ERASE        FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
00466                                                                 decreased from Level 1 to Level 0 (full mass erase) */
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup FLASH_Latency FLASH Latency
00472   * @{
00473   */
00474 #define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS    /*!< FLASH Zero wait state */
00475 #define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS    /*!< FLASH One wait state */
00476 #define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS    /*!< FLASH Two wait states */
00477 #define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS    /*!< FLASH Three wait states */
00478 #define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS    /*!< FLASH Four wait states */
00479 #define FLASH_LATENCY_5           FLASH_ACR_LATENCY_5WS    /*!< FLASH Five wait state */
00480 #define FLASH_LATENCY_6           FLASH_ACR_LATENCY_6WS    /*!< FLASH Six wait state */
00481 #define FLASH_LATENCY_7           FLASH_ACR_LATENCY_7WS    /*!< FLASH Seven wait states */
00482 #define FLASH_LATENCY_8           FLASH_ACR_LATENCY_8WS    /*!< FLASH Eight wait states */
00483 #define FLASH_LATENCY_9           FLASH_ACR_LATENCY_9WS    /*!< FLASH Nine wait states */
00484 #define FLASH_LATENCY_10          FLASH_ACR_LATENCY_10WS   /*!< FLASH Ten wait state */
00485 #define FLASH_LATENCY_11          FLASH_ACR_LATENCY_11WS   /*!< FLASH Eleven wait state */
00486 #define FLASH_LATENCY_12          FLASH_ACR_LATENCY_12WS   /*!< FLASH Twelve wait states */
00487 #define FLASH_LATENCY_13          FLASH_ACR_LATENCY_13WS   /*!< FLASH Thirteen wait states */
00488 #define FLASH_LATENCY_14          FLASH_ACR_LATENCY_14WS   /*!< FLASH Fourteen wait states */
00489 #define FLASH_LATENCY_15          FLASH_ACR_LATENCY_15WS   /*!< FLASH Fifteen wait states */
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup FLASH_Keys FLASH Keys
00495   * @{
00496   */
00497 #define FLASH_KEY1                0x45670123U              /*!< Flash key1 */
00498 #define FLASH_KEY2                0xCDEF89ABU              /*!< Flash key2: used with FLASH_KEY1
00499                                                                 to unlock the FLASH registers access */
00500
00501 #define FLASH_PDKEY1              0x04152637U              /*!< Flash power down key1 */
00502 #define FLASH_PDKEY2              0xFAFBFCFDU              /*!< Flash power down key2: used with FLASH_PDKEY1
00503                                                                 to unlock the RUN_PD bit in FLASH_ACR */
00504
00505 #define FLASH_OPTKEY1             0x08192A3BU              /*!< Flash option byte key1 */
00506 #define FLASH_OPTKEY2             0x4C5D6E7FU              /*!< Flash option byte key2: used with FLASH_OPTKEY1
00507                                                                 to allow option bytes operations */
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup FLASH_Flags FLASH Flags Definition
00513   * @{
00514   */
00515 #define FLASH_FLAG_EOP            FLASH_SR_EOP             /*!< FLASH End of operation flag */
00516 #define FLASH_FLAG_OPERR          FLASH_SR_OPERR           /*!< FLASH Operation error flag */
00517 #define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR         /*!< FLASH Programming error flag */
00518 #define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR          /*!< FLASH Write protection error flag */
00519 #define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR          /*!< FLASH Programming alignment error flag */
00520 #define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR          /*!< FLASH Size error flag  */
00521 #define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR          /*!< FLASH Programming sequence error flag */
00522 #define FLASH_FLAG_MISERR         FLASH_SR_MISERR          /*!< FLASH Fast programming data miss error flag */
00523 #define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR         /*!< FLASH Fast programming error flag */
00524 #define FLASH_FLAG_RDERR          FLASH_SR_RDERR           /*!< FLASH PCROP read error flag */
00525 #define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR         /*!< FLASH Option validity error flag  */
00526 #define FLASH_FLAG_BSY            FLASH_SR_BSY             /*!< FLASH Busy flag */
00527 #define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC          /*!< FLASH ECC correction in 64 LSB bits */
00528 #define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD          /*!< FLASH ECC detection in 64 LSB bits */
00529 #if defined (FLASH_OPTR_DBANK)
00530 #define FLASH_FLAG_ECCC2          FLASH_ECCR_ECCC2         /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */
00531 #define FLASH_FLAG_ECCD2          FLASH_ECCR_ECCD2         /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */
00532 #endif
00533
00534 #define FLASH_FLAG_SR_ERRORS      (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
00535                                    FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
00536                                    FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
00537                                    FLASH_FLAG_OPTVERR)
00538 #if defined (FLASH_OPTR_DBANK)
00539 #define FLASH_FLAG_ECCR_ERRORS    (FLASH_FLAG_ECCC    | FLASH_FLAG_ECCD    | FLASH_FLAG_ECCC2  | FLASH_FLAG_ECCD2)
00540 #else
00541 #define FLASH_FLAG_ECCR_ERRORS    (FLASH_FLAG_ECCC    | FLASH_FLAG_ECCD)
00542 #endif
00543 #define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
00549   * @brief FLASH Interrupt definition
00550   * @{
00551   */
00552 #define FLASH_IT_EOP              FLASH_CR_EOPIE           /*!< End of FLASH Operation Interrupt source */
00553 #define FLASH_IT_OPERR            FLASH_CR_ERRIE           /*!< Error Interrupt source */
00554 #define FLASH_IT_RDERR            FLASH_CR_RDERRIE         /*!< PCROP Read Error Interrupt source*/
00555 #define FLASH_IT_ECCC            (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
00556 /**
00557   * @}
00558   */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /* Exported macros -----------------------------------------------------------*/
00565 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00566   * @brief macros to control FLASH features
00567   * @{
00568   */
00569
00570 /**
00571   * @brief  Set the FLASH Latency.
00572   * @param  __LATENCY__ FLASH Latency.
00573   *         This parameter can be one of the following values :
00574   *           @arg FLASH_LATENCY_0:  FLASH Zero wait state
00575   *           @arg FLASH_LATENCY_1:  FLASH One wait state
00576   *           @arg FLASH_LATENCY_2:  FLASH Two wait states
00577   *           @arg FLASH_LATENCY_3:  FLASH Three wait states
00578   *           @arg FLASH_LATENCY_4:  FLASH Four wait states
00579   *           @arg FLASH_LATENCY_5:  FLASH Five wait states
00580   *           @arg FLASH_LATENCY_6:  FLASH Six wait states
00581   *           @arg FLASH_LATENCY_7:  FLASH Seven wait states
00582   *           @arg FLASH_LATENCY_8:  FLASH Eight wait states
00583   *           @arg FLASH_LATENCY_9:  FLASH Nine wait states
00584   *           @arg FLASH_LATENCY_10: FLASH Ten wait state
00585   *           @arg FLASH_LATENCY_11: FLASH Eleven wait state
00586   *           @arg FLASH_LATENCY_12: FLASH Twelve wait states
00587   *           @arg FLASH_LATENCY_13: FLASH Thirteen wait states
00588   *           @arg FLASH_LATENCY_14: FLASH Fourteen wait states
00589   *           @arg FLASH_LATENCY_15: FLASH Fifteen wait states
00590   * @retval None
00591   */
00592 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
00593
00594 /**
00595   * @brief  Get the FLASH Latency.
00596   * @retval FLASH_Latency.
00597   *         This parameter can be one of the following values :
00598   *           @arg FLASH_LATENCY_0:  FLASH Zero wait state
00599   *           @arg FLASH_LATENCY_1:  FLASH One wait state
00600   *           @arg FLASH_LATENCY_2:  FLASH Two wait states
00601   *           @arg FLASH_LATENCY_3:  FLASH Three wait states
00602   *           @arg FLASH_LATENCY_4:  FLASH Four wait states
00603   *           @arg FLASH_LATENCY_5:  FLASH Five wait states
00604   *           @arg FLASH_LATENCY_6:  FLASH Six wait states
00605   *           @arg FLASH_LATENCY_7:  FLASH Seven wait states
00606   *           @arg FLASH_LATENCY_8:  FLASH Eight wait states
00607   *           @arg FLASH_LATENCY_9:  FLASH Nine wait states
00608   *           @arg FLASH_LATENCY_10: FLASH Ten wait state
00609   *           @arg FLASH_LATENCY_11: FLASH Eleven wait state
00610   *           @arg FLASH_LATENCY_12: FLASH Twelve wait states
00611   *           @arg FLASH_LATENCY_13: FLASH Thirteen wait states
00612   *           @arg FLASH_LATENCY_14: FLASH Fourteen wait states
00613   *           @arg FLASH_LATENCY_15: FLASH Fifteen wait states
00614   */
00615 #define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
00616
00617 /**
00618   * @brief  Enable the FLASH prefetch buffer.
00619   * @retval None
00620   */
00621 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00622
00623 /**
00624   * @brief  Disable the FLASH prefetch buffer.
00625   * @retval None
00626   */
00627 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00628
00629 /**
00630   * @brief  Enable the FLASH instruction cache.
00631   * @retval none
00632   */
00633 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00634
00635 /**
00636   * @brief  Disable the FLASH instruction cache.
00637   * @retval none
00638   */
00639 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00640
00641 /**
00642   * @brief  Enable the FLASH data cache.
00643   * @retval none
00644   */
00645 #define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00646
00647 /**
00648   * @brief  Disable the FLASH data cache.
00649   * @retval none
00650   */
00651 #define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00652
00653 /**
00654   * @brief  Reset the FLASH instruction Cache.
00655   * @note   This function must be used only when the Instruction Cache is disabled.
00656   * @retval None
00657   */
00658 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
00659                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
00660                                                    } while (0)
00661
00662 /**
00663   * @brief  Reset the FLASH data Cache.
00664   * @note   This function must be used only when the data Cache is disabled.
00665   * @retval None
00666   */
00667 #define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
00668                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
00669                                                    } while (0)
00670
00671 /**
00672   * @brief  Enable the FLASH power down during Low-power run mode.
00673   * @note   Writing this bit to 1, automatically the keys are
00674   *         lost and a new unlock sequence is necessary to re-write it to 0.
00675   */
00676 #define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
00677                                                      WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
00678                                                      SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
00679                                                    } while (0)
00680
00681 /**
00682   * @brief  Disable the FLASH power down during Low-power run mode.
00683   * @note   Writing this bit to 0, automatically the keys are
00684   *         lost and a new unlock sequence is necessary to re-write it to 1.
00685   */
00686 #define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
00687                                                      WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
00688                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
00689                                                    } while (0)
00690
00691 /**
00692   * @brief  Enable the FLASH power down during Low-Power sleep mode
00693   * @retval none
00694   */
00695 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
00696
00697 /**
00698   * @brief  Disable the FLASH power down during Low-Power sleep mode
00699   * @retval none
00700   */
00701 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
00702
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
00708   *  @brief macros to handle FLASH interrupts
00709   * @{
00710   */
00711
00712 /**
00713   * @brief  Enable the specified FLASH interrupt.
00714   * @param  __INTERRUPT__ FLASH interrupt
00715   *         This parameter can be any combination of the following values:
00716   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00717   *     @arg FLASH_IT_OPERR: Error Interrupt
00718   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
00719   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
00720   * @retval none
00721   */
00722 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
00723                                                      if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00724                                                    } while (0)
00725
00726 /**
00727   * @brief  Disable the specified FLASH interrupt.
00728   * @param  __INTERRUPT__ FLASH interrupt
00729   *         This parameter can be any combination of the following values:
00730   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00731   *     @arg FLASH_IT_OPERR: Error Interrupt
00732   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
00733   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
00734   * @retval none
00735   */
00736 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
00737                                                      if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00738                                                    } while (0)
00739
00740 /**
00741   * @brief  Check whether the specified FLASH flag is set or not.
00742   * @param  __FLAG__ specifies the FLASH flag to check.
00743   *   This parameter can be one of the following values:
00744   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
00745   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
00746   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
00747   *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
00748   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
00749   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
00750   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
00751   *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
00752   *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
00753   *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
00754   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
00755   *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
00756   *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
00757   *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
00758   *     @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
00759   *     @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
00760   * @note  (*) availability depends on devices
00761   * @retval The new state of FLASH_FLAG (SET or RESET).
00762   */
00763 #define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
00764                                                  (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
00765                                                  (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
00766
00767 /**
00768   * @brief  Clear the FLASH's pending flags.
00769   * @param  __FLAG__ specifies the FLASH flags to clear.
00770   *   This parameter can be any combination of the following values:
00771   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
00772   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
00773   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
00774   *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
00775   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
00776   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
00777   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
00778   *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
00779   *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
00780   *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
00781   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
00782   *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
00783   *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
00784   *     @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
00785   *     @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
00786   *     @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
00787   *     @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
00788   * @note  (*) availability depends on devices
00789   * @retval None
00790   */
00791 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
00792                                                      if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
00793                                                    } while (0)
00794 /**
00795   * @}
00796   */
00797
00798 /* Include FLASH HAL Extended module */
00799 #include "stm32g4xx_hal_flash_ex.h"
00800 #include "stm32g4xx_hal_flash_ramfunc.h"
00801
00802 /* Exported variables --------------------------------------------------------*/
00803 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables
00804   * @{
00805   */
00806 extern FLASH_ProcessTypeDef pFlash;
00807 /**
00808   * @}
00809   */
00810
00811 /* Exported functions --------------------------------------------------------*/
00812 /** @addtogroup FLASH_Exported_Functions
00813   * @{
00814   */
00815
00816 /* Program operation functions  ***********************************************/
00817 /** @addtogroup FLASH_Exported_Functions_Group1
00818   * @{
00819   */
00820 HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00821 HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00822 /* FLASH IRQ handler method */
00823 void               HAL_FLASH_IRQHandler(void);
00824 /* Callbacks in non blocking modes */
00825 void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00826 void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00827 /**
00828   * @}
00829   */
00830
00831 /* Peripheral Control functions  **********************************************/
00832 /** @addtogroup FLASH_Exported_Functions_Group2
00833   * @{
00834   */
00835 HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
00836 HAL_StatusTypeDef  HAL_FLASH_Lock(void);
00837 /* Option bytes control */
00838 HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
00839 HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
00840 HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
00841 /**
00842   * @}
00843   */
00844
00845 /* Peripheral State functions  ************************************************/
00846 /** @addtogroup FLASH_Exported_Functions_Group3
00847   * @{
00848   */
00849 uint32_t HAL_FLASH_GetError(void);
00850 /**
00851   * @}
00852   */
00853
00854 /**
00855   * @}
00856   */
00857
00858 /** @addtogroup FLASH_Private_Functions
00859   * @{
00860   */
00861 HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
00862 /**
00863   * @}
00864   */
00865
00866 /* Private constants --------------------------------------------------------*/
00867 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00868   * @{
00869   */
00870 #define FLASH_SIZE_DATA_REGISTER        FLASHSIZE_BASE
00871
00872 #if defined (FLASH_OPTR_DBANK)
00873 #define FLASH_SIZE                      ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \
00874                                         (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
00875 #define FLASH_BANK_SIZE                 (FLASH_SIZE >> 1)
00876 #define FLASH_PAGE_NB                   ((FLASH_SIZE == 0x00080000U) ? 128U : \
00877                                         ((FLASH_SIZE == 0x00040000U) ? 64U : 32U))
00878 #define FLASH_PAGE_SIZE_128_BITS        0x1000U /* 4 KB */
00879 #else
00880 #define FLASH_SIZE                      ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
00881                                         (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
00882 #define FLASH_BANK_SIZE                 (FLASH_SIZE)
00883 #define FLASH_PAGE_NB                   ((FLASH_SIZE == 0x00080000U) ? 256U : \
00884                                         ((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
00885 #endif
00886
00887 #define FLASH_PAGE_SIZE                 0x800U  /* 2 KB */
00888
00889 #define FLASH_TIMEOUT_VALUE             1000U   /* 1 s  */
00890
00891 /**
00892   * @}
00893   */
00894
00895 /* Private macros ------------------------------------------------------------*/
00896 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00897   *  @{
00898   */
00899
00900 #define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
00901                                             ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00902
00903 #if defined (FLASH_OPTR_DBANK)
00904 #define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
00905                                             ((BANK) == FLASH_BANK_2)  || \
00906                                             ((BANK) == FLASH_BANK_BOTH))
00907
00908 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
00909                                             ((BANK) == FLASH_BANK_2))
00910 #else
00911 #define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)
00912
00913 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)
00914 #endif
00915
00916 #define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
00917                                             ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
00918                                             ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00919
00920 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
00921
00922 #define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
00923
00924 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
00925
00926 #define IS_FLASH_PAGE(PAGE)                ((PAGE) < FLASH_PAGE_NB)
00927
00928 #define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
00929                                             OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
00930
00931 #if defined (FLASH_OPTR_DBANK)
00932 #define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
00933                                             ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
00934 #else
00935 #define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
00936 #endif
00937
00938 #define IS_OB_BOOT_LOCK(VALUE)             (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
00939
00940 #define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0) ||\
00941                                             ((LEVEL) == OB_RDP_LEVEL_1) ||\
00942                                             ((LEVEL) == OB_RDP_LEVEL_2))
00943
00944 #define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
00945
00946 #define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
00947                                             ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
00948                                             ((LEVEL) == OB_BOR_LEVEL_4))
00949
00950 #define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
00951
00952 #define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
00953
00954 #define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
00955
00956 #define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
00957
00958 #define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
00959
00960 #define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
00961
00962 #define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
00963
00964 #if defined (FLASH_OPTR_DBANK)
00965 #define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
00966
00967 #define IS_OB_USER_DBANK(VALUE)            (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
00968 #endif
00969
00970 #if defined (FLASH_OPTR_PB4_PUPEN)
00971 #define IS_OB_USER_PB4_PUPEN(VALUE)        (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
00972 #endif
00973
00974 #define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
00975
00976 #define IS_OB_USER_SRAM_PARITY(VALUE)      (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
00977
00978 #define IS_OB_USER_CCMSRAM_RST(VALUE)      (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
00979
00980 #define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
00981
00982 #define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
00983
00984 #define IS_OB_USER_NRST_MODE(VALUE)        (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
00985                                             ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
00986
00987 #define IS_OB_USER_IRHEN(VALUE)            (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
00988
00989 #define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
00990
00991 #define IS_OB_SECMEM_SIZE(VALUE)           ((VALUE) <= FLASH_PAGE_NB)
00992
00993 #define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
00994                                             ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
00995                                             ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
00996                                             ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
00997                                             ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
00998                                             ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
00999                                             ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
01000                                             ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
01001 /**
01002   * @}
01003   */
01004
01005 /**
01006   * @}
01007   */
01008
01009 /**
01010   * @}
01011   */
01012
01013 #ifdef __cplusplus
01014 }
01015 #endif
01016
01017 #endif /* STM32G4xx_HAL_FLASH_H */
01018
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_flash_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the FLASH extended peripheral:
00008   *           + Extended programming operations functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                    ##### Flash Extended features #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the FLASH interface for STM32G4xx
00016        devices contains the following additional features
00017
00018        (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write
00019            capability (RWW)
00020        (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits
00021        (+) Protected areas including WRP, PCROP and Securable memory
00022
00023                         ##### How to use this driver #####
00024   ==============================================================================
00025   [..] This driver provides functions to configure and program the FLASH memory
00026        of all STM32G4xx devices. It includes
00027       (#) Flash Memory Erase functions:
00028            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00029                 HAL_FLASH_Lock() functions
00030            (++) Erase function: Erase pages, or mass erase banks
00031            (++) There are two modes of erase :
00032              (+++) Polling Mode using HAL_FLASHEx_Erase()
00033              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00034
00035       (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
00036         (++) Configure the write protection areas (WRP)
00037         (++) Set the Read protection Level (RDP)
00038         (++) Program the user Option Bytes
00039         (++) Configure the Proprietary Code ReadOut protection areas (PCROP)
00040         (++) Configure the Securable memory areas
00041         (++) Configure the Boot Lock
00042
00043       (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
00044         (++) Get the configuration of write protection areas (WRP)
00045         (++) Get the level of read protection (RDP)
00046         (++) Get the value of the user Option Bytes
00047         (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP)
00048         (++) Get the configuration of Securable memory areas
00049         (++) Get the status of Boot Lock
00050
00051       (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection()
00052         (++) Deny the access to securable memory area
00053
00054       (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or
00055           HAL_FLASHEx_DisableDebugger()
00056
00057   @endverbatim
00058   ******************************************************************************
00059   * @attention
00060   *
00061   * Copyright (c) 2019 STMicroelectronics.
00062   * All rights reserved.
00063   *
00064   * This software is licensed under terms that can be found in the LICENSE file in
00065   * the root directory of this software component.
00066   * If no LICENSE file comes with this software, it is provided AS-IS.
00067   ******************************************************************************
00068   */
00069
00070 /* Includes ------------------------------------------------------------------*/
00071 #include "stm32g4xx_hal.h"
00072
00073 /** @addtogroup STM32G4xx_HAL_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup FLASHEx FLASHEx
00078   * @brief FLASH Extended HAL module driver
00079   * @{
00080   */
00081
00082 #ifdef HAL_FLASH_MODULE_ENABLED
00083
00084 /* Private typedef -----------------------------------------------------------*/
00085 /* Private define ------------------------------------------------------------*/
00086 /* Private macro -------------------------------------------------------------*/
00087 /* Private variables ---------------------------------------------------------*/
00088 /* Private function prototypes -----------------------------------------------*/
00089 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00090   * @{
00091   */
00092 static void              FLASH_MassErase(uint32_t Banks);
00093 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
00094 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
00095 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
00096 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
00097 static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
00098 static uint32_t          FLASH_OB_GetRDP(void);
00099 static uint32_t          FLASH_OB_GetUser(void);
00100 static void              FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr);
00101 static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank, uint32_t SecMemSize);
00102 static void              FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize);
00103 static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
00104 static uint32_t          FLASH_OB_GetBootLock(void);
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions -------------------------------------------------------*/
00111 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00116   * @brief   Extended IO operation functions
00117   *
00118 @verbatim
00119  ===============================================================================
00120                 ##### Extended programming operation functions #####
00121  ===============================================================================
00122     [..]
00123     This subsection provides a set of functions allowing to manage the Extended FLASH
00124     programming operations Operations.
00125
00126 @endverbatim
00127   * @{
00128   */
00129 /**
00130   * @brief  Perform a mass erase or erase the specified FLASH memory pages.
00131   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00132   *         contains the configuration information for the erasing.
00133   * @param[out]  PageError pointer to variable that contains the configuration
00134   *         information on faulty page in case of error (0xFFFFFFFF means that all
00135   *         the pages have been correctly erased).
00136   * @retval HAL_Status
00137   */
00138 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00139 {
00140   HAL_StatusTypeDef status;
00141   uint32_t page_index;
00142
00143   /* Check the parameters */
00144   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00145
00146   /* Process Locked */
00147   __HAL_LOCK(&pFlash);
00148
00149   /* Wait for last operation to be completed */
00150   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00151
00152   if (status == HAL_OK)
00153   {
00154     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00155
00156     /* Deactivate the cache if they are activated to avoid data misbehavior */
00157     if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
00158     {
00159       if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00160       {
00161         /* Disable data cache  */
00162         __HAL_FLASH_DATA_CACHE_DISABLE();
00163         pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
00164       }
00165       else
00166       {
00167         pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
00168       }
00169     }
00170     else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00171     {
00172       /* Disable data cache  */
00173       __HAL_FLASH_DATA_CACHE_DISABLE();
00174       pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
00175     }
00176     else
00177     {
00178       pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
00179     }
00180
00181     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00182     {
00183       /* Mass erase to be done */
00184       FLASH_MassErase(pEraseInit->Banks);
00185
00186       /* Wait for last operation to be completed */
00187       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00188
00189 #if defined (FLASH_OPTR_DBANK)
00190       /* If the erase operation is completed, disable the MER1 and MER2 Bits */
00191       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
00192 #else
00193       /* If the erase operation is completed, disable the MER1 Bit */
00194       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
00195 #endif
00196     }
00197     else
00198     {
00199       /*Initialization of PageError variable*/
00200       *PageError = 0xFFFFFFFFU;
00201
00202       for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
00203       {
00204         FLASH_PageErase(page_index, pEraseInit->Banks);
00205
00206         /* Wait for last operation to be completed */
00207         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00208
00209         /* If the erase operation is completed, disable the PER Bit */
00210         CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
00211
00212         if (status != HAL_OK)
00213         {
00214           /* In case of error, stop erase procedure and return the faulty page */
00215           *PageError = page_index;
00216           break;
00217         }
00218       }
00219     }
00220
00221     /* Flush the caches to be sure of the data consistency */
00222     FLASH_FlushCaches();
00223   }
00224
00225   /* Process Unlocked */
00226   __HAL_UNLOCK(&pFlash);
00227
00228   return status;
00229 }
00230
00231 /**
00232   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
00233   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00234   *         contains the configuration information for the erasing.
00235   * @retval HAL_Status
00236   */
00237 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00238 {
00239   HAL_StatusTypeDef status = HAL_OK;
00240
00241   /* Process Locked */
00242   __HAL_LOCK(&pFlash);
00243
00244   /* Check the parameters */
00245   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00246
00247   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00248
00249   /* Deactivate the cache if they are activated to avoid data misbehavior */
00250   if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
00251   {
00252     if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00253     {
00254       /* Disable data cache  */
00255       __HAL_FLASH_DATA_CACHE_DISABLE();
00256       pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
00257     }
00258     else
00259     {
00260       pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
00261     }
00262   }
00263   else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00264   {
00265     /* Disable data cache  */
00266     __HAL_FLASH_DATA_CACHE_DISABLE();
00267     pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
00268   }
00269   else
00270   {
00271     pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
00272   }
00273
00274   /* Enable End of Operation and Error interrupts */
00275   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00276
00277   pFlash.Bank = pEraseInit->Banks;
00278
00279   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00280   {
00281     /* Mass erase to be done */
00282     pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
00283     FLASH_MassErase(pEraseInit->Banks);
00284   }
00285   else
00286   {
00287     /* Erase by page to be done */
00288     pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
00289     pFlash.NbPagesToErase = pEraseInit->NbPages;
00290     pFlash.Page = pEraseInit->Page;
00291
00292     /*Erase 1st page and wait for IT */
00293     FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
00294   }
00295
00296   return status;
00297 }
00298
00299 /**
00300   * @brief  Program Option bytes.
00301   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00302   *         contains the configuration information for the programming.
00303   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00304   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
00305   * @note   New option bytes configuration will be taken into account in two cases:
00306   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
00307   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
00308   * @retval HAL_Status
00309   */
00310 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00311 {
00312   HAL_StatusTypeDef status = HAL_OK;
00313
00314   /* Check the parameters */
00315   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00316
00317   /* Process Locked */
00318   __HAL_LOCK(&pFlash);
00319
00320   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00321
00322   /* Write protection configuration */
00323   if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
00324   {
00325     /* Configure of Write protection on the selected area */
00326     if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
00327     {
00328       status = HAL_ERROR;
00329     }
00330   }
00331
00332   /* Read protection configuration */
00333   if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
00334   {
00335     /* Configure the Read protection level */
00336     if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
00337     {
00338       status = HAL_ERROR;
00339     }
00340   }
00341
00342   /* User Configuration */
00343   if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
00344   {
00345     /* Configure the user option bytes */
00346     if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
00347     {
00348       status = HAL_ERROR;
00349     }
00350   }
00351
00352   /* PCROP Configuration */
00353   if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
00354   {
00355     if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
00356     {
00357       /* Configure the Proprietary code readout protection */
00358       if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
00359       {
00360         status = HAL_ERROR;
00361       }
00362     }
00363   }
00364
00365   /* Securable memory Configuration */
00366   if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U)
00367   {
00368     /* Configure the securable memory area */
00369     if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK)
00370     {
00371       status = HAL_ERROR;
00372     }
00373   }
00374
00375   /* Boot Entry Point Configuration */
00376   if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
00377   {
00378     /* Configure the boot unique entry point option */
00379     if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK)
00380     {
00381       status = HAL_ERROR;
00382     }
00383   }
00384
00385   /* Process Unlocked */
00386   __HAL_UNLOCK(&pFlash);
00387
00388   return status;
00389 }
00390
00391 /**
00392   * @brief  Get the Option bytes configuration.
00393   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that contains the
00394   *         configuration information.
00395   * @note   The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
00396   *         which area is requested for the WRP and PCROP, else no information will be returned.
00397   * @retval None
00398   */
00399 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00400 {
00401   pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
00402
00403 #if defined (FLASH_OPTR_DBANK)
00404   if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
00405       (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
00406 #else
00407   if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
00408 #endif
00409   {
00410     pOBInit->OptionType |= OPTIONBYTE_WRP;
00411     /* Get write protection on the selected area */
00412     FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
00413   }
00414
00415   /* Get Read protection level */
00416   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00417
00418   /* Get the user option bytes */
00419   pOBInit->USERConfig = FLASH_OB_GetUser();
00420
00421 #if defined (FLASH_OPTR_DBANK)
00422   if ((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
00423 #else
00424   if (pOBInit->PCROPConfig == FLASH_BANK_1)
00425 #endif
00426   {
00427     pOBInit->OptionType |= OPTIONBYTE_PCROP;
00428     /* Get the Proprietary code readout protection */
00429     FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
00430   }
00431
00432   pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
00433
00434   /* Get the boot entry point */
00435   pOBInit->BootEntryPoint = FLASH_OB_GetBootLock();
00436
00437   /* Get the securable memory area configuration */
00438 #if defined (FLASH_OPTR_DBANK)
00439   if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2))
00440 #else
00441   if (pOBInit->SecBank == FLASH_BANK_1)
00442 #endif
00443   {
00444     pOBInit->OptionType |= OPTIONBYTE_SEC;
00445     FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize));
00446   }
00447 }
00448
00449 /**
00450   * @brief  Enable the FLASH Securable Memory protection.
00451   * @param  Bank: Bank to be protected
00452   *          This parameter can be one of the following values:
00453   *            @arg FLASH_BANK_1: Bank1 to be protected
00454   *            @arg FLASH_BANK_2: Bank2 to be protected (*)
00455   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*)
00456   * @note   (*) availability depends on devices
00457   * @retval HAL Status
00458   */
00459 HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank)
00460 {
00461 #if defined (FLASH_OPTR_DBANK)
00462   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
00463   {
00464     /* Check the parameters */
00465     assert_param(IS_FLASH_BANK(Bank));
00466
00467     /* Enable the Securable Memory Protection Bit for the bank 1 if requested */
00468     if ((Bank & FLASH_BANK_1) != 0U)
00469     {
00470       SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
00471     }
00472
00473     /* Enable the Securable Memory Protection Bit for the bank 2 if requested */
00474     if ((Bank & FLASH_BANK_2) != 0U)
00475     {
00476       SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2);
00477     }
00478   }
00479   else
00480 #endif
00481   {
00482     SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1);
00483   }
00484
00485   return HAL_OK;
00486 }
00487
00488 /**
00489   * @brief  Enable Debugger.
00490   * @note   After calling this API, flash interface allow debugger intrusion.
00491   * @retval None
00492   */
00493 void HAL_FLASHEx_EnableDebugger(void)
00494 {
00495   FLASH->ACR |= FLASH_ACR_DBG_SWEN;
00496 }
00497
00498
00499 /**
00500   * @brief  Disable Debugger.
00501   * @note   After calling this API, Debugger is disabled: it's no more possible to
00502   *         break, see CPU register, etc...
00503   * @retval None
00504   */
00505 void HAL_FLASHEx_DisableDebugger(void)
00506 {
00507   FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
00508 }
00509
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /* Private functions ---------------------------------------------------------*/
00519
00520 /** @addtogroup FLASHEx_Private_Functions
00521   * @{
00522   */
00523 /**
00524   * @brief  Mass erase of FLASH memory.
00525   * @param  Banks Banks to be erased.
00526   *         This parameter can be one of the following values:
00527   *            @arg FLASH_BANK_1: Bank1 to be erased
00528   *            @arg FLASH_BANK_2: Bank2 to be erased (*)
00529   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*)
00530   * @note   (*) availability depends on devices
00531   * @retval None
00532   */
00533 static void FLASH_MassErase(uint32_t Banks)
00534 {
00535 #if defined (FLASH_OPTR_DBANK)
00536   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
00537 #endif
00538   {
00539     /* Check the parameters */
00540     assert_param(IS_FLASH_BANK(Banks));
00541
00542     /* Set the Mass Erase Bit for the bank 1 if requested */
00543     if ((Banks & FLASH_BANK_1) != 0U)
00544     {
00545       SET_BIT(FLASH->CR, FLASH_CR_MER1);
00546     }
00547
00548 #if defined (FLASH_OPTR_DBANK)
00549     /* Set the Mass Erase Bit for the bank 2 if requested */
00550     if ((Banks & FLASH_BANK_2) != 0U)
00551     {
00552       SET_BIT(FLASH->CR, FLASH_CR_MER2);
00553     }
00554 #endif
00555   }
00556 #if defined (FLASH_OPTR_DBANK)
00557   else
00558   {
00559     SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
00560   }
00561 #endif
00562
00563   /* Proceed to erase all sectors */
00564   SET_BIT(FLASH->CR, FLASH_CR_STRT);
00565 }
00566
00567 /**
00568   * @brief  Erase the specified FLASH memory page.
00569   * @param  Page FLASH page to erase.
00570   *         This parameter must be a value between 0 and (max number of pages in the bank - 1).
00571   * @param  Banks Bank where the page will be erased.
00572   *         This parameter can be one of the following values:
00573   *            @arg FLASH_BANK_1: Page in bank 1 to be erased
00574   *            @arg FLASH_BANK_2: Page in bank 2 to be erased (*)
00575   * @note   (*) availability depends on devices
00576   * @retval None
00577   */
00578 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
00579 {
00580   /* Check the parameters */
00581   assert_param(IS_FLASH_PAGE(Page));
00582
00583 #if defined (FLASH_OPTR_DBANK)
00584   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
00585   {
00586     CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
00587   }
00588   else
00589   {
00590     assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
00591
00592     if ((Banks & FLASH_BANK_1) != 0U)
00593     {
00594       CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
00595     }
00596     else
00597     {
00598       SET_BIT(FLASH->CR, FLASH_CR_BKER);
00599     }
00600   }
00601 #endif
00602
00603   /* Proceed to erase the page */
00604   MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
00605   SET_BIT(FLASH->CR, FLASH_CR_PER);
00606   SET_BIT(FLASH->CR, FLASH_CR_STRT);
00607 }
00608
00609 /**
00610   * @brief  Flush the instruction and data caches.
00611   * @retval None
00612   */
00613 void FLASH_FlushCaches(void)
00614 {
00615   FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
00616
00617   /* Flush instruction cache  */
00618   if ((cache == FLASH_CACHE_ICACHE_ENABLED) ||
00619       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
00620   {
00621     /* Disable instruction cache */
00622     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00623     /* Reset instruction cache */
00624     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
00625     /* Enable instruction cache */
00626     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
00627   }
00628
00629   /* Flush data cache */
00630   if ((cache == FLASH_CACHE_DCACHE_ENABLED) ||
00631       (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
00632   {
00633     /* Reset data cache */
00634     __HAL_FLASH_DATA_CACHE_RESET();
00635     /* Enable data cache */
00636     __HAL_FLASH_DATA_CACHE_ENABLE();
00637   }
00638
00639   /* Reset internal variable */
00640   pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
00641 }
00642
00643 /**
00644   * @brief  Configure the write protection area into Option Bytes.
00645   * @note   When the memory read protection level is selected (RDP level = 1),
00646   *         it is not possible to program or erase Flash memory if the CPU debug
00647   *         features are connected (JTAG or single wire) or boot code is being
00648   *         executed from RAM or System flash, even if WRP is not activated.
00649   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00650   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
00651   * @note   New option bytes configuration will be taken into account in two cases:
00652   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
00653   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
00654   * @param  WRPArea specifies the area to be configured.
00655   *         This parameter can be one of the following values:
00656   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
00657   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
00658   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*)
00659   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*)
00660   * @note   (*) availability depends on devices
00661   * @param  WRPStartOffset specifies the start page of the write protected area.
00662   *         This parameter can be page number between 0 and (max number of pages in the bank - 1).
00663   * @param  WRDPEndOffset specifies the end page of the write protected area.
00664   *         This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1).
00665   * @retval HAL_Status
00666   */
00667 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
00668 {
00669   HAL_StatusTypeDef status;
00670
00671   /* Check the parameters */
00672   assert_param(IS_OB_WRPAREA(WRPArea));
00673   assert_param(IS_FLASH_PAGE(WRPStartOffset));
00674   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
00675
00676   /* Wait for last operation to be completed */
00677   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00678
00679   if (status == HAL_OK)
00680   {
00681     /* Configure the write protected area */
00682     if (WRPArea == OB_WRPAREA_BANK1_AREAA)
00683     {
00684       FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
00685     }
00686     else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
00687     {
00688       FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
00689     }
00690 #if defined (FLASH_OPTR_DBANK)
00691     else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
00692     {
00693       FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
00694     }
00695     else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
00696     {
00697       FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
00698     }
00699 #endif
00700     else
00701     {
00702       /* Nothing to do */
00703     }
00704
00705     /* Set OPTSTRT Bit */
00706     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00707
00708     /* Wait for last operation to be completed */
00709     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00710   }
00711
00712   return status;
00713 }
00714
00715 /**
00716   * @brief  Set the read protection level into Option Bytes.
00717   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00718   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
00719   * @note   New option bytes configuration will be taken into account in two cases:
00720   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
00721   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
00722   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
00723   *         to go back to level 1 or 0 !!!
00724   * @param  RDPLevel specifies the read protection level.
00725   *         This parameter can be one of the following values:
00726   *            @arg OB_RDP_LEVEL_0: No protection
00727   *            @arg OB_RDP_LEVEL_1: Memory Read protection
00728   *            @arg OB_RDP_LEVEL_2: Full chip protection
00729   *
00730   * @retval HAL_Status
00731   */
00732 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
00733 {
00734   HAL_StatusTypeDef status;
00735
00736   /* Check the parameters */
00737   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
00738
00739   /* Wait for last operation to be completed */
00740   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00741
00742   if (status == HAL_OK)
00743   {
00744     /* Configure the RDP level in the option bytes register */
00745     MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
00746
00747     /* Set OPTSTRT Bit */
00748     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00749
00750     /* Wait for last operation to be completed */
00751     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00752   }
00753
00754   return status;
00755 }
00756
00757 /**
00758   * @brief  Program the FLASH User Option Bytes.
00759   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00760   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
00761   * @note   New option bytes configuration will be taken into account in two cases:
00762   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
00763   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
00764   * @param  UserType The FLASH User Option Bytes to be modified.
00765   *         This parameter can be a combination of @ref FLASH_OB_USER_Type.
00766   * @param  UserConfig The selected User Option Bytes values:
00767   *         This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
00768   *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY ,
00769   *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
00770   *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
00771   *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
00772   *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1,
00773   *         @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST,
00774   *         @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
00775   *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
00776   * @note   (*) availability depends on devices
00777   * @retval HAL_Status
00778   */
00779 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
00780 {
00781   uint32_t optr_reg_val = 0;
00782   uint32_t optr_reg_mask = 0;
00783   HAL_StatusTypeDef status;
00784
00785   /* Check the parameters */
00786   assert_param(IS_OB_USER_TYPE(UserType));
00787
00788   /* Wait for last operation to be completed */
00789   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00790
00791   if (status == HAL_OK)
00792   {
00793 #if defined(FLASH_OPTR_PB4_PUPEN)
00794     if ((UserType & OB_USER_PB4_PUPEN) != 0U)
00795     {
00796       /* PB4_PUPEN option byte should be modified */
00797       assert_param(IS_OB_USER_PB4_PUPEN(UserConfig & FLASH_OPTR_PB4_PUPEN));
00798
00799       /* Set value and mask for PB4_PUPEN option byte */
00800       optr_reg_val |= (UserConfig & FLASH_OPTR_PB4_PUPEN);
00801       optr_reg_mask |= FLASH_OPTR_PB4_PUPEN;
00802     }
00803 #endif /* FLASH_OPTR_PB4_PUPEN */
00804
00805     if ((UserType & OB_USER_BOR_LEV) != 0U)
00806     {
00807       /* BOR level option byte should be modified */
00808       assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
00809
00810       /* Set value and mask for BOR level option byte */
00811       optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
00812       optr_reg_mask |= FLASH_OPTR_BOR_LEV;
00813     }
00814
00815     if ((UserType & OB_USER_nRST_STOP) != 0U)
00816     {
00817       /* nRST_STOP option byte should be modified */
00818       assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
00819
00820       /* Set value and mask for nRST_STOP option byte */
00821       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
00822       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
00823     }
00824
00825     if ((UserType & OB_USER_nRST_STDBY) != 0U)
00826     {
00827       /* nRST_STDBY option byte should be modified */
00828       assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
00829
00830       /* Set value and mask for nRST_STDBY option byte */
00831       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
00832       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
00833     }
00834
00835     if ((UserType & OB_USER_nRST_SHDW) != 0U)
00836     {
00837       /* nRST_SHDW option byte should be modified */
00838       assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
00839
00840       /* Set value and mask for nRST_SHDW option byte */
00841       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
00842       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
00843     }
00844
00845     if ((UserType & OB_USER_IWDG_SW) != 0U)
00846     {
00847       /* IWDG_SW option byte should be modified */
00848       assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
00849
00850       /* Set value and mask for IWDG_SW option byte */
00851       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
00852       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
00853     }
00854
00855     if ((UserType & OB_USER_IWDG_STOP) != 0U)
00856     {
00857       /* IWDG_STOP option byte should be modified */
00858       assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
00859
00860       /* Set value and mask for IWDG_STOP option byte */
00861       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
00862       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
00863     }
00864
00865     if ((UserType & OB_USER_IWDG_STDBY) != 0U)
00866     {
00867       /* IWDG_STDBY option byte should be modified */
00868       assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
00869
00870       /* Set value and mask for IWDG_STDBY option byte */
00871       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
00872       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
00873     }
00874
00875     if ((UserType & OB_USER_WWDG_SW) != 0U)
00876     {
00877       /* WWDG_SW option byte should be modified */
00878       assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
00879
00880       /* Set value and mask for WWDG_SW option byte */
00881       optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
00882       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
00883     }
00884
00885 #if defined (FLASH_OPTR_BFB2)
00886     if ((UserType & OB_USER_BFB2) != 0U)
00887     {
00888       /* BFB2 option byte should be modified */
00889       assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
00890
00891       /* Set value and mask for BFB2 option byte */
00892       optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
00893       optr_reg_mask |= FLASH_OPTR_BFB2;
00894     }
00895 #endif
00896
00897     if ((UserType & OB_USER_nBOOT1) != 0U)
00898     {
00899       /* nBOOT1 option byte should be modified */
00900       assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
00901
00902       /* Set value and mask for nBOOT1 option byte */
00903       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
00904       optr_reg_mask |= FLASH_OPTR_nBOOT1;
00905     }
00906
00907     if ((UserType & OB_USER_SRAM_PE) != 0U)
00908     {
00909       /* SRAM_PE option byte should be modified */
00910       assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE));
00911
00912       /* Set value and mask for SRAM_PE option byte */
00913       optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
00914       optr_reg_mask |= FLASH_OPTR_SRAM_PE;
00915     }
00916
00917     if ((UserType & OB_USER_CCMSRAM_RST) != 0U)
00918     {
00919       /* CCMSRAM_RST option byte should be modified */
00920       assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST));
00921
00922       /* Set value and mask for CCMSRAM_RST option byte */
00923       optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
00924       optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
00925     }
00926
00927     if ((UserType & OB_USER_nSWBOOT0) != 0U)
00928     {
00929       /* nSWBOOT0 option byte should be modified */
00930       assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
00931
00932       /* Set value and mask for nSWBOOT0 option byte */
00933       optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
00934       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
00935     }
00936
00937     if ((UserType & OB_USER_nBOOT0) != 0U)
00938     {
00939       /* nBOOT0 option byte should be modified */
00940       assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
00941
00942       /* Set value and mask for nBOOT0 option byte */
00943       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
00944       optr_reg_mask |= FLASH_OPTR_nBOOT0;
00945     }
00946
00947     if ((UserType & OB_USER_NRST_MODE) != 0U)
00948     {
00949       /* Reset Configuration option byte should be modified */
00950       assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE));
00951
00952       /* Set value and mask for Reset Configuration option byte */
00953       optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE);
00954       optr_reg_mask |= FLASH_OPTR_NRST_MODE;
00955     }
00956
00957     if ((UserType & OB_USER_IRHEN) != 0U)
00958     {
00959       /* IRH option byte should be modified */
00960       assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN));
00961
00962       /* Set value and mask for IRH option byte */
00963       optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN);
00964       optr_reg_mask |= FLASH_OPTR_IRHEN;
00965     }
00966
00967     /* Configure the option bytes register */
00968     MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
00969
00970     /* Set OPTSTRT Bit */
00971     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00972
00973     /* Wait for last operation to be completed */
00974     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00975   }
00976
00977   return status;
00978 }
00979
00980 /**
00981   * @brief  Configure the Proprietary code readout protection area into Option Bytes.
00982   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00983   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
00984   * @note   New option bytes configuration will be taken into account in two cases:
00985   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
00986   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
00987   * @param  PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
00988   *         This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*)
00989   *         with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
00990   * @note   (*) availability depends on devices
00991   * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection.
00992   *         This parameter can be an address between begin and end of the bank.
00993   * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection.
00994   *         This parameter can be an address between PCROPStartAddr and end of the bank.
00995   * @retval HAL_Status
00996   */
00997 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
00998 {
00999   HAL_StatusTypeDef status;
01000   uint32_t reg_value;
01001   uint32_t bank1_addr;
01002 #if defined (FLASH_OPTR_DBANK)
01003   uint32_t bank2_addr;
01004 #endif
01005
01006   /* Check the parameters */
01007   assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
01008   assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
01009   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
01010   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
01011
01012   /* Wait for last operation to be completed */
01013   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01014
01015   if (status == HAL_OK)
01016   {
01017 #if defined (FLASH_OPTR_DBANK)
01018     /* Get the information about the bank swapping */
01019     if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
01020     {
01021       bank1_addr = FLASH_BASE;
01022       bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
01023     }
01024     else
01025     {
01026       bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
01027       bank2_addr = FLASH_BASE;
01028     }
01029 #else
01030     bank1_addr = FLASH_BASE;
01031 #endif
01032
01033 #if defined (FLASH_OPTR_DBANK)
01034     if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
01035     {
01036       /* Configure the Proprietary code readout protection */
01037       if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
01038       {
01039         reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
01040         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
01041
01042         reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
01043         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
01044       }
01045       else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
01046       {
01047         reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
01048         MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
01049
01050         reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
01051         MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
01052       }
01053       else
01054       {
01055         /* Nothing to do */
01056       }
01057     }
01058     else
01059 #endif
01060     {
01061       /* Configure the Proprietary code readout protection */
01062       if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
01063       {
01064         reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
01065         MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
01066
01067         reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
01068         MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
01069       }
01070 #if defined (FLASH_OPTR_DBANK)
01071       else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
01072       {
01073         reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
01074         MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
01075
01076         reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
01077         MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
01078       }
01079 #endif
01080       else
01081       {
01082         /* Nothing to do */
01083       }
01084     }
01085
01086     MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
01087
01088     /* Set OPTSTRT Bit */
01089     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
01090
01091     /* Wait for last operation to be completed */
01092     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01093   }
01094
01095   return status;
01096 }
01097
01098 /**
01099   * @brief  Configure the Securable memory area into Option Bytes.
01100   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
01101   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
01102   * @note   New option bytes configuration will be taken into account in two cases:
01103   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
01104   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
01105   * @param  SecBank specifies bank of securable memory area to be configured.
01106   *          This parameter can be one of the following values:
01107   *            @arg FLASH_BANK_1: Securable memory in Bank1 to be configured
01108   *            @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*)
01109   * @note   (*) availability depends on devices
01110   * @param  SecSize specifies the number of pages of the Securable memory area,
01111   *         starting from first page of the bank.
01112   *         This parameter can be page number between 0 and (max number of pages in the bank - 1)
01113   * @retval HAL Status
01114   */
01115 static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank, uint32_t SecSize)
01116 {
01117   HAL_StatusTypeDef status;
01118
01119   /* Check the parameters */
01120   assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank));
01121   assert_param(IS_OB_SECMEM_SIZE(SecSize));
01122
01123   /* Wait for last operation to be completed */
01124   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01125
01126   if (status == HAL_OK)
01127   {
01128     /* Configure the write protected area */
01129     if (SecBank == FLASH_BANK_1)
01130     {
01131       MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize);
01132     }
01133 #if defined (FLASH_OPTR_DBANK)
01134     else if (SecBank == FLASH_BANK_2)
01135     {
01136       MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize);
01137     }
01138     else
01139     {
01140       /* Nothing to do */
01141     }
01142 #endif
01143
01144     /* Set OPTSTRT Bit */
01145     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
01146
01147     /* Wait for last operation to be completed */
01148     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01149   }
01150
01151   return status;
01152 }
01153
01154 /**
01155   * @brief  Configure the Boot Lock into Option Bytes.
01156   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
01157   *         cleared with the call of HAL_FLASH_OB_Unlock() function.
01158   * @note   New option bytes configuration will be taken into account in two cases:
01159   *         - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
01160   *         - after a power reset (BOR reset or exit from Standby/Shutdown modes)
01161   * @param  BootLockConfig specifies the boot lock configuration.
01162   *          This parameter can be one of the following values:
01163   *            @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock
01164   *            @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock
01165   *
01166   * @retval HAL_Status
01167   */
01168 static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
01169 {
01170   HAL_StatusTypeDef status;
01171
01172   /* Check the parameters */
01173   assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
01174
01175   /* Wait for last operation to be completed */
01176   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01177
01178   if (status == HAL_OK)
01179   {
01180     MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig);
01181
01182     /* Set OPTSTRT Bit */
01183     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
01184
01185     /* Wait for last operation to be completed */
01186     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01187   }
01188
01189   return status;
01190 }
01191
01192 /**
01193   * @brief  Return the Securable memory area configuration into Option Bytes.
01194   * @param[in]  SecBank specifies the bank where securable memory area is located.
01195   *          This parameter can be one of the following values:
01196   *            @arg FLASH_BANK_1: Securable memory in Bank1
01197   *            @arg FLASH_BANK_2: Securable memory in Bank2 (*)
01198   * @note   (*) availability depends on devices
01199   * @param[out]  SecSize specifies the number of pages used in the securable
01200                  memory area of the bank.
01201   * @retval None
01202   */
01203 static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize)
01204 {
01205   /* Get the configuration of the securable memory area */
01206   if (SecBank == FLASH_BANK_1)
01207   {
01208     *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1);
01209   }
01210 #if defined (FLASH_OPTR_DBANK)
01211   else if (SecBank == FLASH_BANK_2)
01212   {
01213     *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2);
01214   }
01215   else
01216   {
01217     /* Nothing to do */
01218   }
01219 #endif
01220 }
01221
01222 /**
01223   * @brief  Return the Boot Lock configuration into Option Byte.
01224   * @retval BootLockConfig.
01225   *         This return value can be one of the following values:
01226   *            @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled
01227   *            @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled
01228   */
01229 static uint32_t FLASH_OB_GetBootLock(void)
01230 {
01231   return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK);
01232 }
01233
01234 /**
01235   * @brief  Return the Write Protection configuration into Option Bytes.
01236   * @param[in]  WRPArea specifies the area to be returned.
01237   *          This parameter can be one of the following values:
01238   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
01239   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
01240   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x devices)
01241   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x devices)
01242   * @param[out]  WRPStartOffset specifies the address where to copied the start page
01243   *              of the write protected area.
01244   * @param[out]  WRDPEndOffset specifies the address where to copied the end page of
01245   *              the write protected area.
01246   * @retval None
01247   */
01248 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
01249 {
01250   /* Get the configuration of the write protected area */
01251   if (WRPArea == OB_WRPAREA_BANK1_AREAA)
01252   {
01253     *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
01254     *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
01255   }
01256   else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
01257   {
01258     *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
01259     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
01260   }
01261 #if defined (FLASH_OPTR_DBANK)
01262   else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
01263   {
01264     *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
01265     *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos);
01266   }
01267   else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
01268   {
01269     *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
01270     *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos);
01271   }
01272 #endif
01273   else
01274   {
01275     /* Nothing to do */
01276   }
01277 }
01278
01279 /**
01280   * @brief  Return the FLASH Read Protection level into Option Bytes.
01281   * @retval RDP_Level
01282   *         This return value can be one of the following values:
01283   *            @arg OB_RDP_LEVEL_0: No protection
01284   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
01285   *            @arg OB_RDP_LEVEL_2: Full chip protection
01286   */
01287 static uint32_t FLASH_OB_GetRDP(void)
01288 {
01289   uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
01290
01291   if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
01292   {
01293     return (OB_RDP_LEVEL_1);
01294   }
01295   else
01296   {
01297     return rdp_level;
01298   }
01299 }
01300
01301 /**
01302   * @brief  Return the FLASH User Option Byte value.
01303   * @retval OB_user_config
01304   *         This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL,
01305   *         @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
01306   *         @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
01307   *         @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
01308   *         @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW,
01309   *         @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*),
01310   *         @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
01311   *         @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref FLASH_OB_USER_nBOOT0,
01312   *         @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER
01313   * @note  (*) availability depends on devices
01314   */
01315 static uint32_t FLASH_OB_GetUser(void)
01316 {
01317   uint32_t user_config = READ_REG(FLASH->OPTR);
01318   CLEAR_BIT(user_config, FLASH_OPTR_RDP);
01319
01320   return user_config;
01321 }
01322
01323 /**
01324   * @brief  Return the FLASH PCROP configuration into Option Bytes.
01325   * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
01326   *        This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
01327   *        with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE.
01328   * @param[out] PCROPStartAddr specifies the address where to copied the start address
01329   *        of the Proprietary code readout protection.
01330   * @param[out] PCROPEndAddr specifies the address where to copied the end address of
01331   *        the Proprietary code readout protection.
01332   * @retval None
01333   */
01334 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
01335 {
01336   uint32_t reg_value;
01337   uint32_t bank1_addr;
01338 #if defined (FLASH_OPTR_DBANK)
01339   uint32_t bank2_addr;
01340
01341   /* Get the information about the bank swapping */
01342   if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
01343   {
01344     bank1_addr = FLASH_BASE;
01345     bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
01346   }
01347   else
01348   {
01349     bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
01350     bank2_addr = FLASH_BASE;
01351   }
01352 #else
01353   bank1_addr = FLASH_BASE;
01354 #endif
01355
01356 #if defined (FLASH_OPTR_DBANK)
01357   if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
01358   {
01359     if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
01360     {
01361       reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
01362       *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
01363
01364       reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
01365       *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
01366     }
01367     else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
01368     {
01369       reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
01370       *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
01371
01372       reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
01373       *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
01374     }
01375     else
01376     {
01377       /* Nothing to do */
01378     }
01379   }
01380   else
01381 #endif
01382   {
01383     if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
01384     {
01385       reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
01386       *PCROPStartAddr = (reg_value << 3) + bank1_addr;
01387
01388       reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
01389       *PCROPEndAddr = (reg_value << 3) + bank1_addr;
01390     }
01391 #if defined (FLASH_OPTR_DBANK)
01392     else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
01393     {
01394       reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
01395       *PCROPStartAddr = (reg_value << 3) + bank2_addr;
01396
01397       reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
01398       *PCROPEndAddr = (reg_value << 3) + bank2_addr;
01399     }
01400 #endif
01401     else
01402     {
01403       /* Nothing to do */
01404     }
01405   }
01406
01407   *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
01408 }
01409 /**
01410   * @}
01411   */
01412
01413 /**
01414   * @}
01415   */
01416
01417 #endif /* HAL_FLASH_MODULE_ENABLED */
01418
01419 /**
01420   * @}
01421   */
01422
01423 /**
01424   * @}
01425   */
01426
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_flash_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_HAL_FLASH_EX_H
00020 #define STM32G4xx_HAL_FLASH_EX_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup FLASHEx
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038
00039 /* Exported constants --------------------------------------------------------*/
00040
00041 /* Exported macro ------------------------------------------------------------*/
00042
00043 /* Exported functions --------------------------------------------------------*/
00044 /** @addtogroup FLASHEx_Exported_Functions
00045   * @{
00046   */
00047
00048 /* Extended Program operation functions  *************************************/
00049 /** @addtogroup FLASHEx_Exported_Functions_Group1
00050   * @{
00051   */
00052 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00053 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00054 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00055 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00056 HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
00057 void              HAL_FLASHEx_EnableDebugger(void);
00058 void              HAL_FLASHEx_DisableDebugger(void);
00059 /**
00060   * @}
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /** @addtogroup FLASHEx_Private_Functions
00068   * @{
00069   */
00070 void              FLASH_PageErase(uint32_t Page, uint32_t Banks);
00071 void              FLASH_FlushCaches(void);
00072 /**
00073   * @}
00074   */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 #ifdef __cplusplus
00085 }
00086 #endif
00087
00088 #endif /* STM32G4xx_HAL_FLASH_EX_H */
00089
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ramfunc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_flash_ramfunc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash_ramfunc.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH RAMFUNC driver.
00006   *          This file provides a Flash firmware functions which should be
00007   *          executed from internal SRAM
00008   *            + FLASH Power Down in Run mode
00009   *            + FLASH DBANK User Option Byte
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                    ##### Flash RAM functions #####
00015   ==============================================================================
00016
00017     *** ARM Compiler ***
00018     --------------------
00019     [..] RAM functions are defined using the toolchain options.
00020          Functions that are executed in RAM should reside in a separate
00021          source module. Using the 'Options for File' dialog you can simply change
00022          the 'Code / Const' area of a module to a memory space in physical RAM.
00023          Available memory areas are declared in the 'Target' tab of the
00024          Options for Target' dialog.
00025
00026     *** ICCARM Compiler ***
00027     -----------------------
00028     [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
00029
00030     *** GNU Compiler ***
00031     --------------------
00032     [..] RAM functions are defined using a specific toolchain attribute
00033          "__attribute__((section(".RamFunc")))".
00034
00035   @endverbatim
00036   ******************************************************************************
00037   * @attention
00038   *
00039   * Copyright (c) 2019 STMicroelectronics.
00040   * All rights reserved.
00041   *
00042   * This software is licensed under terms that can be found in the LICENSE file in
00043   * the root directory of this software component.
00044   * If no LICENSE file comes with this software, it is provided AS-IS.
00045   ******************************************************************************
00046   */
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32g4xx_hal.h"
00050
00051 /** @addtogroup STM32G4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
00056   * @brief FLASH functions executed from RAM
00057   * @{
00058   */
00059
00060 #ifdef HAL_FLASH_MODULE_ENABLED
00061
00062 /* Private typedef -----------------------------------------------------------*/
00063 /* Private define ------------------------------------------------------------*/
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067 /* Exported functions -------------------------------------------------------*/
00068
00069 /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
00070   * @{
00071   */
00072
00073 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
00074  *  @brief   Data transfers functions
00075  *
00076 @verbatim
00077  ===============================================================================
00078                       ##### ramfunc functions #####
00079  ===============================================================================
00080     [..]
00081     This subsection provides a set of functions that should be executed from RAM.
00082
00083 @endverbatim
00084   * @{
00085   */
00086
00087 /**
00088   * @brief  Enable the Power down in Run Mode
00089   * @note   This function should be called and executed from SRAM memory.
00090   * @retval None
00091   */
00092 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
00093 {
00094   /* Enable the Power Down in Run mode*/
00095   __HAL_FLASH_POWER_DOWN_ENABLE();
00096
00097   return HAL_OK;
00098
00099 }
00100
00101 /**
00102   * @brief  Disable the Power down in Run Mode
00103   * @note   This function should be called and executed from SRAM memory.
00104   * @retval None
00105   */
00106 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
00107 {
00108   /* Disable the Power Down in Run mode*/
00109   __HAL_FLASH_POWER_DOWN_DISABLE();
00110
00111   return HAL_OK;
00112 }
00113
00114 #if defined (FLASH_OPTR_DBANK)
00115 /**
00116   * @brief  Program the FLASH DBANK User Option Byte.
00117   *
00118   * @note   To configure the user option bytes, the option lock bit OPTLOCK must
00119   *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
00120   * @note   To modify the DBANK option byte, no PCROP region should be defined.
00121   *         To deactivate PCROP, user should perform RDP changing.
00122   *
00123   * @param  DBankConfig The FLASH DBANK User Option Byte value.
00124   *         This parameter  can be one of the following values:
00125   *            @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
00126   *            @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
00127   *
00128   * @retval HAL_Status
00129   */
00130 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
00131 {
00132   uint32_t count, reg;
00133   HAL_StatusTypeDef status = HAL_ERROR;
00134
00135   /* Process Locked */
00136   __HAL_LOCK(&pFlash);
00137
00138   /* Check if the PCROP is disabled */
00139   reg = FLASH->PCROP1SR;
00140   if (reg > FLASH->PCROP1ER)
00141   {
00142     reg = FLASH->PCROP2SR;
00143     if (reg > FLASH->PCROP2ER)
00144     {
00145       /* Disable Flash prefetch */
00146       __HAL_FLASH_PREFETCH_BUFFER_DISABLE();
00147
00148       if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
00149       {
00150         /* Disable Flash instruction cache */
00151         __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00152
00153         /* Flush Flash instruction cache */
00154         __HAL_FLASH_INSTRUCTION_CACHE_RESET();
00155       }
00156
00157       if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
00158       {
00159         /* Disable Flash data cache */
00160         __HAL_FLASH_DATA_CACHE_DISABLE();
00161
00162         /* Flush Flash data cache */
00163         __HAL_FLASH_DATA_CACHE_RESET();
00164       }
00165
00166       /* Disable WRP zone A of 1st bank if needed */
00167       reg = FLASH->WRP1AR;
00168       if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
00169           ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
00170       {
00171         MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
00172       }
00173
00174       /* Disable WRP zone B of 1st bank if needed */
00175       reg = FLASH->WRP1BR;
00176       if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
00177           ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
00178       {
00179         MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
00180       }
00181
00182       /* Disable WRP zone A of 2nd bank if needed */
00183       reg = FLASH->WRP2AR;
00184       if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
00185           ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
00186       {
00187         MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
00188       }
00189
00190       /* Disable WRP zone B of 2nd bank if needed */
00191       reg = FLASH->WRP2BR;
00192       if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
00193           ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
00194       {
00195         MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
00196       }
00197
00198       /* Modify the DBANK user option byte */
00199       MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
00200
00201       /* Set OPTSTRT Bit */
00202       SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00203
00204       /* Wait for last operation to be completed */
00205       /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
00206       count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
00207       do
00208       {
00209         if (count == 0U)
00210         {
00211           break;
00212         }
00213         count--;
00214       }
00215       while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
00216
00217       /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00218       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00219
00220       /* Set the bit to force the option byte reloading */
00221       SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00222     }
00223   }
00224
00225   /* Process Unlocked */
00226   __HAL_UNLOCK(&pFlash);
00227
00228   return status;
00229 }
00230 #endif
00231
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239 #endif /* HAL_FLASH_MODULE_ENABLED */
00240
00241
00242
00243 /**
00244   * @}
00245   */
00246
00247 /**
00248   * @}
00249   */
00250
00251
00252
00253
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_flash_ramfunc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_flash_ramfunc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_flash_ramfunc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH RAMFUNC driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_FLASH_RAMFUNC_H
00020 #define STM32G4xx_FLASH_RAMFUNC_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup FLASH_RAMFUNC
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /* Exported macro ------------------------------------------------------------*/
00039 /* Exported functions --------------------------------------------------------*/
00040 /** @addtogroup FLASH_RAMFUNC_Exported_Functions
00041   * @{
00042   */
00043
00044 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
00045   * @{
00046   */
00047 /* Peripheral Control functions  ************************************************/
00048 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
00049 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
00050 #if defined (FLASH_OPTR_DBANK)
00051 __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
00052 #endif
00053 /**
00054   * @}
00055   */
00056
00057 /**
00058   * @}
00059   */
00060
00061 /**
00062   * @}
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 #ifdef __cplusplus
00070 }
00071 #endif
00072
00073 #endif /* STM32G4xx_FLASH_RAMFUNC_H */
00074
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fmac.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_fmac.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_fmac.c
00004   * @author  MCD Application Team
00005   * @brief   FMAC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the FMAC peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Callback functions
00011   *           + IRQ handler management
00012   *           + Peripheral State and Error functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   *
00026   *  @verbatim
00027 ================================================================================
00028             ##### How to use this driver #####
00029 ================================================================================
00030     [..]
00031       The FMAC HAL driver can be used as follows:
00032
00033       (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
00034           (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
00035           (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
00036                (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
00037                (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
00038                (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
00039           (++) In case of using DMA to control data transfer (e.g. access configured
00040                as FMAC_BUFFER_ACCESS_DMA):
00041                (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
00042                      or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
00043                (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
00044                (+++) If the initialization of the internal buffers (coefficients, input,
00045                      output) is done via DMA, configure and enable one DMA channel for
00046                      managing data transfer from memory to memory (preload channel).
00047                (+++) If the input buffer is accessed via DMA, configure and enable one
00048                      DMA channel for managing data transfer from memory to peripheral
00049                      (input channel).
00050                (+++) If the output buffer is accessed via DMA, configure and enable
00051                      one DMA channel for managing data transfer from peripheral to
00052                      memory (output channel).
00053                (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
00054                      using __HAL_LINKDMA().
00055                (+++) Configure the priority and enable the NVIC for the transfer complete
00056                      interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
00057                      and HAL_NVIC_EnableIRQ().
00058
00059       (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
00060           resorts to HAL_FMAC_MspInit() for low-level initialization.
00061
00062       (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
00063           or HAL_FMAC_FilterConfig_DMA().
00064           This function:
00065           (++) Defines the memory area within the FMAC internal memory
00066                (input, coefficients, output) and the associated threshold (input, output).
00067           (++) Configures the filter and its parameters:
00068                (+++) Finite Impulse Response (FIR) filter (also known as convolution).
00069                (+++) Infinite Impulse Response (IIR) filter (direct form 1).
00070           (++) Choose the way to access to the input and output buffers: none, polling,
00071                DMA, IT. "none" means the input and/or output data will be handled by
00072                another IP (ADC, DAC, etc.).
00073           (++) Enable the error interruptions in the input access and/or the output
00074                access is done through IT/DMA. If an error occurs, the interruption
00075                will be triggered in loop. In order to recover, the user will have
00076                to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
00077                Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
00078                the error status will be kept, but no more interrupt will be triggered.
00079           (++) Write the provided coefficients into the internal memory using polling
00080                mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
00081                In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
00082                the handling is over.
00083
00084        (#) Optionally, the user can enable the error interruption related to
00085            saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
00086            filter. If a saturation occurs, the interruption will be triggered in loop.
00087            In order to recover, the user will have to:
00088            (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
00089                 the user wishes to continue all the same.
00090            (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
00091
00092        (#) Optionally, preload input (FIR, IIR) and output (IIR) data using
00093            HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
00094            In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
00095            the handling is over.
00096            This step is optional as the filter can be started without preloaded
00097            data.
00098
00099        (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
00100            This function also configures the output buffer that will be filled from
00101            the circular internal output buffer. The function returns immediately
00102            without updating the provided buffer. The IP processing will be active until
00103            HAL_FMAC_FilterStop() is called.
00104
00105        (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
00106            will be called to indicate that half of the input buffer has been handled.
00107
00108        (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
00109            will be called to require new input data. It will be provided through
00110            HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
00111
00112        (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
00113            will be called to indicate that half of the output buffer has been handled.
00114
00115        (#) If the output internal buffer is accessed via DMA or interrupt,
00116            HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
00117            buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
00118            if the DMA isn't in circular mode.
00119
00120        (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
00121            This function should only be called once the previous input data has been handled
00122            (the preloaded input data isn't concerned).
00123
00124        (#) In all modes except none, provide a new output buffer to be filled via
00125            HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
00126            user's output buffer has been filled.
00127
00128        (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
00129            This function:
00130            (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
00131                 into the FMAC input memory area.
00132            (++) Read the FMAC output memory area and write it into the user's output buffer.
00133            It will return either when:
00134            (++) the user's output buffer is filled.
00135            (++) the user's input buffer has been handled.
00136            The unused data (unread input data or free output data) will not be saved.
00137            The user will have to use the updated input and output sizes to keep track
00138            of them.
00139
00140        (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().
00141
00142        (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
00143            resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.
00144
00145   ##### Callback registration #####
00146   ==================================
00147
00148     [..]
00149       The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS when set to 1
00150       allows the user to configure dynamically the driver callbacks.
00151
00152     [..]
00153       Use Function HAL_FMAC_RegisterCallback() to register a user callback.
00154       Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
00155       (+) ErrorCallback               : Error Callback.
00156       (+) HalfGetDataCallback         : Get Half Data Callback.
00157       (+) GetDataCallback             : Get Data Callback.
00158       (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
00159       (+) OutputDataReadyCallback     : Output Data Ready Callback.
00160       (+) FilterConfigCallback        : Filter Configuration Callback.
00161       (+) FilterPreloadCallback       : Filter Preload Callback.
00162       (+) MspInitCallback             : FMAC MspInit.
00163       (+) MspDeInitCallback           : FMAC MspDeInit.
00164       This function takes as parameters the HAL peripheral handle, the Callback ID
00165       and a pointer to the user callback function.
00166
00167     [..]
00168       Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
00169       weak function.
00170       HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
00171       and the Callback ID.
00172       This function allows to reset following callbacks:
00173       (+) ErrorCallback               : Error Callback.
00174       (+) HalfGetDataCallback         : Get Half Data Callback.
00175       (+) GetDataCallback             : Get Data Callback.
00176       (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
00177       (+) OutputDataReadyCallback     : Output Data Ready Callback.
00178       (+) FilterConfigCallback        : Filter Configuration Callback.
00179       (+) FilterPreloadCallback       : Filter Preload Callback.
00180       (+) MspInitCallback             : FMAC MspInit.
00181       (+) MspDeInitCallback           : FMAC MspDeInit.
00182
00183     [..]
00184       By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
00185       all callbacks are set to the corresponding weak functions:
00186       examples GetDataCallback(), OutputDataReadyCallback().
00187       Exception done for MspInit and MspDeInit functions that are respectively
00188       reset to the legacy weak functions in the HAL_FMAC_Init()
00189       and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
00190       If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
00191       keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00192
00193     [..]
00194       Callbacks can be registered/unregistered in HAL_FMAC_STATE_READY state only.
00195       Exception done MspInit/MspDeInit that can be registered/unregistered
00196       in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
00197       MspInit/DeInit callbacks can be used during the Init/DeInit.
00198       In that case first register the MspInit/MspDeInit user callbacks
00199       using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
00200       or HAL_FMAC_Init() function.
00201
00202     [..]
00203       When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
00204       not defined, the callback registration feature is not available
00205       and weak callbacks are used.
00206
00207
00208   @endverbatim
00209   *
00210   */
00211
00212 /* Includes ------------------------------------------------------------------*/
00213 #include "stm32g4xx_hal.h"
00214
00215 #if defined(FMAC)
00216 #ifdef HAL_FMAC_MODULE_ENABLED
00217
00218 /** @addtogroup STM32G4xx_HAL_Driver
00219   * @{
00220   */
00221
00222 /** @defgroup FMAC FMAC
00223   * @brief    FMAC HAL driver module
00224   * @{
00225   */
00226
00227 /* Private typedef -----------------------------------------------------------*/
00228 /* Private defines -----------------------------------------------------------*/
00229 /** @defgroup  FMAC_Private_Constants   FMAC Private Constants
00230   * @{
00231   */
00232
00233 #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
00234 #define MAX_PRELOAD_INDEX      0xFFU
00235 #define PRELOAD_ACCESS_DMA     0x00U
00236 #define PRELOAD_ACCESS_POLLING 0x01U
00237 #define POLLING_DISABLED       0U
00238 #define POLLING_ENABLED        1U
00239 #define POLLING_NOT_STOPPED    0U
00240 #define POLLING_STOPPED        1U
00241 /* FMAC polling-based communications time-out value */
00242 #define HAL_FMAC_TIMEOUT_VALUE         1000U
00243 /* FMAC reset time-out value */
00244 #define HAL_FMAC_RESET_TIMEOUT_VALUE   500U
00245 /* DMA Read Requests Enable */
00246 #define FMAC_DMA_REN                   FMAC_CR_DMAREN
00247 /* DMA Write Channel Enable */
00248 #define FMAC_DMA_WEN                   FMAC_CR_DMAWEN
00249 /* FMAC Execution Enable */
00250 #define FMAC_START                     FMAC_PARAM_START
00251
00252 /**
00253   * @}
00254   */
00255
00256 /* Private macros ------------------------------------------------------------*/
00257 /** @defgroup  FMAC_Private_Macros   FMAC Private Macros
00258   * @{
00259   */
00260
00261 /**
00262   * @brief  Get the X1 memory area size.
00263   * @param  __HANDLE__ FMAC handle.
00264   * @retval X1_BUF_SIZE
00265   */
00266 #define FMAC_GET_X1_SIZE(__HANDLE__) \
00267   ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
00268
00269 /**
00270   * @brief  Get the X1 watermark.
00271   * @param  __HANDLE__ FMAC handle.
00272   * @retval FULL_WM
00273   */
00274 #define FMAC_GET_X1_FULL_WM(__HANDLE__) \
00275   (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
00276
00277 /**
00278   * @brief  Get the X2 memory area size.
00279   * @param  __HANDLE__ FMAC handle.
00280   * @retval X2_BUF_SIZE
00281   */
00282 #define FMAC_GET_X2_SIZE(__HANDLE__) \
00283   ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
00284
00285 /**
00286   * @brief  Get the Y memory area size.
00287   * @param  __HANDLE__ FMAC handle.
00288   * @retval Y_BUF_SIZE
00289   */
00290 #define FMAC_GET_Y_SIZE(__HANDLE__) \
00291   ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
00292
00293 /**
00294   * @brief  Get the Y watermark.
00295   * @param  __HANDLE__ FMAC handle.
00296   * @retval EMPTY_WM
00297   */
00298 #define FMAC_GET_Y_EMPTY_WM(__HANDLE__) \
00299   (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
00300
00301 /**
00302   * @brief  Get the start bit state.
00303   * @param  __HANDLE__ FMAC handle.
00304   * @retval START
00305   */
00306 #define FMAC_GET_START_BIT(__HANDLE__) \
00307   ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
00308
00309 /**
00310   * @brief  Get the threshold matching the watermark.
00311   * @param  __WM__ Watermark value.
00312   * @retval THRESHOLD
00313   */
00314 #define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
00315                                             ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
00316                                             ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
00317
00318 /**
00319   * @}
00320   */
00321
00322 /* Private variables ---------------------------------------------------------*/
00323 /* Global variables ----------------------------------------------------------*/
00324 /* Private function prototypes -----------------------------------------------*/
00325
00326 static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
00327 static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
00328 static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
00329 static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
00330 static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
00331                                            uint8_t PreloadAccess);
00332 static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
00333                                             int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
00334 static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size);
00335 static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout);
00336 static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
00337                                                           uint16_t *pInputSize);
00338 static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
00339                                                                   uint16_t *pOutputSize);
00340 static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite);
00341 static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead);
00342 static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma);
00343 static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma);
00344 static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma);
00345 static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma);
00346 static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma);
00347 static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
00348 static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
00349
00350 /* Functions Definition ------------------------------------------------------*/
00351
00352 /** @defgroup FMAC_Exported_Functions FMAC Exported Functions
00353   * @{
00354   */
00355
00356 /** @defgroup FMAC_Exported_Functions_Group1 Initialization and de-initialization functions
00357   * @brief    Initialization and Configuration functions
00358   *
00359 @verbatim
00360  ===============================================================================
00361      #####       Initialization and de-initialization functions       #####
00362  ===============================================================================
00363     [..] This section provides functions allowing to:
00364       (+) Initialize the FMAC peripheral and the associated handle
00365       (+) DeInitialize the FMAC peripheral
00366       (+) Initialize the FMAC MSP (MCU Specific Package)
00367       (+) De-Initialize the FMAC MSP
00368       (+) Register a User FMAC Callback
00369       (+) Unregister a FMAC CallBack
00370
00371     [..]
00372
00373 @endverbatim
00374   * @{
00375   */
00376
00377 /**
00378   * @brief  Initialize the FMAC peripheral and the associated handle.
00379   * @param  hfmac pointer to a FMAC_HandleTypeDef structure.
00380   * @retval HAL_StatusTypeDef HAL status
00381   */
00382 HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
00383 {
00384   HAL_StatusTypeDef status;
00385
00386   /* Check the FMAC handle allocation */
00387   if (hfmac == NULL)
00388   {
00389     return HAL_ERROR;
00390   }
00391
00392   /* Check the instance */
00393   assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
00394
00395   if (hfmac->State == HAL_FMAC_STATE_RESET)
00396   {
00397     /* Initialize lock resource */
00398     hfmac->Lock = HAL_UNLOCKED;
00399
00400 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00401     /* Register the default callback functions */
00402     hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;
00403     hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;
00404     hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;
00405     hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback;
00406     hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;
00407     hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;
00408     hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;
00409
00410     if (hfmac->MspInitCallback == NULL)
00411     {
00412       hfmac->MspInitCallback = HAL_FMAC_MspInit;
00413     }
00414
00415     /* Init the low level hardware */
00416     hfmac->MspInitCallback(hfmac);
00417 #else
00418     /* Init the low level hardware */
00419     HAL_FMAC_MspInit(hfmac);
00420 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00421   }
00422
00423   /* Reset pInput and pOutput */
00424   hfmac->FilterParam = 0U;
00425   FMAC_ResetDataPointers(hfmac);
00426
00427   /* Reset FMAC unit (internal pointers) */
00428   if (FMAC_Reset(hfmac) == HAL_ERROR)
00429   {
00430     /* Update FMAC error code and FMAC peripheral state */
00431     hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
00432     hfmac->State = HAL_FMAC_STATE_TIMEOUT;
00433
00434     status = HAL_ERROR;
00435   }
00436   else
00437   {
00438     /* Update FMAC error code and FMAC peripheral state */
00439     hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
00440     hfmac->State = HAL_FMAC_STATE_READY;
00441
00442     status = HAL_OK;
00443   }
00444
00445   __HAL_UNLOCK(hfmac);
00446
00447   return status;
00448 }
00449
00450 /**
00451   * @brief  De-initialize the FMAC peripheral.
00452   * @param  hfmac pointer to a FMAC structure.
00453   * @retval HAL_StatusTypeDef HAL status
00454   */
00455 HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
00456 {
00457   /* Check the FMAC handle allocation */
00458   if (hfmac == NULL)
00459   {
00460     return HAL_ERROR;
00461   }
00462
00463   /* Check the parameters */
00464   assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
00465
00466   /* Change FMAC peripheral state */
00467   hfmac->State = HAL_FMAC_STATE_BUSY;
00468
00469   /* Set FMAC error code to none */
00470   hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
00471
00472   /* Reset pInput and pOutput */
00473   hfmac->FilterParam = 0U;
00474   FMAC_ResetDataPointers(hfmac);
00475
00476 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00477   if (hfmac->MspDeInitCallback == NULL)
00478   {
00479     hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
00480   }
00481   /* DeInit the low level hardware */
00482   hfmac->MspDeInitCallback(hfmac);
00483 #else
00484   /* DeInit the low level hardware: CLOCK, NVIC, DMA */
00485   HAL_FMAC_MspDeInit(hfmac);
00486 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00487
00488   /* Change FMAC peripheral state */
00489   hfmac->State = HAL_FMAC_STATE_RESET;
00490
00491   /* Always release Lock in case of de-initialization */
00492   __HAL_UNLOCK(hfmac);
00493
00494   return HAL_OK;
00495 }
00496
00497 /**
00498   * @brief  Initialize the FMAC MSP.
00499   * @param  hfmac FMAC handle.
00500   * @retval None
00501   */
00502 __weak void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac)
00503 {
00504   /* Prevent unused argument(s) compilation warning */
00505   UNUSED(hfmac);
00506
00507   /* NOTE : This function should not be modified, when the callback is needed,
00508             the HAL_FMAC_MspInit can be implemented in the user file
00509    */
00510 }
00511
00512 /**
00513   * @brief  De-initialize the FMAC MSP.
00514   * @param  hfmac FMAC handle.
00515   * @retval None
00516   */
00517 __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
00518 {
00519   /* Prevent unused argument(s) compilation warning */
00520   UNUSED(hfmac);
00521
00522   /* NOTE : This function should not be modified, when the callback is needed,
00523             the HAL_FMAC_MspDeInit can be implemented in the user file
00524    */
00525 }
00526
00527 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00528 /**
00529   * @brief  Register a User FMAC Callback.
00530   * @note   The User FMAC Callback is to be used instead of the weak predefined callback.
00531   * @note   The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
00532   *         callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
00533   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00534   *         the configuration information for FMAC module.
00535   * @param  CallbackID ID of the callback to be registered.
00536   *         This parameter can be one of the following values:
00537   *           @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
00538   *           @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
00539   *           @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
00540   *           @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
00541   *           @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
00542   *           @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
00543   *           @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
00544   *           @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
00545   *           @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
00546   * @param  pCallback pointer to the Callback function.
00547   * @retval HAL_StatusTypeDef HAL status
00548   */
00549 HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
00550                                             pFMAC_CallbackTypeDef pCallback)
00551 {
00552   HAL_StatusTypeDef status = HAL_OK;
00553
00554   /* Check the FMAC handle allocation */
00555   if (hfmac == NULL)
00556   {
00557     return HAL_ERROR;
00558   }
00559
00560   if (pCallback == NULL)
00561   {
00562     /* Update the error code */
00563     hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00564
00565     return HAL_ERROR;
00566   }
00567
00568   if (hfmac->State == HAL_FMAC_STATE_READY)
00569   {
00570     switch (CallbackID)
00571     {
00572       case HAL_FMAC_ERROR_CB_ID :
00573         hfmac->ErrorCallback = pCallback;
00574         break;
00575
00576       case HAL_FMAC_HALF_GET_DATA_CB_ID :
00577         hfmac->HalfGetDataCallback = pCallback;
00578         break;
00579
00580       case HAL_FMAC_GET_DATA_CB_ID :
00581         hfmac->GetDataCallback = pCallback;
00582         break;
00583
00584       case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
00585         hfmac->HalfOutputDataReadyCallback = pCallback;
00586         break;
00587
00588       case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
00589         hfmac->OutputDataReadyCallback = pCallback;
00590         break;
00591
00592       case HAL_FMAC_FILTER_CONFIG_CB_ID :
00593         hfmac->FilterConfigCallback = pCallback;
00594         break;
00595
00596       case HAL_FMAC_FILTER_PRELOAD_CB_ID :
00597         hfmac->FilterPreloadCallback = pCallback;
00598         break;
00599
00600       case HAL_FMAC_MSPINIT_CB_ID :
00601         hfmac->MspInitCallback = pCallback;
00602         break;
00603
00604       case HAL_FMAC_MSPDEINIT_CB_ID :
00605         hfmac->MspDeInitCallback = pCallback;
00606         break;
00607
00608       default :
00609         /* Update the error code */
00610         hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00611
00612         /* Return error status */
00613         status =  HAL_ERROR;
00614         break;
00615     }
00616   }
00617   else if (hfmac->State == HAL_FMAC_STATE_RESET)
00618   {
00619     switch (CallbackID)
00620     {
00621       case HAL_FMAC_MSPINIT_CB_ID :
00622         hfmac->MspInitCallback = pCallback;
00623         break;
00624
00625       case HAL_FMAC_MSPDEINIT_CB_ID :
00626         hfmac->MspDeInitCallback = pCallback;
00627         break;
00628
00629       default :
00630         /* Update the error code */
00631         hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00632
00633         /* Return error status */
00634         status =  HAL_ERROR;
00635         break;
00636     }
00637   }
00638   else
00639   {
00640     /* Update the error code */
00641     hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00642
00643     /* Return error status */
00644     status =  HAL_ERROR;
00645   }
00646
00647   return status;
00648 }
00649
00650 /**
00651   * @brief  Unregister a FMAC CallBack.
00652   * @note   The FMAC callback is redirected to the weak predefined callback.
00653   * @note   The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
00654   *         callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
00655   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00656   *         the configuration information for FMAC module
00657   * @param  CallbackID ID of the callback to be unregistered.
00658   *         This parameter can be one of the following values:
00659   *           @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
00660   *           @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
00661   *           @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
00662   *           @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
00663   *           @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
00664   *           @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
00665   *           @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
00666   *           @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
00667   *           @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
00668   * @retval HAL_StatusTypeDef HAL status
00669   */
00670 HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
00671 {
00672   HAL_StatusTypeDef status = HAL_OK;
00673
00674   /* Check the FMAC handle allocation */
00675   if (hfmac == NULL)
00676   {
00677     return HAL_ERROR;
00678   }
00679
00680   if (hfmac->State == HAL_FMAC_STATE_READY)
00681   {
00682     switch (CallbackID)
00683     {
00684       case HAL_FMAC_ERROR_CB_ID :
00685         hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;                             /* Legacy weak ErrorCallback       */
00686         break;
00687
00688       case HAL_FMAC_HALF_GET_DATA_CB_ID :
00689         hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;                 /* Legacy weak HalfGetDataCallback */
00690         break;
00691
00692       case HAL_FMAC_GET_DATA_CB_ID :
00693         hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;                         /* Legacy weak GetDataCallback     */
00694         break;
00695
00696       case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
00697         hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
00698                                                                                       HalfOutputDataReadyCallback     */
00699         break;
00700
00701       case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
00702         hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;         /* Legacy weak
00703                                                                                       OutputDataReadyCallback         */
00704         break;
00705
00706       case HAL_FMAC_FILTER_CONFIG_CB_ID :
00707         hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;               /* Legacy weak
00708                                                                                       FilterConfigCallback            */
00709         break;
00710
00711       case HAL_FMAC_FILTER_PRELOAD_CB_ID :
00712         hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;             /* Legacy weak FilterPreloadCallba */
00713         break;
00714
00715       case HAL_FMAC_MSPINIT_CB_ID :
00716         hfmac->MspInitCallback = HAL_FMAC_MspInit;                                 /* Legacy weak MspInitCallback     */
00717         break;
00718
00719       case HAL_FMAC_MSPDEINIT_CB_ID :
00720         hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;                             /* Legacy weak MspDeInitCallback   */
00721         break;
00722
00723       default :
00724         /* Update the error code */
00725         hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00726
00727         /* Return error status */
00728         status =  HAL_ERROR;
00729         break;
00730     }
00731   }
00732   else if (hfmac->State == HAL_FMAC_STATE_RESET)
00733   {
00734     switch (CallbackID)
00735     {
00736       case HAL_FMAC_MSPINIT_CB_ID :
00737         hfmac->MspInitCallback = HAL_FMAC_MspInit;
00738         break;
00739
00740       case HAL_FMAC_MSPDEINIT_CB_ID :
00741         hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
00742         break;
00743
00744       default :
00745         /* Update the error code */
00746         hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00747
00748         /* Return error status */
00749         status =  HAL_ERROR;
00750         break;
00751     }
00752   }
00753   else
00754   {
00755     /* Update the error code */
00756     hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
00757
00758     /* Return error status */
00759     status = HAL_ERROR;
00760   }
00761
00762   return status;
00763 }
00764 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00765
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup FMAC_Exported_Functions_Group2 Peripheral Control functions
00771   * @brief    Control functions.
00772   *
00773 @verbatim
00774   ==============================================================================
00775                       ##### Peripheral Control functions #####
00776   ==============================================================================
00777     [..]  This section provides functions allowing to:
00778       (+) Configure the FMAC peripheral: memory area, filter type and parameters,
00779           way to access to the input and output memory area (none, polling, IT, DMA).
00780       (+) Start the FMAC processing (filter).
00781       (+) Handle the input data that will be provided into FMAC.
00782       (+) Handle the output data provided by FMAC.
00783       (+) Stop the FMAC processing (filter).
00784
00785 @endverbatim
00786   * @{
00787   */
00788
00789 /**
00790   * @brief  Configure the FMAC filter.
00791   * @note   The configuration is done according to the parameters
00792   *         specified in the FMAC_FilterConfigTypeDef structure.
00793   *         The provided data will be loaded using polling mode.
00794   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00795   *         the configuration information for FMAC module.
00796   * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
00797   *         contains the FMAC configuration information.
00798   * @retval HAL_StatusTypeDef HAL status
00799   */
00800 HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
00801 {
00802   return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
00803 }
00804
00805 /**
00806   * @brief  Configure the FMAC filter.
00807   * @note   The configuration is done according to the parameters
00808   *         specified in the FMAC_FilterConfigTypeDef structure.
00809   *         The provided data will be loaded using DMA.
00810   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00811   *         the configuration information for FMAC module.
00812   * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
00813   *         contains the FMAC configuration information.
00814   * @retval HAL_StatusTypeDef HAL status
00815   */
00816 HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
00817 {
00818   return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
00819 }
00820
00821 /**
00822   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
00823   * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
00824   *         The provided data will be loaded using polling mode.
00825   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00826   *         the configuration information for FMAC module.
00827   * @param  pInput Preloading of the first elements of the input buffer (X1).
00828   *         If not needed (no data available when starting), it should be set to NULL.
00829   * @param  InputSize Size of the input vector.
00830   *         As pInput is used for preloading data, it cannot be bigger than the input memory area.
00831   * @param  pOutput [IIR] Preloading of the first elements of the output vector (Y).
00832   *         If not needed, it should be set to NULL.
00833   * @param  OutputSize Size of the output vector.
00834   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
00835   * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
00836   *         (each call filling partly the buffers). In case of overflow (too much data provided through
00837   *         all these calls), an error will be returned.
00838   * @retval HAL_StatusTypeDef HAL status
00839   */
00840 HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
00841                                          int16_t *pOutput, uint8_t OutputSize)
00842 {
00843   return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_POLLING));
00844 }
00845
00846 /**
00847   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
00848   * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
00849   *         The provided data will be loaded using DMA.
00850   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00851   *         the configuration information for FMAC module.
00852   * @param  pInput Preloading of the first elements of the input buffer (X1).
00853   *         If not needed (no data available when starting), it should be set to NULL.
00854   * @param  InputSize Size of the input vector.
00855   *         As pInput is used for preloading data, it cannot be bigger than the input memory area.
00856   * @param  pOutput [IIR] Preloading of the first elements of the output vector (Y).
00857   *         If not needed, it should be set to NULL.
00858   * @param  OutputSize Size of the output vector.
00859   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
00860   * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
00861   *         (each call filling partly the buffers). In case of overflow (too much data provided through
00862   *         all these calls), an error will be returned.
00863   * @retval HAL_StatusTypeDef HAL status
00864   */
00865 HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
00866                                              int16_t *pOutput, uint8_t OutputSize)
00867 {
00868   return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_DMA));
00869 }
00870
00871
00872 /**
00873   * @brief  Start the FMAC processing according to the existing FMAC configuration.
00874   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00875   *         the configuration information for FMAC module.
00876   * @param  pOutput pointer to buffer where output data of FMAC processing will be stored
00877   *         in the next steps.
00878   *         If it is set to NULL, the output will not be read and it will be up to
00879   *         an external IP to empty the output buffer.
00880   * @param  pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
00881   * @retval HAL_StatusTypeDef HAL status
00882   */
00883 HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
00884 {
00885   uint32_t tmpcr = 0U;
00886   HAL_StatusTypeDef status;
00887
00888   /* Check the START bit state */
00889   if (FMAC_GET_START_BIT(hfmac) != 0U)
00890   {
00891     return HAL_ERROR;
00892   }
00893
00894   /* Check that a valid configuration was done previously */
00895   if (hfmac->FilterParam == 0U)
00896   {
00897     return HAL_ERROR;
00898   }
00899
00900   /* Check handle state is ready */
00901   if (hfmac->State == HAL_FMAC_STATE_READY)
00902   {
00903     /* Change the FMAC state */
00904     hfmac->State = HAL_FMAC_STATE_BUSY;
00905
00906     /* CR: Configure the input access (error interruptions enabled only for IT or DMA) */
00907     if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
00908     {
00909       tmpcr |= FMAC_DMA_WEN;
00910     }
00911     else if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT)
00912     {
00913       tmpcr |= FMAC_IT_WIEN;
00914     }
00915     else
00916     {
00917       /* nothing to do */
00918     }
00919
00920     /* CR: Configure the output access (error interruptions enabled only for IT or DMA) */
00921     if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
00922     {
00923       tmpcr |= FMAC_DMA_REN;
00924     }
00925     else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT)
00926     {
00927       tmpcr |= FMAC_IT_RIEN;
00928     }
00929     else
00930     {
00931       /* nothing to do */
00932     }
00933
00934     /* CR: Write the configuration */
00935     MODIFY_REG(hfmac->Instance->CR, \
00936                FMAC_IT_RIEN | FMAC_IT_WIEN | FMAC_DMA_REN | FMAC_CR_DMAWEN, \
00937                tmpcr);
00938
00939     /* Register the new output buffer */
00940     status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
00941
00942     if (status == HAL_OK)
00943     {
00944       /* PARAM: Start the filter ( this can generate interrupts before the end of the HAL_FMAC_FilterStart ) */
00945       WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam));
00946     }
00947
00948     /* Reset the busy flag (do not overwrite the possible write and read flag) */
00949     hfmac->State = HAL_FMAC_STATE_READY;
00950   }
00951   else
00952   {
00953     status = HAL_ERROR;
00954   }
00955
00956   return status;
00957 }
00958
00959 /**
00960   * @brief  Provide a new input buffer that will be loaded into the FMAC input memory area.
00961   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
00962   *         the configuration information for FMAC module.
00963   * @param  pInput New input vector (additional input data).
00964   * @param  pInputSize Size of the input vector (if all the data can't be
00965   *         written, it will be updated with the number of data read from FMAC).
00966   * @retval HAL_StatusTypeDef HAL status
00967   */
00968 HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
00969 {
00970   HAL_StatusTypeDef status;
00971
00972   /* Check the function parameters */
00973   if ((pInput == NULL) || (pInputSize == NULL))
00974   {
00975     return HAL_ERROR;
00976   }
00977   if (*pInputSize == 0U)
00978   {
00979     return HAL_ERROR;
00980   }
00981
00982   /* Check the START bit state */
00983   if (FMAC_GET_START_BIT(hfmac) == 0U)
00984   {
00985     return HAL_ERROR;
00986   }
00987
00988   /* Check the FMAC configuration */
00989   if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
00990   {
00991     return HAL_ERROR;
00992   }
00993
00994   /* Check whether the previous input vector has been handled */
00995   if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
00996   {
00997     return HAL_ERROR;
00998   }
00999
01000   /* Check that FMAC was initialized and that no writing is already ongoing */
01001   if (hfmac->WrState == HAL_FMAC_STATE_READY)
01002   {
01003     /* Register the new input buffer */
01004     status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
01005   }
01006   else
01007   {
01008     status = HAL_ERROR;
01009   }
01010
01011   return status;
01012 }
01013
01014 /**
01015   * @brief  Provide a new output buffer to be filled with the data computed by FMAC unit.
01016   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01017   *         the configuration information for FMAC module.
01018   * @param  pOutput New output vector.
01019   * @param  pOutputSize Size of the output vector (if the vector can't
01020   *         be entirely filled, pOutputSize will be updated with the number
01021   *         of data read from FMAC).
01022   * @retval HAL_StatusTypeDef HAL status
01023   */
01024 HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
01025 {
01026   HAL_StatusTypeDef status;
01027
01028   /* Check the function parameters */
01029   if ((pOutput == NULL) || (pOutputSize == NULL))
01030   {
01031     return HAL_ERROR;
01032   }
01033   if (*pOutputSize == 0U)
01034   {
01035     return HAL_ERROR;
01036   }
01037
01038   /* Check the START bit state */
01039   if (FMAC_GET_START_BIT(hfmac) == 0U)
01040   {
01041     return HAL_ERROR;
01042   }
01043
01044   /* Check the FMAC configuration */
01045   if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
01046   {
01047     return HAL_ERROR;
01048   }
01049
01050   /* Check whether the previous output vector has been handled */
01051   if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
01052   {
01053     return HAL_ERROR;
01054   }
01055
01056   /* Check that FMAC was initialized and that not reading is already ongoing */
01057   if (hfmac->RdState == HAL_FMAC_STATE_READY)
01058   {
01059     /* Register the new output buffer */
01060     status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
01061   }
01062   else
01063   {
01064     status = HAL_ERROR;
01065   }
01066
01067   return status;
01068 }
01069
01070 /**
01071   * @brief  Handle the input and/or output data in polling mode
01072   * @note   This function writes the previously provided user's input data and
01073   *         fills the previously provided user's output buffer,
01074   *         according to the existing FMAC configuration (polling mode only).
01075   *         The function returns when the input data has been handled or
01076   *         when the output data is filled. The possible unused data isn't
01077   *         kept. It will be up to the user to handle it. The previously
01078   *         provided pInputSize and pOutputSize will be used to indicate to the
01079   *         size of the read/written data to the user.
01080   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01081   *         the configuration information for FMAC module.
01082   * @param  Timeout timeout value.
01083   * @retval HAL_StatusTypeDef HAL status
01084   */
01085 HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
01086 {
01087   uint32_t tickstart;
01088   uint8_t inpolling;
01089   uint8_t inpollingover = POLLING_NOT_STOPPED;
01090   uint8_t outpolling;
01091   uint8_t outpollingover = POLLING_NOT_STOPPED;
01092   HAL_StatusTypeDef status;
01093
01094   /* Check the START bit state */
01095   if (FMAC_GET_START_BIT(hfmac) == 0U)
01096   {
01097     return HAL_ERROR;
01098   }
01099
01100   /* Check the configuration */
01101
01102   /* Get the input and output mode (if no buffer was previously provided, nothing will be read/written) */
01103   if ((hfmac->InputAccess  == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pInput  != NULL))
01104   {
01105     inpolling = POLLING_ENABLED;
01106   }
01107   else
01108   {
01109     inpolling = POLLING_DISABLED;
01110   }
01111   if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pOutput != NULL))
01112   {
01113     outpolling = POLLING_ENABLED;
01114   }
01115   else
01116   {
01117     outpolling = POLLING_DISABLED;
01118   }
01119
01120   /* Check the configuration */
01121   if ((inpolling == POLLING_DISABLED) && (outpolling == POLLING_DISABLED))
01122   {
01123     return HAL_ERROR;
01124   }
01125
01126   /* Check handle state is ready */
01127   if (hfmac->State == HAL_FMAC_STATE_READY)
01128   {
01129     /* Change the FMAC state */
01130     hfmac->State = HAL_FMAC_STATE_BUSY;
01131
01132     /* Get tick */
01133     tickstart = HAL_GetTick();
01134
01135     /* Loop on reading and writing until timeout */
01136     while ((HAL_GetTick() - tickstart) < Timeout)
01137     {
01138       /* X1: Check the mode: polling or none */
01139       if (inpolling != POLLING_DISABLED)
01140       {
01141         FMAC_WriteDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
01142         if (hfmac->InputCurrentSize == *(hfmac->pInputSize))
01143         {
01144           inpollingover = POLLING_STOPPED;
01145         }
01146       }
01147
01148       /* Y: Check the mode: polling or none */
01149       if (outpolling != POLLING_DISABLED)
01150       {
01151         FMAC_ReadDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
01152         if (hfmac->OutputCurrentSize == *(hfmac->pOutputSize))
01153         {
01154           outpollingover = POLLING_STOPPED;
01155         }
01156       }
01157
01158       /* Exit if there isn't data to handle anymore on one side or another */
01159       if ((inpollingover != POLLING_NOT_STOPPED) || (outpollingover != POLLING_NOT_STOPPED))
01160       {
01161         break;
01162       }
01163     }
01164
01165     /* Change the FMAC state; update the input and output sizes; reset the indexes */
01166     if (inpolling != POLLING_DISABLED)
01167     {
01168       (*(hfmac->pInputSize))  = hfmac->InputCurrentSize;
01169       FMAC_ResetInputStateAndDataPointers(hfmac);
01170     }
01171     if (outpolling != POLLING_DISABLED)
01172     {
01173       (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
01174       FMAC_ResetOutputStateAndDataPointers(hfmac);
01175     }
01176
01177     /* Reset the busy flag (do not overwrite the possible write and read flag) */
01178     hfmac->State = HAL_FMAC_STATE_READY;
01179
01180     if ((HAL_GetTick() - tickstart) >= Timeout)
01181     {
01182       hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
01183       status = HAL_ERROR;
01184     }
01185     else
01186     {
01187       status = HAL_OK;
01188     }
01189   }
01190   else
01191   {
01192     status = HAL_ERROR;
01193   }
01194
01195   return status;
01196 }
01197
01198 /**
01199   * @brief  Stop the FMAC processing.
01200   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01201   *         the configuration information for FMAC module.
01202   * @retval HAL_StatusTypeDef HAL status
01203   */
01204 HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
01205 {
01206   HAL_StatusTypeDef status;
01207
01208   /* Check handle state is ready */
01209   if (hfmac->State == HAL_FMAC_STATE_READY)
01210   {
01211     /* Change the FMAC state */
01212     hfmac->State = HAL_FMAC_STATE_BUSY;
01213
01214     /* Set the START bit to 0 (stop the previously configured filter) */
01215     CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
01216
01217     /* Disable the interrupts in order to avoid crossing cases */
01218     CLEAR_BIT(hfmac->Instance->CR, FMAC_DMA_REN | FMAC_DMA_WEN | FMAC_IT_RIEN | FMAC_IT_WIEN);
01219
01220     /* In case of IT, update the sizes */
01221     if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pInput != NULL))
01222     {
01223       (*(hfmac->pInputSize))  = hfmac->InputCurrentSize;
01224     }
01225     if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL))
01226     {
01227       (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
01228     }
01229
01230     /* Reset FMAC unit (internal pointers) */
01231     if (FMAC_Reset(hfmac) == HAL_ERROR)
01232     {
01233       /* Update FMAC error code and FMAC peripheral state */
01234       hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
01235       hfmac->State = HAL_FMAC_STATE_TIMEOUT;
01236       status = HAL_ERROR;
01237     }
01238     else
01239     {
01240       /* Reset the data pointers */
01241       FMAC_ResetDataPointers(hfmac);
01242
01243       status = HAL_OK;
01244     }
01245
01246     /* Reset the busy flag */
01247     hfmac->State = HAL_FMAC_STATE_READY;
01248   }
01249   else
01250   {
01251     status = HAL_ERROR;
01252   }
01253
01254   return status;
01255 }
01256
01257 /**
01258   * @}
01259   */
01260
01261 /** @defgroup FMAC_Exported_Functions_Group3 Callback functions
01262   * @brief    Callback functions.
01263   *
01264 @verbatim
01265   ==============================================================================
01266                       ##### Callback functions  #####
01267   ==============================================================================
01268     [..]  This section provides Interruption and DMA callback functions:
01269       (+) DMA or Interrupt: the user's input data is half written (DMA only)
01270           or completely written.
01271       (+) DMA or Interrupt: the user's output buffer is half filled (DMA only)
01272           or completely filled.
01273       (+) DMA or Interrupt: error handling.
01274
01275 @endverbatim
01276   * @{
01277   */
01278
01279 /**
01280   * @brief  FMAC error callback.
01281   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01282   *         the configuration information for FMAC module.
01283   * @retval None
01284   */
01285 __weak void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac)
01286 {
01287   /* Prevent unused argument(s) compilation warning */
01288   UNUSED(hfmac);
01289
01290   /* NOTE : This function should not be modified; when the callback is needed,
01291             the HAL_FMAC_ErrorCallback can be implemented in the user file.
01292    */
01293 }
01294
01295 /**
01296   * @brief  FMAC get half data callback.
01297   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01298   *         the configuration information for FMAC module.
01299   * @retval None
01300   */
01301 __weak void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac)
01302 {
01303   /* Prevent unused argument(s) compilation warning */
01304   UNUSED(hfmac);
01305
01306   /* NOTE : This function should not be modified; when the callback is needed,
01307             the HAL_FMAC_HalfGetDataCallback can be implemented in the user file.
01308    */
01309 }
01310
01311 /**
01312   * @brief  FMAC get data callback.
01313   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01314   *         the configuration information for FMAC module.
01315   * @retval None
01316   */
01317 __weak void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac)
01318 {
01319   /* Prevent unused argument(s) compilation warning */
01320   UNUSED(hfmac);
01321
01322   /* NOTE : This function should not be modified; when the callback is needed,
01323             the HAL_FMAC_GetDataCallback can be implemented in the user file.
01324    */
01325 }
01326
01327 /**
01328   * @brief  FMAC half output data ready callback.
01329   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01330   *         the configuration information for FMAC module.
01331   * @retval None
01332   */
01333 __weak void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
01334 {
01335   /* Prevent unused argument(s) compilation warning */
01336   UNUSED(hfmac);
01337
01338   /* NOTE : This function should not be modified; when the callback is needed,
01339             the HAL_FMAC_HalfOutputDataReadyCallback can be implemented in the user file.
01340    */
01341 }
01342
01343 /**
01344   * @brief  FMAC output data ready callback.
01345   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01346   *         the configuration information for FMAC module.
01347   * @retval None
01348   */
01349 __weak void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
01350 {
01351   /* Prevent unused argument(s) compilation warning */
01352   UNUSED(hfmac);
01353
01354   /* NOTE : This function should not be modified; when the callback is needed,
01355             the HAL_FMAC_OutputDataReadyCallback can be implemented in the user file.
01356    */
01357 }
01358
01359 /**
01360   * @brief  FMAC filter configuration callback.
01361   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01362   *         the configuration information for FMAC module.
01363   * @retval None
01364   */
01365 __weak void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac)
01366 {
01367   /* Prevent unused argument(s) compilation warning */
01368   UNUSED(hfmac);
01369
01370   /* NOTE : This function should not be modified; when the callback is needed,
01371             the HAL_FMAC_FilterConfigCallback can be implemented in the user file.
01372    */
01373 }
01374
01375 /**
01376   * @brief  FMAC filter preload callback.
01377   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01378   *         the configuration information for FMAC module.
01379   * @retval None
01380   */
01381 __weak void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac)
01382 {
01383   /* Prevent unused argument(s) compilation warning */
01384   UNUSED(hfmac);
01385
01386   /* NOTE : This function should not be modified; when the callback is needed,
01387             the HAL_FMAC_FilterPreloadCallback can be implemented in the user file.
01388    */
01389 }
01390
01391 /**
01392   * @}
01393   */
01394
01395 /** @defgroup FMAC_Exported_Functions_Group4 IRQ handler management
01396   * @brief    IRQ handler.
01397   *
01398 @verbatim
01399   ==============================================================================
01400                 ##### IRQ handler management #####
01401   ==============================================================================
01402 [..]  This section provides IRQ handler function.
01403
01404 @endverbatim
01405   * @{
01406   */
01407
01408 /**
01409   * @brief  Handle FMAC interrupt request.
01410   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01411   *         the configuration information for FMAC module.
01412   * @retval None
01413   */
01414 void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
01415 {
01416   uint32_t itsource;
01417
01418   /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
01419   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
01420   if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
01421   {
01422     /* Read some data if possible (Y size is used as a pseudo timeout in order
01423        to not get stuck too long under IT if FMAC keeps on processing input
01424        data reloaded via DMA for instance). */
01425     if (hfmac->pOutput != NULL)
01426     {
01427       FMAC_ReadDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_Y_SIZE(hfmac));
01428     }
01429
01430     /* Indicate that data is ready to be read */
01431     if ((hfmac->pOutput == NULL) || (hfmac->OutputCurrentSize == *(hfmac->pOutputSize)))
01432     {
01433       /* Reset the pointers to indicate new data will be needed */
01434       FMAC_ResetOutputStateAndDataPointers(hfmac);
01435
01436       /* Call the output data ready callback */
01437 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
01438       hfmac->OutputDataReadyCallback(hfmac);
01439 #else
01440       HAL_FMAC_OutputDataReadyCallback(hfmac);
01441 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
01442     }
01443   }
01444
01445   /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
01446   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
01447   if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
01448   {
01449     /* Write some data if possible (X1 size is used as a pseudo timeout in order
01450        to not get stuck too long under IT if FMAC keep on processing input
01451        data whereas its output emptied via DMA for instance). */
01452     if (hfmac->pInput != NULL)
01453     {
01454       FMAC_WriteDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_X1_SIZE(hfmac));
01455     }
01456
01457     /* Indicate that new data will be needed */
01458     if ((hfmac->pInput == NULL) || (hfmac->InputCurrentSize == *(hfmac->pInputSize)))
01459     {
01460       /* Reset the pointers to indicate new data will be needed */
01461       FMAC_ResetInputStateAndDataPointers(hfmac);
01462
01463       /* Call the get data callback */
01464 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
01465       hfmac->GetDataCallback(hfmac);
01466 #else
01467       HAL_FMAC_GetDataCallback(hfmac);
01468 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
01469     }
01470   }
01471
01472   /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
01473   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
01474   if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
01475   {
01476     hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
01477   }
01478
01479   /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
01480   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
01481   if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
01482   {
01483     hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
01484   }
01485
01486   /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
01487   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
01488   if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
01489   {
01490     hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
01491   }
01492
01493   /* Call the error callback if an error occurred */
01494   if (hfmac->ErrorCode != HAL_FMAC_ERROR_NONE)
01495   {
01496     /* Call the error callback */
01497 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
01498     hfmac->ErrorCallback(hfmac);
01499 #else
01500     HAL_FMAC_ErrorCallback(hfmac);
01501 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
01502   }
01503 }
01504
01505 /**
01506   * @}
01507   */
01508
01509 /** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
01510   * @brief    Peripheral State and Error functions.
01511   *
01512 @verbatim
01513   ==============================================================================
01514                  ##### Peripheral State and Error functions #####
01515   ==============================================================================
01516     [..]  This subsection provides functions allowing to
01517       (+) Check the FMAC state
01518       (+) Get error code
01519
01520 @endverbatim
01521   * @{
01522   */
01523
01524 /**
01525   * @brief  Return the FMAC state.
01526   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01527   *         the configuration information for FMAC module.
01528   * @retval HAL_FMAC_StateTypeDef FMAC state
01529   */
01530 HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac)
01531 {
01532   /* Return FMAC state */
01533   return hfmac->State;
01534 }
01535
01536 /**
01537   * @brief  Return the FMAC peripheral error.
01538   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01539   *         the configuration information for FMAC module.
01540   * @note   The returned error is a bit-map combination of possible errors.
01541   * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
01542   */
01543 uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac)
01544 {
01545   /* Return FMAC error code */
01546   return hfmac->ErrorCode;
01547 }
01548
01549 /**
01550   * @}
01551   */
01552
01553 /**
01554   * @}
01555   */
01556
01557 /** @defgroup FMAC_Private_Functions FMAC Private Functions
01558   * @{
01559   */
01560
01561 /**
01562   ==============================================================================
01563                        ##### FMAC Private Functions #####
01564   ==============================================================================
01565   */
01566 /**
01567   * @brief  Perform a reset of the FMAC unit.
01568   * @param  hfmac FMAC handle.
01569   * @retval HAL_StatusTypeDef HAL status
01570   */
01571 static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
01572 {
01573   uint32_t tickstart;
01574
01575   /* Init tickstart for timeout management*/
01576   tickstart = HAL_GetTick();
01577
01578   /* Perform the reset */
01579   SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
01580
01581   /* Wait until flag is reset */
01582   while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
01583   {
01584     if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
01585     {
01586       hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
01587       return HAL_ERROR;
01588     }
01589   }
01590
01591   hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
01592   return HAL_OK;
01593 }
01594
01595 /**
01596   * @brief  Reset the data pointers of the FMAC unit.
01597   * @param  hfmac FMAC handle.
01598   * @retval None
01599   */
01600 static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
01601 {
01602   FMAC_ResetInputStateAndDataPointers(hfmac);
01603   FMAC_ResetOutputStateAndDataPointers(hfmac);
01604 }
01605
01606 /**
01607   * @brief  Reset the input data pointers of the FMAC unit.
01608   * @param  hfmac FMAC handle.
01609   * @retval None
01610   */
01611 static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
01612 {
01613   hfmac->pInput = NULL;
01614   hfmac->pInputSize = NULL;
01615   hfmac->InputCurrentSize = 0U;
01616   hfmac->WrState = HAL_FMAC_STATE_READY;
01617 }
01618
01619 /**
01620   * @brief  Reset the output data pointers of the FMAC unit.
01621   * @param  hfmac FMAC handle.
01622   * @retval None
01623   */
01624 static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
01625 {
01626   hfmac->pOutput = NULL;
01627   hfmac->pOutputSize = NULL;
01628   hfmac->OutputCurrentSize = 0U;
01629   hfmac->RdState = HAL_FMAC_STATE_READY;
01630 }
01631
01632 /**
01633   * @brief  Configure the FMAC filter.
01634   * @note   The configuration is done according to the parameters
01635   *         specified in the FMAC_FilterConfigTypeDef structure.
01636   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01637   *         the configuration information for FMAC module.
01638   * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
01639   *         contains the FMAC configuration information.
01640   * @param  PreloadAccess access mode used for the preload (polling or DMA).
01641   * @retval HAL_StatusTypeDef HAL status
01642   */
01643 static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
01644                                            uint8_t PreloadAccess)
01645 {
01646   uint32_t tickstart;
01647   uint32_t tmpcr;
01648 #if defined(USE_FULL_ASSERT)
01649   uint32_t x2size;
01650 #endif /* USE_FULL_ASSERT */
01651
01652   /* Check the parameters */
01653   assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
01654   assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
01655   assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
01656   assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
01657   assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
01658   assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
01659   assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
01660   assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
01661   assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
01662
01663   /* Check the START bit state */
01664   if (FMAC_GET_START_BIT(hfmac) != 0U)
01665   {
01666     return HAL_ERROR;
01667   }
01668
01669   /* Check handle state is ready */
01670   if (hfmac->State != HAL_FMAC_STATE_READY)
01671   {
01672     return HAL_ERROR;
01673   }
01674
01675   /* Change the FMAC state */
01676   hfmac->State = HAL_FMAC_STATE_BUSY;
01677
01678   /* Get tick */
01679   tickstart = HAL_GetTick();
01680
01681   /* Indicate that there is no valid configuration done */
01682   hfmac->FilterParam = 0U;
01683
01684   /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
01685   if (pConfig->InputBufferSize != 0U)
01686   {
01687     MODIFY_REG(hfmac->Instance->X1BUFCFG,                                                                   \
01688                (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE),                                         \
01689                (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos)     & FMAC_X1BUFCFG_X1_BASE) | \
01690                 ((((uint32_t)(pConfig->InputBufferSize))  << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
01691                  FMAC_X1BUFCFG_X1_BUF_SIZE)));
01692   }
01693
01694   /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
01695   if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
01696   {
01697     /* Check the parameter */
01698     assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
01699
01700     MODIFY_REG(hfmac->Instance->X1BUFCFG, \
01701                FMAC_X1BUFCFG_FULL_WM,     \
01702                ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
01703   }
01704
01705   /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
01706   if (pConfig->CoeffBufferSize != 0U)
01707   {
01708     MODIFY_REG(hfmac->Instance->X2BUFCFG,                                                                   \
01709                (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE),                                         \
01710                (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos)     & FMAC_X2BUFCFG_X2_BASE) | \
01711                 ((((uint32_t)(pConfig->CoeffBufferSize))  << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
01712                  FMAC_X2BUFCFG_X2_BUF_SIZE)));
01713   }
01714
01715   /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
01716   if (pConfig->OutputBufferSize != 0U)
01717   {
01718     MODIFY_REG(hfmac->Instance->YBUFCFG,                                                                    \
01719                (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE),                                             \
01720                (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos)     & FMAC_YBUFCFG_Y_BASE) |    \
01721                 ((((uint32_t)(pConfig->OutputBufferSize))  << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
01722   }
01723
01724   /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
01725   if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
01726   {
01727     /* Check the parameter */
01728     assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
01729
01730     MODIFY_REG(hfmac->Instance->YBUFCFG, \
01731                FMAC_YBUFCFG_EMPTY_WM,    \
01732                ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
01733   }
01734
01735   /* FMAC_CR: Configure the clip feature */
01736   tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
01737
01738   /* FMAC_CR: If IT or DMA will be used, enable error interrupts.
01739     * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
01740   if ((pConfig->InputAccess  == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess  == FMAC_BUFFER_ACCESS_IT) ||
01741       (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
01742   {
01743     tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
01744   }
01745
01746   /* FMAC_CR: write the value */
01747   WRITE_REG(hfmac->Instance->CR, tmpcr);
01748
01749   /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
01750   hfmac->InputAccess = pConfig->InputAccess;
01751   hfmac->OutputAccess = pConfig->OutputAccess;
01752
01753   /* Check whether the configured X2 is big enough for the filter */
01754 #if defined(USE_FULL_ASSERT)
01755   x2size = FMAC_GET_X2_SIZE(hfmac);
01756 #endif /* USE_FULL_ASSERT */
01757   assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
01758                ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
01759                 (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
01760
01761   /* Build the PARAM value that will be used when starting the filter */
01762   hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter |                   \
01763                         ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
01764                         ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
01765                         ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
01766
01767   /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
01768   if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
01769   {
01770     /* FIR/IIR: The provided coefficients should match X2 size */
01771     assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
01772     /* FIR/IIR: The size of pCoeffB should match the parameter P */
01773     assert_param(pConfig->CoeffBSize >= pConfig->P);
01774     /* pCoeffA should be provided for IIR but not for FIR */
01775     /* IIR : if pCoeffB is provided, pCoeffA should also be there */
01776     /* IIR: The size of pCoeffA should match the parameter Q */
01777     assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
01778                   (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
01779                  ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
01780                   (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
01781                   (pConfig->CoeffASize >= pConfig->Q)));
01782
01783     /* Write number of values to be loaded, the data load function and start the operation */
01784     WRITE_REG(hfmac->Instance->PARAM,                      \
01785               (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
01786                ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
01787                FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
01788
01789     if (PreloadAccess == PRELOAD_ACCESS_POLLING)
01790     {
01791       /* Load the buffer into the internal memory */
01792       FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
01793
01794       /* Load pCoeffA if needed */
01795       if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
01796       {
01797         /* Load the buffer into the internal memory */
01798         FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
01799       }
01800
01801       /* Wait for the end of the writing */
01802       if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
01803       {
01804         hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
01805         hfmac->State = HAL_FMAC_STATE_TIMEOUT;
01806         return HAL_ERROR;
01807       }
01808
01809       /* Change the FMAC state */
01810       hfmac->State = HAL_FMAC_STATE_READY;
01811     }
01812     else
01813     {
01814       hfmac->pInput = pConfig->pCoeffA;
01815       hfmac->InputCurrentSize = pConfig->CoeffASize;
01816
01817       /* Set the FMAC DMA transfer complete callback */
01818       hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
01819       hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
01820       /* Set the DMA error callback */
01821       hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
01822
01823       /* Enable the DMA stream managing FMAC preload data write */
01824       return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
01825                                pConfig->CoeffBSize));
01826     }
01827   }
01828   else
01829   {
01830     /* Change the FMAC state */
01831     hfmac->State = HAL_FMAC_STATE_READY;
01832   }
01833
01834   return HAL_OK;
01835 }
01836
01837 /**
01838   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
01839   * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
01840   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
01841   *         the configuration information for FMAC module.
01842   * @param  pInput Preloading of the first elements of the input buffer (X1).
01843   *         If not needed (no data available when starting), it should be set to NULL.
01844   * @param  InputSize Size of the input vector.
01845   *         As pInput is used for preloading data, it cannot be bigger than the input memory area.
01846   * @param  pOutput [IIR] Preloading of the first elements of the output vector (Y).
01847   *         If not needed, it should be set to NULL.
01848   * @param  OutputSize Size of the output vector.
01849   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
01850   * @param  PreloadAccess access mode used for the preload (polling or DMA).
01851   * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
01852   *         (each call filling partly the buffers). In case of overflow (too much data provided through
01853   *         all these calls), an error will be returned.
01854   * @retval HAL_StatusTypeDef HAL status
01855   */
01856 static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
01857                                             int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
01858 {
01859   uint32_t tickstart;
01860   HAL_StatusTypeDef status;
01861
01862   /* Check the START bit state */
01863   if (FMAC_GET_START_BIT(hfmac) != 0U)
01864   {
01865     return HAL_ERROR;
01866   }
01867
01868   /* Check that a valid configuration was done previously */
01869   if (hfmac->FilterParam == 0U)
01870   {
01871     return HAL_ERROR;
01872   }
01873
01874   /* Check the preload input buffers isn't too big */
01875   if ((InputSize > FMAC_GET_X1_SIZE(hfmac)) && (pInput != NULL))
01876   {
01877     return HAL_ERROR;
01878   }
01879
01880   /* Check the preload output buffer isn't too big */
01881   if ((OutputSize > FMAC_GET_Y_SIZE(hfmac)) && (pOutput != NULL))
01882   {
01883     return HAL_ERROR;
01884   }
01885
01886   /* Check handle state is ready */
01887   if (hfmac->State != HAL_FMAC_STATE_READY)
01888   {
01889     return HAL_ERROR;
01890   }
01891
01892   /* Change the FMAC state */
01893   hfmac->State = HAL_FMAC_STATE_BUSY;
01894
01895   /* Get tick */
01896   tickstart = HAL_GetTick();
01897
01898   /* Preload the input buffer if required */
01899   if ((pInput != NULL) && (InputSize != 0U))
01900   {
01901     /* Write number of values to be loaded, the data load function and start the operation */
01902     WRITE_REG(hfmac->Instance->PARAM, \
01903               (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
01904
01905     if (PreloadAccess == PRELOAD_ACCESS_POLLING)
01906     {
01907       /* Load the buffer into the internal memory */
01908       FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
01909
01910       /* Wait for the end of the writing */
01911       if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
01912       {
01913         hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
01914         hfmac->State = HAL_FMAC_STATE_TIMEOUT;
01915         return HAL_ERROR;
01916       }
01917     }
01918     else
01919     {
01920       hfmac->pInput = pOutput;
01921       hfmac->InputCurrentSize = OutputSize;
01922
01923       /* Set the FMAC DMA transfer complete callback */
01924       hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
01925       hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
01926       /* Set the DMA error callback */
01927       hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
01928
01929       /* Enable the DMA stream managing FMAC preload data write */
01930       return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
01931     }
01932   }
01933
01934   /* Preload the output buffer if required */
01935   if ((pOutput != NULL) && (OutputSize != 0U))
01936   {
01937     /* Write number of values to be loaded, the data load function and start the operation */
01938     WRITE_REG(hfmac->Instance->PARAM, \
01939               (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
01940
01941     if (PreloadAccess == PRELOAD_ACCESS_POLLING)
01942     {
01943       /* Load the buffer into the internal memory */
01944       FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
01945
01946       /* Wait for the end of the writing */
01947       if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
01948       {
01949         hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
01950         hfmac->State = HAL_FMAC_STATE_TIMEOUT;
01951         return HAL_ERROR;
01952       }
01953     }
01954     else
01955     {
01956       hfmac->pInput = NULL;
01957       hfmac->InputCurrentSize = 0U;
01958
01959       /* Set the FMAC DMA transfer complete callback */
01960       hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
01961       hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
01962       /* Set the DMA error callback */
01963       hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
01964
01965       /* Enable the DMA stream managing FMAC preload data write */
01966       return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
01967     }
01968   }
01969
01970   /* Update the error codes */
01971   if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
01972   {
01973     hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
01974   }
01975   if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
01976   {
01977     hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
01978   }
01979   if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
01980   {
01981     hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
01982   }
01983
01984   /* Change the FMAC state */
01985   hfmac->State = HAL_FMAC_STATE_READY;
01986
01987   /* Return function status */
01988   if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
01989   {
01990     status = HAL_OK;
01991   }
01992   else
01993   {
01994     status = HAL_ERROR;
01995   }
01996   return status;
01997 }
01998
01999 /**
02000   * @brief  Write data into FMAC internal memory through WDATA and increment input buffer pointer.
02001   * @note   This function is only used with preload functions.
02002   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
02003   *         the configuration information for FMAC module.
02004   * @param  ppData pointer to pointer to the data buffer.
02005   * @param  Size size of the data buffer.
02006   * @retval None
02007   */
02008 static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
02009 {
02010   uint8_t index;
02011
02012   /* Load the buffer into the internal memory */
02013   for (index = Size; index > 0U; index--)
02014   {
02015     WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(*ppData))) & FMAC_WDATA_WDATA));
02016     (*ppData)++;
02017   }
02018 }
02019
02020 /**
02021   * @brief  Handle FMAC Function Timeout.
02022   * @param  hfmac FMAC handle.
02023   * @param  Tickstart Tick start value.
02024   * @param  Timeout Timeout duration.
02025   * @retval HAL_StatusTypeDef HAL status
02026   */
02027 static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
02028 {
02029   /* Wait until flag changes */
02030   while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
02031   {
02032     if ((HAL_GetTick() - Tickstart) > Timeout)
02033     {
02034       hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
02035
02036       return HAL_ERROR;
02037     }
02038   }
02039   return HAL_OK;
02040 }
02041
02042 /**
02043   * @brief  Register the new input buffer, update DMA configuration if needed and change the FMAC state.
02044   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
02045   *         the configuration information for FMAC module.
02046   * @param  pInput New input vector (additional input data).
02047   * @param  pInputSize Size of the input vector (if all the data can't be
02048   *         written, it will be updated with the number of data read from FMAC).
02049   * @retval HAL_StatusTypeDef HAL status
02050   */
02051 static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
02052                                                           uint16_t *pInputSize)
02053 {
02054   /* Change the FMAC state */
02055   hfmac->WrState = HAL_FMAC_STATE_BUSY_WR;
02056
02057   /* Reset the current size */
02058   hfmac->InputCurrentSize = 0U;
02059
02060   /* Handle the pointer depending on the input access */
02061   if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
02062   {
02063     hfmac->pInput = NULL;
02064     hfmac->pInputSize = NULL;
02065
02066     /* Set the FMAC DMA transfer complete callback */
02067     hfmac->hdmaIn->XferHalfCpltCallback = FMAC_DMAHalfGetData;
02068     hfmac->hdmaIn->XferCpltCallback = FMAC_DMAGetData;
02069     /* Set the DMA error callback */
02070     hfmac->hdmaIn->XferErrorCallback = FMAC_DMAError;
02071
02072     /* Enable the DMA stream managing FMAC input data write */
02073     return (HAL_DMA_Start_IT(hfmac->hdmaIn, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, *pInputSize));
02074   }
02075   else
02076   {
02077     /* Update the input data information (polling, IT) */
02078     hfmac->pInput = pInput;
02079     hfmac->pInputSize = pInputSize;
02080   }
02081
02082   return HAL_OK;
02083 }
02084
02085 /**
02086   * @brief  Register the new output buffer, update DMA configuration if needed and change the FMAC state.
02087   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
02088   *         the configuration information for FMAC module.
02089   * @param  pOutput New output vector.
02090   * @param  pOutputSize Size of the output vector (if the vector can't
02091   *         be entirely filled, pOutputSize will be updated with the number
02092   *         of data read from FMAC).
02093   * @retval HAL_StatusTypeDef HAL status
02094   */
02095 static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
02096                                                                   uint16_t *pOutputSize)
02097 {
02098   /* Reset the current size */
02099   hfmac->OutputCurrentSize = 0U;
02100
02101   /* Check whether a valid pointer was provided */
02102   if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
02103   {
02104     /* The user will have to provide a valid configuration later */
02105     hfmac->pOutput = NULL;
02106     hfmac->pOutputSize = NULL;
02107     hfmac->RdState = HAL_FMAC_STATE_READY;
02108   }
02109   /* Handle the pointer depending on the input access */
02110   else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
02111   {
02112     hfmac->pOutput = NULL;
02113     hfmac->pOutputSize = NULL;
02114     hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
02115
02116     /* Set the FMAC DMA transfer complete callback */
02117     hfmac->hdmaOut->XferHalfCpltCallback = FMAC_DMAHalfOutputDataReady;
02118     hfmac->hdmaOut->XferCpltCallback = FMAC_DMAOutputDataReady;
02119     /* Set the DMA error callback */
02120     hfmac->hdmaOut->XferErrorCallback = FMAC_DMAError;
02121
02122     /* Enable the DMA stream managing FMAC output data read */
02123     return (HAL_DMA_Start_IT(hfmac->hdmaOut, (uint32_t)&hfmac->Instance->RDATA, (uint32_t)pOutput, *pOutputSize));
02124   }
02125   else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
02126   {
02127     hfmac->pOutput = NULL;
02128     hfmac->pOutputSize = NULL;
02129     hfmac->RdState = HAL_FMAC_STATE_READY;
02130   }
02131   else
02132   {
02133     /* Update the output data information (polling, IT) */
02134     hfmac->pOutput = pOutput;
02135     hfmac->pOutputSize = pOutputSize;
02136     hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
02137   }
02138
02139   return HAL_OK;
02140 }
02141
02142 /**
02143   * @brief  Read available output data until Y EMPTY is set.
02144   * @param  hfmac FMAC handle.
02145   * @param  MaxSizeToRead Maximum number of data to read (this serves as a timeout
02146   *         if FMAC continuously writes into the output buffer).
02147   * @retval None
02148   */
02149 static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
02150 {
02151   uint16_t maxsize;
02152   uint16_t threshold;
02153   uint32_t tmpvalue;
02154
02155   /* Check if there is data to read */
02156   if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
02157   {
02158     return;
02159   }
02160
02161   /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
02162   if ((hfmac->OutputCurrentSize + MaxSizeToRead) > *(hfmac->pOutputSize))
02163   {
02164     maxsize = *(hfmac->pOutputSize);
02165   }
02166   else
02167   {
02168     maxsize = hfmac->OutputCurrentSize + MaxSizeToRead;
02169   }
02170
02171   /* Read until there is no more room or no more data */
02172   do
02173   {
02174     /* If there is no more room, return */
02175     if (!(hfmac->OutputCurrentSize < maxsize))
02176     {
02177       return;
02178     }
02179
02180     /* Read the available data */
02181     tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
02182     *(hfmac->pOutput) = (int16_t)tmpvalue;
02183     hfmac->pOutput++;
02184     hfmac->OutputCurrentSize++;
02185   } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
02186
02187   /* Y buffer empty flag has just be raised, read the threshold */
02188   threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
02189
02190   /* Update the maximum size if needed (limited data available) */
02191   if ((hfmac->OutputCurrentSize + threshold) < maxsize)
02192   {
02193     maxsize = hfmac->OutputCurrentSize + threshold;
02194   }
02195
02196   /* Read the available data */
02197   while (hfmac->OutputCurrentSize < maxsize)
02198   {
02199     tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
02200     *(hfmac->pOutput) = (int16_t)tmpvalue;
02201     hfmac->pOutput++;
02202     hfmac->OutputCurrentSize++;
02203   }
02204 }
02205
02206 /**
02207   * @brief  Write available input data until X1 FULL is set.
02208   * @param  hfmac FMAC handle.
02209   * @param  MaxSizeToWrite Maximum number of data to write (this serves as a timeout
02210   *         if FMAC continuously empties the input buffer).
02211   * @retval None
02212   */
02213 static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
02214 {
02215   uint16_t maxsize;
02216   uint16_t threshold;
02217
02218   /* Check if there is room in FMAC */
02219   if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
02220   {
02221     return;
02222   }
02223
02224   /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
02225   if ((hfmac->InputCurrentSize + MaxSizeToWrite) > *(hfmac->pInputSize))
02226   {
02227     maxsize = *(hfmac->pInputSize);
02228   }
02229   else
02230   {
02231     maxsize = hfmac->InputCurrentSize + MaxSizeToWrite;
02232   }
02233
02234   /* Write until there is no more room or no more data */
02235   do
02236   {
02237     /* If there is no more room, return */
02238     if (!(hfmac->InputCurrentSize < maxsize))
02239     {
02240       return;
02241     }
02242
02243     /* Write the available data */
02244     WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
02245     hfmac->pInput++;
02246     hfmac->InputCurrentSize++;
02247   } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
02248
02249   /* X1 buffer full flag has just be raised, read the threshold */
02250   threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
02251
02252   /* Update the maximum size if needed (limited data available) */
02253   if ((hfmac->InputCurrentSize + threshold) < maxsize)
02254   {
02255     maxsize = hfmac->InputCurrentSize + threshold;
02256   }
02257
02258   /* Write the available data */
02259   while (hfmac->InputCurrentSize < maxsize)
02260   {
02261     WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
02262     hfmac->pInput++;
02263     hfmac->InputCurrentSize++;
02264   }
02265 }
02266
02267 /**
02268   * @brief  DMA FMAC Input Data process half complete callback.
02269   * @param  hdma DMA handle.
02270   * @retval None
02271   */
02272 static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma)
02273 {
02274   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02275
02276   /* Call half get data callback */
02277 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02278   hfmac->HalfGetDataCallback(hfmac);
02279 #else
02280   HAL_FMAC_HalfGetDataCallback(hfmac);
02281 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02282 }
02283
02284 /**
02285   * @brief  DMA FMAC Input Data process complete callback.
02286   * @param  hdma DMA handle.
02287   * @retval None
02288   */
02289 static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma)
02290 {
02291   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02292
02293   /* Reset the pointers to indicate new data will be needed */
02294   FMAC_ResetInputStateAndDataPointers(hfmac);
02295
02296   /* Call get data callback */
02297 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02298   hfmac->GetDataCallback(hfmac);
02299 #else
02300   HAL_FMAC_GetDataCallback(hfmac);
02301 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02302 }
02303
02304 /**
02305   * @brief  DMA FMAC Output Data process half complete callback.
02306   * @param  hdma DMA handle.
02307   * @retval None
02308   */
02309 static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma)
02310 {
02311   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02312
02313   /* Call half output data ready callback */
02314 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02315   hfmac->HalfOutputDataReadyCallback(hfmac);
02316 #else
02317   HAL_FMAC_HalfOutputDataReadyCallback(hfmac);
02318 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02319 }
02320
02321 /**
02322   * @brief  DMA FMAC Output Data process complete callback.
02323   * @param  hdma DMA handle.
02324   * @retval None
02325   */
02326 static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma)
02327 {
02328   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02329
02330   /* Reset the pointers to indicate new data will be needed */
02331   FMAC_ResetOutputStateAndDataPointers(hfmac);
02332
02333   /* Call output data ready callback */
02334 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02335   hfmac->OutputDataReadyCallback(hfmac);
02336 #else
02337   HAL_FMAC_OutputDataReadyCallback(hfmac);
02338 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02339 }
02340
02341 /**
02342   * @brief  DMA FMAC Filter Configuration process complete callback.
02343   * @param  hdma DMA handle.
02344   * @retval None
02345   */
02346 static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
02347 {
02348   uint8_t index;
02349
02350   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02351
02352   /* If needed, write CoeffA and exit */
02353   if (hfmac->pInput != NULL)
02354   {
02355     /* Set the FMAC DMA transfer complete callback */
02356     hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
02357     hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
02358     /* Set the DMA error callback */
02359     hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
02360
02361     /* Enable the DMA stream managing FMAC preload data write */
02362     if (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, (uint32_t)&hfmac->Instance->WDATA,
02363                          hfmac->InputCurrentSize) == HAL_OK)
02364     {
02365       hfmac->pInput = NULL;
02366       hfmac->InputCurrentSize = 0U;
02367       return;
02368     }
02369
02370     /* If not exited, there was an error: set FMAC handle state to error */
02371     hfmac->State = HAL_FMAC_STATE_ERROR;
02372   }
02373   else
02374   {
02375     /* Wait for the end of the writing */
02376     for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
02377     {
02378       if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
02379       {
02380         break;
02381       }
02382     }
02383
02384     /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
02385     if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
02386     {
02387       hfmac->State = HAL_FMAC_STATE_TIMEOUT;
02388     }
02389     else
02390     {
02391       /* Change the FMAC state */
02392       hfmac->State = HAL_FMAC_STATE_READY;
02393
02394       /* Call output data ready callback */
02395 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02396       hfmac->FilterConfigCallback(hfmac);
02397 #else
02398       HAL_FMAC_FilterConfigCallback(hfmac);
02399 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02400       return;
02401     }
02402   }
02403
02404   /* If not exited, there was an error: set FMAC handle error code to DMA error */
02405   hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
02406
02407   /* Call user callback */
02408 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02409   hfmac->ErrorCallback(hfmac);
02410 #else
02411   HAL_FMAC_ErrorCallback(hfmac);
02412 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02413
02414 }
02415
02416 /**
02417   * @brief  DMA FMAC Filter Configuration process complete callback.
02418   * @param  hdma DMA handle.
02419   * @retval None
02420   */
02421 static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
02422 {
02423   uint8_t index;
02424
02425   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02426
02427   /* Wait for the end of the X1 writing */
02428   for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
02429   {
02430     if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
02431     {
02432       break;
02433     }
02434   }
02435
02436   /* If 'START' is still set, there was an error: set FMAC handle state to error */
02437   if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
02438   {
02439     hfmac->State = HAL_FMAC_STATE_TIMEOUT;
02440     hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
02441   }
02442   /* If needed, preload Y buffer */
02443   else if ((hfmac->pInput != NULL) && (hfmac->InputCurrentSize != 0U))
02444   {
02445     /* Write number of values to be loaded, the data load function and start the operation */
02446     WRITE_REG(hfmac->Instance->PARAM, \
02447               (((uint32_t)(hfmac->InputCurrentSize) << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
02448
02449     /* Set the FMAC DMA transfer complete callback */
02450     hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
02451     hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
02452     /* Set the DMA error callback */
02453     hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
02454
02455     /* Enable the DMA stream managing FMAC preload data write */
02456     if (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, (uint32_t)&hfmac->Instance->WDATA,
02457                          hfmac->InputCurrentSize) == HAL_OK)
02458     {
02459       hfmac->pInput = NULL;
02460       hfmac->InputCurrentSize = 0U;
02461       return;
02462     }
02463
02464     /* If not exited, there was an error */
02465     hfmac->ErrorCode = HAL_FMAC_ERROR_DMA;
02466     hfmac->State = HAL_FMAC_STATE_ERROR;
02467   }
02468   else
02469   {
02470     /* nothing to do */
02471   }
02472
02473   if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
02474   {
02475     /* Change the FMAC state */
02476     hfmac->State = HAL_FMAC_STATE_READY;
02477
02478     /* Call output data ready callback */
02479 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02480     hfmac->FilterPreloadCallback(hfmac);
02481 #else
02482     HAL_FMAC_FilterPreloadCallback(hfmac);
02483 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02484   }
02485   else
02486   {
02487     /* Call user callback */
02488 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02489     hfmac->ErrorCallback(hfmac);
02490 #else
02491     HAL_FMAC_ErrorCallback(hfmac);
02492 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02493   }
02494 }
02495
02496
02497 /**
02498   * @brief  DMA FMAC communication error callback.
02499   * @param  hdma DMA handle.
02500   * @retval None
02501   */
02502 static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
02503 {
02504   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02505
02506   /* Set FMAC handle state to error */
02507   hfmac->State = HAL_FMAC_STATE_ERROR;
02508
02509   /* Set FMAC handle error code to DMA error */
02510   hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
02511
02512   /* Call user callback */
02513 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
02514   hfmac->ErrorCallback(hfmac);
02515 #else
02516   HAL_FMAC_ErrorCallback(hfmac);
02517 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
02518 }
02519 /**
02520   * @}
02521   */
02522
02523
02524 /**
02525   * @}
02526   */
02527
02528 /**
02529   * @}
02530   */
02531
02532 #endif /* HAL_FMAC_MODULE_ENABLED */
02533 #endif /* FMAC */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_fmac.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_fmac.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_fmac.h
00004   * @author  MCD Application Team
00005   * @brief   Header for stm32g4xx_hal_fmac.c module
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_FMAC_H
00021 #define STM32G4xx_HAL_FMAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined(FMAC)
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FMAC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup FMAC_Exported_Types FMAC Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  FMAC HAL State Structure definition
00046   */
00047 typedef enum
00048 {
00049   HAL_FMAC_STATE_RESET       = 0x00U,            /*!< FMAC not yet initialized or disabled                           */
00050   HAL_FMAC_STATE_READY       = 0x20U,            /*!< FMAC initialized and ready for use                             */
00051   HAL_FMAC_STATE_BUSY        = 0x24U,            /*!< FMAC internal process is ongoing                               */
00052   HAL_FMAC_STATE_BUSY_RD     = 0x25U,            /*!< FMAC reading configuration is ongoing                          */
00053   HAL_FMAC_STATE_BUSY_WR     = 0x26U,            /*!< FMAC writing configuration is ongoing                          */
00054   HAL_FMAC_STATE_TIMEOUT     = 0xA0U,            /*!< FMAC in Timeout state                                          */
00055   HAL_FMAC_STATE_ERROR       = 0xE0U             /*!< FMAC in Error state                                            */
00056 } HAL_FMAC_StateTypeDef;
00057
00058 /**
00059   * @brief  FMAC Handle Structure definition
00060   */
00061 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00062 typedef struct __FMAC_HandleTypeDef
00063 #else
00064 typedef struct
00065 #endif  /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00066 {
00067   FMAC_TypeDef               *Instance;          /*!< Register base address */
00068
00069   uint32_t                   FilterParam;        /*!< Filter configuration (operation and parameters).
00070                                                       Set to 0 if no valid configuration was applied. */
00071
00072   uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area):
00073                                                      DMA, IT, Polling, None.
00074                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
00075
00076   uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area):
00077                                                      DMA, IT, Polling, None.
00078                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
00079
00080   int16_t                    *pInput;            /*!< Pointer to FMAC input data buffer */
00081
00082   uint16_t                   InputCurrentSize;   /*!< Number of the input elements already written into FMAC */
00083
00084   uint16_t                   *pInputSize;        /*!< Number of input elements to write (memory allocated to pInput).
00085                                                       In case of early interruption of the filter operation,
00086                                                       its value will be updated. */
00087
00088   int16_t                    *pOutput;           /*!< Pointer to FMAC output data buffer */
00089
00090   uint16_t                   OutputCurrentSize;  /*!< Number of the output elements already read from FMAC */
00091
00092   uint16_t                   *pOutputSize;       /*!< Number of output elements to read (memory allocated to pOutput).
00093                                                       In case of early interruption of the filter operation,
00094                                                       its value will be updated. */
00095
00096   DMA_HandleTypeDef          *hdmaIn;            /*!< FMAC peripheral input data DMA handle parameters */
00097
00098   DMA_HandleTypeDef          *hdmaOut;           /*!< FMAC peripheral output data DMA handle parameters */
00099
00100   DMA_HandleTypeDef          *hdmaPreload;       /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
00101                                                       parameters */
00102
00103 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00104   void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac);               /*!< FMAC error callback                  */
00105
00106   void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac);         /*!< FMAC get half data callback          */
00107
00108   void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac);             /*!< FMAC get data callback               */
00109
00110   void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
00111
00112   void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac);     /*!< FMAC output data ready callback      */
00113
00114   void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac);        /*!< FMAC filter configuration callback   */
00115
00116   void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac);       /*!< FMAC filter preload callback         */
00117
00118   void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac);             /*!< FMAC Msp Init callback               */
00119
00120   void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac);           /*!< FMAC Msp DeInit callback             */
00121
00122 #endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
00123
00124   HAL_LockTypeDef            Lock;               /*!< FMAC locking object */
00125
00126   __IO HAL_FMAC_StateTypeDef State;              /*!< FMAC state related to global handle management
00127                                                       This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
00128
00129   __IO HAL_FMAC_StateTypeDef RdState;            /*!< FMAC state related to read operations (access to Y buffer)
00130                                                       This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
00131
00132   __IO HAL_FMAC_StateTypeDef WrState;            /*!< FMAC state related to write operations (access to X1 buffer)
00133                                                       This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
00134
00135   __IO uint32_t              ErrorCode;          /*!< FMAC peripheral error code
00136                                                       This parameter can be a value of @ref FMAC_Error_Code */
00137
00138 } FMAC_HandleTypeDef;
00139
00140 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00141 /**
00142   * @brief  FMAC Callback ID enumeration definition
00143   */
00144 typedef enum
00145 {
00146   HAL_FMAC_ERROR_CB_ID                  = 0x00U, /*!< FMAC error callback ID                  */
00147   HAL_FMAC_HALF_GET_DATA_CB_ID          = 0x01U, /*!< FMAC get half data callback ID          */
00148   HAL_FMAC_GET_DATA_CB_ID               = 0x02U, /*!< FMAC get data callback ID               */
00149   HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
00150   HAL_FMAC_OUTPUT_DATA_READY_CB_ID      = 0x04U, /*!< FMAC output data ready callback ID      */
00151   HAL_FMAC_FILTER_CONFIG_CB_ID          = 0x05U, /*!< FMAC filter configuration callback ID   */
00152   HAL_FMAC_FILTER_PRELOAD_CB_ID         = 0x06U, /*!< FMAC filter preload callback ID         */
00153
00154   HAL_FMAC_MSPINIT_CB_ID                = 0x07U, /*!< FMAC MspInit callback ID                */
00155   HAL_FMAC_MSPDEINIT_CB_ID              = 0x08U, /*!< FMAC MspDeInit callback ID              */
00156 } HAL_FMAC_CallbackIDTypeDef;
00157
00158 /**
00159   * @brief  HAL FMAC Callback pointer definition
00160   */
00161 typedef  void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac);  /*!< pointer to an FMAC callback function */
00162
00163 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00164
00165 /**
00166   * @brief  FMAC Filter Configuration Structure definition
00167   */
00168 typedef struct
00169 {
00170   uint8_t                    InputBaseAddress;  /*!< Base address of the input buffer (X1) within the internal memory
00171                                                      (0x00 to 0xFF). Ignored if InputBufferSize is set to 0
00172                                                      (previous configuration kept).
00173                                                      Note: the buffers can overlap or even coincide exactly. */
00174
00175   uint8_t                    InputBufferSize;   /*!< Number of 16-bit words allocated to the input buffer
00176                                                      (including the optional "headroom").
00177                                                      0 if a previous configuration should be kept. */
00178
00179   uint32_t                   InputThreshold;    /*!< Input threshold: the buffer full flag will be set if the number
00180                                                      of free spaces in the buffer is lower than this threshold.
00181                                                      This parameter can be a value
00182                                                      of @ref FMAC_Data_Buffer_Threshold. */
00183
00184   uint8_t                    CoeffBaseAddress;  /*!< Base address of the coefficient buffer (X2) within the internal
00185                                                      memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
00186                                                      (previous configuration kept).
00187                                                      Note: the buffers can overlap or even coincide exactly. */
00188
00189   uint8_t                    CoeffBufferSize;   /*!< Number of 16-bit words allocated to the coefficient buffer.
00190                                                      0 if a previous configuration should be kept. */
00191
00192   uint8_t                    OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
00193                                                      memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
00194                                                      (previous configuration kept).
00195                                                      Note: the buffers can overlap or even coincide exactly. */
00196
00197   uint8_t                    OutputBufferSize;  /*!< Number of 16-bit words allocated to the output buffer
00198                                                     (including the optional "headroom").
00199                                                      0 if a previous configuration should be kept. */
00200
00201   uint32_t                   OutputThreshold;   /*!< Output threshold: the buffer empty flag will be set if the number
00202                                                      of unread values in the buffer is lower than this threshold.
00203                                                      This parameter can be a value
00204                                                      of @ref FMAC_Data_Buffer_Threshold. */
00205
00206   int16_t                    *pCoeffA;          /*!< [IIR only] Initialization of the coefficient vector A.
00207                                                      If not needed, it should be set to NULL. */
00208
00209   uint8_t                    CoeffASize;        /*!< Size of the coefficient vector A. */
00210
00211   int16_t                    *pCoeffB;          /*!< Initialization of the coefficient vector B.
00212                                                      If not needed (re-use of a previously loaded buffer),
00213                                                      it should be set to NULL. */
00214
00215   uint8_t                    CoeffBSize;        /*!< Size of the coefficient vector B. */
00216
00217   uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area):
00218                                                      DMA, IT, Polling, None.
00219                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
00220
00221   uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area):
00222                                                      DMA, IT, Polling, None.
00223                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
00224
00225   uint32_t                   Clip;              /*!< Enable or disable the clipping feature. If the q1.15 range
00226                                                      is exceeded, wrapping is done when the clipping feature is disabled
00227                                                      and saturation is done when the clipping feature is enabled.
00228                                                      This parameter can be a value of @ref FMAC_Clip_State. */
00229
00230   uint32_t                   Filter;            /*!< Filter type.
00231                                                      This parameter can be a value
00232                                                      of @ref FMAC_Functions (filter related values). */
00233
00234   uint8_t                    P;                 /*!< Parameter P (vector length, number of filter taps, etc.). */
00235
00236   uint8_t                    Q;                 /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
00237
00238   uint8_t                    R;                 /*!< Parameter R (gain, etc.). Ignored if not needed. */
00239
00240 } FMAC_FilterConfigTypeDef;
00241
00242 /**
00243   * @}
00244   */
00245
00246
00247 /* Exported constants --------------------------------------------------------*/
00248
00249
00250 /** @defgroup FMAC_Exported_Constants FMAC Exported Constants
00251   * @{
00252   */
00253
00254 /** @defgroup FMAC_Error_Code FMAC Error code
00255   * @{
00256   */
00257 #define HAL_FMAC_ERROR_NONE                0x00000000U /*!< No error               */
00258 #define HAL_FMAC_ERROR_SAT                 0x00000001U /*!< Saturation error       */
00259 #define HAL_FMAC_ERROR_UNFL                0x00000002U /*!< Underflow error        */
00260 #define HAL_FMAC_ERROR_OVFL                0x00000004U /*!< Overflow error         */
00261 #define HAL_FMAC_ERROR_DMA                 0x00000008U /*!< DMA error              */
00262 #define HAL_FMAC_ERROR_RESET               0x00000010U /*!< Reset error            */
00263 #define HAL_FMAC_ERROR_PARAM               0x00000020U /*!< Parameter error        */
00264 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00265 #define HAL_FMAC_ERROR_INVALID_CALLBACK    0x00000040U /*!< Invalid Callback error */
00266 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00267 #define HAL_FMAC_ERROR_TIMEOUT             0x00000080U /*!< Timeout error          */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup FMAC_Functions FMAC Functions
00274   * @{
00275   */
00276 #define FMAC_FUNC_LOAD_X1                  (FMAC_PARAM_FUNC_0)                        /*!< Load X1 buffer             */
00277 #define FMAC_FUNC_LOAD_X2                  (FMAC_PARAM_FUNC_1)                        /*!< Load X2 buffer             */
00278 #define FMAC_FUNC_LOAD_Y                   (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)    /*!< Load Y buffer              */
00279 #define FMAC_FUNC_CONVO_FIR                (FMAC_PARAM_FUNC_3)                        /*!< Convolution (FIR filter)   */
00280 #define FMAC_FUNC_IIR_DIRECT_FORM_1        (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)    /*!< IIR filter (direct form 1) */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
00286   * @{
00287   * @note     This parameter sets a watermark for buffer full (input) or buffer empty (output).
00288   */
00289 #define FMAC_THRESHOLD_1                   0x00000000U    /*!< Input: Buffer full flag set if the number of free spaces
00290                                                                in the buffer is less than 1.
00291                                                                Output: Buffer empty flag set if the number
00292                                                                of unread values in the buffer is less than 1. */
00293 #define FMAC_THRESHOLD_2                   0x01000000U    /*!< Input: Buffer full flag set if the number of free spaces
00294                                                                in the buffer is less than 2.
00295                                                                Output: Buffer empty flag set if the number
00296                                                                of unread values in the buffer is less than 2. */
00297 #define FMAC_THRESHOLD_4                   0x02000000U    /*!< Input: Buffer full flag set if the number of free spaces
00298                                                                in the buffer is less than 4.
00299                                                                Output: Buffer empty flag set if the number
00300                                                                of unread values in the buffer is less than 4. */
00301 #define FMAC_THRESHOLD_8                   0x03000000U    /*!< Input: Buffer full flag set if the number of free spaces
00302                                                                in the buffer is less than 8.
00303                                                                Output: Buffer empty flag set if the number
00304                                                                of unread values in the buffer is less than 8. */
00305 #define FMAC_THRESHOLD_NO_VALUE            0xFFFFFFFFU    /*!< The configured threshold value shouldn't be changed */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup FMAC_Buffer_Access FMAC Buffer Access
00311   * @{
00312   */
00313 #define FMAC_BUFFER_ACCESS_NONE            0x00U           /*!< Buffer handled by an external IP (ADC for instance) */
00314 #define FMAC_BUFFER_ACCESS_DMA             0x01U           /*!< Buffer accessed through DMA */
00315 #define FMAC_BUFFER_ACCESS_POLLING         0x02U           /*!< Buffer accessed through polling */
00316 #define FMAC_BUFFER_ACCESS_IT              0x03U           /*!< Buffer accessed through interruptions */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup FMAC_Clip_State FMAC Clip State
00322   * @{
00323   */
00324 #define FMAC_CLIP_DISABLED                 0x00000000U     /*!< Clipping disabled */
00325 #define FMAC_CLIP_ENABLED                  FMAC_CR_CLIPEN  /*!< Clipping enabled */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup FMAC_Flags  FMAC status flags
00331   * @{
00332   */
00333 #define FMAC_FLAG_YEMPTY                   FMAC_SR_YEMPTY  /*!< Y Buffer Empty Flag */
00334 #define FMAC_FLAG_X1FULL                   FMAC_SR_X1FULL  /*!< X1 Buffer Full Flag */
00335 #define FMAC_FLAG_OVFL                     FMAC_SR_OVFL    /*!< Overflow Error Flag */
00336 #define FMAC_FLAG_UNFL                     FMAC_SR_UNFL    /*!< Underflow Error Flag */
00337 #define FMAC_FLAG_SAT                      FMAC_SR_SAT     /*!< Saturation Error Flag
00338                                                                 (this helps in debugging a filter) */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
00344   * @{
00345   */
00346 #define FMAC_IT_RIEN                       FMAC_CR_RIEN    /*!< Read Interrupt Enable */
00347 #define FMAC_IT_WIEN                       FMAC_CR_WIEN    /*!< Write Interrupt Enable */
00348 #define FMAC_IT_OVFLIEN                    FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
00349 #define FMAC_IT_UNFLIEN                    FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
00350 #define FMAC_IT_SATIEN                     FMAC_CR_SATIEN  /*!< Saturation Error Interrupt Enable
00351                                                                 (this helps in debugging a filter) */
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360
00361 /* Exported variables --------------------------------------------------------*/
00362 /** @defgroup FMAC_Exported_variables FMAC Exported variables
00363   * @{
00364   */
00365 /**
00366   * @}
00367   */
00368
00369 /* Exported macros -----------------------------------------------------------*/
00370 /** @defgroup FMAC_Exported_Macros FMAC Exported Macros
00371   * @{
00372   */
00373
00374 /**
00375   * @brief  Reset FMAC handle state.
00376   * @param  __HANDLE__ FMAC handle.
00377   * @retval None
00378   */
00379 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00380 #define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{                                           \
00381                                                       (__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
00382                                                       (__HANDLE__)->MspInitCallback = NULL;       \
00383                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
00384                                                     } while(0U)
00385 #else
00386 #define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
00387 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00388
00389 /**
00390   * @brief  Enable the specified FMAC interrupt
00391   * @param  __HANDLE__ FMAC handle.
00392   * @param  __INTERRUPT__ FMAC Interrupt.
00393   *         This parameter can be any combination of the following values:
00394   *            @arg @ref FMAC_IT_RIEN    Read interrupt enable
00395   *            @arg @ref FMAC_IT_WIEN    Write interrupt enable
00396   *            @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
00397   *            @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
00398   *            @arg @ref FMAC_IT_SATIEN  Saturation error interrupt enable (this helps in debugging a filter)
00399   * @retval None
00400   */
00401 #define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
00402   (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00403
00404 /**
00405   * @brief  Disable the FMAC interrupt
00406   * @param  __HANDLE__ FMAC handle.
00407   * @param  __INTERRUPT__ FMAC Interrupt.
00408   *         This parameter can be any combination of the following values:
00409   *            @arg @ref FMAC_IT_RIEN    Read interrupt enable
00410   *            @arg @ref FMAC_IT_WIEN    Write interrupt enable
00411   *            @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
00412   *            @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
00413   *            @arg @ref FMAC_IT_SATIEN  Saturation error interrupt enable (this helps in debugging a filter)
00414   * @retval None
00415   */
00416 #define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
00417   (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00418
00419 /**
00420   * @brief  Check whether the specified FMAC interrupt occurred or not.
00421   * @param  __HANDLE__ FMAC handle.
00422   * @param  __INTERRUPT__ FMAC interrupt to check.
00423   *         This parameter can be any combination of the following values:
00424   *            @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
00425   *            @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
00426   *            @arg @ref FMAC_FLAG_OVFL   Overflow Error Flag
00427   *            @arg @ref FMAC_FLAG_UNFL   Underflow Error Flag
00428   *            @arg @ref FMAC_FLAG_SAT    Saturation Error Flag
00429   * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
00430   */
00431 #define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
00432   (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
00433
00434 /**
00435   * @brief  Clear specified FMAC interrupt status. Dummy macro as the
00436             interrupt status flags are read-only.
00437   * @param  __HANDLE__ FMAC handle.
00438   * @param  __INTERRUPT__ FMAC interrupt to clear.
00439   * @retval None
00440   */
00441 #define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__)   /* Dummy macro */
00442
00443 /**
00444   * @brief  Check whether the specified FMAC status flag is set or not.
00445   * @param  __HANDLE__ FMAC handle.
00446   * @param  __FLAG__ FMAC flag to check.
00447   *         This parameter can be any combination of the following values:
00448   *            @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
00449   *            @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
00450   *            @arg @ref FMAC_FLAG_OVFL   Overflow Error Flag
00451   *            @arg @ref FMAC_FLAG_UNFL   Underflow Error Flag
00452   *            @arg @ref FMAC_FLAG_SAT    Saturation error Flag
00453   * @retval SET (flag is set) or RESET (flag is reset)
00454   */
00455 #define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
00456   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00457
00458 /**
00459   * @brief  Clear specified FMAC status flag. Dummy macro as no
00460             flag can be cleared.
00461   * @param  __HANDLE__ FMAC handle.
00462   * @param  __FLAG__ FMAC flag to clear.
00463   * @retval None
00464   */
00465 #define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__)     /* Dummy macro */
00466
00467 /**
00468   * @brief  Check whether the specified FMAC interrupt is enabled or not.
00469   * @param  __HANDLE__ FMAC handle.
00470   * @param  __INTERRUPT__ FMAC interrupt to check.
00471   *         This parameter can be one of the following values:
00472   *            @arg @ref FMAC_IT_RIEN    Read interrupt enable
00473   *            @arg @ref FMAC_IT_WIEN    Write interrupt enable
00474   *            @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
00475   *            @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
00476   *            @arg @ref FMAC_IT_SATIEN  Saturation error interrupt enable (this helps in debugging a filter)
00477   * @retval FlagStatus
00478   */
00479 #define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
00480   (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
00481
00482 /**
00483   * @}
00484   */
00485
00486 /* Private defines -----------------------------------------------------------*/
00487 /** @addtogroup  FMAC_Private_Constants
00488   * @{
00489   */
00490
00491 #define FMAC_PARAM_P_MAX_IIR  64U /*!< Maximum value of P parameter with IIR */
00492 #define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
00493 #define FMAC_PARAM_P_MIN       2U /*!< Minimum value of P parameter */
00494 #define FMAC_PARAM_Q_MAX      63U /*!< Maximum value of Q parameter */
00495 #define FMAC_PARAM_Q_MIN       1U /*!< Minimum value of Q parameter */
00496 #define FMAC_PARAM_R_MAX       7U /*!< Maximum value of R parameter */
00497
00498 /**
00499   * @}
00500   */
00501
00502 /* Private Macros-----------------------------------------------------------*/
00503 /** @addtogroup  FMAC_Private_Macros FMAC Private Macros
00504   * @{
00505   */
00506
00507 /**
00508   * @brief  Verify the FMAC function.
00509   * @param  __FUNCTION__ ID of the function.
00510   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00511   */
00512 #define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                         || \
00513                                         ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)                         || \
00514                                         ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)                          || \
00515                                         ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                       || \
00516                                         ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
00517
00518 /**
00519   * @brief  Verify the FMAC load function used for input data, output data or coefficients.
00520   * @param  __FUNCTION__ ID of the load function.
00521   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00522   */
00523 #define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                    || \
00524                                              ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)                    || \
00525                                              ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
00526
00527 /**
00528   * @brief  Verify the FMAC load function used with N values as input or output data.
00529   * @param  __FUNCTION__ ID of the load function.
00530   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00531   */
00532 #define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1)                  || \
00533                                                ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
00534
00535 /**
00536   * @brief  Verify the FMAC load function used with N + M values as coefficients.
00537   * @param  __FUNCTION__ ID of the load function.
00538   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00539   */
00540 #define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
00541
00542 /**
00543   * @brief  Verify the FMAC filter function.
00544   * @param  __FUNCTION__ ID of the filter function.
00545   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
00546   */
00547 #define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                || \
00548                                                ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
00549
00550
00551 /**
00552   * @brief  Verify the FMAC threshold.
00553   * @param  __THRESHOLD__ Value of the threshold.
00554   * @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
00555   */
00556 #define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1)                       || \
00557                                           ((__THRESHOLD__) == FMAC_THRESHOLD_2)                       || \
00558                                           ((__THRESHOLD__) == FMAC_THRESHOLD_4)                       || \
00559                                           ((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE)                || \
00560                                           ((__THRESHOLD__) == FMAC_THRESHOLD_8))
00561
00562 /**
00563   * @brief  Verify the FMAC filter parameter P.
00564   * @param  __P__ Value of the filter parameter P.
00565   * @param  __FUNCTION__ ID of the filter function.
00566   * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
00567   */
00568 #define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               && \
00569                                                (((__P__) >= FMAC_PARAM_P_MIN) && \
00570                                                 ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
00571                                               (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
00572                                                (((__P__) >= FMAC_PARAM_P_MIN) && \
00573                                                 ((__P__) <= FMAC_PARAM_P_MAX_IIR))))
00574
00575 /**
00576   * @brief  Verify the FMAC filter parameter Q.
00577   * @param  __Q__ Value of the filter parameter Q.
00578   * @param  __FUNCTION__ ID of the filter function.
00579   * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
00580   */
00581 #define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                || \
00582                                                (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
00583                                                 (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
00584
00585 /**
00586   * @brief  Verify the FMAC filter parameter R.
00587   * @param  __R__ Value of the filter parameter.
00588   * @param  __FUNCTION__ ID of the filter function.
00589   * @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
00590   */
00591 #define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               || \
00592                                                 ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))      && \
00593                                                ((__R__) <= FMAC_PARAM_R_MAX))
00594
00595 /**
00596   * @brief  Verify the FMAC buffer access.
00597   * @param  __BUFFER_ACCESS__ Type of access.
00598   * @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
00599   */
00600 #define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE)    || \
00601                                                   ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA)     || \
00602                                                   ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
00603                                                   ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
00604
00605 /**
00606   * @brief  Verify the FMAC clip feature.
00607   * @param  __CLIP_STATE__ Clip state.
00608   * @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
00609   */
00610 #define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED)                  || \
00611                                             ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
00612
00613 /**
00614   * @brief  Check whether the threshold is applicable.
00615   * @param  __SIZE__ Size of the matching buffer.
00616   * @param  __WM__ Watermark value.
00617   * @param  __ACCESS__ Access to the buffer (polling, it, dma, none).
00618   * @retval THRESHOLD
00619   */
00620 #define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
00621   (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
00622                     ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
00623                     ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
00624    ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
00625      ((__WM__) == FMAC_THRESHOLD_1))|| \
00626     ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
00627
00628 /**
00629   * @}
00630   */
00631
00632 /* Exported functions ------------------------------------------------------- */
00633 /** @addtogroup FMAC_Exported_Functions
00634   * @{
00635   */
00636
00637 /** @addtogroup FMAC_Exported_Functions_Group1
00638   * @{
00639   */
00640 /* Initialization and de-initialization functions  ****************************/
00641 HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
00642 HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
00643 void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
00644 void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
00645
00646 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
00647 /* Callbacks Register/UnRegister functions  ***********************************/
00648 HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
00649                                             pFMAC_CallbackTypeDef pCallback);
00650 HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
00651 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
00652 /**
00653   * @}
00654   */
00655
00656 /** @addtogroup FMAC_Exported_Functions_Group2
00657   * @{
00658   */
00659 /* Peripheral Control functions ***********************************************/
00660 HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
00661 HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
00662 HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
00663                                          int16_t *pOutput, uint8_t OutputSize);
00664 HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
00665                                              int16_t *pOutput, uint8_t OutputSize);
00666 HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
00667 HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
00668 HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
00669 HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
00670 HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef  *hfmac);
00671 /**
00672   * @}
00673   */
00674
00675 /** @addtogroup FMAC_Exported_Functions_Group3
00676   * @{
00677   */
00678 /* Callback functions *********************************************************/
00679 void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
00680 void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
00681 void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
00682 void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
00683 void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
00684 void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
00685 void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
00686 /**
00687   * @}
00688   */
00689
00690 /** @addtogroup FMAC_Exported_Functions_Group4
00691   * @{
00692   */
00693 /* IRQ handler management *****************************************************/
00694 void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
00695 /**
00696   * @}
00697   */
00698
00699 /** @addtogroup FMAC_Exported_Functions_Group5
00700   * @{
00701   */
00702 /* Peripheral State functions *************************************************/
00703 HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
00704 uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
00705 /**
00706   * @}
00707   */
00708
00709 /**
00710   * @}
00711   */
00712
00713 /**
00714   * @}
00715   */
00716
00717 /**
00718   * @}
00719   */
00720
00721 #endif /* FMAC */
00722
00723 #ifdef __cplusplus
00724 }
00725 #endif
00726
00727 #endif /* STM32G4xx_HAL_FMAC_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                     ##### GPIO Peripheral features #####
00025   ==============================================================================
00026   [..]
00027     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00028         configured by software in several modes:
00029         (++) Input mode
00030         (++) Analog mode
00031         (++) Output mode
00032         (++) Alternate function mode
00033         (++) External interrupt/event lines
00034
00035     (+) During and just after reset, the alternate functions and external interrupt
00036         lines are not active and the I/O ports are configured in input floating mode.
00037
00038     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00039         activated or not.
00040
00041     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00042         type and the IO speed can be selected depending on the VDD value.
00043
00044     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00045         multiplexer that allows only one peripheral alternate function (AF) connected
00046        to an IO pin at a time. In this way, there can be no conflict between peripherals
00047        sharing the same IO pin.
00048
00049     (+) All ports have external interrupt/event capability. To use external interrupt
00050         lines, the port must be configured in input mode. All available GPIO pins are
00051         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00052
00053     (+) The external interrupt/event controller consists of up to 44 edge detectors
00054         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00055         input line can be independently configured to select the type (interrupt or event)
00056         and the corresponding trigger event (rising or falling or both). Each line can
00057         also be masked independently.
00058
00059                      ##### How to use this driver #####
00060   ==============================================================================
00061   [..]
00062     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00063
00064     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00065         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00066         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00067              structure.
00068         (++) In case of Output or alternate function mode selection: the speed is
00069              configured through "Speed" member from GPIO_InitTypeDef structure.
00070         (++) In alternate mode is selection, the alternate function connected to the IO
00071              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00072         (++) Analog mode is required when a pin is to be used as ADC channel
00073              or DAC output.
00074         (++) In case of external interrupt/event selection the "Mode" member from
00075              GPIO_InitTypeDef structure select the type (interrupt or event) and
00076              the corresponding trigger event (rising or falling or both).
00077
00078     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00079         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00080         HAL_NVIC_EnableIRQ().
00081
00082     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00083
00084     (#) To set/reset the level of a pin configured in output mode use
00085         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00086
00087    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00088
00089     (#) During and just after reset, the alternate functions are not
00090         active and the GPIO pins are configured in input floating mode (except JTAG
00091         pins).
00092
00093     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00094         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00095         priority over the GPIO function.
00096
00097     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00098         general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
00099         The HSE has priority over the GPIO function.
00100
00101   @endverbatim
00102   ******************************************************************************
00103   */
00104
00105 /* Includes ------------------------------------------------------------------*/
00106 #include "stm32g4xx_hal.h"
00107
00108 /** @addtogroup STM32G4xx_HAL_Driver
00109   * @{
00110   */
00111
00112 /** @addtogroup GPIO
00113   * @{
00114   */
00115 /** MISRA C:2012 deviation rule has been granted for following rules:
00116   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00117   * range of the shift operator in following API :
00118   * HAL_GPIO_Init
00119   * HAL_GPIO_DeInit
00120   */
00121
00122 #ifdef HAL_GPIO_MODULE_ENABLED
00123
00124 /* Private typedef -----------------------------------------------------------*/
00125 /* Private defines -----------------------------------------------------------*/
00126 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00127   * @{
00128   */
00129 #define GPIO_NUMBER           (16U)
00130 /**
00131   * @}
00132   */
00133
00134 /* Private macros ------------------------------------------------------------*/
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private function prototypes -----------------------------------------------*/
00137 /* Exported functions --------------------------------------------------------*/
00138
00139 /** @addtogroup GPIO_Exported_Functions
00140   * @{
00141   */
00142
00143 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00144   *  @brief    Initialization and Configuration functions
00145   *
00146 @verbatim
00147  ===============================================================================
00148               ##### Initialization and de-initialization functions #####
00149  ===============================================================================
00150
00151 @endverbatim
00152   * @{
00153   */
00154
00155 /**
00156   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00157   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00158   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
00159   *         the configuration information for the specified GPIO peripheral.
00160   * @retval None
00161   */
00162 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00163 {
00164   uint32_t position = 0x00U;
00165   uint32_t iocurrent;
00166   uint32_t temp;
00167
00168   /* Check the parameters */
00169   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00170   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00171   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00172
00173   /* Configure the port pins */
00174   while (((GPIO_Init->Pin) >> position) != 0U)
00175   {
00176     /* Get current io position */
00177     iocurrent = (GPIO_Init->Pin) & (1UL << position);
00178
00179     if (iocurrent != 0x00u)
00180     {
00181       /*--------------------- GPIO Mode Configuration ------------------------*/
00182       /* In case of Output or Alternate function mode selection */
00183       if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
00184          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
00185       {
00186         /* Check the Speed parameter */
00187         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00188         /* Configure the IO Speed */
00189         temp = GPIOx->OSPEEDR;
00190         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
00191         temp |= (GPIO_Init->Speed << (position * 2U));
00192         GPIOx->OSPEEDR = temp;
00193
00194         /* Configure the IO Output Type */
00195         temp = GPIOx->OTYPER;
00196         temp &= ~(GPIO_OTYPER_OT0 << position) ;
00197         temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
00198         GPIOx->OTYPER = temp;
00199       }
00200
00201       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
00202       {
00203         /* Check the Pull parameter */
00204         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00205
00206         /* Activate the Pull-up or Pull down resistor for the current IO */
00207         temp = GPIOx->PUPDR;
00208         temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
00209         temp |= ((GPIO_Init->Pull) << (position * 2U));
00210         GPIOx->PUPDR = temp;
00211       }
00212
00213       /* In case of Alternate function mode selection */
00214       if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
00215       {
00216         /* Check the Alternate function parameters */
00217         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00218         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00219
00220         /* Configure Alternate function mapped with the current IO */
00221         temp = GPIOx->AFR[position >> 3U];
00222         temp &= ~(0xFU << ((position & 0x07U) * 4U));
00223         temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
00224         GPIOx->AFR[position >> 3U] = temp;
00225       }
00226
00227       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00228       temp = GPIOx->MODER;
00229       temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
00230       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
00231       GPIOx->MODER = temp;
00232
00233       /*--------------------- EXTI Mode Configuration ------------------------*/
00234       /* Configure the External Interrupt or event for the current IO */
00235       if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
00236       {
00237         /* Enable SYSCFG Clock */
00238         __HAL_RCC_SYSCFG_CLK_ENABLE();
00239
00240         temp = SYSCFG->EXTICR[position >> 2U];
00241         temp &= ~(0x0FUL << (4U * (position & 0x03U)));
00242         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
00243         SYSCFG->EXTICR[position >> 2U] = temp;
00244
00245         /* Clear Rising Falling edge configuration */
00246         temp = EXTI->RTSR1;
00247         temp &= ~(iocurrent);
00248         if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
00249         {
00250           temp |= iocurrent;
00251         }
00252         EXTI->RTSR1 = temp;
00253
00254         temp = EXTI->FTSR1;
00255         temp &= ~(iocurrent);
00256         if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
00257         {
00258           temp |= iocurrent;
00259         }
00260         EXTI->FTSR1 = temp;
00261
00262         temp = EXTI->EMR1;
00263         temp &= ~(iocurrent);
00264         if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
00265         {
00266           temp |= iocurrent;
00267         }
00268         EXTI->EMR1 = temp;
00269
00270         /* Clear EXTI line configuration */
00271         temp = EXTI->IMR1;
00272         temp &= ~(iocurrent);
00273         if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
00274         {
00275           temp |= iocurrent;
00276         }
00277         EXTI->IMR1 = temp;
00278       }
00279     }
00280
00281     position++;
00282   }
00283 }
00284
00285 /**
00286   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
00287   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00288   * @param  GPIO_Pin specifies the port bit to be written.
00289   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00290   * @retval None
00291   */
00292 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00293 {
00294   uint32_t position = 0x00U;
00295   uint32_t iocurrent;
00296   uint32_t tmp;
00297
00298   /* Check the parameters */
00299   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00300   assert_param(IS_GPIO_PIN(GPIO_Pin));
00301
00302   /* Configure the port pins */
00303   while ((GPIO_Pin >> position) != 0U)
00304   {
00305     /* Get current io position */
00306     iocurrent = (GPIO_Pin) & (1UL << position);
00307
00308     if (iocurrent != 0x00u)
00309     {
00310       /*------------------------- EXTI Mode Configuration --------------------*/
00311       /* Clear the External Interrupt or Event for the current IO */
00312
00313       tmp = SYSCFG->EXTICR[position >> 2U];
00314       tmp &= (0x0FUL << (4U * (position & 0x03U)));
00315       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
00316       {
00317         /* Clear EXTI line configuration */
00318         EXTI->IMR1 &= ~(iocurrent);
00319         EXTI->EMR1 &= ~(iocurrent);
00320
00321         /* Clear Rising Falling edge configuration */
00322         EXTI->FTSR1 &= ~(iocurrent);
00323         EXTI->RTSR1 &= ~(iocurrent);
00324
00325         tmp = 0x0FUL << (4U * (position & 0x03U));
00326         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
00327       }
00328
00329       /*------------------------- GPIO Mode Configuration --------------------*/
00330       /* Configure IO in Analog Mode */
00331       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
00332
00333       /* Configure the default Alternate Function in current IO */
00334       GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
00335
00336       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00337       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
00338
00339       /* Configure the default value IO Output Type */
00340       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position);
00341
00342       /* Configure the default value for IO Speed */
00343       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
00344     }
00345
00346     position++;
00347   }
00348 }
00349
00350 /**
00351   * @}
00352   */
00353
00354 /** @addtogroup GPIO_Exported_Functions_Group2
00355   *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00356   *
00357 @verbatim
00358  ===============================================================================
00359                        ##### IO operation functions #####
00360  ===============================================================================
00361
00362 @endverbatim
00363   * @{
00364   */
00365
00366 /**
00367   * @brief  Read the specified input port pin.
00368   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00369   * @param  GPIO_Pin specifies the port bit to read.
00370   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00371   * @retval The input port pin value.
00372   */
00373 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00374 {
00375   GPIO_PinState bitstatus;
00376
00377   /* Check the parameters */
00378   assert_param(IS_GPIO_PIN(GPIO_Pin));
00379
00380   if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
00381   {
00382     bitstatus = GPIO_PIN_SET;
00383   }
00384   else
00385   {
00386     bitstatus = GPIO_PIN_RESET;
00387   }
00388   return bitstatus;
00389 }
00390
00391 /**
00392   * @brief  Set or clear the selected data port bit.
00393   *
00394   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
00395   *         accesses. In this way, there is no risk of an IRQ occurring between
00396   *         the read and the modify access.
00397   *
00398   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00399   * @param  GPIO_Pin specifies the port bit to be written.
00400   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00401   * @param  PinState specifies the value to be written to the selected bit.
00402   *         This parameter can be one of the GPIO_PinState enum values:
00403   *            @arg GPIO_PIN_RESET: to clear the port pin
00404   *            @arg GPIO_PIN_SET: to set the port pin
00405   * @retval None
00406   */
00407 void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00408 {
00409   /* Check the parameters */
00410   assert_param(IS_GPIO_PIN(GPIO_Pin));
00411   assert_param(IS_GPIO_PIN_ACTION(PinState));
00412
00413   if (PinState != GPIO_PIN_RESET)
00414   {
00415     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00416   }
00417   else
00418   {
00419     GPIOx->BRR = (uint32_t)GPIO_Pin;
00420   }
00421 }
00422
00423 /**
00424   * @brief  Toggle the specified GPIO pin.
00425   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00426   * @param  GPIO_Pin specifies the pin to be toggled.
00427   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00428   * @retval None
00429   */
00430 void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00431 {
00432   uint32_t odr;
00433
00434   /* Check the parameters */
00435   assert_param(IS_GPIO_PIN(GPIO_Pin));
00436
00437   /* get current Output Data Register value */
00438   odr = GPIOx->ODR;
00439
00440   /* Set selected pins that were at low level, and reset ones that were high */
00441   GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
00442 }
00443
00444 /**
00445   * @brief  Lock GPIO Pins configuration registers.
00446   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00447   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00448   * @note   The configuration of the locked GPIO pins can no longer be modified
00449   *         until the next reset.
00450   * @param  GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
00451   * @param  GPIO_Pin specifies the port bits to be locked.
00452   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00453   * @retval None
00454   */
00455 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00456 {
00457   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00458
00459   /* Check the parameters */
00460   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00461   assert_param(IS_GPIO_PIN(GPIO_Pin));
00462
00463   /* Apply lock key write sequence */
00464   tmp |= GPIO_Pin;
00465   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00466   GPIOx->LCKR = tmp;
00467   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00468   GPIOx->LCKR = GPIO_Pin;
00469   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00470   GPIOx->LCKR = tmp;
00471   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00472   tmp = GPIOx->LCKR;
00473
00474   /* read again in order to confirm lock is active */
00475   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
00476   {
00477     return HAL_OK;
00478   }
00479   else
00480   {
00481     return HAL_ERROR;
00482   }
00483 }
00484
00485 /**
00486   * @brief  Handle EXTI interrupt request.
00487   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00488   * @retval None
00489   */
00490 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00491 {
00492   /* EXTI line interrupt detected */
00493   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
00494   {
00495     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00496     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00497   }
00498 }
00499
00500 /**
00501   * @brief  EXTI line detection callback.
00502   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00503   * @retval None
00504   */
00505 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00506 {
00507   /* Prevent unused argument(s) compilation warning */
00508   UNUSED(GPIO_Pin);
00509
00510   /* NOTE: This function should not be modified, when the callback is needed,
00511            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00512    */
00513 }
00514
00515 /**
00516   * @}
00517   */
00518
00519
00520 /**
00521   * @}
00522   */
00523
00524 #endif /* HAL_GPIO_MODULE_ENABLED */
00525 /**
00526   * @}
00527   */
00528
00529 /**
00530   * @}
00531   */
00532
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_GPIO_H
00021 #define STM32G4xx_HAL_GPIO_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup GPIO GPIO
00035   * @brief GPIO HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00042   * @{
00043   */
00044 /**
00045   * @brief   GPIO Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
00050                            This parameter can be any value of @ref GPIO_pins */
00051
00052   uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
00053                            This parameter can be a value of @ref GPIO_mode */
00054
00055   uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00056                            This parameter can be a value of @ref GPIO_pull */
00057
00058   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
00059                            This parameter can be a value of @ref GPIO_speed */
00060
00061   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
00062                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
00063 } GPIO_InitTypeDef;
00064
00065 /**
00066   * @brief  GPIO Bit SET and Bit RESET enumeration
00067   */
00068 typedef enum
00069 {
00070   GPIO_PIN_RESET = 0U,
00071   GPIO_PIN_SET
00072 } GPIO_PinState;
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported constants --------------------------------------------------------*/
00078 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00079   * @{
00080   */
00081 /** @defgroup GPIO_pins GPIO pins
00082   * @{
00083   */
00084 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00085 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00086 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00087 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00088 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00089 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00090 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00091 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00092 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00093 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00094 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00095 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00096 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00097 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00098 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00099 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00100 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00101
00102 #define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup GPIO_mode GPIO mode
00108   * @brief GPIO Configuration Mode
00109   *        Elements values convention: 0x00WX00YZ
00110   *           - W  : EXTI trigger detection on 3 bits
00111   *           - X  : EXTI mode (IT or Event) on 2 bits
00112   *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
00113   *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
00114   * @{
00115   */
00116 #define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
00117 #define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
00118 #define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
00119 #define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
00120 #define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
00121
00122 #define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
00123
00124 #define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
00125 #define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
00126 #define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00127
00128 #define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
00129 #define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
00130 #define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup GPIO_speed GPIO speed
00136   * @brief GPIO Output Maximum frequency
00137   * @{
00138   */
00139 #define  GPIO_SPEED_FREQ_LOW        (0x00000000U)   /*!< range up to 5 MHz, please refer to the product datasheet */
00140 #define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001U)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
00141 #define  GPIO_SPEED_FREQ_HIGH       (0x00000002U)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
00142 #define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003U)   /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup GPIO_pull GPIO pull
00148   * @brief GPIO Pull-Up or Pull-Down Activation
00149   * @{
00150   */
00151 #define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
00152 #define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
00153 #define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
00154 /**
00155   * @}
00156   */
00157
00158 /**
00159   * @}
00160   */
00161
00162 /* Exported macro ------------------------------------------------------------*/
00163 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00164   * @{
00165   */
00166
00167 /**
00168   * @brief  Check whether the specified EXTI line flag is set or not.
00169   * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
00170   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00171   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00172   */
00173 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
00174
00175 /**
00176   * @brief  Clear the EXTI's line pending flags.
00177   * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
00178   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00179   * @retval None
00180   */
00181 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
00182
00183 /**
00184   * @brief  Check whether the specified EXTI line is asserted or not.
00185   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00186   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00187   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00188   */
00189 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
00190
00191 /**
00192   * @brief  Clear the EXTI's line pending bits.
00193   * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
00194   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00195   * @retval None
00196   */
00197 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
00198
00199 /**
00200   * @brief  Generate a Software interrupt on selected EXTI line.
00201   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00202   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00203   * @retval None
00204   */
00205 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Private macros ------------------------------------------------------------*/
00212 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00213   * @{
00214   */
00215 #define GPIO_MODE_Pos                           0U
00216 #define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
00217 #define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
00218 #define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
00219 #define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
00220 #define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
00221 #define OUTPUT_TYPE_Pos                         4U
00222 #define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
00223 #define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
00224 #define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
00225 #define EXTI_MODE_Pos                           16U
00226 #define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
00227 #define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
00228 #define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
00229 #define TRIGGER_MODE_Pos                         20U
00230 #define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
00231 #define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
00232 #define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00238   * @{
00239   */
00240 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00241
00242 #define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
00243                                      (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
00244
00245 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
00246                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
00247                                      ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
00248                                      ((__MODE__) == GPIO_MODE_AF_PP)              ||\
00249                                      ((__MODE__) == GPIO_MODE_AF_OD)              ||\
00250                                      ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
00251                                      ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
00252                                      ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
00253                                      ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
00254                                      ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
00255                                      ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
00256                                      ((__MODE__) == GPIO_MODE_ANALOG))
00257
00258 #define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
00259                                      ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
00260                                      ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
00261                                      ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
00262
00263 #define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
00264                                      ((__PULL__) == GPIO_PULLUP)   || \
00265                                      ((__PULL__) == GPIO_PULLDOWN))
00266 /**
00267   * @}
00268   */
00269
00270 /* Include GPIO HAL Extended module */
00271 #include "stm32g4xx_hal_gpio_ex.h"
00272
00273 /* Exported functions --------------------------------------------------------*/
00274 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00275   *  @brief    GPIO Exported Functions
00276   * @{
00277   */
00278
00279 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00280   *  @brief    Initialization and Configuration functions
00281   * @{
00282   */
00283
00284 /* Initialization and de-initialization functions *****************************/
00285 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00286 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00293   *  @brief    IO operation functions
00294   * @{
00295   */
00296
00297 /* IO operation functions *****************************************************/
00298 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00299 void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00300 void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00301 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00302 void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00303 void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00304
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 #ifdef __cplusplus
00322 }
00323 #endif
00324
00325 #endif /* STM32G4xx_HAL_GPIO_H */
00326
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_gpio_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_gpio_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32G4xx_HAL_GPIO_EX_H
00022 #define STM32G4xx_HAL_GPIO_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32g4xx_hal_def.h"
00030
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup GPIOEx GPIOEx
00036   * @brief GPIO Extended HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /* Exported constants --------------------------------------------------------*/
00042 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
00047   * @{
00048   */
00049
00050 /**
00051   * @brief   AF 0 selection
00052   */
00053 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
00054 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00055 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00056 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
00057
00058 /**
00059   * @brief   AF 1 selection
00060   */
00061 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
00062 #if defined(TIM5)
00063 #define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping   */
00064 #endif /* TIM5 */
00065 #define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
00066 #define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
00067 #define GPIO_AF1_TIM17_COMP1   ((uint8_t)0x01)  /* TIM17/COMP1 Break in Alternate Function mapping  */
00068 #define GPIO_AF1_TIM15         ((uint8_t)0x01)  /* TIM15 Alternate Function mapping  */
00069 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
00070 #define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping     */
00071
00072 /**
00073   * @brief   AF 2 selection
00074   */
00075 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping  */
00076 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping  */
00077 #define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping  */
00078 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping  */
00079 #if defined(TIM5)
00080 #define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping  */
00081 #endif /* TIM5 */
00082 #define GPIO_AF2_TIM8          ((uint8_t)0x02)  /* TIM8 Alternate Function mapping  */
00083 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping */
00084 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /* TIM16 Alternate Function mapping */
00085 #if defined(TIM20)
00086 #define GPIO_AF2_TIM20         ((uint8_t)0x02)  /* TIM20 Alternate Function mapping */
00087 #endif /* TIM20 */
00088 #define GPIO_AF2_TIM1_COMP1    ((uint8_t)0x02)  /* TIM1/COMP1 Break in Alternate Function mapping   */
00089 #define GPIO_AF2_TIM15_COMP1   ((uint8_t)0x02)  /* TIM15/COMP1 Break in Alternate Function mapping  */
00090 #define GPIO_AF2_TIM16_COMP1   ((uint8_t)0x02)  /* TIM16/COMP1 Break in Alternate Function mapping  */
00091 #if defined(TIM20)
00092 #define GPIO_AF2_TIM20_COMP1   ((uint8_t)0x02)  /* TIM20/COMP1 Break in Alternate Function mapping  */
00093 #define GPIO_AF2_TIM20_COMP2   ((uint8_t)0x02)  /* TIM20/COMP2 Break in Alternate Function mapping  */
00094 #endif /* TIM20 */
00095 #define GPIO_AF2_I2C3          ((uint8_t)0x02)  /* I2C3 Alternate Function mapping  */
00096 #define GPIO_AF2_COMP1         ((uint8_t)0x02)  /* COMP1 Alternate Function mapping */
00097
00098 /**
00099   * @brief   AF 3 selection
00100   */
00101 #define GPIO_AF3_TIM15         ((uint8_t)0x03)  /* TIM15 Alternate Function mapping   */
00102 #if defined(TIM20)
00103 #define GPIO_AF3_TIM20         ((uint8_t)0x03)  /* TIM20 Alternate Function mapping   */
00104 #endif /* TIM20 */
00105 #define GPIO_AF3_UCPD1         ((uint8_t)0x03)  /* UCPD1 Alternate Function mapping   */
00106 #define GPIO_AF3_I2C3          ((uint8_t)0x03)  /* I2C3 Alternate Function mapping    */
00107 #if defined(I2C4)
00108 #define GPIO_AF3_I2C4          ((uint8_t)0x03)  /* I2C4 Alternate Function mapping    */
00109 #endif /* I2C4 */
00110 #if defined(HRTIM1)
00111 #define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping  */
00112 #endif /* HRTIM1 */
00113 #if defined(QUADSPI)
00114 #define GPIO_AF3_QUADSPI       ((uint8_t)0x03)  /* QUADSPI Alternate Function mapping */
00115 #endif /* QUADSPI */
00116 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping    */
00117 #define GPIO_AF3_SAI1          ((uint8_t)0x03)  /* SAI1 Alternate Function mapping  */
00118 #define GPIO_AF3_COMP3         ((uint8_t)0x03)  /* COMP3 Alternate Function mapping */
00119
00120 /**
00121   * @brief   AF 4 selection
00122   */
00123 #define GPIO_AF4_TIM1          ((uint8_t)0x04)  /* TIM1 Alternate Function mapping    */
00124 #define GPIO_AF4_TIM8          ((uint8_t)0x04)  /* TIM8 Alternate Function mapping    */
00125 #define GPIO_AF4_TIM16         ((uint8_t)0x04)  /* TIM16 Alternate Function mapping   */
00126 #define GPIO_AF4_TIM17         ((uint8_t)0x04)  /* TIM17 Alternate Function mapping   */
00127 #define GPIO_AF4_TIM8_COMP1    ((uint8_t)0x04)  /* TIM8/COMP1 Break in Alternate Function mapping  */
00128 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
00129 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
00130 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
00131 #if defined(I2C4)
00132 #define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping    */
00133 #endif /* I2C4 */
00134
00135 /**
00136   * @brief   AF 5 selection
00137   */
00138 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping       */
00139 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping       */
00140 #if defined(SPI4)
00141 #define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping       */
00142 #endif /* SPI4 */
00143 #define GPIO_AF5_IR            ((uint8_t)0x05)  /* IR Alternate Function mapping         */
00144 #define GPIO_AF5_TIM8          ((uint8_t)0x05)  /* TIM8 Alternate Function mapping       */
00145 #define GPIO_AF5_TIM8_COMP1    ((uint8_t)0x05)  /* TIM8/COMP1 Break in Alternate Function mapping  */
00146 #define GPIO_AF5_UART4         ((uint8_t)0x05)  /* UART4 Alternate Function mapping      */
00147 #if defined(UART5)
00148 #define GPIO_AF5_UART5         ((uint8_t)0x05)  /* UART5 Alternate Function mapping      */
00149 #endif /* UART5 */
00150 #define GPIO_AF5_I2S2ext       ((uint8_t)0x05)  /* I2S2ext_SD Alternate Function mapping */
00151
00152 /**
00153   * @brief   AF 6 selection
00154   */
00155 #define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping       */
00156 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping       */
00157 #define GPIO_AF6_TIM1          ((uint8_t)0x06)  /* TIM1 Alternate Function mapping       */
00158 #if defined(TIM5)
00159 #define GPIO_AF6_TIM5          ((uint8_t)0x06)  /* TIM5 Alternate Function mapping       */
00160 #endif /* TIM5 */
00161 #define GPIO_AF6_TIM8          ((uint8_t)0x06)  /* TIM8 Alternate Function mapping       */
00162 #if defined(TIM20)
00163 #define GPIO_AF6_TIM20         ((uint8_t)0x06)  /* TIM20 Alternate Function mapping      */
00164 #endif /* TIM20 */
00165 #define GPIO_AF6_TIM1_COMP1    ((uint8_t)0x06)  /* TIM1/COMP1 Break in Alternate Function mapping  */
00166 #define GPIO_AF6_TIM1_COMP2    ((uint8_t)0x06)  /* TIM1/COMP2 Break in Alternate Function mapping  */
00167 #define GPIO_AF6_TIM8_COMP2    ((uint8_t)0x06)  /* TIM8/COMP2 Break in Alternate Function mapping  */
00168 #define GPIO_AF6_IR            ((uint8_t)0x06)  /* IR Alternate Function mapping         */
00169 #define GPIO_AF6_I2S3ext       ((uint8_t)0x06)  /* I2S3ext_SD Alternate Function mapping */
00170
00171 /**
00172   * @brief   AF 7 selection
00173   */
00174 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
00175 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
00176 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
00177 #if defined(COMP5)
00178 #define GPIO_AF7_COMP5         ((uint8_t)0x07)  /* COMP5 Alternate Function mapping   */
00179 #endif /* COMP5 */
00180 #if defined(COMP6)
00181 #define GPIO_AF7_COMP6         ((uint8_t)0x07)  /* COMP6 Alternate Function mapping   */
00182 #endif /* COMP6 */
00183 #if defined(COMP7)
00184 #define GPIO_AF7_COMP7         ((uint8_t)0x07)  /* COMP7 Alternate Function mapping   */
00185 #endif /* COMP7 */
00186
00187 /**
00188   * @brief   AF 8 selection
00189   */
00190 #define GPIO_AF8_COMP1         ((uint8_t)0x08)  /* COMP1 Alternate Function mapping   */
00191 #define GPIO_AF8_COMP2         ((uint8_t)0x08)  /* COMP2 Alternate Function mapping   */
00192 #define GPIO_AF8_COMP3         ((uint8_t)0x08)  /* COMP3 Alternate Function mapping   */
00193 #define GPIO_AF8_COMP4         ((uint8_t)0x08)  /* COMP4 Alternate Function mapping   */
00194 #if defined(COMP5)
00195 #define GPIO_AF8_COMP5         ((uint8_t)0x08)  /* COMP5 Alternate Function mapping   */
00196 #endif /* COMP5 */
00197 #if defined(COMP6)
00198 #define GPIO_AF8_COMP6         ((uint8_t)0x08)  /* COMP6 Alternate Function mapping   */
00199 #endif /* COMP6 */
00200 #if defined(COMP7)
00201 #define GPIO_AF8_COMP7         ((uint8_t)0x08)  /* COMP7 Alternate Function mapping   */
00202 #endif /* COMP7 */
00203 #define GPIO_AF8_I2C3          ((uint8_t)0x08)  /* I2C3 Alternate Function mapping    */
00204 #if defined(I2C4)
00205 #define GPIO_AF8_I2C4          ((uint8_t)0x08)  /* I2C4 Alternate Function mapping    */
00206 #endif /* I2C4 */
00207 #define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
00208 #define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
00209 #if defined(UART5)
00210 #define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
00211 #endif /* UART5 */
00212
00213 /**
00214   * @brief   AF 9 selection
00215   */
00216 #define GPIO_AF9_TIM1          ((uint8_t)0x09)  /* TIM1 Alternate Function mapping    */
00217 #define GPIO_AF9_TIM8          ((uint8_t)0x09)  /* TIM8 Alternate Function mapping    */
00218 #define GPIO_AF9_TIM15         ((uint8_t)0x09)  /* TIM15 Alternate Function mapping   */
00219 #define GPIO_AF9_TIM1_COMP1    ((uint8_t)0x09)  /* TIM1/COMP1 Break in Alternate Function mapping   */
00220 #define GPIO_AF9_TIM8_COMP1    ((uint8_t)0x09)  /* TIM8/COMP1 Break in Alternate Function mapping   */
00221 #define GPIO_AF9_TIM15_COMP1   ((uint8_t)0x09)  /* TIM15/COMP1 Break in Alternate Function mapping  */
00222 #define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping  */
00223 #if defined(FDCAN2)
00224 #define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping  */
00225 #endif /* FDCAN2 */
00226
00227 /**
00228   * @brief   AF 10 selection
00229   */
00230 #define GPIO_AF10_TIM2         ((uint8_t)0x0A)  /* TIM2 Alternate Function mapping    */
00231 #define GPIO_AF10_TIM3         ((uint8_t)0x0A)  /* TIM3 Alternate Function mapping    */
00232 #define GPIO_AF10_TIM4         ((uint8_t)0x0A)  /* TIM4 Alternate Function mapping    */
00233 #define GPIO_AF10_TIM8         ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping    */
00234 #define GPIO_AF10_TIM17        ((uint8_t)0x0A)  /* TIM17 Alternate Function mapping   */
00235 #define GPIO_AF10_TIM8_COMP2   ((uint8_t)0x0A)  /* TIM8/COMP2 Break in Alternate Function mapping    */
00236 #define GPIO_AF10_TIM17_COMP1  ((uint8_t)0x0A)  /* TIM17/COMP1 Break in Alternate Function mapping   */
00237 #if defined(QUADSPI)
00238 #define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* OctoSPI Manager Port 1 Alternate Function mapping */
00239 #endif /* QUADSPI */
00240
00241 /**
00242   * @brief   AF 11 selection
00243   */
00244 #define GPIO_AF11_FDCAN1       ((uint8_t)0x0B)  /* FDCAN1 Alternate Function mapping  */
00245 #if defined(FDCAN3)
00246 #define GPIO_AF11_FDCAN3       ((uint8_t)0x0B)  /* FDCAN3 Alternate Function mapping  */
00247 #endif /* FDCAN3 */
00248 #define GPIO_AF11_TIM1         ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
00249 #define GPIO_AF11_TIM8         ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
00250 #define GPIO_AF11_TIM8_COMP1   ((uint8_t)0x0B)  /* TIM8/COMP1 Break in Alternate Function mapping  */
00251 #define GPIO_AF11_LPTIM1       ((uint8_t)0x0B)  /* LPTIM1 Alternate Function mapping  */
00252
00253 /**
00254   * @brief   AF 12 selection
00255   */
00256 #define GPIO_AF12_LPUART1      ((uint8_t)0x0C)  /* LPUART1 Alternate Function mapping */
00257 #define GPIO_AF12_TIM1         ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
00258 #define GPIO_AF12_TIM1_COMP1   ((uint8_t)0x0C)  /* TIM1/COMP1 Break in Alternate Function mapping  */
00259 #define GPIO_AF12_TIM1_COMP2   ((uint8_t)0x0C)  /* TIM1/COMP2 Break in Alternate Function mapping  */
00260 #if defined(HRTIM1)
00261 #define GPIO_AF12_HRTIM1       ((uint8_t)0x0C)  /* HRTIM1 Alternate Function mapping  */
00262 #endif /* HRTIM1 */
00263 #if defined(FMC_BANK1)
00264 #define GPIO_AF12_FMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
00265 #endif /* FMC_BANK1 */
00266 #define GPIO_AF12_SAI1         ((uint8_t)0x0C)  /* SAI1 Alternate Function mapping  */
00267
00268 /**
00269   * @brief   AF 13 selection
00270   */
00271 #if defined(HRTIM1)
00272 #define GPIO_AF13_HRTIM1       ((uint8_t)0x0D)  /* HRTIM1 Alternate Function mapping  */
00273 #endif /* HRTIM1 */
00274 #define GPIO_AF13_SAI1         ((uint8_t)0x0D)  /* SAI1 Alternate Function mapping  */
00275
00276 /**
00277   * @brief   AF 14 selection
00278   */
00279 #define GPIO_AF14_TIM2         ((uint8_t)0x0E)  /* TIM2 Alternate Function mapping   */
00280 #define GPIO_AF14_TIM15        ((uint8_t)0x0E)  /* TIM15 Alternate Function mapping   */
00281 #define GPIO_AF14_UCPD1        ((uint8_t)0x0E)  /* UCPD1 Alternate Function mapping  */
00282 #define GPIO_AF14_SAI1         ((uint8_t)0x0E)  /* SAI1 Alternate Function mapping  */
00283 #define GPIO_AF14_UART4        ((uint8_t)0x0E)  /* UART4 Alternate Function mapping      */
00284 #if defined(UART5)
00285 #define GPIO_AF14_UART5        ((uint8_t)0x0E)  /* UART5 Alternate Function mapping      */
00286 #endif /* UART5 */
00287
00288 /**
00289   * @brief   AF 15 selection
00290   */
00291 #define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00292
00293 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
00294
00295 /**
00296   * @}
00297   */
00298
00299 /**
00300   * @}
00301   */
00302
00303 /* Exported macro ------------------------------------------------------------*/
00304 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
00305   * @{
00306   */
00307
00308 /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
00309   * @{
00310   */
00311 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0UL :\
00312                                       ((__GPIOx__) == (GPIOB))? 1UL :\
00313                                       ((__GPIOx__) == (GPIOC))? 2UL :\
00314                                       ((__GPIOx__) == (GPIOD))? 3UL :\
00315                                       ((__GPIOx__) == (GPIOE))? 4UL :\
00316                                       ((__GPIOx__) == (GPIOF))? 5UL : 6UL)
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /* Exported functions --------------------------------------------------------*/
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 #ifdef __cplusplus
00336 }
00337 #endif
00338
00339 #endif /* STM32G4xx_HAL_GPIO_EX_H */
00340
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_hrtim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_hrtim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Resolution Timer (HRTIM) peripheral:
00008   *           + HRTIM Initialization
00009   *           + DLL Calibration Start
00010   *           + Timer Time Base Unit Configuration
00011   *           + Simple Time Base Start/Stop
00012   *           + Simple Time Base Start/Stop Interrupt
00013   *           + Simple Time Base Start/Stop DMA Request
00014   *           + Simple Output Compare/PWM Channel Configuration
00015   *           + Simple Output Compare/PWM Channel Start/Stop Interrupt
00016   *           + Simple Output Compare/PWM Channel Start/Stop DMA Request
00017   *           + Simple Input Capture Channel Configuration
00018   *           + Simple Input Capture Channel Start/Stop Interrupt
00019   *           + Simple Input Capture Channel Start/Stop DMA Request
00020   *           + Simple One Pulse Channel Configuration
00021   *           + Simple One Pulse Channel Start/Stop Interrupt
00022   *           + HRTIM External Synchronization Configuration
00023   *           + HRTIM Burst Mode Controller Configuration
00024   *           + HRTIM Burst Mode Controller Enabling
00025   *           + HRTIM External Events Conditioning Configuration
00026   *           + HRTIM Faults Conditioning Configuration
00027   *           + HRTIM Faults Enabling
00028   *           + HRTIM ADC trigger Configuration
00029   *           + Waveform Timer Configuration
00030   *           + Waveform Event Filtering Configuration
00031   *           + Waveform Dead Time Insertion Configuration
00032   *           + Waveform Chopper Mode Configuration
00033   *           + Waveform Compare Unit Configuration
00034   *           + Waveform Capture Unit Configuration
00035   *           + Waveform Output Configuration
00036   *           + Waveform Counter Start/Stop
00037   *           + Waveform Counter Start/Stop Interrupt
00038   *           + Waveform Counter Start/Stop DMA Request
00039   *           + Waveform Output Enabling
00040   *           + Waveform Output Level Set/Get
00041   *           + Waveform Output State Get
00042   *           + Waveform Burst DMA Operation Configuration
00043   *           + Waveform Burst DMA Operation Start
00044   *           + Waveform Timer Counter Software Reset
00045   *           + Waveform Capture Software Trigger
00046   *           + Waveform Burst Mode Controller Software Trigger
00047   *           + Waveform Timer Pre-loadable Registers Update Enabling
00048   *           + Waveform Timer Pre-loadable Registers Software Update
00049   *           + Waveform Timer Delayed Protection Status Get
00050   *           + Waveform Timer Burst Status Get
00051   *           + Waveform Timer Push-Pull Status Get
00052   *           + Peripheral State Get
00053   *
00054   ******************************************************************************
00055   * @attention
00056   *
00057   * Copyright (c) 2019 STMicroelectronics.
00058   * All rights reserved.
00059   *
00060   * This software is licensed under terms that can be found in the LICENSE file
00061   * in the root directory of this software component.
00062   * If no LICENSE file comes with this software, it is provided AS-IS.
00063   *
00064   ******************************************************************************
00065   @verbatim
00066 ==============================================================================
00067                       ##### Simple mode v.s. waveform mode #####
00068 ==============================================================================
00069   [..] The HRTIM HAL API is split into 2 categories:
00070     (#)Simple functions: these functions allow for using a HRTIM timer as a
00071        general purpose timer with high resolution capabilities.
00072        HRTIM simple modes are managed through the set of functions named
00073        HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
00074        to the one defined for the TIM peripheral. When a HRTIM timer operates in
00075        simple mode, only a very limited set of HRTIM features are used.
00076        Following simple modes are proposed:
00077          (++)Output compare mode,
00078          (++)PWM output mode,
00079          (++)Input capture mode,
00080          (++)One pulse mode.
00081     (#)Waveform functions: These functions allow taking advantage of the HRTIM
00082        flexibility to produce numerous types of control signal. When a HRTIM timer
00083        operates in waveform mode, all the HRTIM features are accessible without
00084        any restriction. HRTIM waveform modes are managed through the set of
00085        functions named HAL_HRTIM_Waveform<Function>
00086
00087 ==============================================================================
00088                       ##### How to use this driver #####
00089 ==============================================================================
00090     [..]
00091      (#)Initialize the HRTIM low level resources by implementing the
00092         HAL_HRTIM_MspInit() function:
00093         (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
00094         (##)Connect HRTIM pins to MCU I/Os
00095             (+++) Enable the clock for the HRTIM GPIOs using the following
00096                   function: __HAL_RCC_GPIOx_CLK_ENABLE()
00097             (+++) Configure these GPIO pins in Alternate Function mode using
00098                   HAL_GPIO_Init()
00099         (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
00100             (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00101             (+++)Initialize the DMA handle
00102             (+++)Associate the initialized DMA handle to the appropriate DMA
00103                  handle of the HRTIM handle using __HAL_LINKDMA()
00104             (+++)Initialize the DMA channel using HAL_DMA_Init()
00105             (+++)Configure the priority and enable the NVIC for the transfer
00106                  complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
00107                  and HAL_NVIC_EnableIRQ()
00108         (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
00109             (+++)Configure the priority and enable the NVIC for the concerned
00110                  HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00111
00112     (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
00113        structure (field of the HRTIM handle) specifies which global interrupt of
00114        whole HRTIM must be enabled (Burst mode period, System fault, Faults).
00115        It also contains the HRTIM external synchronization configuration. HRTIM
00116        can act as a master (generating a synchronization signal) or as a slave
00117        (waiting for a trigger to be synchronized).
00118
00119     (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
00120        calibration is executed periodically and compensate for potential voltage
00121        and temperature drifts. DLL calibration period is specified by the
00122        CalibrationRate argument.
00123
00124     (#)HRTIM timers cannot be used until the high resolution unit is ready. This
00125        can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
00126        HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
00127        is still going on when timeout given as argument expires. DLL calibration
00128        can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
00129        In that case an interrupt is generated when the DLL calibration is completed.
00130        Note that as DLL calibration is executed on a periodic basis an interrupt
00131        will be generated at the end of every DLL calibration operation
00132       (worst case: one interrupt every 14 micro seconds !).
00133
00134      (#) Configure HRTIM resources shared by all HRTIM timers
00135         (##)Burst Mode Controller:
00136                 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
00137                      controller: operating mode (continuous or one-shot mode), clock
00138                      (source, prescaler) , trigger(s), period, idle duration.
00139         (##)External Events Conditioning:
00140                 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
00141                      external event channel: source, polarity, edge-sensitivity.
00142                      External event can be used as triggers (timer reset, input
00143                      capture, burst mode, ADC triggers, delayed protection)
00144                      They can also be used to set or reset timer outputs. Up to
00145                      10 event channels are available.
00146                 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
00147                      event sampling clock (used for digital filtering).
00148         (##)Fault Conditioning:
00149                 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
00150                      fault channel: source, polarity, edge-sensitivity. Fault
00151                      channels are used to disable the outputs in case of an
00152                      abnormal operation. Up to 6 fault channels are available.
00153                 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
00154                      sampling clock (used for digital filtering).
00155                 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
00156                      circuitry. By default all fault inputs are disabled.
00157         (##)ADC trigger:
00158                 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
00159                      the update of the ADC trigger register and the ADC trigger.
00160                      4 independent triggers are available to start both the regular
00161                      and the injected sequencers of the 2 ADCs
00162
00163      (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
00164          function must be called whatever the HRTIM timer operating mode is
00165          (simple v.s. waveform). It configures mainly:
00166         (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
00167         (##)The HRTIM  timer clock prescaler
00168         (##)The HRTIM  timer period
00169         (##)The HRTIM  timer repetition counter
00170
00171      *** If the HRTIM timer operates in simple mode ***
00172      ===================================================
00173      [..]
00174      (#) Start or Stop simple timers
00175               (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
00176                   HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
00177                   HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
00178               (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
00179                   HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
00180                   HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
00181                   HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
00182               (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
00183                   HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
00184                   HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
00185                   HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
00186               (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
00187                   HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
00188                   HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
00189                   HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
00190               (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
00191                   HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
00192                   HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
00193
00194      *** If the HRTIM timer operates in waveform mode ***
00195      ====================================================
00196      [..]
00197      (#) Completes waveform timer configuration
00198               (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
00199                   operating in wave form mode mainly consists in:
00200                 (+++)Enabling the HRTIM timer interrupts and DMA requests.
00201                 (+++)Enabling the half mode for the HRTIM timer.
00202                 (+++)Defining how the HRTIM timer reacts to external synchronization input.
00203                 (+++)Enabling the push-pull mode for the HRTIM timer.
00204                 (+++)Enabling the fault channels for the HRTIM timer.
00205                 (+++)Enabling the dead-time insertion for the HRTIM timer.
00206                 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
00207                      on which the delayed protection are applied).
00208                 (+++)Specifying the HRTIM timer update and reset triggers.
00209                 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
00210               (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
00211                   event blanking and windowing circuitry of a HRTIM timer:
00212                 (+++)Blanking:  to mask external events during a defined  time period a defined time period
00213                 (+++)Windowing, to enable external events only during a defined time period
00214               (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
00215                   unit for a HRTIM timer. Allows to generate a couple of
00216                   complementary signals from a single reference waveform,
00217                   with programmable delays between active state.
00218               (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
00219                   the high-frequency carrier signal added on top of the timing
00220                   unit output. Chopper mode can be enabled or disabled for each
00221                    timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
00222               (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
00223                   controller. Allows having multiple HRTIM registers updated
00224                   with a single DMA request. The burst DMA operation is started
00225                   by calling HAL_HRTIM_BurstDMATransfer().
00226               (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
00227                   of a HRTIM timer. This operation consists in setting the
00228                   compare value and possibly specifying the auto delayed mode
00229                   for compare units 2 and 4 (allows to have compare events
00230                   generated relatively to capture events). Note that when auto
00231                   delayed mode is needed, the capture unit associated to the
00232                   compare unit must be configured separately.
00233               (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
00234                   of a HRTIM timer. This operation consists in specifying the
00235                   source(s)  triggering the capture (timer register update event,
00236                   external event, timer output set/reset event, other HRTIM
00237                   timer related events).
00238               (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
00239                   output mainly consists in:
00240                 (+++)Setting the output polarity (active high or active low),
00241                 (+++)Defining the set/reset crossbar for the output,
00242                 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
00243
00244      (#) Set waveform timer output(s) level
00245               (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
00246                   active or inactive level. For example, when deadtime insertion
00247                   is enabled it is necessary to force the output level by software
00248                   to have the outputs in a complementary state as soon as the RUN mode is entered.
00249
00250      (#) Enable or Disable waveform timer output(s)
00251               (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
00252
00253      (#) Start or Stop waveform HRTIM timer(s).
00254               (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
00255               (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
00256               (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
00257      (#) Burst mode controller enabling:
00258               (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
00259                   burst mode controller.
00260
00261      (#) Some HRTIM operations can be triggered by software:
00262               (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
00263                   trigs the burst operation.
00264               (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
00265                   capture of the HRTIM timer counter.
00266               (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
00267                   update of the pre-loadable registers of the HRTIM timer
00268               (++)HAL_HRTIM_SoftwareReset():calling this function resets the
00269                   HRTIM timer counter.
00270
00271      (#) Some functions can be used any time to retrieve HRTIM timer related
00272             information
00273               (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
00274                   capture register of the designated capture unit.
00275               (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
00276                  (ACTIVE/INACTIVE) of the designated timer output.
00277               (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
00278                  (IDLE/RUN/FAULT) of the designated timer output.
00279               (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
00280                  (ACTIVE/INACTIVE) of the designated output when the delayed
00281                   protection was triggered.
00282               (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
00283                  (ACTIVE/INACTIVE) of the burst mode controller.
00284               (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
00285                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00286                  the push-pull status indicates on which output the signal is currently
00287                  active (e.g signal applied on output 1 and output 2 forced
00288                  inactive or vice versa).
00289              (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
00290                  is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
00291                  the idle push-pull status indicates during which period the
00292                  delayed protection request occurred (e.g. protection occurred
00293                  when the output 1 was active and output 2 forced inactive or
00294                  vice versa).
00295
00296      (#) Some functions can be used any time to retrieve actual HRTIM status
00297              (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
00298
00299      *** Callback registration ***
00300      =============================
00301      [..]
00302      The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
00303      allows the user to configure dynamically the driver callbacks.
00304      Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
00305      to register an interrupt callback.
00306
00307      [..]
00308      Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
00309        (+) Fault1Callback               : Fault 1 interrupt callback function
00310        (+) Fault2Callback               : Fault 2 interrupt callback function
00311        (+) Fault3Callback               : Fault 3 interrupt callback function
00312        (+) Fault4Callback               : Fault 4 interrupt callback function
00313        (+) Fault5Callback               : Fault 5 interrupt callback function
00314        (+) Fault6Callback               : Fault 6 interrupt callback function
00315        (+) SystemFaultCallback          : System fault interrupt callback function
00316        (+) DLLCalibrationReadyCallback  : DLL Ready interrupt callback function
00317        (+) BurstModePeriodCallback      : Burst mode period interrupt callback function
00318        (+) SynchronizationEventCallback : Sync Input interrupt callback function
00319        (+) ErrorCallback                : DMA error callback function
00320        (+) MspInitCallback              : HRTIM MspInit callback function
00321        (+) MspDeInitCallback            : HRTIM MspInit callback function
00322
00323      [..]
00324      Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
00325        (+) RegistersUpdateCallback   : Timer x Update interrupt callback function
00326        (+) RepetitionEventCallback   : Timer x Repetition interrupt callback function
00327        (+) Compare1EventCallback     : Timer x Compare 1 match interrupt callback function
00328        (+) Compare2EventCallback     : Timer x Compare 2 match interrupt callback function
00329        (+) Compare3EventCallback     : Timer x Compare 3 match interrupt callback function
00330        (+) Compare4EventCallback     : Timer x Compare 4 match interrupt callback function
00331        (+) Capture1EventCallback     : Timer x Capture 1 interrupts callback function
00332        (+) Capture2EventCallback     : Timer x Capture 2 interrupts callback function
00333        (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
00334        (+) CounterResetCallback      : Timer x counter reset/roll-over interrupt callback function
00335        (+) Output1SetCallback        : Timer x output 1 set interrupt callback function
00336        (+) Output1ResetCallback      : Timer x output 1 reset interrupt callback function
00337        (+) Output2SetCallback        : Timer x output 2 set interrupt callback function
00338        (+) Output2ResetCallback      : Timer x output 2 reset interrupt callback function
00339        (+) BurstDMATransferCallback  : Timer x Burst DMA completed interrupt callback function
00340
00341      [..]
00342      Both functions take as parameters the HAL peripheral handle, the Callback ID
00343      and a pointer to the user callback function.
00344
00345      [..]
00346      Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
00347      to reset a callback to the default weak function. Both functions take  as parameters
00348      the HAL peripheral handle and the Callback ID.
00349
00350      [..]
00351      By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
00352      all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
00353      Exception done for MspInit and MspDeInit functions that are reset to the legacy
00354      weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
00355      callbacks are null (not registered beforehand). If MspInit or MspDeInit are
00356      not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
00357      MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00358
00359      [..]
00360      Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
00361      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00362      in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
00363      (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00364      Then, the user first registers the MspInit/MspDeInit user callbacks
00365      using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
00366      or HAL_HRTIM_Init() function.
00367
00368      [..]
00369      When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
00370      not defined, the callback registration feature is not available and all
00371      callbacks are set to the corresponding weak functions.
00372
00373   @endverbatim
00374   ******************************************************************************
00375   */
00376
00377 /* Includes ------------------------------------------------------------------*/
00378 #include "stm32g4xx_hal.h"
00379
00380 /** @addtogroup STM32G4xx_HAL_Driver
00381   * @{
00382   */
00383
00384 #ifdef HAL_HRTIM_MODULE_ENABLED
00385
00386 #if defined(HRTIM1)
00387
00388 /** @defgroup HRTIM HRTIM
00389   * @brief HRTIM HAL module driver
00390   * @{
00391   */
00392
00393 /* Private typedef -----------------------------------------------------------*/
00394 /* Private define ------------------------------------------------------------*/
00395 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
00396   * @{
00397   */
00398 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
00399                            HRTIM_FLTR_FLT2EN |\
00400                            HRTIM_FLTR_FLT3EN |\
00401                            HRTIM_FLTR_FLT4EN | \
00402                            HRTIM_FLTR_FLT5EN | \
00403                            HRTIM_FLTR_FLT6EN)
00404
00405 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER  |\
00406                                       HRTIM_TIMUPDATETRIGGER_TIMER_A |\
00407                                       HRTIM_TIMUPDATETRIGGER_TIMER_B |\
00408                                       HRTIM_TIMUPDATETRIGGER_TIMER_C |\
00409                                       HRTIM_TIMUPDATETRIGGER_TIMER_D |\
00410                                       HRTIM_TIMUPDATETRIGGER_TIMER_E |\
00411                                       HRTIM_TIMUPDATETRIGGER_TIMER_F)
00412
00413 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
00414                                (HRTIM_FAULTLOCK_READONLY << 8U)  | \
00415                                (HRTIM_FAULTLOCK_READONLY << 16U) | \
00416                                (HRTIM_FAULTLOCK_READONLY << 24U))
00417
00418 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
00419                                (HRTIM_FAULTLOCK_READONLY << 8U))
00420 /**
00421   * @}
00422   */
00423
00424 /* Private macro -------------------------------------------------------------*/
00425 /* Private variables ---------------------------------------------------------*/
00426 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
00427   * @{
00428   */
00429 static uint32_t TimerIdxToTimerId[] =
00430 {
00431   HRTIM_TIMERID_TIMER_A,
00432   HRTIM_TIMERID_TIMER_B,
00433   HRTIM_TIMERID_TIMER_C,
00434   HRTIM_TIMERID_TIMER_D,
00435   HRTIM_TIMERID_TIMER_E,
00436   HRTIM_TIMERID_TIMER_F,
00437   HRTIM_TIMERID_MASTER,
00438 };
00439 /**
00440   * @}
00441   */
00442
00443 /* Private function prototypes -----------------------------------------------*/
00444 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
00445   * @{
00446   */
00447 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
00448                                     const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00449
00450 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
00451                                         uint32_t TimerIdx,
00452                                         const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
00453
00454 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00455                                         const HRTIM_TimerCfgTypeDef * pTimerCfg);
00456
00457 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
00458                                             uint32_t TimerIdx,
00459                                             const HRTIM_TimerCfgTypeDef * pTimerCfg);
00460
00461 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
00462                                              uint32_t TimerIdx,
00463                                              const HRTIM_TimerCtlTypeDef * pTimerCtl);
00464
00465 static void  HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
00466                                              uint32_t TimerIdx,
00467                                              uint32_t pRollOverMode);
00468
00469
00470 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
00471                                     uint32_t TimerIdx,
00472                                     uint32_t CaptureUnit,
00473                                     uint32_t Event);
00474
00475 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
00476                                 uint32_t TimerIdx,
00477                                 uint32_t Output,
00478                                 const HRTIM_OutputCfgTypeDef * pOutputCfg);
00479
00480 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
00481                               uint32_t Event,
00482                               const HRTIM_EventCfgTypeDef * pEventCfg);
00483
00484 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
00485                                   uint32_t TimerIdx,
00486                                   uint32_t Event);
00487
00488 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
00489                                       uint32_t TimerIdx,
00490                                       uint32_t OCChannel);
00491
00492 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
00493                                        uint32_t TimerIdx,
00494                                        uint32_t OCChannel);
00495
00496 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
00497                                                           uint32_t TimerIdx);
00498
00499 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
00500                                          const DMA_HandleTypeDef * hdma);
00501
00502 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
00503                                       uint32_t TimerIdx);
00504
00505 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
00506
00507 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
00508
00509 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
00510                                        uint32_t TimerIdx);
00511
00512 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
00513
00514 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
00515
00516 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
00517
00518 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
00519 /**
00520   * @}
00521   */
00522
00523 /* Exported functions ---------------------------------------------------------*/
00524 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
00525   * @{
00526   */
00527
00528 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
00529  *  @brief    Initialization and Configuration functions
00530 @verbatim
00531  ===============================================================================
00532               ##### Initialization and Time Base Configuration functions #####
00533  ===============================================================================
00534     [..]  This section provides functions allowing to:
00535       (+) Initialize a HRTIM instance
00536       (+) De-initialize a HRTIM instance
00537       (+) Initialize the HRTIM MSP
00538       (+) De-initialize the HRTIM MSP
00539       (+) Start the high-resolution unit (start DLL calibration)
00540       (+) Check that the high resolution unit is ready (DLL calibration done)
00541       (+) Configure the time base unit of a HRTIM timer
00542
00543 @endverbatim
00544   * @{
00545   */
00546
00547 /**
00548   * @brief  Initialize a HRTIM instance
00549   * @param  hhrtim pointer to HAL HRTIM handle
00550   * @retval HAL status
00551   */
00552 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
00553 {
00554   uint8_t timer_idx;
00555   uint32_t hrtim_mcr;
00556
00557   /* Check the HRTIM handle allocation */
00558   if(hhrtim == NULL)
00559   {
00560     return HAL_ERROR;
00561   }
00562
00563   /* Check the parameters */
00564   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00565   assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
00566
00567 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00568   if (hhrtim->State == HAL_HRTIM_STATE_RESET)
00569   {
00570     /* Initialize callback function pointers to their default values */
00571     hhrtim->Fault1Callback               = HAL_HRTIM_Fault1Callback;
00572     hhrtim->Fault2Callback               = HAL_HRTIM_Fault2Callback;
00573     hhrtim->Fault3Callback               = HAL_HRTIM_Fault3Callback;
00574     hhrtim->Fault4Callback               = HAL_HRTIM_Fault4Callback;
00575     hhrtim->Fault5Callback               = HAL_HRTIM_Fault5Callback;
00576     hhrtim->Fault6Callback               = HAL_HRTIM_Fault6Callback;
00577     hhrtim->SystemFaultCallback          = HAL_HRTIM_SystemFaultCallback;
00578     hhrtim->DLLCalibrationReadyCallback  = HAL_HRTIM_DLLCalibrationReadyCallback;
00579     hhrtim->BurstModePeriodCallback      = HAL_HRTIM_BurstModePeriodCallback;
00580     hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
00581     hhrtim->ErrorCallback                = HAL_HRTIM_ErrorCallback;
00582     hhrtim->RegistersUpdateCallback      = HAL_HRTIM_RegistersUpdateCallback;
00583     hhrtim->RepetitionEventCallback      = HAL_HRTIM_RepetitionEventCallback;
00584     hhrtim->Compare1EventCallback        = HAL_HRTIM_Compare1EventCallback;
00585     hhrtim->Compare2EventCallback        = HAL_HRTIM_Compare2EventCallback;
00586     hhrtim->Compare3EventCallback        = HAL_HRTIM_Compare3EventCallback;
00587     hhrtim->Compare4EventCallback        = HAL_HRTIM_Compare4EventCallback;
00588     hhrtim->Capture1EventCallback        = HAL_HRTIM_Capture1EventCallback;
00589     hhrtim->Capture2EventCallback        = HAL_HRTIM_Capture2EventCallback;
00590     hhrtim->DelayedProtectionCallback    = HAL_HRTIM_DelayedProtectionCallback;
00591     hhrtim->CounterResetCallback         = HAL_HRTIM_CounterResetCallback;
00592     hhrtim->Output1SetCallback           = HAL_HRTIM_Output1SetCallback;
00593     hhrtim->Output1ResetCallback         = HAL_HRTIM_Output1ResetCallback;
00594     hhrtim->Output2SetCallback           = HAL_HRTIM_Output2SetCallback;
00595     hhrtim->Output2ResetCallback         = HAL_HRTIM_Output2ResetCallback;
00596     hhrtim->BurstDMATransferCallback     = HAL_HRTIM_BurstDMATransferCallback;
00597
00598     if (hhrtim->MspInitCallback == NULL)
00599     {
00600       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
00601     }
00602   }
00603 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00604
00605   /* Set the HRTIM state */
00606   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00607
00608   /* Initialize the DMA handles */
00609   hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
00610   hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
00611   hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
00612   hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
00613   hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
00614   hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
00615   hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
00616
00617   /* HRTIM output synchronization configuration (if required) */
00618   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
00619   {
00620     /* Check parameters */
00621     assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
00622     assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
00623
00624     /* The synchronization output initialization procedure must be done prior
00625        to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
00626     */
00627     if (hhrtim->Instance == HRTIM1)
00628     {
00629       /* Enable the HRTIM peripheral clock */
00630       __HAL_RCC_HRTIM1_CLK_ENABLE();
00631     }
00632
00633     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00634
00635     /* Set the event to be sent on the synchronization output */
00636     hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
00637     hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
00638
00639     /* Set the polarity of the synchronization output */
00640     hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
00641     hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
00642
00643     /* Update the HRTIM registers */
00644     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00645   }
00646
00647   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00648 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00649   hhrtim->MspInitCallback(hhrtim);
00650 #else
00651   HAL_HRTIM_MspInit(hhrtim);
00652 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00653
00654   /* HRTIM input synchronization configuration (if required) */
00655   if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
00656   {
00657     /* Check parameters */
00658     assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
00659
00660     hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
00661
00662     /* Set the synchronization input source */
00663     hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
00664     hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
00665
00666     /* Update the HRTIM registers */
00667     hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
00668   }
00669
00670   /* Initialize the HRTIM state*/
00671   hhrtim->State = HAL_HRTIM_STATE_READY;
00672
00673   /* Initialize the lock status of the HRTIM HAL API */
00674   __HAL_UNLOCK(hhrtim);
00675
00676   /* Initialize timer related parameters */
00677   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
00678        timer_idx <= HRTIM_TIMERINDEX_MASTER ;
00679        timer_idx++)
00680   {
00681     hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
00682     hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
00683     hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
00684     hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
00685     hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
00686     hhrtim->TimerParam[timer_idx].DMASize = 0U;
00687   }
00688
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief  De-initialize a HRTIM instance
00694   * @param  hhrtim pointer to HAL HRTIM handle
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
00698 {
00699   /* Check the HRTIM handle allocation */
00700   if(hhrtim == NULL)
00701   {
00702     return HAL_ERROR;
00703   }
00704
00705   /* Check the parameters */
00706   assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
00707
00708   /* Set the HRTIM state */
00709   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00710
00711   /* DeInit the low level hardware */
00712 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00713   if (hhrtim->MspDeInitCallback == NULL)
00714   {
00715     hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
00716   }
00717
00718   hhrtim->MspDeInitCallback(hhrtim);
00719 #else
00720   HAL_HRTIM_MspDeInit(hhrtim);
00721 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00722
00723   hhrtim->State = HAL_HRTIM_STATE_READY;
00724
00725   return HAL_OK;
00726 }
00727
00728 /**
00729   * @brief  MSP initialization for a HRTIM instance
00730   * @param  hhrtim pointer to HAL HRTIM handle
00731   * @retval None
00732   */
00733 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
00734 {
00735   /* Prevent unused argument(s) compilation warning */
00736   UNUSED(hhrtim);
00737
00738   /* NOTE: This function should not be modified, when the callback is needed,
00739            the HAL_HRTIM_MspInit could be implemented in the user file
00740    */
00741 }
00742
00743 /**
00744   * @brief  MSP de-initialization of a HRTIM instance
00745   * @param  hhrtim pointer to HAL HRTIM handle
00746   * @retval None
00747   */
00748 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
00749 {
00750   /* Prevent unused argument(s) compilation warning */
00751   UNUSED(hhrtim);
00752
00753   /* NOTE: This function should not be modified, when the callback is needed,
00754            the HAL_HRTIM_MspDeInit could be implemented in the user file
00755    */
00756 }
00757
00758 /**
00759   * @brief  Start the DLL calibration
00760   * @param  hhrtim pointer to HAL HRTIM handle
00761   * @param  CalibrationRate DLL calibration period
00762   *                    This parameter can be one of the following values:
00763   *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
00764   *                    @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
00765   *                    @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
00766   *                    @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
00767   *                    @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
00768   * @retval HAL status
00769   * @note This function locks the HRTIM instance. HRTIM instance is unlocked
00770   *       within the HAL_HRTIM_PollForDLLCalibration function, just before
00771   *       exiting the function.
00772   */
00773 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
00774                                                 uint32_t CalibrationRate)
00775 {
00776   /* Check the parameters */
00777   assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
00778
00779   /* Process Locked */
00780   __HAL_LOCK(hhrtim);
00781
00782   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00783
00784   if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
00785   {
00786     /* One shot DLL calibration */
00787     CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
00788     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
00789   }
00790   else
00791   {
00792     /* Periodic DLL calibration */
00793     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
00794     MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
00795     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
00796   }
00797
00798   /* Set HRTIM state */
00799   hhrtim->State = HAL_HRTIM_STATE_READY;
00800
00801   return HAL_OK;
00802 }
00803
00804 /**
00805   * @brief  Start the DLL calibration.
00806   *         DLL ready interrupt is enabled
00807   * @param  hhrtim pointer to HAL HRTIM handle
00808   * @param  CalibrationRate DLL calibration period
00809   *                    This parameter can be one of the following values:
00810   *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
00811   *                    @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
00812   *                    @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
00813   *                    @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
00814   *                    @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
00815   * @retval HAL status
00816   * @note This function locks the HRTIM instance. HRTIM instance is unlocked
00817   *       within the IRQ processing function when processing the DLL ready
00818   *       interrupt.
00819   * @note If this function is called for periodic calibration, the DLLRDY
00820   *       interrupt is generated every time the calibration completes which
00821   *       will significantly increases the overall interrupt rate.
00822   */
00823 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
00824                                                    uint32_t CalibrationRate)
00825 {
00826   /* Check the parameters */
00827   assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
00828
00829   /* Process Locked */
00830   __HAL_LOCK(hhrtim);
00831
00832   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00833
00834   /* Enable DLL Ready interrupt flag */
00835   __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
00836
00837   if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
00838   {
00839     /* One shot DLL calibration */
00840     CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
00841     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
00842   }
00843   else
00844   {
00845     /* Periodic DLL calibration */
00846     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
00847     MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
00848     SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
00849   }
00850
00851   /* Set HRTIM state */
00852   hhrtim->State = HAL_HRTIM_STATE_READY;
00853
00854   return HAL_OK;
00855 }
00856
00857 /**
00858   * @brief  Poll the DLL calibration ready flag and returns when the flag is
00859   *         set (DLL calibration completed) or upon timeout expiration.
00860   * @param  hhrtim pointer to HAL HRTIM handle
00861   * @param  Timeout Timeout duration in millisecond
00862   * @retval HAL status
00863   */
00864 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
00865                                                   uint32_t Timeout)
00866 {
00867   uint32_t tickstart;
00868
00869   tickstart = HAL_GetTick();
00870
00871   /* Check End of conversion flag */
00872   while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
00873   {
00874     if (Timeout != HAL_MAX_DELAY)
00875     {
00876       if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
00877       {
00878         hhrtim->State = HAL_HRTIM_STATE_ERROR;
00879         return HAL_TIMEOUT;
00880       }
00881     }
00882   }
00883
00884   /* Set HRTIM State */
00885   hhrtim->State = HAL_HRTIM_STATE_READY;
00886
00887   /* Process unlocked */
00888   __HAL_UNLOCK(hhrtim);
00889
00890   return HAL_OK;
00891 }
00892
00893 /**
00894   * @brief  Configure the time base unit of a timer
00895   * @param  hhrtim pointer to HAL HRTIM handle
00896   * @param  TimerIdx Timer index
00897   *                   This parameter can be one of the following values:
00898   *                   @arg HRTIM_TIMERINDEX_MASTER for master timer
00899   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00900   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00901   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00902   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00903   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00904   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
00905   * @param  pTimeBaseCfg pointer to the time base configuration structure
00906   * @note This function must be called prior starting the timer
00907   * @note   The time-base unit initialization parameters specify:
00908   *           The timer counter operating mode (continuous, one shot),
00909   *           The timer clock prescaler,
00910   *           The timer period,
00911   *           The timer repetition counter.
00912   * @retval HAL status
00913   */
00914 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
00915                                            uint32_t TimerIdx,
00916                                            const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
00917 {
00918   /* Check the parameters */
00919   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00920   assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
00921   assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
00922
00923   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
00924   {
00925      return HAL_BUSY;
00926   }
00927
00928   /* Set the HRTIM state */
00929   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00930
00931   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
00932   {
00933     /* Configure master timer time base unit */
00934     HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
00935   }
00936   else
00937   {
00938     /* Configure timing unit time base unit */
00939     HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
00940   }
00941
00942   /* Set HRTIM state */
00943   hhrtim->State = HAL_HRTIM_STATE_READY;
00944
00945   return HAL_OK;
00946 }
00947
00948 /**
00949   * @}
00950   */
00951
00952 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
00953  *  @brief    Simple time base mode functions.
00954 @verbatim
00955  ===============================================================================
00956               ##### Simple time base mode functions #####
00957  ===============================================================================
00958     [..]  This section provides functions allowing to:
00959       (+) Start simple time base
00960       (+) Stop simple time base
00961       (+) Start simple time base and enable interrupt
00962       (+) Stop simple time base and disable interrupt
00963       (+) Start simple time base and enable DMA transfer
00964       (+) Stop simple time base and disable DMA transfer
00965       -@-  When a HRTIM timer operates in simple time base mode, the timer
00966            counter counts from 0 to the period value.
00967
00968 @endverbatim
00969   * @{
00970   */
00971
00972 /**
00973   * @brief  Start the counter of a timer operating in simple time base mode.
00974   * @param  hhrtim pointer to HAL HRTIM handle
00975   * @param  TimerIdx Timer index.
00976   *                   This parameter can be one of the following values:
00977   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
00978   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
00979   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
00980   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
00981   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
00982   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
00983   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
00987                                            uint32_t TimerIdx)
00988 {
00989    /* Check the parameters */
00990   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
00991
00992   /* Process Locked */
00993   __HAL_LOCK(hhrtim);
00994
00995   hhrtim->State = HAL_HRTIM_STATE_BUSY;
00996
00997   /* Enable the timer counter */
00998   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
00999
01000   hhrtim->State = HAL_HRTIM_STATE_READY;
01001
01002   /* Process Unlocked */
01003   __HAL_UNLOCK(hhrtim);
01004
01005   return HAL_OK;
01006 }
01007
01008 /**
01009   * @brief  Stop the counter of a timer operating in simple time base mode.
01010   * @param  hhrtim pointer to HAL HRTIM handle
01011   * @param  TimerIdx Timer index.
01012   *                   This parameter can be one of the following values:
01013   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01014   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01015   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01016   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01017   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01018   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01019   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01020   * @retval HAL status
01021   */
01022 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
01023                                           uint32_t TimerIdx)
01024 {
01025    /* Check the parameters */
01026   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01027
01028   /* Process Locked */
01029   __HAL_LOCK(hhrtim);
01030
01031   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01032
01033   /* Disable the timer counter */
01034   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01035
01036   hhrtim->State = HAL_HRTIM_STATE_READY;
01037
01038   /* Process Unlocked */
01039   __HAL_UNLOCK(hhrtim);
01040
01041   return HAL_OK;
01042 }
01043
01044 /**
01045   * @brief  Start the counter of a timer operating in simple time base mode
01046   *         (Timer repetition interrupt is enabled).
01047   * @param  hhrtim pointer to HAL HRTIM handle
01048   * @param  TimerIdx Timer index.
01049   *                   This parameter can be one of the following values:
01050   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01051   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01052   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01053   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01054   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01055   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01056   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01057   * @retval HAL status
01058   */
01059 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
01060                                               uint32_t TimerIdx)
01061 {
01062    /* Check the parameters */
01063   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01064
01065   /* Process Locked */
01066   __HAL_LOCK(hhrtim);
01067
01068   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01069
01070   /* Enable the repetition interrupt */
01071   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01072   {
01073     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
01074   }
01075   else
01076   {
01077     __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
01078   }
01079
01080   /* Enable the timer counter */
01081   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01082
01083   hhrtim->State = HAL_HRTIM_STATE_READY;
01084
01085   /* Process Unlocked */
01086   __HAL_UNLOCK(hhrtim);
01087
01088   return HAL_OK;
01089 }
01090
01091 /**
01092   * @brief  Stop the counter of a timer operating in simple time base mode
01093   *         (Timer repetition interrupt is disabled).
01094   * @param  hhrtim pointer to HAL HRTIM handle
01095   * @param  TimerIdx Timer index.
01096   *                   This parameter can be one of the following values:
01097   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01098   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01099   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01100   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01101   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01102   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01103   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01104   * @retval HAL status
01105   */
01106 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
01107                                              uint32_t TimerIdx)
01108 {
01109    /* Check the parameters */
01110   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01111
01112   /* Process Locked */
01113   __HAL_LOCK(hhrtim);
01114
01115   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01116
01117   /* Disable the repetition interrupt */
01118   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01119   {
01120     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
01121   }
01122   else
01123   {
01124     __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
01125   }
01126
01127   /* Disable the timer counter */
01128   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01129
01130   hhrtim->State = HAL_HRTIM_STATE_READY;
01131
01132   /* Process Unlocked */
01133   __HAL_UNLOCK(hhrtim);
01134
01135   return HAL_OK;
01136 }
01137
01138 /**
01139   * @brief  Start the counter of a timer operating in simple time base mode
01140   *         (Timer repetition DMA request is enabled).
01141   * @param  hhrtim pointer to HAL HRTIM handle
01142   * @param  TimerIdx Timer index.
01143   *                   This parameter can be one of the following values:
01144   *                    @arg HRTIM_TIMERINDEX_MASTER  for master timer
01145   *                    @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01146   *                    @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01147   *                    @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01148   *                    @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01149   *                    @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01150   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01151   * @param  SrcAddr DMA transfer source address
01152   * @param  DestAddr DMA transfer destination address
01153   * @param  Length The length of data items (data size) to be transferred
01154   *                     from source to destination
01155   */
01156 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01157                                                uint32_t TimerIdx,
01158                                                uint32_t SrcAddr,
01159                                                uint32_t DestAddr,
01160                                                uint32_t Length)
01161 {
01162   DMA_HandleTypeDef * hdma;
01163
01164   /* Check the parameters */
01165   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01166
01167   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01168   {
01169      return HAL_BUSY;
01170   }
01171   if(hhrtim->State == HAL_HRTIM_STATE_READY)
01172   {
01173     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
01174     {
01175       return HAL_ERROR;
01176     }
01177     else
01178     {
01179       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01180     }
01181   }
01182
01183   /* Process Locked */
01184   __HAL_LOCK(hhrtim);
01185
01186   /* Get the timer DMA handler */
01187   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01188
01189   if (hdma == NULL)
01190   {
01191    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01192
01193    /* Process Unlocked */
01194    __HAL_UNLOCK(hhrtim);
01195
01196    return HAL_ERROR;
01197   }
01198
01199   /* Set the DMA transfer completed callback */
01200   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01201   {
01202     hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
01203   }
01204   else
01205   {
01206     hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01207   }
01208
01209   /* Set the DMA error callback */
01210   hdma->XferErrorCallback = HRTIM_DMAError ;
01211
01212   /* Enable the DMA channel */
01213   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
01214     {
01215         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01216
01217         /* Process Unlocked */
01218         __HAL_UNLOCK(hhrtim);
01219
01220         return HAL_ERROR;
01221     }
01222
01223   /* Enable the timer repetition DMA request */
01224   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01225   {
01226     __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01227   }
01228   else
01229   {
01230     __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01231   }
01232
01233   /* Enable the timer counter */
01234   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01235
01236   hhrtim->State = HAL_HRTIM_STATE_READY;
01237
01238   /* Process Unlocked */
01239   __HAL_UNLOCK(hhrtim);
01240
01241   return HAL_OK;
01242 }
01243
01244 /**
01245   * @brief  Stop the counter of a timer operating in simple time base mode
01246   *         (Timer repetition DMA request is disabled).
01247   * @param  hhrtim pointer to HAL HRTIM handle
01248   * @param  TimerIdx Timer index.
01249   *                   This parameter can be one of the following values:
01250   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
01251   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01252   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01253   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01254   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01255   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01256   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01257   * @retval HAL status
01258   */
01259 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01260                                               uint32_t TimerIdx)
01261 {
01262   DMA_HandleTypeDef * hdma;
01263
01264   /* Check the parameters */
01265   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
01266
01267   /* Process Locked */
01268   __HAL_LOCK(hhrtim);
01269
01270   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
01271   {
01272     hhrtim->State = HAL_HRTIM_STATE_READY;
01273
01274     /* Disable the DMA */
01275     if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
01276     {
01277         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01278     }
01279     /* Disable the timer repetition DMA request */
01280     __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
01281   }
01282   else
01283   {
01284     /* Get the timer DMA handler */
01285     hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01286
01287     if (hdma == NULL)
01288     {
01289       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01290     }
01291     else
01292     {
01293       hhrtim->State = HAL_HRTIM_STATE_READY;
01294
01295       /* Disable the DMA */
01296       if (HAL_DMA_Abort(hdma) != HAL_OK)
01297       {
01298          hhrtim->State = HAL_HRTIM_STATE_ERROR;
01299       }
01300
01301       /* Disable the timer repetition DMA request */
01302       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
01303      }
01304   }
01305
01306   /* Disable the timer counter */
01307   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01308
01309   /* Process Unlocked */
01310   __HAL_UNLOCK(hhrtim);
01311
01312   if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
01313   {
01314       return HAL_ERROR;
01315   }
01316   else
01317   {
01318       return HAL_OK;
01319   }
01320 }
01321
01322 /**
01323   * @}
01324   */
01325
01326 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
01327  *  @brief    Simple output compare functions
01328 @verbatim
01329  ===============================================================================
01330               ##### Simple output compare functions #####
01331  ===============================================================================
01332     [..]  This section provides functions allowing to:
01333       (+) Configure simple output channel
01334       (+) Start simple output compare
01335       (+) Stop simple output compare
01336       (+) Start simple output compare and enable interrupt
01337       (+) Stop simple output compare and disable interrupt
01338       (+) Start simple output compare and enable DMA transfer
01339       (+) Stop simple output compare and disable DMA transfer
01340        -@- When a HRTIM timer operates in simple output compare mode
01341            the output level is set to a programmable value when a match
01342            is found between the compare register and the counter.
01343            Compare unit 1 is automatically associated to output 1
01344            Compare unit 2 is automatically associated to output 2
01345 @endverbatim
01346   * @{
01347   */
01348
01349 /**
01350   * @brief  Configure an output in simple output compare mode
01351   * @param  hhrtim pointer to HAL HRTIM handle
01352   * @param  TimerIdx Timer index
01353   *                   This parameter can be one of the following values:
01354   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01355   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01356   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01357   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01358   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01359   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01360   * @param  OCChannel Timer output
01361   *                    This parameter can be one of the following values:
01362   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01363   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01364   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01365   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01366   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01367   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01368   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01369   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01370   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01371   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01372   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01373   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01374   * @param  pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
01375   * @note When the timer operates in simple output compare mode:
01376   *         Output 1 is implicitly controlled by the compare unit 1
01377   *         Output 2 is implicitly controlled by the compare unit 2
01378   *       Output Set/Reset crossbar is set according to the selected output compare mode:
01379   *         Toggle: SETxyR = RSTxyR = CMPy
01380   *         Active: SETxyR = CMPy, RSTxyR = 0
01381   *         Inactive: SETxy =0, RSTxy = CMPy
01382   * @retval HAL status
01383   */
01384 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
01385                                                  uint32_t TimerIdx,
01386                                                  uint32_t OCChannel,
01387                                                  const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
01388 {
01389   uint32_t CompareUnit = (uint32_t)RESET;
01390   HRTIM_OutputCfgTypeDef OutputCfg;
01391
01392   /* Check parameters */
01393   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01394   assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
01395   assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
01396   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
01397   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
01398
01399   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01400   {
01401      return HAL_BUSY;
01402   }
01403
01404   /* Process Locked */
01405   __HAL_LOCK(hhrtim);
01406
01407   /* Set HRTIM state */
01408   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01409
01410   /* Configure timer compare unit */
01411   switch (OCChannel)
01412   {
01413   case HRTIM_OUTPUT_TA1:
01414   case HRTIM_OUTPUT_TB1:
01415   case HRTIM_OUTPUT_TC1:
01416   case HRTIM_OUTPUT_TD1:
01417   case HRTIM_OUTPUT_TE1:
01418   case HRTIM_OUTPUT_TF1:
01419     {
01420       CompareUnit = HRTIM_COMPAREUNIT_1;
01421       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
01422       break;
01423     }
01424   case HRTIM_OUTPUT_TA2:
01425   case HRTIM_OUTPUT_TB2:
01426   case HRTIM_OUTPUT_TC2:
01427   case HRTIM_OUTPUT_TD2:
01428   case HRTIM_OUTPUT_TE2:
01429   case HRTIM_OUTPUT_TF2:
01430     {
01431       CompareUnit = HRTIM_COMPAREUNIT_2;
01432       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
01433       break;
01434     }
01435   default:
01436     {
01437       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01438
01439       /* Process Unlocked */
01440       __HAL_UNLOCK(hhrtim);
01441
01442       break;
01443     }
01444   }
01445
01446   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
01447   {
01448      return HAL_ERROR;
01449   }
01450
01451   /* Configure timer output */
01452   OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
01453   OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
01454   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
01455   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
01456   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
01457   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
01458
01459   switch (pSimpleOCChannelCfg->Mode)
01460   {
01461   case HRTIM_BASICOCMODE_TOGGLE:
01462     {
01463       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01464       {
01465         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01466       }
01467       else
01468       {
01469         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01470       }
01471       OutputCfg.ResetSource = OutputCfg.SetSource;
01472       break;
01473     }
01474
01475   case HRTIM_BASICOCMODE_ACTIVE:
01476     {
01477       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01478       {
01479         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
01480       }
01481       else
01482       {
01483         OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
01484       }
01485       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01486       break;
01487     }
01488
01489   case HRTIM_BASICOCMODE_INACTIVE:
01490     {
01491       if (CompareUnit == HRTIM_COMPAREUNIT_1)
01492       {
01493         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
01494       }
01495       else
01496       {
01497         OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
01498       }
01499       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01500       break;
01501     }
01502
01503   default:
01504     {
01505       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
01506       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
01507
01508       hhrtim->State = HAL_HRTIM_STATE_ERROR;
01509
01510       /* Process Unlocked */
01511       __HAL_UNLOCK(hhrtim);
01512
01513       break;
01514     }
01515   }
01516
01517   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
01518   {
01519      return HAL_ERROR;
01520   }
01521
01522   HRTIM_OutputConfig(hhrtim,
01523                      TimerIdx,
01524                      OCChannel,
01525                      &OutputCfg);
01526
01527   /* Set HRTIM state */
01528   hhrtim->State = HAL_HRTIM_STATE_READY;
01529
01530   /* Process Unlocked */
01531   __HAL_UNLOCK(hhrtim);
01532
01533   return HAL_OK;
01534 }
01535
01536 /**
01537   * @brief  Start the output compare signal generation on the designed timer output
01538   * @param  hhrtim pointer to HAL HRTIM handle
01539   * @param  TimerIdx Timer index
01540   *                   This parameter can be one of the following values:
01541   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01542   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01543   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01544   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01545   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01546   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01547   * @param  OCChannel Timer output
01548   *                    This parameter can be one of the following values:
01549   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01550   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01551   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01552   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01553   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01554   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01555   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01556   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01557   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01558   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01559   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01560   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01561   * @retval HAL status
01562   */
01563 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
01564                                          uint32_t TimerIdx,
01565                                          uint32_t OCChannel)
01566 {
01567    /* Check the parameters */
01568   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01569
01570   /* Process Locked */
01571   __HAL_LOCK(hhrtim);
01572
01573   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01574
01575   /* Enable the timer output */
01576   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01577
01578   /* Enable the timer counter */
01579   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01580
01581   hhrtim->State = HAL_HRTIM_STATE_READY;
01582
01583   /* Process Unlocked */
01584   __HAL_UNLOCK(hhrtim);
01585
01586   return HAL_OK;
01587 }
01588
01589 /**
01590   * @brief  Stop the output compare signal generation on the designed timer output
01591   * @param  hhrtim pointer to HAL HRTIM handle
01592   * @param  TimerIdx Timer index
01593   *                   This parameter can be one of the following values:
01594   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01595   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01596   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01597   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01598   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01599   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01600   * @param  OCChannel Timer output
01601   *                    This parameter can be one of the following values:
01602   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01603   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01604   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01605   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01606   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01607   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01608   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01609   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01610   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01611   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01612   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01613   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01614   * @retval HAL status
01615   */
01616 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
01617                                         uint32_t TimerIdx,
01618                                         uint32_t OCChannel)
01619 {
01620    /* Check the parameters */
01621   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01622
01623   /* Process Locked */
01624   __HAL_LOCK(hhrtim);
01625
01626   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01627
01628   /* Disable the timer output */
01629   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01630
01631   /* Disable the timer counter */
01632   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01633
01634   hhrtim->State = HAL_HRTIM_STATE_READY;
01635
01636   /* Process Unlocked */
01637   __HAL_UNLOCK(hhrtim);
01638
01639   return HAL_OK;
01640 }
01641
01642 /**
01643   * @brief  Start the output compare signal generation on the designed timer output
01644   *         (Interrupt is enabled (see note note below)).
01645   * @param  hhrtim pointer to HAL HRTIM handle
01646   * @param  TimerIdx Timer index
01647   *                   This parameter can be one of the following values:
01648   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01649   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01650   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01651   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01652   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01653   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01654   * @param  OCChannel Timer output
01655   *                    This parameter can be one of the following values:
01656   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01657   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01658   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01659   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01660   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01661   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01662   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01663   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01664   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01665   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01666   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01667   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01668   * @note Interrupt enabling depends on the chosen output compare mode
01669   *          Output toggle: compare match interrupt is enabled
01670   *          Output set active:  output set interrupt is enabled
01671   *          Output set inactive:  output reset interrupt is enabled
01672   * @retval HAL status
01673   */
01674 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
01675                                             uint32_t TimerIdx,
01676                                             uint32_t OCChannel)
01677 {
01678   uint32_t interrupt;
01679
01680    /* Check the parameters */
01681   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01682
01683   /* Process Locked */
01684   __HAL_LOCK(hhrtim);
01685
01686   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01687
01688   /* Get the interrupt to enable (depends on the output compare mode) */
01689   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01690
01691   /* Enable the timer output */
01692   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01693
01694   /* Enable the timer interrupt (depends on the output compare mode) */
01695   __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
01696
01697   /* Enable the timer counter */
01698   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01699
01700   hhrtim->State = HAL_HRTIM_STATE_READY;
01701
01702   /* Process Unlocked */
01703   __HAL_UNLOCK(hhrtim);
01704
01705   return HAL_OK;
01706 }
01707
01708 /**
01709   * @brief  Stop the output compare signal generation on the designed timer output
01710   *         (Interrupt is disabled).
01711   * @param  hhrtim pointer to HAL HRTIM handle
01712   * @param  TimerIdx Timer index
01713   *                   This parameter can be one of the following values:
01714   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01715   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01716   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01717   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01718   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01719   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01720   * @param  OCChannel Timer output
01721   *                    This parameter can be one of the following values:
01722   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01723   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01724   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01725   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01726   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01727   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01728   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01729   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01730   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01731   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01732   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01733   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01734   * @retval HAL status
01735   */
01736 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
01737                                            uint32_t TimerIdx,
01738                                            uint32_t OCChannel)
01739 {
01740   uint32_t interrupt;
01741
01742    /* Check the parameters */
01743   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01744
01745   /* Process Locked */
01746   __HAL_LOCK(hhrtim);
01747
01748   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01749
01750   /* Disable the timer output */
01751   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01752
01753   /* Get the interrupt to disable (depends on the output compare mode) */
01754   interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
01755
01756   /* Disable the timer interrupt */
01757   __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
01758
01759   /* Disable the timer counter */
01760   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01761
01762   hhrtim->State = HAL_HRTIM_STATE_READY;
01763
01764   /* Process Unlocked */
01765   __HAL_UNLOCK(hhrtim);
01766
01767   return HAL_OK;
01768 }
01769
01770 /**
01771   * @brief  Start the output compare signal generation on the designed timer output
01772   *         (DMA request is enabled (see note below)).
01773   * @param  hhrtim pointer to HAL HRTIM handle
01774   * @param  TimerIdx Timer index
01775   *                   This parameter can be one of the following values:
01776   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01777   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01778   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01779   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01780   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01781   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01782   * @param  OCChannel Timer output
01783   *                    This parameter can be one of the following values:
01784   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01785   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01786   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01787   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01788   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01789   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01790   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01791   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01792   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01793   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01794   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01795   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01796   * @param  SrcAddr DMA transfer source address
01797   * @param  DestAddr DMA transfer destination address
01798   * @param  Length The length of data items (data size) to be transferred
01799   *                     from source to destination
01800   * @note  DMA request enabling depends on the chosen output compare mode
01801   *          Output toggle: compare match DMA request is enabled
01802   *          Output set active:  output set DMA request is enabled
01803   *          Output set inactive:  output reset DMA request is enabled
01804   * @retval HAL status
01805   */
01806 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
01807                                              uint32_t TimerIdx,
01808                                              uint32_t OCChannel,
01809                                              uint32_t SrcAddr,
01810                                              uint32_t DestAddr,
01811                                              uint32_t Length)
01812 {
01813   DMA_HandleTypeDef * hdma;
01814   uint32_t dma_request;
01815
01816   /* Check the parameters */
01817   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01818
01819   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
01820   {
01821      return HAL_BUSY;
01822   }
01823   if(hhrtim->State == HAL_HRTIM_STATE_READY)
01824   {
01825     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
01826     {
01827       return HAL_ERROR;
01828     }
01829     else
01830     {
01831       hhrtim->State = HAL_HRTIM_STATE_BUSY;
01832     }
01833   }
01834
01835   /* Process Locked */
01836   __HAL_LOCK(hhrtim);
01837
01838    /* Enable the timer output */
01839   hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
01840
01841   /* Get the DMA request to enable */
01842   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01843
01844   /* Get the timer DMA handler */
01845   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
01846
01847   if (hdma == NULL)
01848   {
01849    hhrtim->State = HAL_HRTIM_STATE_ERROR;
01850
01851    /* Process Unlocked */
01852    __HAL_UNLOCK(hhrtim);
01853
01854    return HAL_ERROR;
01855   }
01856
01857   /* Set the DMA error callback */
01858   hdma->XferErrorCallback = HRTIM_DMAError ;
01859
01860   /* Set the DMA transfer completed callback */
01861   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
01862
01863   /* Enable the DMA channel */
01864   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
01865     {
01866         hhrtim->State = HAL_HRTIM_STATE_ERROR;
01867
01868         /* Process Unlocked */
01869         __HAL_UNLOCK(hhrtim);
01870
01871         return HAL_ERROR;
01872     }
01873
01874   /* Enable the timer DMA request */
01875   __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
01876
01877   /* Enable the timer counter */
01878   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01879
01880   hhrtim->State = HAL_HRTIM_STATE_READY;
01881
01882   /* Process Unlocked */
01883   __HAL_UNLOCK(hhrtim);
01884
01885   return HAL_OK;
01886 }
01887
01888 /**
01889   * @brief  Stop the output compare signal generation on the designed timer output
01890   *         (DMA request is disabled).
01891   * @param  hhrtim pointer to HAL HRTIM handle
01892   * @param  TimerIdx Timer index
01893   *                   This parameter can be one of the following values:
01894   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01895   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01896   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01897   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
01898   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
01899   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
01900   * @param  OCChannel Timer output
01901   *                    This parameter can be one of the following values:
01902   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
01903   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
01904   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
01905   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
01906   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
01907   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
01908   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
01909   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
01910   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
01911   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
01912   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
01913   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
01914   * @retval HAL status
01915   */
01916 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
01917                                             uint32_t TimerIdx,
01918                                             uint32_t OCChannel)
01919 {
01920   uint32_t dma_request;
01921
01922   /* Check the parameters */
01923   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
01924
01925   /* Process Locked */
01926   __HAL_LOCK(hhrtim);
01927
01928   hhrtim->State = HAL_HRTIM_STATE_BUSY;
01929
01930   /* Disable the timer output */
01931   hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
01932
01933   /* Get the timer DMA handler */
01934   /* Disable the DMA */
01935   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
01936   {
01937     hhrtim->State = HAL_HRTIM_STATE_ERROR;
01938
01939     /* Process Unlocked */
01940     __HAL_UNLOCK(hhrtim);
01941
01942     return HAL_ERROR;
01943   }
01944
01945   /* Get the DMA request to disable */
01946   dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
01947
01948   /* Disable the timer DMA request */
01949   __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
01950
01951   /* Disable the timer counter */
01952   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
01953
01954   hhrtim->State = HAL_HRTIM_STATE_READY;
01955
01956   /* Process Unlocked */
01957   __HAL_UNLOCK(hhrtim);
01958
01959   return HAL_OK;
01960 }
01961
01962 /**
01963   * @}
01964   */
01965
01966 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
01967  *  @brief    Simple PWM output functions
01968 @verbatim
01969  ===============================================================================
01970               ##### Simple PWM output functions #####
01971  ===============================================================================
01972     [..]  This section provides functions allowing to:
01973       (+) Configure simple PWM output channel
01974       (+) Start simple PWM output
01975       (+) Stop simple PWM output
01976       (+) Start simple PWM output and enable interrupt
01977       (+) Stop simple PWM output and disable interrupt
01978       (+) Start simple PWM output and enable DMA transfer
01979       (+) Stop simple PWM output and disable DMA transfer
01980       -@- When a HRTIM timer operates in simple PWM output mode
01981           the output level is set to a programmable value when a match is
01982           found between the compare register and the counter and reset when
01983           the timer period is reached. Duty cycle is determined by the
01984           comparison value.
01985           Compare unit 1 is automatically associated to output 1
01986           Compare unit 2 is automatically associated to output 2
01987 @endverbatim
01988   * @{
01989   */
01990
01991 /**
01992   * @brief  Configure an output in simple PWM mode
01993   * @param  hhrtim pointer to HAL HRTIM handle
01994   * @param  TimerIdx Timer index
01995   *                   This parameter can be one of the following values:
01996   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
01997   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
01998   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
01999   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02000   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02001   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02002   * @param  PWMChannel Timer output
02003   *                    This parameter can be one of the following values:
02004   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02005   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02006   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02007   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02008   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02009   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02010   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02011   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02012   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02013   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02014   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02015   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02016   * @param  pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
02017   * @note When the timer operates in simple PWM output mode:
02018   *         Output 1 is implicitly controlled by the compare unit 1
02019   *         Output 2 is implicitly controlled by the compare unit 2
02020   *       Output Set/Reset crossbar is set as follows:
02021   *         Output 1: SETx1R = CMP1, RSTx1R = PER
02022   *         Output 2: SETx2R = CMP2, RST2R = PER
02023   * @note When Simple PWM mode is used the registers preload mechanism is
02024   *       enabled (otherwise the behavior is not guaranteed).
02025   * @retval HAL status
02026   */
02027 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02028                                                   uint32_t TimerIdx,
02029                                                   uint32_t PWMChannel,
02030                                                   const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
02031 {
02032   HRTIM_OutputCfgTypeDef OutputCfg;
02033   uint32_t hrtim_timcr;
02034
02035   /* Check parameters */
02036   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02037   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
02038   assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
02039   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
02040
02041   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02042   {
02043      return HAL_BUSY;
02044   }
02045
02046   /* Process Locked */
02047   __HAL_LOCK(hhrtim);
02048
02049   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02050
02051   /* Configure timer compare unit */
02052   switch (PWMChannel)
02053   {
02054   case HRTIM_OUTPUT_TA1:
02055   case HRTIM_OUTPUT_TB1:
02056   case HRTIM_OUTPUT_TC1:
02057   case HRTIM_OUTPUT_TD1:
02058   case HRTIM_OUTPUT_TE1:
02059   case HRTIM_OUTPUT_TF1:
02060     {
02061       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
02062       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
02063       break;
02064     }
02065
02066   case HRTIM_OUTPUT_TA2:
02067   case HRTIM_OUTPUT_TB2:
02068   case HRTIM_OUTPUT_TC2:
02069   case HRTIM_OUTPUT_TD2:
02070   case HRTIM_OUTPUT_TE2:
02071   case HRTIM_OUTPUT_TF2:
02072     {
02073       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
02074       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
02075       break;
02076     }
02077   default:
02078     {
02079       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
02080       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
02081
02082       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02083
02084       /* Process Unlocked */
02085       __HAL_UNLOCK(hhrtim);
02086
02087       break;
02088     }
02089   }
02090
02091   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02092   {
02093      return HAL_ERROR;
02094   }
02095
02096   /* Configure timer output */
02097   OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
02098   OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
02099   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
02100   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
02101   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
02102   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
02103   OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
02104
02105   HRTIM_OutputConfig(hhrtim,
02106                      TimerIdx,
02107                      PWMChannel,
02108                      &OutputCfg);
02109
02110   /* Enable the registers preload mechanism */
02111   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
02112   hrtim_timcr |= HRTIM_TIMCR_PREEN;
02113   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
02114
02115   hhrtim->State = HAL_HRTIM_STATE_READY;
02116
02117   /* Process Unlocked */
02118   __HAL_UNLOCK(hhrtim);
02119
02120   return HAL_OK;
02121 }
02122
02123 /**
02124   * @brief  Start the PWM output signal generation on the designed timer output
02125   * @param  hhrtim pointer to HAL HRTIM handle
02126   * @param  TimerIdx Timer index
02127   *                   This parameter can be one of the following values:
02128   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02129   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02130   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02131   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02132   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02133   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02134   * @param  PWMChannel Timer output
02135   *                    This parameter can be one of the following values:
02136   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02137   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02138   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02139   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02140   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02141   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02142   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02143   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02144   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02145   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02146   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02147   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02148   * @retval HAL status
02149   */
02150 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
02151                                           uint32_t TimerIdx,
02152                                           uint32_t PWMChannel)
02153 {
02154    /* Check the parameters */
02155   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02156
02157   /* Process Locked */
02158   __HAL_LOCK(hhrtim);
02159
02160   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02161
02162   /* Enable the timer output */
02163   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02164
02165   /* Enable the timer counter */
02166   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02167
02168   hhrtim->State = HAL_HRTIM_STATE_READY;
02169
02170   /* Process Unlocked */
02171   __HAL_UNLOCK(hhrtim);
02172
02173   return HAL_OK;
02174 }
02175
02176 /**
02177   * @brief  Stop the PWM output signal generation on the designed timer output
02178   * @param  hhrtim pointer to HAL HRTIM handle
02179   * @param  TimerIdx Timer index
02180   *                   This parameter can be one of the following values:
02181   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02182   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02183   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02184   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02185   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02186   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02187   * @param  PWMChannel Timer output
02188   *                    This parameter can be one of the following values:
02189   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02190   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02191   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02192   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02193   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02194   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02195   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02196   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02197   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02198   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02199   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02200   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02201   * @retval HAL status
02202   */
02203 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
02204                                          uint32_t TimerIdx,
02205                                          uint32_t PWMChannel)
02206 {
02207    /* Check the parameters */
02208   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02209
02210   /* Process Locked */
02211   __HAL_LOCK(hhrtim);
02212
02213   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02214
02215   /* Disable the timer output */
02216   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02217
02218   /* Disable the timer counter */
02219   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02220
02221   hhrtim->State = HAL_HRTIM_STATE_READY;
02222
02223   /* Process Unlocked */
02224   __HAL_UNLOCK(hhrtim);
02225
02226   return HAL_OK;
02227 }
02228
02229 /**
02230   * @brief  Start the PWM output signal generation on the designed timer output
02231   *         (The compare interrupt is enabled).
02232   * @param  hhrtim pointer to HAL HRTIM handle
02233   * @param  TimerIdx Timer index
02234   *                   This parameter can be one of the following values:
02235   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02236   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02237   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02238   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02239   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02240   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02241   * @param  PWMChannel Timer output
02242   *                    This parameter can be one of the following values:
02243   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02244   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02245   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02246   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02247   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02248   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02249   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02250   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02251   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02252   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02253   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02254   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02255   * @retval HAL status
02256   */
02257 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
02258                                              uint32_t TimerIdx,
02259                                              uint32_t PWMChannel)
02260 {
02261    /* Check the parameters */
02262   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02263
02264   /* Process Locked */
02265   __HAL_LOCK(hhrtim);
02266
02267   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02268
02269   /* Enable the timer output */
02270   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02271
02272   /* Enable the timer interrupt (depends on the PWM output) */
02273   switch (PWMChannel)
02274   {
02275   case HRTIM_OUTPUT_TA1:
02276   case HRTIM_OUTPUT_TB1:
02277   case HRTIM_OUTPUT_TC1:
02278   case HRTIM_OUTPUT_TD1:
02279   case HRTIM_OUTPUT_TE1:
02280   case HRTIM_OUTPUT_TF1:
02281     {
02282       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02283       break;
02284     }
02285
02286   case HRTIM_OUTPUT_TA2:
02287   case HRTIM_OUTPUT_TB2:
02288   case HRTIM_OUTPUT_TC2:
02289   case HRTIM_OUTPUT_TD2:
02290   case HRTIM_OUTPUT_TE2:
02291   case HRTIM_OUTPUT_TF2:
02292     {
02293       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02294       break;
02295     }
02296
02297   default:
02298     {
02299       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02300
02301       /* Process Unlocked */
02302       __HAL_UNLOCK(hhrtim);
02303
02304       break;
02305     }
02306   }
02307
02308   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02309   {
02310      return HAL_ERROR;
02311   }
02312
02313   /* Enable the timer counter */
02314   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02315
02316   hhrtim->State = HAL_HRTIM_STATE_READY;
02317
02318   /* Process Unlocked */
02319   __HAL_UNLOCK(hhrtim);
02320
02321   return HAL_OK;
02322 }
02323
02324 /**
02325   * @brief  Stop the PWM output signal generation on the designed timer output
02326   *         (The compare interrupt is disabled).
02327   * @param  hhrtim pointer to HAL HRTIM handle
02328   * @param  TimerIdx Timer index
02329   *                   This parameter can be one of the following values:
02330   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02331   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02332   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02333   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02334   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02335   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02336   * @param  PWMChannel Timer output
02337   *                    This parameter can be one of the following values:
02338   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02339   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02340   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02341   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02342   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02343   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02344   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02345   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02346   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02347   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02348   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02349   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02350   * @retval HAL status
02351   */
02352 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
02353                                             uint32_t TimerIdx,
02354                                             uint32_t PWMChannel)
02355 {
02356    /* Check the parameters */
02357   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02358
02359   /* Process Locked */
02360   __HAL_LOCK(hhrtim);
02361
02362   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02363
02364   /* Disable the timer output */
02365   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02366
02367   /* Disable the timer interrupt (depends on the PWM output) */
02368   switch (PWMChannel)
02369   {
02370   case HRTIM_OUTPUT_TA1:
02371   case HRTIM_OUTPUT_TB1:
02372   case HRTIM_OUTPUT_TC1:
02373   case HRTIM_OUTPUT_TD1:
02374   case HRTIM_OUTPUT_TE1:
02375   case HRTIM_OUTPUT_TF1:
02376     {
02377       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
02378       break;
02379     }
02380
02381   case HRTIM_OUTPUT_TA2:
02382   case HRTIM_OUTPUT_TB2:
02383   case HRTIM_OUTPUT_TC2:
02384   case HRTIM_OUTPUT_TD2:
02385   case HRTIM_OUTPUT_TE2:
02386   case HRTIM_OUTPUT_TF2:
02387     {
02388       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
02389       break;
02390     }
02391
02392   default:
02393     {
02394       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02395
02396       /* Process Unlocked */
02397       __HAL_UNLOCK(hhrtim);
02398
02399       break;
02400     }
02401   }
02402
02403   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02404   {
02405      return HAL_ERROR;
02406   }
02407
02408   /* Disable the timer counter */
02409   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02410
02411   hhrtim->State = HAL_HRTIM_STATE_READY;
02412
02413   /* Process Unlocked */
02414   __HAL_UNLOCK(hhrtim);
02415
02416   return HAL_OK;
02417 }
02418
02419 /**
02420   * @brief  Start the PWM output signal generation on the designed timer output
02421   *         (The compare DMA request is enabled).
02422   * @param  hhrtim pointer to HAL HRTIM handle
02423   * @param  TimerIdx Timer index
02424   *                   This parameter can be one of the following values:
02425   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02426   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02427   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02428   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02429   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02430   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02431   * @param  PWMChannel Timer output
02432   *                    This parameter can be one of the following values:
02433   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02434   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02435   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02436   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02437   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02438   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02439   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02440   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02441   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02442   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02443   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02444   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02445   * @param  SrcAddr DMA transfer source address
02446   * @param  DestAddr DMA transfer destination address
02447   * @param  Length The length of data items (data size) to be transferred
02448   *                     from source to destination
02449   * @retval HAL status
02450   */
02451 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
02452                                               uint32_t TimerIdx,
02453                                               uint32_t PWMChannel,
02454                                               uint32_t SrcAddr,
02455                                               uint32_t DestAddr,
02456                                               uint32_t Length)
02457 {
02458   DMA_HandleTypeDef * hdma;
02459
02460   /* Check the parameters */
02461   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02462
02463   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02464   {
02465      return HAL_BUSY;
02466   }
02467   if(hhrtim->State == HAL_HRTIM_STATE_READY)
02468   {
02469     if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
02470     {
02471       return HAL_ERROR;
02472     }
02473     else
02474     {
02475       hhrtim->State = HAL_HRTIM_STATE_BUSY;
02476     }
02477   }
02478
02479   /* Process Locked */
02480   __HAL_LOCK(hhrtim);
02481
02482   /* Enable the timer output */
02483   hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
02484
02485   /* Get the timer DMA handler */
02486   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
02487
02488   if (hdma == NULL)
02489   {
02490     hhrtim->State = HAL_HRTIM_STATE_ERROR;
02491
02492     /* Process Unlocked */
02493     __HAL_UNLOCK(hhrtim);
02494
02495     return HAL_ERROR;
02496   }
02497
02498   /* Set the DMA error callback */
02499   hdma->XferErrorCallback = HRTIM_DMAError ;
02500
02501   /* Set the DMA transfer completed callback */
02502   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
02503
02504   /* Enable the DMA channel */
02505   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
02506     {
02507         hhrtim->State = HAL_HRTIM_STATE_ERROR;
02508
02509         /* Process Unlocked */
02510         __HAL_UNLOCK(hhrtim);
02511
02512         return HAL_ERROR;
02513     }
02514
02515   /* Enable the timer DMA request */
02516   switch (PWMChannel)
02517   {
02518   case HRTIM_OUTPUT_TA1:
02519   case HRTIM_OUTPUT_TB1:
02520   case HRTIM_OUTPUT_TC1:
02521   case HRTIM_OUTPUT_TD1:
02522   case HRTIM_OUTPUT_TE1:
02523   case HRTIM_OUTPUT_TF1:
02524     {
02525       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02526       break;
02527     }
02528
02529   case HRTIM_OUTPUT_TA2:
02530   case HRTIM_OUTPUT_TB2:
02531   case HRTIM_OUTPUT_TC2:
02532   case HRTIM_OUTPUT_TD2:
02533   case HRTIM_OUTPUT_TE2:
02534   case HRTIM_OUTPUT_TF2:
02535     {
02536       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02537       break;
02538     }
02539
02540   default:
02541     {
02542       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02543
02544       /* Process Unlocked */
02545       __HAL_UNLOCK(hhrtim);
02546
02547       break;
02548     }
02549   }
02550
02551   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02552   {
02553      return HAL_ERROR;
02554   }
02555
02556   /* Enable the timer counter */
02557   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02558
02559   hhrtim->State = HAL_HRTIM_STATE_READY;
02560
02561   /* Process Unlocked */
02562   __HAL_UNLOCK(hhrtim);
02563
02564   return HAL_OK;
02565 }
02566
02567 /**
02568   * @brief  Stop the PWM output signal generation on the designed timer output
02569   *         (The compare DMA request is disabled).
02570   * @param  hhrtim pointer to HAL HRTIM handle
02571   * @param  TimerIdx Timer index
02572   *                   This parameter can be one of the following values:
02573   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02574   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02575   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02576   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02577   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02578   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02579   * @param  PWMChannel Timer output
02580   *                    This parameter can be one of the following values:
02581   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
02582   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
02583   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
02584   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
02585   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
02586   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
02587   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
02588   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
02589   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
02590   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
02591   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
02592   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
02593   * @retval HAL status
02594   */
02595 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
02596                                              uint32_t TimerIdx,
02597                                              uint32_t PWMChannel)
02598 {
02599   /* Check the parameters */
02600   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
02601
02602   /* Process Locked */
02603   __HAL_LOCK(hhrtim);
02604
02605   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02606
02607   /* Disable the timer output */
02608   hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
02609
02610   /* Get the timer DMA handler */
02611   /* Disable the DMA */
02612   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
02613   {
02614     hhrtim->State = HAL_HRTIM_STATE_ERROR;
02615
02616     /* Process Unlocked */
02617     __HAL_UNLOCK(hhrtim);
02618
02619     return HAL_ERROR;
02620   }
02621
02622   /* Disable the timer DMA request */
02623   switch (PWMChannel)
02624   {
02625   case HRTIM_OUTPUT_TA1:
02626   case HRTIM_OUTPUT_TB1:
02627   case HRTIM_OUTPUT_TC1:
02628   case HRTIM_OUTPUT_TD1:
02629   case HRTIM_OUTPUT_TE1:
02630   case HRTIM_OUTPUT_TF1:
02631     {
02632       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
02633       break;
02634     }
02635
02636   case HRTIM_OUTPUT_TA2:
02637   case HRTIM_OUTPUT_TB2:
02638   case HRTIM_OUTPUT_TC2:
02639   case HRTIM_OUTPUT_TD2:
02640   case HRTIM_OUTPUT_TE2:
02641   case HRTIM_OUTPUT_TF2:
02642     {
02643       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
02644       break;
02645     }
02646
02647   default:
02648     {
02649       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02650
02651       /* Process Unlocked */
02652       __HAL_UNLOCK(hhrtim);
02653
02654       break;
02655     }
02656   }
02657
02658   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02659   {
02660      return HAL_ERROR;
02661   }
02662
02663   /* Disable the timer counter */
02664   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02665
02666   hhrtim->State = HAL_HRTIM_STATE_READY;
02667
02668   /* Process Unlocked */
02669   __HAL_UNLOCK(hhrtim);
02670
02671   return HAL_OK;
02672 }
02673
02674 /**
02675   * @}
02676   */
02677
02678 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
02679  *  @brief    Simple input capture functions
02680 @verbatim
02681  ===============================================================================
02682               ##### Simple input capture functions #####
02683  ===============================================================================
02684     [..]  This section provides functions allowing to:
02685       (+) Configure simple input capture channel
02686       (+) Start simple input capture
02687       (+) Stop simple input capture
02688       (+) Start simple input capture and enable interrupt
02689       (+) Stop simple input capture and disable interrupt
02690       (+) Start simple input capture and enable DMA transfer
02691       (+) Stop simple input capture and disable DMA transfer
02692       -@- When a HRTIM timer operates in simple input capture mode
02693           the Capture Register (HRTIM_CPT1/2xR) is used to latch the
02694          value of the timer counter counter after a transition detected
02695          on a given external event input.
02696 @endverbatim
02697   * @{
02698   */
02699
02700 /**
02701   * @brief  Configure a simple capture
02702   * @param  hhrtim pointer to HAL HRTIM handle
02703   * @param  TimerIdx Timer index
02704   *                   This parameter can be one of the following values:
02705   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02706   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02707   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02708   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02709   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02710   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02711   * @param  CaptureChannel Capture unit
02712   *                    This parameter can be one of the following values:
02713   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02714   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02715   * @param  pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
02716   * @note When the timer operates in simple capture mode the capture is triggered
02717   *       by the designated external event and GPIO input is implicitly used as event source.
02718   *       The cature can be triggered by a rising edge, a falling edge or both
02719   *       edges on event channel.
02720   * @retval HAL status
02721   */
02722 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
02723                                                       uint32_t TimerIdx,
02724                                                       uint32_t CaptureChannel,
02725                                                       const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
02726 {
02727   HRTIM_EventCfgTypeDef EventCfg;
02728
02729   /* Check parameters */
02730   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02731   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02732   assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
02733   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
02734                                       pSimpleCaptureChannelCfg->EventPolarity));
02735   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
02736   assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
02737                                     pSimpleCaptureChannelCfg->EventFilter));
02738
02739   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
02740   {
02741      return HAL_BUSY;
02742   }
02743
02744   /* Process Locked */
02745   __HAL_LOCK(hhrtim);
02746
02747   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02748
02749   /* Configure external event channel */
02750   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
02751   EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
02752   EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
02753   EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
02754   EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
02755
02756   HRTIM_EventConfig(hhrtim,
02757                     pSimpleCaptureChannelCfg->Event,
02758                     &EventCfg);
02759
02760   /* Memorize capture trigger (will be configured when the capture is started */
02761   HRTIM_CaptureUnitConfig(hhrtim,
02762                           TimerIdx,
02763                           CaptureChannel,
02764                           pSimpleCaptureChannelCfg->Event);
02765
02766   hhrtim->State = HAL_HRTIM_STATE_READY;
02767
02768   /* Process Unlocked */
02769   __HAL_UNLOCK(hhrtim);
02770
02771   return HAL_OK;
02772 }
02773
02774 /**
02775   * @brief  Enable a simple capture on the designed capture unit
02776   * @param  hhrtim pointer to HAL HRTIM handle
02777   * @param  TimerIdx Timer index
02778   *                   This parameter can be one of the following values:
02779   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02780   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02781   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02782   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02783   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02784   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02785   * @param  CaptureChannel Timer output
02786   *                    This parameter can be one of the following values:
02787   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02788   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02789   * @retval HAL status
02790   * @note  The external event triggering the capture is available for all timing
02791   *        units. It can be used directly and is active as soon as the timing
02792   *        unit counter is enabled.
02793   */
02794 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
02795                                               uint32_t TimerIdx,
02796                                               uint32_t CaptureChannel)
02797 {
02798    /* Check the parameters */
02799   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02800   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02801
02802   /* Process Locked */
02803   __HAL_LOCK(hhrtim);
02804
02805   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02806
02807   /* Set the capture unit trigger */
02808   switch (CaptureChannel)
02809   {
02810   case HRTIM_CAPTUREUNIT_1:
02811     {
02812       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02813       break;
02814     }
02815
02816   case HRTIM_CAPTUREUNIT_2:
02817     {
02818       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02819       break;
02820     }
02821
02822   default:
02823     {
02824       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02825
02826       /* Process Unlocked */
02827       __HAL_UNLOCK(hhrtim);
02828
02829       break;
02830     }
02831   }
02832
02833   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02834   {
02835      return HAL_ERROR;
02836   }
02837
02838   /* Enable the timer counter */
02839   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02840
02841   hhrtim->State = HAL_HRTIM_STATE_READY;
02842
02843   /* Process Unlocked */
02844   __HAL_UNLOCK(hhrtim);
02845
02846   return HAL_OK;
02847 }
02848
02849 /**
02850   * @brief  Disable a simple capture on the designed capture unit
02851   * @param  hhrtim pointer to HAL HRTIM handle
02852   * @param  TimerIdx Timer index
02853   *                   This parameter can be one of the following values:
02854   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02855   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02856   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02857   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02858   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02859   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02860   * @param  CaptureChannel Timer output
02861   *                    This parameter can be one of the following values:
02862   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02863   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02864   * @retval HAL status
02865   */
02866 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
02867                                              uint32_t TimerIdx,
02868                                              uint32_t CaptureChannel)
02869 {
02870   uint32_t hrtim_cpt1cr;
02871   uint32_t hrtim_cpt2cr;
02872
02873    /* Check the parameters */
02874   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02875   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02876
02877   /* Process Locked */
02878   __HAL_LOCK(hhrtim);
02879
02880   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02881
02882   /* Set the capture unit trigger */
02883   switch (CaptureChannel)
02884   {
02885   case HRTIM_CAPTUREUNIT_1:
02886     {
02887       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
02888       break;
02889     }
02890
02891   case HRTIM_CAPTUREUNIT_2:
02892     {
02893       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
02894       break;
02895     }
02896
02897   default:
02898     {
02899       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02900
02901       /* Process Unlocked */
02902       __HAL_UNLOCK(hhrtim);
02903
02904       break;
02905     }
02906   }
02907
02908   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02909   {
02910      return HAL_ERROR;
02911   }
02912
02913   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
02914   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
02915
02916   /* Disable the timer counter */
02917   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
02918       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
02919   {
02920     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
02921   }
02922
02923   hhrtim->State = HAL_HRTIM_STATE_READY;
02924
02925   /* Process Unlocked */
02926   __HAL_UNLOCK(hhrtim);
02927
02928   return HAL_OK;
02929 }
02930
02931 /**
02932   * @brief  Enable a simple capture on the designed capture unit
02933   *         (Capture interrupt is enabled).
02934   * @param  hhrtim pointer to HAL HRTIM handle
02935   * @param  TimerIdx Timer index
02936   *                   This parameter can be one of the following values:
02937   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
02938   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
02939   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
02940   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
02941   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
02942   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
02943   * @param  CaptureChannel Timer output
02944   *                    This parameter can be one of the following values:
02945   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
02946   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
02947   * @retval HAL status
02948   */
02949 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
02950                                                  uint32_t TimerIdx,
02951                                                  uint32_t CaptureChannel)
02952 {
02953    /* Check the parameters */
02954   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
02955   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
02956
02957   /* Process Locked */
02958   __HAL_LOCK(hhrtim);
02959
02960   hhrtim->State = HAL_HRTIM_STATE_BUSY;
02961
02962   /* Set the capture unit trigger */
02963   switch (CaptureChannel)
02964   {
02965   case HRTIM_CAPTUREUNIT_1:
02966     {
02967       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
02968
02969       /* Enable the capture unit 1 interrupt */
02970       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
02971       break;
02972     }
02973
02974   case HRTIM_CAPTUREUNIT_2:
02975     {
02976       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
02977
02978       /* Enable the capture unit 2 interrupt */
02979       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
02980       break;
02981     }
02982
02983   default:
02984     {
02985       hhrtim->State = HAL_HRTIM_STATE_ERROR;
02986
02987       /* Process Unlocked */
02988       __HAL_UNLOCK(hhrtim);
02989
02990       break;
02991     }
02992   }
02993
02994   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
02995   {
02996      return HAL_ERROR;
02997   }
02998
02999   /* Enable the timer counter */
03000   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03001
03002   hhrtim->State = HAL_HRTIM_STATE_READY;
03003
03004   /* Process Unlocked */
03005   __HAL_UNLOCK(hhrtim);
03006
03007   return HAL_OK;
03008 }
03009
03010 /**
03011   * @brief  Disable a simple capture on the designed capture unit
03012   *         (Capture interrupt is disabled).
03013   * @param  hhrtim pointer to HAL HRTIM handle
03014   * @param  TimerIdx Timer index
03015   *                   This parameter can be one of the following values:
03016   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03017   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03018   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03019   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03020   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03021   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03022   * @param  CaptureChannel Timer output
03023   *                    This parameter can be one of the following values:
03024   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
03025   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
03026   * @retval HAL status
03027   */
03028 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
03029                                                 uint32_t TimerIdx,
03030                                                 uint32_t CaptureChannel)
03031 {
03032
03033   uint32_t hrtim_cpt1cr;
03034   uint32_t hrtim_cpt2cr;
03035
03036    /* Check the parameters */
03037   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03038   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
03039
03040   /* Process Locked */
03041   __HAL_LOCK(hhrtim);
03042
03043   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03044
03045   /* Set the capture unit trigger */
03046   switch (CaptureChannel)
03047   {
03048   case HRTIM_CAPTUREUNIT_1:
03049     {
03050       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
03051
03052       /* Disable the capture unit 1 interrupt */
03053       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
03054       break;
03055     }
03056
03057   case HRTIM_CAPTUREUNIT_2:
03058     {
03059       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
03060
03061       /* Disable the capture unit 2 interrupt */
03062       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
03063       break;
03064     }
03065
03066   default:
03067     {
03068       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03069
03070       /* Process Unlocked */
03071       __HAL_UNLOCK(hhrtim);
03072
03073       break;
03074     }
03075   }
03076
03077   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03078   {
03079      return HAL_ERROR;
03080   }
03081
03082   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
03083   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
03084
03085   /* Disable the timer counter */
03086   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
03087       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
03088   {
03089     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03090   }
03091
03092   hhrtim->State = HAL_HRTIM_STATE_READY;
03093
03094   /* Process Unlocked */
03095   __HAL_UNLOCK(hhrtim);
03096
03097   return HAL_OK;
03098 }
03099
03100 /**
03101   * @brief  Enable a simple capture on the designed capture unit
03102   *         (Capture DMA request is enabled).
03103   * @param  hhrtim pointer to HAL HRTIM handle
03104   * @param  TimerIdx Timer index
03105   *                   This parameter can be one of the following values:
03106   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03107   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03108   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03109   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03110   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03111   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03112   * @param  CaptureChannel Timer output
03113   *                    This parameter can be one of the following values:
03114   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
03115   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
03116   * @param  SrcAddr DMA transfer source address
03117   * @param  DestAddr DMA transfer destination address
03118   * @param  Length The length of data items (data size) to be transferred
03119   *                     from source to destination
03120   * @retval HAL status
03121   */
03122 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
03123                                                   uint32_t TimerIdx,
03124                                                   uint32_t CaptureChannel,
03125                                                   uint32_t SrcAddr,
03126                                                   uint32_t DestAddr,
03127                                                   uint32_t Length)
03128 {
03129   DMA_HandleTypeDef * hdma;
03130
03131    /* Check the parameters */
03132   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03133   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
03134
03135   /* Process Locked */
03136   __HAL_LOCK(hhrtim);
03137
03138   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03139
03140   /* Get the timer DMA handler */
03141   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
03142
03143   if (hdma == NULL)
03144   {
03145    hhrtim->State = HAL_HRTIM_STATE_ERROR;
03146
03147    /* Process Unlocked */
03148    __HAL_UNLOCK(hhrtim);
03149
03150    return HAL_ERROR;
03151   }
03152
03153   /* Set the DMA error callback */
03154   hdma->XferErrorCallback = HRTIM_DMAError ;
03155
03156   /* Set the DMA transfer completed callback */
03157   hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
03158
03159   /* Enable the DMA channel */
03160   if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
03161     {
03162         hhrtim->State = HAL_HRTIM_STATE_ERROR;
03163
03164         /* Process Unlocked */
03165         __HAL_UNLOCK(hhrtim);
03166
03167         return HAL_ERROR;
03168     }
03169
03170   switch (CaptureChannel)
03171   {
03172   case HRTIM_CAPTUREUNIT_1:
03173     {
03174       /* Set the capture unit trigger */
03175       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
03176
03177       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
03178       break;
03179     }
03180
03181   case HRTIM_CAPTUREUNIT_2:
03182     {
03183       /* Set the capture unit trigger */
03184       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
03185
03186       /* Enable the timer DMA request */
03187       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
03188       break;
03189     }
03190
03191   default:
03192     {
03193       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03194
03195       /* Process Unlocked */
03196       __HAL_UNLOCK(hhrtim);
03197
03198       break;
03199     }
03200  }
03201
03202  if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03203   {
03204      return HAL_ERROR;
03205   }
03206
03207   /* Enable the timer counter */
03208   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03209
03210   hhrtim->State = HAL_HRTIM_STATE_READY;
03211
03212   /* Process Unlocked */
03213   __HAL_UNLOCK(hhrtim);
03214
03215   return HAL_OK;
03216 }
03217
03218 /**
03219   * @brief  Disable a simple capture on the designed capture unit
03220   *         (Capture DMA request is disabled).
03221   * @param  hhrtim pointer to HAL HRTIM handle
03222   * @param  TimerIdx Timer index
03223   *                   This parameter can be one of the following values:
03224   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03225   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03226   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03227   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03228   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03229   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03230   * @param  CaptureChannel Timer output
03231   *                    This parameter can be one of the following values:
03232   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
03233   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
03234   * @retval HAL status
03235   */
03236 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
03237                                                  uint32_t TimerIdx,
03238                                                  uint32_t CaptureChannel)
03239 {
03240
03241   uint32_t hrtim_cpt1cr;
03242   uint32_t hrtim_cpt2cr;
03243
03244   /* Check the parameters */
03245   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
03246   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
03247
03248   /* Process Locked */
03249   __HAL_LOCK(hhrtim);
03250
03251   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03252
03253   /* Get the timer DMA handler */
03254   /* Disable the DMA */
03255   if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
03256   {
03257         hhrtim->State = HAL_HRTIM_STATE_ERROR;
03258
03259         /* Process Unlocked */
03260         __HAL_UNLOCK(hhrtim);
03261
03262         return HAL_ERROR;
03263   }
03264
03265   switch (CaptureChannel)
03266   {
03267   case HRTIM_CAPTUREUNIT_1:
03268     {
03269       /* Reset the capture unit trigger */
03270       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
03271
03272       /* Disable the capture unit 1 DMA request */
03273       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
03274       break;
03275     }
03276
03277   case HRTIM_CAPTUREUNIT_2:
03278     {
03279       /* Reset the capture unit trigger */
03280       hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
03281
03282       /* Disable the capture unit 2 DMA request */
03283       __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
03284       break;
03285     }
03286
03287   default:
03288     {
03289       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03290
03291       /* Process Unlocked */
03292       __HAL_UNLOCK(hhrtim);
03293
03294       break;
03295     }
03296   }
03297
03298   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03299   {
03300      return HAL_ERROR;
03301   }
03302
03303   hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
03304   hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
03305
03306   /* Disable the timer counter */
03307   if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
03308       (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
03309   {
03310     __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03311   }
03312
03313   hhrtim->State = HAL_HRTIM_STATE_READY;
03314
03315   /* Process Unlocked */
03316   __HAL_UNLOCK(hhrtim);
03317
03318   return HAL_OK;
03319 }
03320
03321 /**
03322   * @}
03323   */
03324
03325 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
03326  *  @brief    Simple one pulse functions
03327 @verbatim
03328  ===============================================================================
03329               ##### Simple one pulse functions #####
03330  ===============================================================================
03331     [..]  This section provides functions allowing to:
03332       (+) Configure one pulse channel
03333       (+) Start one pulse generation
03334       (+) Stop one pulse generation
03335       (+) Start one pulse generation and enable interrupt
03336       (+) Stop one pulse generation and disable interrupt
03337       -@- When a HRTIM timer operates in simple one pulse mode
03338           the timer counter is started in response to transition detected
03339           on a given external event input to generate a pulse with a
03340           programmable length after a programmable delay.
03341 @endverbatim
03342   * @{
03343   */
03344
03345 /**
03346   * @brief  Configure an output simple one pulse mode
03347   * @param  hhrtim pointer to HAL HRTIM handle
03348   * @param  TimerIdx Timer index
03349   *                   This parameter can be one of the following values:
03350   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03351   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03352   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03353   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03354   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03355   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03356   * @param  OnePulseChannel Timer output
03357   *                    This parameter can be one of the following values:
03358   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03359   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03360   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03361   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03362   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03363   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03364   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03365   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03366   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03367   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03368   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
03369   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
03370   * @param  pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
03371   * @note When the timer operates in simple one pulse mode:
03372   *         the timer counter is implicitly started by the reset event,
03373   *         the reset of the timer counter is triggered by the designated external event
03374   *         GPIO input is implicitly used as event source,
03375   *         Output 1 is implicitly controlled by the compare unit 1,
03376   *         Output 2 is implicitly controlled by the compare unit 2.
03377   *       Output Set/Reset crossbar is set as follows:
03378   *         Output 1: SETx1R = CMP1, RSTx1R = PER
03379   *         Output 2: SETx2R = CMP2, RST2R = PER
03380   * @retval HAL status
03381   * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
03382   *       outputs, the reset event related configuration data provided in the
03383   *       second call will override the reset event related configuration data
03384   *       provided in the first call.
03385   */
03386 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
03387                                                        uint32_t TimerIdx,
03388                                                        uint32_t OnePulseChannel,
03389                                                        const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
03390 {
03391   HRTIM_OutputCfgTypeDef OutputCfg;
03392   HRTIM_EventCfgTypeDef EventCfg;
03393
03394   /* Check parameters */
03395   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03396   assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
03397   assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
03398   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
03399   assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
03400   assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
03401                                       pSimpleOnePulseChannelCfg->EventPolarity));
03402   assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
03403   assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
03404                                     pSimpleOnePulseChannelCfg->EventFilter));
03405
03406   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03407   {
03408      return HAL_BUSY;
03409   }
03410
03411   /* Process Locked */
03412   __HAL_LOCK(hhrtim);
03413
03414   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03415
03416   /* Configure timer compare unit */
03417   switch (OnePulseChannel)
03418   {
03419   case HRTIM_OUTPUT_TA1:
03420   case HRTIM_OUTPUT_TB1:
03421   case HRTIM_OUTPUT_TC1:
03422   case HRTIM_OUTPUT_TD1:
03423   case HRTIM_OUTPUT_TE1:
03424   case HRTIM_OUTPUT_TF1:
03425     {
03426       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
03427       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
03428       break;
03429     }
03430
03431   case HRTIM_OUTPUT_TA2:
03432   case HRTIM_OUTPUT_TB2:
03433   case HRTIM_OUTPUT_TC2:
03434   case HRTIM_OUTPUT_TD2:
03435   case HRTIM_OUTPUT_TE2:
03436   case HRTIM_OUTPUT_TF2:
03437     {
03438       hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
03439       OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
03440       break;
03441     }
03442
03443   default:
03444     {
03445       OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
03446       OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
03447
03448       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03449
03450       /* Process Unlocked */
03451       __HAL_UNLOCK(hhrtim);
03452
03453       break;
03454     }
03455   }
03456
03457   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03458   {
03459      return HAL_ERROR;
03460   }
03461
03462   /* Configure timer output */
03463   OutputCfg.Polarity =  (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
03464   OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
03465   OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
03466   OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
03467   OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
03468   OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
03469   OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
03470
03471   HRTIM_OutputConfig(hhrtim,
03472                      TimerIdx,
03473                      OnePulseChannel,
03474                      &OutputCfg);
03475
03476   /* Configure external event channel */
03477   EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
03478   EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
03479   EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
03480   EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
03481   EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
03482
03483   HRTIM_EventConfig(hhrtim,
03484                     pSimpleOnePulseChannelCfg->Event,
03485                     &EventCfg);
03486
03487   /* Configure the timer reset register */
03488   HRTIM_TIM_ResetConfig(hhrtim,
03489                         TimerIdx,
03490                         pSimpleOnePulseChannelCfg->Event);
03491
03492   hhrtim->State = HAL_HRTIM_STATE_READY;
03493
03494   /* Process Unlocked */
03495   __HAL_UNLOCK(hhrtim);
03496
03497   return HAL_OK;
03498 }
03499
03500 /**
03501   * @brief  Enable the simple one pulse signal generation on the designed output
03502   * @param  hhrtim pointer to HAL HRTIM handle
03503   * @param  TimerIdx Timer index
03504   *                   This parameter can be one of the following values:
03505   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03506   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03507   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03508   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03509   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03510   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03511   * @param  OnePulseChannel Timer output
03512   *                    This parameter can be one of the following values:
03513   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03514   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03515   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03516   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03517   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03518   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03519   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03520   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03521   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03522   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03523   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
03524   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
03525   * @retval HAL status
03526   */
03527 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
03528                                                 uint32_t TimerIdx,
03529                                                 uint32_t OnePulseChannel)
03530 {
03531   /* Check the parameters */
03532   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03533
03534   /* Process Locked */
03535   __HAL_LOCK(hhrtim);
03536
03537   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03538
03539   /* Enable the timer output */
03540   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03541
03542   /* Enable the timer counter */
03543   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03544
03545   hhrtim->State = HAL_HRTIM_STATE_READY;
03546
03547   /* Process Unlocked */
03548   __HAL_UNLOCK(hhrtim);
03549
03550   return HAL_OK;
03551 }
03552
03553 /**
03554   * @brief  Disable the simple one pulse signal generation on the designed output
03555   * @param  hhrtim pointer to HAL HRTIM handle
03556   * @param  TimerIdx Timer index
03557   *                   This parameter can be one of the following values:
03558   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03559   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03560   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03561   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03562   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03563   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03564   * @param  OnePulseChannel Timer output
03565   *                    This parameter can be one of the following values:
03566   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03567   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03568   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03569   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03570   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03571   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03572   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03573   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03574   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03575   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03576   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
03577   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
03578   * @retval HAL status
03579   */
03580 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
03581                                               uint32_t TimerIdx,
03582                                               uint32_t OnePulseChannel)
03583 {
03584   /* Check the parameters */
03585   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03586
03587   /* Process Locked */
03588   __HAL_LOCK(hhrtim);
03589
03590   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03591
03592   /* Disable the timer output */
03593   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03594
03595   /* Disable the timer counter */
03596   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03597
03598   hhrtim->State = HAL_HRTIM_STATE_READY;
03599
03600   /* Process Unlocked */
03601   __HAL_UNLOCK(hhrtim);
03602
03603   return HAL_OK;
03604 }
03605
03606 /**
03607   * @brief  Enable the simple one pulse signal generation on the designed output
03608   *         (The compare interrupt is enabled (pulse start)).
03609   * @param  hhrtim pointer to HAL HRTIM handle
03610   * @param  TimerIdx Timer index
03611   *                   This parameter can be one of the following values:
03612   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03613   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03614   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03615   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03616   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03617   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer E
03618   * @param  OnePulseChannel Timer output
03619   *                    This parameter can be one of the following values:
03620   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03621   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03622   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03623   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03624   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03625   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03626   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03627   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03628   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03629   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03630   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
03631   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
03632   * @retval HAL status
03633   */
03634 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
03635                                                   uint32_t TimerIdx,
03636                                                   uint32_t OnePulseChannel)
03637 {
03638   /* Check the parameters */
03639   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03640
03641   /* Process Locked */
03642   __HAL_LOCK(hhrtim);
03643
03644   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03645
03646   /* Enable the timer output */
03647   hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
03648
03649   /* Enable the timer interrupt (depends on the OnePulse output) */
03650   switch (OnePulseChannel)
03651   {
03652   case HRTIM_OUTPUT_TA1:
03653   case HRTIM_OUTPUT_TB1:
03654   case HRTIM_OUTPUT_TC1:
03655   case HRTIM_OUTPUT_TD1:
03656   case HRTIM_OUTPUT_TE1:
03657   case HRTIM_OUTPUT_TF1:
03658     {
03659       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03660       break;
03661     }
03662
03663   case HRTIM_OUTPUT_TA2:
03664   case HRTIM_OUTPUT_TB2:
03665   case HRTIM_OUTPUT_TC2:
03666   case HRTIM_OUTPUT_TD2:
03667   case HRTIM_OUTPUT_TE2:
03668   case HRTIM_OUTPUT_TF2:
03669     {
03670       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03671       break;
03672     }
03673
03674   default:
03675     {
03676       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03677
03678       /* Process Unlocked */
03679       __HAL_UNLOCK(hhrtim);
03680
03681       break;
03682     }
03683   }
03684
03685   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03686   {
03687      return HAL_ERROR;
03688   }
03689
03690   /* Enable the timer counter */
03691   __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03692
03693   hhrtim->State = HAL_HRTIM_STATE_READY;
03694
03695   /* Process Unlocked */
03696   __HAL_UNLOCK(hhrtim);
03697
03698   return HAL_OK;
03699 }
03700
03701 /**
03702   * @brief  Disable the simple one pulse signal generation on the designed output
03703   *         (The compare interrupt is disabled).
03704   * @param  hhrtim pointer to HAL HRTIM handle
03705   * @param  TimerIdx Timer index
03706   *                   This parameter can be one of the following values:
03707   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03708   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03709   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03710   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03711   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03712   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03713   * @param  OnePulseChannel Timer output
03714   *                    This parameter can be one of the following values:
03715   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
03716   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
03717   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
03718   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
03719   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
03720   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
03721   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
03722   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
03723   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
03724   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
03725   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
03726   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
03727   * @retval HAL status
03728   */
03729 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
03730                                                  uint32_t TimerIdx,
03731                                                  uint32_t OnePulseChannel)
03732 {
03733   /* Check the parameters */
03734   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
03735
03736   /* Process Locked */
03737   __HAL_LOCK(hhrtim);
03738
03739   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03740
03741   /* Disable the timer output */
03742   hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
03743
03744   /* Disable the timer interrupt (depends on the OnePulse output) */
03745   switch (OnePulseChannel)
03746   {
03747   case HRTIM_OUTPUT_TA1:
03748   case HRTIM_OUTPUT_TB1:
03749   case HRTIM_OUTPUT_TC1:
03750   case HRTIM_OUTPUT_TD1:
03751   case HRTIM_OUTPUT_TE1:
03752   case HRTIM_OUTPUT_TF1:
03753     {
03754       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
03755       break;
03756     }
03757
03758   case HRTIM_OUTPUT_TA2:
03759   case HRTIM_OUTPUT_TB2:
03760   case HRTIM_OUTPUT_TC2:
03761   case HRTIM_OUTPUT_TD2:
03762   case HRTIM_OUTPUT_TE2:
03763   case HRTIM_OUTPUT_TF2:
03764     {
03765       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
03766       break;
03767     }
03768
03769   default:
03770     {
03771       hhrtim->State = HAL_HRTIM_STATE_ERROR;
03772
03773       /* Process Unlocked */
03774       __HAL_UNLOCK(hhrtim);
03775
03776       break;
03777     }
03778   }
03779
03780   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
03781   {
03782      return HAL_ERROR;
03783   }
03784
03785   /* Disable the timer counter */
03786   __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
03787
03788   hhrtim->State = HAL_HRTIM_STATE_READY;
03789
03790   /* Process Unlocked */
03791   __HAL_UNLOCK(hhrtim);
03792
03793   return HAL_OK;
03794 }
03795
03796 /**
03797   * @}
03798   */
03799
03800 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
03801  *  @brief    HRTIM configuration functions
03802 @verbatim
03803  ===============================================================================
03804               ##### HRTIM configuration functions #####
03805  ===============================================================================
03806     [..]  This section provides functions allowing to configure the HRTIM
03807           resources shared by all the HRTIM timers operating in waveform mode:
03808       (+) Configure the burst mode controller
03809       (+) Configure an external event conditioning
03810       (+) Configure the external events sampling clock
03811       (+) Configure a fault conditioning
03812       (+) Enable or disable fault inputs
03813       (+) Configure the faults sampling clock
03814       (+) Configure an ADC trigger
03815
03816 @endverbatim
03817   * @{
03818   */
03819
03820 /**
03821   * @brief  Configure the burst mode feature of the HRTIM
03822   * @param  hhrtim pointer to HAL HRTIM handle
03823   * @param  pBurstModeCfg pointer to the burst mode configuration structure
03824   * @retval HAL status
03825   * @note This function must be called before starting the burst mode
03826   *       controller
03827   */
03828 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
03829                                             const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
03830 {
03831   uint32_t hrtim_bmcr;
03832
03833   /* Check parameters */
03834   assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
03835   assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
03836   assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
03837   assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
03838   assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
03839
03840   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03841   {
03842      return HAL_BUSY;
03843   }
03844
03845   /* Process Locked */
03846   __HAL_LOCK(hhrtim);
03847
03848   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03849
03850   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
03851
03852   /* Set the burst mode operating mode */
03853   hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
03854   hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
03855
03856   /* Set the burst mode clock source */
03857   hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
03858   hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
03859
03860   /* Set the burst mode prescaler */
03861   hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
03862   hrtim_bmcr |= pBurstModeCfg->Prescaler;
03863
03864   /* Enable/disable burst mode registers preload */
03865   hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
03866   hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
03867
03868   /* Set the burst mode trigger */
03869   hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
03870
03871   /* Set the burst mode compare value */
03872   hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
03873
03874   /* Set the burst mode period */
03875   hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
03876
03877   /* Update the HRTIM registers */
03878   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
03879
03880   hhrtim->State = HAL_HRTIM_STATE_READY;
03881
03882   /* Process Unlocked */
03883   __HAL_UNLOCK(hhrtim);
03884
03885   return HAL_OK;
03886 }
03887
03888 /**
03889   * @brief  Configure the conditioning of an external event
03890   * @param  hhrtim pointer to HAL HRTIM handle
03891   * @param  Event external event to configure
03892   *                    This parameter can be one of the following values:
03893   *                    @arg HRTIM_EVENT_NONE: no external Event
03894   *                    @arg HRTIM_EVENT_1: External event 1
03895   *                    @arg HRTIM_EVENT_2: External event 2
03896   *                    @arg HRTIM_EVENT_3: External event 3
03897   *                    @arg HRTIM_EVENT_4: External event 4
03898   *                    @arg HRTIM_EVENT_5: External event 5
03899   *                    @arg HRTIM_EVENT_6: External event 6
03900   *                    @arg HRTIM_EVENT_7: External event 7
03901   *                    @arg HRTIM_EVENT_8: External event 8
03902   *                    @arg HRTIM_EVENT_9: External event 9
03903   *                    @arg HRTIM_EVENT_10: External event 10
03904   * @param  pEventCfg pointer to the event conditioning configuration structure
03905   * @note This function must be called before starting the timer
03906   * @retval HAL status
03907   */
03908 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
03909                                         uint32_t Event,
03910                                         const HRTIM_EventCfgTypeDef* pEventCfg)
03911 {
03912   /* Check parameters */
03913   assert_param(IS_HRTIM_EVENT(Event));
03914   assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source));
03915   assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
03916   assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
03917   assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
03918   assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
03919
03920   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03921   {
03922      return HAL_BUSY;
03923   }
03924
03925   /* Process Locked */
03926   __HAL_LOCK(hhrtim);
03927
03928   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03929
03930   /* Configure the event channel */
03931   HRTIM_EventConfig(hhrtim, Event, pEventCfg);
03932
03933   hhrtim->State = HAL_HRTIM_STATE_READY;
03934
03935   /* Process Unlocked */
03936   __HAL_UNLOCK(hhrtim);
03937
03938   return HAL_OK;
03939 }
03940
03941 /**
03942   * @brief  Configure the external event conditioning block prescaler
03943   * @param  hhrtim pointer to HAL HRTIM handle
03944   * @param  Prescaler Prescaler value
03945   *                    This parameter can be one of the following values:
03946   *                    @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
03947   *                    @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
03948   *                    @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
03949   *                    @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
03950   * @note This function must be called before starting the timer
03951   * @retval HAL status
03952   */
03953 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
03954                                                  uint32_t Prescaler)
03955 {
03956   /* Check parameters */
03957   assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
03958
03959   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
03960   {
03961      return HAL_BUSY;
03962   }
03963
03964   /* Process Locked */
03965   __HAL_LOCK(hhrtim);
03966
03967   hhrtim->State = HAL_HRTIM_STATE_BUSY;
03968
03969   /* Set the external event prescaler */
03970   MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
03971
03972   hhrtim->State = HAL_HRTIM_STATE_READY;
03973
03974   /* Process Unlocked */
03975   __HAL_UNLOCK(hhrtim);
03976
03977   return HAL_OK;
03978 }
03979
03980 /**
03981   * @brief  Configure the conditioning of fault input
03982   * @param  hhrtim pointer to HAL HRTIM handle
03983   * @param  Fault fault input to configure
03984   *                    This parameter can be one of the following values:
03985   *                    @arg HRTIM_FAULT_1: Fault input 1
03986   *                    @arg HRTIM_FAULT_2: Fault input 2
03987   *                    @arg HRTIM_FAULT_3: Fault input 3
03988   *                    @arg HRTIM_FAULT_4: Fault input 4
03989   *                    @arg HRTIM_FAULT_5: Fault input 5
03990   *                    @arg HRTIM_FAULT_6: Fault input 6
03991   * @param  pFaultCfg pointer to the fault conditioning configuration structure
03992   * @note This function must be called before starting the timer and before
03993   *       enabling faults inputs
03994   * @retval HAL status
03995   */
03996 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
03997                                         uint32_t Fault,
03998                                         const HRTIM_FaultCfgTypeDef* pFaultCfg)
03999 {
04000   uint32_t hrtim_fltinr1;
04001   uint32_t hrtim_fltinr2;
04002   uint32_t source0,source1;
04003
04004   /* Check parameters */
04005   assert_param(IS_HRTIM_FAULT(Fault));
04006   assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
04007   assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
04008   assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
04009   assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
04010
04011   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04012   {
04013      return HAL_BUSY;
04014   }
04015
04016   /* Process Locked */
04017   __HAL_LOCK(hhrtim);
04018
04019   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04020
04021   /* Configure fault channel */
04022   hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
04023   hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
04024
04025   source0 =  (pFaultCfg->Source & 1U);
04026   source1 = ((pFaultCfg->Source & 2U) >> 1);
04027
04028   switch (Fault)
04029   {
04030   case HRTIM_FAULT_1:
04031     {
04032       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
04033       hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
04034       hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos);
04035       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1);
04036       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT1SRC_1_Pos);
04037       hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
04038       hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
04039       break;
04040     }
04041
04042   case HRTIM_FAULT_2:
04043     {
04044       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
04045       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
04046       hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos);
04047       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1);
04048       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT2SRC_1_Pos);
04049       hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
04050       hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
04051       break;
04052     }
04053
04054   case HRTIM_FAULT_3:
04055     {
04056       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
04057       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
04058       hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos);
04059       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1);
04060       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT3SRC_1_Pos);
04061       hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
04062       hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
04063       break;
04064      }
04065
04066   case HRTIM_FAULT_4:
04067     {
04068       hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
04069       hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
04070       hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos);
04071       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1);
04072       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT4SRC_1_Pos);
04073       hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
04074       hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
04075       break;
04076     }
04077
04078   case HRTIM_FAULT_5:
04079     {
04080       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
04081       hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
04082       hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos);
04083       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1);
04084       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT5SRC_1_Pos);
04085       hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
04086       hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
04087       break;
04088     }
04089
04090   case HRTIM_FAULT_6:
04091     {
04092       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK);
04093       hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P);
04094       hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos);
04095       hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1);
04096       hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT6SRC_1_Pos);
04097       hrtim_fltinr2 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR2_FLT6F);
04098       hrtim_fltinr2 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR2_FLT6LCK);
04099       break;
04100     }
04101
04102   default:
04103     {
04104       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04105
04106       /* Process Unlocked */
04107       __HAL_UNLOCK(hhrtim);
04108
04109       break;
04110     }
04111   }
04112
04113   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04114   {
04115      return HAL_ERROR;
04116   }
04117
04118   /* Update the HRTIM registers except LOCK bit */
04119   hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
04120   hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
04121
04122   /* Update the HRTIM registers LOCK bit */
04123   SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
04124   SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
04125
04126   hhrtim->State = HAL_HRTIM_STATE_READY;
04127
04128   /* Process Unlocked */
04129   __HAL_UNLOCK(hhrtim);
04130
04131   return HAL_OK;
04132 }
04133
04134 /**
04135   * @brief  Configure the fault conditioning block prescaler
04136   * @param  hhrtim pointer to HAL HRTIM handle
04137   * @param  Prescaler Prescaler value
04138   *                    This parameter can be one of the following values:
04139   *                    @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
04140   *                    @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
04141   *                    @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
04142   *                    @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
04143   * @retval HAL status
04144   * @note This function must be called before starting the timer and before
04145   *       enabling faults inputs
04146   */
04147 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
04148                                                  uint32_t Prescaler)
04149 {
04150   /* Check parameters */
04151   assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
04152
04153   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04154   {
04155      return HAL_BUSY;
04156   }
04157
04158   /* Process Locked */
04159   __HAL_LOCK(hhrtim);
04160
04161   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04162
04163   /* Set the external event prescaler */
04164   MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
04165
04166   hhrtim->State = HAL_HRTIM_STATE_READY;
04167
04168   /* Process Unlocked */
04169   __HAL_UNLOCK(hhrtim);
04170
04171   return HAL_OK;
04172 }
04173
04174 /**
04175   * @brief  Configure and Enable the blanking source of a Fault input
04176   * @param  hhrtim pointer to HAL HRTIM handle
04177   * @param  Fault fault input to configure
04178   *                    This parameter can be one of the following values:
04179   *                    @arg HRTIM_FAULT_1: Fault input 1
04180   *                    @arg HRTIM_FAULT_2: Fault input 2
04181   *                    @arg HRTIM_FAULT_3: Fault input 3
04182   *                    @arg HRTIM_FAULT_4: Fault input 4
04183   *                    @arg HRTIM_FAULT_5: Fault input 5
04184   *                    @arg HRTIM_FAULT_6: Fault input 6
04185   * @param  pFaultBlkCfg: pointer to the fault conditioning configuration structure
04186   * @note This function automatically enables the Blanking on Fault
04187   * @note This function must be called when fault is not enabled
04188   * @retval HAL status
04189   */
04190 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,
04191                                                 uint32_t Fault,
04192                                                 const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
04193 {
04194   /* Check parameters */
04195   assert_param(IS_HRTIM_FAULT(Fault));
04196   assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource));
04197
04198   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04199   {
04200      return HAL_BUSY;
04201   }
04202
04203   /* Process Locked */
04204   __HAL_LOCK(hhrtim);
04205
04206   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04207
04208   switch (Fault)
04209   {
04210    case HRTIM_FAULT_1:
04211     {
04212        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04213                   (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE),
04214                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) |
04215                   HRTIM_FLTINR3_FLT1BLKE));
04216        break;
04217     }
04218    case HRTIM_FAULT_2:
04219     {
04220        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04221                   (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE),
04222                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) |
04223                   HRTIM_FLTINR3_FLT2BLKE));
04224        break;
04225     }
04226    case HRTIM_FAULT_3:
04227     {
04228        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04229                   (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE),
04230                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) |
04231                   HRTIM_FLTINR3_FLT3BLKE));
04232        break;
04233     }
04234    case HRTIM_FAULT_4:
04235     {
04236        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04237                   (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE),
04238                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) |
04239                   HRTIM_FLTINR3_FLT4BLKE));
04240        break;
04241     }
04242    case HRTIM_FAULT_5:
04243     {
04244       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
04245                   (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE),
04246                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) |
04247                   HRTIM_FLTINR4_FLT5BLKE));
04248       break;
04249     }
04250    case HRTIM_FAULT_6:
04251     {
04252       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
04253                   (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE),
04254                   ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) |
04255                   HRTIM_FLTINR4_FLT6BLKE));
04256       break;
04257     }
04258
04259   default:
04260     {
04261       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04262
04263       /* Process Unlocked */
04264       __HAL_UNLOCK(hhrtim);
04265
04266       break;
04267     }
04268   }
04269
04270   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04271   {
04272      return HAL_ERROR;
04273   }
04274
04275   hhrtim->State = HAL_HRTIM_STATE_READY;
04276
04277   /* Process Unlocked */
04278   __HAL_UNLOCK(hhrtim);
04279
04280   return HAL_OK;
04281 }
04282
04283 /**
04284   * @brief  Configure the Fault Counter (Threshold and Reset Mode)
04285   * @param  hhrtim pointer to HAL HRTIM handle
04286   * @param  Fault fault input to configure
04287   *                    This parameter can be one of the following values:
04288   *                    @arg HRTIM_FAULT_1: Fault input 1
04289   *                    @arg HRTIM_FAULT_2: Fault input 2
04290   *                    @arg HRTIM_FAULT_3: Fault input 3
04291   *                    @arg HRTIM_FAULT_4: Fault input 4
04292   *                    @arg HRTIM_FAULT_5: Fault input 5
04293   *                    @arg HRTIM_FAULT_6: Fault input 6
04294   * @param  pFaultBlkCfg: pointer to the fault conditioning configuration structure
04295   * @retval HAL status
04296   * @note  A fault is considered valid when the number of
04297   *        events is equal to the (FLTxCNT[3:0]+1) value
04298   *
04299   * @retval HAL status
04300   */
04301 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,
04302                                                uint32_t Fault,
04303                                                const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
04304 {
04305   /* Check parameters */
04306   assert_param(IS_HRTIM_FAULT(Fault));
04307   assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold));
04308   assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode));
04309
04310   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04311   {
04312      return HAL_BUSY;
04313   }
04314
04315   /* Process Locked */
04316   __HAL_LOCK(hhrtim);
04317
04318   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04319
04320   switch (Fault)
04321   {
04322    case HRTIM_FAULT_1:
04323     {
04324        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04325                   (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT),
04326                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) |
04327                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos));
04328        break;
04329     }
04330    case HRTIM_FAULT_2:
04331     {
04332        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04333                   (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT),
04334                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) |
04335                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos));
04336        break;
04337     }
04338    case HRTIM_FAULT_3:
04339     {
04340        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04341                   (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT),
04342                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) |
04343                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos));
04344        break;
04345     }
04346    case HRTIM_FAULT_4:
04347     {
04348        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
04349                   (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT),
04350                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) |
04351                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos));
04352        break;
04353     }
04354    case HRTIM_FAULT_5:
04355     {
04356        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
04357                   (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT),
04358                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) |
04359                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos));
04360        break;
04361     }
04362    case HRTIM_FAULT_6:
04363     {
04364        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
04365                   (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT),
04366                   (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) |
04367                   (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos));
04368        break;
04369     }
04370
04371   default:
04372     {
04373       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04374
04375       /* Process Unlocked */
04376       __HAL_UNLOCK(hhrtim);
04377
04378       break;
04379     }
04380   }
04381
04382   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04383   {
04384      return HAL_ERROR;
04385   }
04386
04387   hhrtim->State = HAL_HRTIM_STATE_READY;
04388
04389   /* Process Unlocked */
04390   __HAL_UNLOCK(hhrtim);
04391
04392   return HAL_OK;
04393 }
04394
04395 /**
04396   * @brief  Reset the fault Counter Reset
04397   * @param  hhrtim pointer to HAL HRTIM handle
04398   * @param  Fault fault input to reset
04399   *                    This parameter can be one of the following values:
04400   *                    @arg HRTIM_FAULT_1: Fault input 1
04401   *                    @arg HRTIM_FAULT_2: Fault input 2
04402   *                    @arg HRTIM_FAULT_3: Fault input 3
04403   *                    @arg HRTIM_FAULT_4: Fault input 4
04404   *                    @arg HRTIM_FAULT_5: Fault input 5
04405   *                    @arg HRTIM_FAULT_6: Fault input 6
04406   * @retval HAL status
04407   */
04408 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,
04409                                               uint32_t Fault)
04410 {
04411   /* Check parameters */
04412   assert_param(IS_HRTIM_FAULT(Fault));
04413
04414   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04415   {
04416      return HAL_BUSY;
04417   }
04418
04419   /* Process Locked */
04420   __HAL_LOCK(hhrtim);
04421
04422   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04423
04424   switch (Fault)
04425   {
04426    case HRTIM_FAULT_1:
04427     {
04428       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ;
04429       break;
04430     }
04431    case HRTIM_FAULT_2:
04432     {
04433       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ;
04434       break;
04435     }
04436    case HRTIM_FAULT_3:
04437     {
04438        MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ;
04439        break;
04440     }
04441    case HRTIM_FAULT_4:
04442     {
04443       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ;
04444       break;
04445     }
04446    case HRTIM_FAULT_5:
04447     {
04448       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ;
04449       break;
04450     }
04451    case HRTIM_FAULT_6:
04452     {
04453       MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ;
04454       break;
04455     }
04456
04457   default:
04458     {
04459       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04460
04461       /* Process Unlocked */
04462       __HAL_UNLOCK(hhrtim);
04463
04464       break;
04465     }
04466   }
04467
04468   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04469   {
04470      return HAL_ERROR;
04471   }
04472
04473   hhrtim->State = HAL_HRTIM_STATE_READY;
04474
04475   /* Process Unlocked */
04476   __HAL_UNLOCK(hhrtim);
04477
04478   return HAL_OK;
04479 }
04480
04481 /**
04482   * @brief  Enable or disables the HRTIMx Fault mode.
04483   * @param  hhrtim pointer to HAL HRTIM handle
04484   * @param  Faults fault input(s) to enable or disable
04485   *                   This parameter can be any combination of the following values:
04486   *                    @arg HRTIM_FAULT_1: Fault input 1
04487   *                    @arg HRTIM_FAULT_2: Fault input 2
04488   *                    @arg HRTIM_FAULT_3: Fault input 3
04489   *                    @arg HRTIM_FAULT_4: Fault input 4
04490   *                    @arg HRTIM_FAULT_5: Fault input 5
04491   *                    @arg HRTIM_FAULT_6: Fault input 6
04492   * @param  Enable Fault(s) enabling
04493   *                    This parameter can be one of the following values:
04494   *                    @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
04495   *                    @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
04496   * @retval None
04497   */
04498 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
04499                         uint32_t Faults,
04500                         uint32_t Enable)
04501 {
04502   /* Check parameters */
04503   assert_param(IS_HRTIM_FAULT(Faults));
04504   assert_param(IS_HRTIM_FAULTMODECTL(Enable));
04505
04506   if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
04507   {
04508     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
04509   }
04510   if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
04511   {
04512     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
04513   }
04514   if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
04515   {
04516     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
04517   }
04518   if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
04519   {
04520     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
04521   }
04522   if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
04523   {
04524     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
04525   }
04526   if ((Faults & HRTIM_FAULT_6) != (uint32_t)RESET)
04527   {
04528     MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT6E, ((Enable << 8U) & HRTIM_FLTINR2_FLT6E));
04529   }
04530 }
04531
04532 /**
04533   * @brief  Configure both the ADC trigger register update source and the ADC
04534   *         trigger source.
04535   * @param  hhrtim pointer to HAL HRTIM handle
04536   * @param  ADCTrigger ADC trigger to configure
04537   *                    This parameter can be one of the following values:
04538   *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
04539   *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
04540   *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
04541   *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
04542   *                    @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
04543   *                    @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
04544   *                    @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
04545   *                    @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
04546   *                    @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
04547   *                    @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
04548   * @param  pADCTriggerCfg pointer to the ADC trigger configuration structure
04549   *                    for Trigger nb (1..4): pADCTriggerCfg->Trigger parameter
04550   *                    can be a combination of the following values
04551   *                    @arg HRTIM_ADCTRIGGEREVENT13_...
04552   *                    @arg HRTIM_ADCTRIGGEREVENT24_...
04553   *                    for Trigger nb (5..10): pADCTriggerCfg->Trigger parameter
04554   *                    can be one of the following values
04555   *                    @arg HRTIM_ADCTRIGGEREVENT579_...
04556   *                    @arg HRTIM_ADCTRIGGEREVENT6810_...
04557   * @retval HAL status
04558   * @note This function must be called before starting the timer
04559   */
04560 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
04561                                              uint32_t ADCTrigger,
04562                                              const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
04563 {
04564   uint32_t hrtim_cr1;
04565   uint32_t hrtim_adcur;
04566
04567   /* Check parameters */
04568   assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
04569   assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
04570
04571   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04572   {
04573      return HAL_BUSY;
04574   }
04575
04576   /* Process Locked */
04577   __HAL_LOCK(hhrtim);
04578
04579   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04580
04581   /* Set the ADC trigger update source */
04582   hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
04583   hrtim_adcur = hhrtim->Instance->sCommonRegs.ADCUR;
04584
04585   switch (ADCTrigger)
04586   {
04587   case HRTIM_ADCTRIGGER_1:
04588     {
04589       hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
04590       hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
04591
04592       /* Set the ADC trigger 1 source */
04593       hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
04594       break;
04595     }
04596
04597   case HRTIM_ADCTRIGGER_2:
04598     {
04599       hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
04600       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
04601
04602       /* Set the ADC trigger 2 source */
04603       hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
04604       break;
04605     }
04606
04607   case HRTIM_ADCTRIGGER_3:
04608     {
04609       hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
04610       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
04611
04612       /* Set the ADC trigger 3 source */
04613       hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
04614       break;
04615     }
04616
04617   case HRTIM_ADCTRIGGER_4:
04618     {
04619       hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
04620       hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
04621
04622       /* Set the ADC trigger 4 source */
04623       hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
04624       break;
04625     }
04626
04627   case HRTIM_ADCTRIGGER_5:
04628     {
04629       hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC);
04630       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC);
04631
04632       /* Set the ADC trigger 5 source */
04633       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD5TRG);
04634       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD5TRG_Pos) & HRTIM_ADCER_AD5TRG);
04635       break;
04636     }
04637
04638   case HRTIM_ADCTRIGGER_6:
04639     {
04640       hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC);
04641       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC);
04642
04643       /* Set the ADC trigger 6 source */
04644       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD6TRG);
04645       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD6TRG_Pos) & HRTIM_ADCER_AD6TRG);
04646       break;
04647     }
04648
04649   case HRTIM_ADCTRIGGER_7:
04650     {
04651       hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC);
04652       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC);
04653
04654       /* Set the ADC trigger 7 source */
04655       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD7TRG);
04656       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD7TRG_Pos) & HRTIM_ADCER_AD7TRG);
04657       break;
04658     }
04659
04660   case HRTIM_ADCTRIGGER_8:
04661     {
04662       hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC);
04663       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC);
04664
04665       /* Set the ADC trigger 8 source */
04666       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD8TRG);
04667       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD8TRG_Pos) & HRTIM_ADCER_AD8TRG);
04668       break;
04669     }
04670
04671   case HRTIM_ADCTRIGGER_9:
04672     {
04673       hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC);
04674       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC);
04675
04676       /* Set the ADC trigger 9 source */
04677       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD9TRG);
04678       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD9TRG_Pos) & HRTIM_ADCER_AD9TRG);
04679       break;
04680     }
04681
04682   case HRTIM_ADCTRIGGER_10:
04683     {
04684       hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC);
04685       hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC);
04686
04687       /* Set the ADC trigger 10 source */
04688       hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD10TRG);
04689       hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD10TRG_Pos) & HRTIM_ADCER_AD10TRG);
04690       break;
04691     }
04692
04693   default:
04694     {
04695       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04696
04697       /* Process Unlocked */
04698       __HAL_UNLOCK(hhrtim);
04699
04700       break;
04701     }
04702   }
04703
04704   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04705   {
04706      return HAL_ERROR;
04707   }
04708
04709   /* Update the HRTIM registers */
04710   if (ADCTrigger < HRTIM_ADCTRIGGER_5)
04711   {
04712    hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
04713   }
04714   else
04715   {
04716    hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur;
04717   }
04718
04719   hhrtim->State = HAL_HRTIM_STATE_READY;
04720
04721   /* Process Unlocked */
04722   __HAL_UNLOCK(hhrtim);
04723
04724   return HAL_OK;
04725 }
04726
04727 /**
04728   * @brief  Configure the ADC trigger postscaler register of the ADC
04729   *         trigger source.
04730   * @param  hhrtim pointer to HAL HRTIM handle
04731   * @param  ADCTrigger ADC trigger to configure
04732   *                    This parameter can be one of the following values:
04733   *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
04734   *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
04735   *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
04736   *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
04737   *                    @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
04738   *                    @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
04739   *                    @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
04740   *                    @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
04741   *                    @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
04742   *                    @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
04743   * @param  Postscaler  value 0..1F
04744   * @retval HAL status
04745   * @note This function must be called before starting the timer
04746   */
04747 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,
04748                                              uint32_t ADCTrigger,
04749                                              uint32_t Postscaler)
04750 {
04751   /* Check parameters */
04752   assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
04753
04754   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04755   {
04756      return HAL_BUSY;
04757   }
04758
04759   /* Process Locked */
04760   __HAL_LOCK(hhrtim);
04761
04762   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04763
04764   switch (ADCTrigger)
04765   {
04766   case HRTIM_ADCTRIGGER_1:
04767     {
04768       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC));
04769       break;
04770     }
04771
04772   case HRTIM_ADCTRIGGER_2:
04773     {
04774       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC));
04775       break;
04776     }
04777
04778   case HRTIM_ADCTRIGGER_3:
04779     {
04780       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC));
04781       break;
04782     }
04783
04784   case HRTIM_ADCTRIGGER_4:
04785     {
04786       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC));
04787       break;
04788     }
04789
04790   case HRTIM_ADCTRIGGER_5:
04791     {
04792       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC));
04793       break;
04794     }
04795
04796   case HRTIM_ADCTRIGGER_6:
04797     {
04798       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC));
04799       break;
04800     }
04801
04802   case HRTIM_ADCTRIGGER_7:
04803     {
04804       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC));
04805       break;
04806     }
04807
04808   case HRTIM_ADCTRIGGER_8:
04809     {
04810       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC));
04811       break;
04812     }
04813
04814   case HRTIM_ADCTRIGGER_9:
04815     {
04816       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC));
04817       break;
04818     }
04819
04820   case HRTIM_ADCTRIGGER_10:
04821     {
04822       MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC));
04823       break;
04824     }
04825
04826   default:
04827     {
04828       hhrtim->State = HAL_HRTIM_STATE_ERROR;
04829
04830       /* Process Unlocked */
04831       __HAL_UNLOCK(hhrtim);
04832
04833       break;
04834     }
04835   }
04836
04837   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
04838   {
04839      return HAL_ERROR;
04840   }
04841
04842   hhrtim->State = HAL_HRTIM_STATE_READY;
04843
04844   /* Process Unlocked */
04845   __HAL_UNLOCK(hhrtim);
04846
04847   return HAL_OK;
04848 }
04849
04850 /**
04851   * @brief  Configure the ADC Roll-Over mode of the ADC
04852   *         trigger source.
04853   * @param  hhrtim pointer to HAL HRTIM handle
04854   * @param  TimerIdx Timer index
04855   *                   This parameter can be one of the following values:
04856   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04857   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04858   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04859   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04860   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04861   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
04862   * @param  RollOverCfg This parameter can be a combination of all the following values:
04863   *                   @arg HRTIM_TIM_FEROM_BOTH  or HRTIM_TIM_FEROM_CREST  or HRTIM_TIM_FEROM_VALLEY
04864   *                   @arg HRTIM_TIM_BMROM_BOTH  or HRTIM_TIM_BMROM_CREST  or HRTIM_TIM_BMROM_VALLEY
04865   *                   @arg HRTIM_TIM_ADROM_BOTH  or HRTIM_TIM_ADROM_CREST  or HRTIM_TIM_ADROM_VALLEY
04866   *                   @arg HRTIM_TIM_OUTROM_BOTH or HRTIM_TIM_OUTROM_CREST or HRTIM_TIM_OUTROM_VALLEY
04867   *                   @arg HRTIM_TIM_ROM_BOTH    or HRTIM_TIM_ROM_CREST    or HRTIM_TIM_ROM_VALLEY
04868   * @note This function must be called before starting the timer
04869   */
04870 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,
04871                                              uint32_t TimerIdx,
04872                                              uint32_t RollOverCfg)
04873 {
04874   /* Check parameters */
04875   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
04876   assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg));
04877
04878   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04879   {
04880      return HAL_BUSY;
04881   }
04882
04883   /* Process Locked */
04884   __HAL_LOCK(hhrtim);
04885
04886   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04887
04888    HRTIM_TimingUnitRollOver_Config(hhrtim,TimerIdx,RollOverCfg);
04889
04890   hhrtim->State = HAL_HRTIM_STATE_READY;
04891
04892   /* Process Unlocked */
04893   __HAL_UNLOCK(hhrtim);
04894
04895   return HAL_OK;
04896 }
04897
04898
04899 /**
04900   * @}
04901   */
04902
04903 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
04904  *  @brief    HRTIM timer configuration and control functions
04905 @verbatim
04906  ===============================================================================
04907               ##### HRTIM timer configuration and control functions #####
04908  ===============================================================================
04909     [..]  This section provides functions used to configure and control a
04910           HRTIM timer operating in waveform mode:
04911       (+) Configure HRTIM timer general behavior
04912       (+) Configure HRTIM timer event filtering
04913       (+) Configure HRTIM timer deadtime insertion
04914       (+) Configure HRTIM timer chopper mode
04915       (+) Configure HRTIM timer burst DMA
04916       (+) Configure HRTIM timer compare unit
04917       (+) Configure HRTIM timer capture unit
04918       (+) Configure HRTIM timer output
04919       (+) Set HRTIM timer output level
04920       (+) Enable HRTIM timer output
04921       (+) Disable HRTIM timer output
04922       (+) Start HRTIM timer
04923       (+) Stop HRTIM timer
04924       (+) Start HRTIM timer and enable interrupt
04925       (+) Stop HRTIM timer and disable interrupt
04926       (+) Start HRTIM timer and enable DMA transfer
04927       (+) Stop HRTIM timer and disable DMA transfer
04928       (+) Enable or disable the burst mode controller
04929       (+) Start the burst mode controller (by software)
04930       (+) Trigger a Capture (by software)
04931       (+) Update the HRTIM timer preloadable registers (by software)
04932       (+) Reset the HRTIM timer counter (by software)
04933       (+) Start a burst DMA transfer
04934       (+) Enable timer register update
04935       (+) Disable timer register update
04936
04937 @endverbatim
04938   * @{
04939   */
04940
04941 /**
04942   * @brief  Configure the general behavior of a timer operating in waveform mode
04943   * @param  hhrtim pointer to HAL HRTIM handle
04944   * @param  TimerIdx Timer index
04945   *                   This parameter can be one of the following values:
04946   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
04947   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
04948   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
04949   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
04950   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
04951   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
04952   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
04953   * @param  pTimerCfg pointer to the timer configuration structure
04954   * @note When the timer operates in waveform mode, all the features supported by
04955   *       the HRTIM are available without any limitation.
04956   * @retval HAL status
04957   * @note This function must be called before starting the timer
04958   */
04959 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
04960                                                 uint32_t TimerIdx,
04961                                                 const HRTIM_TimerCfgTypeDef * pTimerCfg)
04962 {
04963   /* Check parameters */
04964   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
04965
04966   /* Relevant for all HRTIM timers, including the master */
04967   assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
04968   assert_param(IS_HRTIM_INTERLEAVEDMODE(pTimerCfg->InterleavedMode));
04969   assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
04970   assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
04971   assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
04972   assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
04973   assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
04974   assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
04975
04976   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
04977   {
04978      return HAL_BUSY;
04979   }
04980
04981   /* Process Locked */
04982   __HAL_LOCK(hhrtim);
04983
04984   hhrtim->State = HAL_HRTIM_STATE_BUSY;
04985
04986   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
04987   {
04988     /* Check parameters */
04989     assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
04990     assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
04991     assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
04992
04993     /* Configure master timer */
04994     HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
04995   }
04996   else
04997   {
04998     /* Check parameters */
04999     assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
05000     assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
05001     assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
05002     assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
05003     assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
05004     assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
05005     assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
05006                                                pTimerCfg->DeadTimeInsertion));
05007     assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
05008                                                pTimerCfg->DelayedProtectionMode));
05009     assert_param(IS_HRTIM_OUTPUTBALANCEDIDLE(pTimerCfg->BalancedIdleAutomaticResume));
05010     assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
05011     assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
05012     assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
05013     assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
05014
05015     /* Configure timing unit */
05016     HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
05017   }
05018
05019   /* Update timer parameters */
05020   hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
05021   hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
05022   hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
05023   hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
05024   hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
05025
05026   /* Force a software update */
05027   HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
05028
05029   /* Configure slave timer update re-synchronization */
05030   if ((TimerIdx != HRTIM_TIMERINDEX_MASTER)
05031    && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT))
05032   {
05033     MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR,
05034                HRTIM_TIMCR_RSYNCU_Msk,
05035                pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos);
05036   }
05037
05038   hhrtim->State = HAL_HRTIM_STATE_READY;
05039
05040   /* Process Unlocked */
05041   __HAL_UNLOCK(hhrtim);
05042
05043   return HAL_OK;
05044 }
05045
05046 /**
05047   * @brief  Configure the general behavior of a timer operating in waveform mode
05048   * @param  hhrtim pointer to HAL HRTIM handle
05049   * @param  TimerIdx Timer index
05050   *                   This parameter can be one of the following values:
05051   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05052   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05053   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05054   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05055   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05056   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05057   * @param  pTimerCtl pointer to the timer configuration structure
05058   * @note When the timer operates in waveform mode, all the features supported by
05059   *       the HRTIM are available without any limitation.
05060   * @retval HAL status
05061   * @note This function must be called before starting the timer
05062   */
05063 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,
05064                                                 uint32_t TimerIdx,
05065                                                 const HRTIM_TimerCtlTypeDef * pTimerCtl)
05066 {
05067     /* Check parameters */
05068     assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
05069     /* Relevant for all A..F HRTIM timers */
05070     assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode));
05071     assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf));
05072     assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3));
05073     assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
05074     assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
05075     assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
05076     assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
05077
05078     if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05079     {
05080        return HAL_BUSY;
05081     }
05082
05083     /* Process Locked */
05084     __HAL_LOCK(hhrtim);
05085
05086     hhrtim->State = HAL_HRTIM_STATE_BUSY;
05087
05088     /* Configure timing unit */
05089     HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
05090
05091     /* Force a software update */
05092     HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
05093
05094     hhrtim->State = HAL_HRTIM_STATE_READY;
05095
05096     /* Process Unlocked */
05097     __HAL_UNLOCK(hhrtim);
05098
05099     return HAL_OK;
05100 }
05101
05102 /**
05103   * @brief  Configure the Dual Channel Dac behavior of a timer operating in waveform mode
05104   * @param  hhrtim: pointer to HAL HRTIM handle
05105   * @param  TimerIdx Timer index
05106   *                   This parameter can be one of the following values:
05107   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05108   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05109   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05110   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05111   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05112   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05113   * @param  pTimerCtl pointer to the timer DualChannel Dac configuration structure
05114   * @note When the timer operates in waveform mode, all the features supported by
05115   *       the HRTIM are available without any limitation.
05116   * @retval HAL status
05117   * @note This function must be called before starting the timer
05118   */
05119 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,
05120                                                 uint32_t TimerIdx,
05121                                                 const HRTIM_TimerCtlTypeDef * pTimerCtl)
05122 {
05123     assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
05124     assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
05125     assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
05126
05127     if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05128     {
05129      return HAL_BUSY;
05130     }
05131
05132     /* Process Locked */
05133     __HAL_LOCK(hhrtim);
05134
05135     hhrtim->State = HAL_HRTIM_STATE_BUSY;
05136     /* clear DCDS,DCDR,DCDE bits */
05137     CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
05138                    (HRTIM_TIMER_DCDE_ENABLED |
05139                     HRTIM_TIMER_DCDS_OUT1RST |
05140                     HRTIM_TIMER_DCDR_OUT1SET) );
05141
05142     MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 ,
05143                    (HRTIM_TIMER_DCDE_ENABLED |
05144                     HRTIM_TIMER_DCDS_OUT1RST |
05145                     HRTIM_TIMER_DCDR_OUT1SET),
05146                    (pTimerCtl->DualChannelDacReset |
05147                     pTimerCtl->DualChannelDacStep |
05148                     pTimerCtl->DualChannelDacEnable));
05149
05150     hhrtim->State = HAL_HRTIM_STATE_READY;
05151
05152      /* Process Unlocked */
05153      __HAL_UNLOCK(hhrtim);
05154
05155      return HAL_OK;
05156 }
05157
05158 /**
05159   * @brief  Configure the event filtering capabilities of a timer (blanking, windowing)
05160   * @param  hhrtim pointer to HAL HRTIM handle
05161   * @param  TimerIdx Timer index
05162   *                   This parameter can be one of the following values:
05163   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05164   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05165   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05166   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05167   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05168   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05169   * @param  Event external event for which timer event filtering must be configured
05170   *                    This parameter can be one of the following values:
05171   *                    @arg HRTIM_EVENT_1: External event 1
05172   *                    @arg HRTIM_EVENT_2: External event 2
05173   *                    @arg HRTIM_EVENT_3: External event 3
05174   *                    @arg HRTIM_EVENT_4: External event 4
05175   *                    @arg HRTIM_EVENT_5: External event 5
05176   *                    @arg HRTIM_EVENT_6: External event 6
05177   *                    @arg HRTIM_EVENT_7: External event 7
05178   *                    @arg HRTIM_EVENT_8: External event 8
05179   *                    @arg HRTIM_EVENT_9: External event 9
05180   *                    @arg HRTIM_EVENT_10: External event 10
05181   * @param  pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
05182   * @note This function must be called before starting the timer
05183   * @retval HAL status
05184   */
05185 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
05186                                                       uint32_t TimerIdx,
05187                                                       uint32_t Event,
05188                                                       const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
05189 {
05190   /* Check parameters */
05191   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05192   assert_param(IS_HRTIM_EVENT(Event));
05193   assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx,pTimerEventFilteringCfg->Filter));
05194
05195   assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
05196
05197   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05198   {
05199      return HAL_BUSY;
05200   }
05201
05202   /* Process Locked */
05203   __HAL_LOCK(hhrtim);
05204
05205   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05206
05207   /* Configure timer event filtering capabilities */
05208   switch (Event)
05209   {
05210   case HRTIM_EVENT_NONE:
05211     {
05212       CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
05213       CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
05214       break;
05215     }
05216
05217   case HRTIM_EVENT_1:
05218     {
05219       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
05220       break;
05221     }
05222
05223   case HRTIM_EVENT_2:
05224     {
05225       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
05226       break;
05227     }
05228
05229   case HRTIM_EVENT_3:
05230     {
05231       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
05232       break;
05233     }
05234
05235   case HRTIM_EVENT_4:
05236     {
05237       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
05238       break;
05239     }
05240
05241   case HRTIM_EVENT_5:
05242     {
05243       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
05244       break;
05245     }
05246
05247   case HRTIM_EVENT_6:
05248     {
05249       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
05250       break;
05251     }
05252
05253   case HRTIM_EVENT_7:
05254     {
05255       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
05256       break;
05257     }
05258
05259   case HRTIM_EVENT_8:
05260     {
05261       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
05262       break;
05263     }
05264
05265   case HRTIM_EVENT_9:
05266     {
05267       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
05268       break;
05269     }
05270
05271   case HRTIM_EVENT_10:
05272     {
05273       MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
05274       break;
05275     }
05276
05277   default:
05278    {
05279       hhrtim->State = HAL_HRTIM_STATE_ERROR;
05280
05281       /* Process Unlocked */
05282       __HAL_UNLOCK(hhrtim);
05283
05284       break;
05285     }
05286   }
05287
05288   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05289   {
05290      return HAL_ERROR;
05291   }
05292
05293   hhrtim->State = HAL_HRTIM_STATE_READY;
05294
05295   /* Process Unlocked */
05296   __HAL_UNLOCK(hhrtim);
05297
05298   return HAL_OK;
05299 }
05300
05301 /**
05302   * @brief  Configure the external Event Counter A or B of a timer (source, threshold, reset mode)
05303   *         but does not enable : call HAL_HRTIM_ExternalEventCounterEnable afterwards
05304   * @param  hhrtim pointer to HAL HRTIM handle
05305   * @param  TimerIdx Timer index
05306   *                   This parameter can be one of the following values:
05307   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05308   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05309   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05310   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05311   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05312   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05313   * @param  EventCounter external event Counter A or B for which timer event must be configured
05314   *                    This parameter can be one of the following values:
05315   *                    @arg HRTIM_EVENTCOUNTER_A
05316   *                    @arg HRTIM_EVENTCOUNTER_B
05317   * @param  pTimerExternalEventCfg: pointer to the timer external event configuration structure
05318   * @note This function must be called before starting the timer
05319   * @retval HAL status
05320   */
05321 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,
05322                                                       uint32_t TimerIdx,
05323                                                       uint32_t EventCounter,
05324                                                       const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg)
05325 {
05326   uint32_t hrtim_eefr3;
05327
05328   /* Check parameters */
05329   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05330   assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
05331   assert_param(IS_HRTIM_TIMEEVENT_RESETMODE(pTimerExternalEventCfg->ResetMode));
05332   assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter));
05333   assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source));
05334
05335   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05336   {
05337      return HAL_BUSY;
05338   }
05339
05340   /* Process Locked */
05341   __HAL_LOCK(hhrtim);
05342
05343   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05344
05345   if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
05346   {
05347    if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
05348    { /* reset External EventCounter A */
05349      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U);
05350    }
05351    else
05352    {
05353      /* Set timer External EventCounter A configuration */
05354      hrtim_eefr3  = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos;
05355      hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos;
05356      hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos;
05357      /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
05358
05359      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT) , hrtim_eefr3 );
05360    }
05361   }
05362
05363   if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
05364   {
05365    if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
05366    { /* reset External EventCounter B */
05367      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU);
05368    }
05369    else
05370    {
05371      /* Set timer External EventCounter B configuration */
05372      hrtim_eefr3  = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos;
05373      hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos;
05374      hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos;
05375      /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
05376
05377      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT) , hrtim_eefr3 );
05378    }
05379   }
05380   hhrtim->State = HAL_HRTIM_STATE_READY;
05381
05382   /* Process Unlocked */
05383   __HAL_UNLOCK(hhrtim);
05384
05385   return HAL_OK;
05386 }
05387
05388 /**
05389   * @brief  Enable the external event Counter A or B of a timer
05390   * @param  hhrtim: pointer to HAL HRTIM handle
05391   * @param  TimerIdx: Timer index
05392   *                   This parameter can be one of the following values:
05393   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05394   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05395   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05396   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05397   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05398   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05399   * @param  EventCounter external Event Counter A or B for which timer event must be configured
05400   *                    This parameter can be a one of the following values:
05401   *                    @arg HRTIM_EVENTCOUNTER_A
05402   *                    @arg HRTIM_EVENTCOUNTER_B
05403   * @note This function must be called before starting the timer
05404   * @retval HAL status
05405   */
05406 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,
05407                                                       uint32_t TimerIdx,
05408                                                       uint32_t EventCounter)
05409 {
05410   /* Check parameters */
05411   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05412   assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
05413
05414   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05415   {
05416      return HAL_BUSY;
05417   }
05418
05419   /* Process Locked */
05420   __HAL_LOCK(hhrtim);
05421
05422   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05423
05424   if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
05425   {
05426     SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
05427   }
05428   if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
05429   {
05430      SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
05431   }
05432
05433   hhrtim->State = HAL_HRTIM_STATE_READY;
05434
05435   /* Process Unlocked */
05436   __HAL_UNLOCK(hhrtim);
05437
05438   return HAL_OK;
05439 }
05440
05441 /**
05442   * @brief  Disable the external event Counter A or B of a timer
05443   * @param  hhrtim: pointer to HAL HRTIM handle
05444   * @param  TimerIdx: Timer index
05445   *                   This parameter can be one of the following values:
05446   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05447   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05448   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05449   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05450   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05451   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05452   * @param  EventCounter external event Counter A or B for which timer event must be configured
05453   *                    This parameter can be a one of the following values:
05454   *                    @arg HRTIM_EVENTCOUNTER_A
05455   *                    @arg HRTIM_EVENTCOUNTER_B
05456   * @retval HAL status
05457   */
05458 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,
05459                                                       uint32_t TimerIdx,
05460                                                       uint32_t EventCounter)
05461 {
05462   /* Check parameters */
05463   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05464   assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
05465
05466   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05467   {
05468      return HAL_BUSY;
05469   }
05470
05471   /* Process Locked */
05472   __HAL_LOCK(hhrtim);
05473
05474   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05475
05476   if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
05477   {
05478     CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
05479   }
05480
05481   if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
05482   {
05483      CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
05484   }
05485
05486   hhrtim->State = HAL_HRTIM_STATE_READY;
05487
05488   /* Process Unlocked */
05489   __HAL_UNLOCK(hhrtim);
05490
05491   return HAL_OK;
05492 }
05493
05494 /**
05495   * @brief  Reset the external event Counter A or B of a timer
05496   * @param  hhrtim pointer to HAL HRTIM handle
05497   * @param  TimerIdx Timer index
05498   *                   This parameter can be one of the following values:
05499   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05500   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05501   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05502   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05503   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05504   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05505   * @param  EventCounter external event Counter A or B for which timer event must be configured
05506   *                    This parameter can be one of the following values:
05507   *                    @arg HRTIM_EVENTCOUNTER_A
05508   *                    @arg HRTIM_EVENTCOUNTER_B
05509   * @note This function must be called before starting the timer
05510   * @retval HAL status
05511   */
05512 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,
05513                                                       uint32_t TimerIdx,
05514                                                       uint32_t EventCounter)
05515 {
05516   /* Check parameters */
05517   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05518   assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
05519
05520   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05521   {
05522      return HAL_BUSY;
05523   }
05524
05525   /* Process Locked */
05526   __HAL_LOCK(hhrtim);
05527
05528   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05529
05530   if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
05531   {
05532     SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES);
05533   }
05534   if ((EventCounter & HRTIM_EVENTCOUNTER_B)  != 0U)
05535   {
05536      SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,HRTIM_EEFR3_EEVBCRES);
05537   }
05538
05539   hhrtim->State = HAL_HRTIM_STATE_READY;
05540
05541   /* Process Unlocked */
05542   __HAL_UNLOCK(hhrtim);
05543
05544   return HAL_OK;
05545 }
05546
05547 /**
05548   * @brief  Configure the dead-time insertion feature for a timer
05549   * @param  hhrtim pointer to HAL HRTIM handle
05550   * @param  TimerIdx Timer index
05551   *                   This parameter can be one of the following values:
05552   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05553   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05554   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05555   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05556   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05557   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05558   * @param  pDeadTimeCfg pointer to the deadtime insertion configuration structure
05559   * @retval HAL status
05560   * @note This function must be called before starting the timer
05561   */
05562 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
05563                                            uint32_t TimerIdx,
05564                                            const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
05565 {
05566   uint32_t hrtim_dtr;
05567
05568   /* Check parameters */
05569   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05570   assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
05571   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
05572   assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
05573   assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
05574   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
05575   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
05576   assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
05577
05578   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05579   {
05580      return HAL_BUSY;
05581   }
05582
05583   /* Process Locked */
05584   __HAL_LOCK(hhrtim);
05585
05586   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05587
05588   /* Set timer deadtime configuration */
05589   hrtim_dtr  = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
05590   hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
05591   hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
05592   hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
05593   hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
05594   hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
05595   hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
05596   hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
05597   hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
05598
05599   /* Update the HRTIM registers */
05600   MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
05601                  HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
05602                  HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
05603                  HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
05604
05605   hhrtim->State = HAL_HRTIM_STATE_READY;
05606
05607   /* Process Unlocked */
05608   __HAL_UNLOCK(hhrtim);
05609
05610   return HAL_OK;
05611 }
05612
05613 /**
05614   * @brief  Configure the chopper mode feature for a timer
05615   * @param  hhrtim pointer to HAL HRTIM handle
05616   * @param  TimerIdx Timer index
05617   *                   This parameter can be one of the following values:
05618   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05619   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05620   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05621   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05622   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05623   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05624   * @param  pChopperModeCfg pointer to the chopper mode configuration structure
05625   * @retval HAL status
05626   * @note This function must be called before configuring the timer output(s)
05627   */
05628 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
05629                                               uint32_t TimerIdx,
05630                                               const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
05631 {
05632   uint32_t hrtim_chpr;
05633
05634   /* Check parameters */
05635   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
05636   assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
05637   assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
05638   assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
05639
05640   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05641   {
05642      return HAL_BUSY;
05643   }
05644
05645   /* Process Locked */
05646   __HAL_LOCK(hhrtim);
05647
05648   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05649
05650   /* Set timer choppe mode configuration */
05651   hrtim_chpr  = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
05652   hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
05653   hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
05654
05655   /* Update the HRTIM registers */
05656   MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
05657              (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
05658              hrtim_chpr);
05659
05660   hhrtim->State = HAL_HRTIM_STATE_READY;
05661
05662   /* Process Unlocked */
05663   __HAL_UNLOCK(hhrtim);
05664
05665   return HAL_OK;
05666 }
05667
05668 /**
05669   * @brief  Configure the burst DMA controller for a timer
05670   * @param  hhrtim pointer to HAL HRTIM handle
05671   * @param  TimerIdx Timer index
05672   *                  This parameter can be one of the following values:
05673   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05674   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05675   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05676   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05677   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05678   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05679   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05680   * @param  RegistersToUpdate registers to be written by DMA
05681   *                    This parameter can be any combination of the following values:
05682   *                    @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
05683   *                    @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
05684   *                    @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
05685   *                    @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
05686   *                    @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
05687   *                    @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
05688   *                    @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
05689   *                    @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
05690   *                    @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
05691   *                    @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
05692   *                    @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
05693   *                    @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
05694   *                    @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
05695   *                    @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
05696   *                    @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
05697   *                    @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
05698   *                    @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
05699   *                    @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
05700   *                    @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
05701   *                    @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
05702   *                    @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
05703   * @retval HAL status
05704   * @note This function must be called before starting the timer
05705   */
05706 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
05707                                            uint32_t TimerIdx,
05708                                            uint32_t RegistersToUpdate)
05709 {
05710   /* Check parameters */
05711   assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
05712
05713   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05714   {
05715      return HAL_BUSY;
05716   }
05717
05718   /* Process Locked */
05719   __HAL_LOCK(hhrtim);
05720
05721   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05722
05723   /* Set the burst DMA timer update register */
05724   switch (TimerIdx)
05725   {
05726   case HRTIM_TIMERINDEX_TIMER_A:
05727     {
05728       hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
05729       break;
05730     }
05731
05732   case HRTIM_TIMERINDEX_TIMER_B:
05733     {
05734       hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
05735       break;
05736     }
05737
05738   case HRTIM_TIMERINDEX_TIMER_C:
05739     {
05740       hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
05741       break;
05742     }
05743
05744   case HRTIM_TIMERINDEX_TIMER_D:
05745     {
05746       hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
05747       break;
05748     }
05749
05750   case HRTIM_TIMERINDEX_TIMER_E:
05751     {
05752       hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
05753       break;
05754     }
05755
05756   case HRTIM_TIMERINDEX_TIMER_F:
05757     {
05758       hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate;
05759       break;
05760     }
05761
05762   case HRTIM_TIMERINDEX_MASTER:
05763     {
05764       hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
05765       break;
05766     }
05767
05768   default:
05769    {
05770       hhrtim->State = HAL_HRTIM_STATE_ERROR;
05771
05772       /* Process Unlocked */
05773       __HAL_UNLOCK(hhrtim);
05774
05775       break;
05776     }
05777   }
05778
05779   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05780   {
05781      return HAL_ERROR;
05782   }
05783
05784   hhrtim->State = HAL_HRTIM_STATE_READY;
05785
05786   /* Process Unlocked */
05787   __HAL_UNLOCK(hhrtim);
05788
05789   return HAL_OK;
05790 }
05791
05792 /**
05793   * @brief  Configure the compare unit of a timer operating in waveform mode
05794   * @param  hhrtim pointer to HAL HRTIM handle
05795   * @param  TimerIdx Timer index
05796   *                   This parameter can be one of the following values:
05797   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
05798   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
05799   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
05800   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
05801   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
05802   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
05803   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
05804   * @param  CompareUnit Compare unit to configure
05805   *                    This parameter can be one of the following values:
05806   *                    @arg HRTIM_COMPAREUNIT_1: Compare unit 1
05807   *                    @arg HRTIM_COMPAREUNIT_2: Compare unit 2
05808   *                    @arg HRTIM_COMPAREUNIT_3: Compare unit 3
05809   *                    @arg HRTIM_COMPAREUNIT_4: Compare unit 4
05810   * @param  pCompareCfg pointer to the compare unit configuration structure
05811   * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
05812   *       application has to configure separately the capture unit. Capture unit
05813   *       to configure in that case depends on the compare unit auto delayed mode
05814   *       is applied to (see below):
05815   *         Auto delayed on output compare 2: capture unit 1 must be configured
05816   *         Auto delayed on output compare 4: capture unit 2 must be configured
05817   * @retval HAL status
05818   * @note This function must be called before starting the timer
05819   */
05820 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
05821                                                   uint32_t TimerIdx,
05822                                                   uint32_t CompareUnit,
05823                                                   const HRTIM_CompareCfgTypeDef* pCompareCfg)
05824 {
05825   /* Check parameters */
05826   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
05827
05828   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
05829   {
05830      return HAL_BUSY;
05831   }
05832
05833   /* Process Locked */
05834   __HAL_LOCK(hhrtim);
05835
05836   hhrtim->State = HAL_HRTIM_STATE_BUSY;
05837
05838   /* Configure the compare unit */
05839   if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
05840   {
05841     switch (CompareUnit)
05842     {
05843       case HRTIM_COMPAREUNIT_1:
05844         {
05845         hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
05846         break;
05847         }
05848
05849       case HRTIM_COMPAREUNIT_2:
05850         {
05851         hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
05852         break;
05853         }
05854
05855       case HRTIM_COMPAREUNIT_3:
05856         {
05857         hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
05858         break;
05859         }
05860
05861       case HRTIM_COMPAREUNIT_4:
05862         {
05863         hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
05864         break;
05865         }
05866
05867       default:
05868         {
05869         hhrtim->State = HAL_HRTIM_STATE_ERROR;
05870
05871         /* Process Unlocked */
05872         __HAL_UNLOCK(hhrtim);
05873
05874         break;
05875         }
05876     }
05877
05878     if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05879     {
05880      return HAL_ERROR;
05881     }
05882
05883   }
05884   else
05885   {
05886     switch (CompareUnit)
05887     {
05888     case HRTIM_COMPAREUNIT_1:
05889       {
05890         /* Set the compare value */
05891         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
05892         break;
05893       }
05894
05895     case HRTIM_COMPAREUNIT_2:
05896       {
05897         /* Check parameters */
05898         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
05899
05900         /* Set the compare value */
05901         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
05902
05903         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
05904         {
05905           /* Configure auto-delayed mode */
05906           /* DELCMP2 bitfield must be reset when reprogrammed from one value */
05907           /* to the other to reinitialize properly the auto-delayed mechanism */
05908           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
05909           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
05910
05911           /* Set the compare value for timeout compare unit (if any) */
05912           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
05913           {
05914             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
05915           }
05916           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
05917           {
05918             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
05919           }
05920           else
05921           {
05922             /* nothing to do */
05923           }
05924         }
05925         else
05926         {
05927           /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
05928           MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
05929         }
05930          break;
05931       }
05932
05933     case HRTIM_COMPAREUNIT_3:
05934       {
05935         /* Set the compare value */
05936         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
05937         break;
05938       }
05939
05940     case HRTIM_COMPAREUNIT_4:
05941       {
05942         /* Check parameters */
05943         assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
05944
05945         /* Set the compare value */
05946         hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
05947
05948         if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
05949         {
05950           /* Configure auto-delayed mode */
05951           /* DELCMP4 bitfield must be reset when reprogrammed from one value */
05952           /* to the other to reinitialize properly the auto-delayed mechanism */
05953           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
05954           hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
05955
05956           /* Set the compare value for timeout compare unit (if any) */
05957           if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
05958           {
05959             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
05960           }
05961           else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
05962           {
05963             hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
05964           }
05965           else
05966           {
05967             /* nothing to do */
05968           }
05969         }
05970         else
05971         {
05972           /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
05973           MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
05974         }
05975          break;
05976       }
05977
05978   default:
05979      {
05980       hhrtim->State = HAL_HRTIM_STATE_ERROR;
05981
05982       /* Process Unlocked */
05983       __HAL_UNLOCK(hhrtim);
05984
05985       break;
05986      }
05987    }
05988
05989    if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
05990    {
05991      return HAL_ERROR;
05992    }
05993
05994   }
05995   hhrtim->State = HAL_HRTIM_STATE_READY;
05996
05997   /* Process Unlocked */
05998   __HAL_UNLOCK(hhrtim);
05999
06000   return HAL_OK;
06001 }
06002
06003 /**
06004   * @brief  Configure the capture unit of a timer operating in waveform mode
06005   * @param  hhrtim pointer to HAL HRTIM handle
06006   * @param  TimerIdx Timer index
06007   *                   This parameter can be one of the following values:
06008   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06009   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06010   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06011   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06012   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06013   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
06014   * @param  CaptureUnit Capture unit to configure
06015   *                    This parameter can be one of the following values:
06016   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
06017   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
06018   * @param  pCaptureCfg pointer to the compare unit configuration structure
06019   * @retval HAL status
06020   * @note This function must be called before starting the timer
06021   */
06022 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
06023                                                   uint32_t TimerIdx,
06024                                                   uint32_t CaptureUnit,
06025                                                   const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
06026 {
06027   uint32_t Trigger;
06028   uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32);
06029
06030   /* Check parameters */
06031   assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, (uint32_t)(pCaptureCfg->Trigger)));
06032   assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger));
06033   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
06034
06035   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06036   {
06037      return HAL_BUSY;
06038   }
06039
06040   /* Process Locked */
06041   __HAL_LOCK(hhrtim);
06042
06043   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06044
06045   /* TimerF_Trigger is valid for setting other Timers than Timer F */
06046   if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A)
06047     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TA1SET_Pos ); }
06048   else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B)
06049     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TB1SET_Pos ); }
06050   else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C)
06051     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TC1SET_Pos ); }
06052   else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D)
06053     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TD1SET_Pos ); }
06054   else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E)
06055     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TE1SET_Pos ); }
06056   else
06057     { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); }
06058   /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */
06059
06060   /* Configure the capture unit */
06061
06062   switch (CaptureUnit)
06063   {
06064   case HRTIM_CAPTUREUNIT_1:
06065     {
06066       WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger);
06067       break;
06068     }
06069
06070   case HRTIM_CAPTUREUNIT_2:
06071     {
06072       WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger);
06073       break;
06074     }
06075
06076   default:
06077    {
06078       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06079
06080       /* Process Unlocked */
06081       __HAL_UNLOCK(hhrtim);
06082
06083       break;
06084     }
06085   }
06086
06087   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06088   {
06089      return HAL_ERROR;
06090   }
06091
06092
06093   hhrtim->State = HAL_HRTIM_STATE_READY;
06094
06095   /* Process Unlocked */
06096   __HAL_UNLOCK(hhrtim);
06097
06098   return HAL_OK;
06099 }
06100
06101 /**
06102   * @brief  Configure the output of a timer operating in waveform mode
06103   * @param  hhrtim pointer to HAL HRTIM handle
06104   * @param  TimerIdx Timer index
06105   *                   This parameter can be one of the following values:
06106   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06107   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06108   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06109   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06110   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06111   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
06112   * @param  Output Timer output
06113   *                    This parameter can be one of the following values:
06114   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06115   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06116   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06117   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06118   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06119   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06120   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06121   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06122   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06123   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06124   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
06125   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
06126   * @param  pOutputCfg pointer to the timer output configuration structure
06127   * @retval HAL status
06128   * @note This function must be called before configuring the timer and after
06129   *       configuring the deadtime insertion feature (if required).
06130   */
06131 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
06132                                                 uint32_t TimerIdx,
06133                                                 uint32_t Output,
06134                                                 const HRTIM_OutputCfgTypeDef * pOutputCfg)
06135 {
06136   /* Check parameters */
06137   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
06138   assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
06139   assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
06140   assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
06141   assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
06142   assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
06143   assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
06144
06145   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06146   {
06147      return HAL_BUSY;
06148   }
06149
06150   /* Process Locked */
06151   __HAL_LOCK(hhrtim);
06152
06153   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06154
06155   /* Configure the timer output */
06156   HRTIM_OutputConfig(hhrtim,
06157                      TimerIdx,
06158                      Output,
06159                      pOutputCfg);
06160
06161   hhrtim->State = HAL_HRTIM_STATE_READY;
06162
06163   /* Process Unlocked */
06164   __HAL_UNLOCK(hhrtim);
06165
06166   return HAL_OK;
06167 }
06168
06169 /**
06170   * @brief  Force the timer output to its active or inactive state
06171   * @param  hhrtim pointer to HAL HRTIM handle
06172   * @param  TimerIdx Timer index
06173   *                   This parameter can be one of the following values:
06174   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06175   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06176   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06177   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06178   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06179   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
06180   * @param  Output Timer output
06181   *                    This parameter can be one of the following values:
06182   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06183   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06184   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06185   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06186   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06187   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06188   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06189   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06190   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06191   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06192   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
06193   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
06194   * @param OutputLevel indicates whether the output is forced to its active or inactive level
06195   *                    This parameter can be one of the following values:
06196   *                    @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
06197   *                    @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
06198   * @retval HAL status
06199   * @note The 'software set/reset trigger' bit in the output set/reset registers
06200   *       is automatically reset by hardware
06201   */
06202 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
06203                                                    uint32_t TimerIdx,
06204                                                    uint32_t Output,
06205                                                    uint32_t OutputLevel)
06206 {
06207   /* Check parameters */
06208   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
06209   assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
06210
06211   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06212   {
06213      return HAL_BUSY;
06214   }
06215
06216   /* Process Locked */
06217   __HAL_LOCK(hhrtim);
06218
06219   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06220
06221   /* Force timer output level */
06222   switch (Output)
06223   {
06224   case HRTIM_OUTPUT_TA1:
06225   case HRTIM_OUTPUT_TB1:
06226   case HRTIM_OUTPUT_TC1:
06227   case HRTIM_OUTPUT_TD1:
06228   case HRTIM_OUTPUT_TE1:
06229   case HRTIM_OUTPUT_TF1:
06230     {
06231       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
06232       {
06233         /* Force output to its active state */
06234         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
06235       }
06236       else
06237       {
06238         /* Force output to its inactive state */
06239         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
06240       }
06241       break;
06242     }
06243
06244   case HRTIM_OUTPUT_TA2:
06245   case HRTIM_OUTPUT_TB2:
06246   case HRTIM_OUTPUT_TC2:
06247   case HRTIM_OUTPUT_TD2:
06248   case HRTIM_OUTPUT_TE2:
06249   case HRTIM_OUTPUT_TF2:
06250     {
06251       if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
06252       {
06253         /* Force output to its active state */
06254         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
06255       }
06256       else
06257       {
06258         /* Force output to its inactive state */
06259         SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
06260       }
06261       break;
06262     }
06263
06264   default:
06265     {
06266       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06267
06268       /* Process Unlocked */
06269       __HAL_UNLOCK(hhrtim);
06270
06271       break;
06272     }
06273   }
06274
06275   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06276   {
06277      return HAL_ERROR;
06278   }
06279
06280   hhrtim->State = HAL_HRTIM_STATE_READY;
06281
06282   /* Process Unlocked */
06283   __HAL_UNLOCK(hhrtim);
06284
06285   return HAL_OK;
06286 }
06287
06288 /**
06289   * @brief  Enable the generation of the waveform signal on the designated output(s)
06290   *         Outputs can be combined (ORed) to allow for simultaneous output enabling.
06291   * @param  hhrtim pointer to HAL HRTIM handle
06292   * @param  OutputsToStart Timer output(s) to enable
06293   *                    This parameter can be any combination of the following values:
06294   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06295   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06296   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06297   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06298   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06299   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06300   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06301   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06302   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06303   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06304   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
06305   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
06306   * @retval HAL status
06307   */
06308 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
06309                                                 uint32_t OutputsToStart)
06310 {
06311    /* Check the parameters */
06312   assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
06313
06314   /* Process Locked */
06315   __HAL_LOCK(hhrtim);
06316
06317   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06318
06319   /* Enable the HRTIM outputs */
06320   hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
06321
06322   hhrtim->State = HAL_HRTIM_STATE_READY;
06323
06324   /* Process Unlocked */
06325   __HAL_UNLOCK(hhrtim);
06326
06327   return HAL_OK;
06328 }
06329
06330 /**
06331   * @brief  Disable the generation of the waveform signal on the designated output(s)
06332   *         Outputs can be combined (ORed) to allow for simultaneous output disabling.
06333   * @param  hhrtim pointer to HAL HRTIM handle
06334   * @param  OutputsToStop Timer output(s) to disable
06335   *                    This parameter can be any combination of the following values:
06336   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
06337   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
06338   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
06339   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
06340   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
06341   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
06342   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
06343   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
06344   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
06345   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
06346   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
06347   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
06348   * @retval HAL status
06349   */
06350 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
06351                                                uint32_t OutputsToStop)
06352 {
06353    /* Check the parameters */
06354   assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
06355
06356   /* Process Locked */
06357   __HAL_LOCK(hhrtim);
06358
06359   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06360
06361   /* Enable the HRTIM outputs */
06362   hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
06363
06364   hhrtim->State = HAL_HRTIM_STATE_READY;
06365
06366   /* Process Unlocked */
06367   __HAL_UNLOCK(hhrtim);
06368
06369   return HAL_OK;
06370 }
06371
06372 /**
06373   * @brief  Start the counter of the designated timer(s) operating in waveform mode
06374   *         Timers can be combined (ORed) to allow for simultaneous counter start.
06375   * @param  hhrtim pointer to HAL HRTIM handle
06376   * @param  Timers Timer counter(s) to start
06377   *                   This parameter can be any combination of the following values:
06378   *                   @arg HRTIM_TIMERID_MASTER
06379   *                   @arg HRTIM_TIMERID_TIMER_A
06380   *                   @arg HRTIM_TIMERID_TIMER_B
06381   *                   @arg HRTIM_TIMERID_TIMER_C
06382   *                   @arg HRTIM_TIMERID_TIMER_D
06383   *                   @arg HRTIM_TIMERID_TIMER_E
06384   *                   @arg HRTIM_TIMERID_TIMER_F
06385   * @retval HAL status
06386   */
06387 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
06388                                                  uint32_t Timers)
06389 {
06390   /* Check the parameters */
06391   assert_param(IS_HRTIM_TIMERID(Timers));
06392
06393   /* Process Locked */
06394   __HAL_LOCK(hhrtim);
06395
06396   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06397
06398   /* Enable timer(s) counter */
06399   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
06400
06401   hhrtim->State = HAL_HRTIM_STATE_READY;
06402
06403   /* Process Unlocked */
06404   __HAL_UNLOCK(hhrtim);
06405
06406   return HAL_OK;
06407 }
06408
06409 /**
06410   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
06411   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
06412   * @param  hhrtim pointer to HAL HRTIM handle
06413   * @param  Timers Timer counter(s) to stop
06414   *                   This parameter can be any combination of the following values:
06415   *                   @arg HRTIM_TIMERID_MASTER
06416   *                   @arg HRTIM_TIMERID_TIMER_A
06417   *                   @arg HRTIM_TIMERID_TIMER_B
06418   *                   @arg HRTIM_TIMERID_TIMER_C
06419   *                   @arg HRTIM_TIMERID_TIMER_D
06420   *                   @arg HRTIM_TIMERID_TIMER_E
06421   *                   @arg HRTIM_TIMERID_TIMER_F
06422   * @retval HAL status
06423   * @note The counter of a timer is stopped only if all timer outputs are disabled
06424   */
06425 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
06426                                                 uint32_t Timers)
06427 {
06428   /* Check the parameters */
06429   assert_param(IS_HRTIM_TIMERID(Timers));
06430
06431   /* Process Locked */
06432   __HAL_LOCK(hhrtim);
06433
06434   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06435
06436   /* Disable timer(s) counter */
06437   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
06438
06439   hhrtim->State = HAL_HRTIM_STATE_READY;
06440
06441   /* Process Unlocked */
06442   __HAL_UNLOCK(hhrtim);
06443
06444   return HAL_OK;
06445 }
06446
06447 /**
06448   * @brief  Start the counter of the designated timer(s) operating in waveform mode
06449   *         Timers can be combined (ORed) to allow for simultaneous counter start.
06450   * @param  hhrtim pointer to HAL HRTIM handle
06451   * @param  Timers Timer counter(s) to start
06452   *                   This parameter can be any combination of the following values:
06453   *                   @arg HRTIM_TIMERID_MASTER
06454   *                   @arg HRTIM_TIMERID_TIMER_A
06455   *                   @arg HRTIM_TIMERID_TIMER_B
06456   *                   @arg HRTIM_TIMERID_TIMER_C
06457   *                   @arg HRTIM_TIMERID_TIMER_D
06458   *                   @arg HRTIM_TIMERID_TIMER_E
06459   *                   @arg HRTIM_TIMERID_TIMER_F
06460   * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
06461   *       to the timers to start are enabled within this function.
06462   *       Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
06463   *       function.
06464   * @retval HAL status
06465   */
06466 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
06467                                                     uint32_t Timers)
06468 {
06469   uint8_t timer_idx;
06470
06471   /* Check the parameters */
06472   assert_param(IS_HRTIM_TIMERID(Timers));
06473
06474   /* Process Locked */
06475   __HAL_LOCK(hhrtim);
06476
06477   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06478
06479   /* Enable HRTIM interrupts (if required) */
06480   __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
06481
06482   /* Enable master timer related interrupts (if required) */
06483   if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
06484   {
06485     __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
06486                                  hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
06487   }
06488
06489   /* Enable timing unit related interrupts (if required) */
06490   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
06491        timer_idx < HRTIM_TIMERINDEX_MASTER ;
06492        timer_idx++)
06493   {
06494     if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
06495     {
06496       __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
06497                                   timer_idx,
06498                                   hhrtim->TimerParam[timer_idx].InterruptRequests);
06499     }
06500   }
06501
06502   /* Enable timer(s) counter */
06503   hhrtim->Instance->sMasterRegs.MCR |= (Timers);
06504
06505   hhrtim->State = HAL_HRTIM_STATE_READY;
06506
06507   /* Process Unlocked */
06508   __HAL_UNLOCK(hhrtim);
06509
06510   return HAL_OK;}
06511
06512 /**
06513   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
06514   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
06515   * @param  hhrtim pointer to HAL HRTIM handle
06516   * @param  Timers Timer counter(s) to stop
06517   *                   This parameter can be any combination of the following values:
06518   *                   @arg HRTIM_TIMERID_MASTER
06519   *                   @arg HRTIM_TIMERID_TIMER_A
06520   *                   @arg HRTIM_TIMERID_TIMER_B
06521   *                   @arg HRTIM_TIMERID_TIMER_C
06522   *                   @arg HRTIM_TIMERID_TIMER_D
06523   *                   @arg HRTIM_TIMERID_TIMER_E
06524   *                   @arg HRTIM_TIMERID_TIMER_F
06525   * @retval HAL status
06526   * @note The counter of a timer is stopped only if all timer outputs are disabled
06527   * @note All enabled timer related interrupts are disabled.
06528   */
06529 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
06530                                                    uint32_t Timers)
06531 {
06532   /* ++ WA */
06533   __IO uint32_t delai = (uint32_t)(0x17FU);
06534   /* -- WA */
06535
06536   uint8_t timer_idx;
06537
06538   /* Check the parameters */
06539   assert_param(IS_HRTIM_TIMERID(Timers));
06540
06541   /* Process Locked */
06542   __HAL_LOCK(hhrtim);
06543
06544   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06545
06546   /* Disable HRTIM interrupts (if required) */
06547   __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
06548
06549   /* Disable master timer related interrupts (if required) */
06550   if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
06551   {
06552     /* Interrupts enable flag must be cleared one by one */
06553     __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
06554   }
06555
06556   /* Disable timing unit related interrupts (if required) */
06557   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
06558        timer_idx < HRTIM_TIMERINDEX_MASTER ;
06559        timer_idx++)
06560   {
06561     if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
06562     {
06563       __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
06564     }
06565   }
06566
06567   /* ++ WA */
06568   do { delai--; } while (delai != 0U);
06569   /* -- WA */
06570
06571   /* Disable timer(s) counter */
06572   hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
06573
06574   hhrtim->State = HAL_HRTIM_STATE_READY;
06575
06576   /* Process Unlocked */
06577   __HAL_UNLOCK(hhrtim);
06578
06579   return HAL_OK;
06580 }
06581
06582 /**
06583   * @brief  Start the counter of the designated timer(s) operating in waveform mode
06584   *         Timers can be combined (ORed) to allow for simultaneous counter start.
06585   * @param  hhrtim pointer to HAL HRTIM handle
06586   * @param  Timers Timer counter(s) to start
06587   *                   This parameter can be any combination of the following values:
06588   *                   @arg HRTIM_TIMERID_MASTER
06589   *                   @arg HRTIM_TIMERID_TIMER_A
06590   *                   @arg HRTIM_TIMERID_TIMER_B
06591   *                   @arg HRTIM_TIMERID_TIMER_C
06592   *                   @arg HRTIM_TIMERID_TIMER_D
06593   *                   @arg HRTIM_TIMERID_TIMER_E
06594   *                   @arg HRTIM_TIMERID_TIMER_F
06595   * @retval HAL status
06596   * @note This function enables the dma request(s) mentioned in the timer
06597   *       configuration data structure for every timers to start.
06598   * @note The source memory address, the destination memory address and the
06599   *       size of each DMA transfer are specified at timer configuration time
06600   *       (see HAL_HRTIM_WaveformTimerConfig)
06601   */
06602 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
06603                                                      uint32_t Timers)
06604 {
06605   uint8_t timer_idx;
06606   DMA_HandleTypeDef * hdma;
06607
06608   /* Check the parameters */
06609   assert_param(IS_HRTIM_TIMERID(Timers));
06610
06611   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06612   {
06613      return HAL_BUSY;
06614   }
06615
06616   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06617
06618   /* Process Locked */
06619   __HAL_LOCK(hhrtim);
06620
06621   if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
06622       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
06623   {
06624       /* Set the DMA error callback */
06625       hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
06626
06627       /* Set the DMA transfer completed callback */
06628       hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
06629
06630       /* Enable the DMA channel */
06631       if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
06632                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
06633                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
06634                        hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
06635     {
06636             hhrtim->State = HAL_HRTIM_STATE_ERROR;
06637
06638             /* Process Unlocked */
06639             __HAL_UNLOCK(hhrtim);
06640
06641             return HAL_ERROR;
06642         }
06643
06644       /* Enable the timer DMA request */
06645       __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
06646                                    hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
06647   }
06648
06649   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
06650        timer_idx < HRTIM_TIMERINDEX_MASTER ;
06651        timer_idx++)
06652   {
06653     if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
06654          (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
06655     {
06656       /* Get the timer DMA handler */
06657       hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
06658
06659       if (hdma == NULL)
06660       {
06661         hhrtim->State = HAL_HRTIM_STATE_ERROR;
06662
06663         /* Process Unlocked */
06664         __HAL_UNLOCK(hhrtim);
06665
06666         return HAL_ERROR;
06667       }
06668
06669        /* Set the DMA error callback */
06670       hdma->XferErrorCallback = HRTIM_DMAError ;
06671
06672       /* Set the DMA transfer completed callback */
06673       hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
06674
06675       /* Enable the DMA channel */
06676       if (HAL_DMA_Start_IT(hdma,
06677                        hhrtim->TimerParam[timer_idx].DMASrcAddress,
06678                        hhrtim->TimerParam[timer_idx].DMADstAddress,
06679                        hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
06680     {
06681               hhrtim->State = HAL_HRTIM_STATE_ERROR;
06682
06683               /* Process Unlocked */
06684               __HAL_UNLOCK(hhrtim);
06685
06686               return HAL_ERROR;
06687         }
06688
06689       /* Enable the timer DMA request */
06690       __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
06691                                    timer_idx,
06692                                    hhrtim->TimerParam[timer_idx].DMARequests);
06693     }
06694   }
06695
06696   /* Enable the timer counter */
06697   __HAL_HRTIM_ENABLE(hhrtim, Timers);
06698
06699   hhrtim->State = HAL_HRTIM_STATE_READY;
06700
06701   /* Process Unlocked */
06702   __HAL_UNLOCK(hhrtim);
06703
06704   return HAL_OK;
06705 }
06706
06707 /**
06708   * @brief  Stop the counter of the designated timer(s) operating in waveform mode
06709   *         Timers can be combined (ORed) to allow for simultaneous counter stop.
06710   * @param  hhrtim pointer to HAL HRTIM handle
06711   * @param  Timers Timer counter(s) to stop
06712   *                   This parameter can be any combination of the following values:
06713   *                   @arg HRTIM_TIMERID_MASTER
06714   *                   @arg HRTIM_TIMERID_TIMER_A
06715   *                   @arg HRTIM_TIMERID_TIMER_B
06716   *                   @arg HRTIM_TIMERID_TIMER_C
06717   *                   @arg HRTIM_TIMERID_TIMER_D
06718   *                   @arg HRTIM_TIMERID_TIMER_E
06719   *                   @arg HRTIM_TIMERID_TIMER_F
06720   * @retval HAL status
06721   * @note  The counter of a timer is stopped only if all timer outputs are disabled
06722   * @note  All enabled timer related DMA requests are disabled.
06723   */
06724 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
06725                                                     uint32_t Timers)
06726 {
06727   uint8_t timer_idx;
06728
06729   /* Check the parameters */
06730   assert_param(IS_HRTIM_TIMERID(Timers));
06731
06732   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06733
06734   if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
06735       (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
06736   {
06737     /* Disable the DMA */
06738     if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
06739     {
06740           hhrtim->State = HAL_HRTIM_STATE_ERROR;
06741     }
06742     else
06743     {
06744           hhrtim->State = HAL_HRTIM_STATE_READY;
06745           /* Disable the DMA request(s) */
06746           __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
06747                                          hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
06748     }
06749   }
06750
06751   for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
06752        timer_idx < HRTIM_TIMERINDEX_MASTER ;
06753        timer_idx++)
06754   {
06755     if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
06756         (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
06757     {
06758       /* Get the timer DMA handler */
06759       /* Disable the DMA */
06760       if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
06761       {
06762         hhrtim->State = HAL_HRTIM_STATE_ERROR;
06763       }
06764       else
06765       {
06766         hhrtim->State = HAL_HRTIM_STATE_READY;
06767
06768         /* Disable the DMA request(s) */
06769         __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
06770                                       timer_idx,
06771                                       hhrtim->TimerParam[timer_idx].DMARequests);
06772       }
06773     }
06774   }
06775
06776   /* Disable the timer counter */
06777   __HAL_HRTIM_DISABLE(hhrtim, Timers);
06778
06779   if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
06780   {
06781       return HAL_ERROR;
06782   }
06783   else
06784   {
06785       return HAL_OK;
06786   }
06787 }
06788
06789 /**
06790   * @brief  Enable or disables the HRTIM burst mode controller.
06791   * @param  hhrtim pointer to HAL HRTIM handle
06792   * @param  Enable Burst mode controller enabling
06793   *                    This parameter can be one of the following values:
06794   *                    @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
06795   *                    @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
06796   * @retval HAL status
06797   * @note This function must be called after starting the timer(s)
06798   */
06799 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
06800                                          uint32_t Enable)
06801 {
06802   /* Check parameters */
06803   assert_param(IS_HRTIM_BURSTMODECTL(Enable));
06804
06805   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06806   {
06807      return HAL_BUSY;
06808   }
06809
06810   /* Process Locked */
06811   __HAL_LOCK(hhrtim);
06812
06813   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06814
06815   /* Enable/Disable the burst mode controller */
06816   MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
06817
06818   hhrtim->State = HAL_HRTIM_STATE_READY;
06819
06820   /* Process Unlocked */
06821   __HAL_UNLOCK(hhrtim);
06822
06823   return HAL_OK;
06824 }
06825
06826 /**
06827   * @brief  Trig the burst mode operation.
06828   * @param  hhrtim pointer to HAL HRTIM handle
06829   * @retval HAL status
06830   */
06831 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
06832 {
06833   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06834   {
06835      return HAL_BUSY;
06836   }
06837
06838   /* Process Locked */
06839   __HAL_LOCK(hhrtim);
06840
06841   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06842
06843   /* Software trigger of the burst mode controller */
06844   SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
06845
06846   hhrtim->State = HAL_HRTIM_STATE_READY;
06847
06848   /* Process Unlocked */
06849   __HAL_UNLOCK(hhrtim);
06850
06851   return HAL_OK;
06852 }
06853
06854 /**
06855   * @brief  Trig a software capture on the designed capture unit
06856   * @param  hhrtim pointer to HAL HRTIM handle
06857   * @param  TimerIdx Timer index
06858   *                   This parameter can be one of the following values:
06859   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
06860   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
06861   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
06862   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
06863   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
06864   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
06865   * @param  CaptureUnit Capture unit to trig
06866   *                    This parameter can be one of the following values:
06867   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
06868   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
06869   * @retval HAL status
06870   * @note The 'software capture' bit in the capure configuration register is
06871   *       automatically reset by hardware
06872   */
06873 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
06874                                             uint32_t TimerIdx,
06875                                             uint32_t CaptureUnit)
06876 {
06877   /* Check parameters */
06878   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
06879   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
06880
06881   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06882   {
06883      return HAL_BUSY;
06884   }
06885
06886   /* Process Locked */
06887   __HAL_LOCK(hhrtim);
06888
06889   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06890
06891   /* Force a software capture on concerned capture unit */
06892   switch (CaptureUnit)
06893   {
06894   case HRTIM_CAPTUREUNIT_1:
06895     {
06896       SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
06897       break;
06898     }
06899
06900   case HRTIM_CAPTUREUNIT_2:
06901     {
06902       SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
06903       break;
06904     }
06905
06906   default:
06907     {
06908       hhrtim->State = HAL_HRTIM_STATE_ERROR;
06909
06910       /* Process Unlocked */
06911       __HAL_UNLOCK(hhrtim);
06912
06913     break;
06914     }
06915   }
06916
06917   if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
06918   {
06919      return HAL_ERROR;
06920   }
06921
06922   hhrtim->State = HAL_HRTIM_STATE_READY;
06923
06924   /* Process Unlocked */
06925   __HAL_UNLOCK(hhrtim);
06926
06927   return HAL_OK;
06928 }
06929
06930 /**
06931   * @brief  Trig the update of the registers of one or several timers
06932   * @param  hhrtim pointer to HAL HRTIM handle
06933   * @param  Timers timers concerned with the software register update
06934   *                   This parameter can be any combination of the following values:
06935   *                   @arg HRTIM_TIMERUPDATE_MASTER
06936   *                   @arg HRTIM_TIMERUPDATE_A
06937   *                   @arg HRTIM_TIMERUPDATE_B
06938   *                   @arg HRTIM_TIMERUPDATE_C
06939   *                   @arg HRTIM_TIMERUPDATE_D
06940   *                   @arg HRTIM_TIMERUPDATE_E
06941   *                   @arg HRTIM_TIMERUPDATE_F
06942   * @retval HAL status
06943   * @note The 'software update' bits in the HRTIM control register 2 register are
06944   *       automatically reset by hardware
06945   */
06946 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
06947                                            uint32_t Timers)
06948 {
06949   /* Check parameters */
06950   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
06951
06952   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06953   {
06954      return HAL_BUSY;
06955   }
06956
06957   /* Process Locked */
06958   __HAL_LOCK(hhrtim);
06959
06960   hhrtim->State = HAL_HRTIM_STATE_BUSY;
06961
06962   /* Force timer(s) registers update */
06963   hhrtim->Instance->sCommonRegs.CR2 |= Timers;
06964
06965   hhrtim->State = HAL_HRTIM_STATE_READY;
06966
06967   /* Process Unlocked */
06968   __HAL_UNLOCK(hhrtim);
06969
06970   return HAL_OK;
06971 }
06972
06973 /**
06974   * @brief  Swap the Timer  outputs
06975   * @param  hhrtim pointer to HAL HRTIM handle
06976   * @param  Timers timers concerned with the software register update
06977   *                   This parameter can be any combination of the following values:
06978   *                   @arg HRTIM_TIMERSWAP_A
06979   *                   @arg HRTIM_TIMERSWAP_B
06980   *                   @arg HRTIM_TIMERSWAP_C
06981   *                   @arg HRTIM_TIMERSWAP_D
06982   *                   @arg HRTIM_TIMERSWAP_E
06983   *                   @arg HRTIM_TIMERSWAP_F
06984   * @retval HAL status
06985   * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1)
06986   */
06987 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,
06988                                            uint32_t Timers)
06989 {
06990   /* Check parameters */
06991   assert_param(IS_HRTIM_TIMERSWAP(Timers));
06992
06993   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
06994   {
06995      return HAL_BUSY;
06996   }
06997
06998   /* Process Locked */
06999   __HAL_LOCK(hhrtim);
07000
07001   hhrtim->State = HAL_HRTIM_STATE_BUSY;
07002
07003   /* Force timer(s) registers update */
07004   hhrtim->Instance->sCommonRegs.CR2 |= Timers;
07005
07006   hhrtim->State = HAL_HRTIM_STATE_READY;
07007
07008   /* Process Unlocked */
07009   __HAL_UNLOCK(hhrtim);
07010
07011   return HAL_OK;
07012 }
07013
07014 /**
07015   * @brief  Trig the reset of one or several timers
07016   * @param  hhrtim pointer to HAL HRTIM handle
07017   * @param  Timers timers concerned with the software counter reset
07018   *                   This parameter can be any combination of the following values:
07019   *                   @arg HRTIM_TIMERRESET_MASTER
07020   *                   @arg HRTIM_TIMERRESET_TIMER_A
07021   *                   @arg HRTIM_TIMERRESET_TIMER_B
07022   *                   @arg HRTIM_TIMERRESET_TIMER_C
07023   *                   @arg HRTIM_TIMERRESET_TIMER_D
07024   *                   @arg HRTIM_TIMERRESET_TIMER_E
07025   *                   @arg HRTIM_TIMERRESET_TIMER_F
07026   * @retval HAL status
07027   * @note The 'software reset' bits in the HRTIM control register 2  are
07028   *       automatically reset by hardware
07029   */
07030 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
07031                                           uint32_t Timers)
07032 {
07033   /* Check parameters */
07034   assert_param(IS_HRTIM_TIMERRESET(Timers));
07035
07036   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
07037   {
07038      return HAL_BUSY;
07039   }
07040
07041   /* Process Locked */
07042   __HAL_LOCK(hhrtim);
07043
07044   hhrtim->State = HAL_HRTIM_STATE_BUSY;
07045
07046   /* Force timer(s) registers reset */
07047   hhrtim->Instance->sCommonRegs.CR2 = Timers;
07048
07049   hhrtim->State = HAL_HRTIM_STATE_READY;
07050
07051   /* Process Unlocked */
07052   __HAL_UNLOCK(hhrtim);
07053
07054   return HAL_OK;
07055 }
07056
07057 /**
07058   * @brief Swap the output of one or several timers
07059   * @param hhrtim: pointer to HAL HRTIM handle
07060   * @param Timers: timers concerned with the software register update
07061   * This parameter can be any combination of the following values:
07062   * @arg HRTIM_TIMERSWAP_A
07063   * @arg HRTIM_TIMERSWAP_B
07064   * @arg HRTIM_TIMERSWAP_C
07065   * @arg HRTIM_TIMERSWAP_D
07066   * @arg HRTIM_TIMERSWAP_E
07067   * @arg HRTIM_TIMERSWAP_F
07068   * @retval HAL status
07069   */
07070 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,
07071                                           uint32_t Timers)
07072 {
07073    /* Check parameters */
07074    assert_param(IS_HRTIM_TIMERSWAP(Timers));
07075
07076    if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
07077    {
07078      return HAL_BUSY;
07079    }
07080
07081    /* Process Locked */
07082    __HAL_LOCK(hhrtim);
07083
07084    hhrtim->State = HAL_HRTIM_STATE_BUSY;
07085
07086    /* Force timer(s) registers update */
07087    hhrtim->Instance->sCommonRegs.CR2 |= Timers;
07088
07089    hhrtim->State = HAL_HRTIM_STATE_READY;
07090
07091    /* Process Unlocked */
07092    __HAL_UNLOCK(hhrtim);
07093
07094    return HAL_OK;
07095 }
07096
07097 /**
07098   * @brief Un-swap the output of one or several timers
07099   * @param hhrtim: pointer to HAL HRTIM handle
07100   * @param Timers: timers concerned with the software register update
07101   * This parameter can be any combination of the following values:
07102   * @arg HRTIM_TIMERSWAP_A
07103   * @arg HRTIM_TIMERSWAP_B
07104   * @arg HRTIM_TIMERSWAP_C
07105   * @arg HRTIM_TIMERSWAP_D
07106   * @arg HRTIM_TIMERSWAP_E
07107   * @arg HRTIM_TIMERSWAP_F
07108   * @retval HAL status
07109   */
07110 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,
07111                                           uint32_t Timers)
07112 {
07113    /* Check parameters */
07114    assert_param(IS_HRTIM_TIMERSWAP(Timers));
07115
07116    if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
07117    {
07118      return HAL_BUSY;
07119    }
07120
07121    /* Process Locked */
07122    __HAL_LOCK(hhrtim);
07123
07124    hhrtim->State = HAL_HRTIM_STATE_BUSY;
07125
07126    /* Force timer(s) registers update */
07127    hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers);
07128
07129    hhrtim->State = HAL_HRTIM_STATE_READY;
07130
07131    /* Process Unlocked */
07132    __HAL_UNLOCK(hhrtim);
07133
07134    return HAL_OK;
07135 }
07136
07137 /**
07138   * @brief  Start a burst DMA operation to update HRTIM control registers content
07139   * @param  hhrtim pointer to HAL HRTIM handle
07140   * @param  TimerIdx Timer index
07141   *                   This parameter can be one of the following values:
07142   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
07143   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07144   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07145   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07146   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07147   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07148   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07149   * @param  BurstBufferAddress address of the buffer the HRTIM control registers
07150   *                             content will be updated from.
07151   * @param  BurstBufferLength size (in WORDS) of the burst buffer.
07152   * @retval HAL status
07153   * @note The TimerIdx parameter determines the dma channel to be used by the
07154   *       DMA burst controller (see below)
07155   *       HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
07156   *       HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
07157   *       HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
07158   *       HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
07159   *       HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
07160   *       HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
07161   *       HRTIM_TIMERINDEX_TIMER_F: DMA channel 8 is used by the DMA burst controller
07162   */
07163 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
07164                                              uint32_t TimerIdx,
07165                                              uint32_t BurstBufferAddress,
07166                                              uint32_t BurstBufferLength)
07167 {
07168   DMA_HandleTypeDef * hdma;
07169
07170   /* Check the parameters */
07171   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
07172
07173   if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
07174   {
07175      return HAL_BUSY;
07176   }
07177   if(hhrtim->State == HAL_HRTIM_STATE_READY)
07178   {
07179     if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
07180     {
07181       return HAL_ERROR;
07182     }
07183     else
07184     {
07185       hhrtim->State = HAL_HRTIM_STATE_BUSY;
07186     }
07187   }
07188
07189   /* Process Locked */
07190   __HAL_LOCK(hhrtim);
07191
07192   /* Get the timer DMA handler */
07193   hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
07194
07195   if (hdma == NULL)
07196   {
07197     hhrtim->State = HAL_HRTIM_STATE_ERROR;
07198
07199     /* Process Unlocked */
07200     __HAL_UNLOCK(hhrtim);
07201
07202     return HAL_ERROR;
07203   }
07204
07205   /* Set the DMA transfer completed callback */
07206   hdma->XferCpltCallback = HRTIM_BurstDMACplt;
07207
07208   /* Set the DMA error callback */
07209   hdma->XferErrorCallback = HRTIM_DMAError ;
07210
07211   /* Enable the DMA channel */
07212   if (HAL_DMA_Start_IT(hdma,
07213                    BurstBufferAddress,
07214                    (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
07215                    BurstBufferLength) != HAL_OK)
07216     {
07217            hhrtim->State = HAL_HRTIM_STATE_ERROR;
07218
07219            /* Process Unlocked */
07220            __HAL_UNLOCK(hhrtim);
07221
07222            return HAL_ERROR;
07223         }
07224
07225   hhrtim->State = HAL_HRTIM_STATE_READY;
07226
07227   /* Process Unlocked */
07228   __HAL_UNLOCK(hhrtim);
07229
07230   return HAL_OK;
07231 }
07232
07233 /**
07234   * @brief  Enable the transfer from preload to active registers for one
07235   *         or several timing units (including master timer).
07236   * @param  hhrtim pointer to HAL HRTIM handle
07237   * @param  Timers Timer(s) concerned by the register preload enabling command
07238   *                   This parameter can be any combination of the following values:
07239   *                   @arg HRTIM_TIMERUPDATE_MASTER
07240   *                   @arg HRTIM_TIMERUPDATE_A
07241   *                   @arg HRTIM_TIMERUPDATE_B
07242   *                   @arg HRTIM_TIMERUPDATE_C
07243   *                   @arg HRTIM_TIMERUPDATE_D
07244   *                   @arg HRTIM_TIMERUPDATE_E
07245   *                   @arg HRTIM_TIMERUPDATE_E
07246   * @retval HAL status
07247   */
07248 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
07249                                           uint32_t Timers)
07250 {
07251    /* Check the parameters */
07252   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
07253
07254   /* Process Locked */
07255   __HAL_LOCK(hhrtim);
07256
07257   hhrtim->State = HAL_HRTIM_STATE_BUSY;
07258
07259   /* Enable timer(s) registers update */
07260   hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
07261
07262   hhrtim->State = HAL_HRTIM_STATE_READY;
07263
07264   /* Process Unlocked */
07265   __HAL_UNLOCK(hhrtim);
07266
07267   return HAL_OK;
07268   }
07269
07270 /**
07271   * @brief  Disable the transfer from preload to active registers for one
07272   *         or several timing units (including master timer).
07273   * @param  hhrtim pointer to HAL HRTIM handle
07274   * @param  Timers Timer(s) concerned by the register preload disabling command
07275   *                   This parameter can be any combination of the following values:
07276   *                   @arg HRTIM_TIMERUPDATE_MASTER
07277   *                   @arg HRTIM_TIMERUPDATE_A
07278   *                   @arg HRTIM_TIMERUPDATE_B
07279   *                   @arg HRTIM_TIMERUPDATE_C
07280   *                   @arg HRTIM_TIMERUPDATE_D
07281   *                   @arg HRTIM_TIMERUPDATE_E
07282   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07283   * @retval HAL status
07284   */
07285 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
07286                                           uint32_t Timers)
07287 {
07288   /* Check the parameters */
07289   assert_param(IS_HRTIM_TIMERUPDATE(Timers));
07290
07291   /* Process Locked */
07292   __HAL_LOCK(hhrtim);
07293
07294   hhrtim->State = HAL_HRTIM_STATE_BUSY;
07295
07296   /* Enable timer(s) registers update */
07297   hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
07298
07299   hhrtim->State = HAL_HRTIM_STATE_READY;
07300
07301   /* Process Unlocked */
07302   __HAL_UNLOCK(hhrtim);
07303
07304   return HAL_OK;
07305   }
07306
07307 /**
07308   * @}
07309   */
07310
07311 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
07312  *  @brief    Peripheral State functions
07313 @verbatim
07314  ===============================================================================
07315               ##### Peripheral State functions #####
07316  ===============================================================================
07317     [..]  This section provides functions used to get HRTIM or HRTIM timer
07318           specific information:
07319       (+) Get HRTIM HAL state
07320       (+) Get captured value
07321       (+) Get HRTIM timer output level
07322       (+) Get HRTIM timer output state
07323       (+) Get delayed protection status
07324       (+) Get burst status
07325       (+) Get current push-pull status
07326       (+) Get idle push-pull status
07327
07328 @endverbatim
07329   * @{
07330   */
07331
07332 /**
07333   * @brief  Return the HRTIM HAL state
07334   * @param  hhrtim pointer to HAL HRTIM handle
07335   * @retval HAL state
07336   */
07337 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
07338 {
07339   /* Return HRTIM state */
07340   return hhrtim->State;
07341 }
07342
07343 /**
07344   * @brief  Return actual value of the capture register of the designated capture unit
07345   * @param  hhrtim pointer to HAL HRTIM handle
07346   * @param  TimerIdx Timer index
07347   *                   This parameter can be one of the following values:
07348   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07349   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07350   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07351   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07352   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07353   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07354   * @param  CaptureUnit Capture unit to trig
07355   *                    This parameter can be one of the following values:
07356   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
07357   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
07358   * @retval Captured value
07359   */
07360 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
07361                                     uint32_t TimerIdx,
07362                                     uint32_t CaptureUnit)
07363 {
07364   uint32_t captured_value;
07365
07366   /* Check parameters */
07367   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
07368   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
07369
07370   /* Read captured value */
07371   switch (CaptureUnit)
07372   {
07373   case HRTIM_CAPTUREUNIT_1:
07374     {
07375       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU;
07376       break;
07377     }
07378
07379   case HRTIM_CAPTUREUNIT_2:
07380     {
07381       captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU;
07382       break;
07383     }
07384
07385   default:
07386    {
07387        captured_value = 0xFFFFFFFFUL;
07388       break;
07389     }
07390
07391   }
07392
07393   return captured_value;
07394 }
07395
07396 /**
07397   * @brief  Return actual value and direction of the capture register of the designated capture unit
07398   * @param  hhrtim pointer to HAL HRTIM handle
07399   * @param  TimerIdx Timer index
07400   *                   This parameter can be one of the following values:
07401   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07402   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07403   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07404   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07405   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07406   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07407   * @param  CaptureUnit Capture unit to trig
07408   *                    This parameter can be one of the following values:
07409   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
07410   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
07411   * @retval captured value and direction structure
07412   */
07413 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim,
07414                                     uint32_t TimerIdx,
07415                                     uint32_t CaptureUnit)
07416 {
07417   uint32_t tmp;
07418   HRTIM_CaptureValueTypeDef captured;
07419
07420   /* Check parameters */
07421   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
07422   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
07423
07424   /* Read captured value */
07425   switch (CaptureUnit)
07426   {
07427   case HRTIM_CAPTUREUNIT_1:
07428       tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
07429       captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU;
07430       captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR)?1U:0U);
07431     break;
07432   case HRTIM_CAPTUREUNIT_2:
07433       tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
07434       captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU;
07435       captured.Dir = (((tmp & HRTIM_CPT2R_DIR ) == HRTIM_CPT2R_DIR)?1U:0U);
07436     break;
07437   default:
07438       captured.Value = 0xFFFFFFFFUL;
07439       captured.Dir = 0xFFFFFFFFUL;
07440     break;
07441    }
07442
07443   return captured;
07444 }
07445
07446 /**
07447   * @brief  Return actual direction of the capture register of the designated capture unit
07448   * @param  hhrtim pointer to HAL HRTIM handle
07449   * @param  TimerIdx Timer index
07450   *                   This parameter can be one of the following values:
07451   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07452   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07453   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07454   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07455   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07456   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07457   * @param  CaptureUnit Capture unit to trig
07458   *                    This parameter can be one of the following values:
07459   *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
07460   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
07461   * @retval captured direction
07462   *                    @arg This parameter is one HRTIM_Timer_UpDown_Mode :
07463   *                    @arg HRTIM_TIMERUPDOWNMODE_UP
07464   *                    @arg HRTIM_TIMERUPDOWNMODE_UPDOWN
07465   */
07466 uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim,
07467                                     uint32_t TimerIdx,
07468                                     uint32_t CaptureUnit)
07469 {
07470   uint32_t tmp;
07471
07472   /* Check parameters */
07473   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
07474   assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
07475
07476   /* Read captured value */
07477   switch (CaptureUnit)
07478   {
07479   case HRTIM_CAPTUREUNIT_1:
07480       tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR ) >> HRTIM_CPT1R_DIR_Pos);
07481     break;
07482   case HRTIM_CAPTUREUNIT_2:
07483       tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR ) >> HRTIM_CPT2R_DIR_Pos);
07484     break;
07485   default:
07486     tmp = 0xFFFFFFFFU;
07487     break;
07488   }
07489
07490   return tmp;
07491 }
07492
07493
07494 /**
07495   * @brief  Return actual level (active or inactive) of the designated output
07496   * @param  hhrtim pointer to HAL HRTIM handle
07497   * @param  TimerIdx Timer index
07498   *                   This parameter can be one of the following values:
07499   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07500   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07501   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07502   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07503   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07504   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07505   * @param  Output Timer output
07506   *                    This parameter can be one of the following values:
07507   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07508   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07509   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07510   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07511   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07512   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07513   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07514   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07515   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07516   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07517   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
07518   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
07519   * @retval Output level
07520   * @note Returned output level is taken before the output stage (chopper,
07521   *        polarity).
07522   */
07523 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
07524                                           uint32_t TimerIdx,
07525                                           uint32_t Output)
07526 {
07527   uint32_t output_level;
07528
07529   /* Check parameters */
07530   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
07531
07532   /* Read the output level */
07533   switch (Output)
07534   {
07535   case HRTIM_OUTPUT_TA1:
07536   case HRTIM_OUTPUT_TB1:
07537   case HRTIM_OUTPUT_TC1:
07538   case HRTIM_OUTPUT_TD1:
07539   case HRTIM_OUTPUT_TE1:
07540   case HRTIM_OUTPUT_TF1:
07541     {
07542       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
07543       {
07544         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
07545       }
07546       else
07547       {
07548         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
07549       }
07550      break;
07551     }
07552
07553   case HRTIM_OUTPUT_TA2:
07554   case HRTIM_OUTPUT_TB2:
07555   case HRTIM_OUTPUT_TC2:
07556   case HRTIM_OUTPUT_TD2:
07557   case HRTIM_OUTPUT_TE2:
07558   case HRTIM_OUTPUT_TF2:
07559     {
07560       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
07561       {
07562         output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
07563       }
07564       else
07565       {
07566         output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
07567       }
07568       break;
07569     }
07570
07571   default:
07572     {
07573       output_level = 0xFFFFFFFFUL;
07574       break;
07575     }
07576   }
07577
07578   return output_level;
07579 }
07580
07581 /**
07582   * @brief  Return actual state (RUN, IDLE, FAULT) of the designated output
07583   * @param  hhrtim pointer to HAL HRTIM handle
07584   * @param  TimerIdx Timer index
07585   *                   This parameter can be one of the following values:
07586   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07587   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07588   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07589   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07590   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07591   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07592   * @param  Output Timer output
07593   *                    This parameter can be one of the following values:
07594   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07595   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07596   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07597   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07598   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07599   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07600   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07601   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07602   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07603   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07604   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
07605   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
07606   * @retval Output state
07607   */
07608 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
07609                                           uint32_t TimerIdx,
07610                                           uint32_t Output)
07611 {
07612   uint32_t output_bit;
07613   uint32_t output_state;
07614
07615   /* Check parameters */
07616   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
07617
07618   /* Prevent unused argument(s) compilation warning */
07619   UNUSED(TimerIdx);
07620
07621   /* Set output state according to output control status and output disable status */
07622   switch (Output)
07623   {
07624   case HRTIM_OUTPUT_TA1:
07625     {
07626       output_bit = HRTIM_OENR_TA1OEN;
07627       break;
07628     }
07629
07630   case HRTIM_OUTPUT_TA2:
07631     {
07632       output_bit = HRTIM_OENR_TA2OEN;
07633       break;
07634     }
07635
07636   case HRTIM_OUTPUT_TB1:
07637     {
07638       output_bit = HRTIM_OENR_TB1OEN;
07639       break;
07640     }
07641
07642   case HRTIM_OUTPUT_TB2:
07643     {
07644       output_bit = HRTIM_OENR_TB2OEN;
07645       break;
07646     }
07647
07648   case HRTIM_OUTPUT_TC1:
07649     {
07650       output_bit = HRTIM_OENR_TC1OEN;
07651       break;
07652     }
07653
07654   case HRTIM_OUTPUT_TC2:
07655     {
07656       output_bit = HRTIM_OENR_TC2OEN;
07657       break;
07658     }
07659
07660   case HRTIM_OUTPUT_TD1:
07661     {
07662       output_bit = HRTIM_OENR_TD1OEN;
07663       break;
07664     }
07665
07666   case HRTIM_OUTPUT_TD2:
07667     {
07668       output_bit = HRTIM_OENR_TD2OEN;
07669       break;
07670     }
07671
07672   case HRTIM_OUTPUT_TE1:
07673     {
07674       output_bit = HRTIM_OENR_TE1OEN;
07675       break;
07676     }
07677
07678   case HRTIM_OUTPUT_TE2:
07679     {
07680       output_bit = HRTIM_OENR_TE2OEN;
07681       break;
07682     }
07683
07684   case HRTIM_OUTPUT_TF1:
07685     {
07686       output_bit = HRTIM_OENR_TF1OEN;
07687       break;
07688     }
07689
07690   case HRTIM_OUTPUT_TF2:
07691     {
07692       output_bit = HRTIM_OENR_TF2OEN;
07693       break;
07694     }
07695
07696   default:
07697     {
07698       output_bit = 0UL;
07699       break;
07700     }
07701   }
07702
07703   if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
07704   {
07705     /* Output is enabled: output in RUN state (whatever output disable status is)*/
07706     output_state = HRTIM_OUTPUTSTATE_RUN;
07707   }
07708   else
07709   {
07710     if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
07711     {
07712       /* Output is disabled: output in FAULT state */
07713       output_state = HRTIM_OUTPUTSTATE_FAULT;
07714     }
07715     else
07716     {
07717       /* Output is disabled: output in IDLE state */
07718       output_state = HRTIM_OUTPUTSTATE_IDLE;
07719     }
07720   }
07721
07722   return(output_state);
07723 }
07724
07725 /**
07726   * @brief  Return the level (active or inactive) of the designated output
07727   *         when the delayed protection was triggered.
07728   * @param  hhrtim pointer to HAL HRTIM handle
07729   * @param  TimerIdx Timer index
07730   *                   This parameter can be one of the following values:
07731   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07732   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07733   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07734   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07735   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07736   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07737   * @param  Output Timer output
07738   *                    This parameter can be one of the following values:
07739   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
07740   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
07741   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
07742   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
07743   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
07744   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
07745   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
07746   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
07747   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
07748   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
07749   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
07750   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
07751   * @retval Delayed protection status
07752   */
07753 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
07754                                               uint32_t TimerIdx,
07755                                               uint32_t Output)
07756 {
07757   uint32_t delayed_protection_status;
07758
07759   /* Check parameters */
07760   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
07761
07762   /* Read the delayed protection status */
07763   switch (Output)
07764   {
07765   case HRTIM_OUTPUT_TA1:
07766   case HRTIM_OUTPUT_TB1:
07767   case HRTIM_OUTPUT_TC1:
07768   case HRTIM_OUTPUT_TD1:
07769   case HRTIM_OUTPUT_TE1:
07770   case HRTIM_OUTPUT_TF1:
07771     {
07772       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
07773       {
07774         /* Output 1 was active when the delayed idle protection was triggered */
07775         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
07776       }
07777       else
07778       {
07779         /* Output 1 was inactive when the delayed idle protection was triggered */
07780         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
07781       }
07782       break;
07783     }
07784
07785   case HRTIM_OUTPUT_TA2:
07786   case HRTIM_OUTPUT_TB2:
07787   case HRTIM_OUTPUT_TC2:
07788   case HRTIM_OUTPUT_TD2:
07789   case HRTIM_OUTPUT_TE2:
07790   case HRTIM_OUTPUT_TF2:
07791     {
07792       if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
07793       {
07794         /* Output 2 was active when the delayed idle protection was triggered */
07795         delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
07796       }
07797       else
07798       {
07799         /* Output 2 was inactive when the delayed idle protection was triggered */
07800         delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
07801       }
07802       break;
07803     }
07804
07805   default:
07806     {
07807       delayed_protection_status = 0xFFFFFFFFUL;
07808       break;
07809     }
07810   }
07811
07812   return delayed_protection_status;
07813 }
07814
07815 /**
07816   * @brief  Return the actual status (active or inactive) of the burst mode controller
07817   * @param  hhrtim pointer to HAL HRTIM handle
07818   * @retval Burst mode controller status
07819   */
07820 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
07821 {
07822   uint32_t burst_mode_status;
07823
07824   /* Read burst mode status */
07825   burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
07826
07827   return burst_mode_status;
07828 }
07829
07830 /**
07831   * @brief  Indicate on which output the signal is currently active (when the
07832   *         push pull mode is enabled).
07833   * @param  hhrtim pointer to HAL HRTIM handle
07834   * @param  TimerIdx Timer index
07835   *                   This parameter can be one of the following values:
07836   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07837   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07838   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07839   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07840   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07841   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07842   * @retval Burst mode controller status
07843   */
07844 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
07845                                             uint32_t TimerIdx)
07846 {
07847   uint32_t current_pushpull_status;
07848
07849   /* Check the parameters */
07850   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
07851
07852   /* Read current push pull status */
07853   current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
07854
07855   return current_pushpull_status;
07856 }
07857
07858
07859 /**
07860   * @brief  Indicate on which output the signal was applied, in push-pull mode,
07861             balanced fault mode or delayed idle mode, when the protection was triggered.
07862   * @param  hhrtim pointer to HAL HRTIM handle
07863   * @param  TimerIdx Timer index
07864   *                   This parameter can be one of the following values:
07865   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
07866   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
07867   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
07868   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
07869   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
07870   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
07871   * @retval Idle Push Pull Status
07872   */
07873 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
07874                                          uint32_t TimerIdx)
07875 {
07876   uint32_t idle_pushpull_status;
07877
07878   /* Check the parameters */
07879   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
07880
07881   /* Read current push pull status */
07882   idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
07883
07884   return idle_pushpull_status;
07885 }
07886
07887 /**
07888   * @}
07889   */
07890
07891 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
07892  *  @brief  Functions called when HRTIM generates an interrupt
07893  *          7 interrupts can be generated by the master timer:
07894  *            - Master timer registers update
07895  *            - Synchronization event received
07896  *            - Master timer repetition event
07897  *            - Master Compare 1 to 4 event
07898  *          14 interrupts can be generated by each timing unit:
07899  *            - Delayed protection triggered
07900  *            - Counter reset or roll-over event
07901  *            - Output 1 and output 2 reset (transition active to inactive)
07902  *            - Output 1 and output 2 set (transition inactive to active)
07903  *            - Capture 1 and 2 events
07904  *            - Timing unit registers update
07905  *            - Repetition event
07906  *            - Compare 1 to 4 event
07907  *          8 global interrupts are generated for the whole HRTIM:
07908  *            - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
07909  *            - DLL calibration done
07910  *            - Burst mode period completed
07911 @verbatim
07912  ===============================================================================
07913                       ##### HRTIM interrupts handling #####
07914  ===============================================================================
07915     [..]
07916     This subsection provides a set of functions allowing to manage the HRTIM
07917     interrupts:
07918       (+)  HRTIM interrupt handler
07919       (+)  Callback function called when Fault1 interrupt occurs
07920       (+)  Callback function called when Fault2 interrupt occurs
07921       (+)  Callback function called when Fault3 interrupt occurs
07922       (+)  Callback function called when Fault4 interrupt occurs
07923       (+)  Callback function called when Fault5 interrupt occurs
07924       (+)  Callback function called when Fault6 interrupt occurs
07925       (+)  Callback function called when system Fault interrupt occurs
07926       (+)  Callback function called when DLL ready interrupt occurs
07927       (+)  Callback function called when burst mode period interrupt occurs
07928       (+)  Callback function called when synchronization input interrupt occurs
07929       (+)  Callback function called when a timer register update interrupt occurs
07930       (+)  Callback function called when a timer repetition interrupt occurs
07931       (+)  Callback function called when a compare 1 match interrupt occurs
07932       (+)  Callback function called when a compare 2 match interrupt occurs
07933       (+)  Callback function called when a compare 3 match interrupt occurs
07934       (+)  Callback function called when a compare 4 match interrupt occurs
07935       (+)  Callback function called when a capture 1 interrupt occurs
07936       (+)  Callback function called when a capture 2 interrupt occurs
07937       (+)  Callback function called when a delayed protection interrupt occurs
07938       (+)  Callback function called when a timer counter reset interrupt occurs
07939       (+)  Callback function called when a timer output 1 set interrupt occurs
07940       (+)  Callback function called when a timer output 1 reset interrupt occurs
07941       (+)  Callback function called when a timer output 2 set interrupt occurs
07942       (+)  Callback function called when a timer output 2 reset interrupt occurs
07943       (+)  Callback function called when a timer output 2 reset interrupt occurs
07944       (+)  Callback function called upon completion of a burst DMA transfer
07945       (+)  HRTIM callback function registration
07946       (+)  HRTIM callback function unregistration
07947       (+)  HRTIM Timer x callback function registration
07948       (+)  HRTIM Timer x callback function unregistration
07949
07950 @endverbatim
07951   * @{
07952   */
07953
07954 /**
07955   * @brief  This function handles HRTIM interrupt request.
07956   * @param  hhrtim pointer to HAL HRTIM handle
07957   * @param  TimerIdx Timer index
07958   *                   This parameter can be any value of HRTIM_Timer_Index
07959   * @retval None
07960   */
07961 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
07962                           uint32_t TimerIdx)
07963 {
07964   /* HRTIM interrupts handling */
07965   if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
07966   {
07967     HRTIM_HRTIM_ISR(hhrtim);
07968   }
07969   else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
07970   {
07971     /* Master related interrupts handling */
07972     HRTIM_Master_ISR(hhrtim);
07973   }
07974   else
07975   {
07976     /* Timing unit related interrupts handling */
07977     HRTIM_Timer_ISR(hhrtim, TimerIdx);
07978   }
07979
07980 }
07981
07982 /**
07983   * @brief  Callback function invoked when a fault 1 interrupt occurred
07984   * @param  hhrtim pointer to HAL HRTIM handle  * @retval None
07985   * @retval None
07986   */
07987 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
07988 {
07989   /* Prevent unused argument(s) compilation warning */
07990   UNUSED(hhrtim);
07991
07992   /* NOTE : This function should not be modified, when the callback is needed,
07993             the HAL_HRTIM_Fault1Callback could be implemented in the user file
07994    */
07995 }
07996
07997 /**
07998   * @brief  Callback function invoked when a fault 2 interrupt occurred
07999   * @param  hhrtim pointer to HAL HRTIM handle
08000   * @retval None
08001   */
08002 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
08003 {
08004   /* Prevent unused argument(s) compilation warning */
08005   UNUSED(hhrtim);
08006
08007   /* NOTE : This function should not be modified, when the callback is needed,
08008             the HAL_HRTIM_Fault2Callback could be implemented in the user file
08009    */
08010 }
08011
08012 /**
08013   * @brief  Callback function invoked when a fault 3 interrupt occurred
08014   * @param  hhrtim pointer to HAL HRTIM handle
08015   * @retval None
08016   */
08017 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
08018 {
08019   /* Prevent unused argument(s) compilation warning */
08020   UNUSED(hhrtim);
08021
08022   /* NOTE : This function should not be modified, when the callback is needed,
08023             the HAL_HRTIM_Fault3Callback could be implemented in the user file
08024    */
08025 }
08026
08027 /**
08028   * @brief  Callback function invoked when a fault 4 interrupt occurred
08029   * @param  hhrtim pointer to HAL HRTIM handle
08030   * @retval None
08031   */
08032 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
08033 {
08034   /* Prevent unused argument(s) compilation warning */
08035   UNUSED(hhrtim);
08036
08037   /* NOTE : This function should not be modified, when the callback is needed,
08038             the HAL_HRTIM_Fault4Callback could be implemented in the user file
08039    */
08040 }
08041
08042 /**
08043   * @brief  Callback function invoked when a fault 5 interrupt occurred
08044   * @param  hhrtim pointer to HAL HRTIM handle
08045   * @retval None
08046   */
08047 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
08048 {
08049   /* Prevent unused argument(s) compilation warning */
08050   UNUSED(hhrtim);
08051
08052   /* NOTE : This function should not be modified, when the callback is needed,
08053             the HAL_HRTIM_Fault5Callback could be implemented in the user file
08054    */
08055 }
08056
08057 /**
08058   * @brief  Callback function invoked when a fault 6 interrupt occurred
08059   * @param  hhrtim pointer to HAL HRTIM handle
08060   * @retval None
08061   */
08062 __weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim)
08063 {
08064   /* Prevent unused argument(s) compilation warning */
08065   UNUSED(hhrtim);
08066
08067   /* NOTE : This function should not be modified, when the callback is needed,
08068             the HAL_HRTIM_Fault6Callback could be implemented in the user file
08069    */
08070 }
08071
08072 /**
08073   * @brief  Callback function invoked when a system fault interrupt occurred
08074   * @param  hhrtim pointer to HAL HRTIM handle
08075   * @retval None
08076   */
08077 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
08078 {
08079   /* Prevent unused argument(s) compilation warning */
08080   UNUSED(hhrtim);
08081
08082   /* NOTE : This function should not be modified, when the callback is needed,
08083             the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
08084    */
08085 }
08086
08087 /**
08088   * @brief  Callback function invoked when the DLL calibration is completed
08089   * @param  hhrtim pointer to HAL HRTIM handle
08090   * @retval None
08091   */
08092 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
08093 {
08094   /* Prevent unused argument(s) compilation warning */
08095   UNUSED(hhrtim);
08096
08097   /* NOTE : This function should not be modified, when the callback is needed,
08098             the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
08099    */
08100 }
08101
08102 /**
08103   * @brief  Callback function invoked when the end of the burst mode period is reached
08104   * @param  hhrtim pointer to HAL HRTIM handle
08105   * @retval None
08106   */
08107 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
08108 {
08109   /* Prevent unused argument(s) compilation warning */
08110   UNUSED(hhrtim);
08111
08112   /* NOTE : This function should not be modified, when the callback is needed,
08113             the HAL_HRTIM_BurstModeCallback could be implemented in the user file
08114    */
08115 }
08116
08117 /**
08118   * @brief  Callback function invoked when a synchronization input event is received
08119   * @param  hhrtim pointer to HAL HRTIM handle
08120   * @retval None
08121   */
08122 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
08123 {
08124   /* Prevent unused argument(s) compilation warning */
08125   UNUSED(hhrtim);
08126
08127   /* NOTE : This function should not be modified, when the callback is needed,
08128             the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
08129    */
08130 }
08131
08132 /**
08133   * @brief  Callback function invoked when timer registers are updated
08134   * @param  hhrtim pointer to HAL HRTIM handle
08135   * @param  TimerIdx Timer index
08136   *                   This parameter can be one of the following values:
08137   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08138   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08139   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08140   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08141   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08142   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08143   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08144   * @retval None
08145   */
08146 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
08147                                               uint32_t TimerIdx)
08148 {
08149   /* Prevent unused argument(s) compilation warning */
08150   UNUSED(hhrtim);
08151   UNUSED(TimerIdx);
08152
08153   /* NOTE : This function should not be modified, when the callback is needed,
08154             the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
08155    */
08156 }
08157
08158 /**
08159   * @brief  Callback function invoked when timer repetition period has elapsed
08160   * @param  hhrtim pointer to HAL HRTIM handle
08161   * @param  TimerIdx Timer index
08162   *                   This parameter can be one of the following values:
08163   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08164   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08165   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08166   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08167   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08168   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08169   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08170   * @retval None
08171   */
08172 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
08173                                               uint32_t TimerIdx)
08174 {
08175   /* Prevent unused argument(s) compilation warning */
08176   UNUSED(hhrtim);
08177   UNUSED(TimerIdx);
08178
08179   /* NOTE : This function should not be modified, when the callback is needed,
08180             the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
08181    */
08182 }
08183
08184 /**
08185   * @brief  Callback function invoked when the timer counter matches the value
08186   *         programmed in the compare 1 register
08187   * @param  hhrtim pointer to HAL HRTIM handle
08188   * @param  TimerIdx Timer index
08189   *                   This parameter can be one of the following values:
08190   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08191   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08192   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08193   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08194   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08195   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08196   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08197   * @retval None
08198   */
08199 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
08200                                               uint32_t TimerIdx)
08201 {
08202   /* Prevent unused argument(s) compilation warning */
08203   UNUSED(hhrtim);
08204   UNUSED(TimerIdx);
08205
08206   /* NOTE : This function should not be modified, when the callback is needed,
08207             the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
08208    */
08209 }
08210
08211 /**
08212   * @brief  Callback function invoked when the timer counter matches the value
08213   *         programmed in the compare 2 register
08214   * @param  hhrtim pointer to HAL HRTIM handle
08215   * @retval None
08216   * @param  TimerIdx Timer index
08217   *                   This parameter can be one of the following values:
08218   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08219   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08220   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08221   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08222   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08223   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08224   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08225   */
08226 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
08227                                               uint32_t TimerIdx)
08228 {
08229   /* Prevent unused argument(s) compilation warning */
08230   UNUSED(hhrtim);
08231   UNUSED(TimerIdx);
08232
08233   /* NOTE : This function should not be modified, when the callback is needed,
08234             the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
08235    */
08236 }
08237
08238 /**
08239   * @brief  Callback function invoked when the timer counter matches the value
08240   *         programmed in the compare 3 register
08241   * @param  hhrtim pointer to HAL HRTIM handle
08242   * @param  TimerIdx Timer index
08243   *                   This parameter can be one of the following values:
08244   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08245   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08246   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08247   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08248   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08249   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08250   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08251   * @retval None
08252   */
08253 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
08254                                               uint32_t TimerIdx)
08255 {
08256   /* Prevent unused argument(s) compilation warning */
08257   UNUSED(hhrtim);
08258   UNUSED(TimerIdx);
08259
08260   /* NOTE : This function should not be modified, when the callback is needed,
08261             the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
08262    */
08263 }
08264
08265 /**
08266   * @brief  Callback function invoked when the timer counter matches the value
08267   *         programmed in the compare 4 register.
08268   * @param  hhrtim pointer to HAL HRTIM handle
08269   * @param  TimerIdx Timer index
08270   *                   This parameter can be one of the following values:
08271   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08272   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08273   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08274   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08275   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08276   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08277   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08278   * @retval None
08279   */
08280 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
08281                                               uint32_t TimerIdx)
08282 {
08283   /* Prevent unused argument(s) compilation warning */
08284   UNUSED(hhrtim);
08285   UNUSED(TimerIdx);
08286
08287   /* NOTE : This function should not be modified, when the callback is needed,
08288             the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
08289    */
08290 }
08291
08292 /**
08293   * @brief  Callback function invoked when the timer x capture 1 event occurs
08294   * @param  hhrtim pointer to HAL HRTIM handle
08295   * @param  TimerIdx Timer index
08296   *                   This parameter can be one of the following values:
08297   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08298   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08299   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08300   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08301   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08302   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08303   * @retval None
08304   */
08305 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
08306                                               uint32_t TimerIdx)
08307 {
08308   /* Prevent unused argument(s) compilation warning */
08309   UNUSED(hhrtim);
08310   UNUSED(TimerIdx);
08311
08312   /* NOTE : This function should not be modified, when the callback is needed,
08313             the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
08314    */
08315 }
08316
08317 /**
08318   * @brief  Callback function invoked when the timer x capture 2 event occurs
08319   * @param  hhrtim pointer to HAL HRTIM handle
08320   * @param  TimerIdx Timer index
08321   *                   This parameter can be one of the following values:
08322   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08323   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08324   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08325   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08326   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08327   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08328   * @retval None
08329   */
08330 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
08331                                               uint32_t TimerIdx)
08332 {
08333   /* Prevent unused argument(s) compilation warning */
08334   UNUSED(hhrtim);
08335   UNUSED(TimerIdx);
08336
08337   /* NOTE : This function should not be modified, when the callback is needed,
08338             the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
08339    */
08340 }
08341
08342 /**
08343   * @brief  Callback function invoked when the delayed idle or balanced idle mode is
08344   *         entered.
08345   * @param  hhrtim pointer to HAL HRTIM handle
08346   * @param  TimerIdx Timer index
08347   *                   This parameter can be one of the following values:
08348   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08349   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08350   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08351   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08352   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08353   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08354   * @retval None
08355   */
08356 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
08357                                               uint32_t TimerIdx)
08358 {
08359   /* Prevent unused argument(s) compilation warning */
08360   UNUSED(hhrtim);
08361   UNUSED(TimerIdx);
08362
08363   /* NOTE : This function should not be modified, when the callback is needed,
08364             the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
08365    */
08366 }
08367
08368 /**
08369   * @brief  Callback function invoked when the timer x counter reset/roll-over
08370   *         event occurs.
08371   * @param  hhrtim pointer to HAL HRTIM handle
08372   * @param  TimerIdx Timer index
08373   *                   This parameter can be one of the following values:
08374   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08375   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08376   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08377   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08378   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08379   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08380   * @retval None
08381   */
08382 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
08383                                               uint32_t TimerIdx)
08384 {
08385   /* Prevent unused argument(s) compilation warning */
08386   UNUSED(hhrtim);
08387   UNUSED(TimerIdx);
08388
08389   /* NOTE : This function should not be modified, when the callback is needed,
08390             the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
08391    */
08392 }
08393
08394 /**
08395   * @brief  Callback function invoked when the timer x output 1 is set
08396   * @param  hhrtim pointer to HAL HRTIM handle
08397   * @param  TimerIdx Timer index
08398   *                   This parameter can be one of the following values:
08399   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08400   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08401   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08402   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08403   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08404   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08405   * @retval None
08406   */
08407 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
08408                                               uint32_t TimerIdx)
08409 {
08410   /* Prevent unused argument(s) compilation warning */
08411   UNUSED(hhrtim);
08412   UNUSED(TimerIdx);
08413
08414   /* NOTE : This function should not be modified, when the callback is needed,
08415             the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
08416    */
08417 }
08418
08419 /**
08420   * @brief  Callback function invoked when the timer x output 1 is reset
08421   * @param  hhrtim pointer to HAL HRTIM handle
08422   * @param  TimerIdx Timer index
08423   *                   This parameter can be one of the following values:
08424   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08425   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08426   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08427   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08428   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08429   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08430   * @retval None
08431   */
08432 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
08433                                               uint32_t TimerIdx)
08434 {
08435   /* Prevent unused argument(s) compilation warning */
08436   UNUSED(hhrtim);
08437   UNUSED(TimerIdx);
08438
08439   /* NOTE : This function should not be modified, when the callback is needed,
08440             the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
08441    */
08442 }
08443
08444 /**
08445   * @brief  Callback function invoked when the timer x output 2 is set
08446   * @param  hhrtim pointer to HAL HRTIM handle
08447   * @param  TimerIdx Timer index
08448   *                   This parameter can be one of the following values:
08449   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08450   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08451   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08452   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08453   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08454   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08455   * @retval None
08456   */
08457 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
08458                                               uint32_t TimerIdx)
08459 {
08460   /* Prevent unused argument(s) compilation warning */
08461   UNUSED(hhrtim);
08462   UNUSED(TimerIdx);
08463
08464   /* NOTE : This function should not be modified, when the callback is needed,
08465             the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
08466    */
08467 }
08468
08469 /**
08470   * @brief  Callback function invoked when the timer x output 2 is reset
08471   * @param  hhrtim pointer to HAL HRTIM handle
08472   * @param  TimerIdx Timer index
08473   *                   This parameter can be one of the following values:
08474   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08475   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08476   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08477   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08478   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08479   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08480   * @retval None
08481   */
08482 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
08483                                               uint32_t TimerIdx)
08484 {
08485   /* Prevent unused argument(s) compilation warning */
08486   UNUSED(hhrtim);
08487   UNUSED(TimerIdx);
08488
08489   /* NOTE : This function should not be modified, when the callback is needed,
08490             the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
08491    */
08492 }
08493
08494 /**
08495   * @brief  Callback function invoked when a DMA burst transfer is completed
08496   * @param  hhrtim pointer to HAL HRTIM handle
08497   * @param  TimerIdx Timer index
08498   *                   This parameter can be one of the following values:
08499   *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
08500   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
08501   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
08502   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
08503   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
08504   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
08505   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
08506   * @retval None
08507   */
08508 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
08509                                                uint32_t TimerIdx)
08510 {
08511   /* Prevent unused argument(s) compilation warning */
08512   UNUSED(hhrtim);
08513   UNUSED(TimerIdx);
08514
08515   /* NOTE : This function should not be modified, when the callback is needed,
08516             the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
08517    */
08518 }
08519
08520 /**
08521   * @brief  Callback function invoked when a DMA error occurs
08522   * @param  hhrtim pointer to HAL HRTIM handle
08523   * @retval None
08524   */
08525 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
08526 {
08527   /* Prevent unused argument(s) compilation warning */
08528   UNUSED(hhrtim);
08529
08530   /* NOTE : This function should not be modified, when the callback is needed,
08531             the HAL_HRTIM_ErrorCallback could be implemented in the user file
08532    */
08533 }
08534
08535 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
08536 /**
08537   * @brief  HRTIM callback function registration
08538   * @param  hhrtim pointer to HAL HRTIM handle
08539   * @param  CallbackID ID of the HRTIM callback function to register
08540   *                   This parameter can be one of the following values:
08541   *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
08542   *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
08543   *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
08544   *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
08545   *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
08546   *                   @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
08547   *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
08548   *                   @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
08549   *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
08550   *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
08551   *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
08552   *                   @arg HAL_HRTIM_MSPINIT_CB_ID
08553   *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
08554   * @param  pCallback Callback function pointer
08555   * @retval HAL status
08556   */
08557 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
08558                                              HAL_HRTIM_CallbackIDTypeDef CallbackID,
08559                                              pHRTIM_CallbackTypeDef      pCallback)
08560 {
08561   HAL_StatusTypeDef status = HAL_OK;
08562
08563   if (pCallback == NULL)
08564   {
08565     /* Update the state */
08566     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08567
08568     return HAL_ERROR;
08569   }
08570
08571   /* Process locked */
08572   __HAL_LOCK(hhrtim);
08573
08574   if (HAL_HRTIM_STATE_READY == hhrtim->State)
08575   {
08576     switch (CallbackID)
08577     {
08578       case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
08579         hhrtim->Fault1Callback = pCallback;
08580         break;
08581
08582       case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
08583         hhrtim->Fault2Callback = pCallback;
08584         break;
08585
08586       case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
08587         hhrtim->Fault3Callback = pCallback;
08588         break;
08589
08590       case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
08591         hhrtim->Fault4Callback = pCallback;
08592         break;
08593
08594       case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
08595         hhrtim->Fault5Callback = pCallback;
08596         break;
08597
08598       case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
08599         hhrtim->Fault6Callback = pCallback;
08600         break;
08601
08602       case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
08603         hhrtim->SystemFaultCallback = pCallback;
08604         break;
08605
08606       case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
08607         hhrtim->DLLCalibrationReadyCallback = pCallback;
08608         break;
08609
08610       case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
08611         hhrtim->BurstModePeriodCallback = pCallback;
08612         break;
08613
08614       case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
08615         hhrtim->SynchronizationEventCallback = pCallback;
08616         break;
08617
08618       case HAL_HRTIM_ERRORCALLBACK_CB_ID :
08619         hhrtim->ErrorCallback = pCallback;
08620         break;
08621
08622       case HAL_HRTIM_MSPINIT_CB_ID :
08623         hhrtim->MspInitCallback = pCallback;
08624         break;
08625
08626       case HAL_HRTIM_MSPDEINIT_CB_ID :
08627         hhrtim->MspDeInitCallback = pCallback;
08628         break;
08629
08630       default :
08631         /* Update the state */
08632         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08633
08634         /* Return error status */
08635         status = HAL_ERROR;
08636         break;
08637     }
08638   }
08639   else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
08640   {
08641     switch (CallbackID)
08642     {
08643       case HAL_HRTIM_MSPINIT_CB_ID :
08644         hhrtim->MspInitCallback = pCallback;
08645         break;
08646
08647       case HAL_HRTIM_MSPDEINIT_CB_ID :
08648         hhrtim->MspDeInitCallback = pCallback;
08649         break;
08650
08651       default :
08652         /* Update the state */
08653         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08654
08655         /* Return error status */
08656         status = HAL_ERROR;
08657         break;
08658     }
08659   }
08660   else
08661   {
08662     /* Update the state */
08663     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08664
08665     /* Return error status */
08666     status = HAL_ERROR;
08667   }
08668
08669   /* Release Lock */
08670   __HAL_UNLOCK(hhrtim);
08671
08672   return status;
08673 }
08674
08675 /**
08676   * @brief  HRTIM callback function un-registration
08677   * @param  hhrtim pointer to HAL HRTIM handle
08678   * @param  CallbackID ID of the HRTIM callback function to unregister
08679   *                   This parameter can be one of the following values:
08680   *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
08681   *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
08682   *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
08683   *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
08684   *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
08685   *                   @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
08686   *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
08687   *                   @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
08688   *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
08689   *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
08690   *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
08691   *                   @arg HAL_HRTIM_MSPINIT_CB_ID
08692   *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
08693   * @retval HAL status
08694   */
08695 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
08696                                                HAL_HRTIM_CallbackIDTypeDef CallbackID)
08697 {
08698   HAL_StatusTypeDef status = HAL_OK;
08699
08700   /* Process locked */
08701   __HAL_LOCK(hhrtim);
08702
08703   if (HAL_HRTIM_STATE_READY == hhrtim->State)
08704   {
08705     switch (CallbackID)
08706     {
08707     case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
08708       hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
08709       break;
08710
08711     case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
08712       hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
08713       break;
08714
08715     case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
08716       hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
08717       break;
08718
08719     case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
08720       hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
08721       break;
08722
08723     case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
08724       hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
08725       break;
08726
08727     case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
08728       hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
08729       break;
08730
08731     case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
08732       hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
08733       break;
08734
08735     case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
08736       hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
08737       break;
08738
08739     case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
08740       hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
08741       break;
08742
08743     case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
08744       hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
08745       break;
08746
08747     case HAL_HRTIM_ERRORCALLBACK_CB_ID :
08748       hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
08749       break;
08750
08751     case HAL_HRTIM_MSPINIT_CB_ID :
08752       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
08753       break;
08754
08755     case HAL_HRTIM_MSPDEINIT_CB_ID :
08756       hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
08757       break;
08758
08759     default :
08760     /* Update the state */
08761     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08762
08763     /* Return error status */
08764     status = HAL_ERROR;
08765       break;
08766     }
08767   }
08768   else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
08769   {
08770     switch (CallbackID)
08771     {
08772     case HAL_HRTIM_MSPINIT_CB_ID :
08773       hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
08774       break;
08775
08776     case HAL_HRTIM_MSPDEINIT_CB_ID :
08777       hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
08778       break;
08779
08780     default :
08781     /* Update the state */
08782     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08783
08784     /* Return error status */
08785     status =  HAL_ERROR;
08786       break;
08787     }
08788   }
08789   else
08790   {
08791     /* Update the state */
08792     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08793
08794     /* Return error status */
08795     status =  HAL_ERROR;
08796   }
08797
08798   /* Release Lock */
08799   __HAL_UNLOCK(hhrtim);
08800
08801   return status;
08802 }
08803
08804 /**
08805   * @brief  HRTIM Timer x callback function registration
08806   * @param  hhrtim pointer to HAL HRTIM handle
08807   * @param  CallbackID ID of the HRTIM Timer x callback function to register
08808   *                   This parameter can be one of the following values:
08809   *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
08810   *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
08811   *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
08812   *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
08813   *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
08814   *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
08815   *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
08816   *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
08817   *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
08818   *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
08819   *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
08820   *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
08821   *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
08822   *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
08823   *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
08824   * @param  pCallback Callback function pointer
08825   * @retval HAL status
08826   */
08827 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
08828                                                  HAL_HRTIM_CallbackIDTypeDef CallbackID,
08829                                                  pHRTIM_TIMxCallbackTypeDef pCallback)
08830 {
08831   HAL_StatusTypeDef status = HAL_OK;
08832
08833   if (pCallback == NULL)
08834   {
08835     /* Update the state */
08836     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08837
08838     return HAL_ERROR;
08839   }
08840
08841   /* Process locked */
08842   __HAL_LOCK(hhrtim);
08843
08844   if (HAL_HRTIM_STATE_READY == hhrtim->State)
08845   {
08846     switch (CallbackID)
08847     {
08848       case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
08849         hhrtim->RegistersUpdateCallback = pCallback;
08850         break;
08851
08852       case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
08853         hhrtim->RepetitionEventCallback = pCallback;
08854         break;
08855
08856       case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
08857         hhrtim->Compare1EventCallback = pCallback;
08858         break;
08859
08860       case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
08861         hhrtim->Compare2EventCallback = pCallback;
08862         break;
08863
08864       case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
08865         hhrtim->Compare3EventCallback = pCallback;
08866         break;
08867
08868       case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
08869         hhrtim->Compare4EventCallback = pCallback;
08870         break;
08871
08872       case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
08873         hhrtim->Capture1EventCallback = pCallback;
08874         break;
08875
08876       case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
08877         hhrtim->Capture2EventCallback = pCallback;
08878         break;
08879
08880       case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
08881         hhrtim->DelayedProtectionCallback = pCallback;
08882         break;
08883
08884       case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
08885         hhrtim->CounterResetCallback = pCallback;
08886         break;
08887
08888       case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
08889         hhrtim->Output1SetCallback = pCallback;
08890         break;
08891
08892       case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
08893         hhrtim->Output1ResetCallback = pCallback;
08894         break;
08895
08896       case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
08897         hhrtim->Output2SetCallback = pCallback;
08898         break;
08899
08900       case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
08901         hhrtim->Output2ResetCallback = pCallback;
08902         break;
08903
08904       case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
08905         hhrtim->BurstDMATransferCallback = pCallback;
08906         break;
08907
08908     default :
08909         /* Update the state */
08910         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08911
08912         /* Return error status */
08913         status = HAL_ERROR;
08914         break;
08915     }
08916   }
08917   else
08918   {
08919     /* Update the state */
08920     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
08921
08922     /* Return error status */
08923     status = HAL_ERROR;
08924   }
08925
08926   /* Release Lock */
08927   __HAL_UNLOCK(hhrtim);
08928
08929   return status;
08930 }
08931
08932 /**
08933   * @brief  HRTIM Timer x callback function un-registration
08934   * @param  hhrtim pointer to HAL HRTIM handle
08935   * @param  CallbackID ID of the HRTIM callback Timer x function to unregister
08936   *                   This parameter can be one of the following values:
08937   *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
08938   *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
08939   *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
08940   *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
08941   *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
08942   *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
08943   *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
08944   *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
08945   *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
08946   *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
08947   *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
08948   *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
08949   *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
08950   *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
08951   *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
08952   * @retval HAL status
08953   */
08954 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
08955                                                    HAL_HRTIM_CallbackIDTypeDef CallbackID)
08956 {
08957   HAL_StatusTypeDef status = HAL_OK;
08958
08959   /* Process locked */
08960   __HAL_LOCK(hhrtim);
08961
08962   if (HAL_HRTIM_STATE_READY == hhrtim->State)
08963   {
08964     switch (CallbackID)
08965     {
08966       case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
08967         hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
08968         break;
08969
08970       case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
08971         hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
08972         break;
08973
08974       case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
08975         hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
08976         break;
08977
08978       case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
08979         hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
08980         break;
08981
08982       case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
08983         hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
08984         break;
08985
08986       case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
08987         hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
08988         break;
08989
08990       case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
08991         hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
08992         break;
08993
08994       case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
08995         hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
08996         break;
08997
08998       case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
08999         hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
09000         break;
09001
09002       case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
09003         hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
09004         break;
09005
09006       case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
09007         hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
09008         break;
09009
09010       case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
09011         hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
09012         break;
09013
09014       case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
09015         hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
09016         break;
09017
09018       case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
09019         hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
09020         break;
09021
09022       case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
09023         hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
09024         break;
09025
09026     default :
09027         /* Update the state */
09028         hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
09029
09030         /* Return error status */
09031         status = HAL_ERROR;
09032         break;
09033     }
09034   }
09035   else
09036   {
09037     /* Update the state */
09038     hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
09039
09040     /* Return error status */
09041     status = HAL_ERROR;
09042   }
09043
09044   /* Release Lock */
09045   __HAL_UNLOCK(hhrtim);
09046
09047   return status;
09048 }
09049 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
09050 /**
09051   * @}
09052   */
09053
09054 /**
09055   * @}
09056   */
09057
09058 /** @addtogroup HRTIM_Private_Functions
09059   * @{
09060   */
09061
09062 /**
09063   * @brief  Configure the master timer time base
09064   * @param  hhrtim pointer to HAL HRTIM handle
09065   * @param  pTimeBaseCfg pointer to the time base configuration structure
09066   * @retval None
09067   */
09068 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
09069                                     const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
09070 {
09071   uint32_t hrtim_mcr;
09072
09073   /* Configure master timer */
09074   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
09075
09076   /* Set the prescaler ratio */
09077   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
09078   hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
09079
09080   /* Set the operating mode */
09081   hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
09082   hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
09083
09084   /* Update the HRTIM registers */
09085   hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
09086   hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
09087   hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
09088 }
09089
09090 /**
09091   * @brief  Configure timing unit (Timer A to Timer F) time base
09092   * @param  hhrtim pointer to HAL HRTIM handle
09093   * @param  TimerIdx Timer index
09094   * @param  pTimeBaseCfg pointer to the time base configuration structure
09095   * @retval None
09096   */
09097 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
09098                                         uint32_t TimerIdx ,
09099                                         const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
09100 {
09101   uint32_t hrtim_timcr;
09102
09103   /* Configure master timing unit */
09104   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
09105
09106   /* Set the prescaler ratio */
09107   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
09108   hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
09109
09110   /* Set the operating mode */
09111   hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
09112   hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
09113
09114   /* Update the HRTIM registers */
09115   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
09116   hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
09117   hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
09118 }
09119
09120 /**
09121   * @brief  Configure the master timer in waveform mode
09122   * @param  hhrtim pointer to HAL HRTIM handle
09123   * @param  pTimerCfg pointer to the timer configuration data structure
09124   * @retval None
09125   */
09126 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
09127                                         const HRTIM_TimerCfgTypeDef * pTimerCfg)
09128 {
09129   uint32_t hrtim_mcr;
09130   uint32_t hrtim_bmcr;
09131
09132   /* Configure master timer */
09133   hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
09134   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
09135
09136   /* Enable/Disable the half mode */
09137   hrtim_mcr &= ~(HRTIM_MCR_HALF);
09138   hrtim_mcr |= pTimerCfg->HalfModeEnable;
09139
09140   /* INTLVD bits are set to 00 */
09141   hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
09142   if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
09143   {
09144     /* INTLVD bits set to 00 */
09145     hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
09146     hrtim_mcr |= (HRTIM_MCR_HALF);
09147   }
09148   else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
09149   {
09150         hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
09151         hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
09152   }
09153   else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
09154   {
09155         hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
09156         hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
09157   }
09158   else
09159   {
09160         hrtim_mcr &= ~(HRTIM_MCR_HALF);
09161         hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
09162   }
09163
09164   /* Enable/Disable the timer start upon synchronization event reception */
09165   hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
09166   hrtim_mcr |= pTimerCfg->StartOnSync;
09167
09168   /* Enable/Disable the timer reset upon synchronization event reception */
09169   hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
09170   hrtim_mcr |= pTimerCfg->ResetOnSync;
09171
09172   /* Enable/Disable the DAC synchronization event generation */
09173   hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
09174   hrtim_mcr |= pTimerCfg->DACSynchro;
09175
09176   /* Enable/Disable preload mechanism for timer registers */
09177   hrtim_mcr &= ~(HRTIM_MCR_PREEN);
09178   hrtim_mcr |= pTimerCfg->PreloadEnable;
09179
09180   /* Master timer registers update handling */
09181   hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
09182   hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
09183
09184   /* Enable/Disable registers update on repetition */
09185   hrtim_mcr &= ~(HRTIM_MCR_MREPU);
09186   hrtim_mcr |= pTimerCfg->RepetitionUpdate;
09187
09188   /* Set the timer burst mode */
09189   hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
09190   hrtim_bmcr |= pTimerCfg->BurstMode;
09191
09192   /* Update the HRTIM registers */
09193   hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
09194   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
09195 }
09196
09197 /**
09198   * @brief  Configure timing unit (Timer A to Timer F) in waveform mode
09199   * @param  hhrtim pointer to HAL HRTIM handle
09200   * @param  TimerIdx Timer index
09201   * @param  pTimerCfg pointer to the timer configuration data structure
09202   * @retval None
09203   */
09204 static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
09205                                              uint32_t TimerIdx,
09206                                              const HRTIM_TimerCfgTypeDef * pTimerCfg)
09207 {
09208   uint32_t hrtim_timcr;
09209   uint32_t hrtim_timfltr;
09210   uint32_t hrtim_timoutr;
09211   uint32_t hrtim_timrstr;
09212   uint32_t hrtim_bmcr;
09213
09214   /* UPDGAT bitfield must be reset before programming a new value */
09215   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
09216
09217   /* Configure timing unit (Timer A to Timer F) */
09218   hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
09219   hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
09220   hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
09221   hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
09222
09223   /* Enable/Disable the half mode */
09224   hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
09225   hrtim_timcr |= pTimerCfg->HalfModeEnable;
09226
09227   if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
09228   {
09229     /* INTLVD bits set to 00 */
09230     hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
09231     hrtim_timcr |= (HRTIM_TIMCR_HALF);
09232   }
09233   else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
09234   {
09235         hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
09236         hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
09237   }
09238   else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
09239   {
09240         hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
09241         hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
09242   }
09243   else
09244   {
09245         hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
09246         hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
09247   }
09248
09249   /* Enable/Disable the timer start upon synchronization event reception */
09250   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
09251   hrtim_timcr |= pTimerCfg->StartOnSync;
09252
09253   /* Enable/Disable the timer reset upon synchronization event reception */
09254   hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
09255   hrtim_timcr |= pTimerCfg->ResetOnSync;
09256
09257   /* Enable/Disable the DAC synchronization event generation */
09258   hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
09259   hrtim_timcr |= pTimerCfg->DACSynchro;
09260
09261   /* Enable/Disable preload mechanism for timer registers */
09262   hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
09263   hrtim_timcr |= pTimerCfg->PreloadEnable;
09264
09265   /* Timing unit registers update handling */
09266   hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
09267   hrtim_timcr |= pTimerCfg->UpdateGating;
09268
09269   /* Enable/Disable registers update on repetition */
09270   hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
09271   if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
09272   {
09273     hrtim_timcr |= HRTIM_TIMCR_TREPU;
09274   }
09275
09276   /* Set the push-pull mode */
09277   hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
09278   hrtim_timcr |= pTimerCfg->PushPull;
09279
09280   /* Enable/Disable registers update on timer counter reset */
09281   hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
09282   hrtim_timcr |= pTimerCfg->ResetUpdate;
09283
09284   /* Set the timer update trigger */
09285   hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
09286   hrtim_timcr |= pTimerCfg->UpdateTrigger;
09287
09288   /* Enable/Disable the fault channel at timer level */
09289   hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
09290   hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
09291
09292   /* Lock/Unlock fault sources at timer level */
09293   hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
09294   hrtim_timfltr |= pTimerCfg->FaultLock;
09295
09296     /* Enable/Disable dead time insertion at timer level */
09297     hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
09298     hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
09299
09300   /* Enable/Disable delayed protection at timer level
09301      Delayed Idle is available whatever the timer operating mode (regular, push-pull)
09302      Balanced Idle is only available in push-pull mode
09303   */
09304   if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
09305        && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
09306        || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
09307   {
09308     hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
09309     hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
09310   }
09311
09312   /* Set the BIAR mode : one bit for both outputs */
09313   hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
09314   hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
09315
09316   /* Set the timer counter reset trigger */
09317   hrtim_timrstr = pTimerCfg->ResetTrigger;
09318
09319   /* Set the timer burst mode */
09320   switch (TimerIdx)
09321   {
09322   case HRTIM_TIMERINDEX_TIMER_A:
09323     {
09324       hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
09325       hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
09326       break;
09327     }
09328
09329   case HRTIM_TIMERINDEX_TIMER_B:
09330     {
09331       hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
09332       hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
09333       break;
09334     }
09335
09336   case HRTIM_TIMERINDEX_TIMER_C:
09337     {
09338       hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
09339       hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
09340       break;
09341     }
09342
09343   case HRTIM_TIMERINDEX_TIMER_D:
09344     {
09345       hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
09346       hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
09347       break;
09348     }
09349
09350   case HRTIM_TIMERINDEX_TIMER_E:
09351     {
09352       hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
09353       hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
09354       break;
09355     }
09356
09357   case HRTIM_TIMERINDEX_TIMER_F:
09358     {
09359       hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
09360       hrtim_bmcr |= ( pTimerCfg->BurstMode << 6U);
09361       break;
09362     }
09363
09364   default:
09365     break;
09366   }
09367
09368   /* Update the HRTIM registers */
09369   hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
09370   hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
09371   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
09372   hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
09373   hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
09374 }
09375
09376 /**
09377   * @brief  Control timing unit (timer A to timer F) in waveform mode
09378   * @param  hhrtim pointer to HAL HRTIM handle
09379   * @param  TimerIdx Timer index
09380   * @param  pTimerCtl pointer to the timer configuration data structure
09381   * @retval None
09382   */
09383 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
09384                                              uint32_t TimerIdx,
09385                                              const HRTIM_TimerCtlTypeDef * pTimerCtl)
09386 {
09387    uint32_t hrtim_timcr2;
09388
09389    /* Configure timing unit (Timer A to Timer F) */
09390    hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
09391
09392    /* Set the UpDown counting Mode */
09393    hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
09394    hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
09395
09396    /* Set the TrigHalf Mode : requires the counter to be disabled */
09397    hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
09398    hrtim_timcr2 |= pTimerCtl->TrigHalf;
09399
09400    /* define the compare event operating mode */
09401    hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
09402    hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
09403
09404    /* define the compare event operating mode */
09405    hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
09406    hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
09407
09408    if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
09409    {
09410       /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
09411       hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
09412       hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
09413
09414       /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
09415       hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
09416       hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
09417
09418       /* Enable the DualChannel DAC trigger */
09419       hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
09420       hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
09421    }
09422    /* Update the HRTIM registers */
09423    hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2  = hrtim_timcr2;
09424
09425 }
09426
09427 /**
09428   * @brief  Configure timing RollOver Mode (Timer A to Timer F)
09429   * @param  hhrtim pointer to HAL HRTIM handle
09430   * @param  TimerIdx Timer index
09431   * @param  pRollOverMode: a combination of the timer RollOver Mode configuration
09432   * @retval None
09433   */
09434 static void  HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
09435                                              uint32_t TimerIdx,
09436                                              uint32_t pRollOverMode)
09437 {
09438   uint32_t hrtim_timcr2;
09439
09440   /* Configure timing unit (Timer A to Timer F) */
09441   hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
09442
09443   if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U)
09444   {
09445        /* xxROM bitfield must be reset before programming a new value */
09446        hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
09447                          HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
09448
09449        /* Update the HRTIM TIMxCR2 register */
09450        hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
09451                                         HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
09452
09453        hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
09454   }
09455 }
09456
09457 /**
09458   * @brief  Configure a capture unit
09459   * @param  hhrtim pointer to HAL HRTIM handle
09460   * @param  TimerIdx Timer index
09461   * @param  CaptureUnit Capture unit identifier
09462   * @param  Event Event reference
09463   * @retval None
09464   */
09465 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
09466                                     uint32_t TimerIdx,
09467                                     uint32_t CaptureUnit,
09468                                     uint32_t Event)
09469 {
09470   uint32_t CaptureTrigger = 0xFFFFFFFFU;
09471
09472   switch (Event)
09473   {
09474   case HRTIM_EVENT_1:
09475     {
09476       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
09477       break;
09478     }
09479
09480   case HRTIM_EVENT_2:
09481     {
09482       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
09483       break;
09484     }
09485
09486   case HRTIM_EVENT_3:
09487     {
09488       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
09489       break;
09490     }
09491
09492   case HRTIM_EVENT_4:
09493     {
09494       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
09495       break;
09496     }
09497
09498   case HRTIM_EVENT_5:
09499     {
09500       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
09501       break;
09502     }
09503
09504   case HRTIM_EVENT_6:
09505     {
09506       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
09507       break;
09508     }
09509
09510   case HRTIM_EVENT_7:
09511     {
09512       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
09513       break;
09514     }
09515
09516   case HRTIM_EVENT_8:
09517     {
09518       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
09519       break;
09520     }
09521
09522   case HRTIM_EVENT_9:
09523     {
09524       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
09525       break;
09526     }
09527
09528   case HRTIM_EVENT_10:
09529     {
09530       CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
09531       break;
09532     }
09533
09534   default:
09535     break;
09536   }
09537
09538   switch (CaptureUnit)
09539   {
09540   case HRTIM_CAPTUREUNIT_1:
09541     {
09542       hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
09543       break;
09544     }
09545
09546   case HRTIM_CAPTUREUNIT_2:
09547     {
09548       hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
09549       break;
09550     }
09551
09552   default:
09553     break;
09554   }
09555 }
09556
09557 /**
09558   * @brief  Configure the output of a timing unit
09559   * @param  hhrtim pointer to HAL HRTIM handle
09560   * @param  TimerIdx Timer index
09561   * @param  Output timing unit output identifier
09562   * @param  pOutputCfg pointer to the output configuration data structure
09563   * @retval None
09564   */
09565 static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
09566                                 uint32_t TimerIdx,
09567                                 uint32_t Output,
09568                                 const HRTIM_OutputCfgTypeDef * pOutputCfg)
09569 {
09570   uint32_t hrtim_outr;
09571   uint32_t hrtim_dtr;
09572
09573   uint32_t shift = 0U;
09574
09575   hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
09576   hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
09577
09578   switch (Output)
09579   {
09580   case HRTIM_OUTPUT_TA1:
09581   case HRTIM_OUTPUT_TB1:
09582   case HRTIM_OUTPUT_TC1:
09583   case HRTIM_OUTPUT_TD1:
09584   case HRTIM_OUTPUT_TE1:
09585   case HRTIM_OUTPUT_TF1:
09586     {
09587       /* Set the output set/reset crossbar */
09588       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
09589       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
09590       break;
09591     }
09592
09593   case HRTIM_OUTPUT_TA2:
09594   case HRTIM_OUTPUT_TB2:
09595   case HRTIM_OUTPUT_TC2:
09596   case HRTIM_OUTPUT_TD2:
09597   case HRTIM_OUTPUT_TE2:
09598   case HRTIM_OUTPUT_TF2:
09599     {
09600       /* Set the output set/reset crossbar */
09601       hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
09602       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
09603       shift = 16U;
09604       break;
09605     }
09606
09607   default:
09608     break;
09609   }
09610
09611   /* Clear output config */
09612   hrtim_outr &= ~((HRTIM_OUTR_POL1 |
09613                    HRTIM_OUTR_IDLM1 |
09614                    HRTIM_OUTR_IDLES1|
09615                    HRTIM_OUTR_FAULT1|
09616                    HRTIM_OUTR_CHP1 |
09617                    HRTIM_OUTR_DIDL1) << shift);
09618
09619   /* Set the polarity */
09620   hrtim_outr |= (pOutputCfg->Polarity << shift);
09621
09622   /* Set the IDLE mode */
09623   hrtim_outr |= (pOutputCfg->IdleMode << shift);
09624
09625   /* Set the IDLE state */
09626   hrtim_outr |= (pOutputCfg->IdleLevel << shift);
09627
09628   /* Set the FAULT state */
09629   hrtim_outr |= (pOutputCfg->FaultLevel << shift);
09630
09631   /* Set the chopper mode */
09632   hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
09633
09634   /* Set the burst mode entry mode : deadtime insertion when entering the idle
09635      state during a burst mode operation is allowed only under the following
09636      conditions:
09637      - the outputs is active during the burst mode (IDLES=1U)
09638      - positive deadtimes (SDTR/SDTF set to 0U)
09639   */
09640   if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
09641       ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
09642       ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
09643   {
09644     hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
09645   }
09646
09647   /* Update HRTIM register */
09648   hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
09649 }
09650
09651 /**
09652   * @brief  Configure an external event channel
09653   * @param  hhrtim pointer to HAL HRTIM handle
09654   * @param  Event Event channel identifier
09655   * @param  pEventCfg pointer to the event channel configuration data structure
09656   * @retval None
09657   */
09658 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
09659                               uint32_t Event,
09660                               const HRTIM_EventCfgTypeDef *pEventCfg)
09661 {
09662   uint32_t hrtim_eecr1;
09663   uint32_t hrtim_eecr2;
09664   uint32_t hrtim_eecr3;
09665
09666   /* Configure external event channel */
09667   hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
09668   hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
09669   hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
09670
09671   switch (Event)
09672   {
09673   case HRTIM_EVENT_NONE:
09674     {
09675       /* Update the HRTIM registers */
09676       hhrtim->Instance->sCommonRegs.EECR1 = 0U;
09677       hhrtim->Instance->sCommonRegs.EECR2 = 0U;
09678       hhrtim->Instance->sCommonRegs.EECR3 = 0U;
09679       break;
09680     }
09681
09682   case HRTIM_EVENT_1:
09683     {
09684       hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
09685       hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
09686       hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
09687       hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
09688       /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
09689       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09690       /* Update the HRTIM registers (EE1FAST bit) */
09691       hrtim_eecr1 |= (pEventCfg->FastMode  & HRTIM_EECR1_EE1FAST);
09692       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09693       break;
09694     }
09695
09696   case HRTIM_EVENT_2:
09697     {
09698       hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
09699       hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
09700       hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
09701       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
09702       /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
09703       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09704       /* Update the HRTIM registers (EE2FAST bit) */
09705       hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
09706       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09707       break;
09708     }
09709
09710   case HRTIM_EVENT_3:
09711     {
09712       hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
09713       hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
09714       hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
09715       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
09716       /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
09717       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09718       /* Update the HRTIM registers (EE3FAST bit) */
09719       hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
09720       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09721       break;
09722     }
09723
09724   case HRTIM_EVENT_4:
09725     {
09726       hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
09727       hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
09728       hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
09729       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
09730       /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
09731       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09732       /* Update the HRTIM registers (EE4FAST bit) */
09733       hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
09734       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09735       break;
09736     }
09737
09738   case HRTIM_EVENT_5:
09739     {
09740       hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
09741       hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
09742       hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
09743       hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
09744       /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
09745       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09746       /* Update the HRTIM registers (EE5FAST bit) */
09747       hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
09748       hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
09749       break;
09750     }
09751
09752   case HRTIM_EVENT_6:
09753     {
09754       hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
09755       hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
09756       hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
09757       hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
09758       hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
09759       hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
09760       /* Update the HRTIM registers */
09761       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
09762       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
09763       break;
09764     }
09765
09766   case HRTIM_EVENT_7:
09767     {
09768       hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
09769       hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
09770       hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
09771       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
09772       hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
09773       hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
09774       /* Update the HRTIM registers */
09775       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
09776       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
09777       break;
09778     }
09779
09780   case HRTIM_EVENT_8:
09781     {
09782       hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
09783       hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
09784       hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
09785       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
09786       hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
09787       hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
09788       /* Update the HRTIM registers */
09789       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
09790       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
09791       break;
09792     }
09793
09794   case HRTIM_EVENT_9:
09795     {
09796       hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
09797       hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
09798       hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
09799       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
09800       hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
09801       hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
09802       /* Update the HRTIM registers */
09803       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
09804       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
09805       break;
09806     }
09807
09808   case HRTIM_EVENT_10:
09809     {
09810       hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
09811       hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
09812       hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
09813       hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
09814       hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
09815       hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
09816       /* Update the HRTIM registers */
09817       hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
09818       hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
09819       break;
09820     }
09821
09822   default:
09823     break;
09824   }
09825 }
09826
09827 /**
09828   * @brief  Configure the timer counter reset
09829   * @param  hhrtim pointer to HAL HRTIM handle
09830   * @param  TimerIdx Timer index
09831   * @param  Event Event channel identifier
09832   * @retval None
09833   */
09834 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
09835                                   uint32_t TimerIdx,
09836                                   uint32_t Event)
09837 {
09838   switch (Event)
09839   {
09840   case HRTIM_EVENT_1:
09841     {
09842       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
09843       break;
09844     }
09845
09846   case HRTIM_EVENT_2:
09847     {
09848       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
09849       break;
09850     }
09851
09852   case HRTIM_EVENT_3:
09853     {
09854       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
09855       break;
09856     }
09857
09858   case HRTIM_EVENT_4:
09859     {
09860       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
09861       break;
09862     }
09863
09864   case HRTIM_EVENT_5:
09865     {
09866       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
09867       break;
09868     }
09869
09870   case HRTIM_EVENT_6:
09871     {
09872       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
09873       break;
09874     }
09875
09876   case HRTIM_EVENT_7:
09877     {
09878       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
09879       break;
09880     }
09881
09882   case HRTIM_EVENT_8:
09883     {
09884       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
09885       break;
09886     }
09887
09888   case HRTIM_EVENT_9:
09889     {
09890       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
09891       break;
09892     }
09893
09894   case HRTIM_EVENT_10:
09895     {
09896       hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
09897       break;
09898     }
09899
09900   default:
09901     break;
09902   }
09903 }
09904
09905 /**
09906   * @brief  Return the interrupt to enable or disable according to the
09907   *         OC mode.
09908   * @param  hhrtim pointer to HAL HRTIM handle
09909   * @param  TimerIdx Timer index
09910   * @param  OCChannel Timer output
09911   *                    This parameter can be one of the following values:
09912   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
09913   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
09914   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
09915   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
09916   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
09917   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
09918   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
09919   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
09920   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
09921   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
09922   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
09923   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
09924   * @retval Interrupt to enable or disable
09925   */
09926 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
09927                                       uint32_t TimerIdx,
09928                                       uint32_t OCChannel)
09929 {
09930   uint32_t hrtim_set;
09931   uint32_t hrtim_reset;
09932   uint32_t interrupt = 0U;
09933
09934   switch (OCChannel)
09935   {
09936   case HRTIM_OUTPUT_TA1:
09937   case HRTIM_OUTPUT_TB1:
09938   case HRTIM_OUTPUT_TC1:
09939   case HRTIM_OUTPUT_TD1:
09940   case HRTIM_OUTPUT_TE1:
09941   case HRTIM_OUTPUT_TF1:
09942     {
09943       /* Retreives actual OC mode and set interrupt accordingly */
09944       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
09945       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
09946
09947       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
09948           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
09949       {
09950         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
09951         interrupt = HRTIM_TIM_IT_CMP1;
09952       }
09953       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
09954                (hrtim_reset == 0U))
09955       {
09956          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
09957         interrupt = HRTIM_TIM_IT_SET1;
09958       }
09959       else if ((hrtim_set == 0U) &&
09960                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
09961       {
09962          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
09963         interrupt = HRTIM_TIM_IT_RST1;
09964       }
09965       else
09966       {
09967        /* nothing to do */
09968       }
09969       break;
09970     }
09971
09972   case HRTIM_OUTPUT_TA2:
09973   case HRTIM_OUTPUT_TB2:
09974   case HRTIM_OUTPUT_TC2:
09975   case HRTIM_OUTPUT_TD2:
09976   case HRTIM_OUTPUT_TE2:
09977   case HRTIM_OUTPUT_TF2:
09978     {
09979       /* Retreives actual OC mode and set interrupt accordingly */
09980       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
09981       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
09982
09983       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
09984           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
09985       {
09986         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
09987         interrupt = HRTIM_TIM_IT_CMP2;
09988       }
09989       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
09990                (hrtim_reset == 0U))
09991       {
09992          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
09993         interrupt = HRTIM_TIM_IT_SET2;
09994       }
09995       else if ((hrtim_set == 0U) &&
09996                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
09997       {
09998          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
09999         interrupt = HRTIM_TIM_IT_RST2;
10000       }
10001       else
10002       {
10003        /* nothing to do */
10004       }
10005       break;
10006     }
10007
10008   default:
10009     break;
10010   }
10011
10012   return interrupt;
10013 }
10014
10015 /**
10016   * @brief  Return the DMA request to enable or disable according to the
10017   *         OC mode.
10018   * @param  hhrtim pointer to HAL HRTIM handle
10019   * @param  TimerIdx Timer index
10020   * @param  OCChannel Timer output
10021   *                    This parameter can be one of the following values:
10022   *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
10023   *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
10024   *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
10025   *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
10026   *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
10027   *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
10028   *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
10029   *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
10030   *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
10031   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
10032   *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
10033   *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
10034   * @retval DMA request to enable or disable
10035   */
10036 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
10037                                        uint32_t TimerIdx,
10038                                        uint32_t OCChannel)
10039 {
10040   uint32_t hrtim_set;
10041   uint32_t hrtim_reset;
10042   uint32_t dma_request = 0U;
10043
10044   switch (OCChannel)
10045   {
10046   case HRTIM_OUTPUT_TA1:
10047   case HRTIM_OUTPUT_TB1:
10048   case HRTIM_OUTPUT_TC1:
10049   case HRTIM_OUTPUT_TD1:
10050   case HRTIM_OUTPUT_TE1:
10051   case HRTIM_OUTPUT_TF1:
10052     {
10053       /* Retreives actual OC mode and set dma_request accordingly */
10054       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
10055       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
10056
10057       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10058           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10059       {
10060         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10061         dma_request = HRTIM_TIM_DMA_CMP1;
10062       }
10063       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10064                (hrtim_reset == 0U))
10065       {
10066          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10067         dma_request = HRTIM_TIM_DMA_SET1;
10068       }
10069       else if ((hrtim_set == 0U) &&
10070                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10071       {
10072          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10073         dma_request = HRTIM_TIM_DMA_RST1;
10074       }
10075       else
10076       {
10077     /* nothing to do */
10078       }
10079       break;
10080     }
10081
10082   case HRTIM_OUTPUT_TA2:
10083   case HRTIM_OUTPUT_TB2:
10084   case HRTIM_OUTPUT_TC2:
10085   case HRTIM_OUTPUT_TD2:
10086   case HRTIM_OUTPUT_TE2:
10087   case HRTIM_OUTPUT_TF2:
10088     {
10089       /* Retreives actual OC mode and set dma_request accordingly */
10090       hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
10091       hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
10092
10093       if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10094           ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10095       {
10096         /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10097         dma_request = HRTIM_TIM_DMA_CMP2;
10098       }
10099       else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10100                (hrtim_reset == 0U))
10101       {
10102          /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10103         dma_request = HRTIM_TIM_DMA_SET2;
10104       }
10105       else if ((hrtim_set == 0U) &&
10106                ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10107       {
10108          /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10109         dma_request = HRTIM_TIM_DMA_RST2;
10110       }
10111       else
10112       {
10113     /* nothing to do */
10114       }
10115       break;
10116     }
10117
10118   default:
10119     break;
10120   }
10121
10122   return dma_request;
10123 }
10124
10125 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
10126                                                           uint32_t TimerIdx)
10127 {
10128   DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
10129
10130   switch (TimerIdx)
10131   {
10132   case HRTIM_TIMERINDEX_MASTER:
10133     {
10134       hdma = hhrtim->hdmaMaster;
10135       break;
10136     }
10137
10138   case HRTIM_TIMERINDEX_TIMER_A:
10139     {
10140       hdma = hhrtim->hdmaTimerA;
10141       break;
10142     }
10143
10144   case HRTIM_TIMERINDEX_TIMER_B:
10145     {
10146       hdma = hhrtim->hdmaTimerB;
10147       break;
10148     }
10149
10150   case HRTIM_TIMERINDEX_TIMER_C:
10151     {
10152       hdma = hhrtim->hdmaTimerC;
10153       break;
10154     }
10155
10156   case HRTIM_TIMERINDEX_TIMER_D:
10157     {
10158       hdma = hhrtim->hdmaTimerD;
10159       break;
10160     }
10161
10162   case HRTIM_TIMERINDEX_TIMER_E:
10163     {
10164       hdma = hhrtim->hdmaTimerE;
10165       break;
10166     }
10167
10168   case HRTIM_TIMERINDEX_TIMER_F:
10169     {
10170       hdma = hhrtim->hdmaTimerF;
10171       break;
10172     }
10173
10174   default:
10175     break;
10176   }
10177
10178   return hdma;
10179 }
10180
10181 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
10182                                          const DMA_HandleTypeDef * hdma)
10183 {
10184   uint32_t timed_idx = 0xFFFFFFFFU;
10185
10186   if (hdma == hhrtim->hdmaMaster)
10187   {
10188     timed_idx = HRTIM_TIMERINDEX_MASTER;
10189   }
10190   else if (hdma == hhrtim->hdmaTimerA)
10191   {
10192     timed_idx = HRTIM_TIMERINDEX_TIMER_A;
10193   }
10194   else if (hdma == hhrtim->hdmaTimerB)
10195   {
10196     timed_idx = HRTIM_TIMERINDEX_TIMER_B;
10197   }
10198   else if (hdma == hhrtim->hdmaTimerC)
10199   {
10200     timed_idx = HRTIM_TIMERINDEX_TIMER_C;
10201   }
10202   else if (hdma == hhrtim->hdmaTimerD)
10203   {
10204     timed_idx = HRTIM_TIMERINDEX_TIMER_D;
10205   }
10206   else if (hdma == hhrtim->hdmaTimerE)
10207   {
10208     timed_idx = HRTIM_TIMERINDEX_TIMER_E;
10209   }
10210   else if (hdma == hhrtim->hdmaTimerF)
10211   {
10212     timed_idx = HRTIM_TIMERINDEX_TIMER_F;
10213   }
10214   else
10215   {
10216     /* nothing to do */
10217   }
10218   return timed_idx;
10219 }
10220
10221 /**
10222   * @brief  Force an immediate transfer from the preload to the active
10223   *         registers.
10224   * @param  hhrtim pointer to HAL HRTIM handle
10225   * @param  TimerIdx Timer index
10226   * @retval None
10227   */
10228 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
10229                                        uint32_t TimerIdx)
10230 {
10231   switch (TimerIdx)
10232   {
10233   case HRTIM_TIMERINDEX_MASTER:
10234     {
10235       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
10236       break;
10237     }
10238
10239   case HRTIM_TIMERINDEX_TIMER_A:
10240     {
10241       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
10242       break;
10243     }
10244
10245   case HRTIM_TIMERINDEX_TIMER_B:
10246     {
10247       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
10248       break;
10249     }
10250
10251   case HRTIM_TIMERINDEX_TIMER_C:
10252     {
10253       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
10254       break;
10255     }
10256
10257   case HRTIM_TIMERINDEX_TIMER_D:
10258     {
10259       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
10260       break;
10261     }
10262
10263   case HRTIM_TIMERINDEX_TIMER_E:
10264     {
10265       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
10266       break;
10267     }
10268
10269   case HRTIM_TIMERINDEX_TIMER_F:
10270     {
10271       hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
10272       break;
10273     }
10274
10275   default:
10276     break;
10277   }
10278 }
10279
10280
10281 /**
10282   * @brief  HRTIM interrupts service routine
10283   * @param  hhrtim pointer to HAL HRTIM handle
10284   * @retval None
10285   */
10286 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
10287 {
10288   uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10289   uint32_t ierits   = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10290
10291   /* Fault 1 event */
10292   if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
10293   {
10294     if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
10295     {
10296       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
10297
10298       /* Invoke Fault 1 event callback */
10299 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10300       hhrtim->Fault1Callback(hhrtim);
10301 #else
10302       HAL_HRTIM_Fault1Callback(hhrtim);
10303 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10304     }
10305   }
10306
10307   /* Fault 2 event */
10308   if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
10309   {
10310     if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
10311     {
10312       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
10313
10314       /* Invoke Fault 2 event callback */
10315 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10316       hhrtim->Fault2Callback(hhrtim);
10317 #else
10318       HAL_HRTIM_Fault2Callback(hhrtim);
10319 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10320     }
10321   }
10322
10323   /* Fault 3 event */
10324   if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
10325   {
10326     if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
10327     {
10328       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
10329
10330       /* Invoke Fault 3 event callback */
10331 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10332       hhrtim->Fault3Callback(hhrtim);
10333 #else
10334       HAL_HRTIM_Fault3Callback(hhrtim);
10335 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10336     }
10337   }
10338
10339   /* Fault 4 event */
10340   if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
10341   {
10342     if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
10343     {
10344       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
10345
10346       /* Invoke Fault 4 event callback */
10347 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10348       hhrtim->Fault4Callback(hhrtim);
10349 #else
10350       HAL_HRTIM_Fault4Callback(hhrtim);
10351 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10352     }
10353   }
10354
10355   /* Fault 5 event */
10356   if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
10357   {
10358     if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
10359     {
10360       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
10361
10362       /* Invoke Fault 5 event callback */
10363 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10364       hhrtim->Fault5Callback(hhrtim);
10365 #else
10366       HAL_HRTIM_Fault5Callback(hhrtim);
10367 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10368     }
10369   }
10370
10371   /* Fault 6 event */
10372   if((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET)
10373   {
10374     if((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET)
10375     {
10376       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
10377
10378       /* Invoke Fault 6 event callback */
10379 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10380       hhrtim->Fault6Callback(hhrtim);
10381 #else
10382       HAL_HRTIM_Fault6Callback(hhrtim);
10383 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10384     }
10385   }
10386
10387   /* System fault event */
10388   if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
10389   {
10390     if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
10391     {
10392       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
10393
10394       /* Invoke System fault event callback */
10395 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10396       hhrtim->SystemFaultCallback(hhrtim);
10397 #else
10398       HAL_HRTIM_SystemFaultCallback(hhrtim);
10399 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10400     }
10401   }
10402 }
10403
10404 /**
10405 * @brief  Master timer interrupts service routine
10406 * @param  hhrtim pointer to HAL HRTIM handle
10407 * @retval None
10408 */
10409 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
10410 {
10411   uint32_t isrflags  = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10412   uint32_t ierits    = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10413   uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
10414   uint32_t mdierits  = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
10415
10416   /* DLL calibration ready event */
10417   if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
10418   {
10419     if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
10420     {
10421       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
10422
10423       /* Set HRTIM State */
10424       hhrtim->State = HAL_HRTIM_STATE_READY;
10425
10426       /* Process unlocked */
10427       __HAL_UNLOCK(hhrtim);
10428
10429       /* Invoke System fault event callback */
10430 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10431       hhrtim->DLLCalibrationReadyCallback(hhrtim);
10432 #else
10433       HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
10434 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10435     }
10436   }
10437
10438   /* Burst mode period event */
10439   if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
10440   {
10441     if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
10442     {
10443       __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
10444
10445       /* Invoke Burst mode period event callback */
10446 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10447       hhrtim->BurstModePeriodCallback(hhrtim);
10448 #else
10449       HAL_HRTIM_BurstModePeriodCallback(hhrtim);
10450 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10451     }
10452   }
10453
10454   /* Master timer compare 1 event */
10455   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
10456   {
10457     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
10458     {
10459       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
10460
10461       /* Invoke compare 1 event callback */
10462 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10463       hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10464 #else
10465       HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10466 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10467     }
10468   }
10469
10470   /* Master timer compare 2 event */
10471   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
10472   {
10473     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
10474     {
10475       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
10476
10477       /* Invoke compare 2 event callback */
10478 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10479       hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10480 #else
10481       HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10482 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10483     }
10484   }
10485
10486   /* Master timer compare 3 event */
10487   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
10488   {
10489     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
10490     {
10491       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
10492
10493       /* Invoke compare 3 event callback */
10494 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10495       hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10496 #else
10497       HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10498 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10499     }
10500   }
10501
10502   /* Master timer compare 4 event */
10503   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
10504   {
10505     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
10506     {
10507       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
10508
10509       /* Invoke compare 4 event callback */
10510 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10511       hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10512 #else
10513       HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10514 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10515     }
10516   }
10517
10518   /* Master timer repetition event */
10519   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
10520   {
10521     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
10522     {
10523       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
10524
10525       /* Invoke repetition event callback */
10526 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10527       hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10528 #else
10529       HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10530 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10531     }
10532   }
10533
10534   /* Synchronization input event */
10535   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
10536   {
10537     if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
10538     {
10539       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
10540
10541       /* Invoke synchronization event callback */
10542 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10543       hhrtim->SynchronizationEventCallback(hhrtim);
10544 #else
10545       HAL_HRTIM_SynchronizationEventCallback(hhrtim);
10546 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10547     }
10548   }
10549
10550   /* Master timer registers update event */
10551   if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
10552   {
10553     if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
10554     {
10555       __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
10556
10557       /* Invoke registers update event callback */
10558 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10559       hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10560 #else
10561       HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10562 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10563     }
10564   }
10565 }
10566
10567 /**
10568   * @brief  Timer interrupts service routine
10569   * @param  hhrtim pointer to HAL HRTIM handle
10570   * @param  TimerIdx Timer index
10571   *                   This parameter can be one of the following values:
10572   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
10573   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
10574   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
10575   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
10576   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
10577   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
10578   * @retval None
10579 */
10580 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
10581                      uint32_t TimerIdx)
10582 {
10583   uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
10584   uint32_t tdierits  = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
10585
10586   /* Timer compare 1 event */
10587   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
10588   {
10589     if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
10590     {
10591       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
10592
10593       /* Invoke compare 1 event callback */
10594 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10595       hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
10596 #else
10597       HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
10598 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10599     }
10600   }
10601
10602   /* Timer compare 2 event */
10603   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
10604   {
10605     if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
10606     {
10607       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
10608
10609       /* Invoke compare 2 event callback */
10610 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10611       hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
10612 #else
10613       HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
10614 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10615     }
10616   }
10617
10618   /* Timer compare 3 event */
10619   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
10620   {
10621     if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
10622     {
10623       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
10624
10625       /* Invoke compare 3 event callback */
10626 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10627       hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
10628 #else
10629       HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
10630 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10631     }
10632   }
10633
10634   /* Timer compare 4 event */
10635   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
10636   {
10637     if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
10638     {
10639       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
10640
10641       /* Invoke compare 4 event callback */
10642 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10643       hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
10644 #else
10645       HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
10646 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10647     }
10648   }
10649
10650   /* Timer repetition event */
10651   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
10652   {
10653     if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
10654     {
10655       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
10656
10657       /* Invoke repetition event callback */
10658 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10659       hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
10660 #else
10661       HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
10662 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10663     }
10664   }
10665
10666   /* Timer registers update event */
10667   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
10668   {
10669     if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
10670     {
10671       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
10672
10673       /* Invoke registers update event callback */
10674 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10675       hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
10676 #else
10677       HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
10678 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10679     }
10680   }
10681
10682   /* Timer capture 1 event */
10683   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
10684   {
10685     if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
10686     {
10687       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
10688
10689       /* Invoke capture 1 event callback */
10690 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10691       hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
10692 #else
10693       HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
10694 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10695     }
10696   }
10697
10698   /* Timer capture 2 event */
10699   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
10700   {
10701     if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
10702     {
10703       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
10704
10705       /* Invoke capture 2 event callback */
10706 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10707       hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
10708 #else
10709       HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
10710 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10711     }
10712   }
10713
10714   /* Timer output 1 set event */
10715   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
10716   {
10717     if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
10718     {
10719       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
10720
10721       /* Invoke output 1 set event callback */
10722 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10723       hhrtim->Output1SetCallback(hhrtim, TimerIdx);
10724 #else
10725       HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
10726 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10727     }
10728   }
10729
10730   /* Timer output 1 reset event */
10731   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
10732   {
10733     if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
10734     {
10735       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
10736
10737       /* Invoke output 1 reset event callback */
10738 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10739       hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
10740 #else
10741       HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
10742 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10743     }
10744   }
10745
10746   /* Timer output 2 set event */
10747   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
10748   {
10749     if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
10750     {
10751       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
10752
10753       /* Invoke output 2 set event callback */
10754 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10755       hhrtim->Output2SetCallback(hhrtim, TimerIdx);
10756 #else
10757       HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
10758 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10759     }
10760   }
10761
10762   /* Timer output 2 reset event */
10763   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
10764   {
10765     if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
10766     {
10767       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
10768
10769       /* Invoke output 2 reset event callback */
10770 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10771       hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
10772 #else
10773       HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
10774 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10775     }
10776   }
10777
10778   /* Timer reset event */
10779   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
10780   {
10781     if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
10782     {
10783       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
10784
10785       /* Invoke timer reset callback */
10786 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10787       hhrtim->CounterResetCallback(hhrtim, TimerIdx);
10788 #else
10789       HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
10790 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10791     }
10792   }
10793
10794   /* Delayed protection event */
10795   if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
10796   {
10797     if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
10798     {
10799       __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
10800
10801       /* Invoke delayed protection callback */
10802 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10803       hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
10804 #else
10805       HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
10806 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10807     }
10808   }
10809 }
10810
10811 /**
10812   * @brief  DMA callback invoked upon master timer related DMA request completion
10813   * @param  hdma pointer to DMA handle.
10814   * @retval None
10815   */
10816 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
10817 {
10818   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10819
10820   if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
10821   {
10822 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10823     hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10824 #else
10825     HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10826 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10827   }
10828   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
10829   {
10830 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10831     hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10832 #else
10833     HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10834 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10835   }
10836   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
10837   {
10838 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10839     hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10840 #else
10841     HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10842 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10843   }
10844   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
10845   {
10846 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10847     hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10848 #else
10849     HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10850 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10851   }
10852   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
10853   {
10854 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10855     hrtim->SynchronizationEventCallback(hrtim);
10856 #else
10857     HAL_HRTIM_SynchronizationEventCallback(hrtim);
10858 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10859   }
10860   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
10861   {
10862 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10863     hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10864 #else
10865     HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10866 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10867   }
10868   else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
10869   {
10870 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10871     hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10872 #else
10873     HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10874 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10875   }
10876   else
10877   {
10878     /* nothing to do */
10879   }
10880 }
10881
10882 /**
10883   * @brief  DMA callback invoked upon timer A..F related DMA request completion
10884   * @param  hdma pointer to DMA handle.
10885   * @retval None
10886   */
10887 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
10888 {
10889   uint8_t timer_idx;
10890
10891   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10892
10893   timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
10894
10895   if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
10896
10897   if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
10898   {
10899 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10900     hrtim->Compare1EventCallback(hrtim, timer_idx);
10901 #else
10902     HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
10903 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10904   }
10905   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
10906   {
10907 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10908     hrtim->Compare2EventCallback(hrtim, timer_idx);
10909 #else
10910     HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
10911 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10912   }
10913   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
10914   {
10915 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10916     hrtim->Compare3EventCallback(hrtim, timer_idx);
10917 #else
10918     HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
10919 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10920   }
10921   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
10922   {
10923 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10924     hrtim->Compare4EventCallback(hrtim, timer_idx);
10925 #else
10926     HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
10927 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10928   }
10929   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
10930   {
10931 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10932     hrtim->RegistersUpdateCallback(hrtim, timer_idx);
10933 #else
10934     HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
10935 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10936   }
10937   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
10938   {
10939 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10940     hrtim->Capture1EventCallback(hrtim, timer_idx);
10941 #else
10942     HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
10943 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10944   }
10945   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
10946   {
10947 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10948     hrtim->Capture2EventCallback(hrtim, timer_idx);
10949 #else
10950     HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
10951 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10952   }
10953   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
10954   {
10955 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10956     hrtim->Output1SetCallback(hrtim, timer_idx);
10957 #else
10958     HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
10959 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10960   }
10961   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
10962   {
10963 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10964     hrtim->Output1ResetCallback(hrtim, timer_idx);
10965 #else
10966     HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
10967 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10968   }
10969   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
10970   {
10971 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10972     hrtim->Output2SetCallback(hrtim, timer_idx);
10973 #else
10974     HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
10975 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10976   }
10977   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
10978   {
10979 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10980     hrtim->Output2ResetCallback(hrtim, timer_idx);
10981 #else
10982     HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
10983 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10984   }
10985   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
10986   {
10987 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10988     hrtim->CounterResetCallback(hrtim, timer_idx);
10989 #else
10990     HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
10991 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10992   }
10993   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
10994   {
10995 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10996     hrtim->DelayedProtectionCallback(hrtim, timer_idx);
10997 #else
10998     HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
10999 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11000   }
11001   else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
11002   {
11003 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11004     hrtim->RepetitionEventCallback(hrtim, timer_idx);
11005 #else
11006     HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
11007 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11008   }
11009   else
11010   {
11011     /* nothing to do */
11012   }
11013 }
11014
11015 /**
11016 * @brief  DMA error callback
11017 * @param  hdma pointer to DMA handle.
11018 * @retval None
11019 */
11020 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
11021 {
11022   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11023
11024 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11025     hrtim->ErrorCallback(hrtim);
11026 #else
11027   HAL_HRTIM_ErrorCallback(hrtim);
11028 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11029 }
11030
11031 /**
11032   * @brief  DMA callback invoked upon burst DMA transfer completion
11033   * @param  hdma pointer to DMA handle.
11034   * @retval None
11035   */
11036 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
11037 {
11038   HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11039
11040 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11041     hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11042 #else
11043   HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11044 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11045 }
11046
11047 /**
11048   * @}
11049   */
11050
11051 /**
11052   * @}
11053   */
11054
11055 #endif /* HRTIM1 */
11056
11057 #endif /* HAL_HRTIM_MODULE_ENABLED */
11058
11059 /**
11060   * @}
11061   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_hrtim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_hrtim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_HRTIM_H
00021 #define STM32G4xx_HAL_HRTIM_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined(HRTIM1)
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup HRTIM HRTIM
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
00041   * @{
00042   */
00043 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
00044   * @{
00045   */
00046 #define MAX_HRTIM_TIMER 7U
00047 /**
00048   * @}
00049   */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
00055   * @{
00056   */
00057
00058 /**
00059   * @brief  HRTIM Configuration Structure definition - Time base related parameters
00060   */
00061 typedef struct
00062 {
00063   uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
00064                                           This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
00065   uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.
00066                                           The HRTIM instance can be configured to act as a slave (waiting for a trigger
00067                                           to be synchronized) or a master (generating a synchronization signal) or both.
00068                                           This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
00069   uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when
00070                                           the HRTIM instance is configured as a slave).
00071                                           This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
00072   uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
00073                                          (significant only when the HRTIM instance is configured as a master).
00074                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
00075   uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization
00076                                           outputs (significant only when the HRTIM instance is configured as a master).
00077                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
00078 } HRTIM_InitTypeDef;
00079
00080 /**
00081   * @brief  HAL State structures definition
00082   */
00083 typedef enum
00084 {
00085   HAL_HRTIM_STATE_RESET            = 0x00U,    /*!< Peripheral is not yet Initialized                  */
00086   HAL_HRTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00087   HAL_HRTIM_STATE_BUSY             = 0x02U,    /*!< an internal process is ongoing                     */
00088   HAL_HRTIM_STATE_TIMEOUT          = 0x06U,    /*!< Timeout state                                      */
00089   HAL_HRTIM_STATE_ERROR            = 0x07U,    /*!< Error state                                        */
00090 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00091   HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U    /*!< Invalid Callback error */
00092 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00093 } HAL_HRTIM_StateTypeDef;
00094
00095 /**
00096   * @brief HRTIM Timer Structure definition
00097   */
00098 typedef struct
00099 {
00100   uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
00101                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00102                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00103   uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
00104                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
00105                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
00106   uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
00107   uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
00108   uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
00109   uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
00110   uint32_t DMASize;                /*!< Size of the DMA transfer */
00111 } HRTIM_TimerParamTypeDef;
00112
00113 /**
00114   * @brief  HRTIM Handle Structure definition
00115   */
00116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00117 typedef struct __HRTIM_HandleTypeDef
00118 #else
00119 typedef struct
00120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00121 {
00122   HRTIM_TypeDef *              Instance;                     /*!< Register base address */
00123
00124   HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
00125
00126   HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
00127
00128   HAL_LockTypeDef              Lock;                         /*!< Locking object          */
00129
00130   __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
00131
00132   DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */
00133   DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */
00134   DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */
00135   DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */
00136   DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */
00137   DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */
00138   DMA_HandleTypeDef *          hdmaTimerF;                   /*!< Timer F DMA handle parameters */
00139
00140 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00141   void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 1 interrupt callback function pointer                         */
00142   void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 2 interrupt callback function pointer                         */
00143   void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 3 interrupt callback function pointer                         */
00144   void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 4 interrupt callback function pointer                         */
00145   void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 5 interrupt callback function pointer                         */
00146   void (* Fault6Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 6 interrupt callback function pointer                         */
00147   void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                          /*!< System fault interrupt callback function pointer                    */
00148   void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                   /*!< DLL Ready interrupt callback function pointer                       */
00149   void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                      /*!< Burst mode period interrupt callback function pointer               */
00150   void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                 /*!< Sync Input interrupt callback function pointer                      */
00151   void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                                /*!< DMA error callback function pointer                                 */
00152
00153   void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Update interrupt callback function pointer                  */
00154   void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Repetition interrupt callback function pointer              */
00155   void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 1 match interrupt callback function pointer         */
00156   void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 2 match interrupt callback function pointer         */
00157   void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 3 match interrupt callback function pointer         */
00158   void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 4 match interrupt callback function pointer         */
00159   void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 1 interrupts callback function pointer              */
00160   void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 2 interrupts callback function pointer              */
00161   void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer      */
00162   void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x counter reset/roll-over interrupt callback function pointer */
00163   void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 1 set interrupt callback function pointer            */
00164   void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 1 reset interrupt callback function pointer          */
00165   void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 2 set interrupt callback function pointer            */
00166   void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 2 reset interrupt callback function pointer          */
00167   void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);  /*!< Timer x Burst DMA completed interrupt callback function pointer     */
00168
00169   void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                              /*!< HRTIM MspInit callback function pointer                             */
00170   void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                            /*!< HRTIM MspInit callback function pointer                             */
00171 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00172 } HRTIM_HandleTypeDef;
00173
00174 /**
00175   * @brief  Simple output compare mode configuration definition
00176   */
00177 typedef struct
00178 {
00179   uint32_t Period;                   /*!< Specifies the timer period.
00180                                           The period value must be above 3 periods of the fHRTIM clock.
00181                                           Maximum value is = 0xFFDFU */
00182   uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.
00183                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00184   uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
00185                                           This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
00186   uint32_t Mode;                     /*!< Specifies the counter operating mode.
00187                                           This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */
00188 } HRTIM_TimeBaseCfgTypeDef;
00189
00190 /**
00191   * @brief  Simple output compare mode configuration definition
00192   */
00193 typedef struct
00194 {
00195   uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).
00196                             This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
00197   uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
00198                             The compare value must be above or equal to 3 periods of the fHRTIM clock */
00199   uint32_t Polarity;   /*!< Specifies the output polarity.
00200                             This parameter can be any value of @ref HRTIM_Output_Polarity */
00201   uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.
00202                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00203 } HRTIM_SimpleOCChannelCfgTypeDef;
00204
00205 /**
00206   * @brief  Simple PWM output mode configuration definition
00207   */
00208 typedef struct
00209 {
00210   uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
00211                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
00212   uint32_t Polarity;        /*!< Specifies the output polarity.
00213                                  This parameter can be any value of @ref HRTIM_Output_Polarity */
00214   uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.
00215                                  This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00216 } HRTIM_SimplePWMChannelCfgTypeDef;
00217
00218 /**
00219   * @brief  Simple capture mode configuration definition
00220   */
00221 typedef struct
00222 {
00223   uint32_t Event;             /*!< Specifies the external event triggering the capture.
00224                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00225   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00226                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00227   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00228                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00229   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00230                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00231 } HRTIM_SimpleCaptureChannelCfgTypeDef;
00232
00233 /**
00234   * @brief  Simple One Pulse mode configuration definition
00235   */
00236 typedef struct
00237 {
00238   uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
00239                                    The compare value must be above or equal to 3 periods of the fHRTIM clock */
00240   uint32_t OutputPolarity;    /*!< Specifies the output polarity.
00241                                    This parameter can be any value of @ref HRTIM_Output_Polarity */
00242   uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.
00243                                    This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00244   uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.
00245                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
00246   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
00247                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00248   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
00249                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
00250   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00251                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
00252 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
00253
00254 /**
00255   * @brief  Timer configuration definition
00256   */
00257 typedef struct
00258 {
00259   uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.
00260                                        Specifies which interrupts requests must enabled for the timer.
00261                                        This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
00262                                        or @ref HRTIM_Timing_Unit_Interrupt_Enable */
00263   uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.
00264                                        Specifies which DMA requests must be enabled for the timer.
00265                                        This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
00266                                        or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
00267   uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.
00268                                        Specifies the address of the source address of the DMA transfer */
00269   uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.
00270                                        Specifies the address of the destination address of the DMA transfer */
00271   uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.
00272                                        Specifies the size of the DMA transfer */
00273   uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.
00274                                         Specifies whether or not half mode is enabled
00275                                         This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
00276   uint32_t InterleavedMode;         /*!< Relevant for all HRTIM timers, including the master.
00277                                         Specifies whether or not half mode is enabled
00278                                         This parameter can be any value of @ref HRTIM_Interleaved_Mode  */
00279   uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00280                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00281                                         This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
00282   uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.
00283                                         Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
00284                                         This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
00285   uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.
00286                                         Indicates whether or not the a DAC synchronization event is generated.
00287                                         This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
00288   uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.
00289                                         Specifies whether or not register preload is enabled.
00290                                         This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
00291   uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.
00292                                         Specifies how the update occurs with respect to a burst DMA transaction or
00293                                         update enable inputs (Slave timers only).
00294                                         This parameter can be any value of @ref HRTIM_Update_Gating   */
00295   uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.
00296                                         Specifies how the timer behaves during a burst mode operation.
00297                                         This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
00298   uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.
00299                                         Specifies whether or not registers update is triggered by the repetition event.
00300                                         This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
00301   uint32_t PushPull;               /*!< Relevant for Timer A to Timer F.
00302                                         Specifies whether or not the push-pull mode is enabled.
00303                                         This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
00304   uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer F.
00305                                         Specifies which fault channels are enabled for the timer.
00306                                         This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
00307   uint32_t FaultLock;              /*!< Relevant for Timer A to Timer F.
00308                                         Specifies whether or not fault enabling status is write protected.
00309                                         This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
00310   uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer F.
00311                                         Specifies whether or not dead-time insertion is enabled for the timer.
00312                                         This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
00313   uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer F.
00314                                         Specifies the delayed protection mode.
00315                                         This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
00316   uint32_t BalancedIdleAutomaticResume; /*!< Indicates whether or not outputs are automatically re-enabled after a balanced idle event.
00317                                              This parameters can be any value of @ref HRTIM_Output_Balanced_Idle_Auto_Resume */
00318   uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer F.
00319                                         Specifies source(s) triggering the timer registers update.
00320                                         This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
00321   uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer F.
00322                                         Specifies source(s) triggering the timer counter reset.
00323                                         This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
00324   uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer F.
00325                                         Specifies whether or not registers update is triggered when the timer counter is reset.
00326                                         This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
00327   uint32_t ReSyncUpdate;          /*!<  Relevant for Timer A to Timer F.
00328                                         Specifies whether update source is coming from the timing unit @ref HRTIM_Timer_ReSyncUpdate */
00329
00330 } HRTIM_TimerCfgTypeDef;
00331
00332 /**
00333   * @brief  Timer control definition
00334   */
00335 typedef struct
00336 {
00337   uint32_t UpDownMode;            /*!<  Relevant for Timer A to Timer F.
00338                                         Specifies whether or not counter is operating in up or up-down counting mode.
00339                                         This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */
00340   uint32_t TrigHalf;              /*!<  Relevant for Timer A to Timer F.
00341                                         Specifies whether or not compare 2 is operating in Trigger half mode.
00342                                         This parameter can be a value of @ref HRTIM_Timer_TrigHalf_Mode */
00343   uint32_t GreaterCMP3;           /*!<  Relevant for Timer A to Timer F.
00344                                         Specifies whether or not compare 3 is operating in compare match or greater mode.
00345                                         This parameter can be a value of @ref HRTIM_Timer_GreaterCMP3_Mode */
00346   uint32_t GreaterCMP1;           /*!<  Relevant for Timer A to Timer F.
00347                                         Specifies whether or not compare 1 is operating in compare match or greater mode.
00348                                         This parameter can be a value of @ref HRTIM_Timer_GreaterCMP1_Mode */
00349   uint32_t DualChannelDacReset;   /*!<  Relevant for Timer A to Timer F.
00350                                         Specifies how the hrtim_dac_reset_trgx trigger is generated.
00351                                         This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Reset */
00352   uint32_t DualChannelDacStep;    /*!<  Relevant for Timer A to Timer F.
00353                                         Specifies how the hrtim_dac_step_trgx trigger is generated.
00354                                         This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Step */
00355   uint32_t DualChannelDacEnable;  /*!<  Relevant for Timer A to Timer F.
00356                                         Enables or not the dual channel DAC triggering mechanism.
00357                                         This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Enable */
00358 } HRTIM_TimerCtlTypeDef;
00359
00360 /**
00361   * @brief  Compare unit configuration definition
00362   */
00363 typedef struct
00364 {
00365   uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.
00366                                       The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
00367                                       The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
00368   uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.
00369                                       This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
00370   uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
00371                                       CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */
00372 } HRTIM_CompareCfgTypeDef;
00373
00374 /**
00375   * @brief  Capture unit content definition
00376   */
00377 typedef struct
00378 {
00379   uint32_t Value;     /*!< Holds the counter value when the capture event occurred.
00380                            This parameter can be a number between 0x0 and 0xFFFFU */
00381   uint32_t Dir ;     /*!< Holds the counting direction value  when the capture event occurred.
00382                            This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode  */
00383 } HRTIM_CaptureValueTypeDef;
00384
00385 /**
00386   * @brief  Capture unit configuration definition
00387   */
00388 typedef struct
00389 {
00390   uint64_t Trigger;          /*!< Specifies source(s) triggering the capture.
00391                                   This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
00392 } HRTIM_CaptureCfgTypeDef;
00393
00394 /**
00395   * @brief  Output configuration definition
00396   */
00397 typedef struct
00398 {
00399   uint32_t Polarity;                    /*!< Specifies the output polarity.
00400                                              This parameter can be any value of @ref HRTIM_Output_Polarity */
00401   uint32_t SetSource;                   /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
00402                                              This parameter can be a combination of @ref HRTIM_Output_Set_Source */
00403   uint32_t ResetSource;                 /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
00404                                              This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
00405   uint32_t IdleMode;                    /*!< Specifies whether or not the output is affected by a burst mode operation.
00406                                              This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
00407   uint32_t IdleLevel;                   /*!< Specifies whether the output level is active or inactive when in IDLE state.
00408                                              This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
00409   uint32_t FaultLevel;                  /*!< Specifies whether the output level is active or inactive when in FAULT state.
00410                                              This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
00411   uint32_t ChopperModeEnable;           /*!< Indicates whether or not the chopper mode is enabled
00412                                              This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
00413   uint32_t BurstModeEntryDelayed;       /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
00414                                              This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
00415 } HRTIM_OutputCfgTypeDef;
00416
00417 /**
00418   * @brief  External event filtering in timing units configuration definition
00419   */
00420 typedef struct
00421 {
00422   uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.
00423                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
00424   uint32_t Latch;       /*!< Specifies whether or not the signal is latched.
00425                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
00426 } HRTIM_TimerEventFilteringCfgTypeDef;
00427
00428 /**
00429   * @brief  Dead time feature configuration definition
00430   */
00431 typedef struct
00432 {
00433   uint32_t Prescaler;        /*!< Specifies the dead-time prescaler.
00434                                   This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
00435   uint32_t RisingValue;      /*!< Specifies the dead-time following a rising edge.
00436                                   This parameter can be a number between 0x0 and 0x1FFU */
00437   uint32_t RisingSign;       /*!< Specifies whether the dead-time is positive or negative on rising edge.
00438                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
00439   uint32_t RisingLock;       /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
00440                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
00441   uint32_t RisingSignLock;   /*!< Specifies whether or not dead-time rising sign is write protected.
00442                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
00443   uint32_t FallingValue;     /*!< Specifies the dead-time following a falling edge.
00444                                   This parameter can be a number between 0x0 and 0x1FFU */
00445   uint32_t FallingSign;      /*!< Specifies whether the dead-time is positive or negative on falling edge.
00446                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
00447   uint32_t FallingLock;      /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
00448                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
00449   uint32_t FallingSignLock;  /*!< Specifies whether or not dead-time falling sign is write protected.
00450                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
00451 } HRTIM_DeadTimeCfgTypeDef;
00452
00453 /**
00454   * @brief  Chopper mode configuration definition
00455   */
00456 typedef struct
00457 {
00458   uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
00459                               This parameter can be a value of @ref HRTIM_Chopper_Frequency */
00460   uint32_t DutyCycle;    /*!< Specifies the Timer chopper duty cycle value.
00461                               This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
00462   uint32_t StartPulse;   /*!< Specifies the Timer pulse width value.
00463                               This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
00464 } HRTIM_ChopperModeCfgTypeDef;
00465
00466 /**
00467   * @brief  External event channel configuration definition
00468   */
00469 typedef struct
00470 {
00471   uint32_t Source;        /*!< Identifies the source of the external event.
00472                                This parameter can be a value of @ref HRTIM_External_Event_Sources */
00473   uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).
00474                                This parameter can be a value of @ref HRTIM_External_Event_Polarity */
00475   uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.
00476                                This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
00477   uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
00478                                This parameter can be a value of @ref HRTIM_External_Event_Filter */
00479   uint32_t FastMode;      /*!< Indicates whether or not low latency mode is enabled for the external event.
00480                                This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
00481 } HRTIM_EventCfgTypeDef;
00482
00483 /**
00484   * @brief  Fault channel configuration definition
00485   */
00486 typedef struct
00487 {
00488   uint32_t Source;        /*!< Identifies the source of the fault.
00489                                This parameter can be a value of @ref HRTIM_Fault_Sources */
00490   uint32_t Polarity;      /*!< Specifies the polarity of the fault event.
00491                                This parameter can be a value of @ref HRTIM_Fault_Polarity */
00492   uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
00493                                This parameter can be a value of @ref HRTIM_Fault_Filter */
00494   uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.
00495                                This parameter can be a value of @ref HRTIM_Fault_Lock */
00496 } HRTIM_FaultCfgTypeDef;
00497
00498 typedef struct
00499 {
00500   uint32_t Threshold;     /*!< Specifies the Fault counter Threshold.
00501                                This parameter can be a number between 0x0 and 0xF  */
00502   uint32_t ResetMode;     /*!< Specifies the reset mode of a fault event counter.
00503                                This parameter can be a value of @ref HRTIM_Fault_ResetMode */
00504   uint32_t BlankingSource;/*!< Specifies the blanking source of a fault event.
00505                                This parameter can be a value of @ref HRTIM_Fault_Blanking */
00506 } HRTIM_FaultBlankingCfgTypeDef;
00507
00508 /**
00509   * @brief  Burst mode configuration definition
00510   */
00511 typedef struct
00512 {
00513   uint32_t Mode;           /*!< Specifies the burst mode operating mode.
00514                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
00515   uint32_t ClockSource;    /*!< Specifies the burst mode clock source.
00516                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
00517   uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.
00518                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
00519   uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
00520                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
00521   uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.
00522                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
00523   uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.
00524                                 This parameter can be a number between 0x0 and 0xFFFF  */
00525   uint32_t Period;         /*!< Specifies burst mode repetition period.
00526                                 This parameter can be a number between 0x1 and 0xFFFF  */
00527 } HRTIM_BurstModeCfgTypeDef;
00528
00529 /**
00530   * @brief  ADC trigger configuration definition
00531   */
00532 typedef struct
00533 {
00534   uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.
00535                                This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source  */
00536   uint32_t Trigger;       /*!< Specifies the event(s) triggering the ADC conversion.
00537                                This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event  */
00538 } HRTIM_ADCTriggerCfgTypeDef;
00539
00540 /**
00541   * @brief  External Event Counter A or B configuration definition
00542   */
00543 typedef struct
00544 {
00545   uint32_t ResetMode;      /*!< Specifies the External Event Counter A or B Reset Mode.
00546                                 This parameter can be a value of @ref HRTIM_Timer_External_Event_ResetMode  */
00547   uint32_t Source;         /*!< Specifies the External Event Counter source selection.
00548                                 This parameter can be one of @ref HRTIM_External_Event_Channels  */
00549   uint32_t Counter;        /*!< Specifies the External Event Counter Threshold.
00550                                 This parameter can be a number between 0x0 and 0x3F  */
00551 } HRTIM_ExternalEventCfgTypeDef;
00552
00553
00554 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
00555 /**
00556   * @brief  HAL HRTIM Callback ID enumeration definition
00557   */
00558 typedef enum {
00559   HAL_HRTIM_FAULT1CALLBACK_CB_ID               = 0x00U, /*!< Fault 1 interrupt callback ID                         */
00560   HAL_HRTIM_FAULT2CALLBACK_CB_ID               = 0x01U, /*!< Fault 2 interrupt callback ID                         */
00561   HAL_HRTIM_FAULT3CALLBACK_CB_ID               = 0x02U, /*!< Fault 3 interrupt callback ID                         */
00562   HAL_HRTIM_FAULT4CALLBACK_CB_ID               = 0x03U, /*!< Fault 4 interrupt callback ID                         */
00563   HAL_HRTIM_FAULT5CALLBACK_CB_ID               = 0x04U, /*!< Fault 5 interrupt callback ID                         */
00564   HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID          = 0x05U, /*!< System fault interrupt callback ID                    */
00565   HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID   = 0x06U, /*!< DLL Ready interrupt callback ID                       */
00566   HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID      = 0x07U, /*!< Burst mode period interrupt callback ID               */
00567   HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID                      */
00568   HAL_HRTIM_ERRORCALLBACK_CB_ID                = 0x09U, /*!< DMA error callback ID                                 */
00569
00570   HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID      = 0x10U, /*!< Timer x Update interrupt callback ID                  */
00571   HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID      = 0x11U, /*!< Timer x Repetition interrupt callback ID              */
00572   HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID        = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID         */
00573   HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID        = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID         */
00574   HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID        = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID         */
00575   HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID        = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID         */
00576   HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID        = 0x16U, /*!< Timer x Capture 1 interrupts callback ID              */
00577   HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID        = 0x17U, /*!< Timer x Capture 2 interrupts callback ID              */
00578   HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID    = 0x18U, /*!< Timer x Delayed protection interrupt callback ID      */
00579   HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID         = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */
00580   HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID           = 0x1AU, /*!< Timer x output 1 set interrupt callback ID            */
00581   HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID         = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID          */
00582   HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID           = 0x1CU, /*!< Timer x output 2 set interrupt callback ID            */
00583   HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID         = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID          */
00584   HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID     = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID     */
00585
00586   HAL_HRTIM_MSPINIT_CB_ID                      = 0x20U, /*!< HRTIM MspInit callback ID                             */
00587   HAL_HRTIM_MSPDEINIT_CB_ID                    = 0x21U, /*!< HRTIM MspInit callback ID                             */
00588   HAL_HRTIM_FAULT6CALLBACK_CB_ID               = 0x22U, /*!< Fault 6 interrupt callback ID                         */
00589 }HAL_HRTIM_CallbackIDTypeDef;
00590
00591 /**
00592   * @brief  HAL HRTIM Callback function pointer definitions
00593   */
00594 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim);       /*!< HRTIM related callback function pointer         */
00595
00596 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!< HRTIM Timer x related callback function pointer */
00597                                             uint32_t TimerIdx);
00598 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
00599
00600 /**
00601   * @}
00602   */
00603
00604 /* Exported constants --------------------------------------------------------*/
00605 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
00606   * @{
00607   */
00608
00609 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
00610   * @{
00611   * @brief Constants defining the timer indexes
00612   */
00613 #define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */
00614 #define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */
00615 #define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */
00616 #define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */
00617 #define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */
00618 #define HRTIM_TIMERINDEX_TIMER_F 0x5U   /*!< Index used to access timer F registers */
00619 #define HRTIM_TIMERINDEX_MASTER  0x6U   /*!< Index used to access master registers  */
00620 #define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */
00621 /**
00622   * @}
00623   */
00624
00625 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
00626   * @{
00627   * @brief Constants defining timer identifiers
00628   */
00629 #define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier  */
00630 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
00631 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
00632 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
00633 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
00634 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
00635 #define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN)  /*!< Timer F identifier */
00636 /**
00637  * @}
00638  */
00639
00640 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
00641   * @{
00642   * @brief Constants defining compare unit identifiers
00643   */
00644 #define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */
00645 #define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */
00646 #define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */
00647 #define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */
00648  /**
00649   * @}
00650   */
00651
00652 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
00653   * @{
00654   * @brief Constants defining capture unit identifiers
00655   */
00656 #define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */
00657 #define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
00663   * @{
00664   * @brief Constants defining timer output identifiers
00665   */
00666 #define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */
00667 #define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */
00668 #define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */
00669 #define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */
00670 #define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */
00671 #define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */
00672 #define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */
00673 #define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */
00674 #define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */
00675 #define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */
00676 #define HRTIM_OUTPUT_TF1  0x00000400U  /*!< Timer F - Output 1 identifier */
00677 #define HRTIM_OUTPUT_TF2  0x00000800U  /*!< Timer F - Output 2 identifier */
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
00683   * @{
00684   * @brief Constants defining ADC triggers identifiers
00685   */
00686 #define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */
00687 #define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */
00688 #define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */
00689 #define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger
00695   * @{
00696   * @brief Constants defining ADC Extended triggers identifiers
00697   */
00698 #define HRTIM_ADCTRIGGER_5  0x00000010U  /*!< ADC trigger 5 identifier  */
00699 #define HRTIM_ADCTRIGGER_6  0x00000020U  /*!< ADC trigger 6 identifier  */
00700 #define HRTIM_ADCTRIGGER_7  0x00000040U  /*!< ADC trigger 7 identifier  */
00701 #define HRTIM_ADCTRIGGER_8  0x00000080U  /*!< ADC trigger 8 identifier  */
00702 #define HRTIM_ADCTRIGGER_9  0x00000100U  /*!< ADC trigger 9 identifier  */
00703 #define HRTIM_ADCTRIGGER_10 0x00000200U  /*!< ADC trigger 10 identifier */
00704
00705 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
00706     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
00707      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
00708      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
00709      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)   || \
00710      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5)   || \
00711      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6)   || \
00712      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7)   || \
00713      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8)   || \
00714      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9)   || \
00715      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
00716 #define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\
00717     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5)   || \
00718      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6)   || \
00719      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7)   || \
00720      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8)   || \
00721      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9)   || \
00722      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
00723 /**
00724   * @}
00725   */
00726
00727 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
00728   * @{
00729   * @brief Constants defining external event channel identifiers
00730   */
00731 #define HRTIM_EVENT_NONE    (0x00000000U)     /*!< Undefined event channel */
00732 #define HRTIM_EVENT_1       (0x00000001U)     /*!< External event channel 1  identifier */
00733 #define HRTIM_EVENT_2       (0x00000002U)     /*!< External event channel 2  identifier */
00734 #define HRTIM_EVENT_3       (0x00000003U)     /*!< External event channel 3  identifier */
00735 #define HRTIM_EVENT_4       (0x00000004U)     /*!< External event channel 4  identifier */
00736 #define HRTIM_EVENT_5       (0x00000005U)     /*!< External event channel 5  identifier */
00737 #define HRTIM_EVENT_6       (0x00000006U)     /*!< External event channel 6  identifier */
00738 #define HRTIM_EVENT_7       (0x00000007U)     /*!< External event channel 7  identifier */
00739 #define HRTIM_EVENT_8       (0x00000008U)     /*!< External event channel 8  identifier */
00740 #define HRTIM_EVENT_9       (0x00000009U)     /*!< External event channel 9  identifier */
00741 #define HRTIM_EVENT_10      (0x0000000AU)     /*!< External event channel 10 identifier */
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
00747   * @{
00748   * @brief Constants defining fault channel identifiers
00749   */
00750 #define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */
00751 #define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */
00752 #define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */
00753 #define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */
00754 #define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */
00755 #define HRTIM_FAULT_6      (0x20U)     /*!< Fault channel 6 identifier */
00756 /**
00757   * @}
00758   */
00759
00760
00761  /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
00762   * @{
00763   * @brief Constants defining timer high-resolution clock prescaler ratio.
00764   */
00765 #define HRTIM_PRESCALERRATIO_MUL32    (0x00000000U)  /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
00766 #define HRTIM_PRESCALERRATIO_MUL16    (0x00000001U)  /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
00767 #define HRTIM_PRESCALERRATIO_MUL8     (0x00000002U)  /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)  */
00768 #define HRTIM_PRESCALERRATIO_MUL4     (0x00000003U)  /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)    */
00769 #define HRTIM_PRESCALERRATIO_MUL2     (0x00000004U)  /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)    */
00770 #define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)         */
00771 #define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)     */
00772 #define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)        */
00773 /**
00774   * @}
00775   */
00776
00777 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
00778   * @{
00779   * @brief Constants defining timer counter operating mode.
00780   */
00781 #define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00782 #define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */
00783 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00784 /**
00785   * @}
00786   */
00787
00788 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
00789   * @{
00790   * @brief Constants defining half mode enabling status.
00791   */
00792 #define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */
00793 #define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */
00794 /**
00795   * @}
00796   */
00797
00798 /** @defgroup HRTIM_Interleaved_Mode HRTIM Interleaved Mode
00799   * @{
00800   * @brief Constants defining interleaved mode enabling status.
00801   */
00802 #define HRTIM_INTERLEAVED_MODE_DISABLED      0x000U               /*!< HRTIM interleaved Mode is disabled */
00803 #define HRTIM_INTERLEAVED_MODE_DUAL          0x002U               /*!< HRTIM interleaved Mode is Half */
00804 #define HRTIM_INTERLEAVED_MODE_TRIPLE        0x003U               /*!< HRTIM interleaved Mode is Triple */
00805 #define HRTIM_INTERLEAVED_MODE_QUAD          0x004U               /*!< HRTIM interleaved Mode is Quad */
00806 /**
00807   * @}
00808   */
00809
00810 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
00811   * @{
00812   * @brief Constants defining the timer behavior following the synchronization event
00813   */
00814 #define HRTIM_SYNCSTART_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
00815 #define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
00821   * @{
00822   * @brief Constants defining the timer behavior following the synchronization event
00823   */
00824 #define HRTIM_SYNCRESET_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
00825 #define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */
00826 /**
00827   * @}
00828   */
00829
00830 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
00831   * @{
00832   * @brief Constants defining on which output the DAC synchronization event is sent
00833   */
00834 #define HRTIM_DACSYNC_NONE          0x00000000U                                 /*!< No DAC synchronization event generated */
00835 #define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00836 #define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00837 #define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
00838 /**
00839   * @}
00840   */
00841
00842 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
00843   * @{
00844   * @brief Constants defining whether a write access into a preloadable
00845   *        register is done into the active or the preload register.
00846   */
00847 #define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */
00848 #define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */
00849 /**
00850   * @}
00851   */
00852
00853 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
00854   * @{
00855   * @brief Constants defining how the update occurs relatively to the burst DMA
00856   *        transaction and the external update request on update enable inputs 1 to 3.
00857   */
00858 #define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                           /*!< Update done independently from the DMA burst transfer completion */
00859 #define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00860 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00861 #define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
00862 #define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
00863 #define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
00864 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */
00865 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */
00866 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */
00867 /**
00868   * @}
00869   */
00870
00871 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
00872   * @{
00873   * @brief Constants defining how the timer behaves during a burst
00874             mode operation.
00875   */
00876 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U           /*!< Timer counter clock is maintained and the timer operates normally */
00877 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset */
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup HRTIM_Timer_UpDown_Mode HRTIM Timer UpDown Mode
00883   * @{
00884   * @brief Constants defining how the timer counter operates
00885   */
00886 #define HRTIM_TIMERUPDOWNMODE_UP           0x00000000U           /*!< Timer counter is operating in up-counting mode */
00887 #define HRTIM_TIMERUPDOWNMODE_UPDOWN       0x00000001U           /*!< Timer counter is operating in up-down counting mode */
00888 /**
00889   * @}
00890   */
00891
00892 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
00893   * @{
00894   * @brief Constants defining how the timer counter operates
00895   */
00896 #define HRTIM_TIMERTRIGHALF_DISABLED       0x00000000U           /*!< Timer Compare 2 register is behaving in standard mode */
00897 #define HRTIM_TIMERTRIGHALF_ENABLED        (HRTIM_TIMCR2_TRGHLF) /*!< Timer Compare 2 register is behaving in triggered-half mode */
00898 /**
00899   * @}
00900   */
00901
00902 /** @defgroup HRTIM_Timer_GreaterCMP3_Mode HRTIM Timer Greater than Compare 3 PWM Mode
00903   * @{
00904   * @brief Constants defining how the timer compare operates
00905   */
00906 #define HRTIM_TIMERGTCMP3_EQUAL            0x00000000U           /*!< Timer Compare 3 event is generated when counter is equal */
00907 #define HRTIM_TIMERGTCMP3_GREATER          (HRTIM_TIMCR2_GTCMP3) /*!< Timer Compare 3 Reset event is generated when counter is greater */
00908 /**
00909   * @}
00910   */
00911
00912 /** @defgroup HRTIM_Timer_GreaterCMP1_Mode HRTIM Timer Greater than Compare 1 PWM Mode
00913   * @{
00914   * @brief Constants defining how the timer compare operates
00915   */
00916 #define HRTIM_TIMERGTCMP1_EQUAL            0x00000000U           /*!< Timer Compare 1 event is generated when counter is equal */
00917 #define HRTIM_TIMERGTCMP1_GREATER          (HRTIM_TIMCR2_GTCMP1) /*!< Timer Compare 1 event is generated when counter is greater */
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup HRTIM_Timer_DualChannelDac_Reset HRTIM Dual Channel Dac Reset Trigger
00923   * @{
00924   * @brief Constants defining when the hrtim_dac_reset_trgx trigger is generated
00925   */
00926 #define HRTIM_TIMER_DCDR_COUNTER           0x00000000U           /*!< the trigger is generated on counter reset or roll-over event */
00927 #define HRTIM_TIMER_DCDR_OUT1SET           (HRTIM_TIMCR2_DCDR)   /*!< the trigger is generated on output 1 set event */
00928 /**
00929   * @}
00930   */
00931
00932 /** @defgroup HRTIM_Timer_DualChannelDac_Step HRTIM Dual Channel Dac Step Trigger
00933   * @{
00934   * @brief Constants defining when the hrtim_dac_step_trgx trigger is generated
00935  is generated
00936   */
00937 #define HRTIM_TIMER_DCDS_CMP2              0x00000000U           /*!< the trigger is generated on compare 2 event */
00938 #define HRTIM_TIMER_DCDS_OUT1RST           (HRTIM_TIMCR2_DCDS)   /*!< the trigger is generated on output 1 reset event */
00939 /**
00940   * @}
00941   */
00942
00943 /** @defgroup HRTIM_Timer_DualChannelDac_Enable HRTIM Dual Channel DAC Trigger Enable
00944   * @{
00945   * @brief Constants enabling the dual channel DAC triggering mechanism
00946   */
00947 #define HRTIM_TIMER_DCDE_DISABLED          0x00000000U           /*!< the Dual channel DAC trigger is disabled */
00948 #define HRTIM_TIMER_DCDE_ENABLED           (HRTIM_TIMCR2_DCDE)   /*!< the Dual channel DAC trigger is enabled */
00949 /**
00950   * @}
00951   */
00952
00953 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
00954   * @{
00955   * @brief Constants defining whether registers are updated when the timer
00956   *        repetition period is completed (either due to roll-over or
00957   *        reset events)
00958   */
00959 #define HRTIM_UPDATEONREPETITION_DISABLED  0x00000000U           /*!< Update on repetition disabled */
00960 #define HRTIM_UPDATEONREPETITION_ENABLED   (HRTIM_MCR_MREPU)     /*!< Update on repetition enabled */
00961 /**
00962   * @}
00963   */
00964
00965
00966 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
00967   * @{
00968   * @brief Constants defining whether or not the push-pull mode is enabled for
00969   *        a timer.
00970   */
00971 #define HRTIM_TIMPUSHPULLMODE_DISABLED     0x00000000U           /*!< Push-Pull mode disabled */
00972 #define HRTIM_TIMPUSHPULLMODE_ENABLED      (HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
00978   * @{
00979   * @brief Constants defining whether a fault channel is enabled for a timer
00980   */
00981 #define HRTIM_TIMFAULTENABLE_NONE     0x00000000U           /*!< No fault enabled */
00982 #define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */
00983 #define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */
00984 #define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */
00985 #define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */
00986 #define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */
00987 #define HRTIM_TIMFAULTENABLE_FAULT6   (HRTIM_FLTR_FLT6EN)   /*!< Fault 6 enabled */
00988 /**
00989   * @}
00990   */
00991
00992 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
00993   * @{
00994   * @brief Constants defining whether or not fault enabling bits are write
00995   *        protected for a timer
00996   */
00997 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */
00998 #define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */
00999 /**
01000   * @}
01001   */
01002
01003 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
01004   * @{
01005   * @brief Constants defining whether or not fault the dead time insertion
01006   *        feature is enabled for a timer
01007   */
01008 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */
01009 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Dead-time is inserted between output 1 and output 2U */
01010 /**
01011   * @}
01012   */
01013
01014 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
01015   * @{
01016   * @brief Constants defining all possible delayed protection modes
01017   *        for a timer. Also define the source and outputs on which the delayed
01018   *        protection schemes are applied
01019   */
01020 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */
01021 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
01022 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
01023 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
01024 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */
01025 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
01026 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
01027 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
01028 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
01029
01030 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED            (0x00000000U)                                                                             /*!< No action */
01031 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8    (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
01032 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8    (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
01033 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8    (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
01034 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8       (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */
01035 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
01036 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
01037 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9    (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
01038 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9       (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */
01039
01040 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED              (0x00000000U)                                                                             /*!< No action */
01041 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8      (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers F: Output 1 delayed Idle on external Event 6U */
01042 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8      (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 2 delayed Idle on external Event 6U */
01043 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8      (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 1 and output 2 delayed Idle on external Event 6U */
01044 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8         (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Balanced Idle on external Event 6U */
01045 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 1 delayed Idle on external Event 7U */
01046 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Output 2 delayed Idle on external Event 7U */
01047 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9      (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Output 1 and output2 delayed Idle on external Event 7U */
01048 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9         (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers F: Balanced Idle on external Event 7U */
01049 /**
01050   * @}
01051   */
01052
01053 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
01054   * @{
01055   * @brief Constants defining whether the registers update is done synchronously
01056   *        with any other timer or master update
01057   */
01058 #define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */
01059 #define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */
01060 #define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */
01061 #define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */
01062 #define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/
01063 #define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */
01064 #define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */
01065 #define HRTIM_TIMUPDATETRIGGER_TIMER_F  (HRTIM_TIMCR_TFU)    /*!< Register update is triggered by the timer F update */
01066 /**
01067   * @}
01068   */
01069
01070 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
01071   * @{
01072   * @brief Constants defining the events that can be selected to trigger the reset
01073   *        of the timer counter
01074   */
01075 #define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */
01076 #define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */
01077 #define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */
01078 #define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */
01079 #define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */
01080 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */
01081 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */
01082 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */
01083 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */
01084 #define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */
01085 #define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */
01086 #define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */
01087 #define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */
01088 #define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */
01089 #define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */
01090 #define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */
01091 #define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */
01092 #define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */
01093 #define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
01094 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
01095 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
01096 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
01097 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
01098 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
01099 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
01100 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
01101 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
01102 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
01103 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
01104 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
01105 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
01106 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP1 (HRTIM_RSTR_TIMFCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
01107 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP2 (HRTIM_RSTR_TIMFCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
01108 /**
01109   * @}
01110   */
01111
01112 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
01113   * @{
01114   * @brief Constants defining whether the register are updated upon Timerx
01115   *        counter reset or roll-over to 0 after reaching the period value
01116   *        in continuous mode
01117   */
01118 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U           /*!< Update by timer x reset / roll-over disabled */
01119 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */
01120 /**
01121   * @}
01122   */
01123
01124 /** @defgroup HRTIM_Timer_RollOver_Mode HRTIM Timer RollOver Mode
01125   * @{
01126   * @brief Constants defining when the roll-over is generated upon Timerx
01127   *        event generated when the counter is equal to 0 ('VALLEY' mode) or to HRTIM_PERxR value ('CREST' mode) or BOTH
01128   *        This setting only applies when the UDM bit is set. It is not significant otherwise.
01129   */
01130 #define HRTIM_TIM_FEROM_BOTH      0x00000000U              /*!< Roll-over event used by  */
01131 #define HRTIM_TIM_FEROM_CREST     (HRTIM_TIMCR2_FEROM_1)   /*!< the Fault and */
01132 #define HRTIM_TIM_FEROM_VALLEY    (HRTIM_TIMCR2_FEROM_0)   /*!< Event counters */
01133 #define HRTIM_TIM_BMROM_BOTH      0x00000000U              /*!< Roll-over event used in the Burst mode controller */
01134 #define HRTIM_TIM_BMROM_CREST     (HRTIM_TIMCR2_BMROM_1)   /*!< as clock  */
01135 #define HRTIM_TIM_BMROM_VALLEY    (HRTIM_TIMCR2_BMROM_0)   /*!< and as burst mode trigger */
01136 #define HRTIM_TIM_ADROM_BOTH      0x00000000U              /*!< Roll-over event which triggers */
01137 #define HRTIM_TIM_ADROM_CREST     (HRTIM_TIMCR2_ADROM_1)   /*!< the */
01138 #define HRTIM_TIM_ADROM_VALLEY    (HRTIM_TIMCR2_ADROM_0)   /*!< ADC */
01139 #define HRTIM_TIM_OUTROM_BOTH     0x00000000U              /*!< Roll-over event which sets and/or resets the outputs */
01140 #define HRTIM_TIM_OUTROM_CREST    (HRTIM_TIMCR2_OUTROM_1)  /*!< as per HRTIM_SETxyR */
01141 #define HRTIM_TIM_OUTROM_VALLEY   (HRTIM_TIMCR2_OUTROM_0)  /*!< and HRTIM_RSTxyR settings */
01142 #define HRTIM_TIM_ROM_BOTH        0x00000000U              /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/
01143 #define HRTIM_TIM_ROM_CREST       (HRTIM_TIMCR2_ROM_1)     /*!< Update trigger (to transfer content from preload to active registers), */
01144 #define HRTIM_TIM_ROM_VALLEY      (HRTIM_TIMCR2_ROM_0)     /*!< repetition counter decrement and External Event filtering */
01145
01146 #define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\
01147               ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY))  ||\
01148                (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY))  ||\
01149                (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY))  ||\
01150                (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\
01151                (((ROLLOVER) == HRTIM_TIM_ROM_BOTH)    || ((ROLLOVER) == HRTIM_TIM_ROM_CREST)    || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY)))
01152 /**
01153   * @}
01154   */
01155
01156 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
01157   * @{
01158   * @brief Constants defining whether the compare register is behaving in
01159   *        regular mode (compare match issued as soon as counter equal compare),
01160   *        or in auto-delayed mode
01161   */
01162 #define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */
01163 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
01164 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
01165 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
01166 /**
01167   * @}
01168   */
01169
01170 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
01171   * @{
01172   * @brief Constants defining the behavior of the output signal when the timer
01173            operates in basic output compare mode
01174   */
01175 #define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */
01176 #define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */
01177 #define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */
01178
01179 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
01180               (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
01181                ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
01182                ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
01183 /**
01184   * @}
01185   */
01186
01187 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
01188   * @{
01189   * @brief Constants defining the polarity of a timer output
01190   */
01191 #define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is active HIGH */
01192 #define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
01193 /**
01194   * @}
01195   */
01196
01197 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
01198   * @{
01199   * @brief Constants defining the events that can be selected to configure the
01200   *        set crossbar of a timer output
01201   */
01202 #define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */
01203 #define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
01204 #define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */
01205 #define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */
01206 #define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */
01207 #define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */
01208 #define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */
01209 #define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */
01210 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */
01211 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */
01212 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */
01213 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */
01214 /* Timer Events mapping for Timer A */
01215 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01216 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01217 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01218 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01219 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01220 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01221 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01222 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01223 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01224 /* Timer Events mapping for Timer B */
01225 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01226 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01227 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01228 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01229 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01230 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01231 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01232 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01233 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01234 /* Timer Events mapping for Timer C */
01235 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01236 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01237 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01238 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01239 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01240 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01241 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01242 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01243 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01244 /* Timer Events mapping for Timer D */
01245 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01246 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01247 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01248 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01249 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01250 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01251 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01252 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01253 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01254 /* Timer Events mapping for Timer E */
01255 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01256 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01257 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01258 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01259 #define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01260 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01261 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01262 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01263 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01264 /* Timer Events mapping for Timer F */
01265 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01266 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01267 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01268 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01269 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01270 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01271 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01272 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01273 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01274 #define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */
01275 #define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */
01276 #define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */
01277 #define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */
01278 #define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */
01279 #define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */
01280 #define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */
01281 #define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */
01282 #define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */
01283 #define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */
01284 #define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */
01285 /**
01286   * @}
01287   */
01288
01289 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
01290   * @{
01291   * @brief Constants defining the events that can be selected to configure the
01292   *        reset crossbar of a timer output
01293   */
01294 #define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
01295 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
01296 #define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */
01297 #define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */
01298 #define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */
01299 #define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */
01300 #define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */
01301 #define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */
01302 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */
01303 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
01304 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
01305 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
01306 /* Timer Events mapping for Timer A */
01307 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01308 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01309 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01310 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01311 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01312 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01313 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01314 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01315 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01316 /* Timer Events mapping for Timer B */
01317 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01318 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01319 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01320 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01321 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01322 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01323 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01324 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01325 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01326 /* Timer Events mapping for Timer C */
01327 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01328 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01329 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01330 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01331 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01332 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01333 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01334 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01335 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01336 /* Timer Events mapping for Timer D */
01337 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01338 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01339 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01340 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01341 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01342 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01343 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01344 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01345 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01346 /* Timer Events mapping for Timer E */
01347 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01348 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01349 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01350 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01351 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01352 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01353 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01354 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01355 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01356 /* Timer Events mapping for Timer F */
01357 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01358 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01359 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01360 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01361 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01362 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01363 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01364 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01365 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01366 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
01367 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
01368 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
01369 #define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */
01370 #define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */
01371 #define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */
01372 #define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */
01373 #define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */
01374 #define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */
01375 #define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */
01376 #define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */
01377 /**
01378   * @}
01379   */
01380
01381 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
01382   * @{
01383   * @brief Constants defining whether or not the timer output transition to its
01384            IDLE state when burst mode is entered
01385   */
01386 #define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U           /*!< The output is not affected by the burst mode operation */
01387 #define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */
01388  /**
01389   * @}
01390   */
01391
01392 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
01393   * @{
01394   * @brief Constants defining the output level when output is in IDLE state
01395   */
01396 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
01397 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
01398 /**
01399   * @}
01400   */
01401
01402 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
01403   * @{
01404   * @brief Constants defining the output level when output is in FAULT state
01405   */
01406 #define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                  /*!< The output is not affected by the fault input */
01407 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
01408 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
01409 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
01410 /**
01411   * @}
01412   */
01413
01414 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
01415   * @{
01416   * @brief Constants defining whether or not chopper mode is enabled for a timer
01417            output
01418   */
01419 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U           /*!< Output signal is not altered  */
01420 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */
01421 /**
01422   * @}
01423   */
01424
01425 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
01426   * @{
01427   * @brief Constants defining the idle mode entry is delayed by forcing a
01428            dead-time insertion before switching the outputs to their idle state
01429   */
01430 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U           /*!< The programmed Idle state is applied immediately to the Output */
01431 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Dead-time is inserted on output before entering the idle mode */
01432 /**
01433   * @}
01434   */
01435
01436 /** @defgroup HRTIM_Output_Balanced_Idle_Auto_Resume HRTIM Output Balanced Idle Automatic Resume
01437   * @{
01438   * @brief Constants defining if the outputs are automatically
01439            re-enabled after a balanced idle event.
01440   */
01441 #define HRTIM_OUTPUTBIAR_DISABLED   0x00000000U            /*!< output is not automatically re-enabled */
01442 #define HRTIM_OUTPUTBIAR_ENABLED    (HRTIM_OUTR_BIAR)      /*!< output is automatically re-enabled */
01443 /**
01444   * @}
01445   */
01446
01447
01448 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
01449   * @{
01450   * @brief Constants defining the events that can be selected to trigger the
01451   *        capture of the timing unit counter
01452   */
01453 #define HRTIM_CAPTURETRIGGER_NONE         0x00000000U              /*!< Capture trigger is disabled */
01454 #define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */
01455 #define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */
01456 #define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */
01457 #define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */
01458 #define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */
01459 #define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */
01460 #define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */
01461 #define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */
01462 #define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */
01463 #define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */
01464 #define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
01465 #define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */
01466 #define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */
01467 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */
01468 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */
01469 #define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */
01470 #define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */
01471 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */
01472 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */
01473 #define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */
01474 #define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */
01475 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */
01476 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */
01477 #define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */
01478 #define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */
01479 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */
01480 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */
01481 #define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */
01482 #define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */
01483 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */
01484 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */
01485 /**
01486   * @}
01487   */
01488 /** @defgroup HRTIM_Capture_Unit_TimerF_Trigger HRTIM Capture Unit TimerF Trigger
01489   * @{
01490   * @brief Constants defining the events that can be selected to trigger the
01491   *        capture of the timing unit counter
01492   */
01493 #define HRTIM_CAPTURETRIGGER_TF1_SET       ((uint64_t)(HRTIM_CPT1CR_TF1SET  ) << 32)  /*!< Capture is triggered by TF1 output inactive to active transition */
01494 #define HRTIM_CAPTURETRIGGER_TF1_RESET     ((uint64_t)(HRTIM_CPT1CR_TF1RST  ) << 32)  /*!< Capture is triggered by TF1 output active to inactive transition */
01495 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP1   ((uint64_t)(HRTIM_CPT1CR_TIMFCMP1) << 32)  /*!< Timer F Compare 1 triggers Capture */
01496 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP2   ((uint64_t)(HRTIM_CPT1CR_TIMFCMP2) << 32)  /*!< Timer F Compare 2 triggers Capture */
01497 /**
01498   * @}
01499   */
01500
01501 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
01502   * @{
01503   * @brief Constants defining the event filtering applied to external events
01504   *        by a timer
01505   */
01506 #define HRTIM_TIMEEVFLT_NONE                            (0x00000000U)
01507 #define HRTIM_TIMEEVFLT_BLANKINGCMP1                    (HRTIM_EEFR1_EE1FLTR_0)                                                   /*!< Blanking from counter reset/roll-over to Compare 1U */
01508 #define HRTIM_TIMEEVFLT_BLANKINGCMP2                    (HRTIM_EEFR1_EE1FLTR_1)                                                   /*!< Blanking from counter reset/roll-over to Compare 2U */
01509 #define HRTIM_TIMEEVFLT_BLANKINGCMP3                    (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from counter reset/roll-over to Compare 3U */
01510 #define HRTIM_TIMEEVFLT_BLANKINGCMP4                    (HRTIM_EEFR1_EE1FLTR_2)                                                   /*!< Blanking from counter reset/roll-over to Compare 4U */
01511 /* Blanking Filter for TIMER A */
01512 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01513 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01514 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01515 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01516 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01517 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01518 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01519 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01520 /* Blanking Filter for TIMER B */
01521 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01522 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01523 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01524 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01525 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01526 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01527 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01528 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01529 /* Blanking Filter for TIMER C */
01530 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01531 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01532 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01533 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01534 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01535 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01536 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01537 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01538 /* Blanking Filter for TIMER D */
01539 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01540 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01541 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01542 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01543 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01544 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01545 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01546 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01547 /* Blanking Filter for TIMER E */
01548 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01549 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01550 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01551 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01552 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01553 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01554 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01555 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01556 /* Blanking Filter for TIMER F */
01557 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01558 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01559 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01560 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01561 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01562 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01563 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01564 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01565
01566 #define HRTIM_TIMEEVFLT_WINDOWINGCMP2                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from counter reset/roll-over to Compare 2U */
01567 #define HRTIM_TIMEEVFLT_WINDOWINGCMP3                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)   /*!< Windowing from counter reset/roll-over to Compare 3U */
01568 #define HRTIM_TIMEEVFLT_WINDOWINGTIM                    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
01569                                                                                                        | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from another timing unit: TIMWIN source */
01570 /**
01571   * @}
01572   */
01573
01574 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
01575   * @{
01576   * @brief Constants defining whether or not the external event is
01577   *        memorized (latched) and generated as soon as the blanking period
01578   *        is completed or the window ends
01579   */
01580 #define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */
01581 #define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
01582 /**
01583   * @}
01584   */
01585
01586 /** @defgroup HRTIM_Timer_External_Event HRTIM Timer External Event Counter A or B
01587   * @{
01588   * @brief Constants defining the External Event Counter A or B
01589   */
01590 #define HRTIM_EVENTCOUNTER_A    (HRTIM_EEFR3_EEVACE)           /*!< External Event Counter A */
01591 #define HRTIM_EVENTCOUNTER_B    (HRTIM_EEFR3_EEVBCE)           /*!< External Event Counter B */
01592 /**
01593   * @}
01594   */
01595
01596 /** @defgroup HRTIM_Timer_External_Event_ResetMode HRTIM Timer External Counter Reset Mode
01597   * @{
01598   * @brief Constants enabling the External Event Counter A or B Reset Mode
01599   */
01600 #define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL   (0x00000000U)   /*!< External Event Counter is reset on each reset / roll-over event */
01601 #define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL     (0x00000001U)   /*!< External Event Counter is reset on each reset / roll-over event only
01602                                                                         if no event occurs during last counting period */
01603 /**
01604   * @}
01605   */
01606
01607 /** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update
01608   * @{
01609   * @brief Constants defining the update coming condition
01610   */
01611 #define HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL   (0x00000000U)   /*!< update taken into account immediately */
01612 #define HRTIM_TIMERESYNC_UPDATE_CONDITIONAL     (0x00000001U)   /*!< update taken into account on the following Reset/Roll-over event */
01613 /**
01614   * @}
01615   */
01616
01617 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
01618   * @{
01619   * @brief Constants defining division ratio between the timer clock frequency
01620   *        (fHRTIM) and the dead-time generator clock (fDTG)
01621   */
01622 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */
01623 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */
01624 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */
01625 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
01626 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
01627 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
01628 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */
01629 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */
01630 /**
01631   * @}
01632   */
01633
01634 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
01635   * @{
01636   * @brief Constants defining whether the dead-time is positive or negative
01637   *        (overlapping signal) on rising edge
01638   */
01639 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on rising edge */
01640 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative dead-time on rising edge */
01641 /**
01642   * @}
01643   */
01644
01645 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
01646   * @{
01647   * @brief Constants defining whether or not the dead-time (rising sign and
01648   *        value) is write protected
01649   */
01650 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising value and sign is writeable */
01651 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Dead-time rising value and sign is read-only */
01652 /**
01653   * @}
01654   */
01655
01656 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
01657   * @{
01658   * @brief Constants defining whether or not the dead-time rising sign is write
01659   *        protected
01660   */
01661 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising sign is writeable */
01662 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Dead-time rising sign is read-only */
01663 /**
01664   * @}
01665   */
01666
01667 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
01668   * @{
01669   * @brief Constants defining whether the dead-time is positive or negative
01670   *        (overlapping signal) on falling edge
01671   */
01672 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on falling edge */
01673 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative dead-time on falling edge */
01674 /**
01675   * @}
01676   */
01677
01678 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
01679   * @{
01680   * @brief Constants defining whether or not the dead-time (falling sign and
01681   *        value) is write protected
01682   */
01683 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling value and sign is writeable */
01684 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Dead-time falling value and sign is read-only */
01685 /**
01686   * @}
01687   */
01688
01689 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
01690   * @{
01691   * @brief Constants defining whether or not the dead-time falling sign is write
01692   *        protected
01693   */
01694 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling sign is writeable */
01695 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Dead-time falling sign is read-only */
01696 /**
01697   * @}
01698   */
01699
01700 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
01701   * @{
01702   * @brief Constants defining the frequency of the generated high frequency carrier
01703   */
01704 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
01705 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
01706 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
01707 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
01708 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
01709 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
01710 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
01711 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
01712 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
01713 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
01714 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
01715 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
01716 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
01717 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
01718 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
01719 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
01720  /**
01721   * @}
01722   */
01723
01724 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
01725   * @{
01726   * @brief Constants defining the duty cycle of the generated high frequency carrier
01727   *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
01728   */
01729 #define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                                       /*!< Only 1st pulse is present */
01730 #define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */
01731 #define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */
01732 #define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */
01733 #define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */
01734 #define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */
01735 #define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */
01736 #define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
01737 /**
01738   * @}
01739   */
01740
01741 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
01742   * @{
01743   * @brief Constants defining the pulse width of the first pulse of the generated
01744   *        high frequency carrier
01745   */
01746 #define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                          /*!< tSTPW = tHRTIM x 16  */
01747 #define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
01748 #define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
01749 #define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
01750 #define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
01751 #define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
01752 #define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
01753 #define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
01754 #define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
01755 #define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
01756 #define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
01757 #define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
01758 #define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
01759 #define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
01760 #define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
01761 #define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
01762 /**
01763   * @}
01764   */
01765
01766 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
01767   * @{
01768   * @brief Constants defining the options for synchronizing multiple HRTIM
01769   *        instances, as a master unit (generating a synchronization signal)
01770   *        or as a slave (waiting for a trigger to be synchronized)
01771   */
01772 #define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
01773 #define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
01774 #define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
01775 /**
01776   * @}
01777   */
01778
01779 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
01780   * @{
01781   * @brief Constants defining defining the synchronization input source
01782   */
01783 #define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                                  /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
01784 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */
01785 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
01786 /**
01787   * @}
01788   */
01789
01790 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
01791   * @{
01792   * @brief Constants defining the source and event to be sent on the
01793   *        synchronization outputs
01794   */
01795 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
01796 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
01797 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
01798 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
01799 /**
01800   * @}
01801   */
01802
01803 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
01804   * @{
01805   * @brief Constants defining the routing and conditioning of the synchronization output event
01806   */
01807 #define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                   /*!< Synchronization output event is disabled */
01808 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
01809 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
01810 /**
01811   * @}
01812   */
01813
01814 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
01815   * @{
01816   * @brief Constants defining available sources associated to external events
01817   */
01818 #define HRTIM_EEV1SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 1 */
01819 #define HRTIM_EEV2SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 2 */
01820 #define HRTIM_EEV3SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 3 */
01821 #define HRTIM_EEV4SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 4 */
01822 #define HRTIM_EEV5SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 5 */
01823 #define HRTIM_EEV6SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 6 */
01824 #define HRTIM_EEV7SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 7 */
01825 #define HRTIM_EEV8SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 8 */
01826 #define HRTIM_EEV9SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 9 */
01827 #define HRTIM_EEV10SRC_GPIO       0x00000000U                                   /*!< External event source 1U for External Event 10 */
01828 #define HRTIM_EEV1SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 1 */
01829 #define HRTIM_EEV2SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 2 */
01830 #define HRTIM_EEV3SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 3 */
01831 #define HRTIM_EEV4SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 4 */
01832 #define HRTIM_EEV5SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 5 */
01833 #define HRTIM_EEV6SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 6 */
01834 #define HRTIM_EEV7SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 7 */
01835 #define HRTIM_EEV8SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 8 */
01836 #define HRTIM_EEV9SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 9 */
01837 #define HRTIM_EEV10SRC_COMP7_OUT  (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 10 */
01838 #define HRTIM_EEV1SRC_TIM1_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 1 */
01839 #define HRTIM_EEV2SRC_TIM2_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 2 */
01840 #define HRTIM_EEV3SRC_TIM3_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 3 */
01841 #define HRTIM_EEV4SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 4 */
01842 #define HRTIM_EEV5SRC_COMP7_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 5 */
01843 #define HRTIM_EEV6SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 6 */
01844 #define HRTIM_EEV7SRC_TIM7_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 7 */
01845 #define HRTIM_EEV8SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 8 */
01846 #define HRTIM_EEV9SRC_TIM15_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 9 */
01847 #define HRTIM_EEV10SRC_TIM6_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 10 */
01848 #define HRTIM_EEV1SRC_ADC1_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 1 */
01849 #define HRTIM_EEV2SRC_ADC1_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 2 */
01850 #define HRTIM_EEV3SRC_ADC1_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 3 */
01851 #define HRTIM_EEV4SRC_ADC2_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 4 */
01852 #define HRTIM_EEV5SRC_ADC2_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 5 */
01853 #define HRTIM_EEV6SRC_ADC2_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 6 */
01854 #define HRTIM_EEV7SRC_ADC3_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 7 */
01855 #define HRTIM_EEV8SRC_ADC4_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 8 */
01856 #define HRTIM_EEV9SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 9 */
01857 #define HRTIM_EEV10SRC_ADC5_AWD1  (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 10 */
01858 /**
01859   * @}
01860   */
01861
01862 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
01863   * @{
01864   * @brief Constants defining the polarity of an external event
01865   */
01866 #define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */
01867 #define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01868 /**
01869   * @}
01870   */
01871
01872 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
01873   * @{
01874   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
01875   *        of an external event
01876   */
01877 #define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */
01878 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01879 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01880 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01881 /**
01882   * @}
01883   */
01884
01885 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
01886   * @{
01887   * @brief Constants defining whether or not an external event is programmed in
01888            fast mode
01889   */
01890 #define HRTIM_EVENTFASTMODE_DISABLE    (0x00000000U)               /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01891 #define HRTIM_EVENTFASTMODE_ENABLE     (HRTIM_EECR1_EE1FAST)       /*!< External Event is acting asynchronously on outputs (low latency mode) */
01892 /**
01893   * @}
01894   */
01895
01896 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
01897   * @{
01898   * @brief Constants defining the frequency used to sample an external event 6
01899   *        input and the length (N) of the digital filter applied
01900   */
01901 #define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */
01902 #define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */
01903 #define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */
01904 #define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */
01905 #define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */
01906 #define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */
01907 #define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */
01908 #define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */
01909 #define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */
01910 #define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */
01911 #define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */
01912 #define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */
01913 #define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */
01914 #define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */
01915 #define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */
01916 #define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */
01917 /**
01918   * @}
01919   */
01920
01921 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
01922   * @{
01923   * @brief Constants defining division ratio between the timer clock frequency
01924   *        fHRTIM) and the external event signal sampling clock (fEEVS)
01925   *        used by the digital filters
01926   */
01927 #define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */
01928 #define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */
01929 #define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */
01930 #define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */
01931 /**
01932   * @}
01933   */
01934
01935 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
01936   * @{
01937   * @brief Constants defining whether a fault is triggered by any external
01938   *        or internal fault source
01939   */
01940 #define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)              /*!< Fault input is FLT input pin */
01941 #define HRTIM_FAULTSOURCE_INTERNAL          (0x00000001U)              /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01942 #define HRTIM_FAULTSOURCE_EEVINPUT          (0x00000002U)              /*!< Fault input is EEV pin */
01943 /**
01944   * @}
01945   */
01946
01947 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
01948   * @{
01949   * @brief Constants defining the polarity of a fault event
01950   */
01951 #define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)            /*!< Fault input is active low */
01952 #define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
01953 /**
01954   * @}
01955   */
01956
01957 /** @defgroup HRTIM_Fault_Blanking HRTIM Fault Blanking Source
01958   * @{
01959   * @brief Constants defining the blanking source of a fault event
01960   */
01961 #define HRTIM_FAULTBLANKINGMODE_RSTALIGNED  (0x00000000U)     /*!< Fault blanking source is Reset-aligned window */
01962 #define HRTIM_FAULTBLANKINGMODE_MOVING      (0x00000001U)     /*!< Fault blanking source is Moving window */
01963 /**
01964   * @}
01965   */
01966
01967 /** @defgroup HRTIM_Fault_ResetMode HRTIM Fault Reset Mode
01968   * @{
01969   * @brief Constants defining the Counter reset mode of a fault event
01970   */
01971 #define HRTIM_FAULTCOUNTERRST_UNCONDITIONAL  (0x00000000U)       /*!< Fault counter is reset on each reset / roll-over event */
01972 #define HRTIM_FAULTCOUNTERRST_CONDITIONAL    (0x00000001U)       /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod.*/
01973 /**
01974   * @}
01975   */
01976
01977 /** @defgroup HRTIM_Fault_Blanking_Control  HRTIM Fault Blanking Control
01978   * @{
01979   * @brief Constants used to enable or disable the blanking mode of a fault channel
01980   */
01981 #define HRTIM_FAULTBLANKINGCTL_DISABLED 0x00000000U /*!< No blanking on Fault */
01982 #define HRTIM_FAULTBLANKINGCTL_ENABLED  0x00000001U /*!< Fault blanking mode */
01983 /**
01984   * @}
01985   */
01986
01987 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
01988   * @{
01989   * @ brief Constants defining the frequency used to sample the fault input and
01990   *         the length (N) of the digital filter applied
01991   */
01992 #define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */
01993 #define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */
01994 #define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */
01995 #define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */
01996 #define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */
01997 #define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */
01998 #define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */
01999 #define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */
02000 #define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */
02001 #define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */
02002 #define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */
02003 #define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */
02004 #define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */
02005 #define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */
02006 #define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */
02007 #define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */
02008 /**
02009   * @}
02010   */
02011
02012 /** @defgroup HRTIM_Fault_Counter HRTIM Fault counter threshold value
02013   * @{
02014   * @ brief Constants defining the FAULT Counter threshold
02015   */
02016 #define HRTIM_FAULTCOUNTER_NONE     ((uint32_t)0U )  /*!< Counter threshold = 0U */
02017 #define HRTIM_FAULTCOUNTER_1        ((uint32_t)1U )  /*!< Counter threshold = 1U */
02018 #define HRTIM_FAULTCOUNTER_2        ((uint32_t)2U )  /*!< Counter threshold = 2U */
02019 #define HRTIM_FAULTCOUNTER_3        ((uint32_t)3U )  /*!< Counter threshold = 3U */
02020 #define HRTIM_FAULTCOUNTER_4        ((uint32_t)4U )  /*!< Counter threshold = 4U */
02021 #define HRTIM_FAULTCOUNTER_5        ((uint32_t)5U )  /*!< Counter threshold = 5U */
02022 #define HRTIM_FAULTCOUNTER_6        ((uint32_t)6U )  /*!< Counter threshold = 6U */
02023 #define HRTIM_FAULTCOUNTER_7        ((uint32_t)7U )  /*!< Counter threshold = 7U */
02024 #define HRTIM_FAULTCOUNTER_8        ((uint32_t)8U )  /*!< Counter threshold = 8U */
02025 #define HRTIM_FAULTCOUNTER_9        ((uint32_t)9U )  /*!< Counter threshold = 9U */
02026 #define HRTIM_FAULTCOUNTER_10       ((uint32_t)10U)  /*!< Counter threshold = 10U */
02027 #define HRTIM_FAULTCOUNTER_11       ((uint32_t)11U)  /*!< Counter threshold = 11U */
02028 #define HRTIM_FAULTCOUNTER_12       ((uint32_t)12U)  /*!< Counter threshold = 12U */
02029 #define HRTIM_FAULTCOUNTER_13       ((uint32_t)13U)  /*!< Counter threshold = 13U */
02030 #define HRTIM_FAULTCOUNTER_14       ((uint32_t)14U)  /*!< Counter threshold = 14U */
02031 #define HRTIM_FAULTCOUNTER_15       ((uint32_t)15U)  /*!< Counter threshold = 15U */
02032 /**
02033   * @}
02034   */
02035
02036 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
02037   * @{
02038   * @brief Constants defining whether or not the fault programming bits are
02039            write protected
02040   */
02041 #define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)               /*!< Fault settings bits are read/write */
02042 #define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */
02043 /**
02044   * @}
02045   */
02046
02047 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
02048   * @{
02049   * @brief Constants defining the division ratio between the timer clock
02050   *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
02051   *        by the digital filters.
02052   */
02053 #define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */
02054 #define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */
02055 #define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */
02056 #define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */
02057 /**
02058   * @}
02059   */
02060
02061 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
02062   * @{
02063   * @brief Constants defining if the burst mode is entered once or if it is
02064   *        continuously operating
02065   */
02066 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)           /*!< Burst mode operates in single shot mode */
02067 #define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
02068 /**
02069   * @}
02070   */
02071
02072 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
02073   * @{
02074   * @brief Constants defining the clock source for the burst mode counter
02075   */
02076 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
02077 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
02078 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
02079 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
02080 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
02081 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
02082 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_F    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
02083 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
02084 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
02085 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
02086 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
02087 /**
02088   * @}
02089   */
02090
02091 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
02092   * @{
02093   * @brief Constants defining the prescaling ratio of the fHRTIM clock
02094   *        for the burst mode controller
02095   */
02096 #define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */
02097 #define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */
02098 #define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */
02099 #define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */
02100 #define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */
02101 #define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */
02102 #define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */
02103 #define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */
02104 #define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */
02105 #define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */
02106 #define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */
02107 #define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/
02108 #define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */
02109 #define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */
02110 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */
02111 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
02112 /**
02113   * @}
02114   */
02115
02116 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
02117   * @{
02118   * @brief Constants defining whether or not burst mode registers preload
02119            mechanism is enabled, i.e. a write access into a preloadable register
02120           (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
02121   */
02122 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */
02123 #define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */
02124 /**
02125   * @}
02126   */
02127
02128 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
02129   * @{
02130   * @brief Constants defining the events that can be used to trig the burst
02131   *        mode operation
02132   */
02133 #define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U             /*!<  No trigger */
02134 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */
02135 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */
02136 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */
02137 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */
02138 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */
02139 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */
02140 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */
02141 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */
02142 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */
02143 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */
02144 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */
02145 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */
02146 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */
02147 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */
02148 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */
02149 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */
02150 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */
02151 #define HRTIM_BURSTMODETRIGGER_TIMERF_RESET       (HRTIM_BMTRGR_TFRST)    /*!< Timer F reset  */
02152 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */
02153 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */
02154 #define HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION  (HRTIM_BMTRGR_TFREP)    /*!< Timer F repetition  */
02155 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */
02156 #define HRTIM_BURSTMODETRIGGER_TIMERF_CMP1        (HRTIM_BMTRGR_TFCMP1)   /*!< Timer F compare 1  */
02157 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */
02158 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */
02159 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */
02160 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */
02161 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */
02162 #define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */
02163 #define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/
02164 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
02165 /**
02166   * @}
02167   */
02168
02169 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
02170   * @{
02171   * @brief constants defining the source triggering the update of the
02172      HRTIM_ADCxR register (transfer from preload to active register).
02173   */
02174 #define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                   /*!< Master timer */
02175 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */
02176 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */
02177 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
02178 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */
02179 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
02180 #define HRTIM_ADCTRIGGERUPDATE_TIMER_F (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_1) /*!< Timer F */
02181 /**
02182   * @}
02183   */
02184
02185 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
02186   * @{
02187   * @brief constants defining the events triggering ADC conversion.
02188   *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
02189   *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
02190   *        HRTIM_ADCTRIGGEREVENT579_*: ADC Triggers 5 and 7 and 9
02191   *        HRTIM_ADCTRIGGEREVENT6810_*: ADC Triggers 6 and 8 and 10
02192   */
02193 #define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U              /*!< No ADC trigger event */
02194 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */
02195 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */
02196 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */
02197 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */
02198 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */
02199 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */
02200 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */
02201 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */
02202 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */
02203 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */
02204 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2    (HRTIM_ADC1R_AD1TFC2)    /*!< ADC Trigger on Timer F compare 2U */
02205 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */
02206 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */
02207 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */
02208 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */
02209 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3    (HRTIM_ADC1R_AD1TFC3)    /*!< ADC Trigger on Timer F compare 3U */
02210 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */
02211 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */
02212 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */
02213 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */
02214 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4    (HRTIM_ADC1R_AD1TFC4)    /*!< ADC Trigger on Timer F compare 4U */
02215 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */
02216 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */
02217 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */
02218 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD  (HRTIM_ADC1R_AD1TFPER)   /*!< ADC Trigger on Timer F period */
02219 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */
02220 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */
02221 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */
02222 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET   (HRTIM_ADC1R_AD1TFRST)   /*!< ADC Trigger on Timer F reset */
02223 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */
02224 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */
02225 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */
02226
02227 #define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */
02228 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */
02229 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */
02230 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */
02231 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */
02232 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */
02233 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */
02234 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */
02235 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */
02236 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */
02237 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */
02238 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */
02239 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2    (HRTIM_ADC2R_AD2TFC2)    /*!< ADC Trigger on Timer F compare 2U */
02240 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */
02241 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */
02242 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */
02243 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3    (HRTIM_ADC2R_AD2TFC3)    /*!< ADC Trigger on Timer F compare 3U */
02244 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */
02245 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */
02246 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */
02247 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4    (HRTIM_ADC2R_AD2TFC4)    /*!< ADC Trigger on Timer F compare 4U */
02248 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */
02249 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */
02250 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */
02251 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */
02252 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD  (HRTIM_ADC2R_AD2TFPER)   /*!< ADC Trigger on Timer F period */
02253 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */
02254 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */
02255 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */
02256 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */
02257 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */
02258 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */
02259 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */
02260
02261
02262 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1    ((uint32_t)0x00U)  /*!< ADC Trigger on master compare 1U */
02263 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2    ((uint32_t)0x01U)  /*!< ADC Trigger on master compare 2U */
02264 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3    ((uint32_t)0x02U)  /*!< ADC Trigger on master compare 3U */
02265 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4    ((uint32_t)0x03U)  /*!< ADC Trigger on master compare 4U */
02266 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD  ((uint32_t)0x04U)  /*!< ADC Trigger on master period */
02267 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_6        ((uint32_t)0x05U)  /*!< ADC Trigger on external event 6U */
02268 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_7        ((uint32_t)0x06U)  /*!< ADC Trigger on external event 7U */
02269 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_8        ((uint32_t)0x07U)  /*!< ADC Trigger on external event 8U */
02270 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_9        ((uint32_t)0x08U)  /*!< ADC Trigger on external event 9U */
02271 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_10       ((uint32_t)0x09U)  /*!< ADC Trigger on external event 10U */
02272 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2    ((uint32_t)0x0AU)  /*!< ADC Trigger on Timer A compare 2U */
02273 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4    ((uint32_t)0x0BU)  /*!< ADC Trigger on Timer A compare 4U */
02274 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD  ((uint32_t)0x0CU)  /*!< ADC Trigger on Timer A period */
02275 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2    ((uint32_t)0x0DU)  /*!< ADC Trigger on Timer B compare 2U */
02276 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4    ((uint32_t)0x0EU)  /*!< ADC Trigger on Timer B compare 4U */
02277 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD  ((uint32_t)0x0FU)  /*!< ADC Trigger on Timer B period */
02278 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2    ((uint32_t)0x10U)  /*!< ADC Trigger on Timer C compare 2U */
02279 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4    ((uint32_t)0x11U)  /*!< ADC Trigger on Timer C compare 4U */
02280 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD  ((uint32_t)0x12U)  /*!< ADC Trigger on Timer C period */
02281 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET   ((uint32_t)0x13U)  /*!< ADC Trigger on Timer C reset */
02282 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2    ((uint32_t)0x14U)  /*!< ADC Trigger on Timer D compare 2U */
02283 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4    ((uint32_t)0x15U)  /*!< ADC Trigger on Timer D compare 4U */
02284 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD  ((uint32_t)0x16U)  /*!< ADC Trigger on Timer D period */
02285 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET   ((uint32_t)0x17U)  /*!< ADC Trigger on Timer D reset */
02286 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2    ((uint32_t)0x18U)  /*!< ADC Trigger on Timer E compare 2U */
02287 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3    ((uint32_t)0x19U)  /*!< ADC Trigger on Timer E compare 3U */
02288 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4    ((uint32_t)0x1AU)  /*!< ADC Trigger on Timer E compare 4U */
02289 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET   ((uint32_t)0x1BU)  /*!< ADC Trigger on Timer E reset */
02290 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2    ((uint32_t)0x1CU)  /*!< ADC Trigger on Timer F compare 2U */
02291 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3    ((uint32_t)0x1DU)  /*!< ADC Trigger on Timer F compare 3U */
02292 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4    ((uint32_t)0x1EU)  /*!< ADC Trigger on Timer F compare 4U */
02293 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD  ((uint32_t)0x1FU)  /*!< ADC Trigger on Timer F period */
02294
02295 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1    ((uint32_t)0x00U)  /*!< ADC Trigger on master compare 1U */
02296 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2    ((uint32_t)0x01U)  /*!< ADC Trigger on master compare 2U */
02297 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3    ((uint32_t)0x02U)  /*!< ADC Trigger on master compare 3U */
02298 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4    ((uint32_t)0x03U)  /*!< ADC Trigger on master compare 4U */
02299 #define HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD  ((uint32_t)0x04U)  /*!< ADC Trigger on master period */
02300 #define HRTIM_ADCTRIGGEREVENT579_EVENT_1        ((uint32_t)0x05U)  /*!< ADC Trigger on external event 1U */
02301 #define HRTIM_ADCTRIGGEREVENT579_EVENT_2        ((uint32_t)0x06U)  /*!< ADC Trigger on external event 2U */
02302 #define HRTIM_ADCTRIGGEREVENT579_EVENT_3        ((uint32_t)0x07U)  /*!< ADC Trigger on external event 3U */
02303 #define HRTIM_ADCTRIGGEREVENT579_EVENT_4        ((uint32_t)0x08U)  /*!< ADC Trigger on external event 4U */
02304 #define HRTIM_ADCTRIGGEREVENT579_EVENT_5        ((uint32_t)0x09U)  /*!< ADC Trigger on external event 5U */
02305 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3    ((uint32_t)0x0AU)  /*!< ADC Trigger on Timer A compare 3U */
02306 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4    ((uint32_t)0x0BU)  /*!< ADC Trigger on Timer A compare 4U */
02307 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD  ((uint32_t)0x0CU)  /*!< ADC Trigger on Timer A period */
02308 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET   ((uint32_t)0x0DU)  /*!< ADC Trigger on Timer A reset */
02309 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3    ((uint32_t)0x0EU)  /*!< ADC Trigger on Timer B compare 3U */
02310 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4    ((uint32_t)0x0FU)  /*!< ADC Trigger on Timer B compare 4U */
02311 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD  ((uint32_t)0x10U)  /*!< ADC Trigger on Timer B period */
02312 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET   ((uint32_t)0x11U)  /*!< ADC Trigger on Timer B reset */
02313 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3    ((uint32_t)0x12U)  /*!< ADC Trigger on Timer C compare 3U */
02314 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4    ((uint32_t)0x13U)  /*!< ADC Trigger on Timer C compare 4U */
02315 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD  ((uint32_t)0x14U)  /*!< ADC Trigger on Timer C period */
02316 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3    ((uint32_t)0x15U)  /*!< ADC Trigger on Timer D compare 3U */
02317 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4    ((uint32_t)0x16U)  /*!< ADC Trigger on Timer D compare 4U */
02318 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD  ((uint32_t)0x17U)  /*!< ADC Trigger on Timer D period */
02319 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3    ((uint32_t)0x18U)  /*!< ADC Trigger on Timer E compare 3U */
02320 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4    ((uint32_t)0x19U)  /*!< ADC Trigger on Timer E compare 4U */
02321 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD  ((uint32_t)0x1AU)  /*!< ADC Trigger on Timer E period */
02322 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2    ((uint32_t)0x1BU)  /*!< ADC Trigger on Timer F compare 2U */
02323 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3    ((uint32_t)0x1CU)  /*!< ADC Trigger on Timer F compare 3U */
02324 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4    ((uint32_t)0x1DU)  /*!< ADC Trigger on Timer F compare 4U */
02325 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD  ((uint32_t)0x1EU)  /*!< ADC Trigger on Timer F period */
02326 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET   ((uint32_t)0x1FU)  /*!< ADC Trigger on Timer F reset */
02327 /**
02328   * @}
02329   */
02330
02331 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
02332   * @{
02333   * @brief Constants defining the DLL calibration periods (in micro seconds)
02334   */
02335 #define HRTIM_SINGLE_CALIBRATION    0xFFFFFFFFU                                    /*!< Non periodic DLL calibration */
02336 #define HRTIM_CALIBRATIONRATE_0     0x00000000U                                    /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
02337 #define HRTIM_CALIBRATIONRATE_1     (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
02338 #define HRTIM_CALIBRATIONRATE_2     (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
02339 #define HRTIM_CALIBRATIONRATE_3     (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
02340 /**
02341   * @}
02342   */
02343
02344 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
02345   * @{
02346   * @brief Constants defining the registers that can be written during a burst
02347   *        DMA operation
02348   */
02349 #define HRTIM_BURSTDMA_NONE  0x00000000U               /*!< No register is updated by Burst DMA accesses */
02350 #define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
02351 #define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
02352 #define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
02353 #define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
02354 #define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */
02355 #define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */
02356 #define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
02357 #define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
02358 #define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
02359 #define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
02360 #define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */
02361 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
02362 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
02363 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
02364 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
02365 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
02366 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
02367 #define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
02368 #define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
02369 #define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
02370 #define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
02371 #define HRTIM_BURSTDMA_CR2   (HRTIM_BDTUPR_TIMCR2)     /*!< TIMxCR2 register is updated by Burst DMA accesses */
02372 #define HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3)   /*!< EEFxR3 register is updated by Burst DMA accesses */
02373 /**
02374   * @}
02375   */
02376
02377 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
02378   * @{
02379   * @brief Constants used to enable or disable the burst mode controller
02380   */
02381 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U          /*!< Burst mode disabled */
02382 #define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */
02383 /**
02384   * @}
02385   */
02386
02387 /** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
02388   * @{
02389   * @brief Constants used to enable or disable a fault channel
02390   */
02391 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
02392 #define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */
02393 /**
02394   * @}
02395   */
02396
02397 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
02398   * @{
02399   * @brief Constants used to force timer registers update
02400   */
02401 #define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */
02402 #define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */
02403 #define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */
02404 #define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */
02405 #define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */
02406 #define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */
02407 #define HRTIM_TIMERUPDATE_F         (HRTIM_CR2_TFSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer F */
02408 /**
02409   * @}
02410   */
02411
02412 /** @defgroup HRTIM_Software_Timer_SwapOutput  HRTIM Software Timer swap Output
02413   * @{
02414   * @brief Constants used to swap the output of the timer registers
02415   */
02416 #define HRTIM_TIMERSWAP_A         (HRTIM_CR2_SWPA)    /*!< Swap the output of the Timer A */
02417 #define HRTIM_TIMERSWAP_B         (HRTIM_CR2_SWPB)    /*!< Swap the output of the Timer B */
02418 #define HRTIM_TIMERSWAP_C         (HRTIM_CR2_SWPC)    /*!< Swap the output of the Timer C */
02419 #define HRTIM_TIMERSWAP_D         (HRTIM_CR2_SWPD)    /*!< Swap the output of the Timer D */
02420 #define HRTIM_TIMERSWAP_E         (HRTIM_CR2_SWPE)    /*!< Swap the output of the Timer E */
02421 #define HRTIM_TIMERSWAP_F         (HRTIM_CR2_SWPF)    /*!< Swap the output of the Timer F */
02422 /**
02423   * @}
02424   */
02425
02426 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
02427   * @{
02428   * @brief Constants used to force timer counter reset
02429   */
02430 #define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Reset the master timer counter */
02431 #define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Reset the timer A counter */
02432 #define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Reset the timer B counter */
02433 #define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Reset the timer C counter */
02434 #define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Reset the timer D counter */
02435 #define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Reset the timer E counter */
02436 #define HRTIM_TIMERRESET_TIMER_F   (HRTIM_CR2_TFRST)    /*!< Reset the timer F counter */
02437 /**
02438   * @}
02439   */
02440
02441 /** @defgroup HRTIM_Output_Level HRTIM Output Level
02442   * @{
02443   * @brief Constants defining the level of a timer output
02444   */
02445 #define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Force the output to its active state */
02446 #define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Force the output to its inactive state */
02447
02448 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
02449     (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
02450      ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
02451 /**
02452   * @}
02453   */
02454
02455 /** @defgroup HRTIM_Output_State HRTIM Output State
02456   * @{
02457   * @brief Constants defining the state of a timer output
02458   */
02459 #define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or
02460                                                               inactive level as programmed in the crossbar unit */
02461 #define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
02462                                                               outputs are disabled by software or during a burst mode operation */
02463 #define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
02464                                                               FAULTx inputs */
02465 /**
02466   * @}
02467   */
02468
02469 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
02470   * @{
02471   * @brief Constants defining the operating state of the burst mode controller
02472   */
02473 #define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U          /*!< Normal operation */
02474 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */
02475 /**
02476   * @}
02477   */
02478
02479 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
02480   * @{
02481   * @brief Constants defining on which output the signal is currently applied
02482   *        in push-pull mode
02483   */
02484 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U            /*!< Signal applied on output 1 and output 2 forced inactive */
02485 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
02486 /**
02487   * @}
02488   */
02489
02490 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
02491   * @{
02492   * @brief Constants defining on which output the signal was applied, in
02493   *        push-pull mode balanced fault mode or delayed idle mode, when the
02494   *        protection was triggered
02495   */
02496 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U               /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
02497 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
02498 /**
02499   * @}
02500   */
02501
02502 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
02503   * @{
02504   */
02505 #define HRTIM_IT_NONE           0x00000000U           /*!< No interrupt enabled */
02506 #define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */
02507 #define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */
02508 #define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */
02509 #define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */
02510 #define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */
02511 #define HRTIM_IT_FLT6           HRTIM_IER_FLT6        /*!< Fault 6 interrupt enable */
02512 #define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */
02513 #define HRTIM_IT_DLLRDY         HRTIM_IER_DLLRDY      /*!< DLL ready interrupt enable */
02514 #define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */
02515 /**
02516   * @}
02517   */
02518
02519 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
02520   * @{
02521   */
02522 #define HRTIM_MASTER_IT_NONE         0x00000000U           /*!< No interrupt enabled */
02523 #define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */
02524 #define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */
02525 #define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */
02526 #define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */
02527 #define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */
02528 #define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */
02529 #define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */
02530 /**
02531   * @}
02532   */
02533
02534 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
02535   * @{
02536   */
02537 #define HRTIM_TIM_IT_NONE       0x00000000U               /*!< No interrupt enabled */
02538 #define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */
02539 #define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */
02540 #define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */
02541 #define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */
02542 #define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */
02543 #define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */
02544 #define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */
02545 #define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */
02546 #define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */
02547 #define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */
02548 #define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */
02549 #define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */
02550 #define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */
02551 #define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */
02552 /**
02553   * @}
02554   */
02555
02556 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
02557   * @{
02558   */
02559 #define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */
02560 #define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */
02561 #define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */
02562 #define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */
02563 #define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */
02564 #define HRTIM_FLAG_FLT6           HRTIM_ISR_FLT6    /*!< Fault 6 interrupt flag */
02565 #define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */
02566 #define HRTIM_FLAG_DLLRDY         HRTIM_ISR_DLLRDY  /*!< DLL ready interrupt flag */
02567 #define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */
02568 /**
02569   * @}
02570   */
02571
02572 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
02573   * @{
02574   */
02575 #define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */
02576 #define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */
02577 #define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */
02578 #define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4    /*!< Master compare 4 interrupt flag */
02579 #define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP     /*!< Master Repetition interrupt flag */
02580 #define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC     /*!< Synchronization input interrupt flag */
02581 #define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD     /*!< Master update interrupt flag */
02582 /**
02583   * @}
02584   */
02585
02586 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
02587   * @{
02588   */
02589 #define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */
02590 #define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */
02591 #define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */
02592 #define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */
02593 #define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */
02594 #define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */
02595 #define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */
02596 #define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */
02597 #define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */
02598 #define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */
02599 #define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */
02600 #define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */
02601 #define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */
02602 #define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */
02603 /**
02604   * @}
02605   */
02606
02607 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
02608   * @{
02609   */
02610 #define HRTIM_MASTER_DMA_NONE         0x00000000U            /*!< No DMA request enable */
02611 #define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */
02612 #define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */
02613 #define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */
02614 #define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */
02615 #define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */
02616 #define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */
02617 #define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */
02618 /**
02619   * @}
02620   */
02621
02622 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
02623   * @{
02624   */
02625 #define HRTIM_TIM_DMA_NONE       0x00000000U               /*!< No DMA request enable */
02626 #define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */
02627 #define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */
02628 #define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */
02629 #define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */
02630 #define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */
02631 #define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */
02632 #define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */
02633 #define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */
02634 #define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */
02635 #define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */
02636 #define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */
02637 #define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */
02638 #define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */
02639 #define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */
02640 /**
02641   * @}
02642   */
02643
02644 /**
02645   * @}
02646   */
02647
02648 /* Private Constants --------------------------------------------------------*/
02649 /** @addtogroup HRTIM_Private_Constants
02650   * @{
02651   */
02652 #define HRTIM_CAPTUREFTRIGGER_NONE         0x00000000U                  /*!< 32bit value Capture trigger is disabled */
02653 #define HRTIM_CAPTUREFTRIGGER_TF1_SET      (HRTIM_CPT1CR_TF1SET)        /*!< 32bit value Capture is triggered by TF1 output inactive to active transition */
02654 #define HRTIM_CAPTUREFTRIGGER_TF1_RESET    (HRTIM_CPT1CR_TF1RST)        /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */
02655 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1  (HRTIM_CPT1CR_TIMFCMP1)      /*!< 32bit value Timer F Compare 1 triggers Capture */
02656 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2  (HRTIM_CPT1CR_TIMFCMP2)      /*!< 32bit value Timer F Compare 2 triggers Capture */
02657  /**
02658   * @}
02659   */
02660
02661   /* Private macros --------------------------------------------------------*/
02662 /** @addtogroup HRTIM_Private_Macros
02663   * @{
02664   */
02665 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
02666     (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
02667      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02668      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02669      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02670      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02671      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)  || \
02672      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
02673
02674 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
02675      (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
02676       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
02677       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
02678       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
02679       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)  || \
02680       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
02681
02682 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U)
02683
02684 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
02685     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
02686      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
02687      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
02688      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
02689
02690 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
02691     (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
02692      ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
02693
02694 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U)
02695
02696 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
02697     ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
02698      (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
02699       ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
02700     ||                                           \
02701     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
02702      (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
02703       ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
02704     ||                                           \
02705     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
02706      (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
02707       ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
02708     ||                                           \
02709     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
02710      (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
02711       ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
02712     ||                                           \
02713     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
02714      (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
02715       ((OUTPUT) == HRTIM_OUTPUT_TE2)))           \
02716     ||                                           \
02717     (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&    \
02718      (((OUTPUT) == HRTIM_OUTPUT_TF1) ||          \
02719       ((OUTPUT) == HRTIM_OUTPUT_TF2))))
02720
02721 #define IS_HRTIM_TIMEEVENT(EVENT)\
02722       (((EVENT) == HRTIM_EVENTCOUNTER_A)   || \
02723        ((EVENT) == HRTIM_EVENTCOUNTER_B))
02724
02725 #define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\
02726       (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL)   || \
02727        ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL))
02728
02729 #define IS_HRTIM_TIMSYNCUPDATE(EVENT)\
02730       (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL)   || \
02731        ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL))
02732
02733 #define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\
02734        ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\
02735          ((COUNTER) == (uint32_t)0x00U))
02736
02737 #define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\
02738        (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U))
02739
02740 #define IS_HRTIM_EVENT(EVENT)\
02741       (((EVENT) == HRTIM_EVENT_NONE)|| \
02742        ((EVENT) == HRTIM_EVENT_1)   || \
02743        ((EVENT) == HRTIM_EVENT_2)   || \
02744        ((EVENT) == HRTIM_EVENT_3)   || \
02745        ((EVENT) == HRTIM_EVENT_4)   || \
02746        ((EVENT) == HRTIM_EVENT_5)   || \
02747        ((EVENT) == HRTIM_EVENT_6)   || \
02748        ((EVENT) == HRTIM_EVENT_7)   || \
02749        ((EVENT) == HRTIM_EVENT_8)   || \
02750        ((EVENT) == HRTIM_EVENT_9)   || \
02751        ((EVENT) == HRTIM_EVENT_10))
02752
02753 #define IS_HRTIM_FAULT(FAULT)\
02754       (((FAULT) == HRTIM_FAULT_1)   || \
02755        ((FAULT) == HRTIM_FAULT_2)   || \
02756        ((FAULT) == HRTIM_FAULT_3)   || \
02757        ((FAULT) == HRTIM_FAULT_4)   || \
02758        ((FAULT) == HRTIM_FAULT_5)   || \
02759        ((FAULT) == HRTIM_FAULT_6))
02760
02761 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
02762         (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
02763          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
02764          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
02765          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
02766          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
02767          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
02768          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
02769          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
02770
02771 #define IS_HRTIM_MODE(MODE)\
02772           (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
02773            ((MODE) == HRTIM_MODE_SINGLESHOT) || \
02774            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02775
02776 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
02777           (((MODE) == HRTIM_MODE_SINGLESHOT) || \
02778            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
02779
02780
02781 #define IS_HRTIM_HALFMODE(HALFMODE)\
02782             (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
02783              ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
02784
02785 #define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\
02786             (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)  ||  \
02787              ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL)   ||  \
02788              ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)   ||  \
02789              ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE)   ||  \
02790              ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)   ||  \
02791              ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD))
02792
02793 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
02794               (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
02795                ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
02796
02797 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
02798                 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
02799                  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
02800
02801 #define IS_HRTIM_DACSYNC(DACSYNC)\
02802                 (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
02803                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
02804                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
02805                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
02806
02807 #define IS_HRTIM_PRELOAD(PRELOAD)\
02808                 (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
02809                  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
02810
02811 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
02812                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02813                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02814                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
02815
02816 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
02817                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
02818                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
02819                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
02820                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
02821                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
02822                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
02823                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
02824                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
02825                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
02826
02827 #define IS_HRTIM_TIMERBURSTMODE(MODE)                               \
02828                 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
02829                  ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
02830 #define IS_HRTIM_TIMERUPDOWNMODE(MODE)                               \
02831                 (((MODE) == HRTIM_TIMERUPDOWNMODE_UP)  || \
02832                  ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN))
02833
02834 #define IS_HRTIM_TIMERTRGHLFMODE(MODE)                               \
02835                 (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED)  || \
02836                  ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED))
02837
02838 #define IS_HRTIM_TIMERGTCMP3(MODE)                               \
02839                 (((MODE) == HRTIM_TIMERGTCMP3_EQUAL)  || \
02840                  ((MODE) == HRTIM_TIMERGTCMP3_GREATER))
02841
02842 #define IS_HRTIM_TIMERGTCMP1(MODE)                               \
02843                 (((MODE) == HRTIM_TIMERGTCMP1_EQUAL)  || \
02844                  ((MODE) == HRTIM_TIMERGTCMP1_GREATER))
02845
02846 #define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC)                               \
02847                 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER)  || \
02848                  ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET))
02849
02850 #define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC)                               \
02851                 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2)  || \
02852                  ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST))
02853
02854 #define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC)                               \
02855                 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED)  || \
02856                  ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED ))
02857
02858 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \
02859                 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
02860                  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
02861
02862 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
02863                   (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
02864                    ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
02865 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U)
02866
02867 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
02868       (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
02869        ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
02870
02871 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
02872     (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
02873           ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
02874
02875 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
02876           ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
02877             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
02878             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
02879             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
02880             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
02881             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
02882             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
02883             ||                                                                           \
02884             (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
02885              (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
02886              ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
02887
02888 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U)
02889
02890 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x00000000U) == 0x00000000U)
02891
02892
02893 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
02894               (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
02895                ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
02896
02897 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
02898               (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
02899                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
02900                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
02901                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
02902
02903 /* Auto delayed mode is only available for compare units 2 and 4U */
02904 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
02905     ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
02906      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02907       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02908       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02909       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
02910     ||                                                                         \
02911     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
02912      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
02913       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
02914       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
02915       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
02916
02917 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
02918               (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
02919                ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
02920
02921 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
02922
02923 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
02924               (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)             || \
02925                ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)           || \
02926                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)           || \
02927                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)          || \
02928                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)          || \
02929                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)          || \
02930                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)          || \
02931                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)        || \
02932                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1)       || \
02933                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2)       || \
02934                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3)       || \
02935                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4)       || \
02936                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \
02937                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \
02938                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \
02939                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \
02940                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \
02941                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \
02942                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \
02943                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \
02944                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \
02945                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)            || \
02946                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)            || \
02947                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)            || \
02948                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)            || \
02949                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)            || \
02950                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)            || \
02951                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)            || \
02952                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)            || \
02953                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)            || \
02954                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)           || \
02955                ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
02956
02957 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
02958               (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)             || \
02959                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)           || \
02960                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)           || \
02961                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)          || \
02962                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)          || \
02963                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)          || \
02964                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)          || \
02965                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)        || \
02966                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1)       || \
02967                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2)       || \
02968                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3)       || \
02969                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4)       || \
02970                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \
02971                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \
02972                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \
02973                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \
02974                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \
02975                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \
02976                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \
02977                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \
02978                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \
02979                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)            || \
02980                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)            || \
02981                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)            || \
02982                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)            || \
02983                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)            || \
02984                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)            || \
02985                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)            || \
02986                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)            || \
02987                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)            || \
02988                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)           || \
02989                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
02990
02991 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
02992               (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
02993                ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
02994
02995 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
02996               (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
02997                ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
02998
02999 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
03000               (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
03001                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
03002                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
03003                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
03004
03005 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
03006               (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
03007                ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
03008
03009 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
03010               (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
03011                ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
03012
03013 #define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\
03014               (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED)  || \
03015                ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED))
03016
03017 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
03018    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
03019    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
03020    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
03021    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
03022    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
03023    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
03024    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
03025    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
03026    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
03027    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
03028    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
03029    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
03030    ||                                                           \
03031    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
03032      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
03033       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
03034       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
03035       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
03036       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
03037       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
03038       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
03039       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
03040       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
03041       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
03042       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
03043       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
03044       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
03045       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
03046       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
03047       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
03048     ||                                                          \
03049    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
03050      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
03051       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
03052       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
03053       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
03054       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
03055       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
03056       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
03057       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
03058       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
03059       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
03060       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
03061       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
03062       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
03063       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
03064       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
03065       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
03066     ||                                                          \
03067    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
03068      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
03069       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
03070       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
03071       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
03072       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
03073       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
03074       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
03075       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
03076       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
03077       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
03078       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
03079       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
03080       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
03081       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
03082       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
03083       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
03084     ||                                                          \
03085    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
03086      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
03087       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
03088       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
03089       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
03090       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
03091       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
03092       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
03093       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
03094       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
03095       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
03096       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
03097       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
03098       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
03099       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
03100       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
03101       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
03102     ||                                                          \
03103    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
03104      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
03105       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
03106       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
03107       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
03108       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
03109       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
03110       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
03111       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
03112       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
03113       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
03114       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
03115       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
03116       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
03117       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
03118       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
03119       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))  \
03120     ||                                                          \
03121    (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&                    \
03122      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
03123       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
03124       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
03125       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
03126       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
03127       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
03128       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
03129       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
03130       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
03131       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
03132       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
03133       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
03134       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
03135       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
03136       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
03137       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
03138       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
03139       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
03140       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
03141       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
03142
03143 #define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER)    \
03144    (  ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE)        || \
03145       ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET)     || \
03146       ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET)   || \
03147       ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \
03148       ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2))
03149
03150 #define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\
03151    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE)           || \
03152     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1)   || \
03153     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2)   || \
03154     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3)   || \
03155     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4)   || \
03156     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2)  || \
03157     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3)  || \
03158     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM)      \
03159   ||                                                             \
03160    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                     \
03161      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1)  || \
03162       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4)  || \
03163       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2)  || \
03164       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1)  || \
03165       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4)  || \
03166       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1)  || \
03167       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1)  || \
03168       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2)))   \
03169     ||                                                           \
03170    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                     \
03171      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1)  || \
03172       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4)  || \
03173       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2)  || \
03174       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1)  || \
03175       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2)  || \
03176       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2)  || \
03177       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2)  || \
03178       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1)))   \
03179     ||                                                           \
03180    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                     \
03181      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2)  || \
03182       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1)  || \
03183       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4)  || \
03184       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1)  || \
03185       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1)  || \
03186       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4)  || \
03187       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2)  || \
03188       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4)))   \
03189     ||                                                           \
03190    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                     \
03191      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1)  || \
03192       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2)  || \
03193       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1)  || \
03194       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2)  || \
03195       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2)  || \
03196       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1)  || \
03197       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4)  || \
03198       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4)))   \
03199     ||                                                           \
03200    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                     \
03201      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2)  || \
03202       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1)  || \
03203       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1)  || \
03204       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4)  || \
03205       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2)  || \
03206       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1)  || \
03207       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4)  || \
03208       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2)))   \
03209     ||                                                           \
03210    (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&                     \
03211      (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4)  || \
03212       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2)  || \
03213       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4)  || \
03214       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2)  || \
03215       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4)  || \
03216       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1)  || \
03217       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4)  || \
03218       ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2))))
03219
03220 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
03221               (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
03222                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
03223
03224 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
03225                 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
03226                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
03227                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
03228                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
03229                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
03230                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
03231                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
03232                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
03233
03234 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
03235                 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
03236                  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
03237
03238 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
03239                     (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
03240                      ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
03241
03242 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
03243                   (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
03244                    ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
03245
03246 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
03247                       (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
03248                        ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
03249
03250 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
03251                           (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
03252                            ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
03253
03254 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
03255                         (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
03256                          ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
03257
03258 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
03259                         (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
03260                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
03261                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
03262                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
03263                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
03264                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
03265                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
03266                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
03267                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
03268                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
03269                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
03270                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
03271                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
03272                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
03273                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
03274                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
03275
03276 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
03277                         (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
03278                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
03279                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
03280                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
03281                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
03282                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
03283                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
03284                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
03285
03286 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
03287                         (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
03288                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
03289                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
03290                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
03291                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
03292                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
03293                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
03294                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
03295                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
03296                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
03297                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
03298                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
03299                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
03300                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
03301                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
03302                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
03303
03304 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
03305               (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
03306                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
03307                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
03308
03309 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
03310               (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
03311                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
03312                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
03313                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
03314
03315 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
03316               (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
03317                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
03318                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
03319
03320 #define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC)                      \
03321     ((((EVENT) == HRTIM_EVENT_1) &&                             \
03322                  (((EVENTSRC) == HRTIM_EEV1SRC_GPIO      )   || \
03323                   ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT )   || \
03324                   ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO )   || \
03325                   ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 )))    \
03326     ||                                                          \
03327      (((EVENT) == HRTIM_EVENT_2) &&                             \
03328                  (((EVENTSRC) == HRTIM_EEV2SRC_GPIO      )   || \
03329                   ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT )   || \
03330                   ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO )   || \
03331                   ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 )))    \
03332     ||                                                          \
03333      (((EVENT) == HRTIM_EVENT_3) &&                             \
03334                  (((EVENTSRC) == HRTIM_EEV3SRC_GPIO      )   || \
03335                   ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT )   || \
03336                   ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO )   || \
03337                   ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 )))    \
03338     ||                                                          \
03339      (((EVENT) == HRTIM_EVENT_4) &&                             \
03340                  (((EVENTSRC) == HRTIM_EEV4SRC_GPIO      )   || \
03341                   ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT )   || \
03342                   ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT )   || \
03343                   ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 )))    \
03344     ||                                                          \
03345      (((EVENT) == HRTIM_EVENT_5) &&                             \
03346                  (((EVENTSRC) == HRTIM_EEV5SRC_GPIO      )   || \
03347                   ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT )   || \
03348                   ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT )   || \
03349                   ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 )))    \
03350     ||                                                          \
03351      (((EVENT) == HRTIM_EVENT_6) &&                             \
03352                  (((EVENTSRC) == HRTIM_EEV6SRC_GPIO      )   || \
03353                   ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT )   || \
03354                   ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT )   || \
03355                   ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 )))    \
03356     ||                                                          \
03357      (((EVENT) == HRTIM_EVENT_7) &&                             \
03358                  (((EVENTSRC) == HRTIM_EEV7SRC_GPIO      )   || \
03359                   ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT )   || \
03360                   ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO )   || \
03361                   ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 )))    \
03362     ||                                                          \
03363      (((EVENT) == HRTIM_EVENT_8) &&                             \
03364                  (((EVENTSRC) == HRTIM_EEV8SRC_GPIO      )   || \
03365                   ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT )   || \
03366                   ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT )   || \
03367                   ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 )))    \
03368     ||                                                          \
03369      (((EVENT) == HRTIM_EVENT_9) &&                             \
03370                  (((EVENTSRC) == HRTIM_EEV9SRC_GPIO      )   || \
03371                   ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT )   || \
03372                   ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO)   || \
03373                   ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT )))    \
03374     ||                                                          \
03375      (((EVENT) == HRTIM_EVENT_10) &&                            \
03376                  (((EVENTSRC) == HRTIM_EEV10SRC_GPIO     )   || \
03377                   ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT)   || \
03378                   ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO)   || \
03379                   ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))))
03380
03381 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
03382     ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
03383        (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
03384         ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
03385       ||                                                            \
03386       (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
03387        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
03388        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
03389
03390 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
03391                     (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
03392                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
03393                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
03394                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
03395
03396 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
03397     (((((EVENT) == HRTIM_EVENT_1) ||                 \
03398        ((EVENT) == HRTIM_EVENT_2) ||                 \
03399        ((EVENT) == HRTIM_EVENT_3) ||                 \
03400        ((EVENT) == HRTIM_EVENT_4) ||                 \
03401        ((EVENT) == HRTIM_EVENT_5)) &&                \
03402       (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
03403        ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
03404     ||                                               \
03405     (((EVENT) == HRTIM_EVENT_6) ||                   \
03406      ((EVENT) == HRTIM_EVENT_7) ||                   \
03407      ((EVENT) == HRTIM_EVENT_8) ||                   \
03408      ((EVENT) == HRTIM_EVENT_9) ||                   \
03409      ((EVENT) == HRTIM_EVENT_10)))
03410
03411
03412 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
03413       ((((EVENT) == HRTIM_EVENT_1) ||            \
03414         ((EVENT) == HRTIM_EVENT_2) ||            \
03415         ((EVENT) == HRTIM_EVENT_3) ||            \
03416         ((EVENT) == HRTIM_EVENT_4) ||            \
03417         ((EVENT) == HRTIM_EVENT_5))              \
03418        ||                                        \
03419       ((((EVENT) == HRTIM_EVENT_6) ||            \
03420         ((EVENT) == HRTIM_EVENT_7) ||            \
03421         ((EVENT) == HRTIM_EVENT_8) ||            \
03422         ((EVENT) == HRTIM_EVENT_9) ||            \
03423         ((EVENT) == HRTIM_EVENT_10)) &&          \
03424         (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
03425         ((FILTER) == HRTIM_EVENTFILTER_1)     || \
03426         ((FILTER) == HRTIM_EVENTFILTER_2)     || \
03427         ((FILTER) == HRTIM_EVENTFILTER_3)     || \
03428         ((FILTER) == HRTIM_EVENTFILTER_4)     || \
03429         ((FILTER) == HRTIM_EVENTFILTER_5)     || \
03430         ((FILTER) == HRTIM_EVENTFILTER_6)     || \
03431         ((FILTER) == HRTIM_EVENTFILTER_7)     || \
03432         ((FILTER) == HRTIM_EVENTFILTER_8)     || \
03433         ((FILTER) == HRTIM_EVENTFILTER_9)     || \
03434         ((FILTER) == HRTIM_EVENTFILTER_10)    || \
03435         ((FILTER) == HRTIM_EVENTFILTER_11)    || \
03436         ((FILTER) == HRTIM_EVENTFILTER_12)    || \
03437         ((FILTER) == HRTIM_EVENTFILTER_13)    || \
03438         ((FILTER) == HRTIM_EVENTFILTER_14)    || \
03439         ((FILTER) == HRTIM_EVENTFILTER_15))))
03440
03441 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
03442              (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
03443               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
03444               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
03445               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
03446
03447 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
03448               (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
03449                ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \
03450                ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT))
03451
03452 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
03453               (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
03454                ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
03455
03456 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
03457     (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
03458      ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
03459
03460 #define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\
03461               (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \
03462                ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING))
03463
03464 #define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\
03465     (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED)  || \
03466      ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED))
03467
03468 #define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\
03469               (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \
03470                ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL))
03471
03472 #define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\
03473     (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED)  || \
03474      ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED))
03475
03476 #define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\
03477                 (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \
03478                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1)    || \
03479                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2)    || \
03480                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3)    || \
03481                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4)    || \
03482                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5)    || \
03483                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6)    || \
03484                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7)    || \
03485                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8)    || \
03486                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9)    || \
03487                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10)   || \
03488                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11)   || \
03489                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12)   || \
03490                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13)   || \
03491                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14)   || \
03492                  ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15))
03493
03494 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
03495                 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
03496                  ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
03497                  ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
03498                  ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
03499                  ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
03500                  ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
03501                  ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
03502                  ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
03503                  ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
03504                  ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
03505                  ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
03506                  ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
03507                  ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
03508                  ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
03509                  ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
03510                  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
03511
03512 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
03513               (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
03514                ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
03515
03516 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
03517              (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
03518               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
03519               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
03520               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
03521
03522 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
03523               (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
03524                ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
03525
03526 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
03527               (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
03528                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
03529                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
03530                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
03531                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
03532                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
03533                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F)     || \
03534                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
03535                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
03536                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
03537                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
03538
03539 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
03540               (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
03541                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
03542                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
03543                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
03544                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
03545                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
03546                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
03547                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
03548                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
03549                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
03550                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
03551                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
03552                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
03553                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
03554                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
03555                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
03556
03557 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
03558               (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
03559                ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
03560
03561 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
03562               (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
03563                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
03564                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
03565                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
03566                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
03567                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
03568                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
03569                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
03570                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
03571                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
03572                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
03573                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
03574                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
03575                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
03576                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
03577                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
03578                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
03579                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
03580                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_RESET)       || \
03581                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
03582                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
03583                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \
03584                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
03585                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_CMP1)       || \
03586                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
03587                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
03588                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
03589                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
03590                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
03591                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
03592                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
03593                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
03594
03595 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
03596              (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
03597               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
03598               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
03599               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
03600               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
03601               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)  || \
03602               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F))
03603
03604 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
03605     (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
03606      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0)  || \
03607      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1)  || \
03608      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2)  || \
03609      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3))
03610
03611 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \
03612     ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
03613   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
03614   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
03615   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
03616   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
03617   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
03618   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
03619
03620 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
03621     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
03622      ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
03623
03624 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U)
03625
03626 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFF80FFU) == 0x00000000U)
03627
03628 #define IS_HRTIM_TIMERSWAP(TIMERSWAP) (((TIMERSWAP) & 0xFFC0FFFFU) == 0x00000000U)
03629
03630 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFF80U) == 0x00000000U)
03631
03632 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
03633
03634
03635 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
03636
03637
03638 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
03639
03640 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
03641 /**
03642   * @}
03643   */
03644
03645 /* Exported macros -----------------------------------------------------------*/
03646 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
03647   * @{
03648   */
03649
03650 /**
03651   * @brief  configures the actual direction of the counter to UP counting mode
03652   * @param   __HANDLE__ : HRTIM handle.
03653   * @param   __TIMER__  : Timer index
03654   *                   This parameter can be a combination of the following values:
03655   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03656   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03657   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03658   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03659   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03660   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03661   * @retval none
03662   */
03663 #define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\
03664   do {\
03665     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
03666       {\
03667         CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03668       }\
03669     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
03670       {\
03671         CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03672       }\
03673     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
03674       {\
03675          CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03676       }\
03677     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
03678       {\
03679         CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03680       }\
03681     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
03682       {\
03683         CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03684      }\
03685     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
03686       {\
03687         CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03688       }\
03689   } while(0U)
03690
03691 /**
03692   * @brief  configures the actual direction of the counter to UP-DOWN counting mode
03693   * @param   __HANDLE__ : HRTIM handle.
03694   * @param   __TIMER__  : Timer index
03695   *                   This parameter can be a combination of the following values:
03696   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03697   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03698   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03699   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03700   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03701   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03702   * @retval none
03703   */
03704 #define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\
03705   do {\
03706     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
03707       {\
03708         SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03709       }\
03710     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
03711       {\
03712         SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03713       }\
03714     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
03715       {\
03716          SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03717       }\
03718     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
03719       {\
03720         SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03721       }\
03722     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
03723       {\
03724         SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03725      }\
03726     if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
03727       {\
03728         SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
03729       }\
03730   } while(0U)
03731
03732  /**
03733   * @brief  swap the output of the timer
03734   *         HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
03735   *         HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
03736   * @param   __HANDLE__ : HRTIM handle.
03737   * @param   __TIMER__  : Timer index
03738   *                   This parameter can be a combination of the following values:
03739   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03740   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03741   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03742   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03743   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03744   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03745   * @retval none
03746   */
03747 #define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\
03748   do {\
03749     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
03750       {\
03751         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
03752       }\
03753     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
03754       {\
03755         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
03756       }\
03757     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
03758       {\
03759         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
03760       }\
03761     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
03762       {\
03763         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
03764       }\
03765     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
03766       {\
03767         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
03768      }\
03769     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
03770       {\
03771         SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
03772       }\
03773   } while(0U)
03774
03775 /**
03776   * @brief  Un-swap the output of the timer
03777   *         HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
03778   *         HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
03779   * @param   __HANDLE__ : HRTIM handle.
03780   * @param   __TIMER__  : Timer index
03781   *                   This parameter can be a combination of the following values:
03782   *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
03783   *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
03784   *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
03785   *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
03786   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
03787   *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
03788   * @retval none
03789
03790   */
03791 #define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\
03792   do {\
03793     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
03794       {\
03795         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
03796       }\
03797     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
03798       {\
03799         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
03800       }\
03801     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
03802       {\
03803         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
03804       }\
03805     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
03806       {\
03807         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
03808       }\
03809     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
03810       {\
03811         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
03812      }\
03813     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
03814       {\
03815         CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
03816       }\
03817   } while(0U)
03818
03819 /** @brief Reset HRTIM handle state
03820   * @param  __HANDLE__ HRTIM handle.
03821   * @retval None
03822   */
03823 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
03824 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                do{                                                       \
03825                                                                     (__HANDLE__)->State             = HAL_HRTIM_STATE_RESET; \
03826                                                                     (__HANDLE__)->MspInitCallback   = NULL;                  \
03827                                                                     (__HANDLE__)->MspDeInitCallback = NULL;                 \
03828                                                                   } while(0)
03829 #else
03830 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
03831 #endif
03832
03833 /** @brief  Enables or disables the timer counter(s)
03834   * @param  __HANDLE__ specifies the HRTIM Handle.
03835   * @param  __TIMERS__ timers to enable/disable
03836   *        This parameter can be any combinations of the following values:
03837   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
03838   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
03839   *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
03840   *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
03841   *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
03842   *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
03843   *            @arg HRTIM_TIMERID_TIMER_F: Timer F identifier
03844   * @retval None
03845   */
03846 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
03847
03848 /* The counter of a timing unit is disabled only if all the timer outputs */
03849 /* are disabled and no capture is configured                              */
03850 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
03851 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
03852 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
03853 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
03854 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
03855 #define HRTIM_TFOEN_MASK (HRTIM_OENR_TF2OEN | HRTIM_OENR_TF1OEN)
03856 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
03857   do {\
03858     if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
03859       {\
03860         ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
03861       }\
03862     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
03863       {\
03864         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
03865           {\
03866             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
03867           }\
03868       }\
03869     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
03870       {\
03871         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
03872           {\
03873             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
03874           }\
03875       }\
03876     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
03877       {\
03878         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
03879           {\
03880             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
03881           }\
03882       }\
03883     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
03884       {\
03885         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
03886           {\
03887             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
03888           }\
03889       }\
03890     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
03891       {\
03892         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
03893           {\
03894             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
03895           }\
03896       }\
03897     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
03898       {\
03899         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\
03900           {\
03901             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\
03902           }\
03903       }\
03904   } while(0U)
03905
03906 /** @brief  Enables the External Event counter
03907   * @param  __HANDLE__ specifies the HRTIM Handle.
03908   * @param  __TIMERS__ timers to enable/disable
03909   *        This parameter can be one of the following values:
03910   *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
03911   *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
03912   *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
03913   *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
03914   *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
03915   *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
03916   * @param  Event external event Counter A or B for which timer event must be enabled
03917   *                    This parameter can be one of the following values:
03918   *                    @arg HRTIM_EVENTCOUNTER_A
03919   *                    @arg HRTIM_EVENTCOUNTER_B
03920   * @retval None
03921   */
03922 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\
03923   do {\
03924     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
03925     {\
03926       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03927         {\
03928               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03929         }\
03930       if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
03931         {\
03932               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03933         }\
03934     }\
03935     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
03936     {\
03937       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03938         {\
03939               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03940         }\
03941       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
03942         {\
03943               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03944         }\
03945     }\
03946     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
03947     {\
03948       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03949         {\
03950               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03951         }\
03952       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
03953         {\
03954               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03955         }\
03956     }\
03957     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
03958     {\
03959       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03960         {\
03961               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03962         }\
03963       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
03964         {\
03965               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03966         }\
03967     }\
03968     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
03969     {\
03970       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03971         {\
03972               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03973         }\
03974       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
03975         {\
03976               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03977         }\
03978     }\
03979     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
03980     {\
03981       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
03982         {\
03983               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
03984         }\
03985       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
03986         {\
03987               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
03988         }\
03989     }\
03990   } while(0U)
03991
03992 /** @brief  Disables the External Event counter
03993   * @param  __HANDLE__ specifies the HRTIM Handle.
03994   * @param  __TIMERS__ timers to enable/disable
03995   *        This parameter can be one of the following values:
03996   *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
03997   *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
03998   *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
03999   *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
04000   *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
04001   *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
04002   * @param  Event external event A or B for which timer event must be disabled
04003   *                    This parameter can be one of the following values:
04004   *                    @arg HRTIM_EVENTCOUNTER_A
04005   *                    @arg HRTIM_EVENTCOUNTER_B
04006   * @retval None
04007   */
04008 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\
04009   do {\
04010     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
04011     {\
04012       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04013         {\
04014               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04015         }\
04016       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04017         {\
04018               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04019         }\
04020     }\
04021     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
04022     {\
04023       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04024         {\
04025               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04026         }\
04027       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04028         {\
04029               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04030         }\
04031     }\
04032     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
04033     {\
04034       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04035         {\
04036               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04037         }\
04038       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04039         {\
04040               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04041         }\
04042     }\
04043     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
04044     {\
04045       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04046         {\
04047               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04048         }\
04049       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04050         {\
04051               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04052         }\
04053     }\
04054     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
04055     {\
04056       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04057         {\
04058               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04059         }\
04060       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04061         {\
04062               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04063         }\
04064     }\
04065     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
04066     {\
04067       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04068         {\
04069               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
04070         }\
04071       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04072         {\
04073               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
04074         }\
04075     }\
04076   } while(0U)
04077
04078 /** @brief  Resets the External Event counter
04079   * @param  __HANDLE__ specifies the HRTIM Handle.
04080   * @param  __TIMERS__ timers to enable/disable
04081   *        This parameter can be one of the following values:
04082   *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
04083   *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
04084   *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
04085   *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
04086   *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
04087   *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
04088   * @param  Event external event A or B for which timer event must be reset
04089   *                    This parameter can be one of the following values:
04090   *                    @arg HRTIM_EVENTCOUNTER_A
04091   *                    @arg HRTIM_EVENTCOUNTER_B
04092   * @retval None
04093   */
04094 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\
04095   do {\
04096     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
04097     {\
04098       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04099         {\
04100               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04101         }\
04102       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04103         {\
04104               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04105         }\
04106     }\
04107     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
04108     {\
04109       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04110         {\
04111               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04112         }\
04113       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04114         {\
04115               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04116         }\
04117     }\
04118     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
04119     {\
04120       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04121         {\
04122               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04123         }\
04124       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04125         {\
04126               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04127         }\
04128     }\
04129     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
04130     {\
04131       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04132         {\
04133               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04134         }\
04135       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04136         {\
04137               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04138         }\
04139     }\
04140     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
04141     {\
04142       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04143         {\
04144               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04145         }\
04146       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04147         {\
04148               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04149         }\
04150     }\
04151     if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
04152     {\
04153       if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
04154         {\
04155               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
04156         }\
04157       if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
04158         {\
04159               ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
04160         }\
04161     }\
04162   } while(0U)
04163
04164
04165 /** @brief  Enables or disables the specified HRTIM common interrupts.
04166   * @param  __HANDLE__ specifies the HRTIM Handle.
04167   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
04168   *        This parameter can be one of the following values:
04169   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
04170   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
04171   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
04172   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
04173   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
04174   *            @arg HRTIM_IT_FLT6: Fault 6 interrupt enable
04175   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
04176   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
04177   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
04178   * @retval None
04179   */
04180 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
04181 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
04182
04183 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
04184   * @param  __HANDLE__ specifies the HRTIM Handle.
04185   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
04186   *        This parameter can be one of the following values:
04187   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
04188   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
04189   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
04190   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
04191   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
04192   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
04193   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
04194   * @retval None
04195   */
04196 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
04197 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
04198
04199 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
04200   * @param  __HANDLE__ specifies the HRTIM Handle.
04201   * @param  __TIMER__ specified the timing unit (Timer A to F)
04202   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
04203   *        This parameter can be one of the following values:
04204   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
04205   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
04206   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
04207   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
04208   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
04209   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
04210   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
04211   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
04212   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
04213   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
04214   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
04215   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
04216   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
04217   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
04218   * @retval None
04219   */
04220 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
04221 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
04222
04223 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
04224   * @param  __HANDLE__ specifies the HRTIM Handle.
04225   * @param  __INTERRUPT__ specifies the interrupt source to check.
04226   *        This parameter can be one of the following values:
04227   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
04228   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
04229   *            @arg HRTIM_IT_FLT3: Fault 3 enable
04230   *            @arg HRTIM_IT_FLT4: Fault 4 enable
04231   *            @arg HRTIM_IT_FLT5: Fault 5 enable
04232   *            @arg HRTIM_IT_FLT6: Fault 6 enable
04233   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
04234   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
04235   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
04236   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
04237   */
04238 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
04239
04240 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
04241   * @param  __HANDLE__ specifies the HRTIM Handle.
04242   * @param  __INTERRUPT__ specifies the interrupt source to check.
04243   *        This parameter can be one of the following values:
04244   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
04245   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
04246   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
04247   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
04248   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
04249   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
04250   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
04251   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
04252   */
04253 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
04254
04255 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
04256   * @param  __HANDLE__ specifies the HRTIM Handle.
04257   * @param  __TIMER__ specified the timing unit (Timer A to F)
04258   * @param  __INTERRUPT__ specifies the interrupt source to check.
04259   *        This parameter can be one of the following values:
04260   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
04261   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
04262   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
04263   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
04264   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
04265   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
04266   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
04267   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
04268   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
04269   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
04270   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
04271   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
04272   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
04273   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
04274   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
04275   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
04276   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
04277   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
04278   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
04279   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
04280   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
04281   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
04282   */
04283 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
04284
04285 /** @brief  Clears the specified HRTIM common pending flag.
04286   * @param  __HANDLE__ specifies the HRTIM Handle.
04287   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
04288   *        This parameter can be one of the following values:
04289   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
04290   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
04291   *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
04292   *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
04293   *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
04294   *            @arg HRTIM_IT_FLT6: Fault 6 clear flag
04295   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
04296   *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
04297   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
04298   * @retval None
04299   */
04300 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
04301
04302 /** @brief  Clears the specified HRTIM Master pending flag.
04303   * @param  __HANDLE__ specifies the HRTIM Handle.
04304   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
04305   *        This parameter can be one of the following values:
04306   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
04307   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
04308   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
04309   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
04310   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
04311   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
04312   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
04313   * @retval None
04314   */
04315 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
04316
04317 /** @brief  Clears the specified HRTIM Timerx pending flag.
04318   * @param  __HANDLE__ specifies the HRTIM Handle.
04319   * @param  __TIMER__ specified the timing unit (Timer A to F)
04320   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
04321   *        This parameter can be one of the following values:
04322   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
04323   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
04324   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
04325   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
04326   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
04327   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
04328   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
04329   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
04330   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
04331   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
04332   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
04333   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
04334   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
04335   *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
04336   * @retval None
04337   */
04338 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
04339
04340 /* DMA HANDLING */
04341 /** @brief  Enables or disables the specified HRTIM Master timer DMA requests.
04342   * @param  __HANDLE__ specifies the HRTIM Handle.
04343   * @param  __DMA__ specifies the DMA request to enable or disable.
04344   *        This parameter can be one of the following values:
04345   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
04346   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
04347   *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
04348   *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
04349   *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
04350   *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
04351   *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
04352   * @retval None
04353   */
04354 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
04355 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
04356
04357 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
04358   * @param  __HANDLE__ specifies the HRTIM Handle.
04359   * @param  __TIMER__ specified the timing unit (Timer A to F)
04360   * @param  __DMA__ specifies the DMA request to enable or disable.
04361   *        This parameter can be one of the following values:
04362   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
04363   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
04364   *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
04365   *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
04366   *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
04367   *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
04368   *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
04369   *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
04370   *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
04371   *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
04372   *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
04373   *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
04374   *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
04375   *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
04376   * @retval None
04377   */
04378 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
04379 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
04380
04381 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
04382 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
04383
04384 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
04385 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
04386
04387 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
04388 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
04389
04390 /** @brief  Sets the HRTIM timer Counter Register value on runtime
04391   * @param  __HANDLE__ HRTIM Handle.
04392   * @param  __TIMER__ HRTIM timer
04393   *                   This parameter can be one of the following values:
04394   *                   @arg 0x6 for master timer
04395   *                   @arg 0x0 to 0x5 for timers A to F
04396   * @param  __COUNTER__ specifies the Counter Register new value.
04397   * @retval None
04398   */
04399 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
04400   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
04401    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
04402
04403 /** @brief  Gets the HRTIM timer Counter Register value on runtime
04404   * @param  __HANDLE__ HRTIM Handle.
04405   * @param  __TIMER__ HRTIM timer
04406   *                   This parameter can be one of the following values:
04407   *                   @arg 0x6 for master timer
04408   *                   @arg 0x0 to 0x5 for timers A to F
04409   * @retval HRTIM timer Counter Register value
04410   */
04411 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
04412   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
04413    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
04414
04415 /** @brief  Sets the HRTIM timer Period value on runtime
04416   * @param  __HANDLE__ HRTIM Handle.
04417   * @param  __TIMER__ HRTIM timer
04418   *                   This parameter can be one of the following values:
04419   *                   @arg 0x6 for master timer
04420   *                   @arg 0x0 to 0x5 for timers A to F
04421   * @param  __PERIOD__ specifies the Period Register new value.
04422   * @retval None
04423   */
04424 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
04425   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
04426    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
04427
04428 /** @brief  Gets the HRTIM timer Period Register value on runtime
04429   * @param  __HANDLE__ HRTIM Handle.
04430   * @param  __TIMER__ HRTIM timer
04431   *                   This parameter can be one of the following values:
04432   *                   @arg 0x6 for master timer
04433   *                   @arg 0x0 to 0x5 for timers A to F
04434   * @retval timer Period Register
04435   */
04436 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
04437   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
04438    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
04439
04440 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
04441   * @param  __HANDLE__ HRTIM Handle.
04442   * @param  __TIMER__ HRTIM timer
04443   *                   This parameter can be one of the following values:
04444   *                   @arg 0x6 for master timer
04445   *                   @arg 0x0 to 0x5 for timers A to F
04446   * @param  __PRESCALER__ specifies the clock prescaler new value.
04447   *                   This parameter can be one of the following values:
04448   *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
04449   *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
04450   *                   @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
04451   *                   @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
04452   *                   @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
04453   *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
04454   *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
04455   *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
04456   * @retval None
04457   */
04458 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
04459   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
04460    (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
04461
04462 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
04463   * @param  __HANDLE__ HRTIM Handle.
04464   * @param  __TIMER__ HRTIM timer
04465   *                   This parameter can be one of the following values:
04466   *                   @arg 0x6 for master timer
04467   *                   @arg 0x0 to 0x5 for timers A to F
04468   * @retval timer clock prescaler value
04469   */
04470 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
04471   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
04472    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
04473
04474 /** @brief  Sets the HRTIM timer Compare Register value on runtime
04475   * @param  __HANDLE__ HRTIM Handle.
04476   * @param  __TIMER__ HRTIM timer
04477   *                   This parameter can be one of the following values:
04478   *                   @arg 0x0 to 0x5 for timers A to F
04479   * @param  __COMPAREUNIT__ timer compare unit
04480   *                   This parameter can be one of the following values:
04481   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
04482   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
04483   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
04484   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
04485   * @param  __COMPARE__ specifies the Compare new value.
04486   * @retval None
04487   */
04488 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
04489       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
04490         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
04491          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
04492          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
04493          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
04494          : \
04495         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
04496          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
04497          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
04498          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
04499
04500 /** @brief  Gets the HRTIM timer Compare Register value on runtime
04501   * @param  __HANDLE__ HRTIM Handle.
04502   * @param  __TIMER__ HRTIM timer
04503   *                   This parameter can be one of the following values:
04504   *                   @arg 0x0 to 0x5 for timers A to F
04505   * @param  __COMPAREUNIT__ timer compare unit
04506   *                   This parameter can be one of the following values:
04507   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
04508   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
04509   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
04510   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
04511   * @retval Compare value
04512   */
04513 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
04514       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
04515         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
04516          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
04517          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
04518          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
04519          : \
04520         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
04521          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
04522          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
04523          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
04524
04525 /**
04526   * @brief  Enables the Fault Counter
04527   * @param  hhrtim pointer to HAL HRTIM handle
04528   * @param  Fault fault input to enable
04529   *                    This parameter can be one of the following values:
04530   *                    @arg HRTIM_FAULT_1: Fault input 1
04531   *                    @arg HRTIM_FAULT_2: Fault input 2
04532   *                    @arg HRTIM_FAULT_3: Fault input 3
04533   *                    @arg HRTIM_FAULT_4: Fault input 4
04534   *                    @arg HRTIM_FAULT_5: Fault input 5
04535   *                    @arg HRTIM_FAULT_6: Fault input 6
04536   * @note This function must be called when fault is not enabled
04537   * @retval HAL status
04538   */
04539 #define __HAL_HRTIM_FAULT_BLANKING_ENABLE(__HANDLE__, __FAULT__)\
04540   do {\
04541     if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
04542     {\
04543               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\
04544     }\
04545     if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
04546     {\
04547               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\
04548     }\
04549     if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
04550     {\
04551               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\
04552     }\
04553     if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
04554     {\
04555               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\
04556     }\
04557     if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
04558     {\
04559               ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\
04560     }\
04561     if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
04562     {\
04563               ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\
04564     }\
04565   } while(0U)
04566
04567 /**
04568   * @brief  Disables the Fault Counter
04569   * @param  hhrtim pointer to HAL HRTIM handle
04570   * @param  Fault fault input to disable
04571   *                    This parameter can be one of the following values:
04572   *                    @arg HRTIM_FAULT_1: Fault input 1
04573   *                    @arg HRTIM_FAULT_2: Fault input 2
04574   *                    @arg HRTIM_FAULT_3: Fault input 3
04575   *                    @arg HRTIM_FAULT_4: Fault input 4
04576   *                    @arg HRTIM_FAULT_5: Fault input 5
04577   *                    @arg HRTIM_FAULT_6: Fault input 6
04578   * @retval HAL status
04579   */
04580 #define __HAL_HRTIM_FAULT_BLANKING_DISABLE(__HANDLE__, __FAULT__)\
04581   do {\
04582     if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
04583     {\
04584               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\
04585     }\
04586     if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
04587     {\
04588               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\
04589     }\
04590     if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
04591     {\
04592               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\
04593     }\
04594     if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
04595     {\
04596               ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\
04597     }\
04598     if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
04599     {\
04600               ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\
04601     }\
04602     if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
04603     {\
04604               ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\
04605     }\
04606   } while(0U)
04607
04608 /**
04609   * @}
04610   */
04611
04612 /* Exported functions --------------------------------------------------------*/
04613 /** @addtogroup HRTIM_Exported_Functions
04614 * @{
04615 */
04616
04617 /** @addtogroup HRTIM_Exported_Functions_Group1
04618 * @{
04619 */
04620
04621 /* Initialization and Configuration functions  ********************************/
04622 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
04623
04624 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
04625
04626 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
04627
04628 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
04629
04630 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
04631                                            uint32_t TimerIdx,
04632                                            const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
04633
04634 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
04635                                                 uint32_t CalibrationRate);
04636
04637 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
04638                                                    uint32_t CalibrationRate);
04639
04640 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
04641                                                   uint32_t Timeout);
04642
04643 /**
04644   * @}
04645   */
04646
04647 /** @addtogroup HRTIM_Exported_Functions_Group2
04648 * @{
04649 */
04650
04651 /* Simple time base related functions  *****************************************/
04652 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
04653                                            uint32_t TimerIdx);
04654
04655 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
04656                                           uint32_t TimerIdx);
04657
04658 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
04659                                               uint32_t TimerIdx);
04660
04661 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
04662                                              uint32_t TimerIdx);
04663
04664 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
04665                                                uint32_t TimerIdx,
04666                                                uint32_t SrcAddr,
04667                                                uint32_t DestAddr,
04668                                                uint32_t Length);
04669
04670 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
04671                                               uint32_t TimerIdx);
04672
04673 /**
04674   * @}
04675   */
04676
04677 /** @addtogroup HRTIM_Exported_Functions_Group3
04678 * @{
04679 */
04680 /* Simple output compare related functions  ************************************/
04681 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
04682                                                  uint32_t TimerIdx,
04683                                                  uint32_t OCChannel,
04684                                                  const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
04685
04686 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
04687                                          uint32_t TimerIdx,
04688                                          uint32_t OCChannel);
04689
04690 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
04691                                         uint32_t TimerIdx,
04692                                         uint32_t OCChannel);
04693
04694 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
04695                                             uint32_t TimerIdx,
04696                                             uint32_t OCChannel);
04697
04698 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
04699                                            uint32_t TimerIdx,
04700                                            uint32_t OCChannel);
04701
04702 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
04703                                              uint32_t TimerIdx,
04704                                              uint32_t OCChannel,
04705                                              uint32_t SrcAddr,
04706                                              uint32_t DestAddr,
04707                                              uint32_t Length);
04708
04709 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
04710                                             uint32_t TimerIdx,
04711                                             uint32_t OCChannel);
04712
04713 /**
04714   * @}
04715   */
04716
04717 /** @addtogroup HRTIM_Exported_Functions_Group4
04718 * @{
04719 */
04720 /* Simple PWM output related functions  ****************************************/
04721 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
04722                                                   uint32_t TimerIdx,
04723                                                   uint32_t PWMChannel,
04724                                                   const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
04725
04726 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
04727                                           uint32_t TimerIdx,
04728                                           uint32_t PWMChannel);
04729
04730 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
04731                                          uint32_t TimerIdx,
04732                                          uint32_t PWMChannel);
04733
04734 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
04735                                              uint32_t TimerIdx,
04736                                              uint32_t PWMChannel);
04737
04738 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
04739                                             uint32_t TimerIdx,
04740                                             uint32_t PWMChannel);
04741
04742 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
04743                                               uint32_t TimerIdx,
04744                                               uint32_t PWMChannel,
04745                                               uint32_t SrcAddr,
04746                                               uint32_t DestAddr,
04747                                               uint32_t Length);
04748
04749 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
04750                                              uint32_t TimerIdx,
04751                                              uint32_t PWMChannel);
04752
04753 /**
04754   * @}
04755   */
04756
04757 /** @addtogroup HRTIM_Exported_Functions_Group5
04758 * @{
04759 */
04760 /* Simple capture related functions  *******************************************/
04761 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
04762                                                       uint32_t TimerIdx,
04763                                                       uint32_t CaptureChannel,
04764                                                       const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
04765
04766 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
04767                                               uint32_t TimerIdx,
04768                                               uint32_t CaptureChannel);
04769
04770 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
04771                                              uint32_t TimerIdx,
04772                                              uint32_t CaptureChannel);
04773
04774 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
04775                                                  uint32_t TimerIdx,
04776                                                  uint32_t CaptureChannel);
04777
04778 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
04779                                                 uint32_t TimerIdx,
04780                                                 uint32_t CaptureChannel);
04781
04782 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
04783                                                   uint32_t TimerIdx,
04784                                                   uint32_t CaptureChannel,
04785                                                   uint32_t SrcAddr,
04786                                                   uint32_t DestAddr,
04787                                                   uint32_t Length);
04788
04789 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
04790                                                  uint32_t TimerIdx,
04791                                                  uint32_t CaptureChannel);
04792
04793 /**
04794   * @}
04795   */
04796
04797 /** @addtogroup HRTIM_Exported_Functions_Group6
04798 * @{
04799 */
04800 /* Simple one pulse related functions  *****************************************/
04801 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
04802                                                        uint32_t TimerIdx,
04803                                                        uint32_t OnePulseChannel,
04804                                                        const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
04805
04806 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
04807                                                uint32_t TimerIdx,
04808                                                uint32_t OnePulseChannel);
04809
04810 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
04811                                               uint32_t TimerIdx,
04812                                              uint32_t OnePulseChannel);
04813
04814 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
04815                                                   uint32_t TimerIdx,
04816                                                   uint32_t OnePulseChannel);
04817
04818 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
04819                                                  uint32_t TimerIdx,
04820                                                  uint32_t OnePulseChannel);
04821
04822 /**
04823   * @}
04824   */
04825
04826 /** @addtogroup HRTIM_Exported_Functions_Group7
04827 * @{
04828 */
04829 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
04830                                             const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
04831
04832 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
04833                                         uint32_t Event,
04834                                         const HRTIM_EventCfgTypeDef* pEventCfg);
04835
04836 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
04837                                                  uint32_t Prescaler);
04838
04839 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
04840                                         uint32_t Fault,
04841                                         const HRTIM_FaultCfgTypeDef* pFaultCfg);
04842
04843 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
04844                                                  uint32_t Prescaler);
04845
04846 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,
04847                                                uint32_t Fault,
04848                                                const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg);
04849
04850 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,
04851                                                uint32_t Fault,
04852                                                const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg);
04853
04854 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,
04855                                               uint32_t Fault);
04856
04857 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,
04858                                            uint32_t Timers);
04859 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
04860                             uint32_t Faults,
04861                             uint32_t Enable);
04862
04863 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
04864                                              uint32_t ADCTrigger,
04865                                              const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
04866
04867 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,
04868                                              uint32_t ADCTrigger,
04869                                              uint32_t Postscaler);
04870
04871 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,
04872                                              uint32_t TimerIdx,
04873                                              uint32_t RollOverCfg);
04874
04875 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,
04876                                           uint32_t Timers);
04877
04878 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,
04879                                           uint32_t Timers);
04880 /**
04881   * @}
04882   */
04883
04884 /** @addtogroup HRTIM_Exported_Functions_Group8
04885 * @{
04886 */
04887 /* Waveform related functions *************************************************/
04888 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
04889                                                 uint32_t TimerIdx,
04890                                                 const HRTIM_TimerCfgTypeDef * pTimerCfg);
04891
04892 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,
04893                                                 uint32_t TimerIdx,
04894                                                 const HRTIM_TimerCtlTypeDef * pTimerCtl);
04895
04896 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,
04897                                                 uint32_t TimerIdx,
04898                                                 const HRTIM_TimerCtlTypeDef * pTimerCtl);
04899
04900 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
04901                                                   uint32_t TimerIdx,
04902                                                   uint32_t CompareUnit,
04903                                                   const HRTIM_CompareCfgTypeDef* pCompareCfg);
04904
04905 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
04906                                                   uint32_t TimerIdx,
04907                                                   uint32_t CaptureUnit,
04908                                                   const HRTIM_CaptureCfgTypeDef* pCaptureCfg);
04909
04910 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
04911                                                  uint32_t TimerIdx,
04912                                                  uint32_t Output,
04913                                                  const HRTIM_OutputCfgTypeDef * pOutputCfg);
04914
04915 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
04916                                                    uint32_t TimerIdx,
04917                                                    uint32_t Output,
04918                                                    uint32_t OutputLevel);
04919
04920 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
04921                                                       uint32_t TimerIdx,
04922                                                       uint32_t Event,
04923                                                       const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
04924
04925 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,
04926                                                      uint32_t TimerIdx,
04927                                                      uint32_t EventCounter,
04928                                                      const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg);
04929
04930 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,
04931                                                       uint32_t TimerIdx,
04932                                                       uint32_t EventCounter);
04933
04934 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,
04935                                                       uint32_t TimerIdx,
04936                                                       uint32_t EventCounter);
04937
04938 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,
04939                                                            uint32_t TimerIdx,
04940                                                            uint32_t EventCounter);
04941
04942 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
04943                                            uint32_t TimerIdx,
04944                                            const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
04945
04946 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
04947                                               uint32_t TimerIdx,
04948                                               const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
04949
04950 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
04951                                            uint32_t TimerIdx,
04952                                            uint32_t RegistersToUpdate);
04953
04954
04955 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
04956                                                  uint32_t Timers);
04957
04958 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
04959                                                  uint32_t Timers);
04960
04961 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
04962                                                  uint32_t Timers);
04963
04964 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
04965                                                  uint32_t Timers);
04966
04967 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
04968                                                      uint32_t Timers);
04969
04970 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
04971                                                     uint32_t Timers);
04972
04973 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
04974                                                 uint32_t OutputsToStart);
04975
04976 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
04977                                                uint32_t OutputsToStop);
04978
04979 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
04980                                          uint32_t Enable);
04981
04982 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
04983
04984 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
04985                                             uint32_t TimerIdx,
04986                                             uint32_t CaptureUnit);
04987
04988 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
04989                                            uint32_t Timers);
04990
04991 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
04992                                           uint32_t Timers);
04993
04994 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
04995                                              uint32_t TimerIdx,
04996                                              uint32_t BurstBufferAddress,
04997                                              uint32_t BurstBufferLength);
04998
04999 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
05000                                           uint32_t Timers);
05001
05002 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
05003                                           uint32_t Timers);
05004
05005 /**
05006   * @}
05007   */
05008
05009 /** @addtogroup HRTIM_Exported_Functions_Group9
05010 * @{
05011 */
05012 /* HRTIM peripheral state functions */
05013 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim);
05014
05015 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
05016                                     uint32_t TimerIdx,
05017                                     uint32_t CaptureUnit);
05018
05019 uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim,
05020                                     uint32_t TimerIdx,
05021                                     uint32_t CaptureUnit);
05022
05023 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim,
05024                                     uint32_t TimerIdx,
05025                                     uint32_t CaptureUnit);
05026
05027 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
05028                                           uint32_t TimerIdx,
05029                                           uint32_t Output);
05030
05031 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
05032                                           uint32_t TimerIdx,
05033                                           uint32_t Output);
05034
05035 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
05036                                               uint32_t TimerIdx,
05037                                               uint32_t Output);
05038
05039 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim);
05040
05041 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
05042                                             uint32_t TimerIdx);
05043
05044 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
05045                                          uint32_t TimerIdx);
05046
05047 /**
05048   * @}
05049   */
05050
05051 /** @addtogroup HRTIM_Exported_Functions_Group10
05052 * @{
05053 */
05054 /* IRQ handler */
05055 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
05056                           uint32_t TimerIdx);
05057
05058 /* HRTIM events related callback functions */
05059 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
05060 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
05061 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
05062 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
05063 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
05064 void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim);
05065 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
05066 void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
05067 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
05068 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
05069
05070 /* Timer events related callback functions */
05071 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
05072                                               uint32_t TimerIdx);
05073 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
05074                                               uint32_t TimerIdx);
05075 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
05076                                             uint32_t TimerIdx);
05077 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
05078                                             uint32_t TimerIdx);
05079 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
05080                                             uint32_t TimerIdx);
05081 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
05082                                             uint32_t TimerIdx);
05083 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
05084                                             uint32_t TimerIdx);
05085 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
05086                                             uint32_t TimerIdx);
05087 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
05088                                                 uint32_t TimerIdx);
05089 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
05090                                            uint32_t TimerIdx);
05091 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
05092                                          uint32_t TimerIdx);
05093 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
05094                                            uint32_t TimerIdx);
05095 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
05096                                          uint32_t TimerIdx);
05097 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
05098                                            uint32_t TimerIdx);
05099 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
05100                                                uint32_t TimerIdx);
05101 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
05102
05103 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
05104 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
05105                                              HAL_HRTIM_CallbackIDTypeDef CallbackID,
05106                                              pHRTIM_CallbackTypeDef      pCallback);
05107
05108 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
05109                                                HAL_HRTIM_CallbackIDTypeDef CallbackID);
05110
05111 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *        hhrtim,
05112                                                  HAL_HRTIM_CallbackIDTypeDef  CallbackID,
05113                                                  pHRTIM_TIMxCallbackTypeDef   pCallback);
05114
05115 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
05116                                                    HAL_HRTIM_CallbackIDTypeDef CallbackID);
05117 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
05118
05119 /**
05120   * @}
05121   */
05122
05123 /**
05124   * @}
05125   */
05126
05127 /**
05128   * @}
05129   */
05130
05131 /**
05132   * @}
05133   */
05134
05135 #endif /* HRTIM1 */
05136
05137 #ifdef __cplusplus
05138 }
05139 #endif
05140
05141 #endif /* STM32G4xx_HAL_HRTIM_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_i2c.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027     [..]
00028     The I2C HAL driver can be used as follows:
00029
00030     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00031         I2C_HandleTypeDef  hi2c;
00032
00033     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00034         (##) Enable the I2Cx interface clock
00035         (##) I2C pins configuration
00036             (+++) Enable the clock for the I2C GPIOs
00037             (+++) Configure I2C pins as alternate function open-drain
00038         (##) NVIC configuration if you need to use interrupt process
00039             (+++) Configure the I2Cx interrupt priority
00040             (+++) Enable the NVIC I2C IRQ Channel
00041         (##) DMA Configuration if you need to use DMA process
00042             (+++) Declare a DMA_HandleTypeDef handle structure for
00043                   the transmit or receive channel
00044             (+++) Enable the DMAx interface clock using
00045             (+++) Configure the DMA handle parameters
00046             (+++) Configure the DMA Tx or Rx channel
00047             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00048             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00049                   the DMA Tx or Rx channel
00050
00051     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00052         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00053
00054     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00055         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00056
00057     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00058
00059     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00060
00061     *** Polling mode IO operation ***
00062     =================================
00063     [..]
00064       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00065       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00066       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00067       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00068
00069     *** Polling mode IO MEM operation ***
00070     =====================================
00071     [..]
00072       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00073       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00074
00075
00076     *** Interrupt mode IO operation ***
00077     ===================================
00078     [..]
00079       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00080       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
00081            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00082       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00083       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00084            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00085       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00086       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
00087            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00088       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00089       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00090            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00091       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00092            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00093       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00094       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00095            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00096       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00097            This action will inform Master to generate a Stop condition to discard the communication.
00098
00099
00100     *** Interrupt mode or DMA mode IO sequential operation ***
00101     ==========================================================
00102     [..]
00103       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00104           when a direction change during transfer
00105     [..]
00106       (+) A specific option field manage the different steps of a sequential transfer
00107       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
00108       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
00109            no sequential mode
00110       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00111                             and data to transfer without a final stop condition
00112       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
00113                             start condition, address and data to transfer without a final stop condition,
00114                             an then permit a call the same master sequential interface several times
00115                             (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
00116                             or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
00117       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00118                             and with new data to transfer if the direction change or manage only the new data to
00119                             transfer
00120                             if no direction change and without a final stop condition in both cases
00121       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00122                             and with new data to transfer if the direction change or manage only the new data to
00123                             transfer
00124                             if no direction change and with a final stop condition in both cases
00125       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
00126                             after several call of the same master sequential interface several times
00127                             (link with option I2C_FIRST_AND_NEXT_FRAME).
00128                             Usage can, transfer several bytes one by one using
00129                               HAL_I2C_Master_Seq_Transmit_IT
00130                               or HAL_I2C_Master_Seq_Receive_IT
00131                               or HAL_I2C_Master_Seq_Transmit_DMA
00132                               or HAL_I2C_Master_Seq_Receive_DMA
00133                               with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
00134                              Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
00135                               Receive sequence permit to call the opposite interface Receive or Transmit
00136                               without stopping the communication and so generate a restart condition.
00137       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
00138                             each call of the same master sequential
00139                             interface.
00140                             Usage can, transfer several bytes one by one with a restart with slave address between
00141                             each bytes using
00142                               HAL_I2C_Master_Seq_Transmit_IT
00143                               or HAL_I2C_Master_Seq_Receive_IT
00144                               or HAL_I2C_Master_Seq_Transmit_DMA
00145                               or HAL_I2C_Master_Seq_Receive_DMA
00146                               with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
00147                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
00148                             generation of STOP condition.
00149
00150       (+) Different sequential I2C interfaces are listed below:
00151       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
00152             HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
00153       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
00154             users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00155       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
00156             HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
00157       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00158            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00159       (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00160       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00161            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00162       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
00163             HAL_I2C_DisableListen_IT()
00164       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
00165            add their own code to check the Address Match Code and the transmission direction request by master
00166            (Write/Read).
00167       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
00168           add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00169       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
00170             HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
00171       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
00172             users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00173       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
00174             HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
00175       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00176            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00177       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00178            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00179       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00180            This action will inform Master to generate a Stop condition to discard the communication.
00181
00182     *** Interrupt mode IO MEM operation ***
00183     =======================================
00184     [..]
00185       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00186           HAL_I2C_Mem_Write_IT()
00187       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
00188            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00189       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00190           HAL_I2C_Mem_Read_IT()
00191       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
00192            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00193       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00194            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00195
00196     *** DMA mode IO operation ***
00197     ==============================
00198     [..]
00199       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00200           HAL_I2C_Master_Transmit_DMA()
00201       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
00202            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00203       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00204           HAL_I2C_Master_Receive_DMA()
00205       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00206            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00207       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00208           HAL_I2C_Slave_Transmit_DMA()
00209       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
00210            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00211       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00212           HAL_I2C_Slave_Receive_DMA()
00213       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00214            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00215       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00216            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00217       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00218       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00219            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00220       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00221            This action will inform Master to generate a Stop condition to discard the communication.
00222
00223     *** DMA mode IO MEM operation ***
00224     =================================
00225     [..]
00226       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00227           HAL_I2C_Mem_Write_DMA()
00228       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
00229            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00230       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00231           HAL_I2C_Mem_Read_DMA()
00232       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
00233            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00234       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00235            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00236
00237
00238      *** I2C HAL driver macros list ***
00239      ==================================
00240      [..]
00241        Below the list of most used macros in I2C HAL driver.
00242
00243       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00244       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00245       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00246       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00247       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00248       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00249       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00250
00251      *** Callback registration ***
00252      =============================================
00253     [..]
00254      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
00255      allows the user to configure dynamically the driver callbacks.
00256      Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
00257      to register an interrupt callback.
00258     [..]
00259      Function HAL_I2C_RegisterCallback() allows to register following callbacks:
00260        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00261        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00262        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00263        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00264        (+) ListenCpltCallback   : callback for end of listen mode.
00265        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00266        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00267        (+) ErrorCallback        : callback for error detection.
00268        (+) AbortCpltCallback    : callback for abort completion process.
00269        (+) MspInitCallback      : callback for Msp Init.
00270        (+) MspDeInitCallback    : callback for Msp DeInit.
00271      This function takes as parameters the HAL peripheral handle, the Callback ID
00272      and a pointer to the user callback function.
00273     [..]
00274      For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
00275     [..]
00276      Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
00277      weak function.
00278      HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
00279      and the Callback ID.
00280      This function allows to reset following callbacks:
00281        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00282        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00283        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00284        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00285        (+) ListenCpltCallback   : callback for end of listen mode.
00286        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00287        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00288        (+) ErrorCallback        : callback for error detection.
00289        (+) AbortCpltCallback    : callback for abort completion process.
00290        (+) MspInitCallback      : callback for Msp Init.
00291        (+) MspDeInitCallback    : callback for Msp DeInit.
00292     [..]
00293      For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
00294     [..]
00295      By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
00296      all callbacks are set to the corresponding weak functions:
00297      examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
00298      Exception done for MspInit and MspDeInit functions that are
00299      reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
00300      these callbacks are null (not registered beforehand).
00301      If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
00302      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00303     [..]
00304      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
00305      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00306      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
00307      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00308      Then, the user first registers the MspInit/MspDeInit user callbacks
00309      using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
00310      or HAL_I2C_Init() function.
00311     [..]
00312      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
00313      not defined, the callback registration feature is not available and all callbacks
00314      are set to the corresponding weak functions.
00315
00316      [..]
00317        (@) You can refer to the I2C HAL driver header file for more useful macros
00318
00319   @endverbatim
00320   */
00321
00322 /* Includes ------------------------------------------------------------------*/
00323 #include "stm32g4xx_hal.h"
00324
00325 /** @addtogroup STM32G4xx_HAL_Driver
00326   * @{
00327   */
00328
00329 /** @defgroup I2C I2C
00330   * @brief I2C HAL module driver
00331   * @{
00332   */
00333
00334 #ifdef HAL_I2C_MODULE_ENABLED
00335
00336 /* Private typedef -----------------------------------------------------------*/
00337 /* Private define ------------------------------------------------------------*/
00338
00339 /** @defgroup I2C_Private_Define I2C Private Define
00340   * @{
00341   */
00342 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00343 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00344 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00345 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00346 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00347 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00348 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00349 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00350 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00351 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00352
00353 #define MAX_NBYTE_SIZE      255U
00354 #define SLAVE_ADDR_SHIFT     7U
00355 #define SLAVE_ADDR_MSK       0x06U
00356
00357 /* Private define for @ref PreviousState usage */
00358 #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
00359                                                          (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
00360                                               (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
00361 /*!< Mask State define, keep only RX and TX bits */
00362 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
00363 /*!< Default Value */
00364 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00365                                               (uint32_t)HAL_I2C_MODE_MASTER))
00366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00367 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00368                                               (uint32_t)HAL_I2C_MODE_MASTER))
00369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00370 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00371                                               (uint32_t)HAL_I2C_MODE_SLAVE))
00372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
00373 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00374                                               (uint32_t)HAL_I2C_MODE_SLAVE))
00375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00376 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00377                                               (uint32_t)HAL_I2C_MODE_MEM))
00378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00379 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00380                                               (uint32_t)HAL_I2C_MODE_MEM))
00381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00382
00383
00384 /* Private define to centralize the enable/disable of Interrupts */
00385 #define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
00386                                                          @ref I2C_XFER_LISTEN_IT */
00387 #define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
00388                                                          @ref I2C_XFER_LISTEN_IT */
00389 #define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
00390                                                          and @ref I2C_XFER_RX_IT */
00391
00392 #define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
00393                                                          and NACK treatment */
00394 #define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
00395 #define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
00396
00397 /* Private define Sequential Transfer Options default/reset value */
00398 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
00399 /**
00400   * @}
00401   */
00402
00403 /* Private macros ------------------------------------------------------------*/
00404 /** @addtogroup I2C_Private_Macro
00405   * @{
00406   */
00407 /* Macro to get remaining data to transfer on DMA side */
00408 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
00409 /**
00410   * @}
00411   */
00412
00413 /* Private variables ---------------------------------------------------------*/
00414 /* Private function prototypes -----------------------------------------------*/
00415
00416 /** @defgroup I2C_Private_Functions I2C Private Functions
00417   * @{
00418   */
00419 /* Private functions to handle DMA transfer */
00420 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00421 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00422 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00423 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00424 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00425 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00426
00427
00428 /* Private functions to handle IT transfer */
00429 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00430 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
00431 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
00432 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00433 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00434 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00435 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00436
00437 /* Private functions to handle IT transfer */
00438 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
00439                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
00440                                                 uint32_t Tickstart);
00441 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
00442                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
00443                                                uint32_t Tickstart);
00444
00445 /* Private functions for I2C transfer IRQ handler */
00446 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00447                                            uint32_t ITSources);
00448 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00449                                         uint32_t ITSources);
00450 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00451                                           uint32_t ITSources);
00452 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00453                                             uint32_t ITSources);
00454 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00455                                          uint32_t ITSources);
00456 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00457                                            uint32_t ITSources);
00458
00459 /* Private functions to handle flags during polling transfer */
00460 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
00461                                                     uint32_t Timeout, uint32_t Tickstart);
00462 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00463                                                         uint32_t Tickstart);
00464 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00465                                                         uint32_t Tickstart);
00466 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00467                                                         uint32_t Tickstart);
00468 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00469                                              uint32_t Tickstart);
00470
00471 /* Private functions to centralize the enable/disable of Interrupts */
00472 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00473 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00474
00475 /* Private function to treat different error callback */
00476 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
00477
00478 /* Private function to flush TXDR register */
00479 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00480
00481 /* Private function to handle  start, restart or stop a transfer */
00482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
00483                                uint32_t Request);
00484
00485 /* Private function to Convert Specific options */
00486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
00487 /**
00488   * @}
00489   */
00490
00491 /* Exported functions --------------------------------------------------------*/
00492
00493 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00494   * @{
00495   */
00496
00497 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00498   *  @brief    Initialization and Configuration functions
00499   *
00500 @verbatim
00501  ===============================================================================
00502               ##### Initialization and de-initialization functions #####
00503  ===============================================================================
00504     [..]  This subsection provides a set of functions allowing to initialize and
00505           deinitialize the I2Cx peripheral:
00506
00507       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00508           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00509
00510       (+) Call the function HAL_I2C_Init() to configure the selected device with
00511           the selected configuration:
00512         (++) Clock Timing
00513         (++) Own Address 1
00514         (++) Addressing mode (Master, Slave)
00515         (++) Dual Addressing mode
00516         (++) Own Address 2
00517         (++) Own Address 2 Mask
00518         (++) General call mode
00519         (++) Nostretch mode
00520
00521       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00522           of the selected I2Cx peripheral.
00523
00524 @endverbatim
00525   * @{
00526   */
00527
00528 /**
00529   * @brief  Initializes the I2C according to the specified parameters
00530   *         in the I2C_InitTypeDef and initialize the associated handle.
00531   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00532   *                the configuration information for the specified I2C.
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00536 {
00537   /* Check the I2C handle allocation */
00538   if (hi2c == NULL)
00539   {
00540     return HAL_ERROR;
00541   }
00542
00543   /* Check the parameters */
00544   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00545   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00546   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00547   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00548   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00549   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00550   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00551   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00552
00553   if (hi2c->State == HAL_I2C_STATE_RESET)
00554   {
00555     /* Allocate lock resource and initialize it */
00556     hi2c->Lock = HAL_UNLOCKED;
00557
00558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00559     /* Init the I2C Callback settings */
00560     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00561     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00562     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00563     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00564     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00565     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
00566     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
00567     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
00568     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00569     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
00570
00571     if (hi2c->MspInitCallback == NULL)
00572     {
00573       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
00574     }
00575
00576     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00577     hi2c->MspInitCallback(hi2c);
00578 #else
00579     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00580     HAL_I2C_MspInit(hi2c);
00581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00582   }
00583
00584   hi2c->State = HAL_I2C_STATE_BUSY;
00585
00586   /* Disable the selected I2C peripheral */
00587   __HAL_I2C_DISABLE(hi2c);
00588
00589   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00590   /* Configure I2Cx: Frequency range */
00591   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00592
00593   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00594   /* Disable Own Address1 before set the Own Address1 configuration */
00595   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00596
00597   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00598   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00599   {
00600     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00601   }
00602   else /* I2C_ADDRESSINGMODE_10BIT */
00603   {
00604     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00605   }
00606
00607   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00608   /* Configure I2Cx: Addressing Master mode */
00609   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00610   {
00611     SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
00612   }
00613   else
00614   {
00615     /* Clear the I2C ADD10 bit */
00616     CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
00617   }
00618   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00619   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00620
00621   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00622   /* Disable Own Address2 before set the Own Address2 configuration */
00623   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00624
00625   /* Configure I2Cx: Dual mode and Own Address2 */
00626   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
00627                           (hi2c->Init.OwnAddress2Masks << 8));
00628
00629   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00630   /* Configure I2Cx: Generalcall and NoStretch mode */
00631   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00632
00633   /* Enable the selected I2C peripheral */
00634   __HAL_I2C_ENABLE(hi2c);
00635
00636   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00637   hi2c->State = HAL_I2C_STATE_READY;
00638   hi2c->PreviousState = I2C_STATE_NONE;
00639   hi2c->Mode = HAL_I2C_MODE_NONE;
00640
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @brief  DeInitialize the I2C peripheral.
00646   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00647   *                the configuration information for the specified I2C.
00648   * @retval HAL status
00649   */
00650 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00651 {
00652   /* Check the I2C handle allocation */
00653   if (hi2c == NULL)
00654   {
00655     return HAL_ERROR;
00656   }
00657
00658   /* Check the parameters */
00659   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00660
00661   hi2c->State = HAL_I2C_STATE_BUSY;
00662
00663   /* Disable the I2C Peripheral Clock */
00664   __HAL_I2C_DISABLE(hi2c);
00665
00666 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00667   if (hi2c->MspDeInitCallback == NULL)
00668   {
00669     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
00670   }
00671
00672   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00673   hi2c->MspDeInitCallback(hi2c);
00674 #else
00675   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00676   HAL_I2C_MspDeInit(hi2c);
00677 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00678
00679   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00680   hi2c->State = HAL_I2C_STATE_RESET;
00681   hi2c->PreviousState = I2C_STATE_NONE;
00682   hi2c->Mode = HAL_I2C_MODE_NONE;
00683
00684   /* Release Lock */
00685   __HAL_UNLOCK(hi2c);
00686
00687   return HAL_OK;
00688 }
00689
00690 /**
00691   * @brief Initialize the I2C MSP.
00692   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00693   *                the configuration information for the specified I2C.
00694   * @retval None
00695   */
00696 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00697 {
00698   /* Prevent unused argument(s) compilation warning */
00699   UNUSED(hi2c);
00700
00701   /* NOTE : This function should not be modified, when the callback is needed,
00702             the HAL_I2C_MspInit could be implemented in the user file
00703    */
00704 }
00705
00706 /**
00707   * @brief DeInitialize the I2C MSP.
00708   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00709   *                the configuration information for the specified I2C.
00710   * @retval None
00711   */
00712 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00713 {
00714   /* Prevent unused argument(s) compilation warning */
00715   UNUSED(hi2c);
00716
00717   /* NOTE : This function should not be modified, when the callback is needed,
00718             the HAL_I2C_MspDeInit could be implemented in the user file
00719    */
00720 }
00721
00722 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00723 /**
00724   * @brief  Register a User I2C Callback
00725   *         To be used instead of the weak predefined callback
00726   * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
00727   *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
00728   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00729   *                the configuration information for the specified I2C.
00730   * @param  CallbackID ID of the callback to be registered
00731   *         This parameter can be one of the following values:
00732   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00733   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00734   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00735   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00736   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00737   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00738   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00739   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00740   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00741   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00742   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00743   * @param  pCallback pointer to the Callback function
00744   * @retval HAL status
00745   */
00746 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
00747                                            pI2C_CallbackTypeDef pCallback)
00748 {
00749   HAL_StatusTypeDef status = HAL_OK;
00750
00751   if (pCallback == NULL)
00752   {
00753     /* Update the error code */
00754     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00755
00756     return HAL_ERROR;
00757   }
00758
00759   if (HAL_I2C_STATE_READY == hi2c->State)
00760   {
00761     switch (CallbackID)
00762     {
00763       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00764         hi2c->MasterTxCpltCallback = pCallback;
00765         break;
00766
00767       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00768         hi2c->MasterRxCpltCallback = pCallback;
00769         break;
00770
00771       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00772         hi2c->SlaveTxCpltCallback = pCallback;
00773         break;
00774
00775       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00776         hi2c->SlaveRxCpltCallback = pCallback;
00777         break;
00778
00779       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00780         hi2c->ListenCpltCallback = pCallback;
00781         break;
00782
00783       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00784         hi2c->MemTxCpltCallback = pCallback;
00785         break;
00786
00787       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00788         hi2c->MemRxCpltCallback = pCallback;
00789         break;
00790
00791       case HAL_I2C_ERROR_CB_ID :
00792         hi2c->ErrorCallback = pCallback;
00793         break;
00794
00795       case HAL_I2C_ABORT_CB_ID :
00796         hi2c->AbortCpltCallback = pCallback;
00797         break;
00798
00799       case HAL_I2C_MSPINIT_CB_ID :
00800         hi2c->MspInitCallback = pCallback;
00801         break;
00802
00803       case HAL_I2C_MSPDEINIT_CB_ID :
00804         hi2c->MspDeInitCallback = pCallback;
00805         break;
00806
00807       default :
00808         /* Update the error code */
00809         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00810
00811         /* Return error status */
00812         status =  HAL_ERROR;
00813         break;
00814     }
00815   }
00816   else if (HAL_I2C_STATE_RESET == hi2c->State)
00817   {
00818     switch (CallbackID)
00819     {
00820       case HAL_I2C_MSPINIT_CB_ID :
00821         hi2c->MspInitCallback = pCallback;
00822         break;
00823
00824       case HAL_I2C_MSPDEINIT_CB_ID :
00825         hi2c->MspDeInitCallback = pCallback;
00826         break;
00827
00828       default :
00829         /* Update the error code */
00830         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00831
00832         /* Return error status */
00833         status =  HAL_ERROR;
00834         break;
00835     }
00836   }
00837   else
00838   {
00839     /* Update the error code */
00840     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00841
00842     /* Return error status */
00843     status =  HAL_ERROR;
00844   }
00845
00846   return status;
00847 }
00848
00849 /**
00850   * @brief  Unregister an I2C Callback
00851   *         I2C callback is redirected to the weak predefined callback
00852   * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
00853   *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
00854   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00855   *                the configuration information for the specified I2C.
00856   * @param  CallbackID ID of the callback to be unregistered
00857   *         This parameter can be one of the following values:
00858   *         This parameter can be one of the following values:
00859   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00860   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00861   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00862   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00863   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00864   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00865   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00866   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00867   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00868   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00869   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00870   * @retval HAL status
00871   */
00872 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
00873 {
00874   HAL_StatusTypeDef status = HAL_OK;
00875
00876   if (HAL_I2C_STATE_READY == hi2c->State)
00877   {
00878     switch (CallbackID)
00879     {
00880       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00881         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00882         break;
00883
00884       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00885         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00886         break;
00887
00888       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00889         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00890         break;
00891
00892       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00893         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00894         break;
00895
00896       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00897         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00898         break;
00899
00900       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00901         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
00902         break;
00903
00904       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00905         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
00906         break;
00907
00908       case HAL_I2C_ERROR_CB_ID :
00909         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
00910         break;
00911
00912       case HAL_I2C_ABORT_CB_ID :
00913         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00914         break;
00915
00916       case HAL_I2C_MSPINIT_CB_ID :
00917         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00918         break;
00919
00920       case HAL_I2C_MSPDEINIT_CB_ID :
00921         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00922         break;
00923
00924       default :
00925         /* Update the error code */
00926         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00927
00928         /* Return error status */
00929         status =  HAL_ERROR;
00930         break;
00931     }
00932   }
00933   else if (HAL_I2C_STATE_RESET == hi2c->State)
00934   {
00935     switch (CallbackID)
00936     {
00937       case HAL_I2C_MSPINIT_CB_ID :
00938         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00939         break;
00940
00941       case HAL_I2C_MSPDEINIT_CB_ID :
00942         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00943         break;
00944
00945       default :
00946         /* Update the error code */
00947         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00948
00949         /* Return error status */
00950         status =  HAL_ERROR;
00951         break;
00952     }
00953   }
00954   else
00955   {
00956     /* Update the error code */
00957     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00958
00959     /* Return error status */
00960     status =  HAL_ERROR;
00961   }
00962
00963   return status;
00964 }
00965
00966 /**
00967   * @brief  Register the Slave Address Match I2C Callback
00968   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
00969   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00970   *                the configuration information for the specified I2C.
00971   * @param  pCallback pointer to the Address Match Callback function
00972   * @retval HAL status
00973   */
00974 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
00975 {
00976   HAL_StatusTypeDef status = HAL_OK;
00977
00978   if (pCallback == NULL)
00979   {
00980     /* Update the error code */
00981     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00982
00983     return HAL_ERROR;
00984   }
00985
00986   if (HAL_I2C_STATE_READY == hi2c->State)
00987   {
00988     hi2c->AddrCallback = pCallback;
00989   }
00990   else
00991   {
00992     /* Update the error code */
00993     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00994
00995     /* Return error status */
00996     status =  HAL_ERROR;
00997   }
00998
00999   return status;
01000 }
01001
01002 /**
01003   * @brief  UnRegister the Slave Address Match I2C Callback
01004   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
01005   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01006   *                the configuration information for the specified I2C.
01007   * @retval HAL status
01008   */
01009 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
01010 {
01011   HAL_StatusTypeDef status = HAL_OK;
01012
01013   if (HAL_I2C_STATE_READY == hi2c->State)
01014   {
01015     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
01016   }
01017   else
01018   {
01019     /* Update the error code */
01020     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
01021
01022     /* Return error status */
01023     status =  HAL_ERROR;
01024   }
01025
01026   return status;
01027 }
01028
01029 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
01030
01031 /**
01032   * @}
01033   */
01034
01035 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
01036   *  @brief   Data transfers functions
01037   *
01038 @verbatim
01039  ===============================================================================
01040                       ##### IO operation functions #####
01041  ===============================================================================
01042     [..]
01043     This subsection provides a set of functions allowing to manage the I2C data
01044     transfers.
01045
01046     (#) There are two modes of transfer:
01047        (++) Blocking mode : The communication is performed in the polling mode.
01048             The status of all data processing is returned by the same function
01049             after finishing transfer.
01050        (++) No-Blocking mode : The communication is performed using Interrupts
01051             or DMA. These functions return the status of the transfer startup.
01052             The end of the data processing will be indicated through the
01053             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
01054             using DMA mode.
01055
01056     (#) Blocking mode functions are :
01057         (++) HAL_I2C_Master_Transmit()
01058         (++) HAL_I2C_Master_Receive()
01059         (++) HAL_I2C_Slave_Transmit()
01060         (++) HAL_I2C_Slave_Receive()
01061         (++) HAL_I2C_Mem_Write()
01062         (++) HAL_I2C_Mem_Read()
01063         (++) HAL_I2C_IsDeviceReady()
01064
01065     (#) No-Blocking mode functions with Interrupt are :
01066         (++) HAL_I2C_Master_Transmit_IT()
01067         (++) HAL_I2C_Master_Receive_IT()
01068         (++) HAL_I2C_Slave_Transmit_IT()
01069         (++) HAL_I2C_Slave_Receive_IT()
01070         (++) HAL_I2C_Mem_Write_IT()
01071         (++) HAL_I2C_Mem_Read_IT()
01072         (++) HAL_I2C_Master_Seq_Transmit_IT()
01073         (++) HAL_I2C_Master_Seq_Receive_IT()
01074         (++) HAL_I2C_Slave_Seq_Transmit_IT()
01075         (++) HAL_I2C_Slave_Seq_Receive_IT()
01076         (++) HAL_I2C_EnableListen_IT()
01077         (++) HAL_I2C_DisableListen_IT()
01078         (++) HAL_I2C_Master_Abort_IT()
01079
01080     (#) No-Blocking mode functions with DMA are :
01081         (++) HAL_I2C_Master_Transmit_DMA()
01082         (++) HAL_I2C_Master_Receive_DMA()
01083         (++) HAL_I2C_Slave_Transmit_DMA()
01084         (++) HAL_I2C_Slave_Receive_DMA()
01085         (++) HAL_I2C_Mem_Write_DMA()
01086         (++) HAL_I2C_Mem_Read_DMA()
01087         (++) HAL_I2C_Master_Seq_Transmit_DMA()
01088         (++) HAL_I2C_Master_Seq_Receive_DMA()
01089         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
01090         (++) HAL_I2C_Slave_Seq_Receive_DMA()
01091
01092     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
01093         (++) HAL_I2C_MasterTxCpltCallback()
01094         (++) HAL_I2C_MasterRxCpltCallback()
01095         (++) HAL_I2C_SlaveTxCpltCallback()
01096         (++) HAL_I2C_SlaveRxCpltCallback()
01097         (++) HAL_I2C_MemTxCpltCallback()
01098         (++) HAL_I2C_MemRxCpltCallback()
01099         (++) HAL_I2C_AddrCallback()
01100         (++) HAL_I2C_ListenCpltCallback()
01101         (++) HAL_I2C_ErrorCallback()
01102         (++) HAL_I2C_AbortCpltCallback()
01103
01104 @endverbatim
01105   * @{
01106   */
01107
01108 /**
01109   * @brief  Transmits in master mode an amount of data in blocking mode.
01110   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01111   *                the configuration information for the specified I2C.
01112   * @param  DevAddress Target device address: The device 7 bits address value
01113   *         in datasheet must be shifted to the left before calling the interface
01114   * @param  pData Pointer to data buffer
01115   * @param  Size Amount of data to be sent
01116   * @param  Timeout Timeout duration
01117   * @retval HAL status
01118   */
01119 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01120                                           uint16_t Size, uint32_t Timeout)
01121 {
01122   uint32_t tickstart;
01123   uint32_t xfermode;
01124
01125   if (hi2c->State == HAL_I2C_STATE_READY)
01126   {
01127     /* Process Locked */
01128     __HAL_LOCK(hi2c);
01129
01130     /* Init tickstart for timeout management*/
01131     tickstart = HAL_GetTick();
01132
01133     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01134     {
01135       return HAL_ERROR;
01136     }
01137
01138     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01139     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01140     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01141
01142     /* Prepare transfer parameters */
01143     hi2c->pBuffPtr  = pData;
01144     hi2c->XferCount = Size;
01145     hi2c->XferISR   = NULL;
01146
01147     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01148     {
01149       hi2c->XferSize = MAX_NBYTE_SIZE;
01150       xfermode = I2C_RELOAD_MODE;
01151     }
01152     else
01153     {
01154       hi2c->XferSize = hi2c->XferCount;
01155       xfermode = I2C_AUTOEND_MODE;
01156     }
01157
01158     if (hi2c->XferSize > 0U)
01159     {
01160       /* Preload TX register */
01161       /* Write data to TXDR */
01162       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01163
01164       /* Increment Buffer pointer */
01165       hi2c->pBuffPtr++;
01166
01167       hi2c->XferCount--;
01168       hi2c->XferSize--;
01169
01170       /* Send Slave Address */
01171       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01172       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
01173                          I2C_GENERATE_START_WRITE);
01174     }
01175     else
01176     {
01177       /* Send Slave Address */
01178       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01179       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
01180                          I2C_GENERATE_START_WRITE);
01181     }
01182
01183     while (hi2c->XferCount > 0U)
01184     {
01185       /* Wait until TXIS flag is set */
01186       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01187       {
01188         return HAL_ERROR;
01189       }
01190       /* Write data to TXDR */
01191       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01192
01193       /* Increment Buffer pointer */
01194       hi2c->pBuffPtr++;
01195
01196       hi2c->XferCount--;
01197       hi2c->XferSize--;
01198
01199       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01200       {
01201         /* Wait until TCR flag is set */
01202         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01203         {
01204           return HAL_ERROR;
01205         }
01206
01207         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01208         {
01209           hi2c->XferSize = MAX_NBYTE_SIZE;
01210           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01211                              I2C_NO_STARTSTOP);
01212         }
01213         else
01214         {
01215           hi2c->XferSize = hi2c->XferCount;
01216           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01217                              I2C_NO_STARTSTOP);
01218         }
01219       }
01220     }
01221
01222     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01223     /* Wait until STOPF flag is set */
01224     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01225     {
01226       return HAL_ERROR;
01227     }
01228
01229     /* Clear STOP Flag */
01230     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01231
01232     /* Clear Configuration Register 2 */
01233     I2C_RESET_CR2(hi2c);
01234
01235     hi2c->State = HAL_I2C_STATE_READY;
01236     hi2c->Mode  = HAL_I2C_MODE_NONE;
01237
01238     /* Process Unlocked */
01239     __HAL_UNLOCK(hi2c);
01240
01241     return HAL_OK;
01242   }
01243   else
01244   {
01245     return HAL_BUSY;
01246   }
01247 }
01248
01249 /**
01250   * @brief  Receives in master mode an amount of data in blocking mode.
01251   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01252   *                the configuration information for the specified I2C.
01253   * @param  DevAddress Target device address: The device 7 bits address value
01254   *         in datasheet must be shifted to the left before calling the interface
01255   * @param  pData Pointer to data buffer
01256   * @param  Size Amount of data to be sent
01257   * @param  Timeout Timeout duration
01258   * @retval HAL status
01259   */
01260 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01261                                          uint16_t Size, uint32_t Timeout)
01262 {
01263   uint32_t tickstart;
01264
01265   if (hi2c->State == HAL_I2C_STATE_READY)
01266   {
01267     /* Process Locked */
01268     __HAL_LOCK(hi2c);
01269
01270     /* Init tickstart for timeout management*/
01271     tickstart = HAL_GetTick();
01272
01273     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01274     {
01275       return HAL_ERROR;
01276     }
01277
01278     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01279     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01280     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01281
01282     /* Prepare transfer parameters */
01283     hi2c->pBuffPtr  = pData;
01284     hi2c->XferCount = Size;
01285     hi2c->XferISR   = NULL;
01286
01287     /* Send Slave Address */
01288     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01289     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01290     {
01291       hi2c->XferSize = MAX_NBYTE_SIZE;
01292       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01293                          I2C_GENERATE_START_READ);
01294     }
01295     else
01296     {
01297       hi2c->XferSize = hi2c->XferCount;
01298       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01299                          I2C_GENERATE_START_READ);
01300     }
01301
01302     while (hi2c->XferCount > 0U)
01303     {
01304       /* Wait until RXNE flag is set */
01305       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01306       {
01307         return HAL_ERROR;
01308       }
01309
01310       /* Read data from RXDR */
01311       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01312
01313       /* Increment Buffer pointer */
01314       hi2c->pBuffPtr++;
01315
01316       hi2c->XferSize--;
01317       hi2c->XferCount--;
01318
01319       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01320       {
01321         /* Wait until TCR flag is set */
01322         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01323         {
01324           return HAL_ERROR;
01325         }
01326
01327         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01328         {
01329           hi2c->XferSize = MAX_NBYTE_SIZE;
01330           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01331                              I2C_NO_STARTSTOP);
01332         }
01333         else
01334         {
01335           hi2c->XferSize = hi2c->XferCount;
01336           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01337                              I2C_NO_STARTSTOP);
01338         }
01339       }
01340     }
01341
01342     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01343     /* Wait until STOPF flag is set */
01344     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01345     {
01346       return HAL_ERROR;
01347     }
01348
01349     /* Clear STOP Flag */
01350     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01351
01352     /* Clear Configuration Register 2 */
01353     I2C_RESET_CR2(hi2c);
01354
01355     hi2c->State = HAL_I2C_STATE_READY;
01356     hi2c->Mode  = HAL_I2C_MODE_NONE;
01357
01358     /* Process Unlocked */
01359     __HAL_UNLOCK(hi2c);
01360
01361     return HAL_OK;
01362   }
01363   else
01364   {
01365     return HAL_BUSY;
01366   }
01367 }
01368
01369 /**
01370   * @brief  Transmits in slave mode an amount of data in blocking mode.
01371   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01372   *                the configuration information for the specified I2C.
01373   * @param  pData Pointer to data buffer
01374   * @param  Size Amount of data to be sent
01375   * @param  Timeout Timeout duration
01376   * @retval HAL status
01377   */
01378 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
01379                                          uint32_t Timeout)
01380 {
01381   uint32_t tickstart;
01382   uint16_t tmpXferCount;
01383   HAL_StatusTypeDef error;
01384
01385   if (hi2c->State == HAL_I2C_STATE_READY)
01386   {
01387     if ((pData == NULL) || (Size == 0U))
01388     {
01389       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01390       return  HAL_ERROR;
01391     }
01392     /* Process Locked */
01393     __HAL_LOCK(hi2c);
01394
01395     /* Init tickstart for timeout management*/
01396     tickstart = HAL_GetTick();
01397
01398     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01399     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01400     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01401
01402     /* Prepare transfer parameters */
01403     hi2c->pBuffPtr  = pData;
01404     hi2c->XferCount = Size;
01405     hi2c->XferISR   = NULL;
01406
01407     /* Enable Address Acknowledge */
01408     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01409
01410     /* Wait until ADDR flag is set */
01411     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01412     {
01413       /* Disable Address Acknowledge */
01414       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01415       return HAL_ERROR;
01416     }
01417
01418     /* Preload TX data if no stretch enable */
01419     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
01420     {
01421       /* Preload TX register */
01422       /* Write data to TXDR */
01423       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01424
01425       /* Increment Buffer pointer */
01426       hi2c->pBuffPtr++;
01427
01428       hi2c->XferCount--;
01429     }
01430
01431     /* Clear ADDR flag */
01432     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01433
01434     /* If 10bit addressing mode is selected */
01435     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01436     {
01437       /* Wait until ADDR flag is set */
01438       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01439       {
01440         /* Disable Address Acknowledge */
01441         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01442         return HAL_ERROR;
01443       }
01444
01445       /* Clear ADDR flag */
01446       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01447     }
01448
01449     /* Wait until DIR flag is set Transmitter mode */
01450     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
01451     {
01452       /* Disable Address Acknowledge */
01453       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01454       return HAL_ERROR;
01455     }
01456
01457     while (hi2c->XferCount > 0U)
01458     {
01459       /* Wait until TXIS flag is set */
01460       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01461       {
01462         /* Disable Address Acknowledge */
01463         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01464         return HAL_ERROR;
01465       }
01466
01467       /* Write data to TXDR */
01468       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01469
01470       /* Increment Buffer pointer */
01471       hi2c->pBuffPtr++;
01472
01473       hi2c->XferCount--;
01474     }
01475
01476     /* Wait until AF flag is set */
01477     error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
01478
01479     if (error != HAL_OK)
01480     {
01481       /* Check that I2C transfer finished */
01482       /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
01483       /* Mean XferCount == 0 */
01484
01485       tmpXferCount = hi2c->XferCount;
01486       if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
01487       {
01488         /* Reset ErrorCode to NONE */
01489         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01490       }
01491       else
01492       {
01493         /* Disable Address Acknowledge */
01494         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01495         return HAL_ERROR;
01496       }
01497     }
01498     else
01499     {
01500       /* Flush TX register */
01501       I2C_Flush_TXDR(hi2c);
01502
01503       /* Clear AF flag */
01504       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
01505
01506       /* Wait until STOP flag is set */
01507       if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01508       {
01509         /* Disable Address Acknowledge */
01510         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01511
01512         return HAL_ERROR;
01513       }
01514
01515       /* Clear STOP flag */
01516       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01517     }
01518
01519     /* Wait until BUSY flag is reset */
01520     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01521     {
01522       /* Disable Address Acknowledge */
01523       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01524       return HAL_ERROR;
01525     }
01526
01527     /* Disable Address Acknowledge */
01528     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01529
01530     hi2c->State = HAL_I2C_STATE_READY;
01531     hi2c->Mode  = HAL_I2C_MODE_NONE;
01532
01533     /* Process Unlocked */
01534     __HAL_UNLOCK(hi2c);
01535
01536     return HAL_OK;
01537   }
01538   else
01539   {
01540     return HAL_BUSY;
01541   }
01542 }
01543
01544 /**
01545   * @brief  Receive in slave mode an amount of data in blocking mode
01546   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01547   *                the configuration information for the specified I2C.
01548   * @param  pData Pointer to data buffer
01549   * @param  Size Amount of data to be sent
01550   * @param  Timeout Timeout duration
01551   * @retval HAL status
01552   */
01553 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
01554                                         uint32_t Timeout)
01555 {
01556   uint32_t tickstart;
01557
01558   if (hi2c->State == HAL_I2C_STATE_READY)
01559   {
01560     if ((pData == NULL) || (Size == 0U))
01561     {
01562       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01563       return  HAL_ERROR;
01564     }
01565     /* Process Locked */
01566     __HAL_LOCK(hi2c);
01567
01568     /* Init tickstart for timeout management*/
01569     tickstart = HAL_GetTick();
01570
01571     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01572     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01573     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01574
01575     /* Prepare transfer parameters */
01576     hi2c->pBuffPtr  = pData;
01577     hi2c->XferCount = Size;
01578     hi2c->XferSize = hi2c->XferCount;
01579     hi2c->XferISR   = NULL;
01580
01581     /* Enable Address Acknowledge */
01582     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01583
01584     /* Wait until ADDR flag is set */
01585     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01586     {
01587       /* Disable Address Acknowledge */
01588       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01589       return HAL_ERROR;
01590     }
01591
01592     /* Clear ADDR flag */
01593     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01594
01595     /* Wait until DIR flag is reset Receiver mode */
01596     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01597     {
01598       /* Disable Address Acknowledge */
01599       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01600       return HAL_ERROR;
01601     }
01602
01603     while (hi2c->XferCount > 0U)
01604     {
01605       /* Wait until RXNE flag is set */
01606       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01607       {
01608         /* Disable Address Acknowledge */
01609         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01610
01611         /* Store Last receive data if any */
01612         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01613         {
01614           /* Read data from RXDR */
01615           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01616
01617           /* Increment Buffer pointer */
01618           hi2c->pBuffPtr++;
01619
01620           hi2c->XferCount--;
01621           hi2c->XferSize--;
01622         }
01623
01624         return HAL_ERROR;
01625       }
01626
01627       /* Read data from RXDR */
01628       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01629
01630       /* Increment Buffer pointer */
01631       hi2c->pBuffPtr++;
01632
01633       hi2c->XferCount--;
01634       hi2c->XferSize--;
01635     }
01636
01637     /* Wait until STOP flag is set */
01638     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01639     {
01640       /* Disable Address Acknowledge */
01641       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01642       return HAL_ERROR;
01643     }
01644
01645     /* Clear STOP flag */
01646     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01647
01648     /* Wait until BUSY flag is reset */
01649     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01650     {
01651       /* Disable Address Acknowledge */
01652       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01653       return HAL_ERROR;
01654     }
01655
01656     /* Disable Address Acknowledge */
01657     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01658
01659     hi2c->State = HAL_I2C_STATE_READY;
01660     hi2c->Mode  = HAL_I2C_MODE_NONE;
01661
01662     /* Process Unlocked */
01663     __HAL_UNLOCK(hi2c);
01664
01665     return HAL_OK;
01666   }
01667   else
01668   {
01669     return HAL_BUSY;
01670   }
01671 }
01672
01673 /**
01674   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01675   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01676   *                the configuration information for the specified I2C.
01677   * @param  DevAddress Target device address: The device 7 bits address value
01678   *         in datasheet must be shifted to the left before calling the interface
01679   * @param  pData Pointer to data buffer
01680   * @param  Size Amount of data to be sent
01681   * @retval HAL status
01682   */
01683 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01684                                              uint16_t Size)
01685 {
01686   uint32_t xfermode;
01687
01688   if (hi2c->State == HAL_I2C_STATE_READY)
01689   {
01690     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01691     {
01692       return HAL_BUSY;
01693     }
01694
01695     /* Process Locked */
01696     __HAL_LOCK(hi2c);
01697
01698     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01699     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01700     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01701
01702     /* Prepare transfer parameters */
01703     hi2c->pBuffPtr    = pData;
01704     hi2c->XferCount   = Size;
01705     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01706     hi2c->XferISR     = I2C_Master_ISR_IT;
01707
01708     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01709     {
01710       hi2c->XferSize = MAX_NBYTE_SIZE;
01711       xfermode = I2C_RELOAD_MODE;
01712     }
01713     else
01714     {
01715       hi2c->XferSize = hi2c->XferCount;
01716       xfermode = I2C_AUTOEND_MODE;
01717     }
01718
01719     /* Send Slave Address */
01720     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01721     if (hi2c->XferSize > 0U)
01722     {
01723       /* Preload TX register */
01724       /* Write data to TXDR */
01725       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01726
01727       /* Increment Buffer pointer */
01728       hi2c->pBuffPtr++;
01729
01730       hi2c->XferCount--;
01731       hi2c->XferSize--;
01732
01733       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
01734                          I2C_GENERATE_START_WRITE);
01735     }
01736     else
01737     {
01738       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
01739                          I2C_GENERATE_START_WRITE);
01740     }
01741
01742     /* Process Unlocked */
01743     __HAL_UNLOCK(hi2c);
01744
01745     /* Note : The I2C interrupts must be enabled after unlocking current process
01746               to avoid the risk of I2C interrupt handle execution before current
01747               process unlock */
01748
01749     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01750     /* possible to enable all of these */
01751     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01752       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01753     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01754
01755     return HAL_OK;
01756   }
01757   else
01758   {
01759     return HAL_BUSY;
01760   }
01761 }
01762
01763 /**
01764   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01765   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01766   *                the configuration information for the specified I2C.
01767   * @param  DevAddress Target device address: The device 7 bits address value
01768   *         in datasheet must be shifted to the left before calling the interface
01769   * @param  pData Pointer to data buffer
01770   * @param  Size Amount of data to be sent
01771   * @retval HAL status
01772   */
01773 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01774                                             uint16_t Size)
01775 {
01776   uint32_t xfermode;
01777
01778   if (hi2c->State == HAL_I2C_STATE_READY)
01779   {
01780     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01781     {
01782       return HAL_BUSY;
01783     }
01784
01785     /* Process Locked */
01786     __HAL_LOCK(hi2c);
01787
01788     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01789     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01790     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01791
01792     /* Prepare transfer parameters */
01793     hi2c->pBuffPtr    = pData;
01794     hi2c->XferCount   = Size;
01795     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01796     hi2c->XferISR     = I2C_Master_ISR_IT;
01797
01798     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01799     {
01800       hi2c->XferSize = MAX_NBYTE_SIZE;
01801       xfermode = I2C_RELOAD_MODE;
01802     }
01803     else
01804     {
01805       hi2c->XferSize = hi2c->XferCount;
01806       xfermode = I2C_AUTOEND_MODE;
01807     }
01808
01809     /* Send Slave Address */
01810     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01811     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01812
01813     /* Process Unlocked */
01814     __HAL_UNLOCK(hi2c);
01815
01816     /* Note : The I2C interrupts must be enabled after unlocking current process
01817               to avoid the risk of I2C interrupt handle execution before current
01818               process unlock */
01819
01820     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01821     /* possible to enable all of these */
01822     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01823       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01824     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01825
01826     return HAL_OK;
01827   }
01828   else
01829   {
01830     return HAL_BUSY;
01831   }
01832 }
01833
01834 /**
01835   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01836   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01837   *                the configuration information for the specified I2C.
01838   * @param  pData Pointer to data buffer
01839   * @param  Size Amount of data to be sent
01840   * @retval HAL status
01841   */
01842 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01843 {
01844   if (hi2c->State == HAL_I2C_STATE_READY)
01845   {
01846     /* Process Locked */
01847     __HAL_LOCK(hi2c);
01848
01849     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01850     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01851     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01852
01853     /* Enable Address Acknowledge */
01854     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01855
01856     /* Prepare transfer parameters */
01857     hi2c->pBuffPtr    = pData;
01858     hi2c->XferCount   = Size;
01859     hi2c->XferSize    = hi2c->XferCount;
01860     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01861     hi2c->XferISR     = I2C_Slave_ISR_IT;
01862
01863     /* Preload TX data if no stretch enable */
01864     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
01865     {
01866       /* Preload TX register */
01867       /* Write data to TXDR */
01868       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01869
01870       /* Increment Buffer pointer */
01871       hi2c->pBuffPtr++;
01872
01873       hi2c->XferCount--;
01874       hi2c->XferSize--;
01875     }
01876
01877     /* Process Unlocked */
01878     __HAL_UNLOCK(hi2c);
01879
01880     /* Note : The I2C interrupts must be enabled after unlocking current process
01881               to avoid the risk of I2C interrupt handle execution before current
01882               process unlock */
01883
01884     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01885     /* possible to enable all of these */
01886     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01887       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01888     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01889
01890     return HAL_OK;
01891   }
01892   else
01893   {
01894     return HAL_BUSY;
01895   }
01896 }
01897
01898 /**
01899   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01900   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01901   *                the configuration information for the specified I2C.
01902   * @param  pData Pointer to data buffer
01903   * @param  Size Amount of data to be sent
01904   * @retval HAL status
01905   */
01906 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01907 {
01908   if (hi2c->State == HAL_I2C_STATE_READY)
01909   {
01910     /* Process Locked */
01911     __HAL_LOCK(hi2c);
01912
01913     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01914     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01915     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01916
01917     /* Enable Address Acknowledge */
01918     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01919
01920     /* Prepare transfer parameters */
01921     hi2c->pBuffPtr    = pData;
01922     hi2c->XferCount   = Size;
01923     hi2c->XferSize    = hi2c->XferCount;
01924     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01925     hi2c->XferISR     = I2C_Slave_ISR_IT;
01926
01927     /* Process Unlocked */
01928     __HAL_UNLOCK(hi2c);
01929
01930     /* Note : The I2C interrupts must be enabled after unlocking current process
01931               to avoid the risk of I2C interrupt handle execution before current
01932               process unlock */
01933
01934     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01935     /* possible to enable all of these */
01936     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01937       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01938     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01939
01940     return HAL_OK;
01941   }
01942   else
01943   {
01944     return HAL_BUSY;
01945   }
01946 }
01947
01948 /**
01949   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01950   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01951   *                the configuration information for the specified I2C.
01952   * @param  DevAddress Target device address: The device 7 bits address value
01953   *         in datasheet must be shifted to the left before calling the interface
01954   * @param  pData Pointer to data buffer
01955   * @param  Size Amount of data to be sent
01956   * @retval HAL status
01957   */
01958 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01959                                               uint16_t Size)
01960 {
01961   uint32_t xfermode;
01962   HAL_StatusTypeDef dmaxferstatus;
01963   uint32_t sizetoxfer = 0U;
01964
01965   if (hi2c->State == HAL_I2C_STATE_READY)
01966   {
01967     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01968     {
01969       return HAL_BUSY;
01970     }
01971
01972     /* Process Locked */
01973     __HAL_LOCK(hi2c);
01974
01975     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01976     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01977     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01978
01979     /* Prepare transfer parameters */
01980     hi2c->pBuffPtr    = pData;
01981     hi2c->XferCount   = Size;
01982     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01983     hi2c->XferISR     = I2C_Master_ISR_DMA;
01984
01985     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01986     {
01987       hi2c->XferSize = MAX_NBYTE_SIZE;
01988       xfermode = I2C_RELOAD_MODE;
01989     }
01990     else
01991     {
01992       hi2c->XferSize = hi2c->XferCount;
01993       xfermode = I2C_AUTOEND_MODE;
01994     }
01995
01996     if (hi2c->XferSize > 0U)
01997     {
01998       /* Preload TX register */
01999       /* Write data to TXDR */
02000       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02001
02002       /* Increment Buffer pointer */
02003       hi2c->pBuffPtr++;
02004
02005       sizetoxfer = hi2c->XferSize;
02006       hi2c->XferCount--;
02007       hi2c->XferSize--;
02008     }
02009
02010     if (hi2c->XferSize > 0U)
02011     {
02012       if (hi2c->hdmatx != NULL)
02013       {
02014         /* Set the I2C DMA transfer complete callback */
02015         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02016
02017         /* Set the DMA error callback */
02018         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02019
02020         /* Set the unused DMA callbacks to NULL */
02021         hi2c->hdmatx->XferHalfCpltCallback = NULL;
02022         hi2c->hdmatx->XferAbortCallback = NULL;
02023
02024         /* Enable the DMA channel */
02025         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
02026                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02027       }
02028       else
02029       {
02030         /* Update I2C state */
02031         hi2c->State     = HAL_I2C_STATE_READY;
02032         hi2c->Mode      = HAL_I2C_MODE_NONE;
02033
02034         /* Update I2C error code */
02035         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02036
02037         /* Process Unlocked */
02038         __HAL_UNLOCK(hi2c);
02039
02040         return HAL_ERROR;
02041       }
02042
02043       if (dmaxferstatus == HAL_OK)
02044       {
02045         /* Send Slave Address */
02046         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02047         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
02048                            xfermode, I2C_GENERATE_START_WRITE);
02049
02050         /* Update XferCount value */
02051         hi2c->XferCount -= hi2c->XferSize;
02052
02053         /* Process Unlocked */
02054         __HAL_UNLOCK(hi2c);
02055
02056         /* Note : The I2C interrupts must be enabled after unlocking current process
02057                   to avoid the risk of I2C interrupt handle execution before current
02058                   process unlock */
02059         /* Enable ERR and NACK interrupts */
02060         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02061
02062         /* Enable DMA Request */
02063         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02064       }
02065       else
02066       {
02067         /* Update I2C state */
02068         hi2c->State     = HAL_I2C_STATE_READY;
02069         hi2c->Mode      = HAL_I2C_MODE_NONE;
02070
02071         /* Update I2C error code */
02072         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02073
02074         /* Process Unlocked */
02075         __HAL_UNLOCK(hi2c);
02076
02077         return HAL_ERROR;
02078       }
02079     }
02080     else
02081     {
02082       /* Update Transfer ISR function pointer */
02083       hi2c->XferISR = I2C_Master_ISR_IT;
02084
02085       /* Send Slave Address */
02086       /* Set NBYTES to write and generate START condition */
02087       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
02088                          I2C_GENERATE_START_WRITE);
02089
02090       /* Process Unlocked */
02091       __HAL_UNLOCK(hi2c);
02092
02093       /* Note : The I2C interrupts must be enabled after unlocking current process
02094                 to avoid the risk of I2C interrupt handle execution before current
02095                 process unlock */
02096       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02097       /* possible to enable all of these */
02098       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02099         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02100       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02101     }
02102
02103     return HAL_OK;
02104   }
02105   else
02106   {
02107     return HAL_BUSY;
02108   }
02109 }
02110
02111 /**
02112   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
02113   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02114   *                the configuration information for the specified I2C.
02115   * @param  DevAddress Target device address: The device 7 bits address value
02116   *         in datasheet must be shifted to the left before calling the interface
02117   * @param  pData Pointer to data buffer
02118   * @param  Size Amount of data to be sent
02119   * @retval HAL status
02120   */
02121 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
02122                                              uint16_t Size)
02123 {
02124   uint32_t xfermode;
02125   HAL_StatusTypeDef dmaxferstatus;
02126
02127   if (hi2c->State == HAL_I2C_STATE_READY)
02128   {
02129     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02130     {
02131       return HAL_BUSY;
02132     }
02133
02134     /* Process Locked */
02135     __HAL_LOCK(hi2c);
02136
02137     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02138     hi2c->Mode        = HAL_I2C_MODE_MASTER;
02139     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02140
02141     /* Prepare transfer parameters */
02142     hi2c->pBuffPtr    = pData;
02143     hi2c->XferCount   = Size;
02144     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02145     hi2c->XferISR     = I2C_Master_ISR_DMA;
02146
02147     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02148     {
02149       hi2c->XferSize = MAX_NBYTE_SIZE;
02150       xfermode = I2C_RELOAD_MODE;
02151     }
02152     else
02153     {
02154       hi2c->XferSize = hi2c->XferCount;
02155       xfermode = I2C_AUTOEND_MODE;
02156     }
02157
02158     if (hi2c->XferSize > 0U)
02159     {
02160       if (hi2c->hdmarx != NULL)
02161       {
02162         /* Set the I2C DMA transfer complete callback */
02163         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02164
02165         /* Set the DMA error callback */
02166         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02167
02168         /* Set the unused DMA callbacks to NULL */
02169         hi2c->hdmarx->XferHalfCpltCallback = NULL;
02170         hi2c->hdmarx->XferAbortCallback = NULL;
02171
02172         /* Enable the DMA channel */
02173         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
02174                                          hi2c->XferSize);
02175       }
02176       else
02177       {
02178         /* Update I2C state */
02179         hi2c->State     = HAL_I2C_STATE_READY;
02180         hi2c->Mode      = HAL_I2C_MODE_NONE;
02181
02182         /* Update I2C error code */
02183         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02184
02185         /* Process Unlocked */
02186         __HAL_UNLOCK(hi2c);
02187
02188         return HAL_ERROR;
02189       }
02190
02191       if (dmaxferstatus == HAL_OK)
02192       {
02193         /* Send Slave Address */
02194         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02195         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02196
02197         /* Update XferCount value */
02198         hi2c->XferCount -= hi2c->XferSize;
02199
02200         /* Process Unlocked */
02201         __HAL_UNLOCK(hi2c);
02202
02203         /* Note : The I2C interrupts must be enabled after unlocking current process
02204                   to avoid the risk of I2C interrupt handle execution before current
02205                   process unlock */
02206         /* Enable ERR and NACK interrupts */
02207         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02208
02209         /* Enable DMA Request */
02210         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02211       }
02212       else
02213       {
02214         /* Update I2C state */
02215         hi2c->State     = HAL_I2C_STATE_READY;
02216         hi2c->Mode      = HAL_I2C_MODE_NONE;
02217
02218         /* Update I2C error code */
02219         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02220
02221         /* Process Unlocked */
02222         __HAL_UNLOCK(hi2c);
02223
02224         return HAL_ERROR;
02225       }
02226     }
02227     else
02228     {
02229       /* Update Transfer ISR function pointer */
02230       hi2c->XferISR = I2C_Master_ISR_IT;
02231
02232       /* Send Slave Address */
02233       /* Set NBYTES to read and generate START condition */
02234       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02235                          I2C_GENERATE_START_READ);
02236
02237       /* Process Unlocked */
02238       __HAL_UNLOCK(hi2c);
02239
02240       /* Note : The I2C interrupts must be enabled after unlocking current process
02241                 to avoid the risk of I2C interrupt handle execution before current
02242                 process unlock */
02243       /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02244       /* possible to enable all of these */
02245       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02246         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02247       I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02248     }
02249
02250     return HAL_OK;
02251   }
02252   else
02253   {
02254     return HAL_BUSY;
02255   }
02256 }
02257
02258 /**
02259   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
02260   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02261   *                the configuration information for the specified I2C.
02262   * @param  pData Pointer to data buffer
02263   * @param  Size Amount of data to be sent
02264   * @retval HAL status
02265   */
02266 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02267 {
02268   HAL_StatusTypeDef dmaxferstatus;
02269
02270   if (hi2c->State == HAL_I2C_STATE_READY)
02271   {
02272     if ((pData == NULL) || (Size == 0U))
02273     {
02274       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02275       return  HAL_ERROR;
02276     }
02277     /* Process Locked */
02278     __HAL_LOCK(hi2c);
02279
02280     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02281     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02282     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02283
02284     /* Prepare transfer parameters */
02285     hi2c->pBuffPtr    = pData;
02286     hi2c->XferCount   = Size;
02287     hi2c->XferSize    = hi2c->XferCount;
02288     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02289     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02290
02291     /* Preload TX data if no stretch enable */
02292     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
02293     {
02294       /* Preload TX register */
02295       /* Write data to TXDR */
02296       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02297
02298       /* Increment Buffer pointer */
02299       hi2c->pBuffPtr++;
02300
02301       hi2c->XferCount--;
02302       hi2c->XferSize--;
02303     }
02304
02305     if (hi2c->XferCount != 0U)
02306     {
02307       if (hi2c->hdmatx != NULL)
02308       {
02309         /* Set the I2C DMA transfer complete callback */
02310         hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
02311
02312         /* Set the DMA error callback */
02313         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02314
02315         /* Set the unused DMA callbacks to NULL */
02316         hi2c->hdmatx->XferHalfCpltCallback = NULL;
02317         hi2c->hdmatx->XferAbortCallback = NULL;
02318
02319         /* Enable the DMA channel */
02320         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
02321                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
02322                                          hi2c->XferSize);
02323       }
02324       else
02325       {
02326         /* Update I2C state */
02327         hi2c->State     = HAL_I2C_STATE_LISTEN;
02328         hi2c->Mode      = HAL_I2C_MODE_NONE;
02329
02330         /* Update I2C error code */
02331         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02332
02333         /* Process Unlocked */
02334         __HAL_UNLOCK(hi2c);
02335
02336         return HAL_ERROR;
02337       }
02338
02339       if (dmaxferstatus == HAL_OK)
02340       {
02341         /* Enable Address Acknowledge */
02342         hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02343
02344         /* Process Unlocked */
02345         __HAL_UNLOCK(hi2c);
02346
02347         /* Note : The I2C interrupts must be enabled after unlocking current process
02348                   to avoid the risk of I2C interrupt handle execution before current
02349                   process unlock */
02350         /* Enable ERR, STOP, NACK, ADDR interrupts */
02351         I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02352
02353         /* Enable DMA Request */
02354         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02355       }
02356       else
02357       {
02358         /* Update I2C state */
02359         hi2c->State     = HAL_I2C_STATE_LISTEN;
02360         hi2c->Mode      = HAL_I2C_MODE_NONE;
02361
02362         /* Update I2C error code */
02363         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02364
02365         /* Process Unlocked */
02366         __HAL_UNLOCK(hi2c);
02367
02368         return HAL_ERROR;
02369       }
02370     }
02371     else
02372     {
02373       /* Enable Address Acknowledge */
02374       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02375
02376       /* Process Unlocked */
02377       __HAL_UNLOCK(hi2c);
02378
02379       /* Note : The I2C interrupts must be enabled after unlocking current process
02380       to avoid the risk of I2C interrupt handle execution before current
02381       process unlock */
02382       /* Enable ERR, STOP, NACK, ADDR interrupts */
02383       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02384     }
02385
02386     return HAL_OK;
02387   }
02388   else
02389   {
02390     return HAL_BUSY;
02391   }
02392 }
02393
02394 /**
02395   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
02396   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02397   *                the configuration information for the specified I2C.
02398   * @param  pData Pointer to data buffer
02399   * @param  Size Amount of data to be sent
02400   * @retval HAL status
02401   */
02402 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02403 {
02404   HAL_StatusTypeDef dmaxferstatus;
02405
02406   if (hi2c->State == HAL_I2C_STATE_READY)
02407   {
02408     if ((pData == NULL) || (Size == 0U))
02409     {
02410       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02411       return  HAL_ERROR;
02412     }
02413     /* Process Locked */
02414     __HAL_LOCK(hi2c);
02415
02416     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02417     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02418     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02419
02420     /* Prepare transfer parameters */
02421     hi2c->pBuffPtr    = pData;
02422     hi2c->XferCount   = Size;
02423     hi2c->XferSize    = hi2c->XferCount;
02424     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02425     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02426
02427     if (hi2c->hdmarx != NULL)
02428     {
02429       /* Set the I2C DMA transfer complete callback */
02430       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
02431
02432       /* Set the DMA error callback */
02433       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02434
02435       /* Set the unused DMA callbacks to NULL */
02436       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02437       hi2c->hdmarx->XferAbortCallback = NULL;
02438
02439       /* Enable the DMA channel */
02440       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
02441                                        hi2c->XferSize);
02442     }
02443     else
02444     {
02445       /* Update I2C state */
02446       hi2c->State     = HAL_I2C_STATE_LISTEN;
02447       hi2c->Mode      = HAL_I2C_MODE_NONE;
02448
02449       /* Update I2C error code */
02450       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02451
02452       /* Process Unlocked */
02453       __HAL_UNLOCK(hi2c);
02454
02455       return HAL_ERROR;
02456     }
02457
02458     if (dmaxferstatus == HAL_OK)
02459     {
02460       /* Enable Address Acknowledge */
02461       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02462
02463       /* Process Unlocked */
02464       __HAL_UNLOCK(hi2c);
02465
02466       /* Note : The I2C interrupts must be enabled after unlocking current process
02467                 to avoid the risk of I2C interrupt handle execution before current
02468                 process unlock */
02469       /* Enable ERR, STOP, NACK, ADDR interrupts */
02470       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02471
02472       /* Enable DMA Request */
02473       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02474     }
02475     else
02476     {
02477       /* Update I2C state */
02478       hi2c->State     = HAL_I2C_STATE_LISTEN;
02479       hi2c->Mode      = HAL_I2C_MODE_NONE;
02480
02481       /* Update I2C error code */
02482       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02483
02484       /* Process Unlocked */
02485       __HAL_UNLOCK(hi2c);
02486
02487       return HAL_ERROR;
02488     }
02489
02490     return HAL_OK;
02491   }
02492   else
02493   {
02494     return HAL_BUSY;
02495   }
02496 }
02497
02498 /**
02499   * @brief  Write an amount of data in blocking mode to a specific memory address
02500   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02501   *                the configuration information for the specified I2C.
02502   * @param  DevAddress Target device address: The device 7 bits address value
02503   *         in datasheet must be shifted to the left before calling the interface
02504   * @param  MemAddress Internal memory address
02505   * @param  MemAddSize Size of internal memory address
02506   * @param  pData Pointer to data buffer
02507   * @param  Size Amount of data to be sent
02508   * @param  Timeout Timeout duration
02509   * @retval HAL status
02510   */
02511 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02512                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02513 {
02514   uint32_t tickstart;
02515
02516   /* Check the parameters */
02517   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02518
02519   if (hi2c->State == HAL_I2C_STATE_READY)
02520   {
02521     if ((pData == NULL) || (Size == 0U))
02522     {
02523       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02524       return  HAL_ERROR;
02525     }
02526
02527     /* Process Locked */
02528     __HAL_LOCK(hi2c);
02529
02530     /* Init tickstart for timeout management*/
02531     tickstart = HAL_GetTick();
02532
02533     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02534     {
02535       return HAL_ERROR;
02536     }
02537
02538     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02539     hi2c->Mode      = HAL_I2C_MODE_MEM;
02540     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02541
02542     /* Prepare transfer parameters */
02543     hi2c->pBuffPtr  = pData;
02544     hi2c->XferCount = Size;
02545     hi2c->XferISR   = NULL;
02546
02547     /* Send Slave Address and Memory Address */
02548     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02549     {
02550       /* Process Unlocked */
02551       __HAL_UNLOCK(hi2c);
02552       return HAL_ERROR;
02553     }
02554
02555     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
02556     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02557     {
02558       hi2c->XferSize = MAX_NBYTE_SIZE;
02559       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02560     }
02561     else
02562     {
02563       hi2c->XferSize = hi2c->XferCount;
02564       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02565     }
02566
02567     do
02568     {
02569       /* Wait until TXIS flag is set */
02570       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02571       {
02572         return HAL_ERROR;
02573       }
02574
02575       /* Write data to TXDR */
02576       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02577
02578       /* Increment Buffer pointer */
02579       hi2c->pBuffPtr++;
02580
02581       hi2c->XferCount--;
02582       hi2c->XferSize--;
02583
02584       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02585       {
02586         /* Wait until TCR flag is set */
02587         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02588         {
02589           return HAL_ERROR;
02590         }
02591
02592         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02593         {
02594           hi2c->XferSize = MAX_NBYTE_SIZE;
02595           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
02596                              I2C_NO_STARTSTOP);
02597         }
02598         else
02599         {
02600           hi2c->XferSize = hi2c->XferCount;
02601           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02602                              I2C_NO_STARTSTOP);
02603         }
02604       }
02605
02606     } while (hi2c->XferCount > 0U);
02607
02608     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02609     /* Wait until STOPF flag is reset */
02610     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02611     {
02612       return HAL_ERROR;
02613     }
02614
02615     /* Clear STOP Flag */
02616     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02617
02618     /* Clear Configuration Register 2 */
02619     I2C_RESET_CR2(hi2c);
02620
02621     hi2c->State = HAL_I2C_STATE_READY;
02622     hi2c->Mode  = HAL_I2C_MODE_NONE;
02623
02624     /* Process Unlocked */
02625     __HAL_UNLOCK(hi2c);
02626
02627     return HAL_OK;
02628   }
02629   else
02630   {
02631     return HAL_BUSY;
02632   }
02633 }
02634
02635 /**
02636   * @brief  Read an amount of data in blocking mode from a specific memory address
02637   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02638   *                the configuration information for the specified I2C.
02639   * @param  DevAddress Target device address: The device 7 bits address value
02640   *         in datasheet must be shifted to the left before calling the interface
02641   * @param  MemAddress Internal memory address
02642   * @param  MemAddSize Size of internal memory address
02643   * @param  pData Pointer to data buffer
02644   * @param  Size Amount of data to be sent
02645   * @param  Timeout Timeout duration
02646   * @retval HAL status
02647   */
02648 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02649                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02650 {
02651   uint32_t tickstart;
02652
02653   /* Check the parameters */
02654   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02655
02656   if (hi2c->State == HAL_I2C_STATE_READY)
02657   {
02658     if ((pData == NULL) || (Size == 0U))
02659     {
02660       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02661       return  HAL_ERROR;
02662     }
02663
02664     /* Process Locked */
02665     __HAL_LOCK(hi2c);
02666
02667     /* Init tickstart for timeout management*/
02668     tickstart = HAL_GetTick();
02669
02670     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02671     {
02672       return HAL_ERROR;
02673     }
02674
02675     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02676     hi2c->Mode      = HAL_I2C_MODE_MEM;
02677     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02678
02679     /* Prepare transfer parameters */
02680     hi2c->pBuffPtr  = pData;
02681     hi2c->XferCount = Size;
02682     hi2c->XferISR   = NULL;
02683
02684     /* Send Slave Address and Memory Address */
02685     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02686     {
02687       /* Process Unlocked */
02688       __HAL_UNLOCK(hi2c);
02689       return HAL_ERROR;
02690     }
02691
02692     /* Send Slave Address */
02693     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02694     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02695     {
02696       hi2c->XferSize = MAX_NBYTE_SIZE;
02697       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
02698                          I2C_GENERATE_START_READ);
02699     }
02700     else
02701     {
02702       hi2c->XferSize = hi2c->XferCount;
02703       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02704                          I2C_GENERATE_START_READ);
02705     }
02706
02707     do
02708     {
02709       /* Wait until RXNE flag is set */
02710       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
02711       {
02712         return HAL_ERROR;
02713       }
02714
02715       /* Read data from RXDR */
02716       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
02717
02718       /* Increment Buffer pointer */
02719       hi2c->pBuffPtr++;
02720
02721       hi2c->XferSize--;
02722       hi2c->XferCount--;
02723
02724       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02725       {
02726         /* Wait until TCR flag is set */
02727         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02728         {
02729           return HAL_ERROR;
02730         }
02731
02732         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02733         {
02734           hi2c->XferSize = MAX_NBYTE_SIZE;
02735           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
02736                              I2C_NO_STARTSTOP);
02737         }
02738         else
02739         {
02740           hi2c->XferSize = hi2c->XferCount;
02741           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02742                              I2C_NO_STARTSTOP);
02743         }
02744       }
02745     } while (hi2c->XferCount > 0U);
02746
02747     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02748     /* Wait until STOPF flag is reset */
02749     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02750     {
02751       return HAL_ERROR;
02752     }
02753
02754     /* Clear STOP Flag */
02755     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02756
02757     /* Clear Configuration Register 2 */
02758     I2C_RESET_CR2(hi2c);
02759
02760     hi2c->State = HAL_I2C_STATE_READY;
02761     hi2c->Mode  = HAL_I2C_MODE_NONE;
02762
02763     /* Process Unlocked */
02764     __HAL_UNLOCK(hi2c);
02765
02766     return HAL_OK;
02767   }
02768   else
02769   {
02770     return HAL_BUSY;
02771   }
02772 }
02773 /**
02774   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02775   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02776   *                the configuration information for the specified I2C.
02777   * @param  DevAddress Target device address: The device 7 bits address value
02778   *         in datasheet must be shifted to the left before calling the interface
02779   * @param  MemAddress Internal memory address
02780   * @param  MemAddSize Size of internal memory address
02781   * @param  pData Pointer to data buffer
02782   * @param  Size Amount of data to be sent
02783   * @retval HAL status
02784   */
02785 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02786                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02787 {
02788   /* Check the parameters */
02789   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02790
02791   if (hi2c->State == HAL_I2C_STATE_READY)
02792   {
02793     if ((pData == NULL) || (Size == 0U))
02794     {
02795       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02796       return  HAL_ERROR;
02797     }
02798
02799     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02800     {
02801       return HAL_BUSY;
02802     }
02803
02804     /* Process Locked */
02805     __HAL_LOCK(hi2c);
02806
02807     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02808     hi2c->Mode        = HAL_I2C_MODE_MEM;
02809     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02810
02811     /* Prepare transfer parameters */
02812     hi2c->XferSize    = 0U;
02813     hi2c->pBuffPtr    = pData;
02814     hi2c->XferCount   = Size;
02815     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02816     hi2c->XferISR     = I2C_Mem_ISR_IT;
02817     hi2c->Devaddress  = DevAddress;
02818
02819     /* If Memory address size is 8Bit */
02820     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
02821     {
02822       /* Prefetch Memory Address */
02823       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
02824
02825       /* Reset Memaddress content */
02826       hi2c->Memaddress = 0xFFFFFFFFU;
02827     }
02828     /* If Memory address size is 16Bit */
02829     else
02830     {
02831       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
02832       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
02833
02834       /* Prepare Memaddress buffer for LSB part */
02835       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
02836     }
02837     /* Send Slave Address and Memory Address */
02838     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
02839
02840     /* Process Unlocked */
02841     __HAL_UNLOCK(hi2c);
02842
02843     /* Note : The I2C interrupts must be enabled after unlocking current process
02844               to avoid the risk of I2C interrupt handle execution before current
02845               process unlock */
02846
02847     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02848     /* possible to enable all of these */
02849     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02850       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02851     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02852
02853     return HAL_OK;
02854   }
02855   else
02856   {
02857     return HAL_BUSY;
02858   }
02859 }
02860
02861 /**
02862   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02863   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02864   *                the configuration information for the specified I2C.
02865   * @param  DevAddress Target device address: The device 7 bits address value
02866   *         in datasheet must be shifted to the left before calling the interface
02867   * @param  MemAddress Internal memory address
02868   * @param  MemAddSize Size of internal memory address
02869   * @param  pData Pointer to data buffer
02870   * @param  Size Amount of data to be sent
02871   * @retval HAL status
02872   */
02873 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02874                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02875 {
02876   /* Check the parameters */
02877   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02878
02879   if (hi2c->State == HAL_I2C_STATE_READY)
02880   {
02881     if ((pData == NULL) || (Size == 0U))
02882     {
02883       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02884       return  HAL_ERROR;
02885     }
02886
02887     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02888     {
02889       return HAL_BUSY;
02890     }
02891
02892     /* Process Locked */
02893     __HAL_LOCK(hi2c);
02894
02895     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02896     hi2c->Mode        = HAL_I2C_MODE_MEM;
02897     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02898
02899     /* Prepare transfer parameters */
02900     hi2c->pBuffPtr    = pData;
02901     hi2c->XferCount   = Size;
02902     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02903     hi2c->XferISR     = I2C_Mem_ISR_IT;
02904     hi2c->Devaddress  = DevAddress;
02905
02906     /* If Memory address size is 8Bit */
02907     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
02908     {
02909       /* Prefetch Memory Address */
02910       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
02911
02912       /* Reset Memaddress content */
02913       hi2c->Memaddress = 0xFFFFFFFFU;
02914     }
02915     /* If Memory address size is 16Bit */
02916     else
02917     {
02918       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
02919       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
02920
02921       /* Prepare Memaddress buffer for LSB part */
02922       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
02923     }
02924     /* Send Slave Address and Memory Address */
02925     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
02926
02927     /* Process Unlocked */
02928     __HAL_UNLOCK(hi2c);
02929
02930     /* Note : The I2C interrupts must be enabled after unlocking current process
02931               to avoid the risk of I2C interrupt handle execution before current
02932               process unlock */
02933
02934     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02935     /* possible to enable all of these */
02936     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02937       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02938     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02939
02940     return HAL_OK;
02941   }
02942   else
02943   {
02944     return HAL_BUSY;
02945   }
02946 }
02947
02948 /**
02949   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02950   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02951   *                the configuration information for the specified I2C.
02952   * @param  DevAddress Target device address: The device 7 bits address value
02953   *         in datasheet must be shifted to the left before calling the interface
02954   * @param  MemAddress Internal memory address
02955   * @param  MemAddSize Size of internal memory address
02956   * @param  pData Pointer to data buffer
02957   * @param  Size Amount of data to be sent
02958   * @retval HAL status
02959   */
02960 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02961                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02962 {
02963   HAL_StatusTypeDef dmaxferstatus;
02964
02965   /* Check the parameters */
02966   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02967
02968   if (hi2c->State == HAL_I2C_STATE_READY)
02969   {
02970     if ((pData == NULL) || (Size == 0U))
02971     {
02972       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02973       return  HAL_ERROR;
02974     }
02975
02976     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02977     {
02978       return HAL_BUSY;
02979     }
02980
02981     /* Process Locked */
02982     __HAL_LOCK(hi2c);
02983
02984     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02985     hi2c->Mode        = HAL_I2C_MODE_MEM;
02986     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02987
02988     /* Prepare transfer parameters */
02989     hi2c->pBuffPtr    = pData;
02990     hi2c->XferCount   = Size;
02991     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02992     hi2c->XferISR     = I2C_Mem_ISR_DMA;
02993     hi2c->Devaddress  = DevAddress;
02994
02995     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02996     {
02997       hi2c->XferSize = MAX_NBYTE_SIZE;
02998     }
02999     else
03000     {
03001       hi2c->XferSize = hi2c->XferCount;
03002     }
03003
03004     /* If Memory address size is 8Bit */
03005     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
03006     {
03007       /* Prefetch Memory Address */
03008       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03009
03010       /* Reset Memaddress content */
03011       hi2c->Memaddress = 0xFFFFFFFFU;
03012     }
03013     /* If Memory address size is 16Bit */
03014     else
03015     {
03016       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
03017       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03018
03019       /* Prepare Memaddress buffer for LSB part */
03020       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
03021     }
03022
03023     if (hi2c->hdmatx != NULL)
03024     {
03025       /* Set the I2C DMA transfer complete callback */
03026       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
03027
03028       /* Set the DMA error callback */
03029       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03030
03031       /* Set the unused DMA callbacks to NULL */
03032       hi2c->hdmatx->XferHalfCpltCallback = NULL;
03033       hi2c->hdmatx->XferAbortCallback = NULL;
03034
03035       /* Enable the DMA channel */
03036       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
03037                                        hi2c->XferSize);
03038     }
03039     else
03040     {
03041       /* Update I2C state */
03042       hi2c->State     = HAL_I2C_STATE_READY;
03043       hi2c->Mode      = HAL_I2C_MODE_NONE;
03044
03045       /* Update I2C error code */
03046       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03047
03048       /* Process Unlocked */
03049       __HAL_UNLOCK(hi2c);
03050
03051       return HAL_ERROR;
03052     }
03053
03054     if (dmaxferstatus == HAL_OK)
03055     {
03056       /* Send Slave Address and Memory Address */
03057       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03058
03059       /* Process Unlocked */
03060       __HAL_UNLOCK(hi2c);
03061
03062       /* Note : The I2C interrupts must be enabled after unlocking current process
03063                 to avoid the risk of I2C interrupt handle execution before current
03064                 process unlock */
03065       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03066       /* possible to enable all of these */
03067       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03068         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03069       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03070     }
03071     else
03072     {
03073       /* Update I2C state */
03074       hi2c->State     = HAL_I2C_STATE_READY;
03075       hi2c->Mode      = HAL_I2C_MODE_NONE;
03076
03077       /* Update I2C error code */
03078       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03079
03080       /* Process Unlocked */
03081       __HAL_UNLOCK(hi2c);
03082
03083       return HAL_ERROR;
03084     }
03085
03086     return HAL_OK;
03087   }
03088   else
03089   {
03090     return HAL_BUSY;
03091   }
03092 }
03093
03094 /**
03095   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
03096   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03097   *                the configuration information for the specified I2C.
03098   * @param  DevAddress Target device address: The device 7 bits address value
03099   *         in datasheet must be shifted to the left before calling the interface
03100   * @param  MemAddress Internal memory address
03101   * @param  MemAddSize Size of internal memory address
03102   * @param  pData Pointer to data buffer
03103   * @param  Size Amount of data to be read
03104   * @retval HAL status
03105   */
03106 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
03107                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
03108 {
03109   HAL_StatusTypeDef dmaxferstatus;
03110
03111   /* Check the parameters */
03112   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
03113
03114   if (hi2c->State == HAL_I2C_STATE_READY)
03115   {
03116     if ((pData == NULL) || (Size == 0U))
03117     {
03118       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03119       return  HAL_ERROR;
03120     }
03121
03122     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
03123     {
03124       return HAL_BUSY;
03125     }
03126
03127     /* Process Locked */
03128     __HAL_LOCK(hi2c);
03129
03130     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
03131     hi2c->Mode        = HAL_I2C_MODE_MEM;
03132     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
03133
03134     /* Prepare transfer parameters */
03135     hi2c->pBuffPtr    = pData;
03136     hi2c->XferCount   = Size;
03137     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03138     hi2c->XferISR     = I2C_Mem_ISR_DMA;
03139     hi2c->Devaddress  = DevAddress;
03140
03141     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03142     {
03143       hi2c->XferSize = MAX_NBYTE_SIZE;
03144     }
03145     else
03146     {
03147       hi2c->XferSize = hi2c->XferCount;
03148     }
03149
03150     /* If Memory address size is 8Bit */
03151     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
03152     {
03153       /* Prefetch Memory Address */
03154       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03155
03156       /* Reset Memaddress content */
03157       hi2c->Memaddress = 0xFFFFFFFFU;
03158     }
03159     /* If Memory address size is 16Bit */
03160     else
03161     {
03162       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
03163       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03164
03165       /* Prepare Memaddress buffer for LSB part */
03166       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
03167     }
03168
03169     if (hi2c->hdmarx != NULL)
03170     {
03171       /* Set the I2C DMA transfer complete callback */
03172       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03173
03174       /* Set the DMA error callback */
03175       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03176
03177       /* Set the unused DMA callbacks to NULL */
03178       hi2c->hdmarx->XferHalfCpltCallback = NULL;
03179       hi2c->hdmarx->XferAbortCallback = NULL;
03180
03181       /* Enable the DMA channel */
03182       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
03183                                        hi2c->XferSize);
03184     }
03185     else
03186     {
03187       /* Update I2C state */
03188       hi2c->State     = HAL_I2C_STATE_READY;
03189       hi2c->Mode      = HAL_I2C_MODE_NONE;
03190
03191       /* Update I2C error code */
03192       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03193
03194       /* Process Unlocked */
03195       __HAL_UNLOCK(hi2c);
03196
03197       return HAL_ERROR;
03198     }
03199
03200     if (dmaxferstatus == HAL_OK)
03201     {
03202       /* Send Slave Address and Memory Address */
03203       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03204
03205       /* Process Unlocked */
03206       __HAL_UNLOCK(hi2c);
03207
03208       /* Note : The I2C interrupts must be enabled after unlocking current process
03209                 to avoid the risk of I2C interrupt handle execution before current
03210                 process unlock */
03211       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03212       /* possible to enable all of these */
03213       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03214         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03215       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03216     }
03217     else
03218     {
03219       /* Update I2C state */
03220       hi2c->State     = HAL_I2C_STATE_READY;
03221       hi2c->Mode      = HAL_I2C_MODE_NONE;
03222
03223       /* Update I2C error code */
03224       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03225
03226       /* Process Unlocked */
03227       __HAL_UNLOCK(hi2c);
03228
03229       return HAL_ERROR;
03230     }
03231
03232     return HAL_OK;
03233   }
03234   else
03235   {
03236     return HAL_BUSY;
03237   }
03238 }
03239
03240 /**
03241   * @brief  Checks if target device is ready for communication.
03242   * @note   This function is used with Memory devices
03243   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03244   *                the configuration information for the specified I2C.
03245   * @param  DevAddress Target device address: The device 7 bits address value
03246   *         in datasheet must be shifted to the left before calling the interface
03247   * @param  Trials Number of trials
03248   * @param  Timeout Timeout duration
03249   * @retval HAL status
03250   */
03251 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
03252                                         uint32_t Timeout)
03253 {
03254   uint32_t tickstart;
03255
03256   __IO uint32_t I2C_Trials = 0UL;
03257
03258   FlagStatus tmp1;
03259   FlagStatus tmp2;
03260
03261   if (hi2c->State == HAL_I2C_STATE_READY)
03262   {
03263     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
03264     {
03265       return HAL_BUSY;
03266     }
03267
03268     /* Process Locked */
03269     __HAL_LOCK(hi2c);
03270
03271     hi2c->State = HAL_I2C_STATE_BUSY;
03272     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03273
03274     do
03275     {
03276       /* Generate Start */
03277       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
03278
03279       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03280       /* Wait until STOPF flag is set or a NACK flag is set*/
03281       tickstart = HAL_GetTick();
03282
03283       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03284       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03285
03286       while ((tmp1 == RESET) && (tmp2 == RESET))
03287       {
03288         if (Timeout != HAL_MAX_DELAY)
03289         {
03290           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03291           {
03292             /* Update I2C state */
03293             hi2c->State = HAL_I2C_STATE_READY;
03294
03295             /* Update I2C error code */
03296             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03297
03298             /* Process Unlocked */
03299             __HAL_UNLOCK(hi2c);
03300
03301             return HAL_ERROR;
03302           }
03303         }
03304
03305         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03306         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03307       }
03308
03309       /* Check if the NACKF flag has not been set */
03310       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
03311       {
03312         /* Wait until STOPF flag is reset */
03313         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03314         {
03315           return HAL_ERROR;
03316         }
03317
03318         /* Clear STOP Flag */
03319         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03320
03321         /* Device is ready */
03322         hi2c->State = HAL_I2C_STATE_READY;
03323
03324         /* Process Unlocked */
03325         __HAL_UNLOCK(hi2c);
03326
03327         return HAL_OK;
03328       }
03329       else
03330       {
03331         /* Wait until STOPF flag is reset */
03332         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03333         {
03334           return HAL_ERROR;
03335         }
03336
03337         /* Clear NACK Flag */
03338         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03339
03340         /* Clear STOP Flag, auto generated with autoend*/
03341         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03342       }
03343
03344       /* Increment Trials */
03345       I2C_Trials++;
03346     } while (I2C_Trials < Trials);
03347
03348     /* Update I2C state */
03349     hi2c->State = HAL_I2C_STATE_READY;
03350
03351     /* Update I2C error code */
03352     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03353
03354     /* Process Unlocked */
03355     __HAL_UNLOCK(hi2c);
03356
03357     return HAL_ERROR;
03358   }
03359   else
03360   {
03361     return HAL_BUSY;
03362   }
03363 }
03364
03365 /**
03366   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
03367   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03368   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03369   *                the configuration information for the specified I2C.
03370   * @param  DevAddress Target device address: The device 7 bits address value
03371   *         in datasheet must be shifted to the left before calling the interface
03372   * @param  pData Pointer to data buffer
03373   * @param  Size Amount of data to be sent
03374   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03375   * @retval HAL status
03376   */
03377 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03378                                                  uint16_t Size, uint32_t XferOptions)
03379 {
03380   uint32_t xfermode;
03381   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03382   uint32_t sizetoxfer = 0U;
03383
03384   /* Check the parameters */
03385   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03386
03387   if (hi2c->State == HAL_I2C_STATE_READY)
03388   {
03389     /* Process Locked */
03390     __HAL_LOCK(hi2c);
03391
03392     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03393     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03394     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03395
03396     /* Prepare transfer parameters */
03397     hi2c->pBuffPtr    = pData;
03398     hi2c->XferCount   = Size;
03399     hi2c->XferOptions = XferOptions;
03400     hi2c->XferISR     = I2C_Master_ISR_IT;
03401
03402     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03403     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03404     {
03405       hi2c->XferSize = MAX_NBYTE_SIZE;
03406       xfermode = I2C_RELOAD_MODE;
03407     }
03408     else
03409     {
03410       hi2c->XferSize = hi2c->XferCount;
03411       xfermode = hi2c->XferOptions;
03412     }
03413
03414     if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
03415                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
03416     {
03417       /* Preload TX register */
03418       /* Write data to TXDR */
03419       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
03420
03421       /* Increment Buffer pointer */
03422       hi2c->pBuffPtr++;
03423
03424       sizetoxfer = hi2c->XferSize;
03425       hi2c->XferCount--;
03426       hi2c->XferSize--;
03427     }
03428
03429     /* If transfer direction not change and there is no request to start another frame,
03430        do not generate Restart Condition */
03431     /* Mean Previous state is same as current state */
03432     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
03433         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03434     {
03435       xferrequest = I2C_NO_STARTSTOP;
03436     }
03437     else
03438     {
03439       /* Convert OTHER_xxx XferOptions if any */
03440       I2C_ConvertOtherXferOptions(hi2c);
03441
03442       /* Update xfermode accordingly if no reload is necessary */
03443       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03444       {
03445         xfermode = hi2c->XferOptions;
03446       }
03447     }
03448
03449     /* Send Slave Address and set NBYTES to write */
03450     if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
03451     {
03452       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
03453     }
03454     else
03455     {
03456       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03457     }
03458
03459     /* Process Unlocked */
03460     __HAL_UNLOCK(hi2c);
03461
03462     /* Note : The I2C interrupts must be enabled after unlocking current process
03463               to avoid the risk of I2C interrupt handle execution before current
03464               process unlock */
03465     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03466     /* possible to enable all of these */
03467     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03468        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03469     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03470
03471     return HAL_OK;
03472   }
03473   else
03474   {
03475     return HAL_BUSY;
03476   }
03477 }
03478
03479 /**
03480   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
03481   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03482   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03483   *                the configuration information for the specified I2C.
03484   * @param  DevAddress Target device address: The device 7 bits address value
03485   *         in datasheet must be shifted to the left before calling the interface
03486   * @param  pData Pointer to data buffer
03487   * @param  Size Amount of data to be sent
03488   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03489   * @retval HAL status
03490   */
03491 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03492                                                   uint16_t Size, uint32_t XferOptions)
03493 {
03494   uint32_t xfermode;
03495   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03496   HAL_StatusTypeDef dmaxferstatus;
03497   uint32_t sizetoxfer = 0U;
03498
03499   /* Check the parameters */
03500   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03501
03502   if (hi2c->State == HAL_I2C_STATE_READY)
03503   {
03504     /* Process Locked */
03505     __HAL_LOCK(hi2c);
03506
03507     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03508     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03509     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03510
03511     /* Prepare transfer parameters */
03512     hi2c->pBuffPtr    = pData;
03513     hi2c->XferCount   = Size;
03514     hi2c->XferOptions = XferOptions;
03515     hi2c->XferISR     = I2C_Master_ISR_DMA;
03516
03517     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03518     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03519     {
03520       hi2c->XferSize = MAX_NBYTE_SIZE;
03521       xfermode = I2C_RELOAD_MODE;
03522     }
03523     else
03524     {
03525       hi2c->XferSize = hi2c->XferCount;
03526       xfermode = hi2c->XferOptions;
03527     }
03528
03529     if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
03530                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
03531     {
03532       /* Preload TX register */
03533       /* Write data to TXDR */
03534       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
03535
03536       /* Increment Buffer pointer */
03537       hi2c->pBuffPtr++;
03538
03539       sizetoxfer = hi2c->XferSize;
03540       hi2c->XferCount--;
03541       hi2c->XferSize--;
03542     }
03543
03544     /* If transfer direction not change and there is no request to start another frame,
03545        do not generate Restart Condition */
03546     /* Mean Previous state is same as current state */
03547     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
03548         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03549     {
03550       xferrequest = I2C_NO_STARTSTOP;
03551     }
03552     else
03553     {
03554       /* Convert OTHER_xxx XferOptions if any */
03555       I2C_ConvertOtherXferOptions(hi2c);
03556
03557       /* Update xfermode accordingly if no reload is necessary */
03558       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03559       {
03560         xfermode = hi2c->XferOptions;
03561       }
03562     }
03563
03564     if (hi2c->XferSize > 0U)
03565     {
03566       if (hi2c->hdmatx != NULL)
03567       {
03568         /* Set the I2C DMA transfer complete callback */
03569         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
03570
03571         /* Set the DMA error callback */
03572         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03573
03574         /* Set the unused DMA callbacks to NULL */
03575         hi2c->hdmatx->XferHalfCpltCallback = NULL;
03576         hi2c->hdmatx->XferAbortCallback = NULL;
03577
03578         /* Enable the DMA channel */
03579         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
03580                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03581       }
03582       else
03583       {
03584         /* Update I2C state */
03585         hi2c->State     = HAL_I2C_STATE_READY;
03586         hi2c->Mode      = HAL_I2C_MODE_NONE;
03587
03588         /* Update I2C error code */
03589         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03590
03591         /* Process Unlocked */
03592         __HAL_UNLOCK(hi2c);
03593
03594         return HAL_ERROR;
03595       }
03596
03597       if (dmaxferstatus == HAL_OK)
03598       {
03599         /* Send Slave Address and set NBYTES to write */
03600         if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
03601         {
03602           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
03603         }
03604         else
03605         {
03606           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03607         }
03608
03609         /* Update XferCount value */
03610         hi2c->XferCount -= hi2c->XferSize;
03611
03612         /* Process Unlocked */
03613         __HAL_UNLOCK(hi2c);
03614
03615         /* Note : The I2C interrupts must be enabled after unlocking current process
03616                   to avoid the risk of I2C interrupt handle execution before current
03617                   process unlock */
03618         /* Enable ERR and NACK interrupts */
03619         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03620
03621         /* Enable DMA Request */
03622         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03623       }
03624       else
03625       {
03626         /* Update I2C state */
03627         hi2c->State     = HAL_I2C_STATE_READY;
03628         hi2c->Mode      = HAL_I2C_MODE_NONE;
03629
03630         /* Update I2C error code */
03631         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03632
03633         /* Process Unlocked */
03634         __HAL_UNLOCK(hi2c);
03635
03636         return HAL_ERROR;
03637       }
03638     }
03639     else
03640     {
03641       /* Update Transfer ISR function pointer */
03642       hi2c->XferISR = I2C_Master_ISR_IT;
03643
03644       /* Send Slave Address */
03645       /* Set NBYTES to write and generate START condition */
03646       if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
03647       {
03648         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
03649       }
03650       else
03651       {
03652         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03653       }
03654
03655       /* Process Unlocked */
03656       __HAL_UNLOCK(hi2c);
03657
03658       /* Note : The I2C interrupts must be enabled after unlocking current process
03659                 to avoid the risk of I2C interrupt handle execution before current
03660                 process unlock */
03661       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03662       /* possible to enable all of these */
03663       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03664         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03665       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03666     }
03667
03668     return HAL_OK;
03669   }
03670   else
03671   {
03672     return HAL_BUSY;
03673   }
03674 }
03675
03676 /**
03677   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
03678   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03679   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03680   *                the configuration information for the specified I2C.
03681   * @param  DevAddress Target device address: The device 7 bits address value
03682   *         in datasheet must be shifted to the left before calling the interface
03683   * @param  pData Pointer to data buffer
03684   * @param  Size Amount of data to be sent
03685   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03686   * @retval HAL status
03687   */
03688 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03689                                                 uint16_t Size, uint32_t XferOptions)
03690 {
03691   uint32_t xfermode;
03692   uint32_t xferrequest = I2C_GENERATE_START_READ;
03693
03694   /* Check the parameters */
03695   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03696
03697   if (hi2c->State == HAL_I2C_STATE_READY)
03698   {
03699     /* Process Locked */
03700     __HAL_LOCK(hi2c);
03701
03702     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03703     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03704     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03705
03706     /* Prepare transfer parameters */
03707     hi2c->pBuffPtr    = pData;
03708     hi2c->XferCount   = Size;
03709     hi2c->XferOptions = XferOptions;
03710     hi2c->XferISR     = I2C_Master_ISR_IT;
03711
03712     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03713     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03714     {
03715       hi2c->XferSize = MAX_NBYTE_SIZE;
03716       xfermode = I2C_RELOAD_MODE;
03717     }
03718     else
03719     {
03720       hi2c->XferSize = hi2c->XferCount;
03721       xfermode = hi2c->XferOptions;
03722     }
03723
03724     /* If transfer direction not change and there is no request to start another frame,
03725        do not generate Restart Condition */
03726     /* Mean Previous state is same as current state */
03727     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
03728         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03729     {
03730       xferrequest = I2C_NO_STARTSTOP;
03731     }
03732     else
03733     {
03734       /* Convert OTHER_xxx XferOptions if any */
03735       I2C_ConvertOtherXferOptions(hi2c);
03736
03737       /* Update xfermode accordingly if no reload is necessary */
03738       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03739       {
03740         xfermode = hi2c->XferOptions;
03741       }
03742     }
03743
03744     /* Send Slave Address and set NBYTES to read */
03745     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03746
03747     /* Process Unlocked */
03748     __HAL_UNLOCK(hi2c);
03749
03750     /* Note : The I2C interrupts must be enabled after unlocking current process
03751               to avoid the risk of I2C interrupt handle execution before current
03752               process unlock */
03753     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
03754
03755     return HAL_OK;
03756   }
03757   else
03758   {
03759     return HAL_BUSY;
03760   }
03761 }
03762
03763 /**
03764   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
03765   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03766   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03767   *                the configuration information for the specified I2C.
03768   * @param  DevAddress Target device address: The device 7 bits address value
03769   *         in datasheet must be shifted to the left before calling the interface
03770   * @param  pData Pointer to data buffer
03771   * @param  Size Amount of data to be sent
03772   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03773   * @retval HAL status
03774   */
03775 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03776                                                  uint16_t Size, uint32_t XferOptions)
03777 {
03778   uint32_t xfermode;
03779   uint32_t xferrequest = I2C_GENERATE_START_READ;
03780   HAL_StatusTypeDef dmaxferstatus;
03781
03782   /* Check the parameters */
03783   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03784
03785   if (hi2c->State == HAL_I2C_STATE_READY)
03786   {
03787     /* Process Locked */
03788     __HAL_LOCK(hi2c);
03789
03790     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03791     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03792     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03793
03794     /* Prepare transfer parameters */
03795     hi2c->pBuffPtr    = pData;
03796     hi2c->XferCount   = Size;
03797     hi2c->XferOptions = XferOptions;
03798     hi2c->XferISR     = I2C_Master_ISR_DMA;
03799
03800     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03801     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03802     {
03803       hi2c->XferSize = MAX_NBYTE_SIZE;
03804       xfermode = I2C_RELOAD_MODE;
03805     }
03806     else
03807     {
03808       hi2c->XferSize = hi2c->XferCount;
03809       xfermode = hi2c->XferOptions;
03810     }
03811
03812     /* If transfer direction not change and there is no request to start another frame,
03813        do not generate Restart Condition */
03814     /* Mean Previous state is same as current state */
03815     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
03816         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03817     {
03818       xferrequest = I2C_NO_STARTSTOP;
03819     }
03820     else
03821     {
03822       /* Convert OTHER_xxx XferOptions if any */
03823       I2C_ConvertOtherXferOptions(hi2c);
03824
03825       /* Update xfermode accordingly if no reload is necessary */
03826       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03827       {
03828         xfermode = hi2c->XferOptions;
03829       }
03830     }
03831
03832     if (hi2c->XferSize > 0U)
03833     {
03834       if (hi2c->hdmarx != NULL)
03835       {
03836         /* Set the I2C DMA transfer complete callback */
03837         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03838
03839         /* Set the DMA error callback */
03840         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03841
03842         /* Set the unused DMA callbacks to NULL */
03843         hi2c->hdmarx->XferHalfCpltCallback = NULL;
03844         hi2c->hdmarx->XferAbortCallback = NULL;
03845
03846         /* Enable the DMA channel */
03847         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
03848                                          hi2c->XferSize);
03849       }
03850       else
03851       {
03852         /* Update I2C state */
03853         hi2c->State     = HAL_I2C_STATE_READY;
03854         hi2c->Mode      = HAL_I2C_MODE_NONE;
03855
03856         /* Update I2C error code */
03857         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03858
03859         /* Process Unlocked */
03860         __HAL_UNLOCK(hi2c);
03861
03862         return HAL_ERROR;
03863       }
03864
03865       if (dmaxferstatus == HAL_OK)
03866       {
03867         /* Send Slave Address and set NBYTES to read */
03868         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03869
03870         /* Update XferCount value */
03871         hi2c->XferCount -= hi2c->XferSize;
03872
03873         /* Process Unlocked */
03874         __HAL_UNLOCK(hi2c);
03875
03876         /* Note : The I2C interrupts must be enabled after unlocking current process
03877                   to avoid the risk of I2C interrupt handle execution before current
03878                   process unlock */
03879         /* Enable ERR and NACK interrupts */
03880         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03881
03882         /* Enable DMA Request */
03883         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03884       }
03885       else
03886       {
03887         /* Update I2C state */
03888         hi2c->State     = HAL_I2C_STATE_READY;
03889         hi2c->Mode      = HAL_I2C_MODE_NONE;
03890
03891         /* Update I2C error code */
03892         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03893
03894         /* Process Unlocked */
03895         __HAL_UNLOCK(hi2c);
03896
03897         return HAL_ERROR;
03898       }
03899     }
03900     else
03901     {
03902       /* Update Transfer ISR function pointer */
03903       hi2c->XferISR = I2C_Master_ISR_IT;
03904
03905       /* Send Slave Address */
03906       /* Set NBYTES to read and generate START condition */
03907       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
03908                          I2C_GENERATE_START_READ);
03909
03910       /* Process Unlocked */
03911       __HAL_UNLOCK(hi2c);
03912
03913       /* Note : The I2C interrupts must be enabled after unlocking current process
03914                 to avoid the risk of I2C interrupt handle execution before current
03915                 process unlock */
03916       /* Enable ERR, TC, STOP, NACK, RXI interrupt */
03917       /* possible to enable all of these */
03918       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03919         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03920       I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
03921     }
03922
03923     return HAL_OK;
03924   }
03925   else
03926   {
03927     return HAL_BUSY;
03928   }
03929 }
03930
03931 /**
03932   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03933   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03934   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03935   *                the configuration information for the specified I2C.
03936   * @param  pData Pointer to data buffer
03937   * @param  Size Amount of data to be sent
03938   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03939   * @retval HAL status
03940   */
03941 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
03942                                                 uint32_t XferOptions)
03943 {
03944   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03945   FlagStatus tmp;
03946
03947   /* Check the parameters */
03948   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03949
03950   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03951   {
03952     if ((pData == NULL) || (Size == 0U))
03953     {
03954       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03955       return  HAL_ERROR;
03956     }
03957
03958     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03959     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03960
03961     /* Process Locked */
03962     __HAL_LOCK(hi2c);
03963
03964     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03965     /* and then toggle the HAL slave RX state to TX state */
03966     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03967     {
03968       /* Disable associated Interrupts */
03969       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03970
03971       /* Abort DMA Xfer if any */
03972       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03973       {
03974         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03975
03976         if (hi2c->hdmarx != NULL)
03977         {
03978           /* Set the I2C DMA Abort callback :
03979            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03980           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03981
03982           /* Abort DMA RX */
03983           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03984           {
03985             /* Call Directly XferAbortCallback function in case of error */
03986             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03987           }
03988         }
03989       }
03990     }
03991
03992     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03993     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03994     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03995
03996     /* Enable Address Acknowledge */
03997     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03998
03999     /* Prepare transfer parameters */
04000     hi2c->pBuffPtr    = pData;
04001     hi2c->XferCount   = Size;
04002     hi2c->XferSize    = hi2c->XferCount;
04003     hi2c->XferOptions = XferOptions;
04004     hi2c->XferISR     = I2C_Slave_ISR_IT;
04005
04006     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04007     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
04008     {
04009       /* Clear ADDR flag after prepare the transfer parameters */
04010       /* This action will generate an acknowledge to the Master */
04011       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04012     }
04013
04014     /* Process Unlocked */
04015     __HAL_UNLOCK(hi2c);
04016
04017     /* Note : The I2C interrupts must be enabled after unlocking current process
04018     to avoid the risk of I2C interrupt handle execution before current
04019     process unlock */
04020     /* REnable ADDR interrupt */
04021     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
04022
04023     return HAL_OK;
04024   }
04025   else
04026   {
04027     return HAL_ERROR;
04028   }
04029 }
04030
04031 /**
04032   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
04033   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04034   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04035   *                the configuration information for the specified I2C.
04036   * @param  pData Pointer to data buffer
04037   * @param  Size Amount of data to be sent
04038   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04039   * @retval HAL status
04040   */
04041 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
04042                                                  uint32_t XferOptions)
04043 {
04044   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04045   FlagStatus tmp;
04046   HAL_StatusTypeDef dmaxferstatus;
04047
04048   /* Check the parameters */
04049   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04050
04051   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04052   {
04053     if ((pData == NULL) || (Size == 0U))
04054     {
04055       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04056       return  HAL_ERROR;
04057     }
04058
04059     /* Process Locked */
04060     __HAL_LOCK(hi2c);
04061
04062     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04063     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
04064
04065     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04066     /* and then toggle the HAL slave RX state to TX state */
04067     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
04068     {
04069       /* Disable associated Interrupts */
04070       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
04071
04072       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04073       {
04074         /* Abort DMA Xfer if any */
04075         if (hi2c->hdmarx != NULL)
04076         {
04077           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04078
04079           /* Set the I2C DMA Abort callback :
04080           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04081           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04082
04083           /* Abort DMA RX */
04084           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04085           {
04086             /* Call Directly XferAbortCallback function in case of error */
04087             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04088           }
04089         }
04090       }
04091     }
04092     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04093     {
04094       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04095       {
04096         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04097
04098         /* Abort DMA Xfer if any */
04099         if (hi2c->hdmatx != NULL)
04100         {
04101           /* Set the I2C DMA Abort callback :
04102           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04103           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04104
04105           /* Abort DMA TX */
04106           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04107           {
04108             /* Call Directly XferAbortCallback function in case of error */
04109             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04110           }
04111         }
04112       }
04113     }
04114     else
04115     {
04116       /* Nothing to do */
04117     }
04118
04119     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
04120     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04121     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04122
04123     /* Enable Address Acknowledge */
04124     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04125
04126     /* Prepare transfer parameters */
04127     hi2c->pBuffPtr    = pData;
04128     hi2c->XferCount   = Size;
04129     hi2c->XferSize    = hi2c->XferCount;
04130     hi2c->XferOptions = XferOptions;
04131     hi2c->XferISR     = I2C_Slave_ISR_DMA;
04132
04133     if (hi2c->hdmatx != NULL)
04134     {
04135       /* Set the I2C DMA transfer complete callback */
04136       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
04137
04138       /* Set the DMA error callback */
04139       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
04140
04141       /* Set the unused DMA callbacks to NULL */
04142       hi2c->hdmatx->XferHalfCpltCallback = NULL;
04143       hi2c->hdmatx->XferAbortCallback = NULL;
04144
04145       /* Enable the DMA channel */
04146       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
04147                                        hi2c->XferSize);
04148     }
04149     else
04150     {
04151       /* Update I2C state */
04152       hi2c->State     = HAL_I2C_STATE_LISTEN;
04153       hi2c->Mode      = HAL_I2C_MODE_NONE;
04154
04155       /* Update I2C error code */
04156       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
04157
04158       /* Process Unlocked */
04159       __HAL_UNLOCK(hi2c);
04160
04161       return HAL_ERROR;
04162     }
04163
04164     if (dmaxferstatus == HAL_OK)
04165     {
04166       /* Update XferCount value */
04167       hi2c->XferCount -= hi2c->XferSize;
04168
04169       /* Reset XferSize */
04170       hi2c->XferSize = 0;
04171     }
04172     else
04173     {
04174       /* Update I2C state */
04175       hi2c->State     = HAL_I2C_STATE_LISTEN;
04176       hi2c->Mode      = HAL_I2C_MODE_NONE;
04177
04178       /* Update I2C error code */
04179       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04180
04181       /* Process Unlocked */
04182       __HAL_UNLOCK(hi2c);
04183
04184       return HAL_ERROR;
04185     }
04186
04187     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04188     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
04189     {
04190       /* Clear ADDR flag after prepare the transfer parameters */
04191       /* This action will generate an acknowledge to the Master */
04192       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04193     }
04194
04195     /* Process Unlocked */
04196     __HAL_UNLOCK(hi2c);
04197
04198     /* Enable DMA Request */
04199     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
04200
04201     /* Note : The I2C interrupts must be enabled after unlocking current process
04202     to avoid the risk of I2C interrupt handle execution before current
04203     process unlock */
04204     /* Enable ERR, STOP, NACK, ADDR interrupts */
04205     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04206
04207     return HAL_OK;
04208   }
04209   else
04210   {
04211     return HAL_ERROR;
04212   }
04213 }
04214
04215 /**
04216   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
04217   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04218   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04219   *                the configuration information for the specified I2C.
04220   * @param  pData Pointer to data buffer
04221   * @param  Size Amount of data to be sent
04222   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04223   * @retval HAL status
04224   */
04225 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
04226                                                uint32_t XferOptions)
04227 {
04228   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04229   FlagStatus tmp;
04230
04231   /* Check the parameters */
04232   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04233
04234   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04235   {
04236     if ((pData == NULL) || (Size == 0U))
04237     {
04238       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04239       return  HAL_ERROR;
04240     }
04241
04242     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04243     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04244
04245     /* Process Locked */
04246     __HAL_LOCK(hi2c);
04247
04248     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04249     /* and then toggle the HAL slave TX state to RX state */
04250     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04251     {
04252       /* Disable associated Interrupts */
04253       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04254
04255       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04256       {
04257         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04258
04259         /* Abort DMA Xfer if any */
04260         if (hi2c->hdmatx != NULL)
04261         {
04262           /* Set the I2C DMA Abort callback :
04263            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04264           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04265
04266           /* Abort DMA TX */
04267           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04268           {
04269             /* Call Directly XferAbortCallback function in case of error */
04270             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04271           }
04272         }
04273       }
04274     }
04275
04276     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04277     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04278     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04279
04280     /* Enable Address Acknowledge */
04281     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04282
04283     /* Prepare transfer parameters */
04284     hi2c->pBuffPtr    = pData;
04285     hi2c->XferCount   = Size;
04286     hi2c->XferSize    = hi2c->XferCount;
04287     hi2c->XferOptions = XferOptions;
04288     hi2c->XferISR     = I2C_Slave_ISR_IT;
04289
04290     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04291     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
04292     {
04293       /* Clear ADDR flag after prepare the transfer parameters */
04294       /* This action will generate an acknowledge to the Master */
04295       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04296     }
04297
04298     /* Process Unlocked */
04299     __HAL_UNLOCK(hi2c);
04300
04301     /* Note : The I2C interrupts must be enabled after unlocking current process
04302     to avoid the risk of I2C interrupt handle execution before current
04303     process unlock */
04304     /* REnable ADDR interrupt */
04305     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04306
04307     return HAL_OK;
04308   }
04309   else
04310   {
04311     return HAL_ERROR;
04312   }
04313 }
04314
04315 /**
04316   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
04317   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04318   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04319   *                the configuration information for the specified I2C.
04320   * @param  pData Pointer to data buffer
04321   * @param  Size Amount of data to be sent
04322   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04323   * @retval HAL status
04324   */
04325 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
04326                                                 uint32_t XferOptions)
04327 {
04328   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04329   FlagStatus tmp;
04330   HAL_StatusTypeDef dmaxferstatus;
04331
04332   /* Check the parameters */
04333   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04334
04335   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04336   {
04337     if ((pData == NULL) || (Size == 0U))
04338     {
04339       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04340       return  HAL_ERROR;
04341     }
04342
04343     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04344     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04345
04346     /* Process Locked */
04347     __HAL_LOCK(hi2c);
04348
04349     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04350     /* and then toggle the HAL slave TX state to RX state */
04351     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04352     {
04353       /* Disable associated Interrupts */
04354       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04355
04356       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04357       {
04358         /* Abort DMA Xfer if any */
04359         if (hi2c->hdmatx != NULL)
04360         {
04361           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04362
04363           /* Set the I2C DMA Abort callback :
04364            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04365           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04366
04367           /* Abort DMA TX */
04368           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04369           {
04370             /* Call Directly XferAbortCallback function in case of error */
04371             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04372           }
04373         }
04374       }
04375     }
04376     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
04377     {
04378       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04379       {
04380         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04381
04382         /* Abort DMA Xfer if any */
04383         if (hi2c->hdmarx != NULL)
04384         {
04385           /* Set the I2C DMA Abort callback :
04386            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04387           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04388
04389           /* Abort DMA RX */
04390           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04391           {
04392             /* Call Directly XferAbortCallback function in case of error */
04393             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04394           }
04395         }
04396       }
04397     }
04398     else
04399     {
04400       /* Nothing to do */
04401     }
04402
04403     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04404     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04405     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04406
04407     /* Enable Address Acknowledge */
04408     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04409
04410     /* Prepare transfer parameters */
04411     hi2c->pBuffPtr    = pData;
04412     hi2c->XferCount   = Size;
04413     hi2c->XferSize    = hi2c->XferCount;
04414     hi2c->XferOptions = XferOptions;
04415     hi2c->XferISR     = I2C_Slave_ISR_DMA;
04416
04417     if (hi2c->hdmarx != NULL)
04418     {
04419       /* Set the I2C DMA transfer complete callback */
04420       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
04421
04422       /* Set the DMA error callback */
04423       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
04424
04425       /* Set the unused DMA callbacks to NULL */
04426       hi2c->hdmarx->XferHalfCpltCallback = NULL;
04427       hi2c->hdmarx->XferAbortCallback = NULL;
04428
04429       /* Enable the DMA channel */
04430       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
04431                                        (uint32_t)pData, hi2c->XferSize);
04432     }
04433     else
04434     {
04435       /* Update I2C state */
04436       hi2c->State     = HAL_I2C_STATE_LISTEN;
04437       hi2c->Mode      = HAL_I2C_MODE_NONE;
04438
04439       /* Update I2C error code */
04440       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
04441
04442       /* Process Unlocked */
04443       __HAL_UNLOCK(hi2c);
04444
04445       return HAL_ERROR;
04446     }
04447
04448     if (dmaxferstatus == HAL_OK)
04449     {
04450       /* Update XferCount value */
04451       hi2c->XferCount -= hi2c->XferSize;
04452
04453       /* Reset XferSize */
04454       hi2c->XferSize = 0;
04455     }
04456     else
04457     {
04458       /* Update I2C state */
04459       hi2c->State     = HAL_I2C_STATE_LISTEN;
04460       hi2c->Mode      = HAL_I2C_MODE_NONE;
04461
04462       /* Update I2C error code */
04463       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04464
04465       /* Process Unlocked */
04466       __HAL_UNLOCK(hi2c);
04467
04468       return HAL_ERROR;
04469     }
04470
04471     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04472     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
04473     {
04474       /* Clear ADDR flag after prepare the transfer parameters */
04475       /* This action will generate an acknowledge to the Master */
04476       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04477     }
04478
04479     /* Process Unlocked */
04480     __HAL_UNLOCK(hi2c);
04481
04482     /* Enable DMA Request */
04483     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04484
04485     /* Note : The I2C interrupts must be enabled after unlocking current process
04486     to avoid the risk of I2C interrupt handle execution before current
04487     process unlock */
04488     /* REnable ADDR interrupt */
04489     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04490
04491     return HAL_OK;
04492   }
04493   else
04494   {
04495     return HAL_ERROR;
04496   }
04497 }
04498
04499 /**
04500   * @brief  Enable the Address listen mode with Interrupt.
04501   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04502   *                the configuration information for the specified I2C.
04503   * @retval HAL status
04504   */
04505 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
04506 {
04507   if (hi2c->State == HAL_I2C_STATE_READY)
04508   {
04509     hi2c->State = HAL_I2C_STATE_LISTEN;
04510     hi2c->XferISR = I2C_Slave_ISR_IT;
04511
04512     /* Enable the Address Match interrupt */
04513     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04514
04515     return HAL_OK;
04516   }
04517   else
04518   {
04519     return HAL_BUSY;
04520   }
04521 }
04522
04523 /**
04524   * @brief  Disable the Address listen mode with Interrupt.
04525   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04526   *                the configuration information for the specified I2C
04527   * @retval HAL status
04528   */
04529 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
04530 {
04531   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04532   uint32_t tmp;
04533
04534   /* Disable Address listen mode only if a transfer is not ongoing */
04535   if (hi2c->State == HAL_I2C_STATE_LISTEN)
04536   {
04537     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
04538     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
04539     hi2c->State = HAL_I2C_STATE_READY;
04540     hi2c->Mode = HAL_I2C_MODE_NONE;
04541     hi2c->XferISR = NULL;
04542
04543     /* Disable the Address Match interrupt */
04544     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04545
04546     return HAL_OK;
04547   }
04548   else
04549   {
04550     return HAL_BUSY;
04551   }
04552 }
04553
04554 /**
04555   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
04556   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04557   *                the configuration information for the specified I2C.
04558   * @param  DevAddress Target device address: The device 7 bits address value
04559   *         in datasheet must be shifted to the left before calling the interface
04560   * @retval HAL status
04561   */
04562 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
04563 {
04564   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
04565   {
04566     /* Process Locked */
04567     __HAL_LOCK(hi2c);
04568
04569     /* Disable Interrupts and Store Previous state */
04570     if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
04571     {
04572       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04573       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
04574     }
04575     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04576     {
04577       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
04578       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
04579     }
04580     else
04581     {
04582       /* Do nothing */
04583     }
04584
04585     /* Set State at HAL_I2C_STATE_ABORT */
04586     hi2c->State = HAL_I2C_STATE_ABORT;
04587
04588     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
04589     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
04590     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
04591
04592     /* Process Unlocked */
04593     __HAL_UNLOCK(hi2c);
04594
04595     /* Note : The I2C interrupts must be enabled after unlocking current process
04596               to avoid the risk of I2C interrupt handle execution before current
04597               process unlock */
04598     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04599
04600     return HAL_OK;
04601   }
04602   else
04603   {
04604     /* Wrong usage of abort function */
04605     /* This function should be used only in case of abort monitored by master device */
04606     return HAL_ERROR;
04607   }
04608 }
04609
04610 /**
04611   * @}
04612   */
04613
04614 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
04615   * @{
04616   */
04617
04618 /**
04619   * @brief  This function handles I2C event interrupt request.
04620   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04621   *                the configuration information for the specified I2C.
04622   * @retval None
04623   */
04624 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
04625 {
04626   /* Get current IT Flags and IT sources value */
04627   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04628   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04629
04630   /* I2C events treatment -------------------------------------*/
04631   if (hi2c->XferISR != NULL)
04632   {
04633     hi2c->XferISR(hi2c, itflags, itsources);
04634   }
04635 }
04636
04637 /**
04638   * @brief  This function handles I2C error interrupt request.
04639   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04640   *                the configuration information for the specified I2C.
04641   * @retval None
04642   */
04643 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
04644 {
04645   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04646   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04647   uint32_t tmperror;
04648
04649   /* I2C Bus error interrupt occurred ------------------------------------*/
04650   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
04651       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04652   {
04653     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
04654
04655     /* Clear BERR flag */
04656     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
04657   }
04658
04659   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
04660   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
04661       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04662   {
04663     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
04664
04665     /* Clear OVR flag */
04666     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
04667   }
04668
04669   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
04670   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
04671       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04672   {
04673     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
04674
04675     /* Clear ARLO flag */
04676     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
04677   }
04678
04679   /* Store current volatile hi2c->ErrorCode, misra rule */
04680   tmperror = hi2c->ErrorCode;
04681
04682   /* Call the Error Callback in case of Error detected */
04683   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
04684   {
04685     I2C_ITError(hi2c, tmperror);
04686   }
04687 }
04688
04689 /**
04690   * @brief  Master Tx Transfer completed callback.
04691   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04692   *                the configuration information for the specified I2C.
04693   * @retval None
04694   */
04695 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
04696 {
04697   /* Prevent unused argument(s) compilation warning */
04698   UNUSED(hi2c);
04699
04700   /* NOTE : This function should not be modified, when the callback is needed,
04701             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
04702    */
04703 }
04704
04705 /**
04706   * @brief  Master Rx Transfer completed callback.
04707   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04708   *                the configuration information for the specified I2C.
04709   * @retval None
04710   */
04711 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
04712 {
04713   /* Prevent unused argument(s) compilation warning */
04714   UNUSED(hi2c);
04715
04716   /* NOTE : This function should not be modified, when the callback is needed,
04717             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
04718    */
04719 }
04720
04721 /** @brief  Slave Tx Transfer completed callback.
04722   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04723   *                the configuration information for the specified I2C.
04724   * @retval None
04725   */
04726 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
04727 {
04728   /* Prevent unused argument(s) compilation warning */
04729   UNUSED(hi2c);
04730
04731   /* NOTE : This function should not be modified, when the callback is needed,
04732             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
04733    */
04734 }
04735
04736 /**
04737   * @brief  Slave Rx Transfer completed callback.
04738   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04739   *                the configuration information for the specified I2C.
04740   * @retval None
04741   */
04742 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
04743 {
04744   /* Prevent unused argument(s) compilation warning */
04745   UNUSED(hi2c);
04746
04747   /* NOTE : This function should not be modified, when the callback is needed,
04748             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
04749    */
04750 }
04751
04752 /**
04753   * @brief  Slave Address Match callback.
04754   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04755   *                the configuration information for the specified I2C.
04756   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
04757   * @param  AddrMatchCode Address Match Code
04758   * @retval None
04759   */
04760 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
04761 {
04762   /* Prevent unused argument(s) compilation warning */
04763   UNUSED(hi2c);
04764   UNUSED(TransferDirection);
04765   UNUSED(AddrMatchCode);
04766
04767   /* NOTE : This function should not be modified, when the callback is needed,
04768             the HAL_I2C_AddrCallback() could be implemented in the user file
04769    */
04770 }
04771
04772 /**
04773   * @brief  Listen Complete callback.
04774   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04775   *                the configuration information for the specified I2C.
04776   * @retval None
04777   */
04778 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
04779 {
04780   /* Prevent unused argument(s) compilation warning */
04781   UNUSED(hi2c);
04782
04783   /* NOTE : This function should not be modified, when the callback is needed,
04784             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
04785    */
04786 }
04787
04788 /**
04789   * @brief  Memory Tx Transfer completed callback.
04790   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04791   *                the configuration information for the specified I2C.
04792   * @retval None
04793   */
04794 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
04795 {
04796   /* Prevent unused argument(s) compilation warning */
04797   UNUSED(hi2c);
04798
04799   /* NOTE : This function should not be modified, when the callback is needed,
04800             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
04801    */
04802 }
04803
04804 /**
04805   * @brief  Memory Rx Transfer completed callback.
04806   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04807   *                the configuration information for the specified I2C.
04808   * @retval None
04809   */
04810 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
04811 {
04812   /* Prevent unused argument(s) compilation warning */
04813   UNUSED(hi2c);
04814
04815   /* NOTE : This function should not be modified, when the callback is needed,
04816             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
04817    */
04818 }
04819
04820 /**
04821   * @brief  I2C error callback.
04822   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04823   *                the configuration information for the specified I2C.
04824   * @retval None
04825   */
04826 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
04827 {
04828   /* Prevent unused argument(s) compilation warning */
04829   UNUSED(hi2c);
04830
04831   /* NOTE : This function should not be modified, when the callback is needed,
04832             the HAL_I2C_ErrorCallback could be implemented in the user file
04833    */
04834 }
04835
04836 /**
04837   * @brief  I2C abort callback.
04838   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04839   *                the configuration information for the specified I2C.
04840   * @retval None
04841   */
04842 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
04843 {
04844   /* Prevent unused argument(s) compilation warning */
04845   UNUSED(hi2c);
04846
04847   /* NOTE : This function should not be modified, when the callback is needed,
04848             the HAL_I2C_AbortCpltCallback could be implemented in the user file
04849    */
04850 }
04851
04852 /**
04853   * @}
04854   */
04855
04856 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
04857   *  @brief   Peripheral State, Mode and Error functions
04858   *
04859 @verbatim
04860  ===============================================================================
04861             ##### Peripheral State, Mode and Error functions #####
04862  ===============================================================================
04863     [..]
04864     This subsection permit to get in run-time the status of the peripheral
04865     and the data flow.
04866
04867 @endverbatim
04868   * @{
04869   */
04870
04871 /**
04872   * @brief  Return the I2C handle state.
04873   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04874   *                the configuration information for the specified I2C.
04875   * @retval HAL state
04876   */
04877 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
04878 {
04879   /* Return I2C handle state */
04880   return hi2c->State;
04881 }
04882
04883 /**
04884   * @brief  Returns the I2C Master, Slave, Memory or no mode.
04885   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04886   *         the configuration information for I2C module
04887   * @retval HAL mode
04888   */
04889 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
04890 {
04891   return hi2c->Mode;
04892 }
04893
04894 /**
04895   * @brief  Return the I2C error code.
04896   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04897   *              the configuration information for the specified I2C.
04898   * @retval I2C Error Code
04899   */
04900 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
04901 {
04902   return hi2c->ErrorCode;
04903 }
04904
04905 /**
04906   * @}
04907   */
04908
04909 /**
04910   * @}
04911   */
04912
04913 /** @addtogroup I2C_Private_Functions
04914   * @{
04915   */
04916
04917 /**
04918   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
04919   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04920   *                the configuration information for the specified I2C.
04921   * @param  ITFlags Interrupt flags to handle.
04922   * @param  ITSources Interrupt sources enabled.
04923   * @retval HAL status
04924   */
04925 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
04926                                            uint32_t ITSources)
04927 {
04928   uint16_t devaddress;
04929   uint32_t tmpITFlags = ITFlags;
04930
04931   /* Process Locked */
04932   __HAL_LOCK(hi2c);
04933
04934   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
04935       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04936   {
04937     /* Clear NACK Flag */
04938     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04939
04940     /* Set corresponding Error Code */
04941     /* No need to generate STOP, it is automatically done */
04942     /* Error callback will be send during stop flag treatment */
04943     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04944
04945     /* Flush TX register */
04946     I2C_Flush_TXDR(hi2c);
04947   }
04948   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
04949            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04950   {
04951     /* Remove RXNE flag on temporary variable as read done */
04952     tmpITFlags &= ~I2C_FLAG_RXNE;
04953
04954     /* Read data from RXDR */
04955     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04956
04957     /* Increment Buffer pointer */
04958     hi2c->pBuffPtr++;
04959
04960     hi2c->XferSize--;
04961     hi2c->XferCount--;
04962   }
04963   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
04964            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
04965             (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
04966   {
04967     /* Write data to TXDR */
04968     if (hi2c->XferCount != 0U)
04969     {
04970       /* Write data to TXDR */
04971       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04972
04973       /* Increment Buffer pointer */
04974       hi2c->pBuffPtr++;
04975
04976       hi2c->XferSize--;
04977       hi2c->XferCount--;
04978     }
04979   }
04980   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
04981            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04982   {
04983     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
04984     {
04985       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04986
04987       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04988       {
04989         hi2c->XferSize = MAX_NBYTE_SIZE;
04990         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
04991       }
04992       else
04993       {
04994         hi2c->XferSize = hi2c->XferCount;
04995         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04996         {
04997           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
04998                              hi2c->XferOptions, I2C_NO_STARTSTOP);
04999         }
05000         else
05001         {
05002           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
05003                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
05004         }
05005       }
05006     }
05007     else
05008     {
05009       /* Call TxCpltCallback() if no stop mode is set */
05010       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05011       {
05012         /* Call I2C Master Sequential complete process */
05013         I2C_ITMasterSeqCplt(hi2c);
05014       }
05015       else
05016       {
05017         /* Wrong size Status regarding TCR flag event */
05018         /* Call the corresponding callback to inform upper layer of End of Transfer */
05019         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05020       }
05021     }
05022   }
05023   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
05024            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05025   {
05026     if (hi2c->XferCount == 0U)
05027     {
05028       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05029       {
05030         /* Generate a stop condition in case of no transfer option */
05031         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
05032         {
05033           /* Generate Stop */
05034           hi2c->Instance->CR2 |= I2C_CR2_STOP;
05035         }
05036         else
05037         {
05038           /* Call I2C Master Sequential complete process */
05039           I2C_ITMasterSeqCplt(hi2c);
05040         }
05041       }
05042     }
05043     else
05044     {
05045       /* Wrong size Status regarding TC flag event */
05046       /* Call the corresponding callback to inform upper layer of End of Transfer */
05047       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05048     }
05049   }
05050   else
05051   {
05052     /* Nothing to do */
05053   }
05054
05055   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
05056       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05057   {
05058     /* Call I2C Master complete process */
05059     I2C_ITMasterCplt(hi2c, tmpITFlags);
05060   }
05061
05062   /* Process Unlocked */
05063   __HAL_UNLOCK(hi2c);
05064
05065   return HAL_OK;
05066 }
05067
05068 /**
05069   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
05070   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05071   *                the configuration information for the specified I2C.
05072   * @param  ITFlags Interrupt flags to handle.
05073   * @param  ITSources Interrupt sources enabled.
05074   * @retval HAL status
05075   */
05076 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05077                                         uint32_t ITSources)
05078 {
05079   uint32_t direction = I2C_GENERATE_START_WRITE;
05080   uint32_t tmpITFlags = ITFlags;
05081
05082   /* Process Locked */
05083   __HAL_LOCK(hi2c);
05084
05085   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
05086       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05087   {
05088     /* Clear NACK Flag */
05089     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05090
05091     /* Set corresponding Error Code */
05092     /* No need to generate STOP, it is automatically done */
05093     /* Error callback will be send during stop flag treatment */
05094     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05095
05096     /* Flush TX register */
05097     I2C_Flush_TXDR(hi2c);
05098   }
05099   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
05100            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
05101   {
05102     /* Remove RXNE flag on temporary variable as read done */
05103     tmpITFlags &= ~I2C_FLAG_RXNE;
05104
05105     /* Read data from RXDR */
05106     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05107
05108     /* Increment Buffer pointer */
05109     hi2c->pBuffPtr++;
05110
05111     hi2c->XferSize--;
05112     hi2c->XferCount--;
05113   }
05114   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
05115            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
05116   {
05117     if (hi2c->Memaddress == 0xFFFFFFFFU)
05118     {
05119       /* Write data to TXDR */
05120       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
05121
05122       /* Increment Buffer pointer */
05123       hi2c->pBuffPtr++;
05124
05125       hi2c->XferSize--;
05126       hi2c->XferCount--;
05127     }
05128     else
05129     {
05130       /* Write LSB part of Memory Address */
05131       hi2c->Instance->TXDR = hi2c->Memaddress;
05132
05133       /* Reset Memaddress content */
05134       hi2c->Memaddress = 0xFFFFFFFFU;
05135     }
05136   }
05137   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
05138            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05139   {
05140     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
05141     {
05142       if (hi2c->XferCount > MAX_NBYTE_SIZE)
05143       {
05144         hi2c->XferSize = MAX_NBYTE_SIZE;
05145         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05146                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
05147       }
05148       else
05149       {
05150         hi2c->XferSize = hi2c->XferCount;
05151         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05152                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
05153       }
05154     }
05155     else
05156     {
05157       /* Wrong size Status regarding TCR flag event */
05158       /* Call the corresponding callback to inform upper layer of End of Transfer */
05159       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05160     }
05161   }
05162   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
05163            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05164   {
05165     /* Disable Interrupt related to address step */
05166     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05167
05168     /* Enable ERR, TC, STOP, NACK and RXI interrupts */
05169     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
05170
05171     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05172     {
05173       direction = I2C_GENERATE_START_READ;
05174     }
05175
05176     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05177     {
05178       hi2c->XferSize = MAX_NBYTE_SIZE;
05179
05180       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
05181       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05182                          I2C_RELOAD_MODE, direction);
05183     }
05184     else
05185     {
05186       hi2c->XferSize = hi2c->XferCount;
05187
05188       /* Set NBYTES to write and generate RESTART */
05189       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05190                          I2C_AUTOEND_MODE, direction);
05191     }
05192   }
05193   else
05194   {
05195     /* Nothing to do */
05196   }
05197
05198   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
05199       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05200   {
05201     /* Call I2C Master complete process */
05202     I2C_ITMasterCplt(hi2c, tmpITFlags);
05203   }
05204
05205   /* Process Unlocked */
05206   __HAL_UNLOCK(hi2c);
05207
05208   return HAL_OK;
05209 }
05210
05211 /**
05212   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
05213   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05214   *                the configuration information for the specified I2C.
05215   * @param  ITFlags Interrupt flags to handle.
05216   * @param  ITSources Interrupt sources enabled.
05217   * @retval HAL status
05218   */
05219 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05220                                           uint32_t ITSources)
05221 {
05222   uint32_t tmpoptions = hi2c->XferOptions;
05223   uint32_t tmpITFlags = ITFlags;
05224
05225   /* Process locked */
05226   __HAL_LOCK(hi2c);
05227
05228   /* Check if STOPF is set */
05229   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
05230       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05231   {
05232     /* Call I2C Slave complete process */
05233     I2C_ITSlaveCplt(hi2c, tmpITFlags);
05234   }
05235   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
05236            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05237   {
05238     /* Check that I2C transfer finished */
05239     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05240     /* Mean XferCount == 0*/
05241     /* So clear Flag NACKF only */
05242     if (hi2c->XferCount == 0U)
05243     {
05244       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
05245         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
05246            Warning[Pa134]: left and right operands are identical */
05247       {
05248         /* Call I2C Listen complete process */
05249         I2C_ITListenCplt(hi2c, tmpITFlags);
05250       }
05251       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05252       {
05253         /* Clear NACK Flag */
05254         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05255
05256         /* Flush TX register */
05257         I2C_Flush_TXDR(hi2c);
05258
05259         /* Last Byte is Transmitted */
05260         /* Call I2C Slave Sequential complete process */
05261         I2C_ITSlaveSeqCplt(hi2c);
05262       }
05263       else
05264       {
05265         /* Clear NACK Flag */
05266         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05267       }
05268     }
05269     else
05270     {
05271       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05272       /* Clear NACK Flag */
05273       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05274
05275       /* Set ErrorCode corresponding to a Non-Acknowledge */
05276       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05277
05278       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05279       {
05280         /* Call the corresponding callback to inform upper layer of End of Transfer */
05281         I2C_ITError(hi2c, hi2c->ErrorCode);
05282       }
05283     }
05284   }
05285   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
05286            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
05287   {
05288     if (hi2c->XferCount > 0U)
05289     {
05290       /* Read data from RXDR */
05291       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05292
05293       /* Increment Buffer pointer */
05294       hi2c->pBuffPtr++;
05295
05296       hi2c->XferSize--;
05297       hi2c->XferCount--;
05298     }
05299
05300     if ((hi2c->XferCount == 0U) && \
05301         (tmpoptions != I2C_NO_OPTION_FRAME))
05302     {
05303       /* Call I2C Slave Sequential complete process */
05304       I2C_ITSlaveSeqCplt(hi2c);
05305     }
05306   }
05307   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
05308            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05309   {
05310     I2C_ITAddrCplt(hi2c, tmpITFlags);
05311   }
05312   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
05313            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
05314   {
05315     /* Write data to TXDR only if XferCount not reach "0" */
05316     /* A TXIS flag can be set, during STOP treatment      */
05317     /* Check if all Data have already been sent */
05318     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
05319     if (hi2c->XferCount > 0U)
05320     {
05321       /* Write data to TXDR */
05322       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
05323
05324       /* Increment Buffer pointer */
05325       hi2c->pBuffPtr++;
05326
05327       hi2c->XferCount--;
05328       hi2c->XferSize--;
05329     }
05330     else
05331     {
05332       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
05333       {
05334         /* Last Byte is Transmitted */
05335         /* Call I2C Slave Sequential complete process */
05336         I2C_ITSlaveSeqCplt(hi2c);
05337       }
05338     }
05339   }
05340   else
05341   {
05342     /* Nothing to do */
05343   }
05344
05345   /* Process Unlocked */
05346   __HAL_UNLOCK(hi2c);
05347
05348   return HAL_OK;
05349 }
05350
05351 /**
05352   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
05353   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05354   *                the configuration information for the specified I2C.
05355   * @param  ITFlags Interrupt flags to handle.
05356   * @param  ITSources Interrupt sources enabled.
05357   * @retval HAL status
05358   */
05359 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05360                                             uint32_t ITSources)
05361 {
05362   uint16_t devaddress;
05363   uint32_t xfermode;
05364
05365   /* Process Locked */
05366   __HAL_LOCK(hi2c);
05367
05368   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05369       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05370   {
05371     /* Clear NACK Flag */
05372     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05373
05374     /* Set corresponding Error Code */
05375     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05376
05377     /* No need to generate STOP, it is automatically done */
05378     /* But enable STOP interrupt, to treat it */
05379     /* Error callback will be send during stop flag treatment */
05380     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05381
05382     /* Flush TX register */
05383     I2C_Flush_TXDR(hi2c);
05384   }
05385   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
05386            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05387   {
05388     /* Disable TC interrupt */
05389     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
05390
05391     if (hi2c->XferCount != 0U)
05392     {
05393       /* Recover Slave address */
05394       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
05395
05396       /* Prepare the new XferSize to transfer */
05397       if (hi2c->XferCount > MAX_NBYTE_SIZE)
05398       {
05399         hi2c->XferSize = MAX_NBYTE_SIZE;
05400         xfermode = I2C_RELOAD_MODE;
05401       }
05402       else
05403       {
05404         hi2c->XferSize = hi2c->XferCount;
05405         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
05406         {
05407           xfermode = hi2c->XferOptions;
05408         }
05409         else
05410         {
05411           xfermode = I2C_AUTOEND_MODE;
05412         }
05413       }
05414
05415       /* Set the new XferSize in Nbytes register */
05416       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
05417
05418       /* Update XferCount value */
05419       hi2c->XferCount -= hi2c->XferSize;
05420
05421       /* Enable DMA Request */
05422       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05423       {
05424         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05425       }
05426       else
05427       {
05428         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05429       }
05430     }
05431     else
05432     {
05433       /* Call TxCpltCallback() if no stop mode is set */
05434       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05435       {
05436         /* Call I2C Master Sequential complete process */
05437         I2C_ITMasterSeqCplt(hi2c);
05438       }
05439       else
05440       {
05441         /* Wrong size Status regarding TCR flag event */
05442         /* Call the corresponding callback to inform upper layer of End of Transfer */
05443         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05444       }
05445     }
05446   }
05447   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
05448            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05449   {
05450     if (hi2c->XferCount == 0U)
05451     {
05452       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05453       {
05454         /* Generate a stop condition in case of no transfer option */
05455         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
05456         {
05457           /* Generate Stop */
05458           hi2c->Instance->CR2 |= I2C_CR2_STOP;
05459         }
05460         else
05461         {
05462           /* Call I2C Master Sequential complete process */
05463           I2C_ITMasterSeqCplt(hi2c);
05464         }
05465       }
05466     }
05467     else
05468     {
05469       /* Wrong size Status regarding TC flag event */
05470       /* Call the corresponding callback to inform upper layer of End of Transfer */
05471       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05472     }
05473   }
05474   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05475            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05476   {
05477     /* Call I2C Master complete process */
05478     I2C_ITMasterCplt(hi2c, ITFlags);
05479   }
05480   else
05481   {
05482     /* Nothing to do */
05483   }
05484
05485   /* Process Unlocked */
05486   __HAL_UNLOCK(hi2c);
05487
05488   return HAL_OK;
05489 }
05490
05491 /**
05492   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
05493   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05494   *                the configuration information for the specified I2C.
05495   * @param  ITFlags Interrupt flags to handle.
05496   * @param  ITSources Interrupt sources enabled.
05497   * @retval HAL status
05498   */
05499 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05500                                          uint32_t ITSources)
05501 {
05502   uint32_t direction = I2C_GENERATE_START_WRITE;
05503
05504   /* Process Locked */
05505   __HAL_LOCK(hi2c);
05506
05507   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05508       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05509   {
05510     /* Clear NACK Flag */
05511     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05512
05513     /* Set corresponding Error Code */
05514     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05515
05516     /* No need to generate STOP, it is automatically done */
05517     /* But enable STOP interrupt, to treat it */
05518     /* Error callback will be send during stop flag treatment */
05519     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05520
05521     /* Flush TX register */
05522     I2C_Flush_TXDR(hi2c);
05523   }
05524   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
05525            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
05526   {
05527     /* Write LSB part of Memory Address */
05528     hi2c->Instance->TXDR = hi2c->Memaddress;
05529
05530     /* Reset Memaddress content */
05531     hi2c->Memaddress = 0xFFFFFFFFU;
05532   }
05533   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
05534            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05535   {
05536     /* Disable Interrupt related to address step */
05537     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05538
05539     /* Enable only Error interrupt */
05540     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
05541
05542     if (hi2c->XferCount != 0U)
05543     {
05544       /* Prepare the new XferSize to transfer */
05545       if (hi2c->XferCount > MAX_NBYTE_SIZE)
05546       {
05547         hi2c->XferSize = MAX_NBYTE_SIZE;
05548         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05549                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
05550       }
05551       else
05552       {
05553         hi2c->XferSize = hi2c->XferCount;
05554         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05555                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
05556       }
05557
05558       /* Update XferCount value */
05559       hi2c->XferCount -= hi2c->XferSize;
05560
05561       /* Enable DMA Request */
05562       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05563       {
05564         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05565       }
05566       else
05567       {
05568         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05569       }
05570     }
05571     else
05572     {
05573       /* Wrong size Status regarding TCR flag event */
05574       /* Call the corresponding callback to inform upper layer of End of Transfer */
05575       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05576     }
05577   }
05578   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
05579            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05580   {
05581     /* Disable Interrupt related to address step */
05582     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05583
05584     /* Enable only Error and NACK interrupt for data transfer */
05585     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
05586
05587     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05588     {
05589       direction = I2C_GENERATE_START_READ;
05590     }
05591
05592     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05593     {
05594       hi2c->XferSize = MAX_NBYTE_SIZE;
05595
05596       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
05597       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05598                          I2C_RELOAD_MODE, direction);
05599     }
05600     else
05601     {
05602       hi2c->XferSize = hi2c->XferCount;
05603
05604       /* Set NBYTES to write and generate RESTART */
05605       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05606                          I2C_AUTOEND_MODE, direction);
05607     }
05608
05609     /* Update XferCount value */
05610     hi2c->XferCount -= hi2c->XferSize;
05611
05612     /* Enable DMA Request */
05613     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05614     {
05615       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05616     }
05617     else
05618     {
05619       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05620     }
05621   }
05622   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05623            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05624   {
05625     /* Call I2C Master complete process */
05626     I2C_ITMasterCplt(hi2c, ITFlags);
05627   }
05628   else
05629   {
05630     /* Nothing to do */
05631   }
05632
05633   /* Process Unlocked */
05634   __HAL_UNLOCK(hi2c);
05635
05636   return HAL_OK;
05637 }
05638
05639 /**
05640   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
05641   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05642   *                the configuration information for the specified I2C.
05643   * @param  ITFlags Interrupt flags to handle.
05644   * @param  ITSources Interrupt sources enabled.
05645   * @retval HAL status
05646   */
05647 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05648                                            uint32_t ITSources)
05649 {
05650   uint32_t tmpoptions = hi2c->XferOptions;
05651   uint32_t treatdmanack = 0U;
05652   HAL_I2C_StateTypeDef tmpstate;
05653
05654   /* Process locked */
05655   __HAL_LOCK(hi2c);
05656
05657   /* Check if STOPF is set */
05658   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05659       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05660   {
05661     /* Call I2C Slave complete process */
05662     I2C_ITSlaveCplt(hi2c, ITFlags);
05663   }
05664   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05665            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05666   {
05667     /* Check that I2C transfer finished */
05668     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05669     /* Mean XferCount == 0 */
05670     /* So clear Flag NACKF only */
05671     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
05672         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
05673     {
05674       /* Split check of hdmarx, for MISRA compliance */
05675       if (hi2c->hdmarx != NULL)
05676       {
05677         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
05678         {
05679           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
05680           {
05681             treatdmanack = 1U;
05682           }
05683         }
05684       }
05685
05686       /* Split check of hdmatx, for MISRA compliance  */
05687       if (hi2c->hdmatx != NULL)
05688       {
05689         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
05690         {
05691           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
05692           {
05693             treatdmanack = 1U;
05694           }
05695         }
05696       }
05697
05698       if (treatdmanack == 1U)
05699       {
05700         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
05701           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
05702              Warning[Pa134]: left and right operands are identical */
05703         {
05704           /* Call I2C Listen complete process */
05705           I2C_ITListenCplt(hi2c, ITFlags);
05706         }
05707         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05708         {
05709           /* Clear NACK Flag */
05710           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05711
05712           /* Flush TX register */
05713           I2C_Flush_TXDR(hi2c);
05714
05715           /* Last Byte is Transmitted */
05716           /* Call I2C Slave Sequential complete process */
05717           I2C_ITSlaveSeqCplt(hi2c);
05718         }
05719         else
05720         {
05721           /* Clear NACK Flag */
05722           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05723         }
05724       }
05725       else
05726       {
05727         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05728         /* Clear NACK Flag */
05729         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05730
05731         /* Set ErrorCode corresponding to a Non-Acknowledge */
05732         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05733
05734         /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
05735         tmpstate = hi2c->State;
05736
05737         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05738         {
05739           if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
05740           {
05741             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
05742           }
05743           else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
05744           {
05745             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
05746           }
05747           else
05748           {
05749             /* Do nothing */
05750           }
05751
05752           /* Call the corresponding callback to inform upper layer of End of Transfer */
05753           I2C_ITError(hi2c, hi2c->ErrorCode);
05754         }
05755       }
05756     }
05757     else
05758     {
05759       /* Only Clear NACK Flag, no DMA treatment is pending */
05760       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05761     }
05762   }
05763   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
05764            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05765   {
05766     I2C_ITAddrCplt(hi2c, ITFlags);
05767   }
05768   else
05769   {
05770     /* Nothing to do */
05771   }
05772
05773   /* Process Unlocked */
05774   __HAL_UNLOCK(hi2c);
05775
05776   return HAL_OK;
05777 }
05778
05779 /**
05780   * @brief  Master sends target device address followed by internal memory address for write request.
05781   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05782   *                the configuration information for the specified I2C.
05783   * @param  DevAddress Target device address: The device 7 bits address value
05784   *         in datasheet must be shifted to the left before calling the interface
05785   * @param  MemAddress Internal memory address
05786   * @param  MemAddSize Size of internal memory address
05787   * @param  Timeout Timeout duration
05788   * @param  Tickstart Tick start value
05789   * @retval HAL status
05790   */
05791 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
05792                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
05793                                                 uint32_t Tickstart)
05794 {
05795   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
05796
05797   /* Wait until TXIS flag is set */
05798   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05799   {
05800     return HAL_ERROR;
05801   }
05802
05803   /* If Memory address size is 8Bit */
05804   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05805   {
05806     /* Send Memory Address */
05807     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05808   }
05809   /* If Memory address size is 16Bit */
05810   else
05811   {
05812     /* Send MSB of Memory Address */
05813     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05814
05815     /* Wait until TXIS flag is set */
05816     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05817     {
05818       return HAL_ERROR;
05819     }
05820
05821     /* Send LSB of Memory Address */
05822     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05823   }
05824
05825   /* Wait until TCR flag is set */
05826   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
05827   {
05828     return HAL_ERROR;
05829   }
05830
05831   return HAL_OK;
05832 }
05833
05834 /**
05835   * @brief  Master sends target device address followed by internal memory address for read request.
05836   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05837   *                the configuration information for the specified I2C.
05838   * @param  DevAddress Target device address: The device 7 bits address value
05839   *         in datasheet must be shifted to the left before calling the interface
05840   * @param  MemAddress Internal memory address
05841   * @param  MemAddSize Size of internal memory address
05842   * @param  Timeout Timeout duration
05843   * @param  Tickstart Tick start value
05844   * @retval HAL status
05845   */
05846 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
05847                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
05848                                                uint32_t Tickstart)
05849 {
05850   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
05851
05852   /* Wait until TXIS flag is set */
05853   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05854   {
05855     return HAL_ERROR;
05856   }
05857
05858   /* If Memory address size is 8Bit */
05859   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05860   {
05861     /* Send Memory Address */
05862     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05863   }
05864   /* If Memory address size is 16Bit */
05865   else
05866   {
05867     /* Send MSB of Memory Address */
05868     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05869
05870     /* Wait until TXIS flag is set */
05871     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05872     {
05873       return HAL_ERROR;
05874     }
05875
05876     /* Send LSB of Memory Address */
05877     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05878   }
05879
05880   /* Wait until TC flag is set */
05881   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
05882   {
05883     return HAL_ERROR;
05884   }
05885
05886   return HAL_OK;
05887 }
05888
05889 /**
05890   * @brief  I2C Address complete process callback.
05891   * @param  hi2c I2C handle.
05892   * @param  ITFlags Interrupt flags to handle.
05893   * @retval None
05894   */
05895 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05896 {
05897   uint8_t transferdirection;
05898   uint16_t slaveaddrcode;
05899   uint16_t ownadd1code;
05900   uint16_t ownadd2code;
05901
05902   /* Prevent unused argument(s) compilation warning */
05903   UNUSED(ITFlags);
05904
05905   /* In case of Listen state, need to inform upper layer of address match code event */
05906   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
05907   {
05908     transferdirection = I2C_GET_DIR(hi2c);
05909     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
05910     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
05911     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
05912
05913     /* If 10bits addressing mode is selected */
05914     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
05915     {
05916       if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
05917       {
05918         slaveaddrcode = ownadd1code;
05919         hi2c->AddrEventCount++;
05920         if (hi2c->AddrEventCount == 2U)
05921         {
05922           /* Reset Address Event counter */
05923           hi2c->AddrEventCount = 0U;
05924
05925           /* Clear ADDR flag */
05926           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05927
05928           /* Process Unlocked */
05929           __HAL_UNLOCK(hi2c);
05930
05931           /* Call Slave Addr callback */
05932 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05933           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05934 #else
05935           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05936 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05937         }
05938       }
05939       else
05940       {
05941         slaveaddrcode = ownadd2code;
05942
05943         /* Disable ADDR Interrupts */
05944         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05945
05946         /* Process Unlocked */
05947         __HAL_UNLOCK(hi2c);
05948
05949         /* Call Slave Addr callback */
05950 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05951         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05952 #else
05953         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05954 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05955       }
05956     }
05957     /* else 7 bits addressing mode is selected */
05958     else
05959     {
05960       /* Disable ADDR Interrupts */
05961       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05962
05963       /* Process Unlocked */
05964       __HAL_UNLOCK(hi2c);
05965
05966       /* Call Slave Addr callback */
05967 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05968       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05969 #else
05970       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05971 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05972     }
05973   }
05974   /* Else clear address flag only */
05975   else
05976   {
05977     /* Clear ADDR flag */
05978     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05979
05980     /* Process Unlocked */
05981     __HAL_UNLOCK(hi2c);
05982   }
05983 }
05984
05985 /**
05986   * @brief  I2C Master sequential complete process.
05987   * @param  hi2c I2C handle.
05988   * @retval None
05989   */
05990 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
05991 {
05992   /* Reset I2C handle mode */
05993   hi2c->Mode = HAL_I2C_MODE_NONE;
05994
05995   /* No Generate Stop, to permit restart mode */
05996   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
05997   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05998   {
05999     hi2c->State         = HAL_I2C_STATE_READY;
06000     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
06001     hi2c->XferISR       = NULL;
06002
06003     /* Disable Interrupts */
06004     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
06005
06006     /* Process Unlocked */
06007     __HAL_UNLOCK(hi2c);
06008
06009     /* Call the corresponding callback to inform upper layer of End of Transfer */
06010 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06011     hi2c->MasterTxCpltCallback(hi2c);
06012 #else
06013     HAL_I2C_MasterTxCpltCallback(hi2c);
06014 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06015   }
06016   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
06017   else
06018   {
06019     hi2c->State         = HAL_I2C_STATE_READY;
06020     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
06021     hi2c->XferISR       = NULL;
06022
06023     /* Disable Interrupts */
06024     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
06025
06026     /* Process Unlocked */
06027     __HAL_UNLOCK(hi2c);
06028
06029     /* Call the corresponding callback to inform upper layer of End of Transfer */
06030 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06031     hi2c->MasterRxCpltCallback(hi2c);
06032 #else
06033     HAL_I2C_MasterRxCpltCallback(hi2c);
06034 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06035   }
06036 }
06037
06038 /**
06039   * @brief  I2C Slave sequential complete process.
06040   * @param  hi2c I2C handle.
06041   * @retval None
06042   */
06043 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
06044 {
06045   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
06046
06047   /* Reset I2C handle mode */
06048   hi2c->Mode = HAL_I2C_MODE_NONE;
06049
06050   /* If a DMA is ongoing, Update handle size context */
06051   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
06052   {
06053     /* Disable DMA Request */
06054     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06055   }
06056   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
06057   {
06058     /* Disable DMA Request */
06059     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06060   }
06061   else
06062   {
06063     /* Do nothing */
06064   }
06065
06066   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
06067   {
06068     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
06069     hi2c->State         = HAL_I2C_STATE_LISTEN;
06070     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
06071
06072     /* Disable Interrupts */
06073     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
06074
06075     /* Process Unlocked */
06076     __HAL_UNLOCK(hi2c);
06077
06078     /* Call the corresponding callback to inform upper layer of End of Transfer */
06079 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06080     hi2c->SlaveTxCpltCallback(hi2c);
06081 #else
06082     HAL_I2C_SlaveTxCpltCallback(hi2c);
06083 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06084   }
06085
06086   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
06087   {
06088     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
06089     hi2c->State         = HAL_I2C_STATE_LISTEN;
06090     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
06091
06092     /* Disable Interrupts */
06093     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
06094
06095     /* Process Unlocked */
06096     __HAL_UNLOCK(hi2c);
06097
06098     /* Call the corresponding callback to inform upper layer of End of Transfer */
06099 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06100     hi2c->SlaveRxCpltCallback(hi2c);
06101 #else
06102     HAL_I2C_SlaveRxCpltCallback(hi2c);
06103 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06104   }
06105   else
06106   {
06107     /* Nothing to do */
06108   }
06109 }
06110
06111 /**
06112   * @brief  I2C Master complete process.
06113   * @param  hi2c I2C handle.
06114   * @param  ITFlags Interrupt flags to handle.
06115   * @retval None
06116   */
06117 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
06118 {
06119   uint32_t tmperror;
06120   uint32_t tmpITFlags = ITFlags;
06121   __IO uint32_t tmpreg;
06122
06123   /* Clear STOP Flag */
06124   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06125
06126   /* Disable Interrupts and Store Previous state */
06127   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
06128   {
06129     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
06130     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
06131   }
06132   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
06133   {
06134     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
06135     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
06136   }
06137   else
06138   {
06139     /* Do nothing */
06140   }
06141
06142   /* Clear Configuration Register 2 */
06143   I2C_RESET_CR2(hi2c);
06144
06145   /* Reset handle parameters */
06146   hi2c->XferISR       = NULL;
06147   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
06148
06149   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
06150   {
06151     /* Clear NACK Flag */
06152     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06153
06154     /* Set acknowledge error code */
06155     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06156   }
06157
06158   /* Fetch Last receive data if any */
06159   if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
06160   {
06161     /* Read data from RXDR */
06162     tmpreg = (uint8_t)hi2c->Instance->RXDR;
06163     UNUSED(tmpreg);
06164   }
06165
06166   /* Flush TX register */
06167   I2C_Flush_TXDR(hi2c);
06168
06169   /* Store current volatile hi2c->ErrorCode, misra rule */
06170   tmperror = hi2c->ErrorCode;
06171
06172   /* Call the corresponding callback to inform upper layer of End of Transfer */
06173   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
06174   {
06175     /* Call the corresponding callback to inform upper layer of End of Transfer */
06176     I2C_ITError(hi2c, hi2c->ErrorCode);
06177   }
06178   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
06179   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
06180   {
06181     hi2c->State = HAL_I2C_STATE_READY;
06182     hi2c->PreviousState = I2C_STATE_NONE;
06183
06184     if (hi2c->Mode == HAL_I2C_MODE_MEM)
06185     {
06186       hi2c->Mode = HAL_I2C_MODE_NONE;
06187
06188       /* Process Unlocked */
06189       __HAL_UNLOCK(hi2c);
06190
06191       /* Call the corresponding callback to inform upper layer of End of Transfer */
06192 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06193       hi2c->MemTxCpltCallback(hi2c);
06194 #else
06195       HAL_I2C_MemTxCpltCallback(hi2c);
06196 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06197     }
06198     else
06199     {
06200       hi2c->Mode = HAL_I2C_MODE_NONE;
06201
06202       /* Process Unlocked */
06203       __HAL_UNLOCK(hi2c);
06204
06205       /* Call the corresponding callback to inform upper layer of End of Transfer */
06206 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06207       hi2c->MasterTxCpltCallback(hi2c);
06208 #else
06209       HAL_I2C_MasterTxCpltCallback(hi2c);
06210 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06211     }
06212   }
06213   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
06214   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
06215   {
06216     hi2c->State = HAL_I2C_STATE_READY;
06217     hi2c->PreviousState = I2C_STATE_NONE;
06218
06219     if (hi2c->Mode == HAL_I2C_MODE_MEM)
06220     {
06221       hi2c->Mode = HAL_I2C_MODE_NONE;
06222
06223       /* Process Unlocked */
06224       __HAL_UNLOCK(hi2c);
06225
06226       /* Call the corresponding callback to inform upper layer of End of Transfer */
06227 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06228       hi2c->MemRxCpltCallback(hi2c);
06229 #else
06230       HAL_I2C_MemRxCpltCallback(hi2c);
06231 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06232     }
06233     else
06234     {
06235       hi2c->Mode = HAL_I2C_MODE_NONE;
06236
06237       /* Process Unlocked */
06238       __HAL_UNLOCK(hi2c);
06239
06240       /* Call the corresponding callback to inform upper layer of End of Transfer */
06241 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06242       hi2c->MasterRxCpltCallback(hi2c);
06243 #else
06244       HAL_I2C_MasterRxCpltCallback(hi2c);
06245 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06246     }
06247   }
06248   else
06249   {
06250     /* Nothing to do */
06251   }
06252 }
06253
06254 /**
06255   * @brief  I2C Slave complete process.
06256   * @param  hi2c I2C handle.
06257   * @param  ITFlags Interrupt flags to handle.
06258   * @retval None
06259   */
06260 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
06261 {
06262   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
06263   uint32_t tmpITFlags = ITFlags;
06264   uint32_t tmpoptions = hi2c->XferOptions;
06265   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
06266
06267   /* Clear STOP Flag */
06268   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06269
06270   /* Disable Interrupts and Store Previous state */
06271   if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
06272   {
06273     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
06274     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
06275   }
06276   else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
06277   {
06278     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
06279     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
06280   }
06281   else if (tmpstate == HAL_I2C_STATE_LISTEN)
06282   {
06283     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
06284     hi2c->PreviousState = I2C_STATE_NONE;
06285   }
06286   else
06287   {
06288     /* Do nothing */
06289   }
06290
06291   /* Disable Address Acknowledge */
06292   hi2c->Instance->CR2 |= I2C_CR2_NACK;
06293
06294   /* Clear Configuration Register 2 */
06295   I2C_RESET_CR2(hi2c);
06296
06297   /* Flush TX register */
06298   I2C_Flush_TXDR(hi2c);
06299
06300   /* If a DMA is ongoing, Update handle size context */
06301   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
06302   {
06303     /* Disable DMA Request */
06304     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06305
06306     if (hi2c->hdmatx != NULL)
06307     {
06308       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
06309     }
06310   }
06311   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
06312   {
06313     /* Disable DMA Request */
06314     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06315
06316     if (hi2c->hdmarx != NULL)
06317     {
06318       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
06319     }
06320   }
06321   else
06322   {
06323     /* Do nothing */
06324   }
06325
06326   /* Store Last receive data if any */
06327   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
06328   {
06329     /* Remove RXNE flag on temporary variable as read done */
06330     tmpITFlags &= ~I2C_FLAG_RXNE;
06331
06332     /* Read data from RXDR */
06333     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
06334
06335     /* Increment Buffer pointer */
06336     hi2c->pBuffPtr++;
06337
06338     if ((hi2c->XferSize > 0U))
06339     {
06340       hi2c->XferSize--;
06341       hi2c->XferCount--;
06342     }
06343   }
06344
06345   /* All data are not transferred, so set error code accordingly */
06346   if (hi2c->XferCount != 0U)
06347   {
06348     /* Set ErrorCode corresponding to a Non-Acknowledge */
06349     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06350   }
06351
06352   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
06353       (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
06354   {
06355     /* Check that I2C transfer finished */
06356     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
06357     /* Mean XferCount == 0*/
06358     /* So clear Flag NACKF only */
06359     if (hi2c->XferCount == 0U)
06360     {
06361       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
06362         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
06363            Warning[Pa134]: left and right operands are identical */
06364       {
06365         /* Call I2C Listen complete process */
06366         I2C_ITListenCplt(hi2c, tmpITFlags);
06367       }
06368       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
06369       {
06370         /* Clear NACK Flag */
06371         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06372
06373         /* Flush TX register */
06374         I2C_Flush_TXDR(hi2c);
06375
06376         /* Last Byte is Transmitted */
06377         /* Call I2C Slave Sequential complete process */
06378         I2C_ITSlaveSeqCplt(hi2c);
06379       }
06380       else
06381       {
06382         /* Clear NACK Flag */
06383         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06384       }
06385     }
06386     else
06387     {
06388       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
06389       /* Clear NACK Flag */
06390       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06391
06392       /* Set ErrorCode corresponding to a Non-Acknowledge */
06393       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06394
06395       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
06396       {
06397         /* Call the corresponding callback to inform upper layer of End of Transfer */
06398         I2C_ITError(hi2c, hi2c->ErrorCode);
06399       }
06400     }
06401   }
06402
06403   hi2c->Mode = HAL_I2C_MODE_NONE;
06404   hi2c->XferISR = NULL;
06405
06406   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
06407   {
06408     /* Call the corresponding callback to inform upper layer of End of Transfer */
06409     I2C_ITError(hi2c, hi2c->ErrorCode);
06410
06411     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06412     if (hi2c->State == HAL_I2C_STATE_LISTEN)
06413     {
06414       /* Call I2C Listen complete process */
06415       I2C_ITListenCplt(hi2c, tmpITFlags);
06416     }
06417   }
06418   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
06419   {
06420     /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
06421     I2C_ITSlaveSeqCplt(hi2c);
06422
06423     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
06424     hi2c->State = HAL_I2C_STATE_READY;
06425     hi2c->PreviousState = I2C_STATE_NONE;
06426
06427     /* Process Unlocked */
06428     __HAL_UNLOCK(hi2c);
06429
06430     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06431 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06432     hi2c->ListenCpltCallback(hi2c);
06433 #else
06434     HAL_I2C_ListenCpltCallback(hi2c);
06435 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06436   }
06437   /* Call the corresponding callback to inform upper layer of End of Transfer */
06438   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
06439   {
06440     hi2c->State = HAL_I2C_STATE_READY;
06441     hi2c->PreviousState = I2C_STATE_NONE;
06442
06443     /* Process Unlocked */
06444     __HAL_UNLOCK(hi2c);
06445
06446     /* Call the corresponding callback to inform upper layer of End of Transfer */
06447 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06448     hi2c->SlaveRxCpltCallback(hi2c);
06449 #else
06450     HAL_I2C_SlaveRxCpltCallback(hi2c);
06451 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06452   }
06453   else
06454   {
06455     hi2c->State = HAL_I2C_STATE_READY;
06456     hi2c->PreviousState = I2C_STATE_NONE;
06457
06458     /* Process Unlocked */
06459     __HAL_UNLOCK(hi2c);
06460
06461     /* Call the corresponding callback to inform upper layer of End of Transfer */
06462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06463     hi2c->SlaveTxCpltCallback(hi2c);
06464 #else
06465     HAL_I2C_SlaveTxCpltCallback(hi2c);
06466 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06467   }
06468 }
06469
06470 /**
06471   * @brief  I2C Listen complete process.
06472   * @param  hi2c I2C handle.
06473   * @param  ITFlags Interrupt flags to handle.
06474   * @retval None
06475   */
06476 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
06477 {
06478   /* Reset handle parameters */
06479   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
06480   hi2c->PreviousState = I2C_STATE_NONE;
06481   hi2c->State = HAL_I2C_STATE_READY;
06482   hi2c->Mode = HAL_I2C_MODE_NONE;
06483   hi2c->XferISR = NULL;
06484
06485   /* Store Last receive data if any */
06486   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
06487   {
06488     /* Read data from RXDR */
06489     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
06490
06491     /* Increment Buffer pointer */
06492     hi2c->pBuffPtr++;
06493
06494     if ((hi2c->XferSize > 0U))
06495     {
06496       hi2c->XferSize--;
06497       hi2c->XferCount--;
06498
06499       /* Set ErrorCode corresponding to a Non-Acknowledge */
06500       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06501     }
06502   }
06503
06504   /* Disable all Interrupts*/
06505   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06506
06507   /* Clear NACK Flag */
06508   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06509
06510   /* Process Unlocked */
06511   __HAL_UNLOCK(hi2c);
06512
06513   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06514 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06515   hi2c->ListenCpltCallback(hi2c);
06516 #else
06517   HAL_I2C_ListenCpltCallback(hi2c);
06518 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06519 }
06520
06521 /**
06522   * @brief  I2C interrupts error process.
06523   * @param  hi2c I2C handle.
06524   * @param  ErrorCode Error code to handle.
06525   * @retval None
06526   */
06527 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
06528 {
06529   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
06530
06531   uint32_t tmppreviousstate;
06532
06533   /* Reset handle parameters */
06534   hi2c->Mode          = HAL_I2C_MODE_NONE;
06535   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
06536   hi2c->XferCount     = 0U;
06537
06538   /* Set new error code */
06539   hi2c->ErrorCode |= ErrorCode;
06540
06541   /* Disable Interrupts */
06542   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
06543       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
06544       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
06545   {
06546     /* Disable all interrupts, except interrupts related to LISTEN state */
06547     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06548
06549     /* keep HAL_I2C_STATE_LISTEN if set */
06550     hi2c->State         = HAL_I2C_STATE_LISTEN;
06551     hi2c->XferISR       = I2C_Slave_ISR_IT;
06552   }
06553   else
06554   {
06555     /* Disable all interrupts */
06556     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06557
06558     /* Flush TX register */
06559     I2C_Flush_TXDR(hi2c);
06560
06561     /* If state is an abort treatment on going, don't change state */
06562     /* This change will be do later */
06563     if (hi2c->State != HAL_I2C_STATE_ABORT)
06564     {
06565       /* Set HAL_I2C_STATE_READY */
06566       hi2c->State         = HAL_I2C_STATE_READY;
06567
06568       /* Check if a STOPF is detected */
06569       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
06570       {
06571         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
06572         {
06573           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06574           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06575         }
06576
06577         /* Clear STOP Flag */
06578         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06579       }
06580
06581     }
06582     hi2c->XferISR       = NULL;
06583   }
06584
06585   /* Abort DMA TX transfer if any */
06586   tmppreviousstate = hi2c->PreviousState;
06587
06588   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
06589                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
06590   {
06591     if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
06592     {
06593       hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06594     }
06595
06596     if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
06597     {
06598       /* Set the I2C DMA Abort callback :
06599        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
06600       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
06601
06602       /* Process Unlocked */
06603       __HAL_UNLOCK(hi2c);
06604
06605       /* Abort DMA TX */
06606       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
06607       {
06608         /* Call Directly XferAbortCallback function in case of error */
06609         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
06610       }
06611     }
06612     else
06613     {
06614       I2C_TreatErrorCallback(hi2c);
06615     }
06616   }
06617   /* Abort DMA RX transfer if any */
06618   else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
06619                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
06620   {
06621     if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
06622     {
06623       hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06624     }
06625
06626     if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
06627     {
06628       /* Set the I2C DMA Abort callback :
06629         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
06630       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
06631
06632       /* Process Unlocked */
06633       __HAL_UNLOCK(hi2c);
06634
06635       /* Abort DMA RX */
06636       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
06637       {
06638         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
06639         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
06640       }
06641     }
06642     else
06643     {
06644       I2C_TreatErrorCallback(hi2c);
06645     }
06646   }
06647   else
06648   {
06649     I2C_TreatErrorCallback(hi2c);
06650   }
06651 }
06652
06653 /**
06654   * @brief  I2C Error callback treatment.
06655   * @param  hi2c I2C handle.
06656   * @retval None
06657   */
06658 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
06659 {
06660   if (hi2c->State == HAL_I2C_STATE_ABORT)
06661   {
06662     hi2c->State = HAL_I2C_STATE_READY;
06663     hi2c->PreviousState = I2C_STATE_NONE;
06664
06665     /* Process Unlocked */
06666     __HAL_UNLOCK(hi2c);
06667
06668     /* Call the corresponding callback to inform upper layer of End of Transfer */
06669 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06670     hi2c->AbortCpltCallback(hi2c);
06671 #else
06672     HAL_I2C_AbortCpltCallback(hi2c);
06673 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06674   }
06675   else
06676   {
06677     hi2c->PreviousState = I2C_STATE_NONE;
06678
06679     /* Process Unlocked */
06680     __HAL_UNLOCK(hi2c);
06681
06682     /* Call the corresponding callback to inform upper layer of End of Transfer */
06683 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06684     hi2c->ErrorCallback(hi2c);
06685 #else
06686     HAL_I2C_ErrorCallback(hi2c);
06687 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06688   }
06689 }
06690
06691 /**
06692   * @brief  I2C Tx data register flush process.
06693   * @param  hi2c I2C handle.
06694   * @retval None
06695   */
06696 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
06697 {
06698   /* If a pending TXIS flag is set */
06699   /* Write a dummy data in TXDR to clear it */
06700   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
06701   {
06702     hi2c->Instance->TXDR = 0x00U;
06703   }
06704
06705   /* Flush TX register if not empty */
06706   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
06707   {
06708     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
06709   }
06710 }
06711
06712 /**
06713   * @brief  DMA I2C master transmit process complete callback.
06714   * @param  hdma DMA handle
06715   * @retval None
06716   */
06717 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
06718 {
06719   /* Derogation MISRAC2012-Rule-11.5 */
06720   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06721
06722   /* Disable DMA Request */
06723   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06724
06725   /* If last transfer, enable STOP interrupt */
06726   if (hi2c->XferCount == 0U)
06727   {
06728     /* Enable STOP interrupt */
06729     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
06730   }
06731   /* else prepare a new DMA transfer and enable TCReload interrupt */
06732   else
06733   {
06734     /* Update Buffer pointer */
06735     hi2c->pBuffPtr += hi2c->XferSize;
06736
06737     /* Set the XferSize to transfer */
06738     if (hi2c->XferCount > MAX_NBYTE_SIZE)
06739     {
06740       hi2c->XferSize = MAX_NBYTE_SIZE;
06741     }
06742     else
06743     {
06744       hi2c->XferSize = hi2c->XferCount;
06745     }
06746
06747     /* Enable the DMA channel */
06748     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
06749                          hi2c->XferSize) != HAL_OK)
06750     {
06751       /* Call the corresponding callback to inform upper layer of End of Transfer */
06752       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06753     }
06754     else
06755     {
06756       /* Enable TC interrupts */
06757       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
06758     }
06759   }
06760 }
06761
06762
06763 /**
06764   * @brief  DMA I2C slave transmit process complete callback.
06765   * @param  hdma DMA handle
06766   * @retval None
06767   */
06768 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
06769 {
06770   /* Derogation MISRAC2012-Rule-11.5 */
06771   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06772   uint32_t tmpoptions = hi2c->XferOptions;
06773
06774   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
06775   {
06776     /* Disable DMA Request */
06777     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06778
06779     /* Last Byte is Transmitted */
06780     /* Call I2C Slave Sequential complete process */
06781     I2C_ITSlaveSeqCplt(hi2c);
06782   }
06783   else
06784   {
06785     /* No specific action, Master fully manage the generation of STOP condition */
06786     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06787     /* So STOP condition should be manage through Interrupt treatment */
06788   }
06789 }
06790
06791
06792 /**
06793   * @brief DMA I2C master receive process complete callback.
06794   * @param  hdma DMA handle
06795   * @retval None
06796   */
06797 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
06798 {
06799   /* Derogation MISRAC2012-Rule-11.5 */
06800   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06801
06802   /* Disable DMA Request */
06803   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06804
06805   /* If last transfer, enable STOP interrupt */
06806   if (hi2c->XferCount == 0U)
06807   {
06808     /* Enable STOP interrupt */
06809     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
06810   }
06811   /* else prepare a new DMA transfer and enable TCReload interrupt */
06812   else
06813   {
06814     /* Update Buffer pointer */
06815     hi2c->pBuffPtr += hi2c->XferSize;
06816
06817     /* Set the XferSize to transfer */
06818     if (hi2c->XferCount > MAX_NBYTE_SIZE)
06819     {
06820       hi2c->XferSize = MAX_NBYTE_SIZE;
06821     }
06822     else
06823     {
06824       hi2c->XferSize = hi2c->XferCount;
06825     }
06826
06827     /* Enable the DMA channel */
06828     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
06829                          hi2c->XferSize) != HAL_OK)
06830     {
06831       /* Call the corresponding callback to inform upper layer of End of Transfer */
06832       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06833     }
06834     else
06835     {
06836       /* Enable TC interrupts */
06837       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
06838     }
06839   }
06840 }
06841
06842
06843 /**
06844   * @brief  DMA I2C slave receive process complete callback.
06845   * @param  hdma DMA handle
06846   * @retval None
06847   */
06848 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
06849 {
06850   /* Derogation MISRAC2012-Rule-11.5 */
06851   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06852   uint32_t tmpoptions = hi2c->XferOptions;
06853
06854   if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
06855       (tmpoptions != I2C_NO_OPTION_FRAME))
06856   {
06857     /* Disable DMA Request */
06858     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06859
06860     /* Call I2C Slave Sequential complete process */
06861     I2C_ITSlaveSeqCplt(hi2c);
06862   }
06863   else
06864   {
06865     /* No specific action, Master fully manage the generation of STOP condition */
06866     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06867     /* So STOP condition should be manage through Interrupt treatment */
06868   }
06869 }
06870
06871
06872 /**
06873   * @brief  DMA I2C communication error callback.
06874   * @param hdma DMA handle
06875   * @retval None
06876   */
06877 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
06878 {
06879   /* Derogation MISRAC2012-Rule-11.5 */
06880   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06881
06882   /* Disable Acknowledge */
06883   hi2c->Instance->CR2 |= I2C_CR2_NACK;
06884
06885   /* Call the corresponding callback to inform upper layer of End of Transfer */
06886   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06887 }
06888
06889
06890 /**
06891   * @brief DMA I2C communication abort callback
06892   *        (To be called at end of DMA Abort procedure).
06893   * @param hdma DMA handle.
06894   * @retval None
06895   */
06896 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
06897 {
06898   /* Derogation MISRAC2012-Rule-11.5 */
06899   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06900
06901   /* Reset AbortCpltCallback */
06902   if (hi2c->hdmatx != NULL)
06903   {
06904     hi2c->hdmatx->XferAbortCallback = NULL;
06905   }
06906   if (hi2c->hdmarx != NULL)
06907   {
06908     hi2c->hdmarx->XferAbortCallback = NULL;
06909   }
06910
06911   I2C_TreatErrorCallback(hi2c);
06912 }
06913
06914
06915 /**
06916   * @brief  This function handles I2C Communication Timeout. It waits
06917   *                until a flag is no longer in the specified status.
06918   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06919   *                the configuration information for the specified I2C.
06920   * @param  Flag Specifies the I2C flag to check.
06921   * @param  Status The actual Flag status (SET or RESET).
06922   * @param  Timeout Timeout duration
06923   * @param  Tickstart Tick start value
06924   * @retval HAL status
06925   */
06926 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
06927                                                     uint32_t Timeout, uint32_t Tickstart)
06928 {
06929   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
06930   {
06931     /* Check if an error is detected */
06932     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
06933     {
06934       return HAL_ERROR;
06935     }
06936
06937     /* Check for the Timeout */
06938     if (Timeout != HAL_MAX_DELAY)
06939     {
06940       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06941       {
06942         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
06943         {
06944           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06945           hi2c->State = HAL_I2C_STATE_READY;
06946           hi2c->Mode = HAL_I2C_MODE_NONE;
06947
06948           /* Process Unlocked */
06949           __HAL_UNLOCK(hi2c);
06950           return HAL_ERROR;
06951         }
06952       }
06953     }
06954   }
06955   return HAL_OK;
06956 }
06957
06958 /**
06959   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
06960   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06961   *                the configuration information for the specified I2C.
06962   * @param  Timeout Timeout duration
06963   * @param  Tickstart Tick start value
06964   * @retval HAL status
06965   */
06966 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
06967                                                         uint32_t Tickstart)
06968 {
06969   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
06970   {
06971     /* Check if an error is detected */
06972     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
06973     {
06974       return HAL_ERROR;
06975     }
06976
06977     /* Check for the Timeout */
06978     if (Timeout != HAL_MAX_DELAY)
06979     {
06980       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06981       {
06982         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
06983         {
06984           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06985           hi2c->State = HAL_I2C_STATE_READY;
06986           hi2c->Mode = HAL_I2C_MODE_NONE;
06987
06988           /* Process Unlocked */
06989           __HAL_UNLOCK(hi2c);
06990
06991           return HAL_ERROR;
06992         }
06993       }
06994     }
06995   }
06996   return HAL_OK;
06997 }
06998
06999 /**
07000   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
07001   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07002   *                the configuration information for the specified I2C.
07003   * @param  Timeout Timeout duration
07004   * @param  Tickstart Tick start value
07005   * @retval HAL status
07006   */
07007 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
07008                                                         uint32_t Tickstart)
07009 {
07010   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
07011   {
07012     /* Check if an error is detected */
07013     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
07014     {
07015       return HAL_ERROR;
07016     }
07017
07018     /* Check for the Timeout */
07019     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
07020     {
07021       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
07022       {
07023         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
07024         hi2c->State = HAL_I2C_STATE_READY;
07025         hi2c->Mode = HAL_I2C_MODE_NONE;
07026
07027         /* Process Unlocked */
07028         __HAL_UNLOCK(hi2c);
07029
07030         return HAL_ERROR;
07031       }
07032     }
07033   }
07034   return HAL_OK;
07035 }
07036
07037 /**
07038   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
07039   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07040   *                the configuration information for the specified I2C.
07041   * @param  Timeout Timeout duration
07042   * @param  Tickstart Tick start value
07043   * @retval HAL status
07044   */
07045 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
07046                                                         uint32_t Tickstart)
07047 {
07048   HAL_StatusTypeDef status = HAL_OK;
07049
07050   while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
07051   {
07052     /* Check if an error is detected */
07053     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
07054     {
07055       status = HAL_ERROR;
07056     }
07057
07058     /* Check if a STOPF is detected */
07059     if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
07060     {
07061       /* Check if an RXNE is pending */
07062       /* Store Last receive data if any */
07063       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
07064       {
07065         /* Return HAL_OK */
07066         /* The Reading of data from RXDR will be done in caller function */
07067         status = HAL_OK;
07068       }
07069
07070       /* Check a no-acknowledge have been detected */
07071       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
07072       {
07073         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
07074         hi2c->ErrorCode = HAL_I2C_ERROR_AF;
07075
07076         /* Clear STOP Flag */
07077         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
07078
07079         /* Clear Configuration Register 2 */
07080         I2C_RESET_CR2(hi2c);
07081
07082         hi2c->State = HAL_I2C_STATE_READY;
07083         hi2c->Mode = HAL_I2C_MODE_NONE;
07084
07085         /* Process Unlocked */
07086         __HAL_UNLOCK(hi2c);
07087
07088         status = HAL_ERROR;
07089       }
07090       else
07091       {
07092         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
07093       }
07094     }
07095
07096     /* Check for the Timeout */
07097     if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
07098     {
07099       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
07100       {
07101         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
07102         hi2c->State = HAL_I2C_STATE_READY;
07103
07104         /* Process Unlocked */
07105         __HAL_UNLOCK(hi2c);
07106
07107         status = HAL_ERROR;
07108       }
07109     }
07110   }
07111   return status;
07112 }
07113
07114 /**
07115   * @brief  This function handles errors detection during an I2C Communication.
07116   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07117   *                the configuration information for the specified I2C.
07118   * @param  Timeout Timeout duration
07119   * @param  Tickstart Tick start value
07120   * @retval HAL status
07121   */
07122 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
07123 {
07124   HAL_StatusTypeDef status = HAL_OK;
07125   uint32_t itflag   = hi2c->Instance->ISR;
07126   uint32_t error_code = 0;
07127   uint32_t tickstart = Tickstart;
07128   uint32_t tmp1;
07129   HAL_I2C_ModeTypeDef tmp2;
07130
07131   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
07132   {
07133     /* Clear NACKF Flag */
07134     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
07135
07136     /* Wait until STOP Flag is set or timeout occurred */
07137     /* AutoEnd should be initiate after AF */
07138     while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
07139     {
07140       /* Check for the Timeout */
07141       if (Timeout != HAL_MAX_DELAY)
07142       {
07143         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
07144         {
07145           tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
07146           tmp2 = hi2c->Mode;
07147
07148           /* In case of I2C still busy, try to regenerate a STOP manually */
07149           if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
07150               (tmp1 != I2C_CR2_STOP) && \
07151               (tmp2 != HAL_I2C_MODE_SLAVE))
07152           {
07153             /* Generate Stop */
07154             hi2c->Instance->CR2 |= I2C_CR2_STOP;
07155
07156             /* Update Tick with new reference */
07157             tickstart = HAL_GetTick();
07158           }
07159
07160           while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
07161           {
07162             /* Check for the Timeout */
07163             if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
07164             {
07165               error_code |= HAL_I2C_ERROR_TIMEOUT;
07166
07167               status = HAL_ERROR;
07168
07169               break;
07170             }
07171           }
07172         }
07173       }
07174     }
07175
07176     /* In case STOP Flag is detected, clear it */
07177     if (status == HAL_OK)
07178     {
07179       /* Clear STOP Flag */
07180       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
07181     }
07182
07183     error_code |= HAL_I2C_ERROR_AF;
07184
07185     status = HAL_ERROR;
07186   }
07187
07188   /* Refresh Content of Status register */
07189   itflag = hi2c->Instance->ISR;
07190
07191   /* Then verify if an additional errors occurs */
07192   /* Check if a Bus error occurred */
07193   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
07194   {
07195     error_code |= HAL_I2C_ERROR_BERR;
07196
07197     /* Clear BERR flag */
07198     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
07199
07200     status = HAL_ERROR;
07201   }
07202
07203   /* Check if an Over-Run/Under-Run error occurred */
07204   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
07205   {
07206     error_code |= HAL_I2C_ERROR_OVR;
07207
07208     /* Clear OVR flag */
07209     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
07210
07211     status = HAL_ERROR;
07212   }
07213
07214   /* Check if an Arbitration Loss error occurred */
07215   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
07216   {
07217     error_code |= HAL_I2C_ERROR_ARLO;
07218
07219     /* Clear ARLO flag */
07220     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
07221
07222     status = HAL_ERROR;
07223   }
07224
07225   if (status != HAL_OK)
07226   {
07227     /* Flush TX register */
07228     I2C_Flush_TXDR(hi2c);
07229
07230     /* Clear Configuration Register 2 */
07231     I2C_RESET_CR2(hi2c);
07232
07233     hi2c->ErrorCode |= error_code;
07234     hi2c->State = HAL_I2C_STATE_READY;
07235     hi2c->Mode = HAL_I2C_MODE_NONE;
07236
07237     /* Process Unlocked */
07238     __HAL_UNLOCK(hi2c);
07239   }
07240
07241   return status;
07242 }
07243
07244 /**
07245   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
07246   * @param  hi2c I2C handle.
07247   * @param  DevAddress Specifies the slave address to be programmed.
07248   * @param  Size Specifies the number of bytes to be programmed.
07249   *   This parameter must be a value between 0 and 255.
07250   * @param  Mode New state of the I2C START condition generation.
07251   *   This parameter can be one of the following values:
07252   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
07253   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
07254   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
07255   * @param  Request New state of the I2C START condition generation.
07256   *   This parameter can be one of the following values:
07257   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
07258   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
07259   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
07260   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
07261   * @retval None
07262   */
07263 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
07264                                uint32_t Request)
07265 {
07266   /* Check the parameters */
07267   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
07268   assert_param(IS_TRANSFER_MODE(Mode));
07269   assert_param(IS_TRANSFER_REQUEST(Request));
07270
07271   /* Declaration of tmp to prevent undefined behavior of volatile usage */
07272   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
07273                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
07274                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
07275
07276   /* update CR2 register */
07277   MODIFY_REG(hi2c->Instance->CR2, \
07278              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
07279                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
07280                I2C_CR2_START | I2C_CR2_STOP)), tmp);
07281 }
07282
07283 /**
07284   * @brief  Manage the enabling of Interrupts.
07285   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07286   *                the configuration information for the specified I2C.
07287   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
07288   * @retval None
07289   */
07290 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
07291 {
07292   uint32_t tmpisr = 0U;
07293
07294   if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
07295       (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
07296       (hi2c->XferISR != I2C_Mem_ISR_DMA))
07297   {
07298     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
07299     {
07300       /* Enable ERR, STOP, NACK and ADDR interrupts */
07301       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07302     }
07303
07304     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
07305     {
07306       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
07307       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
07308     }
07309
07310     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
07311     {
07312       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
07313       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
07314     }
07315
07316     if (InterruptRequest == I2C_XFER_ERROR_IT)
07317     {
07318       /* Enable ERR and NACK interrupts */
07319       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07320     }
07321
07322     if (InterruptRequest == I2C_XFER_CPLT_IT)
07323     {
07324       /* Enable STOP interrupts */
07325       tmpisr |= I2C_IT_STOPI;
07326     }
07327   }
07328
07329   else
07330   {
07331     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
07332     {
07333       /* Enable ERR, STOP, NACK and ADDR interrupts */
07334       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07335     }
07336
07337     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
07338     {
07339       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
07340       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
07341     }
07342
07343     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
07344     {
07345       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
07346       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
07347     }
07348
07349     if (InterruptRequest == I2C_XFER_ERROR_IT)
07350     {
07351       /* Enable ERR and NACK interrupts */
07352       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07353     }
07354
07355     if (InterruptRequest == I2C_XFER_CPLT_IT)
07356     {
07357       /* Enable STOP interrupts */
07358       tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
07359     }
07360
07361     if (InterruptRequest == I2C_XFER_RELOAD_IT)
07362     {
07363       /* Enable TC interrupts */
07364       tmpisr |= I2C_IT_TCI;
07365     }
07366   }
07367
07368   /* Enable interrupts only at the end */
07369   /* to avoid the risk of I2C interrupt handle execution before */
07370   /* all interrupts requested done */
07371   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
07372 }
07373
07374 /**
07375   * @brief  Manage the disabling of Interrupts.
07376   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07377   *                the configuration information for the specified I2C.
07378   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
07379   * @retval None
07380   */
07381 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
07382 {
07383   uint32_t tmpisr = 0U;
07384
07385   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
07386   {
07387     /* Disable TC and TXI interrupts */
07388     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
07389
07390     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
07391     {
07392       /* Disable NACK and STOP interrupts */
07393       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07394     }
07395   }
07396
07397   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
07398   {
07399     /* Disable TC and RXI interrupts */
07400     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
07401
07402     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
07403     {
07404       /* Disable NACK and STOP interrupts */
07405       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07406     }
07407   }
07408
07409   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
07410   {
07411     /* Disable ADDR, NACK and STOP interrupts */
07412     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07413   }
07414
07415   if (InterruptRequest == I2C_XFER_ERROR_IT)
07416   {
07417     /* Enable ERR and NACK interrupts */
07418     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07419   }
07420
07421   if (InterruptRequest == I2C_XFER_CPLT_IT)
07422   {
07423     /* Enable STOP interrupts */
07424     tmpisr |= I2C_IT_STOPI;
07425   }
07426
07427   if (InterruptRequest == I2C_XFER_RELOAD_IT)
07428   {
07429     /* Enable TC interrupts */
07430     tmpisr |= I2C_IT_TCI;
07431   }
07432
07433   /* Disable interrupts only at the end */
07434   /* to avoid a breaking situation like at "t" time */
07435   /* all disable interrupts request are not done */
07436   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
07437 }
07438
07439 /**
07440   * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
07441   * @param  hi2c I2C handle.
07442   * @retval None
07443   */
07444 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
07445 {
07446   /* if user set XferOptions to I2C_OTHER_FRAME            */
07447   /* it request implicitly to generate a restart condition */
07448   /* set XferOptions to I2C_FIRST_FRAME                    */
07449   if (hi2c->XferOptions == I2C_OTHER_FRAME)
07450   {
07451     hi2c->XferOptions = I2C_FIRST_FRAME;
07452   }
07453   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
07454   /* it request implicitly to generate a restart condition    */
07455   /* then generate a stop condition at the end of transfer    */
07456   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
07457   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
07458   {
07459     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
07460   }
07461   else
07462   {
07463     /* Nothing to do */
07464   }
07465 }
07466
07467 /**
07468   * @}
07469   */
07470
07471 #endif /* HAL_I2C_MODULE_ENABLED */
07472 /**
07473   * @}
07474   */
07475
07476 /**
07477   * @}
07478   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_i2c.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_I2C_H
00021 #define STM32G4xx_HAL_I2C_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup I2C
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup I2C_Exported_Types I2C Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00044   * @brief  I2C Configuration Structure definition
00045   * @{
00046   */
00047 typedef struct
00048 {
00049   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00050                                      This parameter calculated by referring to I2C initialization section
00051                                      in Reference manual */
00052
00053   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00054                                      This parameter can be a 7-bit or 10-bit address. */
00055
00056   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00057                                      This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00058
00059   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00060                                      This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00061
00062   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00063                                      This parameter can be a 7-bit address. */
00064
00065   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
00066                                      mode is selected.
00067                                      This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00068
00069   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00070                                      This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00071
00072   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00073                                      This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00074
00075 } I2C_InitTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HAL_state_structure_definition HAL state structure definition
00082   * @brief  HAL State structure definition
00083   * @note  HAL I2C State value coding follow below described bitmap :\n
00084   *          b7-b6  Error information\n
00085   *             00 : No Error\n
00086   *             01 : Abort (Abort user request on going)\n
00087   *             10 : Timeout\n
00088   *             11 : Error\n
00089   *          b5     Peripheral initialization status\n
00090   *             0  : Reset (peripheral not initialized)\n
00091   *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
00092   *          b4     (not used)\n
00093   *             x  : Should be set to 0\n
00094   *          b3\n
00095   *             0  : Ready or Busy (No Listen mode ongoing)\n
00096   *             1  : Listen (peripheral in Address Listen Mode)\n
00097   *          b2     Intrinsic process state\n
00098   *             0  : Ready\n
00099   *             1  : Busy (peripheral busy with some configuration or internal operations)\n
00100   *          b1     Rx state\n
00101   *             0  : Ready (no Rx operation ongoing)\n
00102   *             1  : Busy (Rx operation ongoing)\n
00103   *          b0     Tx state\n
00104   *             0  : Ready (no Tx operation ongoing)\n
00105   *             1  : Busy (Tx operation ongoing)
00106   * @{
00107   */
00108 typedef enum
00109 {
00110   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00111   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00112   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00113   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00114   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00115   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00116   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00117                                                  process is ongoing                         */
00118   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00119                                                  process is ongoing                         */
00120   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00121
00122 } HAL_I2C_StateTypeDef;
00123
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00129   * @brief  HAL Mode structure definition
00130   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00131   *          b7     (not used)\n
00132   *             x  : Should be set to 0\n
00133   *          b6\n
00134   *             0  : None\n
00135   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00136   *          b5\n
00137   *             0  : None\n
00138   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00139   *          b4\n
00140   *             0  : None\n
00141   *             1  : Master (HAL I2C communication is in Master Mode)\n
00142   *          b3-b2-b1-b0  (not used)\n
00143   *             xxxx : Should be set to 0000
00144   * @{
00145   */
00146 typedef enum
00147 {
00148   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00149   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00150   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00151   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00152
00153 } HAL_I2C_ModeTypeDef;
00154
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00160   * @brief  I2C Error Code definition
00161   * @{
00162   */
00163 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00164 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00165 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00166 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00167 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00168 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00169 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00170 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00171 #define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
00172 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00173 #define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00174 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00175 #define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00181   * @brief  I2C handle Structure definition
00182   * @{
00183   */
00184 typedef struct __I2C_HandleTypeDef
00185 {
00186   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00187
00188   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00189
00190   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00191
00192   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00193
00194   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00195
00196   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00197                                                   be a value of @ref I2C_XFEROPTIONS */
00198
00199   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00200
00201   HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00202   /*!< I2C transfer IRQ handler function pointer */
00203
00204   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00205
00206   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00207
00208
00209   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00210
00211   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00212
00213   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00214
00215   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00216
00217   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00218
00219   __IO uint32_t              Devaddress;     /*!< I2C Target device address                 */
00220
00221   __IO uint32_t              Memaddress;     /*!< I2C Target memory address                 */
00222
00223 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00224   void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00225   /*!< I2C Master Tx Transfer completed callback */
00226   void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00227   /*!< I2C Master Rx Transfer completed callback */
00228   void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00229   /*!< I2C Slave Tx Transfer completed callback  */
00230   void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00231   /*!< I2C Slave Rx Transfer completed callback  */
00232   void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00233   /*!< I2C Listen Complete callback              */
00234   void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00235   /*!< I2C Memory Tx Transfer completed callback */
00236   void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00237   /*!< I2C Memory Rx Transfer completed callback */
00238   void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
00239   /*!< I2C Error callback                        */
00240   void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00241   /*!< I2C Abort callback                        */
00242
00243   void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00244   /*!< I2C Slave Address Match callback */
00245
00246   void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
00247   /*!< I2C Msp Init callback                     */
00248   void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
00249   /*!< I2C Msp DeInit callback                   */
00250
00251 #endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
00252 } I2C_HandleTypeDef;
00253
00254 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00255 /**
00256   * @brief  HAL I2C Callback ID enumeration definition
00257   */
00258 typedef enum
00259 {
00260   HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
00261   HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
00262   HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
00263   HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
00264   HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
00265   HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
00266   HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
00267   HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
00268   HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
00269
00270   HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
00271   HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
00272
00273 } HAL_I2C_CallbackIDTypeDef;
00274
00275 /**
00276   * @brief  HAL I2C Callback pointer definition
00277   */
00278 typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
00279 /*!< pointer to an I2C callback function */
00280 typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
00281                                           uint16_t AddrMatchCode);
00282 /*!< pointer to an I2C Address Match callback function */
00283
00284 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292 /* Exported constants --------------------------------------------------------*/
00293
00294 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00295   * @{
00296   */
00297
00298 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00299   * @{
00300   */
00301 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00302 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00303 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00304 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00305 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00306 #define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
00307
00308 /* List of XferOptions in usage of :
00309  * 1- Restart condition in all use cases (direction change or not)
00310  */
00311 #define  I2C_OTHER_FRAME                (0x000000AAU)
00312 #define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00318   * @{
00319   */
00320 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00321 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00327   * @{
00328   */
00329 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00330 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00336   * @{
00337   */
00338 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00339 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00340 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00341 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00342 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00343 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00344 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00345 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00351   * @{
00352   */
00353 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00354 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00360   * @{
00361   */
00362 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00363 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00369   * @{
00370   */
00371 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00372 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
00378   * @{
00379   */
00380 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00381 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00387   * @{
00388   */
00389 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00390 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00391 #define  I2C_SOFTEND_MODE               (0x00000000U)
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00397   * @{
00398   */
00399 #define  I2C_NO_STARTSTOP               (0x00000000U)
00400 #define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
00401 #define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00402 #define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00408   * @brief I2C Interrupt definition
00409   *        Elements values convention: 0xXXXXXXXX
00410   *           - XXXXXXXX  : Interrupt control mask
00411   * @{
00412   */
00413 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00414 #define I2C_IT_TCI                      I2C_CR1_TCIE
00415 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00416 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00417 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00418 #define I2C_IT_RXI                      I2C_CR1_RXIE
00419 #define I2C_IT_TXI                      I2C_CR1_TXIE
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup I2C_Flag_definition I2C Flag definition
00425   * @{
00426   */
00427 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00428 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00429 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00430 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00431 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00432 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00433 #define I2C_FLAG_TC                     I2C_ISR_TC
00434 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00435 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00436 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00437 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00438 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00439 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00440 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00441 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00442 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 /* Exported macros -----------------------------------------------------------*/
00452
00453 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00454   * @{
00455   */
00456
00457 /** @brief Reset I2C handle state.
00458   * @param  __HANDLE__ specifies the I2C Handle.
00459   * @retval None
00460   */
00461 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00462 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
00463                                                                     (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
00464                                                                     (__HANDLE__)->MspInitCallback = NULL;       \
00465                                                                     (__HANDLE__)->MspDeInitCallback = NULL;     \
00466                                                                   } while(0)
00467 #else
00468 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00469 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00470
00471 /** @brief  Enable the specified I2C interrupt.
00472   * @param  __HANDLE__ specifies the I2C Handle.
00473   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00474   *        This parameter can be one of the following values:
00475   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00476   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00477   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00478   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00479   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00480   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00481   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00482   *
00483   * @retval None
00484   */
00485 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00486
00487 /** @brief  Disable the specified I2C interrupt.
00488   * @param  __HANDLE__ specifies the I2C Handle.
00489   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00490   *        This parameter can be one of the following values:
00491   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00492   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00493   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00494   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00495   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00496   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00497   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00498   *
00499   * @retval None
00500   */
00501 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00502
00503 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00504   * @param  __HANDLE__ specifies the I2C Handle.
00505   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00506   *          This parameter can be one of the following values:
00507   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00508   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00509   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00510   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00511   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00512   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00513   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00514   *
00515   * @retval The new state of __INTERRUPT__ (SET or RESET).
00516   */
00517 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
00518                                                                    (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00519
00520 /** @brief  Check whether the specified I2C flag is set or not.
00521   * @param  __HANDLE__ specifies the I2C Handle.
00522   * @param  __FLAG__ specifies the flag to check.
00523   *        This parameter can be one of the following values:
00524   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00525   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00526   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00527   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00528   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00529   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00530   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00531   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00532   *            @arg @ref I2C_FLAG_BERR    Bus error
00533   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00534   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00535   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00536   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00537   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00538   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00539   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00540   *
00541   * @retval The new state of __FLAG__ (SET or RESET).
00542   */
00543 #define I2C_FLAG_MASK  (0x0001FFFFU)
00544 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
00545                                                     (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00546
00547 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00548   * @param  __HANDLE__ specifies the I2C Handle.
00549   * @param  __FLAG__ specifies the flag to clear.
00550   *          This parameter can be any combination of the following values:
00551   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00552   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00553   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00554   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00555   *            @arg @ref I2C_FLAG_BERR    Bus error
00556   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00557   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00558   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00559   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00560   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00561   *
00562   * @retval None
00563   */
00564 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
00565                                                     ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
00566                                                     ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00567
00568 /** @brief  Enable the specified I2C peripheral.
00569   * @param  __HANDLE__ specifies the I2C Handle.
00570   * @retval None
00571   */
00572 #define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00573
00574 /** @brief  Disable the specified I2C peripheral.
00575   * @param  __HANDLE__ specifies the I2C Handle.
00576   * @retval None
00577   */
00578 #define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00579
00580 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00581   * @param  __HANDLE__ specifies the I2C Handle.
00582   * @retval None
00583   */
00584 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00585 /**
00586   * @}
00587   */
00588
00589 /* Include I2C HAL Extended module */
00590 #include "stm32g4xx_hal_i2c_ex.h"
00591
00592 /* Exported functions --------------------------------------------------------*/
00593 /** @addtogroup I2C_Exported_Functions
00594   * @{
00595   */
00596
00597 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00598   * @{
00599   */
00600 /* Initialization and de-initialization functions******************************/
00601 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00602 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
00603 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00604 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00605
00606 /* Callbacks Register/UnRegister functions  ***********************************/
00607 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00608 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
00609                                            pI2C_CallbackTypeDef pCallback);
00610 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
00611
00612 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
00613 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
00614 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00615 /**
00616   * @}
00617   */
00618
00619 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00620   * @{
00621   */
00622 /* IO operation functions  ****************************************************/
00623 /******* Blocking mode: Polling */
00624 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00625                                           uint16_t Size, uint32_t Timeout);
00626 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00627                                          uint16_t Size, uint32_t Timeout);
00628 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00629                                          uint32_t Timeout);
00630 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00631                                         uint32_t Timeout);
00632 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00633                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00634 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00635                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00636 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
00637                                         uint32_t Timeout);
00638
00639 /******* Non-Blocking mode: Interrupt */
00640 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00641                                              uint16_t Size);
00642 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00643                                             uint16_t Size);
00644 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00645 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00646 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00647                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00648 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00649                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00650
00651 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00652                                                  uint16_t Size, uint32_t XferOptions);
00653 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00654                                                 uint16_t Size, uint32_t XferOptions);
00655 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00656                                                 uint32_t XferOptions);
00657 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00658                                                uint32_t XferOptions);
00659 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00660 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00661 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00662
00663 /******* Non-Blocking mode: DMA */
00664 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00665                                               uint16_t Size);
00666 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00667                                              uint16_t Size);
00668 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00669 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00670 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00671                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00672 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00673                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00674
00675 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00676                                                   uint16_t Size, uint32_t XferOptions);
00677 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00678                                                  uint16_t Size, uint32_t XferOptions);
00679 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00680                                                  uint32_t XferOptions);
00681 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00682                                                 uint32_t XferOptions);
00683 /**
00684   * @}
00685   */
00686
00687 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00688   * @{
00689   */
00690 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00691 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00692 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00693 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00694 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00695 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00696 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00697 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00698 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00699 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00700 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00701 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00702 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00703 /**
00704   * @}
00705   */
00706
00707 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00708   * @{
00709   */
00710 /* Peripheral State, Mode and Error functions  *********************************/
00711 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
00712 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
00713 uint32_t             HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
00714
00715 /**
00716   * @}
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /* Private constants ---------------------------------------------------------*/
00724 /** @defgroup I2C_Private_Constants I2C Private Constants
00725   * @{
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /* Private macros ------------------------------------------------------------*/
00733 /** @defgroup I2C_Private_Macro I2C Private Macros
00734   * @{
00735   */
00736
00737 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00738                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00739
00740 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00741                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00742
00743 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00744                                          ((MASK) == I2C_OA2_MASK01) || \
00745                                          ((MASK) == I2C_OA2_MASK02) || \
00746                                          ((MASK) == I2C_OA2_MASK03) || \
00747                                          ((MASK) == I2C_OA2_MASK04) || \
00748                                          ((MASK) == I2C_OA2_MASK05) || \
00749                                          ((MASK) == I2C_OA2_MASK06) || \
00750                                          ((MASK) == I2C_OA2_MASK07))
00751
00752 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00753                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00754
00755 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00756                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00757
00758 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00759                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00760
00761 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00762                                          ((MODE) == I2C_AUTOEND_MODE) || \
00763                                          ((MODE) == I2C_SOFTEND_MODE))
00764
00765 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00766                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00767                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00768                                          ((REQUEST) == I2C_NO_STARTSTOP))
00769
00770 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00771                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00772                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00773                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00774                                                    ((REQUEST) == I2C_LAST_FRAME)           || \
00775                                                    ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
00776                                                    IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00777
00778 #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
00779                                                         ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
00780
00781 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
00782                                                    (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
00783                                                                           I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
00784                                                                           I2C_CR2_RD_WRN)))
00785
00786 #define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
00787                                                               >> 16U))
00788 #define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
00789                                                              >> 16U))
00790 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00791 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
00792 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
00793
00794 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00795 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00796
00797 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
00798                                                                          (uint16_t)(0xFF00U))) >> 8U)))
00799 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00800
00801 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
00802                                                      (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00803                                                                  (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
00804                                                                 (~I2C_CR2_RD_WRN)) : \
00805                                                      (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00806                                                                  (I2C_CR2_ADD10) | (I2C_CR2_START) | \
00807                                                                  (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
00808
00809 #define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
00810                                                     ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
00811 #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00812 /**
00813   * @}
00814   */
00815
00816 /* Private Functions ---------------------------------------------------------*/
00817 /** @defgroup I2C_Private_Functions I2C Private Functions
00818   * @{
00819   */
00820 /* Private functions are defined in stm32g4xx_hal_i2c.c file */
00821 /**
00822   * @}
00823   */
00824
00825 /**
00826   * @}
00827   */
00828
00829 /**
00830   * @}
00831   */
00832
00833 #ifdef __cplusplus
00834 }
00835 #endif
00836
00837
00838 #endif /* STM32G4xx_HAL_I2C_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_i2c_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2C Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2C Extended peripheral:
00008   *           + Filter Mode Functions
00009   *           + WakeUp Mode Functions
00010   *           + FastModePlus Functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                ##### I2C peripheral Extended features  #####
00026   ==============================================================================
00027
00028   [..] Comparing to other previous devices, the I2C interface for STM32G4xx
00029        devices contains the following additional features
00030
00031        (+) Possibility to disable or enable Analog Noise Filter
00032        (+) Use of a configured Digital Noise Filter
00033        (+) Disable or enable wakeup from Stop mode(s)
00034        (+) Disable or enable Fast Mode Plus
00035
00036                      ##### How to use this driver #####
00037   ==============================================================================
00038   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00039     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00040     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00041     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00042           (++) HAL_I2CEx_EnableWakeUp()
00043           (++) HAL_I2CEx_DisableWakeUp()
00044     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00045           (++) HAL_I2CEx_EnableFastModePlus()
00046           (++) HAL_I2CEx_DisableFastModePlus()
00047   @endverbatim
00048   */
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32g4xx_hal.h"
00052
00053 /** @addtogroup STM32G4xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @defgroup I2CEx I2CEx
00058   * @brief I2C Extended HAL module driver
00059   * @{
00060   */
00061
00062 #ifdef HAL_I2C_MODULE_ENABLED
00063
00064 /* Private typedef -----------------------------------------------------------*/
00065 /* Private define ------------------------------------------------------------*/
00066 /* Private macro -------------------------------------------------------------*/
00067 /* Private variables ---------------------------------------------------------*/
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Private functions ---------------------------------------------------------*/
00070
00071 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
00076   * @brief    Filter Mode Functions
00077   *
00078 @verbatim
00079  ===============================================================================
00080                       ##### Filter Mode Functions #####
00081  ===============================================================================
00082     [..] This section provides functions allowing to:
00083       (+) Configure Noise Filters
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Configure I2C Analog noise filter.
00091   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00092   *                the configuration information for the specified I2Cx peripheral.
00093   * @param  AnalogFilter New state of the Analog filter.
00094   * @retval HAL status
00095   */
00096 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00097 {
00098   /* Check the parameters */
00099   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00100   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00101
00102   if (hi2c->State == HAL_I2C_STATE_READY)
00103   {
00104     /* Process Locked */
00105     __HAL_LOCK(hi2c);
00106
00107     hi2c->State = HAL_I2C_STATE_BUSY;
00108
00109     /* Disable the selected I2C peripheral */
00110     __HAL_I2C_DISABLE(hi2c);
00111
00112     /* Reset I2Cx ANOFF bit */
00113     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00114
00115     /* Set analog filter bit*/
00116     hi2c->Instance->CR1 |= AnalogFilter;
00117
00118     __HAL_I2C_ENABLE(hi2c);
00119
00120     hi2c->State = HAL_I2C_STATE_READY;
00121
00122     /* Process Unlocked */
00123     __HAL_UNLOCK(hi2c);
00124
00125     return HAL_OK;
00126   }
00127   else
00128   {
00129     return HAL_BUSY;
00130   }
00131 }
00132
00133 /**
00134   * @brief  Configure I2C Digital noise filter.
00135   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00136   *                the configuration information for the specified I2Cx peripheral.
00137   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00138   * @retval HAL status
00139   */
00140 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00141 {
00142   uint32_t tmpreg;
00143
00144   /* Check the parameters */
00145   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00146   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00147
00148   if (hi2c->State == HAL_I2C_STATE_READY)
00149   {
00150     /* Process Locked */
00151     __HAL_LOCK(hi2c);
00152
00153     hi2c->State = HAL_I2C_STATE_BUSY;
00154
00155     /* Disable the selected I2C peripheral */
00156     __HAL_I2C_DISABLE(hi2c);
00157
00158     /* Get the old register value */
00159     tmpreg = hi2c->Instance->CR1;
00160
00161     /* Reset I2Cx DNF bits [11:8] */
00162     tmpreg &= ~(I2C_CR1_DNF);
00163
00164     /* Set I2Cx DNF coefficient */
00165     tmpreg |= DigitalFilter << 8U;
00166
00167     /* Store the new register value */
00168     hi2c->Instance->CR1 = tmpreg;
00169
00170     __HAL_I2C_ENABLE(hi2c);
00171
00172     hi2c->State = HAL_I2C_STATE_READY;
00173
00174     /* Process Unlocked */
00175     __HAL_UNLOCK(hi2c);
00176
00177     return HAL_OK;
00178   }
00179   else
00180   {
00181     return HAL_BUSY;
00182   }
00183 }
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
00189   * @brief    WakeUp Mode Functions
00190   *
00191 @verbatim
00192  ===============================================================================
00193                       ##### WakeUp Mode Functions #####
00194  ===============================================================================
00195     [..] This section provides functions allowing to:
00196       (+) Configure Wake Up Feature
00197
00198 @endverbatim
00199   * @{
00200   */
00201
00202 /**
00203   * @brief  Enable I2C wakeup from Stop mode(s).
00204   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00205   *                the configuration information for the specified I2Cx peripheral.
00206   * @retval HAL status
00207   */
00208 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
00209 {
00210   /* Check the parameters */
00211   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00212
00213   if (hi2c->State == HAL_I2C_STATE_READY)
00214   {
00215     /* Process Locked */
00216     __HAL_LOCK(hi2c);
00217
00218     hi2c->State = HAL_I2C_STATE_BUSY;
00219
00220     /* Disable the selected I2C peripheral */
00221     __HAL_I2C_DISABLE(hi2c);
00222
00223     /* Enable wakeup from stop mode */
00224     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00225
00226     __HAL_I2C_ENABLE(hi2c);
00227
00228     hi2c->State = HAL_I2C_STATE_READY;
00229
00230     /* Process Unlocked */
00231     __HAL_UNLOCK(hi2c);
00232
00233     return HAL_OK;
00234   }
00235   else
00236   {
00237     return HAL_BUSY;
00238   }
00239 }
00240
00241 /**
00242   * @brief  Disable I2C wakeup from Stop mode(s).
00243   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00244   *                the configuration information for the specified I2Cx peripheral.
00245   * @retval HAL status
00246   */
00247 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
00248 {
00249   /* Check the parameters */
00250   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00251
00252   if (hi2c->State == HAL_I2C_STATE_READY)
00253   {
00254     /* Process Locked */
00255     __HAL_LOCK(hi2c);
00256
00257     hi2c->State = HAL_I2C_STATE_BUSY;
00258
00259     /* Disable the selected I2C peripheral */
00260     __HAL_I2C_DISABLE(hi2c);
00261
00262     /* Enable wakeup from stop mode */
00263     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00264
00265     __HAL_I2C_ENABLE(hi2c);
00266
00267     hi2c->State = HAL_I2C_STATE_READY;
00268
00269     /* Process Unlocked */
00270     __HAL_UNLOCK(hi2c);
00271
00272     return HAL_OK;
00273   }
00274   else
00275   {
00276     return HAL_BUSY;
00277   }
00278 }
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
00284   * @brief    Fast Mode Plus Functions
00285   *
00286 @verbatim
00287  ===============================================================================
00288                       ##### Fast Mode Plus Functions #####
00289  ===============================================================================
00290     [..] This section provides functions allowing to:
00291       (+) Configure Fast Mode Plus
00292
00293 @endverbatim
00294   * @{
00295   */
00296
00297 /**
00298   * @brief Enable the I2C fast mode plus driving capability.
00299   * @param ConfigFastModePlus Selects the pin.
00300   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00301   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00302   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00303   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00304   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00305   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00306   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00307   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00308   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00309   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00310   * @note  For all I2C4 pins fast mode plus driving capability can be enabled
00311   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
00312   * @retval None
00313   */
00314 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00315 {
00316   /* Check the parameter */
00317   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00318
00319   /* Enable SYSCFG clock */
00320   __HAL_RCC_SYSCFG_CLK_ENABLE();
00321
00322   /* Enable fast mode plus driving capability for selected pin */
00323   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00324 }
00325
00326 /**
00327   * @brief Disable the I2C fast mode plus driving capability.
00328   * @param ConfigFastModePlus Selects the pin.
00329   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00330   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00331   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00332   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00333   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00334   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00335   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00336   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00337   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00338   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00339   * @note  For all I2C4 pins fast mode plus driving capability can be disabled
00340   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
00341   * @retval None
00342   */
00343 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00344 {
00345   /* Check the parameter */
00346   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00347
00348   /* Enable SYSCFG clock */
00349   __HAL_RCC_SYSCFG_CLK_ENABLE();
00350
00351   /* Disable fast mode plus driving capability for selected pin */
00352   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00353 }
00354 /**
00355   * @}
00356   */
00357 /**
00358   * @}
00359   */
00360
00361 #endif /* HAL_I2C_MODULE_ENABLED */
00362 /**
00363   * @}
00364   */
00365
00366 /**
00367   * @}
00368   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2c_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_I2C_EX_H
00021 #define STM32G4xx_HAL_I2C_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup I2CEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00045   * @{
00046   */
00047 #define I2C_ANALOGFILTER_ENABLE         0x00000000U
00048 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00049 /**
00050   * @}
00051   */
00052
00053 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00054   * @{
00055   */
00056 #define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00057 #define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00058 #define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00059 #define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00060 #define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00061 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00062 #define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00063 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00064 #if defined(SYSCFG_CFGR1_I2C4_FMP)
00065 #define I2C_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
00066 #else
00067 #define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
00068 #endif /* SYSCFG_CFGR1_I2C4_FMP */
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported macro ------------------------------------------------------------*/
00078 /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
00079   * @{
00080   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /* Exported functions --------------------------------------------------------*/
00087 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00088   * @{
00089   */
00090
00091 /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
00092   * @{
00093   */
00094 /* Peripheral Control functions  ************************************************/
00095 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00096 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00097 /**
00098   * @}
00099   */
00100
00101 /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
00102   * @{
00103   */
00104 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00105 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00106 /**
00107   * @}
00108   */
00109
00110 /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
00111   * @{
00112   */
00113 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00114 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00115 /**
00116   * @}
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private constants ---------------------------------------------------------*/
00124 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00125   * @{
00126   */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Private macros ------------------------------------------------------------*/
00133 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00134   * @{
00135   */
00136 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00137                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00138
00139 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00140
00141 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
00142                                          ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
00143                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
00144                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
00145                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
00146                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
00147                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
00148                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)    || \
00149                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
00150 /**
00151   * @}
00152   */
00153
00154 /* Private Functions ---------------------------------------------------------*/
00155 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00156   * @{
00157   */
00158 /* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 #ifdef __cplusplus
00172 }
00173 #endif
00174
00175 #endif /* STM32G4xx_HAL_I2C_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2s.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_i2s.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @brief   I2S HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023  ===============================================================================
00024                   ##### How to use this driver #####
00025  ===============================================================================
00026  [..]
00027     The I2S HAL driver can be used as follow:
00028
00029     (#) Declare a I2S_HandleTypeDef handle structure.
00030     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00031         (##) Enable the SPIx interface clock.
00032         (##) I2S pins configuration:
00033             (+++) Enable the clock for the I2S GPIOs.
00034             (+++) Configure these I2S pins as alternate function pull-up.
00035         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00036              and HAL_I2S_Receive_IT() APIs).
00037             (+++) Configure the I2Sx interrupt priority.
00038             (+++) Enable the NVIC I2S IRQ handle.
00039         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00040              and HAL_I2S_Receive_DMA() APIs:
00041             (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
00042             (+++) Enable the DMAx interface clock.
00043             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00044             (+++) Configure the DMA Tx/Rx Stream/Channel.
00045             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00046             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00047                   DMA Tx/Rx Stream/Channel.
00048
00049    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00050        using HAL_I2S_Init() function.
00051
00052    -@- The specific I2S interrupts (Transmission complete interrupt,
00053        RXNE interrupt and Error Interrupts) will be managed using the macros
00054        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00055    -@- Make sure that either:
00056         (+@) SYSCLK is configured or
00057         (+@) PLLADCCLK output is configured or
00058         (+@) HSI is enabled or
00059         (+@) External clock source is configured after setting correctly
00060              the define constant EXTERNAL_CLOCK_VALUE in the stm32g4xx_hal_conf.h file.
00061
00062     (#) Three mode of operations are available within this driver :
00063
00064    *** Polling mode IO operation ***
00065    =================================
00066    [..]
00067      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00068      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00069
00070    *** Interrupt mode IO operation ***
00071    ===================================
00072    [..]
00073      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00074      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00075          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00076      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00077          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00078      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00079      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00080          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00081      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00083      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00084          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00085
00086    *** DMA mode IO operation ***
00087    ==============================
00088    [..]
00089      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00090      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00091          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00092      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00093          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00094      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00095      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00096          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00097      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00098          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00099      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00100          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00101      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00102      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00103      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00104          In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
00105          HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
00106          In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
00107          inside DR register and avoid using DeInit/Init process for the next transfer.
00108
00109    *** I2S HAL driver macros list ***
00110    ===================================
00111    [..]
00112      Below the list of most used macros in I2S HAL driver.
00113
00114       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00115       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00116       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00117       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00118       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00119       (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
00120
00121     [..]
00122       (@) You can refer to the I2S HAL driver header file for more useful macros
00123
00124    *** I2S HAL driver macros list ***
00125    ===================================
00126    [..]
00127        Callback registration:
00128
00129       (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
00130           allows the user to configure dynamically the driver callbacks.
00131           Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
00132
00133           Function HAL_I2S_RegisterCallback() allows to register following callbacks:
00134             (++) TxCpltCallback        : I2S Tx Completed callback
00135             (++) RxCpltCallback        : I2S Rx Completed callback
00136             (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
00137             (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
00138             (++) ErrorCallback         : I2S Error callback
00139             (++) MspInitCallback       : I2S Msp Init callback
00140             (++) MspDeInitCallback     : I2S Msp DeInit callback
00141           This function takes as parameters the HAL peripheral handle, the Callback ID
00142           and a pointer to the user callback function.
00143
00144
00145       (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
00146           weak function.
00147           HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
00148           and the Callback ID.
00149           This function allows to reset following callbacks:
00150             (++) TxCpltCallback        : I2S Tx Completed callback
00151             (++) RxCpltCallback        : I2S Rx Completed callback
00152             (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
00153             (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
00154             (++) ErrorCallback         : I2S Error callback
00155             (++) MspInitCallback       : I2S Msp Init callback
00156             (++) MspDeInitCallback     : I2S Msp DeInit callback
00157
00158        [..]
00159        By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
00160        all callbacks are set to the corresponding weak functions:
00161        examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
00162        Exception done for MspInit and MspDeInit functions that are
00163        reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
00164        these callbacks are null (not registered beforehand).
00165        If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
00166        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00167
00168        [..]
00169        Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
00170        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00171        in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
00172        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00173        Then, the user first registers the MspInit/MspDeInit user callbacks
00174        using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
00175        or HAL_I2S_Init() function.
00176
00177        [..]
00178        When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
00179        not defined, the callback registering feature is not available
00180        and weak (surcharged) callbacks are used.
00181
00182   @endverbatim
00183
00184   */
00185
00186 /* Includes ------------------------------------------------------------------*/
00187 #include "stm32g4xx_hal.h"
00188
00189 #ifdef HAL_I2S_MODULE_ENABLED
00190
00191 #if defined(SPI_I2S_SUPPORT)
00192 /** @addtogroup STM32G4xx_HAL_Driver
00193   * @{
00194   */
00195
00196 /** @defgroup I2S I2S
00197   * @brief I2S HAL module driver
00198   * @{
00199   */
00200
00201 /* Private typedef -----------------------------------------------------------*/
00202 /* Private define ------------------------------------------------------------*/
00203 #define I2S_TIMEOUT_FLAG          100U         /*!< Timeout 100 ms            */
00204 /* Private macro -------------------------------------------------------------*/
00205 /* Private variables ---------------------------------------------------------*/
00206 /* Private function prototypes -----------------------------------------------*/
00207 /** @defgroup I2S_Private_Functions I2S Private Functions
00208   * @{
00209   */
00210 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00211 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00212 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00213 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00214 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00215 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00216 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00217 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
00218                                                         uint32_t Timeout);
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported functions ---------------------------------------------------------*/
00224
00225 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00226   * @{
00227   */
00228
00229 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00230   *  @brief    Initialization and Configuration functions
00231   *
00232 @verbatim
00233  ===============================================================================
00234               ##### Initialization and de-initialization functions #####
00235  ===============================================================================
00236     [..]  This subsection provides a set of functions allowing to initialize and
00237           de-initialize the I2Sx peripheral in simplex mode:
00238
00239       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00240           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00241
00242       (+) Call the function HAL_I2S_Init() to configure the selected device with
00243           the selected configuration:
00244         (++) Mode
00245         (++) Standard
00246         (++) Data Format
00247         (++) MCLK Output
00248         (++) Audio frequency
00249         (++) Polarity
00250
00251      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00252           of the selected I2Sx peripheral.
00253   @endverbatim
00254   * @{
00255   */
00256
00257 /**
00258   * @brief  Initializes the I2S according to the specified parameters
00259   *         in the I2S_InitTypeDef and create the associated handle.
00260   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00261   *         the configuration information for I2S module
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00265 {
00266   uint32_t i2sdiv;
00267   uint32_t i2sodd;
00268   uint32_t packetlength;
00269   uint32_t tmp;
00270   uint32_t i2sclk;
00271
00272   /* Check the I2S handle allocation */
00273   if (hi2s == NULL)
00274   {
00275     return HAL_ERROR;
00276   }
00277
00278   /* Check the I2S parameters */
00279   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00280   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00281   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00282   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00283   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00284   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00285   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00286
00287   if (hi2s->State == HAL_I2S_STATE_RESET)
00288   {
00289     /* Allocate lock resource and initialize it */
00290     hi2s->Lock = HAL_UNLOCKED;
00291
00292 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00293     /* Init the I2S Callback settings */
00294     hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
00295     hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
00296     hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
00297     hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
00298     hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
00299
00300     if (hi2s->MspInitCallback == NULL)
00301     {
00302       hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
00303     }
00304
00305     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00306     hi2s->MspInitCallback(hi2s);
00307 #else
00308     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00309     HAL_I2S_MspInit(hi2s);
00310 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00311   }
00312
00313   hi2s->State = HAL_I2S_STATE_BUSY;
00314
00315   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
00316   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00317   CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00318                                       SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00319                                       SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
00320   hi2s->Instance->I2SPR = 0x0002U;
00321
00322   /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
00323   /* If the requested audio frequency is not the default, compute the prescaler */
00324   if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00325   {
00326     /* Check the frame length (For the Prescaler computing) ********************/
00327     if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
00328     {
00329       /* Packet length is 16 bits */
00330       packetlength = 16U;
00331     }
00332     else
00333     {
00334       /* Packet length is 32 bits */
00335       packetlength = 32U;
00336     }
00337
00338     /* I2S standard */
00339     if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
00340     {
00341       /* In I2S standard packet length is multiplied by 2 */
00342       packetlength = packetlength * 2U;
00343     }
00344
00345     /* Get the source clock value: based on System Clock value */
00346     i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
00347
00348     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00349     if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00350     {
00351       /* MCLK output is enabled */
00352       if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00353       {
00354         tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00355       }
00356       else
00357       {
00358         tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00359       }
00360     }
00361     else
00362     {
00363       /* MCLK output is disabled */
00364       tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00365     }
00366
00367     /* Remove the flatting point */
00368     tmp = tmp / 10U;
00369
00370     /* Check the parity of the divider */
00371     i2sodd = (uint32_t)(tmp & (uint32_t)1U);
00372
00373     /* Compute the i2sdiv prescaler */
00374     i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
00375
00376     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00377     i2sodd = (uint32_t)(i2sodd << 8U);
00378   }
00379   else
00380   {
00381     /* Set the default values */
00382     i2sdiv = 2U;
00383     i2sodd = 0U;
00384   }
00385
00386   /* Test if the divider is 1 or 0 or greater than 0xFF */
00387   if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00388   {
00389     /* Set the error code and execute error callback*/
00390     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
00391     return  HAL_ERROR;
00392   }
00393
00394   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
00395
00396   /* Write to SPIx I2SPR register the computed value */
00397   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
00398
00399   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00400   /* And configure the I2S with the I2S_InitStruct values                      */
00401   MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
00402                                        SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
00403                                        SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00404                                        SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD), \
00405              (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
00406               hi2s->Init.Standard | hi2s->Init.DataFormat | \
00407               hi2s->Init.CPOL));
00408
00409 #if defined(SPI_I2SCFGR_ASTRTEN)
00410   if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
00411   {
00412     /* Write to SPIx I2SCFGR */
00413     SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
00414   }
00415 #endif /* SPI_I2SCFGR_ASTRTEN */
00416
00417   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00418   hi2s->State     = HAL_I2S_STATE_READY;
00419
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief DeInitializes the I2S peripheral
00425   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00426   *         the configuration information for I2S module
00427   * @retval HAL status
00428   */
00429 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00430 {
00431   /* Check the I2S handle allocation */
00432   if (hi2s == NULL)
00433   {
00434     return HAL_ERROR;
00435   }
00436
00437   /* Check the parameters */
00438   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00439
00440   hi2s->State = HAL_I2S_STATE_BUSY;
00441
00442   /* Disable the I2S Peripheral Clock */
00443   __HAL_I2S_DISABLE(hi2s);
00444
00445 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00446   if (hi2s->MspDeInitCallback == NULL)
00447   {
00448     hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
00449   }
00450
00451   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00452   hi2s->MspDeInitCallback(hi2s);
00453 #else
00454   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00455   HAL_I2S_MspDeInit(hi2s);
00456 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00457
00458   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00459   hi2s->State     = HAL_I2S_STATE_RESET;
00460
00461   /* Release Lock */
00462   __HAL_UNLOCK(hi2s);
00463
00464   return HAL_OK;
00465 }
00466
00467 /**
00468   * @brief I2S MSP Init
00469   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00470   *         the configuration information for I2S module
00471   * @retval None
00472   */
00473 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00474 {
00475   /* Prevent unused argument(s) compilation warning */
00476   UNUSED(hi2s);
00477
00478   /* NOTE : This function Should not be modified, when the callback is needed,
00479             the HAL_I2S_MspInit could be implemented in the user file
00480    */
00481 }
00482
00483 /**
00484   * @brief I2S MSP DeInit
00485   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00486   *         the configuration information for I2S module
00487   * @retval None
00488   */
00489 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00490 {
00491   /* Prevent unused argument(s) compilation warning */
00492   UNUSED(hi2s);
00493
00494   /* NOTE : This function Should not be modified, when the callback is needed,
00495             the HAL_I2S_MspDeInit could be implemented in the user file
00496    */
00497 }
00498
00499 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00500 /**
00501   * @brief  Register a User I2S Callback
00502   *         To be used instead of the weak predefined callback
00503   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00504   *                the configuration information for the specified I2S.
00505   * @param  CallbackID ID of the callback to be registered
00506   * @param  pCallback pointer to the Callback function
00507   * @retval HAL status
00508   */
00509 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
00510                                            pI2S_CallbackTypeDef pCallback)
00511 {
00512   HAL_StatusTypeDef status = HAL_OK;
00513
00514   if (pCallback == NULL)
00515   {
00516     /* Update the error code */
00517     hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
00518
00519     return HAL_ERROR;
00520   }
00521   /* Process locked */
00522   __HAL_LOCK(hi2s);
00523
00524   if (HAL_I2S_STATE_READY == hi2s->State)
00525   {
00526     switch (CallbackID)
00527     {
00528       case HAL_I2S_TX_COMPLETE_CB_ID :
00529         hi2s->TxCpltCallback = pCallback;
00530         break;
00531
00532       case HAL_I2S_RX_COMPLETE_CB_ID :
00533         hi2s->RxCpltCallback = pCallback;
00534         break;
00535
00536       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00537         hi2s->TxHalfCpltCallback = pCallback;
00538         break;
00539
00540       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00541         hi2s->RxHalfCpltCallback = pCallback;
00542         break;
00543
00544       case HAL_I2S_ERROR_CB_ID :
00545         hi2s->ErrorCallback = pCallback;
00546         break;
00547
00548       case HAL_I2S_MSPINIT_CB_ID :
00549         hi2s->MspInitCallback = pCallback;
00550         break;
00551
00552       case HAL_I2S_MSPDEINIT_CB_ID :
00553         hi2s->MspDeInitCallback = pCallback;
00554         break;
00555
00556       default :
00557         /* Update the error code */
00558         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00559
00560         /* Return error status */
00561         status =  HAL_ERROR;
00562         break;
00563     }
00564   }
00565   else if (HAL_I2S_STATE_RESET == hi2s->State)
00566   {
00567     switch (CallbackID)
00568     {
00569       case HAL_I2S_MSPINIT_CB_ID :
00570         hi2s->MspInitCallback = pCallback;
00571         break;
00572
00573       case HAL_I2S_MSPDEINIT_CB_ID :
00574         hi2s->MspDeInitCallback = pCallback;
00575         break;
00576
00577       default :
00578         /* Update the error code */
00579         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00580
00581         /* Return error status */
00582         status =  HAL_ERROR;
00583         break;
00584     }
00585   }
00586   else
00587   {
00588     /* Update the error code */
00589     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00590
00591     /* Return error status */
00592     status =  HAL_ERROR;
00593   }
00594
00595   /* Release Lock */
00596   __HAL_UNLOCK(hi2s);
00597   return status;
00598 }
00599
00600 /**
00601   * @brief  Unregister an I2S Callback
00602   *         I2S callback is redirected to the weak predefined callback
00603   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00604   *                the configuration information for the specified I2S.
00605   * @param  CallbackID ID of the callback to be unregistered
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
00609 {
00610   HAL_StatusTypeDef status = HAL_OK;
00611
00612   /* Process locked */
00613   __HAL_LOCK(hi2s);
00614
00615   if (HAL_I2S_STATE_READY == hi2s->State)
00616   {
00617     switch (CallbackID)
00618     {
00619       case HAL_I2S_TX_COMPLETE_CB_ID :
00620         hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
00621         break;
00622
00623       case HAL_I2S_RX_COMPLETE_CB_ID :
00624         hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
00625         break;
00626
00627       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00628         hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
00629         break;
00630
00631       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00632         hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
00633         break;
00634
00635       case HAL_I2S_ERROR_CB_ID :
00636         hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
00637         break;
00638
00639       case HAL_I2S_MSPINIT_CB_ID :
00640         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00641         break;
00642
00643       case HAL_I2S_MSPDEINIT_CB_ID :
00644         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00645         break;
00646
00647       default :
00648         /* Update the error code */
00649         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00650
00651         /* Return error status */
00652         status =  HAL_ERROR;
00653         break;
00654     }
00655   }
00656   else if (HAL_I2S_STATE_RESET == hi2s->State)
00657   {
00658     switch (CallbackID)
00659     {
00660       case HAL_I2S_MSPINIT_CB_ID :
00661         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00662         break;
00663
00664       case HAL_I2S_MSPDEINIT_CB_ID :
00665         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00666         break;
00667
00668       default :
00669         /* Update the error code */
00670         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00671
00672         /* Return error status */
00673         status =  HAL_ERROR;
00674         break;
00675     }
00676   }
00677   else
00678   {
00679     /* Update the error code */
00680     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00681
00682     /* Return error status */
00683     status =  HAL_ERROR;
00684   }
00685
00686   /* Release Lock */
00687   __HAL_UNLOCK(hi2s);
00688   return status;
00689 }
00690 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00696   *  @brief Data transfers functions
00697   *
00698 @verbatim
00699  ===============================================================================
00700                       ##### IO operation functions #####
00701  ===============================================================================
00702     [..]
00703     This subsection provides a set of functions allowing to manage the I2S data
00704     transfers.
00705
00706     (#) There are two modes of transfer:
00707        (++) Blocking mode : The communication is performed in the polling mode.
00708             The status of all data processing is returned by the same function
00709             after finishing transfer.
00710        (++) No-Blocking mode : The communication is performed using Interrupts
00711             or DMA. These functions return the status of the transfer startup.
00712             The end of the data processing will be indicated through the
00713             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00714             using DMA mode.
00715
00716     (#) Blocking mode functions are :
00717         (++) HAL_I2S_Transmit()
00718         (++) HAL_I2S_Receive()
00719
00720     (#) No-Blocking mode functions with Interrupt are :
00721         (++) HAL_I2S_Transmit_IT()
00722         (++) HAL_I2S_Receive_IT()
00723
00724     (#) No-Blocking mode functions with DMA are :
00725         (++) HAL_I2S_Transmit_DMA()
00726         (++) HAL_I2S_Receive_DMA()
00727
00728     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00729         (++) HAL_I2S_TxCpltCallback()
00730         (++) HAL_I2S_RxCpltCallback()
00731         (++) HAL_I2S_ErrorCallback()
00732
00733 @endverbatim
00734   * @{
00735   */
00736
00737 /**
00738   * @brief  Transmit an amount of data in blocking mode
00739   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00740   *         the configuration information for I2S module
00741   * @param  pData a 16-bit pointer to data buffer.
00742   * @param  Size number of data sample to be sent:
00743   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00744   *         configuration phase, the Size parameter means the number of 16-bit data length
00745   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00746   *         the Size parameter means the number of 24-bit or 32-bit data length.
00747   * @param  Timeout Timeout duration
00748   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00749   *         between Master and Slave(example: audio streaming).
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00753 {
00754   uint32_t tmpreg_cfgr;
00755
00756   if ((pData == NULL) || (Size == 0U))
00757   {
00758     return  HAL_ERROR;
00759   }
00760
00761   /* Process Locked */
00762   __HAL_LOCK(hi2s);
00763
00764   if (hi2s->State != HAL_I2S_STATE_READY)
00765   {
00766     __HAL_UNLOCK(hi2s);
00767     return HAL_BUSY;
00768   }
00769
00770   /* Set state and reset error code */
00771   hi2s->State = HAL_I2S_STATE_BUSY_TX;
00772   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00773   hi2s->pTxBuffPtr = pData;
00774
00775   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00776
00777   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
00778   {
00779     hi2s->TxXferSize = (Size << 1U);
00780     hi2s->TxXferCount = (Size << 1U);
00781   }
00782   else
00783   {
00784     hi2s->TxXferSize = Size;
00785     hi2s->TxXferCount = Size;
00786   }
00787
00788   tmpreg_cfgr = hi2s->Instance->I2SCFGR;
00789
00790   /* Check if the I2S is already enabled */
00791   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00792   {
00793     /* Enable I2S peripheral */
00794     __HAL_I2S_ENABLE(hi2s);
00795   }
00796
00797   /* Wait until TXE flag is set */
00798   if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00799   {
00800     /* Set the error code */
00801     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00802     hi2s->State = HAL_I2S_STATE_READY;
00803     __HAL_UNLOCK(hi2s);
00804     return HAL_ERROR;
00805   }
00806
00807   while (hi2s->TxXferCount > 0U)
00808   {
00809     hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
00810     hi2s->pTxBuffPtr++;
00811     hi2s->TxXferCount--;
00812
00813     /* Wait until TXE flag is set */
00814     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00815     {
00816       /* Set the error code */
00817       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00818       hi2s->State = HAL_I2S_STATE_READY;
00819       __HAL_UNLOCK(hi2s);
00820       return HAL_ERROR;
00821     }
00822
00823     /* Check if an underrun occurs */
00824     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00825     {
00826       /* Clear underrun flag */
00827       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00828
00829       /* Set the error code */
00830       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00831     }
00832   }
00833
00834   /* Check if Slave mode is selected */
00835   if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
00836       || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
00837   {
00838     /* Wait until Busy flag is reset */
00839     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
00840     {
00841       /* Set the error code */
00842       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00843       hi2s->State = HAL_I2S_STATE_READY;
00844       __HAL_UNLOCK(hi2s);
00845       return HAL_ERROR;
00846     }
00847   }
00848
00849   hi2s->State = HAL_I2S_STATE_READY;
00850   __HAL_UNLOCK(hi2s);
00851   return HAL_OK;
00852 }
00853
00854 /**
00855   * @brief  Receive an amount of data in blocking mode
00856   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00857   *         the configuration information for I2S module
00858   * @param  pData a 16-bit pointer to data buffer.
00859   * @param  Size number of data sample to be sent:
00860   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00861   *         configuration phase, the Size parameter means the number of 16-bit data length
00862   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00863   *         the Size parameter means the number of 24-bit or 32-bit data length.
00864   * @param  Timeout Timeout duration
00865   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00866   *         between Master and Slave(example: audio streaming).
00867   * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00868   *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00869   * @retval HAL status
00870   */
00871 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00872 {
00873   uint32_t tmpreg_cfgr;
00874
00875   if ((pData == NULL) || (Size == 0U))
00876   {
00877     return  HAL_ERROR;
00878   }
00879
00880   /* Process Locked */
00881   __HAL_LOCK(hi2s);
00882
00883   if (hi2s->State != HAL_I2S_STATE_READY)
00884   {
00885     __HAL_UNLOCK(hi2s);
00886     return HAL_BUSY;
00887   }
00888
00889   /* Set state and reset error code */
00890   hi2s->State = HAL_I2S_STATE_BUSY_RX;
00891   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00892   hi2s->pRxBuffPtr = pData;
00893
00894   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00895
00896   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
00897   {
00898     hi2s->RxXferSize = (Size << 1U);
00899     hi2s->RxXferCount = (Size << 1U);
00900   }
00901   else
00902   {
00903     hi2s->RxXferSize = Size;
00904     hi2s->RxXferCount = Size;
00905   }
00906
00907   /* Check if the I2S is already enabled */
00908   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00909   {
00910     /* Enable I2S peripheral */
00911     __HAL_I2S_ENABLE(hi2s);
00912   }
00913
00914   /* Check if Master Receiver mode is selected */
00915   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00916   {
00917     /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00918     access to the SPI_SR register. */
00919     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00920   }
00921
00922   /* Receive data */
00923   while (hi2s->RxXferCount > 0U)
00924   {
00925     /* Wait until RXNE flag is set */
00926     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
00927     {
00928       /* Set the error code */
00929       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00930       hi2s->State = HAL_I2S_STATE_READY;
00931       __HAL_UNLOCK(hi2s);
00932       return HAL_ERROR;
00933     }
00934
00935     (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
00936     hi2s->pRxBuffPtr++;
00937     hi2s->RxXferCount--;
00938
00939     /* Check if an overrun occurs */
00940     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00941     {
00942       /* Clear overrun flag */
00943       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00944
00945       /* Set the error code */
00946       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00947     }
00948   }
00949
00950   hi2s->State = HAL_I2S_STATE_READY;
00951   __HAL_UNLOCK(hi2s);
00952   return HAL_OK;
00953 }
00954
00955 /**
00956   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
00957   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00958   *         the configuration information for I2S module
00959   * @param  pData a 16-bit pointer to data buffer.
00960   * @param  Size number of data sample to be sent:
00961   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00962   *         configuration phase, the Size parameter means the number of 16-bit data length
00963   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00964   *         the Size parameter means the number of 24-bit or 32-bit data length.
00965   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00966   *         between Master and Slave(example: audio streaming).
00967   * @retval HAL status
00968   */
00969 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00970 {
00971   uint32_t tmpreg_cfgr;
00972
00973   if ((pData == NULL) || (Size == 0U))
00974   {
00975     return  HAL_ERROR;
00976   }
00977
00978   /* Process Locked */
00979   __HAL_LOCK(hi2s);
00980
00981   if (hi2s->State != HAL_I2S_STATE_READY)
00982   {
00983     __HAL_UNLOCK(hi2s);
00984     return HAL_BUSY;
00985   }
00986
00987   /* Set state and reset error code */
00988   hi2s->State = HAL_I2S_STATE_BUSY_TX;
00989   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00990   hi2s->pTxBuffPtr = pData;
00991
00992   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00993
00994   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
00995   {
00996     hi2s->TxXferSize = (Size << 1U);
00997     hi2s->TxXferCount = (Size << 1U);
00998   }
00999   else
01000   {
01001     hi2s->TxXferSize = Size;
01002     hi2s->TxXferCount = Size;
01003   }
01004
01005   /* Enable TXE and ERR interrupt */
01006   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01007
01008   /* Check if the I2S is already enabled */
01009   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01010   {
01011     /* Enable I2S peripheral */
01012     __HAL_I2S_ENABLE(hi2s);
01013   }
01014
01015   __HAL_UNLOCK(hi2s);
01016   return HAL_OK;
01017 }
01018
01019 /**
01020   * @brief  Receive an amount of data in non-blocking mode with Interrupt
01021   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01022   *         the configuration information for I2S module
01023   * @param  pData a 16-bit pointer to the Receive data buffer.
01024   * @param  Size number of data sample to be sent:
01025   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01026   *         configuration phase, the Size parameter means the number of 16-bit data length
01027   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01028   *         the Size parameter means the number of 24-bit or 32-bit data length.
01029   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01030   *         between Master and Slave(example: audio streaming).
01031   * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
01032   * between Master and Slave otherwise the I2S interrupt should be optimized.
01033   * @retval HAL status
01034   */
01035 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01036 {
01037   uint32_t tmpreg_cfgr;
01038
01039   if ((pData == NULL) || (Size == 0U))
01040   {
01041     return  HAL_ERROR;
01042   }
01043
01044   /* Process Locked */
01045   __HAL_LOCK(hi2s);
01046
01047   if (hi2s->State != HAL_I2S_STATE_READY)
01048   {
01049     __HAL_UNLOCK(hi2s);
01050     return HAL_BUSY;
01051   }
01052
01053   /* Set state and reset error code */
01054   hi2s->State = HAL_I2S_STATE_BUSY_RX;
01055   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01056   hi2s->pRxBuffPtr = pData;
01057
01058   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01059
01060   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01061   {
01062     hi2s->RxXferSize = (Size << 1U);
01063     hi2s->RxXferCount = (Size << 1U);
01064   }
01065   else
01066   {
01067     hi2s->RxXferSize = Size;
01068     hi2s->RxXferCount = Size;
01069   }
01070
01071   /* Enable RXNE and ERR interrupt */
01072   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01073
01074   /* Check if the I2S is already enabled */
01075   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01076   {
01077     /* Enable I2S peripheral */
01078     __HAL_I2S_ENABLE(hi2s);
01079   }
01080
01081   __HAL_UNLOCK(hi2s);
01082   return HAL_OK;
01083 }
01084
01085 /**
01086   * @brief  Transmit an amount of data in non-blocking mode with DMA
01087   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01088   *         the configuration information for I2S module
01089   * @param  pData a 16-bit pointer to the Transmit data buffer.
01090   * @param  Size number of data sample to be sent:
01091   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01092   *         configuration phase, the Size parameter means the number of 16-bit data length
01093   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01094   *         the Size parameter means the number of 24-bit or 32-bit data length.
01095   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01096   *         between Master and Slave(example: audio streaming).
01097   * @retval HAL status
01098   */
01099 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01100 {
01101   uint32_t tmpreg_cfgr;
01102
01103   if ((pData == NULL) || (Size == 0U))
01104   {
01105     return  HAL_ERROR;
01106   }
01107
01108   /* Process Locked */
01109   __HAL_LOCK(hi2s);
01110
01111   if (hi2s->State != HAL_I2S_STATE_READY)
01112   {
01113     __HAL_UNLOCK(hi2s);
01114     return HAL_BUSY;
01115   }
01116
01117   /* Set state and reset error code */
01118   hi2s->State = HAL_I2S_STATE_BUSY_TX;
01119   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01120   hi2s->pTxBuffPtr = pData;
01121
01122   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01123
01124   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01125   {
01126     hi2s->TxXferSize = (Size << 1U);
01127     hi2s->TxXferCount = (Size << 1U);
01128   }
01129   else
01130   {
01131     hi2s->TxXferSize = Size;
01132     hi2s->TxXferCount = Size;
01133   }
01134
01135   /* Set the I2S Tx DMA Half transfer complete callback */
01136   hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
01137
01138   /* Set the I2S Tx DMA transfer complete callback */
01139   hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
01140
01141   /* Set the DMA error callback */
01142   hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
01143
01144   /* Enable the Tx DMA Stream/Channel */
01145   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
01146                                  (uint32_t)hi2s->pTxBuffPtr,
01147                                  (uint32_t)&hi2s->Instance->DR,
01148                                  hi2s->TxXferSize))
01149   {
01150     /* Update SPI error code */
01151     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01152     hi2s->State = HAL_I2S_STATE_READY;
01153
01154     __HAL_UNLOCK(hi2s);
01155     return HAL_ERROR;
01156   }
01157
01158   /* Check if the I2S is already enabled */
01159   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01160   {
01161     /* Enable I2S peripheral */
01162     __HAL_I2S_ENABLE(hi2s);
01163   }
01164
01165   /* Check if the I2S Tx request is already enabled */
01166   if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
01167   {
01168     /* Enable Tx DMA Request */
01169     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01170   }
01171
01172   __HAL_UNLOCK(hi2s);
01173   return HAL_OK;
01174 }
01175
01176 /**
01177   * @brief  Receive an amount of data in non-blocking mode with DMA
01178   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01179   *         the configuration information for I2S module
01180   * @param  pData a 16-bit pointer to the Receive data buffer.
01181   * @param  Size number of data sample to be sent:
01182   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01183   *         configuration phase, the Size parameter means the number of 16-bit data length
01184   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01185   *         the Size parameter means the number of 24-bit or 32-bit data length.
01186   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01187   *         between Master and Slave(example: audio streaming).
01188   * @retval HAL status
01189   */
01190 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01191 {
01192   uint32_t tmpreg_cfgr;
01193
01194   if ((pData == NULL) || (Size == 0U))
01195   {
01196     return  HAL_ERROR;
01197   }
01198
01199   /* Process Locked */
01200   __HAL_LOCK(hi2s);
01201
01202   if (hi2s->State != HAL_I2S_STATE_READY)
01203   {
01204     __HAL_UNLOCK(hi2s);
01205     return HAL_BUSY;
01206   }
01207
01208   /* Set state and reset error code */
01209   hi2s->State = HAL_I2S_STATE_BUSY_RX;
01210   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01211   hi2s->pRxBuffPtr = pData;
01212
01213   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01214
01215   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01216   {
01217     hi2s->RxXferSize = (Size << 1U);
01218     hi2s->RxXferCount = (Size << 1U);
01219   }
01220   else
01221   {
01222     hi2s->RxXferSize = Size;
01223     hi2s->RxXferCount = Size;
01224   }
01225
01226   /* Set the I2S Rx DMA Half transfer complete callback */
01227   hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
01228
01229   /* Set the I2S Rx DMA transfer complete callback */
01230   hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
01231
01232   /* Set the DMA error callback */
01233   hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
01234
01235   /* Check if Master Receiver mode is selected */
01236   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
01237   {
01238     /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
01239     access to the SPI_SR register. */
01240     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01241   }
01242
01243   /* Enable the Rx DMA Stream/Channel */
01244   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
01245                                  hi2s->RxXferSize))
01246   {
01247     /* Update SPI error code */
01248     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01249     hi2s->State = HAL_I2S_STATE_READY;
01250
01251     __HAL_UNLOCK(hi2s);
01252     return HAL_ERROR;
01253   }
01254
01255   /* Check if the I2S is already enabled */
01256   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01257   {
01258     /* Enable I2S peripheral */
01259     __HAL_I2S_ENABLE(hi2s);
01260   }
01261
01262   /* Check if the I2S Rx request is already enabled */
01263   if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
01264   {
01265     /* Enable Rx DMA Request */
01266     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01267   }
01268
01269   __HAL_UNLOCK(hi2s);
01270   return HAL_OK;
01271 }
01272
01273 /**
01274   * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
01275   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01276   *         the configuration information for I2S module
01277   * @retval HAL status
01278   */
01279 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
01280 {
01281   /* Process Locked */
01282   __HAL_LOCK(hi2s);
01283
01284   if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
01285   {
01286     /* Disable the I2S DMA Tx request */
01287     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01288   }
01289   else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
01290   {
01291     /* Disable the I2S DMA Rx request */
01292     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01293   }
01294   else
01295   {
01296     /* nothing to do */
01297   }
01298
01299   /* Process Unlocked */
01300   __HAL_UNLOCK(hi2s);
01301
01302   return HAL_OK;
01303 }
01304
01305 /**
01306   * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
01307   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01308   *         the configuration information for I2S module
01309   * @retval HAL status
01310   */
01311 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
01312 {
01313   /* Process Locked */
01314   __HAL_LOCK(hi2s);
01315
01316   if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
01317   {
01318     /* Enable the I2S DMA Tx request */
01319     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01320   }
01321   else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
01322   {
01323     /* Enable the I2S DMA Rx request */
01324     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01325   }
01326   else
01327   {
01328     /* nothing to do */
01329   }
01330
01331   /* If the I2S peripheral is still not enabled, enable it */
01332   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01333   {
01334     /* Enable I2S peripheral */
01335     __HAL_I2S_ENABLE(hi2s);
01336   }
01337
01338   /* Process Unlocked */
01339   __HAL_UNLOCK(hi2s);
01340
01341   return HAL_OK;
01342 }
01343
01344 /**
01345   * @brief  Stops the audio DMA Stream/Channel playing from the Media.
01346   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01347   *         the configuration information for I2S module
01348   * @retval HAL status
01349   */
01350 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01351 {
01352   HAL_StatusTypeDef errorcode = HAL_OK;
01353   /* The Lock is not implemented on this API to allow the user application
01354      to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01355      when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
01356      and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01357      */
01358
01359   if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
01360   {
01361     /* Abort the I2S DMA tx Stream/Channel */
01362     if (hi2s->hdmatx != NULL)
01363     {
01364       /* Disable the I2S DMA tx Stream/Channel */
01365       if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
01366       {
01367         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01368         errorcode = HAL_ERROR;
01369       }
01370     }
01371
01372     /* Wait until TXE flag is set */
01373     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
01374     {
01375       /* Set the error code */
01376       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
01377       hi2s->State = HAL_I2S_STATE_READY;
01378       errorcode   = HAL_ERROR;
01379     }
01380
01381     /* Wait until BSY flag is Reset */
01382     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
01383     {
01384       /* Set the error code */
01385       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
01386       hi2s->State = HAL_I2S_STATE_READY;
01387       errorcode   = HAL_ERROR;
01388     }
01389
01390     /* Disable I2S peripheral */
01391     __HAL_I2S_DISABLE(hi2s);
01392
01393     /* Clear UDR flag */
01394     __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01395
01396     /* Disable the I2S Tx DMA requests */
01397     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01398
01399   }
01400
01401   else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
01402   {
01403     /* Abort the I2S DMA rx Stream/Channel */
01404     if (hi2s->hdmarx != NULL)
01405     {
01406       /* Disable the I2S DMA rx Stream/Channel */
01407       if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
01408       {
01409         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01410         errorcode = HAL_ERROR;
01411       }
01412     }
01413
01414     /* Disable I2S peripheral */
01415     __HAL_I2S_DISABLE(hi2s);
01416
01417     /* Clear OVR flag */
01418     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01419
01420     /* Disable the I2S Rx DMA request */
01421     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01422
01423     if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
01424     {
01425       /* Set the error code */
01426       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
01427
01428       /* Set the I2S State ready */
01429       hi2s->State = HAL_I2S_STATE_READY;
01430       errorcode = HAL_ERROR;
01431     }
01432     else
01433     {
01434       /* Read DR to Flush RX Data */
01435       READ_REG((hi2s->Instance)->DR);
01436     }
01437   }
01438
01439   hi2s->State = HAL_I2S_STATE_READY;
01440
01441   return errorcode;
01442 }
01443
01444 /**
01445   * @brief  This function handles I2S interrupt request.
01446   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01447   *         the configuration information for I2S module
01448   * @retval None
01449   */
01450 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01451 {
01452   uint32_t itsource = hi2s->Instance->CR2;
01453   uint32_t itflag   = hi2s->Instance->SR;
01454
01455   /* I2S in mode Receiver ------------------------------------------------*/
01456   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
01457       (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
01458   {
01459     I2S_Receive_IT(hi2s);
01460     return;
01461   }
01462
01463   /* I2S in mode Tramitter -----------------------------------------------*/
01464   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
01465   {
01466     I2S_Transmit_IT(hi2s);
01467     return;
01468   }
01469
01470   /* I2S interrupt error -------------------------------------------------*/
01471   if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
01472   {
01473     /* I2S Overrun error interrupt occurred ---------------------------------*/
01474     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
01475     {
01476       /* Disable RXNE and ERR interrupt */
01477       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01478
01479       /* Set the error code and execute error callback*/
01480       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
01481     }
01482
01483     /* I2S Underrun error interrupt occurred --------------------------------*/
01484     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
01485     {
01486       /* Disable TXE and ERR interrupt */
01487       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01488
01489       /* Set the error code and execute error callback*/
01490       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
01491     }
01492
01493     /* Set the I2S State ready */
01494     hi2s->State = HAL_I2S_STATE_READY;
01495
01496     /* Call user error callback */
01497 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01498     hi2s->ErrorCallback(hi2s);
01499 #else
01500     HAL_I2S_ErrorCallback(hi2s);
01501 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01502   }
01503 }
01504
01505 /**
01506   * @brief  Tx Transfer Half completed callbacks
01507   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01508   *         the configuration information for I2S module
01509   * @retval None
01510   */
01511 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01512 {
01513   /* Prevent unused argument(s) compilation warning */
01514   UNUSED(hi2s);
01515
01516   /* NOTE : This function Should not be modified, when the callback is needed,
01517             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01518    */
01519 }
01520
01521 /**
01522   * @brief  Tx Transfer completed callbacks
01523   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01524   *         the configuration information for I2S module
01525   * @retval None
01526   */
01527 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01528 {
01529   /* Prevent unused argument(s) compilation warning */
01530   UNUSED(hi2s);
01531
01532   /* NOTE : This function Should not be modified, when the callback is needed,
01533             the HAL_I2S_TxCpltCallback could be implemented in the user file
01534    */
01535 }
01536
01537 /**
01538   * @brief  Rx Transfer half completed callbacks
01539   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01540   *         the configuration information for I2S module
01541   * @retval None
01542   */
01543 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01544 {
01545   /* Prevent unused argument(s) compilation warning */
01546   UNUSED(hi2s);
01547
01548   /* NOTE : This function Should not be modified, when the callback is needed,
01549             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
01550    */
01551 }
01552
01553 /**
01554   * @brief  Rx Transfer completed callbacks
01555   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01556   *         the configuration information for I2S module
01557   * @retval None
01558   */
01559 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01560 {
01561   /* Prevent unused argument(s) compilation warning */
01562   UNUSED(hi2s);
01563
01564   /* NOTE : This function Should not be modified, when the callback is needed,
01565             the HAL_I2S_RxCpltCallback could be implemented in the user file
01566    */
01567 }
01568
01569 /**
01570   * @brief  I2S error callbacks
01571   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01572   *         the configuration information for I2S module
01573   * @retval None
01574   */
01575 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01576 {
01577   /* Prevent unused argument(s) compilation warning */
01578   UNUSED(hi2s);
01579
01580   /* NOTE : This function Should not be modified, when the callback is needed,
01581             the HAL_I2S_ErrorCallback could be implemented in the user file
01582    */
01583 }
01584
01585 /**
01586   * @}
01587   */
01588
01589 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01590   *  @brief   Peripheral State functions
01591   *
01592 @verbatim
01593  ===============================================================================
01594                       ##### Peripheral State and Errors functions #####
01595  ===============================================================================
01596     [..]
01597     This subsection permits to get in run-time the status of the peripheral
01598     and the data flow.
01599
01600 @endverbatim
01601   * @{
01602   */
01603
01604 /**
01605   * @brief  Return the I2S state
01606   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01607   *         the configuration information for I2S module
01608   * @retval HAL state
01609   */
01610 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01611 {
01612   return hi2s->State;
01613 }
01614
01615 /**
01616   * @brief  Return the I2S error code
01617   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01618   *         the configuration information for I2S module
01619   * @retval I2S Error Code
01620   */
01621 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01622 {
01623   return hi2s->ErrorCode;
01624 }
01625 /**
01626   * @}
01627   */
01628
01629 /**
01630   * @}
01631   */
01632
01633 /** @addtogroup I2S_Private_Functions I2S Private Functions
01634   * @{
01635   */
01636 /**
01637   * @brief  DMA I2S transmit process complete callback
01638   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01639   *                the configuration information for the specified DMA module.
01640   * @retval None
01641   */
01642 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01643 {
01644   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01645
01646   /* if DMA is configured in DMA_NORMAL Mode */
01647   if (hdma->Init.Mode == DMA_NORMAL)
01648   {
01649     /* Disable Tx DMA Request */
01650     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01651
01652     hi2s->TxXferCount = 0U;
01653     hi2s->State = HAL_I2S_STATE_READY;
01654   }
01655   /* Call user Tx complete callback */
01656 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01657   hi2s->TxCpltCallback(hi2s);
01658 #else
01659   HAL_I2S_TxCpltCallback(hi2s);
01660 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01661 }
01662
01663 /**
01664   * @brief  DMA I2S transmit process half complete callback
01665   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01666   *                the configuration information for the specified DMA module.
01667   * @retval None
01668   */
01669 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01670 {
01671   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01672
01673   /* Call user Tx half complete callback */
01674 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01675   hi2s->TxHalfCpltCallback(hi2s);
01676 #else
01677   HAL_I2S_TxHalfCpltCallback(hi2s);
01678 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01679 }
01680
01681 /**
01682   * @brief  DMA I2S receive process complete callback
01683   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01684   *                the configuration information for the specified DMA module.
01685   * @retval None
01686   */
01687 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01688 {
01689   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01690
01691   /* if DMA is configured in DMA_NORMAL Mode */
01692   if (hdma->Init.Mode == DMA_NORMAL)
01693   {
01694     /* Disable Rx DMA Request */
01695     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01696     hi2s->RxXferCount = 0U;
01697     hi2s->State = HAL_I2S_STATE_READY;
01698   }
01699   /* Call user Rx complete callback */
01700 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01701   hi2s->RxCpltCallback(hi2s);
01702 #else
01703   HAL_I2S_RxCpltCallback(hi2s);
01704 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01705 }
01706
01707 /**
01708   * @brief  DMA I2S receive process half complete callback
01709   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01710   *                the configuration information for the specified DMA module.
01711   * @retval None
01712   */
01713 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01714 {
01715   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01716
01717   /* Call user Rx half complete callback */
01718 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01719   hi2s->RxHalfCpltCallback(hi2s);
01720 #else
01721   HAL_I2S_RxHalfCpltCallback(hi2s);
01722 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01723 }
01724
01725 /**
01726   * @brief  DMA I2S communication error callback
01727   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01728   *                the configuration information for the specified DMA module.
01729   * @retval None
01730   */
01731 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01732 {
01733   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01734
01735   /* Disable Rx and Tx DMA Request */
01736   CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01737   hi2s->TxXferCount = 0U;
01738   hi2s->RxXferCount = 0U;
01739
01740   hi2s->State = HAL_I2S_STATE_READY;
01741
01742   /* Set the error code and execute error callback*/
01743   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01744   /* Call user error callback */
01745 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01746   hi2s->ErrorCallback(hi2s);
01747 #else
01748   HAL_I2S_ErrorCallback(hi2s);
01749 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01750 }
01751
01752 /**
01753   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
01754   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01755   *         the configuration information for I2S module
01756   * @retval None
01757   */
01758 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01759 {
01760   /* Transmit data */
01761   hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
01762   hi2s->pTxBuffPtr++;
01763   hi2s->TxXferCount--;
01764
01765   if (hi2s->TxXferCount == 0U)
01766   {
01767     /* Disable TXE and ERR interrupt */
01768     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01769
01770     hi2s->State = HAL_I2S_STATE_READY;
01771     /* Call user Tx complete callback */
01772 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01773     hi2s->TxCpltCallback(hi2s);
01774 #else
01775     HAL_I2S_TxCpltCallback(hi2s);
01776 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01777   }
01778 }
01779
01780 /**
01781   * @brief  Receive an amount of data in non-blocking mode with Interrupt
01782   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01783   *         the configuration information for I2S module
01784   * @retval None
01785   */
01786 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01787 {
01788   /* Receive data */
01789   (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
01790   hi2s->pRxBuffPtr++;
01791   hi2s->RxXferCount--;
01792
01793   if (hi2s->RxXferCount == 0U)
01794   {
01795     /* Disable RXNE and ERR interrupt */
01796     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01797
01798     hi2s->State = HAL_I2S_STATE_READY;
01799     /* Call user Rx complete callback */
01800 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01801     hi2s->RxCpltCallback(hi2s);
01802 #else
01803     HAL_I2S_RxCpltCallback(hi2s);
01804 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01805   }
01806 }
01807
01808 /**
01809   * @brief  This function handles I2S Communication Timeout.
01810   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01811   *         the configuration information for I2S module
01812   * @param  Flag Flag checked
01813   * @param  State Value of the flag expected
01814   * @param  Timeout Duration of the timeout
01815   * @retval HAL status
01816   */
01817 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
01818                                                        uint32_t Timeout)
01819 {
01820   uint32_t tickstart;
01821
01822   /* Get tick */
01823   tickstart = HAL_GetTick();
01824
01825   /* Wait until flag is set to status*/
01826   while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01827   {
01828     if (Timeout != HAL_MAX_DELAY)
01829     {
01830       if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
01831       {
01832         /* Set the I2S State ready */
01833         hi2s->State = HAL_I2S_STATE_READY;
01834
01835         /* Process Unlocked */
01836         __HAL_UNLOCK(hi2s);
01837
01838         return HAL_TIMEOUT;
01839       }
01840     }
01841   }
01842   return HAL_OK;
01843 }
01844
01845 /**
01846   * @}
01847   */
01848
01849 /**
01850   * @}
01851   */
01852
01853 /**
01854   * @}
01855   */
01856 #endif /* SPI_I2S_SUPPORT */
01857
01858 #endif /* HAL_I2S_MODULE_ENABLED */
01859
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_i2s.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_i2s.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_I2S_H
00021 #define STM32G4xx_HAL_I2S_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined(SPI_I2S_SUPPORT)
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2S
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup I2S_Exported_Types I2S Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief I2S Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Mode;                /*!< Specifies the I2S operating mode.
00050                                      This parameter can be a value of @ref I2S_Mode */
00051
00052   uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
00053                                      This parameter can be a value of @ref I2S_Standard */
00054
00055   uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
00056                                      This parameter can be a value of @ref I2S_Data_Format */
00057
00058   uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
00059                                      This parameter can be a value of @ref I2S_MCLK_Output */
00060
00061   uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
00062                                      This parameter can be a value of @ref I2S_Audio_Frequency */
00063
00064   uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
00065                                      This parameter can be a value of @ref I2S_Clock_Polarity */
00066 } I2S_InitTypeDef;
00067
00068 /**
00069   * @brief  HAL State structures definition
00070   */
00071 typedef enum
00072 {
00073   HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
00074   HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
00075   HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
00076   HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
00077   HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
00078   HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
00079   HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
00080 } HAL_I2S_StateTypeDef;
00081
00082 /**
00083   * @brief I2S handle Structure definition
00084   */
00085 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
00086 typedef struct __I2S_HandleTypeDef
00087 #else
00088 typedef struct
00089 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00090 {
00091   SPI_TypeDef                *Instance;    /*!< I2S registers base address */
00092
00093   I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
00094
00095   uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
00096
00097   __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
00098
00099   __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
00100
00101   uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
00102
00103   __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
00104
00105   __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
00106                                               (This field is initialized at the
00107                                                same value as transfer size at the
00108                                                beginning of the transfer and
00109                                                decremented when a sample is received
00110                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00111   DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
00112
00113   DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
00114
00115   __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
00116
00117   __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
00118
00119   __IO uint32_t              ErrorCode;    /*!< I2S Error code
00120                                                 This parameter can be a value of @ref I2S_Error */
00121
00122 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00123   void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
00124   void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
00125   void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
00126   void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
00127   void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
00128   void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
00129   void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
00130
00131 #endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
00132 } I2S_HandleTypeDef;
00133
00134 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00135 /**
00136   * @brief  HAL I2S Callback ID enumeration definition
00137   */
00138 typedef enum
00139 {
00140   HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
00141   HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
00142   HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
00143   HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
00144   HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
00145   HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
00146   HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
00147
00148 } HAL_I2S_CallbackIDTypeDef;
00149
00150 /**
00151   * @brief  HAL I2S Callback pointer definition
00152   */
00153 typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
00154
00155 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00162   * @{
00163   */
00164 /** @defgroup I2S_Error I2S Error
00165   * @{
00166   */
00167 #define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
00168 #define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
00169 #define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
00170 #define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
00171 #define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
00172 #define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
00173 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00174 #define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
00175 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00176 #define HAL_I2S_ERROR_BUSY_LINE_RX       (0x00000040U)  /*!< Busy Rx Line error          */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup I2S_Mode I2S Mode
00182   * @{
00183   */
00184 #define I2S_MODE_SLAVE_TX                (0x00000000U)
00185 #define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
00186 #define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
00187 #define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup I2S_Standard I2S Standard
00193   * @{
00194   */
00195 #define I2S_STANDARD_PHILIPS             (0x00000000U)
00196 #define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
00197 #define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
00198 #define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
00199 #define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup I2S_Data_Format I2S Data Format
00205   * @{
00206   */
00207 #define I2S_DATAFORMAT_16B               (0x00000000U)
00208 #define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
00209 #define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
00210 #define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup I2S_MCLK_Output I2S MCLK Output
00216   * @{
00217   */
00218 #define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
00219 #define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00225   * @{
00226   */
00227 #define I2S_AUDIOFREQ_192K               (192000U)
00228 #define I2S_AUDIOFREQ_96K                (96000U)
00229 #define I2S_AUDIOFREQ_48K                (48000U)
00230 #define I2S_AUDIOFREQ_44K                (44100U)
00231 #define I2S_AUDIOFREQ_32K                (32000U)
00232 #define I2S_AUDIOFREQ_22K                (22050U)
00233 #define I2S_AUDIOFREQ_16K                (16000U)
00234 #define I2S_AUDIOFREQ_11K                (11025U)
00235 #define I2S_AUDIOFREQ_8K                 (8000U)
00236 #define I2S_AUDIOFREQ_DEFAULT            (2U)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
00242   * @{
00243   */
00244 #define I2S_CPOL_LOW                     (0x00000000U)
00245 #define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00251   * @{
00252   */
00253 #define I2S_IT_TXE                       SPI_CR2_TXEIE
00254 #define I2S_IT_RXNE                      SPI_CR2_RXNEIE
00255 #define I2S_IT_ERR                       SPI_CR2_ERRIE
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00261   * @{
00262   */
00263 #define I2S_FLAG_TXE                     SPI_SR_TXE
00264 #define I2S_FLAG_RXNE                    SPI_SR_RXNE
00265
00266 #define I2S_FLAG_UDR                     SPI_SR_UDR
00267 #define I2S_FLAG_OVR                     SPI_SR_OVR
00268 #define I2S_FLAG_FRE                     SPI_SR_FRE
00269
00270 #define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
00271 #define I2S_FLAG_BSY                     SPI_SR_BSY
00272
00273 #define I2S_FLAG_MASK                   (SPI_SR_RXNE\
00274                                          | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
00275 /**
00276   * @}
00277   */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported macros -----------------------------------------------------------*/
00284 /** @defgroup I2S_Exported_macros I2S Exported Macros
00285   * @{
00286   */
00287
00288 /** @brief  Reset I2S handle state
00289   * @param  __HANDLE__ specifies the I2S Handle.
00290   * @retval None
00291   */
00292 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00293 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00294                                                                     (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
00295                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00296                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00297                                                                   } while(0)
00298 #else
00299 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00300 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00301
00302 /** @brief  Enable the specified SPI peripheral (in I2S mode).
00303   * @param  __HANDLE__ specifies the I2S Handle.
00304   * @retval None
00305   */
00306 #define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00307
00308 /** @brief  Disable the specified SPI peripheral (in I2S mode).
00309   * @param  __HANDLE__ specifies the I2S Handle.
00310   * @retval None
00311   */
00312 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00313
00314 /** @brief  Enable the specified I2S interrupts.
00315   * @param  __HANDLE__ specifies the I2S Handle.
00316   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00317   *         This parameter can be one of the following values:
00318   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00319   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00320   *            @arg I2S_IT_ERR: Error interrupt enable
00321   * @retval None
00322   */
00323 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00324
00325 /** @brief  Disable the specified I2S interrupts.
00326   * @param  __HANDLE__ specifies the I2S Handle.
00327   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00328   *         This parameter can be one of the following values:
00329   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00330   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00331   *            @arg I2S_IT_ERR: Error interrupt enable
00332   * @retval None
00333   */
00334 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00335
00336 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00337   * @param  __HANDLE__ specifies the I2S Handle.
00338   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00339   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00340   *          This parameter can be one of the following values:
00341   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00342   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00343   *            @arg I2S_IT_ERR: Error interrupt enable
00344   * @retval The new state of __IT__ (TRUE or FALSE).
00345   */
00346 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
00347                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00348
00349 /** @brief  Checks whether the specified I2S flag is set or not.
00350   * @param  __HANDLE__ specifies the I2S Handle.
00351   * @param  __FLAG__ specifies the flag to check.
00352   *         This parameter can be one of the following values:
00353   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00354   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00355   *            @arg I2S_FLAG_UDR: Underrun flag
00356   *            @arg I2S_FLAG_OVR: Overrun flag
00357   *            @arg I2S_FLAG_FRE: Frame error flag
00358   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00359   *            @arg I2S_FLAG_BSY: Busy flag
00360   * @retval The new state of __FLAG__ (TRUE or FALSE).
00361   */
00362 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00363
00364 /** @brief Clears the I2S OVR pending flag.
00365   * @param  __HANDLE__ specifies the I2S Handle.
00366   * @retval None
00367   */
00368 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
00369                                                 __IO uint32_t tmpreg_ovr = 0x00U; \
00370                                                 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
00371                                                 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
00372                                                 UNUSED(tmpreg_ovr); \
00373                                               }while(0U)
00374 /** @brief Clears the I2S UDR pending flag.
00375   * @param  __HANDLE__ specifies the I2S Handle.
00376   * @retval None
00377   */
00378 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
00379                                                 __IO uint32_t tmpreg_udr = 0x00U;\
00380                                                 tmpreg_udr = ((__HANDLE__)->Instance->SR);\
00381                                                 UNUSED(tmpreg_udr); \
00382                                               }while(0U)
00383 /** @brief Flush the I2S DR Register.
00384   * @param  __HANDLE__ specifies the I2S Handle.
00385   * @retval None
00386   */
00387 #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__)  do{\
00388                                                 __IO uint32_t tmpreg_dr = 0x00U;\
00389                                                 tmpreg_dr = ((__HANDLE__)->Instance->DR);\
00390                                                 UNUSED(tmpreg_dr); \
00391                                               }while(0U)
00392 /**
00393   * @}
00394   */
00395
00396 /* Exported functions --------------------------------------------------------*/
00397 /** @addtogroup I2S_Exported_Functions
00398   * @{
00399   */
00400
00401 /** @addtogroup I2S_Exported_Functions_Group1
00402   * @{
00403   */
00404 /* Initialization/de-initialization functions  ********************************/
00405 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00406 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
00407 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00408 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00409
00410 /* Callbacks Register/UnRegister functions  ***********************************/
00411 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00412 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
00413                                            pI2S_CallbackTypeDef pCallback);
00414 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
00415 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup I2S_Exported_Functions_Group2
00421   * @{
00422   */
00423 /* I/O operation functions  ***************************************************/
00424 /* Blocking mode: Polling */
00425 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00426 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00427
00428 /* Non-Blocking mode: Interrupt */
00429 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00430 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00431 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00432
00433 /* Non-Blocking mode: DMA */
00434 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00435 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00436
00437 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00438 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00439 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00440
00441 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00442 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00443 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00444 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00445 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00446 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00447 /**
00448   * @}
00449   */
00450
00451 /** @addtogroup I2S_Exported_Functions_Group3
00452   * @{
00453   */
00454 /* Peripheral Control and State functions  ************************************/
00455 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00456 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Private types -------------------------------------------------------------*/
00466 /* Private variables ---------------------------------------------------------*/
00467 /* Private constants ---------------------------------------------------------*/
00468 /* Private macros ------------------------------------------------------------*/
00469 /** @defgroup I2S_Private_Macros I2S Private Macros
00470   * @{
00471   */
00472
00473 /** @brief  Check whether the specified SPI flag is set or not.
00474   * @param  __SR__  copy of I2S SR register.
00475   * @param  __FLAG__ specifies the flag to check.
00476   *         This parameter can be one of the following values:
00477   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00478   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00479   *            @arg I2S_FLAG_UDR: Underrun error flag
00480   *            @arg I2S_FLAG_OVR: Overrun flag
00481   *            @arg I2S_FLAG_CHSIDE: Channel side flag
00482   *            @arg I2S_FLAG_BSY: Busy flag
00483   * @retval SET or RESET.
00484   */
00485 #define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
00486                                                     & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
00487
00488 /** @brief  Check whether the specified SPI Interrupt is set or not.
00489   * @param  __CR2__  copy of I2S CR2 register.
00490   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00491   *         This parameter can be one of the following values:
00492   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00493   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00494   *            @arg I2S_IT_ERR: Error interrupt enable
00495   * @retval SET or RESET.
00496   */
00497 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
00498                                                             & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00499
00500 /** @brief  Checks if I2S Mode parameter is in allowed range.
00501   * @param  __MODE__ specifies the I2S Mode.
00502   *         This parameter can be a value of @ref I2S_Mode
00503   * @retval None
00504   */
00505 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
00506                                ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
00507                                ((__MODE__) == I2S_MODE_MASTER_TX) || \
00508                                ((__MODE__) == I2S_MODE_MASTER_RX))
00509
00510 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
00511                                        ((__STANDARD__) == I2S_STANDARD_MSB)       || \
00512                                        ((__STANDARD__) == I2S_STANDARD_LSB)       || \
00513                                        ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
00514                                        ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
00515
00516 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
00517                                         ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
00518                                         ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
00519                                         ((__FORMAT__) == I2S_DATAFORMAT_32B))
00520
00521 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
00522                                         ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
00523
00524 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
00525                                       ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
00526                                      ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
00527
00528 /** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
00529   * @param  __CPOL__ specifies the I2S serial clock steady state.
00530   *         This parameter can be a value of @ref I2S_Clock_Polarity
00531   * @retval None
00532   */
00533 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
00534                                ((__CPOL__) == I2S_CPOL_HIGH))
00535
00536 /**
00537   * @}
00538   */
00539
00540 /**
00541   * @}
00542   */
00543
00544 /**
00545   * @}
00546   */
00547 #endif /* SPI_I2S_SUPPORT */
00548
00549 #ifdef __cplusplus
00550 }
00551 #endif
00552
00553 #endif /* STM32G4xx_HAL_I2S_H */
00554
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_irda.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @brief   IRDA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00008   *          (IRDA)
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *           + Peripheral Control functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                         ##### How to use this driver #####
00028   ==============================================================================
00029   [..]
00030     The IRDA HAL driver can be used as follows:
00031
00032     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00033     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00034         in setting the associated USART or UART in IRDA mode:
00035         (++) Enable the USARTx/UARTx interface clock.
00036         (++) USARTx/UARTx pins configuration:
00037             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00038             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00039         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00040              and HAL_IRDA_Receive_IT() APIs):
00041             (+++) Configure the USARTx/UARTx interrupt priority.
00042             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00043             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00044                   RXNE interrupt and Error Interrupts) will be managed using the macros
00045                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00046
00047         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00048              and HAL_IRDA_Receive_DMA() APIs):
00049             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00050             (+++) Enable the DMAx interface clock.
00051             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00052             (+++) Configure the DMA Tx/Rx channel.
00053             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00054             (+++) Configure the priority and enable the NVIC for the transfer
00055                   complete interrupt on the DMA Tx/Rx channel.
00056
00057     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00058         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00059
00060     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00061         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00062              by calling the customized HAL_IRDA_MspInit() API.
00063
00064          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00065              RXNE interrupt and Error Interrupts) will be managed using the macros
00066              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00067
00068     (#) Three operation modes are available within this driver :
00069
00070      *** Polling mode IO operation ***
00071      =================================
00072      [..]
00073        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00074        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00075
00076      *** Interrupt mode IO operation ***
00077      ===================================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00080        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00083        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00087
00088      *** DMA mode IO operation ***
00089      ==============================
00090      [..]
00091        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00092        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00093             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00094        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00095             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00096        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00097        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00098             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00099        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00100             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00101        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00102             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00103
00104      *** IRDA HAL driver macros list ***
00105      ====================================
00106      [..]
00107        Below the list of most used macros in IRDA HAL driver.
00108
00109        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00110        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00111        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00112        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00113        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00114        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00115        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00116
00117      [..]
00118        (@) You can refer to the IRDA HAL driver header file for more useful macros
00119
00120     ##### Callback registration #####
00121     ==================================
00122
00123     [..]
00124     The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
00125     allows the user to configure dynamically the driver callbacks.
00126
00127     [..]
00128     Use Function HAL_IRDA_RegisterCallback() to register a user callback.
00129     Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
00130     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00131     (+) TxCpltCallback            : Tx Complete Callback.
00132     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00133     (+) RxCpltCallback            : Rx Complete Callback.
00134     (+) ErrorCallback             : Error Callback.
00135     (+) AbortCpltCallback         : Abort Complete Callback.
00136     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00137     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00138     (+) MspInitCallback           : IRDA MspInit.
00139     (+) MspDeInitCallback         : IRDA MspDeInit.
00140     This function takes as parameters the HAL peripheral handle, the Callback ID
00141     and a pointer to the user callback function.
00142
00143     [..]
00144     Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
00145     weak function.
00146     HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00147     and the Callback ID.
00148     This function allows to reset following callbacks:
00149     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00150     (+) TxCpltCallback            : Tx Complete Callback.
00151     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00152     (+) RxCpltCallback            : Rx Complete Callback.
00153     (+) ErrorCallback             : Error Callback.
00154     (+) AbortCpltCallback         : Abort Complete Callback.
00155     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00156     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00157     (+) MspInitCallback           : IRDA MspInit.
00158     (+) MspDeInitCallback         : IRDA MspDeInit.
00159
00160     [..]
00161     By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
00162     all callbacks are set to the corresponding weak functions:
00163     examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
00164     Exception done for MspInit and MspDeInit functions that are respectively
00165     reset to the legacy weak functions in the HAL_IRDA_Init()
00166     and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
00167     If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
00168     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00169
00170     [..]
00171     Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
00172     Exception done MspInit/MspDeInit that can be registered/unregistered
00173     in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
00174     MspInit/DeInit callbacks can be used during the Init/DeInit.
00175     In that case first register the MspInit/MspDeInit user callbacks
00176     using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
00177     or HAL_IRDA_Init() function.
00178
00179     [..]
00180     When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
00181     not defined, the callback registration feature is not available
00182     and weak callbacks are used.
00183
00184   @endverbatim
00185   ******************************************************************************
00186   */
00187
00188 /* Includes ------------------------------------------------------------------*/
00189 #include "stm32g4xx_hal.h"
00190
00191 /** @addtogroup STM32G4xx_HAL_Driver
00192   * @{
00193   */
00194
00195 /** @defgroup IRDA IRDA
00196   * @brief HAL IRDA module driver
00197   * @{
00198   */
00199
00200 #ifdef HAL_IRDA_MODULE_ENABLED
00201
00202 /* Private typedef -----------------------------------------------------------*/
00203 /* Private define ------------------------------------------------------------*/
00204 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00205   * @{
00206   */
00207 #define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00208
00209 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00210                                      | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00211
00212 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00213
00214 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00215 /**
00216   * @}
00217   */
00218
00219 /* Private macros ------------------------------------------------------------*/
00220 /** @defgroup IRDA_Private_Macros IRDA Private Macros
00221   * @{
00222   */
00223 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
00224   * @param  __PCLK__ IRDA clock source.
00225   * @param  __BAUD__ Baud rate set by the user.
00226   * @param  __PRESCALER__ IRDA clock prescaler value.
00227   * @retval Division result
00228   */
00229 #define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
00230                                                                   + ((__BAUD__)/2U)) / (__BAUD__))
00231 /**
00232   * @}
00233   */
00234
00235 /* Private variables ---------------------------------------------------------*/
00236 /* Private function prototypes -----------------------------------------------*/
00237 /** @addtogroup IRDA_Private_Functions
00238   * @{
00239   */
00240 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00241 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
00242 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00243 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00244 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00245 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
00246                                                      uint32_t Tickstart, uint32_t Timeout);
00247 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00248 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00249 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00250 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00251 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00252 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00253 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00254 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00255 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00256 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00257 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00258 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00259 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00260 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00261 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported functions --------------------------------------------------------*/
00267
00268 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00269   * @{
00270   */
00271
00272 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00273   *  @brief    Initialization and Configuration functions
00274   *
00275 @verbatim
00276   ==============================================================================
00277               ##### Initialization and Configuration functions #####
00278   ==============================================================================
00279   [..]
00280   This subsection provides a set of functions allowing to initialize the USARTx
00281   in asynchronous IRDA mode.
00282   (+) For the asynchronous mode only these parameters can be configured:
00283       (++) Baud Rate
00284       (++) Word Length
00285       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00286            in the data register is transmitted but is changed by the parity bit.
00287       (++) Power mode
00288       (++) Prescaler setting
00289       (++) Receiver/transmitter modes
00290
00291   [..]
00292   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00293   (details for the procedures are available in reference manual).
00294
00295 @endverbatim
00296
00297   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00298   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00299   following table.
00300
00301     Table 1. IRDA frame format.
00302     +-----------------------------------------------------------------------+
00303     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00304     |---------|---------|-----------|---------------------------------------|
00305     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00306     |---------|---------|-----------|---------------------------------------|
00307     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00308     |---------|---------|-----------|---------------------------------------|
00309     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00310     |---------|---------|-----------|---------------------------------------|
00311     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00312     |---------|---------|-----------|---------------------------------------|
00313     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00314     |---------|---------|-----------|---------------------------------------|
00315     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00316     +-----------------------------------------------------------------------+
00317
00318   * @{
00319   */
00320
00321 /**
00322   * @brief Initialize the IRDA mode according to the specified
00323   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00324   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00325   *               the configuration information for the specified IRDA module.
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00329 {
00330   /* Check the IRDA handle allocation */
00331   if (hirda == NULL)
00332   {
00333     return HAL_ERROR;
00334   }
00335
00336   /* Check the USART/UART associated to the IRDA handle */
00337   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00338
00339   if (hirda->gState == HAL_IRDA_STATE_RESET)
00340   {
00341     /* Allocate lock resource and initialize it */
00342     hirda->Lock = HAL_UNLOCKED;
00343
00344 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00345     IRDA_InitCallbacksToDefault(hirda);
00346
00347     if (hirda->MspInitCallback == NULL)
00348     {
00349       hirda->MspInitCallback = HAL_IRDA_MspInit;
00350     }
00351
00352     /* Init the low level hardware */
00353     hirda->MspInitCallback(hirda);
00354 #else
00355     /* Init the low level hardware : GPIO, CLOCK */
00356     HAL_IRDA_MspInit(hirda);
00357 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00358   }
00359
00360   hirda->gState = HAL_IRDA_STATE_BUSY;
00361
00362   /* Disable the Peripheral to update the configuration registers */
00363   __HAL_IRDA_DISABLE(hirda);
00364
00365   /* Set the IRDA Communication parameters */
00366   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00367   {
00368     return HAL_ERROR;
00369   }
00370
00371   /* In IRDA mode, the following bits must be kept cleared:
00372   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00373   - SCEN and HDSEL bits in the USART_CR3 register.*/
00374   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00375   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00376
00377   /* set the UART/USART in IRDA mode */
00378   hirda->Instance->CR3 |= USART_CR3_IREN;
00379
00380   /* Enable the Peripheral */
00381   __HAL_IRDA_ENABLE(hirda);
00382
00383   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00384   return (IRDA_CheckIdleState(hirda));
00385 }
00386
00387 /**
00388   * @brief DeInitialize the IRDA peripheral.
00389   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00390   *               the configuration information for the specified IRDA module.
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00394 {
00395   /* Check the IRDA handle allocation */
00396   if (hirda == NULL)
00397   {
00398     return HAL_ERROR;
00399   }
00400
00401   /* Check the USART/UART associated to the IRDA handle */
00402   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00403
00404   hirda->gState = HAL_IRDA_STATE_BUSY;
00405
00406   /* DeInit the low level hardware */
00407 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00408   if (hirda->MspDeInitCallback == NULL)
00409   {
00410     hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00411   }
00412   /* DeInit the low level hardware */
00413   hirda->MspDeInitCallback(hirda);
00414 #else
00415   HAL_IRDA_MspDeInit(hirda);
00416 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00417   /* Disable the Peripheral */
00418   __HAL_IRDA_DISABLE(hirda);
00419
00420   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00421   hirda->gState    = HAL_IRDA_STATE_RESET;
00422   hirda->RxState   = HAL_IRDA_STATE_RESET;
00423
00424   /* Process Unlock */
00425   __HAL_UNLOCK(hirda);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief Initialize the IRDA MSP.
00432   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00433   *               the configuration information for the specified IRDA module.
00434   * @retval None
00435   */
00436 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00437 {
00438   /* Prevent unused argument(s) compilation warning */
00439   UNUSED(hirda);
00440
00441   /* NOTE: This function should not be modified, when the callback is needed,
00442            the HAL_IRDA_MspInit can be implemented in the user file
00443    */
00444 }
00445
00446 /**
00447   * @brief DeInitialize the IRDA MSP.
00448   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00449   *               the configuration information for the specified IRDA module.
00450   * @retval None
00451   */
00452 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00453 {
00454   /* Prevent unused argument(s) compilation warning */
00455   UNUSED(hirda);
00456
00457   /* NOTE: This function should not be modified, when the callback is needed,
00458            the HAL_IRDA_MspDeInit can be implemented in the user file
00459    */
00460 }
00461
00462 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00463 /**
00464   * @brief  Register a User IRDA Callback
00465   *         To be used to override the weak predefined callback
00466   * @note   The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
00467   *         to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
00468   * @param  hirda irda handle
00469   * @param  CallbackID ID of the callback to be registered
00470   *         This parameter can be one of the following values:
00471   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00472   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00473   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00474   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00475   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00476   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00477   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00478   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00479   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00480   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00481   * @param  pCallback pointer to the Callback function
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00485                                             pIRDA_CallbackTypeDef pCallback)
00486 {
00487   HAL_StatusTypeDef status = HAL_OK;
00488
00489   if (pCallback == NULL)
00490   {
00491     /* Update the error code */
00492     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00493
00494     return HAL_ERROR;
00495   }
00496
00497   if (hirda->gState == HAL_IRDA_STATE_READY)
00498   {
00499     switch (CallbackID)
00500     {
00501       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00502         hirda->TxHalfCpltCallback = pCallback;
00503         break;
00504
00505       case HAL_IRDA_TX_COMPLETE_CB_ID :
00506         hirda->TxCpltCallback = pCallback;
00507         break;
00508
00509       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00510         hirda->RxHalfCpltCallback = pCallback;
00511         break;
00512
00513       case HAL_IRDA_RX_COMPLETE_CB_ID :
00514         hirda->RxCpltCallback = pCallback;
00515         break;
00516
00517       case HAL_IRDA_ERROR_CB_ID :
00518         hirda->ErrorCallback = pCallback;
00519         break;
00520
00521       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00522         hirda->AbortCpltCallback = pCallback;
00523         break;
00524
00525       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00526         hirda->AbortTransmitCpltCallback = pCallback;
00527         break;
00528
00529       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00530         hirda->AbortReceiveCpltCallback = pCallback;
00531         break;
00532
00533       case HAL_IRDA_MSPINIT_CB_ID :
00534         hirda->MspInitCallback = pCallback;
00535         break;
00536
00537       case HAL_IRDA_MSPDEINIT_CB_ID :
00538         hirda->MspDeInitCallback = pCallback;
00539         break;
00540
00541       default :
00542         /* Update the error code */
00543         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00544
00545         /* Return error status */
00546         status =  HAL_ERROR;
00547         break;
00548     }
00549   }
00550   else if (hirda->gState == HAL_IRDA_STATE_RESET)
00551   {
00552     switch (CallbackID)
00553     {
00554       case HAL_IRDA_MSPINIT_CB_ID :
00555         hirda->MspInitCallback = pCallback;
00556         break;
00557
00558       case HAL_IRDA_MSPDEINIT_CB_ID :
00559         hirda->MspDeInitCallback = pCallback;
00560         break;
00561
00562       default :
00563         /* Update the error code */
00564         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00565
00566         /* Return error status */
00567         status =  HAL_ERROR;
00568         break;
00569     }
00570   }
00571   else
00572   {
00573     /* Update the error code */
00574     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00575
00576     /* Return error status */
00577     status =  HAL_ERROR;
00578   }
00579
00580   return status;
00581 }
00582
00583 /**
00584   * @brief  Unregister an IRDA callback
00585   *         IRDA callback is redirected to the weak predefined callback
00586   * @note   The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
00587   *         to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
00588   * @param  hirda irda handle
00589   * @param  CallbackID ID of the callback to be unregistered
00590   *         This parameter can be one of the following values:
00591   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00592   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00593   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00594   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00595   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00596   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00597   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00598   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00599   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00600   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
00604 {
00605   HAL_StatusTypeDef status = HAL_OK;
00606
00607   if (HAL_IRDA_STATE_READY == hirda->gState)
00608   {
00609     switch (CallbackID)
00610     {
00611       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00612         hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
00613         break;
00614
00615       case HAL_IRDA_TX_COMPLETE_CB_ID :
00616         hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
00617         break;
00618
00619       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00620         hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
00621         break;
00622
00623       case HAL_IRDA_RX_COMPLETE_CB_ID :
00624         hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
00625         break;
00626
00627       case HAL_IRDA_ERROR_CB_ID :
00628         hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback          */
00629         break;
00630
00631       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00632         hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
00633         break;
00634
00635       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00636         hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
00637                                                                                   AbortTransmitCpltCallback          */
00638         break;
00639
00640       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00641         hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak
00642                                                                                   AbortReceiveCpltCallback           */
00643         break;
00644
00645       case HAL_IRDA_MSPINIT_CB_ID :
00646         hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback        */
00647         break;
00648
00649       case HAL_IRDA_MSPDEINIT_CB_ID :
00650         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
00651         break;
00652
00653       default :
00654         /* Update the error code */
00655         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00656
00657         /* Return error status */
00658         status =  HAL_ERROR;
00659         break;
00660     }
00661   }
00662   else if (HAL_IRDA_STATE_RESET == hirda->gState)
00663   {
00664     switch (CallbackID)
00665     {
00666       case HAL_IRDA_MSPINIT_CB_ID :
00667         hirda->MspInitCallback = HAL_IRDA_MspInit;
00668         break;
00669
00670       case HAL_IRDA_MSPDEINIT_CB_ID :
00671         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00672         break;
00673
00674       default :
00675         /* Update the error code */
00676         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00677
00678         /* Return error status */
00679         status =  HAL_ERROR;
00680         break;
00681     }
00682   }
00683   else
00684   {
00685     /* Update the error code */
00686     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00687
00688     /* Return error status */
00689     status =  HAL_ERROR;
00690   }
00691
00692   return status;
00693 }
00694 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00701   *  @brief   IRDA Transmit and Receive functions
00702   *
00703 @verbatim
00704  ===============================================================================
00705                          ##### IO operation functions #####
00706  ===============================================================================
00707   [..]
00708     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00709
00710   [..]
00711     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00712     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00713     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00714     While receiving data, transmission should be avoided as the data to be transmitted
00715     could be corrupted.
00716
00717   [..]
00718     (#) There are two modes of transfer:
00719         (++) Blocking mode: the communication is performed in polling mode.
00720              The HAL status of all data processing is returned by the same function
00721              after finishing transfer.
00722         (++) Non-Blocking mode: the communication is performed using Interrupts
00723              or DMA, these API's return the HAL status.
00724              The end of the data processing will be indicated through the
00725              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00726              using DMA mode.
00727              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00728              will be executed respectively at the end of the Transmit or Receive process
00729              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00730
00731     (#) Blocking mode APIs are :
00732         (++) HAL_IRDA_Transmit()
00733         (++) HAL_IRDA_Receive()
00734
00735     (#) Non Blocking mode APIs with Interrupt are :
00736         (++) HAL_IRDA_Transmit_IT()
00737         (++) HAL_IRDA_Receive_IT()
00738         (++) HAL_IRDA_IRQHandler()
00739
00740     (#) Non Blocking mode functions with DMA are :
00741         (++) HAL_IRDA_Transmit_DMA()
00742         (++) HAL_IRDA_Receive_DMA()
00743         (++) HAL_IRDA_DMAPause()
00744         (++) HAL_IRDA_DMAResume()
00745         (++) HAL_IRDA_DMAStop()
00746
00747     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00748         (++) HAL_IRDA_TxHalfCpltCallback()
00749         (++) HAL_IRDA_TxCpltCallback()
00750         (++) HAL_IRDA_RxHalfCpltCallback()
00751         (++) HAL_IRDA_RxCpltCallback()
00752         (++) HAL_IRDA_ErrorCallback()
00753
00754     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00755         (++) HAL_IRDA_Abort()
00756         (++) HAL_IRDA_AbortTransmit()
00757         (++) HAL_IRDA_AbortReceive()
00758         (++) HAL_IRDA_Abort_IT()
00759         (++) HAL_IRDA_AbortTransmit_IT()
00760         (++) HAL_IRDA_AbortReceive_IT()
00761
00762     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00763         (++) HAL_IRDA_AbortCpltCallback()
00764         (++) HAL_IRDA_AbortTransmitCpltCallback()
00765         (++) HAL_IRDA_AbortReceiveCpltCallback()
00766
00767     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00768         Errors are handled as follows :
00769         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00770              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
00771              in Interrupt mode reception .
00772              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
00773              to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00774              Transfer is kept ongoing on IRDA side.
00775              If user wants to abort it, Abort services should be called by user.
00776         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00777              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00778              Error code is set to allow user to identify error type, and
00779              HAL_IRDA_ErrorCallback() user callback is executed.
00780
00781 @endverbatim
00782   * @{
00783   */
00784
00785 /**
00786   * @brief Send an amount of data in blocking mode.
00787   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00788   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00789   *        of u16 available through pData.
00790   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00791   *               the configuration information for the specified IRDA module.
00792   * @param pData Pointer to data buffer (u8 or u16 data elements).
00793   * @param Size Amount of data elements (u8 or u16) to be sent.
00794   * @param Timeout Specify timeout value.
00795   * @retval HAL status
00796   */
00797 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
00798 {
00799   const uint8_t  *pdata8bits;
00800   const uint16_t *pdata16bits;
00801   uint32_t tickstart;
00802
00803   /* Check that a Tx process is not already ongoing */
00804   if (hirda->gState == HAL_IRDA_STATE_READY)
00805   {
00806     if ((pData == NULL) || (Size == 0U))
00807     {
00808       return  HAL_ERROR;
00809     }
00810
00811     /* Process Locked */
00812     __HAL_LOCK(hirda);
00813
00814     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00815     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00816
00817     /* Init tickstart for timeout management */
00818     tickstart = HAL_GetTick();
00819
00820     hirda->TxXferSize = Size;
00821     hirda->TxXferCount = Size;
00822
00823     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
00824     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00825     {
00826       pdata8bits  = NULL;
00827       pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
00828     }
00829     else
00830     {
00831       pdata8bits  = pData;
00832       pdata16bits = NULL;
00833     }
00834
00835     while (hirda->TxXferCount > 0U)
00836     {
00837       hirda->TxXferCount--;
00838
00839       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00840       {
00841         return HAL_TIMEOUT;
00842       }
00843       if (pdata8bits == NULL)
00844       {
00845         hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
00846         pdata16bits++;
00847       }
00848       else
00849       {
00850         hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
00851         pdata8bits++;
00852       }
00853     }
00854
00855     if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00856     {
00857       return HAL_TIMEOUT;
00858     }
00859
00860     /* At end of Tx process, restore hirda->gState to Ready */
00861     hirda->gState = HAL_IRDA_STATE_READY;
00862
00863     /* Process Unlocked */
00864     __HAL_UNLOCK(hirda);
00865
00866     return HAL_OK;
00867   }
00868   else
00869   {
00870     return HAL_BUSY;
00871   }
00872 }
00873
00874 /**
00875   * @brief Receive an amount of data in blocking mode.
00876   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00877   *        the received data is handled as a set of u16. In this case, Size must reflect the number
00878   *        of u16 available through pData.
00879   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00880   *                the configuration information for the specified IRDA module.
00881   * @param pData Pointer to data buffer (u8 or u16 data elements).
00882   * @param Size Amount of data elements (u8 or u16) to be received.
00883   * @param Timeout Specify timeout value.
00884   * @retval HAL status
00885   */
00886 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00887 {
00888   uint8_t  *pdata8bits;
00889   uint16_t *pdata16bits;
00890   uint16_t uhMask;
00891   uint32_t tickstart;
00892
00893   /* Check that a Rx process is not already ongoing */
00894   if (hirda->RxState == HAL_IRDA_STATE_READY)
00895   {
00896     if ((pData == NULL) || (Size == 0U))
00897     {
00898       return  HAL_ERROR;
00899     }
00900
00901     /* Process Locked */
00902     __HAL_LOCK(hirda);
00903
00904     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00905     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00906
00907     /* Init tickstart for timeout management */
00908     tickstart = HAL_GetTick();
00909
00910     hirda->RxXferSize = Size;
00911     hirda->RxXferCount = Size;
00912
00913     /* Computation of the mask to apply to RDR register
00914        of the UART associated to the IRDA */
00915     IRDA_MASK_COMPUTATION(hirda);
00916     uhMask = hirda->Mask;
00917
00918     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00919     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00920     {
00921       pdata8bits  = NULL;
00922       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00923     }
00924     else
00925     {
00926       pdata8bits  = pData;
00927       pdata16bits = NULL;
00928     }
00929
00930     /* Check data remaining to be received */
00931     while (hirda->RxXferCount > 0U)
00932     {
00933       hirda->RxXferCount--;
00934
00935       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00936       {
00937         return HAL_TIMEOUT;
00938       }
00939       if (pdata8bits == NULL)
00940       {
00941         *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
00942         pdata16bits++;
00943       }
00944       else
00945       {
00946         *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00947         pdata8bits++;
00948       }
00949     }
00950
00951     /* At end of Rx process, restore hirda->RxState to Ready */
00952     hirda->RxState = HAL_IRDA_STATE_READY;
00953
00954     /* Process Unlocked */
00955     __HAL_UNLOCK(hirda);
00956
00957     return HAL_OK;
00958   }
00959   else
00960   {
00961     return HAL_BUSY;
00962   }
00963 }
00964
00965 /**
00966   * @brief Send an amount of data in interrupt mode.
00967   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00968   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00969   *        of u16 available through pData.
00970   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00971   *                the configuration information for the specified IRDA module.
00972   * @param pData Pointer to data buffer (u8 or u16 data elements).
00973   * @param Size Amount of data elements (u8 or u16) to be sent.
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
00977 {
00978   /* Check that a Tx process is not already ongoing */
00979   if (hirda->gState == HAL_IRDA_STATE_READY)
00980   {
00981     if ((pData == NULL) || (Size == 0U))
00982     {
00983       return HAL_ERROR;
00984     }
00985
00986     /* Process Locked */
00987     __HAL_LOCK(hirda);
00988
00989     hirda->pTxBuffPtr = pData;
00990     hirda->TxXferSize = Size;
00991     hirda->TxXferCount = Size;
00992
00993     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00994     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00995
00996     /* Process Unlocked */
00997     __HAL_UNLOCK(hirda);
00998
00999     /* Enable the IRDA Transmit Data Register Empty Interrupt */
01000     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01001
01002     return HAL_OK;
01003   }
01004   else
01005   {
01006     return HAL_BUSY;
01007   }
01008 }
01009
01010 /**
01011   * @brief Receive an amount of data in interrupt mode.
01012   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01013   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01014   *        of u16 available through pData.
01015   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01016   *                the configuration information for the specified IRDA module.
01017   * @param pData Pointer to data buffer (u8 or u16 data elements).
01018   * @param Size Amount of data elements (u8 or u16) to be received.
01019   * @retval HAL status
01020   */
01021 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01022 {
01023   /* Check that a Rx process is not already ongoing */
01024   if (hirda->RxState == HAL_IRDA_STATE_READY)
01025   {
01026     if ((pData == NULL) || (Size == 0U))
01027     {
01028       return HAL_ERROR;
01029     }
01030
01031     /* Process Locked */
01032     __HAL_LOCK(hirda);
01033
01034     hirda->pRxBuffPtr = pData;
01035     hirda->RxXferSize = Size;
01036     hirda->RxXferCount = Size;
01037
01038     /* Computation of the mask to apply to the RDR register
01039        of the UART associated to the IRDA */
01040     IRDA_MASK_COMPUTATION(hirda);
01041
01042     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01043     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01044
01045     /* Process Unlocked */
01046     __HAL_UNLOCK(hirda);
01047
01048     if (hirda->Init.Parity != IRDA_PARITY_NONE)
01049     {
01050       /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
01051       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01052     }
01053     else
01054     {
01055       /* Enable the IRDA Data Register not empty Interrupts */
01056       SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01057     }
01058
01059     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01060     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01061
01062     return HAL_OK;
01063   }
01064   else
01065   {
01066     return HAL_BUSY;
01067   }
01068 }
01069
01070 /**
01071   * @brief Send an amount of data in DMA mode.
01072   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01073   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
01074   *        of u16 available through pData.
01075   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01076   *               the configuration information for the specified IRDA module.
01077   * @param pData pointer to data buffer (u8 or u16 data elements).
01078   * @param Size Amount of data elements (u8 or u16) to be sent.
01079   * @retval HAL status
01080   */
01081 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
01082 {
01083   /* Check that a Tx process is not already ongoing */
01084   if (hirda->gState == HAL_IRDA_STATE_READY)
01085   {
01086     if ((pData == NULL) || (Size == 0U))
01087     {
01088       return HAL_ERROR;
01089     }
01090
01091     /* Process Locked */
01092     __HAL_LOCK(hirda);
01093
01094     hirda->pTxBuffPtr = pData;
01095     hirda->TxXferSize = Size;
01096     hirda->TxXferCount = Size;
01097
01098     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01099     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
01100
01101     /* Set the IRDA DMA transfer complete callback */
01102     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
01103
01104     /* Set the IRDA DMA half transfer complete callback */
01105     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
01106
01107     /* Set the DMA error callback */
01108     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
01109
01110     /* Set the DMA abort callback */
01111     hirda->hdmatx->XferAbortCallback = NULL;
01112
01113     /* Enable the IRDA transmit DMA channel */
01114     if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
01115     {
01116       /* Clear the TC flag in the ICR register */
01117       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
01118
01119       /* Process Unlocked */
01120       __HAL_UNLOCK(hirda);
01121
01122       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01123          in the USART CR3 register */
01124       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01125
01126       return HAL_OK;
01127     }
01128     else
01129     {
01130       /* Set error code to DMA */
01131       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01132
01133       /* Process Unlocked */
01134       __HAL_UNLOCK(hirda);
01135
01136       /* Restore hirda->gState to ready */
01137       hirda->gState = HAL_IRDA_STATE_READY;
01138
01139       return HAL_ERROR;
01140     }
01141   }
01142   else
01143   {
01144     return HAL_BUSY;
01145   }
01146 }
01147
01148 /**
01149   * @brief Receive an amount of data in DMA mode.
01150   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01151   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01152   *        of u16 available through pData.
01153   * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
01154   *         the parity bit (MSB position).
01155   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01156   *               the configuration information for the specified IRDA module.
01157   * @param pData Pointer to data buffer (u8 or u16 data elements).
01158   * @param Size Amount of data elements (u8 or u16) to be received.
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01162 {
01163   /* Check that a Rx process is not already ongoing */
01164   if (hirda->RxState == HAL_IRDA_STATE_READY)
01165   {
01166     if ((pData == NULL) || (Size == 0U))
01167     {
01168       return HAL_ERROR;
01169     }
01170
01171     /* Process Locked */
01172     __HAL_LOCK(hirda);
01173
01174     hirda->pRxBuffPtr = pData;
01175     hirda->RxXferSize = Size;
01176
01177     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01178     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01179
01180     /* Set the IRDA DMA transfer complete callback */
01181     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
01182
01183     /* Set the IRDA DMA half transfer complete callback */
01184     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
01185
01186     /* Set the DMA error callback */
01187     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
01188
01189     /* Set the DMA abort callback */
01190     hirda->hdmarx->XferAbortCallback = NULL;
01191
01192     /* Enable the DMA channel */
01193     if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
01194     {
01195       /* Process Unlocked */
01196       __HAL_UNLOCK(hirda);
01197
01198       if (hirda->Init.Parity != IRDA_PARITY_NONE)
01199       {
01200         /* Enable the UART Parity Error Interrupt */
01201         SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01202       }
01203
01204       /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01205       SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01206
01207       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01208          in the USART CR3 register */
01209       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01210
01211       return HAL_OK;
01212     }
01213     else
01214     {
01215       /* Set error code to DMA */
01216       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01217
01218       /* Process Unlocked */
01219       __HAL_UNLOCK(hirda);
01220
01221       /* Restore hirda->RxState to ready */
01222       hirda->RxState = HAL_IRDA_STATE_READY;
01223
01224       return HAL_ERROR;
01225     }
01226   }
01227   else
01228   {
01229     return HAL_BUSY;
01230   }
01231 }
01232
01233
01234 /**
01235   * @brief Pause the DMA Transfer.
01236   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01237   *                the configuration information for the specified IRDA module.
01238   * @retval HAL status
01239   */
01240 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
01241 {
01242   /* Process Locked */
01243   __HAL_LOCK(hirda);
01244
01245   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01246   {
01247     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01248     {
01249       /* Disable the IRDA DMA Tx request */
01250       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01251     }
01252   }
01253   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01254   {
01255     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01256     {
01257       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01258       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01259       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01260
01261       /* Disable the IRDA DMA Rx request */
01262       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01263     }
01264   }
01265
01266   /* Process Unlocked */
01267   __HAL_UNLOCK(hirda);
01268
01269   return HAL_OK;
01270 }
01271
01272 /**
01273   * @brief Resume the DMA Transfer.
01274   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01275   *                the configuration information for the specified UART module.
01276   * @retval HAL status
01277   */
01278 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
01279 {
01280   /* Process Locked */
01281   __HAL_LOCK(hirda);
01282
01283   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01284   {
01285     /* Enable the IRDA DMA Tx request */
01286     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01287   }
01288   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01289   {
01290     /* Clear the Overrun flag before resuming the Rx transfer*/
01291     __HAL_IRDA_CLEAR_OREFLAG(hirda);
01292
01293     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01294     if (hirda->Init.Parity != IRDA_PARITY_NONE)
01295     {
01296       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01297     }
01298     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01299
01300     /* Enable the IRDA DMA Rx request */
01301     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01302   }
01303
01304   /* Process Unlocked */
01305   __HAL_UNLOCK(hirda);
01306
01307   return HAL_OK;
01308 }
01309
01310 /**
01311   * @brief Stop the DMA Transfer.
01312   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01313   *                the configuration information for the specified UART module.
01314   * @retval HAL status
01315   */
01316 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
01317 {
01318   /* The Lock is not implemented on this API to allow the user application
01319      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
01320      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
01321      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01322      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01323      the stream and the corresponding call back is executed. */
01324
01325   /* Stop IRDA DMA Tx request if ongoing */
01326   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01327   {
01328     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01329     {
01330       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01331
01332       /* Abort the IRDA DMA Tx channel */
01333       if (hirda->hdmatx != NULL)
01334       {
01335         if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01336         {
01337           if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01338           {
01339             /* Set error code to DMA */
01340             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01341
01342             return HAL_TIMEOUT;
01343           }
01344         }
01345       }
01346
01347       IRDA_EndTxTransfer(hirda);
01348     }
01349   }
01350
01351   /* Stop IRDA DMA Rx request if ongoing */
01352   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01353   {
01354     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01355     {
01356       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01357
01358       /* Abort the IRDA DMA Rx channel */
01359       if (hirda->hdmarx != NULL)
01360       {
01361         if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01362         {
01363           if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01364           {
01365             /* Set error code to DMA */
01366             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01367
01368             return HAL_TIMEOUT;
01369           }
01370         }
01371       }
01372
01373       IRDA_EndRxTransfer(hirda);
01374     }
01375   }
01376
01377   return HAL_OK;
01378 }
01379
01380 /**
01381   * @brief  Abort ongoing transfers (blocking mode).
01382   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01383   *               the configuration information for the specified UART module.
01384   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01385   *         This procedure performs following operations :
01386   *           - Disable IRDA Interrupts (Tx and Rx)
01387   *           - Disable the DMA transfer in the peripheral register (if enabled)
01388   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01389   *           - Set handle State to READY
01390   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01391   * @retval HAL status
01392   */
01393 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
01394 {
01395   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01396   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
01397                                    USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01398   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01399
01400   /* Disable the IRDA DMA Tx request if enabled */
01401   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01402   {
01403     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01404
01405     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01406     if (hirda->hdmatx != NULL)
01407     {
01408       /* Set the IRDA DMA Abort callback to Null.
01409          No call back execution at end of DMA abort procedure */
01410       hirda->hdmatx->XferAbortCallback = NULL;
01411
01412       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01413       {
01414         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01415         {
01416           /* Set error code to DMA */
01417           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01418
01419           return HAL_TIMEOUT;
01420         }
01421       }
01422     }
01423   }
01424
01425   /* Disable the IRDA DMA Rx request if enabled */
01426   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01427   {
01428     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01429
01430     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01431     if (hirda->hdmarx != NULL)
01432     {
01433       /* Set the IRDA DMA Abort callback to Null.
01434          No call back execution at end of DMA abort procedure */
01435       hirda->hdmarx->XferAbortCallback = NULL;
01436
01437       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01438       {
01439         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01440         {
01441           /* Set error code to DMA */
01442           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01443
01444           return HAL_TIMEOUT;
01445         }
01446       }
01447     }
01448   }
01449
01450   /* Reset Tx and Rx transfer counters */
01451   hirda->TxXferCount = 0U;
01452   hirda->RxXferCount = 0U;
01453
01454   /* Clear the Error flags in the ICR register */
01455   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01456
01457   /* Restore hirda->gState and hirda->RxState to Ready */
01458   hirda->gState  = HAL_IRDA_STATE_READY;
01459   hirda->RxState = HAL_IRDA_STATE_READY;
01460
01461   /* Reset Handle ErrorCode to No Error */
01462   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01463
01464   return HAL_OK;
01465 }
01466
01467 /**
01468   * @brief  Abort ongoing Transmit transfer (blocking mode).
01469   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01470   *               the configuration information for the specified UART module.
01471   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01472   *         This procedure performs following operations :
01473   *           - Disable IRDA Interrupts (Tx)
01474   *           - Disable the DMA transfer in the peripheral register (if enabled)
01475   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01476   *           - Set handle State to READY
01477   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01478   * @retval HAL status
01479   */
01480 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01481 {
01482   /* Disable TXEIE and TCIE interrupts */
01483   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01484
01485   /* Disable the IRDA DMA Tx request if enabled */
01486   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01487   {
01488     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01489
01490     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01491     if (hirda->hdmatx != NULL)
01492     {
01493       /* Set the IRDA DMA Abort callback to Null.
01494          No call back execution at end of DMA abort procedure */
01495       hirda->hdmatx->XferAbortCallback = NULL;
01496
01497       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01498       {
01499         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01500         {
01501           /* Set error code to DMA */
01502           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01503
01504           return HAL_TIMEOUT;
01505         }
01506       }
01507     }
01508   }
01509
01510   /* Reset Tx transfer counter */
01511   hirda->TxXferCount = 0U;
01512
01513   /* Restore hirda->gState to Ready */
01514   hirda->gState = HAL_IRDA_STATE_READY;
01515
01516   return HAL_OK;
01517 }
01518
01519 /**
01520   * @brief  Abort ongoing Receive transfer (blocking mode).
01521   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01522   *               the configuration information for the specified UART module.
01523   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01524   *         This procedure performs following operations :
01525   *           - Disable IRDA Interrupts (Rx)
01526   *           - Disable the DMA transfer in the peripheral register (if enabled)
01527   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01528   *           - Set handle State to READY
01529   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01530   * @retval HAL status
01531   */
01532 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01533 {
01534   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01535   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01536   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01537
01538   /* Disable the IRDA DMA Rx request if enabled */
01539   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01540   {
01541     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01542
01543     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01544     if (hirda->hdmarx != NULL)
01545     {
01546       /* Set the IRDA DMA Abort callback to Null.
01547          No call back execution at end of DMA abort procedure */
01548       hirda->hdmarx->XferAbortCallback = NULL;
01549
01550       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01551       {
01552         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01553         {
01554           /* Set error code to DMA */
01555           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01556
01557           return HAL_TIMEOUT;
01558         }
01559       }
01560     }
01561   }
01562
01563   /* Reset Rx transfer counter */
01564   hirda->RxXferCount = 0U;
01565
01566   /* Clear the Error flags in the ICR register */
01567   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01568
01569   /* Restore hirda->RxState to Ready */
01570   hirda->RxState = HAL_IRDA_STATE_READY;
01571
01572   return HAL_OK;
01573 }
01574
01575 /**
01576   * @brief  Abort ongoing transfers (Interrupt mode).
01577   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01578   *               the configuration information for the specified UART module.
01579   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01580   *         This procedure performs following operations :
01581   *           - Disable IRDA Interrupts (Tx and Rx)
01582   *           - Disable the DMA transfer in the peripheral register (if enabled)
01583   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01584   *           - Set handle State to READY
01585   *           - At abort completion, call user abort complete callback
01586   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01587   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01588   * @retval HAL status
01589   */
01590 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01591 {
01592   uint32_t abortcplt = 1U;
01593
01594   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01595   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
01596                                    USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01597   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01598
01599   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01600      before any call to DMA Abort functions */
01601   /* DMA Tx Handle is valid */
01602   if (hirda->hdmatx != NULL)
01603   {
01604     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01605        Otherwise, set it to NULL */
01606     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01607     {
01608       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01609     }
01610     else
01611     {
01612       hirda->hdmatx->XferAbortCallback = NULL;
01613     }
01614   }
01615   /* DMA Rx Handle is valid */
01616   if (hirda->hdmarx != NULL)
01617   {
01618     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01619        Otherwise, set it to NULL */
01620     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01621     {
01622       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01623     }
01624     else
01625     {
01626       hirda->hdmarx->XferAbortCallback = NULL;
01627     }
01628   }
01629
01630   /* Disable the IRDA DMA Tx request if enabled */
01631   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01632   {
01633     /* Disable DMA Tx at UART level */
01634     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01635
01636     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01637     if (hirda->hdmatx != NULL)
01638     {
01639       /* IRDA Tx DMA Abort callback has already been initialised :
01640          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01641
01642       /* Abort DMA TX */
01643       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01644       {
01645         hirda->hdmatx->XferAbortCallback = NULL;
01646       }
01647       else
01648       {
01649         abortcplt = 0U;
01650       }
01651     }
01652   }
01653
01654   /* Disable the IRDA DMA Rx request if enabled */
01655   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01656   {
01657     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01658
01659     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01660     if (hirda->hdmarx != NULL)
01661     {
01662       /* IRDA Rx DMA Abort callback has already been initialised :
01663          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01664
01665       /* Abort DMA RX */
01666       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01667       {
01668         hirda->hdmarx->XferAbortCallback = NULL;
01669         abortcplt = 1U;
01670       }
01671       else
01672       {
01673         abortcplt = 0U;
01674       }
01675     }
01676   }
01677
01678   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01679   if (abortcplt == 1U)
01680   {
01681     /* Reset Tx and Rx transfer counters */
01682     hirda->TxXferCount = 0U;
01683     hirda->RxXferCount = 0U;
01684
01685     /* Reset errorCode */
01686     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01687
01688     /* Clear the Error flags in the ICR register */
01689     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01690
01691     /* Restore hirda->gState and hirda->RxState to Ready */
01692     hirda->gState  = HAL_IRDA_STATE_READY;
01693     hirda->RxState = HAL_IRDA_STATE_READY;
01694
01695     /* As no DMA to be aborted, call directly user Abort complete callback */
01696 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01697     /* Call registered Abort complete callback */
01698     hirda->AbortCpltCallback(hirda);
01699 #else
01700     /* Call legacy weak Abort complete callback */
01701     HAL_IRDA_AbortCpltCallback(hirda);
01702 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01703   }
01704
01705   return HAL_OK;
01706 }
01707
01708 /**
01709   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01710   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01711   *               the configuration information for the specified UART module.
01712   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01713   *         This procedure performs following operations :
01714   *           - Disable IRDA Interrupts (Tx)
01715   *           - Disable the DMA transfer in the peripheral register (if enabled)
01716   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01717   *           - Set handle State to READY
01718   *           - At abort completion, call user abort complete callback
01719   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01720   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01721   * @retval HAL status
01722   */
01723 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01724 {
01725   /* Disable TXEIE and TCIE interrupts */
01726   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01727
01728   /* Disable the IRDA DMA Tx request if enabled */
01729   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01730   {
01731     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01732
01733     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01734     if (hirda->hdmatx != NULL)
01735     {
01736       /* Set the IRDA DMA Abort callback :
01737          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01738       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01739
01740       /* Abort DMA TX */
01741       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01742       {
01743         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01744         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01745       }
01746     }
01747     else
01748     {
01749       /* Reset Tx transfer counter */
01750       hirda->TxXferCount = 0U;
01751
01752       /* Restore hirda->gState to Ready */
01753       hirda->gState = HAL_IRDA_STATE_READY;
01754
01755       /* As no DMA to be aborted, call directly user Abort complete callback */
01756 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01757       /* Call registered Abort Transmit Complete Callback */
01758       hirda->AbortTransmitCpltCallback(hirda);
01759 #else
01760       /* Call legacy weak Abort Transmit Complete Callback */
01761       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01762 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01763     }
01764   }
01765   else
01766   {
01767     /* Reset Tx transfer counter */
01768     hirda->TxXferCount = 0U;
01769
01770     /* Restore hirda->gState to Ready */
01771     hirda->gState = HAL_IRDA_STATE_READY;
01772
01773     /* As no DMA to be aborted, call directly user Abort complete callback */
01774 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01775     /* Call registered Abort Transmit Complete Callback */
01776     hirda->AbortTransmitCpltCallback(hirda);
01777 #else
01778     /* Call legacy weak Abort Transmit Complete Callback */
01779     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01780 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01781   }
01782
01783   return HAL_OK;
01784 }
01785
01786 /**
01787   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01788   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01789   *               the configuration information for the specified UART module.
01790   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01791   *         This procedure performs following operations :
01792   *           - Disable IRDA Interrupts (Rx)
01793   *           - Disable the DMA transfer in the peripheral register (if enabled)
01794   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01795   *           - Set handle State to READY
01796   *           - At abort completion, call user abort complete callback
01797   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01798   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01799   * @retval HAL status
01800   */
01801 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01802 {
01803   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01804   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01805   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01806
01807   /* Disable the IRDA DMA Rx request if enabled */
01808   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01809   {
01810     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01811
01812     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01813     if (hirda->hdmarx != NULL)
01814     {
01815       /* Set the IRDA DMA Abort callback :
01816          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01817       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01818
01819       /* Abort DMA RX */
01820       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01821       {
01822         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01823         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01824       }
01825     }
01826     else
01827     {
01828       /* Reset Rx transfer counter */
01829       hirda->RxXferCount = 0U;
01830
01831       /* Clear the Error flags in the ICR register */
01832       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01833
01834       /* Restore hirda->RxState to Ready */
01835       hirda->RxState = HAL_IRDA_STATE_READY;
01836
01837       /* As no DMA to be aborted, call directly user Abort complete callback */
01838 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01839       /* Call registered Abort Receive Complete Callback */
01840       hirda->AbortReceiveCpltCallback(hirda);
01841 #else
01842       /* Call legacy weak Abort Receive Complete Callback */
01843       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01844 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01845     }
01846   }
01847   else
01848   {
01849     /* Reset Rx transfer counter */
01850     hirda->RxXferCount = 0U;
01851
01852     /* Clear the Error flags in the ICR register */
01853     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01854
01855     /* Restore hirda->RxState to Ready */
01856     hirda->RxState = HAL_IRDA_STATE_READY;
01857
01858     /* As no DMA to be aborted, call directly user Abort complete callback */
01859 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01860     /* Call registered Abort Receive Complete Callback */
01861     hirda->AbortReceiveCpltCallback(hirda);
01862 #else
01863     /* Call legacy weak Abort Receive Complete Callback */
01864     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01865 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01866   }
01867
01868   return HAL_OK;
01869 }
01870
01871 /**
01872   * @brief Handle IRDA interrupt request.
01873   * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
01874   *               the configuration information for the specified IRDA module.
01875   * @retval None
01876   */
01877 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01878 {
01879   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01880   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01881   uint32_t cr3its;
01882   uint32_t errorflags;
01883   uint32_t errorcode;
01884
01885   /* If no error occurs */
01886   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01887   if (errorflags == 0U)
01888   {
01889     /* IRDA in mode Receiver ---------------------------------------------------*/
01890     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01891     {
01892       IRDA_Receive_IT(hirda);
01893       return;
01894     }
01895   }
01896
01897   /* If some errors occur */
01898   cr3its = READ_REG(hirda->Instance->CR3);
01899   if ((errorflags != 0U)
01900       && (((cr3its & USART_CR3_EIE) != 0U)
01901           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
01902   {
01903     /* IRDA parity error interrupt occurred -------------------------------------*/
01904     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01905     {
01906       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
01907
01908       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01909     }
01910
01911     /* IRDA frame error interrupt occurred --------------------------------------*/
01912     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01913     {
01914       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
01915
01916       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01917     }
01918
01919     /* IRDA noise error interrupt occurred --------------------------------------*/
01920     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01921     {
01922       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
01923
01924       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01925     }
01926
01927     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
01928     if (((isrflags & USART_ISR_ORE) != 0U) &&
01929         (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
01930     {
01931       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
01932
01933       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01934     }
01935
01936     /* Call IRDA Error Call back function if need be --------------------------*/
01937     if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01938     {
01939       /* IRDA in mode Receiver ---------------------------------------------------*/
01940       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01941       {
01942         IRDA_Receive_IT(hirda);
01943       }
01944
01945       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01946          consider error as blocking */
01947       errorcode = hirda->ErrorCode;
01948       if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
01949           ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
01950       {
01951         /* Blocking error : transfer is aborted
01952            Set the IRDA state ready to be able to start again the process,
01953            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01954         IRDA_EndRxTransfer(hirda);
01955
01956         /* Disable the IRDA DMA Rx request if enabled */
01957         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01958         {
01959           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01960
01961           /* Abort the IRDA DMA Rx channel */
01962           if (hirda->hdmarx != NULL)
01963           {
01964             /* Set the IRDA DMA Abort callback :
01965                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01966             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01967
01968             /* Abort DMA RX */
01969             if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01970             {
01971               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01972               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01973             }
01974           }
01975           else
01976           {
01977 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01978             /* Call registered user error callback */
01979             hirda->ErrorCallback(hirda);
01980 #else
01981             /* Call legacy weak user error callback */
01982             HAL_IRDA_ErrorCallback(hirda);
01983 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01984           }
01985         }
01986         else
01987         {
01988 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01989           /* Call registered user error callback */
01990           hirda->ErrorCallback(hirda);
01991 #else
01992           /* Call legacy weak user error callback */
01993           HAL_IRDA_ErrorCallback(hirda);
01994 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01995         }
01996       }
01997       else
01998       {
01999         /* Non Blocking error : transfer could go on.
02000            Error is notified to user through user error callback */
02001 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02002         /* Call registered user error callback */
02003         hirda->ErrorCallback(hirda);
02004 #else
02005         /* Call legacy weak user error callback */
02006         HAL_IRDA_ErrorCallback(hirda);
02007 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02008         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02009       }
02010     }
02011     return;
02012
02013   } /* End if some error occurs */
02014
02015   /* IRDA in mode Transmitter ------------------------------------------------*/
02016   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
02017   {
02018     IRDA_Transmit_IT(hirda);
02019     return;
02020   }
02021
02022   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
02023   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02024   {
02025     IRDA_EndTransmit_IT(hirda);
02026     return;
02027   }
02028
02029 }
02030
02031 /**
02032   * @brief  Tx Transfer completed callback.
02033   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02034   *               the configuration information for the specified IRDA module.
02035   * @retval None
02036   */
02037 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
02038 {
02039   /* Prevent unused argument(s) compilation warning */
02040   UNUSED(hirda);
02041
02042   /* NOTE : This function should not be modified, when the callback is needed,
02043             the HAL_IRDA_TxCpltCallback can be implemented in the user file.
02044    */
02045 }
02046
02047 /**
02048   * @brief  Tx Half Transfer completed callback.
02049   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02050   *               the configuration information for the specified USART module.
02051   * @retval None
02052   */
02053 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02054 {
02055   /* Prevent unused argument(s) compilation warning */
02056   UNUSED(hirda);
02057
02058   /* NOTE : This function should not be modified, when the callback is needed,
02059             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
02060    */
02061 }
02062
02063 /**
02064   * @brief  Rx Transfer completed callback.
02065   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02066   *               the configuration information for the specified IRDA module.
02067   * @retval None
02068   */
02069 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
02070 {
02071   /* Prevent unused argument(s) compilation warning */
02072   UNUSED(hirda);
02073
02074   /* NOTE : This function should not be modified, when the callback is needed,
02075             the HAL_IRDA_RxCpltCallback can be implemented in the user file.
02076    */
02077 }
02078
02079 /**
02080   * @brief  Rx Half Transfer complete callback.
02081   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02082   *               the configuration information for the specified IRDA module.
02083   * @retval None
02084   */
02085 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02086 {
02087   /* Prevent unused argument(s) compilation warning */
02088   UNUSED(hirda);
02089
02090   /* NOTE : This function should not be modified, when the callback is needed,
02091             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
02092    */
02093 }
02094
02095 /**
02096   * @brief  IRDA error callback.
02097   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02098   *               the configuration information for the specified IRDA module.
02099   * @retval None
02100   */
02101 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
02102 {
02103   /* Prevent unused argument(s) compilation warning */
02104   UNUSED(hirda);
02105
02106   /* NOTE : This function should not be modified, when the callback is needed,
02107             the HAL_IRDA_ErrorCallback can be implemented in the user file.
02108    */
02109 }
02110
02111 /**
02112   * @brief  IRDA Abort Complete callback.
02113   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02114   *               the configuration information for the specified IRDA module.
02115   * @retval None
02116   */
02117 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
02118 {
02119   /* Prevent unused argument(s) compilation warning */
02120   UNUSED(hirda);
02121
02122   /* NOTE : This function should not be modified, when the callback is needed,
02123             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
02124    */
02125 }
02126
02127 /**
02128   * @brief  IRDA Abort Complete callback.
02129   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02130   *               the configuration information for the specified IRDA module.
02131   * @retval None
02132   */
02133 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
02134 {
02135   /* Prevent unused argument(s) compilation warning */
02136   UNUSED(hirda);
02137
02138   /* NOTE : This function should not be modified, when the callback is needed,
02139             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
02140    */
02141 }
02142
02143 /**
02144   * @brief  IRDA Abort Receive Complete callback.
02145   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02146   *               the configuration information for the specified IRDA module.
02147   * @retval None
02148   */
02149 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
02150 {
02151   /* Prevent unused argument(s) compilation warning */
02152   UNUSED(hirda);
02153
02154   /* NOTE : This function should not be modified, when the callback is needed,
02155             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
02156    */
02157 }
02158
02159 /**
02160   * @}
02161   */
02162
02163 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
02164   *  @brief   IRDA State and Errors functions
02165   *
02166 @verbatim
02167   ==============================================================================
02168             ##### Peripheral State and Error functions #####
02169   ==============================================================================
02170   [..]
02171     This subsection provides a set of functions allowing to return the State of IrDA
02172     communication process and also return Peripheral Errors occurred during communication process
02173      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
02174          of the IRDA peripheral handle.
02175      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
02176          communication.
02177
02178 @endverbatim
02179   * @{
02180   */
02181
02182 /**
02183   * @brief Return the IRDA handle state.
02184   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02185   *                the configuration information for the specified IRDA module.
02186   * @retval HAL state
02187   */
02188 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
02189 {
02190   /* Return IRDA handle state */
02191   uint32_t temp1;
02192   uint32_t temp2;
02193   temp1 = (uint32_t)hirda->gState;
02194   temp2 = (uint32_t)hirda->RxState;
02195
02196   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
02197 }
02198
02199 /**
02200   * @brief Return the IRDA handle error code.
02201   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02202   *               the configuration information for the specified IRDA module.
02203   * @retval IRDA Error Code
02204   */
02205 uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
02206 {
02207   return hirda->ErrorCode;
02208 }
02209
02210 /**
02211   * @}
02212   */
02213
02214 /**
02215   * @}
02216   */
02217
02218 /** @defgroup IRDA_Private_Functions IRDA Private Functions
02219   * @{
02220   */
02221
02222 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02223 /**
02224   * @brief  Initialize the callbacks to their default values.
02225   * @param  hirda IRDA handle.
02226   * @retval none
02227   */
02228 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
02229 {
02230   /* Init the IRDA Callback settings */
02231   hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02232   hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02233   hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02234   hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02235   hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
02236   hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02237   hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02238   hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02239
02240 }
02241 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02242
02243 /**
02244   * @brief Configure the IRDA peripheral.
02245   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02246   *               the configuration information for the specified IRDA module.
02247   * @retval HAL status
02248   */
02249 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
02250 {
02251   uint32_t tmpreg;
02252   IRDA_ClockSourceTypeDef clocksource;
02253   HAL_StatusTypeDef ret = HAL_OK;
02254   static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02255   uint32_t pclk;
02256
02257   /* Check the communication parameters */
02258   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
02259   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
02260   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
02261   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
02262   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
02263   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
02264   assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
02265
02266   /*-------------------------- USART CR1 Configuration -----------------------*/
02267   /* Configure the IRDA Word Length, Parity and transfer Mode:
02268      Set the M bits according to hirda->Init.WordLength value
02269      Set PCE and PS bits according to hirda->Init.Parity value
02270      Set TE and RE bits according to hirda->Init.Mode value */
02271   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
02272
02273   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
02274
02275   /*-------------------------- USART CR3 Configuration -----------------------*/
02276   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
02277
02278   /*--------------------- USART clock PRESC Configuration ----------------*/
02279   /* Configure
02280   * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
02281   MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
02282
02283   /*-------------------------- USART GTPR Configuration ----------------------*/
02284   MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
02285
02286   /*-------------------------- USART BRR Configuration -----------------------*/
02287   IRDA_GETCLOCKSOURCE(hirda, clocksource);
02288   tmpreg =   0U;
02289   switch (clocksource)
02290   {
02291     case IRDA_CLOCKSOURCE_PCLK1:
02292       pclk = HAL_RCC_GetPCLK1Freq();
02293       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02294       break;
02295     case IRDA_CLOCKSOURCE_PCLK2:
02296       pclk = HAL_RCC_GetPCLK2Freq();
02297       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02298       break;
02299     case IRDA_CLOCKSOURCE_HSI:
02300       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02301       break;
02302     case IRDA_CLOCKSOURCE_SYSCLK:
02303       pclk = HAL_RCC_GetSysClockFreq();
02304       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02305       break;
02306     case IRDA_CLOCKSOURCE_LSE:
02307       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02308       break;
02309     default:
02310       ret = HAL_ERROR;
02311       break;
02312   }
02313
02314   /* USARTDIV must be greater than or equal to 0d16 */
02315   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02316   {
02317     hirda->Instance->BRR = (uint16_t)tmpreg;
02318   }
02319   else
02320   {
02321     ret = HAL_ERROR;
02322   }
02323
02324   return ret;
02325 }
02326
02327 /**
02328   * @brief Check the IRDA Idle State.
02329   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02330   *               the configuration information for the specified IRDA module.
02331   * @retval HAL status
02332   */
02333 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
02334 {
02335   uint32_t tickstart;
02336
02337   /* Initialize the IRDA ErrorCode */
02338   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02339
02340   /* Init tickstart for timeout management */
02341   tickstart = HAL_GetTick();
02342
02343   /* Check if the Transmitter is enabled */
02344   if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02345   {
02346     /* Wait until TEACK flag is set */
02347     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02348     {
02349       /* Timeout occurred */
02350       return HAL_TIMEOUT;
02351     }
02352   }
02353   /* Check if the Receiver is enabled */
02354   if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02355   {
02356     /* Wait until REACK flag is set */
02357     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02358     {
02359       /* Timeout occurred */
02360       return HAL_TIMEOUT;
02361     }
02362   }
02363
02364   /* Initialize the IRDA state*/
02365   hirda->gState  = HAL_IRDA_STATE_READY;
02366   hirda->RxState = HAL_IRDA_STATE_READY;
02367
02368   /* Process Unlocked */
02369   __HAL_UNLOCK(hirda);
02370
02371   return HAL_OK;
02372 }
02373
02374 /**
02375   * @brief  Handle IRDA Communication Timeout. It waits
02376   *         until a flag is no longer in the specified status.
02377   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02378   *               the configuration information for the specified IRDA module.
02379   * @param  Flag Specifies the IRDA flag to check.
02380   * @param  Status The actual Flag status (SET or RESET)
02381   * @param  Tickstart Tick start value
02382   * @param  Timeout Timeout duration
02383   * @retval HAL status
02384   */
02385 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
02386                                                      uint32_t Tickstart, uint32_t Timeout)
02387 {
02388   /* Wait until flag is set */
02389   while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
02390   {
02391     /* Check for the Timeout */
02392     if (Timeout != HAL_MAX_DELAY)
02393     {
02394       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02395       {
02396         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
02397            interrupts for the interrupt process */
02398         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02399         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02400
02401         hirda->gState  = HAL_IRDA_STATE_READY;
02402         hirda->RxState = HAL_IRDA_STATE_READY;
02403
02404         /* Process Unlocked */
02405         __HAL_UNLOCK(hirda);
02406         return HAL_TIMEOUT;
02407       }
02408     }
02409   }
02410   return HAL_OK;
02411 }
02412
02413
02414 /**
02415   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
02416   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02417   *               the configuration information for the specified IRDA module.
02418   * @retval None
02419   */
02420 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
02421 {
02422   /* Disable TXEIE and TCIE interrupts */
02423   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02424
02425   /* At end of Tx process, restore hirda->gState to Ready */
02426   hirda->gState = HAL_IRDA_STATE_READY;
02427 }
02428
02429 /**
02430   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02431   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02432   *               the configuration information for the specified IRDA module.
02433   * @retval None
02434   */
02435 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
02436 {
02437   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02438   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02439   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02440
02441   /* At end of Rx process, restore hirda->RxState to Ready */
02442   hirda->RxState = HAL_IRDA_STATE_READY;
02443 }
02444
02445
02446 /**
02447   * @brief  DMA IRDA transmit process complete callback.
02448   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02449   *              the configuration information for the specified DMA module.
02450   * @retval None
02451   */
02452 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02453 {
02454   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02455
02456   /* DMA Normal mode */
02457   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02458   {
02459     hirda->TxXferCount = 0U;
02460
02461     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02462        in the IRDA CR3 register */
02463     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
02464
02465     /* Enable the IRDA Transmit Complete Interrupt */
02466     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02467   }
02468   /* DMA Circular mode */
02469   else
02470   {
02471 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02472     /* Call registered Tx complete callback */
02473     hirda->TxCpltCallback(hirda);
02474 #else
02475     /* Call legacy weak Tx complete callback */
02476     HAL_IRDA_TxCpltCallback(hirda);
02477 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02478   }
02479
02480 }
02481
02482 /**
02483   * @brief  DMA IRDA transmit process half complete callback.
02484   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02485   *              the configuration information for the specified DMA module.
02486   * @retval None
02487   */
02488 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
02489 {
02490   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02491
02492 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02493   /* Call registered Tx Half complete callback */
02494   hirda->TxHalfCpltCallback(hirda);
02495 #else
02496   /* Call legacy weak Tx complete callback */
02497   HAL_IRDA_TxHalfCpltCallback(hirda);
02498 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02499 }
02500
02501 /**
02502   * @brief  DMA IRDA receive process complete callback.
02503   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02504   *               the configuration information for the specified DMA module.
02505   * @retval None
02506   */
02507 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02508 {
02509   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02510
02511   /* DMA Normal mode */
02512   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02513   {
02514     hirda->RxXferCount = 0U;
02515
02516     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02517     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
02518     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02519
02520     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02521        in the IRDA CR3 register */
02522     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
02523
02524     /* At end of Rx process, restore hirda->RxState to Ready */
02525     hirda->RxState = HAL_IRDA_STATE_READY;
02526   }
02527
02528 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02529   /* Call registered Rx complete callback */
02530   hirda->RxCpltCallback(hirda);
02531 #else
02532   /* Call legacy weak Rx complete callback */
02533   HAL_IRDA_RxCpltCallback(hirda);
02534 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02535 }
02536
02537 /**
02538   * @brief DMA IRDA receive process half complete callback.
02539   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02540   *              the configuration information for the specified DMA module.
02541   * @retval None
02542   */
02543 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
02544 {
02545   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02546
02547 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02548   /*Call registered Rx Half complete callback*/
02549   hirda->RxHalfCpltCallback(hirda);
02550 #else
02551   /* Call legacy weak Rx Half complete callback */
02552   HAL_IRDA_RxHalfCpltCallback(hirda);
02553 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02554 }
02555
02556 /**
02557   * @brief DMA IRDA communication error callback.
02558   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02559   *              the configuration information for the specified DMA module.
02560   * @retval None
02561   */
02562 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
02563 {
02564   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02565
02566   /* Stop IRDA DMA Tx request if ongoing */
02567   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02568   {
02569     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
02570     {
02571       hirda->TxXferCount = 0U;
02572       IRDA_EndTxTransfer(hirda);
02573     }
02574   }
02575
02576   /* Stop IRDA DMA Rx request if ongoing */
02577   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02578   {
02579     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
02580     {
02581       hirda->RxXferCount = 0U;
02582       IRDA_EndRxTransfer(hirda);
02583     }
02584   }
02585
02586   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
02587 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02588   /* Call registered user error callback */
02589   hirda->ErrorCallback(hirda);
02590 #else
02591   /* Call legacy weak user error callback */
02592   HAL_IRDA_ErrorCallback(hirda);
02593 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02594 }
02595
02596 /**
02597   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
02598   *         (To be called at end of DMA Abort procedure following error occurrence).
02599   * @param  hdma DMA handle.
02600   * @retval None
02601   */
02602 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02603 {
02604   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02605   hirda->RxXferCount = 0U;
02606   hirda->TxXferCount = 0U;
02607
02608 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02609   /* Call registered user error callback */
02610   hirda->ErrorCallback(hirda);
02611 #else
02612   /* Call legacy weak user error callback */
02613   HAL_IRDA_ErrorCallback(hirda);
02614 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02615 }
02616
02617 /**
02618   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02619   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02620   * @note   When this callback is executed, User Abort complete call back is called only if no
02621   *         Abort still ongoing for Rx DMA Handle.
02622   * @param  hdma DMA handle.
02623   * @retval None
02624   */
02625 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02626 {
02627   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02628
02629   hirda->hdmatx->XferAbortCallback = NULL;
02630
02631   /* Check if an Abort process is still ongoing */
02632   if (hirda->hdmarx != NULL)
02633   {
02634     if (hirda->hdmarx->XferAbortCallback != NULL)
02635     {
02636       return;
02637     }
02638   }
02639
02640   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02641   hirda->TxXferCount = 0U;
02642   hirda->RxXferCount = 0U;
02643
02644   /* Reset errorCode */
02645   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02646
02647   /* Clear the Error flags in the ICR register */
02648   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02649
02650   /* Restore hirda->gState and hirda->RxState to Ready */
02651   hirda->gState  = HAL_IRDA_STATE_READY;
02652   hirda->RxState = HAL_IRDA_STATE_READY;
02653
02654   /* Call user Abort complete callback */
02655 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02656   /* Call registered Abort complete callback */
02657   hirda->AbortCpltCallback(hirda);
02658 #else
02659   /* Call legacy weak Abort complete callback */
02660   HAL_IRDA_AbortCpltCallback(hirda);
02661 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02662 }
02663
02664
02665 /**
02666   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02667   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02668   * @note   When this callback is executed, User Abort complete call back is called only if no
02669   *         Abort still ongoing for Tx DMA Handle.
02670   * @param  hdma DMA handle.
02671   * @retval None
02672   */
02673 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02674 {
02675   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02676
02677   hirda->hdmarx->XferAbortCallback = NULL;
02678
02679   /* Check if an Abort process is still ongoing */
02680   if (hirda->hdmatx != NULL)
02681   {
02682     if (hirda->hdmatx->XferAbortCallback != NULL)
02683     {
02684       return;
02685     }
02686   }
02687
02688   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02689   hirda->TxXferCount = 0U;
02690   hirda->RxXferCount = 0U;
02691
02692   /* Reset errorCode */
02693   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02694
02695   /* Clear the Error flags in the ICR register */
02696   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02697
02698   /* Restore hirda->gState and hirda->RxState to Ready */
02699   hirda->gState  = HAL_IRDA_STATE_READY;
02700   hirda->RxState = HAL_IRDA_STATE_READY;
02701
02702   /* Call user Abort complete callback */
02703 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02704   /* Call registered Abort complete callback */
02705   hirda->AbortCpltCallback(hirda);
02706 #else
02707   /* Call legacy weak Abort complete callback */
02708   HAL_IRDA_AbortCpltCallback(hirda);
02709 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02710 }
02711
02712
02713 /**
02714   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02715   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02716   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02717   *         and leads to user Tx Abort Complete callback execution).
02718   * @param  hdma DMA handle.
02719   * @retval None
02720   */
02721 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02722 {
02723   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02724
02725   hirda->TxXferCount = 0U;
02726
02727   /* Restore hirda->gState to Ready */
02728   hirda->gState = HAL_IRDA_STATE_READY;
02729
02730   /* Call user Abort complete callback */
02731 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02732   /* Call registered Abort Transmit Complete Callback */
02733   hirda->AbortTransmitCpltCallback(hirda);
02734 #else
02735   /* Call legacy weak Abort Transmit Complete Callback */
02736   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02737 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02738 }
02739
02740 /**
02741   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02742   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02743   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02744   *         and leads to user Rx Abort Complete callback execution).
02745   * @param  hdma DMA handle.
02746   * @retval None
02747   */
02748 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02749 {
02750   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02751
02752   hirda->RxXferCount = 0U;
02753
02754   /* Clear the Error flags in the ICR register */
02755   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02756
02757   /* Restore hirda->RxState to Ready */
02758   hirda->RxState = HAL_IRDA_STATE_READY;
02759
02760   /* Call user Abort complete callback */
02761 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02762   /* Call registered Abort Receive Complete Callback */
02763   hirda->AbortReceiveCpltCallback(hirda);
02764 #else
02765   /* Call legacy weak Abort Receive Complete Callback */
02766   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02767 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02768 }
02769
02770 /**
02771   * @brief  Send an amount of data in interrupt mode.
02772   * @note   Function is called under interruption only, once
02773   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02774   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02775   *               the configuration information for the specified IRDA module.
02776   * @retval None
02777   */
02778 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02779 {
02780   const uint16_t *tmp;
02781
02782   /* Check that a Tx process is ongoing */
02783   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02784   {
02785     if (hirda->TxXferCount == 0U)
02786     {
02787       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02788       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02789
02790       /* Enable the IRDA Transmit Complete Interrupt */
02791       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02792     }
02793     else
02794     {
02795       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02796       {
02797         tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
02798         hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
02799         hirda->pTxBuffPtr += 2U;
02800       }
02801       else
02802       {
02803         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
02804         hirda->pTxBuffPtr++;
02805       }
02806       hirda->TxXferCount--;
02807     }
02808   }
02809 }
02810
02811 /**
02812   * @brief  Wrap up transmission in non-blocking mode.
02813   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02814   *               the configuration information for the specified IRDA module.
02815   * @retval None
02816   */
02817 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02818 {
02819   /* Disable the IRDA Transmit Complete Interrupt */
02820   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02821
02822   /* Tx process is ended, restore hirda->gState to Ready */
02823   hirda->gState = HAL_IRDA_STATE_READY;
02824
02825 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02826   /* Call registered Tx complete callback */
02827   hirda->TxCpltCallback(hirda);
02828 #else
02829   /* Call legacy weak Tx complete callback */
02830   HAL_IRDA_TxCpltCallback(hirda);
02831 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02832 }
02833
02834 /**
02835   * @brief  Receive an amount of data in interrupt mode.
02836   * @note   Function is called under interruption only, once
02837   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
02838   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02839   *               the configuration information for the specified IRDA module.
02840   * @retval None
02841   */
02842 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02843 {
02844   uint16_t *tmp;
02845   uint16_t  uhMask = hirda->Mask;
02846   uint16_t  uhdata;
02847
02848   /* Check that a Rx process is ongoing */
02849   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02850   {
02851     uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
02852     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02853     {
02854       tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
02855       *tmp = (uint16_t)(uhdata & uhMask);
02856       hirda->pRxBuffPtr  += 2U;
02857     }
02858     else
02859     {
02860       *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
02861       hirda->pRxBuffPtr++;
02862     }
02863
02864     hirda->RxXferCount--;
02865     if (hirda->RxXferCount == 0U)
02866     {
02867       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02868       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02869
02870       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02871       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02872
02873       /* Rx process is completed, restore hirda->RxState to Ready */
02874       hirda->RxState = HAL_IRDA_STATE_READY;
02875
02876 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02877       /* Call registered Rx complete callback */
02878       hirda->RxCpltCallback(hirda);
02879 #else
02880       /* Call legacy weak Rx complete callback */
02881       HAL_IRDA_RxCpltCallback(hirda);
02882 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02883     }
02884   }
02885   else
02886   {
02887     /* Clear RXNE interrupt flag */
02888     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02889   }
02890 }
02891
02892 /**
02893   * @}
02894   */
02895
02896 #endif /* HAL_IRDA_MODULE_ENABLED */
02897 /**
02898   * @}
02899   */
02900
02901 /**
02902   * @}
02903   */
02904
02905
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_irda.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_IRDA_H
00021 #define STM32G4xx_HAL_IRDA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup IRDA
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief IRDA Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00049                                            The baud rate register is computed using the following formula:
00050                                               Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
00051                                            where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
00052
00053   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00054                                            This parameter can be a value of @ref IRDAEx_Word_Length */
00055
00056   uint32_t Parity;                    /*!< Specifies the parity mode.
00057                                            This parameter can be a value of @ref IRDA_Parity
00058                                            @note When parity is enabled, the computed parity is inserted
00059                                                  at the MSB position of the transmitted data (9th bit when
00060                                                  the word length is set to 9 data bits; 8th bit when the
00061                                                  word length is set to 8 data bits). */
00062
00063   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00064                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00065
00066   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00067                                            to achieve low-power frequency.
00068                                            @note Prescaler value 0 is forbidden */
00069
00070   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00071                                            This parameter can be a value of @ref IRDA_Low_Power */
00072
00073   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
00074                                            This parameter can be a value of @ref IRDA_ClockPrescaler. */
00075
00076 } IRDA_InitTypeDef;
00077
00078 /**
00079   * @brief HAL IRDA State definition
00080   * @note  HAL IRDA State value is a combination of 2 different substates:
00081   *        gState and RxState (see @ref IRDA_State_Definition).
00082   *        - gState contains IRDA state information related to global Handle management
00083   *          and also information related to Tx operations.
00084   *          gState value coding follow below described bitmap :
00085   *          b7-b6  Error information
00086   *             00 : No Error
00087   *             01 : (Not Used)
00088   *             10 : Timeout
00089   *             11 : Error
00090   *          b5     Peripheral initialization status
00091   *             0  : Reset (Peripheral not initialized)
00092   *             1  : Init done (Peripheral initialized. HAL IRDA Init function already called)
00093   *          b4-b3  (not used)
00094   *             xx : Should be set to 00
00095   *          b2     Intrinsic process state
00096   *             0  : Ready
00097   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00098   *          b1     (not used)
00099   *             x  : Should be set to 0
00100   *          b0     Tx state
00101   *             0  : Ready (no Tx operation ongoing)
00102   *             1  : Busy (Tx operation ongoing)
00103   *        - RxState contains information related to Rx operations.
00104   *          RxState value coding follow below described bitmap :
00105   *          b7-b6  (not used)
00106   *             xx : Should be set to 00
00107   *          b5     Peripheral initialization status
00108   *             0  : Reset (Peripheral not initialized)
00109   *             1  : Init done (Peripheral initialized)
00110   *          b4-b2  (not used)
00111   *            xxx : Should be set to 000
00112   *          b1     Rx state
00113   *             0  : Ready (no Rx operation ongoing)
00114   *             1  : Busy (Rx operation ongoing)
00115   *          b0     (not used)
00116   *             x  : Should be set to 0.
00117   */
00118 typedef uint32_t HAL_IRDA_StateTypeDef;
00119
00120 /**
00121   * @brief IRDA clock sources definition
00122   */
00123 typedef enum
00124 {
00125   IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source         */
00126   IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source         */
00127   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
00128   IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source        */
00129   IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
00130   IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
00131 } IRDA_ClockSourceTypeDef;
00132
00133 /**
00134   * @brief  IRDA handle Structure definition
00135   */
00136 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00137 typedef struct __IRDA_HandleTypeDef
00138 #else
00139 typedef struct
00140 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00141 {
00142   USART_TypeDef            *Instance;        /*!< USART registers base address       */
00143
00144   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00145
00146   const uint8_t            *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00147
00148   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00149
00150   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00151
00152   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00153
00154   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00155
00156   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00157
00158   uint16_t                 Mask;             /*!< USART RX RDR register mask         */
00159
00160   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00161
00162   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00163
00164   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00165
00166   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00167                                                   and also related to Tx operations.
00168                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00169
00170   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00171                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00172
00173   __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
00174
00175 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00176   void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
00177
00178   void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
00179
00180   void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
00181
00182   void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
00183
00184   void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
00185
00186   void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
00187
00188   void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
00189
00190   void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
00191
00192
00193   void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
00194
00195   void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
00196 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00197
00198 } IRDA_HandleTypeDef;
00199
00200 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00201 /**
00202   * @brief  HAL IRDA Callback ID enumeration definition
00203   */
00204 typedef enum
00205 {
00206   HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
00207   HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
00208   HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
00209   HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
00210   HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
00211   HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
00212   HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
00213   HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
00214
00215   HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
00216   HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
00217
00218 } HAL_IRDA_CallbackIDTypeDef;
00219
00220 /**
00221   * @brief  HAL IRDA Callback pointer definition
00222   */
00223 typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
00224
00225 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported constants --------------------------------------------------------*/
00232 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00233   * @{
00234   */
00235
00236 /** @defgroup IRDA_State_Definition IRDA State Code Definition
00237   * @{
00238   */
00239 #define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
00240                                                                Value is allowed for gState and RxState */
00241 #define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
00242                                                                Value is allowed for gState and RxState */
00243 #define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
00244                                                                Value is allowed for gState only */
00245 #define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
00246                                                                Value is allowed for gState only */
00247 #define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
00248                                                                Value is allowed for RxState only */
00249 #define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
00250                                                                Not to be used for neither gState nor RxState.
00251                                                                Value is result of combination (Or) between
00252                                                                gState and RxState values */
00253 #define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
00254                                                                Value is allowed for gState only */
00255 #define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
00256                                                                Value is allowed for gState only */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup IRDA_Error_Definition IRDA Error Code Definition
00262   * @{
00263   */
00264 #define HAL_IRDA_ERROR_NONE                 (0x00000000U)          /*!< No error                */
00265 #define HAL_IRDA_ERROR_PE                   (0x00000001U)          /*!< Parity error            */
00266 #define HAL_IRDA_ERROR_NE                   (0x00000002U)          /*!< Noise error             */
00267 #define HAL_IRDA_ERROR_FE                   (0x00000004U)          /*!< frame error             */
00268 #define HAL_IRDA_ERROR_ORE                  (0x00000008U)          /*!< Overrun error           */
00269 #define HAL_IRDA_ERROR_DMA                  (0x00000010U)          /*!< DMA transfer error      */
00270 #define HAL_IRDA_ERROR_BUSY                 (0x00000020U)          /*!< Busy Error              */
00271 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00272 #define HAL_IRDA_ERROR_INVALID_CALLBACK     (0x00000040U)          /*!< Invalid Callback error  */
00273 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup IRDA_Parity IRDA Parity
00279   * @{
00280   */
00281 #define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
00282 #define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
00283 #define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00289   * @{
00290   */
00291 #define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
00292 #define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
00293 #define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup IRDA_Low_Power IRDA Low Power
00299   * @{
00300   */
00301 #define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
00302 #define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
00308   * @{
00309   */
00310 #define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00311 #define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00312 #define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00313 #define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00314 #define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00315 #define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00316 #define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00317 #define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00318 #define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00319 #define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00320 #define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00321 #define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup IRDA_State IRDA State
00327   * @{
00328   */
00329 #define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
00330 #define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup IRDA_Mode IRDA Mode
00336   * @{
00337   */
00338 #define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
00339 #define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup IRDA_One_Bit IRDA One Bit Sampling
00345   * @{
00346   */
00347 #define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
00348 #define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00354   * @{
00355   */
00356 #define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
00357 #define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
00363   * @{
00364   */
00365 #define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
00366 #define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00372   * @{
00373   */
00374 #define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00375 #define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00376 #define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup IRDA_Flags IRDA Flags
00382   *        Elements values convention: 0xXXXX
00383   *           - 0xXXXX  : Flag mask in the ISR register
00384   * @{
00385   */
00386 #define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
00387 #define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
00388 #define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
00389 #define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
00390 #define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
00391 #define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
00392 #define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
00393 #define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
00394 #define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
00395 #define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
00396 #define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
00397 #define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00403   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00404   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00405   *           - XX  : Interrupt source register (2bits)
00406   *                 - 01: CR1 register
00407   *                 - 10: CR2 register
00408   *                 - 11: CR3 register
00409   *           - ZZZZ  : Flag position in the ISR register(4bits)
00410   * @{
00411   */
00412 #define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
00413 #define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
00414 #define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
00415 #define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
00416 #define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
00417
00418 /*       Elements values convention: 000000000XXYYYYYb
00419              - YYYYY  : Interrupt source position in the XX register (5bits)
00420              - XX  : Interrupt source register (2bits)
00421                    - 01: CR1 register
00422                    - 10: CR2 register
00423                    - 11: CR3 register */
00424 #define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
00425
00426 /*       Elements values convention: 0000ZZZZ00000000b
00427              - ZZZZ  : Flag position in the ISR register(4bits) */
00428 #define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
00429 #define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
00430 #define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
00436   * @{
00437   */
00438 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00439 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00440 #define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
00441 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00442 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00443 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
00449   * @{
00450   */
00451 #define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
00452 #define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
00453 #define IRDA_CR_POS   5U       /*!< IRDA control register position */
00454 #define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
00455 #define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
00456 /**
00457   * @}
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /* Exported macros -----------------------------------------------------------*/
00465 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00466   * @{
00467   */
00468
00469 /** @brief  Reset IRDA handle state.
00470   * @param  __HANDLE__ IRDA handle.
00471   * @retval None
00472   */
00473 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00474 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00475                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00476                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00477                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00478                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00479                                                      } while(0U)
00480 #else
00481 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00482                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00483                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00484                                                      } while(0U)
00485 #endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
00486
00487 /** @brief  Flush the IRDA DR register.
00488   * @param  __HANDLE__ specifies the IRDA Handle.
00489   * @retval None
00490   */
00491 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00492   do{                                                                    \
00493     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00494     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00495   } while(0U)
00496
00497 /** @brief  Clear the specified IRDA pending flag.
00498   * @param  __HANDLE__ specifies the IRDA Handle.
00499   * @param  __FLAG__ specifies the flag to check.
00500   *          This parameter can be any combination of the following values:
00501   *            @arg @ref IRDA_CLEAR_PEF
00502   *            @arg @ref IRDA_CLEAR_FEF
00503   *            @arg @ref IRDA_CLEAR_NEF
00504   *            @arg @ref IRDA_CLEAR_OREF
00505   *            @arg @ref IRDA_CLEAR_TCF
00506   *            @arg @ref IRDA_CLEAR_IDLEF
00507   * @retval None
00508   */
00509 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00510
00511 /** @brief  Clear the IRDA PE pending flag.
00512   * @param  __HANDLE__ specifies the IRDA Handle.
00513   * @retval None
00514   */
00515 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00516
00517
00518 /** @brief  Clear the IRDA FE pending flag.
00519   * @param  __HANDLE__ specifies the IRDA Handle.
00520   * @retval None
00521   */
00522 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00523
00524 /** @brief  Clear the IRDA NE pending flag.
00525   * @param  __HANDLE__ specifies the IRDA Handle.
00526   * @retval None
00527   */
00528 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00529
00530 /** @brief  Clear the IRDA ORE pending flag.
00531   * @param  __HANDLE__ specifies the IRDA Handle.
00532   * @retval None
00533   */
00534 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00535
00536 /** @brief  Clear the IRDA IDLE pending flag.
00537   * @param  __HANDLE__ specifies the IRDA Handle.
00538   * @retval None
00539   */
00540 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00541
00542 /** @brief  Check whether the specified IRDA flag is set or not.
00543   * @param  __HANDLE__ specifies the IRDA Handle.
00544   * @param  __FLAG__ specifies the flag to check.
00545   *        This parameter can be one of the following values:
00546   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00547   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00548   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00549   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00550   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00551   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00552   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00553   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00554   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00555   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00556   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00557   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00558   * @retval The new state of __FLAG__ (TRUE or FALSE).
00559   */
00560 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00561
00562
00563 /** @brief  Enable the specified IRDA interrupt.
00564   * @param  __HANDLE__ specifies the IRDA Handle.
00565   * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
00566   *          This parameter can be one of the following values:
00567   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00568   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00569   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00570   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00571   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00572   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00573   * @retval None
00574   */
00575 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
00576                                                            ((__HANDLE__)->Instance->CR1 |= (1U << \
00577                                                                ((__INTERRUPT__) & IRDA_IT_MASK))):\
00578                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
00579                                                            ((__HANDLE__)->Instance->CR2 |= (1U << \
00580                                                                ((__INTERRUPT__) & IRDA_IT_MASK))):\
00581                                                            ((__HANDLE__)->Instance->CR3 |= (1U << \
00582                                                                ((__INTERRUPT__) & IRDA_IT_MASK))))
00583
00584 /** @brief  Disable the specified IRDA interrupt.
00585   * @param  __HANDLE__ specifies the IRDA Handle.
00586   * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
00587   *          This parameter can be one of the following values:
00588   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00589   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00590   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00591   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00592   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00593   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00594   * @retval None
00595   */
00596 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
00597                                                            ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
00598                                                                ((__INTERRUPT__) & IRDA_IT_MASK))): \
00599                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
00600                                                            ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
00601                                                                ((__INTERRUPT__) & IRDA_IT_MASK))): \
00602                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
00603                                                                ((__INTERRUPT__) & IRDA_IT_MASK))))
00604
00605 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00606   * @param  __HANDLE__ specifies the IRDA Handle.
00607   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00608   *          This parameter can be one of the following values:
00609   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00610   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00611   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00612   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00613   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00614   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00615   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00616   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00617   * @retval The new state of __IT__ (SET or RESET).
00618   */
00619 #define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
00620   ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
00621
00622 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00623   * @param  __HANDLE__ specifies the IRDA Handle.
00624   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00625   *          This parameter can be one of the following values:
00626   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00627   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00628   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00629   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00630   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00631   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00632   * @retval The new state of __IT__ (SET or RESET).
00633   */
00634 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                                                          \
00635   ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
00636       & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
00637      & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
00638
00639 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00640   * @param  __HANDLE__ specifies the IRDA Handle.
00641   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00642   *                       to clear the corresponding interrupt
00643   *          This parameter can be one of the following values:
00644   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00645   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00646   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00647   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00648   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00649   * @retval None
00650   */
00651 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00652
00653
00654 /** @brief  Set a specific IRDA request flag.
00655   * @param  __HANDLE__ specifies the IRDA Handle.
00656   * @param  __REQ__ specifies the request flag to set
00657   *          This parameter can be one of the following values:
00658   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00659   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00660   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00661   * @retval None
00662   */
00663 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00664
00665 /** @brief  Enable the IRDA one bit sample method.
00666   * @param  __HANDLE__ specifies the IRDA Handle.
00667   * @retval None
00668   */
00669 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00670
00671 /** @brief  Disable the IRDA one bit sample method.
00672   * @param  __HANDLE__ specifies the IRDA Handle.
00673   * @retval None
00674   */
00675 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00676                                                        &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00677
00678 /** @brief  Enable UART/USART associated to IRDA Handle.
00679   * @param  __HANDLE__ specifies the IRDA Handle.
00680   * @retval None
00681   */
00682 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00683
00684 /** @brief  Disable UART/USART associated to IRDA Handle.
00685   * @param  __HANDLE__ specifies the IRDA Handle.
00686   * @retval None
00687   */
00688 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00689
00690 /**
00691   * @}
00692   */
00693
00694 /* Private macros --------------------------------------------------------*/
00695 /** @addtogroup IRDA_Private_Macros
00696   * @{
00697   */
00698
00699 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00700   * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
00701   * @retval True or False
00702   */
00703 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
00704
00705 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00706   * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
00707   * @retval True or False
00708   */
00709 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
00710
00711 /** @brief Ensure that IRDA frame parity is valid.
00712   * @param __PARITY__ IRDA frame parity.
00713   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00714   */
00715 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00716                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00717                                     ((__PARITY__) == IRDA_PARITY_ODD))
00718
00719 /** @brief Ensure that IRDA communication mode is valid.
00720   * @param __MODE__ IRDA communication mode.
00721   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00722   */
00723 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
00724                                         & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
00725
00726 /** @brief Ensure that IRDA power mode is valid.
00727   * @param __MODE__ IRDA power mode.
00728   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00729   */
00730 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00731                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00732
00733 /** @brief Ensure that IRDA clock Prescaler is valid.
00734   * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
00735   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00736   */
00737 #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
00738                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
00739                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
00740                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
00741                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
00742                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
00743                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
00744                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
00745                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
00746                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
00747                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
00748                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
00749
00750 /** @brief Ensure that IRDA state is valid.
00751   * @param __STATE__ IRDA state mode.
00752   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00753   */
00754 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00755                                   ((__STATE__) == IRDA_STATE_ENABLE))
00756
00757 /** @brief Ensure that IRDA associated UART/USART mode is valid.
00758   * @param __MODE__ IRDA associated UART/USART mode.
00759   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00760   */
00761 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00762                                  ((__MODE__) == IRDA_MODE_ENABLE))
00763
00764 /** @brief Ensure that IRDA sampling rate is valid.
00765   * @param __ONEBIT__ IRDA sampling rate.
00766   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00767   */
00768 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00769                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00770
00771 /** @brief Ensure that IRDA DMA TX mode is valid.
00772   * @param __DMATX__ IRDA DMA TX mode.
00773   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00774   */
00775 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00776                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00777
00778 /** @brief Ensure that IRDA DMA RX mode is valid.
00779   * @param __DMARX__ IRDA DMA RX mode.
00780   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00781   */
00782 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00783                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00784
00785 /** @brief Ensure that IRDA request is valid.
00786   * @param __PARAM__ IRDA request.
00787   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00788   */
00789 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00790                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00791                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00792 /**
00793   * @}
00794   */
00795
00796 /* Include IRDA HAL Extended module */
00797 #include "stm32g4xx_hal_irda_ex.h"
00798
00799 /* Exported functions --------------------------------------------------------*/
00800 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00801   * @{
00802   */
00803
00804 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00805   * @{
00806   */
00807
00808 /* Initialization and de-initialization functions  ****************************/
00809 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00810 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00811 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00812 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00813
00814 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00815 /* Callbacks Register/UnRegister functions  ***********************************/
00816 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00817                                             pIRDA_CallbackTypeDef pCallback);
00818 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
00819 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00820
00821 /**
00822   * @}
00823   */
00824
00825 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00826   * @{
00827   */
00828
00829 /* IO operation functions *****************************************************/
00830 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
00831 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00832 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
00833 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00834 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
00835 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00836 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00837 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00838 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00839 /* Transfer Abort functions */
00840 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00841 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00842 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00843 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00844 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00845 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00846
00847 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00848 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00849 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00850 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00851 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00852 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00853 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
00854 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
00855 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
00856
00857 /**
00858   * @}
00859   */
00860
00861 /* Peripheral Control functions  ************************************************/
00862
00863 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00864   * @{
00865   */
00866
00867 /* Peripheral State and Error functions ***************************************/
00868 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
00869 uint32_t              HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
00870
00871 /**
00872   * @}
00873   */
00874
00875 /**
00876   * @}
00877   */
00878
00879 /**
00880   * @}
00881   */
00882
00883 /**
00884   * @}
00885   */
00886
00887 #ifdef __cplusplus
00888 }
00889 #endif
00890
00891 #endif /* STM32G4xx_HAL_IRDA_H */
00892
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_irda_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_irda_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_IRDA_EX_H
00021 #define STM32G4xx_HAL_IRDA_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup IRDAEx IRDAEx
00035   * @brief IRDA Extended HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup IRDAEx_Word_Length IRDAEx Word Length
00046   * @{
00047   */
00048 #define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
00049 #define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
00050 #define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
00051 /**
00052   * @}
00053   */
00054
00055 /**
00056   * @}
00057   */
00058
00059 /* Exported macros -----------------------------------------------------------*/
00060
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00064   * @{
00065   */
00066
00067 /** @brief  Report the IRDA clock source.
00068   * @param  __HANDLE__ specifies the IRDA Handle.
00069   * @param  __CLOCKSOURCE__ output variable.
00070   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00071   */
00072 #if defined(UART5)
00073 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)        \
00074   do {                                                         \
00075     if((__HANDLE__)->Instance == USART1)                       \
00076     {                                                          \
00077       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00078       {                                                        \
00079         case RCC_USART1CLKSOURCE_PCLK2:                        \
00080           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
00081           break;                                               \
00082         case RCC_USART1CLKSOURCE_HSI:                          \
00083           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00084           break;                                               \
00085         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00086           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00087           break;                                               \
00088         case RCC_USART1CLKSOURCE_LSE:                          \
00089           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00090           break;                                               \
00091         default:                                               \
00092           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00093           break;                                               \
00094       }                                                        \
00095     }                                                          \
00096     else if((__HANDLE__)->Instance == USART2)                  \
00097     {                                                          \
00098       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00099       {                                                        \
00100         case RCC_USART2CLKSOURCE_PCLK1:                        \
00101           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00102           break;                                               \
00103         case RCC_USART2CLKSOURCE_HSI:                          \
00104           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00105           break;                                               \
00106         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00107           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00108           break;                                               \
00109         case RCC_USART2CLKSOURCE_LSE:                          \
00110           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00111           break;                                               \
00112         default:                                               \
00113           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00114           break;                                               \
00115       }                                                        \
00116     }                                                          \
00117     else if((__HANDLE__)->Instance == USART3)                  \
00118     {                                                          \
00119       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00120       {                                                        \
00121         case RCC_USART3CLKSOURCE_PCLK1:                        \
00122           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00123           break;                                               \
00124         case RCC_USART3CLKSOURCE_HSI:                          \
00125           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00126           break;                                               \
00127         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00128           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00129           break;                                               \
00130         case RCC_USART3CLKSOURCE_LSE:                          \
00131           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00132           break;                                               \
00133         default:                                               \
00134           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00135           break;                                               \
00136       }                                                        \
00137     }                                                          \
00138     else if((__HANDLE__)->Instance == UART4)                   \
00139     {                                                          \
00140       switch(__HAL_RCC_GET_UART4_SOURCE())                     \
00141       {                                                        \
00142         case RCC_UART4CLKSOURCE_PCLK1:                         \
00143           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00144           break;                                               \
00145         case RCC_UART4CLKSOURCE_HSI:                           \
00146           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00147           break;                                               \
00148         case RCC_UART4CLKSOURCE_SYSCLK:                        \
00149           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00150           break;                                               \
00151         case RCC_UART4CLKSOURCE_LSE:                           \
00152           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00153           break;                                               \
00154         default:                                               \
00155           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00156           break;                                               \
00157       }                                                        \
00158     }                                                          \
00159     else if((__HANDLE__)->Instance == UART5)                   \
00160     {                                                          \
00161       switch(__HAL_RCC_GET_UART5_SOURCE())                     \
00162       {                                                        \
00163         case RCC_UART5CLKSOURCE_PCLK1:                         \
00164           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00165           break;                                               \
00166         case RCC_UART5CLKSOURCE_HSI:                           \
00167           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00168           break;                                               \
00169         case RCC_UART5CLKSOURCE_SYSCLK:                        \
00170           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00171           break;                                               \
00172         case RCC_UART5CLKSOURCE_LSE:                           \
00173           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00174           break;                                               \
00175         default:                                               \
00176           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00177           break;                                               \
00178       }                                                        \
00179     }                                                          \
00180     else                                                       \
00181     {                                                          \
00182       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;          \
00183     }                                                          \
00184   } while(0U)
00185 #elif defined(UART4)
00186 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)        \
00187   do {                                                         \
00188     if((__HANDLE__)->Instance == USART1)                       \
00189     {                                                          \
00190       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00191       {                                                        \
00192         case RCC_USART1CLKSOURCE_PCLK2:                        \
00193           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
00194           break;                                               \
00195         case RCC_USART1CLKSOURCE_HSI:                          \
00196           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00197           break;                                               \
00198         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00199           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00200           break;                                               \
00201         case RCC_USART1CLKSOURCE_LSE:                          \
00202           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00203           break;                                               \
00204         default:                                               \
00205           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00206           break;                                               \
00207       }                                                        \
00208     }                                                          \
00209     else if((__HANDLE__)->Instance == USART2)                  \
00210     {                                                          \
00211       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00212       {                                                        \
00213         case RCC_USART2CLKSOURCE_PCLK1:                        \
00214           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00215           break;                                               \
00216         case RCC_USART2CLKSOURCE_HSI:                          \
00217           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00218           break;                                               \
00219         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00220           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00221           break;                                               \
00222         case RCC_USART2CLKSOURCE_LSE:                          \
00223           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00224           break;                                               \
00225         default:                                               \
00226           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00227           break;                                               \
00228       }                                                        \
00229     }                                                          \
00230     else if((__HANDLE__)->Instance == USART3)                  \
00231     {                                                          \
00232       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00233       {                                                        \
00234         case RCC_USART3CLKSOURCE_PCLK1:                        \
00235           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00236           break;                                               \
00237         case RCC_USART3CLKSOURCE_HSI:                          \
00238           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00239           break;                                               \
00240         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00241           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00242           break;                                               \
00243         case RCC_USART3CLKSOURCE_LSE:                          \
00244           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00245           break;                                               \
00246         default:                                               \
00247           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00248           break;                                               \
00249       }                                                        \
00250     }                                                          \
00251     else if((__HANDLE__)->Instance == UART4)                   \
00252     {                                                          \
00253       switch(__HAL_RCC_GET_UART4_SOURCE())                     \
00254       {                                                        \
00255         case RCC_UART4CLKSOURCE_PCLK1:                         \
00256           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00257           break;                                               \
00258         case RCC_UART4CLKSOURCE_HSI:                           \
00259           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00260           break;                                               \
00261         case RCC_UART4CLKSOURCE_SYSCLK:                        \
00262           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00263           break;                                               \
00264         case RCC_UART4CLKSOURCE_LSE:                           \
00265           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00266           break;                                               \
00267         default:                                               \
00268           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00269           break;                                               \
00270       }                                                        \
00271     }                                                          \
00272     else                                                       \
00273     {                                                          \
00274       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;          \
00275     }                                                          \
00276   } while(0U)
00277 #else
00278 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)        \
00279   do {                                                         \
00280     if((__HANDLE__)->Instance == USART1)                       \
00281     {                                                          \
00282       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00283       {                                                        \
00284         case RCC_USART1CLKSOURCE_PCLK2:                        \
00285           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
00286           break;                                               \
00287         case RCC_USART1CLKSOURCE_HSI:                          \
00288           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00289           break;                                               \
00290         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00291           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00292           break;                                               \
00293         case RCC_USART1CLKSOURCE_LSE:                          \
00294           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00295           break;                                               \
00296         default:                                               \
00297           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00298           break;                                               \
00299       }                                                        \
00300     }                                                          \
00301     else if((__HANDLE__)->Instance == USART2)                  \
00302     {                                                          \
00303       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00304       {                                                        \
00305         case RCC_USART2CLKSOURCE_PCLK1:                        \
00306           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00307           break;                                               \
00308         case RCC_USART2CLKSOURCE_HSI:                          \
00309           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00310           break;                                               \
00311         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00312           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00313           break;                                               \
00314         case RCC_USART2CLKSOURCE_LSE:                          \
00315           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00316           break;                                               \
00317         default:                                               \
00318           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00319           break;                                               \
00320       }                                                        \
00321     }                                                          \
00322     else if((__HANDLE__)->Instance == USART3)                  \
00323     {                                                          \
00324       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00325       {                                                        \
00326         case RCC_USART3CLKSOURCE_PCLK1:                        \
00327           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
00328           break;                                               \
00329         case RCC_USART3CLKSOURCE_HSI:                          \
00330           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00331           break;                                               \
00332         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00333           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00334           break;                                               \
00335         case RCC_USART3CLKSOURCE_LSE:                          \
00336           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00337           break;                                               \
00338         default:                                               \
00339           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00340           break;                                               \
00341       }                                                        \
00342     }                                                          \
00343     else                                                       \
00344     {                                                          \
00345       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;          \
00346     }                                                          \
00347   } while(0U)
00348 #endif /* UART5 */
00349
00350 /** @brief  Compute the mask to apply to retrieve the received data
00351   *         according to the word length and to the parity bits activation.
00352   * @param  __HANDLE__ specifies the IRDA Handle.
00353   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00354   */
00355 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00356   do {                                                                \
00357     if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
00358     {                                                                 \
00359       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00360       {                                                               \
00361         (__HANDLE__)->Mask = 0x01FFU ;                                \
00362       }                                                               \
00363       else                                                            \
00364       {                                                               \
00365         (__HANDLE__)->Mask = 0x00FFU ;                                \
00366       }                                                               \
00367     }                                                                 \
00368     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
00369     {                                                                 \
00370       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00371       {                                                               \
00372         (__HANDLE__)->Mask = 0x00FFU ;                                \
00373       }                                                               \
00374       else                                                            \
00375       {                                                               \
00376         (__HANDLE__)->Mask = 0x007FU ;                                \
00377       }                                                               \
00378     }                                                                 \
00379     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
00380     {                                                                 \
00381       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00382       {                                                               \
00383         (__HANDLE__)->Mask = 0x007FU ;                                \
00384       }                                                               \
00385       else                                                            \
00386       {                                                               \
00387         (__HANDLE__)->Mask = 0x003FU ;                                \
00388       }                                                               \
00389     }                                                                 \
00390     else                                                              \
00391     {                                                                 \
00392       (__HANDLE__)->Mask = 0x0000U;                                   \
00393     }                                                                 \
00394   } while(0U)
00395
00396 /** @brief Ensure that IRDA frame length is valid.
00397   * @param __LENGTH__ IRDA frame length.
00398   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00399   */
00400 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00401                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00402                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00403 /**
00404   * @}
00405   */
00406
00407 /* Exported functions --------------------------------------------------------*/
00408
00409 /**
00410   * @}
00411   */
00412
00413 /**
00414   * @}
00415   */
00416
00417 #ifdef __cplusplus
00418 }
00419 #endif
00420
00421 #endif /* STM32G4xx_HAL_IRDA_EX_H */
00422
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_iwdg.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @brief   IWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00008   *           + Initialization and Start functions
00009   *           + IO operation functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                     ##### IWDG Generic features #####
00025   ==============================================================================
00026   [..]
00027     (+) The IWDG can be started by either software or hardware (configurable
00028         through option byte).
00029
00030     (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
00031         active even if the main clock fails.
00032
00033     (+) Once the IWDG is started, the LSI is forced ON and both cannot be
00034         disabled. The counter starts counting down from the reset value (0xFFF).
00035         When it reaches the end of count value (0x000) a reset signal is
00036         generated (IWDG reset).
00037
00038     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00039         the IWDG_RLR value is reloaded into the counter and the watchdog reset
00040         is prevented.
00041
00042     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00043         in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
00044         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00045         reset occurs.
00046
00047     (+) Debug mode: When the microcontroller enters debug mode (core halted),
00048         the IWDG counter either continues to work normally or stops, depending
00049         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00050         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
00051
00052     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00053          The IWDG timeout may vary due to LSI clock frequency dispersion.
00054          STM32G4xx devices provide the capability to measure the LSI clock
00055          frequency (LSI clock is internally connected to TIM16 CH1 input capture).
00056          The measured value can be used to have an IWDG timeout with an
00057          acceptable accuracy.
00058
00059     [..] Default timeout value (necessary for IWDG_SR status register update):
00060          Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
00061          This frequency being subject to variations as mentioned above, the
00062          default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
00063          below) may become too short or too long.
00064          In such cases, this default timeout value can be tuned by redefining
00065          the constant LSI_VALUE at user-application level (based, for instance,
00066          on the measured LSI clock frequency as explained above).
00067
00068                      ##### How to use this driver #####
00069   ==============================================================================
00070   [..]
00071     (#) Use IWDG using HAL_IWDG_Init() function to :
00072       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00073            clock is forced ON and IWDG counter starts counting down.
00074       (++) Enable write access to configuration registers:
00075           IWDG_PR, IWDG_RLR and IWDG_WINR.
00076       (++) Configure the IWDG prescaler and counter reload value. This reload
00077            value will be loaded in the IWDG counter each time the watchdog is
00078            reloaded, then the IWDG will start counting down from this value.
00079       (++) Depending on window parameter:
00080         (+++) If Window Init parameter is same as Window register value,
00081              nothing more is done but reload counter value in order to exit
00082              function with exact time base.
00083         (+++) Else modify Window register. This will automatically reload
00084              watchdog counter.
00085       (++) Wait for status flags to be reset.
00086
00087     (#) Then the application program must refresh the IWDG counter at regular
00088         intervals during normal operation to prevent an MCU reset, using
00089         HAL_IWDG_Refresh() function.
00090
00091      *** IWDG HAL driver macros list ***
00092      ====================================
00093      [..]
00094        Below the list of most used macros in IWDG HAL driver:
00095       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00096       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00097           the reload register
00098
00099   @endverbatim
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32g4xx_hal.h"
00104
00105 /** @addtogroup STM32G4xx_HAL_Driver
00106   * @{
00107   */
00108
00109 #ifdef HAL_IWDG_MODULE_ENABLED
00110 /** @addtogroup IWDG
00111   * @brief IWDG HAL module driver.
00112   * @{
00113   */
00114
00115 /* Private typedef -----------------------------------------------------------*/
00116 /* Private define ------------------------------------------------------------*/
00117 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00118   * @{
00119   */
00120 /* Status register needs up to 5 LSI clock periods divided by the clock
00121    prescaler to be updated. The number of LSI clock periods is upper-rounded to
00122    6 for the timeout value calculation.
00123    The timeout value is calculated using the highest prescaler (256) and
00124    the LSI_VALUE constant. The value of this constant can be changed by the user
00125    to take into account possible LSI clock period variations.
00126    The timeout value is multiplied by 1000 to be converted in milliseconds.
00127    LSI startup time is also considered here by adding LSI_STARTUP_TIME
00128    converted in milliseconds. */
00129 #define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
00130 #define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
00131 /**
00132   * @}
00133   */
00134
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @addtogroup IWDG_Exported_Functions
00141   * @{
00142   */
00143
00144 /** @addtogroup IWDG_Exported_Functions_Group1
00145   *  @brief    Initialization and Start functions.
00146   *
00147 @verbatim
00148  ===============================================================================
00149           ##### Initialization and Start functions #####
00150  ===============================================================================
00151  [..]  This section provides functions allowing to:
00152       (+) Initialize the IWDG according to the specified parameters in the
00153           IWDG_InitTypeDef of associated handle.
00154       (+) Manage Window option.
00155       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00156           is reloaded in order to exit function with correct time base.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initialize the IWDG according to the specified parameters in the
00164   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00165   *         watchdog is refreshed in order to have correct time base.
00166   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00167   *                the configuration information for the specified IWDG module.
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00171 {
00172   uint32_t tickstart;
00173
00174   /* Check the IWDG handle allocation */
00175   if (hiwdg == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179
00180   /* Check the parameters */
00181   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00182   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00183   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00184   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00185
00186   /* Enable IWDG. LSI is turned on automatically */
00187   __HAL_IWDG_START(hiwdg);
00188
00189   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00190   0x5555 in KR */
00191   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00192
00193   /* Write to IWDG registers the Prescaler & Reload values to work with */
00194   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00195   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00196
00197   /* Check pending flag, if previous update not done, return timeout */
00198   tickstart = HAL_GetTick();
00199
00200   /* Wait for register to be updated */
00201   while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
00202   {
00203     if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
00204     {
00205       if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
00206       {
00207         return HAL_TIMEOUT;
00208       }
00209     }
00210   }
00211
00212   /* If window parameter is different than current value, modify window
00213   register */
00214   if (hiwdg->Instance->WINR != hiwdg->Init.Window)
00215   {
00216     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00217     even if window feature is disabled, Watchdog will be reloaded by writing
00218     windows register */
00219     hiwdg->Instance->WINR = hiwdg->Init.Window;
00220   }
00221   else
00222   {
00223     /* Reload IWDG counter with value defined in the reload register */
00224     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00225   }
00226
00227   /* Return function status */
00228   return HAL_OK;
00229 }
00230
00231
00232 /**
00233   * @}
00234   */
00235
00236
00237 /** @addtogroup IWDG_Exported_Functions_Group2
00238   *  @brief   IO operation functions
00239   *
00240 @verbatim
00241  ===============================================================================
00242                       ##### IO operation functions #####
00243  ===============================================================================
00244  [..]  This section provides functions allowing to:
00245       (+) Refresh the IWDG.
00246
00247 @endverbatim
00248   * @{
00249   */
00250
00251 /**
00252   * @brief  Refresh the IWDG.
00253   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00254   *                the configuration information for the specified IWDG module.
00255   * @retval HAL status
00256   */
00257 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00258 {
00259   /* Reload IWDG counter with value defined in the reload register */
00260   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00261
00262   /* Return function status */
00263   return HAL_OK;
00264 }
00265
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 #endif /* HAL_IWDG_MODULE_ENABLED */
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_iwdg.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_IWDG_H
00021 #define STM32G4xx_HAL_IWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup IWDG IWDG
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  IWDG Init structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00049                             This parameter can be a value of @ref IWDG_Prescaler */
00050
00051   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00052                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00053
00054   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00055                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00056
00057 } IWDG_InitTypeDef;
00058
00059 /**
00060   * @brief  IWDG Handle Structure definition
00061   */
00062 typedef struct
00063 {
00064   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00065
00066   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00067 } IWDG_HandleTypeDef;
00068
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Exported constants --------------------------------------------------------*/
00075 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00076   * @{
00077   */
00078
00079 /** @defgroup IWDG_Prescaler IWDG Prescaler
00080   * @{
00081   */
00082 #define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
00083 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
00084 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
00085 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
00086 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
00087 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
00088 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup IWDG_Window_option IWDG Window option
00094   * @{
00095   */
00096 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported macros -----------------------------------------------------------*/
00106 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  Enable the IWDG peripheral.
00112   * @param  __HANDLE__  IWDG handle
00113   * @retval None
00114   */
00115 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00116
00117 /**
00118   * @brief  Reload IWDG counter with value defined in the reload register
00119   *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
00120   * @param  __HANDLE__  IWDG handle
00121   * @retval None
00122   */
00123 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions --------------------------------------------------------*/
00130 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00131   * @{
00132   */
00133
00134 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00135   * @{
00136   */
00137 /* Initialization/Start functions  ********************************************/
00138 HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00144   * @{
00145   */
00146 /* I/O operation functions ****************************************************/
00147 HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /* Private constants ---------------------------------------------------------*/
00157 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  IWDG Key Register BitMask
00163   */
00164 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00165 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00166 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00167 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Private macros ------------------------------------------------------------*/
00174 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00175   * @{
00176   */
00177
00178 /**
00179   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00180   * @param  __HANDLE__  IWDG handle
00181   * @retval None
00182   */
00183 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00184
00185 /**
00186   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00187   * @param  __HANDLE__  IWDG handle
00188   * @retval None
00189   */
00190 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00191
00192 /**
00193   * @brief  Check IWDG prescaler value.
00194   * @param  __PRESCALER__  IWDG prescaler value
00195   * @retval None
00196   */
00197 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00198                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00199                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00200                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00201                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00202                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00203                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00204
00205 /**
00206   * @brief  Check IWDG reload value.
00207   * @param  __RELOAD__  IWDG reload value
00208   * @retval None
00209   */
00210 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00211
00212 /**
00213   * @brief  Check IWDG window value.
00214   * @param  __WINDOW__  IWDG window value
00215   * @retval None
00216   */
00217 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00218
00219
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231
00232
00233 #ifdef __cplusplus
00234 }
00235 #endif
00236
00237 #endif /* STM32G4xx_HAL_IWDG_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_lptim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_lptim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00008   *           + Initialization and de-initialization functions.
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Reading operation functions.
00012   *           + Peripheral State functions.
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### How to use this driver #####
00028   ==============================================================================
00029     [..]
00030       The LPTIM HAL driver can be used as follows:
00031
00032       (#)Initialize the LPTIM low level resources by implementing the
00033         HAL_LPTIM_MspInit():
00034          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00035          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00036              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00037              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00038              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00039
00040       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00041          configures mainly:
00042          (++) The instance: LPTIM1.
00043          (++) Clock: the counter clock.
00044              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00045                               the internal clock; (APB, LSE or LSI).
00046              (+++) Prescaler: select the clock divider.
00047          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00048                as counter clock source.
00049              (+++) Polarity:   polarity of the active edge for the counter unit
00050                                if the ULPTIM input is selected.
00051              (+++) SampleTime: clock sampling time to configure the clock glitch
00052                                filter.
00053          (++) Trigger: How the counter start.
00054              (+++) Source: trigger can be software or one of the hardware triggers.
00055              (+++) ActiveEdge : only for hardware trigger.
00056              (+++) SampleTime : trigger sampling time to configure the trigger
00057                                 glitch filter.
00058          (++) OutputPolarity : 2 opposite polarities are possible.
00059          (++) UpdateMode: specifies whether the update of the autoreload and
00060               the compare values is done immediately or after the end of current
00061               period.
00062          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00063          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00064               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00065
00066       (#)Six modes are available:
00067
00068          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00069          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00070          mode.
00071
00072          (++) One Pulse Mode: To generate pulse with specified width in response
00073          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00074          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00075
00076          (++) Set once Mode: In this mode, the output changes the level (from
00077          low level to high level if the output polarity is configured high, else
00078          the opposite) when a compare match occurs. To start this mode, call
00079          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00080          interruption mode.
00081
00082          (++) Encoder Mode: To use the encoder interface call
00083          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00084          interruption mode. Only available for LPTIM1 instance.
00085
00086          (++) Time out Mode: an active edge on one selected trigger input rests
00087          the counter. The first trigger event will start the timer, any
00088          successive trigger event will reset the counter and the timer will
00089          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00090          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00091
00092          (++) Counter Mode: counter can be used to count external events on
00093          the LPTIM Input1 or it can be used to count internal clock cycles.
00094          To start this mode, call HAL_LPTIM_Counter_Start() or
00095          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00096
00097
00098       (#) User can stop any process by calling the corresponding API:
00099           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00100           already started in interruption mode.
00101
00102       (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00103
00104     *** Callback registration ***
00105   =============================================
00106   [..]
00107   The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
00108   allows the user to configure dynamically the driver callbacks.
00109   [..]
00110   Use Function HAL_LPTIM_RegisterCallback() to register a callback.
00111   HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00112   the Callback ID and a pointer to the user callback function.
00113   [..]
00114   Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
00115   default weak function.
00116   HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00117   and the Callback ID.
00118   [..]
00119   These functions allow to register/unregister following callbacks:
00120
00121     (+) MspInitCallback         : LPTIM Base Msp Init Callback.
00122     (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
00123     (+) CompareMatchCallback    : Compare match Callback.
00124     (+) AutoReloadMatchCallback : Auto-reload match Callback.
00125     (+) TriggerCallback         : External trigger event detection Callback.
00126     (+) CompareWriteCallback    : Compare register write complete Callback.
00127     (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
00128     (+) DirectionUpCallback     : Up-counting direction change Callback.
00129     (+) DirectionDownCallback   : Down-counting direction change Callback.
00130
00131   [..]
00132   By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
00133   all interrupt callbacks are set to the corresponding weak functions:
00134   examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
00135
00136   [..]
00137   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00138   functionalities in the Init/DeInit only when these callbacks are null
00139   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
00140   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00141
00142   [..]
00143   Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
00144   Exception done MspInit/MspDeInit that can be registered/unregistered
00145   in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
00146   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00147   In that case first register the MspInit/MspDeInit user callbacks
00148   using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
00149
00150   [..]
00151   When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
00152   not defined, the callback registration feature is not available and all callbacks
00153   are set to the corresponding weak functions.
00154
00155   @endverbatim
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32g4xx_hal.h"
00161
00162 /** @addtogroup STM32G4xx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup LPTIM LPTIM
00167   * @brief LPTIM HAL module driver.
00168   * @{
00169   */
00170
00171 #ifdef HAL_LPTIM_MODULE_ENABLED
00172
00173
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @addtogroup LPTIM_Private_Constants
00178   * @{
00179   */
00180 #define TIMEOUT                                     1000UL /* Timeout is 1s */
00181 /**
00182   * @}
00183   */
00184
00185 /* Private macro -------------------------------------------------------------*/
00186 /* Private variables ---------------------------------------------------------*/
00187 /* Private function prototypes -----------------------------------------------*/
00188 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00189 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
00190 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00191 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
00192
00193 /* Exported functions --------------------------------------------------------*/
00194
00195 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00196   * @{
00197   */
00198
00199 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00200   *  @brief    Initialization and Configuration functions.
00201   *
00202 @verbatim
00203   ==============================================================================
00204               ##### Initialization and de-initialization functions #####
00205   ==============================================================================
00206     [..]  This section provides functions allowing to:
00207       (+) Initialize the LPTIM according to the specified parameters in the
00208           LPTIM_InitTypeDef and initialize the associated handle.
00209       (+) DeInitialize the LPTIM peripheral.
00210       (+) Initialize the LPTIM MSP.
00211       (+) DeInitialize the LPTIM MSP.
00212
00213 @endverbatim
00214   * @{
00215   */
00216
00217 /**
00218   * @brief  Initialize the LPTIM according to the specified parameters in the
00219   *         LPTIM_InitTypeDef and initialize the associated handle.
00220   * @param  hlptim LPTIM handle
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00224 {
00225   uint32_t tmpcfgr;
00226
00227   /* Check the LPTIM handle allocation */
00228   if (hlptim == NULL)
00229   {
00230     return HAL_ERROR;
00231   }
00232
00233   /* Check the parameters */
00234   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00235
00236   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00237   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00238   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00239       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00240   {
00241     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00242     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00243   }
00244   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00245   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00246   {
00247     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00248     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00249   }
00250   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00251   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00252   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00253
00254   if (hlptim->State == HAL_LPTIM_STATE_RESET)
00255   {
00256     /* Allocate lock resource and initialize it */
00257     hlptim->Lock = HAL_UNLOCKED;
00258
00259 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00260     /* Reset interrupt callbacks to legacy weak callbacks */
00261     LPTIM_ResetCallback(hlptim);
00262
00263     if (hlptim->MspInitCallback == NULL)
00264     {
00265       hlptim->MspInitCallback = HAL_LPTIM_MspInit;
00266     }
00267
00268     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00269     hlptim->MspInitCallback(hlptim);
00270 #else
00271     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00272     HAL_LPTIM_MspInit(hlptim);
00273 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00274   }
00275
00276   /* Change the LPTIM state */
00277   hlptim->State = HAL_LPTIM_STATE_BUSY;
00278
00279   /* Get the LPTIMx CFGR value */
00280   tmpcfgr = hlptim->Instance->CFGR;
00281
00282   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00283       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00284   {
00285     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00286   }
00287   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00288   {
00289     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00290   }
00291
00292   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00293   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00294                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
00295
00296   /* Set initialization parameters */
00297   tmpcfgr |= (hlptim->Init.Clock.Source    |
00298               hlptim->Init.Clock.Prescaler |
00299               hlptim->Init.OutputPolarity  |
00300               hlptim->Init.UpdateMode      |
00301               hlptim->Init.CounterSource);
00302
00303   /* Glitch filters for internal triggers and  external inputs are configured
00304    * only if an internal clock source is provided to the LPTIM
00305    */
00306   if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
00307   {
00308     tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
00309                 hlptim->Init.UltraLowPowerClock.SampleTime);
00310   }
00311
00312   /* Configure LPTIM external clock polarity and digital filter */
00313   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00314       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00315   {
00316     tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
00317                 hlptim->Init.UltraLowPowerClock.SampleTime);
00318   }
00319
00320   /* Configure LPTIM external trigger */
00321   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00322   {
00323     /* Enable External trigger and set the trigger source */
00324     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00325                 hlptim->Init.Trigger.ActiveEdge |
00326                 hlptim->Init.Trigger.SampleTime);
00327   }
00328
00329   /* Write to LPTIMx CFGR */
00330   hlptim->Instance->CFGR = tmpcfgr;
00331
00332   /* Configure LPTIM input sources */
00333   if (hlptim->Instance == LPTIM1)
00334   {
00335     /* Check LPTIM Input1 and Input2 sources */
00336     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00337     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
00338
00339     /* Configure LPTIM Input1 and Input2 sources */
00340     hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00341   }
00342
00343   /* Change the LPTIM state */
00344   hlptim->State = HAL_LPTIM_STATE_READY;
00345
00346   /* Return function status */
00347   return HAL_OK;
00348 }
00349
00350 /**
00351   * @brief  DeInitialize the LPTIM peripheral.
00352   * @param  hlptim LPTIM handle
00353   * @retval HAL status
00354   */
00355 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00356 {
00357   /* Check the LPTIM handle allocation */
00358   if (hlptim == NULL)
00359   {
00360     return HAL_ERROR;
00361   }
00362
00363   /* Change the LPTIM state */
00364   hlptim->State = HAL_LPTIM_STATE_BUSY;
00365
00366   /* Disable the LPTIM Peripheral Clock */
00367   __HAL_LPTIM_DISABLE(hlptim);
00368
00369   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00370   {
00371     return HAL_TIMEOUT;
00372   }
00373
00374 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00375   if (hlptim->MspDeInitCallback == NULL)
00376   {
00377     hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
00378   }
00379
00380   /* DeInit the low level hardware: CLOCK, NVIC.*/
00381   hlptim->MspDeInitCallback(hlptim);
00382 #else
00383   /* DeInit the low level hardware: CLOCK, NVIC.*/
00384   HAL_LPTIM_MspDeInit(hlptim);
00385 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00386
00387   /* Change the LPTIM state */
00388   hlptim->State = HAL_LPTIM_STATE_RESET;
00389
00390   /* Release Lock */
00391   __HAL_UNLOCK(hlptim);
00392
00393   /* Return function status */
00394   return HAL_OK;
00395 }
00396
00397 /**
00398   * @brief  Initialize the LPTIM MSP.
00399   * @param  hlptim LPTIM handle
00400   * @retval None
00401   */
00402 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00403 {
00404   /* Prevent unused argument(s) compilation warning */
00405   UNUSED(hlptim);
00406
00407   /* NOTE : This function should not be modified, when the callback is needed,
00408             the HAL_LPTIM_MspInit could be implemented in the user file
00409    */
00410 }
00411
00412 /**
00413   * @brief  DeInitialize LPTIM MSP.
00414   * @param  hlptim LPTIM handle
00415   * @retval None
00416   */
00417 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00418 {
00419   /* Prevent unused argument(s) compilation warning */
00420   UNUSED(hlptim);
00421
00422   /* NOTE : This function should not be modified, when the callback is needed,
00423             the HAL_LPTIM_MspDeInit could be implemented in the user file
00424    */
00425 }
00426
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00432   *  @brief   Start-Stop operation functions.
00433   *
00434 @verbatim
00435   ==============================================================================
00436                 ##### LPTIM Start Stop operation functions #####
00437   ==============================================================================
00438     [..]  This section provides functions allowing to:
00439       (+) Start the PWM mode.
00440       (+) Stop the PWM mode.
00441       (+) Start the One pulse mode.
00442       (+) Stop the One pulse mode.
00443       (+) Start the Set once mode.
00444       (+) Stop the Set once mode.
00445       (+) Start the Encoder mode.
00446       (+) Stop the Encoder mode.
00447       (+) Start the Timeout mode.
00448       (+) Stop the Timeout mode.
00449       (+) Start the Counter mode.
00450       (+) Stop the Counter mode.
00451
00452
00453 @endverbatim
00454   * @{
00455   */
00456
00457 /**
00458   * @brief  Start the LPTIM PWM generation.
00459   * @param  hlptim LPTIM handle
00460   * @param  Period Specifies the Autoreload value.
00461   *         This parameter must be a value between 0x0001 and 0xFFFF.
00462   * @param  Pulse Specifies the compare value.
00463   *         This parameter must be a value between 0x0000 and 0xFFFF.
00464   * @retval HAL status
00465   */
00466 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00467 {
00468   /* Check the parameters */
00469   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00470   assert_param(IS_LPTIM_PERIOD(Period));
00471   assert_param(IS_LPTIM_PULSE(Pulse));
00472
00473   /* Set the LPTIM state */
00474   hlptim->State = HAL_LPTIM_STATE_BUSY;
00475
00476   /* Reset WAVE bit to set PWM mode */
00477   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00478
00479   /* Enable the Peripheral */
00480   __HAL_LPTIM_ENABLE(hlptim);
00481
00482   /* Clear flag */
00483   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00484
00485   /* Load the period value in the autoreload register */
00486   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00487
00488   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00489   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00490   {
00491     return HAL_TIMEOUT;
00492   }
00493
00494   /* Clear flag */
00495   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00496
00497   /* Load the pulse value in the compare register */
00498   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00499
00500   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00501   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00502   {
00503     return HAL_TIMEOUT;
00504   }
00505
00506   /* Start timer in continuous mode */
00507   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00508
00509   /* Change the LPTIM state */
00510   hlptim->State = HAL_LPTIM_STATE_READY;
00511
00512   /* Return function status */
00513   return HAL_OK;
00514 }
00515
00516 /**
00517   * @brief  Stop the LPTIM PWM generation.
00518   * @param  hlptim LPTIM handle
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00522 {
00523   /* Check the parameters */
00524   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00525
00526   /* Change the LPTIM state */
00527   hlptim->State = HAL_LPTIM_STATE_BUSY;
00528
00529   /* Disable the Peripheral */
00530   __HAL_LPTIM_DISABLE(hlptim);
00531
00532   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00533   {
00534     return HAL_TIMEOUT;
00535   }
00536
00537   /* Change the LPTIM state */
00538   hlptim->State = HAL_LPTIM_STATE_READY;
00539
00540   /* Return function status */
00541   return HAL_OK;
00542 }
00543
00544 /**
00545   * @brief  Start the LPTIM PWM generation in interrupt mode.
00546   * @param  hlptim LPTIM handle
00547   * @param  Period Specifies the Autoreload value.
00548   *         This parameter must be a value between 0x0001 and 0xFFFF
00549   * @param  Pulse Specifies the compare value.
00550   *         This parameter must be a value between 0x0000 and 0xFFFF
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00554 {
00555   /* Check the parameters */
00556   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00557   assert_param(IS_LPTIM_PERIOD(Period));
00558   assert_param(IS_LPTIM_PULSE(Pulse));
00559
00560   /* Set the LPTIM state */
00561   hlptim->State = HAL_LPTIM_STATE_BUSY;
00562
00563   /* Reset WAVE bit to set PWM mode */
00564   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00565
00566   /* Enable the Peripheral */
00567   __HAL_LPTIM_ENABLE(hlptim);
00568
00569   /* Clear flag */
00570   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00571
00572   /* Load the period value in the autoreload register */
00573   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00574
00575   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00576   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00577   {
00578     return HAL_TIMEOUT;
00579   }
00580
00581   /* Clear flag */
00582   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00583
00584   /* Load the pulse value in the compare register */
00585   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00586
00587   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00588   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00589   {
00590     return HAL_TIMEOUT;
00591   }
00592
00593   /* Disable the Peripheral */
00594   __HAL_LPTIM_DISABLE(hlptim);
00595
00596   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00597   {
00598     return HAL_TIMEOUT;
00599   }
00600
00601   /* Enable Autoreload write complete interrupt */
00602   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00603
00604   /* Enable Compare write complete interrupt */
00605   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00606
00607   /* Enable Autoreload match interrupt */
00608   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00609
00610   /* Enable Compare match interrupt */
00611   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00612
00613   /* If external trigger source is used, then enable external trigger interrupt */
00614   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00615   {
00616     /* Enable external trigger interrupt */
00617     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00618   }
00619
00620   /* Enable the Peripheral */
00621   __HAL_LPTIM_ENABLE(hlptim);
00622
00623   /* Start timer in continuous mode */
00624   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00625
00626   /* Change the LPTIM state */
00627   hlptim->State = HAL_LPTIM_STATE_READY;
00628
00629   /* Return function status */
00630   return HAL_OK;
00631 }
00632
00633 /**
00634   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00635   * @param  hlptim LPTIM handle
00636   * @retval HAL status
00637   */
00638 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00639 {
00640   /* Check the parameters */
00641   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00642
00643   /* Change the LPTIM state */
00644   hlptim->State = HAL_LPTIM_STATE_BUSY;
00645
00646   /* Disable the Peripheral */
00647   __HAL_LPTIM_DISABLE(hlptim);
00648
00649   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00650   {
00651     return HAL_TIMEOUT;
00652   }
00653
00654   /* Disable Autoreload write complete interrupt */
00655   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00656
00657   /* Disable Compare write complete interrupt */
00658   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00659
00660   /* Disable Autoreload match interrupt */
00661   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00662
00663   /* Disable Compare match interrupt */
00664   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00665
00666   /* If external trigger source is used, then disable external trigger interrupt */
00667   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00668   {
00669     /* Disable external trigger interrupt */
00670     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00671   }
00672
00673   /* Change the LPTIM state */
00674   hlptim->State = HAL_LPTIM_STATE_READY;
00675
00676   /* Return function status */
00677   return HAL_OK;
00678 }
00679
00680 /**
00681   * @brief  Start the LPTIM One pulse generation.
00682   * @param  hlptim LPTIM handle
00683   * @param  Period Specifies the Autoreload value.
00684   *         This parameter must be a value between 0x0001 and 0xFFFF.
00685   * @param  Pulse Specifies the compare value.
00686   *         This parameter must be a value between 0x0000 and 0xFFFF.
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00693   assert_param(IS_LPTIM_PERIOD(Period));
00694   assert_param(IS_LPTIM_PULSE(Pulse));
00695
00696   /* Set the LPTIM state */
00697   hlptim->State = HAL_LPTIM_STATE_BUSY;
00698
00699   /* Reset WAVE bit to set one pulse mode */
00700   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00701
00702   /* Enable the Peripheral */
00703   __HAL_LPTIM_ENABLE(hlptim);
00704
00705   /* Clear flag */
00706   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00707
00708   /* Load the period value in the autoreload register */
00709   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00710
00711   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00712   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00713   {
00714     return HAL_TIMEOUT;
00715   }
00716
00717   /* Clear flag */
00718   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00719
00720   /* Load the pulse value in the compare register */
00721   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00722
00723   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00724   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00725   {
00726     return HAL_TIMEOUT;
00727   }
00728
00729   /* Start timer in single (one shot) mode */
00730   __HAL_LPTIM_START_SINGLE(hlptim);
00731
00732   /* Change the LPTIM state */
00733   hlptim->State = HAL_LPTIM_STATE_READY;
00734
00735   /* Return function status */
00736   return HAL_OK;
00737 }
00738
00739 /**
00740   * @brief  Stop the LPTIM One pulse generation.
00741   * @param  hlptim LPTIM handle
00742   * @retval HAL status
00743   */
00744 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00745 {
00746   /* Check the parameters */
00747   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00748
00749   /* Set the LPTIM state */
00750   hlptim->State = HAL_LPTIM_STATE_BUSY;
00751
00752   /* Disable the Peripheral */
00753   __HAL_LPTIM_DISABLE(hlptim);
00754
00755   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00756   {
00757     return HAL_TIMEOUT;
00758   }
00759
00760   /* Change the LPTIM state */
00761   hlptim->State = HAL_LPTIM_STATE_READY;
00762
00763   /* Return function status */
00764   return HAL_OK;
00765 }
00766
00767 /**
00768   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00769   * @param  hlptim LPTIM handle
00770   * @param  Period Specifies the Autoreload value.
00771   *         This parameter must be a value between 0x0001 and 0xFFFF.
00772   * @param  Pulse Specifies the compare value.
00773   *         This parameter must be a value between 0x0000 and 0xFFFF.
00774   * @retval HAL status
00775   */
00776 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00777 {
00778   /* Check the parameters */
00779   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00780   assert_param(IS_LPTIM_PERIOD(Period));
00781   assert_param(IS_LPTIM_PULSE(Pulse));
00782
00783   /* Set the LPTIM state */
00784   hlptim->State = HAL_LPTIM_STATE_BUSY;
00785
00786   /* Reset WAVE bit to set one pulse mode */
00787   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00788
00789   /* Enable the Peripheral */
00790   __HAL_LPTIM_ENABLE(hlptim);
00791
00792   /* Clear flag */
00793   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00794
00795   /* Load the period value in the autoreload register */
00796   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00797
00798   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00799   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00800   {
00801     return HAL_TIMEOUT;
00802   }
00803
00804   /* Clear flag */
00805   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00806
00807   /* Load the pulse value in the compare register */
00808   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00809
00810   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00811   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00812   {
00813     return HAL_TIMEOUT;
00814   }
00815
00816   /* Disable the Peripheral */
00817   __HAL_LPTIM_DISABLE(hlptim);
00818
00819   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00820   {
00821     return HAL_TIMEOUT;
00822   }
00823
00824   /* Enable Autoreload write complete interrupt */
00825   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00826
00827   /* Enable Compare write complete interrupt */
00828   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00829
00830   /* Enable Autoreload match interrupt */
00831   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00832
00833   /* Enable Compare match interrupt */
00834   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00835
00836   /* If external trigger source is used, then enable external trigger interrupt */
00837   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00838   {
00839     /* Enable external trigger interrupt */
00840     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00841   }
00842
00843   /* Enable the Peripheral */
00844   __HAL_LPTIM_ENABLE(hlptim);
00845
00846   /* Start timer in single (one shot) mode */
00847   __HAL_LPTIM_START_SINGLE(hlptim);
00848
00849   /* Change the LPTIM state */
00850   hlptim->State = HAL_LPTIM_STATE_READY;
00851
00852   /* Return function status */
00853   return HAL_OK;
00854 }
00855
00856 /**
00857   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00858   * @param  hlptim LPTIM handle
00859   * @retval HAL status
00860   */
00861 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00862 {
00863   /* Check the parameters */
00864   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00865
00866   /* Set the LPTIM state */
00867   hlptim->State = HAL_LPTIM_STATE_BUSY;
00868
00869
00870   /* Disable the Peripheral */
00871   __HAL_LPTIM_DISABLE(hlptim);
00872
00873   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00874   {
00875     return HAL_TIMEOUT;
00876   }
00877
00878   /* Disable Autoreload write complete interrupt */
00879   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00880
00881   /* Disable Compare write complete interrupt */
00882   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00883
00884   /* Disable Autoreload match interrupt */
00885   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00886
00887   /* Disable Compare match interrupt */
00888   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00889
00890   /* If external trigger source is used, then disable external trigger interrupt */
00891   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00892   {
00893     /* Disable external trigger interrupt */
00894     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00895   }
00896
00897   /* Change the LPTIM state */
00898   hlptim->State = HAL_LPTIM_STATE_READY;
00899
00900   /* Return function status */
00901   return HAL_OK;
00902 }
00903
00904 /**
00905   * @brief  Start the LPTIM in Set once mode.
00906   * @param  hlptim LPTIM handle
00907   * @param  Period Specifies the Autoreload value.
00908   *         This parameter must be a value between 0x0001 and 0xFFFF.
00909   * @param  Pulse Specifies the compare value.
00910   *         This parameter must be a value between 0x0000 and 0xFFFF.
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00914 {
00915   /* Check the parameters */
00916   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00917   assert_param(IS_LPTIM_PERIOD(Period));
00918   assert_param(IS_LPTIM_PULSE(Pulse));
00919
00920   /* Set the LPTIM state */
00921   hlptim->State = HAL_LPTIM_STATE_BUSY;
00922
00923   /* Set WAVE bit to enable the set once mode */
00924   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00925
00926   /* Enable the Peripheral */
00927   __HAL_LPTIM_ENABLE(hlptim);
00928
00929   /* Clear flag */
00930   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00931
00932   /* Load the period value in the autoreload register */
00933   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00934
00935   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00936   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00937   {
00938     return HAL_TIMEOUT;
00939   }
00940
00941   /* Clear flag */
00942   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00943
00944   /* Load the pulse value in the compare register */
00945   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00946
00947   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00948   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00949   {
00950     return HAL_TIMEOUT;
00951   }
00952
00953   /* Start timer in single (one shot) mode */
00954   __HAL_LPTIM_START_SINGLE(hlptim);
00955
00956   /* Change the LPTIM state */
00957   hlptim->State = HAL_LPTIM_STATE_READY;
00958
00959   /* Return function status */
00960   return HAL_OK;
00961 }
00962
00963 /**
00964   * @brief  Stop the LPTIM Set once mode.
00965   * @param  hlptim LPTIM handle
00966   * @retval HAL status
00967   */
00968 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00969 {
00970   /* Check the parameters */
00971   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00972
00973   /* Set the LPTIM state */
00974   hlptim->State = HAL_LPTIM_STATE_BUSY;
00975
00976   /* Disable the Peripheral */
00977   __HAL_LPTIM_DISABLE(hlptim);
00978
00979   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00980   {
00981     return HAL_TIMEOUT;
00982   }
00983
00984   /* Change the LPTIM state */
00985   hlptim->State = HAL_LPTIM_STATE_READY;
00986
00987   /* Return function status */
00988   return HAL_OK;
00989 }
00990
00991 /**
00992   * @brief  Start the LPTIM Set once mode in interrupt mode.
00993   * @param  hlptim LPTIM handle
00994   * @param  Period Specifies the Autoreload value.
00995   *         This parameter must be a value between 0x0000 and 0xFFFF.
00996   * @param  Pulse Specifies the compare value.
00997   *         This parameter must be a value between 0x0000 and 0xFFFF.
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
01001 {
01002   /* Check the parameters */
01003   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01004   assert_param(IS_LPTIM_PERIOD(Period));
01005   assert_param(IS_LPTIM_PULSE(Pulse));
01006
01007   /* Set the LPTIM state */
01008   hlptim->State = HAL_LPTIM_STATE_BUSY;
01009
01010   /* Set WAVE bit to enable the set once mode */
01011   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
01012
01013   /* Enable the Peripheral */
01014   __HAL_LPTIM_ENABLE(hlptim);
01015
01016   /* Clear flag */
01017   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01018
01019   /* Load the period value in the autoreload register */
01020   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01021
01022   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01023   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01024   {
01025     return HAL_TIMEOUT;
01026   }
01027
01028   /* Clear flag */
01029   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01030
01031   /* Load the pulse value in the compare register */
01032   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
01033
01034   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01035   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01036   {
01037     return HAL_TIMEOUT;
01038   }
01039
01040   /* Disable the Peripheral */
01041   __HAL_LPTIM_DISABLE(hlptim);
01042
01043   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01044   {
01045     return HAL_TIMEOUT;
01046   }
01047
01048   /* Enable Autoreload write complete interrupt */
01049   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01050
01051   /* Enable Compare write complete interrupt */
01052   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
01053
01054   /* Enable Autoreload match interrupt */
01055   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01056
01057   /* Enable Compare match interrupt */
01058   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01059
01060   /* If external trigger source is used, then enable external trigger interrupt */
01061   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01062   {
01063     /* Enable external trigger interrupt */
01064     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01065   }
01066
01067   /* Enable the Peripheral */
01068   __HAL_LPTIM_ENABLE(hlptim);
01069
01070   /* Start timer in single (one shot) mode */
01071   __HAL_LPTIM_START_SINGLE(hlptim);
01072
01073   /* Change the LPTIM state */
01074   hlptim->State = HAL_LPTIM_STATE_READY;
01075
01076   /* Return function status */
01077   return HAL_OK;
01078 }
01079
01080 /**
01081   * @brief  Stop the LPTIM Set once mode in interrupt mode.
01082   * @param  hlptim LPTIM handle
01083   * @retval HAL status
01084   */
01085 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01086 {
01087   /* Check the parameters */
01088   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01089
01090   /* Set the LPTIM state */
01091   hlptim->State = HAL_LPTIM_STATE_BUSY;
01092
01093   /* Disable the Peripheral */
01094   __HAL_LPTIM_DISABLE(hlptim);
01095
01096   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01097   {
01098     return HAL_TIMEOUT;
01099   }
01100
01101   /* Disable Autoreload write complete interrupt */
01102   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01103
01104   /* Disable Compare write complete interrupt */
01105   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
01106
01107   /* Disable Autoreload match interrupt */
01108   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01109
01110   /* Disable Compare match interrupt */
01111   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01112
01113   /* If external trigger source is used, then disable external trigger interrupt */
01114   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01115   {
01116     /* Disable external trigger interrupt */
01117     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01118   }
01119
01120   /* Change the LPTIM state */
01121   hlptim->State = HAL_LPTIM_STATE_READY;
01122
01123   /* Return function status */
01124   return HAL_OK;
01125 }
01126
01127 /**
01128   * @brief  Start the Encoder interface.
01129   * @param  hlptim LPTIM handle
01130   * @param  Period Specifies the Autoreload value.
01131   *         This parameter must be a value between 0x0001 and 0xFFFF.
01132   * @retval HAL status
01133   */
01134 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01135 {
01136   uint32_t          tmpcfgr;
01137
01138   /* Check the parameters */
01139   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01140   assert_param(IS_LPTIM_PERIOD(Period));
01141   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01142   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01143   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01144
01145   /* Set the LPTIM state */
01146   hlptim->State = HAL_LPTIM_STATE_BUSY;
01147
01148   /* Get the LPTIMx CFGR value */
01149   tmpcfgr = hlptim->Instance->CFGR;
01150
01151   /* Clear CKPOL bits */
01152   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01153
01154   /* Set Input polarity */
01155   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01156
01157   /* Write to LPTIMx CFGR */
01158   hlptim->Instance->CFGR = tmpcfgr;
01159
01160   /* Set ENC bit to enable the encoder interface */
01161   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01162
01163   /* Enable the Peripheral */
01164   __HAL_LPTIM_ENABLE(hlptim);
01165
01166   /* Clear flag */
01167   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01168
01169   /* Load the period value in the autoreload register */
01170   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01171
01172   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01173   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01174   {
01175     return HAL_TIMEOUT;
01176   }
01177
01178   /* Start timer in continuous mode */
01179   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01180
01181   /* Change the LPTIM state */
01182   hlptim->State = HAL_LPTIM_STATE_READY;
01183
01184   /* Return function status */
01185   return HAL_OK;
01186 }
01187
01188 /**
01189   * @brief  Stop the Encoder interface.
01190   * @param  hlptim LPTIM handle
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
01194 {
01195   /* Check the parameters */
01196   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01197
01198   /* Set the LPTIM state */
01199   hlptim->State = HAL_LPTIM_STATE_BUSY;
01200
01201   /* Disable the Peripheral */
01202   __HAL_LPTIM_DISABLE(hlptim);
01203
01204   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01205   {
01206     return HAL_TIMEOUT;
01207   }
01208
01209   /* Reset ENC bit to disable the encoder interface */
01210   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01211
01212   /* Change the LPTIM state */
01213   hlptim->State = HAL_LPTIM_STATE_READY;
01214
01215   /* Return function status */
01216   return HAL_OK;
01217 }
01218
01219 /**
01220   * @brief  Start the Encoder interface in interrupt mode.
01221   * @param  hlptim LPTIM handle
01222   * @param  Period Specifies the Autoreload value.
01223   *         This parameter must be a value between 0x0000 and 0xFFFF.
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01227 {
01228   uint32_t          tmpcfgr;
01229
01230   /* Check the parameters */
01231   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01232   assert_param(IS_LPTIM_PERIOD(Period));
01233   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01234   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01235   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01236
01237   /* Set the LPTIM state */
01238   hlptim->State = HAL_LPTIM_STATE_BUSY;
01239
01240   /* Configure edge sensitivity for encoder mode */
01241   /* Get the LPTIMx CFGR value */
01242   tmpcfgr = hlptim->Instance->CFGR;
01243
01244   /* Clear CKPOL bits */
01245   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01246
01247   /* Set Input polarity */
01248   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01249
01250   /* Write to LPTIMx CFGR */
01251   hlptim->Instance->CFGR = tmpcfgr;
01252
01253   /* Set ENC bit to enable the encoder interface */
01254   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01255
01256   /* Enable the Peripheral */
01257   __HAL_LPTIM_ENABLE(hlptim);
01258
01259   /* Clear flag */
01260   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01261
01262   /* Load the period value in the autoreload register */
01263   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01264
01265   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01266   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01267   {
01268     return HAL_TIMEOUT;
01269   }
01270
01271   /* Disable the Peripheral */
01272   __HAL_LPTIM_DISABLE(hlptim);
01273
01274   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01275   {
01276     return HAL_TIMEOUT;
01277   }
01278
01279   /* Enable "switch to down direction" interrupt */
01280   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01281
01282   /* Enable "switch to up direction" interrupt */
01283   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01284
01285   /* Enable the Peripheral */
01286   __HAL_LPTIM_ENABLE(hlptim);
01287
01288   /* Start timer in continuous mode */
01289   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01290
01291   /* Change the LPTIM state */
01292   hlptim->State = HAL_LPTIM_STATE_READY;
01293
01294   /* Return function status */
01295   return HAL_OK;
01296 }
01297
01298 /**
01299   * @brief  Stop the Encoder interface in interrupt mode.
01300   * @param  hlptim LPTIM handle
01301   * @retval HAL status
01302   */
01303 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01304 {
01305   /* Check the parameters */
01306   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01307
01308   /* Set the LPTIM state */
01309   hlptim->State = HAL_LPTIM_STATE_BUSY;
01310
01311   /* Disable the Peripheral */
01312   __HAL_LPTIM_DISABLE(hlptim);
01313
01314   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01315   {
01316     return HAL_TIMEOUT;
01317   }
01318
01319   /* Reset ENC bit to disable the encoder interface */
01320   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01321
01322   /* Disable "switch to down direction" interrupt */
01323   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01324
01325   /* Disable "switch to up direction" interrupt */
01326   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01327
01328   /* Change the LPTIM state */
01329   hlptim->State = HAL_LPTIM_STATE_READY;
01330
01331   /* Return function status */
01332   return HAL_OK;
01333 }
01334
01335 /**
01336   * @brief  Start the Timeout function.
01337   * @note   The first trigger event will start the timer, any successive
01338   *         trigger event will reset the counter and the timer restarts.
01339   * @param  hlptim LPTIM handle
01340   * @param  Period Specifies the Autoreload value.
01341   *         This parameter must be a value between 0x0001 and 0xFFFF.
01342   * @param  Timeout Specifies the TimeOut value to reset the counter.
01343   *         This parameter must be a value between 0x0000 and 0xFFFF.
01344   * @retval HAL status
01345   */
01346 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01347 {
01348   /* Check the parameters */
01349   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01350   assert_param(IS_LPTIM_PERIOD(Period));
01351   assert_param(IS_LPTIM_PULSE(Timeout));
01352
01353   /* Set the LPTIM state */
01354   hlptim->State = HAL_LPTIM_STATE_BUSY;
01355
01356   /* Set TIMOUT bit to enable the timeout function */
01357   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01358
01359   /* Enable the Peripheral */
01360   __HAL_LPTIM_ENABLE(hlptim);
01361
01362   /* Clear flag */
01363   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01364
01365   /* Load the period value in the autoreload register */
01366   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01367
01368   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01369   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01370   {
01371     return HAL_TIMEOUT;
01372   }
01373
01374   /* Clear flag */
01375   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01376
01377   /* Load the Timeout value in the compare register */
01378   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01379
01380   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01381   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01382   {
01383     return HAL_TIMEOUT;
01384   }
01385
01386   /* Start timer in continuous mode */
01387   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01388
01389   /* Change the LPTIM state */
01390   hlptim->State = HAL_LPTIM_STATE_READY;
01391
01392   /* Return function status */
01393   return HAL_OK;
01394 }
01395
01396 /**
01397   * @brief  Stop the Timeout function.
01398   * @param  hlptim LPTIM handle
01399   * @retval HAL status
01400   */
01401 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01402 {
01403   /* Check the parameters */
01404   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01405
01406   /* Set the LPTIM state */
01407   hlptim->State = HAL_LPTIM_STATE_BUSY;
01408
01409   /* Disable the Peripheral */
01410   __HAL_LPTIM_DISABLE(hlptim);
01411
01412   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01413   {
01414     return HAL_TIMEOUT;
01415   }
01416
01417   /* Reset TIMOUT bit to enable the timeout function */
01418   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01419
01420   /* Change the LPTIM state */
01421   hlptim->State = HAL_LPTIM_STATE_READY;
01422
01423   /* Return function status */
01424   return HAL_OK;
01425 }
01426
01427 /**
01428   * @brief  Start the Timeout function in interrupt mode.
01429   * @note   The first trigger event will start the timer, any successive
01430   *         trigger event will reset the counter and the timer restarts.
01431   * @param  hlptim LPTIM handle
01432   * @param  Period Specifies the Autoreload value.
01433   *         This parameter must be a value between 0x0001 and 0xFFFF.
01434   * @param  Timeout Specifies the TimeOut value to reset the counter.
01435   *         This parameter must be a value between 0x0000 and 0xFFFF.
01436   * @retval HAL status
01437   */
01438 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01439 {
01440   /* Check the parameters */
01441   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01442   assert_param(IS_LPTIM_PERIOD(Period));
01443   assert_param(IS_LPTIM_PULSE(Timeout));
01444
01445   /* Set the LPTIM state */
01446   hlptim->State = HAL_LPTIM_STATE_BUSY;
01447
01448   /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
01449   __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
01450
01451   /* Set TIMOUT bit to enable the timeout function */
01452   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01453
01454   /* Enable the Peripheral */
01455   __HAL_LPTIM_ENABLE(hlptim);
01456
01457   /* Clear flag */
01458   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01459
01460   /* Load the period value in the autoreload register */
01461   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01462
01463   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01464   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01465   {
01466     return HAL_TIMEOUT;
01467   }
01468
01469   /* Clear flag */
01470   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01471
01472   /* Load the Timeout value in the compare register */
01473   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01474
01475   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01476   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01477   {
01478     return HAL_TIMEOUT;
01479   }
01480
01481   /* Disable the Peripheral */
01482   __HAL_LPTIM_DISABLE(hlptim);
01483
01484   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01485   {
01486     return HAL_TIMEOUT;
01487   }
01488
01489   /* Enable Compare match interrupt */
01490   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01491
01492   /* Enable the Peripheral */
01493   __HAL_LPTIM_ENABLE(hlptim);
01494
01495   /* Start timer in continuous mode */
01496   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01497
01498   /* Change the LPTIM state */
01499   hlptim->State = HAL_LPTIM_STATE_READY;
01500
01501   /* Return function status */
01502   return HAL_OK;
01503 }
01504
01505 /**
01506   * @brief  Stop the Timeout function in interrupt mode.
01507   * @param  hlptim LPTIM handle
01508   * @retval HAL status
01509   */
01510 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01511 {
01512   /* Check the parameters */
01513   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01514
01515
01516   /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
01517   __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
01518
01519   /* Set the LPTIM state */
01520   hlptim->State = HAL_LPTIM_STATE_BUSY;
01521
01522   /* Disable the Peripheral */
01523   __HAL_LPTIM_DISABLE(hlptim);
01524
01525   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01526   {
01527     return HAL_TIMEOUT;
01528   }
01529
01530   /* Reset TIMOUT bit to enable the timeout function */
01531   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01532
01533   /* Disable Compare match interrupt */
01534   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01535
01536   /* Change the LPTIM state */
01537   hlptim->State = HAL_LPTIM_STATE_READY;
01538
01539   /* Return function status */
01540   return HAL_OK;
01541 }
01542
01543 /**
01544   * @brief  Start the Counter mode.
01545   * @param  hlptim LPTIM handle
01546   * @param  Period Specifies the Autoreload value.
01547   *         This parameter must be a value between 0x0001 and 0xFFFF.
01548   * @retval HAL status
01549   */
01550 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01551 {
01552   /* Check the parameters */
01553   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01554   assert_param(IS_LPTIM_PERIOD(Period));
01555
01556   /* Set the LPTIM state */
01557   hlptim->State = HAL_LPTIM_STATE_BUSY;
01558
01559   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01560   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
01561       && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01562   {
01563     /* Check if clock is prescaled */
01564     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01565     /* Set clock prescaler to 0 */
01566     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01567   }
01568
01569   /* Enable the Peripheral */
01570   __HAL_LPTIM_ENABLE(hlptim);
01571
01572   /* Clear flag */
01573   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01574
01575   /* Load the period value in the autoreload register */
01576   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01577
01578   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01579   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01580   {
01581     return HAL_TIMEOUT;
01582   }
01583
01584   /* Start timer in continuous mode */
01585   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01586
01587   /* Change the LPTIM state */
01588   hlptim->State = HAL_LPTIM_STATE_READY;
01589
01590   /* Return function status */
01591   return HAL_OK;
01592 }
01593
01594 /**
01595   * @brief  Stop the Counter mode.
01596   * @param  hlptim LPTIM handle
01597   * @retval HAL status
01598   */
01599 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01600 {
01601   /* Check the parameters */
01602   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01603
01604   /* Set the LPTIM state */
01605   hlptim->State = HAL_LPTIM_STATE_BUSY;
01606
01607   /* Disable the Peripheral */
01608   __HAL_LPTIM_DISABLE(hlptim);
01609
01610   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01611   {
01612     return HAL_TIMEOUT;
01613   }
01614
01615   /* Change the LPTIM state */
01616   hlptim->State = HAL_LPTIM_STATE_READY;
01617
01618   /* Return function status */
01619   return HAL_OK;
01620 }
01621
01622 /**
01623   * @brief  Start the Counter mode in interrupt mode.
01624   * @param  hlptim LPTIM handle
01625   * @param  Period Specifies the Autoreload value.
01626   *         This parameter must be a value between 0x0001 and 0xFFFF.
01627   * @retval HAL status
01628   */
01629 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01630 {
01631   /* Check the parameters */
01632   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01633   assert_param(IS_LPTIM_PERIOD(Period));
01634
01635   /* Set the LPTIM state */
01636   hlptim->State = HAL_LPTIM_STATE_BUSY;
01637
01638   /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
01639   __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
01640
01641   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01642   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
01643       && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01644   {
01645     /* Check if clock is prescaled */
01646     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01647     /* Set clock prescaler to 0 */
01648     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01649   }
01650
01651   /* Enable the Peripheral */
01652   __HAL_LPTIM_ENABLE(hlptim);
01653
01654   /* Clear flag */
01655   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01656
01657   /* Load the period value in the autoreload register */
01658   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01659
01660   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01661   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01662   {
01663     return HAL_TIMEOUT;
01664   }
01665
01666   /* Disable the Peripheral */
01667   __HAL_LPTIM_DISABLE(hlptim);
01668
01669   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01670   {
01671     return HAL_TIMEOUT;
01672   }
01673
01674   /* Enable Autoreload write complete interrupt */
01675   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01676
01677   /* Enable Autoreload match interrupt */
01678   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01679
01680   /* Enable the Peripheral */
01681   __HAL_LPTIM_ENABLE(hlptim);
01682
01683   /* Start timer in continuous mode */
01684   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01685
01686   /* Change the LPTIM state */
01687   hlptim->State = HAL_LPTIM_STATE_READY;
01688
01689   /* Return function status */
01690   return HAL_OK;
01691 }
01692
01693 /**
01694   * @brief  Stop the Counter mode in interrupt mode.
01695   * @param  hlptim LPTIM handle
01696   * @retval HAL status
01697   */
01698 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01699 {
01700   /* Check the parameters */
01701   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01702
01703
01704   /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
01705   __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
01706
01707   /* Set the LPTIM state */
01708   hlptim->State = HAL_LPTIM_STATE_BUSY;
01709
01710   /* Disable the Peripheral */
01711   __HAL_LPTIM_DISABLE(hlptim);
01712
01713   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01714   {
01715     return HAL_TIMEOUT;
01716   }
01717
01718   /* Disable Autoreload write complete interrupt */
01719   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01720
01721   /* Disable Autoreload match interrupt */
01722   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01723   /* Change the LPTIM state */
01724   hlptim->State = HAL_LPTIM_STATE_READY;
01725
01726   /* Return function status */
01727   return HAL_OK;
01728 }
01729
01730 /**
01731   * @}
01732   */
01733
01734 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01735   *  @brief  Read operation functions.
01736   *
01737 @verbatim
01738   ==============================================================================
01739                   ##### LPTIM Read operation functions #####
01740   ==============================================================================
01741 [..]  This section provides LPTIM Reading functions.
01742       (+) Read the counter value.
01743       (+) Read the period (Auto-reload) value.
01744       (+) Read the pulse (Compare)value.
01745 @endverbatim
01746   * @{
01747   */
01748
01749 /**
01750   * @brief  Return the current counter value.
01751   * @param  hlptim LPTIM handle
01752   * @retval Counter value.
01753   */
01754 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
01755 {
01756   /* Check the parameters */
01757   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01758
01759   return (hlptim->Instance->CNT);
01760 }
01761
01762 /**
01763   * @brief  Return the current Autoreload (Period) value.
01764   * @param  hlptim LPTIM handle
01765   * @retval Autoreload value.
01766   */
01767 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
01768 {
01769   /* Check the parameters */
01770   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01771
01772   return (hlptim->Instance->ARR);
01773 }
01774
01775 /**
01776   * @brief  Return the current Compare (Pulse) value.
01777   * @param  hlptim LPTIM handle
01778   * @retval Compare value.
01779   */
01780 uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim)
01781 {
01782   /* Check the parameters */
01783   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01784
01785   return (hlptim->Instance->CMP);
01786 }
01787
01788 /**
01789   * @}
01790   */
01791
01792 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01793   *  @brief  LPTIM  IRQ handler.
01794   *
01795 @verbatim
01796   ==============================================================================
01797                       ##### LPTIM IRQ handler and callbacks  #####
01798   ==============================================================================
01799 [..]  This section provides LPTIM IRQ handler and callback functions called within
01800       the IRQ handler:
01801    (+) LPTIM interrupt request handler
01802    (+) Compare match Callback
01803    (+) Auto-reload match Callback
01804    (+) External trigger event detection Callback
01805    (+) Compare register write complete Callback
01806    (+) Auto-reload register write complete Callback
01807    (+) Up-counting direction change Callback
01808    (+) Down-counting direction change Callback
01809
01810 @endverbatim
01811   * @{
01812   */
01813
01814 /**
01815   * @brief  Handle LPTIM interrupt request.
01816   * @param  hlptim LPTIM handle
01817   * @retval None
01818   */
01819 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01820 {
01821   /* Compare match interrupt */
01822   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01823   {
01824     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01825     {
01826       /* Clear Compare match flag */
01827       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01828
01829       /* Compare match Callback */
01830 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01831       hlptim->CompareMatchCallback(hlptim);
01832 #else
01833       HAL_LPTIM_CompareMatchCallback(hlptim);
01834 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01835     }
01836   }
01837
01838   /* Autoreload match interrupt */
01839   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01840   {
01841     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01842     {
01843       /* Clear Autoreload match flag */
01844       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01845
01846       /* Autoreload match Callback */
01847 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01848       hlptim->AutoReloadMatchCallback(hlptim);
01849 #else
01850       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01851 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01852     }
01853   }
01854
01855   /* Trigger detected interrupt */
01856   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01857   {
01858     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01859     {
01860       /* Clear Trigger detected flag */
01861       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01862
01863       /* Trigger detected callback */
01864 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01865       hlptim->TriggerCallback(hlptim);
01866 #else
01867       HAL_LPTIM_TriggerCallback(hlptim);
01868 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01869     }
01870   }
01871
01872   /* Compare write interrupt */
01873   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01874   {
01875     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01876     {
01877       /* Clear Compare write flag */
01878       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01879
01880       /* Compare write Callback */
01881 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01882       hlptim->CompareWriteCallback(hlptim);
01883 #else
01884       HAL_LPTIM_CompareWriteCallback(hlptim);
01885 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01886     }
01887   }
01888
01889   /* Autoreload write interrupt */
01890   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01891   {
01892     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01893     {
01894       /* Clear Autoreload write flag */
01895       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01896
01897       /* Autoreload write Callback */
01898 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01899       hlptim->AutoReloadWriteCallback(hlptim);
01900 #else
01901       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01902 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01903     }
01904   }
01905
01906   /* Direction counter changed from Down to Up interrupt */
01907   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01908   {
01909     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01910     {
01911       /* Clear Direction counter changed from Down to Up flag */
01912       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01913
01914       /* Direction counter changed from Down to Up Callback */
01915 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01916       hlptim->DirectionUpCallback(hlptim);
01917 #else
01918       HAL_LPTIM_DirectionUpCallback(hlptim);
01919 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01920     }
01921   }
01922
01923   /* Direction counter changed from Up to Down interrupt */
01924   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01925   {
01926     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01927     {
01928       /* Clear Direction counter changed from Up to Down flag */
01929       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01930
01931       /* Direction counter changed from Up to Down Callback */
01932 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01933       hlptim->DirectionDownCallback(hlptim);
01934 #else
01935       HAL_LPTIM_DirectionDownCallback(hlptim);
01936 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01937     }
01938   }
01939 }
01940
01941 /**
01942   * @brief  Compare match callback in non-blocking mode.
01943   * @param  hlptim LPTIM handle
01944   * @retval None
01945   */
01946 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01947 {
01948   /* Prevent unused argument(s) compilation warning */
01949   UNUSED(hlptim);
01950
01951   /* NOTE : This function should not be modified, when the callback is needed,
01952             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01953    */
01954 }
01955
01956 /**
01957   * @brief  Autoreload match callback in non-blocking mode.
01958   * @param  hlptim LPTIM handle
01959   * @retval None
01960   */
01961 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01962 {
01963   /* Prevent unused argument(s) compilation warning */
01964   UNUSED(hlptim);
01965
01966   /* NOTE : This function should not be modified, when the callback is needed,
01967             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01968    */
01969 }
01970
01971 /**
01972   * @brief  Trigger detected callback in non-blocking mode.
01973   * @param  hlptim LPTIM handle
01974   * @retval None
01975   */
01976 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01977 {
01978   /* Prevent unused argument(s) compilation warning */
01979   UNUSED(hlptim);
01980
01981   /* NOTE : This function should not be modified, when the callback is needed,
01982             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01983    */
01984 }
01985
01986 /**
01987   * @brief  Compare write callback in non-blocking mode.
01988   * @param  hlptim LPTIM handle
01989   * @retval None
01990   */
01991 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01992 {
01993   /* Prevent unused argument(s) compilation warning */
01994   UNUSED(hlptim);
01995
01996   /* NOTE : This function should not be modified, when the callback is needed,
01997             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01998    */
01999 }
02000
02001 /**
02002   * @brief  Autoreload write callback in non-blocking mode.
02003   * @param  hlptim LPTIM handle
02004   * @retval None
02005   */
02006 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
02007 {
02008   /* Prevent unused argument(s) compilation warning */
02009   UNUSED(hlptim);
02010
02011   /* NOTE : This function should not be modified, when the callback is needed,
02012             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
02013    */
02014 }
02015
02016 /**
02017   * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
02018   * @param  hlptim LPTIM handle
02019   * @retval None
02020   */
02021 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
02022 {
02023   /* Prevent unused argument(s) compilation warning */
02024   UNUSED(hlptim);
02025
02026   /* NOTE : This function should not be modified, when the callback is needed,
02027             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
02028    */
02029 }
02030
02031 /**
02032   * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
02033   * @param  hlptim LPTIM handle
02034   * @retval None
02035   */
02036 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
02037 {
02038   /* Prevent unused argument(s) compilation warning */
02039   UNUSED(hlptim);
02040
02041   /* NOTE : This function should not be modified, when the callback is needed,
02042             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
02043    */
02044 }
02045
02046 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02047 /**
02048   * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
02049   * @param hlptim LPTIM handle
02050   * @param CallbackID ID of the callback to be registered
02051   *        This parameter can be one of the following values:
02052   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02053   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02054   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02055   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02056   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02057   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02058   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02059   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02060   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02061   * @param pCallback pointer to the callback function
02062   * @retval status
02063   */
02064 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02065                                              HAL_LPTIM_CallbackIDTypeDef CallbackID,
02066                                              pLPTIM_CallbackTypeDef      pCallback)
02067 {
02068   HAL_StatusTypeDef status = HAL_OK;
02069
02070   if (pCallback == NULL)
02071   {
02072     return HAL_ERROR;
02073   }
02074
02075   if (hlptim->State == HAL_LPTIM_STATE_READY)
02076   {
02077     switch (CallbackID)
02078     {
02079       case HAL_LPTIM_MSPINIT_CB_ID :
02080         hlptim->MspInitCallback = pCallback;
02081         break;
02082
02083       case HAL_LPTIM_MSPDEINIT_CB_ID :
02084         hlptim->MspDeInitCallback = pCallback;
02085         break;
02086
02087       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02088         hlptim->CompareMatchCallback = pCallback;
02089         break;
02090
02091       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02092         hlptim->AutoReloadMatchCallback = pCallback;
02093         break;
02094
02095       case HAL_LPTIM_TRIGGER_CB_ID :
02096         hlptim->TriggerCallback = pCallback;
02097         break;
02098
02099       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02100         hlptim->CompareWriteCallback = pCallback;
02101         break;
02102
02103       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02104         hlptim->AutoReloadWriteCallback = pCallback;
02105         break;
02106
02107       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02108         hlptim->DirectionUpCallback = pCallback;
02109         break;
02110
02111       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02112         hlptim->DirectionDownCallback = pCallback;
02113         break;
02114
02115       default :
02116         /* Return error status */
02117         status =  HAL_ERROR;
02118         break;
02119     }
02120   }
02121   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02122   {
02123     switch (CallbackID)
02124     {
02125       case HAL_LPTIM_MSPINIT_CB_ID :
02126         hlptim->MspInitCallback = pCallback;
02127         break;
02128
02129       case HAL_LPTIM_MSPDEINIT_CB_ID :
02130         hlptim->MspDeInitCallback = pCallback;
02131         break;
02132
02133       default :
02134         /* Return error status */
02135         status =  HAL_ERROR;
02136         break;
02137     }
02138   }
02139   else
02140   {
02141     /* Return error status */
02142     status =  HAL_ERROR;
02143   }
02144
02145   return status;
02146 }
02147
02148 /**
02149   * @brief  Unregister a LPTIM callback
02150   *         LLPTIM callback is redirected to the weak predefined callback
02151   * @param hlptim LPTIM handle
02152   * @param CallbackID ID of the callback to be unregistered
02153   *        This parameter can be one of the following values:
02154   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02155   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02156   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02157   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02158   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02159   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02160   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02161   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02162   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02163   * @retval status
02164   */
02165 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02166                                                HAL_LPTIM_CallbackIDTypeDef CallbackID)
02167 {
02168   HAL_StatusTypeDef status = HAL_OK;
02169
02170   if (hlptim->State == HAL_LPTIM_STATE_READY)
02171   {
02172     switch (CallbackID)
02173     {
02174       case HAL_LPTIM_MSPINIT_CB_ID :
02175         /* Legacy weak MspInit Callback */
02176         hlptim->MspInitCallback = HAL_LPTIM_MspInit;
02177         break;
02178
02179       case HAL_LPTIM_MSPDEINIT_CB_ID :
02180         /* Legacy weak Msp DeInit Callback */
02181         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
02182         break;
02183
02184       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02185         /* Legacy weak Compare match Callback */
02186         hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
02187         break;
02188
02189       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02190         /* Legacy weak Auto-reload match Callback */
02191         hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
02192         break;
02193
02194       case HAL_LPTIM_TRIGGER_CB_ID :
02195         /* Legacy weak External trigger event detection Callback */
02196         hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
02197         break;
02198
02199       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02200         /* Legacy weak Compare register write complete Callback */
02201         hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
02202         break;
02203
02204       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02205         /* Legacy weak Auto-reload register write complete Callback */
02206         hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
02207         break;
02208
02209       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02210         /* Legacy weak Up-counting direction change Callback */
02211         hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
02212         break;
02213
02214       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02215         /* Legacy weak Down-counting direction change Callback */
02216         hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
02217         break;
02218
02219       default :
02220         /* Return error status */
02221         status =  HAL_ERROR;
02222         break;
02223     }
02224   }
02225   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02226   {
02227     switch (CallbackID)
02228     {
02229       case HAL_LPTIM_MSPINIT_CB_ID :
02230         /* Legacy weak MspInit Callback */
02231         hlptim->MspInitCallback = HAL_LPTIM_MspInit;
02232         break;
02233
02234       case HAL_LPTIM_MSPDEINIT_CB_ID :
02235         /* Legacy weak Msp DeInit Callback */
02236         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
02237         break;
02238
02239       default :
02240         /* Return error status */
02241         status =  HAL_ERROR;
02242         break;
02243     }
02244   }
02245   else
02246   {
02247     /* Return error status */
02248     status =  HAL_ERROR;
02249   }
02250
02251   return status;
02252 }
02253 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02254
02255 /**
02256   * @}
02257   */
02258
02259 /** @defgroup LPTIM_Group5 Peripheral State functions
02260   *  @brief   Peripheral State functions.
02261   *
02262 @verbatim
02263   ==============================================================================
02264                       ##### Peripheral State functions #####
02265   ==============================================================================
02266     [..]
02267     This subsection permits to get in run-time the status of the peripheral.
02268
02269 @endverbatim
02270   * @{
02271   */
02272
02273 /**
02274   * @brief  Return the LPTIM handle state.
02275   * @param  hlptim LPTIM handle
02276   * @retval HAL state
02277   */
02278 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
02279 {
02280   /* Return LPTIM handle state */
02281   return hlptim->State;
02282 }
02283
02284 /**
02285   * @}
02286   */
02287
02288
02289 /**
02290   * @}
02291   */
02292
02293 /* Private functions ---------------------------------------------------------*/
02294
02295 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
02296   * @{
02297   */
02298 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02299 /**
02300   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
02301   * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
02302   *                the configuration information for LPTIM module.
02303   * @retval None
02304   */
02305 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
02306 {
02307   /* Reset the LPTIM callback to the legacy weak callbacks */
02308   lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;
02309   lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
02310   lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;
02311   lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;
02312   lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
02313   lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;
02314   lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;
02315 }
02316 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02317
02318 /**
02319   * @brief  LPTimer Wait for flag set
02320   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02321   *                the configuration information for LPTIM module.
02322   * @param  flag   The lptim flag
02323   * @retval HAL status
02324   */
02325 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
02326 {
02327   HAL_StatusTypeDef result = HAL_OK;
02328   uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
02329   do
02330   {
02331     count--;
02332     if (count == 0UL)
02333     {
02334       result = HAL_TIMEOUT;
02335     }
02336   } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
02337
02338   return result;
02339 }
02340
02341 /**
02342   * @brief  Disable LPTIM HW instance.
02343   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02344   *                the configuration information for LPTIM module.
02345   * @note   The following sequence is required to solve LPTIM disable HW limitation.
02346   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
02347   *         stuck in LPTIM interrupt when entering Stop mode" section.
02348   * @retval None
02349   */
02350 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
02351 {
02352   uint32_t tmpclksource = 0;
02353   uint32_t tmpIER;
02354   uint32_t tmpCFGR;
02355   uint32_t tmpCMP;
02356   uint32_t tmpARR;
02357   uint32_t primask_bit;
02358   uint32_t tmpOR;
02359
02360   /* Enter critical section */
02361   primask_bit = __get_PRIMASK();
02362   __set_PRIMASK(1) ;
02363
02364   /*********** Save LPTIM Config ***********/
02365   /* Save LPTIM source clock */
02366   switch ((uint32_t)hlptim->Instance)
02367   {
02368     case LPTIM1_BASE:
02369       tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
02370       break;
02371     default:
02372       break;
02373   }
02374
02375   /* Save LPTIM configuration registers */
02376   tmpIER = hlptim->Instance->IER;
02377   tmpCFGR = hlptim->Instance->CFGR;
02378   tmpCMP = hlptim->Instance->CMP;
02379   tmpARR = hlptim->Instance->ARR;
02380   tmpOR = hlptim->Instance->OR;
02381
02382   /*********** Reset LPTIM ***********/
02383   switch ((uint32_t)hlptim->Instance)
02384   {
02385     case LPTIM1_BASE:
02386       __HAL_RCC_LPTIM1_FORCE_RESET();
02387       __HAL_RCC_LPTIM1_RELEASE_RESET();
02388       break;
02389     default:
02390       break;
02391   }
02392
02393   /*********** Restore LPTIM Config ***********/
02394   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
02395   {
02396     /* Force LPTIM source kernel clock from APB */
02397     switch ((uint32_t)hlptim->Instance)
02398     {
02399       case LPTIM1_BASE:
02400         __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
02401         break;
02402       default:
02403         break;
02404     }
02405
02406     if (tmpCMP != 0UL)
02407     {
02408       /* Restore CMP register (LPTIM should be enabled first) */
02409       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02410       hlptim->Instance->CMP = tmpCMP;
02411
02412       /* Wait for the completion of the write operation to the LPTIM_CMP register */
02413       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
02414       {
02415         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02416       }
02417       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
02418     }
02419
02420     if (tmpARR != 0UL)
02421     {
02422       /* Restore ARR register (LPTIM should be enabled first) */
02423       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02424       hlptim->Instance->ARR = tmpARR;
02425
02426       /* Wait for the completion of the write operation to the LPTIM_ARR register */
02427       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
02428       {
02429         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02430       }
02431
02432       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
02433     }
02434
02435     /* Restore LPTIM source kernel clock */
02436     switch ((uint32_t)hlptim->Instance)
02437     {
02438       case LPTIM1_BASE:
02439         __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
02440         break;
02441       default:
02442         break;
02443     }
02444   }
02445
02446   /* Restore configuration registers (LPTIM should be disabled first) */
02447   hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
02448   hlptim->Instance->IER = tmpIER;
02449   hlptim->Instance->CFGR = tmpCFGR;
02450   hlptim->Instance->OR = tmpOR;
02451
02452   /* Exit critical section: restore previous priority mask */
02453   __set_PRIMASK(primask_bit);
02454 }
02455 /**
02456   * @}
02457   */
02458
02459
02460 #endif /* HAL_LPTIM_MODULE_ENABLED */
02461 /**
02462   * @}
02463   */
02464
02465 /**
02466   * @}
02467   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_lptim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_lptim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_LPTIM_H
00021 #define STM32G4xx_HAL_LPTIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034
00035
00036 /** @addtogroup LPTIM
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00042   * @{
00043   */
00044 #define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  EXTI_IMR2_IM37  /*!< External interrupt line 37 Connected to the LPTIM EXTI Line */
00045
00046 /**
00047   * @brief  LPTIM Clock configuration definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t Source;         /*!< Selects the clock source.
00052                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00053
00054   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00055                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00056
00057 } LPTIM_ClockConfigTypeDef;
00058
00059 /**
00060   * @brief  LPTIM Clock configuration definition
00061   */
00062 typedef struct
00063 {
00064   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00065                            if the ULPTIM input is selected.
00066                            Note: This parameter is used only when Ultra low power clock source is used.
00067                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00068                            (one of the Low power oscillator) must be active.
00069                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00070
00071   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00072                            Note: This parameter is used only when Ultra low power clock source is used.
00073                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00074
00075 } LPTIM_ULPClockConfigTypeDef;
00076
00077 /**
00078   * @brief  LPTIM Trigger configuration definition
00079   */
00080 typedef struct
00081 {
00082   uint32_t Source;        /*!< Selects the Trigger source.
00083                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00084
00085   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00086                           Note: This parameter is used only when an external trigger is used.
00087                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00088
00089   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00090                           Note: This parameter is used only when an external trigger is used.
00091                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00092 } LPTIM_TriggerConfigTypeDef;
00093
00094 /**
00095   * @brief  LPTIM Initialization Structure definition
00096   */
00097 typedef struct
00098 {
00099   LPTIM_ClockConfigTypeDef     Clock;             /*!< Specifies the clock parameters */
00100
00101   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
00102
00103   LPTIM_TriggerConfigTypeDef   Trigger;           /*!< Specifies the Trigger parameters */
00104
00105   uint32_t                     OutputPolarity;    /*!< Specifies the Output polarity.
00106                                                   This parameter can be a value of @ref LPTIM_Output_Polarity */
00107
00108   uint32_t                     UpdateMode;        /*!< Specifies whether the update of the autoreload and the compare
00109                                                   values is done immediately or after the end of current period.
00110                                                   This parameter can be a value of @ref LPTIM_Updating_Mode */
00111
00112   uint32_t                     CounterSource;     /*!< Specifies whether the counter is incremented each internal event
00113                                                   or each external event.
00114                                                   This parameter can be a value of @ref LPTIM_Counter_Source */
00115
00116   uint32_t                     Input1Source;      /*!< Specifies source selected for input1 (GPIO or comparator output).
00117                                                   This parameter can be a value of @ref LPTIM_Input1_Source */
00118
00119   uint32_t                     Input2Source;      /*!< Specifies source selected for input2 (GPIO or comparator output).
00120                                                   Note: This parameter is used only for encoder feature so is used only
00121                                                   for LPTIM1 instance.
00122                                                   This parameter can be a value of @ref LPTIM_Input2_Source */
00123 } LPTIM_InitTypeDef;
00124
00125 /**
00126   * @brief  HAL LPTIM State structure definition
00127   */
00128 typedef enum
00129 {
00130   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00131   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00132   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00133   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00134   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
00135 } HAL_LPTIM_StateTypeDef;
00136
00137 /**
00138   * @brief  LPTIM handle Structure definition
00139   */
00140 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00141 typedef struct __LPTIM_HandleTypeDef
00142 #else
00143 typedef struct
00144 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00145 {
00146   LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
00147
00148   LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
00149
00150   HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
00151
00152   HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
00153
00154   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00155
00156 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00157   void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
00158   void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
00159   void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
00160   void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
00161   void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
00162   void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
00163   void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
00164   void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
00165   void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
00166 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00167 } LPTIM_HandleTypeDef;
00168
00169 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00170 /**
00171   * @brief  HAL LPTIM Callback ID enumeration definition
00172   */
00173 typedef enum
00174 {
00175   HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
00176   HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
00177   HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
00178   HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
00179   HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
00180   HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
00181   HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
00182   HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
00183   HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
00184 } HAL_LPTIM_CallbackIDTypeDef;
00185
00186 /**
00187   * @brief  HAL TIM Callback pointer definition
00188   */
00189 typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
00190
00191 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00192 /**
00193   * @}
00194   */
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00198   * @{
00199   */
00200
00201 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00202   * @{
00203   */
00204 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
00205 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00211   * @{
00212   */
00213 #define LPTIM_PRESCALER_DIV1                    0x00000000U
00214 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00215 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00216 #define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
00217 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00218 #define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
00219 #define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
00220 #define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00226   * @{
00227   */
00228
00229 #define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
00230 #define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00236   * @{
00237   */
00238 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
00239 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00240 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00241 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00247   * @{
00248   */
00249 #define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
00250 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00251 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00257   * @{
00258   */
00259 #define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
00260 #define LPTIM_TRIGSOURCE_0                      0x00000000U
00261 #define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
00262 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00263 #define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00264 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00265 #define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00266 #define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00267 #define LPTIM_TRIGSOURCE_7                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00268 #define LPTIM_TRIGSOURCE_8                      LPTIM_CFGR_TRIGSEL_3
00269 #define LPTIM_TRIGSOURCE_9                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)
00270 #define LPTIM_TRIGSOURCE_10                     (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
00271 #define LPTIM_TRIGSOURCE_11                     (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
00272 #define LPTIM_TRIGSOURCE_12                     (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00278   * @{
00279   */
00280 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00281 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00282 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00288   * @{
00289   */
00290 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
00291 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00292 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00293 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00299   * @{
00300   */
00301
00302 #define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
00303 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00309   * @{
00310   */
00311
00312 #define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
00313 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00319   * @{
00320   */
00321
00322 #define LPTIM_INPUT1SOURCE_GPIO         0x00000000U
00323 #define LPTIM_INPUT1SOURCE_COMP1        LPTIM_OR_IN1_0
00324 #define LPTIM_INPUT1SOURCE_COMP3        (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
00325 #if defined(COMP5)
00326 #define LPTIM_INPUT1SOURCE_COMP5        (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
00327 #endif /* COMP5 */
00328 #if defined(COMP7)
00329 #define LPTIM_INPUT1SOURCE_COMP7        (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
00330 #endif /* COMP7 */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00336   * @{
00337   */
00338
00339 #define LPTIM_INPUT2SOURCE_GPIO         0x00000000U
00340 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_IN2_0
00341 #define LPTIM_INPUT2SOURCE_COMP4        (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
00342 #if defined(COMP6)
00343 #define LPTIM_INPUT2SOURCE_COMP6        (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
00344 #endif /* COMP6 */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00350   * @{
00351   */
00352
00353 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00354 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00355 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00356 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00357 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00358 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00359 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00365   * @{
00366   */
00367 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00368 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00369 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00370 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00371 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00372 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00373 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382 /* Exported macros -----------------------------------------------------------*/
00383 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00384   * @{
00385   */
00386
00387 /** @brief Reset LPTIM handle state.
00388   * @param  __HANDLE__ LPTIM handle
00389   * @retval None
00390   */
00391 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00392 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00393                                                         (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
00394                                                         (__HANDLE__)->MspInitCallback   = NULL;                  \
00395                                                         (__HANDLE__)->MspDeInitCallback = NULL;                  \
00396                                                       } while(0)
00397 #else
00398 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00399 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00400
00401 /**
00402   * @brief  Enable the LPTIM peripheral.
00403   * @param  __HANDLE__ LPTIM handle
00404   * @retval None
00405   */
00406 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
00407
00408 /**
00409   * @brief  Disable the LPTIM peripheral.
00410   * @param  __HANDLE__ LPTIM handle
00411   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00412   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00413   *         stuck in LPTIM interrupt when entering Stop mode" section.
00414   * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
00415   *         check for TIMEOUT.
00416   * @retval None
00417   */
00418 #define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
00419
00420 /**
00421   * @brief  Start the LPTIM peripheral in Continuous mode.
00422   * @param  __HANDLE__ LPTIM handle
00423   * @retval None
00424   */
00425 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00426 /**
00427   * @brief  Start the LPTIM peripheral in single mode.
00428   * @param  __HANDLE__ LPTIM handle
00429   * @retval None
00430   */
00431 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00432
00433 /**
00434   * @brief  Reset the LPTIM Counter register in synchronous mode.
00435   * @param  __HANDLE__ LPTIM handle
00436   * @retval None
00437   */
00438 #define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
00439
00440 /**
00441   * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
00442   * @param  __HANDLE__ LPTIM handle
00443   * @retval None
00444   */
00445 #define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
00446
00447 /**
00448   * @brief  Write the passed parameter in the Autoreload register.
00449   * @param  __HANDLE__ LPTIM handle
00450   * @param  __VALUE__ Autoreload value
00451   *         This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
00452   * @retval None
00453   * @note   The ARR register can only be modified when the LPTIM instance is enabled.
00454   */
00455 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00456
00457 /**
00458   * @brief  Write the passed parameter in the Compare register.
00459   * @param  __HANDLE__ LPTIM handle
00460   * @param  __VALUE__ Compare value
00461   * @retval None
00462   * @note   The CMP register can only be modified when the LPTIM instance is enabled.
00463   */
00464 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00465
00466 /**
00467   * @brief  Check whether the specified LPTIM flag is set or not.
00468   * @param  __HANDLE__ LPTIM handle
00469   * @param  __FLAG__ LPTIM flag to check
00470   *            This parameter can be a value of:
00471   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00472   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00473   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00474   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00475   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00476   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00477   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00478   * @retval The state of the specified flag (SET or RESET).
00479   */
00480 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00481
00482 /**
00483   * @brief  Clear the specified LPTIM flag.
00484   * @param  __HANDLE__ LPTIM handle.
00485   * @param  __FLAG__ LPTIM flag to clear.
00486   *            This parameter can be a value of:
00487   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00488   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00489   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00490   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00491   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00492   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00493   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00494   * @retval None.
00495   */
00496 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00497
00498 /**
00499   * @brief  Enable the specified LPTIM interrupt.
00500   * @param  __HANDLE__ LPTIM handle.
00501   * @param  __INTERRUPT__ LPTIM interrupt to set.
00502   *            This parameter can be a value of:
00503   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00504   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00505   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00506   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00507   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00508   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00509   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00510   * @retval None.
00511   * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
00512   */
00513 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00514
00515 /**
00516   * @brief  Disable the specified LPTIM interrupt.
00517   * @param  __HANDLE__ LPTIM handle.
00518   * @param  __INTERRUPT__ LPTIM interrupt to set.
00519   *            This parameter can be a value of:
00520   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00521   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00522   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00523   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00524   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00525   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00526   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00527   * @retval None.
00528   * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
00529   */
00530 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00531
00532 /**
00533   * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
00534   * @param  __HANDLE__ LPTIM handle.
00535   * @param  __INTERRUPT__ LPTIM interrupt to check.
00536   *            This parameter can be a value of:
00537   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00538   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00539   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00540   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00541   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00542   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00543   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00544   * @retval Interrupt status.
00545   */
00546
00547 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
00548                                                                 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00549
00550 /**
00551   * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
00552   * @retval None
00553   */
00554 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR2\
00555                                                         |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00556
00557 /**
00558   * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
00559   * @retval None
00560   */
00561 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR2\
00562                                                         &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00563
00564 /**
00565   * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.
00566   * @retval None.
00567   */
00568 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR2\
00569                                                         |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00570
00571 /**
00572   * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.
00573   * @retval None.
00574   */
00575 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR2\
00576                                                         &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00577
00578 /**
00579   * @}
00580   */
00581
00582 /* Exported functions --------------------------------------------------------*/
00583 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00584   * @{
00585   */
00586
00587 /** @addtogroup LPTIM_Exported_Functions_Group1
00588   *  @brief    Initialization and Configuration functions.
00589   * @{
00590   */
00591 /* Initialization/de-initialization functions  ********************************/
00592 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00593 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00594
00595 /* MSP functions  *************************************************************/
00596 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00597 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00598 /**
00599   * @}
00600   */
00601
00602 /** @addtogroup LPTIM_Exported_Functions_Group2
00603   *  @brief   Start-Stop operation functions.
00604   * @{
00605   */
00606 /* Start/Stop operation functions  *********************************************/
00607 /* ################################# PWM Mode ################################*/
00608 /* Blocking mode: Polling */
00609 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00610 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00611 /* Non-Blocking mode: Interrupt */
00612 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00613 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00614
00615 /* ############################# One Pulse Mode ##############################*/
00616 /* Blocking mode: Polling */
00617 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00618 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00619 /* Non-Blocking mode: Interrupt */
00620 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00621 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00622
00623 /* ############################## Set once Mode ##############################*/
00624 /* Blocking mode: Polling */
00625 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00626 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00627 /* Non-Blocking mode: Interrupt */
00628 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00629 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00630
00631 /* ############################### Encoder Mode ##############################*/
00632 /* Blocking mode: Polling */
00633 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00634 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00635 /* Non-Blocking mode: Interrupt */
00636 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00637 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00638
00639 /* ############################# Time out  Mode ##############################*/
00640 /* Blocking mode: Polling */
00641 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00642 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00643 /* Non-Blocking mode: Interrupt */
00644 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00645 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00646
00647 /* ############################## Counter Mode ###############################*/
00648 /* Blocking mode: Polling */
00649 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00650 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00651 /* Non-Blocking mode: Interrupt */
00652 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00653 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00654 /**
00655   * @}
00656   */
00657
00658 /** @addtogroup LPTIM_Exported_Functions_Group3
00659   *  @brief  Read operation functions.
00660   * @{
00661   */
00662 /* Reading operation functions ************************************************/
00663 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
00664 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
00665 uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
00666 /**
00667   * @}
00668   */
00669
00670 /** @addtogroup LPTIM_Exported_Functions_Group4
00671   *  @brief  LPTIM IRQ handler and callback functions.
00672   * @{
00673   */
00674 /* LPTIM IRQ functions  *******************************************************/
00675 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00676
00677 /* CallBack functions  ********************************************************/
00678 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00679 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00680 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00681 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00682 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00683 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00684 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00685
00686 /* Callbacks Register/UnRegister functions  ***********************************/
00687 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00688 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
00689                                              pLPTIM_CallbackTypeDef pCallback);
00690 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
00691 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00692 /**
00693   * @}
00694   */
00695
00696 /** @addtogroup LPTIM_Group5
00697   *  @brief   Peripheral State functions.
00698   * @{
00699   */
00700 /* Peripheral State functions  ************************************************/
00701 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
00702 /**
00703   * @}
00704   */
00705
00706 /**
00707   * @}
00708   */
00709
00710 /* Private types -------------------------------------------------------------*/
00711 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00712   * @{
00713   */
00714
00715 /**
00716   * @}
00717   */
00718
00719 /* Private variables ---------------------------------------------------------*/
00720 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00721   * @{
00722   */
00723
00724 /**
00725   * @}
00726   */
00727
00728 /* Private constants ---------------------------------------------------------*/
00729 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00730   * @{
00731   */
00732
00733 /**
00734   * @}
00735   */
00736
00737 /* Private macros ------------------------------------------------------------*/
00738 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00739   * @{
00740   */
00741
00742 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00743                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00744
00745
00746 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00747                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00748                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00749                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00750                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00751                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00752                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00753                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00754
00755 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00756
00757 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00758                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00759
00760 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00761                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00762                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00763                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00764
00765 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00766                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00767                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00768
00769 #if defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
00770 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00771                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00772                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00773                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00774                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00775                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00776                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00777                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00778                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
00779                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
00780                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_9) || \
00781                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_10)|| \
00782                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_11)|| \
00783                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_12))
00784 #else
00785 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00786                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00787                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00788                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00789                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00790                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00791                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00792                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00793                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
00794                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
00795                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_9))
00796 #endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
00797
00798 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00799                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00800                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00801
00802 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00803                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00804                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00805                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00806
00807 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00808                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00809
00810 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00811                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00812
00813 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
00814
00815 #define IS_LPTIM_PERIOD(__PERIOD__)             ((0x00000001UL <= (__PERIOD__)) &&\
00816                                                  ((__PERIOD__) <= 0x0000FFFFUL))
00817
00818 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
00819
00820 #if defined(COMP5) && defined(COMP6) && defined(COMP7)
00821 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00822   ((((__INSTANCE__) == LPTIM1) &&                       \
00823     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00824      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||        \
00825      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) ||        \
00826      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) ||        \
00827      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7))))
00828 #else
00829 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00830   ((((__INSTANCE__) == LPTIM1) &&                       \
00831     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00832      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||        \
00833      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))
00834 #endif /* COMP5 && COMP6 && COMP7 */
00835
00836 #if defined(COMP5) && defined(COMP6) && defined(COMP7)
00837 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00838   (((__INSTANCE__) == LPTIM1) &&                       \
00839    (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00840     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) ||        \
00841     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) ||        \
00842     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6)))
00843 #else
00844 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00845   (((__INSTANCE__) == LPTIM1) &&                       \
00846    (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00847     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) ||        \
00848     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))
00849 #endif /* COMP5 && COMP6 && COMP7 */
00850
00851 /**
00852   * @}
00853   */
00854
00855 /* Private functions ---------------------------------------------------------*/
00856 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00857   * @{
00858   */
00859 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
00860 /**
00861   * @}
00862   */
00863
00864 /**
00865   * @}
00866   */
00867
00868
00869 /**
00870   * @}
00871   */
00872
00873 #ifdef __cplusplus
00874 }
00875 #endif
00876
00877 #endif /* STM32G4xx_HAL_LPTIM_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nand.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_nand.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @brief   NAND HAL module driver.
00006   *          This file provides a generic firmware to drive NAND memories mounted
00007   *          as external device.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   @verbatim
00021   ==============================================================================
00022                          ##### How to use this driver #####
00023   ==============================================================================
00024     [..]
00025       This driver is a generic layered driver which contains a set of APIs used to
00026       control NAND flash memories. It uses the FMC layer functions to interface
00027       with NAND devices. This driver is used as follows:
00028
00029       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00030           with control and timing parameters for both common and attribute spaces.
00031
00032       (+) Read NAND flash memory maker and device IDs using the function
00033           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00034           structure declared by the function caller.
00035
00036       (+) Access NAND flash memory by read/write operations using the functions
00037           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
00038           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
00039           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
00040           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
00041           to read/write page(s)/spare area(s). These functions use specific device
00042           information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
00043           structure. The read/write address information is contained by the Nand_Address_Typedef
00044           structure passed as parameter.
00045
00046       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00047
00048       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00049           The erase block address information is contained in the Nand_Address_Typedef
00050           structure passed as parameter.
00051
00052       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00053
00054       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00055           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00056           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00057
00058       (+) You can monitor the NAND device HAL state by calling the function
00059           HAL_NAND_GetState()
00060
00061     [..]
00062       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00063           If a NAND flash device contains different operations and/or implementations,
00064           it should be implemented separately.
00065
00066     *** Callback registration ***
00067     =============================================
00068     [..]
00069       The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
00070       allows the user to configure dynamically the driver callbacks.
00071
00072       Use Functions HAL_NAND_RegisterCallback() to register a user callback,
00073       it allows to register following callbacks:
00074         (+) MspInitCallback    : NAND MspInit.
00075         (+) MspDeInitCallback  : NAND MspDeInit.
00076       This function takes as parameters the HAL peripheral handle, the Callback ID
00077       and a pointer to the user callback function.
00078
00079       Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
00080       weak (overridden) function. It allows to reset following callbacks:
00081         (+) MspInitCallback    : NAND MspInit.
00082         (+) MspDeInitCallback  : NAND MspDeInit.
00083       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00084
00085       By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
00086       all callbacks are reset to the corresponding legacy weak (overridden) functions.
00087       Exception done for MspInit and MspDeInit callbacks that are respectively
00088       reset to the legacy weak (overridden) functions in the HAL_NAND_Init
00089       and  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
00090       If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
00091       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00092
00093       Callbacks can be registered/unregistered in READY state only.
00094       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00095       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00096       during the Init/DeInit.
00097       In that case first register the MspInit/MspDeInit user callbacks
00098       using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
00099       or HAL_NAND_Init function.
00100
00101       When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
00102       not defined, the callback registering feature is not available
00103       and weak (overridden) callbacks are used.
00104
00105   @endverbatim
00106   ******************************************************************************
00107   */
00108
00109 /* Includes ------------------------------------------------------------------*/
00110 #include "stm32g4xx_hal.h"
00111
00112 #if defined(FMC_BANK3)
00113
00114 /** @addtogroup STM32G4xx_HAL_Driver
00115   * @{
00116   */
00117
00118 #ifdef HAL_NAND_MODULE_ENABLED
00119
00120 /** @defgroup NAND NAND
00121   * @brief NAND HAL module driver
00122   * @{
00123   */
00124
00125 /* Private typedef -----------------------------------------------------------*/
00126 /* Private Constants ------------------------------------------------------------*/
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130 /* Exported functions ---------------------------------------------------------*/
00131
00132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00133   * @{
00134   */
00135
00136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00137   * @brief    Initialization and Configuration functions
00138   *
00139   @verbatim
00140   ==============================================================================
00141             ##### NAND Initialization and de-initialization functions #####
00142   ==============================================================================
00143   [..]
00144     This section provides functions allowing to initialize/de-initialize
00145     the NAND memory
00146
00147 @endverbatim
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Perform NAND memory Initialization sequence
00153   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00154   *                the configuration information for NAND module.
00155   * @param  ComSpace_Timing pointer to Common space timing structure
00156   * @param  AttSpace_Timing pointer to Attribute space timing structure
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
00160                                  FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00161 {
00162   /* Check the NAND handle state */
00163   if (hnand == NULL)
00164   {
00165     return HAL_ERROR;
00166   }
00167
00168   if (hnand->State == HAL_NAND_STATE_RESET)
00169   {
00170     /* Allocate lock resource and initialize it */
00171     hnand->Lock = HAL_UNLOCKED;
00172
00173 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00174     if (hnand->MspInitCallback == NULL)
00175     {
00176       hnand->MspInitCallback = HAL_NAND_MspInit;
00177     }
00178     hnand->ItCallback = HAL_NAND_ITCallback;
00179
00180     /* Init the low level hardware */
00181     hnand->MspInitCallback(hnand);
00182 #else
00183     /* Initialize the low level hardware (MSP) */
00184     HAL_NAND_MspInit(hnand);
00185 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00186   }
00187
00188   /* Initialize NAND control Interface */
00189   (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00190
00191   /* Initialize NAND common space timing Interface */
00192   (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00193
00194   /* Initialize NAND attribute space timing Interface */
00195   (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00196
00197   /* Enable the NAND device */
00198   __FMC_NAND_ENABLE(hnand->Instance);
00199
00200   /* Update the NAND controller state */
00201   hnand->State = HAL_NAND_STATE_READY;
00202
00203   return HAL_OK;
00204 }
00205
00206 /**
00207   * @brief  Perform NAND memory De-Initialization sequence
00208   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00209   *                the configuration information for NAND module.
00210   * @retval HAL status
00211   */
00212 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00213 {
00214 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00215   if (hnand->MspDeInitCallback == NULL)
00216   {
00217     hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
00218   }
00219
00220   /* DeInit the low level hardware */
00221   hnand->MspDeInitCallback(hnand);
00222 #else
00223   /* Initialize the low level hardware (MSP) */
00224   HAL_NAND_MspDeInit(hnand);
00225 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00226
00227   /* Configure the NAND registers with their reset values */
00228   (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00229
00230   /* Reset the NAND controller state */
00231   hnand->State = HAL_NAND_STATE_RESET;
00232
00233   /* Release Lock */
00234   __HAL_UNLOCK(hnand);
00235
00236   return HAL_OK;
00237 }
00238
00239 /**
00240   * @brief  NAND MSP Init
00241   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00242   *                the configuration information for NAND module.
00243   * @retval None
00244   */
00245 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00246 {
00247   /* Prevent unused argument(s) compilation warning */
00248   UNUSED(hnand);
00249
00250   /* NOTE : This function Should not be modified, when the callback is needed,
00251             the HAL_NAND_MspInit could be implemented in the user file
00252    */
00253 }
00254
00255 /**
00256   * @brief  NAND MSP DeInit
00257   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00258   *                the configuration information for NAND module.
00259   * @retval None
00260   */
00261 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00262 {
00263   /* Prevent unused argument(s) compilation warning */
00264   UNUSED(hnand);
00265
00266   /* NOTE : This function Should not be modified, when the callback is needed,
00267             the HAL_NAND_MspDeInit could be implemented in the user file
00268    */
00269 }
00270
00271
00272 /**
00273   * @brief  This function handles NAND device interrupt request.
00274   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00275   *                the configuration information for NAND module.
00276   * @retval HAL status
00277   */
00278 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00279 {
00280   /* Check NAND interrupt Rising edge flag */
00281   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00282   {
00283     /* NAND interrupt callback*/
00284 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00285     hnand->ItCallback(hnand);
00286 #else
00287     HAL_NAND_ITCallback(hnand);
00288 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00289
00290     /* Clear NAND interrupt Rising edge pending bit */
00291     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
00292   }
00293
00294   /* Check NAND interrupt Level flag */
00295   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00296   {
00297     /* NAND interrupt callback*/
00298 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00299     hnand->ItCallback(hnand);
00300 #else
00301     HAL_NAND_ITCallback(hnand);
00302 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00303
00304     /* Clear NAND interrupt Level pending bit */
00305     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
00306   }
00307
00308   /* Check NAND interrupt Falling edge flag */
00309   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00310   {
00311     /* NAND interrupt callback*/
00312 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00313     hnand->ItCallback(hnand);
00314 #else
00315     HAL_NAND_ITCallback(hnand);
00316 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00317
00318     /* Clear NAND interrupt Falling edge pending bit */
00319     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
00320   }
00321
00322   /* Check NAND interrupt FIFO empty flag */
00323   if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00324   {
00325     /* NAND interrupt callback*/
00326 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00327     hnand->ItCallback(hnand);
00328 #else
00329     HAL_NAND_ITCallback(hnand);
00330 #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
00331
00332     /* Clear NAND interrupt FIFO empty pending bit */
00333     __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
00334   }
00335
00336 }
00337
00338 /**
00339   * @brief  NAND interrupt feature callback
00340   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00341   *                the configuration information for NAND module.
00342   * @retval None
00343   */
00344 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00345 {
00346   /* Prevent unused argument(s) compilation warning */
00347   UNUSED(hnand);
00348
00349   /* NOTE : This function Should not be modified, when the callback is needed,
00350             the HAL_NAND_ITCallback could be implemented in the user file
00351    */
00352 }
00353
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00359   * @brief    Input Output and memory control functions
00360   *
00361   @verbatim
00362   ==============================================================================
00363                     ##### NAND Input and Output functions #####
00364   ==============================================================================
00365   [..]
00366     This section provides functions allowing to use and control the NAND
00367     memory
00368
00369 @endverbatim
00370   * @{
00371   */
00372
00373 /**
00374   * @brief  Read the NAND memory electronic signature
00375   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00376   *                the configuration information for NAND module.
00377   * @param  pNAND_ID NAND ID structure
00378   * @retval HAL status
00379   */
00380 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00381 {
00382   __IO uint32_t data = 0;
00383   __IO uint32_t data1 = 0;
00384   uint32_t deviceaddress;
00385
00386   /* Check the NAND controller state */
00387   if (hnand->State == HAL_NAND_STATE_BUSY)
00388   {
00389     return HAL_BUSY;
00390   }
00391   else if (hnand->State == HAL_NAND_STATE_READY)
00392   {
00393     /* Process Locked */
00394     __HAL_LOCK(hnand);
00395
00396     /* Update the NAND controller state */
00397     hnand->State = HAL_NAND_STATE_BUSY;
00398
00399     /* Identify the device address */
00400     deviceaddress = NAND_DEVICE;
00401
00402     /* Send Read ID command sequence */
00403     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
00404     __DSB();
00405     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00406     __DSB();
00407
00408     /* Read the electronic signature from NAND flash */
00409     if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
00410     {
00411       data = *(__IO uint32_t *)deviceaddress;
00412
00413       /* Return the data read */
00414       pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00415       pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00416       pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00417       pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00418     }
00419     else
00420     {
00421       data = *(__IO uint32_t *)deviceaddress;
00422       data1 = *((__IO uint32_t *)deviceaddress + 4);
00423
00424       /* Return the data read */
00425       pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00426       pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
00427       pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
00428       pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
00429     }
00430
00431     /* Update the NAND controller state */
00432     hnand->State = HAL_NAND_STATE_READY;
00433
00434     /* Process unlocked */
00435     __HAL_UNLOCK(hnand);
00436   }
00437   else
00438   {
00439     return HAL_ERROR;
00440   }
00441
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @brief  NAND memory reset
00447   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00448   *                the configuration information for NAND module.
00449   * @retval HAL status
00450   */
00451 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00452 {
00453   uint32_t deviceaddress;
00454
00455   /* Check the NAND controller state */
00456   if (hnand->State == HAL_NAND_STATE_BUSY)
00457   {
00458     return HAL_BUSY;
00459   }
00460   else if (hnand->State == HAL_NAND_STATE_READY)
00461   {
00462     /* Process Locked */
00463     __HAL_LOCK(hnand);
00464
00465     /* Update the NAND controller state */
00466     hnand->State = HAL_NAND_STATE_BUSY;
00467
00468     /* Identify the device address */
00469     deviceaddress = NAND_DEVICE;
00470
00471     /* Send NAND reset command */
00472     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
00473
00474     /* Update the NAND controller state */
00475     hnand->State = HAL_NAND_STATE_READY;
00476
00477     /* Process unlocked */
00478     __HAL_UNLOCK(hnand);
00479   }
00480   else
00481   {
00482     return HAL_ERROR;
00483   }
00484
00485   return HAL_OK;
00486
00487 }
00488
00489 /**
00490   * @brief  Configure the device: Enter the physical parameters of the device
00491   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00492   *                the configuration information for NAND module.
00493   * @param  pDeviceConfig  pointer to NAND_DeviceConfigTypeDef structure
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
00497 {
00498   hnand->Config.PageSize           = pDeviceConfig->PageSize;
00499   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
00500   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
00501   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
00502   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
00503   hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
00504   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
00505
00506   return HAL_OK;
00507 }
00508
00509 /**
00510   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
00511   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00512   *                the configuration information for NAND module.
00513   * @param  pAddress  pointer to NAND address structure
00514   * @param  pBuffer  pointer to destination read buffer
00515   * @param  NumPageToRead  number of pages to read from block
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00519                                         uint8_t *pBuffer, uint32_t NumPageToRead)
00520 {
00521   uint32_t index;
00522   uint32_t tickstart;
00523   uint32_t deviceaddress;
00524   uint32_t numpagesread = 0U;
00525   uint32_t nandaddress;
00526   uint32_t nbpages = NumPageToRead;
00527   uint8_t *buff = pBuffer;
00528
00529   /* Check the NAND controller state */
00530   if (hnand->State == HAL_NAND_STATE_BUSY)
00531   {
00532     return HAL_BUSY;
00533   }
00534   else if (hnand->State == HAL_NAND_STATE_READY)
00535   {
00536     /* Process Locked */
00537     __HAL_LOCK(hnand);
00538
00539     /* Update the NAND controller state */
00540     hnand->State = HAL_NAND_STATE_BUSY;
00541
00542     /* Identify the device address */
00543     deviceaddress = NAND_DEVICE;
00544
00545     /* NAND raw address calculation */
00546     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00547
00548     /* Page(s) read loop */
00549     while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00550     {
00551       /* Send read page command sequence */
00552       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00553       __DSB();
00554
00555       /* Cards with page size <= 512 bytes */
00556       if ((hnand->Config.PageSize) <= 512U)
00557       {
00558         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00559         {
00560           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00561           __DSB();
00562           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00563           __DSB();
00564           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00565           __DSB();
00566         }
00567         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00568         {
00569           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00570           __DSB();
00571           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00572           __DSB();
00573           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00574           __DSB();
00575           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00576           __DSB();
00577         }
00578       }
00579       else /* (hnand->Config.PageSize) > 512 */
00580       {
00581         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00582         {
00583           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00584           __DSB();
00585           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00586           __DSB();
00587           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00588           __DSB();
00589           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00590           __DSB();
00591         }
00592         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00593         {
00594           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00595           __DSB();
00596           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00597           __DSB();
00598           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00599           __DSB();
00600           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00601           __DSB();
00602           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00603           __DSB();
00604         }
00605       }
00606
00607       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00608       __DSB();
00609
00610
00611       if (hnand->Config.ExtraCommandEnable == ENABLE)
00612       {
00613         /* Get tick */
00614         tickstart = HAL_GetTick();
00615
00616         /* Read status until NAND is ready */
00617         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00618         {
00619           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00620           {
00621             /* Update the NAND controller state */
00622             hnand->State = HAL_NAND_STATE_ERROR;
00623
00624             /* Process unlocked */
00625             __HAL_UNLOCK(hnand);
00626
00627             return HAL_TIMEOUT;
00628           }
00629         }
00630
00631         /* Go back to read mode */
00632         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00633         __DSB();
00634       }
00635
00636       /* Get Data into Buffer */
00637       for (index = 0U; index < hnand->Config.PageSize; index++)
00638       {
00639         *buff = *(uint8_t *)deviceaddress;
00640         buff++;
00641       }
00642
00643       /* Increment read pages number */
00644       numpagesread++;
00645
00646       /* Decrement pages to read */
00647       nbpages--;
00648
00649       /* Increment the NAND address */
00650       nandaddress = (uint32_t)(nandaddress + 1U);
00651     }
00652
00653     /* Update the NAND controller state */
00654     hnand->State = HAL_NAND_STATE_READY;
00655
00656     /* Process unlocked */
00657     __HAL_UNLOCK(hnand);
00658   }
00659   else
00660   {
00661     return HAL_ERROR;
00662   }
00663
00664   return HAL_OK;
00665 }
00666
00667 /**
00668   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
00669   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00670   *                the configuration information for NAND module.
00671   * @param  pAddress  pointer to NAND address structure
00672   * @param  pBuffer  pointer to destination read buffer. pBuffer should be 16bits aligned
00673   * @param  NumPageToRead  number of pages to read from block
00674   * @retval HAL status
00675   */
00676 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00677                                          uint16_t *pBuffer, uint32_t NumPageToRead)
00678 {
00679   uint32_t index;
00680   uint32_t tickstart;
00681   uint32_t deviceaddress;
00682   uint32_t numpagesread = 0U;
00683   uint32_t nandaddress;
00684   uint32_t nbpages = NumPageToRead;
00685   uint16_t *buff = pBuffer;
00686
00687   /* Check the NAND controller state */
00688   if (hnand->State == HAL_NAND_STATE_BUSY)
00689   {
00690     return HAL_BUSY;
00691   }
00692   else if (hnand->State == HAL_NAND_STATE_READY)
00693   {
00694     /* Process Locked */
00695     __HAL_LOCK(hnand);
00696
00697     /* Update the NAND controller state */
00698     hnand->State = HAL_NAND_STATE_BUSY;
00699
00700     /* Identify the device address */
00701     deviceaddress = NAND_DEVICE;
00702
00703     /* NAND raw address calculation */
00704     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00705
00706     /* Page(s) read loop */
00707     while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00708     {
00709       /* Send read page command sequence */
00710       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00711       __DSB();
00712
00713       /* Cards with page size <= 512 bytes */
00714       if ((hnand->Config.PageSize) <= 512U)
00715       {
00716         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00717         {
00718           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00719           __DSB();
00720           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00721           __DSB();
00722           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00723           __DSB();
00724         }
00725         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00726         {
00727           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00728           __DSB();
00729           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00730           __DSB();
00731           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00732           __DSB();
00733           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00734           __DSB();
00735         }
00736       }
00737       else /* (hnand->Config.PageSize) > 512 */
00738       {
00739         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00740         {
00741           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00742           __DSB();
00743           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00744           __DSB();
00745           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00746           __DSB();
00747           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00748           __DSB();
00749         }
00750         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00751         {
00752           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00753           __DSB();
00754           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00755           __DSB();
00756           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00757           __DSB();
00758           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00759           __DSB();
00760           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00761           __DSB();
00762         }
00763       }
00764
00765       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00766       __DSB();
00767
00768       if (hnand->Config.ExtraCommandEnable == ENABLE)
00769       {
00770         /* Get tick */
00771         tickstart = HAL_GetTick();
00772
00773         /* Read status until NAND is ready */
00774         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00775         {
00776           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00777           {
00778             /* Update the NAND controller state */
00779             hnand->State = HAL_NAND_STATE_ERROR;
00780
00781             /* Process unlocked */
00782             __HAL_UNLOCK(hnand);
00783
00784             return HAL_TIMEOUT;
00785           }
00786         }
00787
00788         /* Go back to read mode */
00789         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00790         __DSB();
00791       }
00792
00793       /* Calculate PageSize */
00794       if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
00795       {
00796         hnand->Config.PageSize = hnand->Config.PageSize / 2U;
00797       }
00798       else
00799       {
00800         /* Do nothing */
00801         /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
00802       }
00803
00804       /* Get Data into Buffer */
00805       for (index = 0U; index < hnand->Config.PageSize; index++)
00806       {
00807         *buff = *(uint16_t *)deviceaddress;
00808         buff++;
00809       }
00810
00811       /* Increment read pages number */
00812       numpagesread++;
00813
00814       /* Decrement pages to read */
00815       nbpages--;
00816
00817       /* Increment the NAND address */
00818       nandaddress = (uint32_t)(nandaddress + 1U);
00819     }
00820
00821     /* Update the NAND controller state */
00822     hnand->State = HAL_NAND_STATE_READY;
00823
00824     /* Process unlocked */
00825     __HAL_UNLOCK(hnand);
00826   }
00827   else
00828   {
00829     return HAL_ERROR;
00830   }
00831
00832   return HAL_OK;
00833 }
00834
00835 /**
00836   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
00837   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00838   *                the configuration information for NAND module.
00839   * @param  pAddress  pointer to NAND address structure
00840   * @param  pBuffer  pointer to source buffer to write
00841   * @param  NumPageToWrite   number of pages to write to block
00842   * @retval HAL status
00843   */
00844 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00845                                          const uint8_t *pBuffer, uint32_t NumPageToWrite)
00846 {
00847   uint32_t index;
00848   uint32_t tickstart;
00849   uint32_t deviceaddress;
00850   uint32_t numpageswritten = 0U;
00851   uint32_t nandaddress;
00852   uint32_t nbpages = NumPageToWrite;
00853   const uint8_t *buff = pBuffer;
00854
00855   /* Check the NAND controller state */
00856   if (hnand->State == HAL_NAND_STATE_BUSY)
00857   {
00858     return HAL_BUSY;
00859   }
00860   else if (hnand->State == HAL_NAND_STATE_READY)
00861   {
00862     /* Process Locked */
00863     __HAL_LOCK(hnand);
00864
00865     /* Update the NAND controller state */
00866     hnand->State = HAL_NAND_STATE_BUSY;
00867
00868     /* Identify the device address */
00869     deviceaddress = NAND_DEVICE;
00870
00871     /* NAND raw address calculation */
00872     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00873
00874     /* Page(s) write loop */
00875     while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00876     {
00877       /* Send write page command sequence */
00878       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00879       __DSB();
00880       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00881       __DSB();
00882
00883       /* Cards with page size <= 512 bytes */
00884       if ((hnand->Config.PageSize) <= 512U)
00885       {
00886         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00887         {
00888           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00889           __DSB();
00890           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00891           __DSB();
00892           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00893           __DSB();
00894         }
00895         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00896         {
00897           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00898           __DSB();
00899           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00900           __DSB();
00901           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00902           __DSB();
00903           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00904           __DSB();
00905         }
00906       }
00907       else /* (hnand->Config.PageSize) > 512 */
00908       {
00909         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
00910         {
00911           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00912           __DSB();
00913           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00914           __DSB();
00915           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00916           __DSB();
00917           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00918           __DSB();
00919         }
00920         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00921         {
00922           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00923           __DSB();
00924           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00925           __DSB();
00926           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00927           __DSB();
00928           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00929           __DSB();
00930           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00931           __DSB();
00932         }
00933       }
00934
00935       /* Write data to memory */
00936       for (index = 0U; index < hnand->Config.PageSize; index++)
00937       {
00938         *(__IO uint8_t *)deviceaddress = *buff;
00939         buff++;
00940         __DSB();
00941       }
00942
00943       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00944       __DSB();
00945
00946       /* Get tick */
00947       tickstart = HAL_GetTick();
00948
00949       /* Read status until NAND is ready */
00950       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
00951       {
00952         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
00953         {
00954           /* Update the NAND controller state */
00955           hnand->State = HAL_NAND_STATE_ERROR;
00956
00957           /* Process unlocked */
00958           __HAL_UNLOCK(hnand);
00959
00960           return HAL_TIMEOUT;
00961         }
00962       }
00963
00964       /* Increment written pages number */
00965       numpageswritten++;
00966
00967       /* Decrement pages to write */
00968       nbpages--;
00969
00970       /* Increment the NAND address */
00971       nandaddress = (uint32_t)(nandaddress + 1U);
00972     }
00973
00974     /* Update the NAND controller state */
00975     hnand->State = HAL_NAND_STATE_READY;
00976
00977     /* Process unlocked */
00978     __HAL_UNLOCK(hnand);
00979   }
00980   else
00981   {
00982     return HAL_ERROR;
00983   }
00984
00985   return HAL_OK;
00986 }
00987
00988 /**
00989   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
00990   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
00991   *                the configuration information for NAND module.
00992   * @param  pAddress  pointer to NAND address structure
00993   * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned
00994   * @param  NumPageToWrite   number of pages to write to block
00995   * @retval HAL status
00996   */
00997 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00998                                           const uint16_t *pBuffer, uint32_t NumPageToWrite)
00999 {
01000   uint32_t index;
01001   uint32_t tickstart;
01002   uint32_t deviceaddress;
01003   uint32_t numpageswritten = 0U;
01004   uint32_t nandaddress;
01005   uint32_t nbpages = NumPageToWrite;
01006   const uint16_t *buff = pBuffer;
01007
01008   /* Check the NAND controller state */
01009   if (hnand->State == HAL_NAND_STATE_BUSY)
01010   {
01011     return HAL_BUSY;
01012   }
01013   else if (hnand->State == HAL_NAND_STATE_READY)
01014   {
01015     /* Process Locked */
01016     __HAL_LOCK(hnand);
01017
01018     /* Update the NAND controller state */
01019     hnand->State = HAL_NAND_STATE_BUSY;
01020
01021     /* Identify the device address */
01022     deviceaddress = NAND_DEVICE;
01023
01024     /* NAND raw address calculation */
01025     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01026
01027     /* Page(s) write loop */
01028     while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01029     {
01030       /* Send write page command sequence */
01031       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01032       __DSB();
01033       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01034       __DSB();
01035
01036       /* Cards with page size <= 512 bytes */
01037       if ((hnand->Config.PageSize) <= 512U)
01038       {
01039         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01040         {
01041           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01042           __DSB();
01043           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01044           __DSB();
01045           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01046           __DSB();
01047         }
01048         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01049         {
01050           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01051           __DSB();
01052           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01053           __DSB();
01054           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01055           __DSB();
01056           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01057           __DSB();
01058         }
01059       }
01060       else /* (hnand->Config.PageSize) > 512 */
01061       {
01062         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01063         {
01064           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01065           __DSB();
01066           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01067           __DSB();
01068           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01069           __DSB();
01070           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01071           __DSB();
01072         }
01073         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01074         {
01075           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01076           __DSB();
01077           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01078           __DSB();
01079           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01080           __DSB();
01081           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01082           __DSB();
01083           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01084           __DSB();
01085         }
01086       }
01087
01088       /* Calculate PageSize */
01089       if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
01090       {
01091         hnand->Config.PageSize = hnand->Config.PageSize / 2U;
01092       }
01093       else
01094       {
01095         /* Do nothing */
01096         /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
01097       }
01098
01099       /* Write data to memory */
01100       for (index = 0U; index < hnand->Config.PageSize; index++)
01101       {
01102         *(__IO uint16_t *)deviceaddress = *buff;
01103         buff++;
01104         __DSB();
01105       }
01106
01107       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01108       __DSB();
01109
01110       /* Get tick */
01111       tickstart = HAL_GetTick();
01112
01113       /* Read status until NAND is ready */
01114       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01115       {
01116         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01117         {
01118           /* Update the NAND controller state */
01119           hnand->State = HAL_NAND_STATE_ERROR;
01120
01121           /* Process unlocked */
01122           __HAL_UNLOCK(hnand);
01123
01124           return HAL_TIMEOUT;
01125         }
01126       }
01127
01128       /* Increment written pages number */
01129       numpageswritten++;
01130
01131       /* Decrement pages to write */
01132       nbpages--;
01133
01134       /* Increment the NAND address */
01135       nandaddress = (uint32_t)(nandaddress + 1U);
01136     }
01137
01138     /* Update the NAND controller state */
01139     hnand->State = HAL_NAND_STATE_READY;
01140
01141     /* Process unlocked */
01142     __HAL_UNLOCK(hnand);
01143   }
01144   else
01145   {
01146     return HAL_ERROR;
01147   }
01148
01149   return HAL_OK;
01150 }
01151
01152 /**
01153   * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
01154   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01155   *                the configuration information for NAND module.
01156   * @param  pAddress  pointer to NAND address structure
01157   * @param  pBuffer pointer to source buffer to write
01158   * @param  NumSpareAreaToRead Number of spare area to read
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
01162                                              uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
01163 {
01164   uint32_t index;
01165   uint32_t tickstart;
01166   uint32_t deviceaddress;
01167   uint32_t numsparearearead = 0U;
01168   uint32_t nandaddress;
01169   uint32_t columnaddress;
01170   uint32_t nbspare = NumSpareAreaToRead;
01171   uint8_t *buff = pBuffer;
01172
01173   /* Check the NAND controller state */
01174   if (hnand->State == HAL_NAND_STATE_BUSY)
01175   {
01176     return HAL_BUSY;
01177   }
01178   else if (hnand->State == HAL_NAND_STATE_READY)
01179   {
01180     /* Process Locked */
01181     __HAL_LOCK(hnand);
01182
01183     /* Update the NAND controller state */
01184     hnand->State = HAL_NAND_STATE_BUSY;
01185
01186     /* Identify the device address */
01187     deviceaddress = NAND_DEVICE;
01188
01189     /* NAND raw address calculation */
01190     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01191
01192     /* Column in page address */
01193     columnaddress = COLUMN_ADDRESS(hnand);
01194
01195     /* Spare area(s) read loop */
01196     while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01197     {
01198       /* Cards with page size <= 512 bytes */
01199       if ((hnand->Config.PageSize) <= 512U)
01200       {
01201         /* Send read spare area command sequence */
01202         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01203         __DSB();
01204
01205         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01206         {
01207           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01208           __DSB();
01209           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01210           __DSB();
01211           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01212           __DSB();
01213         }
01214         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01215         {
01216           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01217           __DSB();
01218           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01219           __DSB();
01220           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01221           __DSB();
01222           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01223           __DSB();
01224         }
01225       }
01226       else /* (hnand->Config.PageSize) > 512 */
01227       {
01228         /* Send read spare area command sequence */
01229         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01230         __DSB();
01231
01232         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01233         {
01234           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01235           __DSB();
01236           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01237           __DSB();
01238           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01239           __DSB();
01240           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01241           __DSB();
01242         }
01243         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01244         {
01245           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01246           __DSB();
01247           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01248           __DSB();
01249           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01250           __DSB();
01251           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01252           __DSB();
01253           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01254           __DSB();
01255         }
01256       }
01257
01258       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01259       __DSB();
01260
01261       if (hnand->Config.ExtraCommandEnable == ENABLE)
01262       {
01263         /* Get tick */
01264         tickstart = HAL_GetTick();
01265
01266         /* Read status until NAND is ready */
01267         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01268         {
01269           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01270           {
01271             /* Update the NAND controller state */
01272             hnand->State = HAL_NAND_STATE_ERROR;
01273
01274             /* Process unlocked */
01275             __HAL_UNLOCK(hnand);
01276
01277             return HAL_TIMEOUT;
01278           }
01279         }
01280
01281         /* Go back to read mode */
01282         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01283         __DSB();
01284       }
01285
01286       /* Get Data into Buffer */
01287       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01288       {
01289         *buff = *(uint8_t *)deviceaddress;
01290         buff++;
01291       }
01292
01293       /* Increment read spare areas number */
01294       numsparearearead++;
01295
01296       /* Decrement spare areas to read */
01297       nbspare--;
01298
01299       /* Increment the NAND address */
01300       nandaddress = (uint32_t)(nandaddress + 1U);
01301     }
01302
01303     /* Update the NAND controller state */
01304     hnand->State = HAL_NAND_STATE_READY;
01305
01306     /* Process unlocked */
01307     __HAL_UNLOCK(hnand);
01308   }
01309   else
01310   {
01311     return HAL_ERROR;
01312   }
01313
01314   return HAL_OK;
01315 }
01316
01317 /**
01318   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
01319   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01320   *                the configuration information for NAND module.
01321   * @param  pAddress  pointer to NAND address structure
01322   * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
01323   * @param  NumSpareAreaToRead Number of spare area to read
01324   * @retval HAL status
01325   */
01326 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
01327                                               uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
01328 {
01329   uint32_t index;
01330   uint32_t tickstart;
01331   uint32_t deviceaddress;
01332   uint32_t numsparearearead = 0U;
01333   uint32_t nandaddress;
01334   uint32_t columnaddress;
01335   uint32_t nbspare = NumSpareAreaToRead;
01336   uint16_t *buff = pBuffer;
01337
01338   /* Check the NAND controller state */
01339   if (hnand->State == HAL_NAND_STATE_BUSY)
01340   {
01341     return HAL_BUSY;
01342   }
01343   else if (hnand->State == HAL_NAND_STATE_READY)
01344   {
01345     /* Process Locked */
01346     __HAL_LOCK(hnand);
01347
01348     /* Update the NAND controller state */
01349     hnand->State = HAL_NAND_STATE_BUSY;
01350
01351     /* Identify the device address */
01352     deviceaddress = NAND_DEVICE;
01353
01354     /* NAND raw address calculation */
01355     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01356
01357     /* Column in page address */
01358     columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
01359
01360     /* Spare area(s) read loop */
01361     while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01362     {
01363       /* Cards with page size <= 512 bytes */
01364       if ((hnand->Config.PageSize) <= 512U)
01365       {
01366         /* Send read spare area command sequence */
01367         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01368         __DSB();
01369
01370         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01371         {
01372           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01373           __DSB();
01374           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01375           __DSB();
01376           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01377           __DSB();
01378         }
01379         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01380         {
01381           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01382           __DSB();
01383           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01384           __DSB();
01385           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01386           __DSB();
01387           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01388           __DSB();
01389         }
01390       }
01391       else /* (hnand->Config.PageSize) > 512 */
01392       {
01393         /* Send read spare area command sequence */
01394         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01395         __DSB();
01396
01397         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01398         {
01399           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01400           __DSB();
01401           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01402           __DSB();
01403           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01404           __DSB();
01405           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01406           __DSB();
01407         }
01408         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01409         {
01410           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01411           __DSB();
01412           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01413           __DSB();
01414           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01415           __DSB();
01416           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01417           __DSB();
01418           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01419           __DSB();
01420         }
01421       }
01422
01423       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01424       __DSB();
01425
01426       if (hnand->Config.ExtraCommandEnable == ENABLE)
01427       {
01428         /* Get tick */
01429         tickstart = HAL_GetTick();
01430
01431         /* Read status until NAND is ready */
01432         while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01433         {
01434           if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01435           {
01436             /* Update the NAND controller state */
01437             hnand->State = HAL_NAND_STATE_ERROR;
01438
01439             /* Process unlocked */
01440             __HAL_UNLOCK(hnand);
01441
01442             return HAL_TIMEOUT;
01443           }
01444         }
01445
01446         /* Go back to read mode */
01447         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01448         __DSB();
01449       }
01450
01451       /* Get Data into Buffer */
01452       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01453       {
01454         *buff = *(uint16_t *)deviceaddress;
01455         buff++;
01456       }
01457
01458       /* Increment read spare areas number */
01459       numsparearearead++;
01460
01461       /* Decrement spare areas to read */
01462       nbspare--;
01463
01464       /* Increment the NAND address */
01465       nandaddress = (uint32_t)(nandaddress + 1U);
01466     }
01467
01468     /* Update the NAND controller state */
01469     hnand->State = HAL_NAND_STATE_READY;
01470
01471     /* Process unlocked */
01472     __HAL_UNLOCK(hnand);
01473   }
01474   else
01475   {
01476     return HAL_ERROR;
01477   }
01478
01479   return HAL_OK;
01480 }
01481
01482 /**
01483   * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
01484   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01485   *                the configuration information for NAND module.
01486   * @param  pAddress  pointer to NAND address structure
01487   * @param  pBuffer  pointer to source buffer to write
01488   * @param  NumSpareAreaTowrite   number of spare areas to write to block
01489   * @retval HAL status
01490   */
01491 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
01492                                               const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
01493 {
01494   uint32_t index;
01495   uint32_t tickstart;
01496   uint32_t deviceaddress;
01497   uint32_t numspareareawritten = 0U;
01498   uint32_t nandaddress;
01499   uint32_t columnaddress;
01500   uint32_t nbspare = NumSpareAreaTowrite;
01501   const uint8_t *buff = pBuffer;
01502
01503   /* Check the NAND controller state */
01504   if (hnand->State == HAL_NAND_STATE_BUSY)
01505   {
01506     return HAL_BUSY;
01507   }
01508   else if (hnand->State == HAL_NAND_STATE_READY)
01509   {
01510     /* Process Locked */
01511     __HAL_LOCK(hnand);
01512
01513     /* Update the NAND controller state */
01514     hnand->State = HAL_NAND_STATE_BUSY;
01515
01516     /* Identify the device address */
01517     deviceaddress = NAND_DEVICE;
01518
01519     /* Page address calculation */
01520     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01521
01522     /* Column in page address */
01523     columnaddress = COLUMN_ADDRESS(hnand);
01524
01525     /* Spare area(s) write loop */
01526     while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01527     {
01528       /* Cards with page size <= 512 bytes */
01529       if ((hnand->Config.PageSize) <= 512U)
01530       {
01531         /* Send write Spare area command sequence */
01532         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01533         __DSB();
01534         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01535         __DSB();
01536
01537         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01538         {
01539           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01540           __DSB();
01541           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01542           __DSB();
01543           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01544           __DSB();
01545         }
01546         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01547         {
01548           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01549           __DSB();
01550           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01551           __DSB();
01552           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01553           __DSB();
01554           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01555           __DSB();
01556         }
01557       }
01558       else /* (hnand->Config.PageSize) > 512 */
01559       {
01560         /* Send write Spare area command sequence */
01561         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01562         __DSB();
01563         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01564         __DSB();
01565
01566         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01567         {
01568           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01569           __DSB();
01570           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01571           __DSB();
01572           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01573           __DSB();
01574           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01575           __DSB();
01576         }
01577         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01578         {
01579           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01580           __DSB();
01581           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01582           __DSB();
01583           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01584           __DSB();
01585           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01586           __DSB();
01587           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01588           __DSB();
01589         }
01590       }
01591
01592       /* Write data to memory */
01593       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01594       {
01595         *(__IO uint8_t *)deviceaddress = *buff;
01596         buff++;
01597         __DSB();
01598       }
01599
01600       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01601       __DSB();
01602
01603       /* Get tick */
01604       tickstart = HAL_GetTick();
01605
01606       /* Read status until NAND is ready */
01607       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01608       {
01609         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01610         {
01611           /* Update the NAND controller state */
01612           hnand->State = HAL_NAND_STATE_ERROR;
01613
01614           /* Process unlocked */
01615           __HAL_UNLOCK(hnand);
01616
01617           return HAL_TIMEOUT;
01618         }
01619       }
01620
01621       /* Increment written spare areas number */
01622       numspareareawritten++;
01623
01624       /* Decrement spare areas to write */
01625       nbspare--;
01626
01627       /* Increment the NAND address */
01628       nandaddress = (uint32_t)(nandaddress + 1U);
01629     }
01630
01631     /* Update the NAND controller state */
01632     hnand->State = HAL_NAND_STATE_READY;
01633
01634     /* Process unlocked */
01635     __HAL_UNLOCK(hnand);
01636   }
01637   else
01638   {
01639     return HAL_ERROR;
01640   }
01641
01642   return HAL_OK;
01643 }
01644
01645 /**
01646   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
01647   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01648   *                the configuration information for NAND module.
01649   * @param  pAddress  pointer to NAND address structure
01650   * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned.
01651   * @param  NumSpareAreaTowrite   number of spare areas to write to block
01652   * @retval HAL status
01653   */
01654 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
01655                                                const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
01656 {
01657   uint32_t index;
01658   uint32_t tickstart;
01659   uint32_t deviceaddress;
01660   uint32_t numspareareawritten = 0U;
01661   uint32_t nandaddress;
01662   uint32_t columnaddress;
01663   uint32_t nbspare = NumSpareAreaTowrite;
01664   const uint16_t *buff = pBuffer;
01665
01666   /* Check the NAND controller state */
01667   if (hnand->State == HAL_NAND_STATE_BUSY)
01668   {
01669     return HAL_BUSY;
01670   }
01671   else if (hnand->State == HAL_NAND_STATE_READY)
01672   {
01673     /* Process Locked */
01674     __HAL_LOCK(hnand);
01675
01676     /* Update the NAND controller state */
01677     hnand->State = HAL_NAND_STATE_BUSY;
01678
01679     /* Identify the device address */
01680     deviceaddress = NAND_DEVICE;
01681
01682     /* NAND raw address calculation */
01683     nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01684
01685     /* Column in page address */
01686     columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
01687
01688     /* Spare area(s) write loop */
01689     while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01690     {
01691       /* Cards with page size <= 512 bytes */
01692       if ((hnand->Config.PageSize) <= 512U)
01693       {
01694         /* Send write Spare area command sequence */
01695         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01696         __DSB();
01697         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01698         __DSB();
01699
01700         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01701         {
01702           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01703           __DSB();
01704           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01705           __DSB();
01706           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01707           __DSB();
01708         }
01709         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01710         {
01711           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
01712           __DSB();
01713           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01714           __DSB();
01715           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01716           __DSB();
01717           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01718           __DSB();
01719         }
01720       }
01721       else /* (hnand->Config.PageSize) > 512 */
01722       {
01723         /* Send write Spare area command sequence */
01724         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01725         __DSB();
01726         *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01727         __DSB();
01728
01729         if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
01730         {
01731           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01732           __DSB();
01733           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01734           __DSB();
01735           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01736           __DSB();
01737           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01738           __DSB();
01739         }
01740         else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01741         {
01742           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01743           __DSB();
01744           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01745           __DSB();
01746           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01747           __DSB();
01748           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01749           __DSB();
01750           *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01751           __DSB();
01752         }
01753       }
01754
01755       /* Write data to memory */
01756       for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
01757       {
01758         *(__IO uint16_t *)deviceaddress = *buff;
01759         buff++;
01760         __DSB();
01761       }
01762
01763       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01764       __DSB();
01765
01766       /* Get tick */
01767       tickstart = HAL_GetTick();
01768
01769       /* Read status until NAND is ready */
01770       while (HAL_NAND_Read_Status(hnand) != NAND_READY)
01771       {
01772         if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
01773         {
01774           /* Update the NAND controller state */
01775           hnand->State = HAL_NAND_STATE_ERROR;
01776
01777           /* Process unlocked */
01778           __HAL_UNLOCK(hnand);
01779
01780           return HAL_TIMEOUT;
01781         }
01782       }
01783
01784       /* Increment written spare areas number */
01785       numspareareawritten++;
01786
01787       /* Decrement spare areas to write */
01788       nbspare--;
01789
01790       /* Increment the NAND address */
01791       nandaddress = (uint32_t)(nandaddress + 1U);
01792     }
01793
01794     /* Update the NAND controller state */
01795     hnand->State = HAL_NAND_STATE_READY;
01796
01797     /* Process unlocked */
01798     __HAL_UNLOCK(hnand);
01799   }
01800   else
01801   {
01802     return HAL_ERROR;
01803   }
01804
01805   return HAL_OK;
01806 }
01807
01808 /**
01809   * @brief  NAND memory Block erase
01810   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01811   *                the configuration information for NAND module.
01812   * @param  pAddress  pointer to NAND address structure
01813   * @retval HAL status
01814   */
01815 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
01816 {
01817   uint32_t deviceaddress;
01818
01819   /* Check the NAND controller state */
01820   if (hnand->State == HAL_NAND_STATE_BUSY)
01821   {
01822     return HAL_BUSY;
01823   }
01824   else if (hnand->State == HAL_NAND_STATE_READY)
01825   {
01826     /* Process Locked */
01827     __HAL_LOCK(hnand);
01828
01829     /* Update the NAND controller state */
01830     hnand->State = HAL_NAND_STATE_BUSY;
01831
01832     /* Identify the device address */
01833     deviceaddress = NAND_DEVICE;
01834
01835     /* Send Erase block command sequence */
01836     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
01837     __DSB();
01838     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01839     __DSB();
01840     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01841     __DSB();
01842     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01843     __DSB();
01844
01845     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
01846     __DSB();
01847
01848     /* Update the NAND controller state */
01849     hnand->State = HAL_NAND_STATE_READY;
01850
01851     /* Process unlocked */
01852     __HAL_UNLOCK(hnand);
01853   }
01854   else
01855   {
01856     return HAL_ERROR;
01857   }
01858
01859   return HAL_OK;
01860 }
01861
01862 /**
01863   * @brief  Increment the NAND memory address
01864   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
01865   *                the configuration information for NAND module.
01866   * @param pAddress pointer to NAND address structure
01867   * @retval The new status of the increment address operation. It can be:
01868   *           - NAND_VALID_ADDRESS: When the new address is valid address
01869   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
01870   */
01871 uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01872 {
01873   uint32_t status = NAND_VALID_ADDRESS;
01874
01875   /* Increment page address */
01876   pAddress->Page++;
01877
01878   /* Check NAND address is valid */
01879   if (pAddress->Page == hnand->Config.BlockSize)
01880   {
01881     pAddress->Page = 0;
01882     pAddress->Block++;
01883
01884     if (pAddress->Block == hnand->Config.PlaneSize)
01885     {
01886       pAddress->Block = 0;
01887       pAddress->Plane++;
01888
01889       if (pAddress->Plane == (hnand->Config.PlaneNbr))
01890       {
01891         status = NAND_INVALID_ADDRESS;
01892       }
01893     }
01894   }
01895
01896   return (status);
01897 }
01898
01899 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
01900 /**
01901   * @brief  Register a User NAND Callback
01902   *         To be used to override the weak predefined callback
01903   * @param hnand : NAND handle
01904   * @param CallbackId : ID of the callback to be registered
01905   *        This parameter can be one of the following values:
01906   *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
01907   *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
01908   *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
01909   * @param pCallback : pointer to the Callback function
01910   * @retval status
01911   */
01912 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
01913                                             pNAND_CallbackTypeDef pCallback)
01914 {
01915   HAL_StatusTypeDef status = HAL_OK;
01916
01917   if (pCallback == NULL)
01918   {
01919     return HAL_ERROR;
01920   }
01921
01922   if (hnand->State == HAL_NAND_STATE_READY)
01923   {
01924     switch (CallbackId)
01925     {
01926       case HAL_NAND_MSP_INIT_CB_ID :
01927         hnand->MspInitCallback = pCallback;
01928         break;
01929       case HAL_NAND_MSP_DEINIT_CB_ID :
01930         hnand->MspDeInitCallback = pCallback;
01931         break;
01932       case HAL_NAND_IT_CB_ID :
01933         hnand->ItCallback = pCallback;
01934         break;
01935       default :
01936         /* update return status */
01937         status =  HAL_ERROR;
01938         break;
01939     }
01940   }
01941   else if (hnand->State == HAL_NAND_STATE_RESET)
01942   {
01943     switch (CallbackId)
01944     {
01945       case HAL_NAND_MSP_INIT_CB_ID :
01946         hnand->MspInitCallback = pCallback;
01947         break;
01948       case HAL_NAND_MSP_DEINIT_CB_ID :
01949         hnand->MspDeInitCallback = pCallback;
01950         break;
01951       default :
01952         /* update return status */
01953         status =  HAL_ERROR;
01954         break;
01955     }
01956   }
01957   else
01958   {
01959     /* update return status */
01960     status =  HAL_ERROR;
01961   }
01962
01963   return status;
01964 }
01965
01966 /**
01967   * @brief  Unregister a User NAND Callback
01968   *         NAND Callback is redirected to the weak predefined callback
01969   * @param hnand : NAND handle
01970   * @param CallbackId : ID of the callback to be unregistered
01971   *        This parameter can be one of the following values:
01972   *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
01973   *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
01974   *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
01975   * @retval status
01976   */
01977 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
01978 {
01979   HAL_StatusTypeDef status = HAL_OK;
01980
01981   if (hnand->State == HAL_NAND_STATE_READY)
01982   {
01983     switch (CallbackId)
01984     {
01985       case HAL_NAND_MSP_INIT_CB_ID :
01986         hnand->MspInitCallback = HAL_NAND_MspInit;
01987         break;
01988       case HAL_NAND_MSP_DEINIT_CB_ID :
01989         hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
01990         break;
01991       case HAL_NAND_IT_CB_ID :
01992         hnand->ItCallback = HAL_NAND_ITCallback;
01993         break;
01994       default :
01995         /* update return status */
01996         status =  HAL_ERROR;
01997         break;
01998     }
01999   }
02000   else if (hnand->State == HAL_NAND_STATE_RESET)
02001   {
02002     switch (CallbackId)
02003     {
02004       case HAL_NAND_MSP_INIT_CB_ID :
02005         hnand->MspInitCallback = HAL_NAND_MspInit;
02006         break;
02007       case HAL_NAND_MSP_DEINIT_CB_ID :
02008         hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
02009         break;
02010       default :
02011         /* update return status */
02012         status =  HAL_ERROR;
02013         break;
02014     }
02015   }
02016   else
02017   {
02018     /* update return status */
02019     status =  HAL_ERROR;
02020   }
02021
02022   return status;
02023 }
02024 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
02025
02026 /**
02027   * @}
02028   */
02029
02030 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
02031   *  @brief   management functions
02032   *
02033 @verbatim
02034   ==============================================================================
02035                          ##### NAND Control functions #####
02036   ==============================================================================
02037   [..]
02038     This subsection provides a set of functions allowing to control dynamically
02039     the NAND interface.
02040
02041 @endverbatim
02042   * @{
02043   */
02044
02045
02046 /**
02047   * @brief  Enables dynamically NAND ECC feature.
02048   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02049   *                the configuration information for NAND module.
02050   * @retval HAL status
02051   */
02052 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
02053 {
02054   /* Check the NAND controller state */
02055   if (hnand->State == HAL_NAND_STATE_BUSY)
02056   {
02057     return HAL_BUSY;
02058   }
02059   else if (hnand->State == HAL_NAND_STATE_READY)
02060   {
02061     /* Update the NAND state */
02062     hnand->State = HAL_NAND_STATE_BUSY;
02063
02064     /* Enable ECC feature */
02065     (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
02066
02067     /* Update the NAND state */
02068     hnand->State = HAL_NAND_STATE_READY;
02069   }
02070   else
02071   {
02072     return HAL_ERROR;
02073   }
02074
02075   return HAL_OK;
02076 }
02077
02078 /**
02079   * @brief  Disables dynamically FMC_NAND ECC feature.
02080   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02081   *                the configuration information for NAND module.
02082   * @retval HAL status
02083   */
02084 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
02085 {
02086   /* Check the NAND controller state */
02087   if (hnand->State == HAL_NAND_STATE_BUSY)
02088   {
02089     return HAL_BUSY;
02090   }
02091   else if (hnand->State == HAL_NAND_STATE_READY)
02092   {
02093     /* Update the NAND state */
02094     hnand->State = HAL_NAND_STATE_BUSY;
02095
02096     /* Disable ECC feature */
02097     (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
02098
02099     /* Update the NAND state */
02100     hnand->State = HAL_NAND_STATE_READY;
02101   }
02102   else
02103   {
02104     return HAL_ERROR;
02105   }
02106
02107   return HAL_OK;
02108 }
02109
02110 /**
02111   * @brief  Disables dynamically NAND ECC feature.
02112   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02113   *                the configuration information for NAND module.
02114   * @param  ECCval pointer to ECC value
02115   * @param  Timeout maximum timeout to wait
02116   * @retval HAL status
02117   */
02118 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
02119 {
02120   HAL_StatusTypeDef status;
02121
02122   /* Check the NAND controller state */
02123   if (hnand->State == HAL_NAND_STATE_BUSY)
02124   {
02125     return HAL_BUSY;
02126   }
02127   else if (hnand->State == HAL_NAND_STATE_READY)
02128   {
02129     /* Update the NAND state */
02130     hnand->State = HAL_NAND_STATE_BUSY;
02131
02132     /* Get NAND ECC value */
02133     status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
02134
02135     /* Update the NAND state */
02136     hnand->State = HAL_NAND_STATE_READY;
02137   }
02138   else
02139   {
02140     return HAL_ERROR;
02141   }
02142
02143   return status;
02144 }
02145
02146 /**
02147   * @}
02148   */
02149
02150
02151 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
02152   *  @brief   Peripheral State functions
02153   *
02154 @verbatim
02155   ==============================================================================
02156                          ##### NAND State functions #####
02157   ==============================================================================
02158   [..]
02159     This subsection permits to get in run-time the status of the NAND controller
02160     and the data flow.
02161
02162 @endverbatim
02163   * @{
02164   */
02165
02166 /**
02167   * @brief  return the NAND state
02168   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02169   *                the configuration information for NAND module.
02170   * @retval HAL state
02171   */
02172 HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
02173 {
02174   return hnand->State;
02175 }
02176
02177 /**
02178   * @brief  NAND memory read status
02179   * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
02180   *                the configuration information for NAND module.
02181   * @retval NAND status
02182   */
02183 uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
02184 {
02185   uint32_t data;
02186   uint32_t deviceaddress;
02187   UNUSED(hnand);
02188
02189   /* Identify the device address */
02190   deviceaddress = NAND_DEVICE;
02191
02192   /* Send Read status operation command */
02193   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
02194
02195   /* Read status register data */
02196   data = *(__IO uint8_t *)deviceaddress;
02197
02198   /* Return the status */
02199   if ((data & NAND_ERROR) == NAND_ERROR)
02200   {
02201     return NAND_ERROR;
02202   }
02203   else if ((data & NAND_READY) == NAND_READY)
02204   {
02205     return NAND_READY;
02206   }
02207   else
02208   {
02209     return NAND_BUSY;
02210   }
02211 }
02212
02213 /**
02214   * @}
02215   */
02216
02217 /**
02218   * @}
02219   */
02220
02221 /**
02222   * @}
02223   */
02224
02225 #endif /* HAL_NAND_MODULE_ENABLED  */
02226
02227 /**
02228   * @}
02229   */
02230
02231 #endif /* FMC_BANK3 */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nand.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_nand.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NAND HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_NAND_H
00021 #define STM32G4xx_HAL_NAND_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 #if defined(FMC_BANK3)
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32g4xx_ll_fmc.h"
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup NAND
00037   * @{
00038   */
00039
00040 /* Exported typedef ----------------------------------------------------------*/
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup NAND_Exported_Types NAND Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL NAND State structures definition
00048   */
00049 typedef enum
00050 {
00051   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00052   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00053   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00054   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00055 } HAL_NAND_StateTypeDef;
00056
00057 /**
00058   * @brief  NAND Memory electronic signature Structure definition
00059   */
00060 typedef struct
00061 {
00062   /*<! NAND memory electronic signature maker and device IDs */
00063
00064   uint8_t Maker_Id;
00065
00066   uint8_t Device_Id;
00067
00068   uint8_t Third_Id;
00069
00070   uint8_t Fourth_Id;
00071 } NAND_IDTypeDef;
00072
00073 /**
00074   * @brief  NAND Memory address Structure definition
00075   */
00076 typedef struct
00077 {
00078   uint16_t Page;   /*!< NAND memory Page address  */
00079
00080   uint16_t Plane;   /*!< NAND memory Zone address  */
00081
00082   uint16_t Block;  /*!< NAND memory Block address */
00083
00084 } NAND_AddressTypeDef;
00085
00086 /**
00087   * @brief  NAND Memory info Structure definition
00088   */
00089 typedef struct
00090 {
00091   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
00092                                               for 8 bits addressing or words for 16 bits addressing             */
00093
00094   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
00095                                               for 8 bits addressing or words for 16 bits addressing             */
00096
00097   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
00098
00099   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
00100
00101   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
00102
00103   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
00104
00105   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
00106                                               parameter is mandatory for some NAND parts after the read
00107                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
00108                                               This parameter could be ENABLE or DISABLE
00109                                               Please check the Read Mode sequence in the NAND device datasheet */
00110 } NAND_DeviceConfigTypeDef;
00111
00112 /**
00113   * @brief  NAND handle Structure definition
00114   */
00115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00116 typedef struct __NAND_HandleTypeDef
00117 #else
00118 typedef struct
00119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
00120 {
00121   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
00122
00123   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
00124
00125   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
00126
00127   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
00128
00129   NAND_DeviceConfigTypeDef       Config;     /*!< NAND physical characteristic information structure    */
00130
00131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00132   void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand);               /*!< NAND Msp Init callback              */
00133   void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand);             /*!< NAND Msp DeInit callback            */
00134   void (* ItCallback)(struct __NAND_HandleTypeDef *hnand);                    /*!< NAND IT callback                    */
00135 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
00136 } NAND_HandleTypeDef;
00137
00138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00139 /**
00140   * @brief  HAL NAND Callback ID enumeration definition
00141   */
00142 typedef enum
00143 {
00144   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
00145   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
00146   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
00147 } HAL_NAND_CallbackIDTypeDef;
00148
00149 /**
00150   * @brief  HAL NAND Callback pointer definition
00151   */
00152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
00153 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported constants --------------------------------------------------------*/
00160 /* Exported macro ------------------------------------------------------------*/
00161 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00162   * @{
00163   */
00164
00165 /** @brief Reset NAND handle state
00166   * @param  __HANDLE__ specifies the NAND handle.
00167   * @retval None
00168   */
00169 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
00171                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
00172                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00173                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00174                                                              } while(0)
00175 #else
00176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00177 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00185   * @{
00186   */
00187
00188 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00189   * @{
00190   */
00191
00192 /* Initialization/de-initialization functions  ********************************/
00193 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
00194                                  FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00195 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00196
00197 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
00198
00199 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00200
00201 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00202 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00203 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00204 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00211   * @{
00212   */
00213
00214 /* IO operation functions  ****************************************************/
00215 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00216
00217 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00218                                          uint8_t *pBuffer, uint32_t NumPageToRead);
00219 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00220                                           const uint8_t *pBuffer, uint32_t NumPageToWrite);
00221 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00222                                               uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00223 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00224                                                const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00225
00226 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00227                                           uint16_t *pBuffer, uint32_t NumPageToRead);
00228 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00229                                            const uint16_t *pBuffer, uint32_t NumPageToWrite);
00230 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00231                                                uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
00232 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
00233                                                 const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
00234
00235 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
00236
00237 uint32_t           HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00238
00239 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
00240 /* NAND callback registering/unregistering */
00241 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
00242                                              pNAND_CallbackTypeDef pCallback);
00243 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
00244 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00251   * @{
00252   */
00253
00254 /* NAND Control functions  ****************************************************/
00255 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00256 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00257 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00264   * @{
00265   */
00266 /* NAND State functions *******************************************************/
00267 HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
00268 uint32_t              HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Private types -------------------------------------------------------------*/
00278 /* Private variables ---------------------------------------------------------*/
00279 /* Private constants ---------------------------------------------------------*/
00280 /** @defgroup NAND_Private_Constants NAND Private Constants
00281   * @{
00282   */
00283 #define NAND_DEVICE                0x80000000UL
00284 #define NAND_WRITE_TIMEOUT         0x01000000UL
00285
00286 #define CMD_AREA                   (1UL<<16U)  /* A16 = CLE high */
00287 #define ADDR_AREA                  (1UL<<17U)  /* A17 = ALE high */
00288
00289 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00290 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00291 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00292 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
00293
00294 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00295 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00296 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00297 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00298 #define NAND_CMD_READID            ((uint8_t)0x90)
00299 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00300 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00301 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00302
00303 /* NAND memory status */
00304 #define NAND_VALID_ADDRESS         0x00000100UL
00305 #define NAND_INVALID_ADDRESS       0x00000200UL
00306 #define NAND_TIMEOUT_ERROR         0x00000400UL
00307 #define NAND_BUSY                  0x00000000UL
00308 #define NAND_ERROR                 0x00000001UL
00309 #define NAND_READY                 0x00000040UL
00310 /**
00311   * @}
00312   */
00313
00314 /* Private macros ------------------------------------------------------------*/
00315 /** @defgroup NAND_Private_Macros NAND Private Macros
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  NAND memory address computation.
00321   * @param  __ADDRESS__ NAND memory address.
00322   * @param  __HANDLE__  NAND handle.
00323   * @retval NAND Raw address value
00324   */
00325 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00326                                                  (((__ADDRESS__)->Block + \
00327                                                    (((__ADDRESS__)->Plane) * \
00328                                                     ((__HANDLE__)->Config.PlaneSize))) * \
00329                                                   ((__HANDLE__)->Config.BlockSize)))
00330
00331 /**
00332   * @brief  NAND memory Column address computation.
00333   * @param  __HANDLE__ NAND handle.
00334   * @retval NAND Raw address value
00335   */
00336 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
00337
00338 /**
00339   * @brief  NAND memory address cycling.
00340   * @param  __ADDRESS__ NAND memory address.
00341   * @retval NAND address cycling value.
00342   */
00343 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00344 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00345 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00346 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00347
00348 /**
00349   * @brief  NAND memory Columns cycling.
00350   * @param  __ADDRESS__ NAND memory address.
00351   * @retval NAND Column address cycling value.
00352   */
00353 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
00354 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /**
00361   * @}
00362   */
00363
00364 /**
00365   * @}
00366   */
00367
00368 /**
00369   * @}
00370   */
00371
00372 #endif /* FMC_BANK3 */
00373
00374 #ifdef __cplusplus
00375 }
00376 #endif
00377
00378 #endif /* STM32G4xx_HAL_NAND_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nor.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_nor.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @brief   NOR HAL module driver.
00006   *          This file provides a generic firmware to drive NOR memories mounted
00007   *          as external device.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   @verbatim
00021   ==============================================================================
00022                      ##### How to use this driver #####
00023   ==============================================================================
00024     [..]
00025       This driver is a generic layered driver which contains a set of APIs used to
00026       control NOR flash memories. It uses the FMC layer functions to interface
00027       with NOR devices. This driver is used as follows:
00028
00029       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00030           with control and timing parameters for both normal and extended mode.
00031
00032       (+) Read NOR flash memory manufacturer code and device IDs using the function
00033           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00034           structure declared by the function caller.
00035
00036       (+) Access NOR flash memory by read/write data unit operations using the functions
00037           HAL_NOR_Read(), HAL_NOR_Program().
00038
00039       (+) Perform NOR flash erase block/chip operations using the functions
00040           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00041
00042       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00043           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00044           structure declared by the function caller.
00045
00046       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00047           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00048
00049       (+) You can monitor the NOR device HAL state by calling the function
00050           HAL_NOR_GetState()
00051     [..]
00052      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00053          If a NOR flash device contains different operations and/or implementations,
00054          it should be implemented separately.
00055
00056      *** NOR HAL driver macros list ***
00057      =============================================
00058      [..]
00059        Below the list of most used macros in NOR HAL driver.
00060
00061       (+) NOR_WRITE : NOR memory write data to specified address
00062
00063     *** Callback registration ***
00064     =============================================
00065     [..]
00066       The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
00067       allows the user to configure dynamically the driver callbacks.
00068
00069       Use Functions HAL_NOR_RegisterCallback() to register a user callback,
00070       it allows to register following callbacks:
00071         (+) MspInitCallback    : NOR MspInit.
00072         (+) MspDeInitCallback  : NOR MspDeInit.
00073       This function takes as parameters the HAL peripheral handle, the Callback ID
00074       and a pointer to the user callback function.
00075
00076       Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
00077       weak (overridden) function. It allows to reset following callbacks:
00078         (+) MspInitCallback    : NOR MspInit.
00079         (+) MspDeInitCallback  : NOR MspDeInit.
00080       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00081
00082       By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
00083       all callbacks are reset to the corresponding legacy weak (overridden) functions.
00084       Exception done for MspInit and MspDeInit callbacks that are respectively
00085       reset to the legacy weak (overridden) functions in the HAL_NOR_Init
00086       and  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
00087       If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
00088       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00089
00090       Callbacks can be registered/unregistered in READY state only.
00091       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00092       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00093       during the Init/DeInit.
00094       In that case first register the MspInit/MspDeInit user callbacks
00095       using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
00096       or HAL_NOR_Init function.
00097
00098       When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
00099       not defined, the callback registering feature is not available
00100       and weak (overridden) callbacks are used.
00101
00102   @endverbatim
00103   ******************************************************************************
00104   */
00105
00106 /* Includes ------------------------------------------------------------------*/
00107 #include "stm32g4xx_hal.h"
00108
00109 #if  defined(FMC_BANK1)
00110
00111 /** @addtogroup STM32G4xx_HAL_Driver
00112   * @{
00113   */
00114
00115 #ifdef HAL_NOR_MODULE_ENABLED
00116
00117 /** @defgroup NOR NOR
00118   * @brief NOR driver modules
00119   * @{
00120   */
00121
00122 /* Private typedef -----------------------------------------------------------*/
00123 /* Private define ------------------------------------------------------------*/
00124
00125 /** @defgroup NOR_Private_Defines NOR Private Defines
00126   * @{
00127   */
00128
00129 /* Constants to define address to set to write a command */
00130 #define NOR_CMD_ADDRESS_FIRST_BYTE            (uint16_t)0x0AAA
00131 #define NOR_CMD_ADDRESS_FIRST_CFI_BYTE        (uint16_t)0x00AA
00132 #define NOR_CMD_ADDRESS_SECOND_BYTE           (uint16_t)0x0555
00133 #define NOR_CMD_ADDRESS_THIRD_BYTE            (uint16_t)0x0AAA
00134
00135 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00136 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00137 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00138 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00139 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00140 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00141 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00142
00143 /* Constants to define data to program a command */
00144 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00145 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00146 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00147 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00148 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00149 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00150 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00151 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00152 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00153 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00154
00155 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00156 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00157 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00158
00159 #define NOR_CMD_READ_ARRAY                    (uint16_t)0x00FF
00160 #define NOR_CMD_WORD_PROGRAM                  (uint16_t)0x0040
00161 #define NOR_CMD_BUFFERED_PROGRAM              (uint16_t)0x00E8
00162 #define NOR_CMD_CONFIRM                       (uint16_t)0x00D0
00163 #define NOR_CMD_BLOCK_ERASE                   (uint16_t)0x0020
00164 #define NOR_CMD_BLOCK_UNLOCK                  (uint16_t)0x0060
00165 #define NOR_CMD_READ_STATUS_REG               (uint16_t)0x0070
00166 #define NOR_CMD_CLEAR_STATUS_REG              (uint16_t)0x0050
00167
00168 /* Mask on NOR STATUS REGISTER */
00169 #define NOR_MASK_STATUS_DQ4                   (uint16_t)0x0010
00170 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00171 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00172 #define NOR_MASK_STATUS_DQ7                   (uint16_t)0x0080
00173
00174 /* Address of the primary command set */
00175 #define NOR_ADDRESS_COMMAND_SET               (uint16_t)0x0013
00176
00177 /* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
00178 #define NOR_INTEL_SHARP_EXT_COMMAND_SET       (uint16_t)0x0001 /* Supported in this driver */
00179 #define NOR_AMD_FUJITSU_COMMAND_SET           (uint16_t)0x0002 /* Supported in this driver */
00180 #define NOR_INTEL_STANDARD_COMMAND_SET        (uint16_t)0x0003 /* Not Supported in this driver */
00181 #define NOR_AMD_FUJITSU_EXT_COMMAND_SET       (uint16_t)0x0004 /* Not Supported in this driver */
00182 #define NOR_WINDBOND_STANDARD_COMMAND_SET     (uint16_t)0x0006 /* Not Supported in this driver */
00183 #define NOR_MITSUBISHI_STANDARD_COMMAND_SET   (uint16_t)0x0100 /* Not Supported in this driver */
00184 #define NOR_MITSUBISHI_EXT_COMMAND_SET        (uint16_t)0x0101 /* Not Supported in this driver */
00185 #define NOR_PAGE_WRITE_COMMAND_SET            (uint16_t)0x0102 /* Not Supported in this driver */
00186 #define NOR_INTEL_PERFORMANCE_COMMAND_SET     (uint16_t)0x0200 /* Not Supported in this driver */
00187 #define NOR_INTEL_DATA_COMMAND_SET            (uint16_t)0x0210 /* Not Supported in this driver */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Private macro -------------------------------------------------------------*/
00194 /* Private variables ---------------------------------------------------------*/
00195 /** @defgroup NOR_Private_Variables NOR Private Variables
00196   * @{
00197   */
00198
00199 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00200
00201 /**
00202   * @}
00203   */
00204
00205 /* Private functions ---------------------------------------------------------*/
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00208   * @{
00209   */
00210
00211 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00212   * @brief    Initialization and Configuration functions
00213   *
00214   @verbatim
00215   ==============================================================================
00216            ##### NOR Initialization and de_initialization functions #####
00217   ==============================================================================
00218   [..]
00219     This section provides functions allowing to initialize/de-initialize
00220     the NOR memory
00221
00222 @endverbatim
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Perform the NOR memory Initialization sequence
00228   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00229   *                the configuration information for NOR module.
00230   * @param  Timing pointer to NOR control timing structure
00231   * @param  ExtTiming pointer to NOR extended mode timing structure
00232   * @retval HAL status
00233   */
00234 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
00235                                FMC_NORSRAM_TimingTypeDef *ExtTiming)
00236 {
00237   uint32_t deviceaddress;
00238   HAL_StatusTypeDef status = HAL_OK;
00239
00240   /* Check the NOR handle parameter */
00241   if (hnor == NULL)
00242   {
00243     return HAL_ERROR;
00244   }
00245
00246   if (hnor->State == HAL_NOR_STATE_RESET)
00247   {
00248     /* Allocate lock resource and initialize it */
00249     hnor->Lock = HAL_UNLOCKED;
00250
00251 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00252     if (hnor->MspInitCallback == NULL)
00253     {
00254       hnor->MspInitCallback = HAL_NOR_MspInit;
00255     }
00256
00257     /* Init the low level hardware */
00258     hnor->MspInitCallback(hnor);
00259 #else
00260     /* Initialize the low level hardware (MSP) */
00261     HAL_NOR_MspInit(hnor);
00262 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
00263   }
00264
00265   /* Initialize NOR control Interface */
00266   (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00267
00268   /* Initialize NOR timing Interface */
00269   (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00270
00271   /* Initialize NOR extended mode timing Interface */
00272   (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
00273                                          hnor->Init.NSBank, hnor->Init.ExtendedMode);
00274
00275   /* Enable the NORSRAM device */
00276   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00277
00278   /* Initialize NOR Memory Data Width*/
00279   if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
00280   {
00281     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00282   }
00283   else
00284   {
00285     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00286   }
00287
00288   /* Initialize the NOR controller state */
00289   hnor->State = HAL_NOR_STATE_READY;
00290
00291   /* Select the NOR device address */
00292   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00293   {
00294     deviceaddress = NOR_MEMORY_ADRESS1;
00295   }
00296   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00297   {
00298     deviceaddress = NOR_MEMORY_ADRESS2;
00299   }
00300   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00301   {
00302     deviceaddress = NOR_MEMORY_ADRESS3;
00303   }
00304   else /* FMC_NORSRAM_BANK4 */
00305   {
00306     deviceaddress = NOR_MEMORY_ADRESS4;
00307   }
00308
00309   if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
00310   {
00311     (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00312
00313     /* Update the NOR controller state */
00314     hnor->State = HAL_NOR_STATE_PROTECTED;
00315   }
00316   else
00317   {
00318     /* Get the value of the command set */
00319     if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00320     {
00321       NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
00322                 NOR_CMD_DATA_CFI);
00323     }
00324     else
00325     {
00326       NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00327     }
00328
00329     hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
00330
00331     status = HAL_NOR_ReturnToReadMode(hnor);
00332   }
00333
00334   return status;
00335 }
00336
00337 /**
00338   * @brief  Perform NOR memory De-Initialization sequence
00339   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00340   *                the configuration information for NOR module.
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00344 {
00345 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00346   if (hnor->MspDeInitCallback == NULL)
00347   {
00348     hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
00349   }
00350
00351   /* DeInit the low level hardware */
00352   hnor->MspDeInitCallback(hnor);
00353 #else
00354   /* De-Initialize the low level hardware (MSP) */
00355   HAL_NOR_MspDeInit(hnor);
00356 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
00357
00358   /* Configure the NOR registers with their reset values */
00359   (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00360
00361   /* Reset the NOR controller state */
00362   hnor->State = HAL_NOR_STATE_RESET;
00363
00364   /* Release Lock */
00365   __HAL_UNLOCK(hnor);
00366
00367   return HAL_OK;
00368 }
00369
00370 /**
00371   * @brief  NOR MSP Init
00372   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00373   *                the configuration information for NOR module.
00374   * @retval None
00375   */
00376 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00377 {
00378   /* Prevent unused argument(s) compilation warning */
00379   UNUSED(hnor);
00380
00381   /* NOTE : This function Should not be modified, when the callback is needed,
00382             the HAL_NOR_MspInit could be implemented in the user file
00383    */
00384 }
00385
00386 /**
00387   * @brief  NOR MSP DeInit
00388   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00389   *                the configuration information for NOR module.
00390   * @retval None
00391   */
00392 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00393 {
00394   /* Prevent unused argument(s) compilation warning */
00395   UNUSED(hnor);
00396
00397   /* NOTE : This function Should not be modified, when the callback is needed,
00398             the HAL_NOR_MspDeInit could be implemented in the user file
00399    */
00400 }
00401
00402 /**
00403   * @brief  NOR MSP Wait for Ready/Busy signal
00404   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00405   *                the configuration information for NOR module.
00406   * @param  Timeout Maximum timeout value
00407   * @retval None
00408   */
00409 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00410 {
00411   /* Prevent unused argument(s) compilation warning */
00412   UNUSED(hnor);
00413   UNUSED(Timeout);
00414
00415   /* NOTE : This function Should not be modified, when the callback is needed,
00416             the HAL_NOR_MspWait could be implemented in the user file
00417    */
00418 }
00419
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00425   * @brief    Input Output and memory control functions
00426   *
00427   @verbatim
00428   ==============================================================================
00429                 ##### NOR Input and Output functions #####
00430   ==============================================================================
00431   [..]
00432     This section provides functions allowing to use and control the NOR memory
00433
00434 @endverbatim
00435   * @{
00436   */
00437
00438 /**
00439   * @brief  Read NOR flash IDs
00440   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00441   *                the configuration information for NOR module.
00442   * @param  pNOR_ID  pointer to NOR ID structure
00443   * @retval HAL status
00444   */
00445 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00446 {
00447   uint32_t deviceaddress;
00448   HAL_NOR_StateTypeDef state;
00449   HAL_StatusTypeDef status = HAL_OK;
00450
00451   /* Check the NOR controller state */
00452   state = hnor->State;
00453   if (state == HAL_NOR_STATE_BUSY)
00454   {
00455     return HAL_BUSY;
00456   }
00457   else if (state == HAL_NOR_STATE_PROTECTED)
00458   {
00459     return HAL_ERROR;
00460   }
00461   else if (state == HAL_NOR_STATE_READY)
00462   {
00463     /* Process Locked */
00464     __HAL_LOCK(hnor);
00465
00466     /* Update the NOR controller state */
00467     hnor->State = HAL_NOR_STATE_BUSY;
00468
00469     /* Select the NOR device address */
00470     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00471     {
00472       deviceaddress = NOR_MEMORY_ADRESS1;
00473     }
00474     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00475     {
00476       deviceaddress = NOR_MEMORY_ADRESS2;
00477     }
00478     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00479     {
00480       deviceaddress = NOR_MEMORY_ADRESS3;
00481     }
00482     else /* FMC_NORSRAM_BANK4 */
00483     {
00484       deviceaddress = NOR_MEMORY_ADRESS4;
00485     }
00486
00487     /* Send read ID command */
00488     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00489     {
00490       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00491       {
00492         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
00493                   NOR_CMD_DATA_FIRST);
00494         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
00495                   NOR_CMD_DATA_SECOND);
00496         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
00497                   NOR_CMD_DATA_AUTO_SELECT);
00498       }
00499       else
00500       {
00501         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00502         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00503         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
00504                   NOR_CMD_DATA_AUTO_SELECT);
00505       }
00506     }
00507     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00508     {
00509       NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
00510     }
00511     else
00512     {
00513       /* Primary command set not supported by the driver */
00514       status = HAL_ERROR;
00515     }
00516
00517     if (status != HAL_ERROR)
00518     {
00519       /* Read the NOR IDs */
00520       pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00521       pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
00522                                                                      DEVICE_CODE1_ADDR);
00523       pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
00524                                                                      DEVICE_CODE2_ADDR);
00525       pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
00526                                                                      DEVICE_CODE3_ADDR);
00527     }
00528
00529     /* Check the NOR controller state */
00530     hnor->State = state;
00531
00532     /* Process unlocked */
00533     __HAL_UNLOCK(hnor);
00534   }
00535   else
00536   {
00537     return HAL_ERROR;
00538   }
00539
00540   return status;
00541 }
00542
00543 /**
00544   * @brief  Returns the NOR memory to Read mode.
00545   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00546   *                the configuration information for NOR module.
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00550 {
00551   uint32_t deviceaddress;
00552   HAL_NOR_StateTypeDef state;
00553   HAL_StatusTypeDef status = HAL_OK;
00554
00555   /* Check the NOR controller state */
00556   state = hnor->State;
00557   if (state == HAL_NOR_STATE_BUSY)
00558   {
00559     return HAL_BUSY;
00560   }
00561   else if (state == HAL_NOR_STATE_PROTECTED)
00562   {
00563     return HAL_ERROR;
00564   }
00565   else if (state == HAL_NOR_STATE_READY)
00566   {
00567     /* Process Locked */
00568     __HAL_LOCK(hnor);
00569
00570     /* Update the NOR controller state */
00571     hnor->State = HAL_NOR_STATE_BUSY;
00572
00573     /* Select the NOR device address */
00574     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00575     {
00576       deviceaddress = NOR_MEMORY_ADRESS1;
00577     }
00578     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00579     {
00580       deviceaddress = NOR_MEMORY_ADRESS2;
00581     }
00582     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00583     {
00584       deviceaddress = NOR_MEMORY_ADRESS3;
00585     }
00586     else /* FMC_NORSRAM_BANK4 */
00587     {
00588       deviceaddress = NOR_MEMORY_ADRESS4;
00589     }
00590
00591     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00592     {
00593       NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00594     }
00595     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00596     {
00597       NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
00598     }
00599     else
00600     {
00601       /* Primary command set not supported by the driver */
00602       status = HAL_ERROR;
00603     }
00604
00605     /* Check the NOR controller state */
00606     hnor->State = state;
00607
00608     /* Process unlocked */
00609     __HAL_UNLOCK(hnor);
00610   }
00611   else
00612   {
00613     return HAL_ERROR;
00614   }
00615
00616   return status;
00617 }
00618
00619 /**
00620   * @brief  Read data from NOR memory
00621   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00622   *                the configuration information for NOR module.
00623   * @param  pAddress pointer to Device address
00624   * @param  pData  pointer to read data
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00628 {
00629   uint32_t deviceaddress;
00630   HAL_NOR_StateTypeDef state;
00631   HAL_StatusTypeDef status = HAL_OK;
00632
00633   /* Check the NOR controller state */
00634   state = hnor->State;
00635   if (state == HAL_NOR_STATE_BUSY)
00636   {
00637     return HAL_BUSY;
00638   }
00639   else if (state == HAL_NOR_STATE_PROTECTED)
00640   {
00641     return HAL_ERROR;
00642   }
00643   else if (state == HAL_NOR_STATE_READY)
00644   {
00645     /* Process Locked */
00646     __HAL_LOCK(hnor);
00647
00648     /* Update the NOR controller state */
00649     hnor->State = HAL_NOR_STATE_BUSY;
00650
00651     /* Select the NOR device address */
00652     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00653     {
00654       deviceaddress = NOR_MEMORY_ADRESS1;
00655     }
00656     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00657     {
00658       deviceaddress = NOR_MEMORY_ADRESS2;
00659     }
00660     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00661     {
00662       deviceaddress = NOR_MEMORY_ADRESS3;
00663     }
00664     else /* FMC_NORSRAM_BANK4 */
00665     {
00666       deviceaddress = NOR_MEMORY_ADRESS4;
00667     }
00668
00669     /* Send read data command */
00670     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00671     {
00672       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00673       {
00674         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
00675                   NOR_CMD_DATA_FIRST);
00676         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
00677                   NOR_CMD_DATA_SECOND);
00678         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
00679                   NOR_CMD_DATA_READ_RESET);
00680       }
00681       else
00682       {
00683         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00684         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00685         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
00686                   NOR_CMD_DATA_READ_RESET);
00687       }
00688     }
00689     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00690     {
00691       NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
00692     }
00693     else
00694     {
00695       /* Primary command set not supported by the driver */
00696       status = HAL_ERROR;
00697     }
00698
00699     if (status != HAL_ERROR)
00700     {
00701       /* Read the data */
00702       *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
00703     }
00704
00705     /* Check the NOR controller state */
00706     hnor->State = state;
00707
00708     /* Process unlocked */
00709     __HAL_UNLOCK(hnor);
00710   }
00711   else
00712   {
00713     return HAL_ERROR;
00714   }
00715
00716   return status;
00717 }
00718
00719 /**
00720   * @brief  Program data to NOR memory
00721   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
00722   *                the configuration information for NOR module.
00723   * @param  pAddress Device address
00724   * @param  pData  pointer to the data to write
00725   * @retval HAL status
00726   */
00727 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00728 {
00729   uint32_t deviceaddress;
00730   HAL_StatusTypeDef status = HAL_OK;
00731
00732   /* Check the NOR controller state */
00733   if (hnor->State == HAL_NOR_STATE_BUSY)
00734   {
00735     return HAL_BUSY;
00736   }
00737   else if (hnor->State == HAL_NOR_STATE_READY)
00738   {
00739     /* Process Locked */
00740     __HAL_LOCK(hnor);
00741
00742     /* Update the NOR controller state */
00743     hnor->State = HAL_NOR_STATE_BUSY;
00744
00745     /* Select the NOR device address */
00746     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00747     {
00748       deviceaddress = NOR_MEMORY_ADRESS1;
00749     }
00750     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00751     {
00752       deviceaddress = NOR_MEMORY_ADRESS2;
00753     }
00754     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00755     {
00756       deviceaddress = NOR_MEMORY_ADRESS3;
00757     }
00758     else /* FMC_NORSRAM_BANK4 */
00759     {
00760       deviceaddress = NOR_MEMORY_ADRESS4;
00761     }
00762
00763     /* Send program data command */
00764     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00765     {
00766       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00767       {
00768         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
00769                   NOR_CMD_DATA_FIRST);
00770         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
00771                   NOR_CMD_DATA_SECOND);
00772         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
00773                   NOR_CMD_DATA_PROGRAM);
00774       }
00775       else
00776       {
00777         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00778         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00779         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00780       }
00781     }
00782     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00783     {
00784       NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
00785     }
00786     else
00787     {
00788       /* Primary command set not supported by the driver */
00789       status = HAL_ERROR;
00790     }
00791
00792     if (status != HAL_ERROR)
00793     {
00794       /* Write the data */
00795       NOR_WRITE(pAddress, *pData);
00796     }
00797
00798     /* Check the NOR controller state */
00799     hnor->State = HAL_NOR_STATE_READY;
00800
00801     /* Process unlocked */
00802     __HAL_UNLOCK(hnor);
00803   }
00804   else
00805   {
00806     return HAL_ERROR;
00807   }
00808
00809   return status;
00810 }
00811
00812 /**
00813   * @brief  Reads a half-word buffer from the NOR memory.
00814   * @param  hnor pointer to the NOR handle
00815   * @param  uwAddress NOR memory internal address to read from.
00816   * @param  pData pointer to the buffer that receives the data read from the
00817   *         NOR memory.
00818   * @param  uwBufferSize  number of Half word to read.
00819   * @retval HAL status
00820   */
00821 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00822                                      uint32_t uwBufferSize)
00823 {
00824   uint32_t deviceaddress;
00825   uint32_t size = uwBufferSize;
00826   uint32_t address = uwAddress;
00827   uint16_t *data = pData;
00828   HAL_NOR_StateTypeDef state;
00829   HAL_StatusTypeDef status = HAL_OK;
00830
00831   /* Check the NOR controller state */
00832   state = hnor->State;
00833   if (state == HAL_NOR_STATE_BUSY)
00834   {
00835     return HAL_BUSY;
00836   }
00837   else if (state == HAL_NOR_STATE_PROTECTED)
00838   {
00839     return HAL_ERROR;
00840   }
00841   else if (state == HAL_NOR_STATE_READY)
00842   {
00843     /* Process Locked */
00844     __HAL_LOCK(hnor);
00845
00846     /* Update the NOR controller state */
00847     hnor->State = HAL_NOR_STATE_BUSY;
00848
00849     /* Select the NOR device address */
00850     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00851     {
00852       deviceaddress = NOR_MEMORY_ADRESS1;
00853     }
00854     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00855     {
00856       deviceaddress = NOR_MEMORY_ADRESS2;
00857     }
00858     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00859     {
00860       deviceaddress = NOR_MEMORY_ADRESS3;
00861     }
00862     else /* FMC_NORSRAM_BANK4 */
00863     {
00864       deviceaddress = NOR_MEMORY_ADRESS4;
00865     }
00866
00867     /* Send read data command */
00868     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00869     {
00870       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00871       {
00872         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
00873                   NOR_CMD_DATA_FIRST);
00874         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
00875                   NOR_CMD_DATA_SECOND);
00876         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
00877                   NOR_CMD_DATA_READ_RESET);
00878       }
00879       else
00880       {
00881         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00882         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00883         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
00884                   NOR_CMD_DATA_READ_RESET);
00885       }
00886     }
00887     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00888     {
00889       NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
00890     }
00891     else
00892     {
00893       /* Primary command set not supported by the driver */
00894       status = HAL_ERROR;
00895     }
00896
00897     if (status != HAL_ERROR)
00898     {
00899       /* Read buffer */
00900       while (size > 0U)
00901       {
00902         *data = *(__IO uint16_t *)address;
00903         data++;
00904         address += 2U;
00905         size--;
00906       }
00907     }
00908
00909     /* Check the NOR controller state */
00910     hnor->State = state;
00911
00912     /* Process unlocked */
00913     __HAL_UNLOCK(hnor);
00914   }
00915   else
00916   {
00917     return HAL_ERROR;
00918   }
00919
00920   return status;
00921 }
00922
00923 /**
00924   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
00925             only with S29GL128P NOR memory.
00926   * @param  hnor pointer to the NOR handle
00927   * @param  uwAddress NOR memory internal start write address
00928   * @param  pData pointer to source data buffer.
00929   * @param  uwBufferSize Size of the buffer to write
00930   * @retval HAL status
00931   */
00932 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00933                                         uint32_t uwBufferSize)
00934 {
00935   uint16_t *p_currentaddress;
00936   const uint16_t *p_endaddress;
00937   uint16_t *data = pData;
00938   uint32_t deviceaddress;
00939   HAL_StatusTypeDef status = HAL_OK;
00940
00941   /* Check the NOR controller state */
00942   if (hnor->State == HAL_NOR_STATE_BUSY)
00943   {
00944     return HAL_BUSY;
00945   }
00946   else if (hnor->State == HAL_NOR_STATE_READY)
00947   {
00948     /* Process Locked */
00949     __HAL_LOCK(hnor);
00950
00951     /* Update the NOR controller state */
00952     hnor->State = HAL_NOR_STATE_BUSY;
00953
00954     /* Select the NOR device address */
00955     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00956     {
00957       deviceaddress = NOR_MEMORY_ADRESS1;
00958     }
00959     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00960     {
00961       deviceaddress = NOR_MEMORY_ADRESS2;
00962     }
00963     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00964     {
00965       deviceaddress = NOR_MEMORY_ADRESS3;
00966     }
00967     else /* FMC_NORSRAM_BANK4 */
00968     {
00969       deviceaddress = NOR_MEMORY_ADRESS4;
00970     }
00971
00972     /* Initialize variables */
00973     p_currentaddress  = (uint16_t *)(deviceaddress + uwAddress);
00974     p_endaddress      = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
00975
00976     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
00977     {
00978       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
00979       {
00980         /* Issue unlock command sequence */
00981         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
00982                   NOR_CMD_DATA_FIRST);
00983         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
00984                   NOR_CMD_DATA_SECOND);
00985       }
00986       else
00987       {
00988         /* Issue unlock command sequence */
00989         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00990         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00991       }
00992       /* Write Buffer Load Command */
00993       NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00994       NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
00995     }
00996     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
00997     {
00998       /* Write Buffer Load Command */
00999       NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
01000       NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
01001     }
01002     else
01003     {
01004       /* Primary command set not supported by the driver */
01005       status = HAL_ERROR;
01006     }
01007
01008     if (status != HAL_ERROR)
01009     {
01010       /* Load Data into NOR Buffer */
01011       while (p_currentaddress <= p_endaddress)
01012       {
01013         NOR_WRITE(p_currentaddress, *data);
01014
01015         data++;
01016         p_currentaddress ++;
01017       }
01018
01019       if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
01020       {
01021         NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
01022       }
01023       else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
01024       {
01025         NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
01026       }
01027     }
01028
01029     /* Check the NOR controller state */
01030     hnor->State = HAL_NOR_STATE_READY;
01031
01032     /* Process unlocked */
01033     __HAL_UNLOCK(hnor);
01034   }
01035   else
01036   {
01037     return HAL_ERROR;
01038   }
01039
01040   return status;
01041
01042 }
01043
01044 /**
01045   * @brief  Erase the specified block of the NOR memory
01046   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01047   *                the configuration information for NOR module.
01048   * @param  BlockAddress  Block to erase address
01049   * @param  Address Device address
01050   * @retval HAL status
01051   */
01052 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
01053 {
01054   uint32_t deviceaddress;
01055   HAL_StatusTypeDef status = HAL_OK;
01056
01057   /* Check the NOR controller state */
01058   if (hnor->State == HAL_NOR_STATE_BUSY)
01059   {
01060     return HAL_BUSY;
01061   }
01062   else if (hnor->State == HAL_NOR_STATE_READY)
01063   {
01064     /* Process Locked */
01065     __HAL_LOCK(hnor);
01066
01067     /* Update the NOR controller state */
01068     hnor->State = HAL_NOR_STATE_BUSY;
01069
01070     /* Select the NOR device address */
01071     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
01072     {
01073       deviceaddress = NOR_MEMORY_ADRESS1;
01074     }
01075     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
01076     {
01077       deviceaddress = NOR_MEMORY_ADRESS2;
01078     }
01079     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
01080     {
01081       deviceaddress = NOR_MEMORY_ADRESS3;
01082     }
01083     else /* FMC_NORSRAM_BANK4 */
01084     {
01085       deviceaddress = NOR_MEMORY_ADRESS4;
01086     }
01087
01088     /* Send block erase command sequence */
01089     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
01090     {
01091       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
01092       {
01093         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
01094                   NOR_CMD_DATA_FIRST);
01095         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
01096                   NOR_CMD_DATA_SECOND);
01097         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
01098                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
01099       }
01100       else
01101       {
01102         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
01103         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
01104         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
01105                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
01106         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
01107                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
01108         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
01109                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
01110       }
01111       NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
01112     }
01113     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
01114     {
01115       NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
01116       NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
01117       NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
01118       NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
01119     }
01120     else
01121     {
01122       /* Primary command set not supported by the driver */
01123       status = HAL_ERROR;
01124     }
01125
01126     /* Check the NOR memory status and update the controller state */
01127     hnor->State = HAL_NOR_STATE_READY;
01128
01129     /* Process unlocked */
01130     __HAL_UNLOCK(hnor);
01131   }
01132   else
01133   {
01134     return HAL_ERROR;
01135   }
01136
01137   return status;
01138
01139 }
01140
01141 /**
01142   * @brief  Erase the entire NOR chip.
01143   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01144   *                the configuration information for NOR module.
01145   * @param  Address  Device address
01146   * @retval HAL status
01147   */
01148 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
01149 {
01150   uint32_t deviceaddress;
01151   HAL_StatusTypeDef status = HAL_OK;
01152   UNUSED(Address);
01153
01154   /* Check the NOR controller state */
01155   if (hnor->State == HAL_NOR_STATE_BUSY)
01156   {
01157     return HAL_BUSY;
01158   }
01159   else if (hnor->State == HAL_NOR_STATE_READY)
01160   {
01161     /* Process Locked */
01162     __HAL_LOCK(hnor);
01163
01164     /* Update the NOR controller state */
01165     hnor->State = HAL_NOR_STATE_BUSY;
01166
01167     /* Select the NOR device address */
01168     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
01169     {
01170       deviceaddress = NOR_MEMORY_ADRESS1;
01171     }
01172     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
01173     {
01174       deviceaddress = NOR_MEMORY_ADRESS2;
01175     }
01176     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
01177     {
01178       deviceaddress = NOR_MEMORY_ADRESS3;
01179     }
01180     else /* FMC_NORSRAM_BANK4 */
01181     {
01182       deviceaddress = NOR_MEMORY_ADRESS4;
01183     }
01184
01185     /* Send NOR chip erase command sequence */
01186     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
01187     {
01188       if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
01189       {
01190         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
01191                   NOR_CMD_DATA_FIRST);
01192         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
01193                   NOR_CMD_DATA_SECOND);
01194         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
01195                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
01196       }
01197       else
01198       {
01199         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
01200         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
01201         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
01202                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
01203         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
01204                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
01205         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
01206                   NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
01207         NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
01208                   NOR_CMD_DATA_CHIP_ERASE);
01209       }
01210     }
01211     else
01212     {
01213       /* Primary command set not supported by the driver */
01214       status = HAL_ERROR;
01215     }
01216
01217     /* Check the NOR memory status and update the controller state */
01218     hnor->State = HAL_NOR_STATE_READY;
01219
01220     /* Process unlocked */
01221     __HAL_UNLOCK(hnor);
01222   }
01223   else
01224   {
01225     return HAL_ERROR;
01226   }
01227
01228   return status;
01229 }
01230
01231 /**
01232   * @brief  Read NOR flash CFI IDs
01233   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01234   *                the configuration information for NOR module.
01235   * @param  pNOR_CFI  pointer to NOR CFI IDs structure
01236   * @retval HAL status
01237   */
01238 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
01239 {
01240   uint32_t deviceaddress;
01241   HAL_NOR_StateTypeDef state;
01242
01243   /* Check the NOR controller state */
01244   state = hnor->State;
01245   if (state == HAL_NOR_STATE_BUSY)
01246   {
01247     return HAL_BUSY;
01248   }
01249   else if (state == HAL_NOR_STATE_PROTECTED)
01250   {
01251     return HAL_ERROR;
01252   }
01253   else if (state == HAL_NOR_STATE_READY)
01254   {
01255     /* Process Locked */
01256     __HAL_LOCK(hnor);
01257
01258     /* Update the NOR controller state */
01259     hnor->State = HAL_NOR_STATE_BUSY;
01260
01261     /* Select the NOR device address */
01262     if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
01263     {
01264       deviceaddress = NOR_MEMORY_ADRESS1;
01265     }
01266     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
01267     {
01268       deviceaddress = NOR_MEMORY_ADRESS2;
01269     }
01270     else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
01271     {
01272       deviceaddress = NOR_MEMORY_ADRESS3;
01273     }
01274     else /* FMC_NORSRAM_BANK4 */
01275     {
01276       deviceaddress = NOR_MEMORY_ADRESS4;
01277     }
01278
01279     /* Send read CFI query command */
01280     if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
01281     {
01282       NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
01283                 NOR_CMD_DATA_CFI);
01284     }
01285     else
01286     {
01287       NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
01288     }
01289     /* read the NOR CFI information */
01290     pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
01291     pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
01292     pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
01293     pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
01294
01295     /* Check the NOR controller state */
01296     hnor->State = state;
01297
01298     /* Process unlocked */
01299     __HAL_UNLOCK(hnor);
01300   }
01301   else
01302   {
01303     return HAL_ERROR;
01304   }
01305
01306   return HAL_OK;
01307 }
01308
01309 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
01310 /**
01311   * @brief  Register a User NOR Callback
01312   *         To be used to override the weak predefined callback
01313   * @param hnor : NOR handle
01314   * @param CallbackId : ID of the callback to be registered
01315   *        This parameter can be one of the following values:
01316   *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
01317   *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
01318   * @param pCallback : pointer to the Callback function
01319   * @retval status
01320   */
01321 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
01322                                            pNOR_CallbackTypeDef pCallback)
01323 {
01324   HAL_StatusTypeDef status = HAL_OK;
01325   HAL_NOR_StateTypeDef state;
01326
01327   if (pCallback == NULL)
01328   {
01329     return HAL_ERROR;
01330   }
01331
01332   state = hnor->State;
01333   if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
01334   {
01335     switch (CallbackId)
01336     {
01337       case HAL_NOR_MSP_INIT_CB_ID :
01338         hnor->MspInitCallback = pCallback;
01339         break;
01340       case HAL_NOR_MSP_DEINIT_CB_ID :
01341         hnor->MspDeInitCallback = pCallback;
01342         break;
01343       default :
01344         /* update return status */
01345         status =  HAL_ERROR;
01346         break;
01347     }
01348   }
01349   else
01350   {
01351     /* update return status */
01352     status =  HAL_ERROR;
01353   }
01354
01355   return status;
01356 }
01357
01358 /**
01359   * @brief  Unregister a User NOR Callback
01360   *         NOR Callback is redirected to the weak predefined callback
01361   * @param hnor : NOR handle
01362   * @param CallbackId : ID of the callback to be unregistered
01363   *        This parameter can be one of the following values:
01364   *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
01365   *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
01366   * @retval status
01367   */
01368 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
01369 {
01370   HAL_StatusTypeDef status = HAL_OK;
01371   HAL_NOR_StateTypeDef state;
01372
01373   state = hnor->State;
01374   if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
01375   {
01376     switch (CallbackId)
01377     {
01378       case HAL_NOR_MSP_INIT_CB_ID :
01379         hnor->MspInitCallback = HAL_NOR_MspInit;
01380         break;
01381       case HAL_NOR_MSP_DEINIT_CB_ID :
01382         hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
01383         break;
01384       default :
01385         /* update return status */
01386         status =  HAL_ERROR;
01387         break;
01388     }
01389   }
01390   else
01391   {
01392     /* update return status */
01393     status =  HAL_ERROR;
01394   }
01395
01396   return status;
01397 }
01398 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
01399
01400 /**
01401   * @}
01402   */
01403
01404 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
01405   *  @brief   management functions
01406   *
01407 @verbatim
01408   ==============================================================================
01409                         ##### NOR Control functions #####
01410   ==============================================================================
01411   [..]
01412     This subsection provides a set of functions allowing to control dynamically
01413     the NOR interface.
01414
01415 @endverbatim
01416   * @{
01417   */
01418
01419 /**
01420   * @brief  Enables dynamically NOR write operation.
01421   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01422   *                the configuration information for NOR module.
01423   * @retval HAL status
01424   */
01425 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
01426 {
01427   /* Check the NOR controller state */
01428   if (hnor->State == HAL_NOR_STATE_PROTECTED)
01429   {
01430     /* Process Locked */
01431     __HAL_LOCK(hnor);
01432
01433     /* Update the NOR controller state */
01434     hnor->State = HAL_NOR_STATE_BUSY;
01435
01436     /* Enable write operation */
01437     (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
01438
01439     /* Update the NOR controller state */
01440     hnor->State = HAL_NOR_STATE_READY;
01441
01442     /* Process unlocked */
01443     __HAL_UNLOCK(hnor);
01444   }
01445   else
01446   {
01447     return HAL_ERROR;
01448   }
01449
01450   return HAL_OK;
01451 }
01452
01453 /**
01454   * @brief  Disables dynamically NOR write operation.
01455   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01456   *                the configuration information for NOR module.
01457   * @retval HAL status
01458   */
01459 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
01460 {
01461   /* Check the NOR controller state */
01462   if (hnor->State == HAL_NOR_STATE_READY)
01463   {
01464     /* Process Locked */
01465     __HAL_LOCK(hnor);
01466
01467     /* Update the NOR controller state */
01468     hnor->State = HAL_NOR_STATE_BUSY;
01469
01470     /* Disable write operation */
01471     (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
01472
01473     /* Update the NOR controller state */
01474     hnor->State = HAL_NOR_STATE_PROTECTED;
01475
01476     /* Process unlocked */
01477     __HAL_UNLOCK(hnor);
01478   }
01479   else
01480   {
01481     return HAL_ERROR;
01482   }
01483
01484   return HAL_OK;
01485 }
01486
01487 /**
01488   * @}
01489   */
01490
01491 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
01492   *  @brief   Peripheral State functions
01493   *
01494 @verbatim
01495   ==============================================================================
01496                       ##### NOR State functions #####
01497   ==============================================================================
01498   [..]
01499     This subsection permits to get in run-time the status of the NOR controller
01500     and the data flow.
01501
01502 @endverbatim
01503   * @{
01504   */
01505
01506 /**
01507   * @brief  return the NOR controller state
01508   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01509   *                the configuration information for NOR module.
01510   * @retval NOR controller state
01511   */
01512 HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
01513 {
01514   return hnor->State;
01515 }
01516
01517 /**
01518   * @brief  Returns the NOR operation status.
01519   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
01520   *                the configuration information for NOR module.
01521   * @param  Address Device address
01522   * @param  Timeout NOR programming Timeout
01523   * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
01524   *         or HAL_NOR_STATUS_TIMEOUT
01525   */
01526 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
01527 {
01528   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
01529   uint16_t tmpsr1;
01530   uint16_t tmpsr2;
01531   uint32_t tickstart;
01532
01533   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
01534   HAL_NOR_MspWait(hnor, Timeout);
01535
01536   /* Get the NOR memory operation status -------------------------------------*/
01537
01538   /* Get tick */
01539   tickstart = HAL_GetTick();
01540
01541   if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
01542   {
01543     while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
01544     {
01545       /* Check for the Timeout */
01546       if (Timeout != HAL_MAX_DELAY)
01547       {
01548         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01549         {
01550           status = HAL_NOR_STATUS_TIMEOUT;
01551         }
01552       }
01553
01554       /* Read NOR status register (DQ6 and DQ5) */
01555       tmpsr1 = *(__IO uint16_t *)Address;
01556       tmpsr2 = *(__IO uint16_t *)Address;
01557
01558       /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01559       if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
01560       {
01561         return HAL_NOR_STATUS_SUCCESS ;
01562       }
01563
01564       if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01565       {
01566         status = HAL_NOR_STATUS_ONGOING;
01567       }
01568
01569       tmpsr1 = *(__IO uint16_t *)Address;
01570       tmpsr2 = *(__IO uint16_t *)Address;
01571
01572       /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
01573       if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
01574       {
01575         return HAL_NOR_STATUS_SUCCESS;
01576       }
01577       if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01578       {
01579         return HAL_NOR_STATUS_ERROR;
01580       }
01581     }
01582   }
01583   else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
01584   {
01585     do
01586     {
01587       NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
01588       tmpsr2 = *(__IO uint16_t *)(Address);
01589
01590       /* Check for the Timeout */
01591       if (Timeout != HAL_MAX_DELAY)
01592       {
01593         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01594         {
01595           return HAL_NOR_STATUS_TIMEOUT;
01596         }
01597       }
01598     } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
01599
01600     NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
01601     tmpsr1 = *(__IO uint16_t *)(Address);
01602     if ((tmpsr1  & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
01603     {
01604       /* Clear the Status Register  */
01605       NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
01606       status = HAL_NOR_STATUS_ERROR;
01607     }
01608     else
01609     {
01610       status = HAL_NOR_STATUS_SUCCESS;
01611     }
01612   }
01613   else
01614   {
01615     /* Primary command set not supported by the driver */
01616     status = HAL_NOR_STATUS_ERROR;
01617   }
01618
01619   /* Return the operation status */
01620   return status;
01621 }
01622
01623 /**
01624   * @}
01625   */
01626
01627 /**
01628   * @}
01629   */
01630
01631 /**
01632   * @}
01633   */
01634
01635 #endif /* HAL_NOR_MODULE_ENABLED */
01636
01637 /**
01638   * @}
01639   */
01640
01641 #endif /* FMC_BANK1 */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_nor.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_nor.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of NOR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_NOR_H
00021 #define STM32G4xx_HAL_NOR_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 #if defined(FMC_BANK1)
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32g4xx_ll_fmc.h"
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup NOR
00037   * @{
00038   */
00039
00040 /* Exported typedef ----------------------------------------------------------*/
00041 /** @defgroup NOR_Exported_Types NOR Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL SRAM State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00051   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00052   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00053   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00054   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
00055 } HAL_NOR_StateTypeDef;
00056
00057 /**
00058   * @brief  FMC NOR Status typedef
00059   */
00060 typedef enum
00061 {
00062   HAL_NOR_STATUS_SUCCESS  = 0U,
00063   HAL_NOR_STATUS_ONGOING,
00064   HAL_NOR_STATUS_ERROR,
00065   HAL_NOR_STATUS_TIMEOUT
00066 } HAL_NOR_StatusTypeDef;
00067
00068 /**
00069   * @brief  FMC NOR ID typedef
00070   */
00071 typedef struct
00072 {
00073   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00074
00075   uint16_t Device_Code1;
00076
00077   uint16_t Device_Code2;
00078
00079   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00080                                     These codes can be accessed by performing read operations with specific
00081                                     control signals and addresses set.They can also be accessed by issuing
00082                                     an Auto Select command                                                   */
00083 } NOR_IDTypeDef;
00084
00085 /**
00086   * @brief  FMC NOR CFI typedef
00087   */
00088 typedef struct
00089 {
00090   /*!< Defines the information stored in the memory's Common flash interface
00091        which contains a description of various electrical and timing parameters,
00092        density information and functions supported by the memory                   */
00093
00094   uint16_t CFI_1;
00095
00096   uint16_t CFI_2;
00097
00098   uint16_t CFI_3;
00099
00100   uint16_t CFI_4;
00101 } NOR_CFITypeDef;
00102
00103 /**
00104   * @brief  NOR handle Structure definition
00105   */
00106 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00107 typedef struct __NOR_HandleTypeDef
00108 #else
00109 typedef struct
00110 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
00111
00112 {
00113   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00114
00115   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00116
00117   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00118
00119   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00120
00121   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00122
00123   uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
00124
00125 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00126   void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
00127   void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
00128 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00129 } NOR_HandleTypeDef;
00130
00131 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00132 /**
00133   * @brief  HAL NOR Callback ID enumeration definition
00134   */
00135 typedef enum
00136 {
00137   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
00138   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
00139 } HAL_NOR_CallbackIDTypeDef;
00140
00141 /**
00142   * @brief  HAL NOR Callback pointer definition
00143   */
00144 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
00145 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /* Exported macro ------------------------------------------------------------*/
00152 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00153   * @{
00154   */
00155 /** @brief Reset NOR handle state
00156   * @param  __HANDLE__ specifies the NOR handle.
00157   * @retval None
00158   */
00159 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00160 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
00161                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
00162                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00163                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00164                                                              } while(0)
00165 #else
00166 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00167 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00168 /**
00169   * @}
00170   */
00171
00172 /* Exported functions --------------------------------------------------------*/
00173 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00174   * @{
00175   */
00176
00177 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00178   * @{
00179   */
00180
00181 /* Initialization/de-initialization functions  ********************************/
00182 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
00183                                FMC_NORSRAM_TimingTypeDef *ExtTiming);
00184 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00185 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00186 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00187 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00188 /**
00189   * @}
00190   */
00191
00192 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00193   * @{
00194   */
00195
00196 /* I/O operation functions  ***************************************************/
00197 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00198 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00199 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00200 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00201
00202 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00203                                      uint32_t uwBufferSize);
00204 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
00205                                         uint32_t uwBufferSize);
00206
00207 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00208 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00209 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00210
00211 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
00212 /* NOR callback registering/unregistering */
00213 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
00214                                            pNOR_CallbackTypeDef pCallback);
00215 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
00216 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
00217 /**
00218   * @}
00219   */
00220
00221 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
00222   * @{
00223   */
00224
00225 /* NOR Control functions  *****************************************************/
00226 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00227 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00228 /**
00229   * @}
00230   */
00231
00232 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
00233   * @{
00234   */
00235
00236 /* NOR State functions ********************************************************/
00237 HAL_NOR_StateTypeDef  HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
00238 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00239 /**
00240   * @}
00241   */
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Private types -------------------------------------------------------------*/
00248 /* Private variables ---------------------------------------------------------*/
00249 /* Private constants ---------------------------------------------------------*/
00250 /** @defgroup NOR_Private_Constants NOR Private Constants
00251   * @{
00252   */
00253 /* NOR device IDs addresses */
00254 #define MC_ADDRESS               ((uint16_t)0x0000)
00255 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00256 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00257 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00258
00259 /* NOR CFI IDs addresses */
00260 #define CFI1_ADDRESS             ((uint16_t)0x0061)
00261 #define CFI2_ADDRESS             ((uint16_t)0x0062)
00262 #define CFI3_ADDRESS             ((uint16_t)0x0063)
00263 #define CFI4_ADDRESS             ((uint16_t)0x0064)
00264
00265 /* NOR operation wait timeout */
00266 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
00267
00268 /* NOR memory data width */
00269 #define NOR_MEMORY_8B            ((uint8_t)0x00)
00270 #define NOR_MEMORY_16B           ((uint8_t)0x01)
00271
00272 /* NOR memory device read/write start address */
00273 #define NOR_MEMORY_ADRESS1       (0x60000000U)
00274 #define NOR_MEMORY_ADRESS2       (0x64000000U)
00275 #define NOR_MEMORY_ADRESS3       (0x68000000U)
00276 #define NOR_MEMORY_ADRESS4       (0x6C000000U)
00277 /**
00278   * @}
00279   */
00280
00281 /* Private macros ------------------------------------------------------------*/
00282 /** @defgroup NOR_Private_Macros NOR Private Macros
00283   * @{
00284   */
00285 /**
00286   * @brief  NOR memory address shifting.
00287   * @param  __NOR_ADDRESS NOR base address
00288   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
00289   * @param  __ADDRESS__ NOR memory address
00290   * @retval NOR shifted address value
00291   */
00292 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
00293   ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
00294               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
00295               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00296
00297 /**
00298   * @brief  NOR memory write data to specified address.
00299   * @param  __ADDRESS__ NOR memory address
00300   * @param  __DATA__ Data to write
00301   * @retval None
00302   */
00303 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
00304                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
00305                                                __DSB();                                                    \
00306                                              } while(0)
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 #endif /* FMC_BANK1 */
00321
00322 #ifdef __cplusplus
00323 }
00324 #endif
00325
00326 #endif /* STM32G4xx_HAL_NOR_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_opamp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the operational amplifiers peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + I/O operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025 ================================================================================
00026           ##### OPAMP Peripheral Features #####
00027 ================================================================================
00028
00029   [..] The device integrates up to 6 operational amplifiers OPAMP1, OPAMP2,
00030        OPAMP3, OPAMP4, OPAMP5 and OPAMP6:
00031
00032        (#) The OPAMP(s) provides several exclusive running modes.
00033        (++) Standalone mode
00034        (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
00035        (++) Follower mode
00036
00037        (#) The OPAMP(s) provide(s) calibration capabilities.
00038        (++) Calibration aims at correcting some offset for running mode.
00039        (++) The OPAMP uses either factory calibration settings OR user defined
00040            calibration (trimming) settings (i.e. trimming mode).
00041        (++) The user defined settings can be figured out using self calibration
00042            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
00043        (++) HAL_OPAMP_SelfCalibrate:
00044        (++) Runs automatically the calibration in 2 steps.
00045             (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
00046             (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
00047             appropriate and enough in most cases).
00048        (++) Enables the user trimming mode
00049        (++) Updates the init structure with trimming values with fresh calibration
00050             results.
00051             The user may store the calibration results for larger
00052             (ex monitoring the trimming as a function of temperature
00053             for instance)
00054        (++) for STM32G4 devices having 6 OPAMPs
00055             HAL_OPAMPEx_SelfCalibrateAll
00056             runs calibration of 6 OPAMPs in parallel.
00057
00058        (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
00059            mode can be set on top.
00060        (++) Timer-controlled Mux mode allows Automatic switching of inputs
00061            configuration (inverting and non inverting).
00062        (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
00063            the user shall select secondary inverting and non inverting inputs.
00064        (++) TIM1 OC6, TIM8 OC6 and TIM20 OC6 provides the alternate switching
00065            tempo between defaults (primary) and secondary inputs.
00066        (++) These 3 timers (TIM1, TIM8 and TIM20) can be combined to design a more
00067            complex switching scheme. So that any of the selected channel can initiate
00068            the configuration switch.
00069
00070        (#) Running mode: Standalone mode
00071        (++) Gain is set externally (gain depends on external loads).
00072        (++) Follower mode also possible externally by connecting the inverting input to
00073            the output.
00074
00075        (#) Running mode: Follower mode
00076        (++) Inverting Input is not connected.
00077
00078        (#) Running mode: Programmable Gain Amplifier (PGA) mode
00079            (Resistor feedback output)
00080        (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
00081            output.
00082        (++) The OPAMP inverting input can be "not" connected, signal to amplify is
00083            connected to non inverting input and gain is positive (2,4,8,16,32 or 64)
00084        (++) The OPAMP inverting input can be connected to VINM0:
00085            If signal is applied to non inverting input, gain is positive (2,4,8,16,32 or 64).
00086            If signal is applied to inverting input, gain is negative (-1,-3,-7,-15-,31 or -63).
00087            In both cases, the other input can be used as bias.
00088
00089
00090             ##### How to use this driver #####
00091 ================================================================================
00092   [..]
00093
00094     *** High speed / normal power mode ***
00095     ============================================
00096     [..]  To run in high speed mode:
00097
00098       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00099       (++) Select OPAMP_POWERMODE_HIGHSPEED
00100       (++) Otherwise select OPAMP_POWERMODE_NORMALSPEED
00101
00102     *** Calibration ***
00103     ============================================
00104     [..]  To run the OPAMP calibration self calibration:
00105
00106       (#) Start calibration using HAL_OPAMP_SelfCalibrate.
00107            Store the calibration results.
00108
00109     *** Running mode ***
00110     ============================================
00111     [..]  To use the OPAMP, perform the following steps:
00112
00113       (#) Fill in the HAL_OPAMP_MspInit() to
00114       (++) Configure the OPAMP input AND output in analog mode using
00115           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
00116
00117       (#) Registrate Callbacks
00118       (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
00119            allows the user to configure dynamically the driver callbacks.
00120
00121       (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
00122            it allows to register following callbacks:
00123       (+++) MspInitCallback         : OPAMP MspInit.
00124       (+++) MspDeInitCallback       : OPAMP MspDeInit.
00125            This function takes as parameters the HAL peripheral handle, the Callback ID
00126            and a pointer to the user callback function.
00127
00128       (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
00129            weak (surcharged) function. It allows to reset following callbacks:
00130       (+++) MspInitCallback         : OPAMP MspInit.
00131       (+++) MspDeInitCallback       : OPAMP MspDeInit.
00132       (+++) All Callbacks
00133
00134       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00135       (++) Select the mode
00136       (++) Select the inverting input
00137       (++) Select the non-inverting input
00138       (++) Select if the internal output should be enabled/disabled (if enabled, regular I/O output is disabled)
00139       (++) Select if the Timer controlled Mux is disabled or enabled and controlled by specified timer(s)
00140       (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
00141       (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
00142       (++) If PGA mode is enabled, Select if inverting input is connected.
00143       (++) If PGA mode is enabled, Select PGA gain to be used.
00144       (++) Select either factory or user defined trimming mode.
00145       (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
00146           (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
00147
00148       (#) Enable the OPAMP using HAL_OPAMP_Start() function.
00149
00150       (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
00151
00152       (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() & HAL_OPAMP_TimerMuxLock functions.
00153           From then the configuration can only be modified
00154       (++) After HW reset
00155       (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.
00156
00157     *** Running mode: change of configuration while OPAMP ON  ***
00158     ============================================
00159     [..]    To Re-configure OPAMP when OPAMP is ON (change on the fly)
00160       (#) If needed, fill in the HAL_OPAMP_MspInit()
00161       (++) This is the case for instance if you wish to use new OPAMP I/O
00162
00163       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00164       (++) As in configure case, selects first the parameters you wish to modify.
00165       (++) If OPAMP control register is locked, it is not possible to modify any values
00166           on the fly (even the timer controlled mux parameters).
00167       (++) If OPAMP timer controlled mux mode register is locked, it is possible to modify any values
00168           of the control register but none on the timer controlled mux mode one.
00169
00170       (#) Change from high speed mode to normal power mode (& vice versa) requires
00171           first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
00172           In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
00173           alone.
00174
00175   @endverbatim
00176   ******************************************************************************
00177   */
00178
00179 /*
00180   Additional Tables:
00181     The OPAMPs non inverting input (both default and secondary) can be
00182     selected among the list shown by table below.
00183
00184     The OPAMPs non inverting input (both default and secondary) can be
00185     selected among the list shown by table below.
00186
00187     Table 1.  OPAMPs inverting/non-inverting inputs for the STM32G4 devices:
00188     +-----------------------------------------------------------------------------------------------+
00189     |                 |        | OPAMP1   | OPAMP2   | OPAMP3      | OPAMP4   | OPAMP5   | OPAMP6   |
00190     |-----------------|--------|----------|----------|-------------|----------|----------|----------|
00191     |                 | No conn|  X       |  X       |  X          |  X       |  X       |  X       |
00192     | Inverting Input | VM0    | PA3      | PA5      | PB2         | PB10     | PB15     | PA1      |
00193     | (1)             | VM1    | PC5      | PC5      | PB10        | PD8      | PA3      | PB1      |
00194     |-----------------|--------|----------|----------|-------------|----------|----------|----------|
00195     |                 | VP0    | PA1      | PA7      | PB0         | PB13     | PB14     | PB12     |
00196     |  Non Inverting  | VP1    | PA3      | PB14     | PB13        | PD11     | PD12     | PD9      |
00197     |    Input        | VP2    | PA7      | PB0      | PA1         | PB11     | PC3      | PB13     |
00198     |                 | VP3    | DAC3_CH1 | PD14     | DAC3_CH2(2) | DAC4_CH1 | DAC4_CH2 | DAC3_CH1 |
00199     +-----------------------------------------------------------------------------------------------+
00200     (1): No connection in follower mode.
00201     (2): Available for STM32G47x/ STM32G48x devices only
00202
00203     Table 2.  OPAMPs outputs for the STM32G4 devices:
00204     +------------------------------------------------------------------------------------+
00205     |                 |        | OPAMP1 | OPAMP2 | OPAMP3   | OPAMP4 | OPAMP5 | OPAMP6   |
00206     |-----------------|--------|--------|--------|----------|--------|--------|----------|
00207     | Output          |        |  PA2   |  PA6   |  PB1     |  PB12  |  PA8   |  PB11    |
00208     |-----------------|--------|--------|--------|----------|--------|--------|----------+
00209     | Internal output |        |  ADC1  |  ADC2  |  ADC2    |  ADC5  |  ADC5  |  ADC4    |
00210     | to ADCs         |        |  CH13  |  CH16  |  CH18    |  CH5   |  CH3   |  CH17(2) |
00211     | (1)             |        |        |        |  ADC3    |        |        |  ADC3    |
00212     |                 |        |        |        |  CH13(2) |        |        |  CH17(3) |
00213     |-----------------|--------|--------|--------|----------|------ -|--------|----------|
00214     | Internal output |        |  ADC1  |  ADC2  |  ADC3    |  ADC4  |  ADC5  |  ADC1    |
00215     | to ADCs input   |        |  CH3   |  CH3   |  CH1(2)  |  CH3   |  CH1   |  CH14    |
00216     | on GPIO         |        |        |        |  ADC1    |  ADC1  |        |  ADC2    |
00217     |                 |        |        |        |  CH12    |  CH11  |        |  CH14    |
00218     +------------------------------------------------------------------------------------+
00219     (1): This ADC channel is connected internally to the OPAMPx_VOUT when OPAINTOEN
00220          bit is set.
00221          In this case, the I/O on which the OPAMPx_VOUT is available, can be used for
00222          another purpose.
00223     (2): Available for STM32G47x/ STM32G48x devices only.
00224     (3): Available for STM32G491/STM32G4A1 devices only.
00225
00226 */
00227
00228 /* Includes ------------------------------------------------------------------*/
00229 #include "stm32g4xx_hal.h"
00230
00231 /** @addtogroup STM32G4xx_HAL_Driver
00232   * @{
00233   */
00234
00235 #ifdef HAL_OPAMP_MODULE_ENABLED
00236
00237 /** @defgroup OPAMP OPAMP
00238   * @brief OPAMP HAL module driver
00239   * @{
00240   */
00241
00242 /* Private typedef -----------------------------------------------------------*/
00243 /* Private define ------------------------------------------------------------*/
00244 /** @defgroup OPAMP_Private_Define OPAMP Private Define
00245   * @{
00246   */
00247 /* CSR register reset value */
00248 #define OPAMP_CSR_RESET_VALUE             (0x00000000UL)
00249 /* CSR register TRIM value upon reset are factory ones, filter them out from CSR register check */
00250 #define OPAMP_CSR_RESET_CHECK_MASK        (~(OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP))
00251 /* CSR init register Mask */
00252 #define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
00253                                                | OPAMP_CSR_HIGHSPEEDEN | OPAMP_CSR_OPAMPINTEN \
00254                                                | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSEL \
00255                                                | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
00256 /* TCMR init register Mask */
00257 #define OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_TCMR_T20CMEN | OPAMP_TCMR_T8CMEN \
00258                                                 | OPAMP_TCMR_T1CMEN | OPAMP_TCMR_VPSSEL \
00259                                                 | OPAMP_TCMR_VMSSEL)
00260 /**
00261   * @}
00262   */
00263
00264 /* Private macro -------------------------------------------------------------*/
00265 /* Private variables ---------------------------------------------------------*/
00266 /* Private function prototypes -----------------------------------------------*/
00267 /* Exported functions ---------------------------------------------------------*/
00268
00269 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00270   * @{
00271   */
00272
00273 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00274   *  @brief    Initialization and Configuration functions
00275   *
00276 @verbatim
00277  ===============================================================================
00278               ##### Initialization and de-initialization  functions #####
00279  ===============================================================================
00280     [..]  This section provides functions allowing to:
00281
00282 @endverbatim
00283   * @{
00284   */
00285
00286 /**
00287   * @brief  Initializes the OPAMP according to the specified
00288   *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.
00289   * @note   If the selected opamp is locked, initialization can't be performed.
00290   *         To unlock the configuration, perform a system reset.
00291   * @param  hopamp OPAMP handle
00292   * @retval HAL status
00293   */
00294 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
00295 {
00296   HAL_StatusTypeDef status = HAL_OK;
00297
00298   /* Check the OPAMP handle allocation and lock status */
00299   /* Init not allowed if calibration is ongoing */
00300   if (hopamp == NULL)
00301   {
00302     return HAL_ERROR;
00303   }
00304   else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00305   {
00306     return HAL_ERROR;
00307   }
00308   else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00309   {
00310     return HAL_ERROR;
00311   }
00312   else
00313   {
00314
00315     /* Check the parameter */
00316     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00317
00318     /* Set OPAMP parameters */
00319     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00320     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
00321     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
00322
00323 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00324     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00325     {
00326       if (hopamp->MspInitCallback == NULL)
00327       {
00328         hopamp->MspInitCallback               = HAL_OPAMP_MspInit;
00329       }
00330     }
00331 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00332
00333     if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00334     {
00335       assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
00336     }
00337     assert_param(IS_FUNCTIONAL_STATE(hopamp->Init.InternalOutput));
00338
00339     assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
00340
00341     if ((hopamp->Init.TimerControlledMuxmode) != OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE)
00342     {
00343       assert_param(IS_OPAMP_SEC_NONINVERTING_INPUT(hopamp->Init.NonInvertingInputSecondary));
00344       assert_param(IS_OPAMP_SEC_INVERTING_INPUT(hopamp->Init.InvertingInputSecondary));
00345     }
00346
00347     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00348     {
00349       assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
00350       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
00351     }
00352
00353     assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
00354     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
00355     {
00356       assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
00357       assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
00358     }
00359
00360     /* Init SYSCFG and the low level hardware to access opamp */
00361     __HAL_RCC_SYSCFG_CLK_ENABLE();
00362
00363     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00364     {
00365       /* Allocate lock resource and initialize it */
00366       hopamp->Lock = HAL_UNLOCKED;
00367     }
00368
00369 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00370     hopamp->MspInitCallback(hopamp);
00371 #else
00372     /* Call MSP init function */
00373     HAL_OPAMP_MspInit(hopamp);
00374 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00375
00376     /* Set OPAMP parameters */
00377     /*     Set  bits according to hopamp->hopamp->Init.Mode value                                 */
00378     /*     Set  bits according to hopamp->hopamp->Init.InvertingInput value                       */
00379     /*     Set  bits according to hopamp->hopamp->Init.NonInvertingInput value                    */
00380     /*     Set  bits according to hopamp->hopamp->Init.InternalOutput value                       */
00381     /*     Set  bits according to hopamp->hopamp->Init.TimerControlledMuxmode value               */
00382     /*     Set  bits according to hopamp->hopamp->Init.InvertingInputSecondary  value             */
00383     /*     Set  bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value           */
00384     /*     Set  bits according to hopamp->hopamp->Init.PgaConnect value                           */
00385     /*     Set  bits according to hopamp->hopamp->Init.PgaGain value                              */
00386     /*     Set  bits according to hopamp->hopamp->Init.UserTrimming value                         */
00387     /*     Set  bits according to hopamp->hopamp->Init.TrimmingValueP value                       */
00388     /*     Set  bits according to hopamp->hopamp->Init.TrimmingValueN value                       */
00389
00390
00391     /* check if OPAMP_PGA_MODE & in Follower mode */
00392     /*   - InvertingInput                         */
00393     /* is Not Applicable                          */
00394
00395     if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
00396     {
00397       /* Update User Trim config first to be able to modify trimming value afterwards */
00398       MODIFY_REG(hopamp->Instance->CSR,
00399                  OPAMP_CSR_USERTRIM,
00400                  hopamp->Init.UserTrimming);
00401       MODIFY_REG(hopamp->Instance->CSR,
00402                  OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK,
00403                  hopamp->Init.PowerMode |
00404                  hopamp->Init.Mode |
00405                  hopamp->Init.NonInvertingInput |
00406                  ((hopamp->Init.InternalOutput == ENABLE) ? OPAMP_CSR_OPAMPINTEN : 0UL) |
00407                  hopamp->Init.PgaConnect |
00408                  hopamp->Init.PgaGain |
00409                  (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) |
00410                  (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
00411     }
00412     else /* OPAMP_STANDALONE_MODE */
00413     {
00414       /* Update User Trim config first to be able to modify trimming value afterwards */
00415       MODIFY_REG(hopamp->Instance->CSR,
00416                  OPAMP_CSR_USERTRIM,
00417                  hopamp->Init.UserTrimming);
00418       MODIFY_REG(hopamp->Instance->CSR,
00419                  OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK,
00420                  hopamp->Init.PowerMode |
00421                  hopamp->Init.Mode |
00422                  hopamp->Init.InvertingInput    |
00423                  hopamp->Init.NonInvertingInput |
00424                  ((hopamp->Init.InternalOutput == ENABLE) ? OPAMP_CSR_OPAMPINTEN : 0UL) |
00425                  hopamp->Init.PgaConnect |
00426                  hopamp->Init.PgaGain |
00427                  (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) |
00428                  (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
00429     }
00430
00431     if ((READ_BIT(hopamp->Instance->TCMR, OPAMP_TCMR_LOCK)) == 0UL)
00432     {
00433       MODIFY_REG(hopamp->Instance->TCMR,
00434                  OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK,
00435                  hopamp->Init.TimerControlledMuxmode |
00436                  hopamp->Init.InvertingInputSecondary  |
00437                  hopamp->Init.NonInvertingInputSecondary);
00438     }
00439
00440     /* Update the OPAMP state*/
00441     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00442     {
00443       /* From RESET state to READY State */
00444       hopamp->State = HAL_OPAMP_STATE_READY;
00445     }
00446     /* else: remain in READY or BUSY state (no update) */
00447
00448     return status;
00449   }
00450 }
00451
00452
00453 /**
00454   * @brief  DeInitializes the OPAMP peripheral
00455   * @note   Deinitialization can't be performed if the OPAMP configuration is locked.
00456   *         To unlock the configuration, perform a system reset.
00457   * @param  hopamp OPAMP handle
00458   * @retval HAL status
00459   */
00460 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
00461 {
00462   HAL_StatusTypeDef status = HAL_OK;
00463
00464   /* Check the OPAMP handle allocation */
00465   /* DeInit not allowed if calibration is ongoing */
00466   if (hopamp == NULL)
00467   {
00468     status = HAL_ERROR;
00469   }
00470   else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00471   {
00472     status = HAL_ERROR;
00473   }
00474   else
00475   {
00476     /* Check the parameter */
00477     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00478
00479     /* Set OPAMP_CSR register to reset value */
00480     WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
00481
00482     /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
00483     /* When OPAMP is locked, unlocking can be achieved thanks to */
00484     /* __HAL_RCC_SYSCFG_CLK_DISABLE() call within HAL_OPAMP_MspDeInit */
00485     /* Note that __HAL_RCC_SYSCFG_CLK_DISABLE() also disables comparator */
00486
00487 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00488     if (hopamp->MspDeInitCallback == NULL)
00489     {
00490       hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
00491     }
00492     /* DeInit the low level hardware */
00493     hopamp->MspDeInitCallback(hopamp);
00494 #else
00495     HAL_OPAMP_MspDeInit(hopamp);
00496 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00497
00498     if (OPAMP_CSR_RESET_VALUE == (hopamp->Instance->CSR & OPAMP_CSR_RESET_CHECK_MASK))
00499     {
00500       /* Update the OPAMP state */
00501       hopamp->State = HAL_OPAMP_STATE_RESET;
00502     }
00503     else /* RESET STATE */
00504     {
00505       /* DeInit not complete */
00506       /* It can be the case if OPAMP was formerly locked */
00507       status = HAL_ERROR;
00508
00509       /* The OPAMP state is NOT updated */
00510     }
00511
00512     /* Process unlocked */
00513     __HAL_UNLOCK(hopamp);
00514   }
00515
00516   return status;
00517 }
00518
00519 /**
00520   * @brief  Initialize the OPAMP MSP.
00521   * @param  hopamp OPAMP handle
00522   * @retval None
00523   */
00524 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
00525 {
00526   /* Prevent unused argument(s) compilation warning */
00527   UNUSED(hopamp);
00528
00529   /* NOTE : This function should not be modified, when the callback is needed,
00530             the HAL_OPAMP_MspInit could be implemented in the user file
00531    */
00532
00533   /* Example */
00534 }
00535
00536 /**
00537   * @brief  DeInitialize OPAMP MSP.
00538   * @param  hopamp OPAMP handle
00539   * @retval None
00540   */
00541 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
00542 {
00543   /* Prevent unused argument(s) compilation warning */
00544   UNUSED(hopamp);
00545
00546   /* NOTE : This function should not be modified, when the callback is needed,
00547             the HAL_OPAMP_MspDeInit could be implemented in the user file
00548    */
00549
00550 }
00551
00552 /**
00553   * @}
00554   */
00555
00556
00557 /** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
00558   *  @brief   Data transfers functions
00559   *
00560 @verbatim
00561  ===============================================================================
00562                       ##### IO operation functions #####
00563  ===============================================================================
00564     [..]
00565     This subsection provides a set of functions allowing to manage the OPAMP data
00566     transfers.
00567
00568 @endverbatim
00569   * @{
00570   */
00571
00572 /**
00573   * @brief  Start the opamp
00574   * @param  hopamp OPAMP handle
00575   * @retval HAL status
00576   */
00577
00578 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
00579 {
00580   HAL_StatusTypeDef status = HAL_OK;
00581
00582   /* Check the OPAMP handle allocation */
00583   /* Check if OPAMP locked */
00584   if (hopamp == NULL)
00585   {
00586     status = HAL_ERROR;
00587   }
00588   else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00589   {
00590     status = HAL_ERROR;
00591   }
00592   else
00593   {
00594     /* Check the parameter */
00595     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00596
00597     if (hopamp->State == HAL_OPAMP_STATE_READY)
00598     {
00599       /* Enable the selected opamp */
00600       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00601
00602       /* Update the OPAMP state*/
00603       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
00604       hopamp->State = HAL_OPAMP_STATE_BUSY;
00605     }
00606     else
00607     {
00608       status = HAL_ERROR;
00609     }
00610
00611
00612   }
00613   return status;
00614 }
00615
00616 /**
00617   * @brief  Stop the opamp
00618   * @param  hopamp OPAMP handle
00619   * @retval HAL status
00620   */
00621 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
00622 {
00623   HAL_StatusTypeDef status = HAL_OK;
00624
00625   /* Check the OPAMP handle allocation */
00626   /* Check if OPAMP locked */
00627   /* Check if OPAMP calibration ongoing */
00628   if (hopamp == NULL)
00629   {
00630     status = HAL_ERROR;
00631   }
00632   else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00633   {
00634     status = HAL_ERROR;
00635   }
00636   else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00637   {
00638     status = HAL_ERROR;
00639   }
00640   else
00641   {
00642     /* Check the parameter */
00643     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00644
00645     if (hopamp->State == HAL_OPAMP_STATE_BUSY)
00646     {
00647       /* Disable the selected opamp */
00648       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00649
00650       /* Update the OPAMP state*/
00651       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
00652       hopamp->State = HAL_OPAMP_STATE_READY;
00653     }
00654     else
00655     {
00656       status = HAL_ERROR;
00657     }
00658   }
00659   return status;
00660 }
00661
00662 /**
00663   * @brief  Run the self calibration of one OPAMP
00664   * @note   Calibration is performed in the mode specified in OPAMP init
00665   *         structure (mode normal or high-speed).
00666   * @param  hopamp handle
00667   * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00668   * @retval HAL status
00669   * @note   Calibration runs about 25 ms.
00670   */
00671
00672 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
00673 {
00674
00675   HAL_StatusTypeDef status = HAL_OK;
00676
00677   uint32_t trimmingvaluen;
00678   uint32_t trimmingvaluep;
00679   uint32_t delta;
00680
00681   /* Check the OPAMP handle allocation */
00682   /* Check if OPAMP locked */
00683   if (hopamp == NULL)
00684   {
00685     status = HAL_ERROR;
00686   }
00687   else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00688   {
00689     status = HAL_ERROR;
00690   }
00691   else
00692   {
00693
00694     /* Check if OPAMP in calibration mode and calibration not yet enable */
00695     if (hopamp->State ==  HAL_OPAMP_STATE_READY)
00696     {
00697       /* Check the parameter */
00698       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00699
00700       /* Set Calibration mode */
00701       /* Non-inverting input connected to calibration reference voltage. */
00702       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00703
00704       /*  user trimming values are used for offset calibration */
00705       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00706
00707       /* Enable calibration */
00708       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
00709
00710       /* 1st calibration - N */
00711       /* Select 90% VREF */
00712       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00713
00714       /* Enable the selected opamp */
00715       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00716
00717       /* Init trimming counter */
00718       /* Medium value */
00719       trimmingvaluen = 16UL;
00720       delta = 8UL;
00721
00722       while (delta != 0UL)
00723       {
00724         /* Set candidate trimming */
00725         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen << OPAMP_INPUT_INVERTING);
00726
00727         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00728         /* Offset trim time: during calibration, minimum time needed between */
00729         /* two steps to have 1 mV accuracy */
00730         HAL_Delay(2);
00731
00732         if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00733         {
00734           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00735           trimmingvaluen += delta;
00736         }
00737         else
00738         {
00739           /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00740           trimmingvaluen -= delta;
00741         }
00742
00743         delta >>= 1;
00744       }
00745
00746       /* Still need to check if righ calibration is current value or un step below */
00747       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00748       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen << OPAMP_INPUT_INVERTING);
00749
00750       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00751       /* Offset trim time: during calibration, minimum time needed between */
00752       /* two steps to have 1 mV accuracy */
00753       HAL_Delay(2);
00754
00755       if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00756       {
00757         /* OPAMP_CSR_OUTCAL is actually one value more */
00758         trimmingvaluen++;
00759         /* Set right trimming */
00760         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen << OPAMP_INPUT_INVERTING);
00761       }
00762
00763       /* 2nd calibration - P */
00764       /* Select 10% VREF */
00765       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00766
00767       /* Init trimming counter */
00768       /* Medium value */
00769       trimmingvaluep = 16UL;
00770       delta = 8UL;
00771
00772       while (delta != 0UL)
00773       {
00774         /* Set candidate trimming */
00775         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
00776
00777         /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00778         /* Offset trim time: during calibration, minimum time needed between */
00779         /* two steps to have 1 mV accuracy */
00780         HAL_Delay(2);
00781
00782         if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00783         {
00784           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00785           trimmingvaluep += delta;
00786         }
00787         else
00788         {
00789           trimmingvaluep -= delta;
00790         }
00791
00792         delta >>= 1;
00793       }
00794
00795       /* Still need to check if righ calibration is current value or un step below */
00796       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
00797       /* Set candidate trimming */
00798       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
00799
00800       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00801       /* Offset trim time: during calibration, minimum time needed between */
00802       /* two steps to have 1 mV accuracy */
00803       HAL_Delay(2);
00804
00805       if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00806       {
00807         /* OPAMP_CSR_OUTCAL is actually one value more */
00808         trimmingvaluep++;
00809         /* Set right trimming */
00810         MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
00811       }
00812
00813       /* Disable calibration */
00814       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
00815
00816       /* Disable the OPAMP */
00817       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00818
00819       /* Set operating mode  */
00820       /* Non-inverting input connected to calibration reference voltage. */
00821       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
00822
00823       /* Self calibration is successful  */
00824       /* Store calibration(user timing) results in init structure. */
00825
00826       /* Write calibration result N */
00827       hopamp->Init.TrimmingValueN = trimmingvaluen;
00828
00829       /* Write calibration result P */
00830       hopamp->Init.TrimmingValueP = trimmingvaluep;
00831
00832       /* Select user timing mode */
00833       /* And updated with calibrated settings */
00834       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
00835       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
00836       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen << OPAMP_INPUT_INVERTING);
00837     }
00838
00839     else
00840     {
00841       /* OPAMP can not be calibrated from this mode */
00842       status = HAL_ERROR;
00843     }
00844   }
00845   return status;
00846 }
00847
00848 /**
00849   * @}
00850   */
00851
00852 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00853   *  @brief   Peripheral Control functions
00854   *
00855 @verbatim
00856  ===============================================================================
00857                       ##### Peripheral Control functions #####
00858  ===============================================================================
00859     [..]
00860     This subsection provides a set of functions allowing to control the OPAMP data
00861     transfers.
00862
00863
00864
00865 @endverbatim
00866   * @{
00867   */
00868
00869 /**
00870   * @brief  Lock the selected opamp configuration.
00871   * @param  hopamp OPAMP handle
00872   * @retval HAL status
00873   */
00874 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
00875 {
00876   HAL_StatusTypeDef status = HAL_OK;
00877
00878   /* Check the OPAMP handle allocation */
00879   /* Check if OPAMP locked */
00880   /* OPAMP can be locked when enabled and running in normal mode */
00881   /*   It is meaningless otherwise */
00882   if (hopamp == NULL)
00883   {
00884     status = HAL_ERROR;
00885   }
00886   else if (hopamp->State != HAL_OPAMP_STATE_BUSY)
00887   {
00888     status = HAL_ERROR;
00889   }
00890   else
00891   {
00892     /* Check the parameter */
00893     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00894
00895     /* Lock OPAMP */
00896     SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_LOCK);
00897
00898     /* OPAMP state changed to locked */
00899     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
00900   }
00901   return status;
00902 }
00903
00904 /**
00905   * @}
00906   */
00907
00908 /**
00909   * @brief  Lock the selected opamp timer controlled mux configuration.
00910   * @param  hopamp OPAMP handle
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_OPAMP_LockTimerMux(OPAMP_HandleTypeDef *hopamp)
00914 {
00915   HAL_StatusTypeDef status = HAL_OK;
00916
00917   /* Check the OPAMP handle allocation                     */
00918   /* Check if OPAMP timer controlled mux is locked         */
00919   /* OPAMP timer controlled mux can be locked when enabled */
00920   /*   It is meaningless otherwise */
00921   if (hopamp == NULL)
00922   {
00923     status = HAL_ERROR;
00924   }
00925   else if (hopamp->State == HAL_OPAMP_STATE_RESET)
00926   {
00927     status = HAL_ERROR;
00928   }
00929   else if (READ_BIT(hopamp->Instance->TCMR, OPAMP_TCMR_LOCK) == OPAMP_TCMR_LOCK)
00930   {
00931     status = HAL_ERROR;
00932   }
00933   else
00934   {
00935     /* Check the parameter */
00936     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00937
00938     /* Lock OPAMP */
00939     SET_BIT(hopamp->Instance->TCMR, OPAMP_TCMR_LOCK);
00940   }
00941   return status;
00942 }
00943
00944 /**
00945   * @}
00946   */
00947
00948 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00949   *  @brief   Peripheral State functions
00950   *
00951 @verbatim
00952  ===============================================================================
00953                       ##### Peripheral State functions #####
00954  ===============================================================================
00955     [..]
00956     This subsection permit to get in run-time the status of the peripheral
00957     and the data flow.
00958
00959 @endverbatim
00960   * @{
00961   */
00962
00963 /**
00964   * @brief  Return the OPAMP state
00965   * @param  hopamp OPAMP handle
00966   * @retval HAL state
00967   */
00968 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
00969 {
00970   /* Check the OPAMP handle allocation */
00971   if (hopamp == NULL)
00972   {
00973     return HAL_OPAMP_STATE_RESET;
00974   }
00975
00976   /* Check the parameter */
00977   assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00978
00979   return hopamp->State;
00980 }
00981
00982 /**
00983   * @brief  Return the OPAMP factory trimming value
00984   * @param  hopamp OPAMP handle
00985   * @param  trimmingoffset Trimming offset (P or N)
00986   * @retval Trimming value (P or N): range: 0->31
00987   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
00988  */
00989
00990 OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
00991 {
00992   uint32_t oldusertrimming = 0UL;
00993   OPAMP_TrimmingValueTypeDef  oldtrimmingvaluep = 0UL, oldtrimmingvaluen = 0UL, trimmingvalue;
00994
00995   /* Check the OPAMP handle allocation */
00996   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
00997   if (hopamp == NULL)
00998   {
00999     return OPAMP_FACTORYTRIMMING_DUMMY;
01000   }
01001   else if (hopamp->State != HAL_OPAMP_STATE_READY)
01002   {
01003     return OPAMP_FACTORYTRIMMING_DUMMY;
01004   }
01005   else
01006   {
01007     /* Check the parameter */
01008     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
01009     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
01010
01011     /* Check the trimming mode */
01012     if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM)) != 0UL)
01013     {
01014       /* User trimming is used */
01015       oldusertrimming = OPAMP_TRIMMING_USER;
01016       /* Store the TrimmingValueP & TrimmingValueN */
01017       oldtrimmingvaluep = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
01018       oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
01019     }
01020
01021     /* Set factory timing mode */
01022     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
01023
01024     /* Get factory trimming  */
01025     if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
01026     {
01027       /* Return TrimOffsetP */
01028       trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING);
01029     }
01030     else
01031     {
01032       /* Return TrimOffsetN */
01033       trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING);
01034     }
01035
01036     /* Restore user trimming configuration if it was formerly set */
01037     /* Check if user trimming was used */
01038     if (oldusertrimming == OPAMP_TRIMMING_USER)
01039     {
01040       /* Restore user trimming */
01041       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
01042       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, oldtrimmingvaluep << OPAMP_INPUT_NONINVERTING);
01043       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, oldtrimmingvaluen << OPAMP_INPUT_INVERTING);
01044     }
01045   }
01046   return trimmingvalue;
01047 }
01048 /**
01049   * @}
01050   */
01051
01052 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
01053 /**
01054   * @brief  Register a User OPAMP Callback
01055   *         To be used instead of the weak (surcharged) predefined callback
01056   * @param hopamp : OPAMP handle
01057   * @param CallbackID : ID of the callback to be registered
01058   *        This parameter can be one of the following values:
01059   *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID       OPAMP MspInit callback ID
01060   *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID     OPAMP MspDeInit callback ID
01061   * @param pCallback : pointer to the Callback function
01062   * @retval status
01063   */
01064 HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId,
01065                                              pOPAMP_CallbackTypeDef pCallback)
01066 {
01067   HAL_StatusTypeDef status = HAL_OK;
01068
01069   if (pCallback == NULL)
01070   {
01071     return HAL_ERROR;
01072   }
01073
01074   /* Process locked */
01075   __HAL_LOCK(hopamp);
01076
01077   if (hopamp->State == HAL_OPAMP_STATE_READY)
01078   {
01079     switch (CallbackId)
01080     {
01081       case HAL_OPAMP_MSPINIT_CB_ID :
01082         hopamp->MspInitCallback = pCallback;
01083         break;
01084       case HAL_OPAMP_MSPDEINIT_CB_ID :
01085         hopamp->MspDeInitCallback = pCallback;
01086         break;
01087       default :
01088         /* update return status */
01089         status =  HAL_ERROR;
01090         break;
01091     }
01092   }
01093   else if (hopamp->State == HAL_OPAMP_STATE_RESET)
01094   {
01095     switch (CallbackId)
01096     {
01097       case HAL_OPAMP_MSPINIT_CB_ID :
01098         hopamp->MspInitCallback = pCallback;
01099         break;
01100       case HAL_OPAMP_MSPDEINIT_CB_ID :
01101         hopamp->MspDeInitCallback = pCallback;
01102         break;
01103       default :
01104         /* update return status */
01105         status =  HAL_ERROR;
01106         break;
01107     }
01108   }
01109   else
01110   {
01111     /* update return status */
01112     status =  HAL_ERROR;
01113   }
01114
01115   /* Release Lock */
01116   __HAL_UNLOCK(hopamp);
01117   return status;
01118 }
01119
01120 /**
01121   * @brief  Unregister a User OPAMP Callback
01122   *         OPAMP Callback is redirected to the weak (surcharged) predefined callback
01123   * @param hopamp : OPAMP handle
01124   * @param CallbackID : ID of the callback to be unregistered
01125   *        This parameter can be one of the following values:
01126   *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID              OPAMP MSP Init Callback ID
01127   *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID            OPAMP MSP DeInit Callback ID
01128   *          @arg @ref HAL_OPAMP_ALL_CB_ID                   OPAMP All Callbacks
01129   * @retval status
01130   */
01131
01132 HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId)
01133 {
01134   HAL_StatusTypeDef status = HAL_OK;
01135
01136   /* Process locked */
01137   __HAL_LOCK(hopamp);
01138
01139   if (hopamp->State == HAL_OPAMP_STATE_READY)
01140   {
01141     switch (CallbackId)
01142     {
01143       case HAL_OPAMP_MSPINIT_CB_ID :
01144         hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01145         break;
01146       case HAL_OPAMP_MSPDEINIT_CB_ID :
01147         hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01148         break;
01149       case HAL_OPAMP_ALL_CB_ID :
01150         hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01151         hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01152         break;
01153       default :
01154         /* update return status */
01155         status =  HAL_ERROR;
01156         break;
01157     }
01158   }
01159   else if (hopamp->State == HAL_OPAMP_STATE_RESET)
01160   {
01161     switch (CallbackId)
01162     {
01163       case HAL_OPAMP_MSPINIT_CB_ID :
01164         hopamp->MspInitCallback = HAL_OPAMP_MspInit;
01165         break;
01166       case HAL_OPAMP_MSPDEINIT_CB_ID :
01167         hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
01168         break;
01169       default :
01170         /* update return status */
01171         status =  HAL_ERROR;
01172         break;
01173     }
01174   }
01175   else
01176   {
01177     /* update return status */
01178     status =  HAL_ERROR;
01179   }
01180
01181   /* Release Lock */
01182   __HAL_UNLOCK(hopamp);
01183   return status;
01184 }
01185
01186 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
01187
01188 /**
01189   * @}
01190   */
01191
01192 /**
01193   * @}
01194   */
01195
01196 #endif /* HAL_OPAMP_MODULE_ENABLED */
01197 /**
01198   * @}
01199   */
01200
01201
01202
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_opamp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_OPAMP_H
00021 #define STM32G4xx_HAL_OPAMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup OPAMP
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup OPAMP_Exported_Types OPAMP Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  OPAMP Init structure definition
00045   */
00046
00047 typedef struct
00048 {
00049   uint32_t PowerMode;                   /*!< Specifies the power mode Normal or High Speed.
00050                                              This parameter must be a value of @ref OPAMP_PowerMode */
00051
00052   uint32_t Mode;                        /*!< Specifies the OPAMP mode
00053                                              This parameter must be a value of @ref OPAMP_Mode
00054                                              mode is either Standalone, Follower or PGA */
00055
00056   uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & Pga modes
00057                                                - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
00058                                                  This parameter must be a value of @ref OPAMP_InvertingInput
00059                                                  InvertingInput is either VINM0 or VINM1
00060                                                - In PGA mode:          i.e when mode is OPAMP_PGA_MODE
00061                                                  & in Follower mode    i.e when mode is OPAMP_FOLLOWER_MODE
00062                                                  This parameter is Not Applicable */
00063
00064   uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
00065                                              This parameter must be a value of @ref OPAMP_NonInvertingInput
00066                                              NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
00067
00068   FunctionalState InternalOutput;       /*!< Specifies the configuration of the internal output from OPAMP to ADC.
00069                                              This parameter can be ENABLE or DISABLE
00070                                              Note: When this output is enabled, regular output to I/O is disabled */
00071
00072   uint32_t TimerControlledMuxmode;      /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
00073                                              This parameter must be a single value of @ref OPAMP_TimerControlledMuxmode
00074                                              or a combination of them to build a more complex switch scheme by
00075                                              using different timers */
00076
00077   uint32_t InvertingInputSecondary;     /*!< Specifies the inverting input (secondary) of the opamp when
00078                                              TimerControlledMuxmode is enabled
00079                                              i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
00080                                                - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
00081                                                  This parameter must be a value of @ref OPAMP_InvertingInputSecondary
00082                                                  InvertingInputSecondary is either VINM0 or VINM1
00083                                                - In PGA mode:          i.e when mode is OPAMP_PGA_MODE
00084                                                  & in Follower mode    i.e when mode is OPAMP_FOLLOWER_MODE
00085                                                  This parameter must be a value of @ref OPAMP_InvertingInputSecondary
00086                                                  and is used to choose secondary mode (PGA or follower) */
00087
00088   uint32_t NonInvertingInputSecondary;  /*!< Specifies the non inverting input (secondary) of the opamp when
00089                                              TimerControlledMuxmode is enabled
00090                                              i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
00091                                              This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
00092                                              NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
00093
00094   uint32_t PgaConnect;                  /*!< Specifies the inverting pin in PGA mode
00095                                              i.e. when mode is OPAMP_PGA_MODE
00096                                              This parameter must be a value of @ref OPAMP_PgaConnect
00097                                              Either: not connected, connected to VINM0
00098                                              In this last case, VINM0 can then be used to input signal (negative gain case
00099                                              with or without bias on VINPx) or to input bias (positive gain case with bias) */
00100
00101   uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
00102                                              i.e. when mode is OPAMP_PGA_MODE.
00103                                              This parameter must be a value of @ref OPAMP_PgaGain
00104                                              (2, 4, 8, 16, 32 or 64) for positive gain & (-1, -3 ,-7, -15, -31 or -63) for negative gain */
00105
00106   uint32_t UserTrimming;                /*!< Specifies the trimming mode
00107                                              This parameter must be a value of @ref OPAMP_UserTrimming
00108                                              UserTrimming is either factory or user trimming */
00109
00110   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
00111                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00112                                              This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00113
00114   uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
00115                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00116                                              This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00117
00118 } OPAMP_InitTypeDef;
00119
00120 /**
00121   * @brief  HAL State structures definition
00122   */
00123
00124 typedef enum
00125 {
00126   HAL_OPAMP_STATE_RESET               = 0x00000000UL, /*!< OPAMP is not yet Initialized          */
00127
00128   HAL_OPAMP_STATE_READY               = 0x00000001UL, /*!< OPAMP is initialized and ready for use */
00129   HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002UL, /*!< OPAMP is enabled in auto calibration mode */
00130
00131   HAL_OPAMP_STATE_BUSY                = 0x00000004UL, /*!< OPAMP is enabled and running in normal mode */
00132   HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005UL, /*!< OPAMP control register is locked
00133                                                          only system reset allows reconfiguring the opamp. */
00134
00135 } HAL_OPAMP_StateTypeDef;
00136
00137 /**
00138   * @brief OPAMP Handle Structure definition
00139   */
00140 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00141 typedef struct __OPAMP_HandleTypeDef
00142 #else
00143 typedef struct
00144 #endif
00145 {
00146   OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
00147   OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
00148   HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
00149   HAL_LockTypeDef   Lock;                           /*!< Locking object          */
00150   __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
00151
00152 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00153   void (* MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
00154   void (* MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
00155 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00156
00157 } OPAMP_HandleTypeDef;
00158
00159 /**
00160   * @brief OPAMP_TrimmingValueTypeDef definition
00161   */
00162
00163 typedef  uint32_t OPAMP_TrimmingValueTypeDef;
00164 /**
00165   * @}
00166   */
00167
00168 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00169 /**
00170   * @brief  HAL OPAMP Callback ID enumeration definition
00171   */
00172 typedef enum
00173 {
00174   HAL_OPAMP_MSPINIT_CB_ID                     = 0x01UL,  /*!< OPAMP MspInit Callback ID           */
00175   HAL_OPAMP_MSPDEINIT_CB_ID                   = 0x02UL,  /*!< OPAMP MspDeInit Callback ID         */
00176   HAL_OPAMP_ALL_CB_ID                          = 0x03UL   /*!< OPAMP All ID                        */
00177 } HAL_OPAMP_CallbackIDTypeDef;
00178
00179 /**
00180   * @brief  HAL OPAMP Callback pointer definition
00181   */
00182 typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
00183 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00184
00185
00186 /* Exported constants --------------------------------------------------------*/
00187 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
00188   * @{
00189   */
00190 /** @defgroup OPAMP_Mode OPAMP Mode
00191   * @{
00192   */
00193 #define OPAMP_STANDALONE_MODE            (0x00000000UL)         /*!< standalone mode */
00194 #define OPAMP_PGA_MODE                   OPAMP_CSR_VMSEL_1      /*!< PGA mode */
00195 #define OPAMP_FOLLOWER_MODE              OPAMP_CSR_VMSEL        /*!< follower mode */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
00201   * @{
00202   */
00203 #define OPAMP_NONINVERTINGINPUT_IO0         (0x00000000UL)        /*!< Non inverting input connected to I/O VINP0
00204                                                                        (PA1  for OPAMP1, PA7  for OPAMP2, PB0  for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
00205                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00206 #define OPAMP_NONINVERTINGINPUT_IO1         OPAMP_CSR_VPSEL_0     /*!< Non inverting input connected to I/O VINP1
00207                                                                        (PA3  for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9  for OPAMP6)
00208                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00209 #define OPAMP_NONINVERTINGINPUT_IO2         OPAMP_CSR_VPSEL_1     /*!< Non inverting input connected to I/O VINP2
00210                                                                        (PA7  for OPAMP1, PB0  for OPAMP2, PA1  for OPAMP3, PB11 for OPAMP4, PC3  for OPAMP5, PB13 for OPAMP6)
00211                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00212 #define OPAMP_NONINVERTINGINPUT_IO3         OPAMP_CSR_VPSEL       /*!< Non inverting input connected to I/O VINP3
00213                                                                        (PD14 for OPAMP2) */
00214 #define OPAMP_NONINVERTINGINPUT_DAC         OPAMP_CSR_VPSEL       /*!< Non inverting input connected internally to DAC channel
00215                                                                        (DAC3_CH1 for OPAMP1, DAC3_CH2  for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
00216                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
00222   * @{
00223   */
00224 #define OPAMP_INVERTINGINPUT_IO0       (0x00000000UL)              /*!< Inverting input connected to I/O VINM0
00225                                                                        (PA3  for OPAMP1, PA5  for OPAMP2, PB2  for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1  for OPAMP6)
00226                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00227 #define OPAMP_INVERTINGINPUT_IO1       OPAMP_CSR_VMSEL_0           /*!< Inverting input connected to I/0 VINM1
00228                                                                        (PC5  for OPAMP1, PC5  for OPAMP2, PB10 for OPAMP3, PB8  for OPAMP4, PA3  for OPAMP5, PB1  for OPAMP6)
00229                                                                        Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
00235   * @note The switch can be controlled either by a single timer or a combination of them,
00236   *       in this case application has to 'ORed' the values below
00237   *       ex OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6
00238   * @{
00239   */
00240 #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE    (0x00000000UL)       /*!< Timer controlled Mux mode disabled */
00241 #define OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6   OPAMP_TCMR_T1CMEN    /*!< Timer controlled Mux mode enabled using TIM1 OC6 */
00242 #define OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6   OPAMP_TCMR_T8CMEN    /*!< Timer controlled Mux mode enabled using TIM8 OC6 */
00243 #if defined(TIM20)
00244 #define OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6  OPAMP_TCMR_T20CMEN   /*!< Timer controlled Mux mode enabled using TIM20 OC6
00245                                                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
00246 #endif
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
00252   * @{
00253   */
00254 #define OPAMP_SEC_NONINVERTINGINPUT_IO0         (0x00000000UL)        /*!< Secondary non inverting input connected to I/O VINP0
00255                                                                            (PA1  for OPAMP1, PA7  for OPAMP2, PB0  for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
00256                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00257 #define OPAMP_SEC_NONINVERTINGINPUT_IO1         OPAMP_TCMR_VPSSEL_0   /*!< Secondary non inverting input connected to I/O VINP1
00258                                                                            (PA3  for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9  for OPAMP6)
00259                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00260 #define OPAMP_SEC_NONINVERTINGINPUT_IO2         OPAMP_TCMR_VPSSEL_1   /*!< Secondary non inverting input connected to I/O VINP2
00261                                                                            (PA7  for OPAMP1, PB0  for OPAMP2, PA1  for OPAMP3, PB11 for OPAMP4, PC3  for OPAMP5, PB13 for OPAMP6)
00262                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00263 #define OPAMP_SEC_NONINVERTINGINPUT_IO3         OPAMP_TCMR_VPSSEL     /*!< Secondary non inverting input connected to I/O VINP3
00264                                                                            (PD14 for OPAMP2) */
00265 #define OPAMP_SEC_NONINVERTINGINPUT_DAC         OPAMP_TCMR_VPSSEL     /*!< Secondary non inverting input connected internally to DAC channel
00266                                                                            (DAC3_CH1 for OPAMP1, DAC3_CH2  for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
00267                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
00273   * @{
00274   */
00275 #define OPAMP_SEC_INVERTINGINPUT_IO0       (0x00000000UL)              /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
00276                                                                             has been configured by call to @ref HAL_OPAMP_Init().
00277                                                                             Secondary inverting input connected to I/O VINM0
00278                                                                             (PA3  for OPAMP1, PA5  for OPAMP2, PB2  for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1  for OPAMP6)
00279                                                                             Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00280 #define OPAMP_SEC_INVERTINGINPUT_IO1       OPAMP_TCMR_VMSSEL           /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
00281                                                                             has been configured by call to @ref HAL_OPAMP_Init().
00282                                                                             Secondary inverting input connected to I/0 VINM1
00283                                                                             (PC5  for OPAMP1, PC5  for OPAMP2, PB10 for OPAMP3, PB8  for OPAMP4, PA3  for OPAMP5, PB1  for OPAMP6)
00284                                                                             Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00285 #define OPAMP_SEC_INVERTINGINPUT_PGA       (0x00000000UL)              /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
00286                                                                            is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
00287                                                                            OPAMP secondary inverting input is:
00288                                                                              - Not connected if configured mode is @ref OPAMP_FOLLOWER_MODE
00289                                                                              - Not connected if configured mode is @ref OPAMP_PGA_MODE and PGA connect mode is @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
00290                                                                              - Connected to VINM0 and possibly VINM1 if any of the other modes as been configured
00291                                                                            (see @ref OPAMP_PgaConnect description for more details on PGA connection modes) */
00292 #define OPAMP_SEC_INVERTINGINPUT_FOLLOWER  OPAMP_TCMR_VMSSEL           /*!< OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
00293                                                                            is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
00294                                                                            OPAMP secondary inverting input is not connected. */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
00300   * @{
00301   */
00302 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO               (0x00000000UL)                            /*!< In PGA mode, the inverting input is not connected */
00303 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0              OPAMP_CSR_PGGAIN_4                        /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
00304 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS         OPAMP_CSR_PGGAIN_3                        /*!< In PGA mode, the inverting input is connected to VINM0
00305                                                                                                       - Input signal on VINM0, bias on VINPx: negative gain
00306                                                                                                       - Bias on VINM0, input signal on VINPx: positive gain */
00307 #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS     (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3)   /*!< In PGA mode, the inverting input is connected to VINM0
00308                                                                                                       - Input signal on VINM0, bias on VINPx: negative gain
00309                                                                                                       - Bias on VINM0, input signal on VINPx: positive gain
00310                                                                                                       And VINM1 is connected too for filtering */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup OPAMP_PgaGain OPAMP Pga Gain
00316   * @note Gain sign:
00317   *         - is positive if the @ref OPAMP_PgaConnect configuration is
00318   *           @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
00319   *         - may be positive or negative if the @ref OPAMP_PgaConnect configuration is
00320   *           @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS
00321   *       see @ref OPAMP_PgaConnect for more details
00322   * @{
00323   */
00324 #define OPAMP_PGA_GAIN_2_OR_MINUS_1          (0x00000000UL)                                                      /*!< PGA gain could be 2  or -1  */
00325 #define OPAMP_PGA_GAIN_4_OR_MINUS_3          (                                          OPAMP_CSR_PGGAIN_0)      /*!< PGA gain could be 4  or -3  */
00326 #define OPAMP_PGA_GAIN_8_OR_MINUS_7          (                     OPAMP_CSR_PGGAIN_1                     )      /*!< PGA gain could be 8  or -7  */
00327 #define OPAMP_PGA_GAIN_16_OR_MINUS_15        (                     OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)      /*!< PGA gain could be 16 or -15 */
00328 #define OPAMP_PGA_GAIN_32_OR_MINUS_31        (OPAMP_CSR_PGGAIN_2                                          )      /*!< PGA gain could be 32 or -31 */
00329 #define OPAMP_PGA_GAIN_64_OR_MINUS_63        (OPAMP_CSR_PGGAIN_2 |                      OPAMP_CSR_PGGAIN_0)      /*!< PGA gain could be 64 or -63 */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup OPAMP_PowerMode OPAMP PowerMode
00335   * @{
00336   */
00337 #define OPAMP_POWERMODE_NORMALSPEED   (0x00000000UL)         /*!< Output in normal mode */
00338 #define OPAMP_POWERMODE_HIGHSPEED     OPAMP_CSR_HIGHSPEEDEN  /*!< Output in highspeed mode */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
00344   * @{
00345   */
00346 #define OPAMP_TRIMMING_FACTORY        (0x00000000UL)                       /*!< Factory trimming */
00347 #define OPAMP_TRIMMING_USER           OPAMP_CSR_USERTRIM                   /*!< User trimming */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
00353   * @{
00354   */
00355 #define OPAMP_FACTORYTRIMMING_DUMMY    (0xFFFFFFFFUL)                         /*!< Dummy trimming value */
00356
00357 #define OPAMP_FACTORYTRIMMING_N        (0x00000000UL)                         /*!< Offset trimming N */
00358 #define OPAMP_FACTORYTRIMMING_P        (0x00000001UL)                         /*!< Offset trimming P */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup OPAMP_VREF OPAMP VREF
00364   * @{
00365   */
00366 #define OPAMP_VREF_3VDDA                    (0x00000000UL)          /*!< OPAMP Vref = 3.3% VDDA */
00367 #define OPAMP_VREF_10VDDA                    OPAMP_CSR_CALSEL_0     /*!< OPAMP Vref = 10% VDDA  */
00368 #define OPAMP_VREF_50VDDA                    OPAMP_CSR_CALSEL_1     /*!< OPAMP Vref = 50% VDDA  */
00369 #define OPAMP_VREF_90VDDA                    OPAMP_CSR_CALSEL       /*!< OPAMP Vref = 90% VDDA  */
00370 /**
00371   * @}
00372   */
00373
00374 /**
00375   * @}
00376   */
00377
00378
00379 /* Private constants ---------------------------------------------------------*/
00380 /** @defgroup OPAMP_Private_Constants OPAMP Private Constants
00381   * @brief   OPAMP Private constants and defines
00382   * @{
00383   */
00384 /** @defgroup OPAMP_Input OPAMP Input
00385   * @{
00386   */
00387 #define OPAMP_INPUT_INVERTING                 ( 24UL) /*!< Inverting input */
00388 #define OPAMP_INPUT_NONINVERTING              ( 19UL) /*!< Non inverting input */
00389
00390 #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
00391                                ((INPUT) == OPAMP_INPUT_NONINVERTING))
00392 /**
00393   * @}
00394   */
00395
00396 /**
00397   * @}
00398   */
00399
00400
00401 /* Private macro -------------------------------------------------------------*/
00402
00403 /** @defgroup OPAMP_Private_Macros OPAMP Private Macros
00404   * @{
00405   */
00406
00407 #define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
00408                                                ((INPUT) == OPAMP_PGA_MODE) || \
00409                                                ((INPUT) == OPAMP_FOLLOWER_MODE))
00410
00411 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00412                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
00413                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
00414                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3) || \
00415                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC))
00416
00417 #define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00418                                          ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
00419
00420 #if defined(TIM20)
00421 #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE)  \
00422   ((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 |    \
00423                  OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 |    \
00424                  OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6))
00425 #else
00426 #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE)  \
00427   ((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 |    \
00428                  OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6))
00429 #endif
00430
00431 #define IS_OPAMP_SEC_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
00432                                                 ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
00433                                                 ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
00434                                                 ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3) || \
00435                                                 ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_DAC))
00436
00437 #define IS_OPAMP_SEC_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
00438                                              ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1) || \
00439                                              ((INPUT) == OPAMP_SEC_INVERTINGINPUT_PGA) || \
00440                                              ((INPUT) == OPAMP_SEC_INVERTINGINPUT_FOLLOWER))
00441
00442 #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)            || \
00443                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0)           || \
00444                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS)      || \
00445                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
00446
00447 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1)   || \
00448                                  ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3)   || \
00449                                  ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7)   || \
00450                                  ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15) || \
00451                                  ((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \
00452                                  ((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63))
00453
00454 #define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMALSPEED) || \
00455                                        ((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) )
00456
00457 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00458                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00459
00460 #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
00461                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
00462
00463 #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FUL)
00464
00465 #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA)  || \
00466                              ((VREF) == OPAMP_VREF_10VDDA) || \
00467                              ((VREF) == OPAMP_VREF_50VDDA) || \
00468                              ((VREF) == OPAMP_VREF_90VDDA))
00469 /**
00470   * @}
00471   */
00472
00473
00474 /* Exported macros -----------------------------------------------------------*/
00475 /** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
00476   * @{
00477   */
00478
00479 /** @brief Reset OPAMP handle state
00480   * @param  __HANDLE__ OPAMP handle.
00481   * @retval None
00482   */
00483 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
00484
00485 /**
00486   * @}
00487   */
00488
00489 /* Include OPAMP HAL Extended module */
00490 #include "stm32g4xx_hal_opamp_ex.h"
00491
00492 /* Exported functions --------------------------------------------------------*/
00493 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00494   * @{
00495   */
00496
00497 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00498   * @{
00499   */
00500
00501 /* Initialization/de-initialization functions  **********************************/
00502 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
00503 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp);
00504 void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
00505 void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
00506 /**
00507   * @}
00508   */
00509
00510
00511 /** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
00512   * @{
00513   */
00514
00515 /* I/O operation functions  *****************************************************/
00516 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
00517 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
00518 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
00519
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00525   * @{
00526   */
00527
00528 /* Peripheral Control functions  ************************************************/
00529 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
00530 /* OPAMP callback registering/unregistering */
00531 HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId,
00532                                              pOPAMP_CallbackTypeDef pCallback);
00533 HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);
00534 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
00535
00536 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
00537 HAL_StatusTypeDef HAL_OPAMP_LockTimerMux(OPAMP_HandleTypeDef *hopamp);
00538
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00544   * @{
00545   */
00546
00547 /* Peripheral State functions  **************************************************/
00548 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
00549 OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
00550
00551 /**
00552   * @}
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /**
00560   * @}
00561   */
00562
00563 /**
00564   * @}
00565   */
00566
00567
00568 #ifdef __cplusplus
00569 }
00570 #endif
00571
00572 #endif /* STM32G4xx_HAL_OPAMP_H */
00573
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_opamp_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_opamp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended OPAMP HAL module driver.
00006   *
00007   *          This file provides firmware functions to manage the following
00008   *          functionalities of the operational amplifiers peripheral:
00009   *           + Extended Initialization and de-initialization functions
00010   *           + Extended Peripheral Control functions
00011   *
00012   @verbatim
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 #ifdef HAL_OPAMP_MODULE_ENABLED
00034
00035 /** @defgroup OPAMPEx OPAMPEx
00036   * @brief OPAMP Extended HAL module driver
00037   * @{
00038   */
00039
00040
00041 /* Private typedef -----------------------------------------------------------*/
00042 /* Private define ------------------------------------------------------------*/
00043 /* Private macro -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Exported functions --------------------------------------------------------*/
00047
00048 /** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00049   * @{
00050   */
00051
00052
00053 /** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00054   * @brief    Extended Self calibration functions
00055   *
00056 @verbatim
00057  ===============================================================================
00058               ##### Extended IO operation functions #####
00059  ===============================================================================
00060   [..]
00061       (+) OPAMP Self calibration.
00062
00063 @endverbatim
00064   * @{
00065   */
00066
00067 /**
00068   * @brief  Run the self calibration of up to 6 OPAMPs in parallel.
00069   * @note   Calibration is performed in the mode specified in OPAMP init
00070   *         structure (mode normal or high-speed).
00071   * @param  hopamp1 handle
00072   * @param  hopamp2 handle
00073   * @param  hopamp3 handle
00074   * @param  hopamp4 handle  (1)
00075   * @param  hopamp5 handle  (1)
00076   * @param  hopamp6 handle  (1)
00077   *         (1) Parameter not present on STM32GBK1CB/STM32G431xx/STM32G441xx/STM32G471xx devices.
00078   * @retval HAL status
00079   * @note   Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00080   * @note   Calibration runs about 25 ms.
00081   */
00082
00083 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
00084 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00085                                                OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6)
00086 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
00087 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00088                                                OPAMP_HandleTypeDef *hopamp3)
00089 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00090 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00091                                                OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6)
00092 #endif
00093 {
00094   uint32_t trimmingvaluen1;
00095   uint32_t trimmingvaluep1;
00096   uint32_t trimmingvaluen2;
00097   uint32_t trimmingvaluep2;
00098   uint32_t trimmingvaluen3;
00099   uint32_t trimmingvaluep3;
00100 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00101   uint32_t trimmingvaluen4;
00102   uint32_t trimmingvaluep4;
00103   uint32_t trimmingvaluen5;
00104   uint32_t trimmingvaluep5;
00105   uint32_t trimmingvaluen6;
00106   uint32_t trimmingvaluep6;
00107 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00108   uint32_t trimmingvaluen6;
00109   uint32_t trimmingvaluep6;
00110 #endif
00111
00112   uint32_t delta;
00113
00114   if ((hopamp1 == NULL) || (hopamp2 == NULL) || (hopamp3 == NULL)
00115 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00116       || (hopamp4 == NULL) || (hopamp5 == NULL) || (hopamp6 == NULL)
00117 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00118       || (hopamp6 == NULL)
00119 #endif
00120      )
00121   {
00122     return HAL_ERROR;
00123   }
00124   else if (hopamp1->State != HAL_OPAMP_STATE_READY)
00125   {
00126     return HAL_ERROR;
00127   }
00128   else if (hopamp2->State != HAL_OPAMP_STATE_READY)
00129   {
00130     return HAL_ERROR;
00131   }
00132   else if (hopamp3->State != HAL_OPAMP_STATE_READY)
00133   {
00134     return HAL_ERROR;
00135   }
00136 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00137   else if (hopamp4->State != HAL_OPAMP_STATE_READY)
00138   {
00139     return HAL_ERROR;
00140   }
00141   else if (hopamp5->State != HAL_OPAMP_STATE_READY)
00142   {
00143     return HAL_ERROR;
00144   }
00145   else if (hopamp6->State != HAL_OPAMP_STATE_READY)
00146   {
00147     return HAL_ERROR;
00148   }
00149 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00150   else if (hopamp6->State != HAL_OPAMP_STATE_READY)
00151   {
00152     return HAL_ERROR;
00153   }
00154 #endif
00155   else
00156   {
00157
00158     /* Check the parameter */
00159     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00160     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00161     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
00162 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00163     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
00164     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance));
00165     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance));
00166 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00167     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance));
00168 #endif
00169
00170     /* Set Calibration mode */
00171     /* Non-inverting input connected to calibration reference voltage. */
00172     SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00173     SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00174     SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
00175 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00176     SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
00177     SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP);
00178     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
00179 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00180     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
00181 #endif
00182
00183     /*  user trimming values are used for offset calibration */
00184     SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00185     SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00186     SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
00187 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00188     SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
00189     SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_USERTRIM);
00190     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM);
00191 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00192     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM);
00193 #endif
00194
00195     /* Enable calibration */
00196     SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00197     SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00198     SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON);
00199 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00200     SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON);
00201     SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON);
00202     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
00203 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00204     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
00205 #endif
00206
00207     /* 1st calibration - N */
00208     /* Select 90% VREF */
00209     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00210     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00211     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00212 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00213     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00214     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00215     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00216 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00217     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
00218 #endif
00219
00220     /* Enable the opamps */
00221     SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00222     SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00223     SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00224 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00225     SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00226     SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00227     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00228 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00229     SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00230 #endif
00231
00232     /* Init trimming counter */
00233     /* Medium value */
00234     trimmingvaluen1 = 16UL;
00235     trimmingvaluen2 = 16UL;
00236     trimmingvaluen3 = 16UL;
00237 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00238     trimmingvaluen4 = 16UL;
00239     trimmingvaluen5 = 16UL;
00240     trimmingvaluen6 = 16UL;
00241 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00242     trimmingvaluen6 = 16UL;
00243 #endif
00244     delta = 8UL;
00245
00246     while (delta != 0UL)
00247     {
00248       /* Set candidate trimming */
00249       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
00250       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
00251       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
00252 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00253       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
00254       MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
00255       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00256 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00257       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00258 #endif
00259
00260       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00261       /* Offset trim time: during calibration, minimum time needed between */
00262       /* two steps to have 1 mV accuracy */
00263       HAL_Delay(2);
00264
00265       if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00266       {
00267         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00268         trimmingvaluen1 += delta;
00269       }
00270       else
00271       {
00272         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00273         trimmingvaluen1 -= delta;
00274       }
00275
00276       if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00277       {
00278         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00279         trimmingvaluen2 += delta;
00280       }
00281       else
00282       {
00283         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00284         trimmingvaluen2 -= delta;
00285       }
00286
00287       if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00288       {
00289         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00290         trimmingvaluen3 += delta;
00291       }
00292       else
00293       {
00294         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00295         trimmingvaluen3 -= delta;
00296       }
00297
00298 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00299       if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00300       {
00301         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00302         trimmingvaluen4 += delta;
00303       }
00304       else
00305       {
00306         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00307         trimmingvaluen4 -= delta;
00308       }
00309
00310       if ((hopamp5->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00311       {
00312         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00313         trimmingvaluen5 += delta;
00314       }
00315       else
00316       {
00317         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00318         trimmingvaluen5 -= delta;
00319       }
00320
00321       if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00322       {
00323         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00324         trimmingvaluen6 += delta;
00325       }
00326       else
00327       {
00328         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00329         trimmingvaluen6 -= delta;
00330       }
00331
00332 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00333       if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00334       {
00335         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00336         trimmingvaluen6 += delta;
00337       }
00338       else
00339       {
00340         /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
00341         trimmingvaluen6 -= delta;
00342       }
00343 #endif
00344
00345       delta >>= 1;
00346     }
00347
00348     /* Still need to check if righ calibration is current value or un step below */
00349     /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
00350     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
00351     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
00352     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
00353 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00354     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
00355     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
00356     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00357 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00358     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00359 #endif
00360
00361     /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00362     /* Offset trim time: during calibration, minimum time needed between */
00363     /* two steps to have 1 mV accuracy */
00364     HAL_Delay(2);
00365
00366     if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00367     {
00368       /* OPAMP_CSR_OUTCAL is actually one value more */
00369       trimmingvaluen1++;
00370       /* Set right trimming */
00371       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
00372     }
00373
00374     if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00375     {
00376       /* OPAMP_CSR_OUTCAL is actually one value more */
00377       trimmingvaluen2++;
00378       /* Set right trimming */
00379       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
00380     }
00381
00382     if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00383     {
00384       /* OPAMP_CSR_OUTCAL is actually one value more */
00385       trimmingvaluen3++;
00386       /* Set right trimming */
00387       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
00388     }
00389
00390 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00391     if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00392     {
00393       /* OPAMP_CSR_OUTCAL is actually one value more */
00394       trimmingvaluen4++;
00395       /* Set right trimming */
00396       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
00397     }
00398
00399     if ((hopamp5->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00400     {
00401       /* OPAMP_CSR_OUTCAL is actually one value more */
00402       trimmingvaluen5++;
00403       /* Set right trimming */
00404       MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
00405     }
00406
00407     if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00408     {
00409       /* OPAMP_CSR_OUTCAL is actually one value more */
00410       trimmingvaluen6++;
00411       /* Set right trimming */
00412       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00413     }
00414
00415 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00416     if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00417     {
00418       /* OPAMP_CSR_OUTCAL is actually one value more */
00419       trimmingvaluen6++;
00420       /* Set right trimming */
00421       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00422     }
00423 #endif
00424
00425     /* 2nd calibration - P */
00426     /* Select 10% VREF */
00427     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00428     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00429     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00430 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00431     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00432     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00433     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00434 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00435     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
00436 #endif
00437
00438     /* Init trimming counter */
00439     /* Medium value */
00440     trimmingvaluep1 = 16UL;
00441     trimmingvaluep2 = 16UL;
00442     trimmingvaluep3 = 16UL;
00443 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00444     trimmingvaluep4 = 16UL;
00445     trimmingvaluep5 = 16UL;
00446     trimmingvaluep6 = 16UL;
00447 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00448     trimmingvaluep6 = 16UL;
00449 #endif
00450
00451     delta = 8UL;
00452
00453     while (delta != 0UL)
00454     {
00455       /* Set candidate trimming */
00456       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
00457       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
00458       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
00459 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00460       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
00461       MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
00462       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00463 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00464       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00465 #endif
00466
00467       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00468       /* Offset trim time: during calibration, minimum time needed between */
00469       /* two steps to have 1 mV accuracy */
00470       HAL_Delay(2);
00471
00472       if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00473       {
00474         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00475         trimmingvaluep1 += delta;
00476       }
00477       else
00478       {
00479         trimmingvaluep1 -= delta;
00480       }
00481
00482       if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00483       {
00484         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00485         trimmingvaluep2 += delta;
00486       }
00487       else
00488       {
00489         trimmingvaluep2 -= delta;
00490       }
00491
00492       if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00493       {
00494         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00495         trimmingvaluep3 += delta;
00496       }
00497       else
00498       {
00499         trimmingvaluep3 -= delta;
00500       }
00501
00502 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00503       if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00504       {
00505         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00506         trimmingvaluep4 += delta;
00507       }
00508       else
00509       {
00510         trimmingvaluep4 -= delta;
00511       }
00512
00513       if ((hopamp5->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00514       {
00515         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00516         trimmingvaluep5 += delta;
00517       }
00518       else
00519       {
00520         trimmingvaluep5 -= delta;
00521       }
00522
00523       if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00524       {
00525         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00526         trimmingvaluep6 += delta;
00527       }
00528       else
00529       {
00530         trimmingvaluep6 -= delta;
00531       }
00532
00533 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00534       if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00535       {
00536         /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
00537         trimmingvaluep6 += delta;
00538       }
00539       else
00540       {
00541         trimmingvaluep6 -= delta;
00542       }
00543 #endif
00544
00545       delta >>= 1;
00546     }
00547
00548     /* Still need to check if righ calibration is current value or un step below */
00549     /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
00550     /* Set candidate trimming */
00551     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
00552     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
00553     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
00554 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00555     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
00556     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
00557     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00558 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00559     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00560 #endif
00561
00562     /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
00563     /* Offset trim time: during calibration, minimum time needed between */
00564     /* two steps to have 1 mV accuracy */
00565     HAL_Delay(2);
00566
00567     if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00568     {
00569       /* Trimming value is actually one value more */
00570       trimmingvaluep1++;
00571       /* Set right trimming */
00572       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
00573     }
00574
00575     if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00576     {
00577       /* Trimming value is actually one value more */
00578       trimmingvaluep2++;
00579       /* Set right trimming */
00580       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
00581     }
00582
00583     if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00584     {
00585       /* Trimming value is actually one value more */
00586       trimmingvaluep3++;
00587       /* Set right trimming */
00588       MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
00589     }
00590
00591 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00592     if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00593     {
00594       /* Trimming value is actually one value more */
00595       trimmingvaluep4++;
00596       /* Set right trimming */
00597       MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
00598     }
00599
00600     if ((hopamp5->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00601     {
00602       /* Trimming value is actually one value more */
00603       trimmingvaluep5++;
00604       /* Set right trimming */
00605       MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
00606     }
00607
00608     if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00609     {
00610       /* Trimming value is actually one value more */
00611       trimmingvaluep6++;
00612       /* Set right trimming */
00613       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00614     }
00615
00616 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00617     if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
00618     {
00619       /* Trimming value is actually one value more */
00620       trimmingvaluep6++;
00621       /* Set right trimming */
00622       MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00623     }
00624 #endif
00625
00626     /* Disable calibration */
00627     CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00628     CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00629     CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON);
00630 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00631     CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON);
00632     CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON);
00633     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
00634 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00635     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
00636 #endif
00637
00638     /* Disable the OPAMPs */
00639     CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00640     CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00641     CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00642 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00643     CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00644     CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00645     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00646 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00647     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00648 #endif
00649
00650     /* Set normal operating mode back */
00651     CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
00652     CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
00653     CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
00654 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00655     CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
00656     CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP);
00657     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
00658 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00659     CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
00660 #endif
00661
00662     /* Self calibration is successful  */
00663     /* Store calibration(user timing) results in init structure. */
00664     /* Select user timing mode */
00665
00666     /* Write calibration result N */
00667     hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00668     hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00669     hopamp3->Init.TrimmingValueN = trimmingvaluen3;
00670 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00671     hopamp4->Init.TrimmingValueN = trimmingvaluen4;
00672     hopamp5->Init.TrimmingValueN = trimmingvaluen5;
00673     hopamp6->Init.TrimmingValueN = trimmingvaluen6;
00674 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00675     hopamp6->Init.TrimmingValueN = trimmingvaluen6;
00676 #endif
00677
00678     /* Write calibration result P */
00679     hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00680     hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00681     hopamp3->Init.TrimmingValueP = trimmingvaluep3;
00682 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00683     hopamp4->Init.TrimmingValueP = trimmingvaluep4;
00684     hopamp5->Init.TrimmingValueP = trimmingvaluep5;
00685     hopamp6->Init.TrimmingValueP = trimmingvaluep6;
00686 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00687     hopamp6->Init.TrimmingValueP = trimmingvaluep6;
00688 #endif
00689
00690     /* Select user timing mode */
00691     /* And updated with calibrated settings */
00692     hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00693     hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00694     hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
00695 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00696     hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
00697     hopamp5->Init.UserTrimming = OPAMP_TRIMMING_USER;
00698     hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER;
00699 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00700     hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER;
00701 #endif
00702
00703     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
00704     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
00705     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
00706 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00707     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
00708     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
00709     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00710 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00711     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
00712 #endif
00713
00714     MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
00715     MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
00716     MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
00717 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
00718     MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
00719     MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
00720     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00721 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00722     MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
00723 #endif
00724
00725   }
00726
00727   return HAL_OK;
00728 }
00729
00730 /**
00731   * @}
00732   */
00733
00734 /**
00735   * @}
00736   */
00737
00738 /**
00739   * @}
00740   */
00741
00742 #endif /* HAL_OPAMP_MODULE_ENABLED */
00743
00744 /**
00745   * @}
00746   */
00747
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_opamp_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_opamp_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_opamp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_OPAMP_EX_H
00021 #define STM32G4xx_HAL_OPAMP_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup OPAMPEx OPAMPEx
00035   * @{
00036   */
00037 /* Exported types ------------------------------------------------------------*/
00038 /* Exported constants --------------------------------------------------------*/
00039 /* Exported macro ------------------------------------------------------------*/
00040 /* Exported functions --------------------------------------------------------*/
00041 /** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
00042   * @{
00043   */
00044
00045 /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00046   * @{
00047   */
00048
00049 /* I/O operation functions  *****************************************************/
00050
00051 #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
00052 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00053                                                OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6);
00054 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
00055 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00056                                                OPAMP_HandleTypeDef *hopamp3);
00057 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00058 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
00059                                                OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6);
00060 #endif
00061
00062 /**
00063   * @}
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078
00079 #ifdef __cplusplus
00080 }
00081 #endif
00082
00083
00084 #endif /* STM32G4xx_HAL_OPAMP_EX_H */
00085
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_pcd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @brief   PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                     ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029       The PCD HAL driver can be used as follows:
00030
00031      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00032          PCD_HandleTypeDef  hpcd;
00033
00034      (#) Fill parameters of Init structure in HCD handle
00035
00036      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00037
00038      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00039          (##) Enable the PCD/USB Low Level interface clock using
00040               (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
00041
00042          (##) Initialize the related GPIO clocks
00043          (##) Configure PCD pin-out
00044          (##) Configure PCD NVIC interrupt
00045
00046      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00047          (##) hpcd.pData = pdev;
00048
00049      (#)Enable PCD transmission and reception:
00050          (##) HAL_PCD_Start();
00051
00052   @endverbatim
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32g4xx_hal.h"
00058
00059 /** @addtogroup STM32G4xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup PCD PCD
00064   * @brief PCD HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_PCD_MODULE_ENABLED
00069
00070 #if defined (USB)
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private constants ---------------------------------------------------------*/
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @defgroup PCD_Private_Macros PCD Private Macros
00077   * @{
00078   */
00079 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00080 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00081 /**
00082   * @}
00083   */
00084
00085 /* Private functions prototypes ----------------------------------------------*/
00086 /** @defgroup PCD_Private_Functions PCD Private Functions
00087   * @{
00088   */
00089
00090 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00091 #if (USE_USB_DOUBLE_BUFFER == 1U)
00092 static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
00093 static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
00094 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported functions --------------------------------------------------------*/
00101 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00102   * @{
00103   */
00104
00105 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00106   *  @brief    Initialization and Configuration functions
00107   *
00108 @verbatim
00109  ===============================================================================
00110             ##### Initialization and de-initialization functions #####
00111  ===============================================================================
00112     [..]  This section provides functions allowing to:
00113
00114 @endverbatim
00115   * @{
00116   */
00117
00118 /**
00119   * @brief  Initializes the PCD according to the specified
00120   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00121   * @param  hpcd PCD handle
00122   * @retval HAL status
00123   */
00124 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00125 {
00126   uint8_t i;
00127
00128   /* Check the PCD handle allocation */
00129   if (hpcd == NULL)
00130   {
00131     return HAL_ERROR;
00132   }
00133
00134   /* Check the parameters */
00135   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00136
00137   if (hpcd->State == HAL_PCD_STATE_RESET)
00138   {
00139     /* Allocate lock resource and initialize it */
00140     hpcd->Lock = HAL_UNLOCKED;
00141
00142 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00143     hpcd->SOFCallback = HAL_PCD_SOFCallback;
00144     hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00145     hpcd->ResetCallback = HAL_PCD_ResetCallback;
00146     hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00147     hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00148     hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00149     hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00150     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
00151     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
00152     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
00153     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
00154     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
00155     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
00156
00157     if (hpcd->MspInitCallback == NULL)
00158     {
00159       hpcd->MspInitCallback = HAL_PCD_MspInit;
00160     }
00161
00162     /* Init the low level hardware */
00163     hpcd->MspInitCallback(hpcd);
00164 #else
00165     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00166     HAL_PCD_MspInit(hpcd);
00167 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
00168   }
00169
00170   hpcd->State = HAL_PCD_STATE_BUSY;
00171
00172   /* Disable the Interrupts */
00173   __HAL_PCD_DISABLE(hpcd);
00174
00175   /* Init endpoints structures */
00176   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00177   {
00178     /* Init ep structure */
00179     hpcd->IN_ep[i].is_in = 1U;
00180     hpcd->IN_ep[i].num = i;
00181     /* Control until ep is activated */
00182     hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00183     hpcd->IN_ep[i].maxpacket = 0U;
00184     hpcd->IN_ep[i].xfer_buff = 0U;
00185     hpcd->IN_ep[i].xfer_len = 0U;
00186   }
00187
00188   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00189   {
00190     hpcd->OUT_ep[i].is_in = 0U;
00191     hpcd->OUT_ep[i].num = i;
00192     /* Control until ep is activated */
00193     hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00194     hpcd->OUT_ep[i].maxpacket = 0U;
00195     hpcd->OUT_ep[i].xfer_buff = 0U;
00196     hpcd->OUT_ep[i].xfer_len = 0U;
00197   }
00198
00199   /* Init Device */
00200   (void)USB_DevInit(hpcd->Instance, hpcd->Init);
00201
00202   hpcd->USB_Address = 0U;
00203   hpcd->State = HAL_PCD_STATE_READY;
00204
00205   /* Activate LPM */
00206   if (hpcd->Init.lpm_enable == 1U)
00207   {
00208     (void)HAL_PCDEx_ActivateLPM(hpcd);
00209   }
00210
00211   return HAL_OK;
00212 }
00213
00214 /**
00215   * @brief  DeInitializes the PCD peripheral.
00216   * @param  hpcd PCD handle
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00220 {
00221   /* Check the PCD handle allocation */
00222   if (hpcd == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   hpcd->State = HAL_PCD_STATE_BUSY;
00228
00229   /* Stop Device */
00230   if (USB_StopDevice(hpcd->Instance) != HAL_OK)
00231   {
00232     return HAL_ERROR;
00233   }
00234
00235 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00236   if (hpcd->MspDeInitCallback == NULL)
00237   {
00238     hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
00239   }
00240
00241   /* DeInit the low level hardware */
00242   hpcd->MspDeInitCallback(hpcd);
00243 #else
00244   /* DeInit the low level hardware: CLOCK, NVIC.*/
00245   HAL_PCD_MspDeInit(hpcd);
00246 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00247
00248   hpcd->State = HAL_PCD_STATE_RESET;
00249
00250   return HAL_OK;
00251 }
00252
00253 /**
00254   * @brief  Initializes the PCD MSP.
00255   * @param  hpcd PCD handle
00256   * @retval None
00257   */
00258 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00259 {
00260   /* Prevent unused argument(s) compilation warning */
00261   UNUSED(hpcd);
00262
00263   /* NOTE : This function should not be modified, when the callback is needed,
00264             the HAL_PCD_MspInit could be implemented in the user file
00265    */
00266 }
00267
00268 /**
00269   * @brief  DeInitializes PCD MSP.
00270   * @param  hpcd PCD handle
00271   * @retval None
00272   */
00273 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00274 {
00275   /* Prevent unused argument(s) compilation warning */
00276   UNUSED(hpcd);
00277
00278   /* NOTE : This function should not be modified, when the callback is needed,
00279             the HAL_PCD_MspDeInit could be implemented in the user file
00280    */
00281 }
00282
00283 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00284 /**
00285   * @brief  Register a User USB PCD Callback
00286   *         To be used instead of the weak predefined callback
00287   * @param  hpcd USB PCD handle
00288   * @param  CallbackID ID of the callback to be registered
00289   *         This parameter can be one of the following values:
00290   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00291   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00292   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00293   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00294   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00295   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00296   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
00297   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00298   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00299   * @param  pCallback pointer to the Callback function
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
00303                                            HAL_PCD_CallbackIDTypeDef CallbackID,
00304                                            pPCD_CallbackTypeDef pCallback)
00305 {
00306   HAL_StatusTypeDef status = HAL_OK;
00307
00308   if (pCallback == NULL)
00309   {
00310     /* Update the error code */
00311     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00312     return HAL_ERROR;
00313   }
00314   /* Process locked */
00315   __HAL_LOCK(hpcd);
00316
00317   if (hpcd->State == HAL_PCD_STATE_READY)
00318   {
00319     switch (CallbackID)
00320     {
00321       case HAL_PCD_SOF_CB_ID :
00322         hpcd->SOFCallback = pCallback;
00323         break;
00324
00325       case HAL_PCD_SETUPSTAGE_CB_ID :
00326         hpcd->SetupStageCallback = pCallback;
00327         break;
00328
00329       case HAL_PCD_RESET_CB_ID :
00330         hpcd->ResetCallback = pCallback;
00331         break;
00332
00333       case HAL_PCD_SUSPEND_CB_ID :
00334         hpcd->SuspendCallback = pCallback;
00335         break;
00336
00337       case HAL_PCD_RESUME_CB_ID :
00338         hpcd->ResumeCallback = pCallback;
00339         break;
00340
00341       case HAL_PCD_CONNECT_CB_ID :
00342         hpcd->ConnectCallback = pCallback;
00343         break;
00344
00345       case HAL_PCD_DISCONNECT_CB_ID :
00346         hpcd->DisconnectCallback = pCallback;
00347         break;
00348
00349       case HAL_PCD_MSPINIT_CB_ID :
00350         hpcd->MspInitCallback = pCallback;
00351         break;
00352
00353       case HAL_PCD_MSPDEINIT_CB_ID :
00354         hpcd->MspDeInitCallback = pCallback;
00355         break;
00356
00357       default :
00358         /* Update the error code */
00359         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00360         /* Return error status */
00361         status =  HAL_ERROR;
00362         break;
00363     }
00364   }
00365   else if (hpcd->State == HAL_PCD_STATE_RESET)
00366   {
00367     switch (CallbackID)
00368     {
00369       case HAL_PCD_MSPINIT_CB_ID :
00370         hpcd->MspInitCallback = pCallback;
00371         break;
00372
00373       case HAL_PCD_MSPDEINIT_CB_ID :
00374         hpcd->MspDeInitCallback = pCallback;
00375         break;
00376
00377       default :
00378         /* Update the error code */
00379         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00380         /* Return error status */
00381         status =  HAL_ERROR;
00382         break;
00383     }
00384   }
00385   else
00386   {
00387     /* Update the error code */
00388     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00389     /* Return error status */
00390     status =  HAL_ERROR;
00391   }
00392
00393   /* Release Lock */
00394   __HAL_UNLOCK(hpcd);
00395   return status;
00396 }
00397
00398 /**
00399   * @brief  Unregister an USB PCD Callback
00400   *         USB PCD callback is redirected to the weak predefined callback
00401   * @param  hpcd USB PCD handle
00402   * @param  CallbackID ID of the callback to be unregistered
00403   *         This parameter can be one of the following values:
00404   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00405   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00406   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00407   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00408   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00409   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00410   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
00411   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00412   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00413   * @retval HAL status
00414   */
00415 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
00416 {
00417   HAL_StatusTypeDef status = HAL_OK;
00418
00419   /* Process locked */
00420   __HAL_LOCK(hpcd);
00421
00422   /* Setup Legacy weak Callbacks  */
00423   if (hpcd->State == HAL_PCD_STATE_READY)
00424   {
00425     switch (CallbackID)
00426     {
00427       case HAL_PCD_SOF_CB_ID :
00428         hpcd->SOFCallback = HAL_PCD_SOFCallback;
00429         break;
00430
00431       case HAL_PCD_SETUPSTAGE_CB_ID :
00432         hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00433         break;
00434
00435       case HAL_PCD_RESET_CB_ID :
00436         hpcd->ResetCallback = HAL_PCD_ResetCallback;
00437         break;
00438
00439       case HAL_PCD_SUSPEND_CB_ID :
00440         hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00441         break;
00442
00443       case HAL_PCD_RESUME_CB_ID :
00444         hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00445         break;
00446
00447       case HAL_PCD_CONNECT_CB_ID :
00448         hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00449         break;
00450
00451       case HAL_PCD_DISCONNECT_CB_ID :
00452         hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00453         break;
00454
00455       case HAL_PCD_MSPINIT_CB_ID :
00456         hpcd->MspInitCallback = HAL_PCD_MspInit;
00457         break;
00458
00459       case HAL_PCD_MSPDEINIT_CB_ID :
00460         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00461         break;
00462
00463       default :
00464         /* Update the error code */
00465         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00466
00467         /* Return error status */
00468         status =  HAL_ERROR;
00469         break;
00470     }
00471   }
00472   else if (hpcd->State == HAL_PCD_STATE_RESET)
00473   {
00474     switch (CallbackID)
00475     {
00476       case HAL_PCD_MSPINIT_CB_ID :
00477         hpcd->MspInitCallback = HAL_PCD_MspInit;
00478         break;
00479
00480       case HAL_PCD_MSPDEINIT_CB_ID :
00481         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00482         break;
00483
00484       default :
00485         /* Update the error code */
00486         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00487
00488         /* Return error status */
00489         status =  HAL_ERROR;
00490         break;
00491     }
00492   }
00493   else
00494   {
00495     /* Update the error code */
00496     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00497
00498     /* Return error status */
00499     status =  HAL_ERROR;
00500   }
00501
00502   /* Release Lock */
00503   __HAL_UNLOCK(hpcd);
00504   return status;
00505 }
00506
00507 /**
00508   * @brief  Register USB PCD Data OUT Stage Callback
00509   *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
00510   * @param  hpcd PCD handle
00511   * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
00512   * @retval HAL status
00513   */
00514 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
00515                                                        pPCD_DataOutStageCallbackTypeDef pCallback)
00516 {
00517   HAL_StatusTypeDef status = HAL_OK;
00518
00519   if (pCallback == NULL)
00520   {
00521     /* Update the error code */
00522     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00523
00524     return HAL_ERROR;
00525   }
00526
00527   /* Process locked */
00528   __HAL_LOCK(hpcd);
00529
00530   if (hpcd->State == HAL_PCD_STATE_READY)
00531   {
00532     hpcd->DataOutStageCallback = pCallback;
00533   }
00534   else
00535   {
00536     /* Update the error code */
00537     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00538
00539     /* Return error status */
00540     status =  HAL_ERROR;
00541   }
00542
00543   /* Release Lock */
00544   __HAL_UNLOCK(hpcd);
00545
00546   return status;
00547 }
00548
00549 /**
00550   * @brief  Unregister the USB PCD Data OUT Stage Callback
00551   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
00552   * @param  hpcd PCD handle
00553   * @retval HAL status
00554   */
00555 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
00556 {
00557   HAL_StatusTypeDef status = HAL_OK;
00558
00559   /* Process locked */
00560   __HAL_LOCK(hpcd);
00561
00562   if (hpcd->State == HAL_PCD_STATE_READY)
00563   {
00564     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
00565   }
00566   else
00567   {
00568     /* Update the error code */
00569     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00570
00571     /* Return error status */
00572     status =  HAL_ERROR;
00573   }
00574
00575   /* Release Lock */
00576   __HAL_UNLOCK(hpcd);
00577
00578   return status;
00579 }
00580
00581 /**
00582   * @brief  Register USB PCD Data IN Stage Callback
00583   *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
00584   * @param  hpcd PCD handle
00585   * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
00586   * @retval HAL status
00587   */
00588 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
00589                                                       pPCD_DataInStageCallbackTypeDef pCallback)
00590 {
00591   HAL_StatusTypeDef status = HAL_OK;
00592
00593   if (pCallback == NULL)
00594   {
00595     /* Update the error code */
00596     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00597
00598     return HAL_ERROR;
00599   }
00600
00601   /* Process locked */
00602   __HAL_LOCK(hpcd);
00603
00604   if (hpcd->State == HAL_PCD_STATE_READY)
00605   {
00606     hpcd->DataInStageCallback = pCallback;
00607   }
00608   else
00609   {
00610     /* Update the error code */
00611     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00612
00613     /* Return error status */
00614     status =  HAL_ERROR;
00615   }
00616
00617   /* Release Lock */
00618   __HAL_UNLOCK(hpcd);
00619
00620   return status;
00621 }
00622
00623 /**
00624   * @brief  Unregister the USB PCD Data IN Stage Callback
00625   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
00626   * @param  hpcd PCD handle
00627   * @retval HAL status
00628   */
00629 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
00630 {
00631   HAL_StatusTypeDef status = HAL_OK;
00632
00633   /* Process locked */
00634   __HAL_LOCK(hpcd);
00635
00636   if (hpcd->State == HAL_PCD_STATE_READY)
00637   {
00638     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
00639   }
00640   else
00641   {
00642     /* Update the error code */
00643     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00644
00645     /* Return error status */
00646     status =  HAL_ERROR;
00647   }
00648
00649   /* Release Lock */
00650   __HAL_UNLOCK(hpcd);
00651
00652   return status;
00653 }
00654
00655 /**
00656   * @brief  Register USB PCD Iso OUT incomplete Callback
00657   *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00658   * @param  hpcd PCD handle
00659   * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
00660   * @retval HAL status
00661   */
00662 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
00663                                                        pPCD_IsoOutIncpltCallbackTypeDef pCallback)
00664 {
00665   HAL_StatusTypeDef status = HAL_OK;
00666
00667   if (pCallback == NULL)
00668   {
00669     /* Update the error code */
00670     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00671
00672     return HAL_ERROR;
00673   }
00674
00675   /* Process locked */
00676   __HAL_LOCK(hpcd);
00677
00678   if (hpcd->State == HAL_PCD_STATE_READY)
00679   {
00680     hpcd->ISOOUTIncompleteCallback = pCallback;
00681   }
00682   else
00683   {
00684     /* Update the error code */
00685     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00686
00687     /* Return error status */
00688     status =  HAL_ERROR;
00689   }
00690
00691   /* Release Lock */
00692   __HAL_UNLOCK(hpcd);
00693
00694   return status;
00695 }
00696
00697 /**
00698   * @brief  Unregister the USB PCD Iso OUT incomplete Callback
00699   *         USB PCD Iso OUT incomplete Callback is redirected
00700   *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00701   * @param  hpcd PCD handle
00702   * @retval HAL status
00703   */
00704 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
00705 {
00706   HAL_StatusTypeDef status = HAL_OK;
00707
00708   /* Process locked */
00709   __HAL_LOCK(hpcd);
00710
00711   if (hpcd->State == HAL_PCD_STATE_READY)
00712   {
00713     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
00714   }
00715   else
00716   {
00717     /* Update the error code */
00718     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00719
00720     /* Return error status */
00721     status =  HAL_ERROR;
00722   }
00723
00724   /* Release Lock */
00725   __HAL_UNLOCK(hpcd);
00726
00727   return status;
00728 }
00729
00730 /**
00731   * @brief  Register USB PCD Iso IN incomplete Callback
00732   *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00733   * @param  hpcd PCD handle
00734   * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
00735   * @retval HAL status
00736   */
00737 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
00738                                                       pPCD_IsoInIncpltCallbackTypeDef pCallback)
00739 {
00740   HAL_StatusTypeDef status = HAL_OK;
00741
00742   if (pCallback == NULL)
00743   {
00744     /* Update the error code */
00745     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00746
00747     return HAL_ERROR;
00748   }
00749
00750   /* Process locked */
00751   __HAL_LOCK(hpcd);
00752
00753   if (hpcd->State == HAL_PCD_STATE_READY)
00754   {
00755     hpcd->ISOINIncompleteCallback = pCallback;
00756   }
00757   else
00758   {
00759     /* Update the error code */
00760     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00761
00762     /* Return error status */
00763     status =  HAL_ERROR;
00764   }
00765
00766   /* Release Lock */
00767   __HAL_UNLOCK(hpcd);
00768
00769   return status;
00770 }
00771
00772 /**
00773   * @brief  Unregister the USB PCD Iso IN incomplete Callback
00774   *         USB PCD Iso IN incomplete Callback is redirected
00775   *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00776   * @param  hpcd PCD handle
00777   * @retval HAL status
00778   */
00779 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
00780 {
00781   HAL_StatusTypeDef status = HAL_OK;
00782
00783   /* Process locked */
00784   __HAL_LOCK(hpcd);
00785
00786   if (hpcd->State == HAL_PCD_STATE_READY)
00787   {
00788     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
00789   }
00790   else
00791   {
00792     /* Update the error code */
00793     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00794
00795     /* Return error status */
00796     status =  HAL_ERROR;
00797   }
00798
00799   /* Release Lock */
00800   __HAL_UNLOCK(hpcd);
00801
00802   return status;
00803 }
00804
00805 /**
00806   * @brief  Register USB PCD BCD Callback
00807   *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
00808   * @param  hpcd PCD handle
00809   * @param  pCallback pointer to the USB PCD BCD Callback function
00810   * @retval HAL status
00811   */
00812 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
00813 {
00814   HAL_StatusTypeDef status = HAL_OK;
00815
00816   if (pCallback == NULL)
00817   {
00818     /* Update the error code */
00819     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00820
00821     return HAL_ERROR;
00822   }
00823
00824   /* Process locked */
00825   __HAL_LOCK(hpcd);
00826
00827   if (hpcd->State == HAL_PCD_STATE_READY)
00828   {
00829     hpcd->BCDCallback = pCallback;
00830   }
00831   else
00832   {
00833     /* Update the error code */
00834     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00835
00836     /* Return error status */
00837     status =  HAL_ERROR;
00838   }
00839
00840   /* Release Lock */
00841   __HAL_UNLOCK(hpcd);
00842
00843   return status;
00844 }
00845
00846 /**
00847   * @brief  Unregister the USB PCD BCD Callback
00848   *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
00849   * @param  hpcd PCD handle
00850   * @retval HAL status
00851   */
00852 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
00853 {
00854   HAL_StatusTypeDef status = HAL_OK;
00855
00856   /* Process locked */
00857   __HAL_LOCK(hpcd);
00858
00859   if (hpcd->State == HAL_PCD_STATE_READY)
00860   {
00861     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
00862   }
00863   else
00864   {
00865     /* Update the error code */
00866     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00867
00868     /* Return error status */
00869     status =  HAL_ERROR;
00870   }
00871
00872   /* Release Lock */
00873   __HAL_UNLOCK(hpcd);
00874
00875   return status;
00876 }
00877
00878 /**
00879   * @brief  Register USB PCD LPM Callback
00880   *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
00881   * @param  hpcd PCD handle
00882   * @param  pCallback pointer to the USB PCD LPM Callback function
00883   * @retval HAL status
00884   */
00885 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
00886 {
00887   HAL_StatusTypeDef status = HAL_OK;
00888
00889   if (pCallback == NULL)
00890   {
00891     /* Update the error code */
00892     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00893
00894     return HAL_ERROR;
00895   }
00896
00897   /* Process locked */
00898   __HAL_LOCK(hpcd);
00899
00900   if (hpcd->State == HAL_PCD_STATE_READY)
00901   {
00902     hpcd->LPMCallback = pCallback;
00903   }
00904   else
00905   {
00906     /* Update the error code */
00907     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00908
00909     /* Return error status */
00910     status =  HAL_ERROR;
00911   }
00912
00913   /* Release Lock */
00914   __HAL_UNLOCK(hpcd);
00915
00916   return status;
00917 }
00918
00919 /**
00920   * @brief  Unregister the USB PCD LPM Callback
00921   *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
00922   * @param  hpcd PCD handle
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
00926 {
00927   HAL_StatusTypeDef status = HAL_OK;
00928
00929   /* Process locked */
00930   __HAL_LOCK(hpcd);
00931
00932   if (hpcd->State == HAL_PCD_STATE_READY)
00933   {
00934     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
00935   }
00936   else
00937   {
00938     /* Update the error code */
00939     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00940
00941     /* Return error status */
00942     status =  HAL_ERROR;
00943   }
00944
00945   /* Release Lock */
00946   __HAL_UNLOCK(hpcd);
00947
00948   return status;
00949 }
00950 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00951
00952 /**
00953   * @}
00954   */
00955
00956 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00957   *  @brief   Data transfers functions
00958   *
00959 @verbatim
00960  ===============================================================================
00961                       ##### IO operation functions #####
00962  ===============================================================================
00963     [..]
00964     This subsection provides a set of functions allowing to manage the PCD data
00965     transfers.
00966
00967 @endverbatim
00968   * @{
00969   */
00970
00971 /**
00972   * @brief  Start the USB device
00973   * @param  hpcd PCD handle
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00977 {
00978   __HAL_LOCK(hpcd);
00979   __HAL_PCD_ENABLE(hpcd);
00980   (void)USB_DevConnect(hpcd->Instance);
00981   __HAL_UNLOCK(hpcd);
00982
00983   return HAL_OK;
00984 }
00985
00986 /**
00987   * @brief  Stop the USB device.
00988   * @param  hpcd PCD handle
00989   * @retval HAL status
00990   */
00991 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00992 {
00993   __HAL_LOCK(hpcd);
00994   __HAL_PCD_DISABLE(hpcd);
00995   (void)USB_DevDisconnect(hpcd->Instance);
00996   __HAL_UNLOCK(hpcd);
00997
00998   return HAL_OK;
00999 }
01000
01001
01002 /**
01003   * @brief  This function handles PCD interrupt request.
01004   * @param  hpcd PCD handle
01005   * @retval HAL status
01006   */
01007 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
01008 {
01009   uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
01010
01011   if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
01012   {
01013     /* servicing of the endpoint correct transfer interrupt */
01014     /* clear of the CTR flag into the sub */
01015     (void)PCD_EP_ISR_Handler(hpcd);
01016
01017     return;
01018   }
01019
01020   if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
01021   {
01022     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
01023
01024 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01025     hpcd->ResetCallback(hpcd);
01026 #else
01027     HAL_PCD_ResetCallback(hpcd);
01028 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01029
01030     (void)HAL_PCD_SetAddress(hpcd, 0U);
01031
01032     return;
01033   }
01034
01035   if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
01036   {
01037     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
01038
01039     return;
01040   }
01041
01042   if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
01043   {
01044     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
01045
01046     return;
01047   }
01048
01049   if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
01050   {
01051     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
01052     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
01053
01054     if (hpcd->LPM_State == LPM_L1)
01055     {
01056       hpcd->LPM_State = LPM_L0;
01057 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01058       hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
01059 #else
01060       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
01061 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01062     }
01063
01064 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01065     hpcd->ResumeCallback(hpcd);
01066 #else
01067     HAL_PCD_ResumeCallback(hpcd);
01068 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01069
01070     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
01071
01072     return;
01073   }
01074
01075   if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
01076   {
01077     /* Force low-power mode in the macrocell */
01078     hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
01079
01080     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
01081     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
01082
01083     hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
01084
01085 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01086     hpcd->SuspendCallback(hpcd);
01087 #else
01088     HAL_PCD_SuspendCallback(hpcd);
01089 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01090
01091     return;
01092   }
01093
01094   /* Handle LPM Interrupt */
01095   if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
01096   {
01097     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
01098     if (hpcd->LPM_State == LPM_L0)
01099     {
01100       /* Force suspend and low-power mode before going to L1 state*/
01101       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
01102       hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
01103
01104       hpcd->LPM_State = LPM_L1;
01105       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
01106 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01107       hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
01108 #else
01109       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
01110 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01111     }
01112     else
01113     {
01114 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01115       hpcd->SuspendCallback(hpcd);
01116 #else
01117       HAL_PCD_SuspendCallback(hpcd);
01118 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01119     }
01120
01121     return;
01122   }
01123
01124   if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
01125   {
01126     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
01127
01128 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01129     hpcd->SOFCallback(hpcd);
01130 #else
01131     HAL_PCD_SOFCallback(hpcd);
01132 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01133
01134     return;
01135   }
01136
01137   if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
01138   {
01139     /* clear ESOF flag in ISTR */
01140     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
01141
01142     return;
01143   }
01144 }
01145
01146
01147 /**
01148   * @brief  Data OUT stage callback.
01149   * @param  hpcd PCD handle
01150   * @param  epnum endpoint number
01151   * @retval None
01152   */
01153 __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01154 {
01155   /* Prevent unused argument(s) compilation warning */
01156   UNUSED(hpcd);
01157   UNUSED(epnum);
01158
01159   /* NOTE : This function should not be modified, when the callback is needed,
01160             the HAL_PCD_DataOutStageCallback could be implemented in the user file
01161    */
01162 }
01163
01164 /**
01165   * @brief  Data IN stage callback
01166   * @param  hpcd PCD handle
01167   * @param  epnum endpoint number
01168   * @retval None
01169   */
01170 __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01171 {
01172   /* Prevent unused argument(s) compilation warning */
01173   UNUSED(hpcd);
01174   UNUSED(epnum);
01175
01176   /* NOTE : This function should not be modified, when the callback is needed,
01177             the HAL_PCD_DataInStageCallback could be implemented in the user file
01178    */
01179 }
01180 /**
01181   * @brief  Setup stage callback
01182   * @param  hpcd PCD handle
01183   * @retval None
01184   */
01185 __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
01186 {
01187   /* Prevent unused argument(s) compilation warning */
01188   UNUSED(hpcd);
01189
01190   /* NOTE : This function should not be modified, when the callback is needed,
01191             the HAL_PCD_SetupStageCallback could be implemented in the user file
01192    */
01193 }
01194
01195 /**
01196   * @brief  USB Start Of Frame callback.
01197   * @param  hpcd PCD handle
01198   * @retval None
01199   */
01200 __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
01201 {
01202   /* Prevent unused argument(s) compilation warning */
01203   UNUSED(hpcd);
01204
01205   /* NOTE : This function should not be modified, when the callback is needed,
01206             the HAL_PCD_SOFCallback could be implemented in the user file
01207    */
01208 }
01209
01210 /**
01211   * @brief  USB Reset callback.
01212   * @param  hpcd PCD handle
01213   * @retval None
01214   */
01215 __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
01216 {
01217   /* Prevent unused argument(s) compilation warning */
01218   UNUSED(hpcd);
01219
01220   /* NOTE : This function should not be modified, when the callback is needed,
01221             the HAL_PCD_ResetCallback could be implemented in the user file
01222    */
01223 }
01224
01225 /**
01226   * @brief  Suspend event callback.
01227   * @param  hpcd PCD handle
01228   * @retval None
01229   */
01230 __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
01231 {
01232   /* Prevent unused argument(s) compilation warning */
01233   UNUSED(hpcd);
01234
01235   /* NOTE : This function should not be modified, when the callback is needed,
01236             the HAL_PCD_SuspendCallback could be implemented in the user file
01237    */
01238 }
01239
01240 /**
01241   * @brief  Resume event callback.
01242   * @param  hpcd PCD handle
01243   * @retval None
01244   */
01245 __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
01246 {
01247   /* Prevent unused argument(s) compilation warning */
01248   UNUSED(hpcd);
01249
01250   /* NOTE : This function should not be modified, when the callback is needed,
01251             the HAL_PCD_ResumeCallback could be implemented in the user file
01252    */
01253 }
01254
01255 /**
01256   * @brief  Incomplete ISO OUT callback.
01257   * @param  hpcd PCD handle
01258   * @param  epnum endpoint number
01259   * @retval None
01260   */
01261 __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01262 {
01263   /* Prevent unused argument(s) compilation warning */
01264   UNUSED(hpcd);
01265   UNUSED(epnum);
01266
01267   /* NOTE : This function should not be modified, when the callback is needed,
01268             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
01269    */
01270 }
01271
01272 /**
01273   * @brief  Incomplete ISO IN callback.
01274   * @param  hpcd PCD handle
01275   * @param  epnum endpoint number
01276   * @retval None
01277   */
01278 __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01279 {
01280   /* Prevent unused argument(s) compilation warning */
01281   UNUSED(hpcd);
01282   UNUSED(epnum);
01283
01284   /* NOTE : This function should not be modified, when the callback is needed,
01285             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
01286    */
01287 }
01288
01289 /**
01290   * @brief  Connection event callback.
01291   * @param  hpcd PCD handle
01292   * @retval None
01293   */
01294 __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
01295 {
01296   /* Prevent unused argument(s) compilation warning */
01297   UNUSED(hpcd);
01298
01299   /* NOTE : This function should not be modified, when the callback is needed,
01300             the HAL_PCD_ConnectCallback could be implemented in the user file
01301    */
01302 }
01303
01304 /**
01305   * @brief  Disconnection event callback.
01306   * @param  hpcd PCD handle
01307   * @retval None
01308   */
01309 __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
01310 {
01311   /* Prevent unused argument(s) compilation warning */
01312   UNUSED(hpcd);
01313
01314   /* NOTE : This function should not be modified, when the callback is needed,
01315             the HAL_PCD_DisconnectCallback could be implemented in the user file
01316    */
01317 }
01318
01319 /**
01320   * @}
01321   */
01322
01323 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
01324   *  @brief   management functions
01325   *
01326 @verbatim
01327  ===============================================================================
01328                       ##### Peripheral Control functions #####
01329  ===============================================================================
01330     [..]
01331     This subsection provides a set of functions allowing to control the PCD data
01332     transfers.
01333
01334 @endverbatim
01335   * @{
01336   */
01337
01338 /**
01339   * @brief  Connect the USB device
01340   * @param  hpcd PCD handle
01341   * @retval HAL status
01342   */
01343 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
01344 {
01345   __HAL_LOCK(hpcd);
01346   (void)USB_DevConnect(hpcd->Instance);
01347   __HAL_UNLOCK(hpcd);
01348
01349   return HAL_OK;
01350 }
01351
01352 /**
01353   * @brief  Disconnect the USB device.
01354   * @param  hpcd PCD handle
01355   * @retval HAL status
01356   */
01357 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
01358 {
01359   __HAL_LOCK(hpcd);
01360   (void)USB_DevDisconnect(hpcd->Instance);
01361   __HAL_UNLOCK(hpcd);
01362
01363   return HAL_OK;
01364 }
01365
01366 /**
01367   * @brief  Set the USB Device address.
01368   * @param  hpcd PCD handle
01369   * @param  address new device address
01370   * @retval HAL status
01371   */
01372 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
01373 {
01374   __HAL_LOCK(hpcd);
01375   hpcd->USB_Address = address;
01376   (void)USB_SetDevAddress(hpcd->Instance, address);
01377   __HAL_UNLOCK(hpcd);
01378
01379   return HAL_OK;
01380 }
01381 /**
01382   * @brief  Open and configure an endpoint.
01383   * @param  hpcd PCD handle
01384   * @param  ep_addr endpoint address
01385   * @param  ep_mps endpoint max packet size
01386   * @param  ep_type endpoint type
01387   * @retval HAL status
01388   */
01389 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
01390                                   uint16_t ep_mps, uint8_t ep_type)
01391 {
01392   HAL_StatusTypeDef  ret = HAL_OK;
01393   PCD_EPTypeDef *ep;
01394
01395   if ((ep_addr & 0x80U) == 0x80U)
01396   {
01397     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01398     ep->is_in = 1U;
01399   }
01400   else
01401   {
01402     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01403     ep->is_in = 0U;
01404   }
01405
01406   ep->num = ep_addr & EP_ADDR_MSK;
01407   ep->maxpacket = ep_mps;
01408   ep->type = ep_type;
01409
01410   /* Set initial data PID. */
01411   if (ep_type == EP_TYPE_BULK)
01412   {
01413     ep->data_pid_start = 0U;
01414   }
01415
01416   __HAL_LOCK(hpcd);
01417   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
01418   __HAL_UNLOCK(hpcd);
01419
01420   return ret;
01421 }
01422
01423 /**
01424   * @brief  Deactivate an endpoint.
01425   * @param  hpcd PCD handle
01426   * @param  ep_addr endpoint address
01427   * @retval HAL status
01428   */
01429 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01430 {
01431   PCD_EPTypeDef *ep;
01432
01433   if ((ep_addr & 0x80U) == 0x80U)
01434   {
01435     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01436     ep->is_in = 1U;
01437   }
01438   else
01439   {
01440     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01441     ep->is_in = 0U;
01442   }
01443   ep->num = ep_addr & EP_ADDR_MSK;
01444
01445   __HAL_LOCK(hpcd);
01446   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
01447   __HAL_UNLOCK(hpcd);
01448   return HAL_OK;
01449 }
01450
01451
01452 /**
01453   * @brief  Receive an amount of data.
01454   * @param  hpcd PCD handle
01455   * @param  ep_addr endpoint address
01456   * @param  pBuf pointer to the reception buffer
01457   * @param  len amount of data to be received
01458   * @retval HAL status
01459   */
01460 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01461 {
01462   PCD_EPTypeDef *ep;
01463
01464   ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01465
01466   /*setup and start the Xfer */
01467   ep->xfer_buff = pBuf;
01468   ep->xfer_len = len;
01469   ep->xfer_count = 0U;
01470   ep->is_in = 0U;
01471   ep->num = ep_addr & EP_ADDR_MSK;
01472
01473   (void)USB_EPStartXfer(hpcd->Instance, ep);
01474
01475   return HAL_OK;
01476 }
01477
01478 /**
01479   * @brief  Get Received Data Size
01480   * @param  hpcd PCD handle
01481   * @param  ep_addr endpoint address
01482   * @retval Data Size
01483   */
01484 uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
01485 {
01486   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
01487 }
01488 /**
01489   * @brief  Send an amount of data
01490   * @param  hpcd PCD handle
01491   * @param  ep_addr endpoint address
01492   * @param  pBuf pointer to the transmission buffer
01493   * @param  len amount of data to be sent
01494   * @retval HAL status
01495   */
01496 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01497 {
01498   PCD_EPTypeDef *ep;
01499
01500   ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01501
01502   /*setup and start the Xfer */
01503   ep->xfer_buff = pBuf;
01504   ep->xfer_len = len;
01505   ep->xfer_fill_db = 1U;
01506   ep->xfer_len_db = len;
01507   ep->xfer_count = 0U;
01508   ep->is_in = 1U;
01509   ep->num = ep_addr & EP_ADDR_MSK;
01510
01511   (void)USB_EPStartXfer(hpcd->Instance, ep);
01512
01513   return HAL_OK;
01514 }
01515
01516 /**
01517   * @brief  Set a STALL condition over an endpoint
01518   * @param  hpcd PCD handle
01519   * @param  ep_addr endpoint address
01520   * @retval HAL status
01521   */
01522 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01523 {
01524   PCD_EPTypeDef *ep;
01525
01526   if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
01527   {
01528     return HAL_ERROR;
01529   }
01530
01531   if ((0x80U & ep_addr) == 0x80U)
01532   {
01533     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01534     ep->is_in = 1U;
01535   }
01536   else
01537   {
01538     ep = &hpcd->OUT_ep[ep_addr];
01539     ep->is_in = 0U;
01540   }
01541
01542   ep->is_stall = 1U;
01543   ep->num = ep_addr & EP_ADDR_MSK;
01544
01545   __HAL_LOCK(hpcd);
01546
01547   (void)USB_EPSetStall(hpcd->Instance, ep);
01548
01549   __HAL_UNLOCK(hpcd);
01550
01551   return HAL_OK;
01552 }
01553
01554 /**
01555   * @brief  Clear a STALL condition over in an endpoint
01556   * @param  hpcd PCD handle
01557   * @param  ep_addr endpoint address
01558   * @retval HAL status
01559   */
01560 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01561 {
01562   PCD_EPTypeDef *ep;
01563
01564   if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
01565   {
01566     return HAL_ERROR;
01567   }
01568
01569   if ((0x80U & ep_addr) == 0x80U)
01570   {
01571     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01572     ep->is_in = 1U;
01573   }
01574   else
01575   {
01576     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01577     ep->is_in = 0U;
01578   }
01579
01580   ep->is_stall = 0U;
01581   ep->num = ep_addr & EP_ADDR_MSK;
01582
01583   __HAL_LOCK(hpcd);
01584   (void)USB_EPClearStall(hpcd->Instance, ep);
01585   __HAL_UNLOCK(hpcd);
01586
01587   return HAL_OK;
01588 }
01589
01590 /**
01591    * @brief  Abort an USB EP transaction.
01592    * @param  hpcd PCD handle
01593    * @param  ep_addr endpoint address
01594    * @retval HAL status
01595    */
01596 HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01597 {
01598   HAL_StatusTypeDef ret;
01599   PCD_EPTypeDef *ep;
01600
01601   if ((0x80U & ep_addr) == 0x80U)
01602   {
01603     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01604   }
01605   else
01606   {
01607     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01608   }
01609
01610   /* Stop Xfer */
01611   ret = USB_EPStopXfer(hpcd->Instance, ep);
01612
01613   return ret;
01614 }
01615
01616 /**
01617   * @brief  Flush an endpoint
01618   * @param  hpcd PCD handle
01619   * @param  ep_addr endpoint address
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01623 {
01624   __HAL_LOCK(hpcd);
01625
01626   if ((ep_addr & 0x80U) == 0x80U)
01627   {
01628     (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
01629   }
01630   else
01631   {
01632     (void)USB_FlushRxFifo(hpcd->Instance);
01633   }
01634
01635   __HAL_UNLOCK(hpcd);
01636
01637   return HAL_OK;
01638 }
01639
01640 /**
01641   * @brief  Activate remote wakeup signalling
01642   * @param  hpcd PCD handle
01643   * @retval HAL status
01644   */
01645 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01646 {
01647   return (USB_ActivateRemoteWakeup(hpcd->Instance));
01648 }
01649
01650 /**
01651   * @brief  De-activate remote wakeup signalling.
01652   * @param  hpcd PCD handle
01653   * @retval HAL status
01654   */
01655 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01656 {
01657   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
01658 }
01659
01660 /**
01661   * @}
01662   */
01663
01664 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01665   *  @brief   Peripheral State functions
01666   *
01667 @verbatim
01668  ===============================================================================
01669                       ##### Peripheral State functions #####
01670  ===============================================================================
01671     [..]
01672     This subsection permits to get in run-time the status of the peripheral
01673     and the data flow.
01674
01675 @endverbatim
01676   * @{
01677   */
01678
01679 /**
01680   * @brief  Return the PCD handle state.
01681   * @param  hpcd PCD handle
01682   * @retval HAL state
01683   */
01684 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
01685 {
01686   return hpcd->State;
01687 }
01688
01689 /**
01690   * @}
01691   */
01692
01693 /**
01694   * @}
01695   */
01696
01697 /* Private functions ---------------------------------------------------------*/
01698 /** @addtogroup PCD_Private_Functions
01699   * @{
01700   */
01701
01702
01703 /**
01704   * @brief  This function handles PCD Endpoint interrupt request.
01705   * @param  hpcd PCD handle
01706   * @retval HAL status
01707   */
01708 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
01709 {
01710   PCD_EPTypeDef *ep;
01711   uint16_t count;
01712   uint16_t wIstr;
01713   uint16_t wEPVal;
01714   uint16_t TxPctSize;
01715   uint8_t epindex;
01716
01717 #if (USE_USB_DOUBLE_BUFFER != 1U)
01718   count = 0U;
01719 #endif /* USE_USB_DOUBLE_BUFFER */
01720
01721   /* stay in loop while pending interrupts */
01722   while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
01723   {
01724     wIstr = hpcd->Instance->ISTR;
01725
01726     /* extract highest priority endpoint number */
01727     epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
01728
01729     if (epindex == 0U)
01730     {
01731       /* Decode and service control endpoint interrupt */
01732
01733       /* DIR bit = origin of the interrupt */
01734       if ((wIstr & USB_ISTR_DIR) == 0U)
01735       {
01736         /* DIR = 0 */
01737
01738         /* DIR = 0 => IN  int */
01739         /* DIR = 0 implies that (EP_CTR_TX = 1) always */
01740         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01741         ep = &hpcd->IN_ep[0];
01742
01743         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01744         ep->xfer_buff += ep->xfer_count;
01745
01746         /* TX COMPLETE */
01747 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01748         hpcd->DataInStageCallback(hpcd, 0U);
01749 #else
01750         HAL_PCD_DataInStageCallback(hpcd, 0U);
01751 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01752
01753         if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
01754         {
01755           hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
01756           hpcd->USB_Address = 0U;
01757         }
01758       }
01759       else
01760       {
01761         /* DIR = 1 */
01762
01763         /* DIR = 1 & CTR_RX => SETUP or OUT int */
01764         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
01765         ep = &hpcd->OUT_ep[0];
01766         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01767
01768         if ((wEPVal & USB_EP_SETUP) != 0U)
01769         {
01770           /* Get SETUP Packet */
01771           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01772
01773           USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
01774                       ep->pmaadress, (uint16_t)ep->xfer_count);
01775
01776           /* SETUP bit kept frozen while CTR_RX = 1 */
01777           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01778
01779           /* Process SETUP Packet*/
01780 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01781           hpcd->SetupStageCallback(hpcd);
01782 #else
01783           HAL_PCD_SetupStageCallback(hpcd);
01784 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01785         }
01786         else if ((wEPVal & USB_EP_CTR_RX) != 0U)
01787         {
01788           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01789
01790           /* Get Control Data OUT Packet */
01791           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01792
01793           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
01794           {
01795             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
01796                         ep->pmaadress, (uint16_t)ep->xfer_count);
01797
01798             ep->xfer_buff += ep->xfer_count;
01799
01800             /* Process Control Data OUT Packet */
01801 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01802             hpcd->DataOutStageCallback(hpcd, 0U);
01803 #else
01804             HAL_PCD_DataOutStageCallback(hpcd, 0U);
01805 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01806           }
01807
01808           wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01809
01810           if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
01811           {
01812             PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
01813             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
01814           }
01815         }
01816       }
01817     }
01818     else
01819     {
01820       /* Decode and service non control endpoints interrupt */
01821       /* process related endpoint register */
01822       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
01823
01824       if ((wEPVal & USB_EP_CTR_RX) != 0U)
01825       {
01826         /* clear int flag */
01827         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
01828         ep = &hpcd->OUT_ep[epindex];
01829
01830         /* OUT Single Buffering */
01831         if (ep->doublebuffer == 0U)
01832         {
01833           count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01834
01835           if (count != 0U)
01836           {
01837             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
01838           }
01839         }
01840 #if (USE_USB_DOUBLE_BUFFER == 1U)
01841         else
01842         {
01843           /* manage double buffer bulk out */
01844           if (ep->type == EP_TYPE_BULK)
01845           {
01846             count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
01847           }
01848           else /* manage double buffer iso out */
01849           {
01850             /* free EP OUT Buffer */
01851             PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
01852
01853             if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
01854             {
01855               /* read from endpoint BUF0Addr buffer */
01856               count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01857
01858               if (count != 0U)
01859               {
01860                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
01861               }
01862             }
01863             else
01864             {
01865               /* read from endpoint BUF1Addr buffer */
01866               count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01867
01868               if (count != 0U)
01869               {
01870                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
01871               }
01872             }
01873           }
01874         }
01875 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01876
01877         /* multi-packet on the NON control OUT endpoint */
01878         ep->xfer_count += count;
01879         ep->xfer_buff += count;
01880
01881         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
01882         {
01883           /* RX COMPLETE */
01884 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01885           hpcd->DataOutStageCallback(hpcd, ep->num);
01886 #else
01887           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
01888 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01889         }
01890         else
01891         {
01892           (void)USB_EPStartXfer(hpcd->Instance, ep);
01893         }
01894       }
01895
01896       if ((wEPVal & USB_EP_CTR_TX) != 0U)
01897       {
01898         ep = &hpcd->IN_ep[epindex];
01899
01900         /* clear int flag */
01901         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
01902
01903         if (ep->type == EP_TYPE_ISOC)
01904         {
01905           ep->xfer_len = 0U;
01906
01907 #if (USE_USB_DOUBLE_BUFFER == 1U)
01908           if (ep->doublebuffer != 0U)
01909           {
01910             if ((wEPVal & USB_EP_DTOG_TX) != 0U)
01911             {
01912               PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
01913             }
01914             else
01915             {
01916               PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
01917             }
01918           }
01919 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01920
01921           /* TX COMPLETE */
01922 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01923           hpcd->DataInStageCallback(hpcd, ep->num);
01924 #else
01925           HAL_PCD_DataInStageCallback(hpcd, ep->num);
01926 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01927         }
01928         else
01929         {
01930           /* Manage Single Buffer Transaction */
01931           if ((wEPVal & USB_EP_KIND) == 0U)
01932           {
01933             /* multi-packet on the NON control IN endpoint */
01934             TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01935
01936             if (ep->xfer_len > TxPctSize)
01937             {
01938               ep->xfer_len -= TxPctSize;
01939             }
01940             else
01941             {
01942               ep->xfer_len = 0U;
01943             }
01944
01945             /* Zero Length Packet? */
01946             if (ep->xfer_len == 0U)
01947             {
01948               /* TX COMPLETE */
01949 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01950               hpcd->DataInStageCallback(hpcd, ep->num);
01951 #else
01952               HAL_PCD_DataInStageCallback(hpcd, ep->num);
01953 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01954             }
01955             else
01956             {
01957               /* Transfer is not yet Done */
01958               ep->xfer_buff += TxPctSize;
01959               ep->xfer_count += TxPctSize;
01960               (void)USB_EPStartXfer(hpcd->Instance, ep);
01961             }
01962           }
01963 #if (USE_USB_DOUBLE_BUFFER == 1U)
01964           /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
01965           else
01966           {
01967             (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
01968           }
01969 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01970         }
01971       }
01972     }
01973   }
01974
01975   return HAL_OK;
01976 }
01977
01978
01979 #if (USE_USB_DOUBLE_BUFFER == 1U)
01980 /**
01981   * @brief  Manage double buffer bulk out transaction from ISR
01982   * @param  hpcd PCD handle
01983   * @param  ep current endpoint handle
01984   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
01985   * @retval HAL status
01986   */
01987 static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
01988                                       PCD_EPTypeDef *ep, uint16_t wEPVal)
01989 {
01990   uint16_t count;
01991
01992   /* Manage Buffer0 OUT */
01993   if ((wEPVal & USB_EP_DTOG_RX) != 0U)
01994   {
01995     /* Get count of received Data on buffer0 */
01996     count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01997
01998     if (ep->xfer_len >= count)
01999     {
02000       ep->xfer_len -= count;
02001     }
02002     else
02003     {
02004       ep->xfer_len = 0U;
02005     }
02006
02007     if (ep->xfer_len == 0U)
02008     {
02009       /* set NAK to OUT endpoint since double buffer is enabled */
02010       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
02011     }
02012
02013     /* Check if Buffer1 is in blocked state which requires to toggle */
02014     if ((wEPVal & USB_EP_DTOG_TX) != 0U)
02015     {
02016       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
02017     }
02018
02019     if (count != 0U)
02020     {
02021       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
02022     }
02023   }
02024   /* Manage Buffer 1 DTOG_RX=0 */
02025   else
02026   {
02027     /* Get count of received data */
02028     count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
02029
02030     if (ep->xfer_len >= count)
02031     {
02032       ep->xfer_len -= count;
02033     }
02034     else
02035     {
02036       ep->xfer_len = 0U;
02037     }
02038
02039     if (ep->xfer_len == 0U)
02040     {
02041       /* set NAK on the current endpoint */
02042       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
02043     }
02044
02045     /*Need to FreeUser Buffer*/
02046     if ((wEPVal & USB_EP_DTOG_TX) == 0U)
02047     {
02048       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
02049     }
02050
02051     if (count != 0U)
02052     {
02053       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
02054     }
02055   }
02056
02057   return count;
02058 }
02059
02060
02061 /**
02062   * @brief  Manage double buffer bulk IN transaction from ISR
02063   * @param  hpcd PCD handle
02064   * @param  ep current endpoint handle
02065   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
02066   * @retval HAL status
02067   */
02068 static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
02069                                                 PCD_EPTypeDef *ep, uint16_t wEPVal)
02070 {
02071   uint32_t len;
02072   uint16_t TxPctSize;
02073
02074   /* Data Buffer0 ACK received */
02075   if ((wEPVal & USB_EP_DTOG_TX) != 0U)
02076   {
02077     /* multi-packet on the NON control IN endpoint */
02078     TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
02079
02080     if (ep->xfer_len > TxPctSize)
02081     {
02082       ep->xfer_len -= TxPctSize;
02083     }
02084     else
02085     {
02086       ep->xfer_len = 0U;
02087     }
02088
02089     /* Transfer is completed */
02090     if (ep->xfer_len == 0U)
02091     {
02092       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02093       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02094
02095       /* TX COMPLETE */
02096 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02097       hpcd->DataInStageCallback(hpcd, ep->num);
02098 #else
02099       HAL_PCD_DataInStageCallback(hpcd, ep->num);
02100 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02101
02102       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
02103       {
02104         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02105       }
02106     }
02107     else /* Transfer is not yet Done */
02108     {
02109       /* need to Free USB Buff */
02110       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
02111       {
02112         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02113       }
02114
02115       /* Still there is data to Fill in the next Buffer */
02116       if (ep->xfer_fill_db == 1U)
02117       {
02118         ep->xfer_buff += TxPctSize;
02119         ep->xfer_count += TxPctSize;
02120
02121         /* Calculate the len of the new buffer to fill */
02122         if (ep->xfer_len_db >= ep->maxpacket)
02123         {
02124           len = ep->maxpacket;
02125           ep->xfer_len_db -= len;
02126         }
02127         else if (ep->xfer_len_db == 0U)
02128         {
02129           len = TxPctSize;
02130           ep->xfer_fill_db = 0U;
02131         }
02132         else
02133         {
02134           ep->xfer_fill_db = 0U;
02135           len = ep->xfer_len_db;
02136           ep->xfer_len_db = 0U;
02137         }
02138
02139         /* Write remaining Data to Buffer */
02140         /* Set the Double buffer counter for pma buffer1 */
02141         PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
02142
02143         /* Copy user buffer to USB PMA */
02144         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
02145       }
02146     }
02147   }
02148   else /* Data Buffer1 ACK received */
02149   {
02150     /* multi-packet on the NON control IN endpoint */
02151     TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
02152
02153     if (ep->xfer_len >= TxPctSize)
02154     {
02155       ep->xfer_len -= TxPctSize;
02156     }
02157     else
02158     {
02159       ep->xfer_len = 0U;
02160     }
02161
02162     /* Transfer is completed */
02163     if (ep->xfer_len == 0U)
02164     {
02165       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02166       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02167
02168       /* TX COMPLETE */
02169 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02170       hpcd->DataInStageCallback(hpcd, ep->num);
02171 #else
02172       HAL_PCD_DataInStageCallback(hpcd, ep->num);
02173 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02174
02175       /* need to Free USB Buff */
02176       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
02177       {
02178         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02179       }
02180     }
02181     else /* Transfer is not yet Done */
02182     {
02183       /* need to Free USB Buff */
02184       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
02185       {
02186         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02187       }
02188
02189       /* Still there is data to Fill in the next Buffer */
02190       if (ep->xfer_fill_db == 1U)
02191       {
02192         ep->xfer_buff += TxPctSize;
02193         ep->xfer_count += TxPctSize;
02194
02195         /* Calculate the len of the new buffer to fill */
02196         if (ep->xfer_len_db >= ep->maxpacket)
02197         {
02198           len = ep->maxpacket;
02199           ep->xfer_len_db -= len;
02200         }
02201         else if (ep->xfer_len_db == 0U)
02202         {
02203           len = TxPctSize;
02204           ep->xfer_fill_db = 0U;
02205         }
02206         else
02207         {
02208           len = ep->xfer_len_db;
02209           ep->xfer_len_db = 0U;
02210           ep->xfer_fill_db = 0;
02211         }
02212
02213         /* Set the Double buffer counter for pmabuffer1 */
02214         PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
02215
02216         /* Copy the user buffer to USB PMA */
02217         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
02218       }
02219     }
02220   }
02221
02222   /*enable endpoint IN*/
02223   PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
02224
02225   return HAL_OK;
02226 }
02227 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02228
02229
02230
02231 /**
02232   * @}
02233   */
02234 #endif /* defined (USB) */
02235 #endif /* HAL_PCD_MODULE_ENABLED */
02236
02237 /**
02238   * @}
02239   */
02240
02241 /**
02242   * @}
02243   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_pcd.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_PCD_H
00021 #define STM32G4xx_HAL_PCD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_ll_usb.h"
00029
00030 #if defined (USB)
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup PCD
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup PCD_Exported_Types PCD Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  PCD State structure definition
00047   */
00048 typedef enum
00049 {
00050   HAL_PCD_STATE_RESET   = 0x00,
00051   HAL_PCD_STATE_READY   = 0x01,
00052   HAL_PCD_STATE_ERROR   = 0x02,
00053   HAL_PCD_STATE_BUSY    = 0x03,
00054   HAL_PCD_STATE_TIMEOUT = 0x04
00055 } PCD_StateTypeDef;
00056
00057 /* Device LPM suspend state */
00058 typedef enum
00059 {
00060   LPM_L0 = 0x00, /* on */
00061   LPM_L1 = 0x01, /* LPM L1 sleep */
00062   LPM_L2 = 0x02, /* suspend */
00063   LPM_L3 = 0x03, /* off */
00064 } PCD_LPM_StateTypeDef;
00065
00066 typedef enum
00067 {
00068   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00069   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00070 } PCD_LPM_MsgTypeDef;
00071
00072 typedef enum
00073 {
00074   PCD_BCD_ERROR                     = 0xFF,
00075   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00076   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00077   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00078   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00079   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00080
00081 } PCD_BCD_MsgTypeDef;
00082
00083
00084
00085
00086
00087 typedef USB_TypeDef        PCD_TypeDef;
00088 typedef USB_CfgTypeDef     PCD_InitTypeDef;
00089 typedef USB_EPTypeDef      PCD_EPTypeDef;
00090
00091
00092 /**
00093   * @brief  PCD Handle Structure definition
00094   */
00095 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00096 typedef struct __PCD_HandleTypeDef
00097 #else
00098 typedef struct
00099 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00100 {
00101   PCD_TypeDef             *Instance;   /*!< Register base address             */
00102   PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
00103   __IO uint8_t            USB_Address; /*!< USB Address                       */
00104   PCD_EPTypeDef           IN_ep[8];    /*!< IN endpoint parameters            */
00105   PCD_EPTypeDef           OUT_ep[8];   /*!< OUT endpoint parameters           */
00106   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
00107   __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
00108   __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
00109   uint32_t                Setup[12];   /*!< Setup packet buffer               */
00110   PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
00111   uint32_t                BESL;
00112
00113
00114   uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
00115                                        This parameter can be set to ENABLE or DISABLE        */
00116
00117   uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
00118                                        This parameter can be set to ENABLE or DISABLE        */
00119   void                    *pData;      /*!< Pointer to upper stack Handler */
00120
00121 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00122   void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
00123   void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
00124   void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
00125   void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
00126   void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
00127   void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
00128   void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
00129
00130   void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
00131   void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
00132   void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
00133   void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
00134   void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
00135   void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
00136
00137   void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
00138   void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
00139 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00140 } PCD_HandleTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145
00146 /* Include PCD HAL Extended module */
00147 #include "stm32g4xx_hal_pcd_ex.h"
00148
00149 /* Exported constants --------------------------------------------------------*/
00150 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00151   * @{
00152   */
00153
00154 /** @defgroup PCD_Speed PCD Speed
00155   * @{
00156   */
00157 #define PCD_SPEED_FULL               USBD_FS_SPEED
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup PCD_PHY_Module PCD PHY Module
00163   * @{
00164   */
00165 #define PCD_PHY_ULPI                 1U
00166 #define PCD_PHY_EMBEDDED             2U
00167 #define PCD_PHY_UTMI                 3U
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup PCD_Error_Code_definition PCD Error Code definition
00173   * @brief  PCD Error Code definition
00174   * @{
00175   */
00176 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00177 #define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00178 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macros -----------------------------------------------------------*/
00189 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00190   *  @brief macros to handle interrupts and specific clock configurations
00191   * @{
00192   */
00193 #define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00194 #define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00195
00196 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
00197   ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00198
00199
00200 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)           (((__HANDLE__)->Instance->ISTR)\
00201                                                                    &= (uint16_t)(~(__INTERRUPT__)))
00202
00203 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                         EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
00204 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                        EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
00205
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported functions --------------------------------------------------------*/
00212 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00213   * @{
00214   */
00215
00216 /* Initialization/de-initialization functions  ********************************/
00217 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00218   * @{
00219   */
00220 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00221 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
00222 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00223 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00224
00225 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00226 /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
00227   * @brief  HAL USB OTG PCD Callback ID enumeration definition
00228   * @{
00229   */
00230 typedef enum
00231 {
00232   HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
00233   HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
00234   HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
00235   HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
00236   HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
00237   HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
00238   HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
00239
00240   HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
00241   HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
00242
00243 } HAL_PCD_CallbackIDTypeDef;
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
00249   * @brief  HAL USB OTG PCD Callback pointer definition
00250   * @{
00251   */
00252
00253 typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
00254 typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
00255 typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
00256 typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
00257 typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
00258 typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
00259 typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
00260
00261 /**
00262   * @}
00263   */
00264
00265 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
00266                                            pPCD_CallbackTypeDef pCallback);
00267
00268 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
00269
00270 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
00271                                                        pPCD_DataOutStageCallbackTypeDef pCallback);
00272
00273 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
00274
00275 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
00276                                                       pPCD_DataInStageCallbackTypeDef pCallback);
00277
00278 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
00279
00280 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
00281                                                        pPCD_IsoOutIncpltCallbackTypeDef pCallback);
00282
00283 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
00284
00285 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
00286                                                       pPCD_IsoInIncpltCallbackTypeDef pCallback);
00287
00288 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
00289
00290 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
00291 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
00292
00293 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
00294 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
00295 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00296 /**
00297   * @}
00298   */
00299
00300 /* I/O operation functions  ***************************************************/
00301 /* Non-Blocking mode: Interrupt */
00302 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00303   * @{
00304   */
00305 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00306 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00307 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00308
00309 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00310 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00311 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00312 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00313 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00314 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00315 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00316
00317 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00318 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00319 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00320 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00321 /**
00322   * @}
00323   */
00324
00325 /* Peripheral Control functions  **********************************************/
00326 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00327   * @{
00328   */
00329 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00330 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00331 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00332 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00333 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00334 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00335 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00336 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00337 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00338 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00339 HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00340 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00341 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00342 uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
00343 /**
00344   * @}
00345   */
00346
00347 /* Peripheral State functions  ************************************************/
00348 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00349   * @{
00350   */
00351 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /* Private constants ---------------------------------------------------------*/
00361 /** @defgroup PCD_Private_Constants PCD Private Constants
00362   * @{
00363   */
00364 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00365   * @{
00366   */
00367
00368
00369 #define USB_WAKEUP_EXTI_LINE                                          (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
00370
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00377   * @{
00378   */
00379 #define PCD_EP0MPS_64                                                 EP_MPS_64
00380 #define PCD_EP0MPS_32                                                 EP_MPS_32
00381 #define PCD_EP0MPS_16                                                 EP_MPS_16
00382 #define PCD_EP0MPS_08                                                 EP_MPS_8
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup PCD_ENDP PCD ENDP
00388   * @{
00389   */
00390 #define PCD_ENDP0                                                     0U
00391 #define PCD_ENDP1                                                     1U
00392 #define PCD_ENDP2                                                     2U
00393 #define PCD_ENDP3                                                     3U
00394 #define PCD_ENDP4                                                     4U
00395 #define PCD_ENDP5                                                     5U
00396 #define PCD_ENDP6                                                     6U
00397 #define PCD_ENDP7                                                     7U
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00403   * @{
00404   */
00405 #define PCD_SNG_BUF                                                   0U
00406 #define PCD_DBL_BUF                                                   1U
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /* Private macros ------------------------------------------------------------*/
00416 /** @defgroup PCD_Private_Macros PCD Private Macros
00417   * @{
00418   */
00419
00420 /********************  Bit definition for USB_COUNTn_RX register  *************/
00421 #define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
00422 #define USB_CNTRX_BLSIZE                      (0x1U << 15)
00423
00424 /* SetENDPOINT */
00425 #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
00426   (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
00427
00428 /* GetENDPOINT */
00429 #define PCD_GET_ENDPOINT(USBx, bEpNum)             (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
00430
00431
00432 /**
00433   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
00434   * @param  USBx USB peripheral instance register address.
00435   * @param  bEpNum Endpoint Number.
00436   * @param  wType Endpoint Type.
00437   * @retval None
00438   */
00439 #define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
00440   (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00441                     ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
00442
00443
00444 /**
00445   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
00446   * @param  USBx USB peripheral instance register address.
00447   * @param  bEpNum Endpoint Number.
00448   * @retval Endpoint Type
00449   */
00450 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
00451
00452 /**
00453   * @brief free buffer used from the application realizing it to the line
00454   *         toggles bit SW_BUF in the double buffered endpoint register
00455   * @param USBx USB device.
00456   * @param   bEpNum, bDir
00457   * @retval None
00458   */
00459 #define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
00460   do { \
00461     if ((bDir) == 0U) \
00462     { \
00463       /* OUT double buffered endpoint */ \
00464       PCD_TX_DTOG((USBx), (bEpNum)); \
00465     } \
00466     else if ((bDir) == 1U) \
00467     { \
00468       /* IN double buffered endpoint */ \
00469       PCD_RX_DTOG((USBx), (bEpNum)); \
00470     } \
00471   } while(0)
00472
00473 /**
00474   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00475   * @param  USBx USB peripheral instance register address.
00476   * @param  bEpNum Endpoint Number.
00477   * @param  wState new state
00478   * @retval None
00479   */
00480 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
00481   do { \
00482     uint16_t _wRegVal; \
00483     \
00484     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
00485     /* toggle first bit ? */ \
00486     if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
00487     { \
00488       _wRegVal ^= USB_EPTX_DTOG1; \
00489     } \
00490     /* toggle second bit ?  */ \
00491     if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
00492     { \
00493       _wRegVal ^= USB_EPTX_DTOG2; \
00494     } \
00495     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00496   } while(0) /* PCD_SET_EP_TX_STATUS */
00497
00498 /**
00499   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00500   * @param  USBx USB peripheral instance register address.
00501   * @param  bEpNum Endpoint Number.
00502   * @param  wState new state
00503   * @retval None
00504   */
00505 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
00506   do { \
00507     uint16_t _wRegVal; \
00508     \
00509     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
00510     /* toggle first bit ? */ \
00511     if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
00512     { \
00513       _wRegVal ^= USB_EPRX_DTOG1; \
00514     } \
00515     /* toggle second bit ? */ \
00516     if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
00517     { \
00518       _wRegVal ^= USB_EPRX_DTOG2; \
00519     } \
00520     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00521   } while(0) /* PCD_SET_EP_RX_STATUS */
00522
00523 /**
00524   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
00525   * @param  USBx USB peripheral instance register address.
00526   * @param  bEpNum Endpoint Number.
00527   * @param  wStaterx new state.
00528   * @param  wStatetx new state.
00529   * @retval None
00530   */
00531 #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
00532   do { \
00533     uint16_t _wRegVal; \
00534     \
00535     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
00536     /* toggle first bit ? */ \
00537     if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
00538     { \
00539       _wRegVal ^= USB_EPRX_DTOG1; \
00540     } \
00541     /* toggle second bit ? */ \
00542     if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
00543     { \
00544       _wRegVal ^= USB_EPRX_DTOG2; \
00545     } \
00546     /* toggle first bit ? */ \
00547     if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
00548     { \
00549       _wRegVal ^= USB_EPTX_DTOG1; \
00550     } \
00551     /* toggle second bit ?  */ \
00552     if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
00553     { \
00554       _wRegVal ^= USB_EPTX_DTOG2; \
00555     } \
00556     \
00557     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00558   } while(0) /* PCD_SET_EP_TXRX_STATUS */
00559
00560 /**
00561   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00562   *         /STAT_RX[1:0])
00563   * @param  USBx USB peripheral instance register address.
00564   * @param  bEpNum Endpoint Number.
00565   * @retval status
00566   */
00567 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
00568 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
00569
00570 /**
00571   * @brief  sets directly the VALID tx/rx-status into the endpoint register
00572   * @param  USBx USB peripheral instance register address.
00573   * @param  bEpNum Endpoint Number.
00574   * @retval None
00575   */
00576 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
00577 #define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
00578
00579 /**
00580   * @brief  checks stall condition in an endpoint.
00581   * @param  USBx USB peripheral instance register address.
00582   * @param  bEpNum Endpoint Number.
00583   * @retval TRUE = endpoint in stall condition.
00584   */
00585 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
00586 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
00587
00588 /**
00589   * @brief  set & clear EP_KIND bit.
00590   * @param  USBx USB peripheral instance register address.
00591   * @param  bEpNum Endpoint Number.
00592   * @retval None
00593   */
00594 #define PCD_SET_EP_KIND(USBx, bEpNum) \
00595   do { \
00596     uint16_t _wRegVal; \
00597     \
00598     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00599     \
00600     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
00601   } while(0) /* PCD_SET_EP_KIND */
00602
00603 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
00604   do { \
00605     uint16_t _wRegVal; \
00606     \
00607     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
00608     \
00609     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00610   } while(0) /* PCD_CLEAR_EP_KIND */
00611
00612 /**
00613   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
00614   * @param  USBx USB peripheral instance register address.
00615   * @param  bEpNum Endpoint Number.
00616   * @retval None
00617   */
00618 #define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
00619 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00620
00621 /**
00622   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00623   * @param  USBx USB peripheral instance register address.
00624   * @param  bEpNum Endpoint Number.
00625   * @retval None
00626   */
00627 #define PCD_SET_BULK_EP_DBUF(USBx, bEpNum)     PCD_SET_EP_KIND((USBx), (bEpNum))
00628 #define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum)   PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00629
00630 /**
00631   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00632   * @param  USBx USB peripheral instance register address.
00633   * @param  bEpNum Endpoint Number.
00634   * @retval None
00635   */
00636 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
00637   do { \
00638     uint16_t _wRegVal; \
00639     \
00640     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
00641     \
00642     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
00643   } while(0) /* PCD_CLEAR_RX_EP_CTR */
00644
00645 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
00646   do { \
00647     uint16_t _wRegVal; \
00648     \
00649     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
00650     \
00651     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
00652   } while(0) /* PCD_CLEAR_TX_EP_CTR */
00653
00654 /**
00655   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00656   * @param  USBx USB peripheral instance register address.
00657   * @param  bEpNum Endpoint Number.
00658   * @retval None
00659   */
00660 #define PCD_RX_DTOG(USBx, bEpNum) \
00661   do { \
00662     uint16_t _wEPVal; \
00663     \
00664     _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00665     \
00666     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
00667   } while(0) /* PCD_RX_DTOG */
00668
00669 #define PCD_TX_DTOG(USBx, bEpNum) \
00670   do { \
00671     uint16_t _wEPVal; \
00672     \
00673     _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00674     \
00675     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
00676   } while(0) /* PCD_TX_DTOG */
00677 /**
00678   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00679   * @param  USBx USB peripheral instance register address.
00680   * @param  bEpNum Endpoint Number.
00681   * @retval None
00682   */
00683 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
00684   do { \
00685     uint16_t _wRegVal; \
00686     \
00687     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
00688     \
00689     if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
00690     { \
00691       PCD_RX_DTOG((USBx), (bEpNum)); \
00692     } \
00693   } while(0) /* PCD_CLEAR_RX_DTOG */
00694
00695 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
00696   do { \
00697     uint16_t _wRegVal; \
00698     \
00699     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
00700     \
00701     if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
00702     { \
00703       PCD_TX_DTOG((USBx), (bEpNum)); \
00704     } \
00705   } while(0) /* PCD_CLEAR_TX_DTOG */
00706
00707 /**
00708   * @brief  Sets address in an endpoint register.
00709   * @param  USBx USB peripheral instance register address.
00710   * @param  bEpNum Endpoint Number.
00711   * @param  bAddr Address.
00712   * @retval None
00713   */
00714 #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
00715   do { \
00716     uint16_t _wRegVal; \
00717     \
00718     _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
00719     \
00720     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00721   } while(0) /* PCD_SET_EP_ADDRESS */
00722
00723 /**
00724   * @brief  Gets address in an endpoint register.
00725   * @param  USBx USB peripheral instance register address.
00726   * @param  bEpNum Endpoint Number.
00727   * @retval None
00728   */
00729 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
00730
00731 #define PCD_EP_TX_CNT(USBx, bEpNum) \
00732   ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
00733                   ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
00734
00735 #define PCD_EP_RX_CNT(USBx, bEpNum) \
00736   ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
00737                   ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
00738
00739
00740 /**
00741   * @brief  sets address of the tx/rx buffer.
00742   * @param  USBx USB peripheral instance register address.
00743   * @param  bEpNum Endpoint Number.
00744   * @param  wAddr address to be set (must be word aligned).
00745   * @retval None
00746   */
00747 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
00748   do { \
00749     __IO uint16_t *_wRegVal; \
00750     uint32_t _wRegBase = (uint32_t)USBx; \
00751     \
00752     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00753     _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
00754     *_wRegVal = ((wAddr) >> 1) << 1; \
00755   } while(0) /* PCD_SET_EP_TX_ADDRESS */
00756
00757 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
00758   do { \
00759     __IO uint16_t *_wRegVal; \
00760     uint32_t _wRegBase = (uint32_t)USBx; \
00761     \
00762     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00763     _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
00764     *_wRegVal = ((wAddr) >> 1) << 1; \
00765   } while(0) /* PCD_SET_EP_RX_ADDRESS */
00766
00767 /**
00768   * @brief  Gets address of the tx/rx buffer.
00769   * @param  USBx USB peripheral instance register address.
00770   * @param  bEpNum Endpoint Number.
00771   * @retval address of the buffer.
00772   */
00773 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
00774 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
00775
00776 /**
00777   * @brief  Sets counter of rx buffer with no. of blocks.
00778   * @param  pdwReg Register pointer
00779   * @param  wCount Counter.
00780   * @param  wNBlocks no. of Blocks.
00781   * @retval None
00782   */
00783 #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
00784   do { \
00785     (wNBlocks) = (wCount) >> 5; \
00786     if (((wCount) & 0x1fU) == 0U) \
00787     { \
00788       (wNBlocks)--; \
00789     } \
00790     *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
00791   } while(0) /* PCD_CALC_BLK32 */
00792
00793 #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
00794   do { \
00795     (wNBlocks) = (wCount) >> 1; \
00796     if (((wCount) & 0x1U) != 0U) \
00797     { \
00798       (wNBlocks)++; \
00799     } \
00800     *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
00801   } while(0) /* PCD_CALC_BLK2 */
00802
00803 #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
00804   do { \
00805     uint32_t wNBlocks; \
00806     \
00807     *(pdwReg) &= 0x3FFU; \
00808     \
00809     if ((wCount) > 62U) \
00810     { \
00811       PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
00812     } \
00813     else \
00814     { \
00815       if ((wCount) == 0U) \
00816       { \
00817         *(pdwReg) |= USB_CNTRX_BLSIZE; \
00818       } \
00819       else \
00820       { \
00821         PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
00822       } \
00823     } \
00824   } while(0) /* PCD_SET_EP_CNT_RX_REG */
00825
00826 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
00827   do { \
00828     uint32_t _wRegBase = (uint32_t)(USBx); \
00829     __IO uint16_t *pdwReg; \
00830     \
00831     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00832     pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
00833     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
00834   } while(0)
00835
00836 /**
00837   * @brief  sets counter for the tx/rx buffer.
00838   * @param  USBx USB peripheral instance register address.
00839   * @param  bEpNum Endpoint Number.
00840   * @param  wCount Counter value.
00841   * @retval None
00842   */
00843 #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
00844   do { \
00845     uint32_t _wRegBase = (uint32_t)(USBx); \
00846     __IO uint16_t *_wRegVal; \
00847     \
00848     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00849     _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
00850     *_wRegVal = (uint16_t)(wCount); \
00851   } while(0)
00852
00853 #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
00854   do { \
00855     uint32_t _wRegBase = (uint32_t)(USBx); \
00856     __IO uint16_t *_wRegVal; \
00857     \
00858     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00859     _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
00860     PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
00861   } while(0)
00862
00863 /**
00864   * @brief  gets counter of the tx buffer.
00865   * @param  USBx USB peripheral instance register address.
00866   * @param  bEpNum Endpoint Number.
00867   * @retval Counter value
00868   */
00869 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
00870 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
00871
00872 /**
00873   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
00874   * @param  USBx USB peripheral instance register address.
00875   * @param  bEpNum Endpoint Number.
00876   * @param  wBuf0Addr buffer 0 address.
00877   * @retval Counter value
00878   */
00879 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
00880   do { \
00881     PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
00882   } while(0) /* PCD_SET_EP_DBUF0_ADDR */
00883
00884 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
00885   do { \
00886     PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
00887   } while(0) /* PCD_SET_EP_DBUF1_ADDR */
00888
00889 /**
00890   * @brief  Sets addresses in a double buffer endpoint.
00891   * @param  USBx USB peripheral instance register address.
00892   * @param  bEpNum Endpoint Number.
00893   * @param  wBuf0Addr: buffer 0 address.
00894   * @param  wBuf1Addr = buffer 1 address.
00895   * @retval None
00896   */
00897 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
00898   do { \
00899     PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
00900     PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
00901   } while(0) /* PCD_SET_EP_DBUF_ADDR */
00902
00903 /**
00904   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00905   * @param  USBx USB peripheral instance register address.
00906   * @param  bEpNum Endpoint Number.
00907   * @retval None
00908   */
00909 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
00910 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
00911
00912 /**
00913   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00914   * @param  USBx USB peripheral instance register address.
00915   * @param  bEpNum Endpoint Number.
00916   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
00917   *         EP_DBUF_IN  = IN
00918   * @param  wCount: Counter value
00919   * @retval None
00920   */
00921 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
00922   do { \
00923     if ((bDir) == 0U) \
00924       /* OUT endpoint */ \
00925     { \
00926       PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
00927     } \
00928     else \
00929     { \
00930       if ((bDir) == 1U) \
00931       { \
00932         /* IN endpoint */ \
00933         PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
00934       } \
00935     } \
00936   } while(0) /* SetEPDblBuf0Count*/
00937
00938 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
00939   do { \
00940     uint32_t _wBase = (uint32_t)(USBx); \
00941     __IO uint16_t *_wEPRegVal; \
00942     \
00943     if ((bDir) == 0U) \
00944     { \
00945       /* OUT endpoint */ \
00946       PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
00947     } \
00948     else \
00949     { \
00950       if ((bDir) == 1U) \
00951       { \
00952         /* IN endpoint */ \
00953         _wBase += (uint32_t)(USBx)->BTABLE; \
00954         _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
00955         *_wEPRegVal = (uint16_t)(wCount); \
00956       } \
00957     } \
00958   } while(0) /* SetEPDblBuf1Count */
00959
00960 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
00961   do { \
00962     PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00963     PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00964   } while(0) /* PCD_SET_EP_DBUF_CNT */
00965
00966 /**
00967   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
00968   * @param  USBx USB peripheral instance register address.
00969   * @param  bEpNum Endpoint Number.
00970   * @retval None
00971   */
00972 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
00973 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
00974
00975
00976
00977 /**
00978   * @}
00979   */
00980
00981 /**
00982   * @}
00983   */
00984
00985 /**
00986   * @}
00987   */
00988 #endif /* defined (USB) */
00989
00990 #ifdef __cplusplus
00991 }
00992 #endif
00993
00994 #endif /* STM32G4xx_HAL_PCD_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_pcd_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   PCD Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32g4xx_hal.h"
00025
00026 /** @addtogroup STM32G4xx_HAL_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup PCDEx PCDEx
00031   * @brief PCD Extended HAL module driver
00032   * @{
00033   */
00034
00035 #ifdef HAL_PCD_MODULE_ENABLED
00036
00037 #if defined (USB)
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043 /* Exported functions --------------------------------------------------------*/
00044
00045 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00046   * @{
00047   */
00048
00049 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00050   * @brief    PCDEx control functions
00051   *
00052 @verbatim
00053  ===============================================================================
00054                  ##### Extended features functions #####
00055  ===============================================================================
00056     [..]  This section provides functions allowing to:
00057       (+) Update FIFO configuration
00058
00059 @endverbatim
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  Configure PMA for EP
00065   * @param  hpcd  Device instance
00066   * @param  ep_addr endpoint address
00067   * @param  ep_kind endpoint Kind
00068   *                  USB_SNG_BUF: Single Buffer used
00069   *                  USB_DBL_BUF: Double Buffer used
00070   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
00071   *                   this parameter is 16-bit value providing the address
00072   *                   in PMA allocated to endpoint.
00073   *                   In case of double buffer endpoint this parameter
00074   *                   is a 32-bit value providing the endpoint buffer 0 address
00075   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00076   *                   in the MSB part of 32-bit value.
00077   * @retval HAL status
00078   */
00079
00080 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
00081                                        uint16_t ep_kind, uint32_t pmaadress)
00082 {
00083   PCD_EPTypeDef *ep;
00084
00085   /* initialize ep structure*/
00086   if ((0x80U & ep_addr) == 0x80U)
00087   {
00088     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
00089   }
00090   else
00091   {
00092     ep = &hpcd->OUT_ep[ep_addr];
00093   }
00094
00095   /* Here we check if the endpoint is single or double Buffer*/
00096   if (ep_kind == PCD_SNG_BUF)
00097   {
00098     /* Single Buffer */
00099     ep->doublebuffer = 0U;
00100     /* Configure the PMA */
00101     ep->pmaadress = (uint16_t)pmaadress;
00102   }
00103 #if (USE_USB_DOUBLE_BUFFER == 1U)
00104   else /* USB_DBL_BUF */
00105   {
00106     /* Double Buffer Endpoint */
00107     ep->doublebuffer = 1U;
00108     /* Configure the PMA */
00109     ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
00110     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
00111   }
00112 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
00113
00114   return HAL_OK;
00115 }
00116
00117 /**
00118   * @brief  Activate BatteryCharging feature.
00119   * @param  hpcd PCD handle
00120   * @retval HAL status
00121   */
00122 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00123 {
00124   USB_TypeDef *USBx = hpcd->Instance;
00125   hpcd->battery_charging_active = 1U;
00126
00127   /* Enable BCD feature */
00128   USBx->BCDR |= USB_BCDR_BCDEN;
00129
00130   /* Enable DCD : Data Contact Detect */
00131   USBx->BCDR &= ~(USB_BCDR_PDEN);
00132   USBx->BCDR &= ~(USB_BCDR_SDEN);
00133   USBx->BCDR |= USB_BCDR_DCDEN;
00134
00135   return HAL_OK;
00136 }
00137
00138 /**
00139   * @brief  Deactivate BatteryCharging feature.
00140   * @param  hpcd PCD handle
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00144 {
00145   USB_TypeDef *USBx = hpcd->Instance;
00146   hpcd->battery_charging_active = 0U;
00147
00148   /* Disable BCD feature */
00149   USBx->BCDR &= ~(USB_BCDR_BCDEN);
00150
00151   return HAL_OK;
00152 }
00153
00154 /**
00155   * @brief  Handle BatteryCharging Process.
00156   * @param  hpcd PCD handle
00157   * @retval HAL status
00158   */
00159 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00160 {
00161   USB_TypeDef *USBx = hpcd->Instance;
00162   uint32_t tickstart = HAL_GetTick();
00163
00164   /* Wait for Min DCD Timeout */
00165   HAL_Delay(300U);
00166
00167   /* Data Pin Contact ? Check Detect flag */
00168   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
00169   {
00170 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00171     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
00172 #else
00173     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00174 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00175   }
00176   /* Primary detection: checks if connected to Standard Downstream Port
00177   (without charging capability) */
00178   USBx->BCDR &= ~(USB_BCDR_DCDEN);
00179   HAL_Delay(50U);
00180   USBx->BCDR |= (USB_BCDR_PDEN);
00181   HAL_Delay(50U);
00182
00183   /* If Charger detect ? */
00184   if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
00185   {
00186     /* Start secondary detection to check connection to Charging Downstream
00187     Port or Dedicated Charging Port */
00188     USBx->BCDR &= ~(USB_BCDR_PDEN);
00189     HAL_Delay(50U);
00190     USBx->BCDR |= (USB_BCDR_SDEN);
00191     HAL_Delay(50U);
00192
00193     /* If CDP ? */
00194     if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
00195     {
00196       /* Dedicated Downstream Port DCP */
00197 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00198       hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00199 #else
00200       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00201 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00202     }
00203     else
00204     {
00205       /* Charging Downstream Port CDP */
00206 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00207       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00208 #else
00209       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00210 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00211     }
00212   }
00213   else /* NO */
00214   {
00215     /* Standard Downstream Port */
00216 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00217     hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00218 #else
00219     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00220 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00221   }
00222
00223   /* Battery Charging capability discovery finished Start Enumeration */
00224   (void)HAL_PCDEx_DeActivateBCD(hpcd);
00225
00226   /* Check for the Timeout, else start USB Device */
00227   if ((HAL_GetTick() - tickstart) > 1000U)
00228   {
00229 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00230     hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
00231 #else
00232     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00233 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00234   }
00235   else
00236   {
00237 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00238     hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00239 #else
00240     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00241 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00242   }
00243 }
00244
00245
00246 /**
00247   * @brief  Activate LPM feature.
00248   * @param  hpcd PCD handle
00249   * @retval HAL status
00250   */
00251 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00252 {
00253
00254   USB_TypeDef *USBx = hpcd->Instance;
00255   hpcd->lpm_active = 1U;
00256   hpcd->LPM_State = LPM_L0;
00257
00258   USBx->LPMCSR |= USB_LPMCSR_LMPEN;
00259   USBx->LPMCSR |= USB_LPMCSR_LPMACK;
00260
00261   return HAL_OK;
00262 }
00263
00264 /**
00265   * @brief  Deactivate LPM feature.
00266   * @param  hpcd PCD handle
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00270 {
00271   USB_TypeDef *USBx = hpcd->Instance;
00272
00273   hpcd->lpm_active = 0U;
00274
00275   USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
00276   USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
00277
00278   return HAL_OK;
00279 }
00280
00281
00282
00283 /**
00284   * @brief  Send LPM message to user layer callback.
00285   * @param  hpcd PCD handle
00286   * @param  msg LPM message
00287   * @retval HAL status
00288   */
00289 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00290 {
00291   /* Prevent unused argument(s) compilation warning */
00292   UNUSED(hpcd);
00293   UNUSED(msg);
00294
00295   /* NOTE : This function should not be modified, when the callback is needed,
00296             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00297    */
00298 }
00299
00300 /**
00301   * @brief  Send BatteryCharging message to user layer callback.
00302   * @param  hpcd PCD handle
00303   * @param  msg LPM message
00304   * @retval HAL status
00305   */
00306 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00307 {
00308   /* Prevent unused argument(s) compilation warning */
00309   UNUSED(hpcd);
00310   UNUSED(msg);
00311
00312   /* NOTE : This function should not be modified, when the callback is needed,
00313             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00314    */
00315 }
00316
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324 #endif /* defined (USB) */
00325 #endif /* HAL_PCD_MODULE_ENABLED */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pcd_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_pcd_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_PCD_EX_H
00021 #define STM32G4xx_HAL_PCD_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif /* __cplusplus */
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined (USB)
00031 /** @addtogroup STM32G4xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup PCDEx
00036   * @{
00037   */
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /* Exported macros -----------------------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00043   * @{
00044   */
00045 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00046   * @{
00047   */
00048
00049
00050
00051 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
00052                                        uint16_t ep_kind, uint32_t pmaadress);
00053
00054
00055 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00056 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00057
00058
00059 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00060 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00061 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00062
00063 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00064 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081 #endif /* defined (USB) */
00082
00083 #ifdef __cplusplus
00084 }
00085 #endif /* __cplusplus */
00086
00087
00088 #endif /* STM32G4xx_HAL_PCD_EX_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_pwr.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g4xx_hal.h"
00026
00027 /** @addtogroup STM32G4xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup PWR PWR
00032   * @brief PWR HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_PWR_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040
00041 /** @defgroup PWR_Private_Defines PWR Private Defines
00042   * @{
00043   */
00044
00045 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00046   * @{
00047   */
00048 #define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */
00049 #define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */
00050 #define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */
00051 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */
00052 /**
00053   * @}
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /* Private macro -------------------------------------------------------------*/
00061 /* Private variables ---------------------------------------------------------*/
00062 /* Private function prototypes -----------------------------------------------*/
00063 /* Exported functions --------------------------------------------------------*/
00064
00065 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00066   * @{
00067   */
00068
00069 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00070   *  @brief    Initialization and de-initialization functions
00071   *
00072 @verbatim
00073  ===============================================================================
00074               ##### Initialization and de-initialization functions #####
00075  ===============================================================================
00076     [..]
00077
00078 @endverbatim
00079   * @{
00080   */
00081
00082 /**
00083   * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
00084   * @retval None
00085   */
00086 void HAL_PWR_DeInit(void)
00087 {
00088   __HAL_RCC_PWR_FORCE_RESET();
00089   __HAL_RCC_PWR_RELEASE_RESET();
00090 }
00091
00092 /**
00093   * @brief Enable access to the backup domain
00094   *        (RTC registers, RTC backup data registers).
00095   * @note  After reset, the backup domain is protected against
00096   *        possible unwanted write accesses.
00097   * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
00098   *        In order to set or modify the RTC clock, the backup domain access must be
00099   *        disabled.
00100   * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
00101   *        back-up domain.
00102   * @retval None
00103   */
00104 void HAL_PWR_EnableBkUpAccess(void)
00105 {
00106   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00107 }
00108
00109 /**
00110   * @brief Disable access to the backup domain
00111   *        (RTC registers, RTC backup data registers).
00112   * @retval None
00113   */
00114 void HAL_PWR_DisableBkUpAccess(void)
00115 {
00116   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00117 }
00118
00119
00120
00121
00122 /**
00123   * @}
00124   */
00125
00126
00127
00128 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00129   *  @brief Low Power modes configuration functions
00130   *
00131 @verbatim
00132
00133  ===============================================================================
00134                  ##### Peripheral Control functions #####
00135  ===============================================================================
00136
00137      [..]
00138      *** PVD configuration ***
00139     =========================
00140     [..]
00141       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00142           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
00143
00144       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00145           than the PVD threshold. This event is internally connected to the EXTI
00146           line16 and can generate an interrupt if enabled. This is done through
00147           __HAL_PVD_EXTI_ENABLE_IT() macro.
00148       (+) The PVD is stopped in Standby mode.
00149
00150
00151     *** WakeUp pin configuration ***
00152     ================================
00153     [..]
00154       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
00155           The polarity of these pins can be set to configure event detection on high
00156           level (rising edge) or low level (falling edge).
00157
00158
00159
00160     *** Low Power modes configuration ***
00161     =====================================
00162     [..]
00163       The devices feature 8 low-power modes:
00164       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
00165       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
00166       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
00167       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
00168       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
00169       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
00170       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
00171       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
00172
00173
00174    *** Low-power run mode ***
00175    ==========================
00176     [..]
00177       (+) Entry: (from main run mode)
00178         (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
00179
00180       (+) Exit:
00181         (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
00182              then can the system clock frequency be increased above 2 MHz.
00183
00184
00185    *** Sleep mode / Low-power sleep mode ***
00186    =========================================
00187     [..]
00188       (+) Entry:
00189           The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
00190           in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
00191           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
00192           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
00193           In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
00194           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00195           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00196
00197       (+) WFI Exit:
00198         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00199              controller (NVIC) or any wake-up event.
00200
00201       (+) WFE Exit:
00202         (++) Any wake-up event such as an EXTI line configured in event mode.
00203
00204          [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
00205              the MCU is in Low-power Run mode.
00206
00207    *** Stop 0, Stop 1 modes ***
00208    ===============================
00209     [..]
00210       (+) Entry:
00211           The Stop 0, Stop 1 modes are entered through the following API's:
00212           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
00213       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
00214           (++) PWR_MAINREGULATOR_ON
00215           (++) PWR_LOWPOWERREGULATOR_ON
00216       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00217           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00218           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00219
00220       (+) WFI Exit:
00221           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
00222           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
00223                when programmed in wakeup mode.
00224       (+) WFE Exit:
00225           (++) Any EXTI Line (Internal or External) configured in Event mode.
00226
00227        [..]
00228           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
00229           depending on the LPR bit setting.
00230
00231    *** Standby mode ***
00232    ====================
00233      [..]
00234       The Standby mode offers two options:
00235       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
00236         SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
00237         and Standby circuitry.
00238       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
00239         SRAM and register contents are lost except for the RTC registers, RTC backup registers
00240         and Standby circuitry.
00241
00242       (++) Entry:
00243           (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
00244                 SRAM1 and register contents are lost except for registers in the Backup domain and
00245                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00246                 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00247                 to set RRS bit.
00248
00249       (++) Exit:
00250           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00251                 external reset in NRST pin, IWDG reset.
00252
00253       [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
00254
00255
00256     *** Shutdown mode ***
00257    ======================
00258      [..]
00259       In Shutdown mode,
00260         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
00261         SRAM and registers contents are lost except for backup domain registers.
00262
00263       (+) Entry:
00264           The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
00265
00266       (+) Exit:
00267           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00268                external reset in NRST pin.
00269
00270          [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
00271
00272
00273    *** Auto-wakeup (AWU) from low-power mode ***
00274    =============================================
00275     [..]
00276       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00277       Wakeup event, a tamper event or a time-stamp event, without depending on
00278       an external interrupt (Auto-wakeup mode).
00279
00280       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
00281
00282
00283         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00284              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00285
00286         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00287              is necessary to configure the RTC to detect the tamper or time stamp event using the
00288              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00289
00290         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00291               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00292
00293 @endverbatim
00294   * @{
00295   */
00296
00297
00298
00299 /**
00300   * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
00301   * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
00302   *        configuration information.
00303   * @note Refer to the electrical characteristics of your device datasheet for
00304   *         more details about the voltage thresholds corresponding to each
00305   *         detection level.
00306   * @retval None
00307   */
00308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00309 {
00310   /* Check the parameters */
00311   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00312   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00313
00314   /* Set PLS bits according to PVDLevel value */
00315   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
00316
00317   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00318   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00319   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00320   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00321   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00322
00323   /* Configure interrupt mode */
00324   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00325   {
00326     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00327   }
00328
00329   /* Configure event mode */
00330   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00331   {
00332     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00333   }
00334
00335   /* Configure the edge */
00336   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00337   {
00338     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00339   }
00340
00341   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00342   {
00343     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00344   }
00345
00346   return HAL_OK;
00347 }
00348
00349
00350 /**
00351   * @brief Enable the Power Voltage Detector (PVD).
00352   * @retval None
00353   */
00354 void HAL_PWR_EnablePVD(void)
00355 {
00356   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00357 }
00358
00359 /**
00360   * @brief Disable the Power Voltage Detector (PVD).
00361   * @retval None
00362   */
00363 void HAL_PWR_DisablePVD(void)
00364 {
00365   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00366 }
00367
00368
00369
00370
00371 /**
00372   * @brief Enable the WakeUp PINx functionality.
00373   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00374   *         This parameter can be one of the following legacy values which set the default polarity
00375   *         i.e. detection on high level (rising edge):
00376   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00377   *
00378   *         or one of the following value where the user can explicitly specify the enabled pin and
00379   *         the chosen polarity:
00380   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00381   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00382   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00383   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00384   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00385   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00386   * @retval None
00387   */
00388 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00389 {
00390   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00391
00392   /* Specifies the Wake-Up pin polarity for the event detection
00393     (rising or falling edge) */
00394   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00395
00396   /* Enable wake-up pin */
00397   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00398
00399
00400 }
00401
00402 /**
00403   * @brief Disable the WakeUp PINx functionality.
00404   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00405   *         This parameter can be one of the following values:
00406   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00407   * @retval None
00408   */
00409 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00410 {
00411   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00412
00413   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
00414 }
00415
00416
00417 /**
00418   * @brief Enter Sleep or Low-power Sleep mode.
00419   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
00420   * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
00421   *          This parameter can be one of the following values:
00422   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00423   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
00424   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
00425   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
00426   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00427   *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
00428   *        Additionally, the clock frequency must be reduced below 2 MHz.
00429   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
00430   *        be done before calling HAL_PWR_EnterSLEEPMode() API.
00431   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
00432   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
00433   * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
00434   *           This parameter can be one of the following values:
00435   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
00436   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
00437   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
00438   *        the interrupt wake up source.
00439   * @retval None
00440   */
00441 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00442 {
00443   /* Check the parameters */
00444   assert_param(IS_PWR_REGULATOR(Regulator));
00445   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00446
00447   /* Set Regulator parameter */
00448   if (Regulator == PWR_MAINREGULATOR_ON)
00449   {
00450     /* If in low-power run mode at this point, exit it */
00451     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00452     {
00453       (void)HAL_PWREx_DisableLowPowerRunMode();
00454     }
00455     /* Regulator now in main mode. */
00456   }
00457   else
00458   {
00459     /* If in run mode, first move to low-power run mode.
00460        The system clock frequency must be below 2 MHz at this point. */
00461     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
00462     {
00463       HAL_PWREx_EnableLowPowerRunMode();
00464     }
00465   }
00466
00467   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00468   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00469
00470   /* Select SLEEP mode entry -------------------------------------------------*/
00471   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00472   {
00473     /* Request Wait For Interrupt */
00474     __WFI();
00475   }
00476   else
00477   {
00478     /* Request Wait For Event */
00479     __SEV();
00480     __WFE();
00481     __WFE();
00482   }
00483
00484 }
00485
00486
00487 /**
00488   * @brief Enter Stop mode
00489   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
00490   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
00491   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00492   * @note  All clocks in the VCORE domain are stopped; the PLL,
00493   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00494   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00495   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00496   *        only to the peripheral requesting it.
00497   *        SRAM1, SRAM2 and register contents are preserved.
00498   *        The BOR is available.
00499   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
00500   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
00501   *         the HSI RC oscillator is selected as system clock.
00502   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
00503   *         startup delay is incurred when waking up.
00504   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
00505   *         is higher although the startup time is reduced.
00506   * @param Regulator: Specifies the regulator state in Stop mode.
00507   *          This parameter can be one of the following values:
00508   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00509   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
00510   * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
00511   *          This parameter can be one of the following values:
00512   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
00513   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
00514   * @retval None
00515   */
00516 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00517 {
00518   /* Check the parameters */
00519   assert_param(IS_PWR_REGULATOR(Regulator));
00520
00521   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
00522   {
00523     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
00524   }
00525   else
00526   {
00527     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
00528   }
00529 }
00530
00531 /**
00532   * @brief Enter Standby mode.
00533   * @note  In Standby mode, the PLL, the HSI and the HSE oscillators are switched
00534   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
00535   *        in which case the regulator is in low-power mode.
00536   *        SRAM1 and register contents are lost except for registers in the Backup domain and
00537   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00538   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00539   *        to set RRS bit.
00540   *        The BOR is available.
00541   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00542   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
00543   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
00544   *        same.
00545   *        These states are effective in Standby mode only if APC bit is set through
00546   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
00547   * @retval None
00548   */
00549 void HAL_PWR_EnterSTANDBYMode(void)
00550 {
00551   /* Set Stand-by mode */
00552   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
00553
00554   /* Set SLEEPDEEP bit of Cortex System Control Register */
00555   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00556
00557 /* This option is used to ensure that store operations are completed */
00558 #if defined ( __CC_ARM)
00559   __force_stores();
00560 #endif
00561   /* Request Wait For Interrupt */
00562   __WFI();
00563 }
00564
00565
00566
00567 /**
00568   * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
00569   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00570   *       re-enters SLEEP mode when an interruption handling is over.
00571   *       Setting this bit is useful when the processor is expected to run only on
00572   *       interruptions handling.
00573   * @retval None
00574   */
00575 void HAL_PWR_EnableSleepOnExit(void)
00576 {
00577   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00578   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00579 }
00580
00581
00582 /**
00583   * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00584   * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00585   *       re-enters SLEEP mode when an interruption handling is over.
00586   * @retval None
00587   */
00588 void HAL_PWR_DisableSleepOnExit(void)
00589 {
00590   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00591   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00592 }
00593
00594
00595
00596 /**
00597   * @brief Enable CORTEX M4 SEVONPEND bit.
00598   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
00599   *       WFE to wake up when an interrupt moves from inactive to pended.
00600   * @retval None
00601   */
00602 void HAL_PWR_EnableSEVOnPend(void)
00603 {
00604   /* Set SEVONPEND bit of Cortex System Control Register */
00605   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00606 }
00607
00608
00609 /**
00610   * @brief Disable CORTEX M4 SEVONPEND bit.
00611   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
00612   *       WFE to wake up when an interrupt moves from inactive to pended.
00613   * @retval None
00614   */
00615 void HAL_PWR_DisableSEVOnPend(void)
00616 {
00617   /* Clear SEVONPEND bit of Cortex System Control Register */
00618   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00619 }
00620
00621
00622
00623
00624
00625 /**
00626   * @brief PWR PVD interrupt callback
00627   * @retval None
00628   */
00629 __weak void HAL_PWR_PVDCallback(void)
00630 {
00631   /* NOTE : This function should not be modified; when the callback is needed,
00632             the HAL_PWR_PVDCallback can be implemented in the user file
00633    */
00634 }
00635
00636 /**
00637   * @}
00638   */
00639
00640 /**
00641   * @}
00642   */
00643
00644 #endif /* HAL_PWR_MODULE_ENABLED */
00645 /**
00646   * @}
00647   */
00648
00649 /**
00650   * @}
00651   */
00652
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_PWR_H
00021 #define STM32G4xx_HAL_PWR_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup PWR
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039
00040 /** @defgroup PWR_Exported_Types PWR Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  PWR PVD configuration structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00050                             This parameter can be a value of @ref PWR_PVD_detection_level. */
00051
00052   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00053                            This parameter can be a value of @ref PWR_PVD_Mode. */
00054 }PWR_PVDTypeDef;
00055
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Exported constants --------------------------------------------------------*/
00062
00063 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00064   * @{
00065   */
00066
00067
00068 /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
00069   * @{
00070   */
00071 #define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
00072 #define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
00073 #define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
00074 #define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
00075 #define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
00076 #define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
00077 #define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
00078 #define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
00084   * @{
00085   */
00086 #define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
00087 #define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00088 #define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00089 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00090 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00091 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00092 #define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00093 /**
00094   * @}
00095   */
00096
00097
00098
00099
00100 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
00101   * @{
00102   */
00103 #define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
00104 #define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
00110   * @{
00111   */
00112 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
00113 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
00119   * @{
00120   */
00121 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
00122 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
00123 /**
00124   * @}
00125   */
00126
00127
00128 /** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
00129   * @{
00130   */
00131 #define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
00137   * @{
00138   */
00139 #define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported macros -----------------------------------------------------------*/
00149 /** @defgroup PWR_Exported_Macros  PWR Exported Macros
00150   * @{
00151   */
00152
00153 /** @brief  Check whether or not a specific PWR flag is set.
00154   * @param  __FLAG__: specifies the flag to check.
00155   *           This parameter can be one of the following values:
00156   *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
00157   *                  was received from the WKUP pin 1.
00158   *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
00159   *                  was received from the WKUP pin 2.
00160   *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
00161   *                  was received from the WKUP pin 3.
00162   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
00163   *                  was received from the WKUP pin 4.
00164   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
00165   *                  was received from the WKUP pin 5.
00166   *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
00167   *                  entered StandBy mode.
00168   *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
00169   *                 the internal wakeup line.
00170   *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
00171   *                 low-power regulator is ready.
00172   *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
00173   *                 regulator is ready in main mode or is in low-power mode.
00174   *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
00175   *                 in the selected voltage range or is still changing to the required voltage level.
00176   *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
00177   *                  below or above the selected PVD threshold.
00178 @if PWR_CR2_PVME1
00179   *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
00180   *                  is below or above PVM1 threshold (applicable when USB feature is supported).
00181 @endif
00182 @if PWR_CR2_PVME2
00183   *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
00184   *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
00185 @endif
00186   *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
00187   *                  is below or above PVM3 threshold.
00188   *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
00189   *                  is below or above PVM4 threshold.
00190   *
00191   * @retval The new state of __FLAG__ (TRUE or FALSE).
00192   */
00193 #define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
00194                                       (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
00195                                       (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
00196
00197 /** @brief  Clear a specific PWR flag.
00198   * @param  __FLAG__: specifies the flag to clear.
00199   *          This parameter can be one of the following values:
00200   *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
00201   *                  was received from the WKUP pin 1.
00202   *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
00203   *                  was received from the WKUP pin 2.
00204   *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
00205   *                  was received from the WKUP pin 3.
00206   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
00207   *                  was received from the WKUP pin 4.
00208   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
00209   *                  was received from the WKUP pin 5.
00210   *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
00211   *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
00212   *                  entered Standby mode.
00213   * @retval None
00214   */
00215 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
00216                                          (PWR->SCR  = (__FLAG__)) :\
00217                                          (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
00218 /**
00219   * @brief Enable the PVD Extended Interrupt Line.
00220   * @retval None
00221   */
00222 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00223
00224 /**
00225   * @brief Disable the PVD Extended Interrupt Line.
00226   * @retval None
00227   */
00228 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00229
00230 /**
00231   * @brief Enable the PVD Event Line.
00232   * @retval None
00233   */
00234 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00235
00236 /**
00237   * @brief Disable the PVD Event Line.
00238   * @retval None
00239   */
00240 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00241
00242 /**
00243   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00244   * @retval None
00245   */
00246 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00247
00248 /**
00249   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00250   * @retval None
00251   */
00252 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00253
00254 /**
00255   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00256   * @retval None
00257   */
00258 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00259
00260
00261 /**
00262   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00263   * @retval None
00264   */
00265 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00266
00267
00268 /**
00269   * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
00270   * @retval None
00271   */
00272 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00273   do {                                                   \
00274     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
00275     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
00276   } while(0)
00277
00278 /**
00279   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00280   * @retval None
00281   */
00282 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00283   do {                                                    \
00284     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
00285     __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
00286   } while(0)
00287
00288 /**
00289   * @brief  Generate a Software interrupt on selected EXTI line.
00290   * @retval None
00291   */
00292 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
00293
00294 /**
00295   * @brief Check whether or not the PVD EXTI interrupt flag is set.
00296   * @retval EXTI PVD Line Status.
00297   */
00298 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
00299
00300 /**
00301   * @brief Clear the PVD EXTI interrupt flag.
00302   * @retval None
00303   */
00304 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
00305
00306 /**
00307   * @}
00308   */
00309
00310
00311 /* Private macros --------------------------------------------------------*/
00312 /** @addtogroup  PWR_Private_Macros   PWR Private Macros
00313   * @{
00314   */
00315
00316 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00317                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00318                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00319                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00320
00321 #define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
00322                                 ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
00323                                 ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
00324                                 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
00325                                 ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
00326                                 ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
00327                                 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
00328
00329 #define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00330                                           ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00331
00332 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00333
00334 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
00335
00336 /**
00337   * @}
00338   */
00339
00340 /* Include PWR HAL Extended module */
00341 #include "stm32g4xx_hal_pwr_ex.h"
00342
00343 /* Exported functions --------------------------------------------------------*/
00344
00345 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00346   * @{
00347   */
00348
00349 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00350   * @{
00351   */
00352
00353 /* Initialization and de-initialization functions *******************************/
00354 void HAL_PWR_DeInit(void);
00355 void HAL_PWR_EnableBkUpAccess(void);
00356 void HAL_PWR_DisableBkUpAccess(void);
00357
00358 /**
00359   * @}
00360   */
00361
00362 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00363   * @{
00364   */
00365
00366 /* Peripheral Control functions  ************************************************/
00367 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00368 void HAL_PWR_EnablePVD(void);
00369 void HAL_PWR_DisablePVD(void);
00370
00371
00372 /* WakeUp pins configuration functions ****************************************/
00373 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00374 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00375
00376 /* Low Power modes configuration functions ************************************/
00377 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00378 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00379 void HAL_PWR_EnterSTANDBYMode(void);
00380
00381 void HAL_PWR_EnableSleepOnExit(void);
00382 void HAL_PWR_DisableSleepOnExit(void);
00383 void HAL_PWR_EnableSEVOnPend(void);
00384 void HAL_PWR_DisableSEVOnPend(void);
00385
00386 void HAL_PWR_PVDCallback(void);
00387
00388
00389 /**
00390   * @}
00391   */
00392
00393 /**
00394   * @}
00395   */
00396
00397 /**
00398   * @}
00399   */
00400
00401 /**
00402   * @}
00403   */
00404
00405 #ifdef __cplusplus
00406 }
00407 #endif
00408
00409
00410 #endif /* STM32G4xx_HAL_PWR_H */
00411
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_pwr_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Extended Initialization and de-initialization functions
00009   *           + Extended Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g4xx_hal.h"
00026
00027 /** @addtogroup STM32G4xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup PWREx PWREx
00032   * @brief PWR Extended HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_PWR_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040
00041
00042 #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
00043 #define PWR_PORTF_AVAILABLE_PINS   0x0000FFFFU /* PF0..PF15 */
00044 #define PWR_PORTG_AVAILABLE_PINS   0x000007FFU /* PG0..PG10 */
00045 #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx)
00046 #define PWR_PORTF_AVAILABLE_PINS   0x00000607U /* PF0..PF2 and PF9 and PF10 */
00047 #define PWR_PORTG_AVAILABLE_PINS   0x00000400U /* PG10 */
00048 #endif
00049
00050 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
00051   * @{
00052   */
00053
00054 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
00055   * @{
00056   */
00057 #define PVM_MODE_IT               0x00010000U    /*!< Mask for interruption yielded by PVM threshold crossing */
00058 #define PVM_MODE_EVT              0x00020000U    /*!< Mask for event yielded by PVM threshold crossing        */
00059 #define PVM_RISING_EDGE           0x00000001U    /*!< Mask for rising edge set as PVM trigger                 */
00060 #define PVM_FALLING_EDGE          0x00000002U    /*!< Mask for falling edge set as PVM trigger                */
00061 /**
00062   * @}
00063   */
00064
00065 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
00066   * @{
00067   */
00068 #define PWR_FLAG_SETTING_DELAY_US                      50UL   /*!< Time out value for REGLPF and VOSF flags setting */
00069 /**
00070   * @}
00071   */
00072
00073
00074
00075 /**
00076   * @}
00077   */
00078
00079
00080
00081 /* Private macro -------------------------------------------------------------*/
00082 /* Private variables ---------------------------------------------------------*/
00083 /* Private function prototypes -----------------------------------------------*/
00084 /* Exported functions --------------------------------------------------------*/
00085
00086 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
00087   * @{
00088   */
00089
00090 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00091   *  @brief   Extended Peripheral Control functions
00092   *
00093 @verbatim
00094  ===============================================================================
00095               ##### Extended Peripheral Initialization and de-initialization functions #####
00096  ===============================================================================
00097     [..]
00098
00099 @endverbatim
00100   * @{
00101   */
00102
00103
00104 /**
00105   * @brief Return Voltage Scaling Range.
00106   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
00107   *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
00108   */
00109 uint32_t HAL_PWREx_GetVoltageRange(void)
00110 {
00111   if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
00112   {
00113     return PWR_REGULATOR_VOLTAGE_SCALE2;
00114   }
00115   else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
00116   {
00117     /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
00118     return PWR_REGULATOR_VOLTAGE_SCALE1;
00119   }
00120   else
00121   {
00122     return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
00123   }
00124 }
00125
00126
00127
00128 /**
00129   * @brief Configure the main internal regulator output voltage.
00130   * @param  VoltageScaling: specifies the regulator output voltage to achieve
00131   *         a tradeoff between performance and power consumption.
00132   *          This parameter can be one of the following values:
00133   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
00134   *                                                typical output voltage at 1.28 V,
00135   *                                                system frequency up to 170 MHz.
00136   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
00137   *                                                typical output voltage at 1.2 V,
00138   *                                                system frequency up to 150 MHz.
00139   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
00140   *                                                typical output voltage at 1.0 V,
00141   *                                                system frequency up to 26 MHz.
00142   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
00143   *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
00144   *        When moving from Range 2 to Range 1, the system frequency can be increased to
00145   *        a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
00146   *        When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to
00147   *        a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
00148   * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
00149   *        cleared before returning the status. If the flag is not cleared within
00150   *        50 microseconds, HAL_TIMEOUT status is reported.
00151   * @retval HAL Status
00152   */
00153 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00154 {
00155   uint32_t wait_loop_index;
00156
00157   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00158
00159   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
00160   {
00161     /* If current range is range 2 */
00162     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
00163     {
00164       /* Make sure Range 1 Boost is enabled */
00165       CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
00166
00167       /* Set Range 1 */
00168       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
00169
00170       /* Wait until VOSF is cleared */
00171       wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
00172       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
00173       {
00174         wait_loop_index--;
00175       }
00176       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
00177       {
00178         return HAL_TIMEOUT;
00179       }
00180     }
00181     /* If current range is range 1 normal or boost mode */
00182     else
00183     {
00184       /* Enable Range 1 Boost (no issue if bit already reset) */
00185       CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
00186     }
00187   }
00188   else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
00189   {
00190     /* If current range is range 2 */
00191     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
00192     {
00193       /* Make sure Range 1 Boost is disabled */
00194       SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
00195
00196       /* Set Range 1 */
00197       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
00198
00199       /* Wait until VOSF is cleared */
00200       wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
00201       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
00202       {
00203         wait_loop_index--;
00204       }
00205       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
00206       {
00207         return HAL_TIMEOUT;
00208       }
00209     }
00210      /* If current range is range 1 normal or boost mode */
00211     else
00212     {
00213       /* Disable Range 1 Boost (no issue if bit already set) */
00214       SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
00215     }
00216   }
00217   else
00218   {
00219     /* Set Range 2 */
00220     MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
00221     /* No need to wait for VOSF to be cleared for this transition */
00222     /* PWR_CR5_R1MODE bit setting has no effect in Range 2        */
00223   }
00224
00225   return HAL_OK;
00226 }
00227
00228
00229 /**
00230   * @brief Enable battery charging.
00231   *        When VDD is present, charge the external battery on VBAT through an internal resistor.
00232   * @param  ResistorSelection: specifies the resistor impedance.
00233   *          This parameter can be one of the following values:
00234   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
00235   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
00236   * @retval None
00237   */
00238 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
00239 {
00240   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
00241
00242   /* Specify resistor selection */
00243   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
00244
00245   /* Enable battery charging */
00246   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00247 }
00248
00249
00250 /**
00251   * @brief Disable battery charging.
00252   * @retval None
00253   */
00254 void HAL_PWREx_DisableBatteryCharging(void)
00255 {
00256   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00257 }
00258
00259
00260 /**
00261   * @brief Enable Internal Wake-up Line.
00262   * @retval None
00263   */
00264 void HAL_PWREx_EnableInternalWakeUpLine(void)
00265 {
00266   SET_BIT(PWR->CR3, PWR_CR3_EIWF);
00267 }
00268
00269
00270 /**
00271   * @brief Disable Internal Wake-up Line.
00272   * @retval None
00273   */
00274 void HAL_PWREx_DisableInternalWakeUpLine(void)
00275 {
00276   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
00277 }
00278
00279
00280
00281 /**
00282   * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
00283   * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
00284   *        pull-up state in Standby and Shutdown modes.
00285   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00286   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00287   * @note  The configuration is lost when exiting the Shutdown mode due to the
00288   *        power-on reset, maintained when exiting the Standby mode.
00289   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00290   *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.
00291   * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input
00292   *        parameter at the same time are set.
00293   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
00294   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
00295   * @param  GPIONumber: Specify the I/O pins numbers.
00296   *         This parameter can be one of the following values:
00297   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
00298   *         I/O pins are available) or the logical OR of several of them to set
00299   *         several bits for a given port in a single API call.
00300   * @retval HAL Status
00301   */
00302 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00303 {
00304   HAL_StatusTypeDef status = HAL_OK;
00305
00306   assert_param(IS_PWR_GPIO(GPIO));
00307   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00308
00309   switch (GPIO)
00310   {
00311     case PWR_GPIO_A:
00312        SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00313        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00314        break;
00315     case PWR_GPIO_B:
00316        SET_BIT(PWR->PUCRB, GPIONumber);
00317        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00318        break;
00319     case PWR_GPIO_C:
00320        SET_BIT(PWR->PUCRC, GPIONumber);
00321        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00322        break;
00323     case PWR_GPIO_D:
00324        SET_BIT(PWR->PUCRD, GPIONumber);
00325        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00326        break;
00327     case PWR_GPIO_E:
00328        SET_BIT(PWR->PUCRE, GPIONumber);
00329        CLEAR_BIT(PWR->PDCRE, GPIONumber);
00330        break;
00331     case PWR_GPIO_F:
00332        SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00333        CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00334        break;
00335     case PWR_GPIO_G:
00336        SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
00337        CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
00338        break;
00339     default:
00340       status = HAL_ERROR;
00341       break;
00342   }
00343
00344   return status;
00345 }
00346
00347
00348 /**
00349   * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
00350   * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
00351   *        in pull-up state in Standby and Shutdown modes.
00352   * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input
00353   *        parameter at the same time are reset.
00354   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
00355   *          (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
00356   * @param  GPIONumber: Specify the I/O pins numbers.
00357   *         This parameter can be one of the following values:
00358   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
00359   *         I/O pins are available) or the logical OR of several of them to reset
00360   *         several bits for a given port in a single API call.
00361   * @retval HAL Status
00362   */
00363 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00364 {
00365   HAL_StatusTypeDef status = HAL_OK;
00366
00367   assert_param(IS_PWR_GPIO(GPIO));
00368   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00369
00370   switch (GPIO)
00371   {
00372     case PWR_GPIO_A:
00373        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00374        break;
00375     case PWR_GPIO_B:
00376        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00377        break;
00378     case PWR_GPIO_C:
00379        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00380        break;
00381     case PWR_GPIO_D:
00382        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00383        break;
00384     case PWR_GPIO_E:
00385        CLEAR_BIT(PWR->PUCRE, GPIONumber);
00386        break;
00387     case PWR_GPIO_F:
00388        CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00389        break;
00390     case PWR_GPIO_G:
00391        CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
00392        break;
00393     default:
00394        status = HAL_ERROR;
00395        break;
00396   }
00397
00398   return status;
00399 }
00400
00401
00402
00403 /**
00404   * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
00405   * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
00406   *        pull-down state in Standby and Shutdown modes.
00407   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00408   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00409   * @note  The configuration is lost when exiting the Shutdown mode due to the
00410   *        power-on reset, maintained when exiting the Standby mode.
00411   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00412   *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.
00413   * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input
00414   *        parameter at the same time are set.
00415   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
00416   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
00417   * @param  GPIONumber: Specify the I/O pins numbers.
00418   *         This parameter can be one of the following values:
00419   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
00420   *         I/O pins are available) or the logical OR of several of them to set
00421   *         several bits for a given port in a single API call.
00422   * @retval HAL Status
00423   */
00424 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00425 {
00426   HAL_StatusTypeDef status = HAL_OK;
00427
00428   assert_param(IS_PWR_GPIO(GPIO));
00429   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00430
00431   switch (GPIO)
00432   {
00433     case PWR_GPIO_A:
00434        SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00435        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00436        break;
00437     case PWR_GPIO_B:
00438        SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00439        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00440        break;
00441     case PWR_GPIO_C:
00442        SET_BIT(PWR->PDCRC, GPIONumber);
00443        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00444        break;
00445     case PWR_GPIO_D:
00446        SET_BIT(PWR->PDCRD, GPIONumber);
00447        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00448        break;
00449     case PWR_GPIO_E:
00450        SET_BIT(PWR->PDCRE, GPIONumber);
00451        CLEAR_BIT(PWR->PUCRE, GPIONumber);
00452        break;
00453     case PWR_GPIO_F:
00454        SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00455        CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00456        break;
00457     case PWR_GPIO_G:
00458        SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
00459        CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
00460        break;
00461     default:
00462       status = HAL_ERROR;
00463       break;
00464   }
00465
00466   return status;
00467 }
00468
00469
00470 /**
00471   * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
00472   * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
00473   *        in pull-down state in Standby and Shutdown modes.
00474   * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input
00475   *        parameter at the same time are reset.
00476   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
00477   *         (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
00478   * @param  GPIONumber: Specify the I/O pins numbers.
00479   *         This parameter can be one of the following values:
00480   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
00481   *         I/O pins are available) or the logical OR of several of them to reset
00482   *         several bits for a given port in a single API call.
00483   * @retval HAL Status
00484   */
00485 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00486 {
00487   HAL_StatusTypeDef status = HAL_OK;
00488
00489   assert_param(IS_PWR_GPIO(GPIO));
00490   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00491
00492   switch (GPIO)
00493   {
00494     case PWR_GPIO_A:
00495        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00496        break;
00497     case PWR_GPIO_B:
00498        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00499        break;
00500     case PWR_GPIO_C:
00501        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00502        break;
00503     case PWR_GPIO_D:
00504        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00505        break;
00506     case PWR_GPIO_E:
00507        CLEAR_BIT(PWR->PDCRE, GPIONumber);
00508        break;
00509     case PWR_GPIO_F:
00510        CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
00511        break;
00512     case PWR_GPIO_G:
00513        CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
00514        break;
00515     default:
00516       status = HAL_ERROR;
00517       break;
00518   }
00519
00520   return status;
00521 }
00522
00523
00524
00525 /**
00526   * @brief Enable pull-up and pull-down configuration.
00527   * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in
00528   *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
00529   * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
00530   *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
00531   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
00532   *        is no conflict when setting PUy or PDy bit.
00533   * @retval None
00534   */
00535 void HAL_PWREx_EnablePullUpPullDownConfig(void)
00536 {
00537   SET_BIT(PWR->CR3, PWR_CR3_APC);
00538 }
00539
00540
00541 /**
00542   * @brief Disable pull-up and pull-down configuration.
00543   * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
00544   *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
00545   * @retval None
00546   */
00547 void HAL_PWREx_DisablePullUpPullDownConfig(void)
00548 {
00549   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00550 }
00551
00552
00553
00554 /**
00555   * @brief Enable SRAM2 content retention in Standby mode.
00556   * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in
00557   *         Standby mode and its content is kept.
00558   * @retval None
00559   */
00560 void HAL_PWREx_EnableSRAM2ContentRetention(void)
00561 {
00562   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00563 }
00564
00565
00566 /**
00567   * @brief Disable SRAM2 content retention in Standby mode.
00568   * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode
00569   *        and its content is lost.
00570   * @retval None
00571   */
00572 void HAL_PWREx_DisableSRAM2ContentRetention(void)
00573 {
00574   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00575 }
00576
00577
00578
00579
00580 #if defined(PWR_CR2_PVME1)
00581 /**
00582   * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
00583   * @retval None
00584   */
00585 void HAL_PWREx_EnablePVM1(void)
00586 {
00587   SET_BIT(PWR->CR2, PWR_PVM_1);
00588 }
00589
00590 /**
00591   * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
00592   * @retval None
00593   */
00594 void HAL_PWREx_DisablePVM1(void)
00595 {
00596   CLEAR_BIT(PWR->CR2, PWR_PVM_1);
00597 }
00598 #endif /* PWR_CR2_PVME1 */
00599
00600
00601 #if defined(PWR_CR2_PVME2)
00602 /**
00603   * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
00604   * @retval None
00605   */
00606 void HAL_PWREx_EnablePVM2(void)
00607 {
00608   SET_BIT(PWR->CR2, PWR_PVM_2);
00609 }
00610
00611 /**
00612   * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
00613   * @retval None
00614   */
00615 void HAL_PWREx_DisablePVM2(void)
00616 {
00617   CLEAR_BIT(PWR->CR2, PWR_PVM_2);
00618 }
00619 #endif /* PWR_CR2_PVME2 */
00620
00621
00622 /**
00623   * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
00624   * @retval None
00625   */
00626 void HAL_PWREx_EnablePVM3(void)
00627 {
00628   SET_BIT(PWR->CR2, PWR_PVM_3);
00629 }
00630
00631 /**
00632   * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
00633   * @retval None
00634   */
00635 void HAL_PWREx_DisablePVM3(void)
00636 {
00637   CLEAR_BIT(PWR->CR2, PWR_PVM_3);
00638 }
00639
00640
00641 /**
00642   * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
00643   * @retval None
00644   */
00645 void HAL_PWREx_EnablePVM4(void)
00646 {
00647   SET_BIT(PWR->CR2, PWR_PVM_4);
00648 }
00649
00650 /**
00651   * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
00652   * @retval None
00653   */
00654 void HAL_PWREx_DisablePVM4(void)
00655 {
00656   CLEAR_BIT(PWR->CR2, PWR_PVM_4);
00657 }
00658
00659
00660
00661
00662 /**
00663   * @brief Configure the Peripheral Voltage Monitoring (PVM).
00664   * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
00665   *        PVM configuration information.
00666   * @note The API configures a single PVM according to the information contained
00667   *       in the input structure. To configure several PVMs, the API must be singly
00668   *       called for each PVM used.
00669   * @note Refer to the electrical characteristics of your device datasheet for
00670   *         more details about the voltage thresholds corresponding to each
00671   *         detection level and to each monitored supply.
00672   * @retval HAL status
00673   */
00674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
00675 {
00676   HAL_StatusTypeDef status = HAL_OK;
00677
00678   /* Check the parameters */
00679   assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
00680   assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
00681
00682
00683   /* Configure EXTI 35 to 38 interrupts if so required:
00684      scan through PVMType to detect which PVMx is set and
00685      configure the corresponding EXTI line accordingly. */
00686   switch (sConfigPVM->PVMType)
00687   {
00688 #if defined(PWR_CR2_PVME1)
00689     case PWR_PVM_1:
00690       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00691       __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
00692       __HAL_PWR_PVM1_EXTI_DISABLE_IT();
00693       __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
00694       __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
00695
00696       /* Configure interrupt mode */
00697       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00698       {
00699         __HAL_PWR_PVM1_EXTI_ENABLE_IT();
00700       }
00701
00702       /* Configure event mode */
00703       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00704       {
00705         __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
00706       }
00707
00708       /* Configure the edge */
00709       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00710       {
00711         __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
00712       }
00713
00714       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00715       {
00716         __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
00717       }
00718       break;
00719 #endif /* PWR_CR2_PVME1 */
00720
00721 #if defined(PWR_CR2_PVME2)
00722     case PWR_PVM_2:
00723       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00724       __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
00725       __HAL_PWR_PVM2_EXTI_DISABLE_IT();
00726       __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
00727       __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
00728
00729       /* Configure interrupt mode */
00730       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00731       {
00732         __HAL_PWR_PVM2_EXTI_ENABLE_IT();
00733       }
00734
00735       /* Configure event mode */
00736       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00737       {
00738         __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
00739       }
00740
00741       /* Configure the edge */
00742       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00743       {
00744         __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
00745       }
00746
00747       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00748       {
00749         __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
00750       }
00751       break;
00752 #endif /* PWR_CR2_PVME2 */
00753
00754     case PWR_PVM_3:
00755       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00756       __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
00757       __HAL_PWR_PVM3_EXTI_DISABLE_IT();
00758       __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
00759       __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
00760
00761       /* Configure interrupt mode */
00762       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00763       {
00764         __HAL_PWR_PVM3_EXTI_ENABLE_IT();
00765       }
00766
00767       /* Configure event mode */
00768       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00769       {
00770         __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
00771       }
00772
00773       /* Configure the edge */
00774       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00775       {
00776         __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
00777       }
00778
00779       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00780       {
00781         __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
00782       }
00783       break;
00784
00785     case PWR_PVM_4:
00786       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00787       __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
00788       __HAL_PWR_PVM4_EXTI_DISABLE_IT();
00789       __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
00790       __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
00791
00792       /* Configure interrupt mode */
00793       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00794       {
00795         __HAL_PWR_PVM4_EXTI_ENABLE_IT();
00796       }
00797
00798       /* Configure event mode */
00799       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00800       {
00801         __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
00802       }
00803
00804       /* Configure the edge */
00805       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00806       {
00807         __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
00808       }
00809
00810       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00811       {
00812         __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
00813       }
00814       break;
00815
00816     default:
00817       status = HAL_ERROR;
00818       break;
00819   }
00820
00821   return status;
00822 }
00823
00824
00825 /**
00826   * @brief Enter Low-power Run mode
00827   * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
00828   * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00829   *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
00830   *        Additionally, the clock frequency must be reduced below 2 MHz.
00831   *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
00832   *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
00833   * @retval None
00834   */
00835 void HAL_PWREx_EnableLowPowerRunMode(void)
00836 {
00837   /* Set Regulator parameter */
00838   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00839 }
00840
00841
00842 /**
00843   * @brief Exit Low-power Run mode.
00844   * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
00845   *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
00846   *        returns HAL_TIMEOUT status). The system clock frequency can then be
00847   *        increased above 2 MHz.
00848   * @retval HAL Status
00849   */
00850 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
00851 {
00852   uint32_t wait_loop_index;
00853
00854   /* Clear LPR bit */
00855   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00856
00857   /* Wait until REGLPF is reset */
00858   wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
00859   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
00860   {
00861     wait_loop_index--;
00862   }
00863   if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00864   {
00865     return HAL_TIMEOUT;
00866   }
00867
00868   return HAL_OK;
00869 }
00870
00871
00872 /**
00873   * @brief Enter Stop 0 mode.
00874   * @note  In Stop 0 mode, main and low voltage regulators are ON.
00875   * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
00876   * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
00877   *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00878   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00879   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00880   *        only to the peripheral requesting it.
00881   *        SRAM1, SRAM2 and register contents are preserved.
00882   *        The BOR is available.
00883   * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
00884   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00885   *         is set; the HSI oscillator is selected if STOPWUCK is cleared.
00886   * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
00887   *         is higher although the startup time is reduced.
00888   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
00889   *          This parameter can be one of the following values:
00890   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
00891   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
00892   * @retval None
00893   */
00894 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
00895 {
00896   /* Check the parameters */
00897   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00898
00899   /* Stop 0 mode with Main Regulator */
00900   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
00901
00902   /* Set SLEEPDEEP bit of Cortex System Control Register */
00903   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00904
00905   /* Select Stop mode entry --------------------------------------------------*/
00906   if(STOPEntry == PWR_STOPENTRY_WFI)
00907   {
00908     /* Request Wait For Interrupt */
00909     __WFI();
00910   }
00911   else
00912   {
00913     /* Request Wait For Event */
00914     __SEV();
00915     __WFE();
00916     __WFE();
00917   }
00918
00919   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00920   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00921 }
00922
00923
00924 /**
00925   * @brief Enter Stop 1 mode.
00926   * @note  In Stop 1 mode, only low power voltage regulator is ON.
00927   * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
00928   * @note  All clocks in the VCORE domain are stopped; the PLL, the HSI
00929   *        and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00930   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00931   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00932   *        only to the peripheral requesting it.
00933   *        SRAM1, SRAM2 and register contents are preserved.
00934   *        The BOR is available.
00935   * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
00936   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00937   *         is set.
00938   * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
00939   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
00940   *          This parameter can be one of the following values:
00941   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
00942   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
00943   * @retval None
00944   */
00945 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
00946 {
00947   /* Check the parameters */
00948   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00949
00950   /* Stop 1 mode with Low-Power Regulator */
00951   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
00952
00953   /* Set SLEEPDEEP bit of Cortex System Control Register */
00954   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00955
00956   /* Select Stop mode entry --------------------------------------------------*/
00957   if(STOPEntry == PWR_STOPENTRY_WFI)
00958   {
00959     /* Request Wait For Interrupt */
00960     __WFI();
00961   }
00962   else
00963   {
00964     /* Request Wait For Event */
00965     __SEV();
00966     __WFE();
00967     __WFE();
00968   }
00969
00970   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00971   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00972 }
00973
00974
00975
00976
00977 /**
00978   * @brief Enter Shutdown mode.
00979   * @note  In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
00980   *        off. The voltage regulator is disabled and Vcore domain is powered off.
00981   *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
00982   *        The BOR is not available.
00983   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00984   * @retval None
00985   */
00986 void HAL_PWREx_EnterSHUTDOWNMode(void)
00987 {
00988
00989   /* Set Shutdown mode */
00990   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
00991
00992   /* Set SLEEPDEEP bit of Cortex System Control Register */
00993   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00994
00995 /* This option is used to ensure that store operations are completed */
00996 #if defined ( __CC_ARM)
00997   __force_stores();
00998 #endif
00999   /* Request Wait For Interrupt */
01000   __WFI();
01001 }
01002
01003
01004
01005
01006 /**
01007   * @brief This function handles the PWR PVD/PVMx interrupt request.
01008   * @note This API should be called under the PVD_PVM_IRQHandler().
01009   * @retval None
01010   */
01011 void HAL_PWREx_PVD_PVM_IRQHandler(void)
01012 {
01013   /* Check PWR exti flag */
01014   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U)
01015   {
01016     /* PWR PVD interrupt user callback */
01017     HAL_PWR_PVDCallback();
01018
01019     /* Clear PVD exti pending bit */
01020     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
01021   }
01022   /* Next, successively check PVMx exti flags */
01023 #if defined(PWR_CR2_PVME1)
01024   if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
01025   {
01026     /* PWR PVM1 interrupt user callback */
01027     HAL_PWREx_PVM1Callback();
01028
01029     /* Clear PVM1 exti pending bit */
01030     __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
01031   }
01032 #endif /* PWR_CR2_PVME1 */
01033 #if defined(PWR_CR2_PVME2)
01034   if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U)
01035   {
01036     /* PWR PVM2 interrupt user callback */
01037     HAL_PWREx_PVM2Callback();
01038
01039     /* Clear PVM2 exti pending bit */
01040     __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
01041   }
01042 #endif /* PWR_CR2_PVME2 */
01043   if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
01044   {
01045     /* PWR PVM3 interrupt user callback */
01046     HAL_PWREx_PVM3Callback();
01047
01048     /* Clear PVM3 exti pending bit */
01049     __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
01050   }
01051   if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U)
01052   {
01053     /* PWR PVM4 interrupt user callback */
01054     HAL_PWREx_PVM4Callback();
01055
01056     /* Clear PVM4 exti pending bit */
01057     __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
01058   }
01059 }
01060
01061
01062 #if defined(PWR_CR2_PVME1)
01063 /**
01064   * @brief PWR PVM1 interrupt callback
01065   * @retval None
01066   */
01067 __weak void HAL_PWREx_PVM1Callback(void)
01068 {
01069   /* NOTE : This function should not be modified; when the callback is needed,
01070             HAL_PWREx_PVM1Callback() API can be implemented in the user file
01071    */
01072 }
01073 #endif /* PWR_CR2_PVME1 */
01074
01075 #if defined(PWR_CR2_PVME2)
01076 /**
01077   * @brief PWR PVM2 interrupt callback
01078   * @retval None
01079   */
01080 __weak void HAL_PWREx_PVM2Callback(void)
01081 {
01082   /* NOTE : This function should not be modified; when the callback is needed,
01083             HAL_PWREx_PVM2Callback() API can be implemented in the user file
01084    */
01085 }
01086 #endif /* PWR_CR2_PVME2 */
01087
01088 /**
01089   * @brief PWR PVM3 interrupt callback
01090   * @retval None
01091   */
01092 __weak void HAL_PWREx_PVM3Callback(void)
01093 {
01094   /* NOTE : This function should not be modified; when the callback is needed,
01095             HAL_PWREx_PVM3Callback() API can be implemented in the user file
01096    */
01097 }
01098
01099 /**
01100   * @brief PWR PVM4 interrupt callback
01101   * @retval None
01102   */
01103 __weak void HAL_PWREx_PVM4Callback(void)
01104 {
01105   /* NOTE : This function should not be modified; when the callback is needed,
01106             HAL_PWREx_PVM4Callback() API can be implemented in the user file
01107    */
01108 }
01109
01110 #if defined(PWR_CR3_UCPD_STDBY)
01111 /**
01112   * @brief Enable UCPD configuration memorization in Standby.
01113   * @retval None
01114   */
01115 void HAL_PWREx_EnableUCPDStandbyMode(void)
01116 {
01117   /* Memorize UCPD configuration when entering standby mode */
01118   SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
01119 }
01120
01121 /**
01122   * @brief Disable UCPD configuration memorization in Standby.
01123   * @note  This function must be called on exiting the Standby mode and before any UCPD
01124   *        configuration update.
01125   * @retval None
01126   */
01127 void HAL_PWREx_DisableUCPDStandbyMode(void)
01128 {
01129   /* Write 0 immediately after Standby exit when using UCPD,
01130      and before writing any UCPD registers */
01131   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
01132 }
01133 #endif /* PWR_CR3_UCPD_STDBY */
01134
01135 #if defined(PWR_CR3_UCPD_DBDIS)
01136 /**
01137   * @brief Enable the USB Type-C dead battery pull-down behavior
01138   *        on UCPDx_CC1 and UCPDx_CC2 pins
01139   * @retval None
01140   */
01141 void HAL_PWREx_EnableUCPDDeadBattery(void)
01142 {
01143   /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
01144   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
01145 }
01146
01147 /**
01148   * @brief Disable the USB Type-C dead battery pull-down behavior
01149   *        on UCPDx_CC1 and UCPDx_CC2 pins
01150   * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
01151   *       which may have a pull-down effect on CC1 and CC2 pins.
01152   *       It is recommended to disable it in all cases, either to stop this pull-down
01153   *       or to hand over control to the UCPD (which should therefore be
01154   *       initialized before doing the disable).
01155   * @retval None
01156   */
01157 void HAL_PWREx_DisableUCPDDeadBattery(void)
01158 {
01159   /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
01160   SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
01161 }
01162 #endif /* PWR_CR3_UCPD_DBDIS */
01163
01164
01165
01166 /**
01167   * @}
01168   */
01169
01170 /**
01171   * @}
01172   */
01173
01174 #endif /* HAL_PWR_MODULE_ENABLED */
01175 /**
01176   * @}
01177   */
01178
01179 /**
01180   * @}
01181   */
01182
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_pwr_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_pwr_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_PWR_EX_H
00021 #define STM32G4xx_HAL_PWR_EX_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup PWREx
00035   * @{
00036   */
00037
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00042   * @{
00043   */
00044
00045
00046 /**
00047   * @brief  PWR PVM configuration structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
00052                            This parameter can be a value of @ref PWREx_PVM_Type. */
00053   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00054                            This parameter can be a value of @ref PWREx_PVM_Mode. */
00055 }PWR_PVMTypeDef;
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Exported constants --------------------------------------------------------*/
00062
00063 /** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
00068   * @{
00069   */
00070 #define PWR_WUP_POLARITY_SHIFT                  0x05U   /*!< Internal constant used to retrieve wakeup pin polariry */
00071 /**
00072   * @}
00073   */
00074
00075
00076 /** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
00077   * @{
00078   */
00079 #define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00080 #define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00081 #define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00082 #define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00083 #define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00084 #define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00085 #define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00086 #define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00087 #define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00088 #define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00089 #define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
00090 #define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
00091 #define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
00092 #define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
00093 #define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
00099   * @{
00100   */
00101 #if defined(PWR_CR2_PVME1)
00102 #define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
00103 #endif /* PWR_CR2_PVME1 */
00104 #if defined(PWR_CR2_PVME2)
00105 #define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
00106 #endif /* PWR_CR2_PVME2 */
00107 #define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
00108 #define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
00114   * @{
00115   */
00116 #define PWR_PVM_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
00117 #define PWR_PVM_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
00118 #define PWR_PVM_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
00119 #define PWR_PVM_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00120 #define PWR_PVM_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
00121 #define PWR_PVM_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
00122 #define PWR_PVM_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
00123 /**
00124   * @}
00125   */
00126
00127
00128
00129 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
00130   * @{
00131   */
00132 #if defined(PWR_CR5_R1MODE)
00133 #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  ((uint32_t)0x00000000)  /*!< Voltage scaling range 1 boost mode  */
00134 #endif /*PWR_CR5_R1MODE */
00135 #define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0           /*!< Voltage scaling range 1 normal mode */
00136 #define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1           /*!< Voltage scaling range 2             */
00137 /**
00138   * @}
00139   */
00140
00141
00142 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
00143   * @{
00144   */
00145 #define PWR_BATTERY_CHARGING_RESISTOR_5           0x00000000U           /*!< VBAT charging through a 5 kOhms resistor   */
00146 #define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
00152   * @{
00153   */
00154 #define PWR_BATTERY_CHARGING_DISABLE        0x00000000U
00155 #define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
00161   * @{
00162   */
00163 #define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
00164 #define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
00165 #define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
00166 #define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
00167 #define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
00168 #define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
00169 #define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
00170 #define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
00171 #define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
00172 #define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
00173 #define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
00174 #define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
00175 #define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
00176 #define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
00177 #define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
00178 #define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup PWREx_GPIO GPIO port
00184   * @{
00185   */
00186 #define PWR_GPIO_A   0x00000000U      /*!< GPIO port A */
00187 #define PWR_GPIO_B   0x00000001U      /*!< GPIO port B */
00188 #define PWR_GPIO_C   0x00000002U      /*!< GPIO port C */
00189 #define PWR_GPIO_D   0x00000003U      /*!< GPIO port D */
00190 #define PWR_GPIO_E   0x00000004U      /*!< GPIO port E */
00191 #define PWR_GPIO_F   0x00000005U      /*!< GPIO port F */
00192 #define PWR_GPIO_G   0x00000006U      /*!< GPIO port G */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
00198   * @{
00199   */
00200 #if defined(PWR_CR2_PVME1)
00201 #define PWR_EXTI_LINE_PVM1  0x00000008U  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
00202 #endif /* PWR_CR2_PVME1 */
00203 #if defined(PWR_CR2_PVME2)
00204 #define PWR_EXTI_LINE_PVM2  0x00000010U  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
00205 #endif /* PWR_CR2_PVME2 */
00206 #define PWR_EXTI_LINE_PVM3  0x00000020U  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
00207 #define PWR_EXTI_LINE_PVM4  0x00000040U  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
00213   * @{
00214   */
00215 #if defined(PWR_CR2_PVME1)
00216 #define PWR_EVENT_LINE_PVM1     0x00000008U     /*!< Event line 35 Connected to the PVM1 EXTI Line */
00217 #endif /* PWR_CR2_PVME1 */
00218 #if defined(PWR_CR2_PVME2)
00219 #define PWR_EVENT_LINE_PVM2     0x00000010U     /*!< Event line 36 Connected to the PVM2 EXTI Line */
00220 #endif /* PWR_CR2_PVME2 */
00221 #define PWR_EVENT_LINE_PVM3     0x00000020U     /*!< Event line 37 Connected to the PVM3 EXTI Line */
00222 #define PWR_EVENT_LINE_PVM4     0x00000040U     /*!< Event line 38 Connected to the PVM4 EXTI Line */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup PWREx_Flag  PWR Status Flags
00228   *        Elements values convention: 0000 0000 0XXY YYYYb
00229   *           - Y YYYY  : Flag position in the XX register (5 bits)
00230   *           - XX  : Status register (2 bits)
00231   *                 - 01: SR1 register
00232   *                 - 10: SR2 register
00233   *        The only exception is PWR_FLAG_WU, encompassing all
00234   *        wake-up flags and set to PWR_SR1_WUF.
00235   * @{
00236   */
00237 #define PWR_FLAG_WUF1                       0x0020U              /*!< Wakeup event on wakeup pin 1 */
00238 #define PWR_FLAG_WUF2                       0x0021U              /*!< Wakeup event on wakeup pin 2 */
00239 #define PWR_FLAG_WUF3                       0x0022U              /*!< Wakeup event on wakeup pin 3 */
00240 #define PWR_FLAG_WUF4                       0x0023U              /*!< Wakeup event on wakeup pin 4 */
00241 #define PWR_FLAG_WUF5                       0x0024U              /*!< Wakeup event on wakeup pin 5 */
00242 #define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
00243 #define PWR_FLAG_SB                         0x0028U              /*!< Standby flag */
00244 #define PWR_FLAG_WUFI                       0x002FU              /*!< Wakeup on internal wakeup line */
00245
00246 #define PWR_FLAG_REGLPS                     0x0048U              /*!< Low-power regulator start flag */
00247 #define PWR_FLAG_REGLPF                     0x0049U              /*!< Low-power regulator flag */
00248 #define PWR_FLAG_VOSF                       0x004AU              /*!< Voltage scaling flag */
00249 #define PWR_FLAG_PVDO                       0x004BU              /*!< Power Voltage Detector output flag */
00250 #if defined(PWR_CR2_PVME1)
00251 #define PWR_FLAG_PVMO1                      0x004CU              /*!< Power Voltage Monitoring 1 output flag */
00252 #endif /* PWR_CR2_PVME1 */
00253 #if defined(PWR_CR2_PVME2)
00254 #define PWR_FLAG_PVMO2                      0x004DU              /*!< Power Voltage Monitoring 2 output flag */
00255 #endif /* PWR_CR2_PVME2 */
00256 #define PWR_FLAG_PVMO3                      0x004EU              /*!< Power Voltage Monitoring 3 output flag */
00257 #define PWR_FLAG_PVMO4                      0x004FU              /*!< Power Voltage Monitoring 4 output flag */
00258 /**
00259   * @}
00260   */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported macros -----------------------------------------------------------*/
00267 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
00268  * @{
00269  */
00270
00271 #if defined(PWR_CR2_PVME1)
00272 /**
00273   * @brief Enable the PVM1 Extended Interrupt Line.
00274   * @retval None
00275   */
00276 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00277
00278 /**
00279   * @brief Disable the PVM1 Extended Interrupt Line.
00280   * @retval None
00281   */
00282 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00283
00284 /**
00285   * @brief Enable the PVM1 Event Line.
00286   * @retval None
00287   */
00288 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00289
00290 /**
00291   * @brief Disable the PVM1 Event Line.
00292   * @retval None
00293   */
00294 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00295
00296 /**
00297   * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
00298   * @retval None
00299   */
00300 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00301
00302 /**
00303   * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
00304   * @retval None
00305   */
00306 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00307
00308 /**
00309   * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
00310   * @retval None
00311   */
00312 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00313
00314
00315 /**
00316   * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
00317   * @retval None
00318   */
00319 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00320
00321
00322 /**
00323   * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
00324   * @retval None
00325   */
00326 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00327   do {                                                    \
00328     __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
00329     __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
00330   } while(0)
00331
00332 /**
00333   * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
00334   * @retval None
00335   */
00336 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00337   do {                                                     \
00338     __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
00339     __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
00340   } while(0)
00341
00342 /**
00343   * @brief  Generate a Software interrupt on selected EXTI line.
00344   * @retval None
00345   */
00346 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
00347
00348 /**
00349   * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
00350   * @retval EXTI PVM1 Line Status.
00351   */
00352 #define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
00353
00354 /**
00355   * @brief Clear the PVM1 EXTI flag.
00356   * @retval None
00357   */
00358 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
00359
00360 #endif /* PWR_CR2_PVME1 */
00361
00362
00363 #if defined(PWR_CR2_PVME2)
00364 /**
00365   * @brief Enable the PVM2 Extended Interrupt Line.
00366   * @retval None
00367   */
00368 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00369
00370 /**
00371   * @brief Disable the PVM2 Extended Interrupt Line.
00372   * @retval None
00373   */
00374 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00375
00376 /**
00377   * @brief Enable the PVM2 Event Line.
00378   * @retval None
00379   */
00380 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00381
00382 /**
00383   * @brief Disable the PVM2 Event Line.
00384   * @retval None
00385   */
00386 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00387
00388 /**
00389   * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
00390   * @retval None
00391   */
00392 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00393
00394 /**
00395   * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
00396   * @retval None
00397   */
00398 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00399
00400 /**
00401   * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
00402   * @retval None
00403   */
00404 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00405
00406
00407 /**
00408   * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
00409   * @retval None
00410   */
00411 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00412
00413
00414 /**
00415   * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
00416   * @retval None
00417   */
00418 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00419   do {                                                    \
00420     __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
00421     __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
00422   } while(0)
00423
00424 /**
00425   * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
00426   * @retval None
00427   */
00428 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00429   do {                                                     \
00430     __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
00431     __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
00432   } while(0)
00433
00434 /**
00435   * @brief  Generate a Software interrupt on selected EXTI line.
00436   * @retval None
00437   */
00438 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
00439
00440 /**
00441   * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
00442   * @retval EXTI PVM2 Line Status.
00443   */
00444 #define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
00445
00446 /**
00447   * @brief Clear the PVM2 EXTI flag.
00448   * @retval None
00449   */
00450 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
00451
00452 #endif /* PWR_CR2_PVME2 */
00453
00454
00455 /**
00456   * @brief Enable the PVM3 Extended Interrupt Line.
00457   * @retval None
00458   */
00459 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00460
00461 /**
00462   * @brief Disable the PVM3 Extended Interrupt Line.
00463   * @retval None
00464   */
00465 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00466
00467 /**
00468   * @brief Enable the PVM3 Event Line.
00469   * @retval None
00470   */
00471 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00472
00473 /**
00474   * @brief Disable the PVM3 Event Line.
00475   * @retval None
00476   */
00477 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00478
00479 /**
00480   * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
00481   * @retval None
00482   */
00483 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00484
00485 /**
00486   * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
00487   * @retval None
00488   */
00489 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00490
00491 /**
00492   * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
00493   * @retval None
00494   */
00495 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00496
00497
00498 /**
00499   * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
00500   * @retval None
00501   */
00502 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00503
00504
00505 /**
00506   * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
00507   * @retval None
00508   */
00509 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00510   do {                                                    \
00511     __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
00512     __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
00513   } while(0)
00514
00515 /**
00516   * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
00517   * @retval None
00518   */
00519 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00520   do {                                                     \
00521     __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
00522     __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
00523   } while(0)
00524
00525 /**
00526   * @brief  Generate a Software interrupt on selected EXTI line.
00527   * @retval None
00528   */
00529 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
00530
00531 /**
00532   * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
00533   * @retval EXTI PVM3 Line Status.
00534   */
00535 #define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
00536
00537 /**
00538   * @brief Clear the PVM3 EXTI flag.
00539   * @retval None
00540   */
00541 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
00542
00543
00544
00545
00546 /**
00547   * @brief Enable the PVM4 Extended Interrupt Line.
00548   * @retval None
00549   */
00550 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00551
00552 /**
00553   * @brief Disable the PVM4 Extended Interrupt Line.
00554   * @retval None
00555   */
00556 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00557
00558 /**
00559   * @brief Enable the PVM4 Event Line.
00560   * @retval None
00561   */
00562 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00563
00564 /**
00565   * @brief Disable the PVM4 Event Line.
00566   * @retval None
00567   */
00568 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00569
00570 /**
00571   * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
00572   * @retval None
00573   */
00574 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00575
00576 /**
00577   * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
00578   * @retval None
00579   */
00580 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00581
00582 /**
00583   * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
00584   * @retval None
00585   */
00586 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00587
00588
00589 /**
00590   * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
00591   * @retval None
00592   */
00593 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00594
00595
00596 /**
00597   * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
00598   * @retval None
00599   */
00600 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00601   do {                                                    \
00602     __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
00603     __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
00604   } while(0)
00605
00606 /**
00607   * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
00608   * @retval None
00609   */
00610 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00611   do {                                                     \
00612     __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
00613     __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
00614   } while(0)
00615
00616 /**
00617   * @brief  Generate a Software interrupt on selected EXTI line.
00618   * @retval None
00619   */
00620 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
00621
00622 /**
00623   * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
00624   * @retval EXTI PVM4 Line Status.
00625   */
00626 #define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
00627
00628 /**
00629   * @brief Clear the PVM4 EXTI flag.
00630   * @retval None
00631   */
00632 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
00633
00634
00635 /**
00636   * @brief Configure the main internal regulator output voltage.
00637   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00638   *         a tradeoff between performance and power consumption.
00639   *          This parameter can be one of the following values:
00640   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST  Regulator voltage output range 1 mode,
00641   *                                                typical output voltage at 1.28 V,
00642   *                                                system frequency up to 170 MHz.
00643   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
00644   *                                                typical output voltage at 1.2 V,
00645   *                                                system frequency up to 150 MHz.
00646   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
00647   *                                                typical output voltage at 1.0 V,
00648   *                                                system frequency up to 26 MHz.
00649   * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
00650   *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
00651   *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
00652   * @retval None
00653   */
00654 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00655                                                             __IO uint32_t tmpreg;                               \
00656                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
00657                                                             /* Delay after an RCC peripheral clock enabling */  \
00658                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
00659                                                             UNUSED(tmpreg);                                     \
00660                                                           } while(0)
00661
00662 /**
00663   * @}
00664   */
00665
00666 /* Private macros --------------------------------------------------------*/
00667 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00668   * @{
00669   */
00670
00671 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
00672                                 ((PIN) == PWR_WAKEUP_PIN2) || \
00673                                 ((PIN) == PWR_WAKEUP_PIN3) || \
00674                                 ((PIN) == PWR_WAKEUP_PIN4) || \
00675                                 ((PIN) == PWR_WAKEUP_PIN5) || \
00676                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
00677                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
00678                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
00679                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
00680                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
00681                                 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
00682                                 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
00683                                 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
00684                                 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
00685                                 ((PIN) == PWR_WAKEUP_PIN5_LOW))
00686
00687 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00688                                ((TYPE) == PWR_PVM_2) ||\
00689                                ((TYPE) == PWR_PVM_3) ||\
00690                                ((TYPE) == PWR_PVM_4))
00691
00692 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
00693                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
00694                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
00695                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
00696                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
00697                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
00698                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
00699
00700 #if defined(PWR_CR5_R1MODE)
00701 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
00702                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1)       || \
00703                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00704 #else
00705 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00706                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00707 #endif
00708
00709
00710 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00711                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00712
00713 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
00714                                            ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
00715
00716 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
00717 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00718                            ((GPIO) == PWR_GPIO_B) ||\
00719                            ((GPIO) == PWR_GPIO_C) ||\
00720                            ((GPIO) == PWR_GPIO_D) ||\
00721                            ((GPIO) == PWR_GPIO_E) ||\
00722                            ((GPIO) == PWR_GPIO_F) ||\
00723                            ((GPIO) == PWR_GPIO_G))
00724
00725
00726 /**
00727   * @}
00728   */
00729
00730
00731 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00732   * @{
00733   */
00734
00735 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00736   * @{
00737   */
00738
00739
00740 /* Peripheral Control functions  **********************************************/
00741 uint32_t HAL_PWREx_GetVoltageRange(void);
00742 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00743 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
00744 void HAL_PWREx_DisableBatteryCharging(void);
00745 void HAL_PWREx_EnableInternalWakeUpLine(void);
00746 void HAL_PWREx_DisableInternalWakeUpLine(void);
00747 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00748 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00749 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00750 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00751 void HAL_PWREx_EnablePullUpPullDownConfig(void);
00752 void HAL_PWREx_DisablePullUpPullDownConfig(void);
00753 void HAL_PWREx_EnableSRAM2ContentRetention(void);
00754 void HAL_PWREx_DisableSRAM2ContentRetention(void);
00755 #if defined(PWR_CR2_PVME1)
00756 void HAL_PWREx_EnablePVM1(void);
00757 void HAL_PWREx_DisablePVM1(void);
00758 #endif /* PWR_CR2_PVME1 */
00759 #if defined(PWR_CR2_PVME2)
00760 void HAL_PWREx_EnablePVM2(void);
00761 void HAL_PWREx_DisablePVM2(void);
00762 #endif /* PWR_CR2_PVME2 */
00763 void HAL_PWREx_EnablePVM3(void);
00764 void HAL_PWREx_DisablePVM3(void);
00765 void HAL_PWREx_EnablePVM4(void);
00766 void HAL_PWREx_DisablePVM4(void);
00767 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
00768
00769 /* Low Power modes configuration functions ************************************/
00770 void HAL_PWREx_EnableLowPowerRunMode(void);
00771 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
00772 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
00773 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
00774 void HAL_PWREx_EnterSHUTDOWNMode(void);
00775
00776 void HAL_PWREx_PVD_PVM_IRQHandler(void);
00777 #if defined(PWR_CR2_PVME1)
00778 void HAL_PWREx_PVM1Callback(void);
00779 #endif /* PWR_CR2_PVME1 */
00780 #if defined(PWR_CR2_PVME2)
00781 void HAL_PWREx_PVM2Callback(void);
00782 #endif /* PWR_CR2_PVME2 */
00783 void HAL_PWREx_PVM3Callback(void);
00784 void HAL_PWREx_PVM4Callback(void);
00785
00786 #if defined(PWR_CR3_UCPD_STDBY)
00787 void HAL_PWREx_EnableUCPDStandbyMode(void);
00788 void HAL_PWREx_DisableUCPDStandbyMode(void);
00789 #endif /* PWR_CR3_UCPD_STDBY */
00790 #if defined(PWR_CR3_UCPD_DBDIS)
00791 void HAL_PWREx_EnableUCPDDeadBattery(void);
00792 void HAL_PWREx_DisableUCPDDeadBattery(void);
00793 #endif /* PWR_CR3_UCPD_DBDIS */
00794
00795 /**
00796   * @}
00797   */
00798
00799 /**
00800   * @}
00801   */
00802
00803 /**
00804   * @}
00805   */
00806
00807 /**
00808   * @}
00809   */
00810
00811 #ifdef __cplusplus
00812 }
00813 #endif
00814
00815
00816 #endif /* STM32G4xx_HAL_PWR_EX_H */
00817
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_qspi.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_qspi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @brief   QSPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the QuadSPI interface (QSPI).
00008   *           + Initialization and de-initialization functions
00009   *           + Indirect functional mode management
00010   *           + Memory-mapped functional mode management
00011   *           + Auto-polling functional mode management
00012   *           + Interrupts and flags management
00013   *           + DMA channel configuration for indirect functional mode
00014   *           + Errors management and abort functionality
00015   *
00016   *
00017   ******************************************************************************
00018   * @attention
00019   *
00020   * Copyright (c) 2019 STMicroelectronics.
00021   * All rights reserved.
00022   *
00023   * This software is licensed under terms that can be found in the LICENSE file
00024   * in the root directory of this software component.
00025   * If no LICENSE file comes with this software, it is provided AS-IS.
00026   *
00027   ******************************************************************************
00028   @verbatim
00029  ===============================================================================
00030                         ##### How to use this driver #####
00031  ===============================================================================
00032   [..]
00033     *** Initialization ***
00034     ======================
00035     [..]
00036       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00037         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00038         (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00039         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00040         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00041         (++) If interrupt mode is used, enable and configure QuadSPI global
00042             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00043         (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
00044             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00045             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00046             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00047       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00048           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00049
00050     *** Indirect functional mode ***
00051     ================================
00052     [..]
00053       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00054           functions :
00055          (++) Instruction phase : the mode used and if present the instruction opcode.
00056          (++) Address phase : the mode used and if present the size and the address value.
00057          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00058              bytes values.
00059          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00060          (++) Data phase : the mode used and if present the number of bytes.
00061          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00062              if activated.
00063          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00064       (#) If no data is required for the command, it is sent directly to the memory :
00065          (++) In polling mode, the output of the function is done when the transfer is complete.
00066          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00067       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00068           HAL_QSPI_Transmit_IT() after the command configuration :
00069          (++) In polling mode, the output of the function is done when the transfer is complete.
00070          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00071              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00072          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00073              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00074       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00075           HAL_QSPI_Receive_IT() after the command configuration :
00076          (++) In polling mode, the output of the function is done when the transfer is complete.
00077          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00078              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00079          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00080              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00081
00082     *** Auto-polling functional mode ***
00083     ====================================
00084     [..]
00085       (#) Configure the command sequence and the auto-polling functional mode using the
00086           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00087          (++) Instruction phase : the mode used and if present the instruction opcode.
00088          (++) Address phase : the mode used and if present the size and the address value.
00089          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00090              bytes values.
00091          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00092          (++) Data phase : the mode used.
00093          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00094              if activated.
00095          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00096          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00097              the polling interval and the automatic stop activation.
00098       (#) After the configuration :
00099          (++) In polling mode, the output of the function is done when the status match is reached. The
00100              automatic stop is activated to avoid an infinite loop.
00101          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00102
00103     *** Memory-mapped functional mode ***
00104     =====================================
00105     [..]
00106       (#) Configure the command sequence and the memory-mapped functional mode using the
00107           HAL_QSPI_MemoryMapped() functions :
00108          (++) Instruction phase : the mode used and if present the instruction opcode.
00109          (++) Address phase : the mode used and the size.
00110          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00111              bytes values.
00112          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00113          (++) Data phase : the mode used.
00114          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00115              if activated.
00116          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00117          (++) The timeout activation and the timeout period.
00118       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00119           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00120
00121     *** Errors management and abort functionality ***
00122     =================================================
00123     [..]
00124       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00125       (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
00126           flushes the fifo :
00127          (++) In polling mode, the output of the function is done when the transfer
00128               complete bit is set and the busy bit cleared.
00129          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
00130               the transfer complete bit is set.
00131
00132     *** Control functions ***
00133     =========================
00134     [..]
00135       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00136       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
00137       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
00138       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00139       (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
00140
00141     *** Callback registration ***
00142     =============================================
00143     [..]
00144       The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
00145       allows the user to configure dynamically the driver callbacks.
00146
00147       Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
00148       it allows to register following callbacks:
00149         (+) ErrorCallback : callback when error occurs.
00150         (+) AbortCpltCallback : callback when abort is completed.
00151         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00152         (+) CmdCpltCallback : callback when a command without data is completed.
00153         (+) RxCpltCallback : callback when a reception transfer is completed.
00154         (+) TxCpltCallback : callback when a transmission transfer is completed.
00155         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00156         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00157         (+) StatusMatchCallback : callback when a status match occurs.
00158         (+) TimeOutCallback : callback when the timeout perioed expires.
00159         (+) MspInitCallback    : QSPI MspInit.
00160         (+) MspDeInitCallback  : QSPI MspDeInit.
00161       This function takes as parameters the HAL peripheral handle, the Callback ID
00162       and a pointer to the user callback function.
00163
00164       Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
00165       weak (overridden) function. It allows to reset following callbacks:
00166         (+) ErrorCallback : callback when error occurs.
00167         (+) AbortCpltCallback : callback when abort is completed.
00168         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00169         (+) CmdCpltCallback : callback when a command without data is completed.
00170         (+) RxCpltCallback : callback when a reception transfer is completed.
00171         (+) TxCpltCallback : callback when a transmission transfer is completed.
00172         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00173         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00174         (+) StatusMatchCallback : callback when a status match occurs.
00175         (+) TimeOutCallback : callback when the timeout perioed expires.
00176         (+) MspInitCallback    : QSPI MspInit.
00177         (+) MspDeInitCallback  : QSPI MspDeInit.
00178       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00179
00180       By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
00181       all callbacks are reset to the corresponding legacy weak (overridden) functions.
00182       Exception done for MspInit and MspDeInit callbacks that are respectively
00183       reset to the legacy weak (overridden) functions in the HAL_QSPI_Init
00184       and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
00185       If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
00186       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00187
00188       Callbacks can be registered/unregistered in READY state only.
00189       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00190       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00191       during the Init/DeInit.
00192       In that case first register the MspInit/MspDeInit user callbacks
00193       using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
00194       or HAL_QSPI_Init function.
00195
00196       When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
00197       not defined, the callback registering feature is not available
00198       and weak (overridden) callbacks are used.
00199
00200     *** Workarounds linked to Silicon Limitation ***
00201     ====================================================
00202     [..]
00203       (#) Workarounds Implemented inside HAL Driver
00204          (++) Extra data written in the FIFO at the end of a read transfer
00205
00206   @endverbatim
00207   ******************************************************************************
00208   */
00209
00210 /* Includes ------------------------------------------------------------------*/
00211 #include "stm32g4xx_hal.h"
00212
00213 #if defined(QUADSPI)
00214
00215 /** @addtogroup STM32G4xx_HAL_Driver
00216   * @{
00217   */
00218
00219 /** @defgroup QSPI QSPI
00220   * @brief QSPI HAL module driver
00221   * @{
00222   */
00223 #ifdef HAL_QSPI_MODULE_ENABLED
00224
00225 /* Private typedef -----------------------------------------------------------*/
00226
00227 /* Private define ------------------------------------------------------------*/
00228 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00229   * @{
00230   */
00231 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/
00232 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00233 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00234 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00235 /**
00236   * @}
00237   */
00238
00239 /* Private macro -------------------------------------------------------------*/
00240 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00241   * @{
00242   */
00243 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00244                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00245                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00246                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00247 /**
00248   * @}
00249   */
00250
00251 /* Private variables ---------------------------------------------------------*/
00252
00253 /* Private function prototypes -----------------------------------------------*/
00254 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
00255 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
00256 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00257 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00258 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
00259 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
00260 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
00261 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00262
00263 /* Exported functions --------------------------------------------------------*/
00264
00265 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00266   * @{
00267   */
00268
00269 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00270   *  @brief    Initialization and Configuration functions
00271   *
00272 @verbatim
00273 ===============================================================================
00274             ##### Initialization and Configuration functions #####
00275  ===============================================================================
00276     [..]
00277     This subsection provides a set of functions allowing to :
00278       (+) Initialize the QuadSPI.
00279       (+) De-initialize the QuadSPI.
00280
00281 @endverbatim
00282   * @{
00283   */
00284
00285 /**
00286   * @brief Initialize the QSPI mode according to the specified parameters
00287   *        in the QSPI_InitTypeDef and initialize the associated handle.
00288   * @param hqspi QSPI handle
00289   * @retval HAL status
00290   */
00291 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00292 {
00293   HAL_StatusTypeDef status;
00294   uint32_t tickstart = HAL_GetTick();
00295
00296   /* Check the QSPI handle allocation */
00297   if(hqspi == NULL)
00298   {
00299     return HAL_ERROR;
00300   }
00301
00302   /* Check the parameters */
00303   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00304   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00305   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00306   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00307   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00308   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00309   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00310   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00311
00312   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00313   {
00314     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00315   }
00316
00317   if(hqspi->State == HAL_QSPI_STATE_RESET)
00318   {
00319     /* Allocate lock resource and initialize it */
00320     hqspi->Lock = HAL_UNLOCKED;
00321
00322 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00323     /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
00324     hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
00325     hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
00326     hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
00327     hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
00328     hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
00329     hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
00330     hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;
00331     hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;
00332     hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
00333     hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
00334
00335     if(hqspi->MspInitCallback == NULL)
00336     {
00337       hqspi->MspInitCallback = HAL_QSPI_MspInit;
00338     }
00339
00340     /* Init the low level hardware */
00341     hqspi->MspInitCallback(hqspi);
00342 #else
00343     /* Init the low level hardware : GPIO, CLOCK */
00344     HAL_QSPI_MspInit(hqspi);
00345 #endif
00346
00347     /* Configure the default timeout for the QSPI memory access */
00348     HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
00349   }
00350
00351   /* Configure QSPI FIFO Threshold */
00352   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
00353              ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
00354
00355   /* Wait till BUSY flag reset */
00356   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00357
00358   if(status == HAL_OK)
00359   {
00360     /* Configure QSPI Clock Prescaler and Sample Shift */
00361     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
00362                ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
00363                 hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
00364
00365     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00366     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00367                ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
00368                 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00369
00370     /* Enable the QSPI peripheral */
00371     __HAL_QSPI_ENABLE(hqspi);
00372
00373     /* Set QSPI error code to none */
00374     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00375
00376     /* Initialize the QSPI state */
00377     hqspi->State = HAL_QSPI_STATE_READY;
00378   }
00379
00380   /* Release Lock */
00381   __HAL_UNLOCK(hqspi);
00382
00383   /* Return function status */
00384   return status;
00385 }
00386
00387 /**
00388   * @brief De-Initialize the QSPI peripheral.
00389   * @param hqspi QSPI handle
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00393 {
00394   /* Check the QSPI handle allocation */
00395   if(hqspi == NULL)
00396   {
00397     return HAL_ERROR;
00398   }
00399
00400   /* Disable the QSPI Peripheral Clock */
00401   __HAL_QSPI_DISABLE(hqspi);
00402
00403 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00404   if(hqspi->MspDeInitCallback == NULL)
00405   {
00406     hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
00407   }
00408
00409   /* DeInit the low level hardware */
00410   hqspi->MspDeInitCallback(hqspi);
00411 #else
00412   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00413   HAL_QSPI_MspDeInit(hqspi);
00414 #endif
00415
00416   /* Set QSPI error code to none */
00417   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00418
00419   /* Initialize the QSPI state */
00420   hqspi->State = HAL_QSPI_STATE_RESET;
00421
00422   /* Release Lock */
00423   __HAL_UNLOCK(hqspi);
00424
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief Initialize the QSPI MSP.
00430   * @param hqspi QSPI handle
00431   * @retval None
00432   */
00433 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00434 {
00435   /* Prevent unused argument(s) compilation warning */
00436   UNUSED(hqspi);
00437
00438   /* NOTE : This function should not be modified, when the callback is needed,
00439             the HAL_QSPI_MspInit can be implemented in the user file
00440    */
00441 }
00442
00443 /**
00444   * @brief DeInitialize the QSPI MSP.
00445   * @param hqspi QSPI handle
00446   * @retval None
00447   */
00448 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00449 {
00450   /* Prevent unused argument(s) compilation warning */
00451   UNUSED(hqspi);
00452
00453   /* NOTE : This function should not be modified, when the callback is needed,
00454             the HAL_QSPI_MspDeInit can be implemented in the user file
00455    */
00456 }
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
00463   *  @brief QSPI Transmit/Receive functions
00464   *
00465 @verbatim
00466  ===============================================================================
00467                       ##### IO operation functions #####
00468  ===============================================================================
00469     [..]
00470     This subsection provides a set of functions allowing to :
00471       (+) Handle the interrupts.
00472       (+) Handle the command sequence.
00473       (+) Transmit data in blocking, interrupt or DMA mode.
00474       (+) Receive data in blocking, interrupt or DMA mode.
00475       (+) Manage the auto-polling functional mode.
00476       (+) Manage the memory-mapped functional mode.
00477
00478 @endverbatim
00479   * @{
00480   */
00481
00482 /**
00483   * @brief Handle QSPI interrupt request.
00484   * @param hqspi QSPI handle
00485   * @retval None
00486   */
00487 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00488 {
00489   __IO uint32_t *data_reg;
00490   uint32_t flag = READ_REG(hqspi->Instance->SR);
00491   uint32_t itsource = READ_REG(hqspi->Instance->CR);
00492
00493   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
00494   if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
00495   {
00496     data_reg = &hqspi->Instance->DR;
00497
00498     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00499     {
00500       /* Transmission process */
00501       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00502       {
00503         if (hqspi->TxXferCount > 0U)
00504         {
00505           /* Fill the FIFO until the threshold is reached */
00506           *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
00507           hqspi->pTxBuffPtr++;
00508           hqspi->TxXferCount--;
00509         }
00510         else
00511         {
00512           /* No more data available for the transfer */
00513           /* Disable the QSPI FIFO Threshold Interrupt */
00514           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00515           break;
00516         }
00517       }
00518     }
00519     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00520     {
00521       /* Receiving Process */
00522       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00523       {
00524         if (hqspi->RxXferCount > 0U)
00525         {
00526           /* Read the FIFO until the threshold is reached */
00527           *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
00528           hqspi->pRxBuffPtr++;
00529           hqspi->RxXferCount--;
00530         }
00531         else
00532         {
00533           /* All data have been received for the transfer */
00534           /* Disable the QSPI FIFO Threshold Interrupt */
00535           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00536           break;
00537         }
00538       }
00539     }
00540     else
00541     {
00542       /* Nothing to do */
00543     }
00544
00545     /* FIFO Threshold callback */
00546 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00547     hqspi->FifoThresholdCallback(hqspi);
00548 #else
00549     HAL_QSPI_FifoThresholdCallback(hqspi);
00550 #endif
00551   }
00552
00553   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00554   else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
00555   {
00556     /* Clear interrupt */
00557     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
00558
00559     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00560     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00561
00562     /* Transfer complete callback */
00563     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00564     {
00565       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00566       {
00567         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00568         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00569
00570         /* Disable the DMA channel */
00571         __HAL_DMA_DISABLE(hqspi->hdma);
00572       }
00573
00574
00575       /* Change state of QSPI */
00576       hqspi->State = HAL_QSPI_STATE_READY;
00577
00578       /* TX Complete callback */
00579 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00580       hqspi->TxCpltCallback(hqspi);
00581 #else
00582       HAL_QSPI_TxCpltCallback(hqspi);
00583 #endif
00584     }
00585     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00586     {
00587       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00588       {
00589         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00590         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00591
00592         /* Disable the DMA channel */
00593         __HAL_DMA_DISABLE(hqspi->hdma);
00594       }
00595       else
00596       {
00597         data_reg = &hqspi->Instance->DR;
00598         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
00599         {
00600           if (hqspi->RxXferCount > 0U)
00601           {
00602             /* Read the last data received in the FIFO until it is empty */
00603             *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
00604             hqspi->pRxBuffPtr++;
00605             hqspi->RxXferCount--;
00606           }
00607           else
00608           {
00609             /* All data have been received for the transfer */
00610             break;
00611           }
00612         }
00613       }
00614
00615
00616       /* Change state of QSPI */
00617       hqspi->State = HAL_QSPI_STATE_READY;
00618
00619       /* RX Complete callback */
00620 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00621       hqspi->RxCpltCallback(hqspi);
00622 #else
00623       HAL_QSPI_RxCpltCallback(hqspi);
00624 #endif
00625     }
00626     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00627     {
00628       /* Change state of QSPI */
00629       hqspi->State = HAL_QSPI_STATE_READY;
00630
00631       /* Command Complete callback */
00632 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00633       hqspi->CmdCpltCallback(hqspi);
00634 #else
00635       HAL_QSPI_CmdCpltCallback(hqspi);
00636 #endif
00637     }
00638     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
00639     {
00640       /* Reset functional mode configuration to indirect write mode by default */
00641       CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
00642
00643       /* Change state of QSPI */
00644       hqspi->State = HAL_QSPI_STATE_READY;
00645
00646       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
00647       {
00648         /* Abort called by the user */
00649
00650         /* Abort Complete callback */
00651 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00652         hqspi->AbortCpltCallback(hqspi);
00653 #else
00654         HAL_QSPI_AbortCpltCallback(hqspi);
00655 #endif
00656       }
00657       else
00658       {
00659         /* Abort due to an error (eg :  DMA error) */
00660
00661         /* Error callback */
00662 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00663         hqspi->ErrorCallback(hqspi);
00664 #else
00665         HAL_QSPI_ErrorCallback(hqspi);
00666 #endif
00667       }
00668     }
00669     else
00670     {
00671      /* Nothing to do */
00672     }
00673   }
00674
00675   /* QSPI Status Match interrupt occurred ------------------------------------*/
00676   else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
00677   {
00678     /* Clear interrupt */
00679     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
00680
00681     /* Check if the automatic poll mode stop is activated */
00682     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
00683     {
00684       /* Disable the QSPI Transfer Error and Status Match Interrupts */
00685       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
00686
00687       /* Change state of QSPI */
00688       hqspi->State = HAL_QSPI_STATE_READY;
00689     }
00690
00691     /* Status match callback */
00692 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00693     hqspi->StatusMatchCallback(hqspi);
00694 #else
00695     HAL_QSPI_StatusMatchCallback(hqspi);
00696 #endif
00697   }
00698
00699   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00700   else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
00701   {
00702     /* Clear interrupt */
00703     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
00704
00705     /* Disable all the QSPI Interrupts */
00706     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00707
00708     /* Set error code */
00709     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00710
00711     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00712     {
00713       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00714       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00715
00716       /* Disable the DMA channel */
00717       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
00718       if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
00719       {
00720         /* Set error code to DMA */
00721         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
00722
00723         /* Change state of QSPI */
00724         hqspi->State = HAL_QSPI_STATE_READY;
00725
00726         /* Error callback */
00727 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00728         hqspi->ErrorCallback(hqspi);
00729 #else
00730         HAL_QSPI_ErrorCallback(hqspi);
00731 #endif
00732       }
00733     }
00734     else
00735     {
00736       /* Change state of QSPI */
00737       hqspi->State = HAL_QSPI_STATE_READY;
00738
00739       /* Error callback */
00740 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00741       hqspi->ErrorCallback(hqspi);
00742 #else
00743       HAL_QSPI_ErrorCallback(hqspi);
00744 #endif
00745     }
00746   }
00747
00748   /* QSPI Timeout interrupt occurred -----------------------------------------*/
00749   else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
00750   {
00751     /* Clear interrupt */
00752     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
00753
00754     /* Timeout callback */
00755 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00756     hqspi->TimeOutCallback(hqspi);
00757 #else
00758     HAL_QSPI_TimeOutCallback(hqspi);
00759 #endif
00760   }
00761
00762    else
00763   {
00764    /* Nothing to do */
00765   }
00766 }
00767
00768 /**
00769   * @brief Set the command configuration.
00770   * @param hqspi QSPI handle
00771   * @param cmd : structure that contains the command configuration information
00772   * @param Timeout Timeout duration
00773   * @note   This function is used only in Indirect Read or Write Modes
00774   * @retval HAL status
00775   */
00776 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00777 {
00778   HAL_StatusTypeDef status;
00779   uint32_t tickstart = HAL_GetTick();
00780
00781   /* Check the parameters */
00782   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00783   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00784   {
00785     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00786   }
00787
00788   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00789   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00790   {
00791     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00792   }
00793
00794   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00795   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00796   {
00797     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00798   }
00799
00800   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00801   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00802
00803   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00804   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00805   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00806
00807   /* Process locked */
00808   __HAL_LOCK(hqspi);
00809
00810   if(hqspi->State == HAL_QSPI_STATE_READY)
00811   {
00812     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00813
00814     /* Update QSPI state */
00815     hqspi->State = HAL_QSPI_STATE_BUSY;
00816
00817     /* Wait till BUSY flag reset */
00818     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00819
00820     if (status == HAL_OK)
00821     {
00822       /* Call the configuration function */
00823       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00824
00825       if (cmd->DataMode == QSPI_DATA_NONE)
00826       {
00827         /* When there is no data phase, the transfer start as soon as the configuration is done
00828         so wait until TC flag is set to go back in idle state */
00829         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00830
00831         if (status == HAL_OK)
00832         {
00833           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00834
00835           /* Update QSPI state */
00836           hqspi->State = HAL_QSPI_STATE_READY;
00837         }
00838       }
00839       else
00840       {
00841         /* Update QSPI state */
00842         hqspi->State = HAL_QSPI_STATE_READY;
00843       }
00844     }
00845   }
00846   else
00847   {
00848     status = HAL_BUSY;
00849   }
00850
00851   /* Process unlocked */
00852   __HAL_UNLOCK(hqspi);
00853
00854   /* Return function status */
00855   return status;
00856 }
00857
00858 /**
00859   * @brief Set the command configuration in interrupt mode.
00860   * @param hqspi QSPI handle
00861   * @param cmd structure that contains the command configuration information
00862   * @note   This function is used only in Indirect Read or Write Modes
00863   * @retval HAL status
00864   */
00865 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00866 {
00867   HAL_StatusTypeDef status;
00868   uint32_t tickstart = HAL_GetTick();
00869
00870   /* Check the parameters */
00871   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00872   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00873   {
00874     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00875   }
00876
00877   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00878   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00879   {
00880     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00881   }
00882
00883   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00884   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00885   {
00886     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00887   }
00888
00889   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00890   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00891
00892   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00893   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00894   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00895
00896   /* Process locked */
00897   __HAL_LOCK(hqspi);
00898
00899   if(hqspi->State == HAL_QSPI_STATE_READY)
00900   {
00901     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00902
00903     /* Update QSPI state */
00904     hqspi->State = HAL_QSPI_STATE_BUSY;
00905
00906     /* Wait till BUSY flag reset */
00907     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00908
00909     if (status == HAL_OK)
00910     {
00911       if (cmd->DataMode == QSPI_DATA_NONE)
00912       {
00913         /* Clear interrupt */
00914         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
00915       }
00916
00917       /* Call the configuration function */
00918       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00919
00920       if (cmd->DataMode == QSPI_DATA_NONE)
00921       {
00922         /* When there is no data phase, the transfer start as soon as the configuration is done
00923         so activate TC and TE interrupts */
00924         /* Process unlocked */
00925         __HAL_UNLOCK(hqspi);
00926
00927         /* Enable the QSPI Transfer Error Interrupt */
00928         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00929       }
00930       else
00931       {
00932         /* Update QSPI state */
00933         hqspi->State = HAL_QSPI_STATE_READY;
00934
00935         /* Process unlocked */
00936         __HAL_UNLOCK(hqspi);
00937       }
00938     }
00939     else
00940     {
00941       /* Process unlocked */
00942       __HAL_UNLOCK(hqspi);
00943     }
00944   }
00945   else
00946   {
00947     status = HAL_BUSY;
00948
00949     /* Process unlocked */
00950     __HAL_UNLOCK(hqspi);
00951   }
00952
00953   /* Return function status */
00954   return status;
00955 }
00956
00957 /**
00958   * @brief Transmit an amount of data in blocking mode.
00959   * @param hqspi QSPI handle
00960   * @param pData pointer to data buffer
00961   * @param Timeout Timeout duration
00962   * @note   This function is used only in Indirect Write Mode
00963   * @retval HAL status
00964   */
00965 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00966 {
00967   HAL_StatusTypeDef status = HAL_OK;
00968   uint32_t tickstart = HAL_GetTick();
00969   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00970
00971   /* Process locked */
00972   __HAL_LOCK(hqspi);
00973
00974   if(hqspi->State == HAL_QSPI_STATE_READY)
00975   {
00976     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00977
00978     if(pData != NULL )
00979     {
00980       /* Update state */
00981       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00982
00983       /* Configure counters and size of the handle */
00984       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00985       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00986       hqspi->pTxBuffPtr = pData;
00987
00988       /* Configure QSPI: CCR register with functional as indirect write */
00989       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00990
00991       while(hqspi->TxXferCount > 0U)
00992       {
00993         /* Wait until FT flag is set to send data */
00994         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
00995
00996         if (status != HAL_OK)
00997         {
00998           break;
00999         }
01000
01001         *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
01002         hqspi->pTxBuffPtr++;
01003         hqspi->TxXferCount--;
01004       }
01005
01006       if (status == HAL_OK)
01007       {
01008         /* Wait until TC flag is set to go back in idle state */
01009         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01010
01011         if (status == HAL_OK)
01012         {
01013           /* Clear Transfer Complete bit */
01014           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01015
01016         }
01017       }
01018
01019       /* Update QSPI state */
01020       hqspi->State = HAL_QSPI_STATE_READY;
01021     }
01022     else
01023     {
01024       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01025       status = HAL_ERROR;
01026     }
01027   }
01028   else
01029   {
01030     status = HAL_BUSY;
01031   }
01032
01033   /* Process unlocked */
01034   __HAL_UNLOCK(hqspi);
01035
01036   return status;
01037 }
01038
01039
01040 /**
01041   * @brief Receive an amount of data in blocking mode.
01042   * @param hqspi QSPI handle
01043   * @param pData pointer to data buffer
01044   * @param Timeout Timeout duration
01045   * @note   This function is used only in Indirect Read Mode
01046   * @retval HAL status
01047   */
01048 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
01049 {
01050   HAL_StatusTypeDef status = HAL_OK;
01051   uint32_t tickstart = HAL_GetTick();
01052   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01053   __IO uint32_t *data_reg = &hqspi->Instance->DR;
01054
01055   /* Process locked */
01056   __HAL_LOCK(hqspi);
01057
01058   if(hqspi->State == HAL_QSPI_STATE_READY)
01059   {
01060     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01061
01062     if(pData != NULL )
01063     {
01064       /* Update state */
01065       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01066
01067       /* Configure counters and size of the handle */
01068       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01069       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01070       hqspi->pRxBuffPtr = pData;
01071
01072       /* Configure QSPI: CCR register with functional as indirect read */
01073       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01074
01075       /* Start the transfer by re-writing the address in AR register */
01076       WRITE_REG(hqspi->Instance->AR, addr_reg);
01077
01078       while(hqspi->RxXferCount > 0U)
01079       {
01080         /* Wait until FT or TC flag is set to read received data */
01081         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
01082
01083         if  (status != HAL_OK)
01084         {
01085           break;
01086         }
01087
01088         *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
01089         hqspi->pRxBuffPtr++;
01090         hqspi->RxXferCount--;
01091       }
01092
01093       if (status == HAL_OK)
01094       {
01095         /* Wait until TC flag is set to go back in idle state */
01096         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01097
01098         if  (status == HAL_OK)
01099         {
01100           /* Clear Transfer Complete bit */
01101           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01102
01103         }
01104       }
01105
01106       /* Update QSPI state */
01107       hqspi->State = HAL_QSPI_STATE_READY;
01108     }
01109     else
01110     {
01111       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01112       status = HAL_ERROR;
01113     }
01114   }
01115   else
01116   {
01117     status = HAL_BUSY;
01118   }
01119
01120   /* Process unlocked */
01121   __HAL_UNLOCK(hqspi);
01122
01123   return status;
01124 }
01125
01126 /**
01127   * @brief  Send an amount of data in non-blocking mode with interrupt.
01128   * @param  hqspi QSPI handle
01129   * @param  pData pointer to data buffer
01130   * @note   This function is used only in Indirect Write Mode
01131   * @retval HAL status
01132   */
01133 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01134 {
01135   HAL_StatusTypeDef status = HAL_OK;
01136
01137   /* Process locked */
01138   __HAL_LOCK(hqspi);
01139
01140   if(hqspi->State == HAL_QSPI_STATE_READY)
01141   {
01142     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01143
01144     if(pData != NULL )
01145     {
01146       /* Update state */
01147       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01148
01149       /* Configure counters and size of the handle */
01150       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01151       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01152       hqspi->pTxBuffPtr = pData;
01153
01154       /* Clear interrupt */
01155       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01156
01157       /* Configure QSPI: CCR register with functional as indirect write */
01158       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01159
01160       /* Process unlocked */
01161       __HAL_UNLOCK(hqspi);
01162
01163       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01164       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01165     }
01166     else
01167     {
01168       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01169       status = HAL_ERROR;
01170
01171       /* Process unlocked */
01172       __HAL_UNLOCK(hqspi);
01173     }
01174   }
01175   else
01176   {
01177     status = HAL_BUSY;
01178
01179     /* Process unlocked */
01180     __HAL_UNLOCK(hqspi);
01181   }
01182
01183   return status;
01184 }
01185
01186 /**
01187   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01188   * @param  hqspi QSPI handle
01189   * @param  pData pointer to data buffer
01190   * @note   This function is used only in Indirect Read Mode
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01194 {
01195   HAL_StatusTypeDef status = HAL_OK;
01196   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01197
01198   /* Process locked */
01199   __HAL_LOCK(hqspi);
01200
01201   if(hqspi->State == HAL_QSPI_STATE_READY)
01202   {
01203     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01204
01205     if(pData != NULL )
01206     {
01207       /* Update state */
01208       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01209
01210       /* Configure counters and size of the handle */
01211       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01212       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01213       hqspi->pRxBuffPtr = pData;
01214
01215       /* Clear interrupt */
01216       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01217
01218       /* Configure QSPI: CCR register with functional as indirect read */
01219       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01220
01221       /* Start the transfer by re-writing the address in AR register */
01222       WRITE_REG(hqspi->Instance->AR, addr_reg);
01223
01224       /* Process unlocked */
01225       __HAL_UNLOCK(hqspi);
01226
01227       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01228       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01229     }
01230     else
01231     {
01232       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01233       status = HAL_ERROR;
01234
01235       /* Process unlocked */
01236       __HAL_UNLOCK(hqspi);
01237     }
01238   }
01239   else
01240   {
01241     status = HAL_BUSY;
01242
01243     /* Process unlocked */
01244     __HAL_UNLOCK(hqspi);
01245   }
01246
01247   return status;
01248 }
01249
01250 /**
01251   * @brief  Send an amount of data in non-blocking mode with DMA.
01252   * @param  hqspi QSPI handle
01253   * @param  pData pointer to data buffer
01254   * @note   This function is used only in Indirect Write Mode
01255   * @note   If DMA peripheral access is configured as halfword, the number
01256   *         of data and the fifo threshold should be aligned on halfword
01257   * @note   If DMA peripheral access is configured as word, the number
01258   *         of data and the fifo threshold should be aligned on word
01259   * @retval HAL status
01260   */
01261 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01262 {
01263   HAL_StatusTypeDef status = HAL_OK;
01264   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
01265
01266   /* Process locked */
01267   __HAL_LOCK(hqspi);
01268
01269   if(hqspi->State == HAL_QSPI_STATE_READY)
01270   {
01271     /* Clear the error code */
01272     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01273
01274     if(pData != NULL )
01275     {
01276       /* Configure counters of the handle */
01277       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01278       {
01279         hqspi->TxXferCount = data_size;
01280       }
01281       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01282       {
01283         if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
01284         {
01285           /* The number of data or the fifo threshold is not aligned on halfword
01286           => no transfer possible with DMA peripheral access configured as halfword */
01287           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01288           status = HAL_ERROR;
01289
01290           /* Process unlocked */
01291           __HAL_UNLOCK(hqspi);
01292         }
01293         else
01294         {
01295           hqspi->TxXferCount = (data_size >> 1U);
01296         }
01297       }
01298       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01299       {
01300         if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
01301         {
01302           /* The number of data or the fifo threshold is not aligned on word
01303           => no transfer possible with DMA peripheral access configured as word */
01304           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01305           status = HAL_ERROR;
01306
01307           /* Process unlocked */
01308           __HAL_UNLOCK(hqspi);
01309         }
01310         else
01311         {
01312           hqspi->TxXferCount = (data_size >> 2U);
01313         }
01314       }
01315       else
01316       {
01317         /* Nothing to do */
01318       }
01319
01320       if (status == HAL_OK)
01321       {
01322         /* Update state */
01323         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01324
01325         /* Clear interrupt */
01326         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01327
01328         /* Configure size and pointer of the handle */
01329         hqspi->TxXferSize = hqspi->TxXferCount;
01330         hqspi->pTxBuffPtr = pData;
01331
01332         /* Configure QSPI: CCR register with functional mode as indirect write */
01333         MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01334
01335         /* Set the QSPI DMA transfer complete callback */
01336         hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
01337
01338         /* Set the QSPI DMA Half transfer complete callback */
01339         hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
01340
01341         /* Set the DMA error callback */
01342         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01343
01344         /* Clear the DMA abort callback */
01345         hqspi->hdma->XferAbortCallback = NULL;
01346
01347         /* Configure the direction of the DMA */
01348         hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
01349         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01350
01351         /* Enable the QSPI transmit DMA Channel */
01352         if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
01353         {
01354           /* Process unlocked */
01355           __HAL_UNLOCK(hqspi);
01356
01357           /* Enable the QSPI transfer error Interrupt */
01358           __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01359
01360           /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01361           SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01362         }
01363         else
01364         {
01365           status = HAL_ERROR;
01366           hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01367           hqspi->State = HAL_QSPI_STATE_READY;
01368
01369           /* Process unlocked */
01370           __HAL_UNLOCK(hqspi);
01371         }
01372      }
01373     }
01374     else
01375     {
01376       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01377       status = HAL_ERROR;
01378
01379       /* Process unlocked */
01380       __HAL_UNLOCK(hqspi);
01381     }
01382   }
01383   else
01384   {
01385     status = HAL_BUSY;
01386
01387     /* Process unlocked */
01388     __HAL_UNLOCK(hqspi);
01389   }
01390
01391   return status;
01392 }
01393
01394 /**
01395   * @brief  Receive an amount of data in non-blocking mode with DMA.
01396   * @param  hqspi QSPI handle
01397   * @param  pData pointer to data buffer.
01398   * @note   This function is used only in Indirect Read Mode
01399   * @note   If DMA peripheral access is configured as halfword, the number
01400   *         of data and the fifo threshold should be aligned on halfword
01401   * @note   If DMA peripheral access is configured as word, the number
01402   *         of data and the fifo threshold should be aligned on word
01403   * @retval HAL status
01404   */
01405 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01406 {
01407   HAL_StatusTypeDef status = HAL_OK;
01408   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01409   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
01410
01411   /* Process locked */
01412   __HAL_LOCK(hqspi);
01413
01414   if(hqspi->State == HAL_QSPI_STATE_READY)
01415   {
01416     /* Clear the error code */
01417     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01418
01419     if(pData != NULL )
01420     {
01421       /* Configure counters of the handle */
01422       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01423       {
01424         hqspi->RxXferCount = data_size;
01425       }
01426       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01427       {
01428         if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
01429         {
01430           /* The number of data or the fifo threshold is not aligned on halfword
01431              => no transfer possible with DMA peripheral access configured as halfword */
01432           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01433           status = HAL_ERROR;
01434
01435           /* Process unlocked */
01436           __HAL_UNLOCK(hqspi);
01437         }
01438         else
01439         {
01440           hqspi->RxXferCount = (data_size >> 1U);
01441         }
01442       }
01443       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01444       {
01445         if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
01446         {
01447           /* The number of data or the fifo threshold is not aligned on word
01448              => no transfer possible with DMA peripheral access configured as word */
01449           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01450           status = HAL_ERROR;
01451
01452           /* Process unlocked */
01453           __HAL_UNLOCK(hqspi);
01454         }
01455         else
01456         {
01457           hqspi->RxXferCount = (data_size >> 2U);
01458         }
01459       }
01460       else
01461       {
01462         /* Nothing to do */
01463       }
01464
01465       if (status == HAL_OK)
01466       {
01467         /* Update state */
01468         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01469
01470         /* Clear interrupt */
01471         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01472
01473         /* Configure size and pointer of the handle */
01474         hqspi->RxXferSize = hqspi->RxXferCount;
01475         hqspi->pRxBuffPtr = pData;
01476
01477         /* Set the QSPI DMA transfer complete callback */
01478         hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
01479
01480         /* Set the QSPI DMA Half transfer complete callback */
01481         hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
01482
01483         /* Set the DMA error callback */
01484         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01485
01486         /* Clear the DMA abort callback */
01487         hqspi->hdma->XferAbortCallback = NULL;
01488
01489         /* Configure the direction of the DMA */
01490         hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
01491         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01492
01493         /* Enable the DMA Channel */
01494         if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
01495         {
01496           /* Configure QSPI: CCR register with functional as indirect read */
01497           MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01498
01499           /* Start the transfer by re-writing the address in AR register */
01500           WRITE_REG(hqspi->Instance->AR, addr_reg);
01501
01502           /* Process unlocked */
01503           __HAL_UNLOCK(hqspi);
01504
01505           /* Enable the QSPI transfer error Interrupt */
01506           __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01507
01508           /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01509           SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01510         }
01511         else
01512         {
01513           status = HAL_ERROR;
01514           hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01515           hqspi->State = HAL_QSPI_STATE_READY;
01516
01517           /* Process unlocked */
01518           __HAL_UNLOCK(hqspi);
01519         }
01520       }
01521     }
01522     else
01523     {
01524       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01525       status = HAL_ERROR;
01526
01527       /* Process unlocked */
01528       __HAL_UNLOCK(hqspi);
01529     }
01530   }
01531   else
01532   {
01533     status = HAL_BUSY;
01534
01535     /* Process unlocked */
01536     __HAL_UNLOCK(hqspi);
01537   }
01538
01539   return status;
01540 }
01541
01542 /**
01543   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01544   * @param  hqspi QSPI handle
01545   * @param  cmd structure that contains the command configuration information.
01546   * @param  cfg structure that contains the polling configuration information.
01547   * @param  Timeout Timeout duration
01548   * @note   This function is used only in Automatic Polling Mode
01549   * @retval HAL status
01550   */
01551 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01552 {
01553   HAL_StatusTypeDef status;
01554   uint32_t tickstart = HAL_GetTick();
01555
01556   /* Check the parameters */
01557   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01558   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01559   {
01560     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01561   }
01562
01563   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01564   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01565   {
01566     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01567   }
01568
01569   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01570   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01571   {
01572     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01573   }
01574
01575   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01576   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01577
01578   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01579   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01580   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01581
01582   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01583   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01584   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01585
01586   /* Process locked */
01587   __HAL_LOCK(hqspi);
01588
01589   if(hqspi->State == HAL_QSPI_STATE_READY)
01590   {
01591     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01592
01593     /* Update state */
01594     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01595
01596     /* Wait till BUSY flag reset */
01597     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01598
01599     if (status == HAL_OK)
01600     {
01601       /* Configure QSPI: PSMAR register with the status match value */
01602       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01603
01604       /* Configure QSPI: PSMKR register with the status mask value */
01605       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01606
01607       /* Configure QSPI: PIR register with the interval value */
01608       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01609
01610       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01611       (otherwise there will be an infinite loop in blocking mode) */
01612       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01613                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01614
01615       /* Call the configuration function */
01616       cmd->NbData = cfg->StatusBytesSize;
01617       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01618
01619       /* Wait until SM flag is set to go back in idle state */
01620       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
01621
01622       if (status == HAL_OK)
01623       {
01624         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01625
01626         /* Update state */
01627         hqspi->State = HAL_QSPI_STATE_READY;
01628       }
01629     }
01630   }
01631   else
01632   {
01633     status = HAL_BUSY;
01634   }
01635
01636   /* Process unlocked */
01637   __HAL_UNLOCK(hqspi);
01638
01639   /* Return function status */
01640   return status;
01641 }
01642
01643 /**
01644   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01645   * @param  hqspi QSPI handle
01646   * @param  cmd structure that contains the command configuration information.
01647   * @param  cfg structure that contains the polling configuration information.
01648   * @note   This function is used only in Automatic Polling Mode
01649   * @retval HAL status
01650   */
01651 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01652 {
01653   HAL_StatusTypeDef status;
01654   uint32_t tickstart = HAL_GetTick();
01655
01656   /* Check the parameters */
01657   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01658   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01659   {
01660     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01661   }
01662
01663   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01664   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01665   {
01666     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01667   }
01668
01669   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01670   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01671   {
01672     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01673   }
01674
01675   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01676   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01677
01678   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01679   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01680   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01681
01682   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01683   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01684   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01685   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01686
01687   /* Process locked */
01688   __HAL_LOCK(hqspi);
01689
01690   if(hqspi->State == HAL_QSPI_STATE_READY)
01691   {
01692     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01693
01694     /* Update state */
01695     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01696
01697     /* Wait till BUSY flag reset */
01698     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01699
01700     if (status == HAL_OK)
01701     {
01702       /* Configure QSPI: PSMAR register with the status match value */
01703       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01704
01705       /* Configure QSPI: PSMKR register with the status mask value */
01706       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01707
01708       /* Configure QSPI: PIR register with the interval value */
01709       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01710
01711       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01712       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01713                (cfg->MatchMode | cfg->AutomaticStop));
01714
01715       /* Clear interrupt */
01716       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01717
01718       /* Call the configuration function */
01719       cmd->NbData = cfg->StatusBytesSize;
01720       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01721
01722       /* Process unlocked */
01723       __HAL_UNLOCK(hqspi);
01724
01725       /* Enable the QSPI Transfer Error and status match Interrupt */
01726       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01727
01728     }
01729     else
01730     {
01731       /* Process unlocked */
01732       __HAL_UNLOCK(hqspi);
01733     }
01734   }
01735   else
01736   {
01737     status = HAL_BUSY;
01738
01739     /* Process unlocked */
01740     __HAL_UNLOCK(hqspi);
01741   }
01742
01743   /* Return function status */
01744   return status;
01745 }
01746
01747 /**
01748   * @brief  Configure the Memory Mapped mode.
01749   * @param  hqspi QSPI handle
01750   * @param  cmd structure that contains the command configuration information.
01751   * @param  cfg structure that contains the memory mapped configuration information.
01752   * @note   This function is used only in Memory mapped Mode
01753   * @retval HAL status
01754   */
01755 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01756 {
01757   HAL_StatusTypeDef status;
01758   uint32_t tickstart = HAL_GetTick();
01759
01760   /* Check the parameters */
01761   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01762   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01763   {
01764   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01765   }
01766
01767   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01768   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01769   {
01770     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01771   }
01772
01773   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01774   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01775   {
01776     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01777   }
01778
01779   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01780   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01781
01782   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01783   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01784   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01785
01786   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01787
01788   /* Process locked */
01789   __HAL_LOCK(hqspi);
01790
01791   if(hqspi->State == HAL_QSPI_STATE_READY)
01792   {
01793     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01794
01795     /* Update state */
01796     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01797
01798     /* Wait till BUSY flag reset */
01799     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01800
01801     if (status == HAL_OK)
01802     {
01803       /* Configure QSPI: CR register with timeout counter enable */
01804     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01805
01806     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01807       {
01808         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01809
01810         /* Configure QSPI: LPTR register with the low-power timeout value */
01811         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01812
01813         /* Clear interrupt */
01814         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
01815
01816         /* Enable the QSPI TimeOut Interrupt */
01817         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01818       }
01819
01820       /* Call the configuration function */
01821       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01822     }
01823   }
01824   else
01825   {
01826     status = HAL_BUSY;
01827   }
01828
01829   /* Process unlocked */
01830   __HAL_UNLOCK(hqspi);
01831
01832   /* Return function status */
01833   return status;
01834 }
01835
01836 /**
01837   * @brief  Transfer Error callback.
01838   * @param  hqspi QSPI handle
01839   * @retval None
01840   */
01841 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01842 {
01843   /* Prevent unused argument(s) compilation warning */
01844   UNUSED(hqspi);
01845
01846   /* NOTE : This function should not be modified, when the callback is needed,
01847             the HAL_QSPI_ErrorCallback could be implemented in the user file
01848    */
01849 }
01850
01851 /**
01852   * @brief  Abort completed callback.
01853   * @param  hqspi QSPI handle
01854   * @retval None
01855   */
01856 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
01857 {
01858   /* Prevent unused argument(s) compilation warning */
01859   UNUSED(hqspi);
01860
01861   /* NOTE: This function should not be modified, when the callback is needed,
01862            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
01863    */
01864 }
01865
01866 /**
01867   * @brief  Command completed callback.
01868   * @param  hqspi QSPI handle
01869   * @retval None
01870   */
01871 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01872 {
01873   /* Prevent unused argument(s) compilation warning */
01874   UNUSED(hqspi);
01875
01876   /* NOTE: This function should not be modified, when the callback is needed,
01877            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01878    */
01879 }
01880
01881 /**
01882   * @brief  Rx Transfer completed callback.
01883   * @param  hqspi QSPI handle
01884   * @retval None
01885   */
01886 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01887 {
01888   /* Prevent unused argument(s) compilation warning */
01889   UNUSED(hqspi);
01890
01891   /* NOTE: This function should not be modified, when the callback is needed,
01892            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01893    */
01894 }
01895
01896 /**
01897   * @brief  Tx Transfer completed callback.
01898   * @param  hqspi QSPI handle
01899   * @retval None
01900   */
01901 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01902 {
01903   /* Prevent unused argument(s) compilation warning */
01904   UNUSED(hqspi);
01905
01906   /* NOTE: This function should not be modified, when the callback is needed,
01907            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01908    */
01909 }
01910
01911 /**
01912   * @brief  Rx Half Transfer completed callback.
01913   * @param  hqspi QSPI handle
01914   * @retval None
01915   */
01916 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01917 {
01918   /* Prevent unused argument(s) compilation warning */
01919   UNUSED(hqspi);
01920
01921   /* NOTE: This function should not be modified, when the callback is needed,
01922            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01923    */
01924 }
01925
01926 /**
01927   * @brief  Tx Half Transfer completed callback.
01928   * @param  hqspi QSPI handle
01929   * @retval None
01930   */
01931 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01932 {
01933   /* Prevent unused argument(s) compilation warning */
01934   UNUSED(hqspi);
01935
01936   /* NOTE: This function should not be modified, when the callback is needed,
01937            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01938    */
01939 }
01940
01941 /**
01942   * @brief  FIFO Threshold callback.
01943   * @param  hqspi QSPI handle
01944   * @retval None
01945   */
01946 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01947 {
01948   /* Prevent unused argument(s) compilation warning */
01949   UNUSED(hqspi);
01950
01951   /* NOTE : This function should not be modified, when the callback is needed,
01952             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01953    */
01954 }
01955
01956 /**
01957   * @brief  Status Match callback.
01958   * @param  hqspi QSPI handle
01959   * @retval None
01960   */
01961 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01962 {
01963   /* Prevent unused argument(s) compilation warning */
01964   UNUSED(hqspi);
01965
01966   /* NOTE : This function should not be modified, when the callback is needed,
01967             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01968    */
01969 }
01970
01971 /**
01972   * @brief  Timeout callback.
01973   * @param  hqspi QSPI handle
01974   * @retval None
01975   */
01976 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01977 {
01978   /* Prevent unused argument(s) compilation warning */
01979   UNUSED(hqspi);
01980
01981   /* NOTE : This function should not be modified, when the callback is needed,
01982             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01983    */
01984 }
01985 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
01986 /**
01987   * @brief  Register a User QSPI Callback
01988   *         To be used to override the weak predefined callback
01989   * @param hqspi QSPI handle
01990   * @param CallbackId ID of the callback to be registered
01991   *        This parameter can be one of the following values:
01992   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
01993   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
01994   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
01995   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
01996   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
01997   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
01998   *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
01999   *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
02000   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
02001   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
02002   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
02003   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
02004   * @param pCallback pointer to the Callback function
02005   * @retval status
02006   */
02007 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
02008 {
02009   HAL_StatusTypeDef status = HAL_OK;
02010
02011   if(pCallback == NULL)
02012   {
02013     /* Update the error code */
02014     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02015     return HAL_ERROR;
02016   }
02017
02018   /* Process locked */
02019   __HAL_LOCK(hqspi);
02020
02021   if(hqspi->State == HAL_QSPI_STATE_READY)
02022   {
02023     switch (CallbackId)
02024     {
02025     case  HAL_QSPI_ERROR_CB_ID :
02026       hqspi->ErrorCallback = pCallback;
02027       break;
02028     case HAL_QSPI_ABORT_CB_ID :
02029       hqspi->AbortCpltCallback = pCallback;
02030       break;
02031     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
02032       hqspi->FifoThresholdCallback = pCallback;
02033       break;
02034     case HAL_QSPI_CMD_CPLT_CB_ID :
02035       hqspi->CmdCpltCallback = pCallback;
02036       break;
02037     case HAL_QSPI_RX_CPLT_CB_ID :
02038       hqspi->RxCpltCallback = pCallback;
02039       break;
02040     case HAL_QSPI_TX_CPLT_CB_ID :
02041       hqspi->TxCpltCallback = pCallback;
02042       break;
02043     case HAL_QSPI_RX_HALF_CPLT_CB_ID :
02044       hqspi->RxHalfCpltCallback = pCallback;
02045       break;
02046     case HAL_QSPI_TX_HALF_CPLT_CB_ID :
02047       hqspi->TxHalfCpltCallback = pCallback;
02048       break;
02049     case HAL_QSPI_STATUS_MATCH_CB_ID :
02050       hqspi->StatusMatchCallback = pCallback;
02051       break;
02052     case HAL_QSPI_TIMEOUT_CB_ID :
02053       hqspi->TimeOutCallback = pCallback;
02054       break;
02055     case HAL_QSPI_MSP_INIT_CB_ID :
02056       hqspi->MspInitCallback = pCallback;
02057       break;
02058     case HAL_QSPI_MSP_DEINIT_CB_ID :
02059       hqspi->MspDeInitCallback = pCallback;
02060       break;
02061     default :
02062       /* Update the error code */
02063       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02064       /* update return status */
02065       status =  HAL_ERROR;
02066       break;
02067     }
02068   }
02069   else if (hqspi->State == HAL_QSPI_STATE_RESET)
02070   {
02071     switch (CallbackId)
02072     {
02073     case HAL_QSPI_MSP_INIT_CB_ID :
02074       hqspi->MspInitCallback = pCallback;
02075       break;
02076     case HAL_QSPI_MSP_DEINIT_CB_ID :
02077       hqspi->MspDeInitCallback = pCallback;
02078       break;
02079     default :
02080       /* Update the error code */
02081       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02082       /* update return status */
02083       status =  HAL_ERROR;
02084       break;
02085     }
02086   }
02087   else
02088   {
02089     /* Update the error code */
02090     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02091     /* update return status */
02092     status =  HAL_ERROR;
02093   }
02094
02095   /* Release Lock */
02096   __HAL_UNLOCK(hqspi);
02097   return status;
02098 }
02099
02100 /**
02101   * @brief  Unregister a User QSPI Callback
02102   *         QSPI Callback is redirected to the weak predefined callback
02103   * @param hqspi QSPI handle
02104   * @param CallbackId ID of the callback to be unregistered
02105   *        This parameter can be one of the following values:
02106   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
02107   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
02108   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
02109   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
02110   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
02111   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
02112   *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
02113   *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
02114   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
02115   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
02116   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
02117   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
02118   * @retval status
02119   */
02120 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
02121 {
02122   HAL_StatusTypeDef status = HAL_OK;
02123
02124   /* Process locked */
02125   __HAL_LOCK(hqspi);
02126
02127   if(hqspi->State == HAL_QSPI_STATE_READY)
02128   {
02129     switch (CallbackId)
02130     {
02131     case  HAL_QSPI_ERROR_CB_ID :
02132       hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
02133       break;
02134     case HAL_QSPI_ABORT_CB_ID :
02135       hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
02136       break;
02137     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
02138       hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
02139       break;
02140     case HAL_QSPI_CMD_CPLT_CB_ID :
02141       hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
02142       break;
02143     case HAL_QSPI_RX_CPLT_CB_ID :
02144       hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
02145       break;
02146     case HAL_QSPI_TX_CPLT_CB_ID :
02147       hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
02148       break;
02149     case HAL_QSPI_RX_HALF_CPLT_CB_ID :
02150       hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
02151       break;
02152     case HAL_QSPI_TX_HALF_CPLT_CB_ID :
02153       hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
02154       break;
02155     case HAL_QSPI_STATUS_MATCH_CB_ID :
02156       hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
02157       break;
02158     case HAL_QSPI_TIMEOUT_CB_ID :
02159       hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
02160       break;
02161     case HAL_QSPI_MSP_INIT_CB_ID :
02162       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02163       break;
02164     case HAL_QSPI_MSP_DEINIT_CB_ID :
02165       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02166       break;
02167     default :
02168       /* Update the error code */
02169       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02170       /* update return status */
02171       status =  HAL_ERROR;
02172       break;
02173     }
02174   }
02175   else if (hqspi->State == HAL_QSPI_STATE_RESET)
02176   {
02177     switch (CallbackId)
02178     {
02179     case HAL_QSPI_MSP_INIT_CB_ID :
02180       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02181       break;
02182     case HAL_QSPI_MSP_DEINIT_CB_ID :
02183       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02184       break;
02185     default :
02186       /* Update the error code */
02187       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02188       /* update return status */
02189       status =  HAL_ERROR;
02190       break;
02191     }
02192   }
02193   else
02194   {
02195     /* Update the error code */
02196     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02197     /* update return status */
02198     status =  HAL_ERROR;
02199   }
02200
02201   /* Release Lock */
02202   __HAL_UNLOCK(hqspi);
02203   return status;
02204 }
02205 #endif
02206
02207 /**
02208   * @}
02209   */
02210
02211 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
02212   *  @brief   QSPI control and State functions
02213   *
02214 @verbatim
02215  ===============================================================================
02216                   ##### Peripheral Control and State functions #####
02217  ===============================================================================
02218     [..]
02219     This subsection provides a set of functions allowing to :
02220       (+) Check in run-time the state of the driver.
02221       (+) Check the error code set during last operation.
02222       (+) Abort any operation.
02223
02224
02225 @endverbatim
02226   * @{
02227   */
02228
02229 /**
02230   * @brief  Return the QSPI handle state.
02231   * @param  hqspi QSPI handle
02232   * @retval HAL state
02233   */
02234 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
02235 {
02236   /* Return QSPI handle state */
02237   return hqspi->State;
02238 }
02239
02240 /**
02241 * @brief  Return the QSPI error code.
02242 * @param  hqspi QSPI handle
02243 * @retval QSPI Error Code
02244 */
02245 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
02246 {
02247   return hqspi->ErrorCode;
02248 }
02249
02250 /**
02251 * @brief  Abort the current transmission.
02252 * @param  hqspi QSPI handle
02253 * @retval HAL status
02254 */
02255 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
02256 {
02257   HAL_StatusTypeDef status = HAL_OK;
02258   uint32_t tickstart = HAL_GetTick();
02259
02260   /* Check if the state is in one of the busy states */
02261   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02262   {
02263     /* Process unlocked */
02264     __HAL_UNLOCK(hqspi);
02265
02266     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
02267     {
02268       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02269       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02270
02271       /* Abort DMA channel */
02272       status = HAL_DMA_Abort(hqspi->hdma);
02273       if(status != HAL_OK)
02274       {
02275         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
02276       }
02277     }
02278
02279     if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
02280     {
02281       /* Configure QSPI: CR register with Abort request */
02282       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02283
02284       /* Wait until TC flag is set to go back in idle state */
02285       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
02286
02287       if (status == HAL_OK)
02288       {
02289         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02290
02291         /* Wait until BUSY flag is reset */
02292         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
02293       }
02294
02295       if (status == HAL_OK)
02296       {
02297         /* Reset functional mode configuration to indirect write mode by default */
02298         CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
02299
02300         /* Update state */
02301         hqspi->State = HAL_QSPI_STATE_READY;
02302       }
02303     }
02304     else
02305     {
02306       /* Update state */
02307       hqspi->State = HAL_QSPI_STATE_READY;
02308     }
02309   }
02310
02311   return status;
02312 }
02313
02314 /**
02315 * @brief  Abort the current transmission (non-blocking function)
02316 * @param  hqspi QSPI handle
02317 * @retval HAL status
02318 */
02319 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
02320 {
02321   HAL_StatusTypeDef status = HAL_OK;
02322
02323   /* Check if the state is in one of the busy states */
02324   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02325   {
02326     /* Process unlocked */
02327     __HAL_UNLOCK(hqspi);
02328
02329     /* Update QSPI state */
02330     hqspi->State = HAL_QSPI_STATE_ABORT;
02331
02332     /* Disable all interrupts */
02333     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
02334
02335     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
02336     {
02337       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02338       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02339
02340       /* Abort DMA channel */
02341       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
02342       if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
02343       {
02344         /* Change state of QSPI */
02345         hqspi->State = HAL_QSPI_STATE_READY;
02346
02347         /* Abort Complete callback */
02348 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02349         hqspi->AbortCpltCallback(hqspi);
02350 #else
02351         HAL_QSPI_AbortCpltCallback(hqspi);
02352 #endif
02353       }
02354     }
02355     else
02356     {
02357       if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
02358       {
02359         /* Clear interrupt */
02360         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02361
02362         /* Enable the QSPI Transfer Complete Interrupt */
02363         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02364
02365         /* Configure QSPI: CR register with Abort request */
02366         SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02367       }
02368       else
02369       {
02370         /* Change state of QSPI */
02371         hqspi->State = HAL_QSPI_STATE_READY;
02372       }
02373     }
02374   }
02375   return status;
02376 }
02377
02378 /** @brief Set QSPI timeout.
02379   * @param  hqspi QSPI handle.
02380   * @param  Timeout Timeout for the QSPI memory access.
02381   * @retval None
02382   */
02383 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
02384 {
02385   hqspi->Timeout = Timeout;
02386 }
02387
02388 /** @brief Set QSPI Fifo threshold.
02389   * @param  hqspi QSPI handle.
02390   * @param  Threshold Threshold of the Fifo (value between 1 and 16).
02391   * @retval HAL status
02392   */
02393 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
02394 {
02395   HAL_StatusTypeDef status = HAL_OK;
02396
02397   /* Process locked */
02398   __HAL_LOCK(hqspi);
02399
02400   if(hqspi->State == HAL_QSPI_STATE_READY)
02401   {
02402     /* Synchronize init structure with new FIFO threshold value */
02403     hqspi->Init.FifoThreshold = Threshold;
02404
02405     /* Configure QSPI FIFO Threshold */
02406     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
02407                ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
02408   }
02409   else
02410   {
02411     status = HAL_BUSY;
02412   }
02413
02414   /* Process unlocked */
02415   __HAL_UNLOCK(hqspi);
02416
02417   /* Return function status */
02418   return status;
02419 }
02420
02421 /** @brief Get QSPI Fifo threshold.
02422   * @param  hqspi QSPI handle.
02423   * @retval Fifo threshold (value between 1 and 16)
02424   */
02425 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
02426 {
02427   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
02428 }
02429
02430 /** @brief  Set FlashID.
02431   * @param  hqspi QSPI handle.
02432   * @param  FlashID Index of the flash memory to be accessed.
02433   *                   This parameter can be a value of @ref QSPI_Flash_Select.
02434   * @note   The FlashID is ignored when dual flash mode is enabled.
02435   * @retval HAL status
02436   */
02437 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
02438 {
02439   HAL_StatusTypeDef status = HAL_OK;
02440
02441   /* Check the parameter */
02442   assert_param(IS_QSPI_FLASH_ID(FlashID));
02443
02444   /* Process locked */
02445   __HAL_LOCK(hqspi);
02446
02447   if(hqspi->State == HAL_QSPI_STATE_READY)
02448   {
02449     /* Synchronize init structure with new FlashID value */
02450     hqspi->Init.FlashID = FlashID;
02451
02452     /* Configure QSPI FlashID */
02453     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
02454   }
02455   else
02456   {
02457     status = HAL_BUSY;
02458   }
02459
02460   /* Process unlocked */
02461   __HAL_UNLOCK(hqspi);
02462
02463   /* Return function status */
02464   return status;
02465 }
02466
02467 /**
02468   * @}
02469   */
02470
02471 /**
02472   * @}
02473   */
02474
02475 /** @defgroup QSPI_Private_Functions QSPI Private Functions
02476   * @{
02477   */
02478
02479 /**
02480   * @brief  DMA QSPI receive process complete callback.
02481   * @param  hdma DMA handle
02482   * @retval None
02483   */
02484 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
02485 {
02486   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02487   hqspi->RxXferCount = 0U;
02488
02489   /* Enable the QSPI transfer complete Interrupt */
02490   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02491 }
02492
02493 /**
02494   * @brief  DMA QSPI transmit process complete callback.
02495   * @param  hdma DMA handle
02496   * @retval None
02497   */
02498 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
02499 {
02500   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02501   hqspi->TxXferCount = 0U;
02502
02503   /* Enable the QSPI transfer complete Interrupt */
02504   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02505 }
02506
02507 /**
02508   * @brief  DMA QSPI receive process half complete callback.
02509   * @param  hdma DMA handle
02510   * @retval None
02511   */
02512 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02513 {
02514   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02515
02516 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02517   hqspi->RxHalfCpltCallback(hqspi);
02518 #else
02519   HAL_QSPI_RxHalfCpltCallback(hqspi);
02520 #endif
02521 }
02522
02523 /**
02524   * @brief  DMA QSPI transmit process half complete callback.
02525   * @param  hdma DMA handle
02526   * @retval None
02527   */
02528 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02529 {
02530   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02531
02532 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02533   hqspi->TxHalfCpltCallback(hqspi);
02534 #else
02535   HAL_QSPI_TxHalfCpltCallback(hqspi);
02536 #endif
02537 }
02538
02539 /**
02540   * @brief  DMA QSPI communication error callback.
02541   * @param  hdma DMA handle
02542   * @retval None
02543   */
02544 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
02545 {
02546   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
02547
02548   hqspi->RxXferCount = 0U;
02549   hqspi->TxXferCount = 0U;
02550   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
02551
02552   /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02553   CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02554
02555   /* Abort the QSPI */
02556   (void)HAL_QSPI_Abort_IT(hqspi);
02557
02558 }
02559
02560 /**
02561   * @brief  DMA QSPI abort complete callback.
02562   * @param  hdma DMA handle
02563   * @retval None
02564   */
02565 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
02566 {
02567   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
02568
02569   hqspi->RxXferCount = 0U;
02570   hqspi->TxXferCount = 0U;
02571
02572   if(hqspi->State == HAL_QSPI_STATE_ABORT)
02573   {
02574     /* DMA Abort called by QSPI abort */
02575     /* Clear interrupt */
02576     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02577
02578     /* Enable the QSPI Transfer Complete Interrupt */
02579     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02580
02581     /* Configure QSPI: CR register with Abort request */
02582     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02583   }
02584   else
02585   {
02586     /* DMA Abort called due to a transfer error interrupt */
02587     /* Change state of QSPI */
02588     hqspi->State = HAL_QSPI_STATE_READY;
02589
02590     /* Error callback */
02591 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02592     hqspi->ErrorCallback(hqspi);
02593 #else
02594     HAL_QSPI_ErrorCallback(hqspi);
02595 #endif
02596   }
02597 }
02598
02599 /**
02600   * @brief  Wait for a flag state until timeout.
02601   * @param  hqspi QSPI handle
02602   * @param  Flag Flag checked
02603   * @param  State Value of the flag expected
02604   * @param  Tickstart Tick start value
02605   * @param  Timeout Duration of the timeout
02606   * @retval HAL status
02607   */
02608 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
02609                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
02610 {
02611   /* Wait until flag is in expected state */
02612   while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
02613   {
02614     /* Check for the Timeout */
02615     if (Timeout != HAL_MAX_DELAY)
02616     {
02617       if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02618       {
02619         hqspi->State     = HAL_QSPI_STATE_ERROR;
02620         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
02621
02622         return HAL_ERROR;
02623       }
02624     }
02625   }
02626   return HAL_OK;
02627 }
02628
02629 /**
02630   * @brief  Configure the communication registers.
02631   * @param  hqspi QSPI handle
02632   * @param  cmd structure that contains the command configuration information
02633   * @param  FunctionalMode functional mode to configured
02634   *           This parameter can be one of the following values:
02635   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
02636   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
02637   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
02638   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
02639   * @retval None
02640   */
02641 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
02642 {
02643   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
02644
02645   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
02646   {
02647     /* Configure QSPI: DLR register with the number of data to read or write */
02648     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
02649   }
02650
02651   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
02652   {
02653     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02654     {
02655       /* Configure QSPI: ABR register with alternate bytes value */
02656       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02657
02658       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02659       {
02660         /*---- Command with instruction, address and alternate bytes ----*/
02661         /* Configure QSPI: CCR register with all communications parameters */
02662         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02663                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02664                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02665                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
02666                                          cmd->Instruction | FunctionalMode));
02667
02668         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02669         {
02670           /* Configure QSPI: AR register with address value */
02671           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02672         }
02673       }
02674       else
02675       {
02676         /* Clear AR register */
02677         CLEAR_REG(hqspi->Instance->AR);
02678
02679         /*---- Command with instruction and alternate bytes ----*/
02680         /* Configure QSPI: CCR register with all communications parameters */
02681         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02682                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02683                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02684                                          cmd->AddressMode | cmd->InstructionMode |
02685                                          cmd->Instruction | FunctionalMode));
02686       }
02687     }
02688     else
02689     {
02690       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02691       {
02692         /*---- Command with instruction and address ----*/
02693         /* Configure QSPI: CCR register with all communications parameters */
02694         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02695                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02696                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
02697                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02698
02699         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02700         {
02701           /* Configure QSPI: AR register with address value */
02702           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02703         }
02704       }
02705       else
02706       {
02707         /* Clear AR register */
02708         CLEAR_REG(hqspi->Instance->AR);
02709
02710         /*---- Command with only instruction ----*/
02711         /* Configure QSPI: CCR register with all communications parameters */
02712         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02713                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02714                                          cmd->AlternateByteMode | cmd->AddressMode |
02715                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02716       }
02717     }
02718   }
02719   else
02720   {
02721     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02722     {
02723       /* Configure QSPI: ABR register with alternate bytes value */
02724       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02725
02726       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02727       {
02728         /*---- Command with address and alternate bytes ----*/
02729         /* Configure QSPI: CCR register with all communications parameters */
02730         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02731                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02732                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02733                                          cmd->AddressSize | cmd->AddressMode |
02734                                          cmd->InstructionMode | FunctionalMode));
02735
02736         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02737         {
02738           /* Configure QSPI: AR register with address value */
02739           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02740         }
02741       }
02742       else
02743       {
02744         /* Clear AR register */
02745         CLEAR_REG(hqspi->Instance->AR);
02746
02747         /*---- Command with only alternate bytes ----*/
02748         /* Configure QSPI: CCR register with all communications parameters */
02749         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02750                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02751                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02752                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02753       }
02754     }
02755     else
02756     {
02757       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02758       {
02759         /*---- Command with only address ----*/
02760         /* Configure QSPI: CCR register with all communications parameters */
02761         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02762                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02763                                          cmd->AlternateByteMode | cmd->AddressSize |
02764                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02765
02766         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02767         {
02768           /* Configure QSPI: AR register with address value */
02769           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02770         }
02771       }
02772       else
02773       {
02774         /* Clear AR register */
02775         CLEAR_REG(hqspi->Instance->AR);
02776
02777         /*---- Command with only data phase ----*/
02778         if (cmd->DataMode != QSPI_DATA_NONE)
02779         {
02780           /* Configure QSPI: CCR register with all communications parameters */
02781           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02782                                            cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02783                                            cmd->AlternateByteMode | cmd->AddressMode |
02784                                            cmd->InstructionMode | FunctionalMode));
02785         }
02786       }
02787     }
02788   }
02789 }
02790
02791 /**
02792   * @}
02793   */
02794
02795 /**
02796   * @}
02797   */
02798
02799 #endif /* HAL_QSPI_MODULE_ENABLED */
02800 /**
02801   * @}
02802   */
02803
02804 /**
02805   * @}
02806   */
02807
02808 #endif /* defined(QUADSPI) */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_qspi.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_qspi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of QSPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_QSPI_H
00021 #define STM32G4xx_HAL_QSPI_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 #if defined(QUADSPI)
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup QSPI
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  QSPI Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00051                                   This parameter can be a number between 0 and 255 */
00052   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00053                                   This parameter can be a value between 1 and 16 */
00054   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00055                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00056                                   This parameter can be a value of @ref QSPI_SampleShifting */
00057   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00058                                   required to address the flash memory. The flash capacity can be up to 4GB
00059                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00060                                   memory-mapped mode is limited to 256MB
00061                                   This parameter can be a number between 0 and 31 */
00062   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00063                                   of clock cycles which the chip select must remain high between commands.
00064                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00065   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00066                                   This parameter can be a value of @ref QSPI_ClockMode */
00067   uint32_t FlashID;            /* Specifies the Flash which will be used,
00068                                   This parameter can be a value of @ref QSPI_Flash_Select */
00069   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00070                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00071 }QSPI_InitTypeDef;
00072
00073 /**
00074   * @brief HAL QSPI State structures definition
00075   */
00076 typedef enum
00077 {
00078   HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
00079   HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
00080   HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
00081   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
00082   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
00083   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
00084   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
00085   HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
00086   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
00087 }HAL_QSPI_StateTypeDef;
00088
00089 /**
00090   * @brief  QSPI Handle Structure definition
00091   */
00092 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00093 typedef struct __QSPI_HandleTypeDef
00094 #else
00095 typedef struct
00096 #endif
00097 {
00098   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00099   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00100   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00101   __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
00102   __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00103   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00104   __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
00105   __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00106   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00107   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00108   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00109   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00110   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00111 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00112   void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
00113   void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00114   void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
00115   void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00116   void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00117   void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00118   void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
00119   void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
00120   void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
00121   void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00122
00123   void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00124   void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00125 #endif
00126 }QSPI_HandleTypeDef;
00127
00128 /**
00129   * @brief  QSPI Command structure definition
00130   */
00131 typedef struct
00132 {
00133   uint32_t Instruction;        /* Specifies the Instruction to be sent
00134                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00135   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00136                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00137   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00138                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00139   uint32_t AddressSize;        /* Specifies the Address Size
00140                                   This parameter can be a value of @ref QSPI_AddressSize */
00141   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00142                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00143   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00144                                   This parameter can be a number between 0 and 31 */
00145   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00146                                   This parameter can be a value of @ref QSPI_InstructionMode */
00147   uint32_t AddressMode;        /* Specifies the Address Mode
00148                                   This parameter can be a value of @ref QSPI_AddressMode */
00149   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00150                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00151   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00152                                   This parameter can be a value of @ref QSPI_DataMode */
00153   uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
00154                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00155                                   until end of memory)*/
00156   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00157                                   This parameter can be a value of @ref QSPI_DdrMode */
00158   uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data
00159                                   output by one quarter of QUADSPI output clock in DDR mode.
00160                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00161   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00162                                   This parameter can be a value of @ref QSPI_SIOOMode */
00163 }QSPI_CommandTypeDef;
00164
00165 /**
00166   * @brief  QSPI Auto Polling mode configuration structure definition
00167   */
00168 typedef struct
00169 {
00170   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00171                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00172   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00173                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00174   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00175                                   This parameter can be any value between 0 and 0xFFFF */
00176   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00177                                   This parameter can be any value between 1 and 4 */
00178   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00179                                   This parameter can be a value of @ref QSPI_MatchMode */
00180   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00181                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00182 }QSPI_AutoPollingTypeDef;
00183
00184 /**
00185   * @brief  QSPI Memory Mapped mode configuration structure definition
00186   */
00187 typedef struct
00188 {
00189   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00190                                   This parameter can be any value between 0 and 0xFFFF */
00191   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
00192                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00193 }QSPI_MemoryMappedTypeDef;
00194
00195 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00196 /**
00197   * @brief  HAL QSPI Callback ID enumeration definition
00198   */
00199 typedef enum
00200 {
00201   HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
00202   HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
00203   HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
00204   HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
00205   HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
00206   HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
00207   HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */
00208   HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */
00209   HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
00210   HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
00211
00212   HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
00213   HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
00214 }HAL_QSPI_CallbackIDTypeDef;
00215
00216 /**
00217   * @brief  HAL QSPI Callback pointer definition
00218   */
00219 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
00220 #endif
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported constants --------------------------------------------------------*/
00226 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00227   * @{
00228   */
00229
00230 /** @defgroup QSPI_ErrorCode QSPI Error Code
00231   * @{
00232   */
00233 #define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
00234 #define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
00235 #define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
00236 #define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
00237 #define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
00238 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00239 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
00240 #endif
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00246   * @{
00247   */
00248 #define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/
00249 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00255   * @{
00256   */
00257 #define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/
00258 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00259 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00260 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00261 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00262 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00263 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00264 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00270   * @{
00271   */
00272 #define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/
00273 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00279   * @{
00280   */
00281 #define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/
00282 #define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
00283 /**
00284   * @}
00285   */
00286
00287   /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
00288   * @{
00289   */
00290 #define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
00291 #define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup QSPI_AddressSize QSPI Address Size
00297   * @{
00298   */
00299 #define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/
00300 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00301 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00302 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00308   * @{
00309   */
00310 #define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/
00311 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00312 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00313 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00319 * @{
00320 */
00321 #define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/
00322 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00323 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00324 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup QSPI_AddressMode QSPI Address Mode
00330 * @{
00331 */
00332 #define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/
00333 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00334 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00335 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00341 * @{
00342 */
00343 #define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/
00344 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00345 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00346 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup QSPI_DataMode QSPI Data Mode
00352   * @{
00353   */
00354 #define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/
00355 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00356 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00357 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00363   * @{
00364   */
00365 #define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/
00366 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
00372   * @{
00373   */
00374 #define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/
00375 #define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one quarter of QUADSPI output clock in DDR mode*/
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00381   * @{
00382   */
00383 #define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/
00384 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup QSPI_MatchMode QSPI Match Mode
00390   * @{
00391   */
00392 #define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/
00393 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00399   * @{
00400   */
00401 #define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/
00402 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00408   * @{
00409   */
00410 #define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/
00411 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup QSPI_Flags QSPI Flags
00417   * @{
00418   */
00419 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00420 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00421 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00422 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00423 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00424 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup QSPI_Interrupts QSPI Interrupts
00430   * @{
00431   */
00432 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00433 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00434 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00435 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00436 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00442   * @brief QSPI Timeout definition
00443   * @{
00444   */
00445 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453
00454 /* Exported macros -----------------------------------------------------------*/
00455 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00456   * @{
00457   */
00458 /** @brief Reset QSPI handle state.
00459   * @param  __HANDLE__ QSPI handle.
00460   * @retval None
00461   */
00462 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00463 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00464                                                                   (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
00465                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
00466                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
00467                                                                } while(0)
00468 #else
00469 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00470 #endif
00471
00472 /** @brief  Enable the QSPI peripheral.
00473   * @param  __HANDLE__ specifies the QSPI Handle.
00474   * @retval None
00475   */
00476 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00477
00478 /** @brief  Disable the QSPI peripheral.
00479   * @param  __HANDLE__ specifies the QSPI Handle.
00480   * @retval None
00481   */
00482 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00483
00484 /** @brief  Enable the specified QSPI interrupt.
00485   * @param  __HANDLE__ specifies the QSPI Handle.
00486   * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.
00487   *          This parameter can be one of the following values:
00488   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00489   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00490   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00491   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00492   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00493   * @retval None
00494   */
00495 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00496
00497
00498 /** @brief  Disable the specified QSPI interrupt.
00499   * @param  __HANDLE__ specifies the QSPI Handle.
00500   * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.
00501   *          This parameter can be one of the following values:
00502   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00503   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00504   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00505   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00506   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00507   * @retval None
00508   */
00509 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00510
00511 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00512   * @param  __HANDLE__ specifies the QSPI Handle.
00513   * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.
00514   *          This parameter can be one of the following values:
00515   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00516   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00517   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00518   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00519   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00520   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00521   */
00522 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00523
00524 /**
00525   * @brief  Check whether the selected QSPI flag is set or not.
00526   * @param  __HANDLE__ specifies the QSPI Handle.
00527   * @param  __FLAG__ specifies the QSPI flag to check.
00528   *          This parameter can be one of the following values:
00529   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00530   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00531   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00532   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00533   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00534   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00535   * @retval None
00536   */
00537 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
00538
00539 /** @brief  Clears the specified QSPI's flag status.
00540   * @param  __HANDLE__ specifies the QSPI Handle.
00541   * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set
00542   *          This parameter can be one of the following values:
00543   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00544   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00545   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00546   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00547   * @retval None
00548   */
00549 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00550 /**
00551   * @}
00552   */
00553
00554 /* Exported functions --------------------------------------------------------*/
00555 /** @addtogroup QSPI_Exported_Functions
00556   * @{
00557   */
00558
00559 /** @addtogroup QSPI_Exported_Functions_Group1
00560   * @{
00561   */
00562 /* Initialization/de-initialization functions  ********************************/
00563 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00564 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00565 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00566 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00567 /**
00568   * @}
00569   */
00570
00571 /** @addtogroup QSPI_Exported_Functions_Group2
00572   * @{
00573   */
00574 /* IO operation functions *****************************************************/
00575 /* QSPI IRQ handler method */
00576 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00577
00578 /* QSPI indirect mode */
00579 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00580 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00581 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00582 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00583 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00584 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00585 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00586 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00587
00588 /* QSPI status flag polling mode */
00589 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00590 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00591
00592 /* QSPI memory-mapped mode */
00593 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00594
00595 /* Callback functions in non-blocking modes ***********************************/
00596 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00597 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00598 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00599
00600 /* QSPI indirect mode */
00601 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00602 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00603 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00604 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00605 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00606
00607 /* QSPI status flag polling mode */
00608 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00609
00610 /* QSPI memory-mapped mode */
00611 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00612
00613 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00614 /* QSPI callback registering/unregistering */
00615 HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
00616 HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
00617 #endif
00618 /**
00619   * @}
00620   */
00621
00622 /** @addtogroup QSPI_Exported_Functions_Group3
00623   * @{
00624   */
00625 /* Peripheral Control and State functions  ************************************/
00626 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (const QSPI_HandleTypeDef *hqspi);
00627 uint32_t              HAL_QSPI_GetError        (const QSPI_HandleTypeDef *hqspi);
00628 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00629 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00630 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00631 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00632 uint32_t              HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
00633 HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
00634 /**
00635   * @}
00636   */
00637
00638 /**
00639   * @}
00640   */
00641 /* End of exported functions -------------------------------------------------*/
00642
00643 /* Private macros ------------------------------------------------------------*/
00644 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00645   * @{
00646   */
00647 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
00648
00649 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 16U))
00650
00651 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00652                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00653
00654 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
00655
00656 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00657                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00658                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00659                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00660                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00661                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00662                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00663                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00664
00665 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00666                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00667
00668 #define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \
00669                                             ((FLASH_ID) == QSPI_FLASH_ID_2))
00670
00671 #define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00672                                             ((MODE) == QSPI_DUALFLASH_DISABLE))
00673
00674 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
00675
00676 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00677                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00678                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00679                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00680
00681 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00682                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00683                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00684                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00685
00686 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
00687
00688 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00689                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00690                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00691                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00692
00693 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00694                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00695                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00696                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00697
00698 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00699                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00700                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00701                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00702
00703 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00704                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00705                                             ((MODE) == QSPI_DATA_2_LINES) || \
00706                                             ((MODE) == QSPI_DATA_4_LINES))
00707
00708 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00709                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00710
00711 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00712                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00713
00714 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00715                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00716
00717 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00718
00719 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
00720
00721 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00722                                             ((MODE) == QSPI_MATCH_MODE_OR))
00723
00724 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00725                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00726
00727 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00728                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00729
00730 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
00731 /**
00732 * @}
00733 */
00734 /* End of private macros -----------------------------------------------------*/
00735
00736 /**
00737   * @}
00738   */
00739
00740 /**
00741   * @}
00742   */
00743
00744 #endif /* defined(QUADSPI) */
00745
00746 #ifdef __cplusplus
00747 }
00748 #endif
00749
00750 #endif /* STM32G4xx_HAL_QSPI_H */
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_rcc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                       ##### RCC specific features #####
00014   ==============================================================================
00015     [..]
00016       After reset the device is running from High Speed Internal oscillator
00017       (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
00018       and I-Cache are disabled, and all peripherals are off except internal
00019       SRAM, Flash and JTAG.
00020
00021       (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
00022           all peripherals mapped on these buses are running at HSI speed.
00023       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00024       (+) All GPIOs are in analog mode, except the JTAG pins which
00025           are assigned to be used for debug purpose.
00026
00027     [..]
00028       Once the device started from reset, the user application has to:
00029       (+) Configure the clock source to be used to drive the System clock
00030           (if the application needs higher frequency/performance)
00031       (+) Configure the System clock frequency and Flash settings
00032       (+) Configure the AHB and APB buses prescalers
00033       (+) Enable the clock for the peripheral(s) to be used
00034       (+) Configure the clock source(s) for peripherals which clocks are not
00035           derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs,
00036           UCPD, I2S, I2C, LPTIM, ADC, QSPI)
00037
00038   @endverbatim
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * Copyright (c) 2019 STMicroelectronics.
00043   * All rights reserved.
00044   *
00045   * This software is licensed under terms that can be found in the LICENSE file in
00046   * the root directory of this software component.
00047   * If no LICENSE file comes with this software, it is provided AS-IS.
00048   ******************************************************************************
00049   */
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32g4xx_hal.h"
00053
00054 /** @addtogroup STM32G4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @defgroup RCC RCC
00059   * @brief RCC HAL module driver
00060   * @{
00061   */
00062
00063 #ifdef HAL_RCC_MODULE_ENABLED
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /** @defgroup RCC_Private_Constants RCC Private Constants
00068  * @{
00069  */
00070 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
00071 #define HSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
00072 #define LSI_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
00073 #define HSI48_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
00074 #define PLL_TIMEOUT_VALUE          2U                /* 2 ms (minimum Tick + 1) */
00075 #define CLOCKSWITCH_TIMEOUT_VALUE  5000U             /* 5 s    */
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macro -------------------------------------------------------------*/
00081 /** @defgroup RCC_Private_Macros RCC Private Macros
00082   * @{
00083   */
00084 #define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__)   ((__RCC_MCOx__) & GPIO_PIN_MASK)
00085
00086 #define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__)    (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
00087
00088 #define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
00089
00090 #define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__)  (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
00091
00092 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
00093             (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
00094 /**
00095   * @}
00096   */
00097
00098 /* Private variables ---------------------------------------------------------*/
00099
00100 /* Private function prototypes -----------------------------------------------*/
00101 /** @defgroup RCC_Private_Functions RCC Private Functions
00102   * @{
00103   */
00104 static uint32_t          RCC_GetSysClockFreqFromPLLSource(void);
00105 /**
00106   * @}
00107   */
00108
00109 /* Exported functions --------------------------------------------------------*/
00110
00111 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00116   *  @brief    Initialization and Configuration functions
00117   *
00118   @verbatim
00119  ===============================================================================
00120            ##### Initialization and de-initialization functions #####
00121  ===============================================================================
00122     [..]
00123       This section provides functions allowing to configure the internal and external oscillators
00124       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
00125        and APB2).
00126
00127     [..] Internal/external clock and PLL configuration
00128          (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
00129              the PLL as System clock source.
00130
00131          (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
00132              clock source.
00133
00134          (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
00135              through the PLL as System clock source. Can be used also optionally as RTC clock source.
00136
00137          (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
00138
00139          (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
00140            (++) The first output is used to generate the high speed system clock (up to 170 MHz).
00141            (++) The second output is used to generate the clock for the USB (48 MHz),
00142                 the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S.
00143            (++) The third output is used to generate a clock for ADC
00144
00145          (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
00146             (HSE used directly or through PLL as System clock source), the System clock
00147              is automatically switched to HSI and an interrupt is generated if enabled.
00148              The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
00149              exception vector.
00150
00151          (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE,
00152              main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin.
00153
00154     [..] System, AHB and APB buses clocks configuration
00155          (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00156              HSE and main PLL.
00157              The AHB clock (HCLK) is derived from System clock through configurable
00158              prescaler and used to clock the CPU, memory and peripherals mapped
00159              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00160              from AHB clock through configurable prescalers and used to clock
00161              the peripherals mapped on these buses. You can use
00162              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00163
00164          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00165
00166            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
00167                 divided by 2 to 31.
00168                 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
00169                 to configure this clock.
00170            (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
00171                 to work correctly, while the RNG peripheral requires a frequency
00172                 equal or lower than to 48 MHz. This clock is derived of the main PLL
00173                 through PLLQ divider. You have to enable the peripheral clock and use
00174                 HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
00175            (+@) IWDG clock which is always the LSI clock.
00176
00177
00178          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz.
00179              The clock source frequency should be adapted depending on the device voltage range
00180              as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
00181
00182   @endverbatim
00183
00184            Table 1. HCLK clock frequency for STM32G4xx devices
00185            +----------------------------------------------------------------------------+
00186            | Latency         |            HCLK clock frequency (MHz)                    |
00187            |                 |----------------------------------------------------------|
00188            |                 |  voltage range 1  |  voltage range 1  | voltage range 2  |
00189            |                 | boost mode 1.28 V | normal mode 1.2 V |     1.0 V        |
00190            |-----------------|-------------------|-------------------|------------------|
00191            |0WS(1 CPU cycles)|    HCLK <= 34     |    HCLK <= 30     |    HCLK <= 13    |
00192            |-----------------|-------------------|-------------------|------------------|
00193            |1WS(2 CPU cycles)|    HCLK <= 68     |    HCLK <= 60     |    HCLK <= 26    |
00194            |-----------------|-------------------|-------------------|------------------|
00195            |2WS(3 CPU cycles)|    HCLK <= 102    |    HCLK <= 90     |        -         |
00196            |-----------------|-------------------|-------------------|------------------|
00197            |3WS(4 CPU cycles)|    HCLK <= 136    |    HCLK <= 120    |        -         |
00198            |-----------------|-------------------|-------------------|------------------|
00199            |4WS(5 CPU cycles)|    HCLK <= 170    |    HCLK <= 150    |        -         |
00200            +----------------------------------------------------------------------------+
00201
00202   * @{
00203   */
00204
00205 /**
00206   * @brief  Reset the RCC clock configuration to the default reset state.
00207   * @note   The default reset state of the clock configuration is given below:
00208   *            - HSI ON and used as system clock source
00209   *            - HSE, PLL OFF
00210   *            - AHB, APB1 and APB2 prescaler set to 1.
00211   *            - CSS, MCO1 OFF
00212   *            - All interrupts disabled
00213   *            - All interrupt and reset flags cleared
00214   * @note   This function doesn't modify the configuration of the
00215   *            - Peripheral clocks
00216   *            - LSI, LSE and RTC clocks
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_RCC_DeInit(void)
00220 {
00221   uint32_t tickstart;
00222
00223   /* Get Start Tick*/
00224   tickstart = HAL_GetTick();
00225
00226   /* Set HSION bit to the reset value */
00227   SET_BIT(RCC->CR, RCC_CR_HSION);
00228
00229   /* Wait till HSI is ready */
00230   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00231   {
00232     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00233     {
00234       return HAL_TIMEOUT;
00235     }
00236   }
00237
00238  /* Set HSITRIM[6:0] bits to the reset value */
00239   SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
00240
00241   /* Get Start Tick*/
00242   tickstart = HAL_GetTick();
00243
00244   /* Reset CFGR register (HSI is selected as system clock source) */
00245   RCC->CFGR = 0x00000001u;
00246
00247   /* Wait till HSI is ready */
00248   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
00249   {
00250     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00251     {
00252       return HAL_TIMEOUT;
00253     }
00254   }
00255
00256   /* Update the SystemCoreClock global variable */
00257   SystemCoreClock = HSI_VALUE;
00258
00259   /* Adapt Systick interrupt period */
00260   if (HAL_InitTick(uwTickPrio) != HAL_OK)
00261   {
00262     return HAL_ERROR;
00263   }
00264
00265   /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */
00266   RCC->CR = RCC_CR_HSION;
00267
00268   /* Then again to HSEBYP in case bypass was enabled */
00269   RCC->CR = RCC_CR_HSION;
00270
00271   /* Get Start Tick*/
00272   tickstart = HAL_GetTick();
00273
00274   /* Wait till PLL is OFF */
00275   while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00276   {
00277     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00278     {
00279       return HAL_TIMEOUT;
00280     }
00281   }
00282
00283   /* once PLL is OFF, reset PLLCFGR register to default value */
00284   RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
00285
00286   /* Disable all interrupts */
00287   CLEAR_REG(RCC->CIER);
00288
00289   /* Clear all interrupt flags */
00290   WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
00291
00292   /* Clear all reset flags */
00293   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
00294
00295   return HAL_OK;
00296 }
00297
00298 /**
00299   * @brief  Initialize the RCC Oscillators according to the specified parameters in the
00300   *         RCC_OscInitTypeDef.
00301   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
00302   *         contains the configuration information for the RCC Oscillators.
00303   * @note   The PLL is not disabled when used as system clock.
00304   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00305   *         supported by this macro. User should request a transition to LSE Off
00306   *         first and then LSE On or LSE Bypass.
00307   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00308   *         supported by this macro. User should request a transition to HSE Off
00309   *         first and then HSE On or HSE Bypass.
00310   * @retval HAL status
00311   */
00312 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00313 {
00314   uint32_t tickstart;
00315   uint32_t temp_sysclksrc;
00316   uint32_t temp_pllckcfg;
00317
00318   /* Check Null pointer */
00319   if (RCC_OscInitStruct == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the parameters */
00325   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00326
00327   /*------------------------------- HSE Configuration ------------------------*/
00328   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00329   {
00330     /* Check the parameters */
00331     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00332
00333     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00334     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
00335
00336     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00337     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
00338     {
00339       if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00340       {
00341         return HAL_ERROR;
00342       }
00343     }
00344     else
00345     {
00346       /* Set the new HSE configuration ---------------------------------------*/
00347       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00348
00349       /* Check the HSE State */
00350       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00351       {
00352         /* Get Start Tick*/
00353         tickstart = HAL_GetTick();
00354
00355         /* Wait till HSE is ready */
00356         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
00357         {
00358           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00359           {
00360             return HAL_TIMEOUT;
00361           }
00362         }
00363       }
00364       else
00365       {
00366         /* Get Start Tick*/
00367         tickstart = HAL_GetTick();
00368
00369         /* Wait till HSE is disabled */
00370         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
00371         {
00372           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00373           {
00374             return HAL_TIMEOUT;
00375           }
00376         }
00377       }
00378     }
00379   }
00380   /*----------------------------- HSI Configuration --------------------------*/
00381   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00382   {
00383     /* Check the parameters */
00384     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00385     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00386
00387     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00388     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00389     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
00390     if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
00391     {
00392       /* When HSI is used as system clock it will not be disabled */
00393       if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00394       {
00395         return HAL_ERROR;
00396       }
00397       /* Otherwise, just the calibration is allowed */
00398       else
00399       {
00400         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00401         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00402
00403         /* Adapt Systick interrupt period */
00404         if (HAL_InitTick(uwTickPrio) != HAL_OK)
00405         {
00406           return HAL_ERROR;
00407         }
00408       }
00409     }
00410     else
00411     {
00412       /* Check the HSI State */
00413       if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00414       {
00415         /* Enable the Internal High Speed oscillator (HSI). */
00416         __HAL_RCC_HSI_ENABLE();
00417
00418         /* Get Start Tick*/
00419         tickstart = HAL_GetTick();
00420
00421         /* Wait till HSI is ready */
00422         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00423         {
00424           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00425           {
00426             return HAL_TIMEOUT;
00427           }
00428         }
00429
00430         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00431         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00432       }
00433       else
00434       {
00435         /* Disable the Internal High Speed oscillator (HSI). */
00436         __HAL_RCC_HSI_DISABLE();
00437
00438         /* Get Start Tick*/
00439         tickstart = HAL_GetTick();
00440
00441         /* Wait till HSI is disabled */
00442         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
00443         {
00444           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00445           {
00446             return HAL_TIMEOUT;
00447           }
00448         }
00449       }
00450     }
00451   }
00452   /*------------------------------ LSI Configuration -------------------------*/
00453   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00454   {
00455     /* Check the parameters */
00456     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00457
00458     /* Check the LSI State */
00459     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00460     {
00461       /* Enable the Internal Low Speed oscillator (LSI). */
00462       __HAL_RCC_LSI_ENABLE();
00463
00464       /* Get Start Tick*/
00465       tickstart = HAL_GetTick();
00466
00467       /* Wait till LSI is ready */
00468       while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
00469       {
00470         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00471         {
00472           return HAL_TIMEOUT;
00473         }
00474       }
00475     }
00476     else
00477     {
00478       /* Disable the Internal Low Speed oscillator (LSI). */
00479       __HAL_RCC_LSI_DISABLE();
00480
00481       /* Get Start Tick*/
00482       tickstart = HAL_GetTick();
00483
00484       /* Wait till LSI is disabled */
00485       while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
00486       {
00487         if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00488         {
00489           return HAL_TIMEOUT;
00490         }
00491       }
00492     }
00493   }
00494   /*------------------------------ LSE Configuration -------------------------*/
00495   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00496   {
00497     FlagStatus       pwrclkchanged = RESET;
00498
00499     /* Check the parameters */
00500     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00501
00502     /* Update LSE configuration in Backup Domain control register    */
00503     /* Requires to enable write access to Backup Domain if necessary */
00504     if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
00505     {
00506       __HAL_RCC_PWR_CLK_ENABLE();
00507       pwrclkchanged = SET;
00508     }
00509
00510     if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00511     {
00512       /* Enable write access to Backup domain */
00513       SET_BIT(PWR->CR1, PWR_CR1_DBP);
00514
00515       /* Wait for Backup domain Write protection disable */
00516       tickstart = HAL_GetTick();
00517
00518       while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00519       {
00520         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00521         {
00522           return HAL_TIMEOUT;
00523         }
00524       }
00525     }
00526
00527     /* Set the new LSE configuration -----------------------------------------*/
00528     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00529
00530     /* Check the LSE State */
00531     if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00532     {
00533       /* Get Start Tick*/
00534       tickstart = HAL_GetTick();
00535
00536       /* Wait till LSE is ready */
00537       while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
00538       {
00539         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00540         {
00541           return HAL_TIMEOUT;
00542         }
00543       }
00544     }
00545     else
00546     {
00547       /* Get Start Tick*/
00548       tickstart = HAL_GetTick();
00549
00550       /* Wait till LSE is disabled */
00551       while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
00552       {
00553         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00554         {
00555           return HAL_TIMEOUT;
00556         }
00557       }
00558     }
00559
00560     /* Restore clock configuration if changed */
00561     if (pwrclkchanged == SET)
00562     {
00563       __HAL_RCC_PWR_CLK_DISABLE();
00564     }
00565   }
00566
00567   /*------------------------------ HSI48 Configuration -----------------------*/
00568   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00569   {
00570     /* Check the parameters */
00571     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00572
00573     /* Check the HSI48 State */
00574     if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
00575     {
00576       /* Enable the Internal Low Speed oscillator (HSI48). */
00577       __HAL_RCC_HSI48_ENABLE();
00578
00579       /* Get Start Tick*/
00580       tickstart = HAL_GetTick();
00581
00582       /* Wait till HSI48 is ready */
00583       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
00584       {
00585         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00586         {
00587           return HAL_TIMEOUT;
00588         }
00589       }
00590     }
00591     else
00592     {
00593       /* Disable the Internal Low Speed oscillator (HSI48). */
00594       __HAL_RCC_HSI48_DISABLE();
00595
00596       /* Get Start Tick*/
00597       tickstart = HAL_GetTick();
00598
00599       /* Wait till HSI48 is disabled */
00600       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
00601       {
00602         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00603         {
00604           return HAL_TIMEOUT;
00605         }
00606       }
00607     }
00608   }
00609
00610   /*-------------------------------- PLL Configuration -----------------------*/
00611   /* Check the parameters */
00612   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00613
00614   if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
00615   {
00616     /* Check if the PLL is used as system clock or not */
00617     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00618     {
00619       if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
00620       {
00621         /* Check the parameters */
00622         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00623         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00624         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00625         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00626         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00627         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
00628
00629         /* Disable the main PLL. */
00630         __HAL_RCC_PLL_DISABLE();
00631
00632         /* Get Start Tick*/
00633         tickstart = HAL_GetTick();
00634
00635         /* Wait till PLL is disabled */
00636         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00637         {
00638           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00639           {
00640             return HAL_TIMEOUT;
00641           }
00642         }
00643
00644         /* Configure the main PLL clock source, multiplication and division factors. */
00645         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00646                              RCC_OscInitStruct->PLL.PLLM,
00647                              RCC_OscInitStruct->PLL.PLLN,
00648                              RCC_OscInitStruct->PLL.PLLP,
00649                              RCC_OscInitStruct->PLL.PLLQ,
00650                              RCC_OscInitStruct->PLL.PLLR);
00651
00652         /* Enable the main PLL. */
00653         __HAL_RCC_PLL_ENABLE();
00654
00655         /* Enable PLL System Clock output. */
00656          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
00657
00658         /* Get Start Tick*/
00659         tickstart = HAL_GetTick();
00660
00661         /* Wait till PLL is ready */
00662         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
00663         {
00664           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00665           {
00666             return HAL_TIMEOUT;
00667           }
00668         }
00669       }
00670       else
00671       {
00672         /* Disable the main PLL. */
00673         __HAL_RCC_PLL_DISABLE();
00674
00675         /* Get Start Tick*/
00676         tickstart = HAL_GetTick();
00677
00678         /* Wait till PLL is disabled */
00679         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00680         {
00681           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00682           {
00683             return HAL_TIMEOUT;
00684           }
00685         }
00686
00687         /* Unselect PLL clock source and disable outputs to save power */
00688         RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
00689       }
00690     }
00691     else
00692     {
00693       /* Check if there is a request to disable the PLL used as System clock source */
00694       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
00695       {
00696         return HAL_ERROR;
00697       }
00698       else
00699       {
00700       /* Do not return HAL_ERROR if request repeats the current configuration */
00701       temp_pllckcfg = RCC->PLLCFGR;
00702       if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
00703          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
00704          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
00705          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
00706          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
00707          (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
00708       {
00709         return HAL_ERROR;
00710       }
00711     }
00712   }
00713   }
00714
00715   return HAL_OK;
00716 }
00717
00718 /**
00719   * @brief  Initialize the CPU, AHB and APB buses clocks according to the specified
00720   *         parameters in the RCC_ClkInitStruct.
00721   * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
00722   *         contains the configuration information for the RCC peripheral.
00723   * @param  FLatency  FLASH Latency
00724   *          This parameter can be one of the following values:
00725   *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
00726   *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
00727   *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycles
00728   *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycles
00729   *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycles
00730   *            @arg FLASH_LATENCY_5   FLASH 5 Latency cycles
00731   *            @arg FLASH_LATENCY_6   FLASH 6 Latency cycles
00732   *            @arg FLASH_LATENCY_7   FLASH 7 Latency cycles
00733   *            @arg FLASH_LATENCY_8   FLASH 8 Latency cycles
00734   *            @arg FLASH_LATENCY_9   FLASH 9 Latency cycles
00735   *            @arg FLASH_LATENCY_10  FLASH 10 Latency cycles
00736   *            @arg FLASH_LATENCY_11  FLASH 11 Latency cycles
00737   *            @arg FLASH_LATENCY_12  FLASH 12 Latency cycles
00738   *            @arg FLASH_LATENCY_13  FLASH 13 Latency cycles
00739   *            @arg FLASH_LATENCY_14  FLASH 14 Latency cycles
00740   *            @arg FLASH_LATENCY_15  FLASH 15 Latency cycles
00741   *
00742   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00743   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
00744   *
00745   * @note   The HSI is used by default as system clock source after
00746   *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
00747   *         the HSI frequency is set to its default value 16 MHz.
00748   *
00749   * @note   The HSI can be selected as system clock source after
00750   *         from STOP modes or in case of failure of the HSE used directly or indirectly
00751   *         as system clock (if the Clock Security System CSS is enabled).
00752   *
00753   * @note   A switch from one clock source to another occurs only if the target
00754   *         clock source is ready (clock stable after startup delay or PLL locked).
00755   *         If a clock source which is not yet ready is selected, the switch will
00756   *         occur when the clock source is ready.
00757   *
00758   * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
00759   *         currently used as system clock source.
00760   *
00761   * @note   Depending on the device voltage range, the software has to set correctly
00762   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00763   *         (for more details refer to section above "Initialization/de-initialization functions")
00764   * @retval None
00765   */
00766 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00767 {
00768   uint32_t tickstart;
00769   uint32_t pllfreq;
00770   uint32_t hpre = RCC_SYSCLK_DIV1;
00771
00772   /* Check Null pointer */
00773   if (RCC_ClkInitStruct == NULL)
00774   {
00775     return HAL_ERROR;
00776   }
00777
00778   /* Check the parameters */
00779   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00780   assert_param(IS_FLASH_LATENCY(FLatency));
00781
00782   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00783     must be correctly programmed according to the frequency of the CPU clock
00784     (HCLK) and the supply voltage of the device. */
00785
00786   /* Increasing the number of wait states because of higher CPU frequency */
00787   if (FLatency > __HAL_FLASH_GET_LATENCY())
00788   {
00789     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00790     __HAL_FLASH_SET_LATENCY(FLatency);
00791
00792     /* Check that the new number of wait states is taken into account to access the Flash
00793     memory by reading the FLASH_ACR register */
00794     if (__HAL_FLASH_GET_LATENCY() != FLatency)
00795     {
00796       return HAL_ERROR;
00797     }
00798   }
00799
00800   /*------------------------- SYSCLK Configuration ---------------------------*/
00801   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00802   {
00803     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00804
00805     /* PLL is selected as System Clock Source */
00806     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00807     {
00808       /* Check the PLL ready flag */
00809       if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
00810       {
00811         return HAL_ERROR;
00812       }
00813       /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
00814       /* Compute target PLL output frequency */
00815       pllfreq = RCC_GetSysClockFreqFromPLLSource();
00816
00817       /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
00818       if(pllfreq > 80000000U)
00819       {
00820         if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
00821             (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
00822               (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
00823         {
00824           MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
00825           hpre = RCC_SYSCLK_DIV2;
00826         }
00827       }
00828     }
00829     else
00830     {
00831       /* HSE is selected as System Clock Source */
00832       if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00833       {
00834         /* Check the HSE ready flag */
00835         if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
00836         {
00837           return HAL_ERROR;
00838         }
00839       }
00840       /* HSI is selected as System Clock Source */
00841       else
00842       {
00843         /* Check the HSI ready flag */
00844         if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00845         {
00846           return HAL_ERROR;
00847         }
00848       }
00849       /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
00850       pllfreq = HAL_RCC_GetSysClockFreq();
00851
00852       /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
00853       if(pllfreq > 80000000U)
00854       {
00855         MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
00856         hpre = RCC_SYSCLK_DIV2;
00857       }
00858
00859     }
00860
00861     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
00862
00863     /* Get Start Tick*/
00864     tickstart = HAL_GetTick();
00865
00866     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
00867     {
00868       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00869       {
00870         return HAL_TIMEOUT;
00871       }
00872     }
00873   }
00874
00875   /*-------------------------- HCLK Configuration --------------------------*/
00876   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00877   {
00878     /* Set the highest APB divider in order to ensure that we do not go through
00879        a non-spec phase whatever we decrease or increase HCLK. */
00880     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00881     {
00882       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
00883     }
00884     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00885     {
00886       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
00887     }
00888
00889     /* Set the new HCLK clock divider */
00890     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00891     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00892   }
00893   else
00894   {
00895     /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
00896     if(hpre == RCC_SYSCLK_DIV2)
00897     {
00898       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
00899     }
00900   }
00901
00902   /* Decreasing the number of wait states because of lower CPU frequency */
00903   if (FLatency < __HAL_FLASH_GET_LATENCY())
00904   {
00905     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00906     __HAL_FLASH_SET_LATENCY(FLatency);
00907
00908     /* Check that the new number of wait states is taken into account to access the Flash
00909     memory by polling the FLASH_ACR register */
00910     tickstart = HAL_GetTick();
00911
00912     while (__HAL_FLASH_GET_LATENCY() != FLatency)
00913     {
00914       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00915       {
00916         return HAL_TIMEOUT;
00917       }
00918     }
00919   }
00920
00921   /*-------------------------- PCLK1 Configuration ---------------------------*/
00922   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00923   {
00924     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00925     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00926   }
00927
00928   /*-------------------------- PCLK2 Configuration ---------------------------*/
00929   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00930   {
00931     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00932     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
00933   }
00934
00935   /* Update the SystemCoreClock global variable */
00936   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
00937
00938   /* Configure the source of time base considering new system clocks settings*/
00939   return HAL_InitTick(uwTickPrio);
00940 }
00941
00942 /**
00943   * @}
00944   */
00945
00946 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00947  *  @brief   RCC clocks control functions
00948  *
00949 @verbatim
00950  ===============================================================================
00951                       ##### Peripheral Control functions #####
00952  ===============================================================================
00953     [..]
00954     This subsection provides a set of functions allowing to:
00955
00956     (+) Output clock to MCO pin.
00957     (+) Retrieve current clock frequencies.
00958     (+) Enable the Clock Security System.
00959
00960 @endverbatim
00961   * @{
00962   */
00963
00964 /**
00965   * @brief  Select the clock source to output on MCO pin(PA8/PG10).
00966   * @note   PA8/PG10 should be configured in alternate function mode.
00967   * @note   The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin)
00968   *         and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it
00969   *         as an MCO pin.
00970   *         The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value.
00971   * @param  RCC_MCOx  specifies the output direction for the clock source.
00972   *          For STM32G4xx family this parameter can have only one value:
00973   *            @arg @ref RCC_MCO_PA8  Clock source to output on MCO1 pin(PA8).
00974   *            @arg @ref RCC_MCO_PG10  Clock source to output on MCO1 pin(PG10).
00975   * @param  RCC_MCOSource  specifies the clock source to output.
00976   *          This parameter can be one of the following values:
00977   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
00978   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
00979   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
00980   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO source
00981   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
00982   *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
00983   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
00984   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
00985   * @param  RCC_MCODiv  specifies the MCO prescaler.
00986   *          This parameter can be one of the following values:
00987   *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
00988   *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
00989   *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
00990   *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
00991   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
00992   * @retval None
00993   */
00994 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00995 {
00996   GPIO_InitTypeDef gpio_initstruct;
00997   uint32_t mcoindex;
00998   uint32_t mco_gpio_index;
00999   GPIO_TypeDef * mco_gpio_port;
01000
01001   /* Check the parameters */
01002   assert_param(IS_RCC_MCO(RCC_MCOx));
01003
01004   /* Common GPIO init parameters */
01005   gpio_initstruct.Mode      = GPIO_MODE_AF_PP;
01006   gpio_initstruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
01007   gpio_initstruct.Pull      = GPIO_NOPULL;
01008
01009   /* Get MCOx selection */
01010   mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
01011
01012   /* Get MCOx GPIO Port */
01013   mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
01014
01015   /* MCOx Clock Enable */
01016   mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
01017   SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
01018
01019   /* Configure the MCOx pin in alternate function mode */
01020   gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
01021   gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
01022   HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
01023
01024    if (mcoindex == RCC_MCO1_INDEX)
01025   {
01026     assert_param(IS_RCC_MCODIV(RCC_MCODiv));
01027     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
01028     /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
01029     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
01030   }
01031 }
01032
01033 /**
01034   * @brief  Return the SYSCLK frequency.
01035   *
01036   * @note   The system frequency computed by this function is not the real
01037   *         frequency in the chip. It is calculated based on the predefined
01038   *         constant and the selected clock source:
01039   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
01040   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
01041   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
01042   *           HSI_VALUE(*) Value multiplied/divided by the PLL factors.
01043   * @note     (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
01044   *               16 MHz) but the real value may vary depending on the variations
01045   *               in voltage and temperature.
01046   * @note     (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value
01047   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
01048   *                frequency of the crystal used. Otherwise, this function may
01049   *                have wrong result.
01050   *
01051   * @note   The result of this function could be not correct when using fractional
01052   *         value for HSE crystal.
01053   *
01054   * @note   This function can be used by the user application to compute the
01055   *         baudrate for the communication peripherals or configure other parameters.
01056   *
01057   * @note   Each time SYSCLK changes, this function must be called to update the
01058   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01059   *
01060   *
01061   * @retval SYSCLK frequency
01062   */
01063 uint32_t HAL_RCC_GetSysClockFreq(void)
01064 {
01065   uint32_t pllvco, pllsource, pllr, pllm;
01066   uint32_t sysclockfreq;
01067
01068   if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
01069   {
01070     /* HSI used as system clock source */
01071     sysclockfreq = HSI_VALUE;
01072   }
01073   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
01074   {
01075     /* HSE used as system clock source */
01076     sysclockfreq = HSE_VALUE;
01077   }
01078   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
01079   {
01080     /* PLL used as system clock  source */
01081
01082     /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
01083     SYSCLK = PLL_VCO / PLLR
01084     */
01085     pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
01086     pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
01087
01088     switch (pllsource)
01089     {
01090     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01091       pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01092       break;
01093
01094     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01095     default:
01096       pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01097       break;
01098     }
01099     pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
01100     sysclockfreq = pllvco/pllr;
01101   }
01102   else
01103   {
01104     sysclockfreq = 0U;
01105   }
01106
01107   return sysclockfreq;
01108 }
01109
01110 /**
01111   * @brief  Return the HCLK frequency.
01112   * @note   Each time HCLK changes, this function must be called to update the
01113   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01114   *
01115   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
01116   * @retval HCLK frequency in Hz
01117   */
01118 uint32_t HAL_RCC_GetHCLKFreq(void)
01119 {
01120   return SystemCoreClock;
01121 }
01122
01123 /**
01124   * @brief  Return the PCLK1 frequency.
01125   * @note   Each time PCLK1 changes, this function must be called to update the
01126   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01127   * @retval PCLK1 frequency in Hz
01128   */
01129 uint32_t HAL_RCC_GetPCLK1Freq(void)
01130 {
01131   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01132   return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
01133 }
01134
01135 /**
01136   * @brief  Return the PCLK2 frequency.
01137   * @note   Each time PCLK2 changes, this function must be called to update the
01138   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01139   * @retval PCLK2 frequency in Hz
01140   */
01141 uint32_t HAL_RCC_GetPCLK2Freq(void)
01142 {
01143   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01144   return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
01145 }
01146
01147 /**
01148   * @brief  Configure the RCC_OscInitStruct according to the internal
01149   *         RCC configuration registers.
01150   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
01151   *         will be configured.
01152   * @retval None
01153   */
01154 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01155 {
01156   /* Check the parameters */
01157   assert_param(RCC_OscInitStruct != (void *)NULL);
01158
01159   /* Set all possible values for the Oscillator type parameter ---------------*/
01160   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
01161                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
01162
01163   /* Get the HSE configuration -----------------------------------------------*/
01164   if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01165   {
01166     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01167   }
01168   else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)
01169   {
01170     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01171   }
01172   else
01173   {
01174     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01175   }
01176
01177   /* Get the HSI configuration -----------------------------------------------*/
01178   if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)
01179   {
01180     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01181   }
01182   else
01183   {
01184     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01185   }
01186
01187   RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;
01188
01189   /* Get the LSE configuration -----------------------------------------------*/
01190   if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01191   {
01192     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01193   }
01194   else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01195   {
01196     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01197   }
01198   else
01199   {
01200     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01201   }
01202
01203   /* Get the LSI configuration -----------------------------------------------*/
01204   if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)
01205   {
01206     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01207   }
01208   else
01209   {
01210     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01211   }
01212
01213   /* Get the HSI48 configuration ---------------------------------------------*/
01214   if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
01215   {
01216     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01217   }
01218   else
01219   {
01220     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01221   }
01222
01223   /* Get the PLL configuration -----------------------------------------------*/
01224   if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)
01225   {
01226     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01227   }
01228   else
01229   {
01230     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01231   }
01232   RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
01233   RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
01234   RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01235   RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01236   RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);
01237   RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
01238 }
01239
01240 /**
01241   * @brief  Configure the RCC_ClkInitStruct according to the internal
01242   *         RCC configuration registers.
01243   * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
01244   *         will be configured.
01245   * @param  pFLatency  Pointer on the Flash Latency.
01246   * @retval None
01247   */
01248 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01249 {
01250   /* Check the parameters */
01251   assert_param(RCC_ClkInitStruct != (void  *)NULL);
01252   assert_param(pFLatency != (void *)NULL);
01253
01254   /* Set all possible values for the Clock type parameter --------------------*/
01255   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01256
01257   /* Get the SYSCLK configuration --------------------------------------------*/
01258   RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
01259
01260   /* Get the HCLK configuration ----------------------------------------------*/
01261   RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
01262
01263   /* Get the APB1 configuration ----------------------------------------------*/
01264   RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
01265
01266   /* Get the APB2 configuration ----------------------------------------------*/
01267   RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
01268
01269   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01270   *pFLatency = __HAL_FLASH_GET_LATENCY();
01271 }
01272
01273 /**
01274   * @brief  Enable the Clock Security System.
01275   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01276   *         is automatically disabled and an interrupt is generated to inform the
01277   *         software about the failure (Clock Security System Interrupt, CSSI),
01278   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01279   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
01280   * @note   The Clock Security System can only be cleared by reset.
01281   * @retval None
01282   */
01283 void HAL_RCC_EnableCSS(void)
01284 {
01285   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
01286 }
01287
01288 /**
01289   * @brief  Enable the LSE Clock Security System.
01290   * @note   If a failure is detected on the external 32 kHz oscillator,
01291   *         the LSE clock is no longer supplied to the RTC but no hardware action
01292   *         is made to the registers. If enabled, an interrupt will be generated
01293   *         and handle through @ref RCCEx_EXTI_LINE_LSECSS
01294   * @note   The Clock Security System can only be cleared by reset or after a LSE failure detection.
01295   * @retval None
01296   */
01297 void HAL_RCC_EnableLSECSS(void)
01298 {
01299   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01300 }
01301
01302 /**
01303   * @brief  Disable the LSE Clock Security System.
01304   * @note   After LSE failure detection, the software must disable LSECSSON
01305   * @note   The Clock Security System can only be cleared by reset otherwise.
01306   * @retval None
01307   */
01308 void HAL_RCC_DisableLSECSS(void)
01309 {
01310   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01311 }
01312
01313 /**
01314   * @brief Handle the RCC Clock Security System interrupt request.
01315   * @note This API should be called under the NMI_Handler().
01316   * @retval None
01317   */
01318 void HAL_RCC_NMI_IRQHandler(void)
01319 {
01320   /* Check RCC CSSF interrupt flag  */
01321   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01322   {
01323     /* RCC Clock Security System interrupt user callback */
01324     HAL_RCC_CSSCallback();
01325
01326     /* Clear RCC CSS pending bit */
01327     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01328   }
01329 }
01330
01331 /**
01332   * @brief  RCC Clock Security System interrupt callback.
01333   * @retval none
01334   */
01335 __weak void HAL_RCC_CSSCallback(void)
01336 {
01337   /* NOTE : This function should not be modified, when the callback is needed,
01338             the HAL_RCC_CSSCallback should be implemented in the user file
01339    */
01340 }
01341
01342 /**
01343   * @}
01344   */
01345
01346 /**
01347   * @}
01348   */
01349
01350 /* Private function prototypes -----------------------------------------------*/
01351 /** @addtogroup RCC_Private_Functions
01352   * @{
01353   */
01354
01355 /**
01356   * @brief  Compute SYSCLK frequency based on PLL SYSCLK source.
01357   * @retval SYSCLK frequency
01358   */
01359 static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
01360 {
01361   uint32_t pllvco, pllsource, pllr, pllm;
01362   uint32_t sysclockfreq;
01363
01364   /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
01365      SYSCLK = PLL_VCO / PLLR
01366    */
01367   pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
01368   pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
01369
01370   switch (pllsource)
01371   {
01372   case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01373     pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01374     break;
01375
01376   case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01377   default:
01378     pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01379     break;
01380   }
01381
01382   pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
01383   sysclockfreq = pllvco/pllr;
01384
01385   return sysclockfreq;
01386 }
01387
01388 /**
01389   * @}
01390   */
01391
01392 #endif /* HAL_RCC_MODULE_ENABLED */
01393 /**
01394   * @}
01395   */
01396
01397 /**
01398   * @}
01399   */
01400
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_rcc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_HAL_RCC_H
00020 #define STM32G4xx_HAL_RCC_H
00021
00022 #ifdef __cplusplus
00023  extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup RCC
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /** @defgroup RCC_Exported_Types RCC Exported Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  RCC PLL configuration structure definition
00044   */
00045 typedef struct
00046 {
00047   uint32_t PLLState;   /*!< The new state of the PLL.
00048                             This parameter can be a value of @ref RCC_PLL_Config                      */
00049
00050   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00051                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00052
00053   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00054                             This parameter must be a value of @ref RCC_PLLM_Clock_Divider             */
00055
00056   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00057                             This parameter must be a number between Min_Data = 8 and Max_Data = 127    */
00058
00059   uint32_t PLLP;       /*!< PLLP: Division factor for ADC clock.
00060                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00061
00062   uint32_t PLLQ;       /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks.
00063                             This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
00064
00065   uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
00066                             User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ.
00067                             This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
00068
00069 }RCC_PLLInitTypeDef;
00070
00071 /**
00072   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00073   */
00074 typedef struct
00075 {
00076   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00077                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00078
00079   uint32_t HSEState;             /*!< The new state of the HSE.
00080                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00081
00082   uint32_t LSEState;             /*!< The new state of the LSE.
00083                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00084
00085   uint32_t HSIState;             /*!< The new state of the HSI.
00086                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00087
00088   uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00089                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00090
00091   uint32_t LSIState;             /*!< The new state of the LSI.
00092                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00093
00094   uint32_t HSI48State;             /*!< The new state of the HSI48.
00095                                         This parameter can be a value of @ref RCC_HSI48_Config */
00096
00097   RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
00098
00099 }RCC_OscInitTypeDef;
00100
00101 /**
00102   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00103   */
00104 typedef struct
00105 {
00106   uint32_t ClockType;             /*!< The clock to be configured.
00107                                        This parameter can be a value of @ref RCC_System_Clock_Type      */
00108
00109   uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
00110                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00111
00112   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00113                                        This parameter can be a value of @ref RCC_AHB_Clock_Source       */
00114
00115   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00116                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00117
00118   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00119                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00120
00121 }RCC_ClkInitTypeDef;
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Exported constants --------------------------------------------------------*/
00128 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00129   * @{
00130   */
00131
00132 /** @defgroup RCC_Timeout_Value Timeout Values
00133   * @{
00134   */
00135 #define RCC_DBP_TIMEOUT_VALUE          2U                        /* 2 ms (minimum Tick + 1) */
00136 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup RCC_Oscillator_Type Oscillator Type
00142   * @{
00143   */
00144 #define RCC_OSCILLATORTYPE_NONE        0x00000000U               /*!< Oscillator configuration unchanged */
00145 #define RCC_OSCILLATORTYPE_HSE         0x00000001U               /*!< HSE to configure */
00146 #define RCC_OSCILLATORTYPE_HSI         0x00000002U               /*!< HSI to configure */
00147 #define RCC_OSCILLATORTYPE_LSE         0x00000004U               /*!< LSE to configure */
00148 #define RCC_OSCILLATORTYPE_LSI         0x00000008U               /*!< LSI to configure */
00149 #define RCC_OSCILLATORTYPE_HSI48       0x00000020U               /*!< HSI48 to configure */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup RCC_HSE_Config HSE Config
00155   * @{
00156   */
00157 #define RCC_HSE_OFF                    0x00000000U                                /*!< HSE clock deactivation */
00158 #define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
00159 #define RCC_HSE_BYPASS                 (RCC_CR_HSEBYP | RCC_CR_HSEON)             /*!< External clock source for HSE clock */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup RCC_LSE_Config LSE Config
00165   * @{
00166   */
00167 #define RCC_LSE_OFF                    0x00000000U                                    /*!< LSE clock deactivation */
00168 #define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
00169 #define RCC_LSE_BYPASS                 (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)             /*!< External clock source for LSE clock */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup RCC_HSI_Config HSI Config
00175   * @{
00176   */
00177 #define RCC_HSI_OFF                    0x00000000U            /*!< HSI clock deactivation */
00178 #define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
00179 #define RCC_HSICALIBRATION_DEFAULT     0x40U                  /* Default HSI calibration trimming value */
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup RCC_LSI_Config LSI Config
00185   * @{
00186   */
00187 #define RCC_LSI_OFF                    0x00000000U            /*!< LSI clock deactivation */
00188 #define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup RCC_HSI48_Config HSI48 Config
00194   * @{
00195   */
00196 #define RCC_HSI48_OFF                  0x00000000U            /*!< HSI48 clock deactivation */
00197 #define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON      /*!< HSI48 clock activation */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup RCC_PLL_Config PLL Config
00203   * @{
00204   */
00205 #define RCC_PLL_NONE                   0x00000000U            /*!< PLL configuration unchanged */
00206 #define RCC_PLL_OFF                    0x00000001U            /*!< PLL deactivation */
00207 #define RCC_PLL_ON                     0x00000002U            /*!< PLL activation */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
00213   * @{
00214   */
00215 #define RCC_PLLM_DIV1                  0x00000001U             /*!< PLLM division factor = 1  */
00216 #define RCC_PLLM_DIV2                  0x00000002U             /*!< PLLM division factor = 2  */
00217 #define RCC_PLLM_DIV3                  0x00000003U             /*!< PLLM division factor = 3  */
00218 #define RCC_PLLM_DIV4                  0x00000004U             /*!< PLLM division factor = 4  */
00219 #define RCC_PLLM_DIV5                  0x00000005U             /*!< PLLM division factor = 5  */
00220 #define RCC_PLLM_DIV6                  0x00000006U             /*!< PLLM division factor = 6  */
00221 #define RCC_PLLM_DIV7                  0x00000007U             /*!< PLLM division factor = 7  */
00222 #define RCC_PLLM_DIV8                  0x00000008U             /*!< PLLM division factor = 8  */
00223 #define RCC_PLLM_DIV9                  0x00000009U             /*!< PLLM division factor = 9  */
00224 #define RCC_PLLM_DIV10                 0x0000000AU             /*!< PLLM division factor = 10 */
00225 #define RCC_PLLM_DIV11                 0x0000000BU             /*!< PLLM division factor = 11 */
00226 #define RCC_PLLM_DIV12                 0x0000000CU             /*!< PLLM division factor = 12 */
00227 #define RCC_PLLM_DIV13                 0x0000000DU             /*!< PLLM division factor = 13 */
00228 #define RCC_PLLM_DIV14                 0x0000000EU             /*!< PLLM division factor = 14 */
00229 #define RCC_PLLM_DIV15                 0x0000000FU             /*!< PLLM division factor = 15 */
00230 #define RCC_PLLM_DIV16                 0x00000010U             /*!< PLLM division factor = 16 */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00236   * @{
00237   */
00238 #define RCC_PLLP_DIV2                  0x00000002U             /*!< PLLP division factor = 2  */
00239 #define RCC_PLLP_DIV3                  0x00000003U             /*!< PLLP division factor = 3  */
00240 #define RCC_PLLP_DIV4                  0x00000004U             /*!< PLLP division factor = 4  */
00241 #define RCC_PLLP_DIV5                  0x00000005U             /*!< PLLP division factor = 5  */
00242 #define RCC_PLLP_DIV6                  0x00000006U             /*!< PLLP division factor = 6  */
00243 #define RCC_PLLP_DIV7                  0x00000007U             /*!< PLLP division factor = 7  */
00244 #define RCC_PLLP_DIV8                  0x00000008U             /*!< PLLP division factor = 8  */
00245 #define RCC_PLLP_DIV9                  0x00000009U             /*!< PLLP division factor = 9  */
00246 #define RCC_PLLP_DIV10                 0x0000000AU             /*!< PLLP division factor = 10 */
00247 #define RCC_PLLP_DIV11                 0x0000000BU             /*!< PLLP division factor = 11 */
00248 #define RCC_PLLP_DIV12                 0x0000000CU             /*!< PLLP division factor = 12 */
00249 #define RCC_PLLP_DIV13                 0x0000000DU             /*!< PLLP division factor = 13 */
00250 #define RCC_PLLP_DIV14                 0x0000000EU             /*!< PLLP division factor = 14 */
00251 #define RCC_PLLP_DIV15                 0x0000000FU             /*!< PLLP division factor = 15 */
00252 #define RCC_PLLP_DIV16                 0x00000010U             /*!< PLLP division factor = 16 */
00253 #define RCC_PLLP_DIV17                 0x00000011U             /*!< PLLP division factor = 17 */
00254 #define RCC_PLLP_DIV18                 0x00000012U             /*!< PLLP division factor = 18 */
00255 #define RCC_PLLP_DIV19                 0x00000013U             /*!< PLLP division factor = 19 */
00256 #define RCC_PLLP_DIV20                 0x00000014U             /*!< PLLP division factor = 20 */
00257 #define RCC_PLLP_DIV21                 0x00000015U             /*!< PLLP division factor = 21 */
00258 #define RCC_PLLP_DIV22                 0x00000016U             /*!< PLLP division factor = 22 */
00259 #define RCC_PLLP_DIV23                 0x00000017U             /*!< PLLP division factor = 23 */
00260 #define RCC_PLLP_DIV24                 0x00000018U             /*!< PLLP division factor = 24 */
00261 #define RCC_PLLP_DIV25                 0x00000019U             /*!< PLLP division factor = 25 */
00262 #define RCC_PLLP_DIV26                 0x0000001AU             /*!< PLLP division factor = 26 */
00263 #define RCC_PLLP_DIV27                 0x0000001BU             /*!< PLLP division factor = 27 */
00264 #define RCC_PLLP_DIV28                 0x0000001CU             /*!< PLLP division factor = 28 */
00265 #define RCC_PLLP_DIV29                 0x0000001DU             /*!< PLLP division factor = 29 */
00266 #define RCC_PLLP_DIV30                 0x0000001EU             /*!< PLLP division factor = 30 */
00267 #define RCC_PLLP_DIV31                 0x0000001FU             /*!< PLLP division factor = 31 */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
00273   * @{
00274   */
00275 #define RCC_PLLQ_DIV2                  0x00000002U             /*!< PLLQ division factor = 2 */
00276 #define RCC_PLLQ_DIV4                  0x00000004U             /*!< PLLQ division factor = 4 */
00277 #define RCC_PLLQ_DIV6                  0x00000006U             /*!< PLLQ division factor = 6 */
00278 #define RCC_PLLQ_DIV8                  0x00000008U             /*!< PLLQ division factor = 8 */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
00284   * @{
00285   */
00286 #define RCC_PLLR_DIV2                  0x00000002U             /*!< PLLR division factor = 2 */
00287 #define RCC_PLLR_DIV4                  0x00000004U             /*!< PLLR division factor = 4 */
00288 #define RCC_PLLR_DIV6                  0x00000006U             /*!< PLLR division factor = 6 */
00289 #define RCC_PLLR_DIV8                  0x00000008U             /*!< PLLR division factor = 8 */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00295   * @{
00296   */
00297 #define RCC_PLLSOURCE_NONE             0x00000000U              /*!< No clock selected as PLL entry clock source  */
00298 #define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
00299 #define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
00305   * @{
00306   */
00307 #define RCC_PLL_ADCCLK                 RCC_PLLCFGR_PLLPEN      /*!< PLLADCCLK selection from main PLL */
00308 #define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */
00309 #define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup RCC_System_Clock_Type System Clock Type
00315   * @{
00316   */
00317 #define RCC_CLOCKTYPE_SYSCLK           0x00000001U              /*!< SYSCLK to configure */
00318 #define RCC_CLOCKTYPE_HCLK             0x00000002U              /*!< HCLK to configure */
00319 #define RCC_CLOCKTYPE_PCLK1            0x00000004U              /*!< PCLK1 to configure */
00320 #define RCC_CLOCKTYPE_PCLK2            0x00000008U              /*!< PCLK2 to configure */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RCC_System_Clock_Source System Clock Source
00326   * @{
00327   */
00328 #define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00329 #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00330 #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00336   * @{
00337   */
00338 #define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00339 #define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00340 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00346   * @{
00347   */
00348 #define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00349 #define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00350 #define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00351 #define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00352 #define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00353 #define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00354 #define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00355 #define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00356 #define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
00362   * @{
00363   */
00364 #define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00365 #define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00366 #define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00367 #define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00368 #define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00374   * @{
00375   */
00376 #define RCC_RTCCLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock */
00377 #define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00378 #define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00379 #define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup RCC_MCO_Index MCO Index
00385   * @{
00386   */
00387 /* 32     28      20       16      0
00388    --------------------------------
00389    | MCO   | GPIO  | GPIO  | GPIO  |
00390    | Index |  AF   | Port  |  Pin  |
00391    -------------------------------*/
00392
00393 #define RCC_MCO_GPIOPORT_POS           16U
00394 #define RCC_MCO_GPIOPORT_MASK          (0xFUL << RCC_MCO_GPIOPORT_POS)
00395 #define RCC_MCO_GPIOAF_POS             20U
00396 #define RCC_MCO_GPIOAF_MASK            (0xFFUL << RCC_MCO_GPIOAF_POS)
00397 #define RCC_MCO_INDEX_POS              28U
00398 #define RCC_MCO_INDEX_MASK             (0x1UL << RCC_MCO_INDEX_POS)
00399 #define RCC_MCO1_INDEX                 (0x0UL << RCC_MCO_INDEX_POS)             /*!< MCO1 index */
00400 #define RCC_MCO_PA8                    (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
00401 #define RCC_MCO_PG10                   (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
00402
00403 /* Legacy Defines*/
00404 #define RCC_MCO1                       RCC_MCO_PA8
00405 #define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
00411   * @{
00412   */
00413 #define RCC_MCO1SOURCE_NOCLOCK         0x00000000U                            /*!< MCO1 output disabled, no clock on MCO1 */
00414 #define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00415 #define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
00416 #define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00417 #define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
00418 #define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00419 #define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00420 #define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
00426   * @{
00427   */
00428 #define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */
00429 #define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */
00430 #define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */
00431 #define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */
00432 #define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup RCC_Interrupt Interrupts
00438   * @{
00439   */
00440 #define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
00441 #define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
00442 #define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */
00443 #define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
00444 #define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
00445 #define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00446 #define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00447 #define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup RCC_Flag Flags
00453   *        Elements values convention: XXXYYYYYb
00454   *           - YYYYY  : Flag position in the register
00455   *           - XXX  : Register index
00456   *                 - 001: CR register
00457   *                 - 010: BDCR register
00458   *                 - 011: CSR register
00459   *                 - 100: CRRCR register
00460   * @{
00461   */
00462 /* Flags in the CR register */
00463 #define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
00464 #define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
00465 #define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
00466
00467 /* Flags in the BDCR register */
00468 #define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */
00469 #define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
00470
00471 /* Flags in the CSR register */
00472 #define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)    /*!< LSI Ready flag */
00473 #define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */
00474 #define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< PIN reset flag */
00475 #define RCC_FLAG_BORRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)   /*!< BOR reset flag */
00476 #define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */
00477 #define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Independent Watchdog reset flag */
00478 #define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */
00479 #define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */
00480
00481 /* Flags in the CRRCR register */
00482 #define RCC_FLAG_HSI48RDY              ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
00488   * @{
00489   */
00490 #define RCC_LSEDRIVE_LOW                 0x00000000U            /*!< LSE low drive capability */
00491 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
00492 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
00493 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
00494 /**
00495   * @}
00496   */
00497
00498 /**
00499   * @}
00500   */
00501
00502 /* Exported macros -----------------------------------------------------------*/
00503
00504 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00505   * @{
00506   */
00507
00508 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00509   * @brief  Enable or disable the AHB1 peripheral clock.
00510   * @note   After reset, the peripheral clock (used for registers read/write access)
00511   *         is disabled and the application software has to enable this clock before
00512   *         using it.
00513   * @{
00514   */
00515
00516 #define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
00517                                                  __IO uint32_t tmpreg; \
00518                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
00519                                                  /* Delay after an RCC peripheral clock enabling */ \
00520                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
00521                                                  UNUSED(tmpreg); \
00522                                                } while(0)
00523
00524 #define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
00525                                                  __IO uint32_t tmpreg; \
00526                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
00527                                                  /* Delay after an RCC peripheral clock enabling */ \
00528                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
00529                                                  UNUSED(tmpreg); \
00530                                                } while(0)
00531
00532 #define __HAL_RCC_DMAMUX1_CLK_ENABLE()          do { \
00533                                                  __IO uint32_t tmpreg; \
00534                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
00535                                                  /* Delay after an RCC peripheral clock enabling */ \
00536                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
00537                                                  UNUSED(tmpreg); \
00538                                                } while(0)
00539
00540 #define __HAL_RCC_CORDIC_CLK_ENABLE()            do { \
00541                                                  __IO uint32_t tmpreg; \
00542                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
00543                                                  /* Delay after an RCC peripheral clock enabling */ \
00544                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
00545                                                  UNUSED(tmpreg); \
00546                                                } while(0)
00547
00548 #define __HAL_RCC_FMAC_CLK_ENABLE()              do { \
00549                                                  __IO uint32_t tmpreg; \
00550                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
00551                                                  /* Delay after an RCC peripheral clock enabling */ \
00552                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
00553                                                  UNUSED(tmpreg); \
00554                                                } while(0)
00555
00556 #define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
00557                                                  __IO uint32_t tmpreg; \
00558                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
00559                                                  /* Delay after an RCC peripheral clock enabling */ \
00560                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
00561                                                  UNUSED(tmpreg); \
00562                                                } while(0)
00563
00564 #define __HAL_RCC_CRC_CLK_ENABLE()             do { \
00565                                                  __IO uint32_t tmpreg; \
00566                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
00567                                                  /* Delay after an RCC peripheral clock enabling */ \
00568                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
00569                                                  UNUSED(tmpreg); \
00570                                                } while(0)
00571
00572 #define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
00573
00574 #define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
00575
00576 #define __HAL_RCC_DMAMUX1_CLK_DISABLE()        CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
00577
00578 #define __HAL_RCC_CORDIC_CLK_DISABLE()         CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
00579
00580 #define __HAL_RCC_FMAC_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
00581
00582 #define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
00583
00584 #define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
00585
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
00591   * @brief  Enable or disable the AHB2 peripheral clock.
00592   * @note   After reset, the peripheral clock (used for registers read/write access)
00593   *         is disabled and the application software has to enable this clock before
00594   *         using it.
00595   * @{
00596   */
00597
00598 #define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
00599                                                  __IO uint32_t tmpreg; \
00600                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
00601                                                  /* Delay after an RCC peripheral clock enabling */ \
00602                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
00603                                                  UNUSED(tmpreg); \
00604                                                } while(0)
00605
00606 #define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
00607                                                  __IO uint32_t tmpreg; \
00608                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
00609                                                  /* Delay after an RCC peripheral clock enabling */ \
00610                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
00611                                                  UNUSED(tmpreg); \
00612                                                } while(0)
00613
00614 #define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
00615                                                  __IO uint32_t tmpreg; \
00616                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
00617                                                  /* Delay after an RCC peripheral clock enabling */ \
00618                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
00619                                                  UNUSED(tmpreg); \
00620                                                } while(0)
00621
00622 #define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
00623                                                  __IO uint32_t tmpreg; \
00624                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
00625                                                  /* Delay after an RCC peripheral clock enabling */ \
00626                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
00627                                                  UNUSED(tmpreg); \
00628                                                } while(0)
00629
00630 #define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
00631                                                  __IO uint32_t tmpreg; \
00632                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
00633                                                  /* Delay after an RCC peripheral clock enabling */ \
00634                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
00635                                                  UNUSED(tmpreg); \
00636                                                } while(0)
00637
00638 #define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
00639                                                  __IO uint32_t tmpreg; \
00640                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
00641                                                  /* Delay after an RCC peripheral clock enabling */ \
00642                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
00643                                                  UNUSED(tmpreg); \
00644                                                } while(0)
00645
00646 #define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \
00647                                                  __IO uint32_t tmpreg; \
00648                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
00649                                                  /* Delay after an RCC peripheral clock enabling */ \
00650                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
00651                                                  UNUSED(tmpreg); \
00652                                                } while(0)
00653
00654 #define __HAL_RCC_ADC12_CLK_ENABLE()             do { \
00655                                                  __IO uint32_t tmpreg; \
00656                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
00657                                                  /* Delay after an RCC peripheral clock enabling */ \
00658                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
00659                                                  UNUSED(tmpreg); \
00660                                                } while(0)
00661
00662 #if defined(ADC345_COMMON)
00663 #define __HAL_RCC_ADC345_CLK_ENABLE()             do { \
00664                                                  __IO uint32_t tmpreg; \
00665                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
00666                                                  /* Delay after an RCC peripheral clock enabling */ \
00667                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
00668                                                  UNUSED(tmpreg); \
00669                                                } while(0)
00670 #endif /* ADC345_COMMON */
00671
00672 #define __HAL_RCC_DAC1_CLK_ENABLE()             do { \
00673                                                  __IO uint32_t tmpreg; \
00674                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
00675                                                  /* Delay after an RCC peripheral clock enabling */ \
00676                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
00677                                                  UNUSED(tmpreg); \
00678                                                } while(0)
00679
00680 #if defined(DAC2)
00681 #define __HAL_RCC_DAC2_CLK_ENABLE()             do { \
00682                                                  __IO uint32_t tmpreg; \
00683                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
00684                                                  /* Delay after an RCC peripheral clock enabling */ \
00685                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
00686                                                  UNUSED(tmpreg); \
00687                                                } while(0)
00688 #endif /* DAC2 */
00689
00690 #define __HAL_RCC_DAC3_CLK_ENABLE()             do { \
00691                                                  __IO uint32_t tmpreg; \
00692                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
00693                                                  /* Delay after an RCC peripheral clock enabling */ \
00694                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
00695                                                  UNUSED(tmpreg); \
00696                                                } while(0)
00697
00698 #if defined(DAC4)
00699 #define __HAL_RCC_DAC4_CLK_ENABLE()             do { \
00700                                                  __IO uint32_t tmpreg; \
00701                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
00702                                                  /* Delay after an RCC peripheral clock enabling */ \
00703                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
00704                                                  UNUSED(tmpreg); \
00705                                                } while(0)
00706 #endif /* DAC4 */
00707
00708 #if defined(AES)
00709 #define __HAL_RCC_AES_CLK_ENABLE()             do { \
00710                                                  __IO uint32_t tmpreg; \
00711                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
00712                                                  /* Delay after an RCC peripheral clock enabling */ \
00713                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
00714                                                  UNUSED(tmpreg); \
00715                                                } while(0)
00716 #endif /* AES */
00717
00718 #define __HAL_RCC_RNG_CLK_ENABLE()             do { \
00719                                                  __IO uint32_t tmpreg; \
00720                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
00721                                                  /* Delay after an RCC peripheral clock enabling */ \
00722                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
00723                                                  UNUSED(tmpreg); \
00724                                                } while(0)
00725
00726
00727 #define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
00728
00729 #define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
00730
00731 #define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
00732
00733 #define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
00734
00735 #define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
00736
00737 #define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
00738
00739 #define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
00740
00741 #define __HAL_RCC_ADC12_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
00742
00743 #if defined(ADC345_COMMON)
00744 #define __HAL_RCC_ADC345_CLK_DISABLE()         CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
00745 #endif /* ADC345_COMMON */
00746
00747 #define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
00748
00749 #if defined(DAC2)
00750 #define __HAL_RCC_DAC2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
00751 #endif /* DAC2 */
00752
00753 #define __HAL_RCC_DAC3_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
00754
00755 #if defined(DAC4)
00756 #define __HAL_RCC_DAC4_CLK_DISABLE()           CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
00757 #endif /* DAC4 */
00758
00759 #if defined(AES)
00760 #define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
00761 #endif /* AES */
00762
00763 #define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
00764
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
00770   * @brief  Enable or disable the AHB3 peripheral clock.
00771   * @note   After reset, the peripheral clock (used for registers read/write access)
00772   *         is disabled and the application software has to enable this clock before
00773   *         using it.
00774   * @{
00775   */
00776
00777 #if defined(FMC_BANK1)
00778 #define __HAL_RCC_FMC_CLK_ENABLE()             do { \
00779                                                  __IO uint32_t tmpreg; \
00780                                                  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
00781                                                  /* Delay after an RCC peripheral clock enabling */ \
00782                                                  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
00783                                                  UNUSED(tmpreg); \
00784                                                } while(0)
00785 #endif /* FMC_BANK1 */
00786
00787 #if defined(QUADSPI)
00788 #define __HAL_RCC_QSPI_CLK_ENABLE()            do { \
00789                                                  __IO uint32_t tmpreg; \
00790                                                  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
00791                                                  /* Delay after an RCC peripheral clock enabling */ \
00792                                                  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
00793                                                  UNUSED(tmpreg); \
00794                                                } while(0)
00795 #endif /* QUADSPI */
00796
00797 #if defined(FMC_BANK1)
00798 #define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
00799 #endif /* FMC_BANK1 */
00800
00801 #if defined(QUADSPI)
00802 #define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
00803 #endif /* QUADSPI */
00804
00805 /**
00806   * @}
00807   */
00808
00809 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00810   * @brief  Enable or disable the APB1 peripheral clock.
00811   * @note   After reset, the peripheral clock (used for registers read/write access)
00812   *         is disabled and the application software has to enable this clock before
00813   *         using it.
00814   * @{
00815   */
00816
00817 #define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
00818                                                  __IO uint32_t tmpreg; \
00819                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
00820                                                  /* Delay after an RCC peripheral clock enabling */ \
00821                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
00822                                                  UNUSED(tmpreg); \
00823                                                } while(0)
00824
00825 #define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
00826                                                  __IO uint32_t tmpreg; \
00827                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
00828                                                  /* Delay after an RCC peripheral clock enabling */ \
00829                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
00830                                                  UNUSED(tmpreg); \
00831                                                } while(0)
00832
00833 #define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
00834                                                  __IO uint32_t tmpreg; \
00835                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
00836                                                  /* Delay after an RCC peripheral clock enabling */ \
00837                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
00838                                                  UNUSED(tmpreg); \
00839                                                } while(0)
00840
00841 #if defined(TIM5)
00842 #define __HAL_RCC_TIM5_CLK_ENABLE()            do { \
00843                                                  __IO uint32_t tmpreg; \
00844                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
00845                                                  /* Delay after an RCC peripheral clock enabling */ \
00846                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
00847                                                  UNUSED(tmpreg); \
00848                                                } while(0)
00849 #endif /* TIM5 */
00850
00851 #define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
00852                                                  __IO uint32_t tmpreg; \
00853                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
00854                                                  /* Delay after an RCC peripheral clock enabling */ \
00855                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
00856                                                  UNUSED(tmpreg); \
00857                                                } while(0)
00858
00859 #define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
00860                                                  __IO uint32_t tmpreg; \
00861                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
00862                                                  /* Delay after an RCC peripheral clock enabling */ \
00863                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
00864                                                  UNUSED(tmpreg); \
00865                                                } while(0)
00866
00867 #define __HAL_RCC_CRS_CLK_ENABLE()             do { \
00868                                                  __IO uint32_t tmpreg; \
00869                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
00870                                                  /* Delay after an RCC peripheral clock enabling */ \
00871                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
00872                                                  UNUSED(tmpreg); \
00873                                                } while(0)
00874
00875 #define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \
00876                                                  __IO uint32_t tmpreg; \
00877                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
00878                                                  /* Delay after an RCC peripheral clock enabling */ \
00879                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
00880                                                  UNUSED(tmpreg); \
00881                                                } while(0)
00882
00883 #define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
00884                                                  __IO uint32_t tmpreg; \
00885                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
00886                                                  /* Delay after an RCC peripheral clock enabling */ \
00887                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
00888                                                  UNUSED(tmpreg); \
00889                                                } while(0)
00890
00891 #define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
00892                                                  __IO uint32_t tmpreg; \
00893                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
00894                                                  /* Delay after an RCC peripheral clock enabling */ \
00895                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
00896                                                  UNUSED(tmpreg); \
00897                                                } while(0)
00898
00899 #define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
00900                                                  __IO uint32_t tmpreg; \
00901                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
00902                                                  /* Delay after an RCC peripheral clock enabling */ \
00903                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
00904                                                  UNUSED(tmpreg); \
00905                                                } while(0)
00906
00907 #define __HAL_RCC_USART2_CLK_ENABLE()          do { \
00908                                                  __IO uint32_t tmpreg; \
00909                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
00910                                                  /* Delay after an RCC peripheral clock enabling */ \
00911                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
00912                                                  UNUSED(tmpreg); \
00913                                                } while(0)
00914
00915 #define __HAL_RCC_USART3_CLK_ENABLE()          do { \
00916                                                  __IO uint32_t tmpreg; \
00917                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
00918                                                  /* Delay after an RCC peripheral clock enabling */ \
00919                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
00920                                                  UNUSED(tmpreg); \
00921                                                } while(0)
00922
00923 #if defined(UART4)
00924 #define __HAL_RCC_UART4_CLK_ENABLE()           do { \
00925                                                  __IO uint32_t tmpreg; \
00926                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
00927                                                  /* Delay after an RCC peripheral clock enabling */ \
00928                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
00929                                                  UNUSED(tmpreg); \
00930                                                } while(0)
00931 #endif /* UART4 */
00932
00933 #if defined(UART5)
00934 #define __HAL_RCC_UART5_CLK_ENABLE()           do { \
00935                                                  __IO uint32_t tmpreg; \
00936                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
00937                                                  /* Delay after an RCC peripheral clock enabling */ \
00938                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
00939                                                  UNUSED(tmpreg); \
00940                                                } while(0)
00941 #endif /* UART5 */
00942
00943 #define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
00944                                                  __IO uint32_t tmpreg; \
00945                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
00946                                                  /* Delay after an RCC peripheral clock enabling */ \
00947                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
00948                                                  UNUSED(tmpreg); \
00949                                                } while(0)
00950
00951 #define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
00952                                                  __IO uint32_t tmpreg; \
00953                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
00954                                                  /* Delay after an RCC peripheral clock enabling */ \
00955                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
00956                                                  UNUSED(tmpreg); \
00957                                                } while(0)
00958
00959 #define __HAL_RCC_USB_CLK_ENABLE()            do { \
00960                                                  __IO uint32_t tmpreg; \
00961                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
00962                                                  /* Delay after an RCC peripheral clock enabling */ \
00963                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
00964                                                  UNUSED(tmpreg); \
00965                                                } while(0)
00966
00967 #if defined(FDCAN1)
00968 #define __HAL_RCC_FDCAN_CLK_ENABLE()          do { \
00969                                                  __IO uint32_t tmpreg; \
00970                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
00971                                                  /* Delay after an RCC peripheral clock enabling */ \
00972                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
00973                                                  UNUSED(tmpreg); \
00974                                                } while(0)
00975 #endif /* FDCAN1 */
00976
00977 #define __HAL_RCC_PWR_CLK_ENABLE()            do { \
00978                                                  __IO uint32_t tmpreg; \
00979                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
00980                                                  /* Delay after an RCC peripheral clock enabling */ \
00981                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
00982                                                  UNUSED(tmpreg); \
00983                                                } while(0)
00984
00985 #define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
00986                                                  __IO uint32_t tmpreg; \
00987                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
00988                                                  /* Delay after an RCC peripheral clock enabling */ \
00989                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
00990                                                  UNUSED(tmpreg); \
00991                                                } while(0)
00992
00993 #define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
00994                                                  __IO uint32_t tmpreg; \
00995                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
00996                                                  /* Delay after an RCC peripheral clock enabling */ \
00997                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
00998                                                  UNUSED(tmpreg); \
00999                                                } while(0)
01000
01001 #define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
01002                                                  __IO uint32_t tmpreg; \
01003                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
01004                                                  /* Delay after an RCC peripheral clock enabling */ \
01005                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
01006                                                  UNUSED(tmpreg); \
01007                                                } while(0)
01008
01009 #if defined(I2C4)
01010 #define __HAL_RCC_I2C4_CLK_ENABLE()            do { \
01011                                                  __IO uint32_t tmpreg; \
01012                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
01013                                                  /* Delay after an RCC peripheral clock enabling */ \
01014                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
01015                                                  UNUSED(tmpreg); \
01016                                                } while(0)
01017 #endif /* I2C4 */
01018
01019 #define __HAL_RCC_UCPD1_CLK_ENABLE()           do { \
01020                                                  __IO uint32_t tmpreg; \
01021                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
01022                                                  /* Delay after an RCC peripheral clock enabling */ \
01023                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
01024                                                  UNUSED(tmpreg); \
01025                                                } while(0)
01026
01027 #define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
01028
01029 #define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
01030
01031 #define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
01032
01033 #if defined(TIM5)
01034 #define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
01035 #endif /* TIM5 */
01036
01037 #define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
01038
01039 #define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
01040
01041 #define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
01042
01043 #define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
01044
01045 #define __HAL_RCC_WWDG_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
01046
01047 #define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
01048
01049 #define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
01050
01051 #define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
01052
01053 #define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
01054
01055 #if defined(UART4)
01056 #define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
01057 #endif /* UART4 */
01058
01059 #if defined(UART5)
01060 #define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
01061 #endif /* UART5 */
01062
01063 #define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
01064
01065 #define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
01066
01067 #define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
01068
01069 #if defined(FDCAN1)
01070 #define __HAL_RCC_FDCAN_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
01071 #endif /* FDCAN1 */
01072
01073 #define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
01074
01075 #define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
01076
01077 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
01078
01079 #define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
01080
01081 #if defined(I2C4)
01082 #define __HAL_RCC_I2C4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
01083 #endif /* I2C4 */
01084
01085 #define __HAL_RCC_UCPD1_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
01086
01087 /**
01088   * @}
01089   */
01090
01091 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
01092   * @brief  Enable or disable the APB2 peripheral clock.
01093   * @note   After reset, the peripheral clock (used for registers read/write access)
01094   *         is disabled and the application software has to enable this clock before
01095   *         using it.
01096   * @{
01097   */
01098
01099 #define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
01100                                                  __IO uint32_t tmpreg; \
01101                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
01102                                                  /* Delay after an RCC peripheral clock enabling */ \
01103                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
01104                                                  UNUSED(tmpreg); \
01105                                                } while(0)
01106
01107 #define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
01108                                                  __IO uint32_t tmpreg; \
01109                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
01110                                                  /* Delay after an RCC peripheral clock enabling */ \
01111                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
01112                                                  UNUSED(tmpreg); \
01113                                                } while(0)
01114
01115 #define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
01116                                                  __IO uint32_t tmpreg; \
01117                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
01118                                                  /* Delay after an RCC peripheral clock enabling */ \
01119                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
01120                                                  UNUSED(tmpreg); \
01121                                                } while(0)
01122
01123 #define __HAL_RCC_TIM8_CLK_ENABLE()            do { \
01124                                                  __IO uint32_t tmpreg; \
01125                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
01126                                                  /* Delay after an RCC peripheral clock enabling */ \
01127                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
01128                                                  UNUSED(tmpreg); \
01129                                                } while(0)
01130
01131 #define __HAL_RCC_USART1_CLK_ENABLE()          do { \
01132                                                  __IO uint32_t tmpreg; \
01133                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
01134                                                  /* Delay after an RCC peripheral clock enabling */ \
01135                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
01136                                                  UNUSED(tmpreg); \
01137                                                } while(0)
01138
01139 #if defined(SPI4)
01140 #define __HAL_RCC_SPI4_CLK_ENABLE()            do { \
01141                                                  __IO uint32_t tmpreg; \
01142                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
01143                                                  /* Delay after an RCC peripheral clock enabling */ \
01144                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
01145                                                  UNUSED(tmpreg); \
01146                                                } while(0)
01147 #endif /* SPI4 */
01148
01149 #define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
01150                                                  __IO uint32_t tmpreg; \
01151                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
01152                                                  /* Delay after an RCC peripheral clock enabling */ \
01153                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
01154                                                  UNUSED(tmpreg); \
01155                                                } while(0)
01156
01157 #define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
01158                                                  __IO uint32_t tmpreg; \
01159                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
01160                                                  /* Delay after an RCC peripheral clock enabling */ \
01161                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
01162                                                  UNUSED(tmpreg); \
01163                                                } while(0)
01164
01165 #define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
01166                                                  __IO uint32_t tmpreg; \
01167                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
01168                                                  /* Delay after an RCC peripheral clock enabling */ \
01169                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
01170                                                  UNUSED(tmpreg); \
01171                                                } while(0)
01172
01173 #if defined(TIM20)
01174 #define __HAL_RCC_TIM20_CLK_ENABLE()           do { \
01175                                                  __IO uint32_t tmpreg; \
01176                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
01177                                                  /* Delay after an RCC peripheral clock enabling */ \
01178                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
01179                                                  UNUSED(tmpreg); \
01180                                                } while(0)
01181 #endif /* TIM20 */
01182
01183 #define __HAL_RCC_SAI1_CLK_ENABLE()            do { \
01184                                                  __IO uint32_t tmpreg; \
01185                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
01186                                                  /* Delay after an RCC peripheral clock enabling */ \
01187                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
01188                                                  UNUSED(tmpreg); \
01189                                                } while(0)
01190
01191 #if defined(HRTIM1)
01192 #define __HAL_RCC_HRTIM1_CLK_ENABLE()           do { \
01193                                                  __IO uint32_t tmpreg; \
01194                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
01195                                                  /* Delay after an RCC peripheral clock enabling */ \
01196                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
01197                                                  UNUSED(tmpreg); \
01198                                                } while(0)
01199 #endif /* HRTIM1 */
01200
01201 #define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
01202
01203 #define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
01204
01205 #define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
01206
01207 #define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
01208
01209 #define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
01210
01211 #if defined(SPI4)
01212 #define __HAL_RCC_SPI4_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
01213 #endif /* SPI4 */
01214
01215 #define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
01216
01217 #define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
01218
01219 #define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
01220
01221 #if defined(TIM20)
01222 #define __HAL_RCC_TIM20_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
01223 #endif /* TIM20 */
01224
01225 #define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
01226
01227 #if defined(HRTIM1)
01228 #define __HAL_RCC_HRTIM1_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
01229 #endif /* HRTIM1 */
01230
01231 /**
01232   * @}
01233   */
01234
01235 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
01236   * @brief  Check whether the AHB1 peripheral clock is enabled or not.
01237   * @note   After reset, the peripheral clock (used for registers read/write access)
01238   *         is disabled and the application software has to enable this clock before
01239   *         using it.
01240   * @{
01241   */
01242
01243 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
01244
01245 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
01246
01247 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
01248
01249 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
01250
01251 #define __HAL_RCC_FMAC_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
01252
01253 #define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
01254
01255 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
01256
01257 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
01258
01259 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
01260
01261 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED()    (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
01262
01263 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
01264
01265 #define __HAL_RCC_FMAC_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
01266
01267 #define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
01268
01269 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
01270
01271 /**
01272   * @}
01273   */
01274
01275 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
01276   * @brief  Check whether the AHB2 peripheral clock is enabled or not.
01277   * @note   After reset, the peripheral clock (used for registers read/write access)
01278   *         is disabled and the application software has to enable this clock before
01279   *         using it.
01280   * @{
01281   */
01282
01283 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
01284
01285 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
01286
01287 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
01288
01289 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
01290
01291 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
01292
01293 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
01294
01295 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
01296
01297 #define __HAL_RCC_ADC12_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
01298
01299 #if defined(ADC345_COMMON)
01300 #define __HAL_RCC_ADC345_IS_CLK_ENABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
01301 #endif /* ADC345_COMMON */
01302
01303 #define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
01304
01305 #if defined(DAC2)
01306 #define __HAL_RCC_DAC2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
01307 #endif /* DAC2 */
01308
01309 #define __HAL_RCC_DAC3_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
01310
01311 #if defined(DAC4)
01312 #define __HAL_RCC_DAC4_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
01313 #endif /* DAC4 */
01314
01315 #if defined(AES)
01316 #define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
01317 #endif /* AES */
01318
01319 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
01320
01321
01322 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
01323
01324 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
01325
01326 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
01327
01328 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
01329
01330 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
01331
01332 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
01333
01334 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
01335
01336 #define __HAL_RCC_ADC12_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
01337
01338 #if defined(ADC345_COMMON)
01339 #define __HAL_RCC_ADC345_IS_CLK_DISABLED()     (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
01340 #endif /* ADC345_COMMON */
01341
01342 #define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
01343
01344 #if defined(DAC2)
01345 #define __HAL_RCC_DAC2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
01346 #endif /* DAC2 */
01347
01348 #define __HAL_RCC_DAC3_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
01349
01350 #if defined(DAC4)
01351 #define __HAL_RCC_DAC4_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
01352 #endif /* DAC4 */
01353
01354 #if defined(AES)
01355 #define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
01356 #endif /* AES */
01357
01358 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
01359
01360 /**
01361   * @}
01362   */
01363
01364 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
01365   * @brief  Check whether the AHB3 peripheral clock is enabled or not.
01366   * @note   After reset, the peripheral clock (used for registers read/write access)
01367   *         is disabled and the application software has to enable this clock before
01368   *         using it.
01369   * @{
01370   */
01371
01372 #if defined(FMC_BANK1)
01373 #define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
01374 #endif /* FMC_BANK1 */
01375
01376 #if defined(QUADSPI)
01377 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
01378 #endif /* QUADSPI */
01379
01380 #if defined(FMC_BANK1)
01381 #define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
01382 #endif /* FMC_BANK1 */
01383
01384 #if defined(QUADSPI)
01385 #define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
01386 #endif /* QUADSPI */
01387
01388 /**
01389   * @}
01390   */
01391
01392 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
01393   * @brief  Check whether the APB1 peripheral clock is enabled or not.
01394   * @note   After reset, the peripheral clock (used for registers read/write access)
01395   *         is disabled and the application software has to enable this clock before
01396   *         using it.
01397   * @{
01398   */
01399
01400 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
01401
01402 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
01403
01404 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
01405
01406 #if defined(TIM5)
01407 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
01408 #endif /* TIM5 */
01409
01410 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
01411
01412 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
01413
01414 #define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
01415
01416 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
01417
01418 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
01419
01420 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
01421
01422 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
01423
01424 #define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
01425
01426 #define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
01427
01428 #if defined(UART4)
01429 #define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
01430 #endif /* UART4 */
01431
01432 #if defined(UART5)
01433 #define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
01434 #endif /* UART5 */
01435
01436 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
01437
01438 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
01439
01440 #define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
01441
01442 #if defined(FDCAN1)
01443 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
01444 #endif /* FDCAN1 */
01445
01446 #define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
01447
01448 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
01449
01450 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
01451
01452 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
01453
01454 #if defined(I2C4)
01455 #define __HAL_RCC_I2C4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
01456 #endif /* I2C4 */
01457
01458 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
01459
01460 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
01461
01462 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
01463
01464 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
01465
01466 #if defined(TIM5)
01467 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
01468 #endif /* TIM5 */
01469
01470 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
01471
01472 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
01473
01474 #define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
01475
01476 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
01477
01478 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
01479
01480 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
01481
01482 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
01483
01484 #define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
01485
01486 #define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
01487
01488 #if defined(UART4)
01489 #define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
01490 #endif /* UART4 */
01491
01492 #if defined(UART5)
01493 #define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
01494 #endif /* UART5 */
01495
01496 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
01497
01498 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
01499
01500 #if defined(USB)
01501 #define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
01502 #endif /* USB */
01503
01504 #if defined(FDCAN1)
01505 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
01506 #endif /* FDCAN1 */
01507
01508 #define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
01509
01510 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
01511
01512 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
01513
01514 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
01515
01516 #if defined(I2C4)
01517 #define __HAL_RCC_I2C4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
01518 #endif /* I2C4 */
01519
01520 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
01521
01522 /**
01523   * @}
01524   */
01525
01526 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
01527   * @brief  Check whether the APB2 peripheral clock is enabled or not.
01528   * @note   After reset, the peripheral clock (used for registers read/write access)
01529   *         is disabled and the application software has to enable this clock before
01530   *         using it.
01531   * @{
01532   */
01533
01534 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
01535
01536 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
01537
01538 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
01539
01540 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
01541
01542 #define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
01543
01544 #if defined(SPI4)
01545 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
01546 #endif /* SPI4 */
01547
01548 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
01549
01550 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
01551
01552 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
01553
01554 #if defined(TIM20)
01555 #define __HAL_RCC_TIM20_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
01556 #endif /* TIM20 */
01557
01558 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
01559
01560 #if defined(HRTIM1)
01561 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
01562 #endif /* HRTIM1 */
01563
01564
01565 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
01566
01567 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
01568
01569 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
01570
01571 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
01572
01573 #define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
01574
01575 #if defined(SPI4)
01576 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
01577 #endif /* SPI4 */
01578
01579 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
01580
01581 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
01582
01583 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
01584
01585 #if defined(TIM20)
01586 #define __HAL_RCC_TIM20_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
01587 #endif /* TIM20 */
01588
01589 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
01590
01591 #if defined(HRTIM1)
01592 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
01593 #endif /* HRTIM1 */
01594
01595 /**
01596   * @}
01597   */
01598
01599 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
01600   * @brief  Force or release AHB1 peripheral reset.
01601   * @{
01602   */
01603 #define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
01604
01605 #define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
01606
01607 #define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
01608
01609 #define __HAL_RCC_DMAMUX1_FORCE_RESET()        SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
01610
01611 #define __HAL_RCC_CORDIC_FORCE_RESET()         SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
01612
01613 #define __HAL_RCC_FMAC_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
01614
01615 #define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
01616
01617 #define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
01618
01619
01620 #define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
01621
01622 #define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
01623
01624 #define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
01625
01626 #define __HAL_RCC_DMAMUX1_RELEASE_RESET()      CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
01627
01628 #define __HAL_RCC_CORDIC_RELEASE_RESET()       CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
01629
01630 #define __HAL_RCC_FMAC_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
01631
01632 #define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
01633
01634 #define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
01635
01636 /**
01637   * @}
01638   */
01639
01640 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
01641   * @brief  Force or release AHB2 peripheral reset.
01642   * @{
01643   */
01644 #define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
01645
01646 #define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
01647
01648 #define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
01649
01650 #define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
01651
01652 #define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
01653
01654 #define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
01655
01656 #define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
01657
01658 #define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
01659
01660 #define __HAL_RCC_ADC12_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
01661
01662 #if defined(ADC345_COMMON)
01663 #define __HAL_RCC_ADC345_FORCE_RESET()         SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
01664 #endif /* ADC345_COMMON */
01665
01666 #define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
01667
01668 #if defined(DAC2)
01669 #define __HAL_RCC_DAC2_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
01670 #endif /* DAC2 */
01671
01672 #define __HAL_RCC_DAC3_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
01673
01674 #if defined(DAC4)
01675 #define __HAL_RCC_DAC4_FORCE_RESET()           SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
01676 #endif /* DAC4 */
01677
01678 #if defined(AES)
01679 #define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
01680 #endif /* AES */
01681
01682 #define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
01683
01684
01685 #define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
01686
01687 #define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
01688
01689 #define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
01690
01691 #define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
01692
01693 #define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
01694
01695 #define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
01696
01697 #define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
01698
01699 #define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
01700
01701 #define __HAL_RCC_ADC12_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
01702
01703 #if defined(ADC345_COMMON)
01704 #define __HAL_RCC_ADC345_RELEASE_RESET()       CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
01705 #endif /* ADC345_COMMON */
01706
01707 #define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
01708
01709 #if defined(DAC2)
01710 #define __HAL_RCC_DAC2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
01711 #endif /* DAC2 */
01712
01713 #define __HAL_RCC_DAC3_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
01714
01715 #if defined(DAC4)
01716 #define __HAL_RCC_DAC4_RELEASE_RESET()         CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
01717 #endif /* DAC4 */
01718
01719 #if defined(AES)
01720 #define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
01721 #endif /* AES */
01722
01723 #define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
01724
01725 /**
01726   * @}
01727   */
01728
01729 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
01730   * @brief  Force or release AHB3 peripheral reset.
01731   * @{
01732   */
01733 #define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
01734
01735 #if defined(FMC_BANK1)
01736 #define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
01737 #endif /* FMC_BANK1 */
01738
01739 #if defined(QUADSPI)
01740 #define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
01741 #endif /* QUADSPI */
01742
01743 #define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
01744
01745 #if defined(FMC_BANK1)
01746 #define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
01747 #endif /* FMC_BANK1 */
01748
01749 #if defined(QUADSPI)
01750 #define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
01751 #endif /* QUADSPI */
01752
01753 /**
01754   * @}
01755   */
01756
01757 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
01758   * @brief  Force or release APB1 peripheral reset.
01759   * @{
01760   */
01761 #define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
01762
01763 #define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
01764
01765 #define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
01766
01767 #define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
01768
01769 #if defined(TIM5)
01770 #define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
01771 #endif /* TIM5 */
01772
01773 #define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
01774
01775 #define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
01776
01777 #define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
01778
01779 #define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
01780
01781 #define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
01782
01783 #define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
01784
01785 #define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
01786
01787 #if defined(UART4)
01788 #define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
01789 #endif /* UART4 */
01790
01791 #if defined(UART5)
01792 #define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
01793 #endif /* UART5 */
01794
01795 #define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
01796
01797 #define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
01798
01799 #define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
01800
01801 #if defined(FDCAN1)
01802 #define __HAL_RCC_FDCAN_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
01803 #endif /* FDCAN1 */
01804
01805 #define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
01806
01807 #define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
01808
01809 #define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
01810
01811 #define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
01812
01813 #if defined(I2C4)
01814 #define __HAL_RCC_I2C4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
01815 #endif /* I2C4 */
01816
01817 #define __HAL_RCC_UCPD1_FORCE_RESET()          SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
01818
01819 #define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
01820
01821 #define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
01822
01823 #define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
01824
01825 #define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
01826
01827 #if defined(TIM5)
01828 #define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
01829 #endif /* TIM5 */
01830
01831 #define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
01832
01833 #define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
01834
01835 #define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
01836
01837 #define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
01838
01839 #define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
01840
01841 #define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
01842
01843 #define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
01844
01845 #if defined(UART4)
01846 #define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
01847 #endif /* UART4 */
01848
01849 #if defined(UART5)
01850 #define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
01851 #endif /* UART5 */
01852
01853 #define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
01854
01855 #define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
01856
01857 #define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
01858
01859 #if defined(FDCAN1)
01860 #define __HAL_RCC_FDCAN_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
01861 #endif /* FDCAN1 */
01862
01863 #define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
01864
01865 #define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
01866
01867 #define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
01868
01869 #define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
01870
01871 #if defined(I2C4)
01872 #define __HAL_RCC_I2C4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
01873 #endif /* I2C4 */
01874
01875 #define __HAL_RCC_UCPD1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
01876
01877 /**
01878   * @}
01879   */
01880
01881 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
01882   * @brief  Force or release APB2 peripheral reset.
01883   * @{
01884   */
01885 #define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
01886
01887 #define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
01888
01889 #define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
01890
01891 #define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
01892
01893 #define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
01894
01895 #define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
01896
01897 #if defined(SPI4)
01898 #define __HAL_RCC_SPI4_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
01899 #endif /* SPI4 */
01900
01901 #define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
01902
01903 #define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
01904
01905 #define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
01906
01907 #if defined(TIM20)
01908 #define __HAL_RCC_TIM20_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
01909 #endif /* TIM20 */
01910
01911 #define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
01912
01913 #if defined(HRTIM1)
01914 #define __HAL_RCC_HRTIM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
01915 #endif /* HRTIM1 */
01916
01917
01918 #define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)
01919
01920 #define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
01921
01922 #define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
01923
01924 #define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
01925
01926 #define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
01927
01928 #define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
01929
01930 #if defined(SPI4)
01931 #define __HAL_RCC_SPI4_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
01932 #endif /* SPI4 */
01933
01934 #define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
01935
01936 #define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
01937
01938 #define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
01939
01940 #if defined(TIM20)
01941 #define __HAL_RCC_TIM20_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
01942 #endif /* TIM20 */
01943
01944 #define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
01945
01946 #if defined(HRTIM1)
01947 #define __HAL_RCC_HRTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
01948 #endif /* HRTIM1 */
01949
01950 /**
01951   * @}
01952   */
01953
01954 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
01955   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
01956   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01957   *         power consumption.
01958   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01959   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01960   * @{
01961   */
01962
01963 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
01964
01965 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
01966
01967 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
01968
01969 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
01970
01971 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
01972
01973 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
01974
01975 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
01976
01977 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
01978
01979
01980 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
01981
01982 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
01983
01984 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
01985
01986 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
01987
01988 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
01989
01990 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
01991
01992 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
01993
01994 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
01995
01996 /**
01997   * @}
01998   */
01999
02000 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
02001   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
02002   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02003   *         power consumption.
02004   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02005   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02006   * @{
02007   */
02008
02009 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
02010
02011 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
02012
02013 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
02014
02015 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
02016
02017 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
02018
02019 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
02020
02021 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
02022
02023 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
02024
02025 #define __HAL_RCC_CCM_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
02026
02027 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
02028
02029 #if defined(ADC345_COMMON)
02030 #define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
02031 #endif /* ADC345_COMMON */
02032
02033 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
02034
02035 #if defined(DAC2)
02036 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
02037 #endif /* DAC2 */
02038
02039 #define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
02040
02041 #if defined(DAC4)
02042 #define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
02043 #endif /* DAC4 */
02044
02045 #if defined(AES)
02046 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
02047 #endif /* AES */
02048
02049 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
02050
02051
02052 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
02053
02054 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
02055
02056 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
02057
02058 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
02059
02060 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
02061
02062 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
02063
02064 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
02065
02066 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
02067
02068 #define __HAL_RCC_CCM_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
02069
02070 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
02071
02072 #if defined(ADC345_COMMON)
02073 #define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
02074 #endif /* ADC345_COMMON */
02075
02076 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
02077
02078 #if defined(DAC2)
02079 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
02080 #endif /* DAC2 */
02081
02082 #define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
02083
02084 #if defined(DAC4)
02085 #define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
02086 #endif /* DAC4 */
02087
02088 #if defined(AES)
02089 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
02090 #endif /* AES */
02091
02092 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
02093
02094 /**
02095   * @}
02096   */
02097
02098 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
02099   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
02100   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02101   *         power consumption.
02102   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02103   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02104   * @{
02105   */
02106
02107 #if defined(FMC_BANK1)
02108 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
02109 #endif /* FMC_BANK1 */
02110
02111 #if defined(QUADSPI)
02112 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
02113 #endif /* QUADSPI */
02114
02115 #if defined(FMC_BANK1)
02116 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
02117 #endif /* FMC_BANK1 */
02118
02119 #if defined(QUADSPI)
02120 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
02121 #endif /* QUADSPI */
02122
02123 /**
02124   * @}
02125   */
02126
02127 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
02128   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
02129   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02130   *         power consumption.
02131   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02132   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02133   * @{
02134   */
02135
02136 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
02137
02138 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
02139
02140 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
02141
02142 #if defined(TIM5)
02143 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
02144 #endif /* TIM5 */
02145
02146 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
02147
02148 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
02149
02150 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
02151
02152 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
02153
02154 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
02155
02156 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
02157
02158 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
02159
02160 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
02161
02162 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
02163
02164 #if defined(UART4)
02165 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
02166 #endif /* UART4 */
02167
02168 #if defined(UART5)
02169 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
02170 #endif /* UART5 */
02171
02172 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
02173
02174 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
02175
02176 #if defined(USB)
02177 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
02178 #endif /* USB */
02179
02180 #if defined(FDCAN1)
02181 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
02182 #endif /* FDCAN1 */
02183
02184 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
02185
02186 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
02187
02188 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
02189
02190 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
02191
02192 #if defined(I2C4)
02193 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
02194 #endif /* I2C4 */
02195
02196 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
02197
02198
02199 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
02200
02201 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
02202
02203 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
02204
02205 #if defined(TIM5)
02206 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
02207 #endif /* TIM5 */
02208
02209 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
02210
02211 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
02212
02213 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
02214
02215 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
02216
02217 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
02218
02219 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
02220
02221 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
02222
02223 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
02224
02225 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
02226
02227 #if defined(UART4)
02228 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
02229 #endif /* UART4 */
02230
02231 #if defined(UART5)
02232 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
02233 #endif /* UART5 */
02234
02235 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
02236
02237 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
02238
02239 #if defined(USB)
02240 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
02241 #endif /* USB */
02242
02243 #if defined(FDCAN1)
02244 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
02245 #endif /* FDCAN1 */
02246
02247 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
02248
02249 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
02250
02251 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
02252
02253 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
02254
02255 #if defined(I2C4)
02256 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
02257 #endif /* I2C4 */
02258
02259 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
02260
02261 /**
02262   * @}
02263   */
02264
02265 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
02266   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02267   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02268   *         power consumption.
02269   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02270   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02271   * @{
02272   */
02273
02274 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
02275
02276 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
02277
02278 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
02279
02280 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
02281
02282 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
02283
02284 #if defined(SPI4)
02285 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
02286 #endif /* SPI4 */
02287
02288 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
02289
02290 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
02291
02292 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
02293
02294 #if defined(TIM20)
02295 #define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
02296 #endif /* TIM20 */
02297
02298 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
02299
02300 #if defined(HRTIM1)
02301 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
02302 #endif /* HRTIM1 */
02303
02304
02305 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
02306
02307 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
02308
02309 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
02310
02311 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
02312
02313 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
02314
02315 #if defined(SPI4)
02316 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
02317 #endif /* SPI4 */
02318
02319 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
02320
02321 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
02322
02323 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
02324
02325 #if defined(TIM20)
02326 #define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
02327 #endif /* TIM20 */
02328
02329 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
02330
02331 #if defined(HRTIM1)
02332 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
02333 #endif /* HRTIM1 */
02334
02335 /**
02336   * @}
02337   */
02338
02339 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
02340   * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02341   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02342   *         power consumption.
02343   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02344   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02345   * @{
02346   */
02347
02348 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
02349
02350 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
02351
02352 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
02353
02354 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
02355
02356 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
02357
02358 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
02359
02360 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
02361
02362 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
02363
02364
02365 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
02366
02367 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
02368
02369 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
02370
02371 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
02372
02373 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
02374
02375 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
02376
02377 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
02378
02379 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
02380
02381 /**
02382   * @}
02383   */
02384
02385 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
02386   * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02387   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02388   *         power consumption.
02389   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02390   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02391   * @{
02392   */
02393
02394 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
02395
02396 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
02397
02398 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
02399
02400 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
02401
02402 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
02403
02404 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
02405
02406 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
02407
02408 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
02409
02410 #define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
02411
02412 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
02413
02414 #if defined(ADC345_COMMON)
02415 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
02416 #endif /* ADC345_COMMON */
02417
02418 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
02419
02420 #if defined(DAC2)
02421 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
02422 #endif /* DAC2 */
02423
02424 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
02425
02426 #if defined(DAC4)
02427 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
02428 #endif /* DAC4 */
02429
02430 #if defined(AES)
02431 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
02432 #endif /* AES */
02433
02434 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
02435
02436
02437 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
02438
02439 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
02440
02441 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
02442
02443 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
02444
02445 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
02446
02447 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
02448
02449 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
02450
02451 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
02452
02453 #define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
02454
02455 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
02456
02457 #if defined(ADC345_COMMON)
02458 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
02459 #endif /* ADC345_COMMON */
02460
02461 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
02462
02463 #if defined(DAC2)
02464 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
02465 #endif /* DAC2 */
02466
02467 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
02468
02469 #if defined(DAC4)
02470 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
02471 #endif /* DAC4 */
02472
02473 #if defined(AES)
02474 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
02475 #endif /* AES */
02476
02477 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
02478
02479 /**
02480   * @}
02481   */
02482
02483 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
02484   * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
02485   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02486   *         power consumption.
02487   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02488   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02489   * @{
02490   */
02491
02492 #if defined(FMC_BANK1)
02493 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
02494 #endif /* FMC_BANK1 */
02495
02496 #if defined(QUADSPI)
02497 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
02498 #endif /* QUADSPI */
02499
02500 #if defined(FMC_BANK1)
02501 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
02502 #endif /* FMC_BANK1 */
02503
02504 #if defined(QUADSPI)
02505 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
02506 #endif /* QUADSPI */
02507
02508 /**
02509   * @}
02510   */
02511
02512 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
02513   * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02514   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02515   *         power consumption.
02516   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02517   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02518   * @{
02519   */
02520
02521 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
02522
02523 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
02524
02525 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
02526
02527 #if defined(TIM5)
02528 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
02529 #endif /* TIM5 */
02530
02531 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
02532
02533 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
02534
02535 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
02536
02537 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
02538
02539 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
02540
02541 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
02542
02543 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
02544
02545 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
02546
02547 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
02548
02549 #if defined(UART4)
02550 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
02551 #endif /* UART4 */
02552
02553 #if defined(UART5)
02554 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
02555 #endif /* UART5 */
02556
02557 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
02558
02559 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
02560
02561 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
02562
02563 #if defined(FDCAN1)
02564 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
02565 #endif /* FDCAN1 */
02566
02567 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
02568
02569 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
02570
02571 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
02572
02573 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
02574
02575 #if defined(I2C4)
02576 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
02577 #endif /* I2C4 */
02578
02579 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
02580
02581
02582 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
02583
02584 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
02585
02586 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
02587
02588 #if defined(TIM5)
02589 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
02590 #endif /* TIM5 */
02591
02592 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
02593
02594 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
02595
02596 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
02597
02598 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
02599
02600 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
02601
02602 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
02603
02604 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
02605
02606 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
02607
02608 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
02609
02610 #if defined(UART4)
02611 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
02612 #endif /* UART4 */
02613
02614 #if defined(UART5)
02615 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
02616 #endif /* UART5 */
02617
02618 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
02619
02620 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
02621
02622 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
02623
02624 #if defined(FDCAN1)
02625 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
02626 #endif /* FDCAN1 */
02627
02628 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
02629
02630 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
02631
02632 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
02633
02634 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
02635
02636 #if defined(I2C4)
02637 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
02638 #endif /* I2C4 */
02639
02640 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
02641
02642 /**
02643   * @}
02644   */
02645
02646 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
02647   * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02648   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02649   *         power consumption.
02650   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02651   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02652   * @{
02653   */
02654
02655 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
02656
02657 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
02658
02659 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
02660
02661 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
02662
02663 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
02664
02665 #if defined(SPI4)
02666 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
02667 #endif /* SPI4 */
02668
02669 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
02670
02671 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
02672
02673 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
02674
02675 #if defined(TIM20)
02676 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
02677 #endif /* TIM20 */
02678
02679 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
02680
02681 #if defined(HRTIM1)
02682 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
02683 #endif /* HRTIM1 */
02684
02685
02686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
02687
02688 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
02689
02690 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
02691
02692 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
02693
02694 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
02695
02696 #if defined(SPI4)
02697 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
02698 #endif /* SPI4 */
02699
02700 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
02701
02702 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
02703
02704 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
02705
02706 #if defined(TIM20)
02707 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
02708 #endif /* TIM20 */
02709
02710 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
02711
02712 #if defined(HRTIM1)
02713 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
02714 #endif /* HRTIM1 */
02715
02716
02717 /**
02718   * @}
02719   */
02720
02721 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
02722   * @{
02723   */
02724
02725 /** @brief  Macros to force or release the Backup domain reset.
02726   * @note   This function resets the RTC peripheral (including the backup registers)
02727   *         and the RTC clock source selection in RCC_CSR register.
02728   * @note   The BKPSRAM is not affected by this reset.
02729   * @retval None
02730   */
02731 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02732
02733 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02734
02735 /**
02736   * @}
02737   */
02738
02739 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
02740   * @{
02741   */
02742
02743 /** @brief  Macros to enable or disable the RTC clock.
02744   * @note   As the RTC is in the Backup domain and write access is denied to
02745   *         this domain after reset, you have to enable write access using
02746   *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
02747   *         (to be done once after reset).
02748   * @note   These macros must be used after the RTC clock source was selected.
02749   * @retval None
02750   */
02751 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02752
02753 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02754
02755 /**
02756   * @}
02757   */
02758
02759 /** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
02760   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
02761   *         It is used (enabled by hardware) as system clock source after startup
02762   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
02763   *         of the HSE used directly or indirectly as system clock (if the Clock
02764   *         Security System CSS is enabled).
02765   * @note   HSI can not be stopped if it is used as system clock source. In this case,
02766   *         you have to select another source of the system clock then stop the HSI.
02767   * @note   After enabling the HSI, the application software should wait on HSIRDY
02768   *         flag to be set indicating that HSI clock is stable and can be used as
02769   *         system clock source.
02770   *         This parameter can be: ENABLE or DISABLE.
02771   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
02772   *         clock cycles.
02773   * @retval None
02774   */
02775 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
02776
02777 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
02778
02779 /** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
02780   * @note   The calibration is used to compensate for the variations in voltage
02781   *         and temperature that influence the frequency of the internal HSI RC.
02782   * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
02783   *         (default is RCC_HSICALIBRATION_DEFAULT).
02784   *         This parameter must be a number between 0 and 0x7F.
02785   * @retval None
02786   */
02787 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
02788                   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
02789
02790 /**
02791   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
02792   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
02793   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
02794   *           speed because of the HSI startup time.
02795   * @note     The enable of this function has not effect on the HSION bit.
02796   *           This parameter can be: ENABLE or DISABLE.
02797   * @retval None
02798   */
02799 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
02800
02801 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
02802
02803 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
02804   * @note   After enabling the LSI, the application software should wait on
02805   *         LSIRDY flag to be set indicating that LSI clock is stable and can
02806   *         be used to clock the IWDG and/or the RTC.
02807   * @note   LSI can not be disabled if the IWDG is running.
02808   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
02809   *         clock cycles.
02810   * @retval None
02811   */
02812 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
02813
02814 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
02815
02816 /**
02817   * @brief  Macro to configure the External High Speed oscillator (HSE).
02818   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
02819   *         supported by this macro. User should request a transition to HSE Off
02820   *         first and then HSE On or HSE Bypass.
02821   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
02822   *         software should wait on HSERDY flag to be set indicating that HSE clock
02823   *         is stable and can be used to clock the PLL and/or system clock.
02824   * @note   HSE state can not be changed if it is used directly or through the
02825   *         PLL as system clock. In this case, you have to select another source
02826   *         of the system clock then change the HSE state (ex. disable it).
02827   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
02828   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
02829   *         was previously enabled you have to enable it again after calling this
02830   *         function.
02831   * @param  __STATE__ specifies the new state of the HSE.
02832   *         This parameter can be one of the following values:
02833   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
02834   *                                   6 HSE oscillator clock cycles.
02835   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
02836   *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
02837   * @retval None
02838   */
02839 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                    \
02840                     do {                                                   \
02841                       if((__STATE__) == RCC_HSE_ON)                        \
02842                       {                                                    \
02843                         SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
02844                       }                                                    \
02845                       else if((__STATE__) == RCC_HSE_BYPASS)               \
02846                       {                                                    \
02847                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                   \
02848                         SET_BIT(RCC->CR, RCC_CR_HSEON);                    \
02849                       }                                                    \
02850                       else                                                 \
02851                       {                                                    \
02852                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                  \
02853                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                 \
02854                       }                                                    \
02855                     } while(0)
02856
02857 /**
02858   * @brief  Macro to configure the External Low Speed oscillator (LSE).
02859   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
02860   *         supported by this macro. User should request a transition to LSE Off
02861   *         first and then LSE On or LSE Bypass.
02862   * @note   As the LSE is in the Backup domain and write access is denied to
02863   *         this domain after reset, you have to enable write access using
02864   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02865   *         (to be done once after reset).
02866   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
02867   *         software should wait on LSERDY flag to be set indicating that LSE clock
02868   *         is stable and can be used to clock the RTC.
02869   * @param  __STATE__ specifies the new state of the LSE.
02870   *         This parameter can be one of the following values:
02871   *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
02872   *                                   6 LSE oscillator clock cycles.
02873   *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
02874   *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
02875   * @retval None
02876   */
02877 #define __HAL_RCC_LSE_CONFIG(__STATE__)                                        \
02878                     do {                                                       \
02879                       if((__STATE__) == RCC_LSE_ON)                            \
02880                       {                                                        \
02881                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
02882                       }                                                        \
02883                       else if((__STATE__) == RCC_LSE_BYPASS)                   \
02884                       {                                                        \
02885                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                   \
02886                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                    \
02887                       }                                                        \
02888                       else                                                     \
02889                       {                                                        \
02890                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                  \
02891                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                 \
02892                       }                                                        \
02893                     } while(0)
02894
02895 /** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
02896   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
02897   * @note   After enabling the HSI48, the application software should wait on HSI48RDY
02898   *         flag to be set indicating that HSI48 clock is stable.
02899   *         This parameter can be: ENABLE or DISABLE.
02900   * @retval None
02901   */
02902 #define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
02903
02904 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
02905
02906 /** @brief  Macros to configure the RTC clock (RTCCLK).
02907   * @note   As the RTC clock configuration bits are in the Backup domain and write
02908   *         access is denied to this domain after reset, you have to enable write
02909   *         access using the Power Backup Access macro before to configure
02910   *         the RTC clock source (to be done once after reset).
02911   * @note   Once the RTC clock is configured it cannot be changed unless the
02912   *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
02913   *         a Power On Reset (POR).
02914   *
02915   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
02916   *         This parameter can be one of the following values:
02917   *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.
02918   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02919   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02920   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02921   *
02922   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
02923   *         work in STOP and STANDBY modes, and can be used as wakeup source.
02924   *         However, when the HSE clock is used as RTC clock source, the RTC
02925   *         cannot be used in STOP and STANDBY modes.
02926   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
02927   *         RTC clock source).
02928   * @retval None
02929   */
02930 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
02931                   MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
02932
02933
02934 /** @brief  Macro to get the RTC clock source.
02935   * @retval The returned value can be one of the following:
02936   *            @arg @ref RCC_RTCCLKSOURCE_NONE  No clock selected as RTC clock.
02937   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02938   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02939   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02940   */
02941 #define  __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
02942
02943 /** @brief  Macros to enable or disable the main PLL.
02944   * @note   After enabling the main PLL, the application software should wait on
02945   *         PLLRDY flag to be set indicating that PLL clock is stable and can
02946   *         be used as system clock source.
02947   * @note   The main PLL can not be disabled if it is used as system clock source
02948   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
02949   * @retval None
02950   */
02951 #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
02952
02953 #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
02954
02955 /** @brief  Macro to configure the PLL clock source.
02956   * @note   This function must be used only when the main PLL is disabled.
02957   * @param  __PLLSOURCE__ specifies the PLL entry clock source.
02958   *         This parameter can be one of the following values:
02959   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02960   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02961   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02962   * @retval None
02963   *
02964   */
02965 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
02966                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
02967
02968 /** @brief  Macro to configure the PLL source division factor M.
02969   * @note   This function must be used only when the main PLL is disabled.
02970   * @param  __PLLM__ specifies the division factor for PLL VCO input clock
02971   *         This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
02972   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02973   *         frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
02974   *         of 8 MHz to limit PLL jitter.
02975   * @retval None
02976   *
02977   */
02978 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
02979                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
02980
02981 /**
02982   * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
02983   * @note   This macro must be used only when the main PLL is disabled.
02984   * @note   This macro preserves the PLL's output clocks enable state.
02985   *
02986   * @param  __PLLSOURCE__ specifies the PLL entry clock source.
02987   *          This parameter can be one of the following values:
02988   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02989   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02990   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02991   *
02992   * @param  __PLLM__ specifies the division factor for PLL VCO input clock.
02993   *          This parameter must be a value of @ref RCC_PLLM_Clock_Divider
02994   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02995   *         frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
02996   *         of 8 MHz to limit PLL jitter.
02997   *
02998   * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock.
02999   *          This parameter must be a number between 8 and 127.
03000   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
03001   *         output frequency is between 64 and 344 MHz.
03002   *
03003   * @param  __PLLP__ specifies the division factor for SAI clock.
03004   *          This parameter must be a number in the range (2 to 31).
03005   *
03006   * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
03007   *          This parameter must be in the range (2, 4, 6 or 8).
03008   * @note   If the USB OTG FS is used in your application, you have to set the
03009   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
03010   *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
03011   *         correctly.
03012   * @param  __PLLR__ specifies the division factor for the main system clock.
03013   * @note   You have to set the PLLR parameter correctly to not exceed 170MHZ.
03014   *          This parameter must be in the range (2, 4, 6 or 8).
03015   * @retval None
03016   */
03017 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
03018                   MODIFY_REG(RCC->PLLCFGR, \
03019                              (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
03020                               RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
03021                              ((__PLLSOURCE__) | \
03022                               (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
03023                               ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
03024                               ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
03025                               ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
03026                               ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
03027
03028 /** @brief  Macro to get the oscillator used as PLL clock source.
03029   * @retval The oscillator used as PLL clock source. The returned value can be one
03030   *         of the following:
03031   *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
03032   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
03033   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
03034   */
03035 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
03036
03037 /**
03038   * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
03039   * @note   Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime
03040   *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
03041   *         be stopped if used as System Clock.
03042   * @param  __PLLCLOCKOUT__ specifies the PLL clock to be output.
03043   *          This parameter can be one or a combination of the following values:
03044   *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate a clock on ADC.
03045   *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB (48 MHz),
03046   *                                   FDCAN (<=48 MHz) and QSPI (<=48 MHz).
03047   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 170MHz)
03048   * @retval None
03049   */
03050 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03051
03052 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03053
03054 /**
03055   * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
03056   * @param  __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
03057   *          This parameter can be one of the following values:
03058   *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate a clock on ADC.
03059   *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB (48 MHz),
03060   *                                   FDCAN (<=48 MHz) and QSPI (<=48 MHz).
03061   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 170MHz)
03062   * @retval SET / RESET
03063   */
03064 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03065
03066 /**
03067   * @brief  Macro to configure the system clock source.
03068   * @param  __SYSCLKSOURCE__ specifies the system clock source.
03069   *          This parameter can be one of the following values:
03070   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
03071   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
03072   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
03073   * @retval None
03074   */
03075 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
03076                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
03077
03078 /** @brief  Macro to get the clock source used as system clock.
03079   * @retval The clock source used as system clock. The returned value can be one
03080   *         of the following:
03081   *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
03082   *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
03083   *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
03084   */
03085 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
03086
03087 /**
03088   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
03089   * @note   As the LSE is in the Backup domain and write access is denied to
03090   *         this domain after reset, you have to enable write access using
03091   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
03092   *         (to be done once after reset).
03093   * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.
03094   *          This parameter can be one of the following values:
03095   *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
03096   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
03097   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
03098   *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
03099   * @retval None
03100   */
03101 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
03102                   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
03103
03104 /** @brief  Macro to configure the MCO clock.
03105   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
03106   *          This parameter can be one of the following values:
03107   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
03108   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
03109   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
03110   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO source
03111   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
03112   *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
03113   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
03114   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
03115   * @param  __MCODIV__ specifies the MCO clock prescaler.
03116   *          This parameter can be one of the following values:
03117   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
03118   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
03119   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
03120   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
03121   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
03122   */
03123 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
03124                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
03125
03126 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
03127   * @brief macros to manage the specified RCC Flags and interrupts.
03128   * @{
03129   */
03130
03131 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
03132   *         the selected interrupts).
03133   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
03134   *         This parameter can be any combination of the following values:
03135   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03136   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03137   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03138   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03139   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03140   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03141   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03142   * @retval None
03143   */
03144 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
03145
03146 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
03147   *        the selected interrupts).
03148   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
03149   *         This parameter can be any combination of the following values:
03150   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03151   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03152   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03153   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03154   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03155   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03156   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03157   * @retval None
03158   */
03159 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
03160
03161 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
03162   *         bits to clear the selected interrupt pending bits.
03163   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
03164   *         This parameter can be any combination of the following values:
03165   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03166   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03167   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03168   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03169   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03170   *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
03171   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03172   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03173   * @retval None
03174   */
03175 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
03176
03177 /** @brief  Check whether the RCC interrupt has occurred or not.
03178   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
03179   *         This parameter can be one of the following values:
03180   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03181   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03182   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03183   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03184   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03185   *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
03186   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03187   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
03188   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
03189   */
03190 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
03191
03192 /** @brief Set RMVF bit to clear the reset flags.
03193   *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
03194   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
03195   * @retval None
03196  */
03197 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
03198
03199 /** @brief  Check whether the selected RCC flag is set or not.
03200   * @param  __FLAG__ specifies the flag to check.
03201   *         This parameter can be one of the following values:
03202   *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
03203   *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
03204   *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
03205   *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
03206   *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
03207   *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
03208   *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready
03209   *            @arg @ref RCC_FLAG_BORRST  BOR reset
03210   *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
03211   *            @arg @ref RCC_FLAG_PINRST  Pin reset
03212   *            @arg @ref RCC_FLAG_SFTRST  Software reset
03213   *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
03214   *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
03215   *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
03216   * @retval The new state of __FLAG__ (TRUE or FALSE).
03217   */
03218 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                     \
03219                                         ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                  \
03220                                         ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                   \
03221                                         ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &    \
03222                                           ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
03223                                             ? 1U : 0U)
03224
03225 /**
03226   * @}
03227   */
03228
03229 /**
03230   * @}
03231   */
03232
03233 /* Private constants ---------------------------------------------------------*/
03234 /** @addtogroup RCC_Private_Constants
03235   * @{
03236   */
03237 /* Defines used for Flags */
03238 #define CR_REG_INDEX              1U
03239 #define BDCR_REG_INDEX            2U
03240 #define CSR_REG_INDEX             3U
03241 #define CRRCR_REG_INDEX           4U
03242
03243 #define RCC_FLAG_MASK             0x1FU
03244
03245 /* Define used for IS_RCC_CLOCKTYPE() */
03246 #define RCC_CLOCKTYPE_ALL              (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2)  /*!< All clcoktype to configure */
03247
03248 /**
03249   * @}
03250   */
03251
03252 /* Private macros ------------------------------------------------------------*/
03253 /** @addtogroup RCC_Private_Macros
03254   * @{
03255   */
03256
03257 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
03258                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
03259                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
03260                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
03261                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
03262                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))
03263
03264 #define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
03265                               ((__HSE__) == RCC_HSE_BYPASS))
03266
03267 #define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
03268                               ((__LSE__) == RCC_LSE_BYPASS))
03269
03270 #define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
03271
03272 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
03273
03274 #define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
03275
03276 #define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
03277
03278 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
03279                              ((__PLL__) == RCC_PLL_ON))
03280
03281 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
03282                                       ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
03283                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
03284
03285 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
03286
03287 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
03288
03289 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
03290
03291 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
03292                                       ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
03293
03294 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
03295                                       ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
03296
03297 #define IS_RCC_CLOCKTYPE(__CLK__)  ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
03298
03299 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
03300                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
03301                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
03302
03303 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
03304                                ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
03305                                ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
03306                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
03307                                ((__HCLK__) == RCC_SYSCLK_DIV512))
03308
03309 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
03310                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
03311                                ((__PCLK__) == RCC_HCLK_DIV16))
03312
03313 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE)   || \
03314                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
03315                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
03316                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
03317
03318 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \
03319                               ((__MCOX__) == RCC_MCO_PG10))
03320
03321 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
03322                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
03323                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
03324                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
03325                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
03326                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
03327                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
03328                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
03329
03330 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
03331                                 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
03332                                 ((__DIV__) == RCC_MCODIV_16))
03333
03334 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
03335                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
03336                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
03337                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
03338
03339 /**
03340   * @}
03341   */
03342
03343 /* Include RCC HAL Extended module */
03344 #include "stm32g4xx_hal_rcc_ex.h"
03345
03346 /* Exported functions --------------------------------------------------------*/
03347 /** @addtogroup RCC_Exported_Functions
03348   * @{
03349   */
03350
03351
03352 /** @addtogroup RCC_Exported_Functions_Group1
03353   * @{
03354   */
03355
03356 /* Initialization and de-initialization functions  ******************************/
03357 HAL_StatusTypeDef HAL_RCC_DeInit(void);
03358 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03359 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
03360
03361 /**
03362   * @}
03363   */
03364
03365 /** @addtogroup RCC_Exported_Functions_Group2
03366   * @{
03367   */
03368
03369 /* Peripheral Control functions  ************************************************/
03370 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
03371 void              HAL_RCC_EnableCSS(void);
03372 void              HAL_RCC_EnableLSECSS(void);
03373 void              HAL_RCC_DisableLSECSS(void);
03374 uint32_t          HAL_RCC_GetSysClockFreq(void);
03375 uint32_t          HAL_RCC_GetHCLKFreq(void);
03376 uint32_t          HAL_RCC_GetPCLK1Freq(void);
03377 uint32_t          HAL_RCC_GetPCLK2Freq(void);
03378 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03379 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
03380 /* CSS NMI IRQ handler */
03381 void              HAL_RCC_NMI_IRQHandler(void);
03382 /* User Callbacks in non blocking mode (IT mode) */
03383 void              HAL_RCC_CSSCallback(void);
03384
03385 /**
03386   * @}
03387   */
03388
03389 /**
03390   * @}
03391   */
03392
03393 /**
03394   * @}
03395   */
03396
03397 /**
03398   * @}
03399   */
03400
03401 #ifdef __cplusplus
03402 }
03403 #endif
03404
03405 #endif /* STM32G4xx_HAL_RCC_H */
03406
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_rcc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities RCC extended peripheral:
00008   *           + Extended Peripheral Control functions
00009   *           + Extended Clock management functions
00010   *           + Extended Clock Recovery System Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file in
00019   * the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g4xx_hal.h"
00026
00027 /** @addtogroup STM32G4xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup RCCEx RCCEx
00032   * @brief RCC Extended HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_RCC_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private defines -----------------------------------------------------------*/
00040 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
00041  * @{
00042  */
00043 #define PLL_TIMEOUT_VALUE        2U                /* 2 ms (minimum Tick + 1) */
00044
00045 #define DIVIDER_P_UPDATE          0U
00046 #define DIVIDER_Q_UPDATE          1U
00047 #define DIVIDER_R_UPDATE          2U
00048
00049 #define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()
00050 #define LSCO_GPIO_PORT            GPIOA
00051 #define LSCO_PIN                  GPIO_PIN_2
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private function prototypes -----------------------------------------------*/
00059 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
00060  * @{
00061  */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /* Exported functions --------------------------------------------------------*/
00068
00069 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00070   * @{
00071   */
00072
00073 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00074  *  @brief  Extended Peripheral Control functions
00075  *
00076 @verbatim
00077  ===============================================================================
00078                 ##### Extended Peripheral Control functions  #####
00079  ===============================================================================
00080     [..]
00081     This subsection provides a set of functions allowing to control the RCC Clocks
00082     frequencies.
00083     [..]
00084     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00085         select the RTC clock source; in this case the Backup domain will be reset in
00086         order to modify the RTC Clock source, as consequence RTC registers (including
00087         the backup registers) are set to their reset values.
00088
00089 @endverbatim
00090   * @{
00091   */
00092 /**
00093   * @brief  Initialize the RCC extended peripherals clocks according to the specified
00094   *         parameters in the RCC_PeriphCLKInitTypeDef.
00095   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
00096   *         contains a field PeriphClockSelection which can be a combination of the following values:
00097   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00098   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00099   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00100   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00101   *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
00102   *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
00103   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00104   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
00105   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
00106   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
00107   *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
00108   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
00109   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
00110   *            @arg @ref RCC_PERIPHCLK_I2S  I2S peripheral clock
00111   *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
00112   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
00113   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
00114   *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
00115   *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
00116   *            @arg @ref RCC_PERIPHCLK_QSPI  QuadSPI peripheral clock (only for devices with QuadSPI)
00117   *
00118   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00119   *         the RTC clock source: in this case the access to Backup domain is enabled.
00120   *
00121   * @retval HAL status
00122   */
00123 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00124 {
00125   uint32_t tmpregister;
00126   uint32_t tickstart;
00127   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
00128   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
00129
00130   /* Check the parameters */
00131   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00132
00133   /*-------------------------- RTC clock source configuration ----------------------*/
00134   if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
00135   {
00136     FlagStatus       pwrclkchanged = RESET;
00137
00138     /* Check for RTC Parameters used to output RTCCLK */
00139     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00140
00141     /* Enable Power Clock */
00142     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00143     {
00144       __HAL_RCC_PWR_CLK_ENABLE();
00145       pwrclkchanged = SET;
00146     }
00147
00148     /* Enable write access to Backup domain */
00149     SET_BIT(PWR->CR1, PWR_CR1_DBP);
00150
00151     /* Wait for Backup domain Write protection disable */
00152     tickstart = HAL_GetTick();
00153
00154     while((PWR->CR1 & PWR_CR1_DBP) == 0U)
00155     {
00156       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00157       {
00158         ret = HAL_TIMEOUT;
00159         break;
00160       }
00161     }
00162
00163     if(ret == HAL_OK)
00164     {
00165       /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
00166       tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
00167
00168       if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
00169       {
00170         /* Store the content of BDCR register before the reset of Backup Domain */
00171         tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
00172         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00173         __HAL_RCC_BACKUPRESET_FORCE();
00174         __HAL_RCC_BACKUPRESET_RELEASE();
00175         /* Restore the Content of BDCR register */
00176         RCC->BDCR = tmpregister;
00177       }
00178
00179       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
00180       if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
00181       {
00182         /* Get Start Tick*/
00183         tickstart = HAL_GetTick();
00184
00185         /* Wait till LSE is ready */
00186         while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
00187         {
00188           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00189           {
00190             ret = HAL_TIMEOUT;
00191             break;
00192           }
00193         }
00194       }
00195
00196       if(ret == HAL_OK)
00197       {
00198         /* Apply new RTC clock source selection */
00199         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00200       }
00201       else
00202       {
00203         /* set overall return value */
00204         status = ret;
00205       }
00206     }
00207     else
00208     {
00209       /* set overall return value */
00210       status = ret;
00211     }
00212
00213     /* Restore clock configuration if changed */
00214     if(pwrclkchanged == SET)
00215     {
00216       __HAL_RCC_PWR_CLK_DISABLE();
00217     }
00218   }
00219
00220   /*-------------------------- USART1 clock source configuration -------------------*/
00221   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00222   {
00223     /* Check the parameters */
00224     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00225
00226     /* Configure the USART1 clock source */
00227     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00228   }
00229
00230   /*-------------------------- USART2 clock source configuration -------------------*/
00231   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
00232   {
00233     /* Check the parameters */
00234     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
00235
00236     /* Configure the USART2 clock source */
00237     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
00238   }
00239
00240   /*-------------------------- USART3 clock source configuration -------------------*/
00241   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
00242   {
00243     /* Check the parameters */
00244     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
00245
00246     /* Configure the USART3 clock source */
00247     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
00248   }
00249
00250 #if defined(UART4)
00251   /*-------------------------- UART4 clock source configuration --------------------*/
00252   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
00253   {
00254     /* Check the parameters */
00255     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
00256
00257     /* Configure the UART4 clock source */
00258     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
00259   }
00260 #endif /* UART4 */
00261
00262 #if defined(UART5)
00263
00264   /*-------------------------- UART5 clock source configuration --------------------*/
00265   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
00266   {
00267     /* Check the parameters */
00268     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
00269
00270     /* Configure the UART5 clock source */
00271     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
00272   }
00273
00274 #endif /* UART5 */
00275
00276   /*-------------------------- LPUART1 clock source configuration ------------------*/
00277   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
00278   {
00279     /* Check the parameters */
00280     assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
00281
00282     /* Configure the LPUAR1 clock source */
00283     __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
00284   }
00285
00286   /*-------------------------- I2C1 clock source configuration ---------------------*/
00287   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00288   {
00289     /* Check the parameters */
00290     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00291
00292     /* Configure the I2C1 clock source */
00293     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00294   }
00295
00296   /*-------------------------- I2C2 clock source configuration ---------------------*/
00297   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
00298   {
00299     /* Check the parameters */
00300     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
00301
00302     /* Configure the I2C2 clock source */
00303     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
00304   }
00305
00306   /*-------------------------- I2C3 clock source configuration ---------------------*/
00307   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
00308   {
00309     /* Check the parameters */
00310     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
00311
00312     /* Configure the I2C3 clock source */
00313     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
00314   }
00315
00316 #if defined(I2C4)
00317
00318   /*-------------------------- I2C4 clock source configuration ---------------------*/
00319   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
00320   {
00321     /* Check the parameters */
00322     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
00323
00324     /* Configure the I2C4 clock source */
00325     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
00326   }
00327
00328 #endif /* I2C4 */
00329
00330   /*-------------------------- LPTIM1 clock source configuration ---------------------*/
00331   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
00332   {
00333     /* Check the parameters */
00334     assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
00335
00336     /* Configure the LPTIM1 clock source */
00337     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
00338   }
00339
00340   /*-------------------------- SAI1 clock source configuration ---------------------*/
00341   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
00342   {
00343     /* Check the parameters */
00344     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
00345
00346     /* Configure the SAI1 interface clock source */
00347     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00348
00349     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
00350     {
00351       /* Enable PLL48M1CLK output */
00352       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00353     }
00354   }
00355
00356   /*-------------------------- I2S clock source configuration ---------------------*/
00357   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
00358   {
00359     /* Check the parameters */
00360     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
00361
00362     /* Configure the I2S interface clock source */
00363     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
00364
00365     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
00366     {
00367       /* Enable PLL48M1CLK output */
00368       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00369     }
00370   }
00371
00372 #if defined(FDCAN1)
00373   /*-------------------------- FDCAN clock source configuration ---------------------*/
00374   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
00375   {
00376     /* Check the parameters */
00377     assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
00378
00379     /* Configure the FDCAN interface clock source */
00380     __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
00381
00382     if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
00383     {
00384       /* Enable PLL48M1CLK output */
00385       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00386     }
00387   }
00388 #endif /* FDCAN1 */
00389
00390 #if defined(USB)
00391
00392   /*-------------------------- USB clock source configuration ----------------------*/
00393   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
00394   {
00395     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
00396     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
00397
00398     if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
00399     {
00400       /* Enable PLL48M1CLK output */
00401       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00402     }
00403   }
00404
00405 #endif /* USB */
00406
00407   /*-------------------------- RNG clock source configuration ----------------------*/
00408   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
00409   {
00410     assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
00411     __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
00412
00413     if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
00414     {
00415       /* Enable PLL48M1CLK output */
00416       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00417     }
00418   }
00419
00420   /*-------------------------- ADC12 clock source configuration ----------------------*/
00421   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
00422   {
00423     /* Check the parameters */
00424     assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
00425
00426     /* Configure the ADC12 interface clock source */
00427     __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
00428
00429     if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
00430     {
00431       /* Enable PLLADCCLK output */
00432       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
00433     }
00434   }
00435
00436 #if defined(ADC345_COMMON)
00437   /*-------------------------- ADC345 clock source configuration ----------------------*/
00438   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
00439   {
00440     /* Check the parameters */
00441     assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
00442
00443     /* Configure the ADC345 interface clock source */
00444     __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
00445
00446     if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
00447     {
00448       /* Enable PLLADCCLK output */
00449       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
00450     }
00451   }
00452 #endif /* ADC345_COMMON */
00453
00454 #if defined(QUADSPI)
00455
00456   /*-------------------------- QuadSPIx clock source configuration ----------------*/
00457   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
00458   {
00459     /* Check the parameters */
00460     assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
00461
00462     /* Configure the QuadSPI clock source */
00463     __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
00464
00465     if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
00466     {
00467       /* Enable PLL48M1CLK output */
00468       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00469     }
00470   }
00471
00472 #endif /* QUADSPI */
00473
00474   return status;
00475 }
00476
00477 /**
00478   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
00479   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
00480   *         returns the configuration information for the Extended Peripherals
00481   *         clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4,
00482   *         LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
00483   * @retval None
00484   */
00485 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00486 {
00487   /* Set all possible values for the extended clock type parameter------------*/
00488
00489 #if defined(STM32G474xx) || defined(STM32G484xx)
00490
00491   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
00492                                         RCC_PERIPHCLK_UART5   | \
00493                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00494                                         RCC_PERIPHCLK_I2C4    | \
00495                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN  | \
00496                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
00497                                         RCC_PERIPHCLK_QSPI    | \
00498                                         RCC_PERIPHCLK_RTC;
00499 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00500
00501   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
00502                                         RCC_PERIPHCLK_UART5   | \
00503                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00504                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN  | \
00505                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
00506                                         RCC_PERIPHCLK_QSPI    | \
00507                                         RCC_PERIPHCLK_RTC;
00508
00509 #elif defined(STM32G473xx) || defined(STM32G483xx)
00510
00511   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
00512                                         RCC_PERIPHCLK_UART5   | \
00513                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00514                                         RCC_PERIPHCLK_I2C4    | \
00515                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | \
00516                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | RCC_PERIPHCLK_ADC345 | \
00517                                         RCC_PERIPHCLK_QSPI    | \
00518                                         RCC_PERIPHCLK_RTC;
00519
00520 #elif defined(STM32G471xx)
00521
00522   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
00523                                         RCC_PERIPHCLK_UART5   | \
00524                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00525                                         RCC_PERIPHCLK_I2C4    | \
00526                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | \
00527                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
00528                                         RCC_PERIPHCLK_RTC;
00529 #elif defined(STM32G431xx) || defined(STM32G441xx)
00530
00531   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | \
00532                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00533                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN    | \
00534                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
00535                                         RCC_PERIPHCLK_RTC;
00536 #elif defined(STM32GBK1CB)
00537
00538   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
00539                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   | \
00540                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_I2S    | RCC_PERIPHCLK_FDCAN    | \
00541                                         RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB    | RCC_PERIPHCLK_ADC12  | \
00542                                         RCC_PERIPHCLK_RTC;
00543
00544 #endif /* STM32G431xx */
00545
00546
00547   /* Get the USART1 clock source ---------------------------------------------*/
00548   PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
00549   /* Get the USART2 clock source ---------------------------------------------*/
00550   PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
00551   /* Get the USART3 clock source ---------------------------------------------*/
00552   PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
00553
00554 #if defined(UART4)
00555   /* Get the UART4 clock source ----------------------------------------------*/
00556   PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
00557 #endif /* UART4 */
00558
00559 #if defined(UART5)
00560   /* Get the UART5 clock source ----------------------------------------------*/
00561   PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
00562 #endif /* UART5 */
00563
00564   /* Get the LPUART1 clock source --------------------------------------------*/
00565   PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
00566
00567   /* Get the I2C1 clock source -----------------------------------------------*/
00568   PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
00569
00570   /* Get the I2C2 clock source ----------------------------------------------*/
00571   PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
00572
00573   /* Get the I2C3 clock source -----------------------------------------------*/
00574   PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
00575
00576 #if defined(I2C4)
00577   /* Get the I2C4 clock source -----------------------------------------------*/
00578   PeriphClkInit->I2c4ClockSelection    = __HAL_RCC_GET_I2C4_SOURCE();
00579 #endif /* I2C4 */
00580
00581   /* Get the LPTIM1 clock source ---------------------------------------------*/
00582   PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
00583
00584   /* Get the SAI1 clock source -----------------------------------------------*/
00585   PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
00586
00587   /* Get the I2S clock source -----------------------------------------------*/
00588   PeriphClkInit->I2sClockSelection    = __HAL_RCC_GET_I2S_SOURCE();
00589
00590 #if defined(FDCAN1)
00591   /* Get the FDCAN clock source -----------------------------------------------*/
00592   PeriphClkInit->FdcanClockSelection    = __HAL_RCC_GET_FDCAN_SOURCE();
00593 #endif /* FDCAN1 */
00594
00595 #if defined(USB)
00596   /* Get the USB clock source ------------------------------------------------*/
00597   PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
00598 #endif /* USB */
00599
00600   /* Get the RNG clock source ------------------------------------------------*/
00601   PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
00602
00603   /* Get the ADC12 clock source -----------------------------------------------*/
00604   PeriphClkInit->Adc12ClockSelection     = __HAL_RCC_GET_ADC12_SOURCE();
00605
00606 #if defined(ADC345_COMMON)
00607   /* Get the ADC345 clock source ----------------------------------------------*/
00608   PeriphClkInit->Adc345ClockSelection     = __HAL_RCC_GET_ADC345_SOURCE();
00609 #endif /* ADC345_COMMON */
00610
00611 #if defined(QUADSPI)
00612   /* Get the QuadSPIclock source --------------------------------------------*/
00613   PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
00614 #endif /* QUADSPI */
00615
00616   /* Get the RTC clock source ------------------------------------------------*/
00617   PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
00618
00619 }
00620
00621 /**
00622   * @brief  Return the peripheral clock frequency for peripherals with clock source from PLL
00623   * @note   Return 0 if peripheral clock identifier not managed by this API
00624   * @param  PeriphClk  Peripheral clock identifier
00625   *         This parameter can be one of the following values:
00626   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00627   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock
00628   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock
00629   *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
00630   *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
00631   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00632   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
00633   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
00634   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
00635   *            @arg @ref RCC_PERIPHCLK_I2C4  I2C4 peripheral clock (only for devices with I2C4)
00636   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
00637   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
00638   *            @arg @ref RCC_PERIPHCLK_I2S  SPI peripheral clock
00639   *            @arg @ref RCC_PERIPHCLK_FDCAN  FDCAN peripheral clock (only for devices with FDCAN)
00640   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
00641   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
00642   *            @arg @ref RCC_PERIPHCLK_ADC12  ADC1 and ADC2 peripheral clock
00643   *            @arg @ref RCC_PERIPHCLK_ADC345  ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5)
00644   *            @arg @ref RCC_PERIPHCLK_QSPI  QSPI peripheral clock (only for devices with QSPI)
00645   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00646   * @retval Frequency in Hz
00647   */
00648 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00649 {
00650   uint32_t frequency = 0U;
00651   uint32_t srcclk;
00652   uint32_t pllvco, plln, pllp;
00653
00654   /* Check the parameters */
00655   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00656
00657   if(PeriphClk == RCC_PERIPHCLK_RTC)
00658   {
00659     /* Get the current RTC source */
00660     srcclk = __HAL_RCC_GET_RTC_SOURCE();
00661
00662     /* Check if LSE is ready and if RTC clock selection is LSE */
00663     if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
00664     {
00665       frequency = LSE_VALUE;
00666     }
00667     /* Check if LSI is ready and if RTC clock selection is LSI */
00668     else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
00669     {
00670       frequency = LSI_VALUE;
00671     }
00672     /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
00673     else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
00674     {
00675       frequency = HSE_VALUE / 32U;
00676     }
00677     /* Clock not enabled for RTC*/
00678     else
00679     {
00680       /* nothing to do: frequency already initialized to 0 */
00681     }
00682   }
00683   else
00684   {
00685     /* Other external peripheral clock source than RTC */
00686
00687     /* Compute PLL clock input */
00688     if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
00689     {
00690       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
00691       {
00692         pllvco = HSI_VALUE;
00693       }
00694       else
00695       {
00696         pllvco = 0U;
00697       }
00698     }
00699     else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
00700     {
00701       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
00702       {
00703         pllvco = HSE_VALUE;
00704       }
00705       else
00706       {
00707         pllvco = 0U;
00708       }
00709     }
00710     else /* No source */
00711     {
00712       pllvco = 0U;
00713     }
00714
00715     /* f(PLL Source) / PLLM */
00716     pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
00717
00718     switch(PeriphClk)
00719     {
00720
00721     case RCC_PERIPHCLK_USART1:
00722       /* Get the current USART1 source */
00723       srcclk = __HAL_RCC_GET_USART1_SOURCE();
00724
00725       if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
00726       {
00727         frequency = HAL_RCC_GetPCLK2Freq();
00728       }
00729       else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
00730       {
00731         frequency = HAL_RCC_GetSysClockFreq();
00732       }
00733       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) )
00734       {
00735         frequency = HSI_VALUE;
00736       }
00737       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
00738       {
00739         frequency = LSE_VALUE;
00740       }
00741       /* Clock not enabled for USART1 */
00742       else
00743       {
00744         /* nothing to do: frequency already initialized to 0 */
00745       }
00746       break;
00747
00748     case RCC_PERIPHCLK_USART2:
00749       /* Get the current USART2 source */
00750       srcclk = __HAL_RCC_GET_USART2_SOURCE();
00751
00752       if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
00753       {
00754         frequency = HAL_RCC_GetPCLK1Freq();
00755       }
00756       else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
00757       {
00758         frequency = HAL_RCC_GetSysClockFreq();
00759       }
00760       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
00761       {
00762         frequency = HSI_VALUE;
00763       }
00764       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))  && (srcclk == RCC_USART2CLKSOURCE_LSE))
00765       {
00766         frequency = LSE_VALUE;
00767       }
00768       /* Clock not enabled for USART2 */
00769       else
00770       {
00771         /* nothing to do: frequency already initialized to 0 */
00772       }
00773       break;
00774
00775     case RCC_PERIPHCLK_USART3:
00776       /* Get the current USART3 source */
00777       srcclk = __HAL_RCC_GET_USART3_SOURCE();
00778
00779       if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
00780       {
00781         frequency = HAL_RCC_GetPCLK1Freq();
00782       }
00783       else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
00784       {
00785         frequency = HAL_RCC_GetSysClockFreq();
00786       }
00787       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
00788       {
00789         frequency = HSI_VALUE;
00790       }
00791       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
00792       {
00793         frequency = LSE_VALUE;
00794       }
00795       /* Clock not enabled for USART3 */
00796       else
00797       {
00798         /* nothing to do: frequency already initialized to 0 */
00799       }
00800       break;
00801
00802 #if defined(UART4)
00803     case RCC_PERIPHCLK_UART4:
00804       /* Get the current UART4 source */
00805       srcclk = __HAL_RCC_GET_UART4_SOURCE();
00806
00807       if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
00808       {
00809         frequency = HAL_RCC_GetPCLK1Freq();
00810       }
00811       else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
00812       {
00813         frequency = HAL_RCC_GetSysClockFreq();
00814       }
00815       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
00816       {
00817         frequency = HSI_VALUE;
00818       }
00819       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
00820       {
00821         frequency = LSE_VALUE;
00822       }
00823       /* Clock not enabled for UART4 */
00824       else
00825       {
00826         /* nothing to do: frequency already initialized to 0 */
00827       }
00828       break;
00829 #endif /* UART4 */
00830
00831 #if defined(UART5)
00832     case RCC_PERIPHCLK_UART5:
00833       /* Get the current UART5 source */
00834       srcclk = __HAL_RCC_GET_UART5_SOURCE();
00835
00836       if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
00837       {
00838         frequency = HAL_RCC_GetPCLK1Freq();
00839       }
00840       else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
00841       {
00842         frequency = HAL_RCC_GetSysClockFreq();
00843       }
00844       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
00845       {
00846         frequency = HSI_VALUE;
00847       }
00848       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
00849       {
00850         frequency = LSE_VALUE;
00851       }
00852       /* Clock not enabled for UART5 */
00853       else
00854       {
00855         /* nothing to do: frequency already initialized to 0 */
00856       }
00857       break;
00858 #endif /* UART5 */
00859
00860     case RCC_PERIPHCLK_LPUART1:
00861       /* Get the current LPUART1 source */
00862       srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
00863
00864       if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
00865       {
00866         frequency = HAL_RCC_GetPCLK1Freq();
00867       }
00868       else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
00869       {
00870         frequency = HAL_RCC_GetSysClockFreq();
00871       }
00872       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
00873       {
00874         frequency = HSI_VALUE;
00875       }
00876       else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
00877       {
00878         frequency = LSE_VALUE;
00879       }
00880       /* Clock not enabled for LPUART1 */
00881       else
00882       {
00883         /* nothing to do: frequency already initialized to 0 */
00884       }
00885       break;
00886
00887     case RCC_PERIPHCLK_I2C1:
00888       /* Get the current I2C1 source */
00889       srcclk = __HAL_RCC_GET_I2C1_SOURCE();
00890
00891       if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
00892       {
00893         frequency = HAL_RCC_GetPCLK1Freq();
00894       }
00895       else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
00896       {
00897         frequency = HAL_RCC_GetSysClockFreq();
00898       }
00899       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
00900       {
00901         frequency = HSI_VALUE;
00902       }
00903       /* Clock not enabled for I2C1 */
00904       else
00905       {
00906         /* nothing to do: frequency already initialized to 0 */
00907       }
00908       break;
00909
00910     case RCC_PERIPHCLK_I2C2:
00911       /* Get the current I2C2 source */
00912       srcclk = __HAL_RCC_GET_I2C2_SOURCE();
00913
00914       if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
00915       {
00916         frequency = HAL_RCC_GetPCLK1Freq();
00917       }
00918       else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
00919       {
00920         frequency = HAL_RCC_GetSysClockFreq();
00921       }
00922       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
00923       {
00924         frequency = HSI_VALUE;
00925       }
00926       /* Clock not enabled for I2C2 */
00927       else
00928       {
00929         /* nothing to do: frequency already initialized to 0 */
00930       }
00931       break;
00932
00933     case RCC_PERIPHCLK_I2C3:
00934       /* Get the current I2C3 source */
00935       srcclk = __HAL_RCC_GET_I2C3_SOURCE();
00936
00937       if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
00938       {
00939         frequency = HAL_RCC_GetPCLK1Freq();
00940       }
00941       else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
00942       {
00943         frequency = HAL_RCC_GetSysClockFreq();
00944       }
00945       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
00946       {
00947         frequency = HSI_VALUE;
00948       }
00949       /* Clock not enabled for I2C3 */
00950       else
00951       {
00952         /* nothing to do: frequency already initialized to 0 */
00953       }
00954       break;
00955
00956 #if defined(I2C4)
00957
00958     case RCC_PERIPHCLK_I2C4:
00959       /* Get the current I2C4 source */
00960       srcclk = __HAL_RCC_GET_I2C4_SOURCE();
00961
00962       if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
00963       {
00964         frequency = HAL_RCC_GetPCLK1Freq();
00965       }
00966       else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
00967       {
00968         frequency = HAL_RCC_GetSysClockFreq();
00969       }
00970       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
00971       {
00972         frequency = HSI_VALUE;
00973       }
00974       /* Clock not enabled for I2C4 */
00975       else
00976       {
00977         /* nothing to do: frequency already initialized to 0 */
00978       }
00979       break;
00980
00981 #endif /* I2C4 */
00982
00983     case RCC_PERIPHCLK_LPTIM1:
00984       /* Get the current LPTIM1 source */
00985       srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
00986
00987       if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
00988       {
00989         frequency = HAL_RCC_GetPCLK1Freq();
00990       }
00991       else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
00992       {
00993         frequency = LSI_VALUE;
00994       }
00995       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
00996       {
00997         frequency = HSI_VALUE;
00998       }
00999       else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
01000       {
01001         frequency = LSE_VALUE;
01002       }
01003       /* Clock not enabled for LPTIM1 */
01004       else
01005       {
01006         /* nothing to do: frequency already initialized to 0 */
01007       }
01008       break;
01009
01010     case RCC_PERIPHCLK_SAI1:
01011       /* Get the current SAI1 source */
01012       srcclk = __HAL_RCC_GET_SAI1_SOURCE();
01013
01014       if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
01015       {
01016         frequency = HAL_RCC_GetSysClockFreq();
01017       }
01018       else if(srcclk == RCC_SAI1CLKSOURCE_PLL)
01019       {
01020         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
01021         {
01022           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01023           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01024           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01025         }
01026       }
01027       else if(srcclk == RCC_SAI1CLKSOURCE_EXT)
01028       {
01029         /* External clock used.*/
01030         frequency = EXTERNAL_CLOCK_VALUE;
01031       }
01032       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI))
01033       {
01034         frequency = HSI_VALUE;
01035       }
01036       /* Clock not enabled for SAI1 */
01037       else
01038       {
01039         /* nothing to do: frequency already initialized to 0 */
01040       }
01041       break;
01042
01043     case RCC_PERIPHCLK_I2S:
01044       /* Get the current I2Sx source */
01045       srcclk = __HAL_RCC_GET_I2S_SOURCE();
01046
01047       if(srcclk == RCC_I2SCLKSOURCE_SYSCLK)
01048       {
01049         frequency = HAL_RCC_GetSysClockFreq();
01050       }
01051       else if(srcclk == RCC_I2SCLKSOURCE_PLL)
01052       {
01053         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
01054         {
01055           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01056           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01057           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01058         }
01059       }
01060       else if(srcclk == RCC_I2SCLKSOURCE_EXT)
01061       {
01062         /* External clock used.*/
01063         frequency = EXTERNAL_CLOCK_VALUE;
01064       }
01065       else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI))
01066       {
01067         frequency = HSI_VALUE;
01068       }
01069       /* Clock not enabled for I2S */
01070       else
01071       {
01072         /* nothing to do: frequency already initialized to 0 */
01073       }
01074       break;
01075
01076 #if defined(FDCAN1)
01077     case RCC_PERIPHCLK_FDCAN:
01078       /* Get the current FDCANx source */
01079       srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
01080
01081       if(srcclk == RCC_FDCANCLKSOURCE_PCLK1)
01082       {
01083         frequency = HAL_RCC_GetPCLK1Freq();
01084       }
01085       else if(srcclk == RCC_FDCANCLKSOURCE_HSE)
01086       {
01087         frequency = HSE_VALUE;
01088       }
01089       else if(srcclk == RCC_FDCANCLKSOURCE_PLL)
01090       {
01091         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
01092         {
01093           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01094           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01095           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01096         }
01097       }
01098       /* Clock not enabled for FDCAN */
01099       else
01100       {
01101         /* nothing to do: frequency already initialized to 0 */
01102       }
01103       break;
01104 #endif /* FDCAN1 */
01105
01106 #if defined(USB)
01107
01108     case RCC_PERIPHCLK_USB:
01109       /* Get the current USB source */
01110       srcclk = __HAL_RCC_GET_USB_SOURCE();
01111
01112       if(srcclk == RCC_USBCLKSOURCE_PLL)  /* PLL ? */
01113       {
01114         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01115         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01116         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01117       }
01118       else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */
01119       {
01120         frequency = HSI48_VALUE;
01121       }
01122       else /* No clock source */
01123       {
01124         /* nothing to do: frequency already initialized to 0 */
01125       }
01126       break;
01127
01128 #endif /* USB */
01129
01130     case RCC_PERIPHCLK_RNG:
01131       /* Get the current RNG source */
01132       srcclk = __HAL_RCC_GET_RNG_SOURCE();
01133
01134       if(srcclk == RCC_RNGCLKSOURCE_PLL)  /* PLL ? */
01135       {
01136         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01137         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01138         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01139       }
01140       else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */
01141       {
01142         frequency = HSI48_VALUE;
01143       }
01144       else /* No clock source */
01145       {
01146         /* nothing to do: frequency already initialized to 0 */
01147       }
01148       break;
01149
01150     case RCC_PERIPHCLK_ADC12:
01151       /* Get the current ADC12 source */
01152       srcclk = __HAL_RCC_GET_ADC12_SOURCE();
01153
01154       if(srcclk == RCC_ADC12CLKSOURCE_PLL)
01155       {
01156         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
01157         {
01158           /* f(PLLP) = f(VCO input) * PLLN / PLLP */
01159           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01160           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
01161           if(pllp == 0U)
01162           {
01163             if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
01164             {
01165               pllp = 17U;
01166             }
01167             else
01168             {
01169               pllp = 7U;
01170             }
01171           }
01172           frequency = (pllvco * plln) / pllp;
01173         }
01174       }
01175       else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK)
01176       {
01177         frequency = HAL_RCC_GetSysClockFreq();
01178       }
01179       /* Clock not enabled for ADC12 */
01180       else
01181       {
01182         /* nothing to do: frequency already initialized to 0 */
01183       }
01184       break;
01185
01186 #if defined(ADC345_COMMON)
01187     case RCC_PERIPHCLK_ADC345:
01188       /* Get the current ADC345 source */
01189       srcclk = __HAL_RCC_GET_ADC345_SOURCE();
01190
01191       if(srcclk == RCC_ADC345CLKSOURCE_PLL)
01192       {
01193         if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
01194         {
01195           /* f(PLLP) = f(VCO input) * PLLN / PLLP */
01196           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01197           pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
01198           if(pllp == 0U)
01199           {
01200             if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
01201             {
01202               pllp = 17U;
01203             }
01204             else
01205             {
01206               pllp = 7U;
01207             }
01208           }
01209           frequency = (pllvco * plln) / pllp;
01210         }
01211       }
01212       else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK)
01213       {
01214         frequency = HAL_RCC_GetSysClockFreq();
01215       }
01216       /* Clock not enabled for ADC345 */
01217       else
01218       {
01219         /* nothing to do: frequency already initialized to 0 */
01220       }
01221       break;
01222 #endif /* ADC345_COMMON */
01223
01224 #if defined(QUADSPI)
01225
01226     case RCC_PERIPHCLK_QSPI:
01227       /* Get the current QSPI source */
01228       srcclk = __HAL_RCC_GET_QSPI_SOURCE();
01229
01230       if(srcclk == RCC_QSPICLKSOURCE_PLL)  /* PLL ? */
01231       {
01232         /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01233         plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01234         frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
01235       }
01236       else if(srcclk == RCC_QSPICLKSOURCE_HSI)
01237       {
01238         frequency = HSI_VALUE;
01239       }
01240       else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK)
01241       {
01242         frequency = HAL_RCC_GetSysClockFreq();
01243       }
01244       else /* No clock source */
01245       {
01246         /* nothing to do: frequency already initialized to 0 */
01247       }
01248       break;
01249
01250 #endif /* QUADSPI */
01251
01252     default:
01253       break;
01254     }
01255   }
01256
01257   return(frequency);
01258 }
01259
01260 /**
01261   * @}
01262   */
01263
01264 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
01265  *  @brief  Extended Clock management functions
01266  *
01267 @verbatim
01268  ===============================================================================
01269                 ##### Extended clock management functions  #####
01270  ===============================================================================
01271     [..]
01272     This subsection provides a set of functions allowing to control the
01273     activation or deactivation of LSE CSS,
01274     Low speed clock output and clock after wake-up from STOP mode.
01275 @endverbatim
01276   * @{
01277   */
01278
01279 /**
01280   * @brief  Enable the LSE Clock Security System.
01281   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
01282   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
01283   *         clock with HAL_RCCEx_PeriphCLKConfig().
01284   * @retval None
01285   */
01286 void HAL_RCCEx_EnableLSECSS(void)
01287 {
01288   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01289 }
01290
01291 /**
01292   * @brief  Disable the LSE Clock Security System.
01293   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
01294   * @retval None
01295   */
01296 void HAL_RCCEx_DisableLSECSS(void)
01297 {
01298   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01299
01300   /* Disable LSE CSS IT if any */
01301   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
01302 }
01303
01304 /**
01305   * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
01306   * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
01307   * @retval None
01308   */
01309 void HAL_RCCEx_EnableLSECSS_IT(void)
01310 {
01311   /* Enable LSE CSS */
01312   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01313
01314   /* Enable LSE CSS IT */
01315   __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
01316
01317   /* Enable IT on EXTI Line 19 */
01318   __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
01319   __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
01320 }
01321
01322 /**
01323   * @brief Handle the RCC LSE Clock Security System interrupt request.
01324   * @retval None
01325   */
01326 void HAL_RCCEx_LSECSS_IRQHandler(void)
01327 {
01328   /* Check RCC LSE CSSF flag  */
01329   if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
01330   {
01331     /* RCC LSE Clock Security System interrupt user callback */
01332     HAL_RCCEx_LSECSS_Callback();
01333
01334     /* Clear RCC LSE CSS pending bit */
01335     __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
01336   }
01337 }
01338
01339 /**
01340   * @brief  RCCEx LSE Clock Security System interrupt callback.
01341   * @retval none
01342   */
01343 __weak void HAL_RCCEx_LSECSS_Callback(void)
01344 {
01345   /* NOTE : This function should not be modified, when the callback is needed,
01346             the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
01347    */
01348 }
01349
01350 /**
01351   * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
01352   * @param  LSCOSource  specifies the Low Speed clock source to output.
01353   *          This parameter can be one of the following values:
01354   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
01355   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
01356   * @retval None
01357   */
01358 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
01359 {
01360   GPIO_InitTypeDef GPIO_InitStruct;
01361   FlagStatus       pwrclkchanged = RESET;
01362   FlagStatus       backupchanged = RESET;
01363
01364   /* Check the parameters */
01365   assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
01366
01367   /* LSCO Pin Clock Enable */
01368   __LSCO_CLK_ENABLE();
01369
01370   /* Configure the LSCO pin in analog mode */
01371   GPIO_InitStruct.Pin = LSCO_PIN;
01372   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
01373   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
01374   GPIO_InitStruct.Pull = GPIO_NOPULL;
01375   HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
01376
01377   /* Update LSCOSEL clock source in Backup Domain control register */
01378   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
01379   {
01380     __HAL_RCC_PWR_CLK_ENABLE();
01381     pwrclkchanged = SET;
01382   }
01383   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01384   {
01385     HAL_PWR_EnableBkUpAccess();
01386     backupchanged = SET;
01387   }
01388
01389   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
01390
01391   if(backupchanged == SET)
01392   {
01393     HAL_PWR_DisableBkUpAccess();
01394   }
01395   if(pwrclkchanged == SET)
01396   {
01397     __HAL_RCC_PWR_CLK_DISABLE();
01398   }
01399 }
01400
01401 /**
01402   * @brief  Disable the Low Speed clock output.
01403   * @retval None
01404   */
01405 void HAL_RCCEx_DisableLSCO(void)
01406 {
01407   FlagStatus       pwrclkchanged = RESET;
01408   FlagStatus       backupchanged = RESET;
01409
01410   /* Update LSCOEN bit in Backup Domain control register */
01411   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
01412   {
01413     __HAL_RCC_PWR_CLK_ENABLE();
01414     pwrclkchanged = SET;
01415   }
01416   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01417   {
01418     /* Enable access to the backup domain */
01419     HAL_PWR_EnableBkUpAccess();
01420     backupchanged = SET;
01421   }
01422
01423   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01424
01425   /* Restore previous configuration */
01426   if(backupchanged == SET)
01427   {
01428     /* Disable access to the backup domain */
01429     HAL_PWR_DisableBkUpAccess();
01430   }
01431   if(pwrclkchanged == SET)
01432   {
01433     __HAL_RCC_PWR_CLK_DISABLE();
01434   }
01435 }
01436
01437
01438 /**
01439   * @}
01440   */
01441
01442 #if defined(CRS)
01443
01444 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
01445  *  @brief  Extended Clock Recovery System Control functions
01446  *
01447 @verbatim
01448  ===============================================================================
01449                 ##### Extended Clock Recovery System Control functions  #####
01450  ===============================================================================
01451     [..]
01452       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
01453
01454       (#) In System clock config, HSI48 needs to be enabled
01455
01456       (#) Enable CRS clock in IP MSP init which will use CRS functions
01457
01458       (#) Call CRS functions as follows:
01459           (##) Prepare synchronization configuration necessary for HSI48 calibration
01460               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
01461                         and also HSI48 oscillator smooth trimming.
01462               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
01463                         directly reload value with target and sychronization frequencies values
01464           (##) Call function HAL_RCCEx_CRSConfig which
01465               (+++) Resets CRS registers to their default values.
01466               (+++) Configures CRS registers with synchronization configuration
01467               (+++) Enables automatic calibration and frequency error counter feature
01468            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
01469            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
01470            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
01471            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
01472            should be used as SYNC signal.
01473
01474           (##) A polling function is provided to wait for complete synchronization
01475               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
01476               (+++) According to CRS status, user can decide to adjust again the calibration or continue
01477                         application if synchronization is OK
01478
01479       (#) User can retrieve information related to synchronization in calling function
01480             HAL_RCCEx_CRSGetSynchronizationInfo()
01481
01482       (#) Regarding synchronization status and synchronization information, user can try a new calibration
01483            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
01484            Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
01485            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
01486            incremented), while when it is detected during the upcounting phase it means that the actual frequency
01487            is higher (and that the TRIM value should be decremented).
01488
01489       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
01490           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
01491               (++) Call function HAL_RCCEx_CRSConfig()
01492               (++) Enable CRS_IRQn (thanks to NVIC functions)
01493               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
01494               (++) Implement CRS status management in the following user callbacks called from
01495                    HAL_RCCEx_CRS_IRQHandler():
01496                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
01497                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
01498                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
01499                    (+++) HAL_RCCEx_CRS_ErrorCallback()
01500
01501       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
01502           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
01503
01504 @endverbatim
01505  * @{
01506  */
01507
01508 /**
01509   * @brief  Start automatic synchronization for polling mode
01510   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
01511   * @retval None
01512   */
01513 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
01514 {
01515   uint32_t value;
01516
01517   /* Check the parameters */
01518   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
01519   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
01520   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
01521   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
01522   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
01523   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
01524
01525   /* CONFIGURATION */
01526
01527   /* Before configuration, reset CRS registers to their default values*/
01528   __HAL_RCC_CRS_FORCE_RESET();
01529   __HAL_RCC_CRS_RELEASE_RESET();
01530
01531   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
01532   /* Set the SYNCSRC[1:0] bits according to Source value */
01533   /* Set the SYNCSPOL bit according to Polarity value */
01534   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
01535   /* Set the RELOAD[15:0] bits according to ReloadValue value */
01536   value |= pInit->ReloadValue;
01537   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
01538   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
01539   WRITE_REG(CRS->CFGR, value);
01540
01541   /* Adjust HSI48 oscillator smooth trimming */
01542   /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
01543   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
01544
01545   /* START AUTOMATIC SYNCHRONIZATION*/
01546
01547   /* Enable Automatic trimming & Frequency error counter */
01548   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
01549 }
01550
01551 /**
01552   * @brief  Generate the software synchronization event
01553   * @retval None
01554   */
01555 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
01556 {
01557   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
01558 }
01559
01560 /**
01561   * @brief  Return synchronization info
01562   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
01563   * @retval None
01564   */
01565 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
01566 {
01567   /* Check the parameter */
01568   assert_param(pSynchroInfo != (void *)NULL);
01569
01570   /* Get the reload value */
01571   pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
01572
01573   /* Get HSI48 oscillator smooth trimming */
01574   pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
01575
01576   /* Get Frequency error capture */
01577   pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
01578
01579   /* Get Frequency error direction */
01580   pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
01581 }
01582
01583 /**
01584 * @brief Wait for CRS Synchronization status.
01585 * @param Timeout  Duration of the timeout
01586 * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
01587 *        frequency.
01588 * @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
01589 * @retval Combination of Synchronization status
01590 *          This parameter can be a combination of the following values:
01591 *            @arg @ref RCC_CRS_TIMEOUT
01592 *            @arg @ref RCC_CRS_SYNCOK
01593 *            @arg @ref RCC_CRS_SYNCWARN
01594 *            @arg @ref RCC_CRS_SYNCERR
01595 *            @arg @ref RCC_CRS_SYNCMISS
01596 *            @arg @ref RCC_CRS_TRIMOVF
01597 */
01598 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
01599 {
01600   uint32_t crsstatus = RCC_CRS_NONE;
01601   uint32_t tickstart;
01602
01603   /* Get timeout */
01604   tickstart = HAL_GetTick();
01605
01606   /* Wait for CRS flag or timeout detection */
01607   do
01608   {
01609     if(Timeout != HAL_MAX_DELAY)
01610     {
01611       if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01612       {
01613         crsstatus = RCC_CRS_TIMEOUT;
01614       }
01615     }
01616     /* Check CRS SYNCOK flag  */
01617     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
01618     {
01619       /* CRS SYNC event OK */
01620       crsstatus |= RCC_CRS_SYNCOK;
01621
01622       /* Clear CRS SYNC event OK bit */
01623       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
01624     }
01625
01626     /* Check CRS SYNCWARN flag  */
01627     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
01628     {
01629       /* CRS SYNC warning */
01630       crsstatus |= RCC_CRS_SYNCWARN;
01631
01632       /* Clear CRS SYNCWARN bit */
01633       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
01634     }
01635
01636     /* Check CRS TRIM overflow flag  */
01637     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
01638     {
01639       /* CRS SYNC Error */
01640       crsstatus |= RCC_CRS_TRIMOVF;
01641
01642       /* Clear CRS Error bit */
01643       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
01644     }
01645
01646     /* Check CRS Error flag  */
01647     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
01648     {
01649       /* CRS SYNC Error */
01650       crsstatus |= RCC_CRS_SYNCERR;
01651
01652       /* Clear CRS Error bit */
01653       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
01654     }
01655
01656     /* Check CRS SYNC Missed flag  */
01657     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
01658     {
01659       /* CRS SYNC Missed */
01660       crsstatus |= RCC_CRS_SYNCMISS;
01661
01662       /* Clear CRS SYNC Missed bit */
01663       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
01664     }
01665
01666     /* Check CRS Expected SYNC flag  */
01667     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
01668     {
01669       /* frequency error counter reached a zero value */
01670       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
01671     }
01672   } while(RCC_CRS_NONE == crsstatus);
01673
01674   return crsstatus;
01675 }
01676
01677 /**
01678   * @brief Handle the Clock Recovery System interrupt request.
01679   * @retval None
01680   */
01681 void HAL_RCCEx_CRS_IRQHandler(void)
01682 {
01683   uint32_t crserror = RCC_CRS_NONE;
01684   /* Get current IT flags and IT sources values */
01685   uint32_t itflags = READ_REG(CRS->ISR);
01686   uint32_t itsources = READ_REG(CRS->CR);
01687
01688   /* Check CRS SYNCOK flag  */
01689   if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
01690   {
01691     /* Clear CRS SYNC event OK flag */
01692     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
01693
01694     /* user callback */
01695     HAL_RCCEx_CRS_SyncOkCallback();
01696   }
01697   /* Check CRS SYNCWARN flag  */
01698   else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
01699   {
01700     /* Clear CRS SYNCWARN flag */
01701     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
01702
01703     /* user callback */
01704     HAL_RCCEx_CRS_SyncWarnCallback();
01705   }
01706   /* Check CRS Expected SYNC flag  */
01707   else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
01708   {
01709     /* frequency error counter reached a zero value */
01710     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
01711
01712     /* user callback */
01713     HAL_RCCEx_CRS_ExpectedSyncCallback();
01714   }
01715   /* Check CRS Error flags  */
01716   else
01717   {
01718     if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
01719     {
01720       if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
01721       {
01722         crserror |= RCC_CRS_SYNCERR;
01723       }
01724       if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
01725       {
01726         crserror |= RCC_CRS_SYNCMISS;
01727       }
01728       if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
01729       {
01730         crserror |= RCC_CRS_TRIMOVF;
01731       }
01732
01733       /* Clear CRS Error flags */
01734       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
01735
01736       /* user error callback */
01737       HAL_RCCEx_CRS_ErrorCallback(crserror);
01738     }
01739   }
01740 }
01741
01742 /**
01743   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
01744   * @retval none
01745   */
01746 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
01747 {
01748   /* NOTE : This function should not be modified, when the callback is needed,
01749             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
01750    */
01751 }
01752
01753 /**
01754   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
01755   * @retval none
01756   */
01757 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
01758 {
01759   /* NOTE : This function should not be modified, when the callback is needed,
01760             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
01761    */
01762 }
01763
01764 /**
01765   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
01766   * @retval none
01767   */
01768 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
01769 {
01770   /* NOTE : This function should not be modified, when the callback is needed,
01771             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
01772    */
01773 }
01774
01775 /**
01776   * @brief  RCCEx Clock Recovery System Error interrupt callback.
01777   * @param  Error Combination of Error status.
01778   *         This parameter can be a combination of the following values:
01779   *           @arg @ref RCC_CRS_SYNCERR
01780   *           @arg @ref RCC_CRS_SYNCMISS
01781   *           @arg @ref RCC_CRS_TRIMOVF
01782   * @retval none
01783   */
01784 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
01785 {
01786   /* Prevent unused argument(s) compilation warning */
01787   UNUSED(Error);
01788
01789   /* NOTE : This function should not be modified, when the callback is needed,
01790             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
01791    */
01792 }
01793
01794 /**
01795   * @}
01796   */
01797
01798 #endif /* CRS */
01799
01800 /**
01801   * @}
01802   */
01803
01804 /** @addtogroup RCCEx_Private_Functions
01805  * @{
01806  */
01807
01808 /**
01809   * @}
01810   */
01811
01812 /**
01813   * @}
01814   */
01815
01816 #endif /* HAL_RCC_MODULE_ENABLED */
01817 /**
01818   * @}
01819   */
01820
01821 /**
01822   * @}
01823   */
01824
01825
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rcc_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_rcc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_HAL_RCC_EX_H
00020 #define STM32G4xx_HAL_RCC_EX_H
00021
00022 #ifdef __cplusplus
00023  extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx_hal_def.h"
00028
00029 /** @addtogroup STM32G4xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup RCCEx
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038
00039 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  RCC extended clocks structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00049                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00050
00051   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
00052                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00053
00054   uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
00055                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
00056
00057   uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
00058                                         This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
00059
00060 #if defined(UART4)
00061   uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
00062                                         This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00063 #endif /* UART4 */
00064
00065 #if defined(UART5)
00066   uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
00067                                         This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00068
00069 #endif /* UART5 */
00070
00071   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
00072                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00073
00074   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
00075                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00076
00077   uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
00078                                         This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00079
00080   uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
00081                                         This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00082
00083 #if defined(I2C4)
00084
00085   uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.
00086                                         This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
00087 #endif /* I2C4 */
00088
00089   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
00090                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00091
00092   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
00093                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00094
00095   uint32_t I2sClockSelection;     /*!< Specifies I2S clock source.
00096                                         This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
00097 #if defined(FDCAN1)
00098
00099   uint32_t FdcanClockSelection;     /*!< Specifies FDCAN clock source.
00100                                         This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
00101 #endif /* FDCAN1 */
00102 #if defined(USB)
00103
00104   uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for RNG).
00105                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00106 #endif /* USB */
00107
00108   uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB).
00109                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
00110
00111   uint32_t Adc12ClockSelection;    /*!< Specifies ADC12 interface clock source.
00112                                         This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
00113
00114 #if defined(ADC345_COMMON)
00115   uint32_t Adc345ClockSelection;   /*!< Specifies ADC345 interface clock source.
00116                                         This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */
00117 #endif /* ADC345_COMMON */
00118
00119 #if defined(QUADSPI)
00120   uint32_t QspiClockSelection;     /*!< Specifies QuadSPI clock source.
00121                                         This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
00122 #endif
00123
00124   uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
00125                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00126 }RCC_PeriphCLKInitTypeDef;
00127
00128 /**
00129   * @brief RCC_CRS Init structure definition
00130   */
00131 typedef struct
00132 {
00133   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00134                                        This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
00135
00136   uint32_t Source;                /*!< Specifies the SYNC signal source.
00137                                        This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
00138
00139   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00140                                        This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00141
00142   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00143                                        It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00144                                        This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00145
00146   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00147                                        This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00148
00149   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00150                                        This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00151
00152 }RCC_CRSInitTypeDef;
00153
00154 /**
00155   * @brief RCC_CRS Synchronization structure definition
00156   */
00157 typedef struct
00158 {
00159   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00160                                        This parameter must be a number between 0 and 0xFFFF */
00161
00162   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00163                                        This parameter must be a number between 0 and 0x7F */
00164
00165   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00166                                        value latched in the time of the last SYNC event.
00167                                        This parameter must be a number between 0 and 0xFFFF */
00168
00169   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00170                                        frequency error counter latched in the time of the last SYNC event.
00171                                        It shows whether the actual frequency is below or above the target.
00172                                        This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00173
00174 }RCC_CRSSynchroInfoTypeDef;
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported constants --------------------------------------------------------*/
00181 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00182   * @{
00183   */
00184
00185 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
00186   * @{
00187   */
00188 #define RCC_LSCOSOURCE_LSI             0x00000000U           /*!< LSI selection for low speed clock output */
00189 #define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00195   * @{
00196   */
00197 #define RCC_PERIPHCLK_USART1           0x00000001U
00198 #define RCC_PERIPHCLK_USART2           0x00000002U
00199 #define RCC_PERIPHCLK_USART3           0x00000004U
00200 #if defined(UART4)
00201 #define RCC_PERIPHCLK_UART4            0x00000008U
00202 #endif /* UART4 */
00203 #if defined(UART5)
00204 #define RCC_PERIPHCLK_UART5            0x00000010U
00205 #endif /* UART5 */
00206 #define RCC_PERIPHCLK_LPUART1          0x00000020U
00207 #define RCC_PERIPHCLK_I2C1             0x00000040U
00208 #define RCC_PERIPHCLK_I2C2             0x00000080U
00209 #define RCC_PERIPHCLK_I2C3             0x00000100U
00210 #define RCC_PERIPHCLK_LPTIM1           0x00000200U
00211 #define RCC_PERIPHCLK_SAI1             0x00000400U
00212 #define RCC_PERIPHCLK_I2S              0x00000800U
00213 #if defined(FDCAN1)
00214 #define RCC_PERIPHCLK_FDCAN            0x00001000U
00215 #endif /* FDCAN1 */
00216 #define RCC_PERIPHCLK_USB              0x00002000U
00217 #define RCC_PERIPHCLK_RNG              0x00004000U
00218 #define RCC_PERIPHCLK_ADC12            0x00008000U
00219 #if defined(ADC345_COMMON)
00220 #define RCC_PERIPHCLK_ADC345           0x00010000U
00221 #endif /* ADC345_COMMON */
00222 #if defined(I2C4)
00223 #define RCC_PERIPHCLK_I2C4             0x00020000U
00224 #endif /* I2C4 */
00225 #if defined(QUADSPI)
00226 #define RCC_PERIPHCLK_QSPI             0x00040000U
00227 #endif /* QUADSPI */
00228 #define RCC_PERIPHCLK_RTC              0x00080000U
00229 /**
00230   * @}
00231   */
00232
00233
00234 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
00235   * @{
00236   */
00237 #define RCC_USART1CLKSOURCE_PCLK2      0x00000000U
00238 #define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
00239 #define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
00240 #define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
00246   * @{
00247   */
00248 #define RCC_USART2CLKSOURCE_PCLK1      0x00000000U
00249 #define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
00250 #define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
00251 #define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
00257   * @{
00258   */
00259 #define RCC_USART3CLKSOURCE_PCLK1      0x00000000U
00260 #define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
00261 #define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
00262 #define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
00263 /**
00264   * @}
00265   */
00266
00267 #if defined(UART4)
00268 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
00269   * @{
00270   */
00271 #define RCC_UART4CLKSOURCE_PCLK1       0x00000000U
00272 #define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
00273 #define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
00274 #define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
00275 /**
00276   * @}
00277   */
00278 #endif /* UART4 */
00279
00280 #if defined(UART5)
00281 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
00282   * @{
00283   */
00284 #define RCC_UART5CLKSOURCE_PCLK1       0x00000000U
00285 #define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
00286 #define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
00287 #define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
00288 /**
00289   * @}
00290   */
00291 #endif /* UART5 */
00292
00293 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
00294   * @{
00295   */
00296 #define RCC_LPUART1CLKSOURCE_PCLK1     0x00000000U
00297 #define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
00298 #define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
00299 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
00305   * @{
00306   */
00307 #define RCC_I2C1CLKSOURCE_PCLK1        0x00000000U
00308 #define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
00309 #define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
00315   * @{
00316   */
00317 #define RCC_I2C2CLKSOURCE_PCLK1        0x00000000U
00318 #define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
00319 #define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
00325   * @{
00326   */
00327 #define RCC_I2C3CLKSOURCE_PCLK1        0x00000000U
00328 #define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
00329 #define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
00335   * @{
00336   */
00337 #define RCC_LPTIM1CLKSOURCE_PCLK1      0x00000000U
00338 #define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
00339 #define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
00340 #define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00346   * @{
00347   */
00348 #define RCC_SAI1CLKSOURCE_SYSCLK       0x00000000U
00349 #define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_0
00350 #define RCC_SAI1CLKSOURCE_EXT          RCC_CCIPR_SAI1SEL_1
00351 #define RCC_SAI1CLKSOURCE_HSI          (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
00357   * @{
00358   */
00359 #define RCC_I2SCLKSOURCE_SYSCLK       0x00000000U
00360 #define RCC_I2SCLKSOURCE_PLL          RCC_CCIPR_I2S23SEL_0
00361 #define RCC_I2SCLKSOURCE_EXT          RCC_CCIPR_I2S23SEL_1
00362 #define RCC_I2SCLKSOURCE_HSI          (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
00363 /**
00364   * @}
00365   */
00366 #if defined(FDCAN1)
00367 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
00368   * @{
00369   */
00370 #define RCC_FDCANCLKSOURCE_HSE          0x00000000U
00371 #define RCC_FDCANCLKSOURCE_PLL          RCC_CCIPR_FDCANSEL_0
00372 #define RCC_FDCANCLKSOURCE_PCLK1        RCC_CCIPR_FDCANSEL_1
00373 /**
00374   * @}
00375   */
00376 #endif /* FDCAN1 */
00377
00378 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
00379   * @{
00380   */
00381 #define RCC_RNGCLKSOURCE_HSI48         0x00000000U
00382 #define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
00388   * @{
00389   */
00390 #define RCC_USBCLKSOURCE_HSI48         0x00000000U
00391 #define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
00397   * @{
00398   */
00399 #define RCC_ADC12CLKSOURCE_NONE        0x00000000U
00400 #define RCC_ADC12CLKSOURCE_PLL         RCC_CCIPR_ADC12SEL_0
00401 #define RCC_ADC12CLKSOURCE_SYSCLK      RCC_CCIPR_ADC12SEL_1
00402 /**
00403   * @}
00404   */
00405
00406 #if defined(ADC345_COMMON)
00407 /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
00408   * @{
00409   */
00410 #define RCC_ADC345CLKSOURCE_NONE     0x00000000U
00411 #define RCC_ADC345CLKSOURCE_PLL      RCC_CCIPR_ADC345SEL_0
00412 #define RCC_ADC345CLKSOURCE_SYSCLK   RCC_CCIPR_ADC345SEL_1
00413 /**
00414   * @}
00415   */
00416 #endif /* ADC345_COMMON */
00417
00418 #if defined(I2C4)
00419 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
00420   * @{
00421   */
00422 #define RCC_I2C4CLKSOURCE_PCLK1        0x00000000U
00423 #define RCC_I2C4CLKSOURCE_SYSCLK       RCC_CCIPR2_I2C4SEL_0
00424 #define RCC_I2C4CLKSOURCE_HSI          RCC_CCIPR2_I2C4SEL_1
00425 /**
00426   * @}
00427   */
00428 #endif /* I2C4 */
00429
00430 #if defined(QUADSPI)
00431 /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
00432   * @{
00433   */
00434 #define RCC_QSPICLKSOURCE_SYSCLK    0x00000000U
00435 #define RCC_QSPICLKSOURCE_HSI       RCC_CCIPR2_QSPISEL_0
00436 #define RCC_QSPICLKSOURCE_PLL       RCC_CCIPR2_QSPISEL_1
00437 /**
00438   * @}
00439   */
00440 #endif /* QUADSPI */
00441
00442 /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
00443   * @{
00444   */
00445 #define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
00451   * @{
00452   */
00453 #define RCC_CRS_NONE                   0x00000000U
00454 #define RCC_CRS_TIMEOUT                0x00000001U
00455 #define RCC_CRS_SYNCOK                 0x00000002U
00456 #define RCC_CRS_SYNCWARN               0x00000004U
00457 #define RCC_CRS_SYNCERR                0x00000008U
00458 #define RCC_CRS_SYNCMISS               0x00000010U
00459 #define RCC_CRS_TRIMOVF                0x00000020U
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
00465   * @{
00466   */
00467 #define RCC_CRS_SYNC_SOURCE_GPIO       0x00000000U             /*!< Synchro Signal source GPIO */
00468 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00469 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00470 /**
00471   * @}
00472   */
00473
00474 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
00475   * @{
00476   */
00477 #define RCC_CRS_SYNC_DIV1        0x00000000U                               /*!< Synchro Signal not divided (default) */
00478 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00479 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00480 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00481 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00482 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00483 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00484 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
00490   * @{
00491   */
00492 #define RCC_CRS_SYNC_POLARITY_RISING   0x00000000U             /*!< Synchro Active on rising edge (default) */
00493 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
00499   * @{
00500   */
00501 #define RCC_CRS_RELOADVALUE_DEFAULT    0x0000BB7FU             /*!< The reset value of the RELOAD field corresponds
00502                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
00508   * @{
00509   */
00510 #define RCC_CRS_ERRORLIMIT_DEFAULT     0x00000022U             /*!< Default Frequency error limit */
00511 /**
00512   * @}
00513   */
00514
00515 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
00516   * @{
00517   */
00518 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U             /*!< The default value is 64, which corresponds to the middle of the trimming interval.
00519                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
00520                                                                       corresponds to a higher output frequency */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
00526   * @{
00527   */
00528 #define RCC_CRS_FREQERRORDIR_UP        0x00000000U               /*!< Upcounting direction, the actual frequency is above the target */
00529 #define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR             /*!< Downcounting direction, the actual frequency is below the target */
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
00535   * @{
00536   */
00537 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
00538 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
00539 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
00540 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
00541 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
00542 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
00543 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
00544
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
00550   * @{
00551   */
00552 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
00553 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
00554 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
00555 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
00556 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
00557 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
00558 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /* Exported macros -----------------------------------------------------------*/
00569 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00570  * @{
00571  */
00572
00573 /** @brief  Macro to configure the USART1 clock (USART1CLK).
00574   *
00575   * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
00576   *          This parameter can be one of the following values:
00577   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
00578   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
00579   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00580   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
00581   * @retval None
00582   */
00583 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
00584                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
00585
00586 /** @brief  Macro to get the USART1 clock source.
00587   * @retval The clock source can be one of the following values:
00588   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
00589   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
00590   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00591   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
00592   */
00593 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
00594
00595 /** @brief  Macro to configure the USART2 clock (USART2CLK).
00596   *
00597   * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
00598   *          This parameter can be one of the following values:
00599   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
00600   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
00601   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
00602   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
00603   * @retval None
00604   */
00605 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
00606                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
00607
00608 /** @brief  Macro to get the USART2 clock source.
00609   * @retval The clock source can be one of the following values:
00610   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
00611   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
00612   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
00613   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
00614   */
00615 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
00616
00617 /** @brief  Macro to configure the USART3 clock (USART3CLK).
00618   *
00619   * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
00620   *          This parameter can be one of the following values:
00621   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
00622   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
00623   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
00624   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
00625   * @retval None
00626   */
00627 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
00628                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
00629
00630 /** @brief  Macro to get the USART3 clock source.
00631   * @retval The clock source can be one of the following values:
00632   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
00633   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
00634   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
00635   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
00636   */
00637 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
00638
00639 #if defined(UART4)
00640 /** @brief  Macro to configure the UART4 clock (UART4CLK).
00641   *
00642   * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
00643   *          This parameter can be one of the following values:
00644   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
00645   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
00646   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
00647   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
00648   * @retval None
00649   */
00650 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
00651                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
00652
00653 /** @brief  Macro to get the UART4 clock source.
00654   * @retval The clock source can be one of the following values:
00655   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
00656   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
00657   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
00658   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
00659   */
00660 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
00661 #endif /* UART4 */
00662
00663 #if defined(UART5)
00664
00665 /** @brief  Macro to configure the UART5 clock (UART5CLK).
00666   *
00667   * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
00668   *          This parameter can be one of the following values:
00669   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
00670   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
00671   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
00672   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
00673   * @retval None
00674   */
00675 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
00676                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
00677
00678 /** @brief  Macro to get the UART5 clock source.
00679   * @retval The clock source can be one of the following values:
00680   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
00681   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
00682   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
00683   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
00684   */
00685 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
00686
00687 #endif /* UART5 */
00688
00689 /** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
00690   *
00691   * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
00692   *          This parameter can be one of the following values:
00693   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
00694   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
00695   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
00696   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
00697   * @retval None
00698   */
00699 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
00700                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
00701
00702 /** @brief  Macro to get the LPUART1 clock source.
00703   * @retval The clock source can be one of the following values:
00704   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
00705   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
00706   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
00707   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
00708   */
00709 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
00710
00711 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
00712   *
00713   * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
00714   *          This parameter can be one of the following values:
00715   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
00716   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
00717   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00718   * @retval None
00719   */
00720 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
00721                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
00722
00723 /** @brief  Macro to get the I2C1 clock source.
00724   * @retval The clock source can be one of the following values:
00725   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
00726   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
00727   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00728   */
00729 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
00730
00731
00732 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
00733   *
00734   * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
00735   *          This parameter can be one of the following values:
00736   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
00737   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
00738   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
00739   * @retval None
00740   */
00741 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
00742                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
00743
00744 /** @brief  Macro to get the I2C2 clock source.
00745   * @retval The clock source can be one of the following values:
00746   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
00747   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
00748   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
00749   */
00750 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
00751
00752 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
00753   *
00754   * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
00755   *          This parameter can be one of the following values:
00756   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
00757   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
00758   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
00759   * @retval None
00760   */
00761 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
00762                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
00763
00764 /** @brief  Macro to get the I2C3 clock source.
00765   * @retval The clock source can be one of the following values:
00766   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
00767   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
00768   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
00769   */
00770 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
00771
00772 #if defined(I2C4)
00773
00774 /** @brief  Macro to configure the I2C4 clock (I2C4CLK).
00775   *
00776   * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
00777   *          This parameter can be one of the following values:
00778   *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
00779   *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
00780   *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
00781   * @retval None
00782   */
00783 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
00784                   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
00785
00786 /** @brief  Macro to get the I2C4 clock source.
00787   * @retval The clock source can be one of the following values:
00788   *            @arg @ref RCC_I2C4CLKSOURCE_PCLK1  PCLK1 selected as I2C4 clock
00789   *            @arg @ref RCC_I2C4CLKSOURCE_HSI  HSI selected as I2C4 clock
00790   *            @arg @ref RCC_I2C4CLKSOURCE_SYSCLK  System Clock selected as I2C4 clock
00791   */
00792 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
00793
00794 #endif /* I2C4 */
00795
00796 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
00797   *
00798   * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
00799   *          This parameter can be one of the following values:
00800   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
00801   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
00802   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
00803   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
00804   * @retval None
00805   */
00806 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
00807                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
00808
00809 /** @brief  Macro to get the LPTIM1 clock source.
00810   * @retval The clock source can be one of the following values:
00811   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
00812   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
00813   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
00814   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
00815   */
00816 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
00817
00818 /**
00819   * @brief  Macro to configure the SAI1 clock source.
00820   * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
00821   *         from the HSI, system PLL, System Clock or external clock.
00822   *          This parameter can be one of the following values:
00823   *             @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
00824   *             @arg @ref RCC_SAI1CLKSOURCE_PLL    SAI1 clock = PLL "Q" clock
00825   *             @arg @ref RCC_SAI1CLKSOURCE_EXT    SAI1 clock = EXT
00826   *             @arg @ref RCC_SAI1CLKSOURCE_HSI    SAI1 clock = HSI
00827   *
00828   * @retval None
00829   */
00830 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
00831                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
00832
00833 /** @brief  Macro to get the SAI1 clock source.
00834   * @retval The clock source can be one of the following values:
00835   *             @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
00836   *             @arg @ref RCC_SAI1CLKSOURCE_PLL    SAI1 clock = PLL "Q" clock
00837   *             @arg @ref RCC_SAI1CLKSOURCE_EXT    SAI1 clock = EXT
00838   *             @arg @ref RCC_SAI1CLKSOURCE_HSI    SAI1 clock = HSI
00839   *
00840   */
00841 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
00842
00843 /**
00844   * @brief  Macro to configure the I2S clock source.
00845   * @param  __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
00846   *         from the HSI, system PLL, System Clock or external clock.
00847   *          This parameter can be one of the following values:
00848   *             @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
00849   *             @arg @ref RCC_I2SCLKSOURCE_PLL    I2S clock = PLL "Q" clock
00850   *             @arg @ref RCC_I2SCLKSOURCE_EXT    I2S clock = EXT
00851   *             @arg @ref RCC_I2SCLKSOURCE_HSI    I2S clock = HSI
00852   *
00853   * @retval None
00854   */
00855 #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\
00856                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
00857
00858 /** @brief  Macro to get the I2S clock source.
00859   * @retval The clock source can be one of the following values:
00860   *             @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
00861   *             @arg @ref RCC_I2SCLKSOURCE_PLL    I2S clock = PLL "Q" clock
00862   *             @arg @ref RCC_I2SCLKSOURCE_EXT    I2S clock = EXT
00863   *             @arg @ref RCC_I2SCLKSOURCE_HSI    I2S clock = HSI
00864   *
00865   */
00866 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
00867
00868 #if defined(FDCAN1)
00869 /**
00870   * @brief  Macro to configure the FDCAN clock source.
00871   * @param  __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived
00872   *         from the HSE, system PLL or PCLK1.
00873   *          This parameter can be one of the following values:
00874   *             @arg @ref RCC_FDCANCLKSOURCE_HSE   FDCAN clock = HSE
00875   *             @arg @ref RCC_FDCANCLKSOURCE_PLL   FDCAN clock = PLL "Q" clock
00876   *             @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
00877   *
00878   * @retval None
00879   */
00880 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\
00881                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
00882
00883 /** @brief  Macro to get the FDCAN clock source.
00884   * @retval The clock source can be one of the following values:
00885   *             @arg @ref RCC_FDCANCLKSOURCE_HSE   FDCAN clock = HSE
00886   *             @arg @ref RCC_FDCANCLKSOURCE_PLL   FDCAN clock = PLL "Q" clock
00887   *             @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
00888   *
00889   */
00890 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
00891 #endif /* FDCAN1 */
00892
00893 /** @brief  Macro to configure the RNG clock.
00894   *
00895   * @note  USB and RNG peripherals share the same 48MHz clock source.
00896   *
00897   * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
00898   *         This parameter can be one of the following values:
00899   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock for devices with HSI48
00900   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
00901   * @retval None
00902   */
00903 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
00904                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
00905
00906 /** @brief  Macro to get the RNG clock.
00907   * @retval The clock source can be one of the following values:
00908   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock for devices with HSI48
00909   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock selected as RNG clock
00910   */
00911 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
00912
00913 #if defined(USB)
00914
00915 /** @brief  Macro to configure the USB clock (USBCLK).
00916   *
00917   * @note  USB, RNG peripherals share the same 48MHz clock source.
00918   *
00919   * @param  __USB_CLKSOURCE__ specifies the USB clock source.
00920   *         This parameter can be one of the following values:
00921   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
00922   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
00923   * @retval None
00924   */
00925 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
00926                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
00927
00928 /** @brief  Macro to get the USB clock source.
00929   * @retval The clock source can be one of the following values:
00930   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
00931   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
00932   */
00933 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
00934
00935 #endif /* USB */
00936
00937 /** @brief  Macro to configure the ADC12 interface clock.
00938   * @param  __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source.
00939   *         This parameter can be one of the following values:
00940   *            @arg @ref RCC_ADC12CLKSOURCE_NONE    No clock selected as ADC12 clock
00941   *            @arg @ref RCC_ADC12CLKSOURCE_PLL     PLL Clock selected as ADC12 clock
00942   *            @arg @ref RCC_ADC12CLKSOURCE_SYSCLK  System Clock selected as ADC12 clock
00943   * @retval None
00944   */
00945 #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
00946                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
00947
00948 /** @brief  Macro to get the ADC12 clock source.
00949   * @retval The clock source can be one of the following values:
00950   *            @arg @ref RCC_ADC12CLKSOURCE_NONE    No clock selected as ADC12 clock
00951   *            @arg @ref RCC_ADC12CLKSOURCE_PLL     PLL Clock selected as ADC12 clock
00952   *            @arg @ref RCC_ADC12CLKSOURCE_SYSCLK  System Clock selected as ADC12 clock
00953   */
00954 #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
00955
00956 #if defined(ADC345_COMMON)
00957 /** @brief  Macro to configure the ADC345 interface clock.
00958   * @param  __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source.
00959   *         This parameter can be one of the following values:
00960   *            @arg @ref RCC_ADC345CLKSOURCE_NONE    No clock selected as ADC345 clock
00961   *            @arg @ref RCC_ADC345CLKSOURCE_PLL     PLL Clock selected as ADC345 clock
00962   *            @arg @ref RCC_ADC345CLKSOURCE_SYSCLK  System Clock selected as ADC345 clock
00963   * @retval None
00964   */
00965 #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
00966                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
00967
00968 /** @brief  Macro to get the ADC345 clock source.
00969   * @retval The clock source can be one of the following values:
00970   *            @arg @ref RCC_ADC345CLKSOURCE_NONE    No clock selected as ADC345 clock
00971   *            @arg @ref RCC_ADC345CLKSOURCE_PLL     PLL Clock selected as ADC345 clock
00972   *            @arg @ref RCC_ADC345CLKSOURCE_SYSCLK  System Clock selected as ADC345 clock
00973   */
00974 #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
00975 #endif /* ADC345_COMMON */
00976
00977 #if defined(QUADSPI)
00978
00979 /** @brief  Macro to configure the QuadSPI clock.
00980   * @param  __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
00981   *         This parameter can be one of the following values:
00982   *            @arg @ref RCC_QSPICLKSOURCE_SYSCLK  System Clock selected as QuadSPI clock
00983   *            @arg @ref RCC_QSPICLKSOURCE_HSI     HSI clock selected as QuadSPI clock
00984   *            @arg @ref RCC_QSPICLKSOURCE_PLL     PLL Q divider clock selected as QuadSPI clock
00985   * @retval None
00986   */
00987 #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
00988                   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
00989
00990 /** @brief  Macro to get the QuadSPI clock source.
00991   * @retval The clock source can be one of the following values:
00992   *            @arg @ref RCC_QSPICLKSOURCE_SYSCLK  System Clock selected as QuadSPI clock
00993   *            @arg @ref RCC_QSPICLKSOURCE_HSI     HSI clock selected as QuadSPI clock
00994   *            @arg @ref RCC_QSPICLKSOURCE_PLL     PLL Q divider clock selected as QuadSPI clock
00995   */
00996 #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
00997
00998 #endif /* QUADSPI */
00999
01000 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
01001   * @brief macros to manage the specified RCC Flags and interrupts.
01002   * @{
01003   */
01004
01005 /**
01006   * @brief Enable the RCC LSE CSS Extended Interrupt Line.
01007   * @retval None
01008   */
01009 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01010
01011 /**
01012   * @brief Disable the RCC LSE CSS Extended Interrupt Line.
01013   * @retval None
01014   */
01015 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01016
01017 /**
01018   * @brief Enable the RCC LSE CSS Event Line.
01019   * @retval None.
01020   */
01021 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01022
01023 /**
01024   * @brief Disable the RCC LSE CSS Event Line.
01025   * @retval None.
01026   */
01027 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01028
01029
01030 /**
01031   * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
01032   * @retval None.
01033   */
01034 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01035
01036
01037 /**
01038   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
01039   * @retval None.
01040   */
01041 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01042
01043
01044 /**
01045   * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
01046   * @retval None.
01047   */
01048 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01049
01050 /**
01051   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
01052   * @retval None.
01053   */
01054 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01055
01056 /**
01057   * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01058   * @retval None.
01059   */
01060 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
01061   do {                                                      \
01062     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
01063     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
01064   } while(0)
01065
01066 /**
01067   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01068   * @retval None.
01069   */
01070 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
01071   do {                                                       \
01072     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
01073     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
01074   } while(0)
01075
01076 /**
01077   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
01078   * @retval EXTI RCC LSE CSS Line Status.
01079   */
01080 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
01081
01082 /**
01083   * @brief Clear the RCC LSE CSS EXTI flag.
01084   * @retval None.
01085   */
01086 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
01087
01088 /**
01089   * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
01090   * @retval None.
01091   */
01092 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
01093
01094
01095 /**
01096   * @brief  Enable the specified CRS interrupts.
01097   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
01098   *          This parameter can be any combination of the following values:
01099   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01100   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01101   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01102   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01103   * @retval None
01104   */
01105 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
01106
01107 /**
01108   * @brief  Disable the specified CRS interrupts.
01109   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
01110   *          This parameter can be any combination of the following values:
01111   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01112   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01113   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01114   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01115   * @retval None
01116   */
01117 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
01118
01119 /** @brief  Check whether the CRS interrupt has occurred or not.
01120   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
01121   *         This parameter can be one of the following values:
01122   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01123   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01124   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01125   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01126   * @retval The new state of __INTERRUPT__ (SET or RESET).
01127   */
01128 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
01129
01130 /** @brief  Clear the CRS interrupt pending bits
01131   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01132   *         This parameter can be any combination of the following values:
01133   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01134   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01135   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01136   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01137   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
01138   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
01139   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
01140   */
01141 /* CRS IT Error Mask */
01142 #define  RCC_CRS_IT_ERROR_MASK                 (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
01143
01144 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
01145                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
01146                                                  { \
01147                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
01148                                                  } \
01149                                                  else \
01150                                                  { \
01151                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
01152                                                  } \
01153                                                } while(0)
01154
01155 /**
01156   * @brief  Check whether the specified CRS flag is set or not.
01157   * @param  __FLAG__ specifies the flag to check.
01158   *          This parameter can be one of the following values:
01159   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01160   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01161   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01162   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01163   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01164   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01165   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01166   * @retval The new state of _FLAG_ (TRUE or FALSE).
01167   */
01168 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
01169
01170 /**
01171   * @brief  Clear the CRS specified FLAG.
01172   * @param __FLAG__ specifies the flag to clear.
01173   *          This parameter can be one of the following values:
01174   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01175   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01176   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01177   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01178   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01179   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01180   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01181   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
01182   * @retval None
01183   */
01184
01185 /* CRS Flag Error Mask */
01186 #define RCC_CRS_FLAG_ERROR_MASK                (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
01187
01188 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
01189                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
01190                                                  { \
01191                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
01192                                                  } \
01193                                                  else \
01194                                                  { \
01195                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
01196                                                  } \
01197                                                } while(0)
01198
01199
01200 /**
01201   * @}
01202   */
01203
01204 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
01205   * @{
01206   */
01207 /**
01208   * @brief  Enable the oscillator clock for frequency error counter.
01209   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
01210   * @retval None
01211   */
01212 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
01213
01214 /**
01215   * @brief  Disable the oscillator clock for frequency error counter.
01216   * @retval None
01217   */
01218 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
01219
01220 /**
01221   * @brief  Enable the automatic hardware adjustment of TRIM bits.
01222   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
01223   * @retval None
01224   */
01225 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01226
01227 /**
01228   * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
01229   * @retval None
01230   */
01231 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01232
01233 /**
01234   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
01235   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
01236   *             of the synchronization source after prescaling. It is then decreased by one in order to
01237   *             reach the expected synchronization on the zero value. The formula is the following:
01238   *             RELOAD = (fTARGET / fSYNC) -1
01239   * @param  __FTARGET__ Target frequency (value in Hz)
01240   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
01241   * @retval None
01242   */
01243 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
01244
01245 /**
01246   * @}
01247   */
01248
01249 /**
01250   * @}
01251   */
01252
01253 /* Exported functions --------------------------------------------------------*/
01254 /** @addtogroup RCCEx_Exported_Functions
01255   * @{
01256   */
01257
01258 /** @addtogroup RCCEx_Exported_Functions_Group1
01259   * @{
01260   */
01261
01262 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01263 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01264 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01265
01266 /**
01267   * @}
01268   */
01269
01270 /** @addtogroup RCCEx_Exported_Functions_Group2
01271   * @{
01272   */
01273
01274 void              HAL_RCCEx_EnableLSECSS(void);
01275 void              HAL_RCCEx_DisableLSECSS(void);
01276 void              HAL_RCCEx_EnableLSECSS_IT(void);
01277 void              HAL_RCCEx_LSECSS_IRQHandler(void);
01278 void              HAL_RCCEx_LSECSS_Callback(void);
01279 void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
01280 void              HAL_RCCEx_DisableLSCO(void);
01281
01282 /**
01283   * @}
01284   */
01285
01286 /** @addtogroup RCCEx_Exported_Functions_Group3
01287   * @{
01288   */
01289
01290 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01291 void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01292 void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01293 uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01294 void              HAL_RCCEx_CRS_IRQHandler(void);
01295 void              HAL_RCCEx_CRS_SyncOkCallback(void);
01296 void              HAL_RCCEx_CRS_SyncWarnCallback(void);
01297 void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01298 void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01299
01300 /**
01301   * @}
01302   */
01303
01304 /**
01305   * @}
01306   */
01307
01308 /* Private macros ------------------------------------------------------------*/
01309 /** @addtogroup RCCEx_Private_Macros
01310   * @{
01311   */
01312
01313 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
01314                                        ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
01315
01316 #if defined(STM32G474xx) || defined(STM32G484xx)
01317
01318 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01319                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01320                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01321                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01322                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
01323                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
01324                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01325                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01326                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01327                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01328                 (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
01329                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01330                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01331                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01332                 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
01333                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01334                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01335                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01336                 (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
01337                 (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
01338                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01339 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
01340
01341 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01342                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01343                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01344                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01345                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
01346                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
01347                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01348                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01349                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01350                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01351                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01352                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01353                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01354                 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
01355                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01356                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01357                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01358                 (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
01359                 (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
01360                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01361 #elif defined(STM32G473xx) || defined(STM32G483xx)
01362
01363 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01364                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01365                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01366                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01367                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
01368                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
01369                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01370                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01371                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01372                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01373                 (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
01374                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01375                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01376                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01377                 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
01378                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01379                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01380                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01381                 (((__SELECTION__) & RCC_PERIPHCLK_ADC345)      == RCC_PERIPHCLK_ADC345)  || \
01382                 (((__SELECTION__) & RCC_PERIPHCLK_QSPI)        == RCC_PERIPHCLK_QSPI)    || \
01383                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01384
01385 #elif defined(STM32G471xx)
01386
01387 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01388                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01389                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01390                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01391                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
01392                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
01393                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01394                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01395                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01396                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01397                 (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
01398                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01399                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01400                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01401                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01402                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01403                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01404                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01405
01406 #elif defined(STM32G431xx) || defined(STM32G441xx)
01407
01408 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01409                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01410                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01411                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01412                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
01413                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01414                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01415                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01416                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01417                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01418                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01419                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01420                 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
01421                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01422                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01423                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01424                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01425
01426 #elif defined(STM32GBK1CB)
01427 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01428                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
01429                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
01430                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
01431                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1) || \
01432                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
01433                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
01434                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
01435                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
01436                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
01437                 (((__SELECTION__) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
01438                 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)   || \
01439                 (((__SELECTION__) & RCC_PERIPHCLK_USB)         == RCC_PERIPHCLK_USB)     || \
01440                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)         == RCC_PERIPHCLK_RNG)     || \
01441                 (((__SELECTION__) & RCC_PERIPHCLK_ADC12)       == RCC_PERIPHCLK_ADC12)   || \
01442                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
01443
01444 #endif /* STM32G474xx || STM32G484xx */
01445
01446 #define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
01447                (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
01448                 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
01449                 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
01450                 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
01451
01452 #define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
01453                (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
01454                 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
01455                 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
01456                 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
01457
01458 #define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
01459                (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
01460                 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
01461                 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
01462                 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
01463
01464 #if defined(UART4)
01465 #define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
01466                (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
01467                 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
01468                 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
01469                 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
01470 #endif /* UART4 */
01471
01472 #if defined(UART5)
01473 #define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
01474                (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
01475                 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
01476                 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
01477                 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
01478
01479 #endif /* UART5 */
01480
01481 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
01482                (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
01483                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
01484                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
01485                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
01486
01487 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
01488                (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
01489                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
01490                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
01491
01492 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
01493                (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
01494                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
01495                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
01496
01497 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
01498                (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
01499                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
01500                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
01501
01502 #if defined(I2C4)
01503
01504 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__)   \
01505                (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
01506                 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
01507                 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
01508
01509 #endif /* I2C4 */
01510
01511 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)  \
01512                (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
01513                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \
01514                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \
01515                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
01516
01517 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__)   \
01518                (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK)  || \
01519                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
01520                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT)     || \
01521                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
01522
01523 #define IS_RCC_I2SCLKSOURCE(__SOURCE__)   \
01524                (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK)  || \
01525                 ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL)     || \
01526                 ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT)     || \
01527                 ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
01528
01529 #if defined(FDCAN1)
01530 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__)   \
01531                (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
01532                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
01533                 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
01534
01535 #endif /* FDCAN1 */
01536 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
01537                (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
01538                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
01539
01540 #if defined(USB)
01541 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
01542                (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
01543                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
01544
01545 #endif /* USB */
01546
01547 #define IS_RCC_ADC12CLKSOURCE(__SOURCE__)  \
01548                (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE)    || \
01549                 ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL)     || \
01550                 ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
01551
01552 #if defined(ADC345_COMMON)
01553 #define IS_RCC_ADC345CLKSOURCE(__SOURCE__)  \
01554                (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE)    || \
01555                 ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL)     || \
01556                 ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
01557 #endif /* ADC345_COMMON */
01558
01559 #if defined(QUADSPI)
01560
01561 #define IS_RCC_QSPICLKSOURCE(__SOURCE__)  \
01562                 (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI)   || \
01563                  ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \
01564                  ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
01565
01566 #endif /* QUADSPI */
01567
01568 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
01569                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
01570                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
01571
01572 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
01573                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
01574                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
01575                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
01576
01577 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
01578                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
01579
01580 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
01581
01582 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
01583
01584 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
01585
01586 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
01587                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
01588
01589 /**
01590   * @}
01591   */
01592
01593 /**
01594   * @}
01595   */
01596
01597 /**
01598   * @}
01599   */
01600
01601 #ifdef __cplusplus
01602 }
01603 #endif
01604
01605 #endif /* STM32G4xx_HAL_RCC_EX_H */
01606
Generated on Wed Dec 6 2023 15:11:27 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rng.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_rng.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Random Number Generator (RNG) peripheral:
00008   *           + Initialization and configuration functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                      ##### How to use this driver #####
00026   ==============================================================================
00027   [..]
00028       The RNG HAL driver can be used as follows:
00029
00030       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00031           in HAL_RNG_MspInit().
00032       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00033       (#) Wait until the 32 bit Random Number Generator contains a valid
00034           random data using (polling/interrupt) mode.
00035       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00036
00037     ##### Callback registration #####
00038     ==================================
00039
00040     [..]
00041     The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
00042     allows the user to configure dynamically the driver callbacks.
00043
00044     [..]
00045     Use Function HAL_RNG_RegisterCallback() to register a user callback.
00046     Function HAL_RNG_RegisterCallback() allows to register following callbacks:
00047     (+) ErrorCallback             : RNG Error Callback.
00048     (+) MspInitCallback           : RNG MspInit.
00049     (+) MspDeInitCallback         : RNG MspDeInit.
00050     This function takes as parameters the HAL peripheral handle, the Callback ID
00051     and a pointer to the user callback function.
00052
00053     [..]
00054     Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
00055     weak (overridden) function.
00056     HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00057     and the Callback ID.
00058     This function allows to reset following callbacks:
00059     (+) ErrorCallback             : RNG Error Callback.
00060     (+) MspInitCallback           : RNG MspInit.
00061     (+) MspDeInitCallback         : RNG MspDeInit.
00062
00063     [..]
00064     For specific callback ReadyDataCallback, use dedicated register callbacks:
00065     respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
00066
00067     [..]
00068     By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
00069     all callbacks are set to the corresponding weak (overridden) functions:
00070     example HAL_RNG_ErrorCallback().
00071     Exception done for MspInit and MspDeInit functions that are respectively
00072     reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
00073     and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
00074     If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
00075     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00076
00077     [..]
00078     Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
00079     Exception done MspInit/MspDeInit that can be registered/unregistered
00080     in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
00081     MspInit/DeInit callbacks can be used during the Init/DeInit.
00082     In that case first register the MspInit/MspDeInit user callbacks
00083     using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
00084     or HAL_RNG_Init() function.
00085
00086     [..]
00087     When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
00088     not defined, the callback registration feature is not available
00089     and weak (overridden) callbacks are used.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32g4xx_hal.h"
00097
00098 /** @addtogroup STM32G4xx_HAL_Driver
00099   * @{
00100   */
00101
00102 #if defined (RNG)
00103
00104 /** @addtogroup RNG
00105   * @brief RNG HAL module driver.
00106   * @{
00107   */
00108
00109 #ifdef HAL_RNG_MODULE_ENABLED
00110
00111 /* Private types -------------------------------------------------------------*/
00112 /* Private defines -----------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup RNG_Private_Constants RNG Private Constants
00116   * @{
00117   */
00118 #define RNG_TIMEOUT_VALUE     2U
00119 /**
00120   * @}
00121   */
00122 /* Private macros ------------------------------------------------------------*/
00123 /* Private functions prototypes ----------------------------------------------*/
00124 /* Private functions ---------------------------------------------------------*/
00125 /* Exported functions --------------------------------------------------------*/
00126
00127 /** @addtogroup RNG_Exported_Functions
00128   * @{
00129   */
00130
00131 /** @addtogroup RNG_Exported_Functions_Group1
00132   *  @brief   Initialization and configuration functions
00133   *
00134 @verbatim
00135  ===============================================================================
00136           ##### Initialization and configuration functions #####
00137  ===============================================================================
00138     [..]  This section provides functions allowing to:
00139       (+) Initialize the RNG according to the specified parameters
00140           in the RNG_InitTypeDef and create the associated handle
00141       (+) DeInitialize the RNG peripheral
00142       (+) Initialize the RNG MSP
00143       (+) DeInitialize RNG MSP
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  Initializes the RNG peripheral and creates the associated handle.
00151   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00152   *                the configuration information for RNG.
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00156 {
00157   /* Check the RNG handle allocation */
00158   if (hrng == NULL)
00159   {
00160     return HAL_ERROR;
00161   }
00162   /* Check the parameters */
00163   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00164   assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
00165
00166 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00167   if (hrng->State == HAL_RNG_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hrng->Lock = HAL_UNLOCKED;
00171
00172     hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
00173     hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
00174
00175     if (hrng->MspInitCallback == NULL)
00176     {
00177       hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
00178     }
00179
00180     /* Init the low level hardware */
00181     hrng->MspInitCallback(hrng);
00182   }
00183 #else
00184   if (hrng->State == HAL_RNG_STATE_RESET)
00185   {
00186     /* Allocate lock resource and initialize it */
00187     hrng->Lock = HAL_UNLOCKED;
00188
00189     /* Init the low level hardware */
00190     HAL_RNG_MspInit(hrng);
00191   }
00192 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00193
00194   /* Change RNG peripheral state */
00195   hrng->State = HAL_RNG_STATE_BUSY;
00196
00197   /* Clock Error Detection Configuration */
00198   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
00199
00200   /* Enable the RNG Peripheral */
00201   __HAL_RNG_ENABLE(hrng);
00202
00203   /* Initialize the RNG state */
00204   hrng->State = HAL_RNG_STATE_READY;
00205
00206   /* Initialise the error code */
00207   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213 /**
00214   * @brief  DeInitializes the RNG peripheral.
00215   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00216   *                the configuration information for RNG.
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00220 {
00221   /* Check the RNG handle allocation */
00222   if (hrng == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   /* Clear Clock Error Detection bit */
00228   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
00229   /* Disable the RNG Peripheral */
00230   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00231
00232   /* Clear RNG interrupt status flags */
00233   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00234
00235 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00236   if (hrng->MspDeInitCallback == NULL)
00237   {
00238     hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
00239   }
00240
00241   /* DeInit the low level hardware */
00242   hrng->MspDeInitCallback(hrng);
00243 #else
00244   /* DeInit the low level hardware */
00245   HAL_RNG_MspDeInit(hrng);
00246 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00247
00248   /* Update the RNG state */
00249   hrng->State = HAL_RNG_STATE_RESET;
00250
00251   /* Initialise the error code */
00252   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00253
00254   /* Release Lock */
00255   __HAL_UNLOCK(hrng);
00256
00257   /* Return the function status */
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Initializes the RNG MSP.
00263   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00264   *                the configuration information for RNG.
00265   * @retval None
00266   */
00267 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(hrng);
00271   /* NOTE : This function should not be modified. When the callback is needed,
00272             function HAL_RNG_MspInit must be implemented in the user file.
00273    */
00274 }
00275
00276 /**
00277   * @brief  DeInitializes the RNG MSP.
00278   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00279   *                the configuration information for RNG.
00280   * @retval None
00281   */
00282 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(hrng);
00286   /* NOTE : This function should not be modified. When the callback is needed,
00287             function HAL_RNG_MspDeInit must be implemented in the user file.
00288    */
00289 }
00290
00291 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00292 /**
00293   * @brief  Register a User RNG Callback
00294   *         To be used instead of the weak predefined callback
00295   * @param  hrng RNG handle
00296   * @param  CallbackID ID of the callback to be registered
00297   *         This parameter can be one of the following values:
00298   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00299   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00300   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00301   * @param  pCallback pointer to the Callback function
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
00305                                            pRNG_CallbackTypeDef pCallback)
00306 {
00307   HAL_StatusTypeDef status = HAL_OK;
00308
00309   if (pCallback == NULL)
00310   {
00311     /* Update the error code */
00312     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00313     return HAL_ERROR;
00314   }
00315
00316   if (HAL_RNG_STATE_READY == hrng->State)
00317   {
00318     switch (CallbackID)
00319     {
00320       case HAL_RNG_ERROR_CB_ID :
00321         hrng->ErrorCallback = pCallback;
00322         break;
00323
00324       case HAL_RNG_MSPINIT_CB_ID :
00325         hrng->MspInitCallback = pCallback;
00326         break;
00327
00328       case HAL_RNG_MSPDEINIT_CB_ID :
00329         hrng->MspDeInitCallback = pCallback;
00330         break;
00331
00332       default :
00333         /* Update the error code */
00334         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00335         /* Return error status */
00336         status =  HAL_ERROR;
00337         break;
00338     }
00339   }
00340   else if (HAL_RNG_STATE_RESET == hrng->State)
00341   {
00342     switch (CallbackID)
00343     {
00344       case HAL_RNG_MSPINIT_CB_ID :
00345         hrng->MspInitCallback = pCallback;
00346         break;
00347
00348       case HAL_RNG_MSPDEINIT_CB_ID :
00349         hrng->MspDeInitCallback = pCallback;
00350         break;
00351
00352       default :
00353         /* Update the error code */
00354         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00355         /* Return error status */
00356         status =  HAL_ERROR;
00357         break;
00358     }
00359   }
00360   else
00361   {
00362     /* Update the error code */
00363     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00364     /* Return error status */
00365     status =  HAL_ERROR;
00366   }
00367
00368   return status;
00369 }
00370
00371 /**
00372   * @brief  Unregister an RNG Callback
00373   *         RNG callback is redirected to the weak predefined callback
00374   * @param  hrng RNG handle
00375   * @param  CallbackID ID of the callback to be unregistered
00376   *         This parameter can be one of the following values:
00377   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00378   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00379   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00380   * @retval HAL status
00381   */
00382 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
00383 {
00384   HAL_StatusTypeDef status = HAL_OK;
00385
00386
00387   if (HAL_RNG_STATE_READY == hrng->State)
00388   {
00389     switch (CallbackID)
00390     {
00391       case HAL_RNG_ERROR_CB_ID :
00392         hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
00393         break;
00394
00395       case HAL_RNG_MSPINIT_CB_ID :
00396         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00397         break;
00398
00399       case HAL_RNG_MSPDEINIT_CB_ID :
00400         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
00401         break;
00402
00403       default :
00404         /* Update the error code */
00405         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00406         /* Return error status */
00407         status =  HAL_ERROR;
00408         break;
00409     }
00410   }
00411   else if (HAL_RNG_STATE_RESET == hrng->State)
00412   {
00413     switch (CallbackID)
00414     {
00415       case HAL_RNG_MSPINIT_CB_ID :
00416         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00417         break;
00418
00419       case HAL_RNG_MSPDEINIT_CB_ID :
00420         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
00421         break;
00422
00423       default :
00424         /* Update the error code */
00425         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00426         /* Return error status */
00427         status =  HAL_ERROR;
00428         break;
00429     }
00430   }
00431   else
00432   {
00433     /* Update the error code */
00434     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00435     /* Return error status */
00436     status =  HAL_ERROR;
00437   }
00438
00439   return status;
00440 }
00441
00442 /**
00443   * @brief  Register Data Ready RNG Callback
00444   *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
00445   * @param  hrng RNG handle
00446   * @param  pCallback pointer to the Data Ready Callback function
00447   * @retval HAL status
00448   */
00449 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
00450 {
00451   HAL_StatusTypeDef status = HAL_OK;
00452
00453   if (pCallback == NULL)
00454   {
00455     /* Update the error code */
00456     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00457     return HAL_ERROR;
00458   }
00459   /* Process locked */
00460   __HAL_LOCK(hrng);
00461
00462   if (HAL_RNG_STATE_READY == hrng->State)
00463   {
00464     hrng->ReadyDataCallback = pCallback;
00465   }
00466   else
00467   {
00468     /* Update the error code */
00469     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00470     /* Return error status */
00471     status =  HAL_ERROR;
00472   }
00473
00474   /* Release Lock */
00475   __HAL_UNLOCK(hrng);
00476   return status;
00477 }
00478
00479 /**
00480   * @brief  UnRegister the Data Ready RNG Callback
00481   *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
00482   * @param  hrng RNG handle
00483   * @retval HAL status
00484   */
00485 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
00486 {
00487   HAL_StatusTypeDef status = HAL_OK;
00488
00489   /* Process locked */
00490   __HAL_LOCK(hrng);
00491
00492   if (HAL_RNG_STATE_READY == hrng->State)
00493   {
00494     hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
00495   }
00496   else
00497   {
00498     /* Update the error code */
00499     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00500     /* Return error status */
00501     status =  HAL_ERROR;
00502   }
00503
00504   /* Release Lock */
00505   __HAL_UNLOCK(hrng);
00506   return status;
00507 }
00508
00509 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00510
00511 /**
00512   * @}
00513   */
00514
00515 /** @addtogroup RNG_Exported_Functions_Group2
00516   *  @brief   Peripheral Control functions
00517   *
00518 @verbatim
00519  ===============================================================================
00520                       ##### Peripheral Control functions #####
00521  ===============================================================================
00522     [..]  This section provides functions allowing to:
00523       (+) Get the 32 bit Random number
00524       (+) Get the 32 bit Random number with interrupt enabled
00525       (+) Handle RNG interrupt request
00526
00527 @endverbatim
00528   * @{
00529   */
00530
00531 /**
00532   * @brief  Generates a 32-bit random number.
00533   * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
00534   *         random number is available in the DR register (RNG_FLAG_DRDY flag set
00535   *         whenever a random number is available through the RNG_DR register).
00536   *         After transitioning from 0 to 1 (random number available),
00537   *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
00538   *         four words from the RNG_DR register, i.e. further function calls
00539   *         will immediately return a new u32 random number (additional words are
00540   *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
00541   * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
00542   *         flag is automatically cleared.
00543   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00544   *                the configuration information for RNG.
00545   * @param  random32bit pointer to generated random number variable if successful.
00546   * @retval HAL status
00547   */
00548
00549 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00550 {
00551   uint32_t tickstart;
00552   HAL_StatusTypeDef status = HAL_OK;
00553
00554   /* Process Locked */
00555   __HAL_LOCK(hrng);
00556
00557   /* Check RNG peripheral state */
00558   if (hrng->State == HAL_RNG_STATE_READY)
00559   {
00560     /* Change RNG peripheral state */
00561     hrng->State = HAL_RNG_STATE_BUSY;
00562
00563     /* Get tick */
00564     tickstart = HAL_GetTick();
00565
00566     /* Check if data register contains valid random data */
00567     while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00568     {
00569       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00570       {
00571         /* New check to avoid false timeout detection in case of preemption */
00572         if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00573         {
00574           hrng->State = HAL_RNG_STATE_READY;
00575           hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00576           /* Process Unlocked */
00577           __HAL_UNLOCK(hrng);
00578           return HAL_ERROR;
00579         }
00580       }
00581     }
00582
00583     /* Get a 32bit Random number */
00584     hrng->RandomNumber = hrng->Instance->DR;
00585     *random32bit = hrng->RandomNumber;
00586
00587     hrng->State = HAL_RNG_STATE_READY;
00588   }
00589   else
00590   {
00591     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00592     status = HAL_ERROR;
00593   }
00594
00595   /* Process Unlocked */
00596   __HAL_UNLOCK(hrng);
00597
00598   return status;
00599 }
00600
00601 /**
00602   * @brief  Generates a 32-bit random number in interrupt mode.
00603   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00604   *                the configuration information for RNG.
00605   * @retval HAL status
00606   */
00607 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00608 {
00609   HAL_StatusTypeDef status = HAL_OK;
00610
00611   /* Process Locked */
00612   __HAL_LOCK(hrng);
00613
00614   /* Check RNG peripheral state */
00615   if (hrng->State == HAL_RNG_STATE_READY)
00616   {
00617     /* Change RNG peripheral state */
00618     hrng->State = HAL_RNG_STATE_BUSY;
00619
00620     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00621     __HAL_RNG_ENABLE_IT(hrng);
00622   }
00623   else
00624   {
00625     /* Process Unlocked */
00626     __HAL_UNLOCK(hrng);
00627
00628     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00629     status = HAL_ERROR;
00630   }
00631
00632   return status;
00633 }
00634
00635 /**
00636   * @brief  Handles RNG interrupt request.
00637   * @note   In the case of a clock error, the RNG is no more able to generate
00638   *         random numbers because the PLL48CLK clock is not correct. User has
00639   *         to check that the clock controller is correctly configured to provide
00640   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00641   *         The clock error has no impact on the previously generated
00642   *         random numbers, and the RNG_DR register contents can be used.
00643   * @note   In the case of a seed error, the generation of random numbers is
00644   *         interrupted as long as the SECS bit is '1'. If a number is
00645   *         available in the RNG_DR register, it must not be used because it may
00646   *         not have enough entropy. In this case, it is recommended to clear the
00647   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00648   *         the RNG peripheral to reinitialize and restart the RNG.
00649   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00650   *         or CEIS are set.
00651   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00652   *                the configuration information for RNG.
00653   * @retval None
00654
00655   */
00656 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00657 {
00658   uint32_t rngclockerror = 0U;
00659   uint32_t itflag   = hrng->Instance->SR;
00660
00661   /* RNG clock error interrupt occurred */
00662   if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
00663   {
00664     /* Update the error code */
00665     hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
00666     rngclockerror = 1U;
00667   }
00668   else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
00669   {
00670     /* Update the error code */
00671     hrng->ErrorCode = HAL_RNG_ERROR_SEED;
00672     rngclockerror = 1U;
00673   }
00674   else
00675   {
00676     /* Nothing to do */
00677   }
00678
00679   if (rngclockerror == 1U)
00680   {
00681     /* Change RNG peripheral state */
00682     hrng->State = HAL_RNG_STATE_ERROR;
00683
00684 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00685     /* Call registered Error callback */
00686     hrng->ErrorCallback(hrng);
00687 #else
00688     /* Call legacy weak Error callback */
00689     HAL_RNG_ErrorCallback(hrng);
00690 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00691
00692     /* Clear the clock error flag */
00693     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
00694
00695     return;
00696   }
00697
00698   /* Check RNG data ready interrupt occurred */
00699   if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
00700   {
00701     /* Generate random number once, so disable the IT */
00702     __HAL_RNG_DISABLE_IT(hrng);
00703
00704     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00705     hrng->RandomNumber = hrng->Instance->DR;
00706
00707     if (hrng->State != HAL_RNG_STATE_ERROR)
00708     {
00709       /* Change RNG peripheral state */
00710       hrng->State = HAL_RNG_STATE_READY;
00711       /* Process Unlocked */
00712       __HAL_UNLOCK(hrng);
00713
00714 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00715       /* Call registered Data Ready callback */
00716       hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
00717 #else
00718       /* Call legacy weak Data Ready callback */
00719       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00720 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00721     }
00722   }
00723 }
00724
00725 /**
00726   * @brief  Read latest generated random number.
00727   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00728   *                the configuration information for RNG.
00729   * @retval random value
00730   */
00731 uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
00732 {
00733   return (hrng->RandomNumber);
00734 }
00735
00736 /**
00737   * @brief  Data Ready callback in non-blocking mode.
00738   * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
00739   *         from DR register in IRQ Handler and is provided as callback parameter.
00740   *         Depending on valid data available in the conditioning output buffer,
00741   *         additional words can be read by the application from DR register till
00742   *         DRDY bit remains high.
00743   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00744   *                the configuration information for RNG.
00745   * @param  random32bit generated random number.
00746   * @retval None
00747   */
00748 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00749 {
00750   /* Prevent unused argument(s) compilation warning */
00751   UNUSED(hrng);
00752   UNUSED(random32bit);
00753   /* NOTE : This function should not be modified. When the callback is needed,
00754             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00755    */
00756 }
00757
00758 /**
00759   * @brief  RNG error callbacks.
00760   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00761   *                the configuration information for RNG.
00762   * @retval None
00763   */
00764 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00765 {
00766   /* Prevent unused argument(s) compilation warning */
00767   UNUSED(hrng);
00768   /* NOTE : This function should not be modified. When the callback is needed,
00769             function HAL_RNG_ErrorCallback must be implemented in the user file.
00770    */
00771 }
00772 /**
00773   * @}
00774   */
00775
00776
00777 /** @addtogroup RNG_Exported_Functions_Group3
00778   *  @brief   Peripheral State functions
00779   *
00780 @verbatim
00781  ===============================================================================
00782                       ##### Peripheral State functions #####
00783  ===============================================================================
00784     [..]
00785     This subsection permits to get in run-time the status of the peripheral
00786     and the data flow.
00787
00788 @endverbatim
00789   * @{
00790   */
00791
00792 /**
00793   * @brief  Returns the RNG state.
00794   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00795   *                the configuration information for RNG.
00796   * @retval HAL state
00797   */
00798 HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
00799 {
00800   return hrng->State;
00801 }
00802
00803 /**
00804   * @brief  Return the RNG handle error code.
00805   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00806   * @retval RNG Error Code
00807   */
00808 uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
00809 {
00810   /* Return RNG Error Code */
00811   return hrng->ErrorCode;
00812 }
00813 /**
00814   * @}
00815   */
00816
00817 /**
00818   * @}
00819   */
00820
00821
00822 #endif /* HAL_RNG_MODULE_ENABLED */
00823 /**
00824   * @}
00825   */
00826
00827 #endif /* RNG */
00828
00829 /**
00830   * @}
00831   */
00832
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rng.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_rng.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_RNG_H
00021 #define STM32G4xx_HAL_RNG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @defgroup RNG RNG
00037   * @brief RNG HAL module driver
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup RNG_Exported_Types RNG Exported Types
00044   * @{
00045   */
00046
00047 /** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
00053 } RNG_InitTypeDef;
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
00060   * @{
00061   */
00062 typedef enum
00063 {
00064   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00065   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00066   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00067   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00068   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00069
00070 } HAL_RNG_StateTypeDef;
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
00077   * @{
00078   */
00079 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00080 typedef struct  __RNG_HandleTypeDef
00081 #else
00082 typedef struct
00083 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00084 {
00085   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00086
00087   RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
00088
00089   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00090
00091   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00092
00093   __IO  uint32_t              ErrorCode;    /*!< RNG Error code          */
00094
00095   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00096
00097 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00098   void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
00099   void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
00100
00101   void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
00102   void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
00103 #endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
00104
00105 } RNG_HandleTypeDef;
00106
00107 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00108 /**
00109   * @brief  HAL RNG Callback ID enumeration definition
00110   */
00111 typedef enum
00112 {
00113   HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
00114
00115   HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
00116   HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
00117
00118 } HAL_RNG_CallbackIDTypeDef;
00119
00120 /**
00121   * @brief  HAL RNG Callback pointer definition
00122   */
00123 typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
00124 typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
00125
00126 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00142   * @{
00143   */
00144 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00145 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00146 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00152   * @{
00153   */
00154 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00155 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00156 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
00162   * @{
00163   */
00164 #define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
00165 #define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup RNG_Error_Definition   RNG Error Definition
00171   * @{
00172   */
00173 #define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error          */
00174 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00175 #define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
00176 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00177 #define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error     */
00178 #define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
00179 #define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
00180 #define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Exported macros -----------------------------------------------------------*/
00190 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00191   * @{
00192   */
00193
00194 /** @brief Reset RNG handle state
00195   * @param  __HANDLE__ RNG Handle
00196   * @retval None
00197   */
00198 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00199 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00200                                                        (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
00201                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00202                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00203                                                     } while(0U)
00204 #else
00205 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00206 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00207
00208 /**
00209   * @brief  Enables the RNG peripheral.
00210   * @param  __HANDLE__ RNG Handle
00211   * @retval None
00212   */
00213 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00214
00215 /**
00216   * @brief  Disables the RNG peripheral.
00217   * @param  __HANDLE__ RNG Handle
00218   * @retval None
00219   */
00220 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00221
00222 /**
00223   * @brief  Check the selected RNG flag status.
00224   * @param  __HANDLE__ RNG Handle
00225   * @param  __FLAG__ RNG flag
00226   *          This parameter can be one of the following values:
00227   *            @arg RNG_FLAG_DRDY:  Data ready
00228   *            @arg RNG_FLAG_CECS:  Clock error current status
00229   *            @arg RNG_FLAG_SECS:  Seed error current status
00230   * @retval The new state of __FLAG__ (SET or RESET).
00231   */
00232 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00233
00234 /**
00235   * @brief  Clears the selected RNG flag status.
00236   * @param  __HANDLE__ RNG handle
00237   * @param  __FLAG__ RNG flag to clear
00238   * @note   WARNING: This is a dummy macro for HAL code alignment,
00239   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00240   * @retval None
00241   */
00242 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00243
00244 /**
00245   * @brief  Enables the RNG interrupts.
00246   * @param  __HANDLE__ RNG Handle
00247   * @retval None
00248   */
00249 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00250
00251 /**
00252   * @brief  Disables the RNG interrupts.
00253   * @param  __HANDLE__ RNG Handle
00254   * @retval None
00255   */
00256 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00257
00258 /**
00259   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00260   * @param  __HANDLE__ RNG Handle
00261   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
00262   *         This parameter can be one of the following values:
00263   *            @arg RNG_IT_DRDY: Data ready interrupt
00264   *            @arg RNG_IT_CEI: Clock error interrupt
00265   *            @arg RNG_IT_SEI: Seed error interrupt
00266   * @retval The new state of __INTERRUPT__ (SET or RESET).
00267   */
00268 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00269
00270 /**
00271   * @brief  Clear the RNG interrupt status flags.
00272   * @param  __HANDLE__ RNG Handle
00273   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
00274   *          This parameter can be one of the following values:
00275   *            @arg RNG_IT_CEI: Clock error interrupt
00276   *            @arg RNG_IT_SEI: Seed error interrupt
00277   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00278   * @retval None
00279   */
00280 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00281
00282 /**
00283   * @}
00284   */
00285
00286 /* Exported functions --------------------------------------------------------*/
00287 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00288   * @{
00289   */
00290
00291 /** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
00292   * @{
00293   */
00294 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00295 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
00296 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00297 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00298
00299 /* Callbacks Register/UnRegister functions  ***********************************/
00300 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00301 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
00302                                            pRNG_CallbackTypeDef pCallback);
00303 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
00304
00305 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
00306 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
00307 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00314   * @{
00315   */
00316 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00317 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00318 uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
00319
00320 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00321 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00322 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00329   * @{
00330   */
00331 HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
00332 uint32_t             HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Private macros ------------------------------------------------------------*/
00342 /** @defgroup RNG_Private_Macros RNG Private Macros
00343   * @{
00344   */
00345 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00346                        ((IT) == RNG_IT_SEI))
00347
00348 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00349                            ((FLAG) == RNG_FLAG_CECS) || \
00350                            ((FLAG) == RNG_FLAG_SECS))
00351
00352 /**
00353   * @brief Verify the RNG Clock Error Detection mode.
00354   * @param __MODE__ RNG Clock Error Detection mode
00355   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00356   */
00357 #define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
00358                                 ((__MODE__) == RNG_CED_DISABLE))
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 #endif /* RNG */
00368
00369 /**
00370   * @}
00371   */
00372
00373 #ifdef __cplusplus
00374 }
00375 #endif
00376
00377
00378 #endif /* STM32G4xx_HAL_RNG_H */
00379
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_rtc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real-Time Clock (RTC) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Calendar (Time and Date) configuration
00010   *           + Alarms (Alarm A and Alarm B) configuration
00011   *           + WakeUp Timer configuration
00012   *           + TimeStamp configuration
00013   *           + Tampers configuration
00014   *           + Backup Data Registers configuration
00015   *           + RTC Tamper and TimeStamp Pins Selection
00016   *           + Interrupts and flags management
00017   *
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * Copyright (c) 2019 STMicroelectronics.
00022   * All rights reserved.
00023   *
00024   * This software is licensed under terms that can be found in the LICENSE file
00025   * in the root directory of this software component.
00026   * If no LICENSE file comes with this software, it is provided AS-IS.
00027   *
00028   ******************************************************************************
00029   @verbatim
00030  ===============================================================================
00031                           ##### RTC Operating Condition #####
00032  ===============================================================================
00033   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00034        from the VBAT voltage when the main VDD supply is powered off.
00035        To retain the content of the RTC backup registers and supply the RTC
00036        when VDD is turned off, VBAT pin can be connected to an optional
00037        standby voltage supplied by a battery or by another source.
00038
00039                    ##### Backup Domain Reset #####
00040  ===============================================================================
00041   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00042        to their reset values.
00043        A backup domain reset is generated when one of the following events occurs:
00044     (#) Software reset, triggered by setting the BDRST bit in the
00045         RCC Backup domain control register (RCC_BDCR).
00046     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00047     (#) Tamper detection event resets all data backup registers.
00048
00049                    ##### Backup Domain Access #####
00050   ==================================================================
00051   [..] After reset, the backup domain (RTC registers and RTC backup data registers)
00052        is protected against possible unwanted write accesses.
00053   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00054     (+) Enable the Power Controller (PWR) APB1 interface clock using the
00055         __HAL_RCC_PWR_CLK_ENABLE() function.
00056     (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00057     (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
00058     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
00059
00060   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00061     (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00062         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
00063     (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00064
00065                   ##### How to use RTC Driver #####
00066  ===================================================================
00067   [..]
00068     (+) Enable the RTC domain access (see description in the section above).
00069     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00070         format using the HAL_RTC_Init() function.
00071
00072   *** Time and Date configuration ***
00073   ===================================
00074   [..]
00075     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00076         and HAL_RTC_SetDate() functions.
00077     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00078
00079   *** Alarm configuration ***
00080   ===========================
00081   [..]
00082     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00083             You can also configure the RTC Alarm with interrupt mode using the
00084             HAL_RTC_SetAlarm_IT() function.
00085     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00086
00087                   ##### RTC and low power modes #####
00088   ==================================================================
00089   [..] The MCU can be woken up from a low power mode by an RTC alternate
00090        function.
00091   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00092        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00093        These RTC alternate functions can wake up the system from the Stop and
00094        Standby low power modes.
00095   [..] The system can also wake up from low power modes without depending
00096        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00097        or the RTC wakeup events.
00098   [..] The RTC provides a programmable time base for waking up from the
00099        Stop or Standby mode at regular intervals.
00100        Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
00101        is LSE or LSI.
00102
00103   *** Callback registration ***
00104   =============================================
00105   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00106   not defined, the callback registration feature is not available and all callbacks
00107   are set to the corresponding weak functions. This is the recommended configuration
00108   in order to optimize memory/code consumption footprint/performances.
00109
00110   [..]
00111   The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
00112   allows the user to configure dynamically the driver callbacks.
00113   Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
00114
00115   [..]
00116   Function HAL_RTC_RegisterCallback() allows to register following callbacks:
00117     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00118     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00119     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00120     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00121     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00122     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00123     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00124     (+) Tamper4EventCallback         : RTC Tamper 4 Event callback.
00125     (+) Tamper5EventCallback         : RTC Tamper 5 Event callback.
00126     (+) Tamper6EventCallback         : RTC Tamper 6 Event callback.
00127     (+) Tamper7EventCallback         : RTC Tamper 7 Event callback.
00128     (+) Tamper8EventCallback         : RTC Tamper 8 Event callback.
00129     (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback.
00130     (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback.
00131     (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback.
00132     (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback.
00133     (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback.
00134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
00135     (+) AlarmAEventCallback_S          : RTC Alarm A Event callback_S
00136     (+) AlarmBEventCallback_S          : RTC Alarm B Event callback_S.
00137     (+) TimeStampEventCallback_S       : RTC TimeStampEvent callback_S.
00138     (+) WakeUpTimerEventCallback_S     : RTC WakeUpTimerEvent callback_S.
00139     (+) Tamper1EventCallback_S         : RTC Tamper 1 Event callback_S.
00140     (+) Tamper2EventCallback_S         : RTC Tamper 2 Event callback_S.
00141     (+) Tamper3EventCallback_S         : RTC Tamper 3 Event callback_S.
00142     (+) Tamper4EventCallback_S         : RTC Tamper 4 Event callback_S.
00143     (+) Tamper5EventCallback_S         : RTC Tamper 5 Event callback_S.
00144     (+) Tamper6EventCallback_S         : RTC Tamper 6 Event callback_S.
00145     (+) Tamper7EventCallback_S         : RTC Tamper 7 Event callback_S.
00146     (+) Tamper8EventCallback_S         : RTC Tamper 8 Event callback_S.
00147     (+) InternalTamper1EventCallback_S : RTC InternalTamper 1 Event callback_S.
00148     (+) InternalTamper2EventCallback_S : RTC InternalTamper 2 Event callback_S.
00149     (+) InternalTamper3EventCallback_S : RTC InternalTamper 3 Event callback_S.
00150     (+) InternalTamper5EventCallback_S : RTC InternalTamper 5 Event callback_S.
00151     (+) InternalTamper8EventCallback_S : RTC InternalTamper 8 Event callback_S.
00152 #endif
00153     (+) MspInitCallback              : RTC MspInit callback.
00154     (+) MspDeInitCallback            : RTC MspDeInit callback.
00155   [..]
00156   This function takes as parameters the HAL peripheral handle, the Callback ID
00157   and a pointer to the user callback function.
00158
00159   [..]
00160   Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
00161   weak function.
00162   HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00163   and the Callback ID.
00164   This function allows to reset following callbacks:
00165     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00166     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00167     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00168     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00169     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00170     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00171     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00172     (+) Tamper4EventCallback         : RTC Tamper 4 Event callback.
00173     (+) Tamper5EventCallback         : RTC Tamper 5 Event callback.
00174     (+) Tamper6EventCallback         : RTC Tamper 6 Event callback.
00175     (+) Tamper7EventCallback         : RTC Tamper 7 Event callback.
00176     (+) Tamper8EventCallback         : RTC Tamper 8 Event callback.
00177     (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Event callback.
00178     (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Event callback.
00179     (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback.
00180     (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback.
00181     (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback.
00182     (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback.
00183     (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Event callback.
00184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
00185     (+) AlarmAEventCallback_S          : RTC Alarm A Event callback secure.
00186     (+) AlarmBEventCallback_S          : RTC Alarm B Event callback secure.
00187     (+) TimeStampEventCallback_S       : RTC TimeStamp Event callback secure.
00188     (+) WakeUpTimerEventCallback_S     : RTC WakeUpTimer Event callback secure.
00189     (+) Tamper1EventCallback_S         : RTC Tamper 1 Event callback secure.
00190     (+) Tamper2EventCallback_S         : RTC Tamper 2 Event callback secure.
00191     (+) Tamper3EventCallback_S         : RTC Tamper 3 Event callback secure.
00192     (+) Tamper4EventCallback_S         : RTC Tamper 4 Event callback secure.
00193     (+) Tamper5EventCallback_S         : RTC Tamper 5 Event callback secure.
00194     (+) Tamper6EventCallback_S         : RTC Tamper 6 Event callback secure.
00195     (+) Tamper7EventCallback_S         : RTC Tamper 7 Event callback secure.
00196     (+) Tamper8EventCallback_S         : RTC Tamper 8 Event callback secure.
00197     (+) InternalTamper1EventCallback_S : RTC Internal Tamper 1 Event callback secure.
00198     (+) InternalTamper2EventCallback_S : RTC Internal Tamper 2 Event callback secure.
00199     (+) InternalTamper3EventCallback_S : RTC Internal Tamper 3 Event callback secure.
00200     (+) InternalTamper4EventCallback_S : RTC Internal Tamper 4 Event callback secure.
00201     (+) InternalTamper5EventCallback_S : RTC Internal Tamper 5 Event callback secure.
00202     (+) InternalTamper6EventCallback_S : RTC Internal Tamper 6 Event callback secure.
00203     (+) InternalTamper8EventCallback_S : RTC Internal Tamper 8 Event callback secure.
00204 #endif
00205     (+) MspInitCallback              : RTC MspInit callback.
00206     (+) MspDeInitCallback            : RTC MspDeInit callback.
00207
00208   [..]
00209   By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
00210   all callbacks are set to the corresponding weak functions :
00211   examples AlarmAEventCallback(), TimeStampEventCallback().
00212   Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
00213   in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
00214   (not registered beforehand).
00215   If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
00216   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00217
00218   [..]
00219   Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
00220   Exception done MspInit/MspDeInit that can be registered/unregistered
00221   in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
00222   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00223   In that case first register the MspInit/MspDeInit user callbacks
00224   using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
00225   or HAL_RTC_Init() function.
00226
00227   [..]
00228   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00229   not defined, the callback registration feature is not available and all callbacks
00230   are set to the corresponding weak functions.
00231
00232   @endverbatim
00233   ******************************************************************************
00234   */
00235
00236 /* Includes ------------------------------------------------------------------*/
00237 #include "stm32g4xx_hal.h"
00238
00239 /** @addtogroup STM32G4xx_HAL_Driver
00240   * @{
00241   */
00242
00243
00244 /** @addtogroup RTC
00245   * @brief RTC HAL module driver
00246   * @{
00247   */
00248
00249 #ifdef HAL_RTC_MODULE_ENABLED
00250
00251 /* Private typedef -----------------------------------------------------------*/
00252 /* Private define ------------------------------------------------------------*/
00253 /* Private macro -------------------------------------------------------------*/
00254 /* Private variables ---------------------------------------------------------*/
00255 /* Private function prototypes -----------------------------------------------*/
00256 /* Exported functions --------------------------------------------------------*/
00257
00258 /** @addtogroup RTC_Exported_Functions
00259   * @{
00260   */
00261
00262 /** @addtogroup RTC_Exported_Functions_Group1
00263   *  @brief    Initialization and Configuration functions
00264   *
00265 @verbatim
00266  ===============================================================================
00267               ##### Initialization and de-initialization functions #####
00268  ===============================================================================
00269    [..] This section provides functions allowing to initialize and configure the
00270          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00271          RTC registers Write protection, enter and exit the RTC initialization mode,
00272          RTC registers synchronization check and reference clock detection enable.
00273          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00274              It is split into 2 programmable prescalers to minimize power consumption.
00275              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00276              (++) When both prescalers are used, it is recommended to configure the
00277                  asynchronous prescaler to a high value to minimize power consumption.
00278          (#) All RTC registers are Write protected. Writing to the RTC registers
00279              is enabled by writing a key into the Write Protection register, RTC_WPR.
00280          (#) To configure the RTC Calendar, user application should enter
00281              initialization mode. In this mode, the calendar counter is stopped
00282              and its value can be updated. When the initialization sequence is
00283              complete, the calendar restarts counting after 4 RTCCLK cycles.
00284          (#) To read the calendar through the shadow registers after Calendar
00285              initialization, calendar update or after wakeup from low power modes
00286              the software must first clear the RSF flag. The software must then
00287              wait until it is set again before reading the calendar, which means
00288              that the calendar registers have been correctly copied into the
00289              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00290              implements the above software sequence (RSF clear and RSF check).
00291
00292 @endverbatim
00293   * @{
00294   */
00295
00296 /**
00297   * @brief  Initialize the RTC peripheral
00298   * @param  hrtc RTC handle
00299   * @retval HAL status
00300   */
00301 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00302 {
00303   HAL_StatusTypeDef status = HAL_ERROR;
00304
00305   /* Check the RTC peripheral state */
00306   if (hrtc != NULL)
00307   {
00308     /* Check the parameters */
00309     assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00310     assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00311     assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00312     assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00313     assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00314     assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00315     assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00316     assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
00317
00318 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00319     if (hrtc->State == HAL_RTC_STATE_RESET)
00320     {
00321       /* Allocate lock resource and initialize it */
00322       hrtc->Lock = HAL_UNLOCKED;
00323
00324       hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
00325       hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
00326       hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
00327       hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00328       hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
00329       hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;     /* Legacy weak Tamper2EventCallback     */
00330 #if (RTC_TAMP_NB == 3)
00331       hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;     /* Legacy weak Tamper3EventCallback     */
00332 #endif /* RTC_TAMP_NB */
00333 #ifdef RTC_TAMP_INT_1_SUPPORT
00334       hrtc->InternalTamper1EventCallback =  HAL_RTCEx_InternalTamper1EventCallback;   /*!< Legacy weak InternalTamper1EventCallback */
00335 #endif /* RTC_TAMP_INT_1_SUPPORT */
00336 #ifdef RTC_TAMP_INT_2_SUPPORT
00337       hrtc->InternalTamper2EventCallback =  HAL_RTCEx_InternalTamper2EventCallback;   /*!< Legacy weak InternalTamper2EventCallback */
00338 #endif /* RTC_TAMP_INT_2_SUPPORT */
00339       hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;   /*!< Legacy weak InternalTamper3EventCallback */
00340       hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;   /*!< Legacy weak InternalTamper4EventCallback */
00341       hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;   /*!< Legacy weak InternalTamper5EventCallback */
00342 #ifdef RTC_TAMP_INT_6_SUPPORT
00343       hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;   /*!< Legacy weak InternalTamper6EventCallback */
00344 #endif /* RTC_TAMP_INT_6_SUPPORT */
00345 #ifdef RTC_TAMP_INT_7_SUPPORT
00346       hrtc->InternalTamper7EventCallback  =  HAL_RTCEx_InternalTamper7EventCallback;  /*!< Legacy weak InternalTamper7EventCallback */
00347 #endif /* RTC_TAMP_INT_7_SUPPORT */
00348
00349       if (hrtc->MspInitCallback == NULL)
00350       {
00351         hrtc->MspInitCallback = HAL_RTC_MspInit;
00352       }
00353       /* Init the low level hardware */
00354       hrtc->MspInitCallback(hrtc);
00355
00356       if (hrtc->MspDeInitCallback == NULL)
00357       {
00358         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00359       }
00360     }
00361 #else
00362     if (hrtc->State == HAL_RTC_STATE_RESET)
00363     {
00364       /* Allocate lock resource and initialize it */
00365       hrtc->Lock = HAL_UNLOCKED;
00366
00367       /* Initialize RTC MSP */
00368       HAL_RTC_MspInit(hrtc);
00369     }
00370 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00371
00372     /* Set RTC state */
00373     hrtc->State = HAL_RTC_STATE_BUSY;
00374
00375     /* Check whether the calendar needs to be initialized */
00376     if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
00377     {
00378       /* Disable the write protection for RTC registers */
00379       __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00380
00381       /* Enter Initialization mode */
00382       status = RTC_EnterInitMode(hrtc);
00383
00384       if (status == HAL_OK)
00385       {
00386         /* Clear RTC_CR FMT, OSEL and POL Bits */
00387         CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
00388         /* Set RTC_CR register */
00389         SET_BIT(hrtc->Instance->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
00390
00391         /* Configure the RTC PRER */
00392         WRITE_REG(hrtc->Instance->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
00393
00394         /* Exit Initialization mode */
00395         status = RTC_ExitInitMode(hrtc);
00396       }
00397
00398       if (status == HAL_OK)
00399       {
00400         MODIFY_REG(hrtc->Instance->CR, \
00401                    RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
00402                    hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00403       }
00404
00405       /* Enable the write protection for RTC registers */
00406       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00407     }
00408     else
00409     {
00410       /* The calendar is already initialized */
00411       status = HAL_OK;
00412     }
00413
00414     if (status == HAL_OK)
00415     {
00416       hrtc->State = HAL_RTC_STATE_READY;
00417     }
00418   }
00419
00420   return status;
00421 }
00422
00423 /**
00424   * @brief  DeInitialize the RTC peripheral.
00425   * @note   This function does not reset the RTC Backup Data registers.
00426   * @param  hrtc RTC handle
00427   * @retval HAL status
00428   */
00429 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00430 {
00431   HAL_StatusTypeDef status;
00432
00433   /* Set RTC state */
00434   hrtc->State = HAL_RTC_STATE_BUSY;
00435
00436   /* Disable the write protection for RTC registers */
00437   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00438
00439   status = RTC_EnterInitMode(hrtc);
00440
00441   /* Set Initialization mode */
00442   if (status != HAL_OK)
00443   {
00444     /* Set RTC state */
00445     hrtc->State = HAL_RTC_STATE_ERROR;
00446   }
00447   else
00448   {
00449     /* Reset all RTC CR register bits */
00450     CLEAR_REG(hrtc->Instance->CR);
00451     WRITE_REG(hrtc->Instance->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00452     CLEAR_REG(hrtc->Instance->TR);
00453     WRITE_REG(hrtc->Instance->WUTR, RTC_WUTR_WUT);
00454     WRITE_REG(hrtc->Instance->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU)));
00455     CLEAR_REG(hrtc->Instance->ALRMAR);
00456     CLEAR_REG(hrtc->Instance->ALRMBR);
00457     CLEAR_REG(hrtc->Instance->SHIFTR);
00458     CLEAR_REG(hrtc->Instance->CALR);
00459     CLEAR_REG(hrtc->Instance->ALRMASSR);
00460     CLEAR_REG(hrtc->Instance->ALRMBSSR);
00461     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | RTC_SCR_CALRAF);
00462
00463     /* Exit initialization mode */
00464     CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
00465
00466     status = HAL_RTC_WaitForSynchro(hrtc);
00467
00468     if (status != HAL_OK)
00469     {
00470       hrtc->State = HAL_RTC_STATE_ERROR;
00471     }
00472     else
00473     {
00474       /* Reset TAMP registers */
00475       WRITE_REG(TAMP->CR1, RTC_INT_TAMPER_ALL);
00476       CLEAR_REG(TAMP->CR2);
00477       CLEAR_REG(TAMP->FLTCR);
00478     }
00479   }
00480
00481   /* Enable the write protection for RTC registers */
00482   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00483
00484   if (status == HAL_OK)
00485   {
00486 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00487     if (hrtc->MspDeInitCallback == NULL)
00488     {
00489       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00490     }
00491
00492     /* DeInit the low level hardware: CLOCK, NVIC.*/
00493     hrtc->MspDeInitCallback(hrtc);
00494
00495 #else
00496     /* De-Initialize RTC MSP */
00497     HAL_RTC_MspDeInit(hrtc);
00498 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00499
00500     hrtc->State = HAL_RTC_STATE_RESET;
00501   }
00502
00503   /* Release Lock */
00504   __HAL_UNLOCK(hrtc);
00505
00506   return status;
00507 }
00508
00509 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00510 /**
00511   * @brief  Register a User RTC Callback
00512   *         To be used instead of the weak predefined callback
00513   * @param  hrtc RTC handle
00514   * @param  CallbackID ID of the callback to be registered
00515   *         This parameter can be one of the following values:
00516   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00517   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00518   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00519   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00520   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00521   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00522   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
00523   *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
00524   *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
00525   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00526   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00527   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00528   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00529   *          @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
00530   *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
00531   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
00532   * @param  pCallback pointer to the Callback function
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
00536                                            pRTC_CallbackTypeDef pCallback)
00537 {
00538   HAL_StatusTypeDef status = HAL_OK;
00539
00540   if (pCallback == NULL)
00541   {
00542     return HAL_ERROR;
00543   }
00544
00545   /* Process locked */
00546   __HAL_LOCK(hrtc);
00547
00548   if (HAL_RTC_STATE_READY == hrtc->State)
00549   {
00550     switch (CallbackID)
00551     {
00552       case HAL_RTC_ALARM_A_EVENT_CB_ID :
00553         hrtc->AlarmAEventCallback = pCallback;
00554         break;
00555
00556       case HAL_RTC_ALARM_B_EVENT_CB_ID :
00557         hrtc->AlarmBEventCallback = pCallback;
00558         break;
00559
00560       case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00561         hrtc->TimeStampEventCallback = pCallback;
00562         break;
00563
00564       case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00565         hrtc->WakeUpTimerEventCallback = pCallback;
00566         break;
00567
00568       case HAL_RTC_TAMPER1_EVENT_CB_ID :
00569         hrtc->Tamper1EventCallback = pCallback;
00570         break;
00571
00572       case HAL_RTC_TAMPER2_EVENT_CB_ID :
00573         hrtc->Tamper2EventCallback = pCallback;
00574         break;
00575
00576 #if (RTC_TAMP_NB == 3)
00577       case HAL_RTC_TAMPER3_EVENT_CB_ID :
00578         hrtc->Tamper3EventCallback = pCallback;
00579         break;
00580
00581 #endif /* RTC_TAMP_NB */
00582
00583 #ifdef RTC_TAMP_INT_1_SUPPORT
00584       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
00585         hrtc->InternalTamper1EventCallback = pCallback;
00586         break;
00587 #endif /* RTC_TAMP_INT_1_SUPPORT */
00588
00589 #ifdef RTC_TAMP_INT_2_SUPPORT
00590       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
00591         hrtc->InternalTamper2EventCallback = pCallback;
00592         break;
00593
00594 #endif /* RTC_TAMP_INT_2_SUPPORT */
00595       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00596         hrtc->InternalTamper3EventCallback = pCallback;
00597         break;
00598
00599       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00600         hrtc->InternalTamper4EventCallback = pCallback;
00601         break;
00602
00603       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00604         hrtc->InternalTamper5EventCallback = pCallback;
00605         break;
00606
00607 #ifdef RTC_TAMP_INT_6_SUPPORT
00608       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00609         hrtc->InternalTamper6EventCallback = pCallback;
00610         break;
00611
00612 #endif /* RTC_TAMP_INT_6_SUPPORT */
00613 #ifdef RTC_TAMP_INT_7_SUPPORT
00614       case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
00615         hrtc->InternalTamper7EventCallback = pCallback;
00616         break;
00617
00618 #endif /* RTC_TAMP_INT_7_SUPPORT */
00619       case HAL_RTC_MSPINIT_CB_ID :
00620         hrtc->MspInitCallback = pCallback;
00621         break;
00622
00623       case HAL_RTC_MSPDEINIT_CB_ID :
00624         hrtc->MspDeInitCallback = pCallback;
00625         break;
00626
00627       default :
00628         /* Return error status */
00629         status =  HAL_ERROR;
00630         break;
00631     }
00632   }
00633   else if (HAL_RTC_STATE_RESET == hrtc->State)
00634   {
00635     switch (CallbackID)
00636     {
00637       case HAL_RTC_MSPINIT_CB_ID :
00638         hrtc->MspInitCallback = pCallback;
00639         break;
00640
00641       case HAL_RTC_MSPDEINIT_CB_ID :
00642         hrtc->MspDeInitCallback = pCallback;
00643         break;
00644
00645       default :
00646         /* Return error status */
00647         status =  HAL_ERROR;
00648         break;
00649     }
00650   }
00651   else
00652   {
00653     /* Return error status */
00654     status =  HAL_ERROR;
00655   }
00656
00657   /* Release Lock */
00658   __HAL_UNLOCK(hrtc);
00659
00660   return status;
00661 }
00662
00663 /**
00664   * @brief  Unregister an RTC Callback
00665   *         RTC callback is redirected to the weak predefined callback
00666   * @param  hrtc RTC handle
00667   * @param  CallbackID ID of the callback to be unregistered
00668   *         This parameter can be one of the following values:
00669   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00670   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00671   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00672   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00673   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00674   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00675   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
00676   *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID
00677   *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID
00678   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00679   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00680   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00681   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00682   *          @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID
00683   *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
00684   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
00685   * @retval HAL status
00686   */
00687 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
00688 {
00689   HAL_StatusTypeDef status = HAL_OK;
00690
00691   /* Process locked */
00692   __HAL_LOCK(hrtc);
00693
00694   if (HAL_RTC_STATE_READY == hrtc->State)
00695   {
00696     switch (CallbackID)
00697     {
00698       case HAL_RTC_ALARM_A_EVENT_CB_ID :
00699         hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
00700         break;
00701
00702       case HAL_RTC_ALARM_B_EVENT_CB_ID :
00703         hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
00704         break;
00705
00706       case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00707         hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
00708         break;
00709
00710       case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00711         hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00712         break;
00713
00714       case HAL_RTC_TAMPER1_EVENT_CB_ID :
00715         hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
00716         break;
00717
00718       case HAL_RTC_TAMPER2_EVENT_CB_ID :
00719         hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
00720         break;
00721
00722 #if (RTC_TAMP_NB == 3)
00723       case HAL_RTC_TAMPER3_EVENT_CB_ID :
00724         hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
00725         break;
00726 #endif /* RTC_TAMP_NB */
00727 #ifdef RTC_TAMP_INT_1_SUPPORT
00728       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
00729         hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback;      /* Legacy weak InternalTamper1EventCallback         */
00730         break;
00731 #endif /* RTC_TAMP_INT_1_SUPPORT */
00732
00733 #ifdef RTC_TAMP_INT_2_SUPPORT
00734       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
00735         hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback;      /* Legacy weak InternalTamper2EventCallback         */
00736         break;
00737
00738 #endif /* RTC_TAMP_INT_2_SUPPORT */
00739       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00740         hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback;      /* Legacy weak InternalTamper3EventCallback         */
00741         break;
00742
00743       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00744         hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback;      /* Legacy weak InternalTamper4EventCallback         */
00745         break;
00746
00747       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00748         hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback;      /* Legacy weak InternalTamper5EventCallback         */
00749         break;
00750
00751 #ifdef RTC_TAMP_INT_6_SUPPORT
00752       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00753         hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback;      /* Legacy weak InternalTamper6EventCallback         */
00754         break;
00755
00756 #endif /* RTC_TAMP_INT_6_SUPPORT */
00757 #ifdef RTC_TAMP_INT_7_SUPPORT
00758       case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
00759         hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback;      /* Legacy weak InternalTamper7EventCallback         */
00760         break;
00761
00762 #endif /* RTC_TAMP_INT_7_SUPPORT */
00763       case HAL_RTC_MSPINIT_CB_ID :
00764         hrtc->MspInitCallback = HAL_RTC_MspInit;
00765         break;
00766
00767       case HAL_RTC_MSPDEINIT_CB_ID :
00768         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00769         break;
00770
00771       default :
00772         /* Return error status */
00773         status =  HAL_ERROR;
00774         break;
00775     }
00776   }
00777   else if (HAL_RTC_STATE_RESET == hrtc->State)
00778   {
00779     switch (CallbackID)
00780     {
00781       case HAL_RTC_MSPINIT_CB_ID :
00782         hrtc->MspInitCallback = HAL_RTC_MspInit;
00783         break;
00784
00785       case HAL_RTC_MSPDEINIT_CB_ID :
00786         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00787         break;
00788
00789       default :
00790         /* Return error status */
00791         status =  HAL_ERROR;
00792         break;
00793     }
00794   }
00795   else
00796   {
00797     /* Return error status */
00798     status =  HAL_ERROR;
00799   }
00800
00801   /* Release Lock */
00802   __HAL_UNLOCK(hrtc);
00803
00804   return status;
00805 }
00806 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00807
00808 /**
00809   * @brief  Initialize the RTC MSP.
00810   * @param  hrtc RTC handle
00811   * @retval None
00812   */
00813 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
00814 {
00815   /* Prevent unused argument(s) compilation warning */
00816   UNUSED(hrtc);
00817
00818   /* NOTE : This function should not be modified, when the callback is needed,
00819             the HAL_RTC_MspInit could be implemented in the user file
00820    */
00821 }
00822
00823 /**
00824   * @brief  DeInitialize the RTC MSP.
00825   * @param  hrtc RTC handle
00826   * @retval None
00827   */
00828 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
00829 {
00830   /* Prevent unused argument(s) compilation warning */
00831   UNUSED(hrtc);
00832
00833   /* NOTE : This function should not be modified, when the callback is needed,
00834             the HAL_RTC_MspDeInit could be implemented in the user file
00835    */
00836 }
00837
00838 /**
00839   * @}
00840   */
00841
00842 /** @addtogroup RTC_Exported_Functions_Group2
00843   *  @brief   RTC Time and Date functions
00844   *
00845 @verbatim
00846  ===============================================================================
00847                  ##### RTC Time and Date functions #####
00848  ===============================================================================
00849
00850  [..] This section provides functions allowing to configure Time and Date features
00851
00852 @endverbatim
00853   * @{
00854   */
00855
00856 /**
00857   * @brief  Set RTC current time.
00858   * @param  hrtc RTC handle
00859   * @param  sTime Pointer to Time structure
00860   * @param  Format Specifies the format of the entered parameters.
00861   *          This parameter can be one of the following values:
00862   *            @arg RTC_FORMAT_BIN: Binary data format
00863   *            @arg RTC_FORMAT_BCD: BCD data format
00864   * @retval HAL status
00865   */
00866 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00867 {
00868   uint32_t tmpreg;
00869   HAL_StatusTypeDef status;
00870
00871   /* Check the parameters */
00872   assert_param(IS_RTC_FORMAT(Format));
00873   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00874   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00875
00876   /* Process Locked */
00877   __HAL_LOCK(hrtc);
00878
00879   hrtc->State = HAL_RTC_STATE_BUSY;
00880
00881   /* Disable the write protection for RTC registers */
00882   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00883
00884   /* Enter Initialization mode */
00885   status = RTC_EnterInitMode(hrtc);
00886   if (status == HAL_OK)
00887   {
00888     if (Format == RTC_FORMAT_BIN)
00889     {
00890       if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
00891       {
00892         assert_param(IS_RTC_HOUR12(sTime->Hours));
00893         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00894       }
00895       else
00896       {
00897         sTime->TimeFormat = 0x00U;
00898         assert_param(IS_RTC_HOUR24(sTime->Hours));
00899       }
00900       assert_param(IS_RTC_MINUTES(sTime->Minutes));
00901       assert_param(IS_RTC_SECONDS(sTime->Seconds));
00902
00903       tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
00904                           ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00905                           ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \
00906                           (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
00907     }
00908     else
00909     {
00910       if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
00911       {
00912         assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
00913         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00914       }
00915       else
00916       {
00917         sTime->TimeFormat = 0x00U;
00918         assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00919       }
00920       assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00921       assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00922       tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
00923                 ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00924                 ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \
00925                 ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
00926     }
00927
00928     /* Set the RTC_TR register */
00929     WRITE_REG(hrtc->Instance->TR, (tmpreg & RTC_TR_RESERVED_MASK));
00930
00931     /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
00932     CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
00933
00934     /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
00935     SET_BIT(hrtc->Instance->CR, (sTime->DayLightSaving | sTime->StoreOperation));
00936
00937     /* Exit Initialization mode */
00938     status = RTC_ExitInitMode(hrtc);
00939   }
00940   /* Enable the write protection for RTC registers */
00941   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00942
00943   if (status == HAL_OK)
00944   {
00945      hrtc->State = HAL_RTC_STATE_READY;
00946   }
00947     __HAL_UNLOCK(hrtc);
00948
00949   return status;
00950 }
00951
00952 /**
00953   * @brief  Get RTC current time.
00954   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00955   *        value in second fraction ratio with time unit following generic formula:
00956   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00957   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00958   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00959   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00960   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00961   *        to ensure consistency between the time and date values.
00962   * @param  hrtc RTC handle
00963   * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
00964   *                with input format (BIN or BCD), also SubSeconds field returning the
00965   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00966   *                factor to be used for second fraction ratio computation.
00967   * @param  Format Specifies the format of the entered parameters.
00968   *          This parameter can be one of the following values:
00969   *            @arg RTC_FORMAT_BIN: Binary data format
00970   *            @arg RTC_FORMAT_BCD: BCD data format
00971   * @retval HAL status
00972   */
00973 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00974 {
00975   uint32_t tmpreg;
00976
00977   /* Check the parameters */
00978   assert_param(IS_RTC_FORMAT(Format));
00979
00980   /* Get subseconds structure field from the corresponding register*/
00981   sTime->SubSeconds = READ_REG(hrtc->Instance->SSR);
00982
00983   /* Get SecondFraction structure field from the corresponding register field*/
00984   sTime->SecondFraction = (uint32_t)(READ_REG(hrtc->Instance->PRER) & RTC_PRER_PREDIV_S);
00985
00986   /* Get the TR register */
00987   tmpreg = (uint32_t)(READ_REG(hrtc->Instance->TR) & RTC_TR_RESERVED_MASK);
00988
00989   /* Fill the structure fields with the read parameters */
00990   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
00991   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
00992   sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
00993   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
00994
00995   /* Check the input parameters format */
00996   if (Format == RTC_FORMAT_BIN)
00997   {
00998     /* Convert the time structure parameters to Binary format */
00999     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
01000     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
01001     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
01002   }
01003
01004   return HAL_OK;
01005 }
01006
01007 /**
01008   * @brief  Set RTC current date.
01009   * @param  hrtc RTC handle
01010   * @param  sDate Pointer to date structure
01011   * @param  Format specifies the format of the entered parameters.
01012   *          This parameter can be one of the following values:
01013   *            @arg RTC_FORMAT_BIN: Binary data format
01014   *            @arg RTC_FORMAT_BCD: BCD data format
01015   * @retval HAL status
01016   */
01017 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
01018 {
01019   uint32_t datetmpreg;
01020   HAL_StatusTypeDef status;
01021
01022   /* Check the parameters */
01023   assert_param(IS_RTC_FORMAT(Format));
01024
01025   /* Process Locked */
01026   __HAL_LOCK(hrtc);
01027
01028   hrtc->State = HAL_RTC_STATE_BUSY;
01029
01030   if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
01031   {
01032     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
01033   }
01034
01035   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
01036
01037   if (Format == RTC_FORMAT_BIN)
01038   {
01039     assert_param(IS_RTC_YEAR(sDate->Year));
01040     assert_param(IS_RTC_MONTH(sDate->Month));
01041     assert_param(IS_RTC_DATE(sDate->Date));
01042
01043     datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
01044                   ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
01045                   ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \
01046                   ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
01047   }
01048   else
01049   {
01050     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
01051     assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
01052     assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
01053
01054     datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
01055                   (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
01056                   (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \
01057                   (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
01058   }
01059
01060   /* Disable the write protection for RTC registers */
01061   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01062
01063   /* Enter Initialization mode */
01064   status = RTC_EnterInitMode(hrtc);
01065   if (status == HAL_OK)
01066   {
01067     /* Set the RTC_DR register */
01068     WRITE_REG(hrtc->Instance->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK));
01069
01070     /* Exit Initialization mode */
01071     status = RTC_ExitInitMode(hrtc);
01072   }
01073
01074   /* Enable the write protection for RTC registers */
01075   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01076
01077   if (status == HAL_OK)
01078   {
01079
01080     hrtc->State = HAL_RTC_STATE_READY ;
01081   }
01082   /* Process Unlocked */
01083   __HAL_UNLOCK(hrtc);
01084
01085   return status;
01086 }
01087
01088 /**
01089   * @brief  Get RTC current date.
01090   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
01091   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
01092   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
01093   * @param  hrtc RTC handle
01094   * @param  sDate Pointer to Date structure
01095   * @param  Format Specifies the format of the entered parameters.
01096   *          This parameter can be one of the following values:
01097   *            @arg RTC_FORMAT_BIN:  Binary data format
01098   *            @arg RTC_FORMAT_BCD:  BCD data format
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
01102 {
01103   uint32_t datetmpreg;
01104
01105   /* Check the parameters */
01106   assert_param(IS_RTC_FORMAT(Format));
01107
01108   /* Get the DR register */
01109   datetmpreg = (uint32_t)(READ_REG(hrtc->Instance->DR) & RTC_DR_RESERVED_MASK);
01110
01111   /* Fill the structure fields with the read parameters */
01112   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
01113   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
01114   sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
01115   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
01116
01117   /* Check the input parameters format */
01118   if (Format == RTC_FORMAT_BIN)
01119   {
01120     /* Convert the date structure parameters to Binary format */
01121     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
01122     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
01123     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
01124   }
01125   return HAL_OK;
01126 }
01127
01128 /**
01129   * @}
01130   */
01131
01132 /** @addtogroup RTC_Exported_Functions_Group3
01133   *  @brief   RTC Alarm functions
01134   *
01135 @verbatim
01136  ===============================================================================
01137                  ##### RTC Alarm functions #####
01138  ===============================================================================
01139
01140  [..] This section provides functions allowing to configure Alarm feature
01141
01142 @endverbatim
01143   * @{
01144   */
01145 /**
01146   * @brief  Set the specified RTC Alarm.
01147   * @param  hrtc RTC handle
01148   * @param  sAlarm Pointer to Alarm structure
01149   * @param  Format Specifies the format of the entered parameters.
01150   *          This parameter can be one of the following values:
01151   *             @arg RTC_FORMAT_BIN: Binary data format
01152   *             @arg RTC_FORMAT_BCD: BCD data format
01153   * @retval HAL status
01154   */
01155 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01156 {
01157   uint32_t tickstart;
01158   uint32_t tmpreg;
01159   uint32_t subsecondtmpreg;
01160
01161   /* Check the parameters */
01162   assert_param(IS_RTC_FORMAT(Format));
01163   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01164   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01165   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01166   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01167   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01168
01169   /* Process Locked */
01170   __HAL_LOCK(hrtc);
01171
01172   hrtc->State = HAL_RTC_STATE_BUSY;
01173
01174   if (Format == RTC_FORMAT_BIN)
01175   {
01176     if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
01177     {
01178       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01179       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01180     }
01181     else
01182     {
01183       sAlarm->AlarmTime.TimeFormat = 0x00U;
01184       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01185     }
01186     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01187     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01188
01189 #ifdef  USE_FULL_ASSERT
01190     if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01191     {
01192       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01193     }
01194     else
01195     {
01196       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01197     }
01198 #endif /* USE_FULL_ASSERT*/
01199     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01200               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01201               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01202               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01203               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01204               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01205               ((uint32_t)sAlarm->AlarmMask));
01206   }
01207   else /* Format BCD */
01208   {
01209     if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
01210     {
01211       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01212       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01213     }
01214     else
01215     {
01216       sAlarm->AlarmTime.TimeFormat = 0x00U;
01217       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01218     }
01219
01220     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01221     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01222
01223 #ifdef  USE_FULL_ASSERT
01224     if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01225     {
01226       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01227     }
01228     else
01229     {
01230       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01231     }
01232
01233 #endif /* USE_FULL_ASSERT */
01234     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01235               ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01236               ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01237               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01238               ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01239               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01240               ((uint32_t)sAlarm->AlarmMask));
01241   }
01242
01243   /* Configure the Alarm A or Alarm B Sub Second registers */
01244   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01245
01246   /* Disable the write protection for RTC registers */
01247   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01248
01249   /* Configure the Alarm register */
01250   if (sAlarm->Alarm == RTC_ALARM_A)
01251   {
01252     /* Disable the Alarm A interrupt */
01253     /* In case of interrupt mode is used, the interrupt source must disabled */
01254     CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
01255
01256     /* Clear flag alarm A */
01257     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRAF);
01258
01259     tickstart = HAL_GetTick();
01260     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01261     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRAWF) == 0U)
01262     {
01263       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01264       {
01265         /* Enable the write protection for RTC registers */
01266         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01267
01268         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01269
01270         /* Process Unlocked */
01271         __HAL_UNLOCK(hrtc);
01272
01273         return HAL_TIMEOUT;
01274       }
01275     }
01276
01277     WRITE_REG(hrtc->Instance->ALRMAR, tmpreg);
01278     /* Configure the Alarm A Sub Second register */
01279     WRITE_REG(hrtc->Instance->ALRMASSR, subsecondtmpreg);
01280     /* Configure the Alarm state: Enable Alarm */
01281     SET_BIT(hrtc->Instance->CR, RTC_CR_ALRAE);
01282   }
01283   else
01284   {
01285     /* Disable the Alarm B interrupt */
01286     /* In case of interrupt mode is used, the interrupt source must disabled */
01287     CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
01288
01289     /* Clear flag alarm B */
01290     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRBF);
01291
01292     tickstart = HAL_GetTick();
01293     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01294     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRBWF) == 0U)
01295     {
01296       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01297       {
01298         /* Enable the write protection for RTC registers */
01299         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01300
01301         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01302
01303         /* Process Unlocked */
01304         __HAL_UNLOCK(hrtc);
01305
01306         return HAL_TIMEOUT;
01307       }
01308     }
01309
01310     WRITE_REG(hrtc->Instance->ALRMBR, tmpreg);
01311     /* Configure the Alarm B Sub Second register */
01312     WRITE_REG(hrtc->Instance->ALRMBSSR, subsecondtmpreg);
01313     /* Configure the Alarm state: Enable Alarm */
01314     SET_BIT(hrtc->Instance->CR, RTC_CR_ALRBE);
01315   }
01316
01317   /* Enable the write protection for RTC registers */
01318   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01319
01320   /* Change RTC state */
01321   hrtc->State = HAL_RTC_STATE_READY;
01322
01323   /* Process Unlocked */
01324   __HAL_UNLOCK(hrtc);
01325
01326   return HAL_OK;
01327 }
01328
01329 /**
01330   * @brief  Set the specified RTC Alarm with Interrupt.
01331   * @note   The Alarm register can only be written when the corresponding Alarm
01332   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
01333   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
01334   * @param  hrtc RTC handle
01335   * @param  sAlarm Pointer to Alarm structure
01336   * @param  Format Specifies the format of the entered parameters.
01337   *          This parameter can be one of the following values:
01338   *             @arg RTC_FORMAT_BIN: Binary data format
01339   *             @arg RTC_FORMAT_BCD: BCD data format
01340   * @retval HAL status
01341   */
01342 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01343 {
01344   uint32_t tickstart;
01345   uint32_t tmpreg;
01346   uint32_t subsecondtmpreg;
01347
01348   /* Check the parameters */
01349   assert_param(IS_RTC_FORMAT(Format));
01350   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01351   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01352   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01353   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01354   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01355
01356   /* Process Locked */
01357   __HAL_LOCK(hrtc);
01358
01359   hrtc->State = HAL_RTC_STATE_BUSY;
01360
01361   if (Format == RTC_FORMAT_BIN)
01362   {
01363     if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
01364     {
01365       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01366       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01367     }
01368     else
01369     {
01370       sAlarm->AlarmTime.TimeFormat = 0x00U;
01371       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01372     }
01373     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01374     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01375
01376 #ifdef  USE_FULL_ASSERT
01377     if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01378     {
01379       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01380     }
01381     else
01382     {
01383       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01384     }
01385 #endif /* USE_FULL_ASSERT */
01386     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01387               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01388               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01389               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01390               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01391               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01392               ((uint32_t)sAlarm->AlarmMask));
01393   }
01394   else /* Format BCD */
01395   {
01396     if (READ_BIT(hrtc->Instance->CR, RTC_CR_FMT) != 0U)
01397     {
01398       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01399       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01400     }
01401     else
01402     {
01403       sAlarm->AlarmTime.TimeFormat = 0x00U;
01404       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01405     }
01406
01407     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01408     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01409
01410 #ifdef  USE_FULL_ASSERT
01411     if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01412     {
01413       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01414     }
01415     else
01416     {
01417       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01418     }
01419
01420 #endif /* USE_FULL_ASSERT */
01421     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01422               ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01423               ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01424               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01425               ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01426               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01427               ((uint32_t)sAlarm->AlarmMask));
01428   }
01429
01430   /* Configure the Alarm A or Alarm B Sub Second registers */
01431   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01432
01433   /* Disable the write protection for RTC registers */
01434   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01435
01436   /* Configure the Alarm register */
01437   if (sAlarm->Alarm == RTC_ALARM_A)
01438   {
01439     /* Disable the Alarm A interrupt */
01440     CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
01441
01442     /* Clear flag alarm A */
01443     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRAF);
01444     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01445
01446     tickstart = HAL_GetTick();
01447     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01448     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRAWF) == 0U)
01449     {
01450       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01451       {
01452         /* Enable the write protection for RTC registers */
01453         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01454
01455         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01456
01457         /* Process Unlocked */
01458         __HAL_UNLOCK(hrtc);
01459
01460         return HAL_TIMEOUT;
01461       }
01462     }
01463
01464     WRITE_REG(hrtc->Instance->ALRMAR, tmpreg);
01465     /* Configure the Alarm A Sub Second register */
01466     WRITE_REG(hrtc->Instance->ALRMASSR, subsecondtmpreg);
01467     /* Configure the Alarm interrupt : Enable Alarm */
01468     SET_BIT(hrtc->Instance->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
01469   }
01470   else
01471   {
01472     /* Disable the Alarm B interrupt */
01473     CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
01474
01475     /* Clear flag alarm B */
01476     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRBF);
01477     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01478
01479     tickstart = HAL_GetTick();
01480     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01481     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRBWF) == 0U)
01482     {
01483       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01484       {
01485         /* Enable the write protection for RTC registers */
01486         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01487
01488         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01489
01490         /* Process Unlocked */
01491         __HAL_UNLOCK(hrtc);
01492
01493         return HAL_TIMEOUT;
01494       }
01495     }
01496
01497     WRITE_REG(hrtc->Instance->ALRMBR, tmpreg);
01498     /* Configure the Alarm B Sub Second register */
01499     WRITE_REG(hrtc->Instance->ALRMBSSR, subsecondtmpreg);
01500     /* Configure the Alarm B interrupt : Enable Alarm */
01501     SET_BIT(hrtc->Instance->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
01502   }
01503
01504   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01505   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01506   __HAL_RTC_ALARM_EXTI_RISING_IT();
01507
01508   /* Enable the write protection for RTC registers */
01509   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01510
01511   /* Change RTC state */
01512   hrtc->State = HAL_RTC_STATE_READY;
01513
01514   /* Process Unlocked */
01515   __HAL_UNLOCK(hrtc);
01516
01517   return HAL_OK;
01518 }
01519
01520 /**
01521   * @brief  Deactivate the specified RTC Alarm.
01522   * @param  hrtc RTC handle
01523   * @param  Alarm Specifies the Alarm.
01524   *          This parameter can be one of the following values:
01525   *            @arg RTC_ALARM_A:  AlarmA
01526   *            @arg RTC_ALARM_B:  AlarmB
01527   * @retval HAL status
01528   */
01529 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01530 {
01531   uint32_t tickstart;
01532
01533   /* Check the parameters */
01534   assert_param(IS_RTC_ALARM(Alarm));
01535
01536   /* Process Locked */
01537   __HAL_LOCK(hrtc);
01538
01539   hrtc->State = HAL_RTC_STATE_BUSY;
01540
01541   /* Disable the write protection for RTC registers */
01542   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01543
01544   if (Alarm == RTC_ALARM_A)
01545   {
01546     /* AlarmA */
01547     /* In case of interrupt mode is used, the interrupt source must disabled */
01548     CLEAR_BIT(hrtc->Instance->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
01549     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01550
01551     tickstart = HAL_GetTick();
01552
01553     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01554     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRAWF) == 0U)
01555     {
01556       if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
01557       {
01558         /* Enable the write protection for RTC registers */
01559         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01560
01561         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01562
01563         /* Process Unlocked */
01564         __HAL_UNLOCK(hrtc);
01565
01566         return HAL_TIMEOUT;
01567       }
01568     }
01569   }
01570   else
01571   {
01572     /* AlarmB */
01573     /* In case of interrupt mode is used, the interrupt source must disabled */
01574     CLEAR_BIT(hrtc->Instance->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
01575     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01576
01577     tickstart = HAL_GetTick();
01578
01579     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01580     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_ALRBWF) == 0U)
01581     {
01582       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01583       {
01584         /* Enable the write protection for RTC registers */
01585         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01586
01587         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01588
01589         /* Process Unlocked */
01590         __HAL_UNLOCK(hrtc);
01591
01592         return HAL_TIMEOUT;
01593       }
01594     }
01595   }
01596   /* Enable the write protection for RTC registers */
01597   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01598
01599   hrtc->State = HAL_RTC_STATE_READY;
01600
01601   /* Process Unlocked */
01602   __HAL_UNLOCK(hrtc);
01603
01604   return HAL_OK;
01605 }
01606
01607 /**
01608   * @brief  Get the RTC Alarm value and masks.
01609   * @param  hrtc RTC handle
01610   * @param  sAlarm Pointer to Date structure
01611   * @param  Alarm Specifies the Alarm.
01612   *          This parameter can be one of the following values:
01613   *             @arg RTC_ALARM_A: AlarmA
01614   *             @arg RTC_ALARM_B: AlarmB
01615   * @param  Format Specifies the format of the entered parameters.
01616   *          This parameter can be one of the following values:
01617   *             @arg RTC_FORMAT_BIN: Binary data format
01618   *             @arg RTC_FORMAT_BCD: BCD data format
01619   * @retval HAL status
01620   */
01621 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01622 {
01623   uint32_t tmpreg, subsecondtmpreg;
01624
01625   /* Check the parameters */
01626   assert_param(IS_RTC_FORMAT(Format));
01627   assert_param(IS_RTC_ALARM(Alarm));
01628
01629   if (Alarm == RTC_ALARM_A)
01630   {
01631     /* AlarmA */
01632     sAlarm->Alarm = RTC_ALARM_A;
01633
01634     tmpreg = READ_REG(hrtc->Instance->ALRMAR);
01635     subsecondtmpreg = (uint32_t)(READ_REG(hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
01636
01637     /* Fill the structure with the read parameters */
01638     sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
01639     sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
01640     sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos);
01641     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos);
01642     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01643     sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
01644     sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01645     sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01646   }
01647   else
01648   {
01649     sAlarm->Alarm = RTC_ALARM_B;
01650
01651     tmpreg = READ_REG(hrtc->Instance->ALRMBR);
01652     subsecondtmpreg = (uint32_t)(READ_REG(hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01653
01654     /* Fill the structure with the read parameters */
01655     sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos);
01656     sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos);
01657     sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos);
01658     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos);
01659     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01660     sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos);
01661     sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
01662     sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01663   }
01664
01665   if (Format == RTC_FORMAT_BIN)
01666   {
01667     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01668     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01669     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01670     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01671   }
01672
01673   return HAL_OK;
01674 }
01675
01676 /**
01677   * @brief  Handle Alarm interrupt request.
01678   * @param  hrtc RTC handle
01679   * @retval None
01680   */
01681 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
01682 {
01683   /* Get interrupt status */
01684   uint32_t tmp = READ_REG(hrtc->Instance->MISR);
01685
01686   if ((tmp & RTC_MISR_ALRAMF) != 0U)
01687   {
01688     /* Clear the AlarmA interrupt pending bit */
01689     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRAF);
01690     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01691
01692 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01693     /* Call Compare Match registered Callback */
01694     hrtc->AlarmAEventCallback(hrtc);
01695 #else
01696     HAL_RTC_AlarmAEventCallback(hrtc);
01697 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01698   }
01699
01700   if ((tmp & RTC_MISR_ALRBMF) != 0U)
01701   {
01702     /* Clear the AlarmB interrupt pending bit */
01703     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRBF);
01704     __HAL_RTC_ALARM_EXTI_CLEAR_IT();
01705
01706 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01707     /* Call Compare Match registered Callback */
01708     hrtc->AlarmBEventCallback(hrtc);
01709 #else
01710     HAL_RTCEx_AlarmBEventCallback(hrtc);
01711 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01712   }
01713
01714   /* Change RTC state */
01715   hrtc->State = HAL_RTC_STATE_READY;
01716 }
01717
01718 /**
01719   * @brief  Alarm A callback.
01720   * @param  hrtc RTC handle
01721   * @retval None
01722   */
01723 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01724 {
01725   /* Prevent unused argument(s) compilation warning */
01726   UNUSED(hrtc);
01727
01728   /* NOTE : This function should not be modified, when the callback is needed,
01729             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01730    */
01731 }
01732
01733 /**
01734   * @brief  Handle AlarmA Polling request.
01735   * @param  hrtc RTC handle
01736   * @param  Timeout Timeout duration
01737   * @retval HAL status
01738   */
01739 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01740 {
01741
01742   uint32_t tickstart = HAL_GetTick();
01743
01744   while (READ_BIT(hrtc->Instance->SR, RTC_SR_ALRAF) == 0U)
01745   {
01746     if (Timeout != HAL_MAX_DELAY)
01747     {
01748       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01749       {
01750         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01751
01752         /* Process Unlocked */
01753         __HAL_UNLOCK(hrtc);
01754
01755         return HAL_TIMEOUT;
01756       }
01757     }
01758   }
01759
01760   /* Clear the Alarm interrupt pending bit */
01761   WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRAF);
01762
01763   /* Change RTC state */
01764   hrtc->State = HAL_RTC_STATE_READY;
01765
01766   return HAL_OK;
01767 }
01768
01769 /**
01770   * @}
01771   */
01772
01773 /** @addtogroup RTC_Exported_Functions_Group4
01774   *  @brief   Peripheral Control functions
01775   *
01776 @verbatim
01777  ===============================================================================
01778                      ##### Peripheral Control functions #####
01779  ===============================================================================
01780     [..]
01781     This subsection provides functions allowing to
01782       (+) Wait for RTC Time and Date Synchronization
01783
01784 @endverbatim
01785   * @{
01786   */
01787
01788 /**
01789   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01790   *         synchronized with RTC APB clock.
01791   * @note   The RTC Resynchronization mode is write protected, use the
01792   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01793   * @note   To read the calendar through the shadow registers after Calendar
01794   *         initialization, calendar update or after wakeup from low power modes
01795   *         the software must first clear the RSF flag.
01796   *         The software must then wait until it is set again before reading
01797   *         the calendar, which means that the calendar registers have been
01798   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01799   * @param  hrtc RTC handle
01800   * @retval HAL status
01801   */
01802 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
01803 {
01804   uint32_t tickstart;
01805
01806   /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
01807   hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK));
01808
01809   tickstart = HAL_GetTick();
01810
01811   /* Wait the registers to be synchronised */
01812   while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_RSF) == 0U)
01813   {
01814     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
01815     {
01816       return HAL_TIMEOUT;
01817     }
01818   }
01819
01820   return HAL_OK;
01821 }
01822
01823 /**
01824   * @}
01825   */
01826
01827 /** @addtogroup RTC_Exported_Functions_Group5
01828   *  @brief   Peripheral State functions
01829   *
01830 @verbatim
01831  ===============================================================================
01832                      ##### Peripheral State functions #####
01833  ===============================================================================
01834     [..]
01835     This subsection provides functions allowing to
01836       (+) Get RTC state
01837
01838 @endverbatim
01839   * @{
01840   */
01841 /**
01842   * @brief  Return the RTC handle state.
01843   * @param  hrtc RTC handle
01844   * @retval HAL state
01845   */
01846 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
01847 {
01848   /* Return RTC handle state */
01849   return hrtc->State;
01850 }
01851
01852 /**
01853   * @}
01854   */
01855 /**
01856   * @}
01857   */
01858
01859 /** @addtogroup RTC_Private_Functions
01860   * @{
01861   */
01862 /**
01863   * @brief  Enter the RTC Initialization mode.
01864   * @note   The RTC Initialization mode is write protected, use the
01865   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01866   * @param  hrtc RTC handle
01867   * @retval HAL status
01868   */
01869 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
01870 {
01871   uint32_t tickstart;
01872   HAL_StatusTypeDef status = HAL_OK;
01873
01874   /* Check if the Initialization mode is set */
01875   if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
01876   {
01877     /* Set the Initialization mode */
01878     SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
01879
01880     tickstart = HAL_GetTick();
01881     /* Wait till RTC is in INIT state and if Time out is reached exit */
01882     while ((READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
01883     {
01884       if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
01885       {
01886         status = HAL_TIMEOUT;
01887         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01888       }
01889     }
01890   }
01891
01892   return status;
01893 }
01894
01895
01896 /**
01897   * @brief  Exit the RTC Initialization mode.
01898   * @param  hrtc RTC handle
01899   * @retval HAL status
01900   */
01901 HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
01902 {
01903   HAL_StatusTypeDef status = HAL_OK;
01904
01905   /* Exit Initialization mode */
01906   CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
01907
01908   /* If CR_BYPSHAD bit = 0, wait for synchro */
01909   if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
01910   {
01911     if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01912     {
01913       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01914       status = HAL_TIMEOUT;
01915     }
01916   }
01917   else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */
01918   {
01919     /* Clear BYPSHAD bit */
01920     CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD);
01921     if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01922     {
01923       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01924       status = HAL_TIMEOUT;
01925     }
01926     /* Restore BYPSHAD bit */
01927     SET_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD);
01928   }
01929
01930   return status;
01931 }
01932
01933
01934
01935 /**
01936   * @brief  Convert a 2 digit decimal to BCD format.
01937   * @param  Value Byte to be converted
01938   * @retval Converted byte
01939   */
01940 uint8_t RTC_ByteToBcd2(uint8_t Value)
01941 {
01942   uint32_t bcdhigh = 0U;
01943   uint8_t tmp_Value = Value;
01944
01945   while (tmp_Value >= 10U)
01946   {
01947     bcdhigh++;
01948     tmp_Value -= 10U;
01949   }
01950
01951   return ((uint8_t)(bcdhigh << 4U) | tmp_Value);
01952 }
01953
01954 /**
01955   * @brief  Convert from 2 digit BCD to Binary.
01956   * @param  Value BCD value to be converted
01957   * @retval Converted word
01958   */
01959 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01960 {
01961   uint32_t tmp;
01962   tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U;
01963   return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
01964 }
01965
01966 /**
01967   * @brief  Daylight Saving Time, Add one hour to the calendar in one single operation
01968   *         without going through the initialization procedure.
01969   * @param  hrtc RTC handle
01970   * @retval None
01971   */
01972 void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
01973 {
01974   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01975   SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
01976   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01977 }
01978
01979 /**
01980   * @brief  Daylight Saving Time, Subtract one hour from the calendar in one
01981   *         single operation without going through the initialization procedure.
01982   * @param  hrtc RTC handle
01983   * @retval None
01984   */
01985 void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
01986 {
01987   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01988   SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
01989   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01990 }
01991
01992 /**
01993   * @brief  Daylight Saving Time, Set the store operation bit.
01994   * @note   It can be used by the software in order to memorize the DST status.
01995   * @param  hrtc RTC handle
01996   * @retval None
01997   */
01998 void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
01999 {
02000   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02001   SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
02002   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02003 }
02004
02005 /**
02006   * @brief  Daylight Saving Time, Clear the store operation bit.
02007   * @param  hrtc RTC handle
02008   * @retval None
02009   */
02010 void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
02011 {
02012   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
02013   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
02014   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
02015 }
02016
02017 /**
02018   * @brief  Daylight Saving Time, Read the store operation bit.
02019   * @param  hrtc RTC handle
02020   * @retval operation see RTC_StoreOperation_Definitions
02021   */
02022 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
02023 {
02024   return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
02025 }
02026
02027 /**
02028   * @}
02029   */
02030
02031 #endif /* HAL_RTC_MODULE_ENABLED */
02032 /**
02033   * @}
02034   */
02035
02036 /**
02037   * @}
02038   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_rtc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_RTC_H
00021 #define STM32G4xx_HAL_RTC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup RTC RTC
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup RTC_Exported_Types RTC Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  HAL State structures definition
00045   */
00046 typedef enum
00047 {
00048   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00049   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00050   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00051   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00052   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00053
00054 } HAL_RTCStateTypeDef;
00055
00056 /**
00057   * @brief  RTC Configuration Structure definition
00058   */
00059 typedef struct
00060 {
00061   uint32_t HourFormat;        /*!< Specifies the RTC Hour Format.
00062                                  This parameter can be a value of @ref RTC_Hour_Formats */
00063
00064   uint32_t AsynchPrediv;      /*!< Specifies the RTC Asynchronous Predivider value.
00065                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00066
00067   uint32_t SynchPrediv;       /*!< Specifies the RTC Synchronous Predivider value.
00068                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00069
00070   uint32_t OutPut;            /*!< Specifies which signal will be routed to the RTC output.
00071                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00072
00073   uint32_t OutPutRemap;       /*!< Specifies the remap for RTC output.
00074                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00075
00076   uint32_t OutPutPolarity;    /*!< Specifies the polarity of the output signal.
00077                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00078
00079   uint32_t OutPutType;        /*!< Specifies the RTC Output Pin mode.
00080                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00081
00082   uint32_t OutPutPullUp;      /*!< Specifies the RTC Output Pull-Up mode.
00083                                  This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
00084 } RTC_InitTypeDef;
00085
00086 /**
00087   * @brief  RTC Time structure definition
00088   */
00089 typedef struct
00090 {
00091   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00092                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00093                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00094
00095   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00096                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00097
00098   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00099                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00100
00101   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00102                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00103
00104   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00105                                  This parameter corresponds to a time unit range between [0-1] Second
00106                                  with [1 Sec / SecondFraction +1] granularity */
00107
00108   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00109                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00110                                  This parameter corresponds to a time unit range between [0-1] Second
00111                                  with [1 Sec / SecondFraction +1] granularity.
00112                                  This field will be used only by HAL_RTC_GetTime function */
00113
00114   uint32_t DayLightSaving;  /*!< This interface is deprecated. To manage Daylight Saving Time,
00115                                  please use HAL_RTC_DST_xxx functions */
00116
00117   uint32_t StoreOperation;  /*!< This interface is deprecated. To manage Daylight Saving Time,
00118                                  please use HAL_RTC_DST_xxx functions */
00119 } RTC_TimeTypeDef;
00120
00121 /**
00122   * @brief  RTC Date structure definition
00123   */
00124 typedef struct
00125 {
00126   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00127                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00128
00129   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00130                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00131
00132   uint8_t Date;     /*!< Specifies the RTC Date.
00133                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00134
00135   uint8_t Year;     /*!< Specifies the RTC Date Year.
00136                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00137 } RTC_DateTypeDef;
00138
00139 /**
00140   * @brief  RTC Alarm structure definition
00141   */
00142 typedef struct
00143 {
00144   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00145
00146   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00147                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00148
00149   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00150                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00151
00152   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00153                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00154
00155   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00156                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00157                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00158
00159   uint32_t Alarm;                /*!< Specifies the alarm .
00160                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00161 } RTC_AlarmTypeDef;
00162
00163 /**
00164   * @brief  RTC Handle Structure definition
00165   */
00166 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00167 typedef struct __RTC_HandleTypeDef
00168 #else
00169 typedef struct
00170 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00171 {
00172   RTC_TypeDef               *Instance;  /*!< Legacy register base address. Not used anymore,
00173                                              the driver directly uses cmsis base address */
00174
00175   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00176
00177   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00178
00179   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00180
00181 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00182   void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);                   /*!< RTC Alarm A Event callback           */
00183   void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);                   /*!< RTC Alarm B Event callback           */
00184   void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC TimeStamp Event callback         */
00185   void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC WakeUpTimer Event callback       */
00186
00187   void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);                  /*!< RTC Tamper 1 Event callback          */
00188   void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);                  /*!< RTC Tamper 2 Event callback          */
00189 #if (RTC_TAMP_NB == 3)
00190   void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);                  /*!< RTC Tamper 3 Event callback          */
00191 #endif /* RTC_TAMP_NB */
00192   void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 1 Event callback */
00193 #ifdef RTC_TAMP_INT_2_SUPPORT
00194   void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 2 Event callback */
00195 #endif /* RTC_TAMP_INT_2_SUPPORT */
00196   void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 3 Event callback */
00197   void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 4 Event callback */
00198   void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 5 Event callback */
00199 #ifdef RTC_TAMP_INT_6_SUPPORT
00200   void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 6 Event callback */
00201 #endif /* RTC_TAMP_INT_6_SUPPORT */
00202 #ifdef RTC_TAMP_INT_7_SUPPORT
00203   void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Internal Tamper 7 Event callback */
00204 #endif /* RTC_TAMP_INT_7_SUPPORT */
00205
00206   void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                       /*!< RTC Msp Init callback                */
00207   void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);                     /*!< RTC Msp DeInit callback              */
00208
00209 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00210
00211 } RTC_HandleTypeDef;
00212
00213 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00214 /**
00215   * @brief  HAL LPTIM Callback ID enumeration definition
00216   */
00217 typedef enum
00218 {
00219   HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00U,    /*!< RTC Alarm A Event Callback ID      */
00220   HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01U,    /*!< RTC Alarm B Event Callback ID      */
00221   HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02U,    /*!< RTC TimeStamp Event Callback ID    */
00222   HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03U,    /*!< RTC WakeUp Timer Event Callback ID */
00223   HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04U,    /*!< RTC Tamper 1 Callback ID           */
00224   HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05U,    /*!< RTC Tamper 2 Callback ID           */
00225   HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06U,    /*!< RTC Tamper 3 Callback ID           */
00226   HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 0x07U,    /*!< RTC Internal Tamper 1 Callback ID  */
00227   HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 0x08U,    /*!< RTC Internal Tamper 2 Callback ID  */
00228   HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 0x09U,    /*!< RTC Internal Tamper 3 Callback ID  */
00229   HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 0x0AU,    /*!< RTC Internal Tamper 4 Callback ID  */
00230   HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 0x0BU,    /*!< RTC Internal Tamper 5 Callback ID  */
00231   HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 0x0CU,    /*!< RTC Internal Tamper 6 Callback ID  */
00232   HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID  = 0x0DU,    /*!< RTC Internal Tamper 7 Callback ID  */
00233   HAL_RTC_MSPINIT_CB_ID                 = 0x0EU,    /*!< RTC Msp Init callback ID           */
00234   HAL_RTC_MSPDEINIT_CB_ID               = 0x0FU     /*!< RTC Msp DeInit callback ID         */
00235 } HAL_RTC_CallbackIDTypeDef;
00236
00237 /**
00238   * @brief  HAL RTC Callback pointer definition
00239   */
00240 typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
00241 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Exported constants --------------------------------------------------------*/
00248 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00249   * @{
00250   */
00251
00252 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00253   * @{
00254   */
00255 #define RTC_HOURFORMAT_24                   0x00000000U
00256 #define RTC_HOURFORMAT_12                   RTC_CR_FMT
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
00262   * @{
00263   */
00264 #define RTC_OUTPUT_DISABLE                  0x00000000U
00265 #define RTC_OUTPUT_ALARMA                   RTC_CR_OSEL_0
00266 #define RTC_OUTPUT_ALARMB                   RTC_CR_OSEL_1
00267 #define RTC_OUTPUT_WAKEUP                   RTC_CR_OSEL
00268 #define RTC_OUTPUT_TAMPER                   RTC_CR_TAMPOE
00269 /**
00270   * @}
00271   */
00272
00273
00274 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00275   * @{
00276   */
00277 #define RTC_OUTPUT_POLARITY_HIGH            0x00000000U
00278 #define RTC_OUTPUT_POLARITY_LOW             RTC_CR_POL
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00284   * @{
00285   */
00286 #define RTC_OUTPUT_TYPE_PUSHPULL            0x00000000U
00287 #define RTC_OUTPUT_TYPE_OPENDRAIN           RTC_CR_TAMPALRM_TYPE
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
00293   * @{
00294   */
00295 #define RTC_OUTPUT_PULLUP_NONE              0x00000000U
00296 #define RTC_OUTPUT_PULLUP_ON                RTC_CR_TAMPALRM_PU
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00302   * @{
00303   */
00304 #define RTC_OUTPUT_REMAP_NONE               0x00000000U
00305 #define RTC_OUTPUT_REMAP_POS1               RTC_CR_OUT2EN
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00311   * @{
00312   */
00313 #define RTC_HOURFORMAT12_AM                 0x0U
00314 #define RTC_HOURFORMAT12_PM                 0x1U
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
00320   * @{
00321   */
00322 #define RTC_DAYLIGHTSAVING_SUB1H            RTC_CR_SUB1H
00323 #define RTC_DAYLIGHTSAVING_ADD1H            RTC_CR_ADD1H
00324 #define RTC_DAYLIGHTSAVING_NONE             0x00000000U
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
00330   * @{
00331   */
00332 #define RTC_STOREOPERATION_RESET            0x00000000U
00333 #define RTC_STOREOPERATION_SET              RTC_CR_BKP
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00339   * @{
00340   */
00341 #define RTC_FORMAT_BIN                      0x00000000U
00342 #define RTC_FORMAT_BCD                      0x00000001U
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00348   * @{
00349   */
00350
00351 /* Coded in BCD format */
00352 #define RTC_MONTH_JANUARY                   ((uint8_t)0x01U)
00353 #define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02U)
00354 #define RTC_MONTH_MARCH                     ((uint8_t)0x03U)
00355 #define RTC_MONTH_APRIL                     ((uint8_t)0x04U)
00356 #define RTC_MONTH_MAY                       ((uint8_t)0x05U)
00357 #define RTC_MONTH_JUNE                      ((uint8_t)0x06U)
00358 #define RTC_MONTH_JULY                      ((uint8_t)0x07U)
00359 #define RTC_MONTH_AUGUST                    ((uint8_t)0x08U)
00360 #define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09U)
00361 #define RTC_MONTH_OCTOBER                   ((uint8_t)0x10U)
00362 #define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11U)
00363 #define RTC_MONTH_DECEMBER                  ((uint8_t)0x12U)
00364
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00370   * @{
00371   */
00372 #define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01U)
00373 #define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02U)
00374 #define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03U)
00375 #define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04U)
00376 #define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05U)
00377 #define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06U)
00378 #define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07U)
00379
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
00385   * @{
00386   */
00387 #define RTC_ALARMDATEWEEKDAYSEL_DATE        0x00000000U
00388 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY     RTC_ALRMAR_WDSEL
00389
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
00395   * @{
00396   */
00397 #define RTC_ALARMMASK_NONE                  0x00000000U
00398 #define RTC_ALARMMASK_DATEWEEKDAY           RTC_ALRMAR_MSK4
00399 #define RTC_ALARMMASK_HOURS                 RTC_ALRMAR_MSK3
00400 #define RTC_ALARMMASK_MINUTES               RTC_ALRMAR_MSK2
00401 #define RTC_ALARMMASK_SECONDS               RTC_ALRMAR_MSK1
00402 #define RTC_ALARMMASK_ALL                   (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS  | \
00403                                              RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
00404
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00410   * @{
00411   */
00412 #define RTC_ALARM_A                         RTC_CR_ALRAE
00413 #define RTC_ALARM_B                         RTC_CR_ALRBE
00414
00415 /**
00416   * @}
00417   */
00418
00419
00420 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00421   * @{
00422   */
00423 #define RTC_ALARMSUBSECONDMASK_ALL          0x00000000U                                                              /*!< All Alarm SS fields are masked.
00424                                                                                                                           There is no comparison on sub seconds
00425                                                                                                                           for Alarm */
00426 #define RTC_ALARMSUBSECONDMASK_SS14_1       RTC_ALRMASSR_MASKSS_0                                                    /*!< SS[14:1] not used in Alarm
00427                                                                                                                           comparison. Only SS[0] is compared.    */
00428 #define RTC_ALARMSUBSECONDMASK_SS14_2       RTC_ALRMASSR_MASKSS_1                                                    /*!< SS[14:2] not used in Alarm
00429                                                                                                                           comparison. Only SS[1:0] are compared  */
00430 #define RTC_ALARMSUBSECONDMASK_SS14_3       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)                          /*!< SS[14:3] not used in Alarm
00431                                                                                                                           comparison. Only SS[2:0] are compared  */
00432 #define RTC_ALARMSUBSECONDMASK_SS14_4       RTC_ALRMASSR_MASKSS_2                                                    /*!< SS[14:4] not used in Alarm
00433                                                                                                                           comparison. Only SS[3:0] are compared  */
00434 #define RTC_ALARMSUBSECONDMASK_SS14_5       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:5] not used in Alarm
00435                                                                                                                           comparison. Only SS[4:0] are compared  */
00436 #define RTC_ALARMSUBSECONDMASK_SS14_6       (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:6] not used in Alarm
00437                                                                                                                           comparison. Only SS[5:0] are compared  */
00438 #define RTC_ALARMSUBSECONDMASK_SS14_7       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:7] not used in Alarm
00439                                                                                                                           comparison. Only SS[6:0] are compared  */
00440 #define RTC_ALARMSUBSECONDMASK_SS14_8       RTC_ALRMASSR_MASKSS_3                                                    /*!< SS[14:8] not used in Alarm
00441                                                                                                                           comparison. Only SS[7:0] are compared  */
00442 #define RTC_ALARMSUBSECONDMASK_SS14_9       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:9] not used in Alarm
00443                                                                                                                           comparison. Only SS[8:0] are compared  */
00444 #define RTC_ALARMSUBSECONDMASK_SS14_10      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:10] not used in Alarm
00445                                                                                                                           comparison. Only SS[9:0] are compared  */
00446 #define RTC_ALARMSUBSECONDMASK_SS14_11      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:11] not used in Alarm
00447                                                                                                                           comparison. Only SS[10:0] are compared */
00448 #define RTC_ALARMSUBSECONDMASK_SS14_12      (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:12] not used in Alarm
00449                                                                                                                           comparison.Only SS[11:0] are compared  */
00450 #define RTC_ALARMSUBSECONDMASK_SS14_13      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:13] not used in Alarm
00451                                                                                                                           comparison. Only SS[12:0] are compared */
00452 #define RTC_ALARMSUBSECONDMASK_SS14         (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] not used in Alarm
00453                                                                                                                           comparison. Only SS[13:0] are compared  */
00454 #define RTC_ALARMSUBSECONDMASK_NONE         RTC_ALRMASSR_MASKSS                                                      /*!< SS[14:0] are compared and must match
00455                                                                                                                           to activate alarm. */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00461   * @{
00462   */
00463 #define RTC_IT_TS                           RTC_CR_TSIE        /*!< Enable Timestamp Interrupt    */
00464 #define RTC_IT_WUT                          RTC_CR_WUTIE       /*!< Enable Wakeup timer Interrupt */
00465 #define RTC_IT_ALRA                         RTC_CR_ALRAIE      /*!< Enable Alarm A Interrupt      */
00466 #define RTC_IT_ALRB                         RTC_CR_ALRBIE      /*!< Enable Alarm B Interrupt      */
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup RTC_Flag_Mask    RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
00472   * @{
00473   */
00474 #define RTC_FLAG_MASK                       0x001FU            /*!< RTC flags mask (5bits) */
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00480   *        Elements values convention: 000000XX000YYYYYb
00481   *           - YYYYY  : Interrupt flag position in the XX register (5bits)
00482   *           - XX  : Interrupt status register (2bits)
00483   *                 - 01: ICSR register
00484   *                 - 10: SR or SCR or MISR registers
00485   * @{
00486   */
00487 #define RTC_FLAG_RECALPF                    (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
00488 #define RTC_FLAG_INITF                      (0x00000100U | RTC_ICSR_INITF_Pos)   /*!< Initialization flag */
00489 #define RTC_FLAG_RSF                        (0x00000100U | RTC_ICSR_RSF_Pos)     /*!< Registers synchronization flag */
00490 #define RTC_FLAG_INITS                      (0x00000100U | RTC_ICSR_INITS_Pos)   /*!< Initialization status flag */
00491 #define RTC_FLAG_SHPF                       (0x00000100U | RTC_ICSR_SHPF_Pos)    /*!< Shift operation pending flag */
00492 #define RTC_FLAG_WUTWF                      (0x00000100U | RTC_ICSR_WUTWF_Pos)   /*!< Wakeup timer write flag */
00493 #define RTC_FLAG_ALRBWF                     (0x00000100U | RTC_ICSR_ALRBWF_Pos)  /*!< Alarm B write flag */
00494 #define RTC_FLAG_ALRAWF                     (0x00000100U | RTC_ICSR_ALRAWF_Pos)  /*!< Alarm A write flag */
00495 #define RTC_FLAG_ITSF                       (0x00000200U | RTC_SR_ITSF_Pos)      /*!< Internal Time-stamp flag */
00496 #define RTC_FLAG_TSOVF                      (0x00000200U | RTC_SR_TSOVF_Pos)     /*!< Time-stamp overflow flag */
00497 #define RTC_FLAG_TSF                        (0x00000200U | RTC_SR_TSF_Pos)       /*!< Time-stamp flag */
00498 #define RTC_FLAG_WUTF                       (0x00000200U | RTC_SR_WUTF_Pos)      /*!< Wakeup timer flag */
00499 #define RTC_FLAG_ALRBF                      (0x00000200U | RTC_SR_ALRBF_Pos)     /*!< Alarm B flag */
00500 #define RTC_FLAG_ALRAF                      (0x00000200U | RTC_SR_ALRAF_Pos)     /*!< Alarm A flag */
00501  /**
00502   * @}
00503   */
00504
00505 /** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
00506   * @{
00507   */
00508 #define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
00509 #define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
00510 #define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
00511 #define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
00512 #define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
00513 #define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /* Exported macros -----------------------------------------------------------*/
00523 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00524   * @{
00525   */
00526
00527 /** @brief Reset RTC handle state
00528   * @param  __HANDLE__ RTC handle.
00529   * @retval None
00530   */
00531 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00532 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
00533                                                       (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
00534                                                       (__HANDLE__)->MspInitCallback = NULL;\
00535                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00536                                                      }while(0)
00537 #else
00538 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00539 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00540
00541 /**
00542   * @brief  Disable the write protection for RTC registers.
00543   * @param  __HANDLE__ specifies the RTC handle.
00544   * @retval None
00545   */
00546 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00547   do{                                       \
00548     (__HANDLE__)->Instance->WPR = 0xCAU;   \
00549     (__HANDLE__)->Instance->WPR = 0x53U;   \
00550   } while(0U)
00551
00552 /**
00553   * @brief  Enable the write protection for RTC registers.
00554   * @param  __HANDLE__ specifies the RTC handle.
00555   * @retval None
00556   */
00557 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00558   do{                                       \
00559     (__HANDLE__)->Instance->WPR = 0xFFU;   \
00560   } while(0U)
00561
00562 /**
00563   * @brief  Check whether the RTC Calendar is initialized.
00564   * @param  __HANDLE__ specifies the RTC handle.
00565   * @retval None
00566   */
00567 #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__)  (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
00568
00569 /**
00570   * @brief  Add 1 hour (summer time change).
00571   * @note   This interface is deprecated.
00572   *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
00573   * @param  __HANDLE__ specifies the RTC handle.
00574   * @param  __BKP__ Backup
00575   *         This parameter can be:
00576   *            @arg @ref RTC_STOREOPERATION_RESET
00577   *            @arg @ref RTC_STOREOPERATION_SET
00578   * @retval None
00579   */
00580 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                         \
00581   do {                                                              \
00582     __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
00583     SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);            \
00584     MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00585     __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
00586   } while(0);
00587
00588 /**
00589   * @brief  Subtract 1 hour (winter time change).
00590   * @note   This interface is deprecated.
00591   *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
00592   * @param  __HANDLE__ specifies the RTC handle.
00593   * @param  __BKP__ Backup
00594   *         This parameter can be:
00595   *            @arg @ref RTC_STOREOPERATION_RESET
00596   *            @arg @ref RTC_STOREOPERATION_SET
00597   * @retval None
00598   */
00599 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                         \
00600   do {                                                              \
00601     __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
00602     SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);            \
00603     MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00604     __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
00605   } while(0);
00606
00607 /**
00608   * @brief  Enable the RTC ALARMA peripheral.
00609   * @param  __HANDLE__ specifies the RTC handle.
00610   * @retval None
00611   */
00612 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00613
00614 /**
00615   * @brief  Disable the RTC ALARMA peripheral.
00616   * @param  __HANDLE__ specifies the RTC handle.
00617   * @retval None
00618   */
00619 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00620
00621 /**
00622   * @brief  Enable the RTC ALARMB peripheral.
00623   * @param  __HANDLE__ specifies the RTC handle.
00624   * @retval None
00625   */
00626 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00627
00628 /**
00629   * @brief  Disable the RTC ALARMB peripheral.
00630   * @param  __HANDLE__ specifies the RTC handle.
00631   * @retval None
00632   */
00633 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00634
00635 /**
00636   * @brief  Enable the RTC Alarm interrupt.
00637   * @param  __HANDLE__ specifies the RTC handle.
00638   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00639   *          This parameter can be any combination of the following values:
00640   *             @arg @ref RTC_IT_ALRA Alarm A interrupt
00641   *             @arg @ref RTC_IT_ALRB Alarm B interrupt
00642   * @retval None
00643   */
00644 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00645
00646 /**
00647   * @brief  Disable the RTC Alarm interrupt.
00648   * @param  __HANDLE__ specifies the RTC handle.
00649   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00650   *         This parameter can be any combination of the following values:
00651   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00652   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00653   * @retval None
00654   */
00655 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00656
00657 /**
00658   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00659   * @param  __HANDLE__ specifies the RTC handle.
00660   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00661   *         This parameter can be:
00662   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00663   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00664   * @retval None
00665   */
00666 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
00667
00668 /**
00669   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00670   * @param  __HANDLE__ specifies the RTC handle.
00671   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00672   *         This parameter can be:
00673   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00674   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00675   * @retval None
00676   */
00677 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
00678
00679 /**
00680   * @brief  Get the selected RTC Alarms flag status.
00681   * @param  __HANDLE__ specifies the RTC handle.
00682   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
00683   *         This parameter can be:
00684   *            @arg @ref RTC_FLAG_ALRAF
00685   *            @arg @ref RTC_FLAG_ALRBF
00686   *            @arg @ref RTC_FLAG_ALRAWF
00687   *            @arg @ref RTC_FLAG_ALRBWF
00688   * @retval None
00689   */
00690 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00691
00692 /**
00693   * @brief  Clear the RTC Alarms pending flags.
00694   * @param  __HANDLE__ specifies the RTC handle.
00695   * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
00696   *          This parameter can be:
00697   *             @arg @ref RTC_FLAG_ALRAF
00698   *             @arg @ref RTC_FLAG_ALRBF
00699   * @retval None
00700   */
00701 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \
00702                                                             ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))
00703 /**
00704   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00705   * @retval None
00706   */
00707 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00708
00709 /**
00710   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00711   * @retval None
00712   */
00713 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00714
00715 /**
00716   * @brief  Enable event on the RTC Alarm associated Exti line.
00717   * @retval None
00718   */
00719 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00720
00721 /**
00722   * @brief  Disable event on the RTC Alarm associated Exti line.
00723   * @retval None
00724   */
00725 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00726
00727 /**
00728   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00729   * @retval None
00730   */
00731 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00732
00733 /**
00734   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00735   * @retval None
00736   */
00737 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00738
00739 /**
00740   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00741   * @retval None
00742   */
00743 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00744
00745 /**
00746   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00747   * @retval None
00748   */
00749 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00750
00751 /**
00752   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00753   * @retval None
00754   */
00755 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00756                                                                 __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
00757                                                                 __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
00758                                                               } while(0)
00759
00760 /**
00761   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00762   * @retval None
00763   */
00764 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00765                                                                 __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
00766                                                                 __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
00767                                                               } while(0)
00768
00769 /**
00770   * @brief  set rising edge interrupt on the RTC Alarm associated Exti line.
00771   * @retval None
00772   */
00773 #define __HAL_RTC_ALARM_EXTI_RISING_IT()            (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00774
00775 /**
00776   * @brief  set rising edge interrupt on the RTC Alarm associated Exti line.
00777   * @retval None
00778   */
00779 #define __HAL_RTC_ALARM_EXTI_FALLING_IT()            (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00780
00781 /**
00782   * @brief  clear interrupt on the RTC Alarm associated Exti line.
00783   * @retval None
00784   */
00785 #define __HAL_RTC_ALARM_EXTI_CLEAR_IT()              (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
00786
00787
00788 /**
00789   * @}
00790   */
00791
00792 /* Include RTC HAL Extended module */
00793 #include "stm32g4xx_hal_rtc_ex.h"
00794
00795 /* Exported functions --------------------------------------------------------*/
00796 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00797   * @{
00798   */
00799
00800 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00801   * @{
00802   */
00803 /* Initialization and de-initialization functions  ****************************/
00804 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00805 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00806
00807 void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00808 void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00809 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00810
00811 /* Callbacks Register/UnRegister functions  ***********************************/
00812 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
00813                                            pRTC_CallbackTypeDef pCallback);
00814 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
00815 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00821   * @{
00822   */
00823 /* RTC Time and Date functions ************************************************/
00824 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00825 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00826 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00827 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00828 void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
00829 void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
00830 void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
00831 void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
00832 uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
00833 /**
00834   * @}
00835   */
00836
00837 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00838   * @{
00839   */
00840 /* RTC Alarm functions ********************************************************/
00841 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00842 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00843 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00844 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00845 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00846 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00847 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00848 /**
00849   * @}
00850   */
00851
00852 /** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
00853   * @{
00854   */
00855 /* Peripheral Control functions ***********************************************/
00856 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
00857 /**
00858   * @}
00859   */
00860
00861 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
00862   * @{
00863   */
00864 /* Peripheral State functions *************************************************/
00865 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00866 /**
00867   * @}
00868   */
00869
00870 /**
00871   * @}
00872   */
00873
00874 /* Private types -------------------------------------------------------------*/
00875 /* Private variables ---------------------------------------------------------*/
00876 /* Private constants ---------------------------------------------------------*/
00877 /** @defgroup RTC_Private_Constants RTC Private Constants
00878   * @{
00879   */
00880 /* Masks Definition */
00881 #define RTC_TR_RESERVED_MASK                (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
00882                                              RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
00883                                              RTC_TR_SU)
00884 #define RTC_DR_RESERVED_MASK                (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
00885                                              RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
00886                                              RTC_DR_DU)
00887 #define RTC_ICSR_RESERVED_MASK              (RTC_ICSR_RECALPF | RTC_ICSR_INIT | RTC_ICSR_INITF | \
00888                                             RTC_ICSR_RSF | RTC_ICSR_INITS | RTC_ICSR_SHPF | \
00889                                             RTC_ICSR_WUTWF | RTC_ICSR_ALRBWF | RTC_ICSR_ALRAWF)
00890 #define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
00891 #define RTC_INIT_MASK                       0xFFFFFFFFU
00892
00893 #define RTC_TIMEOUT_VALUE                   1000U
00894
00895 /**
00896   * @}
00897   */
00898
00899 /* Private macros ------------------------------------------------------------*/
00900 /** @defgroup RTC_Private_Macros RTC Private Macros
00901   * @{
00902   */
00903
00904 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00905   * @{
00906   */
00907 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
00908                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
00909                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
00910                                ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
00911                                ((OUTPUT) == RTC_OUTPUT_TAMPER))
00912
00913 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00914                                         ((FORMAT) == RTC_HOURFORMAT_24))
00915
00916 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00917                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00918
00919 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00920                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00921
00922 #define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
00923                                     ((TYPE) == RTC_OUTPUT_PULLUP_ON))
00924
00925 #define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
00926                                       ((REMAP) == RTC_OUTPUT_REMAP_POS1))
00927
00928 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
00929                                   ((PM) == RTC_HOURFORMAT12_PM))
00930
00931 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00932                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00933                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00934
00935 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00936                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00937
00938 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
00939                                ((FORMAT) == RTC_FORMAT_BCD))
00940
00941 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99u)
00942
00943 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))
00944
00945 #define IS_RTC_DATE(DATE)              (((DATE) >= 1u) && ((DATE) <= 31u))
00946
00947 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00948                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00949                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00950                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00951                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00952                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00953                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00954
00955 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
00956
00957 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00958                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00959                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00960                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00961                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00962                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00963                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00964
00965 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00966                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00967
00968 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
00969
00970 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
00971                                   ((ALARM) == RTC_ALARM_B))
00972
00973 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
00974
00975 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0UL) || \
00976                                                      (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
00977
00978 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
00979
00980 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
00981
00982 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0u) && ((HOUR) <= 12u))
00983
00984 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23u)
00985
00986 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)
00987
00988 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59u)
00989
00990 /**
00991   * @}
00992   */
00993
00994 /**
00995   * @}
00996   */
00997
00998 /* Private functions -------------------------------------------------------------*/
00999 /** @defgroup RTC_Private_Functions RTC Private Functions
01000   * @{
01001   */
01002 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
01003 HAL_StatusTypeDef  RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
01004 uint8_t            RTC_ByteToBcd2(uint8_t Value);
01005 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
01006 /**
01007   * @}
01008   */
01009
01010
01011 /**
01012   * @}
01013   */
01014
01015 /**
01016   * @}
01017   */
01018
01019 #ifdef __cplusplus
01020 }
01021 #endif
01022
01023 #endif /* STM32G4xx_HAL_RTC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_rtc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00008   *           + RTC Time Stamp functions
00009   *           + RTC Tamper functions
00010   *           + RTC Wake-up functions
00011   *           + Extended Control functions
00012   *           + Extended RTC features functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                   ##### How to use this driver #####
00028   ==============================================================================
00029   [..]
00030     (+) Enable the RTC domain access.
00031     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00032         format using the HAL_RTC_Init() function.
00033
00034   *** RTC Wakeup configuration ***
00035   ================================
00036   [..]
00037     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00038         function. You can also configure the RTC Wakeup timer with interrupt mode
00039         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00040     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00041         function.
00042
00043   *** Outputs configuration ***
00044   =============================
00045   [..]  The RTC has 2 different outputs:
00046     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00047         and WaKeUp signals.
00048         To output the selected RTC signal, use the HAL_RTC_Init() function.
00049     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00050         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00051     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00052         the RTC_OR register.
00053     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00054         automatically configured in output alternate function.
00055
00056   *** Smooth digital Calibration configuration ***
00057   ================================================
00058   [..]
00059     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00060         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00061         function.
00062
00063   *** TimeStamp configuration ***
00064   ===============================
00065   [..]
00066     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00067         You can also configure the RTC TimeStamp with interrupt mode using the
00068         HAL_RTCEx_SetTimeStamp_IT() function.
00069     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00070         function.
00071
00072   *** Internal TimeStamp configuration ***
00073   ===============================
00074   [..]
00075     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00076         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00077     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00078         function.
00079
00080    *** Tamper configuration ***
00081    ============================
00082    [..]
00083      (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00084          or Level according to the Tamper filter (if equal to 0 Edge else Level)
00085          value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00086          Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00087          with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00088      (+) The default configuration of the Tamper erases the backup registers. To avoid
00089          erase, enable the NoErase field on the RTC_TAMPCR register.
00090      (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization
00091          by setting ClockEnable init field to RTC_CLOCK_DISABLE.
00092      (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
00093          setting Interrupt field.
00094
00095    *** Backup Data Registers configuration ***
00096    ===========================================
00097    [..]
00098      (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00099          function.
00100      (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00101          function.
00102
00103   @endverbatim
00104   ******************************************************************************
00105   */
00106
00107 /* Includes ------------------------------------------------------------------*/
00108 #include "stm32g4xx_hal.h"
00109
00110 /** @addtogroup STM32G4xx_HAL_Driver
00111   * @{
00112   */
00113
00114 /** @addtogroup RTCEx
00115   * @brief RTC Extended HAL module driver
00116   * @{
00117   */
00118
00119 #ifdef HAL_RTC_MODULE_ENABLED
00120
00121 /* Private typedef -----------------------------------------------------------*/
00122 /* Private define ------------------------------------------------------------*/
00123
00124 /* Private macro -------------------------------------------------------------*/
00125 /* Private variables ---------------------------------------------------------*/
00126 /* Private function prototypes -----------------------------------------------*/
00127 /* Exported functions --------------------------------------------------------*/
00128
00129 /** @addtogroup RTCEx_Exported_Functions
00130   * @{
00131   */
00132
00133
00134 /** @addtogroup RTCEx_Exported_Functions_Group1
00135   *  @brief   RTC TimeStamp and Tamper functions
00136   *
00137 @verbatim
00138  ===============================================================================
00139                  ##### RTC TimeStamp and Tamper functions #####
00140  ===============================================================================
00141
00142  [..] This section provides functions allowing to configure TimeStamp feature
00143
00144 @endverbatim
00145   * @{
00146   */
00147
00148 /**
00149   * @brief  Set TimeStamp.
00150   * @note   This API must be called before enabling the TimeStamp feature.
00151   * @param  hrtc RTC handle
00152   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00153   *         activated.
00154   *          This parameter can be one of the following values:
00155   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00156   *                                        rising edge of the related pin.
00157   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00158   *                                         falling edge of the related pin.
00159   * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
00160   *          This parameter can be one of the following values:
00161   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00162   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00163   *               compatibility, this parameter is required.
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00167 {
00168   /* Check the parameters */
00169   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00170   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00171   UNUSED(RTC_TimeStampPin);
00172
00173   /* Process Locked */
00174   __HAL_LOCK(hrtc);
00175
00176   hrtc->State = HAL_RTC_STATE_BUSY;
00177
00178   /* Get the RTC_CR register and clear the bits to be configured */
00179   CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
00180
00181   /* Disable the write protection for RTC registers */
00182   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00183
00184   /* Configure the Time Stamp TSEDGE and Enable bits */
00185   SET_BIT(hrtc->Instance->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE);
00186
00187   /* Enable the write protection for RTC registers */
00188   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00189
00190   /* Change RTC state */
00191   hrtc->State = HAL_RTC_STATE_READY;
00192
00193   /* Process Unlocked */
00194   __HAL_UNLOCK(hrtc);
00195
00196   return HAL_OK;
00197 }
00198
00199 /**
00200   * @brief  Set TimeStamp with Interrupt.
00201   * @note   This API must be called before enabling the TimeStamp feature.
00202   * @param  hrtc RTC handle
00203   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00204   *         activated.
00205   *          This parameter can be one of the following values:
00206   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00207   *                                        rising edge of the related pin.
00208   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00209   *                                         falling edge of the related pin.
00210   * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
00211   *          This parameter can be one of the following values:
00212   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00213   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00214   *               compatibility, this parameter is required.
00215   * @retval HAL status
00216   */
00217 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00218 {
00219   /* Check the parameters */
00220   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00221   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00222   UNUSED(RTC_TimeStampPin);
00223
00224   /* Process Locked */
00225   __HAL_LOCK(hrtc);
00226
00227   hrtc->State = HAL_RTC_STATE_BUSY;
00228
00229   /* Disable the write protection for RTC registers */
00230   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00231
00232   /* Get the RTC_CR register and clear the bits to be configured */
00233   CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
00234
00235   /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
00236   SET_BIT(hrtc->Instance->CR, (uint32_t)TimeStampEdge);
00237
00238   /* clear interrupt flag if any */
00239   WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CITSF);
00240
00241   /* Enable IT timestamp */
00242   SET_BIT(hrtc->Instance->CR, (RTC_CR_TSE | RTC_CR_TSIE));
00243
00244   /* Enable the write protection for RTC registers */
00245   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00246
00247   /* RTC timestamp Interrupt Configuration: EXTI configuration (always rising edge)*/
00248   __HAL_RTC_TIMESTAMP_EXTI_RISING_IT();
00249   __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
00250
00251   hrtc->State = HAL_RTC_STATE_READY;
00252
00253   /* Process Unlocked */
00254   __HAL_UNLOCK(hrtc);
00255
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Deactivate TimeStamp.
00261   * @param  hrtc RTC handle
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00265 {
00266   /* Process Locked */
00267   __HAL_LOCK(hrtc);
00268
00269   hrtc->State = HAL_RTC_STATE_BUSY;
00270
00271   /* Disable the write protection for RTC registers */
00272   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00273
00274   /* clear event or interrupt flag */
00275   WRITE_REG(hrtc->Instance->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF));
00276
00277   /* In case of interrupt mode is used, the interrupt source must disabled */
00278   CLEAR_BIT(hrtc->Instance->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
00279
00280   __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT();
00281
00282   /* Enable the write protection for RTC registers */
00283   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00284
00285   hrtc->State = HAL_RTC_STATE_READY;
00286
00287   /* Process Unlocked */
00288   __HAL_UNLOCK(hrtc);
00289
00290   return HAL_OK;
00291 }
00292
00293 /**
00294   * @brief  Set Internal TimeStamp.
00295   * @note   This API must be called before enabling the internal TimeStamp feature.
00296   * @param  hrtc RTC handle
00297   * @retval HAL status
00298   */
00299 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00300 {
00301   /* Process Locked */
00302   __HAL_LOCK(hrtc);
00303
00304   hrtc->State = HAL_RTC_STATE_BUSY;
00305
00306   /* Disable the write protection for RTC registers */
00307   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00308
00309   /* Configure the internal Time Stamp Enable bits */
00310   SET_BIT(hrtc->Instance->CR, RTC_CR_ITSE);
00311
00312   /* Enable the write protection for RTC registers */
00313   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00314
00315   /* Change RTC state */
00316   hrtc->State = HAL_RTC_STATE_READY;
00317
00318   /* Process Unlocked */
00319   __HAL_UNLOCK(hrtc);
00320
00321   return HAL_OK;
00322 }
00323
00324 /**
00325   * @brief  Deactivate Internal TimeStamp.
00326   * @param  hrtc RTC handle
00327   * @retval HAL status
00328   */
00329 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00330 {
00331   /* Process Locked */
00332   __HAL_LOCK(hrtc);
00333
00334   hrtc->State = HAL_RTC_STATE_BUSY;
00335
00336   /* Disable the write protection for RTC registers */
00337   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00338
00339   /* Configure the internal Time Stamp Enable bits */
00340   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_ITSE);
00341
00342   /* Enable the write protection for RTC registers */
00343   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00344
00345   hrtc->State = HAL_RTC_STATE_READY;
00346
00347   /* Process Unlocked */
00348   __HAL_UNLOCK(hrtc);
00349
00350   return HAL_OK;
00351 }
00352
00353 /**
00354   * @brief  Get the RTC TimeStamp value.
00355   * @param  hrtc RTC handle
00356   * @param  sTimeStamp Pointer to Time structure
00357   * @param  sTimeStampDate Pointer to Date structure
00358   * @param  Format specifies the format of the entered parameters.
00359   *          This parameter can be one of the following values:
00360   *             @arg RTC_FORMAT_BIN: Binary data format
00361   *             @arg RTC_FORMAT_BCD: BCD data format
00362   * @retval HAL status
00363   */
00364 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
00365                                          RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
00366 {
00367   uint32_t tmptime, tmpdate;
00368
00369   /* Check the parameters */
00370   assert_param(IS_RTC_FORMAT(Format));
00371
00372   /* Get the TimeStamp time and date registers values */
00373   tmptime = (uint32_t)READ_BIT(hrtc->Instance->TSTR, RTC_TR_RESERVED_MASK);
00374   tmpdate = (uint32_t)READ_BIT(hrtc->Instance->TSDR, RTC_DR_RESERVED_MASK);
00375
00376   /* Fill the Time structure fields with the read parameters */
00377   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos);
00378   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
00379   sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos);
00380   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos);
00381   sTimeStamp->SubSeconds = (uint32_t)READ_BIT(hrtc->Instance->TSSSR, RTC_TSSSR_SS);
00382
00383   /* Fill the Date structure fields with the read parameters */
00384   sTimeStampDate->Year = 0U;
00385   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
00386   sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos);
00387   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos);
00388
00389   /* Check the input parameters format */
00390   if (Format == RTC_FORMAT_BIN)
00391   {
00392     /* Convert the TimeStamp structure parameters to Binary format */
00393     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00394     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00395     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00396
00397     /* Convert the DateTimeStamp structure parameters to Binary format */
00398     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00399     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00400     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00401   }
00402
00403   /* Clear the TIMESTAMP Flags */
00404   WRITE_REG(hrtc->Instance->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF));
00405
00406   return HAL_OK;
00407 }
00408
00409 /**
00410   * @brief  TimeStamp callback.
00411   * @param  hrtc RTC handle
00412   * @retval None
00413   */
00414 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00415 {
00416   /* Prevent unused argument(s) compilation warning */
00417   UNUSED(hrtc);
00418
00419   /* NOTE : This function should not be modified, when the callback is needed,
00420             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00421   */
00422 }
00423
00424 /**
00425   * @brief  Handle TimeStamp interrupt request.
00426   * @param  hrtc RTC handle
00427   * @retval None
00428   */
00429 void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00430 {
00431   /* Clear the EXTI Flag for RTC TimeStamp */
00432   __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG();
00433
00434   __IO uint32_t misr = READ_REG(hrtc->Instance->MISR);
00435
00436   /* Get the TimeStamp interrupt source enable */
00437   if ((misr & RTC_MISR_TSMF) != 0U)
00438   {
00439 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00440     /* Call TimeStampEvent registered Callback */
00441     hrtc->TimeStampEventCallback(hrtc);
00442 #else
00443     /* TIMESTAMP callback */
00444     HAL_RTCEx_TimeStampEventCallback(hrtc);
00445 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00446     /* check if TimeStamp is Internal, since ITSE bit is set in the CR */
00447     if ((misr & RTC_MISR_ITSMF) != 0U)
00448     {
00449       /* internal Timestamp interrupt */
00450       /* ITSF flag is set, TSF must be cleared together with ITSF (this will clear timestamp time and date registers) */
00451       WRITE_REG(hrtc->Instance->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF));
00452     }
00453     else
00454     {
00455       /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */
00456       WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CTSF);
00457     }
00458   }
00459
00460   /* Change RTC state */
00461   hrtc->State = HAL_RTC_STATE_READY;
00462 }
00463
00464 /**
00465   * @brief  Handle TimeStamp polling request.
00466   * @param  hrtc RTC handle
00467   * @param  Timeout Timeout duration
00468   * @retval HAL status
00469   */
00470 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00471 {
00472   uint32_t tickstart = HAL_GetTick();
00473
00474   while (READ_BIT(hrtc->Instance->SR, RTC_SR_TSF) == 0U)
00475   {
00476     if (READ_BIT(hrtc->Instance->SR, RTC_SR_TSOVF) != 0U)
00477     {
00478       /* Clear the TIMESTAMP OverRun Flag */
00479       WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CTSOVF);
00480
00481       /* Change TIMESTAMP state */
00482       hrtc->State = HAL_RTC_STATE_ERROR;
00483
00484       return HAL_ERROR;
00485     }
00486
00487     if (Timeout != HAL_MAX_DELAY)
00488     {
00489       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00490       {
00491         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00492
00493         /* Process Unlocked */
00494         __HAL_UNLOCK(hrtc);
00495
00496         return HAL_TIMEOUT;
00497       }
00498     }
00499   }
00500
00501   /* Change RTC state */
00502   hrtc->State = HAL_RTC_STATE_READY;
00503
00504   return HAL_OK;
00505 }
00506
00507 /**
00508   * @}
00509   */
00510
00511 /** @addtogroup RTCEx_Exported_Functions_Group2
00512   * @brief    RTC Wake-up functions
00513   *
00514 @verbatim
00515  ===============================================================================
00516                         ##### RTC Wake-up functions #####
00517  ===============================================================================
00518
00519  [..] This section provides functions allowing to configure Wake-up feature
00520
00521 @endverbatim
00522   * @{
00523   */
00524
00525 /**
00526   * @brief  Set wake up timer.
00527   * @param  hrtc RTC handle
00528   * @param  WakeUpCounter Wake up counter
00529   * @param  WakeUpClock Wake up clock
00530   * @retval HAL status
00531   */
00532 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00533 {
00534   uint32_t tickstart;
00535
00536   /* Check the parameters */
00537   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00538   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00539
00540   /* Process Locked */
00541   __HAL_LOCK(hrtc);
00542
00543   hrtc->State = HAL_RTC_STATE_BUSY;
00544
00545   /* Disable the write protection for RTC registers */
00546   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00547
00548   /* Clear WUTE in RTC_CR to disable the wakeup timer */
00549   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
00550
00551   /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
00552      counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
00553      calendar initialization mode. */
00554   if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
00555   {
00556     tickstart = HAL_GetTick();
00557
00558     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00559     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
00560     {
00561       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00562       {
00563         /* Enable the write protection for RTC registers */
00564         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00565
00566         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00567
00568         /* Process Unlocked */
00569         __HAL_UNLOCK(hrtc);
00570
00571         return HAL_TIMEOUT;
00572       }
00573     }
00574   }
00575
00576   /* Configure the clock source */
00577   MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
00578
00579   /* Configure the Wakeup Timer counter */
00580   WRITE_REG(hrtc->Instance->WUTR, (uint32_t)WakeUpCounter);
00581
00582   /* Enable the Wakeup Timer */
00583   SET_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
00584
00585   /* Enable the write protection for RTC registers */
00586   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00587
00588   hrtc->State = HAL_RTC_STATE_READY;
00589
00590   /* Process Unlocked */
00591   __HAL_UNLOCK(hrtc);
00592
00593   return HAL_OK;
00594 }
00595
00596 /**
00597   * @brief  Set wake up timer with interrupt.
00598   * @param  hrtc RTC handle
00599   * @param  WakeUpCounter Wake up counter
00600   * @param  WakeUpClock Wake up clock
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00604 {
00605   uint32_t tickstart;
00606
00607   /* Check the parameters */
00608   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00609   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00610
00611   /* Process Locked */
00612   __HAL_LOCK(hrtc);
00613
00614   hrtc->State = HAL_RTC_STATE_BUSY;
00615
00616   /* Disable the write protection for RTC registers */
00617   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00618
00619   /* Clear WUTE in RTC_CR to disable the wakeup timer */
00620   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
00621
00622   /* Clear flag Wake-Up */
00623   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
00624
00625   /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
00626      counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
00627      calendar initialization mode. */
00628   if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
00629   {
00630     tickstart = HAL_GetTick();
00631
00632     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00633     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
00634     {
00635       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00636       {
00637         /* Enable the write protection for RTC registers */
00638         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00639
00640         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00641
00642         /* Process Unlocked */
00643         __HAL_UNLOCK(hrtc);
00644
00645         return HAL_TIMEOUT;
00646       }
00647     }
00648   }
00649   /* Configure the Wakeup Timer counter */
00650   WRITE_REG(hrtc->Instance->WUTR, (uint32_t)WakeUpCounter);
00651
00652   /* Configure the clock source */
00653   MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
00654
00655   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
00656   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
00657   __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT();
00658
00659   /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer */
00660   SET_BIT(hrtc->Instance->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
00661
00662   /* Enable the write protection for RTC registers */
00663   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00664
00665   hrtc->State = HAL_RTC_STATE_READY;
00666
00667   /* Process Unlocked */
00668   __HAL_UNLOCK(hrtc);
00669
00670   return HAL_OK;
00671 }
00672
00673 /**
00674   * @brief  Deactivate wake up timer counter.
00675   * @param  hrtc RTC handle
00676   * @retval HAL status
00677   */
00678 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
00679 {
00680   uint32_t tickstart;
00681
00682   /* Process Locked */
00683   __HAL_LOCK(hrtc);
00684
00685   hrtc->State = HAL_RTC_STATE_BUSY;
00686
00687   /* Disable the write protection for RTC registers */
00688   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00689
00690   /* Disable the Wakeup Timer */
00691   /* In case of interrupt mode is used, the interrupt source must disabled */
00692   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE | RTC_CR_WUTIE);
00693
00694   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT();
00695
00696   tickstart = HAL_GetTick();
00697   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00698   while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
00699   {
00700     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00701     {
00702       /* Enable the write protection for RTC registers */
00703       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00704
00705       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00706
00707       /* Process Unlocked */
00708       __HAL_UNLOCK(hrtc);
00709
00710       return HAL_TIMEOUT;
00711     }
00712   }
00713
00714   /* Enable the write protection for RTC registers */
00715   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00716
00717   hrtc->State = HAL_RTC_STATE_READY;
00718
00719   /* Process Unlocked */
00720   __HAL_UNLOCK(hrtc);
00721
00722   return HAL_OK;
00723 }
00724
00725 /**
00726   * @brief  Get wake up timer counter.
00727   * @param  hrtc RTC handle
00728   * @retval Counter value
00729   */
00730 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
00731 {
00732   /* Get the counter value */
00733   return (uint32_t)(READ_BIT(hrtc->Instance->WUTR, RTC_WUTR_WUT));
00734 }
00735
00736 /**
00737   * @brief  Handle Wake Up Timer interrupt request.
00738   * @param  hrtc RTC handle
00739   * @retval None
00740   */
00741 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
00742 {
00743   /* Get the pending status of the WAKEUPTIMER Interrupt */
00744   if (READ_BIT(hrtc->Instance->SR, RTC_SR_WUTF) != 0U)
00745   {
00746     /* Clear the WAKEUPTIMER interrupt pending bit */
00747     WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CWUTF);
00748     __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT();
00749
00750 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00751     /* Call WakeUpTimerEvent registered Callback */
00752     hrtc->WakeUpTimerEventCallback(hrtc);
00753 #else
00754     /* WAKEUPTIMER callback */
00755     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
00756 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00757   }
00758
00759   /* Change RTC state */
00760   hrtc->State = HAL_RTC_STATE_READY;
00761 }
00762
00763 /**
00764   * @brief  Wake Up Timer callback.
00765   * @param  hrtc RTC handle
00766   * @retval None
00767   */
00768 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
00769 {
00770   /* Prevent unused argument(s) compilation warning */
00771   UNUSED(hrtc);
00772
00773   /* NOTE : This function should not be modified, when the callback is needed,
00774             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
00775    */
00776 }
00777
00778
00779 /**
00780   * @brief  Handle Wake Up Timer Polling.
00781   * @param  hrtc RTC handle
00782   * @param  Timeout Timeout duration
00783   * @retval HAL status
00784   */
00785 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00786 {
00787   uint32_t tickstart = HAL_GetTick();
00788
00789   while (READ_BIT(hrtc->Instance->SR, RTC_SR_WUTF) == 0U)
00790   {
00791     if (Timeout != HAL_MAX_DELAY)
00792     {
00793       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00794       {
00795         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00796
00797         /* Process Unlocked */
00798         __HAL_UNLOCK(hrtc);
00799
00800         return HAL_TIMEOUT;
00801       }
00802     }
00803   }
00804
00805   /* Clear the WAKEUPTIMER Flag */
00806   WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CWUTF);
00807
00808   /* Change RTC state */
00809   hrtc->State = HAL_RTC_STATE_READY;
00810
00811   return HAL_OK;
00812 }
00813
00814 /**
00815   * @}
00816   */
00817
00818
00819 /** @addtogroup RTCEx_Exported_Functions_Group3
00820   * @brief    Extended Peripheral Control functions
00821   *
00822 @verbatim
00823  ===============================================================================
00824               ##### Extended Peripheral Control functions #####
00825  ===============================================================================
00826     [..]
00827     This subsection provides functions allowing to
00828       (+) Write a data in a specified RTC Backup data register
00829       (+) Read a data in a specified RTC Backup data register
00830       (+) Set the Coarse calibration parameters.
00831       (+) Deactivate the Coarse calibration parameters
00832       (+) Set the Smooth calibration parameters.
00833       (+) Configure the Synchronization Shift Control Settings.
00834       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
00835       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
00836       (+) Enable the RTC reference clock detection.
00837       (+) Disable the RTC reference clock detection.
00838       (+) Enable the Bypass Shadow feature.
00839       (+) Disable the Bypass Shadow feature.
00840
00841 @endverbatim
00842   * @{
00843   */
00844
00845
00846
00847 /**
00848   * @brief  Set the Smooth calibration parameters.
00849   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
00850   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
00851   *         SmoothCalibMinusPulsesValue must be equal to 0.
00852   * @param  hrtc RTC handle
00853   * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
00854   *          This parameter can be can be one of the following values :
00855   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
00856   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
00857   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
00858   * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
00859   *          This parameter can be one of the following values:
00860   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
00861   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
00862   * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
00863   *          This parameter can be one any value from 0 to 0x000001FF.
00864   * @retval HAL status
00865   */
00866 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
00867                                            uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
00868 {
00869   uint32_t tickstart;
00870
00871   /* Check the parameters */
00872   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
00873   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
00874   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
00875
00876   /* Process Locked */
00877   __HAL_LOCK(hrtc);
00878
00879   hrtc->State = HAL_RTC_STATE_BUSY;
00880
00881   /* Disable the write protection for RTC registers */
00882   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00883
00884   /* check if a calibration is pending*/
00885   if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_RECALPF) != 0U)
00886   {
00887     tickstart = HAL_GetTick();
00888
00889     /* check if a calibration is pending*/
00890     while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_RECALPF) != 0U)
00891     {
00892       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00893       {
00894         /* Enable the write protection for RTC registers */
00895         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00896
00897         /* Change RTC state */
00898         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00899
00900         /* Process Unlocked */
00901         __HAL_UNLOCK(hrtc);
00902
00903         return HAL_TIMEOUT;
00904       }
00905     }
00906   }
00907
00908   /* Configure the Smooth calibration settings */
00909   MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM),
00910              (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
00911
00912
00913   /* Enable the write protection for RTC registers */
00914   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00915
00916   /* Change RTC state */
00917   hrtc->State = HAL_RTC_STATE_READY;
00918
00919   /* Process Unlocked */
00920   __HAL_UNLOCK(hrtc);
00921
00922   return HAL_OK;
00923 }
00924
00925 /**
00926   * @brief  Configure the Synchronization Shift Control Settings.
00927   * @note   When REFCKON is set, firmware must not write to Shift control register.
00928   * @param  hrtc RTC handle
00929   * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
00930   *          This parameter can be one of the following values:
00931   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
00932   *             @arg RTC_SHIFTADD1S_RESET: No effect.
00933   * @param  ShiftSubFS Select the number of Second Fractions to substitute.
00934   *          This parameter can be one any value from 0 to 0x7FFF.
00935   * @retval HAL status
00936   */
00937 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
00938 {
00939   uint32_t tickstart;
00940
00941   /* Check the parameters */
00942   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
00943   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
00944
00945   /* Process Locked */
00946   __HAL_LOCK(hrtc);
00947
00948   hrtc->State = HAL_RTC_STATE_BUSY;
00949
00950   /* Disable the write protection for RTC registers */
00951   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00952
00953   tickstart = HAL_GetTick();
00954
00955   /* Wait until the shift is completed*/
00956   while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_SHPF) != 0U)
00957   {
00958     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
00959     {
00960       /* Enable the write protection for RTC registers */
00961       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00962
00963       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00964
00965       /* Process Unlocked */
00966       __HAL_UNLOCK(hrtc);
00967
00968       return HAL_TIMEOUT;
00969     }
00970   }
00971
00972   /* Check if the reference clock detection is disabled */
00973   if (READ_BIT(hrtc->Instance->CR, RTC_CR_REFCKON) == 0U)
00974   {
00975     /* Configure the Shift settings */
00976     MODIFY_REG(hrtc->Instance->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S));
00977
00978     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00979     if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
00980     {
00981       if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00982       {
00983         /* Enable the write protection for RTC registers */
00984         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00985
00986         hrtc->State = HAL_RTC_STATE_ERROR;
00987
00988         /* Process Unlocked */
00989         __HAL_UNLOCK(hrtc);
00990
00991         return HAL_ERROR;
00992       }
00993     }
00994   }
00995   else
00996   {
00997     /* Enable the write protection for RTC registers */
00998     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00999
01000     /* Change RTC state */
01001     hrtc->State = HAL_RTC_STATE_ERROR;
01002
01003     /* Process Unlocked */
01004     __HAL_UNLOCK(hrtc);
01005
01006     return HAL_ERROR;
01007   }
01008
01009   /* Enable the write protection for RTC registers */
01010   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01011
01012   /* Change RTC state */
01013   hrtc->State = HAL_RTC_STATE_READY;
01014
01015   /* Process Unlocked */
01016   __HAL_UNLOCK(hrtc);
01017
01018   return HAL_OK;
01019 }
01020
01021 /**
01022   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01023   * @param  hrtc RTC handle
01024   * @param  CalibOutput Select the Calibration output Selection .
01025   *          This parameter can be one of the following values:
01026   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01027   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01028   * @retval HAL status
01029   */
01030 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
01031 {
01032   /* Check the parameters */
01033   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01034
01035   /* Process Locked */
01036   __HAL_LOCK(hrtc);
01037
01038   hrtc->State = HAL_RTC_STATE_BUSY;
01039
01040   /* Disable the write protection for RTC registers */
01041   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01042
01043   /* Configure the RTC_CR register */
01044   MODIFY_REG(hrtc->Instance->CR, RTC_CR_COSEL, (uint32_t)CalibOutput);
01045
01046   /* Enable calibration output */
01047   SET_BIT(hrtc->Instance->CR, RTC_CR_COE);
01048
01049   /* Enable the write protection for RTC registers */
01050   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01051
01052   /* Change RTC state */
01053   hrtc->State = HAL_RTC_STATE_READY;
01054
01055   /* Process Unlocked */
01056   __HAL_UNLOCK(hrtc);
01057
01058   return HAL_OK;
01059 }
01060
01061 /**
01062   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01063   * @param  hrtc RTC handle
01064   * @retval HAL status
01065   */
01066 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
01067 {
01068   /* Process Locked */
01069   __HAL_LOCK(hrtc);
01070
01071   hrtc->State = HAL_RTC_STATE_BUSY;
01072
01073   /* Disable the write protection for RTC registers */
01074   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01075
01076   /* Disable calibration output */
01077   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_COE);
01078
01079   /* Enable the write protection for RTC registers */
01080   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01081
01082   /* Change RTC state */
01083   hrtc->State = HAL_RTC_STATE_READY;
01084
01085   /* Process Unlocked */
01086   __HAL_UNLOCK(hrtc);
01087
01088   return HAL_OK;
01089 }
01090
01091 /**
01092   * @brief  Enable the RTC reference clock detection.
01093   * @param  hrtc RTC handle
01094   * @retval HAL status
01095   */
01096 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
01097 {
01098   HAL_StatusTypeDef status;
01099
01100   /* Process Locked */
01101   __HAL_LOCK(hrtc);
01102
01103   hrtc->State = HAL_RTC_STATE_BUSY;
01104
01105   /* Disable the write protection for RTC registers */
01106   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01107
01108   /* Enter Initialization mode */
01109   status = RTC_EnterInitMode(hrtc);
01110   if (status == HAL_OK)
01111   {
01112     /* Enable clockref detection */
01113     SET_BIT(hrtc->Instance->CR, RTC_CR_REFCKON);
01114
01115     /* Exit Initialization mode */
01116     status = RTC_ExitInitMode(hrtc);
01117   }
01118
01119   /* Enable the write protection for RTC registers */
01120   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01121
01122   if (status == HAL_OK)
01123   {
01124     hrtc->State = HAL_RTC_STATE_READY;
01125   }
01126
01127   /* Process Unlocked */
01128   __HAL_UNLOCK(hrtc);
01129
01130   return status;
01131 }
01132
01133 /**
01134   * @brief  Disable the RTC reference clock detection.
01135   * @param  hrtc RTC handle
01136   * @retval HAL status
01137   */
01138 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
01139 {
01140   HAL_StatusTypeDef status;
01141
01142   /* Process Locked */
01143   __HAL_LOCK(hrtc);
01144
01145   hrtc->State = HAL_RTC_STATE_BUSY;
01146
01147   /* Disable the write protection for RTC registers */
01148   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01149
01150   /* Enter Initialization mode */
01151   status = RTC_EnterInitMode(hrtc);
01152   if (status == HAL_OK)
01153   {
01154     /* Disable clockref detection */
01155     CLEAR_BIT(hrtc->Instance->CR, RTC_CR_REFCKON);
01156
01157     /* Exit Initialization mode */
01158     status = RTC_ExitInitMode(hrtc);
01159   }
01160
01161   /* Enable the write protection for RTC registers */
01162   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01163
01164   if (status == HAL_OK)
01165   {
01166     hrtc->State = HAL_RTC_STATE_READY;
01167   }
01168
01169   /* Process Unlocked */
01170   __HAL_UNLOCK(hrtc);
01171
01172   return status;
01173 }
01174
01175 /**
01176   * @brief  Enable the Bypass Shadow feature.
01177   * @note   When the Bypass Shadow is enabled the calendar value are taken
01178   *         directly from the Calendar counter.
01179   * @param  hrtc RTC handle
01180   * @retval HAL status
01181   */
01182 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
01183 {
01184   /* Process Locked */
01185   __HAL_LOCK(hrtc);
01186
01187   hrtc->State = HAL_RTC_STATE_BUSY;
01188
01189   /* Disable the write protection for RTC registers */
01190   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01191
01192   /* Set the BYPSHAD bit */
01193   SET_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD);
01194
01195   /* Enable the write protection for RTC registers */
01196   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01197
01198   /* Change RTC state */
01199   hrtc->State = HAL_RTC_STATE_READY;
01200
01201   /* Process Unlocked */
01202   __HAL_UNLOCK(hrtc);
01203
01204   return HAL_OK;
01205 }
01206
01207 /**
01208   * @brief  Disable the Bypass Shadow feature.
01209   * @note   When the Bypass Shadow is enabled the calendar value are taken
01210   *         directly from the Calendar counter.
01211   * @param  hrtc RTC handle
01212   * @retval HAL status
01213   */
01214 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
01215 {
01216   /* Process Locked */
01217   __HAL_LOCK(hrtc);
01218
01219   hrtc->State = HAL_RTC_STATE_BUSY;
01220
01221   /* Disable the write protection for RTC registers */
01222   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01223
01224   /* Reset the BYPSHAD bit */
01225   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD);
01226
01227   /* Enable the write protection for RTC registers */
01228   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01229
01230   /* Change RTC state */
01231   hrtc->State = HAL_RTC_STATE_READY;
01232
01233   /* Process Unlocked */
01234   __HAL_UNLOCK(hrtc);
01235
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @}
01241   */
01242
01243 /** @addtogroup RTCEx_Exported_Functions_Group4
01244   * @brief    Extended features functions
01245   *
01246 @verbatim
01247  ===============================================================================
01248                  ##### Extended features functions #####
01249  ===============================================================================
01250     [..]  This section provides functions allowing to:
01251       (+) RTC Alarm B callback
01252       (+) RTC Poll for Alarm B request
01253
01254 @endverbatim
01255   * @{
01256   */
01257
01258 /**
01259   * @brief  Alarm B callback.
01260   * @param  hrtc RTC handle
01261   * @retval None
01262   */
01263 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01264 {
01265   /* Prevent unused argument(s) compilation warning */
01266   UNUSED(hrtc);
01267
01268   /* NOTE : This function should not be modified, when the callback is needed,
01269             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01270    */
01271 }
01272
01273 /**
01274   * @brief  Handle Alarm B Polling request.
01275   * @param  hrtc RTC handle
01276   * @param  Timeout Timeout duration
01277   * @retval HAL status
01278   */
01279 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01280 {
01281   uint32_t tickstart = HAL_GetTick();
01282
01283   while (READ_BIT(hrtc->Instance->SR, RTC_SR_ALRBF) == 0U)
01284   {
01285     if (Timeout != HAL_MAX_DELAY)
01286     {
01287       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01288       {
01289         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01290
01291         /* Process Unlocked */
01292         __HAL_UNLOCK(hrtc);
01293
01294         return HAL_TIMEOUT;
01295       }
01296     }
01297   }
01298
01299   /* Clear the Alarm Flag */
01300   WRITE_REG(hrtc->Instance->SCR, RTC_SCR_CALRBF);
01301
01302   /* Change RTC state */
01303   hrtc->State = HAL_RTC_STATE_READY;
01304
01305   return HAL_OK;
01306 }
01307
01308 /**
01309   * @}
01310   */
01311
01312 /** @addtogroup RTCEx_Exported_Functions_Group5
01313   * @brief      Extended RTC Tamper functions
01314   *
01315 @verbatim
01316   ==============================================================================
01317                          ##### Tamper functions #####
01318   ==============================================================================
01319   [..]
01320    (+) Before calling any tamper or internal tamper function, you have to call first
01321        HAL_RTC_Init() function.
01322    (+) In that ine you can select to output tamper event on RTC pin.
01323   [..]
01324    (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
01325        or Level according to the Tamper filter (if equal to 0 Edge else Level)
01326        value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
01327        Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
01328        You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
01329    (+) The default configuration of the Tamper erases the backup registers. To avoid
01330        erase, enable the NoErase field on the TAMP_TAMPCR register.
01331   [..]
01332    (+) Enable Internal Tamper and configure it with interrupt, timestamp using
01333        the HAL_RTCEx_SetInternalTamper() function.
01334
01335 @endverbatim
01336   * @{
01337   */
01338
01339
01340 /**
01341   * @brief  Set Tamper
01342   * @param  hrtc RTC handle
01343   * @param  sTamper Pointer to Tamper Structure.
01344   * @retval HAL status
01345   */
01346 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
01347 {
01348   uint32_t tmpreg;
01349
01350   /* Check the parameters */
01351   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
01352   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
01353   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
01354   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
01355   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
01356   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
01357   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
01358   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
01359   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
01360   /* Trigger and Filter have exclusive configurations */
01361   assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL)))
01362                || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))));
01363
01364   /* Configuration register 2 */
01365   tmpreg = READ_REG(TAMP->CR2);
01366   tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
01367
01368   if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
01369   {
01370     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
01371   }
01372
01373   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
01374   {
01375     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos);
01376   }
01377
01378   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
01379   {
01380     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
01381   }
01382   WRITE_REG(TAMP->CR2, tmpreg);
01383
01384   /* Filter control register */
01385   WRITE_REG(TAMP->FLTCR, (sTamper->Filter | sTamper->SamplingFrequency | \
01386                           sTamper->PrechargeDuration | sTamper->TamperPullUp));
01387
01388   /* timestamp on tamper */
01389   if (READ_BIT(hrtc->Instance->CR, RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection))
01390   {
01391     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01392     MODIFY_REG(hrtc->Instance->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
01393     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01394   }
01395
01396   /* Control register 1 */
01397   SET_BIT(TAMP->CR1, sTamper->Tamper);
01398
01399   return HAL_OK;
01400 }
01401
01402
01403 /**
01404   * @brief  Set Tamper in IT mode
01405   * @param  hrtc RTC handle
01406   * @param  sTamper Pointer to Tamper Structure.
01407   * @retval HAL status
01408   */
01409 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
01410 {
01411   uint32_t tmpreg;
01412
01413   /* Check the parameters */
01414   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
01415   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
01416   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
01417   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
01418   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
01419   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
01420   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
01421   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
01422   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
01423
01424   /* Configuration register 2 */
01425   tmpreg = READ_REG(TAMP->CR2);
01426   tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
01427
01428   if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
01429   {
01430     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
01431   }
01432
01433   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
01434   {
01435     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos);
01436   }
01437
01438   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
01439   {
01440     tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos);
01441   }
01442   WRITE_REG(TAMP->CR2, tmpreg);
01443
01444   /* Filter control register */
01445   WRITE_REG(TAMP->FLTCR, (sTamper->Filter | sTamper->SamplingFrequency | \
01446                           sTamper->PrechargeDuration | sTamper->TamperPullUp));
01447
01448   /* timestamp on tamper */
01449   if (READ_BIT(hrtc->Instance->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
01450   {
01451     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01452     MODIFY_REG(hrtc->Instance->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
01453     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01454   }
01455
01456   /* RTC Tamper Interrupt Configuration: EXTI configuration */
01457   __HAL_RTC_TAMPER_EXTI_ENABLE_IT();
01458   __HAL_RTC_TAMPER_EXTI_RISING_IT();
01459   __HAL_RTC_TAMPER_EXTI_CLEAR_IT();
01460
01461   /* Interrupt enable register */
01462   SET_BIT(TAMP->IER, sTamper->Tamper);
01463
01464   /* Control register 1 */
01465   SET_BIT(TAMP->CR1, sTamper->Tamper);
01466
01467   return HAL_OK;
01468 }
01469
01470 /**
01471   * @brief  Deactivate Tamper.
01472   * @param  hrtc RTC handle
01473   * @param  Tamper Selected tamper pin.
01474   *         This parameter can be a combination of the following values:
01475   *         @arg RTC_TAMPER_1
01476   *         @arg RTC_TAMPER_2
01477   * @retval HAL status
01478   */
01479 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
01480 {
01481   assert_param(IS_RTC_TAMPER(Tamper));
01482
01483   /* Disable the selected Tamper pin */
01484   CLEAR_BIT(TAMP->CR1, Tamper);
01485
01486   /* Clear tamper mask/noerase/trigger configuration */
01487   CLEAR_BIT(TAMP->CR2, ((Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MF_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos)));
01488
01489   /* Clear tamper interrupt mode configuration */
01490   CLEAR_BIT(TAMP->IER, Tamper);
01491
01492   /* Clear tamper interrupt and event flags (WO register) */
01493   WRITE_REG(TAMP->SCR, Tamper);
01494
01495   /* In case of interrupt mode is used, the interrupt source must disabled */
01496   __HAL_RTC_TAMPER_EXTI_CLEAR_IT();
01497
01498   return HAL_OK;
01499 }
01500
01501
01502 /**
01503   * @brief  Tamper event polling.
01504   * @param  hrtc RTC handle
01505   * @param  Tamper Selected tamper pin.
01506   *         This parameter can be a combination of the following values:
01507   *         @arg RTC_TAMPER_1
01508   *         @arg RTC_TAMPER_2
01509   * @param  Timeout Timeout duration
01510   * @retval HAL status
01511   */
01512 HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
01513 {
01514   uint32_t tickstart = HAL_GetTick();
01515
01516   UNUSED(hrtc);
01517
01518   assert_param(IS_RTC_TAMPER(Tamper));
01519
01520   /* Get the status of the Interrupt */
01521   while (READ_BIT(TAMP->SR, Tamper) != Tamper)
01522   {
01523     if (Timeout != HAL_MAX_DELAY)
01524     {
01525       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01526       {
01527         return HAL_TIMEOUT;
01528       }
01529     }
01530   }
01531
01532   /* Clear the Tamper Flag */
01533   WRITE_REG(TAMP->SCR, Tamper);
01534
01535   return HAL_OK;
01536 }
01537
01538
01539 /**
01540   * @brief  Set Internal Tamper in interrupt mode
01541   * @param  hrtc RTC handle
01542   * @param  sIntTamper Pointer to Internal Tamper Structure.
01543   * @retval HAL status
01544   */
01545 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
01546 {
01547
01548   /* Check the parameters */
01549   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01550   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01551
01552   /* timestamp on internal tamper */
01553   if (READ_BIT(hrtc->Instance->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
01554   {
01555     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01556     MODIFY_REG(hrtc->Instance->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
01557     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01558   }
01559
01560   /* Control register 1 */
01561   SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
01562
01563   return HAL_OK;
01564 }
01565
01566
01567 /**
01568   * @brief  Set Internal Tamper
01569   * @param  hrtc RTC handle
01570   * @param  sIntTamper Pointer to Internal Tamper Structure.
01571   * @retval HAL status
01572   */
01573 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
01574 {
01575   /* Check the parameters */
01576   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01577   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01578
01579   /* timestamp on internal tamper */
01580   if (READ_BIT(hrtc->Instance->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
01581   {
01582     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01583     MODIFY_REG(hrtc->Instance->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
01584     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01585   }
01586
01587   /* RTC Tamper Interrupt Configuration: EXTI configuration */
01588   __HAL_RTC_TAMPER_EXTI_ENABLE_IT();
01589   __HAL_RTC_TAMPER_EXTI_RISING_IT();
01590
01591   /* Interrupt enable register */
01592   SET_BIT(TAMP->IER, sIntTamper->IntTamper);
01593
01594   /* Control register 1 */
01595   SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
01596
01597   return HAL_OK;
01598 }
01599
01600 /**
01601   * @brief  Deactivate Internal Tamper.
01602   * @param  hrtc RTC handle
01603   * @param  IntTamper Selected internal tamper event.
01604   *          This parameter can be any combination of existing internal tampers.
01605   * @retval HAL status
01606   */
01607 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
01608 {
01609   UNUSED(hrtc);
01610
01611   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01612
01613   /* Disable the selected Tamper pin */
01614   CLEAR_BIT(TAMP->CR1, IntTamper);
01615
01616   /* Clear internal tamper interrupt mode configuration */
01617   CLEAR_BIT(TAMP->IER, IntTamper);
01618
01619   /* Clear internal tamper interrupt */
01620   WRITE_REG(TAMP->SCR, IntTamper);
01621
01622   /* In case of interrupt mode is used, the interrupt source must disabled */
01623   __HAL_RTC_TAMPER_EXTI_CLEAR_IT();
01624
01625   return HAL_OK;
01626 }
01627
01628
01629 /**
01630   * @brief  Internal Tamper event polling.
01631   * @param  hrtc RTC handle
01632   * @param  IntTamper selected tamper.
01633   *          This parameter can be any combination of existing internal tampers.
01634   * @param  Timeout Timeout duration
01635   * @retval HAL status
01636   */
01637 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
01638 {
01639   UNUSED(hrtc);
01640
01641   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01642
01643   uint32_t tickstart = HAL_GetTick();
01644
01645   /* Get the status of the Interrupt */
01646   while (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
01647   {
01648     if (Timeout != HAL_MAX_DELAY)
01649     {
01650       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01651       {
01652         return HAL_TIMEOUT;
01653       }
01654     }
01655   }
01656
01657   /* Clear the Tamper Flag */
01658   WRITE_REG(TAMP->SCR, IntTamper);
01659
01660   return HAL_OK;
01661 }
01662
01663
01664 /**
01665   * @brief  Handle Tamper interrupt request.
01666   * @param  hrtc RTC handle
01667   * @retval None
01668   */
01669 void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
01670 {
01671   uint32_t tmp;
01672
01673   /* Get interrupt status */
01674   tmp = READ_REG(TAMP->MISR);
01675
01676   /* Check enable interrupts */
01677   tmp &= READ_REG(TAMP->IER);
01678
01679   /* Immediately clear flags */
01680   WRITE_REG(TAMP->SCR, tmp);
01681
01682   /* In case of interrupt mode is used, the interrupt source must disabled */
01683   __HAL_RTC_TAMPER_EXTI_CLEAR_IT();
01684
01685   /* Check Tamper1 status */
01686   if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
01687   {
01688 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01689     /* Call Tamper 1 Event registered Callback */
01690     hrtc->Tamper1EventCallback(hrtc);
01691 #else
01692     /* Tamper1 callback */
01693     HAL_RTCEx_Tamper1EventCallback(hrtc);
01694 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01695   }
01696
01697   /* Check Tamper2 status */
01698   if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
01699   {
01700 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01701     /* Call Tamper 2 Event registered Callback */
01702     hrtc->Tamper2EventCallback(hrtc);
01703 #else
01704     /* Tamper2 callback */
01705     HAL_RTCEx_Tamper2EventCallback(hrtc);
01706 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01707   }
01708 #if (RTC_TAMP_NB == 3)
01709
01710   /* Check Tamper3 status */
01711   if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
01712   {
01713 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01714     /* Call Tamper 3 Event registered Callback */
01715     hrtc->Tamper3EventCallback(hrtc);
01716 #else
01717     /* Tamper3 callback */
01718     HAL_RTCEx_Tamper3EventCallback(hrtc);
01719 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01720   }
01721 #endif /* RTC_TAMP_NB */
01722
01723 #ifdef RTC_TAMP_INT_1_SUPPORT
01724   /* Check Internal Tamper1 status */
01725   if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
01726   {
01727 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01728     /* Call Internal Tamper 1 Event registered Callback */
01729     hrtc->InternalTamper1EventCallback(hrtc);
01730 #else
01731     /* Internal Tamper1 callback */
01732     HAL_RTCEx_InternalTamper1EventCallback(hrtc);
01733 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01734   }
01735 #endif /* RTC_TAMP_INT_1_SUPPORT */
01736
01737 #ifdef RTC_TAMP_INT_2_SUPPORT
01738
01739   /* Check Internal Tamper2 status */
01740   if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
01741   {
01742 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01743     /* Call Internal Tamper 2 Event registered Callback */
01744     hrtc->InternalTamper2EventCallback(hrtc);
01745 #else
01746     /* Internal Tamper2 callback */
01747     HAL_RTCEx_InternalTamper2EventCallback(hrtc);
01748 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01749   }
01750 #endif /* RTC_TAMP_INT_2_SUPPORT */
01751
01752   /* Check Internal Tamper3 status */
01753   if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
01754   {
01755 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01756     /* Call Internal Tamper 3 Event registered Callback */
01757     hrtc->InternalTamper3EventCallback(hrtc);
01758 #else
01759     /* Internal Tamper3 callback */
01760     HAL_RTCEx_InternalTamper3EventCallback(hrtc);
01761 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01762   }
01763
01764   /* Check Internal Tamper4 status */
01765   if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4)
01766   {
01767 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01768     /* Call Internal Tamper 4 Event registered Callback */
01769     hrtc->InternalTamper4EventCallback(hrtc);
01770 #else
01771     /* Internal Tamper4 callback */
01772     HAL_RTCEx_InternalTamper4EventCallback(hrtc);
01773 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01774   }
01775
01776   /* Check Internal Tamper5 status */
01777   if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
01778   {
01779 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01780     /* Call Internal Tamper 5 Event registered Callback */
01781     hrtc->InternalTamper5EventCallback(hrtc);
01782 #else
01783     /* Internal Tamper5 callback */
01784     HAL_RTCEx_InternalTamper5EventCallback(hrtc);
01785 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01786   }
01787 #ifdef RTC_TAMP_INT_6_SUPPORT
01788
01789   /* Check Internal Tamper6 status */
01790   if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
01791   {
01792 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01793     /* Call Internal Tamper 6 Event registered Callback */
01794     hrtc->InternalTamper6EventCallback(hrtc);
01795 #else
01796     /* Internal Tamper6 callback */
01797     HAL_RTCEx_InternalTamper6EventCallback(hrtc);
01798 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01799   }
01800 #endif /* RTC_TAMP_INT_6_SUPPORT */
01801 #ifdef RTC_TAMP_INT_7_SUPPORT
01802
01803   /* Check Internal Tamper7 status */
01804   if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
01805   {
01806 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01807     /* Call Internal Tamper 7 Event registered Callback */
01808     hrtc->InternalTamper7EventCallback(hrtc);
01809 #else
01810     /* Internal Tamper7 callback */
01811     HAL_RTCEx_InternalTamper7EventCallback(hrtc);
01812 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01813   }
01814 #endif /* RTC_TAMP_INT_7_SUPPORT */
01815 }
01816
01817 /**
01818   * @brief  Tamper 1 callback.
01819   * @param  hrtc RTC handle
01820   * @retval None
01821   */
01822 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
01823 {
01824   /* Prevent unused argument(s) compilation warning */
01825   UNUSED(hrtc);
01826
01827   /* NOTE : This function should not be modified, when the callback is needed,
01828             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
01829    */
01830 }
01831
01832 /**
01833   * @brief  Tamper 2 callback.
01834   * @param  hrtc RTC handle
01835   * @retval None
01836   */
01837 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
01838 {
01839   /* Prevent unused argument(s) compilation warning */
01840   UNUSED(hrtc);
01841
01842   /* NOTE : This function should not be modified, when the callback is needed,
01843             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
01844    */
01845 }
01846 #if (RTC_TAMP_NB == 3)
01847
01848 /**
01849   * @brief  Tamper 3 callback.
01850   * @param  hrtc RTC handle
01851   * @retval None
01852   */
01853 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
01854 {
01855   /* Prevent unused argument(s) compilation warning */
01856   UNUSED(hrtc);
01857
01858   /* NOTE : This function should not be modified, when the callback is needed,
01859             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
01860    */
01861 }
01862 #endif /* RTC_TAMP_NB */
01863
01864 #ifdef RTC_TAMP_INT_1_SUPPORT
01865 /**
01866   * @brief  Internal Tamper 1 callback.
01867   * @param  hrtc RTC handle
01868   * @retval None
01869   */
01870 __weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc)
01871 {
01872   /* Prevent unused argument(s) compilation warning */
01873   UNUSED(hrtc);
01874
01875   /* NOTE : This function should not be modified, when the callback is needed,
01876             the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file
01877    */
01878 }
01879 #endif /* RTC_TAMP_INT_1_SUPPORT */
01880
01881 #ifdef RTC_TAMP_INT_2_SUPPORT
01882 /**
01883   * @brief  Internal Tamper 2 callback.
01884   * @param  hrtc RTC handle
01885   * @retval None
01886   */
01887 __weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc)
01888 {
01889   /* Prevent unused argument(s) compilation warning */
01890   UNUSED(hrtc);
01891
01892   /* NOTE : This function should not be modified, when the callback is needed,
01893             the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file
01894    */
01895 }
01896 #endif /* RTC_TAMP_INT_2_SUPPORT */
01897
01898 /**
01899   * @brief  Internal Tamper 3 callback.
01900   * @param  hrtc RTC handle
01901   * @retval None
01902   */
01903 __weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc)
01904 {
01905   /* Prevent unused argument(s) compilation warning */
01906   UNUSED(hrtc);
01907
01908   /* NOTE : This function should not be modified, when the callback is needed,
01909             the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file
01910    */
01911 }
01912
01913 /**
01914   * @brief  Internal Tamper 4 callback.
01915   * @param  hrtc RTC handle
01916   * @retval None
01917   */
01918 __weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc)
01919 {
01920   /* Prevent unused argument(s) compilation warning */
01921   UNUSED(hrtc);
01922
01923   /* NOTE : This function should not be modified, when the callback is needed,
01924             the HAL_RTCEx_InternalTamper4EventCallback could be implemented in the user file
01925    */
01926 }
01927
01928 /**
01929   * @brief  Internal Tamper 5 callback.
01930   * @param  hrtc RTC handle
01931   * @retval None
01932   */
01933 __weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc)
01934 {
01935   /* Prevent unused argument(s) compilation warning */
01936   UNUSED(hrtc);
01937
01938   /* NOTE : This function should not be modified, when the callback is needed,
01939             the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file
01940    */
01941 }
01942
01943 #ifdef RTC_TAMP_INT_6_SUPPORT
01944
01945 /**
01946   * @brief  Internal Tamper 6 callback.
01947   * @param  hrtc RTC handle
01948   * @retval None
01949   */
01950 __weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc)
01951 {
01952   /* Prevent unused argument(s) compilation warning */
01953   UNUSED(hrtc);
01954
01955   /* NOTE : This function should not be modified, when the callback is needed,
01956             the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file
01957    */
01958 }
01959
01960 #endif /* RTC_TAMP_INT_6_SUPPORT */
01961 #ifdef RTC_TAMP_INT_7_SUPPORT
01962 /**
01963   * @brief  Internal Tamper 7 callback.
01964   * @param  hrtc RTC handle
01965   * @retval None
01966   */
01967 __weak void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc)
01968 {
01969   /* Prevent unused argument(s) compilation warning */
01970   UNUSED(hrtc);
01971
01972   /* NOTE : This function should not be modified, when the callback is needed,
01973             the HAL_RTCEx_InternalTamper7EventCallback could be implemented in the user file
01974    */
01975 }
01976 #endif /* RTC_TAMP_INT_7_SUPPORT */
01977
01978 /**
01979   * @}
01980   */
01981
01982
01983 /** @addtogroup RTCEx_Exported_Functions_Group6
01984   * @brief      Extended RTC Backup register functions
01985   *
01986 @verbatim
01987   ===============================================================================
01988              ##### Extended RTC Backup register functions #####
01989   ===============================================================================
01990   [..]
01991    (+) Before calling any tamper or internal tamper function, you have to call first
01992        HAL_RTC_Init() function.
01993    (+) In that ine you can select to output tamper event on RTC pin.
01994   [..]
01995    This subsection provides functions allowing to
01996    (+) Write a data in a specified RTC Backup data register
01997    (+) Read a data in a specified RTC Backup data register
01998 @endverbatim
01999   * @{
02000   */
02001
02002
02003 /**
02004   * @brief  Write a data in a specified TAMP Backup data register.
02005   * @param  hrtc RTC handle
02006   * @param  BackupRegister RTC Backup data Register number.
02007   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
02008   *          specify the register.
02009   * @param  Data Data to be written in the specified TAMP Backup data register.
02010   * @retval None
02011   */
02012 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
02013 {
02014   uint32_t tmp;
02015
02016   UNUSED(hrtc);
02017   /* Check the parameters */
02018   assert_param(IS_RTC_BKP(BackupRegister));
02019
02020   tmp = (uint32_t) &(TAMP->BKP0R);
02021   tmp += (BackupRegister * 4U);
02022
02023   /* Write the specified register */
02024   *(__IO uint32_t *)tmp = (uint32_t)Data;
02025 }
02026
02027
02028 /**
02029   * @brief  Reads data from the specified TAMP Backup data Register.
02030   * @param  hrtc RTC handle
02031   * @param  BackupRegister RTC Backup data Register number.
02032   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB to
02033   *          specify the register.
02034   * @retval Read value
02035   */
02036 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
02037 {
02038   uint32_t tmp;
02039
02040   UNUSED(hrtc);
02041   /* Check the parameters */
02042   assert_param(IS_RTC_BKP(BackupRegister));
02043
02044   tmp = (uint32_t) &(TAMP->BKP0R);
02045   tmp += (BackupRegister * 4U);
02046
02047   /* Read the specified register */
02048   return (*(__IO uint32_t *)tmp);
02049 }
02050
02051 /**
02052   * @}
02053   */
02054
02055 /**
02056   * @}
02057   */
02058
02059 #endif /* HAL_RTC_MODULE_ENABLED */
02060 /**
02061   * @}
02062   */
02063
02064
02065 /**
02066   * @}
02067   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_rtc_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_rtc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_RTC_EX_H
00021 #define STM32G4xx_HAL_RTC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup RTCEx RTCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
00044   * @{
00045   */
00046 typedef struct
00047 {
00048   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00049                                              This parameter can be a value of @ref RTCEx_Tamper_Pins */
00050
00051   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00052                                              This parameter can be a value of @ref RTCEx_Tamper_Trigger */
00053
00054   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00055                                              This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
00056
00057   uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
00058                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
00059
00060   uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.
00061                                              This parameter can be a value of @ref RTCEx_Tamper_Filter */
00062
00063   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00064                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */
00065
00066   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00067                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */
00068
00069   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00070                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
00071
00072   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00073                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
00074 } RTC_TamperTypeDef;
00075 /**
00076   * @}
00077   */
00078
00079
00080 /** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
00081   * @{
00082   */
00083 typedef struct
00084 {
00085   uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
00086                                              This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
00087
00088   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00089                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
00090 } RTC_InternalTamperTypeDef;
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00101   * @{
00102   */
00103
00104 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
00105   * @{
00106   */
00107 #define RTC_TIMESTAMPEDGE_RISING        0x00000000U
00108 #define RTC_TIMESTAMPEDGE_FALLING       RTC_CR_TSEDGE
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
00114   * @{
00115   */
00116 #define RTC_TIMESTAMPPIN_DEFAULT            0x00000000U
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
00122   * @{
00123   */
00124 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000U
00125 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
00126 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
00127 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
00128 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
00129 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
00135   * @{
00136   */
00137 #define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000U              /*!< If RTCCLK = 32768 Hz, Smooth calibration
00138                                                                      period is 32s,  else 2exp20 RTCCLK pulses */
00139 #define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16          /*!< If RTCCLK = 32768 Hz, Smooth calibration
00140                                                                      period is 16s, else 2exp19 RTCCLK pulses */
00141 #define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8           /*!< If RTCCLK = 32768 Hz, Smooth calibration
00142                                                                      period is 8s, else 2exp18 RTCCLK pulses */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
00148   * @{
00149   */
00150 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP         /*!< The number of RTCCLK pulses added
00151                                                                      during a X -second window = Y - CALM[8:0]
00152                                                                      with Y = 512, 256, 128 when X = 32, 16, 8 */
00153 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000U           /*!< The number of RTCCLK pulses subbstited
00154                                                                      during a 32-second window = CALM[8:0] */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
00161   * @{
00162   */
00163 #define RTC_CALIBOUTPUT_512HZ            0x00000000U
00164 #define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
00165
00166 /**
00167   * @}
00168   */
00169
00170
00171 /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
00172   * @{
00173   */
00174 #define RTC_SHIFTADD1S_RESET      0x00000000U
00175 #define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup RTCEx_Tamper_Pins  RTCEx Tamper Pins Definition
00181   * @{
00182   */
00183 #define RTC_TAMPER_1                        TAMP_CR1_TAMP1E
00184 #define RTC_TAMPER_2                        TAMP_CR1_TAMP2E
00185 #if (RTC_TAMP_NB == 3)
00186 #define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
00187 #define RTC_TAMPER_ALL                      (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )
00188 #elif (RTC_TAMP_NB == 8)
00189 #define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
00190 #define RTC_TAMPER_4                        TAMP_CR1_TAMP4E
00191 #define RTC_TAMPER_5                        TAMP_CR1_TAMP5E
00192 #define RTC_TAMPER_6                        TAMP_CR1_TAMP6E
00193 #define RTC_TAMPER_7                        TAMP_CR1_TAMP7E
00194 #define RTC_TAMPER_8                        TAMP_CR1_TAMP8E
00195 #define RTC_TAMPER_ALL                      (RTC_TAMPER_1 | RTC_TAMPER_2 |\
00196                                              RTC_TAMPER_3 | RTC_TAMPER_4 |\
00197                                              RTC_TAMPER_5 | RTC_TAMPER_6 |\
00198                                              RTC_TAMPER_7 | RTC_TAMPER_8 )
00199 #else
00200 #define RTC_TAMPER_ALL                      (RTC_TAMPER_1 | RTC_TAMPER_2)
00201 #endif /* RTC_TAMP_NB */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup RTCEx_Internal_Tamper_Pins  RTCEx Internal Tamper Pins Definition
00207   * @{
00208   */
00209 #if defined  (RTC_TAMP_INT_1_SUPPORT)
00210 #define RTC_INT_TAMPER_1                    TAMP_CR1_ITAMP1E
00211 #else
00212 #define RTC_INT_TAMPER_1                    0U
00213 #endif /* RTC_TAMP_INT_1_SUPPORT */
00214 #if defined (RTC_TAMP_INT_2_SUPPORT)
00215 #define RTC_INT_TAMPER_2                    TAMP_CR1_ITAMP2E
00216 #else
00217 #define RTC_INT_TAMPER_2                    0U
00218 #endif /* RTC_TAMP_INT_2_SUPPORT */
00219 #define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E
00220 #define RTC_INT_TAMPER_4                    TAMP_CR1_ITAMP4E
00221 #define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E
00222 #if defined (RTC_TAMP_INT_6_SUPPORT)
00223 #define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E
00224 #else
00225 #define RTC_INT_TAMPER_6                    0U
00226 #endif /* RTC_TAMP_INT_6_SUPPORT */
00227 #if defined (RTC_TAMP_INT_7_SUPPORT)
00228 #define RTC_INT_TAMPER_7                    TAMP_CR1_ITAMP7E
00229 #else
00230 #define RTC_INT_TAMPER_7                    0U
00231 #endif /* RTC_TAMP_INT_7_SUPPORT */
00232 #if defined (RTC_TAMP_INT_8_SUPPORT)
00233 #define RTC_INT_TAMPER_8                    TAMP_CR1_ITAMP8E
00234 #else
00235 #define RTC_INT_TAMPER_8                    0U
00236 #endif /* RTC_TAMP_INT_8_SUPPORT */
00237
00238 #define RTC_INT_TAMPER_ALL              ( RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
00239                                           RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
00240                                           RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
00241                                           RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 )
00242 /**
00243   * @}
00244  */
00245
00246 /** @defgroup RTCEx_Tamper_Trigger  RTCEx Tamper Trigger
00247   * @{
00248   */
00249 #define RTC_TAMPERTRIGGER_RISINGEDGE        0x00U  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
00250 #define RTC_TAMPERTRIGGER_FALLINGEDGE       0x01U  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
00251 #define RTC_TAMPERTRIGGER_LOWLEVEL          0x02U  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
00252 #define RTC_TAMPERTRIGGER_HIGHLEVEL         0x03U  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup RTCEx_Tamper_MaskFlag  RTCEx Tamper MaskFlag
00258   * @{
00259   */
00260 #define RTC_TAMPERMASK_FLAG_DISABLE         0x00U
00261 #define RTC_TAMPERMASK_FLAG_ENABLE          0x01U
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup RTCEx_Tamper_EraseBackUp  RTCEx Tamper EraseBackUp
00267   * @{
00268   */
00269 #define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00U
00270 #define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01U
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup RTCEx_Tamper_Filter  RTCEx Tamper Filter
00276   * @{
00277   */
00278 #define RTC_TAMPERFILTER_DISABLE           0x00000000U             /*!< Tamper filter is disabled */
00279 #define RTC_TAMPERFILTER_2SAMPLE           TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2
00280                                                                          consecutive samples at the active level */
00281 #define RTC_TAMPERFILTER_4SAMPLE           TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4
00282                                                                          consecutive samples at the active level */
00283 #define RTC_TAMPERFILTER_8SAMPLE           TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8
00284                                                                          consecutive samples at the active level */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup RTCEx_Tamper_Sampling_Frequencies  RTCEx Tamper Sampling Frequencies
00290   * @{
00291   */
00292 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled
00293                                                                                                       with a frequency =  RTCCLK / 32768 */
00294 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
00295                                                                                                       with a frequency =  RTCCLK / 16384 */
00296 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled
00297                                                                                                       with a frequency =  RTCCLK / 8192  */
00298 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
00299                                                                                                       with a frequency =  RTCCLK / 4096  */
00300 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled
00301                                                                                                       with a frequency =  RTCCLK / 2048  */
00302 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00303                                                                                                       with a frequency =  RTCCLK / 1024  */
00304 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00305                                                                                                       with a frequency =  RTCCLK / 512   */
00306 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
00307                                                  TAMP_FLTCR_TAMPFREQ_2)                         /*!< Each of the tamper inputs are sampled
00308 with a frequency =  RTCCLK / 256   */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration  RTCEx Tamper Pin Precharge Duration
00314   * @{
00315   */
00316 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U                                       /*!< Tamper pins are pre-charged before
00317                                                                                                         sampling during 1 RTCCLK cycle  */
00318 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0                             /*!< Tamper pins are pre-charged before
00319                                                                                                         sampling during 2 RTCCLK cycles */
00320 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1                             /*!< Tamper pins are pre-charged before
00321                                                                                                         sampling during 4 RTCCLK cycles */
00322 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)   /*!< Tamper pins are pre-charged before
00323                                                                                                         sampling during 8 RTCCLK cycles */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RTCEx_Tamper_Pull_UP  RTCEx Tamper Pull UP
00329   * @{
00330   */
00331 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000U           /*!< Tamper pins are pre-charged before sampling */
00332 #define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS  /*!< Tamper pins pre-charge is disabled          */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection
00338   * @{
00339   */
00340 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000U    /*!< TimeStamp on Tamper Detection event is not saved */
00341 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS  /*!< TimeStamp on Tamper Detection event saved        */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup RTCEx_Internal_Tamper_Interrupt  RTCEx Internal Tamper Interrupt
00347   * @{
00348   */
00349 #define RTC_IT_TAMP_1                      TAMP_IER_TAMP1IE     /*!< Tamper 1 Interrupt */
00350 #define RTC_IT_TAMP_2                      TAMP_IER_TAMP2IE     /*!< Tamper 2 Interrupt */
00351 #if (RTC_TAMP_NB == 3)
00352 #define RTC_IT_TAMP_3                      TAMP_IER_TAMP3IE     /*!< Tamper 3 Interrupt */
00353 #define RTC_IT_TAMP_ALL                   (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )
00354 #elif (RTC_TAMP_NB == 8)
00355 #define RTC_IT_TAMP_3                      TAMP_IER_TAMP3IE     /*!< Tamper 3 Interrupt */
00356 #define RTC_IT_TAMP_4                      TAMP_IER_TAMP4IE     /*!< Tamper 4 Interrupt */
00357 #define RTC_IT_TAMP_5                      TAMP_IER_TAMP5IE     /*!< Tamper 5 Interrupt */
00358 #define RTC_IT_TAMP_6                      TAMP_IER_TAMP6IE     /*!< Tamper 6 Interrupt */
00359 #define RTC_IT_TAMP_7                      TAMP_IER_TAMP7IE     /*!< Tamper 7 Interrupt */
00360 #define RTC_IT_TAMP_8                      TAMP_IER_TAMP8IE     /*!< Tamper 8 Interrupt */
00361 #define RTC_IT_TAMP_ALL                   (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\
00362                                            RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\
00363                                            RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\
00364                                            RTC_IT_TAMP_7 | RTC_IT_TAMP_8 )
00365 #else
00366 #define RTC_IT_TAMP_ALL                   (RTC_IT_TAMP_1 | RTC_IT_TAMP_2)
00367 #endif /* RTC_TAMP_NB */
00368
00369 #if defined (RTC_TAMP_INT_1_SUPPORT)
00370 #define RTC_IT_INT_TAMP_1                   TAMP_IER_ITAMP1IE    /*!< Tamper 1 internal Interrupt */
00371 #else
00372 #define RTC_IT_INT_TAMP_1                   0U
00373 #endif /* RTC_TAMP_INT_1_SUPPORT */
00374 #if defined (RTC_TAMP_INT_2_SUPPORT)
00375 #define RTC_IT_INT_TAMP_2                   TAMP_IER_ITAMP2IE    /*!< Tamper 2 internal Interrupt */
00376 #else
00377 #define RTC_IT_INT_TAMP_2                   0U
00378 #endif /* RTC_TAMP_INT_2_SUPPORT */
00379 #define RTC_IT_INT_TAMP_3                   TAMP_IER_ITAMP3IE    /*!< Tamper 3 internal Interrupt */
00380 #define RTC_IT_INT_TAMP_4                   TAMP_IER_ITAMP4IE    /*!< Tamper 4 internal Interrupt */
00381 #define RTC_IT_INT_TAMP_5                   TAMP_IER_ITAMP5IE    /*!< Tamper 5 internal Interrupt */
00382 #if defined (RTC_TAMP_INT_6_SUPPORT)
00383 #define RTC_IT_INT_TAMP_6                   TAMP_IER_ITAMP6IE    /*!< Tamper 6 internal Interrupt */
00384 #else
00385 #define RTC_IT_INT_TAMP_6                   0U
00386 #endif /* RTC_TAMP_INT_6_SUPPORT */
00387 #if defined (RTC_TAMP_INT_7_SUPPORT)
00388 #define RTC_IT_INT_TAMP_7                   TAMP_IER_ITAMP7IE    /*!< Tamper 7 internal Interrupt */
00389 #else
00390 #define RTC_IT_INT_TAMP_7                   0U
00391 #endif /* RTC_TAMP_INT_7_SUPPORT */
00392 #if defined (RTC_TAMP_INT_8_SUPPORT)
00393 #define RTC_IT_INT_TAMP_8                   TAMP_IER_ITAMP8IE    /*!< Tamper 8 internal Interrupt */
00394 #else
00395 #define RTC_IT_INT_TAMP_8                   0U
00396 #endif /* RTC_TAMP_INT_8_SUPPORT */
00397
00398 #define RTC_IT_INT_TAMP_ALL                 (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
00399                                              RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\
00400                                              RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\
00401                                              RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 )
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup RTCEx_Flags  RTCEx Flags
00407   * @{
00408   */
00409
00410 #define RTC_FLAG_TAMP_1                     TAMP_SR_TAMP1F
00411 #define RTC_FLAG_TAMP_2                     TAMP_SR_TAMP2F
00412 #if (RTC_TAMP_NB == 3)
00413 #define RTC_FLAG_TAMP_3                     TAMP_SR_TAMP3F
00414 #define RTC_FLAG_TAMP_ALL                   (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)
00415 #elif (RTC_TAMP_NB == 8)
00416 #define RTC_FLAG_TAMP_3                     TAMP_SR_TAMP3F
00417 #define RTC_FLAG_TAMP_4                     TAMP_SR_TAMP4F
00418 #define RTC_FLAG_TAMP_5                     TAMP_SR_TAMP5F
00419 #define RTC_FLAG_TAMP_6                     TAMP_SR_TAMP6F
00420 #define RTC_FLAG_TAMP_7                     TAMP_SR_TAMP7F
00421 #define RTC_FLAG_TAMP_8                     TAMP_SR_TAMP8F
00422 #define RTC_FLAG_TAMP_ALL                   (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
00423                                              RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 |\
00424                                              RTC_FLAG_TAMP_6 | RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
00425
00426 #else
00427 #define RTC_FLAG_TAMP_ALL                   (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2)
00428 #endif /* RTC_TAMP_NB */
00429
00430 #if defined (RTC_TAMP_INT_1_SUPPORT)
00431 #define RTC_FLAG_INT_TAMP_1                 TAMP_SR_ITAMP1F      /*!< Tamper 1 Interrupt flag */
00432 #else
00433 #define RTC_FLAG_INT_TAMP_1                 0U
00434 #endif /* RTC_TAMP_INT_1_SUPPORT */
00435 #if defined (RTC_TAMP_INT_2_SUPPORT)
00436 #define RTC_FLAG_INT_TAMP_2                 TAMP_SR_ITAMP2F      /*!< Tamper 2 Interrupt flag */
00437 #else
00438 #define RTC_FLAG_INT_TAMP_2                 0U
00439 #endif /* RTC_TAMP_INT_2_SUPPORT */
00440 #define RTC_FLAG_INT_TAMP_3                 TAMP_SR_ITAMP3F      /*!< Tamper 3 Interrupt flag */
00441 #define RTC_FLAG_INT_TAMP_4                 TAMP_SR_ITAMP4F      /*!< Tamper 4 Interrupt flag */
00442 #define RTC_FLAG_INT_TAMP_5                 TAMP_SR_ITAMP5F      /*!< Tamper 5 Interrupt flag */
00443 #if defined (RTC_TAMP_INT_6_SUPPORT)
00444 #define RTC_FLAG_INT_TAMP_6                 TAMP_SR_ITAMP6F      /*!< Tamper 6 Interrupt flag */
00445 #else
00446 #define RTC_FLAG_INT_TAMP_6                 0U
00447 #endif /* RTC_TAMP_INT_6_SUPPORT */
00448 #if defined (RTC_TAMP_INT_7_SUPPORT)
00449 #define RTC_FLAG_INT_TAMP_7                 TAMP_SR_ITAMP7F      /*!< Tamper 7 Interrupt flag */
00450 #else
00451 #define RTC_FLAG_INT_TAMP_7                 0U
00452 #endif /* RTC_TAMP_INT_7_SUPPORT */
00453 #if defined (RTC_TAMP_INT_8_SUPPORT)
00454 #define RTC_FLAG_INT_TAMP_8                 TAMP_SR_ITAMP8F      /*!< Tamper 8 Interrupt flag */
00455 #else
00456 #define RTC_FLAG_INT_TAMP_8                 0U
00457 #endif /* RTC_TAMP_INT_8_SUPPORT */
00458 #define RTC_FLAG_INT_TAMP_ALL               (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\
00459                                              RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\
00460                                              RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_6 |\
00461                                              RTC_FLAG_INT_TAMP_7 | RTC_FLAG_INT_TAMP_8)
00462 /**
00463   * @}
00464   */
00465
00466
00467 /** @defgroup RTCEx_Backup_Registers  RTCEx Backup Registers Definition
00468   * @{
00469   */
00470 #define RTC_BKP_NUMBER                    RTC_BACKUP_NB
00471 #if (RTC_BACKUP_NB == 5)
00472 #define RTC_BKP_DR0                       0x00000000U
00473 #define RTC_BKP_DR1                       0x00000001U
00474 #define RTC_BKP_DR2                       0x00000002U
00475 #define RTC_BKP_DR3                       0x00000003U
00476 #define RTC_BKP_DR4                       0x00000004U
00477 #elif  (RTC_BACKUP_NB == 16)
00478 #define RTC_BKP_DR0                       0x00U
00479 #define RTC_BKP_DR1                       0x01U
00480 #define RTC_BKP_DR2                       0x02U
00481 #define RTC_BKP_DR3                       0x03U
00482 #define RTC_BKP_DR4                       0x04U
00483 #define RTC_BKP_DR5                       0x05U
00484 #define RTC_BKP_DR6                       0x06U
00485 #define RTC_BKP_DR7                       0x07U
00486 #define RTC_BKP_DR8                       0x08U
00487 #define RTC_BKP_DR9                       0x09U
00488 #define RTC_BKP_DR10                      0x0AU
00489 #define RTC_BKP_DR11                      0x0BU
00490 #define RTC_BKP_DR12                      0x0CU
00491 #define RTC_BKP_DR13                      0x0DU
00492 #define RTC_BKP_DR14                      0x0EU
00493 #define RTC_BKP_DR15                      0x0FU
00494 #elif  (RTC_BACKUP_NB == 32)
00495 #define RTC_BKP_DR0                       0x00U
00496 #define RTC_BKP_DR1                       0x01U
00497 #define RTC_BKP_DR2                       0x02U
00498 #define RTC_BKP_DR3                       0x03U
00499 #define RTC_BKP_DR4                       0x04U
00500 #define RTC_BKP_DR5                       0x05U
00501 #define RTC_BKP_DR6                       0x06U
00502 #define RTC_BKP_DR7                       0x07U
00503 #define RTC_BKP_DR8                       0x08U
00504 #define RTC_BKP_DR9                       0x09U
00505 #define RTC_BKP_DR10                      0x0AU
00506 #define RTC_BKP_DR11                      0x0BU
00507 #define RTC_BKP_DR12                      0x0CU
00508 #define RTC_BKP_DR13                      0x0DU
00509 #define RTC_BKP_DR14                      0x0EU
00510 #define RTC_BKP_DR15                      0x0FU
00511 #define RTC_BKP_DR16                      0x10U
00512 #define RTC_BKP_DR17                      0x11U
00513 #define RTC_BKP_DR18                      0x12U
00514 #define RTC_BKP_DR19                      0x13U
00515 #define RTC_BKP_DR20                      0x14U
00516 #define RTC_BKP_DR21                      0x15U
00517 #define RTC_BKP_DR22                      0x16U
00518 #define RTC_BKP_DR23                      0x17U
00519 #define RTC_BKP_DR24                      0x18U
00520 #define RTC_BKP_DR25                      0x19U
00521 #define RTC_BKP_DR26                      0x1AU
00522 #define RTC_BKP_DR27                      0x1BU
00523 #define RTC_BKP_DR28                      0x1CU
00524 #define RTC_BKP_DR29                      0x1DU
00525 #define RTC_BKP_DR30                      0x1EU
00526 #define RTC_BKP_DR31                      0x1FU
00527 #else
00528 #error "no RTC Backup Registers Definition"
00529 #endif /* RTC_BKP_NUMBER */
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /* Exported macros -----------------------------------------------------------*/
00539 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00540   * @{
00541   */
00542
00543 /** @brief  Clear the specified RTC pending flag.
00544   * @param  __HANDLE__ specifies the RTC Handle.
00545   * @param  __FLAG__ specifies the flag to check.
00546   *          This parameter can be any combination of the following values:
00547   *            @arg @ref RTC_CLEAR_ITSF               Clear Internal Time-stamp flag
00548   *            @arg @ref RTC_CLEAR_TSOVF              Clear Time-stamp overflow flag
00549   *            @arg @ref RTC_CLEAR_TSF                Clear Time-stamp flag
00550   *            @arg @ref RTC_CLEAR_WUTF               Clear Wakeup timer flag
00551   *            @arg @ref RTC_CLEAR_ALRBF              Clear Alarm B flag
00552   *            @arg @ref RTC_CLEAR_ALRAF              Clear Alarm A flag
00553   * @retval None
00554   */
00555 #define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->SCR = (__FLAG__))
00556
00557
00558 /** @brief  Check whether the specified RTC flag is set or not.
00559   * @param  __HANDLE__ specifies the RTC Handle.
00560   * @param  __FLAG__ specifies the flag to check.
00561   *          This parameter can be any combination of the following values:
00562   *            @arg @ref RTC_FLAG_RECALPF             Recalibration pending Flag
00563   *            @arg @ref RTC_FLAG_INITF               Initialization flag
00564   *            @arg @ref RTC_FLAG_RSF                 Registers synchronization flag
00565   *            @arg @ref RTC_FLAG_INITS               Initialization status flag
00566   *            @arg @ref RTC_FLAG_SHPF                Shift operation pending flag
00567   *            @arg @ref RTC_FLAG_WUTWF               Wakeup timer write flag
00568   *            @arg @ref RTC_FLAG_ALRBWF              Alarm B write flag
00569   *            @arg @ref RTC_FLAG_ALRAWF              Alarm A write flag
00570   *            @arg @ref RTC_FLAG_ITSF                Internal Time-stamp flag
00571   *            @arg @ref RTC_FLAG_TSOVF               Time-stamp overflow flag
00572   *            @arg @ref RTC_FLAG_TSF                 Time-stamp flag
00573   *            @arg @ref RTC_FLAG_WUTF                Wakeup timer flag
00574   *            @arg @ref RTC_FLAG_ALRBF               Alarm B flag
00575   *            @arg @ref RTC_FLAG_ALRAF               Alarm A flag
00576   * @retval None
00577   */
00578 #define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)    (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
00579                                                      ((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
00580
00581 /* ---------------------------------WAKEUPTIMER---------------------------------*/
00582 /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
00583   * @{
00584   */
00585 /**
00586   * @brief  Enable the RTC WakeUp Timer peripheral.
00587   * @param  __HANDLE__ specifies the RTC handle.
00588   * @retval None
00589   */
00590 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00591
00592 /**
00593   * @brief  Disable the RTC WakeUp Timer peripheral.
00594   * @param  __HANDLE__ specifies the RTC handle.
00595   * @retval None
00596   */
00597 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00598
00599 /**
00600   * @brief  Enable the RTC WakeUpTimer interrupt.
00601   * @param  __HANDLE__ specifies the RTC handle.
00602   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
00603   *         This parameter can be:
00604   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00605   * @retval None
00606   */
00607 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00608
00609 /**
00610   * @brief  Disable the RTC WakeUpTimer interrupt.
00611   * @param  __HANDLE__ specifies the RTC handle.
00612   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
00613   *         This parameter can be:
00614   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00615   * @retval None
00616   */
00617 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00618
00619
00620 /**
00621   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00622   * @param  __HANDLE__ specifies the RTC handle.
00623   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
00624   *         This parameter can be:
00625   *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
00626   * @retval None
00627   */
00628 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->MISR)\
00629                                                                          & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)
00630 /**
00631   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00632   * @param  __HANDLE__ specifies the RTC handle.
00633   * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
00634   *         This parameter can be:
00635   *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
00636   * @retval None
00637   */
00638 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR)\
00639                                                                             & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
00640
00641 /**
00642   * @brief  Get the selected RTC WakeUpTimers flag status.
00643   * @param  __HANDLE__ specifies the RTC handle.
00644   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
00645   *          This parameter can be:
00646   *             @arg @ref RTC_FLAG_WUTF
00647   *             @arg @ref RTC_FLAG_WUTWF
00648   * @retval None
00649   */
00650 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00651
00652 /**
00653   * @brief  Clear the RTC Wake Up timers pending flags.
00654   * @param  __HANDLE__ specifies the RTC handle.
00655   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
00656   *         This parameter can be:
00657   *            @arg @ref RTC_FLAG_WUTF
00658   * @retval None
00659   */
00660 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
00661
00662 /* WAKE-UP TIMER EXTI */
00663 /* ------------------ */
00664 /**
00665   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00666   * @retval None
00667   */
00668 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00669
00670 /**
00671   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00672   * @retval None
00673   */
00674 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00675
00676 /**
00677   * @brief  set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
00678   * @retval None
00679   */
00680 #define __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT()       (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00681
00682 /**
00683   * @brief  set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
00684   * @retval None
00685   */
00686 #define __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT()       (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00687
00688 /**
00689   * @brief  Clear the interrupt on the RTC WakeUp Timer associated Exti line.
00690   * @retval None
00691   */
00692 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT()         (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00693
00694 /**
00695   * @brief  Clear the interrupt on the RTC WakeUp Timer associated Exti line.
00696   * @retval None
00697   */
00698 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()           (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00699
00700 /**
00701   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00702   * @retval None.
00703   */
00704 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00705
00706 /**
00707   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00708   * @retval None.
00709   */
00710 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00711
00712 /**
00713   * @}
00714   */
00715
00716 /* ---------------------------------TIMESTAMP---------------------------------*/
00717 /** @defgroup RTCEx_Timestamp RTC Timestamp
00718   * @{
00719   */
00720 /**
00721   * @brief  Enable the RTC TimeStamp peripheral.
00722   * @param  __HANDLE__ specifies the RTC handle.
00723   * @retval None
00724   */
00725 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00726
00727 /**
00728   * @brief  Disable the RTC TimeStamp peripheral.
00729   * @param  __HANDLE__ specifies the RTC handle.
00730   * @retval None
00731   */
00732 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00733
00734 /**
00735   * @brief  Enable the RTC TimeStamp interrupt.
00736   * @param  __HANDLE__ specifies the RTC handle.
00737   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
00738   *         This parameter can be:
00739   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00740   * @retval None
00741   */
00742 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00743
00744 /**
00745   * @brief  Disable the RTC TimeStamp interrupt.
00746   * @param  __HANDLE__ specifies the RTC handle.
00747   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
00748   *         This parameter can be:
00749   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00750   * @retval None
00751   */
00752 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00753
00754 /**
00755   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00756   * @param  __HANDLE__ specifies the RTC handle.
00757   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
00758   *         This parameter can be:
00759   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00760   * @retval None
00761   */
00762 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->MISR)\
00763                                                                         & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
00764 /**
00765   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00766   * @param  __HANDLE__ specifies the RTC handle.
00767   * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
00768   *         This parameter can be:
00769   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00770   * @retval None
00771   */
00772 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR)\
00773                                                                             & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
00774
00775 /**
00776   * @brief  Get the selected RTC TimeStamps flag status.
00777   * @param  __HANDLE__ specifies the RTC handle.
00778   * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
00779   *         This parameter can be:
00780   *            @arg @ref RTC_FLAG_TSF
00781   *            @arg @ref RTC_FLAG_TSOVF
00782   * @retval None
00783   */
00784 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
00785
00786 /**
00787   * @brief  Clear the RTC Time Stamps pending flags.
00788   * @param  __HANDLE__ specifies the RTC handle.
00789   * @param  __FLAG__ specifies the RTC TimeStamp Flag to clear.
00790   *          This parameter can be:
00791   *             @arg @ref RTC_FLAG_TSF
00792   *             @arg @ref RTC_FLAG_TSOVF
00793   * @retval None
00794   */
00795 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
00796
00797 /* TIMESTAMP TIMER EXTI */
00798 /* -------------------- */
00799
00800 /**
00801   * @brief  Enable interrupt on the RTC Timestamp associated Exti line.
00802   * @retval None
00803   */
00804 #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00805
00806 /**
00807   * @brief  Disable interrupt on the RTC Timestamp associated Exti line.
00808   * @retval None
00809   */
00810 #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
00811
00812 /**
00813   * @brief  set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
00814   * @retval None
00815   */
00816 #define __HAL_RTC_TIMESTAMP_EXTI_RISING_IT()       (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00817
00818 /**
00819   * @brief  set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
00820   * @retval None
00821   */
00822 #define __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT()       (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00823
00824 /**
00825   * @brief  Clear the interrupt on the RTC WakeUp Timer associated Exti line.
00826   * @retval None
00827   */
00828 #define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT()         (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
00829
00830 /**
00831   * @brief  Clear the interrupt on the RTC Timestamp associated Exti line.
00832   * @retval None
00833  */
00834 #define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG()      (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
00835
00836 /**
00837   * @brief  Enable event on the RTC Timestamp associated Exti line.
00838   * @retval None
00839   */
00840 #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00841
00842 /**
00843   * @brief  Disable event on the RTC Timestamp associated Exti line.
00844   * @retval None
00845   */
00846 #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
00847
00848 /**
00849   * @brief  Enable the RTC internal TimeStamp peripheral.
00850   * @param  __HANDLE__ specifies the RTC handle.
00851   * @retval None
00852   */
00853 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00854
00855 /**
00856   * @brief  Disable the RTC internal TimeStamp peripheral.
00857   * @param  __HANDLE__ specifies the RTC handle.
00858   * @retval None
00859   */
00860 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00861
00862 /**
00863   * @brief  Get the selected RTC Internal Time Stamps flag status.
00864   * @param  __HANDLE__ specifies the RTC handle.
00865   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
00866   *         This parameter can be:
00867   *            @arg @ref RTC_FLAG_ITSF
00868   * @retval None
00869   */
00870 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
00871
00872 /**
00873   * @brief  Clear the RTC Internal Time Stamps pending flags.
00874   * @param  __HANDLE__ specifies the RTC handle.
00875   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
00876   * This parameter can be:
00877   *             @arg @ref RTC_FLAG_ITSF
00878   * @retval None
00879   */
00880 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
00881
00882 /**
00883   * @brief  Enable the RTC TimeStamp on Tamper detection.
00884   * @param  __HANDLE__ specifies the RTC handle.
00885   * @retval None
00886   */
00887 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
00888
00889 /**
00890   * @brief  Disable the RTC TimeStamp on Tamper detection.
00891   * @param  __HANDLE__ specifies the RTC handle.
00892   * @retval None
00893   */
00894 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
00895
00896 /**
00897   * @brief  Enable the RTC Tamper detection output.
00898   * @param  __HANDLE__ specifies the RTC handle.
00899   * @retval None
00900   */
00901 #define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
00902
00903 /**
00904   * @brief  Disable the RTC Tamper detection output.
00905   * @param  __HANDLE__ specifies the RTC handle.
00906   * @retval None
00907   */
00908 #define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
00909
00910
00911 /**
00912   * @}
00913   */
00914
00915
00916 /* ------------------------------Calibration----------------------------------*/
00917 /** @defgroup RTCEx_Calibration RTC Calibration
00918   * @{
00919   */
00920
00921 /**
00922   * @brief  Enable the RTC calibration output.
00923   * @param  __HANDLE__ specifies the RTC handle.
00924   * @retval None
00925   */
00926 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00927
00928 /**
00929   * @brief  Disable the calibration output.
00930   * @param  __HANDLE__ specifies the RTC handle.
00931   * @retval None
00932   */
00933 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00934
00935
00936 /**
00937   * @brief  Enable the clock reference detection.
00938   * @param  __HANDLE__ specifies the RTC handle.
00939   * @retval None
00940   */
00941 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00942
00943 /**
00944   * @brief  Disable the clock reference detection.
00945   * @param  __HANDLE__ specifies the RTC handle.
00946   * @retval None
00947   */
00948 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00949
00950
00951 /**
00952   * @brief  Get the selected RTC shift operations flag status.
00953   * @param  __HANDLE__ specifies the RTC handle.
00954   * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
00955   *          This parameter can be:
00956   *             @arg @ref RTC_FLAG_SHPF
00957   * @retval None
00958   */
00959 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00960 /**
00961   * @}
00962   */
00963
00964
00965 /* ------------------------------Tamper----------------------------------*/
00966 /** @defgroup RTCEx_Tamper RTCEx tamper
00967   * @{
00968   */
00969 /**
00970   * @brief  Enable the TAMP Tamper input detection.
00971   * @param  __HANDLE__ specifies the RTC handle.
00972   * @param  __TAMPER__ specifies the RTC Tamper source to be enabled.
00973   *         This parameter can be any combination of the following values:
00974   *            @arg  RTC_TAMPER_ALL: All tampers
00975   *            @arg  RTC_TAMPER_1: Tamper1
00976   *            @arg  RTC_TAMPER_2: Tamper2
00977   * @retval None
00978   */
00979 #define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__)            (TAMP->CR1 |= (__TAMPER__))
00980
00981 /**
00982   * @brief  Disable the TAMP Tamper input detection.
00983   * @param  __HANDLE__ specifies the RTC handle.
00984   * @param  __TAMPER__ specifies the RTC Tamper sources to be enabled.
00985   *         This parameter can be any combination of the following values:
00986   *            @arg  RTC_TAMPER_ALL: All tampers
00987   *            @arg  RTC_TAMPER_1: Tamper1
00988   *            @arg  RTC_TAMPER_2: Tamper2
00989   */
00990 #define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__)           (TAMP->CR1 &= ~(__TAMPER__))
00991
00992
00993 /**************************************************************************************************/
00994 /**
00995   * @brief  Enable the TAMP Tamper interrupt.
00996   * @param  __HANDLE__ specifies the RTC handle.
00997   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
00998   *          This parameter can be any combination of the following values:
00999   *             @arg  RTC_IT_TAMP_ALL: All tampers interrupts
01000   *             @arg  RTC_IT_TAMP_1: Tamper1 interrupt
01001   *             @arg  RTC_IT_TAMP_2: Tamper2 interrupt
01002   * @retval None
01003   */
01004 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)      (TAMP->IER |= (__INTERRUPT__))
01005
01006
01007 /**
01008   * @brief  Disable the TAMP Tamper interrupt.
01009   * @param  __HANDLE__ specifies the RTC handle.
01010   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
01011   *         This parameter can be any combination of the following values:
01012   *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
01013   *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
01014   *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
01015   * @retval None
01016   */
01017 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)     (TAMP->IER &= ~(__INTERRUPT__))
01018
01019
01020 /**************************************************************************************************/
01021 /**
01022   * @brief  Check whether the specified TAMP Tamper interrupt has occurred or not.
01023   * @param  __HANDLE__ specifies the RTC handle.
01024   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
01025   *         This parameter can be:
01026   *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
01027   *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
01028   *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
01029   * @retval None
01030   */
01031 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)         ((((TAMP->MISR)\
01032                                                                       & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
01033
01034
01035 /**
01036   * @brief  Check whether the specified TAMP Tamper interrupt has been enabled or not.
01037   * @param  __HANDLE__ specifies the RTC handle.
01038   * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
01039   *         This parameter can be:
01040   *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
01041   *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
01042   *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
01043   * @retval None
01044   */
01045 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((TAMP->IER)\
01046                                                                       & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
01047
01048
01049 /**
01050   * @brief  Get the selected TAMP Tampers flag status.
01051   * @param  __HANDLE__ specifies the RTC handle.
01052   * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
01053   *          This parameter can be:
01054   *             @arg RTC_FLAG_TAMP_ALL: All tampers flag
01055   *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
01056   *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
01057   * @retval None
01058   */
01059 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)            (((TAMP->SR) & (__FLAG__)) != 0UL)
01060
01061
01062 /**
01063   * @brief  Clear the TAMP Tampers pending flags.
01064   * @param  __HANDLE__ specifies the RTC handle.
01065   * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
01066   *          This parameter can be:
01067   *             @arg RTC_FLAG_TAMP_ALL: All tampers flag
01068   *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
01069   *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
01070   * @retval None
01071   */
01072 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((TAMP->SCR) = (__FLAG__))
01073
01074
01075 /**
01076   * @brief  Enable interrupt on the RTC Tamper associated Exti line.
01077   * @retval None
01078   */
01079 #define __HAL_RTC_TAMPER_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
01080
01081
01082 /**
01083   * @brief  Disable interrupt on the RTC Tamper associated Exti line.
01084   * @retval None
01085   */
01086 #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
01087
01088
01089 /**
01090   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
01091   * @retval None
01092   */
01093 #define __HAL_RTC_TAMPER_EXTI_RISING_IT()        (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
01094
01095
01096 /**
01097   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
01098   * @retval None
01099   */
01100 #define __HAL_RTC_TAMPER_EXTI_FALLING_IT()       (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
01101
01102
01103 /**
01104   * @brief  Clear the interrupt on the RTC WakeUp Timer associated Exti line.
01105   * @retval None
01106   */
01107 #define __HAL_RTC_TAMPER_EXTI_CLEAR_IT()         (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)
01108
01109
01110 /**
01111   * @brief  Enable event on the RTC Tamper associated Exti line.
01112   * @retval None
01113   */
01114 #define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT()     (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
01115
01116
01117 /**
01118   * @brief  Disable event on the RTC Tamper associated Exti line.
01119   * @retval None
01120   */
01121 #define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT()    (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
01122
01123
01124 /**
01125   * @}
01126   */
01127
01128 /**
01129   * @}
01130   */
01131
01132 /* Exported functions --------------------------------------------------------*/
01133 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
01134   * @{
01135   */
01136
01137 /* RTC TimeStamp functions *****************************************/
01138 /** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
01139   * @{
01140   */
01141
01142 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01143 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01144 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
01145 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01146 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01147 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
01148                                          RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
01149 void              HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
01150 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01151 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
01152 /**
01153   * @}
01154   */
01155
01156
01157 /* RTC Wake-up functions ******************************************************/
01158 /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
01159   * @{
01160   */
01161
01162 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01163 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01164 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
01165 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
01166 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
01167 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
01168 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01169 /**
01170   * @}
01171   */
01172
01173 /* Extended Control functions ************************************************/
01174 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
01175   * @{
01176   */
01177
01178 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
01179                                            uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
01180 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
01181 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
01182 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
01183 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
01184 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
01185 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
01186 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
01187 /**
01188   * @}
01189   */
01190
01191 /* Extended RTC features functions *******************************************/
01192 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01193   * @{
01194   */
01195
01196 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
01197 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01198 /**
01199   * @}
01200   */
01201
01202 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
01203   * @{
01204   */
01205 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
01206 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
01207 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
01208 HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
01209 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
01210 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
01211 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
01212 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
01213 void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
01214 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
01215 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
01216 #if (RTC_TAMP_NB == 3)
01217 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
01218 #endif /* RTC_TAMP_NB */
01219
01220 #ifdef RTC_TAMP_INT_1_SUPPORT
01221 void              HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
01222 #endif /* RTC_TAMP_INT_1_SUPPORT */
01223 #ifdef RTC_TAMP_INT_2_SUPPORT
01224 void              HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
01225 #endif /* RTC_TAMP_INT_2_SUPPORT */
01226 void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
01227 void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
01228 void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
01229 #ifdef RTC_TAMP_INT_6_SUPPORT
01230 void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
01231 #endif /* RTC_TAMP_INT_6_SUPPORT */
01232 #ifdef RTC_TAMP_INT_7_SUPPORT
01233 void              HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
01234 #endif /* RTC_TAMP_INT_7_SUPPORT */
01235 /**
01236   * @}
01237   */
01238
01239 /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
01240   * @{
01241   */
01242 void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
01243 uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
01244
01245 /**
01246   * @}
01247   */
01248
01249
01250 /**
01251   * @}
01252   */
01253
01254 /* Private types -------------------------------------------------------------*/
01255 /* Private variables ---------------------------------------------------------*/
01256 /* Private constants ---------------------------------------------------------*/
01257 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
01258   * @{
01259   */
01260 #define RTC_EXTI_LINE_ALARM_EVENT             EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
01261 #define RTC_EXTI_LINE_TIMESTAMP_EVENT         EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
01262 #define RTC_EXTI_LINE_TAMPER_EVENT            EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
01263 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
01264 /**
01265   * @}
01266   */
01267
01268 /* Private macros ------------------------------------------------------------*/
01269 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
01270   * @{
01271   */
01272
01273 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
01274   * @{
01275   */
01276 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01277                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01278
01279
01280 #define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01281
01282
01283
01284 #define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01285                                                        ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01286
01287 #define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)    (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
01288                                                       ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
01289
01290
01291 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
01292                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01293                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01294                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01295                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01296                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01297
01298 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
01299
01300 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01301                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01302                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01303
01304 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01305                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01306
01307 #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
01308
01309 #define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
01310                                        ((LPCAL) == RTC_LPCAL_RESET))
01311
01312 #define IS_RTC_TAMPER(__TAMPER__)                ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
01313                                                   (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
01314
01315 #define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
01316                                                   (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
01317
01318 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)       (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
01319                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
01320                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
01321                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
01322
01323 #define IS_RTC_TAMPER_ERASE_MODE(__MODE__)       (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
01324                                                   ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
01325
01326 #define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)  (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
01327                                                   ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
01328
01329 #define IS_RTC_TAMPER_FILTER(__FILTER__)         (((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
01330                                                   ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
01331                                                   ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
01332                                                   ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
01333
01334 #define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)    (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
01335                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
01336                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
01337                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
01338                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
01339                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
01340                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
01341                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
01342
01343 #define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)   (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
01344                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
01345                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
01346                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
01347
01348 #define IS_RTC_TAMPER_PULLUP_STATE(__STATE__)    (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
01349                                                   ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
01350
01351 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01352                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01353
01354 #define IS_RTC_BKP(__BKP__)   ((__BKP__) < RTC_BKP_NUMBER)
01355
01356 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01357                                  ((SEL) == RTC_SHIFTADD1S_SET))
01358
01359 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
01360
01361 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01362                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01363 /**
01364   * @}
01365   */
01366
01367 /**
01368   * @}
01369   */
01370
01371 /**
01372   * @}
01373   */
01374
01375 /**
01376   * @}
01377   */
01378
01379 #ifdef __cplusplus
01380 }
01381 #endif
01382
01383 #endif /* STM32G4xx_HAL_RTC_EX_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_sai.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @brief   SAI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + I/O operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                   ##### How to use this driver #####
00027   ==============================================================================
00028
00029   [..]
00030     The SAI HAL driver can be used as follows:
00031
00032     (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
00033     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00034         (##) Enable the SAI interface clock.
00035         (##) SAI pins configuration:
00036             (+++) Enable the clock for the SAI GPIOs.
00037             (+++) Configure these SAI pins as alternate function pull-up.
00038         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00039              and HAL_SAI_Receive_IT() APIs):
00040             (+++) Configure the SAI interrupt priority.
00041             (+++) Enable the NVIC SAI IRQ handle.
00042
00043         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00044              and HAL_SAI_Receive_DMA() APIs):
00045             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00046             (+++) Enable the DMAx interface clock.
00047             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00048             (+++) Configure the DMA Tx/Rx Stream.
00049             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00050             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00051                 DMA Tx/Rx Stream.
00052
00053     (#) The initialization can be done by two ways
00054         (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
00055         (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
00056
00057   [..]
00058     (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00059         will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
00060         inside the transmit and receive process.
00061   [..]
00062     (@) Make sure that SAI clock source is configured:
00063         (+@) SYSCLK or
00064         (+@) PLLQ output or
00065         (+@) HSI or
00066         (+@) External clock source which is configured after setting correctly
00067              the define constant EXTERNAL_CLOCK_VALUE in the stm32g4xx_hal_conf.h file.
00068
00069   [..]
00070     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00071         for the external slaves even if there is no data in the FIFO, However FS signal
00072         generation is conditioned by the presence of data in the FIFO.
00073
00074   [..]
00075     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00076         and FS signal for the external slaves.
00077
00078   [..]
00079     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00080         (+@) First bit Offset <= (SLOT size - Data size)
00081         (+@) Data size <= SLOT size
00082         (+@) Number of SLOT x SLOT size = Frame length
00083         (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00084
00085   [..]
00086     (@) PDM interface can be activated through HAL_SAI_Init function.
00087         Please note that PDM interface is only available for SAI1 sub-block A.
00088         PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
00089
00090   [..]
00091     Three operation modes are available within this driver :
00092
00093     *** Polling mode IO operation ***
00094     =================================
00095     [..]
00096       (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00097       (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00098
00099     *** Interrupt mode IO operation ***
00100     ===================================
00101     [..]
00102       (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
00103       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00104           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00105       (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
00106       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00107           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00108       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00109           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00110
00111     *** DMA mode IO operation ***
00112     =============================
00113     [..]
00114       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00115       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00116           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00117       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
00118       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00119           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00120       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00121           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00122       (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00123       (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00124       (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00125
00126     *** SAI HAL driver additional function list ***
00127     ===============================================
00128     [..]
00129       Below the list the others API available SAI HAL driver :
00130
00131       (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
00132       (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
00133       (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
00134       (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
00135       (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
00136       (+) HAL_SAI_Abort(): Abort the current transfer
00137
00138     *** SAI HAL driver macros list ***
00139     ==================================
00140     [..]
00141       Below the list of most used macros in SAI HAL driver :
00142
00143       (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
00144       (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
00145       (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
00146       (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
00147       (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
00148           enabled or disabled
00149       (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
00150
00151     *** Callback registration ***
00152     =============================
00153     [..]
00154     The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
00155     allows the user to configure dynamically the driver callbacks.
00156     Use functions HAL_SAI_RegisterCallback() to register a user callback.
00157
00158     [..]
00159     Function HAL_SAI_RegisterCallback() allows to register following callbacks:
00160       (+) RxCpltCallback     : SAI receive complete.
00161       (+) RxHalfCpltCallback : SAI receive half complete.
00162       (+) TxCpltCallback     : SAI transmit complete.
00163       (+) TxHalfCpltCallback : SAI transmit half complete.
00164       (+) ErrorCallback      : SAI error.
00165       (+) MspInitCallback    : SAI MspInit.
00166       (+) MspDeInitCallback  : SAI MspDeInit.
00167     [..]
00168     This function takes as parameters the HAL peripheral handle, the callback ID
00169     and a pointer to the user callback function.
00170
00171     [..]
00172     Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
00173     weak function.
00174     HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00175     and the callback ID.
00176     [..]
00177     This function allows to reset following callbacks:
00178       (+) RxCpltCallback     : SAI receive complete.
00179       (+) RxHalfCpltCallback : SAI receive half complete.
00180       (+) TxCpltCallback     : SAI transmit complete.
00181       (+) TxHalfCpltCallback : SAI transmit half complete.
00182       (+) ErrorCallback      : SAI error.
00183       (+) MspInitCallback    : SAI MspInit.
00184       (+) MspDeInitCallback  : SAI MspDeInit.
00185
00186     [..]
00187     By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
00188     all callbacks are reset to the corresponding legacy weak functions:
00189     examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
00190     Exception done for MspInit and MspDeInit callbacks that are respectively
00191     reset to the legacy weak functions in the HAL_SAI_Init
00192     and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
00193     If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
00194     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00195
00196     [..]
00197     Callbacks can be registered/unregistered in READY state only.
00198     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00199     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00200     during the Init/DeInit.
00201     In that case first register the MspInit/MspDeInit user callbacks
00202     using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
00203     or HAL_SAI_Init function.
00204
00205     [..]
00206     When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
00207     not defined, the callback registering feature is not available
00208     and weak callbacks are used.
00209
00210   @endverbatim
00211   */
00212
00213 /* Includes ------------------------------------------------------------------*/
00214 #include "stm32g4xx_hal.h"
00215
00216 /** @addtogroup STM32G4xx_HAL_Driver
00217   * @{
00218   */
00219
00220 /** @defgroup SAI SAI
00221   * @brief SAI HAL module driver
00222   * @{
00223   */
00224
00225 #ifdef HAL_SAI_MODULE_ENABLED
00226
00227 /* Private typedef -----------------------------------------------------------*/
00228 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00229   * @{
00230   */
00231 typedef enum
00232 {
00233   SAI_MODE_DMA,
00234   SAI_MODE_IT
00235 } SAI_ModeTypedef;
00236 /**
00237   * @}
00238   */
00239
00240 /* Private define ------------------------------------------------------------*/
00241 /** @defgroup SAI_Private_Constants  SAI Private Constants
00242   * @{
00243   */
00244 #define SAI_DEFAULT_TIMEOUT      4U
00245 #define SAI_LONG_TIMEOUT         1000U
00246 #define SAI_SPDIF_FRAME_LENGTH   64U
00247 #define SAI_AC97_FRAME_LENGTH    256U
00248 /**
00249   * @}
00250   */
00251
00252 /* Private macro -------------------------------------------------------------*/
00253 /* Private variables ---------------------------------------------------------*/
00254 /* Private function prototypes -----------------------------------------------*/
00255 /** @defgroup SAI_Private_Functions  SAI Private Functions
00256   * @{
00257   */
00258 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00259 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
00260 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00261 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00262
00263 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00264 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00265 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00266 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00267 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00268 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00269 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00270
00271 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00272 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00273 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00274 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00275 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00276 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
00277 /**
00278   * @}
00279   */
00280
00281 /* Exported functions ---------------------------------------------------------*/
00282 /** @defgroup SAI_Exported_Functions SAI Exported Functions
00283   * @{
00284   */
00285
00286 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00287   * @brief    Initialization and Configuration functions
00288   *
00289 @verbatim
00290  ===============================================================================
00291              ##### Initialization and de-initialization functions #####
00292  ===============================================================================
00293   [..]  This subsection provides a set of functions allowing to initialize and
00294         de-initialize the SAIx peripheral:
00295
00296       (+) User must implement HAL_SAI_MspInit() function in which he configures
00297           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00298
00299       (+) Call the function HAL_SAI_Init() to configure the selected device with
00300           the selected configuration:
00301         (++) Mode (Master/slave TX/RX)
00302         (++) Protocol
00303         (++) Data Size
00304         (++) MCLK Output
00305         (++) Audio frequency
00306         (++) FIFO Threshold
00307         (++) Frame Config
00308         (++) Slot Config
00309         (++) PDM Config
00310
00311       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00312           of the selected SAI peripheral.
00313
00314 @endverbatim
00315   * @{
00316   */
00317
00318 /**
00319   * @brief  Initialize the structure FrameInit, SlotInit and the low part of
00320   *         Init according to the specified parameters and call the function
00321   *         HAL_SAI_Init to initialize the SAI block.
00322   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00323   *              the configuration information for SAI module.
00324   * @param  protocol one of the supported protocol @ref SAI_Protocol
00325   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
00326   *                   the configuration information for SAI module.
00327   * @param  nbslot Number of slot.
00328   * @retval HAL status
00329   */
00330 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00331 {
00332   HAL_StatusTypeDef status;
00333
00334   /* Check the parameters */
00335   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00336   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00337
00338   switch (protocol)
00339   {
00340     case SAI_I2S_STANDARD :
00341     case SAI_I2S_MSBJUSTIFIED :
00342     case SAI_I2S_LSBJUSTIFIED :
00343       status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00344       break;
00345     case SAI_PCM_LONG :
00346     case SAI_PCM_SHORT :
00347       status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00348       break;
00349     default :
00350       status = HAL_ERROR;
00351       break;
00352   }
00353
00354   if (status == HAL_OK)
00355   {
00356     status = HAL_SAI_Init(hsai);
00357   }
00358
00359   return status;
00360 }
00361
00362 /**
00363   * @brief  Initialize the SAI according to the specified parameters.
00364   *         in the SAI_InitTypeDef structure and initialize the associated handle.
00365   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00366   *              the configuration information for SAI module.
00367   * @retval HAL status
00368   */
00369 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00370 {
00371   uint32_t ckstr_bits;
00372   uint32_t syncen_bits;
00373
00374   /* Check the SAI handle allocation */
00375   if (hsai == NULL)
00376   {
00377     return HAL_ERROR;
00378   }
00379
00380   /* check the instance */
00381   assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
00382
00383   /* Check the SAI Block parameters */
00384   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00385   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00386   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00387   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00388   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00389   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00390   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00391   assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
00392   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00393   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00394   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00395   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00396   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00397   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00398   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00399   assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
00400
00401   /* Check the SAI Block Frame parameters */
00402   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00403   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00404   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00405   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00406   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00407
00408   /* Check the SAI Block Slot parameters */
00409   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00410   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00411   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00412   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00413
00414   /* Check the SAI PDM parameters */
00415   assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
00416   if (hsai->Init.PdmInit.Activation == ENABLE)
00417   {
00418     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
00419     assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
00420     /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */
00421     if ((hsai->Instance != SAI1_Block_A) ||
00422         (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
00423         (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
00424     {
00425       return HAL_ERROR;
00426     }
00427   }
00428
00429   if (hsai->State == HAL_SAI_STATE_RESET)
00430   {
00431     /* Allocate lock resource and initialize it */
00432     hsai->Lock = HAL_UNLOCKED;
00433
00434 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00435     /* Reset callback pointers to the weak predefined callbacks */
00436     hsai->RxCpltCallback     = HAL_SAI_RxCpltCallback;
00437     hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00438     hsai->TxCpltCallback     = HAL_SAI_TxCpltCallback;
00439     hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00440     hsai->ErrorCallback      = HAL_SAI_ErrorCallback;
00441
00442     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00443     if (hsai->MspInitCallback == NULL)
00444     {
00445       hsai->MspInitCallback = HAL_SAI_MspInit;
00446     }
00447     hsai->MspInitCallback(hsai);
00448 #else
00449     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00450     HAL_SAI_MspInit(hsai);
00451 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00452   }
00453
00454   /* Disable the selected SAI peripheral */
00455   if (SAI_Disable(hsai) != HAL_OK)
00456   {
00457     return HAL_ERROR;
00458   }
00459
00460   hsai->State = HAL_SAI_STATE_BUSY;
00461
00462   /* SAI Block Synchro Configuration -----------------------------------------*/
00463   /* This setting must be done with both audio block (A & B) disabled         */
00464   switch (hsai->Init.Synchro)
00465   {
00466     case SAI_ASYNCHRONOUS :
00467       syncen_bits = 0;
00468       break;
00469     case SAI_SYNCHRONOUS :
00470       syncen_bits = SAI_xCR1_SYNCEN_0;
00471       break;
00472     default :
00473       syncen_bits = 0;
00474       break;
00475   }
00476
00477   if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00478   {
00479     uint32_t freq = 0;
00480     uint32_t tmpval;
00481
00482     /* In this case, the MCKDIV value is calculated to get AudioFrequency */
00483     if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00484     {
00485       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00486     }
00487
00488     /* Configure Master Clock Divider using the following formula :
00489        - If NODIV = 1 :
00490          MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
00491        - If NODIV = 0 :
00492          MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
00493     if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
00494     {
00495       /* NODIV = 1 */
00496       uint32_t tmpframelength;
00497
00498       if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
00499       {
00500         /* For SPDIF protocol, frame length is set by hardware to 64 */
00501         tmpframelength = SAI_SPDIF_FRAME_LENGTH;
00502       }
00503       else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
00504       {
00505         /* For AC97 protocol, frame length is set by hardware to 256 */
00506         tmpframelength = SAI_AC97_FRAME_LENGTH;
00507       }
00508       else
00509       {
00510         /* For free protocol, frame length is set by user */
00511         tmpframelength = hsai->FrameInit.FrameLength;
00512       }
00513
00514       /* (freq x 10) to keep Significant digits */
00515       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
00516     }
00517     else
00518     {
00519       /* NODIV = 0 */
00520       uint32_t tmposr;
00521       tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
00522       /* (freq x 10) to keep Significant digits */
00523       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
00524     }
00525     hsai->Init.Mckdiv = tmpval / 10U;
00526
00527     /* Round result to the nearest integer */
00528     if ((tmpval % 10U) > 8U)
00529     {
00530       hsai->Init.Mckdiv += 1U;
00531     }
00532
00533     /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
00534     if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
00535     {
00536       hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
00537     }
00538   }
00539   /* Check the SAI Block master clock divider parameter */
00540   assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
00541
00542   /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
00543   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00544   {
00545     /* Transmit */
00546     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
00547   }
00548   else
00549   {
00550     /* Receive */
00551     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
00552   }
00553
00554   /* SAI Block Configuration -------------------------------------------------*/
00555   /* SAI CR1 Configuration */
00556   hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00557                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
00558                            SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00559                            SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR |     \
00560                            SAI_xCR1_MCKEN);
00561
00562   hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00563                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00564                           ckstr_bits | syncen_bits |                             \
00565                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00566                           hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00567                           hsai->Init.MckOverSampling | hsai->Init.MckOutput);
00568
00569   /* SAI CR2 Configuration */
00570   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00571   hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00572
00573   /* SAI Frame Configuration -----------------------------------------*/
00574   hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00575                              SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
00576   hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
00577                            hsai->FrameInit.FSOffset |
00578                            hsai->FrameInit.FSDefinition |
00579                            hsai->FrameInit.FSPolarity   |
00580                            ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
00581
00582   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00583   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00584   hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |  \
00585                               SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
00586
00587   hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
00588                            (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) <<  8);
00589
00590   /* SAI PDM Configuration ---------------------------------------------------*/
00591   if (hsai->Instance == SAI1_Block_A)
00592   {
00593     /* Disable PDM interface */
00594     SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
00595     if (hsai->Init.PdmInit.Activation == ENABLE)
00596     {
00597       /* Configure and enable PDM interface */
00598       SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable |
00599                      ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
00600       SAI1->PDMCR |= SAI_PDMCR_PDMEN;
00601     }
00602   }
00603
00604   /* Initialize the error code */
00605   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00606
00607   /* Initialize the SAI state */
00608   hsai->State = HAL_SAI_STATE_READY;
00609
00610   /* Release Lock */
00611   __HAL_UNLOCK(hsai);
00612
00613   return HAL_OK;
00614 }
00615
00616 /**
00617   * @brief  DeInitialize the SAI peripheral.
00618   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00619   *              the configuration information for SAI module.
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00623 {
00624   /* Check the SAI handle allocation */
00625   if (hsai == NULL)
00626   {
00627     return HAL_ERROR;
00628   }
00629
00630   hsai->State = HAL_SAI_STATE_BUSY;
00631
00632   /* Disabled All interrupt and clear all the flag */
00633   hsai->Instance->IMR = 0;
00634   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00635
00636   /* Disable the SAI */
00637   if (SAI_Disable(hsai) != HAL_OK)
00638   {
00639     /* Reset SAI state to ready */
00640     hsai->State = HAL_SAI_STATE_READY;
00641
00642     /* Release Lock */
00643     __HAL_UNLOCK(hsai);
00644
00645     return HAL_ERROR;
00646   }
00647
00648   /* Flush the fifo */
00649   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00650
00651   /* Disable SAI PDM interface */
00652   if (hsai->Instance == SAI1_Block_A)
00653   {
00654     /* Reset PDM delays */
00655     SAI1->PDMDLY = 0U;
00656
00657     /* Disable PDM interface */
00658     SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
00659   }
00660
00661   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00662 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00663   if (hsai->MspDeInitCallback == NULL)
00664   {
00665     hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00666   }
00667   hsai->MspDeInitCallback(hsai);
00668 #else
00669   HAL_SAI_MspDeInit(hsai);
00670 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00671
00672   /* Initialize the error code */
00673   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00674
00675   /* Initialize the SAI state */
00676   hsai->State = HAL_SAI_STATE_RESET;
00677
00678   /* Release Lock */
00679   __HAL_UNLOCK(hsai);
00680
00681   return HAL_OK;
00682 }
00683
00684 /**
00685   * @brief Initialize the SAI MSP.
00686   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00687   *              the configuration information for SAI module.
00688   * @retval None
00689   */
00690 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00691 {
00692   /* Prevent unused argument(s) compilation warning */
00693   UNUSED(hsai);
00694
00695   /* NOTE : This function should not be modified, when the callback is needed,
00696             the HAL_SAI_MspInit could be implemented in the user file
00697    */
00698 }
00699
00700 /**
00701   * @brief DeInitialize the SAI MSP.
00702   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00703   *              the configuration information for SAI module.
00704   * @retval None
00705   */
00706 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00707 {
00708   /* Prevent unused argument(s) compilation warning */
00709   UNUSED(hsai);
00710
00711   /* NOTE : This function should not be modified, when the callback is needed,
00712             the HAL_SAI_MspDeInit could be implemented in the user file
00713    */
00714 }
00715
00716 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00717 /**
00718   * @brief  Register a user SAI callback
00719   *         to be used instead of the weak predefined callback.
00720   * @param  hsai SAI handle.
00721   * @param  CallbackID ID of the callback to be registered.
00722   *         This parameter can be one of the following values:
00723   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00724   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00725   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00726   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00727   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00728   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00729   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00730   * @param  pCallback pointer to the callback function.
00731   * @retval HAL status.
00732   */
00733 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00734                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00735                                            pSAI_CallbackTypeDef      pCallback)
00736 {
00737   HAL_StatusTypeDef status = HAL_OK;
00738
00739   if (pCallback == NULL)
00740   {
00741     /* update the error code */
00742     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00743     /* update return status */
00744     status = HAL_ERROR;
00745   }
00746   else
00747   {
00748     if (HAL_SAI_STATE_READY == hsai->State)
00749     {
00750       switch (CallbackID)
00751       {
00752         case HAL_SAI_RX_COMPLETE_CB_ID :
00753           hsai->RxCpltCallback = pCallback;
00754           break;
00755         case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00756           hsai->RxHalfCpltCallback = pCallback;
00757           break;
00758         case HAL_SAI_TX_COMPLETE_CB_ID :
00759           hsai->TxCpltCallback = pCallback;
00760           break;
00761         case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00762           hsai->TxHalfCpltCallback = pCallback;
00763           break;
00764         case HAL_SAI_ERROR_CB_ID :
00765           hsai->ErrorCallback = pCallback;
00766           break;
00767         case HAL_SAI_MSPINIT_CB_ID :
00768           hsai->MspInitCallback = pCallback;
00769           break;
00770         case HAL_SAI_MSPDEINIT_CB_ID :
00771           hsai->MspDeInitCallback = pCallback;
00772           break;
00773         default :
00774           /* update the error code */
00775           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00776           /* update return status */
00777           status = HAL_ERROR;
00778           break;
00779       }
00780     }
00781     else if (HAL_SAI_STATE_RESET == hsai->State)
00782     {
00783       switch (CallbackID)
00784       {
00785         case HAL_SAI_MSPINIT_CB_ID :
00786           hsai->MspInitCallback = pCallback;
00787           break;
00788         case HAL_SAI_MSPDEINIT_CB_ID :
00789           hsai->MspDeInitCallback = pCallback;
00790           break;
00791         default :
00792           /* update the error code */
00793           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00794           /* update return status */
00795           status = HAL_ERROR;
00796           break;
00797       }
00798     }
00799     else
00800     {
00801       /* update the error code */
00802       hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00803       /* update return status */
00804       status = HAL_ERROR;
00805     }
00806   }
00807   return status;
00808 }
00809
00810 /**
00811   * @brief  Unregister a user SAI callback.
00812   *         SAI callback is redirected to the weak predefined callback.
00813   * @param  hsai SAI handle.
00814   * @param  CallbackID ID of the callback to be unregistered.
00815   *         This parameter can be one of the following values:
00816   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00817   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00818   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00819   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00820   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00821   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00822   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00823   * @retval HAL status.
00824   */
00825 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00826                                              HAL_SAI_CallbackIDTypeDef CallbackID)
00827 {
00828   HAL_StatusTypeDef status = HAL_OK;
00829
00830   if (HAL_SAI_STATE_READY == hsai->State)
00831   {
00832     switch (CallbackID)
00833     {
00834       case HAL_SAI_RX_COMPLETE_CB_ID :
00835         hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
00836         break;
00837       case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00838         hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00839         break;
00840       case HAL_SAI_TX_COMPLETE_CB_ID :
00841         hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
00842         break;
00843       case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00844         hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00845         break;
00846       case HAL_SAI_ERROR_CB_ID :
00847         hsai->ErrorCallback = HAL_SAI_ErrorCallback;
00848         break;
00849       case HAL_SAI_MSPINIT_CB_ID :
00850         hsai->MspInitCallback = HAL_SAI_MspInit;
00851         break;
00852       case HAL_SAI_MSPDEINIT_CB_ID :
00853         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00854         break;
00855       default :
00856         /* update the error code */
00857         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00858         /* update return status */
00859         status = HAL_ERROR;
00860         break;
00861     }
00862   }
00863   else if (HAL_SAI_STATE_RESET == hsai->State)
00864   {
00865     switch (CallbackID)
00866     {
00867       case HAL_SAI_MSPINIT_CB_ID :
00868         hsai->MspInitCallback = HAL_SAI_MspInit;
00869         break;
00870       case HAL_SAI_MSPDEINIT_CB_ID :
00871         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00872         break;
00873       default :
00874         /* update the error code */
00875         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00876         /* update return status */
00877         status = HAL_ERROR;
00878         break;
00879     }
00880   }
00881   else
00882   {
00883     /* update the error code */
00884     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00885     /* update return status */
00886     status = HAL_ERROR;
00887   }
00888   return status;
00889 }
00890 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00891
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00897   * @brief    Data transfers functions
00898   *
00899 @verbatim
00900   ==============================================================================
00901                       ##### IO operation functions #####
00902   ==============================================================================
00903   [..]
00904     This subsection provides a set of functions allowing to manage the SAI data
00905     transfers.
00906
00907     (+) There are two modes of transfer:
00908       (++) Blocking mode : The communication is performed in the polling mode.
00909            The status of all data processing is returned by the same function
00910            after finishing transfer.
00911       (++) No-Blocking mode : The communication is performed using Interrupts
00912            or DMA. These functions return the status of the transfer startup.
00913            The end of the data processing will be indicated through the
00914            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00915            using DMA mode.
00916
00917     (+) Blocking mode functions are :
00918       (++) HAL_SAI_Transmit()
00919       (++) HAL_SAI_Receive()
00920
00921     (+) Non Blocking mode functions with Interrupt are :
00922       (++) HAL_SAI_Transmit_IT()
00923       (++) HAL_SAI_Receive_IT()
00924
00925     (+) Non Blocking mode functions with DMA are :
00926       (++) HAL_SAI_Transmit_DMA()
00927       (++) HAL_SAI_Receive_DMA()
00928
00929     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00930       (++) HAL_SAI_TxCpltCallback()
00931       (++) HAL_SAI_RxCpltCallback()
00932       (++) HAL_SAI_ErrorCallback()
00933
00934 @endverbatim
00935   * @{
00936   */
00937
00938 /**
00939   * @brief  Transmit an amount of data in blocking mode.
00940   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00941   *              the configuration information for SAI module.
00942   * @param  pData Pointer to data buffer
00943   * @param  Size Amount of data to be sent
00944   * @param  Timeout Timeout duration
00945   * @retval HAL status
00946   */
00947 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00948 {
00949   uint32_t tickstart = HAL_GetTick();
00950   uint32_t temp;
00951
00952   if ((pData == NULL) || (Size == 0U))
00953   {
00954     return  HAL_ERROR;
00955   }
00956
00957   if (hsai->State == HAL_SAI_STATE_READY)
00958   {
00959     /* Process Locked */
00960     __HAL_LOCK(hsai);
00961
00962     hsai->XferSize = Size;
00963     hsai->XferCount = Size;
00964     hsai->pBuffPtr = pData;
00965     hsai->State = HAL_SAI_STATE_BUSY_TX;
00966     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00967
00968     /* Check if the SAI is already enabled */
00969     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
00970     {
00971       /* fill the fifo with data before to enabled the SAI */
00972       SAI_FillFifo(hsai);
00973       /* Enable SAI peripheral */
00974       __HAL_SAI_ENABLE(hsai);
00975     }
00976
00977     while (hsai->XferCount > 0U)
00978     {
00979       /* Write data if the FIFO is not full */
00980       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00981       {
00982         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00983         {
00984           hsai->Instance->DR = *hsai->pBuffPtr;
00985           hsai->pBuffPtr++;
00986         }
00987         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
00988         {
00989           temp = (uint32_t)(*hsai->pBuffPtr);
00990           hsai->pBuffPtr++;
00991           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
00992           hsai->pBuffPtr++;
00993           hsai->Instance->DR = temp;
00994         }
00995         else
00996         {
00997           temp = (uint32_t)(*hsai->pBuffPtr);
00998           hsai->pBuffPtr++;
00999           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
01000           hsai->pBuffPtr++;
01001           temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
01002           hsai->pBuffPtr++;
01003           temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
01004           hsai->pBuffPtr++;
01005           hsai->Instance->DR = temp;
01006         }
01007         hsai->XferCount--;
01008       }
01009       else
01010       {
01011         /* Check for the Timeout */
01012         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01013         {
01014           /* Update error code */
01015           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01016
01017           /* Clear all the flags */
01018           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01019
01020           /* Disable SAI peripheral */
01021           /* No need to check return value because state update, unlock and error return will be performed later */
01022           (void) SAI_Disable(hsai);
01023
01024           /* Flush the fifo */
01025           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01026
01027           /* Change the SAI state */
01028           hsai->State = HAL_SAI_STATE_READY;
01029
01030           /* Process Unlocked */
01031           __HAL_UNLOCK(hsai);
01032
01033           return HAL_ERROR;
01034         }
01035       }
01036     }
01037
01038     hsai->State = HAL_SAI_STATE_READY;
01039
01040     /* Process Unlocked */
01041     __HAL_UNLOCK(hsai);
01042
01043     return HAL_OK;
01044   }
01045   else
01046   {
01047     return HAL_BUSY;
01048   }
01049 }
01050
01051 /**
01052   * @brief  Receive an amount of data in blocking mode.
01053   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01054   *              the configuration information for SAI module.
01055   * @param  pData Pointer to data buffer
01056   * @param  Size Amount of data to be received
01057   * @param  Timeout Timeout duration
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01061 {
01062   uint32_t tickstart = HAL_GetTick();
01063   uint32_t temp;
01064
01065   if ((pData == NULL) || (Size == 0U))
01066   {
01067     return  HAL_ERROR;
01068   }
01069
01070   if (hsai->State == HAL_SAI_STATE_READY)
01071   {
01072     /* Process Locked */
01073     __HAL_LOCK(hsai);
01074
01075     hsai->pBuffPtr = pData;
01076     hsai->XferSize = Size;
01077     hsai->XferCount = Size;
01078     hsai->State = HAL_SAI_STATE_BUSY_RX;
01079     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01080
01081     /* Check if the SAI is already enabled */
01082     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01083     {
01084       /* Enable SAI peripheral */
01085       __HAL_SAI_ENABLE(hsai);
01086     }
01087
01088     /* Receive data */
01089     while (hsai->XferCount > 0U)
01090     {
01091       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
01092       {
01093         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01094         {
01095           *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
01096           hsai->pBuffPtr++;
01097         }
01098         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01099         {
01100           temp = hsai->Instance->DR;
01101           *hsai->pBuffPtr = (uint8_t)temp;
01102           hsai->pBuffPtr++;
01103           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01104           hsai->pBuffPtr++;
01105         }
01106         else
01107         {
01108           temp = hsai->Instance->DR;
01109           *hsai->pBuffPtr = (uint8_t)temp;
01110           hsai->pBuffPtr++;
01111           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01112           hsai->pBuffPtr++;
01113           *hsai->pBuffPtr = (uint8_t)(temp >> 16);
01114           hsai->pBuffPtr++;
01115           *hsai->pBuffPtr = (uint8_t)(temp >> 24);
01116           hsai->pBuffPtr++;
01117         }
01118         hsai->XferCount--;
01119       }
01120       else
01121       {
01122         /* Check for the Timeout */
01123         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01124         {
01125           /* Update error code */
01126           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01127
01128           /* Clear all the flags */
01129           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01130
01131           /* Disable SAI peripheral */
01132           /* No need to check return value because state update, unlock and error return will be performed later */
01133           (void) SAI_Disable(hsai);
01134
01135           /* Flush the fifo */
01136           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01137
01138           /* Change the SAI state */
01139           hsai->State = HAL_SAI_STATE_READY;
01140
01141           /* Process Unlocked */
01142           __HAL_UNLOCK(hsai);
01143
01144           return HAL_ERROR;
01145         }
01146       }
01147     }
01148
01149     hsai->State = HAL_SAI_STATE_READY;
01150
01151     /* Process Unlocked */
01152     __HAL_UNLOCK(hsai);
01153
01154     return HAL_OK;
01155   }
01156   else
01157   {
01158     return HAL_BUSY;
01159   }
01160 }
01161
01162 /**
01163   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01164   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01165   *              the configuration information for SAI module.
01166   * @param  pData Pointer to data buffer
01167   * @param  Size Amount of data to be sent
01168   * @retval HAL status
01169   */
01170 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01171 {
01172   if ((pData == NULL) || (Size == 0U))
01173   {
01174     return  HAL_ERROR;
01175   }
01176
01177   if (hsai->State == HAL_SAI_STATE_READY)
01178   {
01179     /* Process Locked */
01180     __HAL_LOCK(hsai);
01181
01182     hsai->pBuffPtr = pData;
01183     hsai->XferSize = Size;
01184     hsai->XferCount = Size;
01185     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01186     hsai->State = HAL_SAI_STATE_BUSY_TX;
01187
01188     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01189     {
01190       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
01191     }
01192     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01193     {
01194       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
01195     }
01196     else
01197     {
01198       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
01199     }
01200
01201     /* Fill the fifo before starting the communication */
01202     SAI_FillFifo(hsai);
01203
01204     /* Enable FRQ and OVRUDR interrupts */
01205     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01206
01207     /* Check if the SAI is already enabled */
01208     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01209     {
01210       /* Enable SAI peripheral */
01211       __HAL_SAI_ENABLE(hsai);
01212     }
01213     /* Process Unlocked */
01214     __HAL_UNLOCK(hsai);
01215
01216     return HAL_OK;
01217   }
01218   else
01219   {
01220     return HAL_BUSY;
01221   }
01222 }
01223
01224 /**
01225   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01226   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01227   *              the configuration information for SAI module.
01228   * @param  pData Pointer to data buffer
01229   * @param  Size Amount of data to be received
01230   * @retval HAL status
01231   */
01232 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01233 {
01234   if ((pData == NULL) || (Size == 0U))
01235   {
01236     return  HAL_ERROR;
01237   }
01238
01239   if (hsai->State == HAL_SAI_STATE_READY)
01240   {
01241     /* Process Locked */
01242     __HAL_LOCK(hsai);
01243
01244     hsai->pBuffPtr = pData;
01245     hsai->XferSize = Size;
01246     hsai->XferCount = Size;
01247     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01248     hsai->State = HAL_SAI_STATE_BUSY_RX;
01249
01250     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01251     {
01252       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
01253     }
01254     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01255     {
01256       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
01257     }
01258     else
01259     {
01260       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
01261     }
01262
01263     /* Enable TXE and OVRUDR interrupts */
01264     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01265
01266     /* Check if the SAI is already enabled */
01267     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01268     {
01269       /* Enable SAI peripheral */
01270       __HAL_SAI_ENABLE(hsai);
01271     }
01272
01273     /* Process Unlocked */
01274     __HAL_UNLOCK(hsai);
01275
01276     return HAL_OK;
01277   }
01278   else
01279   {
01280     return HAL_BUSY;
01281   }
01282 }
01283
01284 /**
01285   * @brief Pause the audio stream playing from the Media.
01286   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01287   *              the configuration information for SAI module.
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
01291 {
01292   /* Process Locked */
01293   __HAL_LOCK(hsai);
01294
01295   /* Pause the audio file playing by disabling the SAI DMA requests */
01296   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01297
01298   /* Process Unlocked */
01299   __HAL_UNLOCK(hsai);
01300
01301   return HAL_OK;
01302 }
01303
01304 /**
01305   * @brief Resume the audio stream playing from the Media.
01306   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01307   *              the configuration information for SAI module.
01308   * @retval HAL status
01309   */
01310 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
01311 {
01312   /* Process Locked */
01313   __HAL_LOCK(hsai);
01314
01315   /* Enable the SAI DMA requests */
01316   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01317
01318   /* If the SAI peripheral is still not enabled, enable it */
01319   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01320   {
01321     /* Enable SAI peripheral */
01322     __HAL_SAI_ENABLE(hsai);
01323   }
01324
01325   /* Process Unlocked */
01326   __HAL_UNLOCK(hsai);
01327
01328   return HAL_OK;
01329 }
01330
01331 /**
01332   * @brief Stop the audio stream playing from the Media.
01333   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01334   *              the configuration information for SAI module.
01335   * @retval HAL status
01336   */
01337 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
01338 {
01339   HAL_StatusTypeDef status = HAL_OK;
01340
01341   /* Process Locked */
01342   __HAL_LOCK(hsai);
01343
01344   /* Disable SAI peripheral */
01345   if (SAI_Disable(hsai) != HAL_OK)
01346   {
01347     status = HAL_ERROR;
01348   }
01349
01350   /* Disable the SAI DMA request */
01351   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01352
01353   /* Abort the SAI Tx DMA Stream */
01354   if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
01355   {
01356     /* No need to check the returned value of HAL_DMA_Abort. */
01357     /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01358     (void) HAL_DMA_Abort(hsai->hdmatx);
01359   }
01360
01361   /* Abort the SAI Rx DMA Stream */
01362   if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01363   {
01364     /* No need to check the returned value of HAL_DMA_Abort. */
01365     /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01366     (void) HAL_DMA_Abort(hsai->hdmarx);
01367   }
01368
01369   /* Flush the fifo */
01370   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01371
01372   /* Set hsai state to ready */
01373   hsai->State = HAL_SAI_STATE_READY;
01374
01375   /* Process Unlocked */
01376   __HAL_UNLOCK(hsai);
01377
01378   return status;
01379 }
01380
01381 /**
01382   * @brief Abort the current transfer and disable the SAI.
01383   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01384   *              the configuration information for SAI module.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
01388 {
01389   HAL_StatusTypeDef status = HAL_OK;
01390
01391   /* Process Locked */
01392   __HAL_LOCK(hsai);
01393
01394   /* Disable SAI peripheral */
01395   if (SAI_Disable(hsai) != HAL_OK)
01396   {
01397     status = HAL_ERROR;
01398   }
01399
01400   /* Check SAI DMA is enabled or not */
01401   if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01402   {
01403     /* Disable the SAI DMA request */
01404     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01405
01406     /* Abort the SAI Tx DMA Stream */
01407     if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
01408     {
01409       /* No need to check the returned value of HAL_DMA_Abort. */
01410       /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01411       (void) HAL_DMA_Abort(hsai->hdmatx);
01412     }
01413
01414     /* Abort the SAI Rx DMA Stream */
01415     if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01416     {
01417       /* No need to check the returned value of HAL_DMA_Abort. */
01418       /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01419       (void) HAL_DMA_Abort(hsai->hdmarx);
01420     }
01421   }
01422
01423   /* Disabled All interrupt and clear all the flag */
01424   hsai->Instance->IMR = 0;
01425   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01426
01427   /* Flush the fifo */
01428   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01429
01430   /* Set hsai state to ready */
01431   hsai->State = HAL_SAI_STATE_READY;
01432
01433   /* Process Unlocked */
01434   __HAL_UNLOCK(hsai);
01435
01436   return status;
01437 }
01438
01439 /**
01440   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01441   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01442   *              the configuration information for SAI module.
01443   * @param  pData Pointer to data buffer
01444   * @param  Size Amount of data to be sent
01445   * @retval HAL status
01446   */
01447 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01448 {
01449   uint32_t tickstart = HAL_GetTick();
01450
01451   if ((pData == NULL) || (Size == 0U))
01452   {
01453     return  HAL_ERROR;
01454   }
01455
01456   if (hsai->State == HAL_SAI_STATE_READY)
01457   {
01458     /* Process Locked */
01459     __HAL_LOCK(hsai);
01460
01461     hsai->pBuffPtr = pData;
01462     hsai->XferSize = Size;
01463     hsai->XferCount = Size;
01464     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01465     hsai->State = HAL_SAI_STATE_BUSY_TX;
01466
01467     /* Set the SAI Tx DMA Half transfer complete callback */
01468     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01469
01470     /* Set the SAI TxDMA transfer complete callback */
01471     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01472
01473     /* Set the DMA error callback */
01474     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01475
01476     /* Set the DMA Tx abort callback */
01477     hsai->hdmatx->XferAbortCallback = NULL;
01478
01479     /* Enable the Tx DMA Stream */
01480     if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
01481     {
01482       __HAL_UNLOCK(hsai);
01483       return  HAL_ERROR;
01484     }
01485
01486     /* Enable the interrupts for error handling */
01487     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01488
01489     /* Enable SAI Tx DMA Request */
01490     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01491
01492     /* Wait until FIFO is not empty */
01493     while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
01494     {
01495       /* Check for the Timeout */
01496       if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
01497       {
01498         /* Update error code */
01499         hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01500
01501         /* Process Unlocked */
01502         __HAL_UNLOCK(hsai);
01503
01504         return HAL_TIMEOUT;
01505       }
01506     }
01507
01508     /* Check if the SAI is already enabled */
01509     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01510     {
01511       /* Enable SAI peripheral */
01512       __HAL_SAI_ENABLE(hsai);
01513     }
01514
01515     /* Process Unlocked */
01516     __HAL_UNLOCK(hsai);
01517
01518     return HAL_OK;
01519   }
01520   else
01521   {
01522     return HAL_BUSY;
01523   }
01524 }
01525
01526 /**
01527   * @brief  Receive an amount of data in non-blocking mode with DMA.
01528   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01529   *              the configuration information for SAI module.
01530   * @param  pData Pointer to data buffer
01531   * @param  Size Amount of data to be received
01532   * @retval HAL status
01533   */
01534 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01535 {
01536
01537   if ((pData == NULL) || (Size == 0U))
01538   {
01539     return  HAL_ERROR;
01540   }
01541
01542   if (hsai->State == HAL_SAI_STATE_READY)
01543   {
01544     /* Process Locked */
01545     __HAL_LOCK(hsai);
01546
01547     hsai->pBuffPtr = pData;
01548     hsai->XferSize = Size;
01549     hsai->XferCount = Size;
01550     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01551     hsai->State = HAL_SAI_STATE_BUSY_RX;
01552
01553     /* Set the SAI Rx DMA Half transfer complete callback */
01554     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01555
01556     /* Set the SAI Rx DMA transfer complete callback */
01557     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01558
01559     /* Set the DMA error callback */
01560     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01561
01562     /* Set the DMA Rx abort callback */
01563     hsai->hdmarx->XferAbortCallback = NULL;
01564
01565     /* Enable the Rx DMA Stream */
01566     if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
01567     {
01568       __HAL_UNLOCK(hsai);
01569       return  HAL_ERROR;
01570     }
01571
01572     /* Enable the interrupts for error handling */
01573     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01574
01575     /* Enable SAI Rx DMA Request */
01576     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01577
01578     /* Check if the SAI is already enabled */
01579     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01580     {
01581       /* Enable SAI peripheral */
01582       __HAL_SAI_ENABLE(hsai);
01583     }
01584
01585     /* Process Unlocked */
01586     __HAL_UNLOCK(hsai);
01587
01588     return HAL_OK;
01589   }
01590   else
01591   {
01592     return HAL_BUSY;
01593   }
01594 }
01595
01596 /**
01597   * @brief  Enable the Tx mute mode.
01598   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01599   *              the configuration information for SAI module.
01600   * @param  val  value sent during the mute @ref SAI_Block_Mute_Value
01601   * @retval HAL status
01602   */
01603 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01604 {
01605   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01606
01607   if (hsai->State != HAL_SAI_STATE_RESET)
01608   {
01609     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01610     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
01611     return HAL_OK;
01612   }
01613   return HAL_ERROR;
01614 }
01615
01616 /**
01617   * @brief  Disable the Tx mute mode.
01618   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01619   *              the configuration information for SAI module.
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01623 {
01624   if (hsai->State != HAL_SAI_STATE_RESET)
01625   {
01626     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01627     return HAL_OK;
01628   }
01629   return HAL_ERROR;
01630 }
01631
01632 /**
01633   * @brief  Enable the Rx mute detection.
01634   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01635   *              the configuration information for SAI module.
01636   * @param  callback function called when the mute is detected.
01637   * @param  counter number a data before mute detection max 63.
01638   * @retval HAL status
01639   */
01640 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01641 {
01642   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01643
01644   if (hsai->State != HAL_SAI_STATE_RESET)
01645   {
01646     /* set the mute counter */
01647     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01648     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
01649     hsai->mutecallback = callback;
01650     /* enable the IT interrupt */
01651     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01652     return HAL_OK;
01653   }
01654   return HAL_ERROR;
01655 }
01656
01657 /**
01658   * @brief  Disable the Rx mute detection.
01659   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01660   *              the configuration information for SAI module.
01661   * @retval HAL status
01662   */
01663 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01664 {
01665   if (hsai->State != HAL_SAI_STATE_RESET)
01666   {
01667     /* set the mutecallback to NULL */
01668     hsai->mutecallback = NULL;
01669     /* enable the IT interrupt */
01670     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01671     return HAL_OK;
01672   }
01673   return HAL_ERROR;
01674 }
01675
01676 /**
01677   * @brief  Handle SAI interrupt request.
01678   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01679   *              the configuration information for SAI module.
01680   * @retval None
01681   */
01682 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01683 {
01684   if (hsai->State != HAL_SAI_STATE_RESET)
01685   {
01686     uint32_t itflags = hsai->Instance->SR;
01687     uint32_t itsources = hsai->Instance->IMR;
01688     uint32_t cr1config = hsai->Instance->CR1;
01689     uint32_t tmperror;
01690
01691     /* SAI Fifo request interrupt occurred -----------------------------------*/
01692     if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
01693     {
01694       hsai->InterruptServiceRoutine(hsai);
01695     }
01696     /* SAI Overrun error interrupt occurred ----------------------------------*/
01697     else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01698     {
01699       /* Clear the SAI Overrun flag */
01700       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01701       /* Get the SAI error code */
01702       tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01703       /* Change the SAI error code */
01704       hsai->ErrorCode |= tmperror;
01705       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01706 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01707       hsai->ErrorCallback(hsai);
01708 #else
01709       HAL_SAI_ErrorCallback(hsai);
01710 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01711     }
01712     /* SAI mutedet interrupt occurred ----------------------------------*/
01713     else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01714     {
01715       /* Clear the SAI mutedet flag */
01716       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01717       /* call the call back function */
01718       if (hsai->mutecallback != NULL)
01719       {
01720         /* inform the user that an RX mute event has been detected */
01721         hsai->mutecallback();
01722       }
01723     }
01724     /* SAI AFSDET interrupt occurred ----------------------------------*/
01725     else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01726     {
01727       /* Clear the SAI AFSDET flag */
01728       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
01729
01730       /* Change the SAI error code */
01731       hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
01732
01733       /* Check SAI DMA is enabled or not */
01734       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01735       {
01736         /* Abort the SAI DMA Streams */
01737         if (hsai->hdmatx != NULL)
01738         {
01739           /* Set the DMA Tx abort callback */
01740           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01741
01742           /* Abort DMA in IT mode */
01743           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01744           {
01745             /* Update SAI error code */
01746             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01747
01748             /* Call SAI error callback */
01749 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01750             hsai->ErrorCallback(hsai);
01751 #else
01752             HAL_SAI_ErrorCallback(hsai);
01753 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01754           }
01755         }
01756         if (hsai->hdmarx != NULL)
01757         {
01758           /* Set the DMA Rx abort callback */
01759           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01760
01761           /* Abort DMA in IT mode */
01762           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01763           {
01764             /* Update SAI error code */
01765             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01766
01767             /* Call SAI error callback */
01768 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01769             hsai->ErrorCallback(hsai);
01770 #else
01771             HAL_SAI_ErrorCallback(hsai);
01772 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01773           }
01774         }
01775       }
01776       else
01777       {
01778         /* Abort SAI */
01779         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
01780         (void) HAL_SAI_Abort(hsai);
01781
01782         /* Set error callback */
01783 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01784         hsai->ErrorCallback(hsai);
01785 #else
01786         HAL_SAI_ErrorCallback(hsai);
01787 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01788       }
01789     }
01790     /* SAI LFSDET interrupt occurred ----------------------------------*/
01791     else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01792     {
01793       /* Clear the SAI LFSDET flag */
01794       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
01795
01796       /* Change the SAI error code */
01797       hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
01798
01799       /* Check SAI DMA is enabled or not */
01800       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01801       {
01802         /* Abort the SAI DMA Streams */
01803         if (hsai->hdmatx != NULL)
01804         {
01805           /* Set the DMA Tx abort callback */
01806           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01807
01808           /* Abort DMA in IT mode */
01809           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01810           {
01811             /* Update SAI error code */
01812             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01813
01814             /* Call SAI error callback */
01815 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01816             hsai->ErrorCallback(hsai);
01817 #else
01818             HAL_SAI_ErrorCallback(hsai);
01819 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01820           }
01821         }
01822         if (hsai->hdmarx != NULL)
01823         {
01824           /* Set the DMA Rx abort callback */
01825           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01826
01827           /* Abort DMA in IT mode */
01828           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01829           {
01830             /* Update SAI error code */
01831             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01832
01833             /* Call SAI error callback */
01834 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01835             hsai->ErrorCallback(hsai);
01836 #else
01837             HAL_SAI_ErrorCallback(hsai);
01838 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01839           }
01840         }
01841       }
01842       else
01843       {
01844         /* Abort SAI */
01845         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
01846         (void) HAL_SAI_Abort(hsai);
01847
01848         /* Set error callback */
01849 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01850         hsai->ErrorCallback(hsai);
01851 #else
01852         HAL_SAI_ErrorCallback(hsai);
01853 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01854       }
01855     }
01856     /* SAI WCKCFG interrupt occurred ----------------------------------*/
01857     else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01858     {
01859       /* Clear the SAI WCKCFG flag */
01860       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
01861
01862       /* Change the SAI error code */
01863       hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
01864
01865       /* Check SAI DMA is enabled or not */
01866       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01867       {
01868         /* Abort the SAI DMA Streams */
01869         if (hsai->hdmatx != NULL)
01870         {
01871           /* Set the DMA Tx abort callback */
01872           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01873
01874           /* Abort DMA in IT mode */
01875           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01876           {
01877             /* Update SAI error code */
01878             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01879
01880             /* Call SAI error callback */
01881 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01882             hsai->ErrorCallback(hsai);
01883 #else
01884             HAL_SAI_ErrorCallback(hsai);
01885 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01886           }
01887         }
01888         if (hsai->hdmarx != NULL)
01889         {
01890           /* Set the DMA Rx abort callback */
01891           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01892
01893           /* Abort DMA in IT mode */
01894           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01895           {
01896             /* Update SAI error code */
01897             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01898
01899             /* Call SAI error callback */
01900 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01901             hsai->ErrorCallback(hsai);
01902 #else
01903             HAL_SAI_ErrorCallback(hsai);
01904 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01905           }
01906         }
01907       }
01908       else
01909       {
01910         /* If WCKCFG occurs, SAI audio block is automatically disabled */
01911         /* Disable all interrupts and clear all flags */
01912         hsai->Instance->IMR = 0U;
01913         hsai->Instance->CLRFR = 0xFFFFFFFFU;
01914         /* Set the SAI state to ready to be able to start again the process */
01915         hsai->State = HAL_SAI_STATE_READY;
01916
01917         /* Initialize XferCount */
01918         hsai->XferCount = 0U;
01919
01920         /* SAI error Callback */
01921 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01922         hsai->ErrorCallback(hsai);
01923 #else
01924         HAL_SAI_ErrorCallback(hsai);
01925 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01926       }
01927     }
01928     /* SAI CNRDY interrupt occurred ----------------------------------*/
01929     else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01930     {
01931       /* Clear the SAI CNRDY flag */
01932       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01933       /* Change the SAI error code */
01934       hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
01935       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01936 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01937       hsai->ErrorCallback(hsai);
01938 #else
01939       HAL_SAI_ErrorCallback(hsai);
01940 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
01941     }
01942     else
01943     {
01944       /* Nothing to do */
01945     }
01946   }
01947 }
01948
01949 /**
01950   * @brief Tx Transfer completed callback.
01951   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01952   *              the configuration information for SAI module.
01953   * @retval None
01954   */
01955 __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01956 {
01957   /* Prevent unused argument(s) compilation warning */
01958   UNUSED(hsai);
01959
01960   /* NOTE : This function should not be modified, when the callback is needed,
01961             the HAL_SAI_TxCpltCallback could be implemented in the user file
01962    */
01963 }
01964
01965 /**
01966   * @brief Tx Transfer Half completed callback.
01967   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01968   *              the configuration information for SAI module.
01969   * @retval None
01970   */
01971 __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01972 {
01973   /* Prevent unused argument(s) compilation warning */
01974   UNUSED(hsai);
01975
01976   /* NOTE : This function should not be modified, when the callback is needed,
01977             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01978    */
01979 }
01980
01981 /**
01982   * @brief Rx Transfer completed callback.
01983   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01984   *              the configuration information for SAI module.
01985   * @retval None
01986   */
01987 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01988 {
01989   /* Prevent unused argument(s) compilation warning */
01990   UNUSED(hsai);
01991
01992   /* NOTE : This function should not be modified, when the callback is needed,
01993             the HAL_SAI_RxCpltCallback could be implemented in the user file
01994    */
01995 }
01996
01997 /**
01998   * @brief Rx Transfer half completed callback.
01999   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02000   *              the configuration information for SAI module.
02001   * @retval None
02002   */
02003 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
02004 {
02005   /* Prevent unused argument(s) compilation warning */
02006   UNUSED(hsai);
02007
02008   /* NOTE : This function should not be modified, when the callback is needed,
02009             the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
02010    */
02011 }
02012
02013 /**
02014   * @brief SAI error callback.
02015   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02016   *              the configuration information for SAI module.
02017   * @retval None
02018   */
02019 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
02020 {
02021   /* Prevent unused argument(s) compilation warning */
02022   UNUSED(hsai);
02023
02024   /* NOTE : This function should not be modified, when the callback is needed,
02025             the HAL_SAI_ErrorCallback could be implemented in the user file
02026    */
02027 }
02028
02029 /**
02030   * @}
02031   */
02032
02033 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
02034   * @brief    Peripheral State functions
02035   *
02036 @verbatim
02037   ===============================================================================
02038                 ##### Peripheral State and Errors functions #####
02039   ===============================================================================
02040   [..]
02041     This subsection permits to get in run-time the status of the peripheral
02042     and the data flow.
02043
02044 @endverbatim
02045   * @{
02046   */
02047
02048 /**
02049   * @brief  Return the SAI handle state.
02050   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02051   *              the configuration information for SAI module.
02052   * @retval HAL state
02053   */
02054 HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai)
02055 {
02056   return hsai->State;
02057 }
02058
02059 /**
02060   * @brief  Return the SAI error code.
02061   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02062   *              the configuration information for the specified SAI Block.
02063   * @retval SAI Error Code
02064   */
02065 uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai)
02066 {
02067   return hsai->ErrorCode;
02068 }
02069
02070 /**
02071   * @}
02072   */
02073
02074 /**
02075   * @}
02076   */
02077
02078 /** @addtogroup SAI_Private_Functions
02079   * @brief      Private functions
02080   * @{
02081   */
02082
02083 /**
02084   * @brief  Initialize the SAI I2S protocol according to the specified parameters
02085   *         in the SAI_InitTypeDef and create the associated handle.
02086   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02087   *              the configuration information for SAI module.
02088   * @param  protocol one of the supported protocol.
02089   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize.
02090   * @param  nbslot number of slot minimum value is 2 and max is 16.
02091   *         the value must be a multiple of 2.
02092   * @retval HAL status
02093   */
02094 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02095 {
02096   HAL_StatusTypeDef status = HAL_OK;
02097
02098   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02099   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02100   /* Compute ClockStrobing according AudioMode */
02101   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02102   {
02103     /* Transmit */
02104     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02105   }
02106   else
02107   {
02108     /* Receive */
02109     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02110   }
02111   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
02112   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02113   hsai->SlotInit.FirstBitOffset  = 0;
02114   hsai->SlotInit.SlotNumber      = nbslot;
02115
02116   /* in IS2 the number of slot must be even */
02117   if ((nbslot & 0x1U) != 0U)
02118   {
02119     return HAL_ERROR;
02120   }
02121
02122   if (protocol == SAI_I2S_STANDARD)
02123   {
02124     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
02125     hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
02126   }
02127   else
02128   {
02129      /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
02130     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
02131     hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
02132   }
02133
02134   /* Frame definition */
02135   switch (datasize)
02136   {
02137     case SAI_PROTOCOL_DATASIZE_16BIT:
02138       hsai->Init.DataSize = SAI_DATASIZE_16;
02139       hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
02140       hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
02141       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02142       break;
02143     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02144       hsai->Init.DataSize = SAI_DATASIZE_16;
02145       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02146       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02147       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02148       break;
02149     case SAI_PROTOCOL_DATASIZE_24BIT:
02150       hsai->Init.DataSize = SAI_DATASIZE_24;
02151       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02152       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02153       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02154       break;
02155     case SAI_PROTOCOL_DATASIZE_32BIT:
02156       hsai->Init.DataSize = SAI_DATASIZE_32;
02157       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02158       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02159       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02160       break;
02161     default :
02162       status = HAL_ERROR;
02163       break;
02164   }
02165   if (protocol == SAI_I2S_LSBJUSTIFIED)
02166   {
02167     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
02168     {
02169       hsai->SlotInit.FirstBitOffset = 16;
02170     }
02171     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
02172     {
02173       hsai->SlotInit.FirstBitOffset = 8;
02174     }
02175   }
02176   return status;
02177 }
02178
02179 /**
02180   * @brief  Initialize the SAI PCM protocol according to the specified parameters
02181   *         in the SAI_InitTypeDef and create the associated handle.
02182   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02183   *              the configuration information for SAI module.
02184   * @param  protocol one of the supported protocol
02185   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
02186   * @param  nbslot number of slot minimum value is 1 and the max is 16.
02187   * @retval HAL status
02188   */
02189 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02190 {
02191   HAL_StatusTypeDef status = HAL_OK;
02192
02193   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02194   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02195   /* Compute ClockStrobing according AudioMode */
02196   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02197   {
02198     /* Transmit */
02199     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02200   }
02201   else
02202   {
02203     /* Receive */
02204     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02205   }
02206   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
02207   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
02208   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
02209   hsai->SlotInit.FirstBitOffset  = 0;
02210   hsai->SlotInit.SlotNumber      = nbslot;
02211   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02212
02213   if (protocol == SAI_PCM_SHORT)
02214   {
02215     hsai->FrameInit.ActiveFrameLength = 1;
02216   }
02217   else
02218   {
02219     /* SAI_PCM_LONG */
02220     hsai->FrameInit.ActiveFrameLength = 13;
02221   }
02222
02223   switch (datasize)
02224   {
02225     case SAI_PROTOCOL_DATASIZE_16BIT:
02226       hsai->Init.DataSize = SAI_DATASIZE_16;
02227       hsai->FrameInit.FrameLength = 16U * nbslot;
02228       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02229       break;
02230     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02231       hsai->Init.DataSize = SAI_DATASIZE_16;
02232       hsai->FrameInit.FrameLength = 32U * nbslot;
02233       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02234       break;
02235     case SAI_PROTOCOL_DATASIZE_24BIT :
02236       hsai->Init.DataSize = SAI_DATASIZE_24;
02237       hsai->FrameInit.FrameLength = 32U * nbslot;
02238       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02239       break;
02240     case SAI_PROTOCOL_DATASIZE_32BIT:
02241       hsai->Init.DataSize = SAI_DATASIZE_32;
02242       hsai->FrameInit.FrameLength = 32U * nbslot;
02243       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02244       break;
02245     default :
02246       status = HAL_ERROR;
02247       break;
02248   }
02249
02250   return status;
02251 }
02252
02253 /**
02254   * @brief  Fill the fifo.
02255   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02256   *              the configuration information for SAI module.
02257   * @retval None
02258   */
02259 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
02260 {
02261   uint32_t temp;
02262
02263   /* fill the fifo with data before to enabled the SAI */
02264   while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
02265   {
02266     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
02267     {
02268       hsai->Instance->DR = *hsai->pBuffPtr;
02269       hsai->pBuffPtr++;
02270     }
02271     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
02272     {
02273       temp = (uint32_t)(*hsai->pBuffPtr);
02274       hsai->pBuffPtr++;
02275       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02276       hsai->pBuffPtr++;
02277       hsai->Instance->DR = temp;
02278     }
02279     else
02280     {
02281       temp = (uint32_t)(*hsai->pBuffPtr);
02282       hsai->pBuffPtr++;
02283       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02284       hsai->pBuffPtr++;
02285       temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02286       hsai->pBuffPtr++;
02287       temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02288       hsai->pBuffPtr++;
02289       hsai->Instance->DR = temp;
02290     }
02291     hsai->XferCount--;
02292   }
02293 }
02294
02295 /**
02296   * @brief  Return the interrupt flag to set according the SAI setup.
02297   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02298   *              the configuration information for SAI module.
02299   * @param  mode SAI_MODE_DMA or SAI_MODE_IT
02300   * @retval the list of the IT flag to enable
02301   */
02302 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
02303 {
02304   uint32_t tmpIT = SAI_IT_OVRUDR;
02305
02306   if (mode == SAI_MODE_IT)
02307   {
02308     tmpIT |= SAI_IT_FREQ;
02309   }
02310
02311   if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
02312       ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
02313   {
02314     tmpIT |= SAI_IT_CNRDY;
02315   }
02316
02317   if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02318   {
02319     tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
02320   }
02321   else
02322   {
02323     /* hsai has been configured in master mode */
02324     tmpIT |= SAI_IT_WCKCFG;
02325   }
02326   return tmpIT;
02327 }
02328
02329 /**
02330   * @brief  Disable the SAI and wait for the disabling.
02331   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02332   *              the configuration information for SAI module.
02333   * @retval None
02334   */
02335 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
02336 {
02337   uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
02338   HAL_StatusTypeDef status = HAL_OK;
02339
02340   /* Disable the SAI instance */
02341   __HAL_SAI_DISABLE(hsai);
02342
02343   do
02344   {
02345     /* Check for the Timeout */
02346     if (count == 0U)
02347     {
02348       /* Update error code */
02349       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
02350       status = HAL_TIMEOUT;
02351       break;
02352     }
02353     count--;
02354   } while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
02355
02356   return status;
02357 }
02358
02359 /**
02360   * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
02361   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02362   *              the configuration information for SAI module.
02363   * @retval None
02364   */
02365 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
02366 {
02367   if (hsai->XferCount == 0U)
02368   {
02369     /* Handle the end of the transmission */
02370     /* Disable FREQ and OVRUDR interrupts */
02371     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02372     hsai->State = HAL_SAI_STATE_READY;
02373 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02374     hsai->TxCpltCallback(hsai);
02375 #else
02376     HAL_SAI_TxCpltCallback(hsai);
02377 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02378   }
02379   else
02380   {
02381     /* Write data on DR register */
02382     hsai->Instance->DR = *hsai->pBuffPtr;
02383     hsai->pBuffPtr++;
02384     hsai->XferCount--;
02385   }
02386 }
02387
02388 /**
02389   * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
02390   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02391   *              the configuration information for SAI module.
02392   * @retval None
02393   */
02394 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
02395 {
02396   if (hsai->XferCount == 0U)
02397   {
02398     /* Handle the end of the transmission */
02399     /* Disable FREQ and OVRUDR interrupts */
02400     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02401     hsai->State = HAL_SAI_STATE_READY;
02402 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02403     hsai->TxCpltCallback(hsai);
02404 #else
02405     HAL_SAI_TxCpltCallback(hsai);
02406 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02407   }
02408   else
02409   {
02410     /* Write data on DR register */
02411     uint32_t temp;
02412     temp = (uint32_t)(*hsai->pBuffPtr);
02413     hsai->pBuffPtr++;
02414     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02415     hsai->pBuffPtr++;
02416     hsai->Instance->DR = temp;
02417     hsai->XferCount--;
02418   }
02419 }
02420
02421 /**
02422   * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
02423   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02424   *              the configuration information for SAI module.
02425   * @retval None
02426   */
02427 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
02428 {
02429   if (hsai->XferCount == 0U)
02430   {
02431     /* Handle the end of the transmission */
02432     /* Disable FREQ and OVRUDR interrupts */
02433     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02434     hsai->State = HAL_SAI_STATE_READY;
02435 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02436     hsai->TxCpltCallback(hsai);
02437 #else
02438     HAL_SAI_TxCpltCallback(hsai);
02439 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02440   }
02441   else
02442   {
02443     /* Write data on DR register */
02444     uint32_t temp;
02445     temp = (uint32_t)(*hsai->pBuffPtr);
02446     hsai->pBuffPtr++;
02447     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02448     hsai->pBuffPtr++;
02449     temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02450     hsai->pBuffPtr++;
02451     temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02452     hsai->pBuffPtr++;
02453     hsai->Instance->DR = temp;
02454     hsai->XferCount--;
02455   }
02456 }
02457
02458 /**
02459   * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
02460   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02461   *              the configuration information for SAI module.
02462   * @retval None
02463   */
02464 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
02465 {
02466   /* Receive data */
02467   *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
02468   hsai->pBuffPtr++;
02469   hsai->XferCount--;
02470
02471   /* Check end of the transfer */
02472   if (hsai->XferCount == 0U)
02473   {
02474     /* Disable TXE and OVRUDR interrupts */
02475     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02476
02477     /* Clear the SAI Overrun flag */
02478     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02479
02480     hsai->State = HAL_SAI_STATE_READY;
02481 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02482     hsai->RxCpltCallback(hsai);
02483 #else
02484     HAL_SAI_RxCpltCallback(hsai);
02485 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02486   }
02487 }
02488
02489 /**
02490   * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
02491   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02492   *              the configuration information for SAI module.
02493   * @retval None
02494   */
02495 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
02496 {
02497   uint32_t temp;
02498
02499   /* Receive data */
02500   temp = hsai->Instance->DR;
02501   *hsai->pBuffPtr = (uint8_t)temp;
02502   hsai->pBuffPtr++;
02503   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02504   hsai->pBuffPtr++;
02505   hsai->XferCount--;
02506
02507   /* Check end of the transfer */
02508   if (hsai->XferCount == 0U)
02509   {
02510     /* Disable TXE and OVRUDR interrupts */
02511     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02512
02513     /* Clear the SAI Overrun flag */
02514     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02515
02516     hsai->State = HAL_SAI_STATE_READY;
02517 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02518     hsai->RxCpltCallback(hsai);
02519 #else
02520     HAL_SAI_RxCpltCallback(hsai);
02521 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02522   }
02523 }
02524
02525 /**
02526   * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
02527   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02528   *              the configuration information for SAI module.
02529   * @retval None
02530   */
02531 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
02532 {
02533   uint32_t temp;
02534
02535   /* Receive data */
02536   temp = hsai->Instance->DR;
02537   *hsai->pBuffPtr = (uint8_t)temp;
02538   hsai->pBuffPtr++;
02539   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02540   hsai->pBuffPtr++;
02541   *hsai->pBuffPtr = (uint8_t)(temp >> 16);
02542   hsai->pBuffPtr++;
02543   *hsai->pBuffPtr = (uint8_t)(temp >> 24);
02544   hsai->pBuffPtr++;
02545   hsai->XferCount--;
02546
02547   /* Check end of the transfer */
02548   if (hsai->XferCount == 0U)
02549   {
02550     /* Disable TXE and OVRUDR interrupts */
02551     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02552
02553     /* Clear the SAI Overrun flag */
02554     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02555
02556     hsai->State = HAL_SAI_STATE_READY;
02557 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02558     hsai->RxCpltCallback(hsai);
02559 #else
02560     HAL_SAI_RxCpltCallback(hsai);
02561 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02562   }
02563 }
02564
02565 /**
02566   * @brief  DMA SAI transmit process complete callback.
02567   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02568   *              the configuration information for the specified DMA module.
02569   * @retval None
02570   */
02571 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
02572 {
02573   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02574
02575   if (hdma->Init.Mode != DMA_CIRCULAR)
02576   {
02577     hsai->XferCount = 0;
02578
02579     /* Disable SAI Tx DMA Request */
02580     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02581
02582     /* Stop the interrupts error handling */
02583     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02584
02585     hsai->State = HAL_SAI_STATE_READY;
02586   }
02587 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02588   hsai->TxCpltCallback(hsai);
02589 #else
02590   HAL_SAI_TxCpltCallback(hsai);
02591 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02592 }
02593
02594 /**
02595   * @brief  DMA SAI transmit process half complete callback.
02596   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02597   *              the configuration information for the specified DMA module.
02598   * @retval None
02599   */
02600 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02601 {
02602   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02603
02604 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02605   hsai->TxHalfCpltCallback(hsai);
02606 #else
02607   HAL_SAI_TxHalfCpltCallback(hsai);
02608 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02609 }
02610
02611 /**
02612   * @brief  DMA SAI receive process complete callback.
02613   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02614   *              the configuration information for the specified DMA module.
02615   * @retval None
02616   */
02617 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
02618 {
02619   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02620
02621   if (hdma->Init.Mode != DMA_CIRCULAR)
02622   {
02623     /* Disable Rx DMA Request */
02624     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02625     hsai->XferCount = 0;
02626
02627     /* Stop the interrupts error handling */
02628     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02629
02630     hsai->State = HAL_SAI_STATE_READY;
02631   }
02632 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02633   hsai->RxCpltCallback(hsai);
02634 #else
02635   HAL_SAI_RxCpltCallback(hsai);
02636 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02637 }
02638
02639 /**
02640   * @brief  DMA SAI receive process half complete callback
02641   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02642   *              the configuration information for the specified DMA module.
02643   * @retval None
02644   */
02645 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02646 {
02647   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02648
02649 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02650   hsai->RxHalfCpltCallback(hsai);
02651 #else
02652   HAL_SAI_RxHalfCpltCallback(hsai);
02653 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02654 }
02655
02656 /**
02657   * @brief  DMA SAI communication error callback.
02658   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02659   *              the configuration information for the specified DMA module.
02660   * @retval None
02661   */
02662 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
02663 {
02664   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02665
02666   /* Set SAI error code */
02667   hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02668
02669   /* Disable the SAI DMA request */
02670   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02671
02672   /* Disable SAI peripheral */
02673   /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02674   (void) SAI_Disable(hsai);
02675
02676   /* Set the SAI state ready to be able to start again the process */
02677   hsai->State = HAL_SAI_STATE_READY;
02678
02679   /* Initialize XferCount */
02680   hsai->XferCount = 0U;
02681
02682   /* SAI error Callback */
02683 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02684   hsai->ErrorCallback(hsai);
02685 #else
02686   HAL_SAI_ErrorCallback(hsai);
02687 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02688 }
02689
02690 /**
02691   * @brief  DMA SAI Abort callback.
02692   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02693   *              the configuration information for the specified DMA module.
02694   * @retval None
02695   */
02696 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
02697 {
02698   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02699
02700   /* Disable DMA request */
02701   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02702
02703   /* Disable all interrupts and clear all flags */
02704   hsai->Instance->IMR = 0U;
02705   hsai->Instance->CLRFR = 0xFFFFFFFFU;
02706
02707   if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
02708   {
02709     /* Disable SAI peripheral */
02710     /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02711     (void) SAI_Disable(hsai);
02712
02713     /* Flush the fifo */
02714     SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
02715   }
02716   /* Set the SAI state to ready to be able to start again the process */
02717   hsai->State = HAL_SAI_STATE_READY;
02718
02719   /* Initialize XferCount */
02720   hsai->XferCount = 0U;
02721
02722   /* SAI error Callback */
02723 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02724   hsai->ErrorCallback(hsai);
02725 #else
02726   HAL_SAI_ErrorCallback(hsai);
02727 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
02728 }
02729
02730 /**
02731   * @}
02732   */
02733
02734 #endif /* HAL_SAI_MODULE_ENABLED */
02735 /**
02736   * @}
02737   */
02738
02739 /**
02740   * @}
02741   */
02742
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_sai.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SAI_H
00021 #define STM32G4xx_HAL_SAI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SAI
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SAI_Exported_Types SAI Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  HAL State structures definition
00045   */
00046 typedef enum
00047 {
00048   HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
00049   HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
00050   HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
00051   HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
00052   HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
00053 } HAL_SAI_StateTypeDef;
00054
00055 /**
00056   * @brief  SAI Callback prototype
00057   */
00058 typedef void (*SAIcallback)(void);
00059
00060 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
00061   * @brief  SAI PDM Init structure definition
00062   * @{
00063   */
00064 typedef struct
00065 {
00066   FunctionalState  Activation;  /*!< Enable/disable PDM interface */
00067   uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
00068                                      This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00069   uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
00070                                      This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
00071 } SAI_PdmInitTypeDef;
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
00077   * @brief  SAI Init Structure definition
00078   * @{
00079   */
00080 typedef struct
00081 {
00082   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00083                                      This parameter can be a value of @ref SAI_Block_Mode */
00084
00085   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00086                                      This parameter can be a value of @ref SAI_Block_Synchronization */
00087
00088   uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
00089                                      for BlockA and BlockB
00090                                      This parameter can be a value of @ref SAI_Block_SyncExt
00091                                      @note If both audio blocks of same SAI are used, this parameter has
00092                                            to be set to the same value for each audio block */
00093
00094   uint32_t MckOutput;           /*!< Specifies whether master clock output will be generated or not.
00095                                      This parameter can be a value of @ref SAI_Block_MckOutput */
00096
00097   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00098                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00099                                      @note This value has to be set before enabling the audio block
00100                                            but after the audio block configuration. */
00101
00102   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00103                                      This parameter can be a value of @ref SAI_Block_NoDivider
00104                                      @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00105                                            should be aligned to a number equal to a power of 2, from 8 to 256.
00106                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can
00107                                            take any of the values from 8 to 256. */
00108
00109   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00110                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
00111
00112   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00113                                      This parameter can be a value of @ref SAI_Audio_Frequency */
00114
00115   uint32_t Mckdiv;              /*!< Specifies the master clock divider.
00116                                      This parameter must be a number between Min_Data = 0 and Max_Data = 63.
00117                                      @note This parameter is used only if AudioFrequency is set to
00118                                            SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
00119
00120   uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
00121                                      This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
00122
00123   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00124                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
00125
00126   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00127                                      This parameter can be a value of @ref SAI_Block_Companding_Mode */
00128
00129   uint32_t TriState;            /*!< Specifies the companding mode type.
00130                                      This parameter can be a value of @ref SAI_TRIState_Management */
00131
00132   SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */
00133
00134   /* This part of the structure is automatically filled if your are using the high level initialisation
00135      function HAL_SAI_InitProtocol */
00136
00137   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00138                                  This parameter can be a value of @ref SAI_Block_Protocol */
00139
00140   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00141                                  This parameter can be a value of @ref SAI_Block_Data_Size */
00142
00143   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00144                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
00145
00146   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00147                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing */
00148 } SAI_InitTypeDef;
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
00154   * @brief  SAI Frame Init structure definition
00155   * @note   For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
00156   * @{
00157   */
00158 typedef struct
00159 {
00160
00161   uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00162                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00163                                     @note If master clock MCLK_x pin is declared as an output, the frame length
00164                                           should be aligned to a number equal to power of 2 in order to keep
00165                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */
00166
00167   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00168                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00169                                     of the active level of FS signal in audio frame.
00170                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
00171
00172   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00173                                     This parameter can be a value of @ref SAI_Block_FS_Definition */
00174
00175   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00176                                     This parameter can be a value of @ref SAI_Block_FS_Polarity */
00177
00178   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00179                                     This parameter can be a value of @ref SAI_Block_FS_Offset */
00180
00181 } SAI_FrameInitTypeDef;
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
00187   * @brief   SAI Block Slot Init Structure definition
00188   * @note    For SPDIF protocol, these parameters are not used (set by hardware).
00189   * @note    For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
00190   * @{
00191   */
00192 typedef struct
00193 {
00194   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00195                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00196
00197   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00198                                  This parameter can be a value of @ref SAI_Block_Slot_Size */
00199
00200   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00201                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00202
00203   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00204                                  This parameter can be a value of @ref SAI_Block_Slot_Active */
00205 } SAI_SlotInitTypeDef;
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
00211   * @brief  SAI handle Structure definition
00212   * @{
00213   */
00214 typedef struct __SAI_HandleTypeDef
00215 {
00216   SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
00217
00218   SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
00219
00220   SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
00221
00222   SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
00223
00224   uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
00225
00226   uint16_t                  XferSize;     /*!< SAI transfer size */
00227
00228   uint16_t                  XferCount;    /*!< SAI transfer counter */
00229
00230   DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
00231
00232   DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
00233
00234   SAIcallback               mutecallback; /*!< SAI mute callback */
00235
00236   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
00237
00238   HAL_LockTypeDef           Lock;         /*!< SAI locking object */
00239
00240   __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
00241
00242   __IO uint32_t             ErrorCode;    /*!< SAI Error code */
00243
00244 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00245   void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */
00246   void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */
00247   void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */
00248   void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */
00249   void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */
00250   void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */
00251   void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */
00252 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00253 } SAI_HandleTypeDef;
00254 /**
00255   * @}
00256   */
00257
00258 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00259 /**
00260   * @brief  SAI callback ID enumeration definition
00261   */
00262 typedef enum
00263 {
00264   HAL_SAI_RX_COMPLETE_CB_ID     = 0x00U, /*!< SAI receive complete callback ID */
00265   HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
00266   HAL_SAI_TX_COMPLETE_CB_ID     = 0x02U, /*!< SAI transmit complete callback ID */
00267   HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
00268   HAL_SAI_ERROR_CB_ID           = 0x04U, /*!< SAI error callback ID */
00269   HAL_SAI_MSPINIT_CB_ID         = 0x05U, /*!< SAI MSP init callback ID */
00270   HAL_SAI_MSPDEINIT_CB_ID       = 0x06U  /*!< SAI MSP de-init callback ID */
00271 } HAL_SAI_CallbackIDTypeDef;
00272
00273 /**
00274   * @brief  SAI callback pointer definition
00275   */
00276 typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
00277 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported constants --------------------------------------------------------*/
00284 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00285   * @{
00286   */
00287
00288 /** @defgroup SAI_Error_Code SAI Error Code
00289   * @{
00290   */
00291 #define HAL_SAI_ERROR_NONE             0x00000000U  /*!< No error */
00292 #define HAL_SAI_ERROR_OVR              0x00000001U  /*!< Overrun Error */
00293 #define HAL_SAI_ERROR_UDR              0x00000002U  /*!< Underrun error */
00294 #define HAL_SAI_ERROR_AFSDET           0x00000004U  /*!< Anticipated Frame synchronisation detection */
00295 #define HAL_SAI_ERROR_LFSDET           0x00000008U  /*!< Late Frame synchronisation detection */
00296 #define HAL_SAI_ERROR_CNREADY          0x00000010U  /*!< codec not ready */
00297 #define HAL_SAI_ERROR_WCKCFG           0x00000020U  /*!< Wrong clock configuration */
00298 #define HAL_SAI_ERROR_TIMEOUT          0x00000040U  /*!< Timeout error */
00299 #define HAL_SAI_ERROR_DMA              0x00000080U  /*!< DMA error */
00300 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00301 #define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U  /*!< Invalid callback error */
00302 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00308   * @{
00309   */
00310 #define SAI_SYNCEXT_DISABLE          0U
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
00316   * @{
00317   */
00318 #define SAI_MCK_OUTPUT_DISABLE      0x00000000U
00319 #define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup SAI_Protocol SAI Supported protocol
00325   * @{
00326   */
00327 #define SAI_I2S_STANDARD      0U
00328 #define SAI_I2S_MSBJUSTIFIED  1U
00329 #define SAI_I2S_LSBJUSTIFIED  2U
00330 #define SAI_PCM_LONG          3U
00331 #define SAI_PCM_SHORT         4U
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00337   * @{
00338   */
00339 #define SAI_PROTOCOL_DATASIZE_16BIT         0U
00340 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
00341 #define SAI_PROTOCOL_DATASIZE_24BIT         2U
00342 #define SAI_PROTOCOL_DATASIZE_32BIT         3U
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00348   * @{
00349   */
00350 #define SAI_AUDIO_FREQUENCY_192K          192000U
00351 #define SAI_AUDIO_FREQUENCY_96K           96000U
00352 #define SAI_AUDIO_FREQUENCY_48K           48000U
00353 #define SAI_AUDIO_FREQUENCY_44K           44100U
00354 #define SAI_AUDIO_FREQUENCY_32K           32000U
00355 #define SAI_AUDIO_FREQUENCY_22K           22050U
00356 #define SAI_AUDIO_FREQUENCY_16K           16000U
00357 #define SAI_AUDIO_FREQUENCY_11K           11025U
00358 #define SAI_AUDIO_FREQUENCY_8K            8000U
00359 #define SAI_AUDIO_FREQUENCY_MCKDIV        0U
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
00365   * @{
00366   */
00367 #define SAI_MCK_OVERSAMPLING_DISABLE      0x00000000U
00368 #define SAI_MCK_OVERSAMPLING_ENABLE       SAI_xCR1_OSR
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
00374   * @{
00375   */
00376 #define SAI_PDM_CLOCK1_ENABLE     SAI_PDMCR_CKEN1
00377 #define SAI_PDM_CLOCK2_ENABLE     SAI_PDMCR_CKEN2
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup SAI_Block_Mode SAI Block Mode
00383   * @{
00384   */
00385 #define SAI_MODEMASTER_TX         0x00000000U
00386 #define SAI_MODEMASTER_RX         SAI_xCR1_MODE_0
00387 #define SAI_MODESLAVE_TX          SAI_xCR1_MODE_1
00388 #define SAI_MODESLAVE_RX          (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
00389
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00395   * @{
00396   */
00397 #define SAI_FREE_PROTOCOL                 0x00000000U
00398 #define SAI_SPDIF_PROTOCOL                SAI_xCR1_PRTCFG_0
00399 #define SAI_AC97_PROTOCOL                 SAI_xCR1_PRTCFG_1
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00405   * @{
00406   */
00407 #define SAI_DATASIZE_8     SAI_xCR1_DS_1
00408 #define SAI_DATASIZE_10    (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00409 #define SAI_DATASIZE_16    SAI_xCR1_DS_2
00410 #define SAI_DATASIZE_20    (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
00411 #define SAI_DATASIZE_24    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
00412 #define SAI_DATASIZE_32    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00418   * @{
00419   */
00420 #define SAI_FIRSTBIT_MSB                  0x00000000U
00421 #define SAI_FIRSTBIT_LSB                  SAI_xCR1_LSBFIRST
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00427   * @{
00428   */
00429 #define SAI_CLOCKSTROBING_FALLINGEDGE     0U
00430 #define SAI_CLOCKSTROBING_RISINGEDGE      1U
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00436   * @{
00437   */
00438 #define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
00439 #define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00445   * @{
00446   */
00447 #define SAI_OUTPUTDRIVE_DISABLE          0x00000000U
00448 #define SAI_OUTPUTDRIVE_ENABLE           SAI_xCR1_OUTDRIV
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00454   * @{
00455   */
00456 #define SAI_MASTERDIVIDER_ENABLE         0x00000000U
00457 #define SAI_MASTERDIVIDER_DISABLE        SAI_xCR1_NODIV
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00463   * @{
00464   */
00465 #define SAI_FS_STARTFRAME                 0x00000000U
00466 #define SAI_FS_CHANNEL_IDENTIFICATION     SAI_xFRCR_FSDEF
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00472   * @{
00473   */
00474 #define SAI_FS_ACTIVE_LOW                  0x00000000U
00475 #define SAI_FS_ACTIVE_HIGH                 SAI_xFRCR_FSPOL
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00481   * @{
00482   */
00483 #define SAI_FS_FIRSTBIT                   0x00000000U
00484 #define SAI_FS_BEFOREFIRSTBIT             SAI_xFRCR_FSOFF
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00490   * @{
00491   */
00492 #define SAI_SLOTSIZE_DATASIZE             0x00000000U
00493 #define SAI_SLOTSIZE_16B                  SAI_xSLOTR_SLOTSZ_0
00494 #define SAI_SLOTSIZE_32B                  SAI_xSLOTR_SLOTSZ_1
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00500   * @{
00501   */
00502 #define SAI_SLOT_NOTACTIVE           0x00000000U
00503 #define SAI_SLOTACTIVE_0             0x00000001U
00504 #define SAI_SLOTACTIVE_1             0x00000002U
00505 #define SAI_SLOTACTIVE_2             0x00000004U
00506 #define SAI_SLOTACTIVE_3             0x00000008U
00507 #define SAI_SLOTACTIVE_4             0x00000010U
00508 #define SAI_SLOTACTIVE_5             0x00000020U
00509 #define SAI_SLOTACTIVE_6             0x00000040U
00510 #define SAI_SLOTACTIVE_7             0x00000080U
00511 #define SAI_SLOTACTIVE_8             0x00000100U
00512 #define SAI_SLOTACTIVE_9             0x00000200U
00513 #define SAI_SLOTACTIVE_10            0x00000400U
00514 #define SAI_SLOTACTIVE_11            0x00000800U
00515 #define SAI_SLOTACTIVE_12            0x00001000U
00516 #define SAI_SLOTACTIVE_13            0x00002000U
00517 #define SAI_SLOTACTIVE_14            0x00004000U
00518 #define SAI_SLOTACTIVE_15            0x00008000U
00519 #define SAI_SLOTACTIVE_ALL           0x0000FFFFU
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00525   * @{
00526   */
00527 #define SAI_STEREOMODE               0x00000000U
00528 #define SAI_MONOMODE                 SAI_xCR1_MONO
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00534   * @{
00535   */
00536 #define SAI_OUTPUT_NOTRELEASED    0x00000000U
00537 #define SAI_OUTPUT_RELEASED       SAI_xCR2_TRIS
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00543   * @{
00544   */
00545 #define SAI_FIFOTHRESHOLD_EMPTY  0x00000000U
00546 #define SAI_FIFOTHRESHOLD_1QF    SAI_xCR2_FTH_0
00547 #define SAI_FIFOTHRESHOLD_HF     SAI_xCR2_FTH_1
00548 #define SAI_FIFOTHRESHOLD_3QF    (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
00549 #define SAI_FIFOTHRESHOLD_FULL   SAI_xCR2_FTH_2
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00555   * @{
00556   */
00557 #define SAI_NOCOMPANDING                 0x00000000U
00558 #define SAI_ULAW_1CPL_COMPANDING         SAI_xCR2_COMP_1
00559 #define SAI_ALAW_1CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
00560 #define SAI_ULAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
00561 #define SAI_ALAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
00562 /**
00563   * @}
00564   */
00565
00566 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00567   * @{
00568   */
00569 #define SAI_ZERO_VALUE                     0x00000000U
00570 #define SAI_LAST_SENT_VALUE                SAI_xCR2_MUTEVAL
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00576   * @{
00577   */
00578 #define SAI_IT_OVRUDR                     SAI_xIMR_OVRUDRIE
00579 #define SAI_IT_MUTEDET                    SAI_xIMR_MUTEDETIE
00580 #define SAI_IT_WCKCFG                     SAI_xIMR_WCKCFGIE
00581 #define SAI_IT_FREQ                       SAI_xIMR_FREQIE
00582 #define SAI_IT_CNRDY                      SAI_xIMR_CNRDYIE
00583 #define SAI_IT_AFSDET                     SAI_xIMR_AFSDETIE
00584 #define SAI_IT_LFSDET                     SAI_xIMR_LFSDETIE
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00590   * @{
00591   */
00592 #define SAI_FLAG_OVRUDR                   SAI_xSR_OVRUDR
00593 #define SAI_FLAG_MUTEDET                  SAI_xSR_MUTEDET
00594 #define SAI_FLAG_WCKCFG                   SAI_xSR_WCKCFG
00595 #define SAI_FLAG_FREQ                     SAI_xSR_FREQ
00596 #define SAI_FLAG_CNRDY                    SAI_xSR_CNRDY
00597 #define SAI_FLAG_AFSDET                   SAI_xSR_AFSDET
00598 #define SAI_FLAG_LFSDET                   SAI_xSR_LFSDET
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00604   * @{
00605   */
00606 #define SAI_FIFOSTATUS_EMPTY              0x00000000U
00607 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
00608 #define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
00609 #define SAI_FIFOSTATUS_HALFFULL           0x00030000U
00610 #define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
00611 #define SAI_FIFOSTATUS_FULL               0x00050000U
00612 /**
00613   * @}
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 /* Exported macro ------------------------------------------------------------*/
00621 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00622   * @brief macros to handle interrupts and specific configurations
00623   * @{
00624   */
00625
00626 /** @brief Reset SAI handle state.
00627   * @param  __HANDLE__ specifies the SAI Handle.
00628   * @retval None
00629   */
00630 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00631 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00632                                                      (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
00633                                                      (__HANDLE__)->MspInitCallback = NULL;      \
00634                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
00635                                                    } while(0)
00636 #else
00637 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00638 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00639
00640 /** @brief  Enable the specified SAI interrupts.
00641   * @param  __HANDLE__ specifies the SAI Handle.
00642   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00643   *         This parameter can be one of the following values:
00644   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00645   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00646   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00647   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00648   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00649   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00650   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00651   * @retval None
00652   */
00653 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00654
00655 /** @brief  Disable the specified SAI interrupts.
00656   * @param  __HANDLE__ specifies the SAI Handle.
00657   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00658   *         This parameter can be one of the following values:
00659   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00660   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00661   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00662   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00663   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00664   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00665   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00666   * @retval None
00667   */
00668 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00669
00670 /** @brief  Check whether the specified SAI interrupt source is enabled or not.
00671   * @param  __HANDLE__ specifies the SAI Handle.
00672   * @param  __INTERRUPT__ specifies the SAI interrupt source to check.
00673   *         This parameter can be one of the following values:
00674   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00675   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00676   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00677   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00678   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00679   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00680   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00681   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00682   */
00683 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
00684                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00685
00686 /** @brief  Check whether the specified SAI flag is set or not.
00687   * @param  __HANDLE__ specifies the SAI Handle.
00688   * @param  __FLAG__ specifies the flag to check.
00689   *         This parameter can be one of the following values:
00690   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00691   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00692   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00693   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00694   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00695   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00696   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00697   * @retval The new state of __FLAG__ (TRUE or FALSE).
00698   */
00699 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00700
00701 /** @brief  Clear the specified SAI pending flag.
00702   * @param  __HANDLE__ specifies the SAI Handle.
00703   * @param  __FLAG__ specifies the flag to check.
00704   *          This parameter can be any combination of the following values:
00705   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00706   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00707   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00708   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00709   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00710   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00711   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00712   *
00713   * @retval None
00714   */
00715 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00716
00717 /** @brief  Enable SAI.
00718   * @param  __HANDLE__ specifies the SAI Handle.
00719   * @retval None
00720   */
00721 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00722
00723 /** @brief  Disable SAI.
00724   * @param  __HANDLE__ specifies the SAI Handle.
00725   * @retval None
00726   */
00727 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00728
00729 /**
00730   * @}
00731   */
00732
00733 /* Include SAI HAL Extension module */
00734 #include "stm32g4xx_hal_sai_ex.h"
00735
00736 /* Exported functions --------------------------------------------------------*/
00737 /** @addtogroup SAI_Exported_Functions
00738   * @{
00739   */
00740
00741 /* Initialization/de-initialization functions  ********************************/
00742 /** @addtogroup SAI_Exported_Functions_Group1
00743   * @{
00744   */
00745 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00746 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00747 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
00748 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00749 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00750
00751 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00752 /* SAI callbacks register/unregister functions ********************************/
00753 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00754                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00755                                            pSAI_CallbackTypeDef      pCallback);
00756 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00757                                              HAL_SAI_CallbackIDTypeDef CallbackID);
00758 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00759 /**
00760   * @}
00761   */
00762
00763 /* I/O operation functions  ***************************************************/
00764 /** @addtogroup SAI_Exported_Functions_Group2
00765   * @{
00766   */
00767 /* Blocking mode: Polling */
00768 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00769 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00770
00771 /* Non-Blocking mode: Interrupt */
00772 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00773 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00774
00775 /* Non-Blocking mode: DMA */
00776 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00777 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00778 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00779 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00780 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00781
00782 /* Abort function */
00783 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00784
00785 /* Mute management */
00786 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00787 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00788 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00789 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00790
00791 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00792 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00793 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00794 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00795 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00796 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00797 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00798 /**
00799   * @}
00800   */
00801
00802 /** @addtogroup SAI_Exported_Functions_Group3
00803   * @{
00804   */
00805 /* Peripheral State functions  ************************************************/
00806 HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
00807 uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
00808 /**
00809   * @}
00810   */
00811
00812 /**
00813   * @}
00814   */
00815
00816 /* Private macros ------------------------------------------------------------*/
00817 /** @defgroup SAI_Private_Macros SAI Private Macros
00818   * @{
00819   */
00820 #define IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE)
00821
00822 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00823                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00824                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00825                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00826                                                ((PROTOCOL) == SAI_PCM_SHORT))
00827
00828 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00829                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00830                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00831                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00832
00833 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00834                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00835                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00836                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00837                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00838
00839 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
00840                                               ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
00841
00842 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))
00843
00844 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
00845                                         (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
00846
00847 #define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
00848                                   ((MODE) == SAI_MODEMASTER_RX) || \
00849                                   ((MODE) == SAI_MODESLAVE_TX)  || \
00850                                   ((MODE) == SAI_MODESLAVE_RX))
00851
00852 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00853                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00854                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00855
00856 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00857                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00858                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00859                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00860                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00861                                          ((DATASIZE) == SAI_DATASIZE_32))
00862
00863 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00864                                      ((BIT) == SAI_FIRSTBIT_LSB))
00865
00866 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00867                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00868
00869 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
00870                                        ((SYNCHRO) == SAI_SYNCHRONOUS))
00871
00872 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
00873                                         ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
00874
00875 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00876                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00877
00878 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00879                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00880
00881 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
00882
00883 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00884                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00885
00886 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00887                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00888                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00889                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00890                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00891
00892 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00893                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00894                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00895                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00896                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00897
00898 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00899                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00900
00901 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00902                                        ((MODE) == SAI_STEREOMODE))
00903
00904 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00905
00906 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
00907
00908 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00909                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00910                                       ((SIZE) == SAI_SLOTSIZE_32B))
00911
00912 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
00913
00914 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00915                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00916
00917 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00918                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00919
00920 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00921                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00922
00923 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
00924
00925 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
00926
00927 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
00928
00929 /**
00930   * @}
00931   */
00932
00933 /* Private functions ---------------------------------------------------------*/
00934 /** @defgroup SAI_Private_Functions SAI Private Functions
00935   * @{
00936   */
00937
00938 /**
00939   * @}
00940   */
00941
00942 /**
00943   * @}
00944   */
00945
00946 /**
00947   * @}
00948   */
00949
00950 #ifdef __cplusplus
00951 }
00952 #endif
00953
00954 #endif /* STM32G4xx_HAL_SAI_H */
00955
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_sai_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SAI Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionality of the SAI Peripheral Controller:
00008   *           + Modify PDM microphone delays.
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32g4xx_hal.h"
00025
00026 /** @addtogroup STM32G4xx_HAL_Driver
00027   * @{
00028   */
00029 #ifdef HAL_SAI_MODULE_ENABLED
00030
00031 /** @defgroup SAIEx SAIEx
00032   * @brief SAI Extended HAL module driver
00033   * @{
00034   */
00035
00036 /* Private types -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private constants ---------------------------------------------------------*/
00039 /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
00040   * @{
00041   */
00042 #define SAI_PDM_DELAY_MASK          0x77U
00043 #define SAI_PDM_DELAY_OFFSET        8U
00044 #define SAI_PDM_RIGHT_DELAY_OFFSET  4U
00045 /**
00046   * @}
00047   */
00048
00049 /* Private macros ------------------------------------------------------------*/
00050 /* Private functions ---------------------------------------------------------*/
00051 /* Exported functions --------------------------------------------------------*/
00052 /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00053   * @{
00054   */
00055
00056 /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00057   * @brief    SAIEx control functions
00058   *
00059 @verbatim
00060  ===============================================================================
00061                  ##### Extended features functions #####
00062  ===============================================================================
00063     [..]  This section provides functions allowing to:
00064       (+) Modify PDM microphone delays
00065
00066 @endverbatim
00067   * @{
00068   */
00069
00070 /**
00071   * @brief  Configure PDM microphone delays.
00072   * @param  hsai SAI handle.
00073   * @param  pdmMicDelay Microphone delays configuration.
00074   * @retval HAL status
00075   */
00076 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
00077                                               const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
00078 {
00079   HAL_StatusTypeDef status = HAL_OK;
00080   uint32_t offset;
00081
00082   /* Check that SAI sub-block is SAI1 sub-block A */
00083   if (hsai->Instance != SAI1_Block_A)
00084   {
00085     status = HAL_ERROR;
00086   }
00087   else
00088   {
00089     /* Check microphone delay parameters */
00090     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
00091     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
00092     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
00093
00094     /* Compute offset on PDMDLY register according mic pair number */
00095     offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
00096
00097     /* Check SAI state and offset */
00098     if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
00099     {
00100       /* Reset current delays for specified microphone */
00101       SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
00102
00103       /* Apply new microphone delays */
00104       SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
00105     }
00106     else
00107     {
00108       status = HAL_ERROR;
00109     }
00110   }
00111   return status;
00112 }
00113
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 #endif /* HAL_SAI_MODULE_ENABLED */
00127 /**
00128   * @}
00129   */
00130
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sai_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_sai_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SAI_EX_H
00021 #define STM32G4xx_HAL_SAI_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SAIEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  PDM microphone delay structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.
00049                              This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00050
00051   uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.
00052                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00053
00054   uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.
00055                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00056 } SAIEx_PdmMicDelayParamTypeDef;
00057
00058 /**
00059   * @}
00060   */
00061
00062 /* Exported constants --------------------------------------------------------*/
00063 /* Exported macros -----------------------------------------------------------*/
00064 /* Exported functions --------------------------------------------------------*/
00065 /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00066   * @{
00067   */
00068
00069 /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00070   * @{
00071   */
00072 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
00073                                               const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Private macros ------------------------------------------------------------*/
00083 /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
00084   * @{
00085   */
00086 #define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 #ifdef __cplusplus
00100 }
00101 #endif
00102
00103 #endif /* STM32G4xx_HAL_SAI_EX_H */
00104
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_smartcard.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the SMARTCARD peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028   [..]
00029     The SMARTCARD HAL driver can be used as follows:
00030
00031     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00032     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00033     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00034         (++) Enable the USARTx interface clock.
00035         (++) USART pins configuration:
00036              (+++) Enable the clock for the USART GPIOs.
00037              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00038         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00039              and HAL_SMARTCARD_Receive_IT() APIs):
00040              (+++) Configure the USARTx interrupt priority.
00041              (+++) Enable the NVIC USART IRQ handle.
00042         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00043              and HAL_SMARTCARD_Receive_DMA() APIs):
00044              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00045              (+++) Enable the DMAx interface clock.
00046              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00047              (+++) Configure the DMA Tx/Rx channel.
00048              (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00049              (+++) Configure the priority and enable the NVIC for the transfer complete
00050                    interrupt on the DMA Tx/Rx channel.
00051
00052     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00053         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00054         error enabling or disabling in the hsmartcard handle Init structure.
00055
00056     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00057         in the hsmartcard handle AdvancedInit structure.
00058
00059     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00060         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00061              by calling the customized HAL_SMARTCARD_MspInit() API.
00062         [..]
00063         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00064              RXNE interrupt and Error Interrupts) will be managed using the macros
00065              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00066
00067     [..]
00068     [..] Three operation modes are available within this driver :
00069
00070      *** Polling mode IO operation ***
00071      =================================
00072      [..]
00073        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00074        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00075
00076      *** Interrupt mode IO operation ***
00077      ===================================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00080        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00083        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00087
00088      *** DMA mode IO operation ***
00089      ==============================
00090      [..]
00091        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00092        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00093             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00094        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00095        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00096             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00097        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00098             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00099
00100      *** SMARTCARD HAL driver macros list ***
00101      ========================================
00102      [..]
00103        Below the list of most used macros in SMARTCARD HAL driver.
00104
00105        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00106        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00107        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00108        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00109        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00110
00111      [..]
00112        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00113
00114     ##### Callback registration #####
00115     ==================================
00116
00117     [..]
00118     The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
00119     allows the user to configure dynamically the driver callbacks.
00120
00121     [..]
00122     Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
00123     Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
00124     (+) TxCpltCallback            : Tx Complete Callback.
00125     (+) RxCpltCallback            : Rx Complete Callback.
00126     (+) ErrorCallback             : Error Callback.
00127     (+) AbortCpltCallback         : Abort Complete Callback.
00128     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00129     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00130     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00131     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00132     (+) MspInitCallback           : SMARTCARD MspInit.
00133     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00134     This function takes as parameters the HAL peripheral handle, the Callback ID
00135     and a pointer to the user callback function.
00136
00137     [..]
00138     Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
00139     weak function.
00140     HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00141     and the Callback ID.
00142     This function allows to reset following callbacks:
00143     (+) TxCpltCallback            : Tx Complete Callback.
00144     (+) RxCpltCallback            : Rx Complete Callback.
00145     (+) ErrorCallback             : Error Callback.
00146     (+) AbortCpltCallback         : Abort Complete Callback.
00147     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00148     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00149     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00150     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00151     (+) MspInitCallback           : SMARTCARD MspInit.
00152     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00153
00154     [..]
00155     By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
00156     all callbacks are set to the corresponding weak functions:
00157     examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
00158     Exception done for MspInit and MspDeInit functions that are respectively
00159     reset to the legacy weak functions in the HAL_SMARTCARD_Init()
00160     and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
00161     If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
00162     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00163
00164     [..]
00165     Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
00166     Exception done MspInit/MspDeInit that can be registered/unregistered
00167     in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
00168     MspInit/DeInit callbacks can be used during the Init/DeInit.
00169     In that case first register the MspInit/MspDeInit user callbacks
00170     using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
00171     or HAL_SMARTCARD_Init() function.
00172
00173     [..]
00174     When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
00175     not defined, the callback registration feature is not available
00176     and weak callbacks are used.
00177
00178
00179   @endverbatim
00180   ******************************************************************************
00181   */
00182
00183 /* Includes ------------------------------------------------------------------*/
00184 #include "stm32g4xx_hal.h"
00185
00186 /** @addtogroup STM32G4xx_HAL_Driver
00187   * @{
00188   */
00189
00190 /** @defgroup SMARTCARD SMARTCARD
00191   * @brief HAL SMARTCARD module driver
00192   * @{
00193   */
00194
00195 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00196
00197 /* Private typedef -----------------------------------------------------------*/
00198 /* Private define ------------------------------------------------------------*/
00199 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00200   * @{
00201   */
00202 #define SMARTCARD_TEACK_REACK_TIMEOUT  1000U       /*!< SMARTCARD TX or RX enable acknowledge time-out value */
00203
00204 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
00205                                       USART_CR1_RE | USART_CR1_OVER8| \
00206                                       USART_CR1_FIFOEN))  /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00207
00208 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
00209                                           USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00210
00211 #define USART_CR2_FIELDS  ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
00212                                       USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00213
00214 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
00215                                       USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00216
00217 #define USART_BRR_MIN  0x10U        /*!< USART BRR minimum authorized value */
00218
00219 #define USART_BRR_MAX  0x0000FFFFU  /*!< USART BRR maximum authorized value */
00220 /**
00221   * @}
00222   */
00223
00224 /* Private macros ------------------------------------------------------------*/
00225 /* Private variables ---------------------------------------------------------*/
00226 /* Private function prototypes -----------------------------------------------*/
00227 /** @addtogroup SMARTCARD_Private_Functions
00228   * @{
00229   */
00230 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00231 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
00232 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00233 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00234 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00235 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00236 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
00237                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00238 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00239 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00240 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00241 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00242 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00243 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00244 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00245 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00246 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00247 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00248 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00249 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00250 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00251 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00252 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00253 /**
00254   * @}
00255   */
00256
00257 /* Exported functions --------------------------------------------------------*/
00258
00259 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00260   * @{
00261   */
00262
00263 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00264   * @brief    Initialization and Configuration functions
00265   *
00266 @verbatim
00267   ==============================================================================
00268               ##### Initialization and Configuration functions #####
00269   ==============================================================================
00270   [..]
00271   This subsection provides a set of functions allowing to initialize the USARTx
00272   associated to the SmartCard.
00273   (+) These parameters can be configured:
00274       (++) Baud Rate
00275       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00276       (++) Receiver/transmitter modes
00277       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00278       (++) Prescaler value
00279       (++) Guard bit time
00280       (++) NACK enabling or disabling on transmission error
00281
00282   (+) The following advanced features can be configured as well:
00283       (++) TX and/or RX pin level inversion
00284       (++) data logical level inversion
00285       (++) RX and TX pins swap
00286       (++) RX overrun detection disabling
00287       (++) DMA disabling on RX error
00288       (++) MSB first on communication line
00289       (++) Time out enabling (and if activated, timeout value)
00290       (++) Block length
00291       (++) Auto-retry counter
00292   [..]
00293   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00294   (details for the procedures are available in reference manual).
00295
00296 @endverbatim
00297
00298   The USART frame format is given in the following table:
00299
00300     Table 1. USART frame format.
00301     +---------------------------------------------------------------+
00302     | M1M0 bits |  PCE bit  |            USART frame                |
00303     |-----------------------|---------------------------------------|
00304     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00305     +---------------------------------------------------------------+
00306
00307
00308   * @{
00309   */
00310
00311 /**
00312   * @brief  Initialize the SMARTCARD mode according to the specified
00313   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00314   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00315   *                    the configuration information for the specified SMARTCARD module.
00316   * @retval HAL status
00317   */
00318 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00319 {
00320   /* Check the SMARTCARD handle allocation */
00321   if (hsmartcard == NULL)
00322   {
00323     return HAL_ERROR;
00324   }
00325
00326   /* Check the USART associated to the SMARTCARD handle */
00327   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00328
00329   if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00330   {
00331     /* Allocate lock resource and initialize it */
00332     hsmartcard->Lock = HAL_UNLOCKED;
00333
00334 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00335     SMARTCARD_InitCallbacksToDefault(hsmartcard);
00336
00337     if (hsmartcard->MspInitCallback == NULL)
00338     {
00339       hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00340     }
00341
00342     /* Init the low level hardware */
00343     hsmartcard->MspInitCallback(hsmartcard);
00344 #else
00345     /* Init the low level hardware : GPIO, CLOCK */
00346     HAL_SMARTCARD_MspInit(hsmartcard);
00347 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00348   }
00349
00350   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00351
00352   /* Disable the Peripheral to set smartcard mode */
00353   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00354
00355   /* In SmartCard mode, the following bits must be kept cleared:
00356   - LINEN in the USART_CR2 register,
00357   - HDSEL and IREN  bits in the USART_CR3 register.*/
00358   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00359   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00360
00361   /* set the USART in SMARTCARD mode */
00362   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00363
00364   /* Set the SMARTCARD Communication parameters */
00365   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00366   {
00367     return HAL_ERROR;
00368   }
00369
00370   /* Set the SMARTCARD transmission completion indication */
00371   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00372
00373   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00374   {
00375     SMARTCARD_AdvFeatureConfig(hsmartcard);
00376   }
00377
00378   /* Enable the Peripheral */
00379   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00380
00381   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00382   return (SMARTCARD_CheckIdleState(hsmartcard));
00383 }
00384
00385 /**
00386   * @brief  DeInitialize the SMARTCARD peripheral.
00387   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00388   *                    the configuration information for the specified SMARTCARD module.
00389   * @retval HAL status
00390   */
00391 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00392 {
00393   /* Check the SMARTCARD handle allocation */
00394   if (hsmartcard == NULL)
00395   {
00396     return HAL_ERROR;
00397   }
00398
00399   /* Check the USART/UART associated to the SMARTCARD handle */
00400   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00401
00402   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00403
00404   /* Disable the Peripheral */
00405   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00406
00407   WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
00408   WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
00409   WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
00410   WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
00411   WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
00412
00413   /* DeInit the low level hardware */
00414 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00415   if (hsmartcard->MspDeInitCallback == NULL)
00416   {
00417     hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00418   }
00419   /* DeInit the low level hardware */
00420   hsmartcard->MspDeInitCallback(hsmartcard);
00421 #else
00422   HAL_SMARTCARD_MspDeInit(hsmartcard);
00423 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00424
00425   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00426   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00427   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00428
00429   /* Process Unlock */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Initialize the SMARTCARD MSP.
00437   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00438   *                    the configuration information for the specified SMARTCARD module.
00439   * @retval None
00440   */
00441 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00442 {
00443   /* Prevent unused argument(s) compilation warning */
00444   UNUSED(hsmartcard);
00445
00446   /* NOTE : This function should not be modified, when the callback is needed,
00447             the HAL_SMARTCARD_MspInit can be implemented in the user file
00448    */
00449 }
00450
00451 /**
00452   * @brief  DeInitialize the SMARTCARD MSP.
00453   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00454   *                    the configuration information for the specified SMARTCARD module.
00455   * @retval None
00456   */
00457 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00458 {
00459   /* Prevent unused argument(s) compilation warning */
00460   UNUSED(hsmartcard);
00461
00462   /* NOTE : This function should not be modified, when the callback is needed,
00463             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00464    */
00465 }
00466
00467 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00468 /**
00469   * @brief  Register a User SMARTCARD Callback
00470   *         To be used to override the weak predefined callback
00471   * @note   The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
00472   *         in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
00473   *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
00474   * @param  hsmartcard smartcard handle
00475   * @param  CallbackID ID of the callback to be registered
00476   *         This parameter can be one of the following values:
00477   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00478   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00479   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00480   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00481   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00482   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00483   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00484   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00485   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00486   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00487   * @param  pCallback pointer to the Callback function
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00491                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
00492                                                  pSMARTCARD_CallbackTypeDef pCallback)
00493 {
00494   HAL_StatusTypeDef status = HAL_OK;
00495
00496   if (pCallback == NULL)
00497   {
00498     /* Update the error code */
00499     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00500
00501     return HAL_ERROR;
00502   }
00503
00504   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00505   {
00506     switch (CallbackID)
00507     {
00508
00509       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00510         hsmartcard->TxCpltCallback = pCallback;
00511         break;
00512
00513       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00514         hsmartcard->RxCpltCallback = pCallback;
00515         break;
00516
00517       case HAL_SMARTCARD_ERROR_CB_ID :
00518         hsmartcard->ErrorCallback = pCallback;
00519         break;
00520
00521       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00522         hsmartcard->AbortCpltCallback = pCallback;
00523         break;
00524
00525       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00526         hsmartcard->AbortTransmitCpltCallback = pCallback;
00527         break;
00528
00529       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00530         hsmartcard->AbortReceiveCpltCallback = pCallback;
00531         break;
00532
00533       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00534         hsmartcard->RxFifoFullCallback = pCallback;
00535         break;
00536
00537       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00538         hsmartcard->TxFifoEmptyCallback = pCallback;
00539         break;
00540
00541       case HAL_SMARTCARD_MSPINIT_CB_ID :
00542         hsmartcard->MspInitCallback = pCallback;
00543         break;
00544
00545       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00546         hsmartcard->MspDeInitCallback = pCallback;
00547         break;
00548
00549       default :
00550         /* Update the error code */
00551         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00552
00553         /* Return error status */
00554         status =  HAL_ERROR;
00555         break;
00556     }
00557   }
00558   else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00559   {
00560     switch (CallbackID)
00561     {
00562       case HAL_SMARTCARD_MSPINIT_CB_ID :
00563         hsmartcard->MspInitCallback = pCallback;
00564         break;
00565
00566       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00567         hsmartcard->MspDeInitCallback = pCallback;
00568         break;
00569
00570       default :
00571         /* Update the error code */
00572         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00573
00574         /* Return error status */
00575         status =  HAL_ERROR;
00576         break;
00577     }
00578   }
00579   else
00580   {
00581     /* Update the error code */
00582     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00583
00584     /* Return error status */
00585     status =  HAL_ERROR;
00586   }
00587
00588   return status;
00589 }
00590
00591 /**
00592   * @brief  Unregister an SMARTCARD callback
00593   *         SMARTCARD callback is redirected to the weak predefined callback
00594   * @note   The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
00595   *         in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
00596   *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
00597   * @param  hsmartcard smartcard handle
00598   * @param  CallbackID ID of the callback to be unregistered
00599   *         This parameter can be one of the following values:
00600   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00601   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00602   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00603   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00604   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00605   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00606   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00607   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00608   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00609   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00613                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
00614 {
00615   HAL_StatusTypeDef status = HAL_OK;
00616
00617   if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
00618   {
00619     switch (CallbackID)
00620     {
00621       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00622         hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                 /* Legacy weak TxCpltCallback */
00623         break;
00624
00625       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00626         hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                 /* Legacy weak RxCpltCallback */
00627         break;
00628
00629       case HAL_SMARTCARD_ERROR_CB_ID :
00630         hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                   /* Legacy weak ErrorCallback  */
00631         break;
00632
00633       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00634         hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;           /* Legacy weak AbortCpltCallback */
00635         break;
00636
00637       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00638         hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
00639                                                                                             AbortTransmitCpltCallback*/
00640         break;
00641
00642       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00643         hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
00644                                                                                            AbortReceiveCpltCallback */
00645         break;
00646
00647       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00648         hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback */
00649         break;
00650
00651       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00652         hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback;    /* Legacy weak TxFifoEmptyCallback */
00653         break;
00654
00655       case HAL_SMARTCARD_MSPINIT_CB_ID :
00656         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                       /* Legacy weak MspInitCallback  */
00657         break;
00658
00659       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00660         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                   /* Legacy weak MspDeInitCallback */
00661         break;
00662
00663       default :
00664         /* Update the error code */
00665         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00666
00667         /* Return error status */
00668         status =  HAL_ERROR;
00669         break;
00670     }
00671   }
00672   else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
00673   {
00674     switch (CallbackID)
00675     {
00676       case HAL_SMARTCARD_MSPINIT_CB_ID :
00677         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00678         break;
00679
00680       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00681         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00682         break;
00683
00684       default :
00685         /* Update the error code */
00686         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00687
00688         /* Return error status */
00689         status =  HAL_ERROR;
00690         break;
00691     }
00692   }
00693   else
00694   {
00695     /* Update the error code */
00696     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00697
00698     /* Return error status */
00699     status =  HAL_ERROR;
00700   }
00701
00702   return status;
00703 }
00704 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00705
00706 /**
00707   * @}
00708   */
00709
00710 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00711   * @brief    SMARTCARD Transmit and Receive functions
00712   *
00713 @verbatim
00714   ==============================================================================
00715                          ##### IO operation functions #####
00716   ==============================================================================
00717   [..]
00718     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00719
00720   [..]
00721     Smartcard is a single wire half duplex communication protocol.
00722     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00723     defined in the ISO 7816-3 standard. The USART should be configured as:
00724     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00725     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00726
00727   [..]
00728     (#) There are two modes of transfer:
00729         (##) Blocking mode: The communication is performed in polling mode.
00730              The HAL status of all data processing is returned by the same function
00731              after finishing transfer.
00732         (##) Non-Blocking mode: The communication is performed using Interrupts
00733              or DMA, the relevant API's return the HAL status.
00734              The end of the data processing will be indicated through the
00735              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00736              using DMA mode.
00737         (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00738              will be executed respectively at the end of the Transmit or Receive process
00739              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00740              error is detected.
00741
00742     (#) Blocking mode APIs are :
00743         (##) HAL_SMARTCARD_Transmit()
00744         (##) HAL_SMARTCARD_Receive()
00745
00746     (#) Non Blocking mode APIs with Interrupt are :
00747         (##) HAL_SMARTCARD_Transmit_IT()
00748         (##) HAL_SMARTCARD_Receive_IT()
00749         (##) HAL_SMARTCARD_IRQHandler()
00750
00751     (#) Non Blocking mode functions with DMA are :
00752         (##) HAL_SMARTCARD_Transmit_DMA()
00753         (##) HAL_SMARTCARD_Receive_DMA()
00754
00755     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00756         (##) HAL_SMARTCARD_TxCpltCallback()
00757         (##) HAL_SMARTCARD_RxCpltCallback()
00758         (##) HAL_SMARTCARD_ErrorCallback()
00759
00760   [..]
00761     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00762         (##) HAL_SMARTCARD_Abort()
00763         (##) HAL_SMARTCARD_AbortTransmit()
00764         (##) HAL_SMARTCARD_AbortReceive()
00765         (##) HAL_SMARTCARD_Abort_IT()
00766         (##) HAL_SMARTCARD_AbortTransmit_IT()
00767         (##) HAL_SMARTCARD_AbortReceive_IT()
00768
00769     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
00770         a set of Abort Complete Callbacks are provided:
00771         (##) HAL_SMARTCARD_AbortCpltCallback()
00772         (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
00773         (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
00774
00775     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00776         Errors are handled as follows :
00777        (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00778            to be evaluated by user : this concerns Frame Error,
00779            Parity Error or Noise Error in Interrupt mode reception .
00780            Received character is then retrieved and stored in Rx buffer,
00781            Error code is set to allow user to identify error type,
00782            and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00783            If user wants to abort it, Abort services should be called by user.
00784        (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00785            This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
00786            mode reception and all errors in DMA mode.
00787            Error code is set to allow user to identify error type,
00788            and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00789
00790 @endverbatim
00791   * @{
00792   */
00793
00794 /**
00795   * @brief  Send an amount of data in blocking mode.
00796   * @note   When FIFO mode is enabled, writing a data in the TDR register adds one
00797   *         data to the TXFIFO. Write operations to the TDR register are performed
00798   *         when TXFNF flag is set. From hardware perspective, TXFNF flag and
00799   *         TXE are mapped on the same bit-field.
00800   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00801   *                    the configuration information for the specified SMARTCARD module.
00802   * @param  pData pointer to data buffer.
00803   * @param  Size amount of data to be sent.
00804   * @param  Timeout  Timeout duration.
00805   * @retval HAL status
00806   */
00807 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
00808                                          uint32_t Timeout)
00809 {
00810   uint32_t tickstart;
00811   const uint8_t  *ptmpdata = pData;
00812
00813   /* Check that a Tx process is not already ongoing */
00814   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00815   {
00816     if ((ptmpdata == NULL) || (Size == 0U))
00817     {
00818       return  HAL_ERROR;
00819     }
00820
00821     /* Process Locked */
00822     __HAL_LOCK(hsmartcard);
00823
00824     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00825
00826     /* Init tickstart for timeout management */
00827     tickstart = HAL_GetTick();
00828
00829     /* Disable the Peripheral first to update mode for TX master */
00830     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00831
00832     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
00833        the bidirectional line to detect a NACK signal in case of parity error.
00834        Therefore, the receiver block must be enabled as well (RE bit must be set). */
00835     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
00836         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00837     {
00838       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00839     }
00840     /* Enable Tx */
00841     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00842
00843     /* Enable the Peripheral */
00844     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00845
00846     /* Perform a TX/RX FIFO Flush */
00847     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
00848
00849     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00850     hsmartcard->TxXferSize = Size;
00851     hsmartcard->TxXferCount = Size;
00852
00853     while (hsmartcard->TxXferCount > 0U)
00854     {
00855       hsmartcard->TxXferCount--;
00856       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00857       {
00858         return HAL_TIMEOUT;
00859       }
00860       hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
00861       ptmpdata++;
00862     }
00863     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
00864                                          tickstart, Timeout) != HAL_OK)
00865     {
00866       return HAL_TIMEOUT;
00867     }
00868
00869     /* Disable the Peripheral first to update mode */
00870     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00871     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
00872         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00873     {
00874       /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
00875          for Transmit phase. Disable this receiver block. */
00876       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00877     }
00878     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00879         || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00880     {
00881       /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
00882       __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
00883     }
00884     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00885
00886     /* At end of Tx process, restore hsmartcard->gState to Ready */
00887     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00888
00889     /* Process Unlocked */
00890     __HAL_UNLOCK(hsmartcard);
00891
00892     return HAL_OK;
00893   }
00894   else
00895   {
00896     return HAL_BUSY;
00897   }
00898 }
00899
00900 /**
00901   * @brief  Receive an amount of data in blocking mode.
00902   * @note   When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00903   *         is not empty. Read operations from the RDR register are performed when
00904   *         RXFNE flag is set. From hardware perspective, RXFNE flag and
00905   *         RXNE are mapped on the same bit-field.
00906   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00907   *                    the configuration information for the specified SMARTCARD module.
00908   * @param  pData pointer to data buffer.
00909   * @param  Size amount of data to be received.
00910   * @param  Timeout Timeout duration.
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
00914                                         uint32_t Timeout)
00915 {
00916   uint32_t tickstart;
00917   uint8_t  *ptmpdata = pData;
00918
00919   /* Check that a Rx process is not already ongoing */
00920   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00921   {
00922     if ((ptmpdata == NULL) || (Size == 0U))
00923     {
00924       return  HAL_ERROR;
00925     }
00926
00927     /* Process Locked */
00928     __HAL_LOCK(hsmartcard);
00929
00930     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00931     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00932
00933     /* Init tickstart for timeout management */
00934     tickstart = HAL_GetTick();
00935
00936     hsmartcard->RxXferSize = Size;
00937     hsmartcard->RxXferCount = Size;
00938
00939     /* Check the remain data to be received */
00940     while (hsmartcard->RxXferCount > 0U)
00941     {
00942       hsmartcard->RxXferCount--;
00943
00944       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00945       {
00946         return HAL_TIMEOUT;
00947       }
00948       *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00949       ptmpdata++;
00950     }
00951
00952     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00953     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00954
00955     /* Process Unlocked */
00956     __HAL_UNLOCK(hsmartcard);
00957
00958     return HAL_OK;
00959   }
00960   else
00961   {
00962     return HAL_BUSY;
00963   }
00964 }
00965
00966 /**
00967   * @brief  Send an amount of data in interrupt mode.
00968   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
00969   *         USART_TDR register is empty, i.e one interrupt per data to transmit.
00970   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
00971   *         TXFIFO threshold reached. In that case the interrupt rate depends on
00972   *         TXFIFO threshold configuration.
00973   * @note   This function sets the hsmartcard->TxIsr function pointer according to
00974   *         the FIFO mode (data transmission processing depends on FIFO mode).
00975   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00976   *                    the configuration information for the specified SMARTCARD module.
00977   * @param  pData pointer to data buffer.
00978   * @param  Size amount of data to be sent.
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
00982 {
00983   /* Check that a Tx process is not already ongoing */
00984   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00985   {
00986     if ((pData == NULL) || (Size == 0U))
00987     {
00988       return HAL_ERROR;
00989     }
00990
00991     /* Process Locked */
00992     __HAL_LOCK(hsmartcard);
00993
00994     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00995     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00996
00997     hsmartcard->pTxBuffPtr  = pData;
00998     hsmartcard->TxXferSize  = Size;
00999     hsmartcard->TxXferCount = Size;
01000     hsmartcard->TxISR       = NULL;
01001
01002     /* Disable the Peripheral first to update mode for TX master */
01003     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01004
01005     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
01006        the bidirectional line to detect a NACK signal in case of parity error.
01007        Therefore, the receiver block must be enabled as well (RE bit must be set). */
01008     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
01009         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
01010     {
01011       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01012     }
01013     /* Enable Tx */
01014     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01015
01016     /* Enable the Peripheral */
01017     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01018
01019     /* Perform a TX/RX FIFO Flush */
01020     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
01021
01022     /* Configure Tx interrupt processing */
01023     if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
01024     {
01025       /* Set the Tx ISR function pointer */
01026       hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
01027
01028       /* Process Unlocked */
01029       __HAL_UNLOCK(hsmartcard);
01030
01031       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01032       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01033
01034       /* Enable the TX FIFO threshold interrupt */
01035       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01036     }
01037     else
01038     {
01039       /* Set the Tx ISR function pointer */
01040       hsmartcard->TxISR = SMARTCARD_TxISR;
01041
01042       /* Process Unlocked */
01043       __HAL_UNLOCK(hsmartcard);
01044
01045       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01046       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01047
01048       /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
01049       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01050     }
01051
01052     return HAL_OK;
01053   }
01054   else
01055   {
01056     return HAL_BUSY;
01057   }
01058 }
01059
01060 /**
01061   * @brief  Receive an amount of data in interrupt mode.
01062   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
01063   *         USART_RDR register can be read, i.e one interrupt per data to receive.
01064   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
01065   *         RXFIFO threshold reached. In that case the interrupt rate depends on
01066   *         RXFIFO threshold configuration.
01067   * @note   This function sets the hsmartcard->RxIsr function pointer according to
01068   *         the FIFO mode (data reception processing depends on FIFO mode).
01069   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01070   *                    the configuration information for the specified SMARTCARD module.
01071   * @param  pData pointer to data buffer.
01072   * @param  Size amount of data to be received.
01073   * @retval HAL status
01074   */
01075 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01076 {
01077   /* Check that a Rx process is not already ongoing */
01078   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01079   {
01080     if ((pData == NULL) || (Size == 0U))
01081     {
01082       return HAL_ERROR;
01083     }
01084
01085     /* Process Locked */
01086     __HAL_LOCK(hsmartcard);
01087
01088     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01089     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01090
01091     hsmartcard->pRxBuffPtr = pData;
01092     hsmartcard->RxXferSize = Size;
01093     hsmartcard->RxXferCount = Size;
01094
01095     /* Configure Rx interrupt processing */
01096     if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
01097     {
01098       /* Set the Rx ISR function pointer */
01099       hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
01100
01101       /* Process Unlocked */
01102       __HAL_UNLOCK(hsmartcard);
01103
01104       /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
01105       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01106       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
01107     }
01108     else
01109     {
01110       /* Set the Rx ISR function pointer */
01111       hsmartcard->RxISR = SMARTCARD_RxISR;
01112
01113       /* Process Unlocked */
01114       __HAL_UNLOCK(hsmartcard);
01115
01116       /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
01117       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01118     }
01119
01120     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01121     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01122
01123     return HAL_OK;
01124   }
01125   else
01126   {
01127     return HAL_BUSY;
01128   }
01129 }
01130
01131 /**
01132   * @brief  Send an amount of data in DMA mode.
01133   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01134   *                    the configuration information for the specified SMARTCARD module.
01135   * @param  pData pointer to data buffer.
01136   * @param  Size amount of data to be sent.
01137   * @retval HAL status
01138   */
01139 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
01140 {
01141   /* Check that a Tx process is not already ongoing */
01142   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01143   {
01144     if ((pData == NULL) || (Size == 0U))
01145     {
01146       return HAL_ERROR;
01147     }
01148
01149     /* Process Locked */
01150     __HAL_LOCK(hsmartcard);
01151
01152     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
01153
01154     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01155     hsmartcard->pTxBuffPtr = pData;
01156     hsmartcard->TxXferSize = Size;
01157     hsmartcard->TxXferCount = Size;
01158
01159     /* Disable the Peripheral first to update mode for TX master */
01160     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01161
01162     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
01163        the bidirectional line to detect a NACK signal in case of parity error.
01164        Therefore, the receiver block must be enabled as well (RE bit must be set). */
01165     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
01166         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
01167     {
01168       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01169     }
01170     /* Enable Tx */
01171     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01172
01173     /* Enable the Peripheral */
01174     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01175
01176     /* Perform a TX/RX FIFO Flush */
01177     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
01178
01179     /* Set the SMARTCARD DMA transfer complete callback */
01180     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
01181
01182     /* Set the SMARTCARD error callback */
01183     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
01184
01185     /* Set the DMA abort callback */
01186     hsmartcard->hdmatx->XferAbortCallback = NULL;
01187
01188     /* Enable the SMARTCARD transmit DMA channel */
01189     if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
01190                          Size) == HAL_OK)
01191     {
01192       /* Clear the TC flag in the ICR register */
01193       CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
01194
01195       /* Process Unlocked */
01196       __HAL_UNLOCK(hsmartcard);
01197
01198       /* Enable the UART Error Interrupt: (Frame error) */
01199       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01200
01201       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01202          in the SMARTCARD associated USART CR3 register */
01203       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01204
01205       return HAL_OK;
01206     }
01207     else
01208     {
01209       /* Set error code to DMA */
01210       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01211
01212       /* Process Unlocked */
01213       __HAL_UNLOCK(hsmartcard);
01214
01215       /* Restore hsmartcard->State to ready */
01216       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01217
01218       return HAL_ERROR;
01219     }
01220   }
01221   else
01222   {
01223     return HAL_BUSY;
01224   }
01225 }
01226
01227 /**
01228   * @brief  Receive an amount of data in DMA mode.
01229   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01230   *                    the configuration information for the specified SMARTCARD module.
01231   * @param  pData pointer to data buffer.
01232   * @param  Size amount of data to be received.
01233   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
01234   *         the received data contain the parity bit (MSB position).
01235   * @retval HAL status
01236   */
01237 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01238 {
01239   /* Check that a Rx process is not already ongoing */
01240   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01241   {
01242     if ((pData == NULL) || (Size == 0U))
01243     {
01244       return HAL_ERROR;
01245     }
01246
01247     /* Process Locked */
01248     __HAL_LOCK(hsmartcard);
01249
01250     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01251     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01252
01253     hsmartcard->pRxBuffPtr = pData;
01254     hsmartcard->RxXferSize = Size;
01255
01256     /* Set the SMARTCARD DMA transfer complete callback */
01257     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
01258
01259     /* Set the SMARTCARD DMA error callback */
01260     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
01261
01262     /* Set the DMA abort callback */
01263     hsmartcard->hdmarx->XferAbortCallback = NULL;
01264
01265     /* Enable the DMA channel */
01266     if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
01267                          Size) == HAL_OK)
01268     {
01269       /* Process Unlocked */
01270       __HAL_UNLOCK(hsmartcard);
01271
01272       /* Enable the SMARTCARD Parity Error Interrupt */
01273       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01274
01275       /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01276       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01277
01278       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01279          in the SMARTCARD associated USART CR3 register */
01280       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01281
01282       return HAL_OK;
01283     }
01284     else
01285     {
01286       /* Set error code to DMA */
01287       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01288
01289       /* Process Unlocked */
01290       __HAL_UNLOCK(hsmartcard);
01291
01292       /* Restore hsmartcard->State to ready */
01293       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01294
01295       return HAL_ERROR;
01296     }
01297   }
01298   else
01299   {
01300     return HAL_BUSY;
01301   }
01302 }
01303
01304 /**
01305   * @brief  Abort ongoing transfers (blocking mode).
01306   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01307   *                    the configuration information for the specified SMARTCARD module.
01308   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01309   *         This procedure performs following operations :
01310   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01311   *           - Disable the DMA transfer in the peripheral register (if enabled)
01312   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01313   *           - Set handle State to READY
01314   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01315   * @retval HAL status
01316   */
01317 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
01318 {
01319   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
01320      ERR (Frame error, noise error, overrun error) interrupts */
01321   CLEAR_BIT(hsmartcard->Instance->CR1,
01322             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01323              USART_CR1_EOBIE));
01324   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01325
01326   /* Disable the SMARTCARD DMA Tx request if enabled */
01327   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01328   {
01329     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01330
01331     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01332     if (hsmartcard->hdmatx != NULL)
01333     {
01334       /* Set the SMARTCARD DMA Abort callback to Null.
01335          No call back execution at end of DMA abort procedure */
01336       hsmartcard->hdmatx->XferAbortCallback = NULL;
01337
01338       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01339       {
01340         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01341         {
01342           /* Set error code to DMA */
01343           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01344
01345           return HAL_TIMEOUT;
01346         }
01347       }
01348     }
01349   }
01350
01351   /* Disable the SMARTCARD DMA Rx request if enabled */
01352   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01353   {
01354     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01355
01356     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01357     if (hsmartcard->hdmarx != NULL)
01358     {
01359       /* Set the SMARTCARD DMA Abort callback to Null.
01360          No call back execution at end of DMA abort procedure */
01361       hsmartcard->hdmarx->XferAbortCallback = NULL;
01362
01363       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01364       {
01365         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01366         {
01367           /* Set error code to DMA */
01368           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01369
01370           return HAL_TIMEOUT;
01371         }
01372       }
01373     }
01374   }
01375
01376   /* Reset Tx and Rx transfer counters */
01377   hsmartcard->TxXferCount = 0U;
01378   hsmartcard->RxXferCount = 0U;
01379
01380   /* Clear the Error flags in the ICR register */
01381   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01382                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
01383                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01384
01385   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01386   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01387   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01388
01389   /* Reset Handle ErrorCode to No Error */
01390   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01391
01392   return HAL_OK;
01393 }
01394
01395 /**
01396   * @brief  Abort ongoing Transmit transfer (blocking mode).
01397   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01398   *                    the configuration information for the specified SMARTCARD module.
01399   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01400   *         This procedure performs following operations :
01401   *           - Disable SMARTCARD Interrupts (Tx)
01402   *           - Disable the DMA transfer in the peripheral register (if enabled)
01403   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01404   *           - Set handle State to READY
01405   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01406   * @retval HAL status
01407   */
01408 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
01409 {
01410   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01411   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01412   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01413
01414   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01415   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01416   {
01417     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01418     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01419   }
01420
01421   /* Disable the SMARTCARD DMA Tx request if enabled */
01422   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01423   {
01424     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01425
01426     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01427     if (hsmartcard->hdmatx != NULL)
01428     {
01429       /* Set the SMARTCARD DMA Abort callback to Null.
01430          No call back execution at end of DMA abort procedure */
01431       hsmartcard->hdmatx->XferAbortCallback = NULL;
01432
01433       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01434       {
01435         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01436         {
01437           /* Set error code to DMA */
01438           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01439
01440           return HAL_TIMEOUT;
01441         }
01442       }
01443     }
01444   }
01445
01446   /* Reset Tx transfer counter */
01447   hsmartcard->TxXferCount = 0U;
01448
01449   /* Clear the Error flags in the ICR register */
01450   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01451
01452   /* Restore hsmartcard->gState to Ready */
01453   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01454
01455   return HAL_OK;
01456 }
01457
01458 /**
01459   * @brief  Abort ongoing Receive transfer (blocking mode).
01460   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01461   *                    the configuration information for the specified SMARTCARD module.
01462   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01463   *         This procedure performs following operations :
01464   *           - Disable SMARTCARD Interrupts (Rx)
01465   *           - Disable the DMA transfer in the peripheral register (if enabled)
01466   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01467   *           - Set handle State to READY
01468   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01469   * @retval HAL status
01470   */
01471 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
01472 {
01473   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01474   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
01475                                         USART_CR1_EOBIE));
01476   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01477
01478   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01479   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01480   {
01481     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01482     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01483   }
01484
01485   /* Disable the SMARTCARD DMA Rx request if enabled */
01486   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01487   {
01488     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01489
01490     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01491     if (hsmartcard->hdmarx != NULL)
01492     {
01493       /* Set the SMARTCARD DMA Abort callback to Null.
01494          No call back execution at end of DMA abort procedure */
01495       hsmartcard->hdmarx->XferAbortCallback = NULL;
01496
01497       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01498       {
01499         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01500         {
01501           /* Set error code to DMA */
01502           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01503
01504           return HAL_TIMEOUT;
01505         }
01506       }
01507     }
01508   }
01509
01510   /* Reset Rx transfer counter */
01511   hsmartcard->RxXferCount = 0U;
01512
01513   /* Clear the Error flags in the ICR register */
01514   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01515                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
01516                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01517
01518   /* Restore hsmartcard->RxState to Ready */
01519   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01520
01521   return HAL_OK;
01522 }
01523
01524 /**
01525   * @brief  Abort ongoing transfers (Interrupt mode).
01526   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01527   *                    the configuration information for the specified SMARTCARD module.
01528   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01529   *         This procedure performs following operations :
01530   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01531   *           - Disable the DMA transfer in the peripheral register (if enabled)
01532   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01533   *           - Set handle State to READY
01534   *           - At abort completion, call user abort complete callback
01535   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01536   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01537   * @retval HAL status
01538   */
01539 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01540 {
01541   uint32_t abortcplt = 1U;
01542
01543   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
01544      ERR (Frame error, noise error, overrun error) interrupts */
01545   CLEAR_BIT(hsmartcard->Instance->CR1,
01546             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01547              USART_CR1_EOBIE));
01548   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01549
01550   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
01551      DMA Abort complete callbacks should be initialised before any call
01552      to DMA Abort functions */
01553   /* DMA Tx Handle is valid */
01554   if (hsmartcard->hdmatx != NULL)
01555   {
01556     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01557        Otherwise, set it to NULL */
01558     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01559     {
01560       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01561     }
01562     else
01563     {
01564       hsmartcard->hdmatx->XferAbortCallback = NULL;
01565     }
01566   }
01567   /* DMA Rx Handle is valid */
01568   if (hsmartcard->hdmarx != NULL)
01569   {
01570     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01571        Otherwise, set it to NULL */
01572     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01573     {
01574       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01575     }
01576     else
01577     {
01578       hsmartcard->hdmarx->XferAbortCallback = NULL;
01579     }
01580   }
01581
01582   /* Disable the SMARTCARD DMA Tx request if enabled */
01583   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01584   {
01585     /* Disable DMA Tx at UART level */
01586     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01587
01588     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01589     if (hsmartcard->hdmatx != NULL)
01590     {
01591       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01592          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01593
01594       /* Abort DMA TX */
01595       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01596       {
01597         hsmartcard->hdmatx->XferAbortCallback = NULL;
01598       }
01599       else
01600       {
01601         abortcplt = 0U;
01602       }
01603     }
01604   }
01605
01606   /* Disable the SMARTCARD DMA Rx request if enabled */
01607   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01608   {
01609     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01610
01611     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01612     if (hsmartcard->hdmarx != NULL)
01613     {
01614       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01615          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01616
01617       /* Abort DMA RX */
01618       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01619       {
01620         hsmartcard->hdmarx->XferAbortCallback = NULL;
01621         abortcplt = 1U;
01622       }
01623       else
01624       {
01625         abortcplt = 0U;
01626       }
01627     }
01628   }
01629
01630   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01631   if (abortcplt == 1U)
01632   {
01633     /* Reset Tx and Rx transfer counters */
01634     hsmartcard->TxXferCount = 0U;
01635     hsmartcard->RxXferCount = 0U;
01636
01637     /* Clear ISR function pointers */
01638     hsmartcard->RxISR = NULL;
01639     hsmartcard->TxISR = NULL;
01640
01641     /* Reset errorCode */
01642     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01643
01644     /* Clear the Error flags in the ICR register */
01645     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01646                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01647                                SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01648
01649     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01650     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01651     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01652
01653     /* As no DMA to be aborted, call directly user Abort complete callback */
01654 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01655     /* Call registered Abort complete callback */
01656     hsmartcard->AbortCpltCallback(hsmartcard);
01657 #else
01658     /* Call legacy weak Abort complete callback */
01659     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01660 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01661   }
01662
01663   return HAL_OK;
01664 }
01665
01666 /**
01667   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01668   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01669   *                    the configuration information for the specified SMARTCARD module.
01670   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01671   *         This procedure performs following operations :
01672   *           - Disable SMARTCARD Interrupts (Tx)
01673   *           - Disable the DMA transfer in the peripheral register (if enabled)
01674   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01675   *           - Set handle State to READY
01676   *           - At abort completion, call user abort complete callback
01677   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01678   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01679   * @retval HAL status
01680   */
01681 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01682 {
01683   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01684   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01685   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01686
01687   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01688   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01689   {
01690     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01691     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01692   }
01693
01694   /* Disable the SMARTCARD DMA Tx request if enabled */
01695   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01696   {
01697     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01698
01699     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01700     if (hsmartcard->hdmatx != NULL)
01701     {
01702       /* Set the SMARTCARD DMA Abort callback :
01703          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01704       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01705
01706       /* Abort DMA TX */
01707       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01708       {
01709         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01710         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01711       }
01712     }
01713     else
01714     {
01715       /* Reset Tx transfer counter */
01716       hsmartcard->TxXferCount = 0U;
01717
01718       /* Clear TxISR function pointers */
01719       hsmartcard->TxISR = NULL;
01720
01721       /* Restore hsmartcard->gState to Ready */
01722       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01723
01724       /* As no DMA to be aborted, call directly user Abort complete callback */
01725 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01726       /* Call registered Abort Transmit Complete Callback */
01727       hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01728 #else
01729       /* Call legacy weak Abort Transmit Complete Callback */
01730       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01731 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01732     }
01733   }
01734   else
01735   {
01736     /* Reset Tx transfer counter */
01737     hsmartcard->TxXferCount = 0U;
01738
01739     /* Clear TxISR function pointers */
01740     hsmartcard->TxISR = NULL;
01741
01742     /* Clear the Error flags in the ICR register */
01743     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01744
01745     /* Restore hsmartcard->gState to Ready */
01746     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01747
01748     /* As no DMA to be aborted, call directly user Abort complete callback */
01749 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01750     /* Call registered Abort Transmit Complete Callback */
01751     hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01752 #else
01753     /* Call legacy weak Abort Transmit Complete Callback */
01754     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01755 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01756   }
01757
01758   return HAL_OK;
01759 }
01760
01761 /**
01762   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01763   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01764   *                    the configuration information for the specified SMARTCARD module.
01765   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01766   *         This procedure performs following operations :
01767   *           - Disable SMARTCARD Interrupts (Rx)
01768   *           - Disable the DMA transfer in the peripheral register (if enabled)
01769   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01770   *           - Set handle State to READY
01771   *           - At abort completion, call user abort complete callback
01772   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01773   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01774   * @retval HAL status
01775   */
01776 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01777 {
01778   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01779   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
01780                                         USART_CR1_EOBIE));
01781   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01782
01783   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01784   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01785   {
01786     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01787     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01788   }
01789
01790   /* Disable the SMARTCARD DMA Rx request if enabled */
01791   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01792   {
01793     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01794
01795     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01796     if (hsmartcard->hdmarx != NULL)
01797     {
01798       /* Set the SMARTCARD DMA Abort callback :
01799          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01800       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01801
01802       /* Abort DMA RX */
01803       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01804       {
01805         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01806         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01807       }
01808     }
01809     else
01810     {
01811       /* Reset Rx transfer counter */
01812       hsmartcard->RxXferCount = 0U;
01813
01814       /* Clear RxISR function pointer */
01815       hsmartcard->RxISR = NULL;
01816
01817       /* Clear the Error flags in the ICR register */
01818       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01819                                  SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01820                                  SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01821
01822       /* Restore hsmartcard->RxState to Ready */
01823       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01824
01825       /* As no DMA to be aborted, call directly user Abort complete callback */
01826 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01827       /* Call registered Abort Receive Complete Callback */
01828       hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01829 #else
01830       /* Call legacy weak Abort Receive Complete Callback */
01831       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01832 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01833     }
01834   }
01835   else
01836   {
01837     /* Reset Rx transfer counter */
01838     hsmartcard->RxXferCount = 0U;
01839
01840     /* Clear RxISR function pointer */
01841     hsmartcard->RxISR = NULL;
01842
01843     /* Clear the Error flags in the ICR register */
01844     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01845                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01846                                SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01847
01848     /* Restore hsmartcard->RxState to Ready */
01849     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01850
01851     /* As no DMA to be aborted, call directly user Abort complete callback */
01852 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01853     /* Call registered Abort Receive Complete Callback */
01854     hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01855 #else
01856     /* Call legacy weak Abort Receive Complete Callback */
01857     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01858 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01859   }
01860
01861   return HAL_OK;
01862 }
01863
01864 /**
01865   * @brief  Handle SMARTCARD interrupt requests.
01866   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01867   *                    the configuration information for the specified SMARTCARD module.
01868   * @retval None
01869   */
01870 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01871 {
01872   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01873   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01874   uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
01875   uint32_t errorflags;
01876   uint32_t errorcode;
01877
01878   /* If no error occurs */
01879   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01880   if (errorflags == 0U)
01881   {
01882     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01883     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01884         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01885             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01886     {
01887       if (hsmartcard->RxISR != NULL)
01888       {
01889         hsmartcard->RxISR(hsmartcard);
01890       }
01891       return;
01892     }
01893   }
01894
01895   /* If some errors occur */
01896   if ((errorflags != 0U)
01897       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
01898            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
01899   {
01900     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01901     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01902     {
01903       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01904
01905       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01906     }
01907
01908     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01909     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01910     {
01911       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01912
01913       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01914     }
01915
01916     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01917     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01918     {
01919       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01920
01921       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01922     }
01923
01924     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01925     if (((isrflags & USART_ISR_ORE) != 0U)
01926         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01927             || ((cr3its & USART_CR3_RXFTIE) != 0U)
01928             || ((cr3its & USART_CR3_EIE) != 0U)))
01929     {
01930       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01931
01932       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01933     }
01934
01935     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01936     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
01937     {
01938       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01939
01940       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01941     }
01942
01943     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01944     if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01945     {
01946       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01947       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01948           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01949               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01950       {
01951         if (hsmartcard->RxISR != NULL)
01952         {
01953           hsmartcard->RxISR(hsmartcard);
01954         }
01955       }
01956
01957       /* If Error is to be considered as blocking :
01958           - Receiver Timeout error in Reception
01959           - Overrun error in Reception
01960           - any error occurs in DMA mode reception
01961       */
01962       errorcode = hsmartcard->ErrorCode;
01963       if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01964           || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
01965       {
01966         /* Blocking error : transfer is aborted
01967            Set the SMARTCARD state ready to be able to start again the process,
01968            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01969         SMARTCARD_EndRxTransfer(hsmartcard);
01970
01971         /* Disable the SMARTCARD DMA Rx request if enabled */
01972         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01973         {
01974           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01975
01976           /* Abort the SMARTCARD DMA Rx channel */
01977           if (hsmartcard->hdmarx != NULL)
01978           {
01979             /* Set the SMARTCARD DMA Abort callback :
01980                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01981             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01982
01983             /* Abort DMA RX */
01984             if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01985             {
01986               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01987               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01988             }
01989           }
01990           else
01991           {
01992 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01993             /* Call registered user error callback */
01994             hsmartcard->ErrorCallback(hsmartcard);
01995 #else
01996             /* Call legacy weak user error callback */
01997             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01998 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01999           }
02000         }
02001         else
02002         {
02003 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02004           /* Call registered user error callback */
02005           hsmartcard->ErrorCallback(hsmartcard);
02006 #else
02007           /* Call legacy weak user error callback */
02008           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02009 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02010         }
02011       }
02012       /* other error type to be considered as blocking :
02013           - Frame error in Transmission
02014       */
02015       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02016                && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
02017       {
02018         /* Blocking error : transfer is aborted
02019            Set the SMARTCARD state ready to be able to start again the process,
02020            Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
02021         SMARTCARD_EndTxTransfer(hsmartcard);
02022
02023         /* Disable the SMARTCARD DMA Tx request if enabled */
02024         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02025         {
02026           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02027
02028           /* Abort the SMARTCARD DMA Tx channel */
02029           if (hsmartcard->hdmatx != NULL)
02030           {
02031             /* Set the SMARTCARD DMA Abort callback :
02032                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
02033             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
02034
02035             /* Abort DMA TX */
02036             if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
02037             {
02038               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
02039               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
02040             }
02041           }
02042           else
02043           {
02044 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02045             /* Call registered user error callback */
02046             hsmartcard->ErrorCallback(hsmartcard);
02047 #else
02048             /* Call legacy weak user error callback */
02049             HAL_SMARTCARD_ErrorCallback(hsmartcard);
02050 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02051           }
02052         }
02053         else
02054         {
02055 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02056           /* Call registered user error callback */
02057           hsmartcard->ErrorCallback(hsmartcard);
02058 #else
02059           /* Call legacy weak user error callback */
02060           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02061 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02062         }
02063       }
02064       else
02065       {
02066         /* Non Blocking error : transfer could go on.
02067            Error is notified to user through user error callback */
02068 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02069         /* Call registered user error callback */
02070         hsmartcard->ErrorCallback(hsmartcard);
02071 #else
02072         /* Call legacy weak user error callback */
02073         HAL_SMARTCARD_ErrorCallback(hsmartcard);
02074 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02075         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02076       }
02077     }
02078     return;
02079
02080   } /* End if some error occurs */
02081
02082   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
02083   if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
02084   {
02085     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02086     __HAL_UNLOCK(hsmartcard);
02087 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02088     /* Call registered Rx complete callback */
02089     hsmartcard->RxCpltCallback(hsmartcard);
02090 #else
02091     /* Call legacy weak Rx complete callback */
02092     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02093 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02094     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
02095        to be available during HAL_SMARTCARD_RxCpltCallback() processing */
02096     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
02097     return;
02098   }
02099
02100   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
02101   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02102       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02103           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02104   {
02105     if (hsmartcard->TxISR != NULL)
02106     {
02107       hsmartcard->TxISR(hsmartcard);
02108     }
02109     return;
02110   }
02111
02112   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
02113   if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02114   {
02115     if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02116     {
02117       SMARTCARD_EndTransmit_IT(hsmartcard);
02118       return;
02119     }
02120   }
02121
02122   /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
02123   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02124   {
02125 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02126     /* Call registered Tx Fifo Empty Callback */
02127     hsmartcard->TxFifoEmptyCallback(hsmartcard);
02128 #else
02129     /* Call legacy weak Tx Fifo Empty Callback */
02130     HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
02131 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02132     return;
02133   }
02134
02135   /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
02136   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02137   {
02138 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02139     /* Call registered Rx Fifo Full Callback */
02140     hsmartcard->RxFifoFullCallback(hsmartcard);
02141 #else
02142     /* Call legacy weak Rx Fifo Full Callback */
02143     HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
02144 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02145     return;
02146   }
02147 }
02148
02149 /**
02150   * @brief  Tx Transfer completed callback.
02151   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02152   *                    the configuration information for the specified SMARTCARD module.
02153   * @retval None
02154   */
02155 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02156 {
02157   /* Prevent unused argument(s) compilation warning */
02158   UNUSED(hsmartcard);
02159
02160   /* NOTE : This function should not be modified, when the callback is needed,
02161             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
02162    */
02163 }
02164
02165 /**
02166   * @brief  Rx Transfer completed callback.
02167   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02168   *                    the configuration information for the specified SMARTCARD module.
02169   * @retval None
02170   */
02171 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02172 {
02173   /* Prevent unused argument(s) compilation warning */
02174   UNUSED(hsmartcard);
02175
02176   /* NOTE : This function should not be modified, when the callback is needed,
02177             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
02178    */
02179 }
02180
02181 /**
02182   * @brief  SMARTCARD error callback.
02183   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02184   *                    the configuration information for the specified SMARTCARD module.
02185   * @retval None
02186   */
02187 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02188 {
02189   /* Prevent unused argument(s) compilation warning */
02190   UNUSED(hsmartcard);
02191
02192   /* NOTE : This function should not be modified, when the callback is needed,
02193             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
02194    */
02195 }
02196
02197 /**
02198   * @brief  SMARTCARD Abort Complete callback.
02199   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02200   *                    the configuration information for the specified SMARTCARD module.
02201   * @retval None
02202   */
02203 __weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02204 {
02205   /* Prevent unused argument(s) compilation warning */
02206   UNUSED(hsmartcard);
02207
02208   /* NOTE : This function should not be modified, when the callback is needed,
02209             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
02210    */
02211 }
02212
02213 /**
02214   * @brief  SMARTCARD Abort Complete callback.
02215   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02216   *                    the configuration information for the specified SMARTCARD module.
02217   * @retval None
02218   */
02219 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02220 {
02221   /* Prevent unused argument(s) compilation warning */
02222   UNUSED(hsmartcard);
02223
02224   /* NOTE : This function should not be modified, when the callback is needed,
02225             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
02226    */
02227 }
02228
02229 /**
02230   * @brief  SMARTCARD Abort Receive Complete callback.
02231   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02232   *                    the configuration information for the specified SMARTCARD module.
02233   * @retval None
02234   */
02235 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02236 {
02237   /* Prevent unused argument(s) compilation warning */
02238   UNUSED(hsmartcard);
02239
02240   /* NOTE : This function should not be modified, when the callback is needed,
02241             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
02242    */
02243 }
02244
02245 /**
02246   * @}
02247   */
02248
02249 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
02250   * @brief    SMARTCARD State and Errors functions
02251   *
02252 @verbatim
02253   ==============================================================================
02254                   ##### Peripheral State and Errors functions #####
02255   ==============================================================================
02256   [..]
02257     This subsection provides a set of functions allowing to return the State of SmartCard
02258     handle and also return Peripheral Errors occurred during communication process
02259      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
02260          of the SMARTCARD peripheral.
02261      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
02262          communication.
02263
02264 @endverbatim
02265   * @{
02266   */
02267
02268 /**
02269   * @brief  Return the SMARTCARD handle state.
02270   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02271   *                    the configuration information for the specified SMARTCARD module.
02272   * @retval SMARTCARD handle state
02273   */
02274 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
02275 {
02276   /* Return SMARTCARD handle state */
02277   uint32_t temp1;
02278   uint32_t temp2;
02279   temp1 = (uint32_t)hsmartcard->gState;
02280   temp2 = (uint32_t)hsmartcard->RxState;
02281
02282   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
02283 }
02284
02285 /**
02286   * @brief  Return the SMARTCARD handle error code.
02287   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02288   *                    the configuration information for the specified SMARTCARD module.
02289   * @retval SMARTCARD handle Error Code
02290   */
02291 uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
02292 {
02293   return hsmartcard->ErrorCode;
02294 }
02295
02296 /**
02297   * @}
02298   */
02299
02300 /**
02301   * @}
02302   */
02303
02304 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
02305   * @{
02306   */
02307
02308 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02309 /**
02310   * @brief  Initialize the callbacks to their default values.
02311   * @param  hsmartcard SMARTCARD handle.
02312   * @retval none
02313   */
02314 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
02315 {
02316   /* Init the SMARTCARD Callback settings */
02317   hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback    */
02318   hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback    */
02319   hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback     */
02320   hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback */
02321   hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
02322                                                                                       AbortTransmitCpltCallback     */
02323   hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
02324                                                                                       AbortReceiveCpltCallback      */
02325   hsmartcard->RxFifoFullCallback        = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak
02326                                                                                       RxFifoFullCallback            */
02327   hsmartcard->TxFifoEmptyCallback       = HAL_SMARTCARDEx_TxFifoEmptyCallback;     /* Legacy weak
02328                                                                                       TxFifoEmptyCallback           */
02329
02330 }
02331 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
02332
02333 /**
02334   * @brief  Configure the SMARTCARD associated USART peripheral.
02335   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02336   *                    the configuration information for the specified SMARTCARD module.
02337   * @retval HAL status
02338   */
02339 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02340 {
02341   uint32_t tmpreg;
02342   SMARTCARD_ClockSourceTypeDef clocksource;
02343   HAL_StatusTypeDef ret = HAL_OK;
02344   static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02345   uint32_t pclk;
02346
02347   /* Check the parameters */
02348   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
02349   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
02350   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
02351   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
02352   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
02353   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
02354   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
02355   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
02356   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
02357   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
02358   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
02359   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
02360   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
02361   assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
02362
02363   /*-------------------------- USART CR1 Configuration -----------------------*/
02364   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
02365    * Oversampling is forced to 16 (OVER8 = 0).
02366    * Configure the Parity and Mode:
02367    *  set PS bit according to hsmartcard->Init.Parity value
02368    *  set TE and RE bits according to hsmartcard->Init.Mode value */
02369   tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
02370             ((uint32_t)hsmartcard->Init.WordLength));
02371   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02372
02373   /*-------------------------- USART CR2 Configuration -----------------------*/
02374   tmpreg = hsmartcard->Init.StopBits;
02375   /* Synchronous mode is activated by default */
02376   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
02377   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
02378   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
02379   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02380
02381   /*-------------------------- USART CR3 Configuration -----------------------*/
02382   /* Configure
02383    * - one-bit sampling method versus three samples' majority rule
02384    *   according to hsmartcard->Init.OneBitSampling
02385    * - NACK transmission in case of parity error according
02386    *   to hsmartcard->Init.NACKEnable
02387    * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
02388
02389   tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
02390   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
02391   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02392
02393   /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
02394   /* Configure
02395   * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
02396   MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
02397
02398   /*-------------------------- USART GTPR Configuration ----------------------*/
02399   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
02400   MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
02401
02402   /*-------------------------- USART RTOR Configuration ----------------------*/
02403   tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
02404   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
02405   {
02406     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
02407     tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
02408   }
02409   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
02410
02411   /*-------------------------- USART BRR Configuration -----------------------*/
02412   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
02413   tmpreg =   0U;
02414   switch (clocksource)
02415   {
02416     case SMARTCARD_CLOCKSOURCE_PCLK1:
02417       pclk = HAL_RCC_GetPCLK1Freq();
02418       tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02419                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02420       break;
02421     case SMARTCARD_CLOCKSOURCE_PCLK2:
02422       pclk = HAL_RCC_GetPCLK2Freq();
02423       tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02424                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02425       break;
02426     case SMARTCARD_CLOCKSOURCE_HSI:
02427       tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02428                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02429       break;
02430     case SMARTCARD_CLOCKSOURCE_SYSCLK:
02431       pclk = HAL_RCC_GetSysClockFreq();
02432       tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02433                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02434       break;
02435     case SMARTCARD_CLOCKSOURCE_LSE:
02436       tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02437                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02438       break;
02439     default:
02440       ret = HAL_ERROR;
02441       break;
02442   }
02443
02444   /* USARTDIV must be greater than or equal to 0d16 */
02445   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02446   {
02447     hsmartcard->Instance->BRR = (uint16_t)tmpreg;
02448   }
02449   else
02450   {
02451     ret = HAL_ERROR;
02452   }
02453
02454   /* Initialize the number of data to process during RX/TX ISR execution */
02455   hsmartcard->NbTxDataToProcess = 1U;
02456   hsmartcard->NbRxDataToProcess = 1U;
02457
02458   /* Clear ISR function pointers */
02459   hsmartcard->RxISR   = NULL;
02460   hsmartcard->TxISR   = NULL;
02461
02462   return ret;
02463 }
02464
02465
02466 /**
02467   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
02468   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02469   *                   the configuration information for the specified SMARTCARD module.
02470   * @retval None
02471   */
02472 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02473 {
02474   /* Check whether the set of advanced features to configure is properly set */
02475   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
02476
02477   /* if required, configure TX pin active level inversion */
02478   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
02479   {
02480     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
02481     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
02482   }
02483
02484   /* if required, configure RX pin active level inversion */
02485   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
02486   {
02487     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
02488     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
02489   }
02490
02491   /* if required, configure data inversion */
02492   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
02493   {
02494     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
02495     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
02496   }
02497
02498   /* if required, configure RX/TX pins swap */
02499   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
02500   {
02501     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
02502     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
02503   }
02504
02505   /* if required, configure RX overrun detection disabling */
02506   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02507   {
02508     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
02509     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
02510   }
02511
02512   /* if required, configure DMA disabling on reception error */
02513   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
02514   {
02515     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
02516     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
02517   }
02518
02519   /* if required, configure MSB first on communication line */
02520   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
02521   {
02522     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
02523     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
02524   }
02525
02526 }
02527
02528 /**
02529   * @brief Check the SMARTCARD Idle State.
02530   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02531   *                   the configuration information for the specified SMARTCARD module.
02532   * @retval HAL status
02533   */
02534 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
02535 {
02536   uint32_t tickstart;
02537
02538   /* Initialize the SMARTCARD ErrorCode */
02539   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02540
02541   /* Init tickstart for timeout management */
02542   tickstart = HAL_GetTick();
02543
02544   /* Check if the Transmitter is enabled */
02545   if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02546   {
02547     /* Wait until TEACK flag is set */
02548     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
02549                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02550     {
02551       /* Timeout occurred */
02552       return HAL_TIMEOUT;
02553     }
02554   }
02555   /* Check if the Receiver is enabled */
02556   if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02557   {
02558     /* Wait until REACK flag is set */
02559     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
02560                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02561     {
02562       /* Timeout occurred */
02563       return HAL_TIMEOUT;
02564     }
02565   }
02566
02567   /* Initialize the SMARTCARD states */
02568   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02569   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02570
02571   /* Process Unlocked */
02572   __HAL_UNLOCK(hsmartcard);
02573
02574   return HAL_OK;
02575 }
02576
02577 /**
02578   * @brief  Handle SMARTCARD Communication Timeout. It waits
02579   *         until a flag is no longer in the specified status.
02580   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02581   *                   the configuration information for the specified SMARTCARD module.
02582   * @param  Flag Specifies the SMARTCARD flag to check.
02583   * @param  Status The actual Flag status (SET or RESET).
02584   * @param  Tickstart Tick start value
02585   * @param  Timeout Timeout duration.
02586   * @retval HAL status
02587   */
02588 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
02589                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02590 {
02591   /* Wait until flag is set */
02592   while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
02593   {
02594     /* Check for the Timeout */
02595     if (Timeout != HAL_MAX_DELAY)
02596     {
02597       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02598       {
02599         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
02600            interrupts for the interrupt process */
02601         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02602         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02603
02604         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02605         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02606
02607         /* Process Unlocked */
02608         __HAL_UNLOCK(hsmartcard);
02609         return HAL_TIMEOUT;
02610       }
02611     }
02612   }
02613   return HAL_OK;
02614 }
02615
02616
02617 /**
02618   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
02619   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02620   *                    the configuration information for the specified SMARTCARD module.
02621   * @retval None
02622   */
02623 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02624 {
02625   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
02626   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02627   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02628
02629   /* At end of Tx process, restore hsmartcard->gState to Ready */
02630   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02631 }
02632
02633
02634 /**
02635   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02636   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02637   *                    the configuration information for the specified SMARTCARD module.
02638   * @retval None
02639   */
02640 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02641 {
02642   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02643   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02644   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02645
02646   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02647   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02648 }
02649
02650
02651 /**
02652   * @brief  DMA SMARTCARD transmit process complete callback.
02653   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02654   *              the configuration information for the specified DMA module.
02655   * @retval None
02656   */
02657 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02658 {
02659   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02660   hsmartcard->TxXferCount = 0U;
02661
02662   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02663   in the SMARTCARD associated USART CR3 register */
02664   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02665
02666   /* Enable the SMARTCARD Transmit Complete Interrupt */
02667   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02668 }
02669
02670 /**
02671   * @brief  DMA SMARTCARD receive process complete callback.
02672   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02673   *              the configuration information for the specified DMA module.
02674   * @retval None
02675   */
02676 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02677 {
02678   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02679   hsmartcard->RxXferCount = 0U;
02680
02681   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02682   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02683   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02684
02685   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02686      in the SMARTCARD associated USART CR3 register */
02687   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
02688
02689   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02690   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02691
02692 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02693   /* Call registered Rx complete callback */
02694   hsmartcard->RxCpltCallback(hsmartcard);
02695 #else
02696   /* Call legacy weak Rx complete callback */
02697   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02698 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02699 }
02700
02701 /**
02702   * @brief  DMA SMARTCARD communication error callback.
02703   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02704   *              the configuration information for the specified DMA module.
02705   * @retval None
02706   */
02707 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
02708 {
02709   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02710
02711   /* Stop SMARTCARD DMA Tx request if ongoing */
02712   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02713   {
02714     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02715     {
02716       hsmartcard->TxXferCount = 0U;
02717       SMARTCARD_EndTxTransfer(hsmartcard);
02718     }
02719   }
02720
02721   /* Stop SMARTCARD DMA Rx request if ongoing */
02722   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02723   {
02724     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
02725     {
02726       hsmartcard->RxXferCount = 0U;
02727       SMARTCARD_EndRxTransfer(hsmartcard);
02728     }
02729   }
02730
02731   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02732 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02733   /* Call registered user error callback */
02734   hsmartcard->ErrorCallback(hsmartcard);
02735 #else
02736   /* Call legacy weak user error callback */
02737   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02738 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02739 }
02740
02741 /**
02742   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02743   *         (To be called at end of DMA Abort procedure following error occurrence).
02744   * @param  hdma DMA handle.
02745   * @retval None
02746   */
02747 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02748 {
02749   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02750   hsmartcard->RxXferCount = 0U;
02751   hsmartcard->TxXferCount = 0U;
02752
02753 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02754   /* Call registered user error callback */
02755   hsmartcard->ErrorCallback(hsmartcard);
02756 #else
02757   /* Call legacy weak user error callback */
02758   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02759 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02760 }
02761
02762 /**
02763   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02764   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02765   * @note   When this callback is executed, User Abort complete call back is called only if no
02766   *         Abort still ongoing for Rx DMA Handle.
02767   * @param  hdma DMA handle.
02768   * @retval None
02769   */
02770 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02771 {
02772   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02773
02774   hsmartcard->hdmatx->XferAbortCallback = NULL;
02775
02776   /* Check if an Abort process is still ongoing */
02777   if (hsmartcard->hdmarx != NULL)
02778   {
02779     if (hsmartcard->hdmarx->XferAbortCallback != NULL)
02780     {
02781       return;
02782     }
02783   }
02784
02785   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02786   hsmartcard->TxXferCount = 0U;
02787   hsmartcard->RxXferCount = 0U;
02788
02789   /* Reset errorCode */
02790   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02791
02792   /* Clear the Error flags in the ICR register */
02793   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02794                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02795                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02796
02797   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02798   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02799   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02800
02801 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02802   /* Call registered Abort complete callback */
02803   hsmartcard->AbortCpltCallback(hsmartcard);
02804 #else
02805   /* Call legacy weak Abort complete callback */
02806   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02807 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02808 }
02809
02810
02811 /**
02812   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02813   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02814   * @note   When this callback is executed, User Abort complete call back is called only if no
02815   *         Abort still ongoing for Tx DMA Handle.
02816   * @param  hdma DMA handle.
02817   * @retval None
02818   */
02819 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02820 {
02821   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02822
02823   hsmartcard->hdmarx->XferAbortCallback = NULL;
02824
02825   /* Check if an Abort process is still ongoing */
02826   if (hsmartcard->hdmatx != NULL)
02827   {
02828     if (hsmartcard->hdmatx->XferAbortCallback != NULL)
02829     {
02830       return;
02831     }
02832   }
02833
02834   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02835   hsmartcard->TxXferCount = 0U;
02836   hsmartcard->RxXferCount = 0U;
02837
02838   /* Reset errorCode */
02839   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02840
02841   /* Clear the Error flags in the ICR register */
02842   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02843                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02844                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02845
02846   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02847   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02848   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02849
02850 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02851   /* Call registered Abort complete callback */
02852   hsmartcard->AbortCpltCallback(hsmartcard);
02853 #else
02854   /* Call legacy weak Abort complete callback */
02855   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02856 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02857 }
02858
02859
02860 /**
02861   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02862   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02863   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02864   *         and leads to user Tx Abort Complete callback execution).
02865   * @param  hdma DMA handle.
02866   * @retval None
02867   */
02868 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02869 {
02870   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02871
02872   hsmartcard->TxXferCount = 0U;
02873
02874   /* Clear the Error flags in the ICR register */
02875   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02876
02877   /* Restore hsmartcard->gState to Ready */
02878   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02879
02880 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02881   /* Call registered Abort Transmit Complete Callback */
02882   hsmartcard->AbortTransmitCpltCallback(hsmartcard);
02883 #else
02884   /* Call legacy weak Abort Transmit Complete Callback */
02885   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02886 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02887 }
02888
02889 /**
02890   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02891   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02892   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02893   *         and leads to user Rx Abort Complete callback execution).
02894   * @param  hdma DMA handle.
02895   * @retval None
02896   */
02897 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02898 {
02899   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02900
02901   hsmartcard->RxXferCount = 0U;
02902
02903   /* Clear the Error flags in the ICR register */
02904   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02905                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02906                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02907
02908   /* Restore hsmartcard->RxState to Ready */
02909   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02910
02911 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02912   /* Call registered Abort Receive Complete Callback */
02913   hsmartcard->AbortReceiveCpltCallback(hsmartcard);
02914 #else
02915   /* Call legacy weak Abort Receive Complete Callback */
02916   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02917 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02918 }
02919
02920 /**
02921   * @brief  Send an amount of data in non-blocking mode.
02922   * @note   Function called under interruption only, once
02923   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02924   *         and when the FIFO mode is disabled.
02925   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02926   *                    the configuration information for the specified SMARTCARD module.
02927   * @retval None
02928   */
02929 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
02930 {
02931   /* Check that a Tx process is ongoing */
02932   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02933   {
02934     if (hsmartcard->TxXferCount == 0U)
02935     {
02936       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02937       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02938
02939       /* Enable the SMARTCARD Transmit Complete Interrupt */
02940       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02941     }
02942     else
02943     {
02944       hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02945       hsmartcard->pTxBuffPtr++;
02946       hsmartcard->TxXferCount--;
02947     }
02948   }
02949 }
02950
02951 /**
02952   * @brief  Send an amount of data in non-blocking mode.
02953   * @note   Function called under interruption only, once
02954   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02955   *         and when the FIFO mode is enabled.
02956   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02957   *                    the configuration information for the specified SMARTCARD module.
02958   * @retval None
02959   */
02960 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
02961 {
02962   uint16_t   nb_tx_data;
02963
02964   /* Check that a Tx process is ongoing */
02965   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02966   {
02967     for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
02968     {
02969       if (hsmartcard->TxXferCount == 0U)
02970       {
02971         /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02972         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02973
02974         /* Enable the SMARTCARD Transmit Complete Interrupt */
02975         __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02976       }
02977       else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
02978       {
02979         hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02980         hsmartcard->pTxBuffPtr++;
02981         hsmartcard->TxXferCount--;
02982       }
02983       else
02984       {
02985         /* Nothing to do */
02986       }
02987     }
02988   }
02989 }
02990
02991 /**
02992   * @brief  Wrap up transmission in non-blocking mode.
02993   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02994   *                    the configuration information for the specified SMARTCARD module.
02995   * @retval None
02996   */
02997 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02998 {
02999   /* Disable the SMARTCARD Transmit Complete Interrupt */
03000   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
03001
03002   /* Check if a receive process is ongoing or not. If not disable ERR IT */
03003   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
03004   {
03005     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
03006     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03007   }
03008
03009   /* Disable the Peripheral first to update mode */
03010   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
03011   if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
03012       && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
03013   {
03014     /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
03015        for Transmit phase. Disable this receiver block. */
03016     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
03017   }
03018   if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
03019       || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
03020   {
03021     /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
03022     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
03023   }
03024   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
03025
03026   /* Tx process is ended, restore hsmartcard->gState to Ready */
03027   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
03028
03029   /* Clear TxISR function pointer */
03030   hsmartcard->TxISR = NULL;
03031
03032 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03033   /* Call registered Tx complete callback */
03034   hsmartcard->TxCpltCallback(hsmartcard);
03035 #else
03036   /* Call legacy weak Tx complete callback */
03037   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
03038 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03039 }
03040
03041 /**
03042   * @brief  Receive an amount of data in non-blocking mode.
03043   * @note   Function called under interruption only, once
03044   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03045   *         and when the FIFO mode is disabled.
03046   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03047   *                    the configuration information for the specified SMARTCARD module.
03048   * @retval None
03049   */
03050 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
03051 {
03052   /* Check that a Rx process is ongoing */
03053   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03054   {
03055     *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03056     hsmartcard->pRxBuffPtr++;
03057
03058     hsmartcard->RxXferCount--;
03059     if (hsmartcard->RxXferCount == 0U)
03060     {
03061       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03062
03063       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03064       if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03065       {
03066         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03067         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03068       }
03069
03070       /* Disable the SMARTCARD Parity Error Interrupt */
03071       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03072
03073       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03074
03075       /* Clear RxISR function pointer */
03076       hsmartcard->RxISR = NULL;
03077
03078 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03079       /* Call registered Rx complete callback */
03080       hsmartcard->RxCpltCallback(hsmartcard);
03081 #else
03082       /* Call legacy weak Rx complete callback */
03083       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03084 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03085     }
03086   }
03087   else
03088   {
03089     /* Clear RXNE interrupt flag */
03090     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03091   }
03092 }
03093
03094 /**
03095   * @brief  Receive an amount of data in non-blocking mode.
03096   * @note   Function called under interruption only, once
03097   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03098   *         and when the FIFO mode is enabled.
03099   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03100   *                    the configuration information for the specified SMARTCARD module.
03101   * @retval None
03102   */
03103 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
03104 {
03105   uint16_t   nb_rx_data;
03106   uint16_t rxdatacount;
03107
03108   /* Check that a Rx process is ongoing */
03109   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03110   {
03111     for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03112     {
03113       *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03114       hsmartcard->pRxBuffPtr++;
03115
03116       hsmartcard->RxXferCount--;
03117       if (hsmartcard->RxXferCount == 0U)
03118       {
03119         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03120
03121         /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03122         if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03123         {
03124           /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03125           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03126         }
03127
03128         /* Disable the SMARTCARD Parity Error Interrupt */
03129         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03130
03131         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03132
03133         /* Clear RxISR function pointer */
03134         hsmartcard->RxISR = NULL;
03135
03136 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03137         /* Call registered Rx complete callback */
03138         hsmartcard->RxCpltCallback(hsmartcard);
03139 #else
03140         /* Call legacy weak Rx complete callback */
03141         HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03142 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03143       }
03144     }
03145
03146     /* When remaining number of bytes to receive is less than the RX FIFO
03147     threshold, next incoming frames are processed as if FIFO mode was
03148     disabled (i.e. one interrupt per received frame).
03149     */
03150     rxdatacount = hsmartcard->RxXferCount;
03151     if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
03152     {
03153       /* Disable the UART RXFT interrupt*/
03154       CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
03155
03156       /* Update the RxISR function pointer */
03157       hsmartcard->RxISR = SMARTCARD_RxISR;
03158
03159       /* Enable the UART Data Register Not Empty interrupt */
03160       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03161     }
03162   }
03163   else
03164   {
03165     /* Clear RXNE interrupt flag */
03166     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03167   }
03168 }
03169
03170 /**
03171   * @}
03172   */
03173
03174 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
03175 /**
03176   * @}
03177   */
03178
03179 /**
03180   * @}
03181   */
03182
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_smartcard.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SMARTCARD_H
00021 #define STM32G4xx_HAL_SMARTCARD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMARTCARD
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief SMARTCARD Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00049                                            The baud rate register is computed using the following formula:
00050                                               Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
00051                                            where usart_ker_ckpres is the USART input clock divided by a prescaler */
00052
00053   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00054                                            This parameter @ref SMARTCARD_Word_Length can only be
00055                                            set to 9 (8 data + 1 parity bits). */
00056
00057   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00058                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00059
00060   uint16_t Parity;                    /*!< Specifies the parity mode.
00061                                            This parameter can be a value of @ref SMARTCARD_Parity
00062                                            @note The parity is enabled by default (PCE is forced to 1).
00063                                                  Since the WordLength is forced to 8 bits + parity, M is
00064                                                  forced to 1 and the parity bit is the 9th bit. */
00065
00066   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00067                                            This parameter can be a value of @ref SMARTCARD_Mode */
00068
00069   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00070                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00071
00072   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00073                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00074
00075   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00076                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00077                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00078
00079   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote
00080                                            is selected. Selecting the single sample method increases
00081                                            the receiver tolerance to clock deviations. This parameter can be a value
00082                                            of @ref SMARTCARD_OneBit_Sampling. */
00083
00084   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
00085                                            This parameter can be any value from 0x01 to 0x1F. Prescaler value is
00086                                            multiplied by 2 to give the division factor of the source clock frequency */
00087
00088   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00089
00090   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00091                                            in case of parity error.
00092                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00093
00094   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00095                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00096
00097   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00098                                            it is used to implement the Character Wait Time (CWT) and
00099                                            Block Wait Time (BWT). It is coded over 24 bits. */
00100
00101   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00102                                            This parameter can be any value from 0x0 to 0xFF */
00103
00104   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00105                                             receive and transmit mode). When set to 0, retransmission is
00106                                             disabled. Otherwise, its maximum value is 7 (before signalling
00107                                             an error) */
00108
00109   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00110                                            This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
00111
00112 } SMARTCARD_InitTypeDef;
00113
00114 /**
00115   * @brief  SMARTCARD advanced features initialization structure definition
00116   */
00117 typedef struct
00118 {
00119   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00120                                            advanced features may be initialized at the same time. This parameter
00121                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00122
00123   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00124                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00125
00126   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00127                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00128
00129   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00130                                            vs negative/inverted logic).
00131                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00132
00133   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00134                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00135
00136   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00137                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00138
00139   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00140                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00141
00142   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00143                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00144
00145   uint16_t TxCompletionIndication;    /*!< Specifies which transmission completion indication is used: before (when
00146                                            relevant flag is available) or once guard time period has elapsed.
00147                                            This parameter can be a value
00148                                            of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00149 } SMARTCARD_AdvFeatureInitTypeDef;
00150
00151 /**
00152   * @brief HAL SMARTCARD State definition
00153   * @note  HAL SMARTCARD State value is a combination of 2 different substates:
00154   *        gState and RxState (see @ref SMARTCARD_State_Definition).
00155   *        - gState contains SMARTCARD state information related to global Handle management
00156   *          and also information related to Tx operations.
00157   *          gState value coding follow below described bitmap :
00158   *          b7-b6  Error information
00159   *             00 : No Error
00160   *             01 : (Not Used)
00161   *             10 : Timeout
00162   *             11 : Error
00163   *          b5     Peripheral initialization status
00164   *             0  : Reset (Peripheral not initialized)
00165   *             1  : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
00166   *          b4-b3  (not used)
00167   *             xx : Should be set to 00
00168   *          b2     Intrinsic process state
00169   *             0  : Ready
00170   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00171   *          b1     (not used)
00172   *             x  : Should be set to 0
00173   *          b0     Tx state
00174   *             0  : Ready (no Tx operation ongoing)
00175   *             1  : Busy (Tx operation ongoing)
00176   *        - RxState contains information related to Rx operations.
00177   *          RxState value coding follow below described bitmap :
00178   *          b7-b6  (not used)
00179   *             xx : Should be set to 00
00180   *          b5     Peripheral initialization status
00181   *             0  : Reset (Peripheral not initialized)
00182   *             1  : Init done (Peripheral initialized)
00183   *          b4-b2  (not used)
00184   *            xxx : Should be set to 000
00185   *          b1     Rx state
00186   *             0  : Ready (no Rx operation ongoing)
00187   *             1  : Busy (Rx operation ongoing)
00188   *          b0     (not used)
00189   *             x  : Should be set to 0.
00190   */
00191 typedef uint32_t HAL_SMARTCARD_StateTypeDef;
00192
00193 /**
00194   * @brief  SMARTCARD handle Structure definition
00195   */
00196 typedef struct __SMARTCARD_HandleTypeDef
00197 {
00198   USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
00199
00200   SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
00201
00202   SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
00203
00204   const uint8_t                     *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
00205
00206   uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
00207
00208   __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
00209
00210   uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
00211
00212   uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
00213
00214   __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
00215
00216   uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
00217
00218   uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
00219
00220   uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
00221                                                                 This parameter can be a value of
00222                                                                 @ref SMARTCARDEx_FIFO_mode.                           */
00223
00224   void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
00225
00226   void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
00227
00228   DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
00229
00230   DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
00231
00232   HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
00233
00234   __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global
00235                                                                 Handle management and also related to Tx operations.
00236                                                                 This parameter can be a value
00237                                                                 of @ref HAL_SMARTCARD_StateTypeDef                    */
00238
00239   __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
00240                                                                 This parameter can be a value
00241                                                                 of @ref HAL_SMARTCARD_StateTypeDef                    */
00242
00243   __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
00244
00245 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00246   void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
00247
00248   void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
00249
00250   void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
00251
00252   void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
00253
00254   void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
00255
00256   void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
00257
00258   void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
00259
00260   void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
00261
00262   void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
00263
00264   void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
00265 #endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00266
00267 } SMARTCARD_HandleTypeDef;
00268
00269 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00270 /**
00271   * @brief  HAL SMARTCARD Callback ID enumeration definition
00272   */
00273 typedef enum
00274 {
00275   HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
00276   HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
00277   HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
00278   HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
00279   HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
00280   HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
00281   HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
00282   HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
00283
00284   HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
00285   HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
00286
00287 } HAL_SMARTCARD_CallbackIDTypeDef;
00288
00289 /**
00290   * @brief  HAL SMARTCARD Callback pointer definition
00291   */
00292 typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
00293
00294 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00295
00296 /**
00297   * @brief  SMARTCARD clock sources
00298   */
00299 typedef enum
00300 {
00301   SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source         */
00302   SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01U, /*!< PCLK2 clock source         */
00303   SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source           */
00304   SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source        */
00305   SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source           */
00306   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */
00307 } SMARTCARD_ClockSourceTypeDef;
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Exported constants --------------------------------------------------------*/
00314 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00315   * @{
00316   */
00317
00318 /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
00319   * @{
00320   */
00321 #define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized. Value
00322                                                                                   is allowed for gState and RxState */
00323 #define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for
00324                                                                                   use. Value is allowed for gState
00325                                                                                   and RxState                       */
00326 #define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
00327                                                                                   Value is allowed for gState only  */
00328 #define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
00329                                                                                   Value is allowed for gState only  */
00330 #define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
00331                                                                                   Value is allowed for RxState only */
00332 #define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception
00333                                                                                   process is ongoing Not to be used for
00334                                                                                   neither gState nor RxState.
00335                                                                                   Value is result of combination (Or)
00336                                                                                   between gState and RxState values */
00337 #define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
00338                                                                                   Value is allowed for gState only  */
00339 #define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
00340                                                                                   Value is allowed for gState only  */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
00346   * @{
00347   */
00348 #define HAL_SMARTCARD_ERROR_NONE             (0x00000000U)         /*!< No error                */
00349 #define HAL_SMARTCARD_ERROR_PE               (0x00000001U)         /*!< Parity error            */
00350 #define HAL_SMARTCARD_ERROR_NE               (0x00000002U)         /*!< Noise error             */
00351 #define HAL_SMARTCARD_ERROR_FE               (0x00000004U)         /*!< frame error             */
00352 #define HAL_SMARTCARD_ERROR_ORE              (0x00000008U)         /*!< Overrun error           */
00353 #define HAL_SMARTCARD_ERROR_DMA              (0x00000010U)         /*!< DMA transfer error      */
00354 #define HAL_SMARTCARD_ERROR_RTO              (0x00000020U)         /*!< Receiver TimeOut error  */
00355 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00356 #define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)         /*!< Invalid Callback error  */
00357 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00363   * @{
00364   */
00365 #define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00371   * @{
00372   */
00373 #define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
00374 #define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00380   * @{
00381   */
00382 #define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
00383 #define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00389   * @{
00390   */
00391 #define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
00392 #define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
00393 #define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00399   * @{
00400   */
00401 #define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
00402 #define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00408   * @{
00409   */
00410 #define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
00411 #define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00417   * @{
00418   */
00419 #define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00420 #define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00426   * @{
00427   */
00428 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
00429 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00435   * @{
00436   */
00437 #define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
00438 #define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00444   * @{
00445   */
00446 #define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
00447 #define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
00453   * @{
00454   */
00455 #define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00456 #define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00457 #define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00458 #define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00459 #define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00460 #define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00461 #define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00462 #define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00463 #define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00464 #define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00465 #define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00466 #define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00472   * @{
00473   */
00474 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
00475 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00481   * @{
00482   */
00483 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
00484 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00490   * @{
00491   */
00492 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
00493 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00499   * @{
00500   */
00501 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
00502 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00508   * @{
00509   */
00510 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
00511 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00517   * @{
00518   */
00519 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
00520 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00526   * @{
00527   */
00528 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
00529 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00535   * @{
00536   */
00537 #define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
00538 #define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00544   * @{
00545   */
00546 #define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
00547 #define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
00548 #define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
00549 #define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
00550 #define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
00551 /**
00552   * @}
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /* Exported macros -----------------------------------------------------------*/
00560 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00561   * @{
00562   */
00563
00564 /** @brief  Reset SMARTCARD handle states.
00565   * @param  __HANDLE__ SMARTCARD handle.
00566   * @retval None
00567   */
00568 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00569 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00570                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00571                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00572                                                             (__HANDLE__)->MspInitCallback = NULL;                 \
00573                                                             (__HANDLE__)->MspDeInitCallback = NULL;               \
00574                                                           } while(0U)
00575 #else
00576 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00577                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00578                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00579                                                           } while(0U)
00580 #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
00581
00582 /** @brief  Flush the Smartcard Data registers.
00583   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00584   * @retval None
00585   */
00586 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
00587   do{                                                                     \
00588     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00589     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00590   } while(0U)
00591
00592 /** @brief  Clear the specified SMARTCARD pending flag.
00593   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00594   * @param  __FLAG__ specifies the flag to check.
00595   *          This parameter can be any combination of the following values:
00596   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00597   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00598   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00599   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00600   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00601   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00602   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
00603   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00604   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00605   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
00606   * @retval None
00607   */
00608 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00609
00610 /** @brief  Clear the SMARTCARD PE pending flag.
00611   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00612   * @retval None
00613   */
00614 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00615
00616 /** @brief  Clear the SMARTCARD FE pending flag.
00617   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00618   * @retval None
00619   */
00620 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00621
00622 /** @brief  Clear the SMARTCARD NE pending flag.
00623   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00624   * @retval None
00625   */
00626 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00627
00628 /** @brief  Clear the SMARTCARD ORE pending flag.
00629   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00630   * @retval None
00631   */
00632 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00633
00634 /** @brief  Clear the SMARTCARD IDLE pending flag.
00635   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00636   * @retval None
00637   */
00638 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00639
00640 /** @brief  Check whether the specified Smartcard flag is set or not.
00641   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00642   * @param  __FLAG__ specifies the flag to check.
00643   *        This parameter can be one of the following values:
00644   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
00645   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00646   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00647   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00648   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00649   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00650   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00651   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00652   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00653   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00654   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00655   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00656   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00657   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00658   *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
00659   *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
00660   *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
00661   *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
00662   *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
00663   *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
00664   * @retval The new state of __FLAG__ (TRUE or FALSE).
00665   */
00666 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00667
00668 /** @brief  Enable the specified SmartCard interrupt.
00669   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00670   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
00671   *          This parameter can be one of the following values:
00672   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00673   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00674   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00675   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00676   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before
00677   *                                          guard time interrupt (when interruption available)
00678   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00679   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00680   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00681   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00682   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00683   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00684   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00685   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00686   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00687   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00688   * @retval None
00689   */
00690 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00691                                                                   SMARTCARD_CR_POS) == 1U)?\
00692                                                                 ((__HANDLE__)->Instance->CR1 |= (1UL <<\
00693                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
00694                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00695                                                                   SMARTCARD_CR_POS) == 2U)?\
00696                                                                 ((__HANDLE__)->Instance->CR2 |= (1UL <<\
00697                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00698                                                                 ((__HANDLE__)->Instance->CR3 |= (1UL <<\
00699                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00700
00701 /** @brief  Disable the specified SmartCard interrupt.
00702   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00703   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
00704   *          This parameter can be one of the following values:
00705   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00706   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00707   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00708   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00709   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard
00710   *                                          time interrupt (when interruption available)
00711   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00712   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00713   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00714   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00715   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00716   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00717   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00718   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00719   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00720   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00721   * @retval None
00722   */
00723 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00724                                                                   SMARTCARD_CR_POS) == 1U)?\
00725                                                                 ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
00726                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00727                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00728                                                                   SMARTCARD_CR_POS) == 2U)?\
00729                                                                 ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
00730                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00731                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
00732                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00733
00734 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00735   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00736   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
00737   *          This parameter can be one of the following values:
00738   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00739   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00740   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00741   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00742   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
00743   *                                          interrupt (when interruption available)
00744   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00745   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00746   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00747   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00748   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00749   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00750   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00751   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00752   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00753   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00754   * @retval The new state of __INTERRUPT__ (SET or RESET).
00755   */
00756 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
00757                                                            (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
00758                                                                & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
00759                                                            ? SET : RESET)
00760
00761 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00762   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00763   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
00764   *          This parameter can be one of the following values:
00765   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00766   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00767   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00768   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00769   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
00770   *                                          interrupt (when interruption available)
00771   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00772   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00773   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00774   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00775   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00776   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00777   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00778   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00779   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00780   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00781   * @retval The new state of __INTERRUPT__ (SET or RESET).
00782   */
00783 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00784                                                                        SMARTCARD_CR_POS) == 0x01U)?\
00785                                                                      (__HANDLE__)->Instance->CR1 : \
00786                                                                      (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00787                                                                         SMARTCARD_CR_POS) == 0x02U)?\
00788                                                                       (__HANDLE__)->Instance->CR2 : \
00789                                                                       (__HANDLE__)->Instance->CR3)) &\
00790                                                                     (0x01UL << (((uint16_t)(__INTERRUPT__))\
00791                                                                                 & SMARTCARD_IT_MASK)))  != 0U)\
00792                                                                   ? SET : RESET)
00793
00794 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00795   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00796   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00797   *                       to clear the corresponding interrupt.
00798   *          This parameter can be one of the following values:
00799   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00800   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00801   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00802   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00803   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00804   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
00805   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00806   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00807   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00808   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00809   * @retval None
00810   */
00811 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00812
00813 /** @brief  Set a specific SMARTCARD request flag.
00814   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00815   * @param  __REQ__ specifies the request flag to set
00816   *          This parameter can be one of the following values:
00817   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00818   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00819   * @retval None
00820   */
00821 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00822
00823 /** @brief  Enable the SMARTCARD one bit sample method.
00824   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00825   * @retval None
00826   */
00827 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00828
00829 /** @brief  Disable the SMARTCARD one bit sample method.
00830   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00831   * @retval None
00832   */
00833 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00834                                                             &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00835
00836 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00837   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00838   * @retval None
00839   */
00840 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00841
00842 /** @brief  Disable the USART associated to the SMARTCARD Handle
00843   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00844   * @retval None
00845   */
00846 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00847
00848 /**
00849   * @}
00850   */
00851
00852 /* Private macros -------------------------------------------------------------*/
00853 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00854   * @{
00855   */
00856
00857 /** @brief  Report the SMARTCARD clock source.
00858   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00859   * @param  __CLOCKSOURCE__ output variable.
00860   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00861   */
00862 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00863   do {                                                         \
00864     if((__HANDLE__)->Instance == USART1)                       \
00865     {                                                          \
00866       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00867       {                                                        \
00868         case RCC_USART1CLKSOURCE_PCLK2:                        \
00869           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
00870           break;                                               \
00871         case RCC_USART1CLKSOURCE_HSI:                          \
00872           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00873           break;                                               \
00874         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00875           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00876           break;                                               \
00877         case RCC_USART1CLKSOURCE_LSE:                          \
00878           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00879           break;                                               \
00880         default:                                               \
00881           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00882           break;                                               \
00883       }                                                        \
00884     }                                                          \
00885     else if((__HANDLE__)->Instance == USART2)                  \
00886     {                                                          \
00887       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00888       {                                                        \
00889         case RCC_USART2CLKSOURCE_PCLK1:                        \
00890           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00891           break;                                               \
00892         case RCC_USART2CLKSOURCE_HSI:                          \
00893           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00894           break;                                               \
00895         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00896           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00897           break;                                               \
00898         case RCC_USART2CLKSOURCE_LSE:                          \
00899           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00900           break;                                               \
00901         default:                                               \
00902           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00903           break;                                               \
00904       }                                                        \
00905     }                                                          \
00906     else if((__HANDLE__)->Instance == USART3)                  \
00907     {                                                          \
00908       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00909       {                                                        \
00910         case RCC_USART3CLKSOURCE_PCLK1:                        \
00911           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00912           break;                                               \
00913         case RCC_USART3CLKSOURCE_HSI:                          \
00914           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00915           break;                                               \
00916         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00917           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00918           break;                                               \
00919         case RCC_USART3CLKSOURCE_LSE:                          \
00920           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00921           break;                                               \
00922         default:                                               \
00923           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00924           break;                                               \
00925       }                                                        \
00926     }                                                          \
00927     else                                                       \
00928     {                                                          \
00929       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00930     }                                                          \
00931   } while(0U)
00932
00933 /** @brief  Check the Baud rate range.
00934   * @note   The maximum Baud Rate is derived from the maximum clock on G4 (150 MHz)
00935   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
00936   * @param  __BAUDRATE__ Baud rate set by the configuration function.
00937   * @retval Test result (TRUE or FALSE)
00938   */
00939 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9375001U)
00940
00941 /** @brief  Check the block length range.
00942   * @note   The maximum SMARTCARD block length is 0xFF.
00943   * @param  __LENGTH__ block length.
00944   * @retval Test result (TRUE or FALSE)
00945   */
00946 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
00947
00948 /** @brief  Check the receiver timeout value.
00949   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00950   * @param  __TIMEOUTVALUE__ receiver timeout value.
00951   * @retval Test result (TRUE or FALSE)
00952   */
00953 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
00954
00955 /** @brief  Check the SMARTCARD autoretry counter value.
00956   * @note   The maximum number of retransmissions is 0x7.
00957   * @param  __COUNT__ number of retransmissions.
00958   * @retval Test result (TRUE or FALSE)
00959   */
00960 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
00961
00962 /** @brief Ensure that SMARTCARD frame length is valid.
00963   * @param __LENGTH__ SMARTCARD frame length.
00964   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00965   */
00966 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00967
00968 /** @brief Ensure that SMARTCARD frame number of stop bits is valid.
00969   * @param __STOPBITS__ SMARTCARD frame number of stop bits.
00970   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00971   */
00972 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00973                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00974
00975 /** @brief Ensure that SMARTCARD frame parity is valid.
00976   * @param __PARITY__ SMARTCARD frame parity.
00977   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00978   */
00979 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00980                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00981
00982 /** @brief Ensure that SMARTCARD communication mode is valid.
00983   * @param __MODE__ SMARTCARD communication mode.
00984   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00985   */
00986 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00987
00988 /** @brief Ensure that SMARTCARD frame polarity is valid.
00989   * @param __CPOL__ SMARTCARD frame polarity.
00990   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00991   */
00992 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
00993                                          || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00994
00995 /** @brief Ensure that SMARTCARD frame phase is valid.
00996   * @param __CPHA__ SMARTCARD frame phase.
00997   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00998   */
00999 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
01000
01001 /** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
01002   * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
01003   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
01004   */
01005 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
01006                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
01007
01008 /** @brief Ensure that SMARTCARD frame sampling is valid.
01009   * @param __ONEBIT__ SMARTCARD frame sampling.
01010   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01011   */
01012 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
01013                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
01014
01015 /** @brief Ensure that SMARTCARD NACK transmission setting is valid.
01016   * @param __NACK__ SMARTCARD NACK transmission setting.
01017   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
01018   */
01019 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
01020                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
01021
01022 /** @brief Ensure that SMARTCARD receiver timeout setting is valid.
01023   * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
01024   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01025   */
01026 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
01027                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
01028
01029 /** @brief Ensure that SMARTCARD clock Prescaler is valid.
01030   * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
01031   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01032   */
01033 #define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
01034                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
01035                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
01036                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
01037                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
01038                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
01039                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
01040                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
01041                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
01042                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
01043                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
01044                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
01045
01046 /** @brief Ensure that SMARTCARD advanced features initialization is valid.
01047   * @param __INIT__ SMARTCARD advanced features initialization.
01048   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01049   */
01050 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
01051                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
01052                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
01053                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
01054                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
01055                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01056                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
01057                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01058
01059 /** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
01060   * @param __TXINV__ SMARTCARD frame TX inversion setting.
01061   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01062   */
01063 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
01064                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
01065
01066 /** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
01067   * @param __RXINV__ SMARTCARD frame RX inversion setting.
01068   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01069   */
01070 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
01071                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
01072
01073 /** @brief Ensure that SMARTCARD frame data inversion setting is valid.
01074   * @param __DATAINV__ SMARTCARD frame data inversion setting.
01075   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01076   */
01077 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
01078                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
01079
01080 /** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
01081   * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
01082   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01083   */
01084 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
01085                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
01086
01087 /** @brief Ensure that SMARTCARD frame overrun setting is valid.
01088   * @param __OVERRUN__ SMARTCARD frame overrun setting.
01089   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01090   */
01091 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
01092                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
01093
01094 /** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
01095   * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
01096   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01097   */
01098 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01099                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
01100
01101 /** @brief Ensure that SMARTCARD frame MSB first setting is valid.
01102   * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
01103   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01104   */
01105 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
01106                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
01107
01108 /** @brief Ensure that SMARTCARD request parameter is valid.
01109   * @param __PARAM__ SMARTCARD request parameter.
01110   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01111   */
01112 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
01113                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
01114
01115 /**
01116   * @}
01117   */
01118
01119 /* Include SMARTCARD HAL Extended module */
01120 #include "stm32g4xx_hal_smartcard_ex.h"
01121
01122 /* Exported functions --------------------------------------------------------*/
01123 /** @addtogroup SMARTCARD_Exported_Functions
01124   * @{
01125   */
01126
01127 /* Initialization and de-initialization functions  ****************************/
01128 /** @addtogroup SMARTCARD_Exported_Functions_Group1
01129   * @{
01130   */
01131
01132 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01133 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01134 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01135 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01136
01137 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01138 /* Callbacks Register/UnRegister functions  ***********************************/
01139 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01140                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
01141                                                  pSMARTCARD_CallbackTypeDef pCallback);
01142 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01143                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
01144 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
01145
01146 /**
01147   * @}
01148   */
01149
01150 /* IO operation functions *****************************************************/
01151 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01152   * @{
01153   */
01154
01155 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
01156                                          uint32_t Timeout);
01157 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
01158                                         uint32_t Timeout);
01159 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
01160 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01161 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
01162 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01163 /* Transfer Abort functions */
01164 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01165 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01166 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01167 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01168 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01169 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01170
01171 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01172 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01173 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01174 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01175 void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01176 void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01177 void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01178
01179 /**
01180   * @}
01181   */
01182
01183 /* Peripheral State and Error functions ***************************************/
01184 /** @addtogroup SMARTCARD_Exported_Functions_Group4
01185   * @{
01186   */
01187
01188 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
01189 uint32_t                   HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
01190
01191 /**
01192   * @}
01193   */
01194
01195 /**
01196   * @}
01197   */
01198
01199 /**
01200   * @}
01201   */
01202
01203 /**
01204   * @}
01205   */
01206
01207 #ifdef __cplusplus
01208 }
01209 #endif
01210
01211 #endif /* STM32G4xx_HAL_SMARTCARD_H */
01212
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_smartcard_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides extended firmware functions to manage the following
00007   *          functionalities of the SmartCard.
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   =============================================================================
00024                ##### SMARTCARD peripheral extended features  #####
00025   =============================================================================
00026   [..]
00027   The Extended SMARTCARD HAL driver can be used as follows:
00028
00029     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00030         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00031         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00032
00033     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00034
00035         -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
00036             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00037             configured prior starting RX/TX transfers.
00038
00039   @endverbatim
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g4xx_hal.h"
00045
00046 /** @addtogroup STM32G4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SMARTCARDEx SMARTCARDEx
00051   * @brief SMARTCARD Extended HAL module driver
00052   * @{
00053   */
00054 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
00059   * @{
00060   */
00061 /* UART RX FIFO depth */
00062 #define RX_FIFO_DEPTH 8U
00063
00064 /* UART TX FIFO depth */
00065 #define TX_FIFO_DEPTH 8U
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
00074
00075 /* Exported functions --------------------------------------------------------*/
00076 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00077   * @{
00078   */
00079
00080 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00081   * @brief    Extended control functions
00082   *
00083 @verbatim
00084   ===============================================================================
00085                       ##### Peripheral Control functions #####
00086   ===============================================================================
00087   [..]
00088   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00089      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00090      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00091      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00092      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /** @brief Update on the fly the SMARTCARD block length in RTOR register.
00099   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00100   *                    the configuration information for the specified SMARTCARD module.
00101   * @param BlockLength SMARTCARD block length (8-bit long at most)
00102   * @retval None
00103   */
00104 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00105 {
00106   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
00107 }
00108
00109 /** @brief Update on the fly the receiver timeout value in RTOR register.
00110   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00111   *                    the configuration information for the specified SMARTCARD module.
00112   * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
00113   *                     value must be less or equal to 0x0FFFFFFFF.
00114   * @retval None
00115   */
00116 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00117 {
00118   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00119   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00120 }
00121
00122 /** @brief Enable the SMARTCARD receiver timeout feature.
00123   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00124   *                    the configuration information for the specified SMARTCARD module.
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00128 {
00129   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00130   {
00131     /* Process Locked */
00132     __HAL_LOCK(hsmartcard);
00133
00134     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00135
00136     /* Set the USART RTOEN bit */
00137     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00138
00139     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00140
00141     /* Process Unlocked */
00142     __HAL_UNLOCK(hsmartcard);
00143
00144     return HAL_OK;
00145   }
00146   else
00147   {
00148     return HAL_BUSY;
00149   }
00150 }
00151
00152 /** @brief Disable the SMARTCARD receiver timeout feature.
00153   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00154   *                    the configuration information for the specified SMARTCARD module.
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00158 {
00159   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00160   {
00161     /* Process Locked */
00162     __HAL_LOCK(hsmartcard);
00163
00164     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00165
00166     /* Clear the USART RTOEN bit */
00167     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00168
00169     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00170
00171     /* Process Unlocked */
00172     __HAL_UNLOCK(hsmartcard);
00173
00174     return HAL_OK;
00175   }
00176   else
00177   {
00178     return HAL_BUSY;
00179   }
00180 }
00181
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
00187   * @brief   SMARTCARD Transmit and Receive functions
00188   *
00189 @verbatim
00190  ===============================================================================
00191                       ##### IO operation functions #####
00192  ===============================================================================
00193     [..]
00194     This subsection provides a set of FIFO mode related callback functions.
00195
00196     (#) TX/RX Fifos Callbacks:
00197         (++) HAL_SMARTCARDEx_RxFifoFullCallback()
00198         (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
00199
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  SMARTCARD RX Fifo full callback.
00206   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00207   *                   the configuration information for the specified SMARTCARD module.
00208   * @retval None
00209   */
00210 __weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hsmartcard);
00214
00215   /* NOTE : This function should not be modified, when the callback is needed,
00216             the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
00217    */
00218 }
00219
00220 /**
00221   * @brief  SMARTCARD TX Fifo empty callback.
00222   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00223   *                   the configuration information for the specified SMARTCARD module.
00224   * @retval None
00225   */
00226 __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00227 {
00228   /* Prevent unused argument(s) compilation warning */
00229   UNUSED(hsmartcard);
00230
00231   /* NOTE : This function should not be modified, when the callback is needed,
00232             the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
00233    */
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
00241   *  @brief   SMARTCARD control functions
00242   *
00243 @verbatim
00244  ===============================================================================
00245                   ##### Peripheral FIFO Control functions #####
00246  ===============================================================================
00247     [..]
00248     This subsection provides a set of functions allowing to control the SMARTCARD
00249     FIFO feature.
00250      (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
00251      (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
00252      (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00253      (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00254 @endverbatim
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Enable the FIFO mode.
00260   * @param hsmartcard SMARTCARD handle.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00264 {
00265   uint32_t tmpcr1;
00266
00267   /* Check parameters */
00268   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00269
00270   /* Process Locked */
00271   __HAL_LOCK(hsmartcard);
00272
00273   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00274
00275   /* Save actual SMARTCARD configuration */
00276   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00277
00278   /* Disable SMARTCARD */
00279   __HAL_SMARTCARD_DISABLE(hsmartcard);
00280
00281   /* Enable FIFO mode */
00282   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00283   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
00284
00285   /* Restore SMARTCARD configuration */
00286   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00287
00288   /* Determine the number of data to process during RX/TX ISR execution */
00289   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00290
00291   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00292
00293   /* Process Unlocked */
00294   __HAL_UNLOCK(hsmartcard);
00295
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Disable the FIFO mode.
00301   * @param hsmartcard SMARTCARD handle.
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00305 {
00306   uint32_t tmpcr1;
00307
00308   /* Check parameters */
00309   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00310
00311   /* Process Locked */
00312   __HAL_LOCK(hsmartcard);
00313
00314   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00315
00316   /* Save actual SMARTCARD configuration */
00317   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00318
00319   /* Disable SMARTCARD */
00320   __HAL_SMARTCARD_DISABLE(hsmartcard);
00321
00322   /* Enable FIFO mode */
00323   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00324   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
00325
00326   /* Restore SMARTCARD configuration */
00327   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00328
00329   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00330
00331   /* Process Unlocked */
00332   __HAL_UNLOCK(hsmartcard);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Set the TXFIFO threshold.
00339   * @param hsmartcard      SMARTCARD handle.
00340   * @param Threshold  TX FIFO threshold value
00341   *          This parameter can be one of the following values:
00342   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
00343   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
00344   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
00345   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
00346   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
00347   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00351 {
00352   uint32_t tmpcr1;
00353
00354   /* Check parameters */
00355   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00356   assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
00357
00358   /* Process Locked */
00359   __HAL_LOCK(hsmartcard);
00360
00361   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00362
00363   /* Save actual SMARTCARD configuration */
00364   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00365
00366   /* Disable SMARTCARD */
00367   __HAL_SMARTCARD_DISABLE(hsmartcard);
00368
00369   /* Update TX threshold configuration */
00370   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00371
00372   /* Determine the number of data to process during RX/TX ISR execution */
00373   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00374
00375   /* Restore SMARTCARD configuration */
00376   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00377
00378   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00379
00380   /* Process Unlocked */
00381   __HAL_UNLOCK(hsmartcard);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Set the RXFIFO threshold.
00388   * @param hsmartcard      SMARTCARD handle.
00389   * @param Threshold  RX FIFO threshold value
00390   *          This parameter can be one of the following values:
00391   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
00392   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
00393   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
00394   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
00395   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
00396   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00400 {
00401   uint32_t tmpcr1;
00402
00403   /* Check parameters */
00404   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00405   assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsmartcard);
00409
00410   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00411
00412   /* Save actual SMARTCARD configuration */
00413   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00414
00415   /* Disable SMARTCARD */
00416   __HAL_SMARTCARD_DISABLE(hsmartcard);
00417
00418   /* Update RX threshold configuration */
00419   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00420
00421   /* Determine the number of data to process during RX/TX ISR execution */
00422   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00423
00424   /* Restore SMARTCARD configuration */
00425   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00426
00427   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00428
00429   /* Process Unlocked */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @}
00437   */
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
00444   * @{
00445   */
00446
00447 /**
00448   * @brief Calculate the number of data to process in RX/TX ISR.
00449   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00450   *       the USART configuration registers.
00451   * @param hsmartcard SMARTCARD handle.
00452   * @retval None
00453   */
00454 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
00455 {
00456   uint8_t rx_fifo_depth;
00457   uint8_t tx_fifo_depth;
00458   uint8_t rx_fifo_threshold;
00459   uint8_t tx_fifo_threshold;
00460   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00461   static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00462   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00463
00464   if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
00465   {
00466     hsmartcard->NbTxDataToProcess = 1U;
00467     hsmartcard->NbRxDataToProcess = 1U;
00468   }
00469   else
00470   {
00471     rx_fifo_depth = RX_FIFO_DEPTH;
00472     tx_fifo_depth = TX_FIFO_DEPTH;
00473     rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00474     tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00475     hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
00476                                     (uint16_t)denominator[tx_fifo_threshold];
00477     hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
00478                                     (uint16_t)denominator[rx_fifo_threshold];
00479   }
00480 }
00481
00482 /**
00483   * @}
00484   */
00485
00486 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00487
00488 /**
00489   * @}
00490   */
00491
00492 /**
00493   * @}
00494   */
00495
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smartcard_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_smartcard_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SMARTCARD_EX_H
00021 #define STM32G4xx_HAL_SMARTCARD_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMARTCARDEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040
00041 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00046   * @{
00047   */
00048 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00049 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00055   * @{
00056   */
00057 #define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
00058 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
00059 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
00060 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
00061 #define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
00062 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
00063 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
00064 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
00065 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
00066 /**
00067   * @}
00068   */
00069
00070 /** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
00071   * @brief    SMARTCARD FIFO mode
00072   * @{
00073   */
00074 #define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00075 #define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
00081   * @brief    SMARTCARD TXFIFO level
00082   * @{
00083   */
00084 #define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00085 #define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
00086 #define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
00087 #define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
00088 #define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
00089 #define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
00095   * @brief    SMARTCARD RXFIFO level
00096   * @{
00097   */
00098 #define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
00099 #define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
00100 #define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
00101 #define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
00102 #define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
00103 #define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00109   *        Elements values convention: 0xXXXX
00110   *           - 0xXXXX  : Flag mask in the ISR register
00111   * @{
00112   */
00113 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
00114 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
00115 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
00116 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
00117 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
00118 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
00119 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
00120 #define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
00121 #define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
00122 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
00123 #define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
00124 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
00125 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
00126 #define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
00127 #define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
00128 #define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
00129 #define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
00130 #define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
00131 #define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
00132 #define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00138   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00139   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00140   *           - XX  : Interrupt source register (2 bits)
00141   *                 - 01: CR1 register
00142   *                 - 10: CR2 register
00143   *                 - 11: CR3 register
00144   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00145   * @{
00146   */
00147 #define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
00148 #define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
00149 #define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
00150 #define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
00151 #define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
00152 #define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
00153 #define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
00154
00155 #define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
00156 #define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
00157 #define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
00158 #define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
00159
00160 #define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
00161 #define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
00162 #define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
00163
00164 #define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
00165 #define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
00166 #define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
00167 #define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00173   * @{
00174   */
00175 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00176 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00177 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
00178 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00179 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00180 #define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
00181 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00182 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00183 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00184 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192 /* Exported macros -----------------------------------------------------------*/
00193 /* Private macros ------------------------------------------------------------*/
00194 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00195   * @{
00196   */
00197
00198 /** @brief  Set the Transmission Completion flag
00199   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00200   * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
00201   *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
00202   *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
00203   * @retval None
00204   */
00205 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
00206   do {                                                                                                       \
00207     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
00208     {                                                                                                        \
00209       (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
00210     }                                                                                                        \
00211     else                                                                                                     \
00212     {                                                                                                        \
00213       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00214     }                                                                                                        \
00215   } while(0U)
00216
00217 /** @brief  Return the transmission completion flag.
00218   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00219   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00220   *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
00221   *        reported.
00222   * @retval Transmission completion flag
00223   */
00224 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
00225   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00226
00227
00228 /** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00229   * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
00230   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00231   */
00232 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
00233                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00234
00235 /** @brief Ensure that SMARTCARD FIFO mode is valid.
00236   * @param __STATE__ SMARTCARD FIFO mode.
00237   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00238   */
00239 #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
00240                                                 ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
00241
00242 /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
00243   * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
00244   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00245   */
00246 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
00247                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
00248                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
00249                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
00250                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
00251                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
00252
00253 /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
00254   * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
00255   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00256   */
00257 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
00258                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
00259                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
00260                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
00261                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
00262                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
00263
00264 /**
00265   * @}
00266   */
00267
00268 /* Exported functions --------------------------------------------------------*/
00269 /** @addtogroup SMARTCARDEx_Exported_Functions
00270   * @{
00271   */
00272
00273 /* Initialization and de-initialization functions  ****************************/
00274 /* IO operation methods *******************************************************/
00275
00276 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00277   * @{
00278   */
00279
00280 /* Peripheral Control functions ***********************************************/
00281 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00282 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00283 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00284 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00285
00286 /**
00287   * @}
00288   */
00289
00290 /* Exported functions --------------------------------------------------------*/
00291 /** @addtogroup SMARTCARDEx_Exported_Functions_Group2
00292   * @{
00293   */
00294
00295 /* IO operation functions *****************************************************/
00296 void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00297 void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00298
00299 /**
00300   * @}
00301   */
00302
00303 /** @addtogroup SMARTCARDEx_Exported_Functions_Group3
00304   * @{
00305   */
00306
00307 /* Peripheral Control functions ***********************************************/
00308 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00309 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00310 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00311 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Private functions ---------------------------------------------------------*/
00322
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 #ifdef __cplusplus
00332 }
00333 #endif
00334
00335 #endif /* STM32G4xx_HAL_SMARTCARD_EX_H */
00336
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_smbus.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the System Management Bus (SMBus) peripheral,
00008   *          based on I2C principles of operation :
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029     The SMBUS HAL driver can be used as follows:
00030
00031     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00032         SMBUS_HandleTypeDef  hsmbus;
00033
00034     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
00035         (##) Enable the SMBUSx interface clock
00036         (##) SMBUS pins configuration
00037             (+++) Enable the clock for the SMBUS GPIOs
00038             (+++) Configure SMBUS pins as alternate function open-drain
00039         (##) NVIC configuration if you need to use interrupt process
00040             (+++) Configure the SMBUSx interrupt priority
00041             (+++) Enable the NVIC SMBUS IRQ Channel
00042
00043     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
00044         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00045         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00046
00047     (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
00048         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049              by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
00050
00051     (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
00052
00053     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00054
00055     *** Interrupt mode IO operation ***
00056     ===================================
00057     [..]
00058       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
00059           using HAL_SMBUS_Master_Transmit_IT()
00060       (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
00061            add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
00062       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
00063           using HAL_SMBUS_Master_Receive_IT()
00064       (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
00065            add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
00066       (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
00067       (++) The associated previous transfer callback is called at the end of abort process
00068       (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00069       (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00070       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00071            using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
00072       (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
00073            add their own code to check the Address Match Code and the transmission direction
00074            request by master/host (Write/Read).
00075       (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
00076            add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
00077       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
00078           using HAL_SMBUS_Slave_Transmit_IT()
00079       (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
00080            add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
00081       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
00082           using HAL_SMBUS_Slave_Receive_IT()
00083       (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
00084            add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
00085       (+) Enable/Disable the SMBUS alert mode using
00086           HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
00087       (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
00088            add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00089            to check the Alert Error Code using function HAL_SMBUS_GetError()
00090       (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
00091       (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
00092            add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00093            to check the Error Code using function HAL_SMBUS_GetError()
00094
00095      *** SMBUS HAL driver macros list ***
00096      ==================================
00097      [..]
00098        Below the list of most used macros in SMBUS HAL driver.
00099
00100       (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
00101       (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
00102       (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
00103       (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
00104       (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
00105       (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
00106
00107      *** Callback registration ***
00108      =============================================
00109     [..]
00110      The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
00111      allows the user to configure dynamically the driver callbacks.
00112      Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
00113      to register an interrupt callback.
00114     [..]
00115      Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
00116        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00117        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00118        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00119        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00120        (+) ListenCpltCallback   : callback for end of listen mode.
00121        (+) ErrorCallback        : callback for error detection.
00122        (+) MspInitCallback      : callback for Msp Init.
00123        (+) MspDeInitCallback    : callback for Msp DeInit.
00124      This function takes as parameters the HAL peripheral handle, the Callback ID
00125      and a pointer to the user callback function.
00126     [..]
00127      For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
00128     [..]
00129      Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
00130      weak function.
00131      HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
00132      and the Callback ID.
00133      This function allows to reset following callbacks:
00134        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00135        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00136        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00137        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00138        (+) ListenCpltCallback   : callback for end of listen mode.
00139        (+) ErrorCallback        : callback for error detection.
00140        (+) MspInitCallback      : callback for Msp Init.
00141        (+) MspDeInitCallback    : callback for Msp DeInit.
00142     [..]
00143      For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
00144     [..]
00145      By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
00146      all callbacks are set to the corresponding weak functions:
00147      examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
00148      Exception done for MspInit and MspDeInit functions that are
00149      reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
00150      these callbacks are null (not registered beforehand).
00151      If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
00152      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00153     [..]
00154      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
00155      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00156      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
00157      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00158      Then, the user first registers the MspInit/MspDeInit user callbacks
00159      using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
00160      or HAL_SMBUS_Init() function.
00161     [..]
00162      When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
00163      not defined, the callback registration feature is not available and all callbacks
00164      are set to the corresponding weak functions.
00165
00166      [..]
00167        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00168
00169   @endverbatim
00170   */
00171
00172 /* Includes ------------------------------------------------------------------*/
00173 #include "stm32g4xx_hal.h"
00174
00175 /** @addtogroup STM32G4xx_HAL_Driver
00176   * @{
00177   */
00178
00179 /** @defgroup SMBUS SMBUS
00180   * @brief SMBUS HAL module driver
00181   * @{
00182   */
00183
00184 #ifdef HAL_SMBUS_MODULE_ENABLED
00185
00186 /* Private typedef -----------------------------------------------------------*/
00187 /* Private constants ---------------------------------------------------------*/
00188 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00189   * @{
00190   */
00191 #define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
00192 #define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
00193 #define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
00194 #define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
00195 #define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
00196 #define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
00197 #define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
00198 #define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
00199 #define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
00200 #define MAX_NBYTE_SIZE      255U
00201 /**
00202   * @}
00203   */
00204
00205 /* Private macro -------------------------------------------------------------*/
00206 /* Private variables ---------------------------------------------------------*/
00207 /* Private function prototypes -----------------------------------------------*/
00208 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00209   * @{
00210   */
00211 /* Private functions to handle flags during polling transfer */
00212 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
00213                                                       FlagStatus Status, uint32_t Timeout);
00214
00215 /* Private functions for SMBUS transfer IRQ handler */
00216 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00217 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00218 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
00219
00220 /* Private functions to centralize the enable/disable of Interrupts */
00221 static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00222 static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00223
00224 /* Private function to flush TXDR register */
00225 static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
00226
00227 /* Private function to handle start, restart or stop a transfer */
00228 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
00229                                  uint32_t Mode, uint32_t Request);
00230
00231 /* Private function to Convert Specific options */
00232 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
00233 /**
00234   * @}
00235   */
00236
00237 /* Exported functions --------------------------------------------------------*/
00238
00239 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00240   * @{
00241   */
00242
00243 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00244   *  @brief    Initialization and Configuration functions
00245   *
00246 @verbatim
00247  ===============================================================================
00248               ##### Initialization and de-initialization functions #####
00249  ===============================================================================
00250     [..]  This subsection provides a set of functions allowing to initialize and
00251           deinitialize the SMBUSx peripheral:
00252
00253       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00254           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00255
00256       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00257           the selected configuration:
00258         (++) Clock Timing
00259         (++) Bus Timeout
00260         (++) Analog Filer mode
00261         (++) Own Address 1
00262         (++) Addressing mode (Master, Slave)
00263         (++) Dual Addressing mode
00264         (++) Own Address 2
00265         (++) Own Address 2 Mask
00266         (++) General call mode
00267         (++) Nostretch mode
00268         (++) Packet Error Check mode
00269         (++) Peripheral mode
00270
00271
00272       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00273           of the selected SMBUSx peripheral.
00274
00275       (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
00276           HAL_SMBUS_ConfigDigitalFilter().
00277
00278 @endverbatim
00279   * @{
00280   */
00281
00282 /**
00283   * @brief  Initialize the SMBUS according to the specified parameters
00284   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00285   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00286   *                the configuration information for the specified SMBUS.
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00290 {
00291   /* Check the SMBUS handle allocation */
00292   if (hsmbus == NULL)
00293   {
00294     return HAL_ERROR;
00295   }
00296
00297   /* Check the parameters */
00298   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00299   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00300   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00301   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00302   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00303   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00304   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00305   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00306   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00307   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00308   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00309
00310   if (hsmbus->State == HAL_SMBUS_STATE_RESET)
00311   {
00312     /* Allocate lock resource and initialize it */
00313     hsmbus->Lock = HAL_UNLOCKED;
00314
00315 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00316     hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00317     hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00318     hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00319     hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00320     hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00321     hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
00322     hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
00323
00324     if (hsmbus->MspInitCallback == NULL)
00325     {
00326       hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
00327     }
00328
00329     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00330     hsmbus->MspInitCallback(hsmbus);
00331 #else
00332     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00333     HAL_SMBUS_MspInit(hsmbus);
00334 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00335   }
00336
00337   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00338
00339   /* Disable the selected SMBUS peripheral */
00340   __HAL_SMBUS_DISABLE(hsmbus);
00341
00342   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00343   /* Configure SMBUSx: Frequency range */
00344   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00345
00346   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00347   /* Configure SMBUSx: Bus Timeout  */
00348   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00349   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00350   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00351
00352   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00353   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00354   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00355
00356   if (hsmbus->Init.OwnAddress1 != 0UL)
00357   {
00358     if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00359     {
00360       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00361     }
00362     else /* SMBUS_ADDRESSINGMODE_10BIT */
00363     {
00364       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00365     }
00366   }
00367
00368   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00369   /* Configure SMBUSx: Addressing Master mode */
00370   if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00371   {
00372     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00373   }
00374   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00375   /* AUTOEND and NACK bit will be manage during Transfer process */
00376   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00377
00378   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00379   /* Configure SMBUSx: Dual mode and Own Address2 */
00380   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
00381                             (hsmbus->Init.OwnAddress2Masks << 8U));
00382
00383   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00384   /* Configure SMBUSx: Generalcall and NoStretch mode */
00385   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
00386                            hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
00387                            hsmbus->Init.AnalogFilter);
00388
00389   /* Enable Slave Byte Control only in case of Packet Error Check is enabled
00390      and SMBUS Peripheral is set in Slave mode */
00391   if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
00392       ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
00393        (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
00394   {
00395     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00396   }
00397
00398   /* Enable the selected SMBUS peripheral */
00399   __HAL_SMBUS_ENABLE(hsmbus);
00400
00401   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00402   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00403   hsmbus->State = HAL_SMBUS_STATE_READY;
00404
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief  DeInitialize the SMBUS peripheral.
00410   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00411   *                the configuration information for the specified SMBUS.
00412   * @retval HAL status
00413   */
00414 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00415 {
00416   /* Check the SMBUS handle allocation */
00417   if (hsmbus == NULL)
00418   {
00419     return HAL_ERROR;
00420   }
00421
00422   /* Check the parameters */
00423   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00424
00425   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00426
00427   /* Disable the SMBUS Peripheral Clock */
00428   __HAL_SMBUS_DISABLE(hsmbus);
00429
00430 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00431   if (hsmbus->MspDeInitCallback == NULL)
00432   {
00433     hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
00434   }
00435
00436   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00437   hsmbus->MspDeInitCallback(hsmbus);
00438 #else
00439   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00440   HAL_SMBUS_MspDeInit(hsmbus);
00441 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00442
00443   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00444   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00445   hsmbus->State = HAL_SMBUS_STATE_RESET;
00446
00447   /* Release Lock */
00448   __HAL_UNLOCK(hsmbus);
00449
00450   return HAL_OK;
00451 }
00452
00453 /**
00454   * @brief Initialize the SMBUS MSP.
00455   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00456   *                the configuration information for the specified SMBUS.
00457   * @retval None
00458   */
00459 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00460 {
00461   /* Prevent unused argument(s) compilation warning */
00462   UNUSED(hsmbus);
00463
00464   /* NOTE : This function should not be modified, when the callback is needed,
00465             the HAL_SMBUS_MspInit could be implemented in the user file
00466    */
00467 }
00468
00469 /**
00470   * @brief DeInitialize the SMBUS MSP.
00471   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00472   *                the configuration information for the specified SMBUS.
00473   * @retval None
00474   */
00475 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00476 {
00477   /* Prevent unused argument(s) compilation warning */
00478   UNUSED(hsmbus);
00479
00480   /* NOTE : This function should not be modified, when the callback is needed,
00481             the HAL_SMBUS_MspDeInit could be implemented in the user file
00482    */
00483 }
00484
00485 /**
00486   * @brief  Configure Analog noise filter.
00487   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00488   *                the configuration information for the specified SMBUS.
00489   * @param  AnalogFilter This parameter can be one of the following values:
00490   *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
00491   *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
00492   * @retval HAL status
00493   */
00494 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
00495 {
00496   /* Check the parameters */
00497   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00498   assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
00499
00500   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00501   {
00502     /* Process Locked */
00503     __HAL_LOCK(hsmbus);
00504
00505     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00506
00507     /* Disable the selected SMBUS peripheral */
00508     __HAL_SMBUS_DISABLE(hsmbus);
00509
00510     /* Reset ANOFF bit */
00511     hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00512
00513     /* Set analog filter bit*/
00514     hsmbus->Instance->CR1 |= AnalogFilter;
00515
00516     __HAL_SMBUS_ENABLE(hsmbus);
00517
00518     hsmbus->State = HAL_SMBUS_STATE_READY;
00519
00520     /* Process Unlocked */
00521     __HAL_UNLOCK(hsmbus);
00522
00523     return HAL_OK;
00524   }
00525   else
00526   {
00527     return HAL_BUSY;
00528   }
00529 }
00530
00531 /**
00532   * @brief  Configure Digital noise filter.
00533   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00534   *                the configuration information for the specified SMBUS.
00535   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
00539 {
00540   uint32_t tmpreg;
00541
00542   /* Check the parameters */
00543   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00544   assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
00545
00546   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00547   {
00548     /* Process Locked */
00549     __HAL_LOCK(hsmbus);
00550
00551     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00552
00553     /* Disable the selected SMBUS peripheral */
00554     __HAL_SMBUS_DISABLE(hsmbus);
00555
00556     /* Get the old register value */
00557     tmpreg = hsmbus->Instance->CR1;
00558
00559     /* Reset I2C DNF bits [11:8] */
00560     tmpreg &= ~(I2C_CR1_DNF);
00561
00562     /* Set I2Cx DNF coefficient */
00563     tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
00564
00565     /* Store the new register value */
00566     hsmbus->Instance->CR1 = tmpreg;
00567
00568     __HAL_SMBUS_ENABLE(hsmbus);
00569
00570     hsmbus->State = HAL_SMBUS_STATE_READY;
00571
00572     /* Process Unlocked */
00573     __HAL_UNLOCK(hsmbus);
00574
00575     return HAL_OK;
00576   }
00577   else
00578   {
00579     return HAL_BUSY;
00580   }
00581 }
00582
00583 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00584 /**
00585   * @brief  Register a User SMBUS Callback
00586   *         To be used instead of the weak predefined callback
00587   * @note   The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
00588   *         HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
00589   *         HAL_SMBUS_MSPDEINIT_CB_ID.
00590   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00591   *                the configuration information for the specified SMBUS.
00592   * @param  CallbackID ID of the callback to be registered
00593   *         This parameter can be one of the following values:
00594   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00595   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00596   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00597   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00598   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00599   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00600   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00601   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00602   * @param  pCallback pointer to the Callback function
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00606                                              HAL_SMBUS_CallbackIDTypeDef CallbackID,
00607                                              pSMBUS_CallbackTypeDef pCallback)
00608 {
00609   HAL_StatusTypeDef status = HAL_OK;
00610
00611   if (pCallback == NULL)
00612   {
00613     /* Update the error code */
00614     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00615
00616     return HAL_ERROR;
00617   }
00618
00619   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00620   {
00621     switch (CallbackID)
00622     {
00623       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00624         hsmbus->MasterTxCpltCallback = pCallback;
00625         break;
00626
00627       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00628         hsmbus->MasterRxCpltCallback = pCallback;
00629         break;
00630
00631       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00632         hsmbus->SlaveTxCpltCallback = pCallback;
00633         break;
00634
00635       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00636         hsmbus->SlaveRxCpltCallback = pCallback;
00637         break;
00638
00639       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00640         hsmbus->ListenCpltCallback = pCallback;
00641         break;
00642
00643       case HAL_SMBUS_ERROR_CB_ID :
00644         hsmbus->ErrorCallback = pCallback;
00645         break;
00646
00647       case HAL_SMBUS_MSPINIT_CB_ID :
00648         hsmbus->MspInitCallback = pCallback;
00649         break;
00650
00651       case HAL_SMBUS_MSPDEINIT_CB_ID :
00652         hsmbus->MspDeInitCallback = pCallback;
00653         break;
00654
00655       default :
00656         /* Update the error code */
00657         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00658
00659         /* Return error status */
00660         status =  HAL_ERROR;
00661         break;
00662     }
00663   }
00664   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00665   {
00666     switch (CallbackID)
00667     {
00668       case HAL_SMBUS_MSPINIT_CB_ID :
00669         hsmbus->MspInitCallback = pCallback;
00670         break;
00671
00672       case HAL_SMBUS_MSPDEINIT_CB_ID :
00673         hsmbus->MspDeInitCallback = pCallback;
00674         break;
00675
00676       default :
00677         /* Update the error code */
00678         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00679
00680         /* Return error status */
00681         status =  HAL_ERROR;
00682         break;
00683     }
00684   }
00685   else
00686   {
00687     /* Update the error code */
00688     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00689
00690     /* Return error status */
00691     status =  HAL_ERROR;
00692   }
00693
00694   return status;
00695 }
00696
00697 /**
00698   * @brief  Unregister an SMBUS Callback
00699   *         SMBUS callback is redirected to the weak predefined callback
00700   * @note   The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
00701   *         HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
00702   *         HAL_SMBUS_MSPDEINIT_CB_ID
00703   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00704   *                the configuration information for the specified SMBUS.
00705   * @param  CallbackID ID of the callback to be unregistered
00706   *         This parameter can be one of the following values:
00707   *         This parameter can be one of the following values:
00708   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00709   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00710   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00711   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00712   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00713   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00714   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00715   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00716   * @retval HAL status
00717   */
00718 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00719                                                HAL_SMBUS_CallbackIDTypeDef CallbackID)
00720 {
00721   HAL_StatusTypeDef status = HAL_OK;
00722
00723   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00724   {
00725     switch (CallbackID)
00726     {
00727       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00728         hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00729         break;
00730
00731       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00732         hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00733         break;
00734
00735       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00736         hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00737         break;
00738
00739       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00740         hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00741         break;
00742
00743       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00744         hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00745         break;
00746
00747       case HAL_SMBUS_ERROR_CB_ID :
00748         hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
00749         break;
00750
00751       case HAL_SMBUS_MSPINIT_CB_ID :
00752         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00753         break;
00754
00755       case HAL_SMBUS_MSPDEINIT_CB_ID :
00756         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00757         break;
00758
00759       default :
00760         /* Update the error code */
00761         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00762
00763         /* Return error status */
00764         status =  HAL_ERROR;
00765         break;
00766     }
00767   }
00768   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00769   {
00770     switch (CallbackID)
00771     {
00772       case HAL_SMBUS_MSPINIT_CB_ID :
00773         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00774         break;
00775
00776       case HAL_SMBUS_MSPDEINIT_CB_ID :
00777         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00778         break;
00779
00780       default :
00781         /* Update the error code */
00782         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00783
00784         /* Return error status */
00785         status =  HAL_ERROR;
00786         break;
00787     }
00788   }
00789   else
00790   {
00791     /* Update the error code */
00792     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00793
00794     /* Return error status */
00795     status =  HAL_ERROR;
00796   }
00797
00798   return status;
00799 }
00800
00801 /**
00802   * @brief  Register the Slave Address Match SMBUS Callback
00803   *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
00804   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00805   *                the configuration information for the specified SMBUS.
00806   * @param  pCallback pointer to the Address Match Callback function
00807   * @retval HAL status
00808   */
00809 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
00810                                                  pSMBUS_AddrCallbackTypeDef pCallback)
00811 {
00812   HAL_StatusTypeDef status = HAL_OK;
00813
00814   if (pCallback == NULL)
00815   {
00816     /* Update the error code */
00817     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00818
00819     return HAL_ERROR;
00820   }
00821
00822   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00823   {
00824     hsmbus->AddrCallback = pCallback;
00825   }
00826   else
00827   {
00828     /* Update the error code */
00829     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00830
00831     /* Return error status */
00832     status =  HAL_ERROR;
00833   }
00834
00835   return status;
00836 }
00837
00838 /**
00839   * @brief  UnRegister the Slave Address Match SMBUS Callback
00840   *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
00841   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00842   *                the configuration information for the specified SMBUS.
00843   * @retval HAL status
00844   */
00845 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
00846 {
00847   HAL_StatusTypeDef status = HAL_OK;
00848
00849   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00850   {
00851     hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
00852   }
00853   else
00854   {
00855     /* Update the error code */
00856     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00857
00858     /* Return error status */
00859     status =  HAL_ERROR;
00860   }
00861
00862   return status;
00863 }
00864
00865 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00866
00867 /**
00868   * @}
00869   */
00870
00871 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00872   *  @brief   Data transfers functions
00873   *
00874 @verbatim
00875  ===============================================================================
00876                       ##### IO operation functions #####
00877  ===============================================================================
00878     [..]
00879     This subsection provides a set of functions allowing to manage the SMBUS data
00880     transfers.
00881
00882     (#) Blocking mode function to check if device is ready for usage is :
00883         (++) HAL_SMBUS_IsDeviceReady()
00884
00885     (#) There is only one mode of transfer:
00886        (++) Non-Blocking mode : The communication is performed using Interrupts.
00887             These functions return the status of the transfer startup.
00888             The end of the data processing will be indicated through the
00889             dedicated SMBUS IRQ when using Interrupt mode.
00890
00891     (#) Non-Blocking mode functions with Interrupt are :
00892         (++) HAL_SMBUS_Master_Transmit_IT()
00893         (++) HAL_SMBUS_Master_Receive_IT()
00894         (++) HAL_SMBUS_Slave_Transmit_IT()
00895         (++) HAL_SMBUS_Slave_Receive_IT()
00896         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00897         (++) HAL_SMBUS_DisableListen_IT()
00898         (++) HAL_SMBUS_EnableAlert_IT()
00899         (++) HAL_SMBUS_DisableAlert_IT()
00900
00901     (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
00902         (++) HAL_SMBUS_MasterTxCpltCallback()
00903         (++) HAL_SMBUS_MasterRxCpltCallback()
00904         (++) HAL_SMBUS_SlaveTxCpltCallback()
00905         (++) HAL_SMBUS_SlaveRxCpltCallback()
00906         (++) HAL_SMBUS_AddrCallback()
00907         (++) HAL_SMBUS_ListenCpltCallback()
00908         (++) HAL_SMBUS_ErrorCallback()
00909
00910 @endverbatim
00911   * @{
00912   */
00913
00914 /**
00915   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00916   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00917   *                the configuration information for the specified SMBUS.
00918   * @param  DevAddress Target device address: The device 7 bits address value
00919   *         in datasheet must be shifted to the left before calling the interface
00920   * @param  pData Pointer to data buffer
00921   * @param  Size Amount of data to be sent
00922   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00926                                                uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00927 {
00928   uint32_t tmp;
00929   uint32_t sizetoxfer;
00930
00931   /* Check the parameters */
00932   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00933
00934   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00935   {
00936     /* Process Locked */
00937     __HAL_LOCK(hsmbus);
00938
00939     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00940     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00941     /* Prepare transfer parameters */
00942     hsmbus->pBuffPtr = pData;
00943     hsmbus->XferCount = Size;
00944     hsmbus->XferOptions = XferOptions;
00945
00946     /* In case of Quick command, remove autoend mode */
00947     /* Manage the stop generation by software */
00948     if (hsmbus->pBuffPtr == NULL)
00949     {
00950       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00951     }
00952
00953     if (Size > MAX_NBYTE_SIZE)
00954     {
00955       hsmbus->XferSize = MAX_NBYTE_SIZE;
00956     }
00957     else
00958     {
00959       hsmbus->XferSize = Size;
00960     }
00961
00962     sizetoxfer = hsmbus->XferSize;
00963     if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
00964                               (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
00965                               (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
00966                               (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
00967     {
00968       if (hsmbus->pBuffPtr != NULL)
00969       {
00970         /* Preload TX register */
00971         /* Write data to TXDR */
00972         hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
00973
00974         /* Increment Buffer pointer */
00975         hsmbus->pBuffPtr++;
00976
00977         hsmbus->XferCount--;
00978         hsmbus->XferSize--;
00979       }
00980       else
00981       {
00982         return HAL_ERROR;
00983       }
00984     }
00985
00986     /* Send Slave Address */
00987     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00988     if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE))
00989     {
00990       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
00991                            SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
00992                            SMBUS_GENERATE_START_WRITE);
00993     }
00994     else
00995     {
00996       /* If transfer direction not change, do not generate Restart Condition */
00997       /* Mean Previous state is same as current state */
00998
00999       /* Store current volatile XferOptions, misra rule */
01000       tmp = hsmbus->XferOptions;
01001
01002       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
01003           (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
01004       {
01005         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions,
01006                              SMBUS_NO_STARTSTOP);
01007       }
01008       /* Else transfer direction change, so generate Restart with new transfer direction */
01009       else
01010       {
01011         /* Convert OTHER_xxx XferOptions if any */
01012         SMBUS_ConvertOtherXferOptions(hsmbus);
01013
01014         /* Handle Transfer */
01015         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
01016                              hsmbus->XferOptions,
01017                              SMBUS_GENERATE_START_WRITE);
01018       }
01019
01020       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
01021       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01022       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01023       {
01024         if (hsmbus->XferSize > 0U)
01025         {
01026           hsmbus->XferSize--;
01027           hsmbus->XferCount--;
01028         }
01029         else
01030         {
01031           return HAL_ERROR;
01032         }
01033       }
01034     }
01035
01036     /* Process Unlocked */
01037     __HAL_UNLOCK(hsmbus);
01038
01039     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01040               to avoid the risk of SMBUS interrupt handle execution before current
01041               process unlock */
01042     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01043
01044     return HAL_OK;
01045   }
01046   else
01047   {
01048     return HAL_BUSY;
01049   }
01050 }
01051
01052 /**
01053   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
01054   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01055   *                the configuration information for the specified SMBUS.
01056   * @param  DevAddress Target device address: The device 7 bits address value
01057   *         in datasheet must be shifted to the left before calling the interface
01058   * @param  pData Pointer to data buffer
01059   * @param  Size Amount of data to be sent
01060   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01061   * @retval HAL status
01062   */
01063 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
01064                                               uint16_t Size, uint32_t XferOptions)
01065 {
01066   uint32_t tmp;
01067
01068   /* Check the parameters */
01069   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01070
01071   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01072   {
01073     /* Process Locked */
01074     __HAL_LOCK(hsmbus);
01075
01076     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01077     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01078
01079     /* Prepare transfer parameters */
01080     hsmbus->pBuffPtr = pData;
01081     hsmbus->XferCount = Size;
01082     hsmbus->XferOptions = XferOptions;
01083
01084     /* In case of Quick command, remove autoend mode */
01085     /* Manage the stop generation by software */
01086     if (hsmbus->pBuffPtr == NULL)
01087     {
01088       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
01089     }
01090
01091     if (Size > MAX_NBYTE_SIZE)
01092     {
01093       hsmbus->XferSize = MAX_NBYTE_SIZE;
01094     }
01095     else
01096     {
01097       hsmbus->XferSize = Size;
01098     }
01099
01100     /* Send Slave Address */
01101     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01102     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01103     {
01104       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
01105                            SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
01106                            SMBUS_GENERATE_START_READ);
01107     }
01108     else
01109     {
01110       /* If transfer direction not change, do not generate Restart Condition */
01111       /* Mean Previous state is same as current state */
01112
01113       /* Store current volatile XferOptions, Misra rule */
01114       tmp = hsmbus->XferOptions;
01115
01116       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
01117           (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
01118       {
01119         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01120                              SMBUS_NO_STARTSTOP);
01121       }
01122       /* Else transfer direction change, so generate Restart with new transfer direction */
01123       else
01124       {
01125         /* Convert OTHER_xxx XferOptions if any */
01126         SMBUS_ConvertOtherXferOptions(hsmbus);
01127
01128         /* Handle Transfer */
01129         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
01130                              hsmbus->XferOptions,
01131                              SMBUS_GENERATE_START_READ);
01132       }
01133     }
01134
01135     /* Process Unlocked */
01136     __HAL_UNLOCK(hsmbus);
01137
01138     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01139               to avoid the risk of SMBUS interrupt handle execution before current
01140               process unlock */
01141     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01142
01143     return HAL_OK;
01144   }
01145   else
01146   {
01147     return HAL_BUSY;
01148   }
01149 }
01150
01151 /**
01152   * @brief  Abort a master/host SMBUS process communication with Interrupt.
01153   * @note   This abort can be called only if state is ready
01154   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01155   *                the configuration information for the specified SMBUS.
01156   * @param  DevAddress Target device address: The device 7 bits address value
01157   *         in datasheet must be shifted to the left before calling the interface
01158   * @retval HAL status
01159   */
01160 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
01161 {
01162   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01163   {
01164     /* Process Locked */
01165     __HAL_LOCK(hsmbus);
01166
01167     /* Keep the same state as previous */
01168     /* to perform as well the call of the corresponding end of transfer callback */
01169     if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01170     {
01171       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
01172     }
01173     else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01174     {
01175       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01176     }
01177     else
01178     {
01179       /* Wrong usage of abort function */
01180       /* This function should be used only in case of abort monitored by master device */
01181       return HAL_ERROR;
01182     }
01183     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01184
01185     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
01186     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
01187     SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
01188
01189     /* Process Unlocked */
01190     __HAL_UNLOCK(hsmbus);
01191
01192     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01193               to avoid the risk of SMBUS interrupt handle execution before current
01194               process unlock */
01195     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01196     {
01197       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01198     }
01199     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01200     {
01201       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01202     }
01203     else
01204     {
01205       /* Nothing to do */
01206     }
01207
01208     return HAL_OK;
01209   }
01210   else
01211   {
01212     return HAL_BUSY;
01213   }
01214 }
01215
01216 /**
01217   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01218   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01219   *                the configuration information for the specified SMBUS.
01220   * @param  pData Pointer to data buffer
01221   * @param  Size Amount of data to be sent
01222   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01223   * @retval HAL status
01224   */
01225 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
01226                                               uint32_t XferOptions)
01227 {
01228   /* Check the parameters */
01229   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01230
01231   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01232   {
01233     if ((pData == NULL) || (Size == 0UL))
01234     {
01235       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01236       return HAL_ERROR;
01237     }
01238
01239     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01240     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
01241
01242     /* Process Locked */
01243     __HAL_LOCK(hsmbus);
01244
01245     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
01246     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01247
01248     /* Set SBC bit to manage Acknowledge at each bit */
01249     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01250
01251     /* Enable Address Acknowledge */
01252     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01253
01254     /* Prepare transfer parameters */
01255     hsmbus->pBuffPtr = pData;
01256     hsmbus->XferCount = Size;
01257     hsmbus->XferOptions = XferOptions;
01258
01259     /* Convert OTHER_xxx XferOptions if any */
01260     SMBUS_ConvertOtherXferOptions(hsmbus);
01261
01262     if (Size > MAX_NBYTE_SIZE)
01263     {
01264       hsmbus->XferSize = MAX_NBYTE_SIZE;
01265     }
01266     else
01267     {
01268       hsmbus->XferSize = Size;
01269     }
01270
01271     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01272     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01273     {
01274       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
01275                            SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
01276                            SMBUS_NO_STARTSTOP);
01277     }
01278     else
01279     {
01280       /* Set NBYTE to transmit */
01281       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01282                            SMBUS_NO_STARTSTOP);
01283
01284       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01285       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01286       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01287       {
01288         hsmbus->XferSize--;
01289         hsmbus->XferCount--;
01290       }
01291     }
01292
01293     /* Clear ADDR flag after prepare the transfer parameters */
01294     /* This action will generate an acknowledge to the HOST */
01295     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01296
01297     /* Process Unlocked */
01298     __HAL_UNLOCK(hsmbus);
01299
01300     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01301               to avoid the risk of SMBUS interrupt handle execution before current
01302               process unlock */
01303     /* REnable ADDR interrupt */
01304     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
01305
01306     return HAL_OK;
01307   }
01308   else
01309   {
01310     return HAL_BUSY;
01311   }
01312 }
01313
01314 /**
01315   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01316   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01317   *                the configuration information for the specified SMBUS.
01318   * @param  pData Pointer to data buffer
01319   * @param  Size Amount of data to be sent
01320   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
01324                                              uint32_t XferOptions)
01325 {
01326   /* Check the parameters */
01327   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01328
01329   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01330   {
01331     if ((pData == NULL) || (Size == 0UL))
01332     {
01333       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01334       return HAL_ERROR;
01335     }
01336
01337     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01338     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
01339
01340     /* Process Locked */
01341     __HAL_LOCK(hsmbus);
01342
01343     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
01344     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01345
01346     /* Set SBC bit to manage Acknowledge at each bit */
01347     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01348
01349     /* Enable Address Acknowledge */
01350     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01351
01352     /* Prepare transfer parameters */
01353     hsmbus->pBuffPtr = pData;
01354     hsmbus->XferSize = Size;
01355     hsmbus->XferCount = Size;
01356     hsmbus->XferOptions = XferOptions;
01357
01358     /* Convert OTHER_xxx XferOptions if any */
01359     SMBUS_ConvertOtherXferOptions(hsmbus);
01360
01361     /* Set NBYTE to receive */
01362     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
01363     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
01364     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
01365     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
01366     if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
01367     {
01368       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01369                            SMBUS_NO_STARTSTOP);
01370     }
01371     else
01372     {
01373       SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
01374     }
01375
01376     /* Clear ADDR flag after prepare the transfer parameters */
01377     /* This action will generate an acknowledge to the HOST */
01378     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01379
01380     /* Process Unlocked */
01381     __HAL_UNLOCK(hsmbus);
01382
01383     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01384               to avoid the risk of SMBUS interrupt handle execution before current
01385               process unlock */
01386     /* REnable ADDR interrupt */
01387     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
01388
01389     return HAL_OK;
01390   }
01391   else
01392   {
01393     return HAL_BUSY;
01394   }
01395 }
01396
01397 /**
01398   * @brief  Enable the Address listen mode with Interrupt.
01399   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01400   *                the configuration information for the specified SMBUS.
01401   * @retval HAL status
01402   */
01403 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01404 {
01405   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01406
01407   /* Enable the Address Match interrupt */
01408   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
01409
01410   return HAL_OK;
01411 }
01412
01413 /**
01414   * @brief  Disable the Address listen mode with Interrupt.
01415   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01416   *                the configuration information for the specified SMBUS.
01417   * @retval HAL status
01418   */
01419 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01420 {
01421   /* Disable Address listen mode only if a transfer is not ongoing */
01422   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01423   {
01424     hsmbus->State = HAL_SMBUS_STATE_READY;
01425
01426     /* Disable the Address Match interrupt */
01427     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01428
01429     return HAL_OK;
01430   }
01431   else
01432   {
01433     return HAL_BUSY;
01434   }
01435 }
01436
01437 /**
01438   * @brief  Enable the SMBUS alert mode with Interrupt.
01439   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01440   *                the configuration information for the specified SMBUSx peripheral.
01441   * @retval HAL status
01442   */
01443 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01444 {
01445   /* Enable SMBus alert */
01446   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
01447
01448   /* Clear ALERT flag */
01449   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01450
01451   /* Enable Alert Interrupt */
01452   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
01453
01454   return HAL_OK;
01455 }
01456 /**
01457   * @brief  Disable the SMBUS alert mode with Interrupt.
01458   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01459   *                the configuration information for the specified SMBUSx peripheral.
01460   * @retval HAL status
01461   */
01462 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01463 {
01464   /* Enable SMBus alert */
01465   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
01466
01467   /* Disable Alert Interrupt */
01468   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
01469
01470   return HAL_OK;
01471 }
01472
01473 /**
01474   * @brief  Check if target device is ready for communication.
01475   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01476   *                the configuration information for the specified SMBUS.
01477   * @param  DevAddress Target device address: The device 7 bits address value
01478   *         in datasheet must be shifted to the left before calling the interface
01479   * @param  Trials Number of trials
01480   * @param  Timeout Timeout duration
01481   * @retval HAL status
01482   */
01483 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
01484                                           uint32_t Timeout)
01485 {
01486   uint32_t tickstart;
01487
01488   __IO uint32_t SMBUS_Trials = 0UL;
01489
01490   FlagStatus tmp1;
01491   FlagStatus tmp2;
01492
01493   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01494   {
01495     if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
01496     {
01497       return HAL_BUSY;
01498     }
01499
01500     /* Process Locked */
01501     __HAL_LOCK(hsmbus);
01502
01503     hsmbus->State = HAL_SMBUS_STATE_BUSY;
01504     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01505
01506     do
01507     {
01508       /* Generate Start */
01509       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
01510
01511       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01512       /* Wait until STOPF flag is set or a NACK flag is set*/
01513       tickstart = HAL_GetTick();
01514
01515       tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01516       tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01517
01518       while ((tmp1 == RESET) && (tmp2 == RESET))
01519       {
01520         if (Timeout != HAL_MAX_DELAY)
01521         {
01522           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01523           {
01524             /* Device is ready */
01525             hsmbus->State = HAL_SMBUS_STATE_READY;
01526
01527             /* Update SMBUS error code */
01528             hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01529
01530             /* Process Unlocked */
01531             __HAL_UNLOCK(hsmbus);
01532             return HAL_ERROR;
01533           }
01534         }
01535
01536         tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01537         tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01538       }
01539
01540       /* Check if the NACKF flag has not been set */
01541       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
01542       {
01543         /* Wait until STOPF flag is reset */
01544         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01545         {
01546           return HAL_ERROR;
01547         }
01548
01549         /* Clear STOP Flag */
01550         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01551
01552         /* Device is ready */
01553         hsmbus->State = HAL_SMBUS_STATE_READY;
01554
01555         /* Process Unlocked */
01556         __HAL_UNLOCK(hsmbus);
01557
01558         return HAL_OK;
01559       }
01560       else
01561       {
01562         /* Wait until STOPF flag is reset */
01563         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01564         {
01565           return HAL_ERROR;
01566         }
01567
01568         /* Clear NACK Flag */
01569         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01570
01571         /* Clear STOP Flag, auto generated with autoend*/
01572         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01573       }
01574
01575       /* Check if the maximum allowed number of trials has been reached */
01576       if (SMBUS_Trials == Trials)
01577       {
01578         /* Generate Stop */
01579         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01580
01581         /* Wait until STOPF flag is reset */
01582         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01583         {
01584           return HAL_ERROR;
01585         }
01586
01587         /* Clear STOP Flag */
01588         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01589       }
01590
01591       /* Increment Trials */
01592       SMBUS_Trials++;
01593     } while (SMBUS_Trials < Trials);
01594
01595     hsmbus->State = HAL_SMBUS_STATE_READY;
01596
01597     /* Update SMBUS error code */
01598     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01599
01600     /* Process Unlocked */
01601     __HAL_UNLOCK(hsmbus);
01602
01603     return HAL_ERROR;
01604   }
01605   else
01606   {
01607     return HAL_BUSY;
01608   }
01609 }
01610 /**
01611   * @}
01612   */
01613
01614 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01615   * @{
01616   */
01617
01618 /**
01619   * @brief  Handle SMBUS event interrupt request.
01620   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01621   *                the configuration information for the specified SMBUS.
01622   * @retval None
01623   */
01624 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01625 {
01626   /* Use a local variable to store the current ISR flags */
01627   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01628   uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
01629   uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
01630
01631   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01632   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
01633                                            SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
01634       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
01635        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
01636        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
01637        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01638        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01639   {
01640     /* Slave mode selected */
01641     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01642     {
01643       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01644     }
01645     /* Master mode selected */
01646     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01647     {
01648       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01649     }
01650     else
01651     {
01652       /* Nothing to do */
01653     }
01654   }
01655
01656   /* SMBUS in mode Receiver ----------------------------------------------------*/
01657   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
01658                                            SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
01659       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
01660        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
01661        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
01662        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01663        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01664   {
01665     /* Slave mode selected */
01666     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01667     {
01668       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01669     }
01670     /* Master mode selected */
01671     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01672     {
01673       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01674     }
01675     else
01676     {
01677       /* Nothing to do */
01678     }
01679   }
01680
01681   /* SMBUS in mode Listener Only --------------------------------------------------*/
01682   if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
01683        (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
01684        (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
01685       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
01686        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01687        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01688   {
01689     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01690     {
01691       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01692     }
01693   }
01694 }
01695
01696 /**
01697   * @brief  Handle SMBUS error interrupt request.
01698   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01699   *                the configuration information for the specified SMBUS.
01700   * @retval None
01701   */
01702 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01703 {
01704   SMBUS_ITErrorHandler(hsmbus);
01705 }
01706
01707 /**
01708   * @brief  Master Tx Transfer completed callback.
01709   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01710   *                the configuration information for the specified SMBUS.
01711   * @retval None
01712   */
01713 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01714 {
01715   /* Prevent unused argument(s) compilation warning */
01716   UNUSED(hsmbus);
01717
01718   /* NOTE : This function should not be modified, when the callback is needed,
01719             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01720    */
01721 }
01722
01723 /**
01724   * @brief  Master Rx Transfer completed callback.
01725   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01726   *                the configuration information for the specified SMBUS.
01727   * @retval None
01728   */
01729 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01730 {
01731   /* Prevent unused argument(s) compilation warning */
01732   UNUSED(hsmbus);
01733
01734   /* NOTE : This function should not be modified, when the callback is needed,
01735             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01736    */
01737 }
01738
01739 /** @brief  Slave Tx Transfer completed callback.
01740   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01741   *                the configuration information for the specified SMBUS.
01742   * @retval None
01743   */
01744 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01745 {
01746   /* Prevent unused argument(s) compilation warning */
01747   UNUSED(hsmbus);
01748
01749   /* NOTE : This function should not be modified, when the callback is needed,
01750             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01751    */
01752 }
01753
01754 /**
01755   * @brief  Slave Rx Transfer completed callback.
01756   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01757   *                the configuration information for the specified SMBUS.
01758   * @retval None
01759   */
01760 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01761 {
01762   /* Prevent unused argument(s) compilation warning */
01763   UNUSED(hsmbus);
01764
01765   /* NOTE : This function should not be modified, when the callback is needed,
01766             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01767    */
01768 }
01769
01770 /**
01771   * @brief  Slave Address Match callback.
01772   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01773   *                the configuration information for the specified SMBUS.
01774   * @param  TransferDirection Master request Transfer Direction (Write/Read)
01775   * @param  AddrMatchCode Address Match Code
01776   * @retval None
01777   */
01778 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
01779                                    uint16_t AddrMatchCode)
01780 {
01781   /* Prevent unused argument(s) compilation warning */
01782   UNUSED(hsmbus);
01783   UNUSED(TransferDirection);
01784   UNUSED(AddrMatchCode);
01785
01786   /* NOTE : This function should not be modified, when the callback is needed,
01787             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01788    */
01789 }
01790
01791 /**
01792   * @brief  Listen Complete callback.
01793   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01794   *                the configuration information for the specified SMBUS.
01795   * @retval None
01796   */
01797 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01798 {
01799   /* Prevent unused argument(s) compilation warning */
01800   UNUSED(hsmbus);
01801
01802   /* NOTE : This function should not be modified, when the callback is needed,
01803             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01804    */
01805 }
01806
01807 /**
01808   * @brief  SMBUS error callback.
01809   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01810   *                the configuration information for the specified SMBUS.
01811   * @retval None
01812   */
01813 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01814 {
01815   /* Prevent unused argument(s) compilation warning */
01816   UNUSED(hsmbus);
01817
01818   /* NOTE : This function should not be modified, when the callback is needed,
01819             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01820    */
01821 }
01822
01823 /**
01824   * @}
01825   */
01826
01827 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01828   *  @brief   Peripheral State and Errors functions
01829   *
01830 @verbatim
01831  ===============================================================================
01832             ##### Peripheral State and Errors functions #####
01833  ===============================================================================
01834     [..]
01835     This subsection permits to get in run-time the status of the peripheral
01836     and the data flow.
01837
01838 @endverbatim
01839   * @{
01840   */
01841
01842 /**
01843   * @brief  Return the SMBUS handle state.
01844   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01845   *                the configuration information for the specified SMBUS.
01846   * @retval HAL state
01847   */
01848 uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
01849 {
01850   /* Return SMBUS handle state */
01851   return hsmbus->State;
01852 }
01853
01854 /**
01855   * @brief  Return the SMBUS error code.
01856   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01857   *              the configuration information for the specified SMBUS.
01858   * @retval SMBUS Error Code
01859   */
01860 uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
01861 {
01862   return hsmbus->ErrorCode;
01863 }
01864
01865 /**
01866   * @}
01867   */
01868
01869 /**
01870   * @}
01871   */
01872
01873 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01874   *  @brief   Data transfers Private functions
01875   * @{
01876   */
01877
01878 /**
01879   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01880   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01881   *                the configuration information for the specified SMBUS.
01882   * @param  StatusFlags Value of Interrupt Flags.
01883   * @retval HAL status
01884   */
01885 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
01886 {
01887   uint16_t DevAddress;
01888
01889   /* Process Locked */
01890   __HAL_LOCK(hsmbus);
01891
01892   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
01893   {
01894     /* Clear NACK Flag */
01895     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01896
01897     /* Set corresponding Error Code */
01898     /* No need to generate STOP, it is automatically done */
01899     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01900
01901     /* Flush TX register */
01902     SMBUS_Flush_TXDR(hsmbus);
01903
01904     /* Process Unlocked */
01905     __HAL_UNLOCK(hsmbus);
01906
01907     /* Call the Error callback to inform upper layer */
01908 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01909     hsmbus->ErrorCallback(hsmbus);
01910 #else
01911     HAL_SMBUS_ErrorCallback(hsmbus);
01912 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01913   }
01914   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
01915   {
01916     /* Check and treat errors if errors occurs during STOP process */
01917     SMBUS_ITErrorHandler(hsmbus);
01918
01919     /* Call the corresponding callback to inform upper layer of End of Transfer */
01920     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01921     {
01922       /* Disable Interrupt */
01923       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01924
01925       /* Clear STOP Flag */
01926       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01927
01928       /* Clear Configuration Register 2 */
01929       SMBUS_RESET_CR2(hsmbus);
01930
01931       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01932       /* Disable the selected SMBUS peripheral */
01933       __HAL_SMBUS_DISABLE(hsmbus);
01934
01935       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01936       hsmbus->State = HAL_SMBUS_STATE_READY;
01937
01938       /* Process Unlocked */
01939       __HAL_UNLOCK(hsmbus);
01940
01941       /* Re-enable the selected SMBUS peripheral */
01942       __HAL_SMBUS_ENABLE(hsmbus);
01943
01944       /* Call the corresponding callback to inform upper layer of End of Transfer */
01945 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01946       hsmbus->MasterTxCpltCallback(hsmbus);
01947 #else
01948       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01949 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01950     }
01951     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01952     {
01953       /* Store Last receive data if any */
01954       if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01955       {
01956         /* Read data from RXDR */
01957         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01958
01959         /* Increment Buffer pointer */
01960         hsmbus->pBuffPtr++;
01961
01962         if ((hsmbus->XferSize > 0U))
01963         {
01964           hsmbus->XferSize--;
01965           hsmbus->XferCount--;
01966         }
01967       }
01968
01969       /* Disable Interrupt */
01970       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01971
01972       /* Clear STOP Flag */
01973       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01974
01975       /* Clear Configuration Register 2 */
01976       SMBUS_RESET_CR2(hsmbus);
01977
01978       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01979       hsmbus->State = HAL_SMBUS_STATE_READY;
01980
01981       /* Process Unlocked */
01982       __HAL_UNLOCK(hsmbus);
01983
01984       /* Call the corresponding callback to inform upper layer of End of Transfer */
01985 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01986       hsmbus->MasterRxCpltCallback(hsmbus);
01987 #else
01988       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01989 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01990     }
01991     else
01992     {
01993       /* Nothing to do */
01994     }
01995   }
01996   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01997   {
01998     /* Read data from RXDR */
01999     *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02000
02001     /* Increment Buffer pointer */
02002     hsmbus->pBuffPtr++;
02003
02004     /* Increment Size counter */
02005     hsmbus->XferSize--;
02006     hsmbus->XferCount--;
02007   }
02008   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
02009   {
02010     /* Write data to TXDR */
02011     hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
02012
02013     /* Increment Buffer pointer */
02014     hsmbus->pBuffPtr++;
02015
02016     /* Increment Size counter */
02017     hsmbus->XferSize--;
02018     hsmbus->XferCount--;
02019   }
02020   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
02021   {
02022     if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
02023     {
02024       DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
02025
02026       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
02027       {
02028         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
02029                              (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
02030                              SMBUS_NO_STARTSTOP);
02031         hsmbus->XferSize = MAX_NBYTE_SIZE;
02032       }
02033       else
02034       {
02035         hsmbus->XferSize = hsmbus->XferCount;
02036         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
02037                              SMBUS_NO_STARTSTOP);
02038         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02039         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02040         if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02041         {
02042           hsmbus->XferSize--;
02043           hsmbus->XferCount--;
02044         }
02045       }
02046     }
02047     else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
02048     {
02049       /* Call TxCpltCallback() if no stop mode is set */
02050       if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02051       {
02052         /* Call the corresponding callback to inform upper layer of End of Transfer */
02053         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02054         {
02055           /* Disable Interrupt */
02056           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02057           hsmbus->PreviousState = hsmbus->State;
02058           hsmbus->State = HAL_SMBUS_STATE_READY;
02059
02060           /* Process Unlocked */
02061           __HAL_UNLOCK(hsmbus);
02062
02063           /* Call the corresponding callback to inform upper layer of End of Transfer */
02064 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02065           hsmbus->MasterTxCpltCallback(hsmbus);
02066 #else
02067           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02068 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02069         }
02070         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02071         {
02072           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02073           hsmbus->PreviousState = hsmbus->State;
02074           hsmbus->State = HAL_SMBUS_STATE_READY;
02075
02076           /* Process Unlocked */
02077           __HAL_UNLOCK(hsmbus);
02078
02079           /* Call the corresponding callback to inform upper layer of End of Transfer */
02080 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02081           hsmbus->MasterRxCpltCallback(hsmbus);
02082 #else
02083           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02084 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02085         }
02086         else
02087         {
02088           /* Nothing to do */
02089         }
02090       }
02091     }
02092     else
02093     {
02094       /* Nothing to do */
02095     }
02096   }
02097   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
02098   {
02099     if (hsmbus->XferCount == 0U)
02100     {
02101       /* Specific use case for Quick command */
02102       if (hsmbus->pBuffPtr == NULL)
02103       {
02104         /* Generate a Stop command */
02105         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
02106       }
02107       /* Call TxCpltCallback() if no stop mode is set */
02108       else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02109       {
02110         /* No Generate Stop, to permit restart mode */
02111         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
02112
02113         /* Call the corresponding callback to inform upper layer of End of Transfer */
02114         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02115         {
02116           /* Disable Interrupt */
02117           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02118           hsmbus->PreviousState = hsmbus->State;
02119           hsmbus->State = HAL_SMBUS_STATE_READY;
02120
02121           /* Process Unlocked */
02122           __HAL_UNLOCK(hsmbus);
02123
02124           /* Call the corresponding callback to inform upper layer of End of Transfer */
02125 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02126           hsmbus->MasterTxCpltCallback(hsmbus);
02127 #else
02128           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02129 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02130         }
02131         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02132         {
02133           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02134           hsmbus->PreviousState = hsmbus->State;
02135           hsmbus->State = HAL_SMBUS_STATE_READY;
02136
02137           /* Process Unlocked */
02138           __HAL_UNLOCK(hsmbus);
02139
02140           /* Call the corresponding callback to inform upper layer of End of Transfer */
02141 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02142           hsmbus->MasterRxCpltCallback(hsmbus);
02143 #else
02144           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02145 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02146         }
02147         else
02148         {
02149           /* Nothing to do */
02150         }
02151       }
02152       else
02153       {
02154         /* Nothing to do */
02155       }
02156     }
02157   }
02158   else
02159   {
02160     /* Nothing to do */
02161   }
02162
02163   /* Process Unlocked */
02164   __HAL_UNLOCK(hsmbus);
02165
02166   return HAL_OK;
02167 }
02168 /**
02169   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
02170   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02171   *                the configuration information for the specified SMBUS.
02172   * @param  StatusFlags Value of Interrupt Flags.
02173   * @retval HAL status
02174   */
02175 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
02176 {
02177   uint8_t TransferDirection;
02178   uint16_t SlaveAddrCode;
02179
02180   /* Process Locked */
02181   __HAL_LOCK(hsmbus);
02182
02183   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
02184   {
02185     /* Check that SMBUS transfer finished */
02186     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
02187     /* Mean XferCount == 0*/
02188     /* So clear Flag NACKF only */
02189     if (hsmbus->XferCount == 0U)
02190     {
02191       /* Clear NACK Flag */
02192       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02193
02194       /* Flush TX register */
02195       SMBUS_Flush_TXDR(hsmbus);
02196
02197       /* Process Unlocked */
02198       __HAL_UNLOCK(hsmbus);
02199     }
02200     else
02201     {
02202       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
02203       /* Clear NACK Flag */
02204       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02205
02206       /* Set HAL State to "Idle" State, mean to LISTEN state */
02207       /* So reset Slave Busy state */
02208       hsmbus->PreviousState = hsmbus->State;
02209       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02210       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02211
02212       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
02213       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02214
02215       /* Set ErrorCode corresponding to a Non-Acknowledge */
02216       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
02217
02218       /* Flush TX register */
02219       SMBUS_Flush_TXDR(hsmbus);
02220
02221       /* Process Unlocked */
02222       __HAL_UNLOCK(hsmbus);
02223
02224       /* Call the Error callback to inform upper layer */
02225 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02226       hsmbus->ErrorCallback(hsmbus);
02227 #else
02228       HAL_SMBUS_ErrorCallback(hsmbus);
02229 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02230     }
02231   }
02232   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
02233   {
02234     TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
02235     SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
02236
02237     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
02238     /* Other ADDRInterrupt will be treat in next Listen usecase */
02239     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
02240
02241     /* Process Unlocked */
02242     __HAL_UNLOCK(hsmbus);
02243
02244     /* Call Slave Addr callback */
02245 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02246     hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02247 #else
02248     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02249 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02250   }
02251   else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
02252            (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
02253   {
02254     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
02255     {
02256       /* Read data from RXDR */
02257       *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02258
02259       /* Increment Buffer pointer */
02260       hsmbus->pBuffPtr++;
02261
02262       hsmbus->XferSize--;
02263       hsmbus->XferCount--;
02264
02265       if (hsmbus->XferCount == 1U)
02266       {
02267         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
02268         /* or only the last Byte of Transfer */
02269         /* So reset the RELOAD bit mode */
02270         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
02271         SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02272       }
02273       else if (hsmbus->XferCount == 0U)
02274       {
02275         /* Last Byte is received, disable Interrupt */
02276         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02277
02278         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
02279         hsmbus->PreviousState = hsmbus->State;
02280         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02281
02282         /* Process Unlocked */
02283         __HAL_UNLOCK(hsmbus);
02284
02285         /* Call the corresponding callback to inform upper layer of End of Transfer */
02286 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02287         hsmbus->SlaveRxCpltCallback(hsmbus);
02288 #else
02289         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
02290 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02291       }
02292       else
02293       {
02294         /* Set Reload for next Bytes */
02295         SMBUS_TransferConfig(hsmbus, 0, 1,
02296                              SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
02297                              SMBUS_NO_STARTSTOP);
02298
02299         /* Ack last Byte Read */
02300         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
02301       }
02302     }
02303     else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02304     {
02305       if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
02306       {
02307         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
02308         {
02309           SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
02310                                (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
02311                                SMBUS_NO_STARTSTOP);
02312           hsmbus->XferSize = MAX_NBYTE_SIZE;
02313         }
02314         else
02315         {
02316           hsmbus->XferSize = hsmbus->XferCount;
02317           SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
02318                                SMBUS_NO_STARTSTOP);
02319           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02320           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02321           if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02322           {
02323             hsmbus->XferSize--;
02324             hsmbus->XferCount--;
02325           }
02326         }
02327       }
02328     }
02329     else
02330     {
02331       /* Nothing to do */
02332     }
02333   }
02334   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
02335   {
02336     /* Write data to TXDR only if XferCount not reach "0" */
02337     /* A TXIS flag can be set, during STOP treatment      */
02338     /* Check if all Data have already been sent */
02339     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
02340     if (hsmbus->XferCount > 0U)
02341     {
02342       /* Write data to TXDR */
02343       hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
02344
02345       /* Increment Buffer pointer */
02346       hsmbus->pBuffPtr++;
02347
02348       hsmbus->XferCount--;
02349       hsmbus->XferSize--;
02350     }
02351
02352     if (hsmbus->XferCount == 0U)
02353     {
02354       /* Last Byte is Transmitted */
02355       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
02356       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02357       hsmbus->PreviousState = hsmbus->State;
02358       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02359
02360       /* Process Unlocked */
02361       __HAL_UNLOCK(hsmbus);
02362
02363       /* Call the corresponding callback to inform upper layer of End of Transfer */
02364 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02365       hsmbus->SlaveTxCpltCallback(hsmbus);
02366 #else
02367       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
02368 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02369     }
02370   }
02371   else
02372   {
02373     /* Nothing to do */
02374   }
02375
02376   /* Check if STOPF is set */
02377   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
02378   {
02379     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
02380     {
02381       /* Store Last receive data if any */
02382       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
02383       {
02384         /* Read data from RXDR */
02385         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02386
02387         /* Increment Buffer pointer */
02388         hsmbus->pBuffPtr++;
02389
02390         if ((hsmbus->XferSize > 0U))
02391         {
02392           hsmbus->XferSize--;
02393           hsmbus->XferCount--;
02394         }
02395       }
02396
02397       /* Disable RX and TX Interrupts */
02398       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02399
02400       /* Disable ADDR Interrupt */
02401       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
02402
02403       /* Disable Address Acknowledge */
02404       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
02405
02406       /* Clear Configuration Register 2 */
02407       SMBUS_RESET_CR2(hsmbus);
02408
02409       /* Clear STOP Flag */
02410       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
02411
02412       /* Clear ADDR flag */
02413       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
02414
02415       hsmbus->XferOptions = 0;
02416       hsmbus->PreviousState = hsmbus->State;
02417       hsmbus->State = HAL_SMBUS_STATE_READY;
02418
02419       /* Process Unlocked */
02420       __HAL_UNLOCK(hsmbus);
02421
02422       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
02423 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02424       hsmbus->ListenCpltCallback(hsmbus);
02425 #else
02426       HAL_SMBUS_ListenCpltCallback(hsmbus);
02427 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02428     }
02429   }
02430
02431   /* Process Unlocked */
02432   __HAL_UNLOCK(hsmbus);
02433
02434   return HAL_OK;
02435 }
02436 /**
02437   * @brief  Manage the enabling of Interrupts.
02438   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02439   *                the configuration information for the specified SMBUS.
02440   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02441   * @retval HAL status
02442   */
02443 static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02444 {
02445   uint32_t tmpisr = 0UL;
02446
02447   if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
02448   {
02449     /* Enable ERR interrupt */
02450     tmpisr |= SMBUS_IT_ERRI;
02451   }
02452
02453   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02454   {
02455     /* Enable ADDR, STOP interrupt */
02456     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
02457   }
02458
02459   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02460   {
02461     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02462     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
02463   }
02464
02465   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02466   {
02467     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02468     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
02469   }
02470
02471   /* Enable interrupts only at the end */
02472   /* to avoid the risk of SMBUS interrupt handle execution before */
02473   /* all interrupts requested done */
02474   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
02475 }
02476 /**
02477   * @brief  Manage the disabling of Interrupts.
02478   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02479   *                the configuration information for the specified SMBUS.
02480   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02481   * @retval HAL status
02482   */
02483 static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02484 {
02485   uint32_t tmpisr = 0UL;
02486   uint32_t tmpstate = hsmbus->State;
02487
02488   if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
02489   {
02490     /* Disable ERR interrupt */
02491     tmpisr |= SMBUS_IT_ERRI;
02492   }
02493
02494   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02495   {
02496     /* Disable TC, STOP, NACK and TXI interrupt */
02497     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
02498
02499     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02500         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02501     {
02502       /* Disable ERR interrupt */
02503       tmpisr |= SMBUS_IT_ERRI;
02504     }
02505
02506     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02507     {
02508       /* Disable STOP and NACK interrupt */
02509       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02510     }
02511   }
02512
02513   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02514   {
02515     /* Disable TC, STOP, NACK and RXI interrupt */
02516     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
02517
02518     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02519         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02520     {
02521       /* Disable ERR interrupt */
02522       tmpisr |= SMBUS_IT_ERRI;
02523     }
02524
02525     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02526     {
02527       /* Disable STOP and NACK interrupt */
02528       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02529     }
02530   }
02531
02532   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02533   {
02534     /* Disable ADDR, STOP and NACK interrupt */
02535     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02536
02537     if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02538     {
02539       /* Disable ERR interrupt */
02540       tmpisr |= SMBUS_IT_ERRI;
02541     }
02542   }
02543
02544   /* Disable interrupts only at the end */
02545   /* to avoid a breaking situation like at "t" time */
02546   /* all disable interrupts request are not done */
02547   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
02548 }
02549
02550 /**
02551   * @brief  SMBUS interrupts error handler.
02552   * @param  hsmbus SMBUS handle.
02553   * @retval None
02554   */
02555 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
02556 {
02557   uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
02558   uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
02559   uint32_t tmpstate;
02560   uint32_t tmperror;
02561
02562   /* SMBUS Bus error interrupt occurred ------------------------------------*/
02563   if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
02564       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02565   {
02566     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
02567
02568     /* Clear BERR flag */
02569     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
02570   }
02571
02572   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02573   if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
02574       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02575   {
02576     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
02577
02578     /* Clear OVR flag */
02579     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
02580   }
02581
02582   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
02583   if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
02584       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02585   {
02586     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
02587
02588     /* Clear ARLO flag */
02589     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
02590   }
02591
02592   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
02593   if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
02594       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02595   {
02596     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
02597
02598     /* Clear TIMEOUT flag */
02599     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
02600   }
02601
02602   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
02603   if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
02604       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02605   {
02606     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
02607
02608     /* Clear ALERT flag */
02609     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
02610   }
02611
02612   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
02613   if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
02614       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02615   {
02616     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
02617
02618     /* Clear PEC error flag */
02619     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
02620   }
02621
02622   if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
02623   {
02624     /* Flush TX register */
02625     SMBUS_Flush_TXDR(hsmbus);
02626   }
02627
02628   /* Store current volatile hsmbus->ErrorCode, misra rule */
02629   tmperror = hsmbus->ErrorCode;
02630
02631   /* Call the Error Callback in case of Error detected */
02632   if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
02633   {
02634     /* Do not Reset the HAL state in case of ALERT error */
02635     if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
02636     {
02637       /* Store current volatile hsmbus->State, misra rule */
02638       tmpstate = hsmbus->State;
02639
02640       if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02641           || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
02642       {
02643         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
02644         /* keep HAL_SMBUS_STATE_LISTEN if set */
02645         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
02646         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
02647       }
02648     }
02649
02650     /* Call the Error callback to inform upper layer */
02651 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02652     hsmbus->ErrorCallback(hsmbus);
02653 #else
02654     HAL_SMBUS_ErrorCallback(hsmbus);
02655 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02656   }
02657 }
02658
02659 /**
02660   * @brief  Handle SMBUS Communication Timeout.
02661   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02662   *                the configuration information for the specified SMBUS.
02663   * @param  Flag Specifies the SMBUS flag to check.
02664   * @param  Status The new Flag status (SET or RESET).
02665   * @param  Timeout Timeout duration
02666   * @retval HAL status
02667   */
02668 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
02669                                                       FlagStatus Status, uint32_t Timeout)
02670 {
02671   uint32_t tickstart = HAL_GetTick();
02672
02673   /* Wait until flag is set */
02674   while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
02675   {
02676     /* Check for the Timeout */
02677     if (Timeout != HAL_MAX_DELAY)
02678     {
02679       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
02680       {
02681         hsmbus->PreviousState = hsmbus->State;
02682         hsmbus->State = HAL_SMBUS_STATE_READY;
02683
02684         /* Update SMBUS error code */
02685         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
02686
02687         /* Process Unlocked */
02688         __HAL_UNLOCK(hsmbus);
02689
02690         return HAL_ERROR;
02691       }
02692     }
02693   }
02694
02695   return HAL_OK;
02696 }
02697
02698 /**
02699   * @brief  SMBUS Tx data register flush process.
02700   * @param  hsmbus SMBUS handle.
02701   * @retval None
02702   */
02703 static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
02704 {
02705   /* If a pending TXIS flag is set */
02706   /* Write a dummy data in TXDR to clear it */
02707   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
02708   {
02709     hsmbus->Instance->TXDR = 0x00U;
02710   }
02711
02712   /* Flush TX register if not empty */
02713   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
02714   {
02715     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
02716   }
02717 }
02718
02719 /**
02720   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
02721   * @param  hsmbus SMBUS handle.
02722   * @param  DevAddress specifies the slave address to be programmed.
02723   * @param  Size specifies the number of bytes to be programmed.
02724   *   This parameter must be a value between 0 and 255.
02725   * @param  Mode New state of the SMBUS START condition generation.
02726   *   This parameter can be one or a combination  of the following values:
02727   *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
02728   *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
02729   *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
02730   *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
02731   * @param  Request New state of the SMBUS START condition generation.
02732   *   This parameter can be one of the following values:
02733   *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
02734   *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
02735   *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
02736   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
02737   * @retval None
02738   */
02739 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
02740                                  uint32_t Mode, uint32_t Request)
02741 {
02742   /* Check the parameters */
02743   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
02744   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
02745   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
02746
02747   /* update CR2 register */
02748   MODIFY_REG(hsmbus->Instance->CR2,
02749              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
02750                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
02751                I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
02752              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
02753                         (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
02754                         (uint32_t)Mode | (uint32_t)Request));
02755 }
02756
02757 /**
02758   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
02759   * @param  hsmbus SMBUS handle.
02760   * @retval None
02761   */
02762 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
02763 {
02764   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02765   /* it request implicitly to generate a restart condition */
02766   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02767   if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02768   {
02769     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02770   }
02771   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02772   /* it request implicitly to generate a restart condition      */
02773   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02774   else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02775   {
02776     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02777   }
02778   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02779   /* it request implicitly to generate a restart condition             */
02780   /* then generate a stop condition at the end of transfer             */
02781   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02782   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02783   {
02784     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02785   }
02786   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02787   /* it request implicitly to generate a restart condition               */
02788   /* then generate a stop condition at the end of transfer               */
02789   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02790   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02791   {
02792     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02793   }
02794   else
02795   {
02796     /* Nothing to do */
02797   }
02798 }
02799 /**
02800   * @}
02801   */
02802
02803 #endif /* HAL_SMBUS_MODULE_ENABLED */
02804 /**
02805   * @}
02806   */
02807
02808 /**
02809   * @}
02810   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_smbus.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SMBUS_H
00021 #define STM32G4xx_HAL_SMBUS_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMBUS
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00044   * @brief  SMBUS Configuration Structure definition
00045   * @{
00046   */
00047 typedef struct
00048 {
00049   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00050                                         This parameter calculated by referring to SMBUS initialization section
00051                                         in Reference manual */
00052   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00053                                         This parameter can be a value of @ref SMBUS_Analog_Filter */
00054
00055   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00056                                         This parameter can be a 7-bit or 10-bit address. */
00057
00058   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00059                                         This parameter can be a value of @ref SMBUS_addressing_mode */
00060
00061   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00062                                         This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00063
00064   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00065                                         This parameter can be a 7-bit address. */
00066
00067   uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
00068                                         if dual addressing mode is selected
00069                                         This parameter can be a value of @ref SMBUS_own_address2_masks. */
00070
00071   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00072                                         This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00073
00074   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00075                                         This parameter can be a value of @ref SMBUS_nostretch_mode */
00076
00077   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00078                                         This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00079
00080   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00081                                         This parameter can be a value of @ref SMBUS_peripheral_mode */
00082
00083   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00084                                         (Enable bits and different timeout values)
00085                                         This parameter calculated by referring to SMBUS initialization section
00086                                         in Reference manual */
00087 } SMBUS_InitTypeDef;
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HAL_state_definition HAL state definition
00093   * @brief  HAL State definition
00094   * @{
00095   */
00096 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00097 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00098 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00099 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00103 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00109   * @brief  SMBUS Error Code definition
00110   * @{
00111   */
00112 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00113 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00114 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00115 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00116 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00117 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00118 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00119 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00120 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00121 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00122 #define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
00123 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00124 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00130   * @brief  SMBUS handle Structure definition
00131   * @{
00132   */
00133 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00134 typedef struct __SMBUS_HandleTypeDef
00135 #else
00136 typedef struct
00137 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00138 {
00139   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00140
00141   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00142
00143   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00144
00145   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00146
00147   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00148
00149   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00150
00151   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00152
00153   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00154
00155   __IO uint32_t                State;           /*!< SMBUS communication state          */
00156
00157   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00158
00159 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00160   void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00161   /*!< SMBUS Master Tx Transfer completed callback */
00162   void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00163   /*!< SMBUS Master Rx Transfer completed callback */
00164   void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00165   /*!< SMBUS Slave Tx Transfer completed callback  */
00166   void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00167   /*!< SMBUS Slave Rx Transfer completed callback  */
00168   void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00169   /*!< SMBUS Listen Complete callback              */
00170   void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00171   /*!< SMBUS Error callback                        */
00172
00173   void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00174   /*!< SMBUS Slave Address Match callback */
00175
00176   void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00177   /*!< SMBUS Msp Init callback                     */
00178   void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00179   /*!< SMBUS Msp DeInit callback                   */
00180
00181 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00182 } SMBUS_HandleTypeDef;
00183
00184 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00185 /**
00186   * @brief  HAL SMBUS Callback ID enumeration definition
00187   */
00188 typedef enum
00189 {
00190   HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
00191   HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
00192   HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
00193   HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
00194   HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
00195   HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
00196
00197   HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
00198   HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
00199
00200 } HAL_SMBUS_CallbackIDTypeDef;
00201
00202 /**
00203   * @brief  HAL SMBUS Callback pointer definition
00204   */
00205 typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
00206 /*!< pointer to an SMBUS callback function */
00207 typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
00208                                             uint16_t AddrMatchCode);
00209 /*!< pointer to an SMBUS Address Match callback function */
00210
00211 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219 /* Exported constants --------------------------------------------------------*/
00220
00221 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00222   * @{
00223   */
00224
00225 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00226   * @{
00227   */
00228 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00229 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00235   * @{
00236   */
00237 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00238 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00244   * @{
00245   */
00246
00247 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00248 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
00254   * @{
00255   */
00256
00257 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00258 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00259 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00260 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00261 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00262 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00263 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00264 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00265 /**
00266   * @}
00267   */
00268
00269
00270 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00271   * @{
00272   */
00273 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00274 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00280   * @{
00281   */
00282 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00283 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00289   * @{
00290   */
00291 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00292 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00298   * @{
00299   */
00300 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00301 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00302 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00308   * @{
00309   */
00310
00311 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00312 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00313 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00314 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00320   * @{
00321   */
00322
00323 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00324 #define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
00325 #define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00326 #define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00332   * @{
00333   */
00334
00335 /* List of XferOptions in usage of :
00336  * 1- Restart condition when direction change
00337  * 2- No Restart condition in other use cases
00338  */
00339 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00340 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00341 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00342 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00343 #define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
00344 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00345 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00346
00347 /* List of XferOptions in usage of :
00348  * 1- Restart condition in all use cases (direction change or not)
00349  */
00350 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00351 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00352 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00353 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00359   * @brief SMBUS Interrupt definition
00360   *        Elements values convention: 0xXXXXXXXX
00361   *           - XXXXXXXX  : Interrupt control mask
00362   * @{
00363   */
00364 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00365 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00366 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00367 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00368 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00369 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00370 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00371 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
00372                                                  SMBUS_IT_NACKI | SMBUS_IT_TXI)
00373 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
00374                                                  SMBUS_IT_RXI)
00375 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00376 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00382   * @brief Flag definition
00383   *        Elements values convention: 0xXXXXYYYY
00384   *           - XXXXXXXX  : Flag mask
00385   * @{
00386   */
00387
00388 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00389 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00390 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00391 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00392 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00393 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00394 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00395 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00396 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00397 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00398 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00399 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00400 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00401 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00402 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00403 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /* Exported macros ------------------------------------------------------------*/
00413 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00414   * @{
00415   */
00416
00417 /** @brief  Reset SMBUS handle state.
00418   * @param  __HANDLE__ specifies the SMBUS Handle.
00419   * @retval None
00420   */
00421 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00422 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
00423                                                                  (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
00424                                                                  (__HANDLE__)->MspInitCallback = NULL;            \
00425                                                                  (__HANDLE__)->MspDeInitCallback = NULL;          \
00426                                                                } while(0)
00427 #else
00428 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00429 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00430
00431 /** @brief  Enable the specified SMBUS interrupts.
00432   * @param  __HANDLE__ specifies the SMBUS Handle.
00433   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00434   *        This parameter can be one of the following values:
00435   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00436   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00437   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00438   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00439   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00440   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00441   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00442   *
00443   * @retval None
00444   */
00445 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00446
00447 /** @brief  Disable the specified SMBUS interrupts.
00448   * @param  __HANDLE__ specifies the SMBUS Handle.
00449   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00450   *        This parameter can be one of the following values:
00451   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00452   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00453   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00454   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00455   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00456   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00457   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00458   *
00459   * @retval None
00460   */
00461 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00462
00463 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00464   * @param  __HANDLE__ specifies the SMBUS Handle.
00465   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
00466   *          This parameter can be one of the following values:
00467   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00468   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00469   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00470   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00471   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00472   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00473   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00474   *
00475   * @retval The new state of __IT__ (SET or RESET).
00476   */
00477 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
00478   ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00479
00480 /** @brief  Check whether the specified SMBUS flag is set or not.
00481   * @param  __HANDLE__ specifies the SMBUS Handle.
00482   * @param  __FLAG__ specifies the flag to check.
00483   *        This parameter can be one of the following values:
00484   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00485   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
00486   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
00487   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00488   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00489   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00490   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
00491   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
00492   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00493   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00494   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00495   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00496   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00497   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00498   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
00499   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
00500   *
00501   * @retval The new state of __FLAG__ (SET or RESET).
00502   */
00503 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00504 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
00505   (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
00506     ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00507
00508 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00509   * @param  __HANDLE__ specifies the SMBUS Handle.
00510   * @param  __FLAG__ specifies the flag to clear.
00511   *          This parameter can be any combination of the following values:
00512   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00513   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00514   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00515   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00516   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00517   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00518   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00519   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00520   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00521   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00522   *
00523   * @retval None
00524   */
00525 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) == SMBUS_FLAG_TXE) ? \
00526                                                        ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
00527                                                        ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00528
00529 /** @brief  Enable the specified SMBUS peripheral.
00530   * @param  __HANDLE__ specifies the SMBUS Handle.
00531   * @retval None
00532   */
00533 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00534
00535 /** @brief  Disable the specified SMBUS peripheral.
00536   * @param  __HANDLE__ specifies the SMBUS Handle.
00537   * @retval None
00538   */
00539 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00540
00541 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00542   * @param  __HANDLE__ specifies the SMBUS Handle.
00543   * @retval None
00544   */
00545 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00546
00547 /**
00548   * @}
00549   */
00550
00551
00552 /* Private constants ---------------------------------------------------------*/
00553
00554 /* Private macros ------------------------------------------------------------*/
00555 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00556   * @{
00557   */
00558
00559 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00560                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00561
00562 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
00563
00564 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00565                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00566
00567 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00568                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00569
00570 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00571                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00572                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00573                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00574                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00575                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00576                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00577                                                          ((MASK) == SMBUS_OA2_MASK07))
00578
00579 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00580                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00581
00582 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00583                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00584
00585 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00586                                                          ((PEC) == SMBUS_PEC_ENABLE))
00587
00588 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
00589                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00590                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00591
00592 #define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
00593                                                       ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00594                                                       ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00595                                                       ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00596                                                       ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00597                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00598                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00599                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
00600                                                                   SMBUS_RELOAD_MODE )))
00601
00602
00603 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00604                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
00605                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
00606                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
00607
00608
00609 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
00610                                                       ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
00611                                                       ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00612                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00613                                                       ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00614                                                       ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
00615                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00616                                                       ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
00617
00618 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
00619                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
00620                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
00621                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00622
00623 #define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
00624                                                         (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
00625                                                                                I2C_CR1_PECEN)))
00626 #define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
00627                                                         (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
00628                                                                                I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
00629                                                                                I2C_CR2_RD_WRN)))
00630
00631 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
00632                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00633                                                                        (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
00634                                                                       (~I2C_CR2_RD_WRN)) : \
00635                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & \
00636                                                                         (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
00637                                                                        (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00638
00639 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
00640 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00641 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00642 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00643 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00644
00645 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
00646                                                           ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00647 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00648
00649 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00650 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00651
00652 /**
00653   * @}
00654   */
00655
00656 /* Include SMBUS HAL Extended module */
00657 #include "stm32g4xx_hal_smbus_ex.h"
00658
00659 /* Exported functions --------------------------------------------------------*/
00660 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00661   * @{
00662   */
00663
00664 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00665   * @{
00666   */
00667
00668 /* Initialization and de-initialization functions  ****************************/
00669 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00670 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
00671 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00672 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00673 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
00674 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
00675
00676 /* Callbacks Register/UnRegister functions  ***********************************/
00677 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00678 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00679                                              HAL_SMBUS_CallbackIDTypeDef CallbackID,
00680                                              pSMBUS_CallbackTypeDef pCallback);
00681 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00682                                                HAL_SMBUS_CallbackIDTypeDef CallbackID);
00683
00684 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
00685                                                  pSMBUS_AddrCallbackTypeDef pCallback);
00686 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
00687 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00688 /**
00689   * @}
00690   */
00691
00692 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00693   * @{
00694   */
00695
00696 /* IO operation functions  *****************************************************/
00697 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00698   * @{
00699   */
00700 /******* Blocking mode: Polling */
00701 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
00702                                           uint32_t Timeout);
00703 /**
00704   * @}
00705   */
00706
00707 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00708   * @{
00709   */
00710 /******* Non-Blocking mode: Interrupt */
00711 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00712                                                uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00713 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00714                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00715 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00716 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
00717                                               uint32_t XferOptions);
00718 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
00719                                              uint32_t XferOptions);
00720
00721 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00722 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00723 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00724 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00725 /**
00726   * @}
00727   */
00728
00729 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00730   * @{
00731   */
00732 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00733 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00734 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00735 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00736 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00737 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00738 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00739 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00740 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00741 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00742
00743 /**
00744   * @}
00745   */
00746
00747 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00748   *  @{
00749   */
00750
00751 /* Peripheral State and Errors functions  **************************************************/
00752 uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
00753 uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
00754
00755 /**
00756   * @}
00757   */
00758
00759 /**
00760   * @}
00761   */
00762
00763 /* Private Functions ---------------------------------------------------------*/
00764 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00765   * @{
00766   */
00767 /* Private functions are defined in stm32g4xx_hal_smbus.c file */
00768 /**
00769   * @}
00770   */
00771
00772 /**
00773   * @}
00774   */
00775
00776 /**
00777   * @}
00778   */
00779
00780 /**
00781   * @}
00782   */
00783
00784 #ifdef __cplusplus
00785 }
00786 #endif
00787
00788
00789 #endif /* STM32G4xx_HAL_SMBUS_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_smbus_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smbus_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of SMBUS Extended peripheral:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                ##### SMBUS peripheral Extended features  #####
00024   ==============================================================================
00025
00026   [..] Comparing to other previous devices, the SMBUS interface for STM32G4xx
00027        devices contains the following additional features
00028
00029        (+) Disable or enable wakeup from Stop mode(s)
00030        (+) Disable or enable Fast Mode Plus
00031
00032                      ##### How to use this driver #####
00033   ==============================================================================
00034     (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
00035           (++) HAL_SMBUSEx_EnableWakeUp()
00036           (++) HAL_SMBUSEx_DisableWakeUp()
00037     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00038           (++) HAL_SMBUSEx_EnableFastModePlus()
00039           (++) HAL_SMBUSEx_DisableFastModePlus()
00040   @endverbatim
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g4xx_hal.h"
00045
00046 /** @addtogroup STM32G4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SMBUSEx SMBUSEx
00051   * @brief SMBUS Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_SMBUS_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /* Private macro -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private function prototypes -----------------------------------------------*/
00062 /* Private functions ---------------------------------------------------------*/
00063
00064 /** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
00065   * @{
00066   */
00067
00068 /** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
00069   * @brief    WakeUp Mode Functions
00070   *
00071 @verbatim
00072  ===============================================================================
00073                       ##### WakeUp Mode Functions #####
00074  ===============================================================================
00075     [..] This section provides functions allowing to:
00076       (+) Configure Wake Up Feature
00077
00078 @endverbatim
00079   * @{
00080   */
00081
00082 /**
00083   * @brief  Enable SMBUS wakeup from Stop mode(s).
00084   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00085   *                the configuration information for the specified SMBUSx peripheral.
00086   * @retval HAL status
00087   */
00088 HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
00089 {
00090   /* Check the parameters */
00091   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
00092
00093   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00094   {
00095     /* Process Locked */
00096     __HAL_LOCK(hsmbus);
00097
00098     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00099
00100     /* Disable the selected SMBUS peripheral */
00101     __HAL_SMBUS_DISABLE(hsmbus);
00102
00103     /* Enable wakeup from stop mode */
00104     hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
00105
00106     __HAL_SMBUS_ENABLE(hsmbus);
00107
00108     hsmbus->State = HAL_SMBUS_STATE_READY;
00109
00110     /* Process Unlocked */
00111     __HAL_UNLOCK(hsmbus);
00112
00113     return HAL_OK;
00114   }
00115   else
00116   {
00117     return HAL_BUSY;
00118   }
00119 }
00120
00121 /**
00122   * @brief  Disable SMBUS wakeup from Stop mode(s).
00123   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00124   *                the configuration information for the specified SMBUSx peripheral.
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
00128 {
00129   /* Check the parameters */
00130   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
00131
00132   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00133   {
00134     /* Process Locked */
00135     __HAL_LOCK(hsmbus);
00136
00137     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00138
00139     /* Disable the selected SMBUS peripheral */
00140     __HAL_SMBUS_DISABLE(hsmbus);
00141
00142     /* Disable wakeup from stop mode */
00143     hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00144
00145     __HAL_SMBUS_ENABLE(hsmbus);
00146
00147     hsmbus->State = HAL_SMBUS_STATE_READY;
00148
00149     /* Process Unlocked */
00150     __HAL_UNLOCK(hsmbus);
00151
00152     return HAL_OK;
00153   }
00154   else
00155   {
00156     return HAL_BUSY;
00157   }
00158 }
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
00164   * @brief    Fast Mode Plus Functions
00165   *
00166 @verbatim
00167  ===============================================================================
00168                       ##### Fast Mode Plus Functions #####
00169  ===============================================================================
00170     [..] This section provides functions allowing to:
00171       (+) Configure Fast Mode Plus
00172
00173 @endverbatim
00174   * @{
00175   */
00176
00177 /**
00178   * @brief Enable the SMBUS fast mode plus driving capability.
00179   * @param ConfigFastModePlus Selects the pin.
00180   *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
00181   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00182   *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
00183   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00184   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00185   *        can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
00186   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00187   *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
00188   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00189   *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
00190   * @note  For all I2C4 pins fast mode plus driving capability can be enabled
00191   *        only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
00192   * @retval None
00193   */
00194 void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00195 {
00196   /* Check the parameter */
00197   assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
00198
00199   /* Enable SYSCFG clock */
00200   __HAL_RCC_SYSCFG_CLK_ENABLE();
00201
00202   /* Enable fast mode plus driving capability for selected pin */
00203   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00204 }
00205
00206 /**
00207   * @brief Disable the SMBUS fast mode plus driving capability.
00208   * @param ConfigFastModePlus Selects the pin.
00209   *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
00210   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00211   *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
00212   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00213   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00214   *        can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
00215   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00216   *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
00217   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00218   *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
00219   * @note  For all I2C4 pins fast mode plus driving capability can be disabled
00220   *        only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
00221   * @retval None
00222   */
00223 void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00224 {
00225   /* Check the parameter */
00226   assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
00227
00228   /* Enable SYSCFG clock */
00229   __HAL_RCC_SYSCFG_CLK_ENABLE();
00230
00231   /* Disable fast mode plus driving capability for selected pin */
00232   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00233 }
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 /**
00244   * @}
00245   */
00246
00247 #endif /* HAL_SMBUS_MODULE_ENABLED */
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_smbus_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_smbus_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_smbus_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SMBUS_EX_H
00021 #define STM32G4xx_HAL_SMBUS_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMBUSEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
00045   * @{
00046   */
00047 #define SMBUS_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00048 #define SMBUS_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00049 #define SMBUS_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00050 #define SMBUS_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00051 #define SMBUS_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00052 #define SMBUS_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00053 #define SMBUS_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00054 #define SMBUS_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00055 #if defined(SYSCFG_CFGR1_I2C4_FMP)
00056 #define SMBUS_FASTMODEPLUS_I2C4           SYSCFG_CFGR1_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
00057 #else
00058 #define SMBUS_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
00059 #endif /* SYSCFG_CFGR1_I2C4_FMP */
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Exported macro ------------------------------------------------------------*/
00069 /** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
00070   * @{
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported functions --------------------------------------------------------*/
00078 /** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
00079   * @{
00080   */
00081
00082 /** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
00083   * @{
00084   */
00085 /* Peripheral Control functions  ************************************************/
00086 HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
00087 HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
00088 /**
00089   * @}
00090   */
00091
00092 /** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
00093   * @{
00094   */
00095 void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00096 void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Private constants ---------------------------------------------------------*/
00106 /** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
00107   * @{
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Private macros ------------------------------------------------------------*/
00115 /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
00116   * @{
00117   */
00118 #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
00119                                            ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)  || \
00120                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)  || \
00121                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)  || \
00122                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)  || \
00123                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
00124                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
00125                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
00126                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)))
00127 /**
00128   * @}
00129   */
00130
00131 /* Private Functions ---------------------------------------------------------*/
00132 /** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
00133   * @{
00134   */
00135 /* Private functions are defined in stm32g4xx_hal_smbus_ex.c file */
00136 /**
00137   * @}
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 #ifdef __cplusplus
00149 }
00150 #endif
00151
00152 #endif /* STM32G4xx_HAL_SMBUS_EX_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_spi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027     [..]
00028       The SPI HAL driver can be used as follows:
00029
00030       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00031           SPI_HandleTypeDef  hspi;
00032
00033       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00034           (##) Enable the SPIx interface clock
00035           (##) SPI pins configuration
00036               (+++) Enable the clock for the SPI GPIOs
00037               (+++) Configure these SPI pins as alternate function push-pull
00038           (##) NVIC configuration if you need to use interrupt process
00039               (+++) Configure the SPIx interrupt priority
00040               (+++) Enable the NVIC SPI IRQ handle
00041           (##) DMA Configuration if you need to use DMA process
00042               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00043               (+++) Enable the DMAx clock
00044               (+++) Configure the DMA handle parameters
00045               (+++) Configure the DMA Tx or Rx Stream/Channel
00046               (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
00047               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00048
00049       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00050           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00051
00052       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00053           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00054               by calling the customized HAL_SPI_MspInit() API.
00055      [..]
00056        Circular mode restriction:
00057       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00058           (##) Master 2Lines RxOnly
00059           (##) Master 1Line Rx
00060       (#) The CRC feature is not managed when the DMA circular mode is enabled
00061       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00062           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00063      [..]
00064        Master Receive mode restriction:
00065       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
00066           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00067           does not initiate a new transfer the following procedure has to be respected:
00068           (##) HAL_SPI_DeInit()
00069           (##) HAL_SPI_Init()
00070      [..]
00071        Callback registration:
00072
00073       (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
00074           allows the user to configure dynamically the driver callbacks.
00075           Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
00076
00077           Function HAL_SPI_RegisterCallback() allows to register following callbacks:
00078             (++) TxCpltCallback        : SPI Tx Completed callback
00079             (++) RxCpltCallback        : SPI Rx Completed callback
00080             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00081             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00082             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00083             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00084             (++) ErrorCallback         : SPI Error callback
00085             (++) AbortCpltCallback     : SPI Abort callback
00086             (++) MspInitCallback       : SPI Msp Init callback
00087             (++) MspDeInitCallback     : SPI Msp DeInit callback
00088           This function takes as parameters the HAL peripheral handle, the Callback ID
00089           and a pointer to the user callback function.
00090
00091
00092       (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
00093           weak function.
00094           HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00095           and the Callback ID.
00096           This function allows to reset following callbacks:
00097             (++) TxCpltCallback        : SPI Tx Completed callback
00098             (++) RxCpltCallback        : SPI Rx Completed callback
00099             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00100             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00101             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00102             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00103             (++) ErrorCallback         : SPI Error callback
00104             (++) AbortCpltCallback     : SPI Abort callback
00105             (++) MspInitCallback       : SPI Msp Init callback
00106             (++) MspDeInitCallback     : SPI Msp DeInit callback
00107
00108        [..]
00109        By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
00110        all callbacks are set to the corresponding weak functions:
00111        examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
00112        Exception done for MspInit and MspDeInit functions that are
00113        reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
00114        these callbacks are null (not registered beforehand).
00115        If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
00116        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00117
00118        [..]
00119        Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
00120        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00121        in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
00122        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00123        Then, the user first registers the MspInit/MspDeInit user callbacks
00124        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
00125        or HAL_SPI_Init() function.
00126
00127        [..]
00128        When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
00129        not defined, the callback registering feature is not available
00130        and weak (surcharged) callbacks are used.
00131
00132      [..]
00133        Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
00134        the following table resume the max SPI frequency reached with data size 8bits/16bits,
00135          according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
00136
00137   @endverbatim
00138
00139   Additional table :
00140
00141        DataSize = SPI_DATASIZE_8BIT:
00142        +----------------------------------------------------------------------------------------------+
00143        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00144        | Process | Transfer mode  |---------------------|----------------------|----------------------|
00145        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00146        |==============================================================================================|
00147        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00148        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00149        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00150        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00151        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00152        |=========|================|==========|==========|===========|==========|===========|==========|
00153        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00154        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00155        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00156        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00157        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00158        |=========|================|==========|==========|===========|==========|===========|==========|
00159        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00160        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00161        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00162        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00163        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00164        +----------------------------------------------------------------------------------------------+
00165
00166        DataSize = SPI_DATASIZE_16BIT:
00167        +----------------------------------------------------------------------------------------------+
00168        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00169        | Process | Transfer mode  |---------------------|----------------------|----------------------|
00170        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00171        |==============================================================================================|
00172        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00173        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00174        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00175        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00176        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00177        |=========|================|==========|==========|===========|==========|===========|==========|
00178        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00179        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00180        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00181        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00182        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00183        |=========|================|==========|==========|===========|==========|===========|==========|
00184        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00185        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00186        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00187        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00188        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00189        +----------------------------------------------------------------------------------------------+
00190        @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
00191              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00192        @note
00193             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00194             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00195             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00196
00197   */
00198
00199 /* Includes ------------------------------------------------------------------*/
00200 #include "stm32g4xx_hal.h"
00201
00202 /** @addtogroup STM32G4xx_HAL_Driver
00203   * @{
00204   */
00205
00206 /** @defgroup SPI SPI
00207   * @brief SPI HAL module driver
00208   * @{
00209   */
00210 #ifdef HAL_SPI_MODULE_ENABLED
00211
00212 /* Private typedef -----------------------------------------------------------*/
00213 /* Private defines -----------------------------------------------------------*/
00214 /** @defgroup SPI_Private_Constants SPI Private Constants
00215   * @{
00216   */
00217 #define SPI_DEFAULT_TIMEOUT 100U
00218 /**
00219   * @}
00220   */
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /* Private variables ---------------------------------------------------------*/
00224 /* Private function prototypes -----------------------------------------------*/
00225 /** @defgroup SPI_Private_Functions SPI Private Functions
00226   * @{
00227   */
00228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
00239                                                        uint32_t Timeout, uint32_t Tickstart);
00240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
00241                                                        uint32_t Timeout, uint32_t Tickstart);
00242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00250 #if (USE_SPI_CRC != 0U)
00251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00255 #endif /* USE_SPI_CRC */
00256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00263 /**
00264   * @}
00265   */
00266
00267 /* Exported functions --------------------------------------------------------*/
00268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00269   * @{
00270   */
00271
00272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00273   *  @brief    Initialization and Configuration functions
00274   *
00275 @verbatim
00276  ===============================================================================
00277               ##### Initialization and de-initialization functions #####
00278  ===============================================================================
00279     [..]  This subsection provides a set of functions allowing to initialize and
00280           de-initialize the SPIx peripheral:
00281
00282       (+) User must implement HAL_SPI_MspInit() function in which he configures
00283           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00284
00285       (+) Call the function HAL_SPI_Init() to configure the selected device with
00286           the selected configuration:
00287         (++) Mode
00288         (++) Direction
00289         (++) Data Size
00290         (++) Clock Polarity and Phase
00291         (++) NSS Management
00292         (++) BaudRate Prescaler
00293         (++) FirstBit
00294         (++) TIMode
00295         (++) CRC Calculation
00296         (++) CRC Polynomial if CRC enabled
00297         (++) CRC Length, used only with Data8 and Data16
00298         (++) FIFO reception threshold
00299
00300       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00301           of the selected SPIx peripheral.
00302
00303 @endverbatim
00304   * @{
00305   */
00306
00307 /**
00308   * @brief  Initialize the SPI according to the specified parameters
00309   *         in the SPI_InitTypeDef and initialize the associated handle.
00310   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00311   *               the configuration information for SPI module.
00312   * @retval HAL status
00313   */
00314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00315 {
00316   uint32_t frxth;
00317
00318   /* Check the SPI handle allocation */
00319   if (hspi == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the parameters */
00325   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00326   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00327   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00328   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00329   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00330   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00331   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00332   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00333   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00334   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00335   {
00336     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00337     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00338
00339     if (hspi->Init.Mode == SPI_MODE_MASTER)
00340     {
00341       assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00342     }
00343     else
00344     {
00345       /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
00346       hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
00347     }
00348   }
00349   else
00350   {
00351     assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00352
00353     /* Force polarity and phase to TI protocaol requirements */
00354     hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
00355     hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
00356   }
00357 #if (USE_SPI_CRC != 0U)
00358   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00359   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00360   {
00361     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00362     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00363   }
00364 #else
00365   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00366 #endif /* USE_SPI_CRC */
00367
00368   if (hspi->State == HAL_SPI_STATE_RESET)
00369   {
00370     /* Allocate lock resource and initialize it */
00371     hspi->Lock = HAL_UNLOCKED;
00372
00373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00374     /* Init the SPI Callback settings */
00375     hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
00376     hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
00377     hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
00378     hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
00379     hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
00380     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00381     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
00382     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00383
00384     if (hspi->MspInitCallback == NULL)
00385     {
00386       hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
00387     }
00388
00389     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00390     hspi->MspInitCallback(hspi);
00391 #else
00392     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00393     HAL_SPI_MspInit(hspi);
00394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00395   }
00396
00397   hspi->State = HAL_SPI_STATE_BUSY;
00398
00399   /* Disable the selected SPI peripheral */
00400   __HAL_SPI_DISABLE(hspi);
00401
00402   /* Align by default the rs fifo threshold on the data size */
00403   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00404   {
00405     frxth = SPI_RXFIFO_THRESHOLD_HF;
00406   }
00407   else
00408   {
00409     frxth = SPI_RXFIFO_THRESHOLD_QF;
00410   }
00411
00412   /* CRC calculation is valid only for 16Bit and 8 Bit */
00413   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
00414   {
00415     /* CRC must be disabled */
00416     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00417   }
00418
00419   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00420   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00421   Communication speed, First bit and CRC calculation state */
00422   WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
00423                                   (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
00424                                   (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
00425                                   (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
00426                                   (hspi->Init.NSS & SPI_CR1_SSM) |
00427                                   (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
00428                                   (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
00429                                   (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
00430 #if (USE_SPI_CRC != 0U)
00431   /*---------------------------- SPIx CRCL Configuration -------------------*/
00432   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00433   {
00434     /* Align the CRC Length on the data size */
00435     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00436     {
00437       /* CRC Length aligned on the data size : value set by default */
00438       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00439       {
00440         hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00441       }
00442       else
00443       {
00444         hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00445       }
00446     }
00447
00448     /* Configure : CRC Length */
00449     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00450     {
00451       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
00452     }
00453   }
00454 #endif /* USE_SPI_CRC */
00455
00456   /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
00457   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
00458                                   (hspi->Init.TIMode & SPI_CR2_FRF) |
00459                                   (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
00460                                   (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
00461                                   (frxth & SPI_CR2_FRXTH)));
00462
00463 #if (USE_SPI_CRC != 0U)
00464   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00465   /* Configure : CRC Polynomial */
00466   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00467   {
00468     WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
00469   }
00470 #endif /* USE_SPI_CRC */
00471
00472 #if defined(SPI_I2SCFGR_I2SMOD)
00473   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00474   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00475 #endif /* SPI_I2SCFGR_I2SMOD */
00476
00477   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00478   hspi->State     = HAL_SPI_STATE_READY;
00479
00480   return HAL_OK;
00481 }
00482
00483 /**
00484   * @brief  De-Initialize the SPI peripheral.
00485   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00486   *               the configuration information for SPI module.
00487   * @retval HAL status
00488   */
00489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00490 {
00491   /* Check the SPI handle allocation */
00492   if (hspi == NULL)
00493   {
00494     return HAL_ERROR;
00495   }
00496
00497   /* Check SPI Instance parameter */
00498   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00499
00500   hspi->State = HAL_SPI_STATE_BUSY;
00501
00502   /* Disable the SPI Peripheral Clock */
00503   __HAL_SPI_DISABLE(hspi);
00504
00505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00506   if (hspi->MspDeInitCallback == NULL)
00507   {
00508     hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
00509   }
00510
00511   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00512   hspi->MspDeInitCallback(hspi);
00513 #else
00514   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00515   HAL_SPI_MspDeInit(hspi);
00516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00517
00518   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00519   hspi->State = HAL_SPI_STATE_RESET;
00520
00521   /* Release Lock */
00522   __HAL_UNLOCK(hspi);
00523
00524   return HAL_OK;
00525 }
00526
00527 /**
00528   * @brief  Initialize the SPI MSP.
00529   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00530   *               the configuration information for SPI module.
00531   * @retval None
00532   */
00533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00534 {
00535   /* Prevent unused argument(s) compilation warning */
00536   UNUSED(hspi);
00537
00538   /* NOTE : This function should not be modified, when the callback is needed,
00539             the HAL_SPI_MspInit should be implemented in the user file
00540    */
00541 }
00542
00543 /**
00544   * @brief  De-Initialize the SPI MSP.
00545   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00546   *               the configuration information for SPI module.
00547   * @retval None
00548   */
00549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00550 {
00551   /* Prevent unused argument(s) compilation warning */
00552   UNUSED(hspi);
00553
00554   /* NOTE : This function should not be modified, when the callback is needed,
00555             the HAL_SPI_MspDeInit should be implemented in the user file
00556    */
00557 }
00558
00559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00560 /**
00561   * @brief  Register a User SPI Callback
00562   *         To be used instead of the weak predefined callback
00563   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00564   *                the configuration information for the specified SPI.
00565   * @param  CallbackID ID of the callback to be registered
00566   * @param  pCallback pointer to the Callback function
00567   * @retval HAL status
00568   */
00569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
00570                                            pSPI_CallbackTypeDef pCallback)
00571 {
00572   HAL_StatusTypeDef status = HAL_OK;
00573
00574   if (pCallback == NULL)
00575   {
00576     /* Update the error code */
00577     hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
00578
00579     return HAL_ERROR;
00580   }
00581   /* Process locked */
00582   __HAL_LOCK(hspi);
00583
00584   if (HAL_SPI_STATE_READY == hspi->State)
00585   {
00586     switch (CallbackID)
00587     {
00588       case HAL_SPI_TX_COMPLETE_CB_ID :
00589         hspi->TxCpltCallback = pCallback;
00590         break;
00591
00592       case HAL_SPI_RX_COMPLETE_CB_ID :
00593         hspi->RxCpltCallback = pCallback;
00594         break;
00595
00596       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00597         hspi->TxRxCpltCallback = pCallback;
00598         break;
00599
00600       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00601         hspi->TxHalfCpltCallback = pCallback;
00602         break;
00603
00604       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00605         hspi->RxHalfCpltCallback = pCallback;
00606         break;
00607
00608       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00609         hspi->TxRxHalfCpltCallback = pCallback;
00610         break;
00611
00612       case HAL_SPI_ERROR_CB_ID :
00613         hspi->ErrorCallback = pCallback;
00614         break;
00615
00616       case HAL_SPI_ABORT_CB_ID :
00617         hspi->AbortCpltCallback = pCallback;
00618         break;
00619
00620       case HAL_SPI_MSPINIT_CB_ID :
00621         hspi->MspInitCallback = pCallback;
00622         break;
00623
00624       case HAL_SPI_MSPDEINIT_CB_ID :
00625         hspi->MspDeInitCallback = pCallback;
00626         break;
00627
00628       default :
00629         /* Update the error code */
00630         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00631
00632         /* Return error status */
00633         status =  HAL_ERROR;
00634         break;
00635     }
00636   }
00637   else if (HAL_SPI_STATE_RESET == hspi->State)
00638   {
00639     switch (CallbackID)
00640     {
00641       case HAL_SPI_MSPINIT_CB_ID :
00642         hspi->MspInitCallback = pCallback;
00643         break;
00644
00645       case HAL_SPI_MSPDEINIT_CB_ID :
00646         hspi->MspDeInitCallback = pCallback;
00647         break;
00648
00649       default :
00650         /* Update the error code */
00651         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00652
00653         /* Return error status */
00654         status =  HAL_ERROR;
00655         break;
00656     }
00657   }
00658   else
00659   {
00660     /* Update the error code */
00661     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00662
00663     /* Return error status */
00664     status =  HAL_ERROR;
00665   }
00666
00667   /* Release Lock */
00668   __HAL_UNLOCK(hspi);
00669   return status;
00670 }
00671
00672 /**
00673   * @brief  Unregister an SPI Callback
00674   *         SPI callback is redirected to the weak predefined callback
00675   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00676   *                the configuration information for the specified SPI.
00677   * @param  CallbackID ID of the callback to be unregistered
00678   * @retval HAL status
00679   */
00680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
00681 {
00682   HAL_StatusTypeDef status = HAL_OK;
00683
00684   /* Process locked */
00685   __HAL_LOCK(hspi);
00686
00687   if (HAL_SPI_STATE_READY == hspi->State)
00688   {
00689     switch (CallbackID)
00690     {
00691       case HAL_SPI_TX_COMPLETE_CB_ID :
00692         hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
00693         break;
00694
00695       case HAL_SPI_RX_COMPLETE_CB_ID :
00696         hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
00697         break;
00698
00699       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00700         hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
00701         break;
00702
00703       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00704         hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
00705         break;
00706
00707       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00708         hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
00709         break;
00710
00711       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00712         hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00713         break;
00714
00715       case HAL_SPI_ERROR_CB_ID :
00716         hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
00717         break;
00718
00719       case HAL_SPI_ABORT_CB_ID :
00720         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00721         break;
00722
00723       case HAL_SPI_MSPINIT_CB_ID :
00724         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00725         break;
00726
00727       case HAL_SPI_MSPDEINIT_CB_ID :
00728         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00729         break;
00730
00731       default :
00732         /* Update the error code */
00733         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00734
00735         /* Return error status */
00736         status =  HAL_ERROR;
00737         break;
00738     }
00739   }
00740   else if (HAL_SPI_STATE_RESET == hspi->State)
00741   {
00742     switch (CallbackID)
00743     {
00744       case HAL_SPI_MSPINIT_CB_ID :
00745         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00746         break;
00747
00748       case HAL_SPI_MSPDEINIT_CB_ID :
00749         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00750         break;
00751
00752       default :
00753         /* Update the error code */
00754         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00755
00756         /* Return error status */
00757         status =  HAL_ERROR;
00758         break;
00759     }
00760   }
00761   else
00762   {
00763     /* Update the error code */
00764     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00765
00766     /* Return error status */
00767     status =  HAL_ERROR;
00768   }
00769
00770   /* Release Lock */
00771   __HAL_UNLOCK(hspi);
00772   return status;
00773 }
00774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00780   *  @brief   Data transfers functions
00781   *
00782 @verbatim
00783   ==============================================================================
00784                       ##### IO operation functions #####
00785  ===============================================================================
00786  [..]
00787     This subsection provides a set of functions allowing to manage the SPI
00788     data transfers.
00789
00790     [..] The SPI supports master and slave mode :
00791
00792     (#) There are two modes of transfer:
00793        (++) Blocking mode: The communication is performed in polling mode.
00794             The HAL status of all data processing is returned by the same function
00795             after finishing transfer.
00796        (++) No-Blocking mode: The communication is performed using Interrupts
00797             or DMA, These APIs return the HAL status.
00798             The end of the data processing will be indicated through the
00799             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00800             using DMA mode.
00801             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00802             will be executed respectively at the end of the transmit or Receive process
00803             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00804
00805     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00806         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00807
00808 @endverbatim
00809   * @{
00810   */
00811
00812 /**
00813   * @brief  Transmit an amount of data in blocking mode.
00814   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00815   *               the configuration information for SPI module.
00816   * @param  pData pointer to data buffer
00817   * @param  Size amount of data to be sent
00818   * @param  Timeout Timeout duration
00819   * @retval HAL status
00820   */
00821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00822 {
00823   uint32_t tickstart;
00824   HAL_StatusTypeDef errorcode = HAL_OK;
00825   uint16_t initial_TxXferCount;
00826
00827   /* Check Direction parameter */
00828   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00829
00830   /* Process Locked */
00831   __HAL_LOCK(hspi);
00832
00833   /* Init tickstart for timeout management*/
00834   tickstart = HAL_GetTick();
00835   initial_TxXferCount = Size;
00836
00837   if (hspi->State != HAL_SPI_STATE_READY)
00838   {
00839     errorcode = HAL_BUSY;
00840     goto error;
00841   }
00842
00843   if ((pData == NULL) || (Size == 0U))
00844   {
00845     errorcode = HAL_ERROR;
00846     goto error;
00847   }
00848
00849   /* Set the transaction information */
00850   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00851   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00852   hspi->pTxBuffPtr  = (uint8_t *)pData;
00853   hspi->TxXferSize  = Size;
00854   hspi->TxXferCount = Size;
00855
00856   /*Init field not used in handle to zero */
00857   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00858   hspi->RxXferSize  = 0U;
00859   hspi->RxXferCount = 0U;
00860   hspi->TxISR       = NULL;
00861   hspi->RxISR       = NULL;
00862
00863   /* Configure communication direction : 1Line */
00864   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00865   {
00866     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
00867     __HAL_SPI_DISABLE(hspi);
00868     SPI_1LINE_TX(hspi);
00869   }
00870
00871 #if (USE_SPI_CRC != 0U)
00872   /* Reset CRC Calculation */
00873   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00874   {
00875     SPI_RESET_CRC(hspi);
00876   }
00877 #endif /* USE_SPI_CRC */
00878
00879   /* Check if the SPI is already enabled */
00880   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00881   {
00882     /* Enable SPI peripheral */
00883     __HAL_SPI_ENABLE(hspi);
00884   }
00885
00886   /* Transmit data in 16 Bit mode */
00887   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00888   {
00889     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00890     {
00891       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00892       hspi->pTxBuffPtr += sizeof(uint16_t);
00893       hspi->TxXferCount--;
00894     }
00895     /* Transmit data in 16 Bit mode */
00896     while (hspi->TxXferCount > 0U)
00897     {
00898       /* Wait until TXE flag is set to send data */
00899       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00900       {
00901         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00902         hspi->pTxBuffPtr += sizeof(uint16_t);
00903         hspi->TxXferCount--;
00904       }
00905       else
00906       {
00907         /* Timeout management */
00908         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00909         {
00910           errorcode = HAL_TIMEOUT;
00911           hspi->State = HAL_SPI_STATE_READY;
00912           goto error;
00913         }
00914       }
00915     }
00916   }
00917   /* Transmit data in 8 Bit mode */
00918   else
00919   {
00920     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00921     {
00922       if (hspi->TxXferCount > 1U)
00923       {
00924         /* write on the data register in packing mode */
00925         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00926         hspi->pTxBuffPtr += sizeof(uint16_t);
00927         hspi->TxXferCount -= 2U;
00928       }
00929       else
00930       {
00931         *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00932         hspi->pTxBuffPtr ++;
00933         hspi->TxXferCount--;
00934       }
00935     }
00936     while (hspi->TxXferCount > 0U)
00937     {
00938       /* Wait until TXE flag is set to send data */
00939       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00940       {
00941         if (hspi->TxXferCount > 1U)
00942         {
00943           /* write on the data register in packing mode */
00944           hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00945           hspi->pTxBuffPtr += sizeof(uint16_t);
00946           hspi->TxXferCount -= 2U;
00947         }
00948         else
00949         {
00950           *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00951           hspi->pTxBuffPtr++;
00952           hspi->TxXferCount--;
00953         }
00954       }
00955       else
00956       {
00957         /* Timeout management */
00958         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00959         {
00960           errorcode = HAL_TIMEOUT;
00961           hspi->State = HAL_SPI_STATE_READY;
00962           goto error;
00963         }
00964       }
00965     }
00966   }
00967 #if (USE_SPI_CRC != 0U)
00968   /* Enable CRC Transmission */
00969   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00970   {
00971     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00972   }
00973 #endif /* USE_SPI_CRC */
00974
00975   /* Check the end of the transaction */
00976   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00977   {
00978     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00979   }
00980
00981   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00982   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
00983   {
00984     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00985   }
00986
00987   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00988   {
00989     errorcode = HAL_ERROR;
00990   }
00991   else
00992   {
00993     hspi->State = HAL_SPI_STATE_READY;
00994   }
00995
00996 error:
00997   /* Process Unlocked */
00998   __HAL_UNLOCK(hspi);
00999   return errorcode;
01000 }
01001
01002 /**
01003   * @brief  Receive an amount of data in blocking mode.
01004   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01005   *               the configuration information for SPI module.
01006   * @param  pData pointer to data buffer
01007   * @param  Size amount of data to be received
01008   * @param  Timeout Timeout duration
01009   * @retval HAL status
01010   */
01011 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01012 {
01013 #if (USE_SPI_CRC != 0U)
01014   __IO uint32_t tmpreg = 0U;
01015   __IO uint8_t  *ptmpreg8;
01016   __IO uint8_t  tmpreg8 = 0;
01017 #endif /* USE_SPI_CRC */
01018   uint32_t tickstart;
01019   HAL_StatusTypeDef errorcode = HAL_OK;
01020
01021   if (hspi->State != HAL_SPI_STATE_READY)
01022   {
01023     errorcode = HAL_BUSY;
01024     goto error;
01025   }
01026
01027   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
01028   {
01029     hspi->State = HAL_SPI_STATE_BUSY_RX;
01030     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01031     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
01032   }
01033
01034   /* Process Locked */
01035   __HAL_LOCK(hspi);
01036
01037   /* Init tickstart for timeout management*/
01038   tickstart = HAL_GetTick();
01039
01040   if ((pData == NULL) || (Size == 0U))
01041   {
01042     errorcode = HAL_ERROR;
01043     goto error;
01044   }
01045
01046   /* Set the transaction information */
01047   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01048   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01049   hspi->pRxBuffPtr  = (uint8_t *)pData;
01050   hspi->RxXferSize  = Size;
01051   hspi->RxXferCount = Size;
01052
01053   /*Init field not used in handle to zero */
01054   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01055   hspi->TxXferSize  = 0U;
01056   hspi->TxXferCount = 0U;
01057   hspi->RxISR       = NULL;
01058   hspi->TxISR       = NULL;
01059
01060 #if (USE_SPI_CRC != 0U)
01061   /* Reset CRC Calculation */
01062   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01063   {
01064     SPI_RESET_CRC(hspi);
01065     /* this is done to handle the CRCNEXT before the latest data */
01066     hspi->RxXferCount--;
01067   }
01068 #endif /* USE_SPI_CRC */
01069
01070   /* Set the Rx Fifo threshold */
01071   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01072   {
01073     /* Set RX Fifo threshold according the reception data length: 16bit */
01074     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01075   }
01076   else
01077   {
01078     /* Set RX Fifo threshold according the reception data length: 8bit */
01079     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01080   }
01081
01082   /* Configure communication direction: 1Line */
01083   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01084   {
01085     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01086     __HAL_SPI_DISABLE(hspi);
01087     SPI_1LINE_RX(hspi);
01088   }
01089
01090   /* Check if the SPI is already enabled */
01091   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01092   {
01093     /* Enable SPI peripheral */
01094     __HAL_SPI_ENABLE(hspi);
01095   }
01096
01097   /* Receive data in 8 Bit mode */
01098   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
01099   {
01100     /* Transfer loop */
01101     while (hspi->RxXferCount > 0U)
01102     {
01103       /* Check the RXNE flag */
01104       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01105       {
01106         /* read the received data */
01107         (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01108         hspi->pRxBuffPtr += sizeof(uint8_t);
01109         hspi->RxXferCount--;
01110       }
01111       else
01112       {
01113         /* Timeout management */
01114         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01115         {
01116           errorcode = HAL_TIMEOUT;
01117           hspi->State = HAL_SPI_STATE_READY;
01118           goto error;
01119         }
01120       }
01121     }
01122   }
01123   else
01124   {
01125     /* Transfer loop */
01126     while (hspi->RxXferCount > 0U)
01127     {
01128       /* Check the RXNE flag */
01129       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01130       {
01131         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01132         hspi->pRxBuffPtr += sizeof(uint16_t);
01133         hspi->RxXferCount--;
01134       }
01135       else
01136       {
01137         /* Timeout management */
01138         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01139         {
01140           errorcode = HAL_TIMEOUT;
01141           hspi->State = HAL_SPI_STATE_READY;
01142           goto error;
01143         }
01144       }
01145     }
01146   }
01147
01148 #if (USE_SPI_CRC != 0U)
01149   /* Handle the CRC Transmission */
01150   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01151   {
01152     /* freeze the CRC before the latest data */
01153     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01154
01155     /* Read the latest data */
01156     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01157     {
01158       /* the latest data has not been received */
01159       errorcode = HAL_TIMEOUT;
01160       goto error;
01161     }
01162
01163     /* Receive last data in 16 Bit mode */
01164     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01165     {
01166       *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01167     }
01168     /* Receive last data in 8 Bit mode */
01169     else
01170     {
01171       (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01172     }
01173
01174     /* Wait the CRC data */
01175     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01176     {
01177       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01178       errorcode = HAL_TIMEOUT;
01179       goto error;
01180     }
01181
01182     /* Read CRC to Flush DR and RXNE flag */
01183     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01184     {
01185       /* Read 16bit CRC */
01186       tmpreg = READ_REG(hspi->Instance->DR);
01187       /* To avoid GCC warning */
01188       UNUSED(tmpreg);
01189     }
01190     else
01191     {
01192       /* Initialize the 8bit temporary pointer */
01193       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
01194       /* Read 8bit CRC */
01195       tmpreg8 = *ptmpreg8;
01196       /* To avoid GCC warning */
01197       UNUSED(tmpreg8);
01198
01199       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01200       {
01201         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01202         {
01203           /* Error on the CRC reception */
01204           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01205           errorcode = HAL_TIMEOUT;
01206           goto error;
01207         }
01208         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01209         tmpreg8 = *ptmpreg8;
01210         /* To avoid GCC warning */
01211         UNUSED(tmpreg8);
01212       }
01213     }
01214   }
01215 #endif /* USE_SPI_CRC */
01216
01217   /* Check the end of the transaction */
01218   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01219   {
01220     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01221   }
01222
01223 #if (USE_SPI_CRC != 0U)
01224   /* Check if CRC error occurred */
01225   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01226   {
01227     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01228     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01229   }
01230 #endif /* USE_SPI_CRC */
01231
01232   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01233   {
01234     errorcode = HAL_ERROR;
01235   }
01236   else
01237   {
01238     hspi->State = HAL_SPI_STATE_READY;
01239   }
01240
01241 error :
01242   __HAL_UNLOCK(hspi);
01243   return errorcode;
01244 }
01245
01246 /**
01247   * @brief  Transmit and Receive an amount of data in blocking mode.
01248   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01249   *               the configuration information for SPI module.
01250   * @param  pTxData pointer to transmission data buffer
01251   * @param  pRxData pointer to reception data buffer
01252   * @param  Size amount of data to be sent and received
01253   * @param  Timeout Timeout duration
01254   * @retval HAL status
01255   */
01256 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
01257                                           uint32_t Timeout)
01258 {
01259   uint16_t             initial_TxXferCount;
01260   uint16_t             initial_RxXferCount;
01261   uint32_t             tmp_mode;
01262   HAL_SPI_StateTypeDef tmp_state;
01263   uint32_t             tickstart;
01264 #if (USE_SPI_CRC != 0U)
01265   __IO uint32_t tmpreg = 0U;
01266   uint32_t             spi_cr1;
01267   uint32_t             spi_cr2;
01268   __IO uint8_t  *ptmpreg8;
01269   __IO uint8_t  tmpreg8 = 0;
01270 #endif /* USE_SPI_CRC */
01271
01272   /* Variable used to alternate Rx and Tx during transfer */
01273   uint32_t             txallowed = 1U;
01274   HAL_StatusTypeDef    errorcode = HAL_OK;
01275
01276   /* Check Direction parameter */
01277   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01278
01279   /* Process Locked */
01280   __HAL_LOCK(hspi);
01281
01282   /* Init tickstart for timeout management*/
01283   tickstart = HAL_GetTick();
01284
01285   /* Init temporary variables */
01286   tmp_state           = hspi->State;
01287   tmp_mode            = hspi->Init.Mode;
01288   initial_TxXferCount = Size;
01289   initial_RxXferCount = Size;
01290 #if (USE_SPI_CRC != 0U)
01291   spi_cr1             = READ_REG(hspi->Instance->CR1);
01292   spi_cr2             = READ_REG(hspi->Instance->CR2);
01293 #endif /* USE_SPI_CRC */
01294
01295   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01296         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01297   {
01298     errorcode = HAL_BUSY;
01299     goto error;
01300   }
01301
01302   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01303   {
01304     errorcode = HAL_ERROR;
01305     goto error;
01306   }
01307
01308   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01309   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01310   {
01311     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01312   }
01313
01314   /* Set the transaction information */
01315   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01316   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01317   hspi->RxXferCount = Size;
01318   hspi->RxXferSize  = Size;
01319   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01320   hspi->TxXferCount = Size;
01321   hspi->TxXferSize  = Size;
01322
01323   /*Init field not used in handle to zero */
01324   hspi->RxISR       = NULL;
01325   hspi->TxISR       = NULL;
01326
01327 #if (USE_SPI_CRC != 0U)
01328   /* Reset CRC Calculation */
01329   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01330   {
01331     SPI_RESET_CRC(hspi);
01332   }
01333 #endif /* USE_SPI_CRC */
01334
01335   /* Set the Rx Fifo threshold */
01336   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
01337   {
01338     /* Set fiforxthreshold according the reception data length: 16bit */
01339     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01340   }
01341   else
01342   {
01343     /* Set fiforxthreshold according the reception data length: 8bit */
01344     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01345   }
01346
01347   /* Check if the SPI is already enabled */
01348   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01349   {
01350     /* Enable SPI peripheral */
01351     __HAL_SPI_ENABLE(hspi);
01352   }
01353
01354   /* Transmit and Receive data in 16 Bit mode */
01355   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01356   {
01357     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01358     {
01359       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01360       hspi->pTxBuffPtr += sizeof(uint16_t);
01361       hspi->TxXferCount--;
01362
01363 #if (USE_SPI_CRC != 0U)
01364       /* Enable CRC Transmission */
01365       if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01366       {
01367         /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01368         if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01369         {
01370           SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01371         }
01372         SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01373       }
01374 #endif /* USE_SPI_CRC */
01375
01376     }
01377     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01378     {
01379       /* Check TXE flag */
01380       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01381       {
01382         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01383         hspi->pTxBuffPtr += sizeof(uint16_t);
01384         hspi->TxXferCount--;
01385         /* Next Data is a reception (Rx). Tx not allowed */
01386         txallowed = 0U;
01387
01388 #if (USE_SPI_CRC != 0U)
01389         /* Enable CRC Transmission */
01390         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01391         {
01392           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01393           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01394           {
01395             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01396           }
01397           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01398         }
01399 #endif /* USE_SPI_CRC */
01400       }
01401
01402       /* Check RXNE flag */
01403       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01404       {
01405         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01406         hspi->pRxBuffPtr += sizeof(uint16_t);
01407         hspi->RxXferCount--;
01408         /* Next Data is a Transmission (Tx). Tx is allowed */
01409         txallowed = 1U;
01410       }
01411       if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
01412       {
01413         errorcode = HAL_TIMEOUT;
01414         hspi->State = HAL_SPI_STATE_READY;
01415         goto error;
01416       }
01417     }
01418   }
01419   /* Transmit and Receive data in 8 Bit mode */
01420   else
01421   {
01422     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01423     {
01424       if (hspi->TxXferCount > 1U)
01425       {
01426         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01427         hspi->pTxBuffPtr += sizeof(uint16_t);
01428         hspi->TxXferCount -= 2U;
01429       }
01430       else
01431       {
01432         *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
01433         hspi->pTxBuffPtr++;
01434         hspi->TxXferCount--;
01435
01436 #if (USE_SPI_CRC != 0U)
01437         /* Enable CRC Transmission */
01438         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01439         {
01440           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01441           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01442           {
01443             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01444           }
01445           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01446         }
01447 #endif /* USE_SPI_CRC */
01448       }
01449     }
01450     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01451     {
01452       /* Check TXE flag */
01453       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01454       {
01455         if (hspi->TxXferCount > 1U)
01456         {
01457           hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01458           hspi->pTxBuffPtr += sizeof(uint16_t);
01459           hspi->TxXferCount -= 2U;
01460         }
01461         else
01462         {
01463           *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
01464           hspi->pTxBuffPtr++;
01465           hspi->TxXferCount--;
01466         }
01467         /* Next Data is a reception (Rx). Tx not allowed */
01468         txallowed = 0U;
01469
01470 #if (USE_SPI_CRC != 0U)
01471         /* Enable CRC Transmission */
01472         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01473         {
01474           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01475           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01476           {
01477             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01478           }
01479           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01480         }
01481 #endif /* USE_SPI_CRC */
01482       }
01483
01484       /* Wait until RXNE flag is reset */
01485       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01486       {
01487         if (hspi->RxXferCount > 1U)
01488         {
01489           *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01490           hspi->pRxBuffPtr += sizeof(uint16_t);
01491           hspi->RxXferCount -= 2U;
01492           if (hspi->RxXferCount <= 1U)
01493           {
01494             /* Set RX Fifo threshold before to switch on 8 bit data size */
01495             SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01496           }
01497         }
01498         else
01499         {
01500           (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01501           hspi->pRxBuffPtr++;
01502           hspi->RxXferCount--;
01503         }
01504         /* Next Data is a Transmission (Tx). Tx is allowed */
01505         txallowed = 1U;
01506       }
01507       if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
01508       {
01509         errorcode = HAL_TIMEOUT;
01510         hspi->State = HAL_SPI_STATE_READY;
01511         goto error;
01512       }
01513     }
01514   }
01515
01516 #if (USE_SPI_CRC != 0U)
01517   /* Read CRC from DR to close CRC calculation process */
01518   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01519   {
01520     /* Wait until TXE flag */
01521     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01522     {
01523       /* Error on the CRC reception */
01524       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01525       errorcode = HAL_TIMEOUT;
01526       goto error;
01527     }
01528     /* Read CRC */
01529     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01530     {
01531       /* Read 16bit CRC */
01532       tmpreg = READ_REG(hspi->Instance->DR);
01533       /* To avoid GCC warning */
01534       UNUSED(tmpreg);
01535     }
01536     else
01537     {
01538       /* Initialize the 8bit temporary pointer */
01539       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
01540       /* Read 8bit CRC */
01541       tmpreg8 = *ptmpreg8;
01542       /* To avoid GCC warning */
01543       UNUSED(tmpreg8);
01544
01545       if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01546       {
01547         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01548         {
01549           /* Error on the CRC reception */
01550           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01551           errorcode = HAL_TIMEOUT;
01552           goto error;
01553         }
01554         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01555         tmpreg8 = *ptmpreg8;
01556         /* To avoid GCC warning */
01557         UNUSED(tmpreg8);
01558       }
01559     }
01560   }
01561
01562   /* Check if CRC error occurred */
01563   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01564   {
01565     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01566     /* Clear CRC Flag */
01567     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01568
01569     errorcode = HAL_ERROR;
01570   }
01571 #endif /* USE_SPI_CRC */
01572
01573   /* Check the end of the transaction */
01574   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01575   {
01576     errorcode = HAL_ERROR;
01577     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01578   }
01579
01580   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01581   {
01582     errorcode = HAL_ERROR;
01583   }
01584   else
01585   {
01586     hspi->State = HAL_SPI_STATE_READY;
01587   }
01588
01589 error :
01590   __HAL_UNLOCK(hspi);
01591   return errorcode;
01592 }
01593
01594 /**
01595   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01596   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01597   *               the configuration information for SPI module.
01598   * @param  pData pointer to data buffer
01599   * @param  Size amount of data to be sent
01600   * @retval HAL status
01601   */
01602 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01603 {
01604   HAL_StatusTypeDef errorcode = HAL_OK;
01605
01606   /* Check Direction parameter */
01607   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01608
01609
01610   if ((pData == NULL) || (Size == 0U))
01611   {
01612     errorcode = HAL_ERROR;
01613     goto error;
01614   }
01615
01616   if (hspi->State != HAL_SPI_STATE_READY)
01617   {
01618     errorcode = HAL_BUSY;
01619     goto error;
01620   }
01621
01622   /* Process Locked */
01623   __HAL_LOCK(hspi);
01624
01625   /* Set the transaction information */
01626   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01627   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01628   hspi->pTxBuffPtr  = (uint8_t *)pData;
01629   hspi->TxXferSize  = Size;
01630   hspi->TxXferCount = Size;
01631
01632   /* Init field not used in handle to zero */
01633   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01634   hspi->RxXferSize  = 0U;
01635   hspi->RxXferCount = 0U;
01636   hspi->RxISR       = NULL;
01637
01638   /* Set the function for IT treatment */
01639   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01640   {
01641     hspi->TxISR = SPI_TxISR_16BIT;
01642   }
01643   else
01644   {
01645     hspi->TxISR = SPI_TxISR_8BIT;
01646   }
01647
01648   /* Configure communication direction : 1Line */
01649   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01650   {
01651     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01652     __HAL_SPI_DISABLE(hspi);
01653     SPI_1LINE_TX(hspi);
01654   }
01655
01656 #if (USE_SPI_CRC != 0U)
01657   /* Reset CRC Calculation */
01658   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01659   {
01660     SPI_RESET_CRC(hspi);
01661   }
01662 #endif /* USE_SPI_CRC */
01663
01664   /* Check if the SPI is already enabled */
01665   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01666   {
01667     /* Enable SPI peripheral */
01668     __HAL_SPI_ENABLE(hspi);
01669   }
01670
01671   /* Process Unlocked */
01672   __HAL_UNLOCK(hspi);
01673   /* Enable TXE and ERR interrupt */
01674   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01675
01676 error :
01677   return errorcode;
01678 }
01679
01680 /**
01681   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01682   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01683   *               the configuration information for SPI module.
01684   * @param  pData pointer to data buffer
01685   * @param  Size amount of data to be sent
01686   * @retval HAL status
01687   */
01688 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01689 {
01690   HAL_StatusTypeDef errorcode = HAL_OK;
01691
01692
01693   if (hspi->State != HAL_SPI_STATE_READY)
01694   {
01695     errorcode = HAL_BUSY;
01696     goto error;
01697   }
01698
01699   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01700   {
01701     hspi->State = HAL_SPI_STATE_BUSY_RX;
01702     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01703     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01704   }
01705
01706
01707   if ((pData == NULL) || (Size == 0U))
01708   {
01709     errorcode = HAL_ERROR;
01710     goto error;
01711   }
01712
01713   /* Process Locked */
01714   __HAL_LOCK(hspi);
01715
01716   /* Set the transaction information */
01717   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01718   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01719   hspi->pRxBuffPtr  = (uint8_t *)pData;
01720   hspi->RxXferSize  = Size;
01721   hspi->RxXferCount = Size;
01722
01723   /* Init field not used in handle to zero */
01724   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01725   hspi->TxXferSize  = 0U;
01726   hspi->TxXferCount = 0U;
01727   hspi->TxISR       = NULL;
01728
01729   /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
01730   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01731   {
01732     /* Set RX Fifo threshold according the reception data length: 16 bit */
01733     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01734     hspi->RxISR = SPI_RxISR_16BIT;
01735   }
01736   else
01737   {
01738     /* Set RX Fifo threshold according the reception data length: 8 bit */
01739     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01740     hspi->RxISR = SPI_RxISR_8BIT;
01741   }
01742
01743   /* Configure communication direction : 1Line */
01744   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01745   {
01746     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01747     __HAL_SPI_DISABLE(hspi);
01748     SPI_1LINE_RX(hspi);
01749   }
01750
01751 #if (USE_SPI_CRC != 0U)
01752   /* Reset CRC Calculation */
01753   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01754   {
01755     hspi->CRCSize = 1U;
01756     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01757     {
01758       hspi->CRCSize = 2U;
01759     }
01760     SPI_RESET_CRC(hspi);
01761   }
01762   else
01763   {
01764     hspi->CRCSize = 0U;
01765   }
01766 #endif /* USE_SPI_CRC */
01767
01768   /* Note : The SPI must be enabled after unlocking current process
01769             to avoid the risk of SPI interrupt handle execution before current
01770             process unlock */
01771
01772   /* Check if the SPI is already enabled */
01773   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01774   {
01775     /* Enable SPI peripheral */
01776     __HAL_SPI_ENABLE(hspi);
01777   }
01778
01779   /* Process Unlocked */
01780   __HAL_UNLOCK(hspi);
01781   /* Enable RXNE and ERR interrupt */
01782   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01783
01784 error :
01785   return errorcode;
01786 }
01787
01788 /**
01789   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01790   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01791   *               the configuration information for SPI module.
01792   * @param  pTxData pointer to transmission data buffer
01793   * @param  pRxData pointer to reception data buffer
01794   * @param  Size amount of data to be sent and received
01795   * @retval HAL status
01796   */
01797 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01798 {
01799   uint32_t             tmp_mode;
01800   HAL_SPI_StateTypeDef tmp_state;
01801   HAL_StatusTypeDef    errorcode = HAL_OK;
01802
01803   /* Check Direction parameter */
01804   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01805
01806   /* Init temporary variables */
01807   tmp_state           = hspi->State;
01808   tmp_mode            = hspi->Init.Mode;
01809
01810   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01811         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01812   {
01813     errorcode = HAL_BUSY;
01814     goto error;
01815   }
01816
01817   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01818   {
01819     errorcode = HAL_ERROR;
01820     goto error;
01821   }
01822
01823   /* Process locked */
01824   __HAL_LOCK(hspi);
01825
01826   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01827   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01828   {
01829     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01830   }
01831
01832   /* Set the transaction information */
01833   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01834   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01835   hspi->TxXferSize  = Size;
01836   hspi->TxXferCount = Size;
01837   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01838   hspi->RxXferSize  = Size;
01839   hspi->RxXferCount = Size;
01840
01841   /* Set the function for IT treatment */
01842   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01843   {
01844     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01845     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01846   }
01847   else
01848   {
01849     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01850     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01851   }
01852
01853 #if (USE_SPI_CRC != 0U)
01854   /* Reset CRC Calculation */
01855   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01856   {
01857     hspi->CRCSize = 1U;
01858     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01859     {
01860       hspi->CRCSize = 2U;
01861     }
01862     SPI_RESET_CRC(hspi);
01863   }
01864   else
01865   {
01866     hspi->CRCSize = 0U;
01867   }
01868 #endif /* USE_SPI_CRC */
01869
01870   /* Check if packing mode is enabled and if there is more than 2 data to receive */
01871   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
01872   {
01873     /* Set RX Fifo threshold according the reception data length: 16 bit */
01874     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01875   }
01876   else
01877   {
01878     /* Set RX Fifo threshold according the reception data length: 8 bit */
01879     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01880   }
01881
01882
01883   /* Check if the SPI is already enabled */
01884   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01885   {
01886     /* Enable SPI peripheral */
01887     __HAL_SPI_ENABLE(hspi);
01888   }
01889
01890   /* Process Unlocked */
01891   __HAL_UNLOCK(hspi);
01892   /* Enable TXE, RXNE and ERR interrupt */
01893   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01894
01895 error :
01896   return errorcode;
01897 }
01898
01899 /**
01900   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01901   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01902   *               the configuration information for SPI module.
01903   * @param  pData pointer to data buffer
01904   * @param  Size amount of data to be sent
01905   * @retval HAL status
01906   */
01907 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01908 {
01909   HAL_StatusTypeDef errorcode = HAL_OK;
01910
01911   /* Check tx dma handle */
01912   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01913
01914   /* Check Direction parameter */
01915   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01916
01917   /* Process Locked */
01918   __HAL_LOCK(hspi);
01919
01920   if (hspi->State != HAL_SPI_STATE_READY)
01921   {
01922     errorcode = HAL_BUSY;
01923     goto error;
01924   }
01925
01926   if ((pData == NULL) || (Size == 0U))
01927   {
01928     errorcode = HAL_ERROR;
01929     goto error;
01930   }
01931
01932   /* Set the transaction information */
01933   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01934   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01935   hspi->pTxBuffPtr  = (uint8_t *)pData;
01936   hspi->TxXferSize  = Size;
01937   hspi->TxXferCount = Size;
01938
01939   /* Init field not used in handle to zero */
01940   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01941   hspi->TxISR       = NULL;
01942   hspi->RxISR       = NULL;
01943   hspi->RxXferSize  = 0U;
01944   hspi->RxXferCount = 0U;
01945
01946   /* Configure communication direction : 1Line */
01947   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01948   {
01949     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01950     __HAL_SPI_DISABLE(hspi);
01951     SPI_1LINE_TX(hspi);
01952   }
01953
01954 #if (USE_SPI_CRC != 0U)
01955   /* Reset CRC Calculation */
01956   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01957   {
01958     SPI_RESET_CRC(hspi);
01959   }
01960 #endif /* USE_SPI_CRC */
01961
01962   /* Set the SPI TxDMA Half transfer complete callback */
01963   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01964
01965   /* Set the SPI TxDMA transfer complete callback */
01966   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01967
01968   /* Set the DMA error callback */
01969   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01970
01971   /* Set the DMA AbortCpltCallback */
01972   hspi->hdmatx->XferAbortCallback = NULL;
01973
01974   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01975   /* Packing mode is enabled only if the DMA setting is HALWORD */
01976   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01977   {
01978     /* Check the even/odd of the data size + crc if enabled */
01979     if ((hspi->TxXferCount & 0x1U) == 0U)
01980     {
01981       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01982       hspi->TxXferCount = (hspi->TxXferCount >> 1U);
01983     }
01984     else
01985     {
01986       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01987       hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01988     }
01989   }
01990
01991   /* Enable the Tx DMA Stream/Channel */
01992   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
01993                                  hspi->TxXferCount))
01994   {
01995     /* Update SPI error code */
01996     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
01997     errorcode = HAL_ERROR;
01998
01999     goto error;
02000   }
02001
02002   /* Check if the SPI is already enabled */
02003   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02004   {
02005     /* Enable SPI peripheral */
02006     __HAL_SPI_ENABLE(hspi);
02007   }
02008
02009   /* Enable the SPI Error Interrupt Bit */
02010   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02011
02012   /* Enable Tx DMA Request */
02013   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02014
02015 error :
02016   /* Process Unlocked */
02017   __HAL_UNLOCK(hspi);
02018   return errorcode;
02019 }
02020
02021 /**
02022   * @brief  Receive an amount of data in non-blocking mode with DMA.
02023   * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
02024   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02025   *               the configuration information for SPI module.
02026   * @param  pData pointer to data buffer
02027   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
02028   * @param  Size amount of data to be sent
02029   * @retval HAL status
02030   */
02031 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
02032 {
02033   HAL_StatusTypeDef errorcode = HAL_OK;
02034
02035   /* Check rx dma handle */
02036   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
02037
02038   if (hspi->State != HAL_SPI_STATE_READY)
02039   {
02040     errorcode = HAL_BUSY;
02041     goto error;
02042   }
02043
02044   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
02045   {
02046     hspi->State = HAL_SPI_STATE_BUSY_RX;
02047
02048     /* Check tx dma handle */
02049     assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
02050
02051     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
02052     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
02053   }
02054
02055   /* Process Locked */
02056   __HAL_LOCK(hspi);
02057
02058   if ((pData == NULL) || (Size == 0U))
02059   {
02060     errorcode = HAL_ERROR;
02061     goto error;
02062   }
02063
02064   /* Set the transaction information */
02065   hspi->State       = HAL_SPI_STATE_BUSY_RX;
02066   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02067   hspi->pRxBuffPtr  = (uint8_t *)pData;
02068   hspi->RxXferSize  = Size;
02069   hspi->RxXferCount = Size;
02070
02071   /*Init field not used in handle to zero */
02072   hspi->RxISR       = NULL;
02073   hspi->TxISR       = NULL;
02074   hspi->TxXferSize  = 0U;
02075   hspi->TxXferCount = 0U;
02076
02077   /* Configure communication direction : 1Line */
02078   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
02079   {
02080     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
02081     __HAL_SPI_DISABLE(hspi);
02082     SPI_1LINE_RX(hspi);
02083   }
02084
02085 #if (USE_SPI_CRC != 0U)
02086   /* Reset CRC Calculation */
02087   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02088   {
02089     SPI_RESET_CRC(hspi);
02090   }
02091 #endif /* USE_SPI_CRC */
02092
02093
02094   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02095   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02096   {
02097     /* Set RX Fifo threshold according the reception data length: 16bit */
02098     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02099   }
02100   else
02101   {
02102     /* Set RX Fifo threshold according the reception data length: 8bit */
02103     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02104
02105     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02106     {
02107       /* Set RX Fifo threshold according the reception data length: 16bit */
02108       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02109
02110       if ((hspi->RxXferCount & 0x1U) == 0x0U)
02111       {
02112         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02113         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02114       }
02115       else
02116       {
02117         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02118         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02119       }
02120     }
02121   }
02122
02123   /* Set the SPI RxDMA Half transfer complete callback */
02124   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02125
02126   /* Set the SPI Rx DMA transfer complete callback */
02127   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
02128
02129   /* Set the DMA error callback */
02130   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02131
02132   /* Set the DMA AbortCpltCallback */
02133   hspi->hdmarx->XferAbortCallback = NULL;
02134
02135   /* Enable the Rx DMA Stream/Channel  */
02136   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02137                                  hspi->RxXferCount))
02138   {
02139     /* Update SPI error code */
02140     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02141     errorcode = HAL_ERROR;
02142
02143     goto error;
02144   }
02145
02146   /* Check if the SPI is already enabled */
02147   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02148   {
02149     /* Enable SPI peripheral */
02150     __HAL_SPI_ENABLE(hspi);
02151   }
02152
02153   /* Enable the SPI Error Interrupt Bit */
02154   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02155
02156   /* Enable Rx DMA Request */
02157   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02158
02159 error:
02160   /* Process Unlocked */
02161   __HAL_UNLOCK(hspi);
02162   return errorcode;
02163 }
02164
02165 /**
02166   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
02167   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02168   *               the configuration information for SPI module.
02169   * @param  pTxData pointer to transmission data buffer
02170   * @param  pRxData pointer to reception data buffer
02171   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
02172   * @param  Size amount of data to be sent
02173   * @retval HAL status
02174   */
02175 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
02176                                               uint16_t Size)
02177 {
02178   uint32_t             tmp_mode;
02179   HAL_SPI_StateTypeDef tmp_state;
02180   HAL_StatusTypeDef errorcode = HAL_OK;
02181
02182   /* Check rx & tx dma handles */
02183   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
02184   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
02185
02186   /* Check Direction parameter */
02187   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
02188
02189   /* Process locked */
02190   __HAL_LOCK(hspi);
02191
02192   /* Init temporary variables */
02193   tmp_state           = hspi->State;
02194   tmp_mode            = hspi->Init.Mode;
02195
02196   if (!((tmp_state == HAL_SPI_STATE_READY) ||
02197         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
02198   {
02199     errorcode = HAL_BUSY;
02200     goto error;
02201   }
02202
02203   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
02204   {
02205     errorcode = HAL_ERROR;
02206     goto error;
02207   }
02208
02209   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
02210   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
02211   {
02212     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
02213   }
02214
02215   /* Set the transaction information */
02216   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02217   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
02218   hspi->TxXferSize  = Size;
02219   hspi->TxXferCount = Size;
02220   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
02221   hspi->RxXferSize  = Size;
02222   hspi->RxXferCount = Size;
02223
02224   /* Init field not used in handle to zero */
02225   hspi->RxISR       = NULL;
02226   hspi->TxISR       = NULL;
02227
02228 #if (USE_SPI_CRC != 0U)
02229   /* Reset CRC Calculation */
02230   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02231   {
02232     SPI_RESET_CRC(hspi);
02233   }
02234 #endif /* USE_SPI_CRC */
02235
02236   /* Reset the threshold bit */
02237   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
02238
02239   /* The packing mode management is enabled by the DMA settings according the spi data size */
02240   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02241   {
02242     /* Set fiforxthreshold according the reception data length: 16bit */
02243     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02244   }
02245   else
02246   {
02247     /* Set RX Fifo threshold according the reception data length: 8bit */
02248     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02249
02250     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02251     {
02252       if ((hspi->TxXferSize & 0x1U) == 0x0U)
02253       {
02254         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02255         hspi->TxXferCount = hspi->TxXferCount >> 1U;
02256       }
02257       else
02258       {
02259         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02260         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
02261       }
02262     }
02263
02264     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02265     {
02266       /* Set RX Fifo threshold according the reception data length: 16bit */
02267       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02268
02269       if ((hspi->RxXferCount & 0x1U) == 0x0U)
02270       {
02271         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02272         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02273       }
02274       else
02275       {
02276         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02277         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02278       }
02279     }
02280   }
02281
02282   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
02283   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
02284   {
02285     /* Set the SPI Rx DMA Half transfer complete callback */
02286     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02287     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
02288   }
02289   else
02290   {
02291     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
02292     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
02293     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
02294   }
02295
02296   /* Set the DMA error callback */
02297   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02298
02299   /* Set the DMA AbortCpltCallback */
02300   hspi->hdmarx->XferAbortCallback = NULL;
02301
02302   /* Enable the Rx DMA Stream/Channel  */
02303   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02304                                  hspi->RxXferCount))
02305   {
02306     /* Update SPI error code */
02307     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02308     errorcode = HAL_ERROR;
02309
02310     goto error;
02311   }
02312
02313   /* Enable Rx DMA Request */
02314   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02315
02316   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
02317   is performed in DMA reception complete callback  */
02318   hspi->hdmatx->XferHalfCpltCallback = NULL;
02319   hspi->hdmatx->XferCpltCallback     = NULL;
02320   hspi->hdmatx->XferErrorCallback    = NULL;
02321   hspi->hdmatx->XferAbortCallback    = NULL;
02322
02323   /* Enable the Tx DMA Stream/Channel  */
02324   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
02325                                  hspi->TxXferCount))
02326   {
02327     /* Update SPI error code */
02328     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02329     errorcode = HAL_ERROR;
02330
02331     goto error;
02332   }
02333
02334   /* Check if the SPI is already enabled */
02335   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02336   {
02337     /* Enable SPI peripheral */
02338     __HAL_SPI_ENABLE(hspi);
02339   }
02340   /* Enable the SPI Error Interrupt Bit */
02341   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02342
02343   /* Enable Tx DMA Request */
02344   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02345
02346 error :
02347   /* Process Unlocked */
02348   __HAL_UNLOCK(hspi);
02349   return errorcode;
02350 }
02351
02352 /**
02353   * @brief  Abort ongoing transfer (blocking mode).
02354   * @param  hspi SPI handle.
02355   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02356   *         started in Interrupt or DMA mode.
02357   *         This procedure performs following operations :
02358   *           - Disable SPI Interrupts (depending of transfer direction)
02359   *           - Disable the DMA transfer in the peripheral register (if enabled)
02360   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
02361   *           - Set handle State to READY
02362   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
02363   * @retval HAL status
02364   */
02365 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
02366 {
02367   HAL_StatusTypeDef errorcode;
02368   __IO uint32_t count;
02369   __IO uint32_t resetcount;
02370
02371   /* Initialized local variable  */
02372   errorcode = HAL_OK;
02373   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02374   count = resetcount;
02375
02376   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02377   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02378
02379   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
02380   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02381   {
02382     hspi->TxISR = SPI_AbortTx_ISR;
02383     /* Wait HAL_SPI_STATE_ABORT state */
02384     do
02385     {
02386       if (count == 0U)
02387       {
02388         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02389         break;
02390       }
02391       count--;
02392     } while (hspi->State != HAL_SPI_STATE_ABORT);
02393     /* Reset Timeout Counter */
02394     count = resetcount;
02395   }
02396
02397   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02398   {
02399     hspi->RxISR = SPI_AbortRx_ISR;
02400     /* Wait HAL_SPI_STATE_ABORT state */
02401     do
02402     {
02403       if (count == 0U)
02404       {
02405         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02406         break;
02407       }
02408       count--;
02409     } while (hspi->State != HAL_SPI_STATE_ABORT);
02410     /* Reset Timeout Counter */
02411     count = resetcount;
02412   }
02413
02414   /* Disable the SPI DMA Tx request if enabled */
02415   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02416   {
02417     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
02418     if (hspi->hdmatx != NULL)
02419     {
02420       /* Set the SPI DMA Abort callback :
02421       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02422       hspi->hdmatx->XferAbortCallback = NULL;
02423
02424       /* Abort DMA Tx Handle linked to SPI Peripheral */
02425       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02426       {
02427         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02428       }
02429
02430       /* Disable Tx DMA Request */
02431       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
02432
02433       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02434       {
02435         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02436       }
02437
02438       /* Disable SPI Peripheral */
02439       __HAL_SPI_DISABLE(hspi);
02440
02441       /* Empty the FRLVL fifo */
02442       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02443       {
02444         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02445       }
02446     }
02447   }
02448
02449   /* Disable the SPI DMA Rx request if enabled */
02450   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02451   {
02452     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02453     if (hspi->hdmarx != NULL)
02454     {
02455       /* Set the SPI DMA Abort callback :
02456       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02457       hspi->hdmarx->XferAbortCallback = NULL;
02458
02459       /* Abort DMA Rx Handle linked to SPI Peripheral */
02460       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02461       {
02462         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02463       }
02464
02465       /* Disable peripheral */
02466       __HAL_SPI_DISABLE(hspi);
02467
02468       /* Control the BSY flag */
02469       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02470       {
02471         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02472       }
02473
02474       /* Empty the FRLVL fifo */
02475       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02476       {
02477         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02478       }
02479
02480       /* Disable Rx DMA Request */
02481       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
02482     }
02483   }
02484   /* Reset Tx and Rx transfer counters */
02485   hspi->RxXferCount = 0U;
02486   hspi->TxXferCount = 0U;
02487
02488   /* Check error during Abort procedure */
02489   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02490   {
02491     /* return HAL_Error in case of error during Abort procedure */
02492     errorcode = HAL_ERROR;
02493   }
02494   else
02495   {
02496     /* Reset errorCode */
02497     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02498   }
02499
02500   /* Clear the Error flags in the SR register */
02501   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02502   __HAL_SPI_CLEAR_FREFLAG(hspi);
02503
02504   /* Restore hspi->state to ready */
02505   hspi->State = HAL_SPI_STATE_READY;
02506
02507   return errorcode;
02508 }
02509
02510 /**
02511   * @brief  Abort ongoing transfer (Interrupt mode).
02512   * @param  hspi SPI handle.
02513   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02514   *         started in Interrupt or DMA mode.
02515   *         This procedure performs following operations :
02516   *           - Disable SPI Interrupts (depending of transfer direction)
02517   *           - Disable the DMA transfer in the peripheral register (if enabled)
02518   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02519   *           - Set handle State to READY
02520   *           - At abort completion, call user abort complete callback
02521   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02522   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02523   * @retval HAL status
02524   */
02525 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02526 {
02527   HAL_StatusTypeDef errorcode;
02528   uint32_t abortcplt ;
02529   __IO uint32_t count;
02530   __IO uint32_t resetcount;
02531
02532   /* Initialized local variable  */
02533   errorcode = HAL_OK;
02534   abortcplt = 1U;
02535   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02536   count = resetcount;
02537
02538   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02539   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02540
02541   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
02542   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02543   {
02544     hspi->TxISR = SPI_AbortTx_ISR;
02545     /* Wait HAL_SPI_STATE_ABORT state */
02546     do
02547     {
02548       if (count == 0U)
02549       {
02550         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02551         break;
02552       }
02553       count--;
02554     } while (hspi->State != HAL_SPI_STATE_ABORT);
02555     /* Reset Timeout Counter */
02556     count = resetcount;
02557   }
02558
02559   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02560   {
02561     hspi->RxISR = SPI_AbortRx_ISR;
02562     /* Wait HAL_SPI_STATE_ABORT state */
02563     do
02564     {
02565       if (count == 0U)
02566       {
02567         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02568         break;
02569       }
02570       count--;
02571     } while (hspi->State != HAL_SPI_STATE_ABORT);
02572     /* Reset Timeout Counter */
02573     count = resetcount;
02574   }
02575
02576   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
02577      before any call to DMA Abort functions */
02578   /* DMA Tx Handle is valid */
02579   if (hspi->hdmatx != NULL)
02580   {
02581     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
02582        Otherwise, set it to NULL */
02583     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02584     {
02585       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02586     }
02587     else
02588     {
02589       hspi->hdmatx->XferAbortCallback = NULL;
02590     }
02591   }
02592   /* DMA Rx Handle is valid */
02593   if (hspi->hdmarx != NULL)
02594   {
02595     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02596        Otherwise, set it to NULL */
02597     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02598     {
02599       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02600     }
02601     else
02602     {
02603       hspi->hdmarx->XferAbortCallback = NULL;
02604     }
02605   }
02606
02607   /* Disable the SPI DMA Tx request if enabled */
02608   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02609   {
02610     /* Abort the SPI DMA Tx Stream/Channel */
02611     if (hspi->hdmatx != NULL)
02612     {
02613       /* Abort DMA Tx Handle linked to SPI Peripheral */
02614       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02615       {
02616         hspi->hdmatx->XferAbortCallback = NULL;
02617         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02618       }
02619       else
02620       {
02621         abortcplt = 0U;
02622       }
02623     }
02624   }
02625   /* Disable the SPI DMA Rx request if enabled */
02626   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02627   {
02628     /* Abort the SPI DMA Rx Stream/Channel */
02629     if (hspi->hdmarx != NULL)
02630     {
02631       /* Abort DMA Rx Handle linked to SPI Peripheral */
02632       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02633       {
02634         hspi->hdmarx->XferAbortCallback = NULL;
02635         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02636       }
02637       else
02638       {
02639         abortcplt = 0U;
02640       }
02641     }
02642   }
02643
02644   if (abortcplt == 1U)
02645   {
02646     /* Reset Tx and Rx transfer counters */
02647     hspi->RxXferCount = 0U;
02648     hspi->TxXferCount = 0U;
02649
02650     /* Check error during Abort procedure */
02651     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02652     {
02653       /* return HAL_Error in case of error during Abort procedure */
02654       errorcode = HAL_ERROR;
02655     }
02656     else
02657     {
02658       /* Reset errorCode */
02659       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02660     }
02661
02662     /* Clear the Error flags in the SR register */
02663     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02664     __HAL_SPI_CLEAR_FREFLAG(hspi);
02665
02666     /* Restore hspi->State to Ready */
02667     hspi->State = HAL_SPI_STATE_READY;
02668
02669     /* As no DMA to be aborted, call directly user Abort complete callback */
02670 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02671     hspi->AbortCpltCallback(hspi);
02672 #else
02673     HAL_SPI_AbortCpltCallback(hspi);
02674 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02675   }
02676
02677   return errorcode;
02678 }
02679
02680 /**
02681   * @brief  Pause the DMA Transfer.
02682   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02683   *               the configuration information for the specified SPI module.
02684   * @retval HAL status
02685   */
02686 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02687 {
02688   /* Process Locked */
02689   __HAL_LOCK(hspi);
02690
02691   /* Disable the SPI DMA Tx & Rx requests */
02692   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02693
02694   /* Process Unlocked */
02695   __HAL_UNLOCK(hspi);
02696
02697   return HAL_OK;
02698 }
02699
02700 /**
02701   * @brief  Resume the DMA Transfer.
02702   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02703   *               the configuration information for the specified SPI module.
02704   * @retval HAL status
02705   */
02706 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02707 {
02708   /* Process Locked */
02709   __HAL_LOCK(hspi);
02710
02711   /* Enable the SPI DMA Tx & Rx requests */
02712   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02713
02714   /* Process Unlocked */
02715   __HAL_UNLOCK(hspi);
02716
02717   return HAL_OK;
02718 }
02719
02720 /**
02721   * @brief  Stop the DMA Transfer.
02722   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02723   *               the configuration information for the specified SPI module.
02724   * @retval HAL status
02725   */
02726 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02727 {
02728   HAL_StatusTypeDef errorcode = HAL_OK;
02729   /* The Lock is not implemented on this API to allow the user application
02730      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
02731      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
02732      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
02733      */
02734
02735   /* Abort the SPI DMA tx Stream/Channel  */
02736   if (hspi->hdmatx != NULL)
02737   {
02738     if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
02739     {
02740       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02741       errorcode = HAL_ERROR;
02742     }
02743   }
02744   /* Abort the SPI DMA rx Stream/Channel  */
02745   if (hspi->hdmarx != NULL)
02746   {
02747     if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
02748     {
02749       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02750       errorcode = HAL_ERROR;
02751     }
02752   }
02753
02754   /* Disable the SPI DMA Tx & Rx requests */
02755   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02756   hspi->State = HAL_SPI_STATE_READY;
02757   return errorcode;
02758 }
02759
02760 /**
02761   * @brief  Handle SPI interrupt request.
02762   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02763   *               the configuration information for the specified SPI module.
02764   * @retval None
02765   */
02766 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02767 {
02768   uint32_t itsource = hspi->Instance->CR2;
02769   uint32_t itflag   = hspi->Instance->SR;
02770
02771   /* SPI in mode Receiver ----------------------------------------------------*/
02772   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
02773       (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
02774   {
02775     hspi->RxISR(hspi);
02776     return;
02777   }
02778
02779   /* SPI in mode Transmitter -------------------------------------------------*/
02780   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
02781   {
02782     hspi->TxISR(hspi);
02783     return;
02784   }
02785
02786   /* SPI in Error Treatment --------------------------------------------------*/
02787   if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02788        || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
02789   {
02790     /* SPI Overrun error interrupt occurred ----------------------------------*/
02791     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02792     {
02793       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
02794       {
02795         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02796         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02797       }
02798       else
02799       {
02800         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02801         return;
02802       }
02803     }
02804
02805     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02806     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
02807     {
02808       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02809       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02810     }
02811
02812     /* SPI Frame error interrupt occurred ------------------------------------*/
02813     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
02814     {
02815       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02816       __HAL_SPI_CLEAR_FREFLAG(hspi);
02817     }
02818
02819     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02820     {
02821       /* Disable all interrupts */
02822       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
02823
02824       hspi->State = HAL_SPI_STATE_READY;
02825       /* Disable the SPI DMA requests if enabled */
02826       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
02827       {
02828         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
02829
02830         /* Abort the SPI DMA Rx channel */
02831         if (hspi->hdmarx != NULL)
02832         {
02833           /* Set the SPI DMA Abort callback :
02834           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02835           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02836           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
02837           {
02838             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02839           }
02840         }
02841         /* Abort the SPI DMA Tx channel */
02842         if (hspi->hdmatx != NULL)
02843         {
02844           /* Set the SPI DMA Abort callback :
02845           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02846           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02847           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
02848           {
02849             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02850           }
02851         }
02852       }
02853       else
02854       {
02855         /* Call user error callback */
02856 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02857         hspi->ErrorCallback(hspi);
02858 #else
02859         HAL_SPI_ErrorCallback(hspi);
02860 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02861       }
02862     }
02863     return;
02864   }
02865 }
02866
02867 /**
02868   * @brief  Tx Transfer completed callback.
02869   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02870   *               the configuration information for SPI module.
02871   * @retval None
02872   */
02873 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02874 {
02875   /* Prevent unused argument(s) compilation warning */
02876   UNUSED(hspi);
02877
02878   /* NOTE : This function should not be modified, when the callback is needed,
02879             the HAL_SPI_TxCpltCallback should be implemented in the user file
02880    */
02881 }
02882
02883 /**
02884   * @brief  Rx Transfer completed callback.
02885   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02886   *               the configuration information for SPI module.
02887   * @retval None
02888   */
02889 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02890 {
02891   /* Prevent unused argument(s) compilation warning */
02892   UNUSED(hspi);
02893
02894   /* NOTE : This function should not be modified, when the callback is needed,
02895             the HAL_SPI_RxCpltCallback should be implemented in the user file
02896    */
02897 }
02898
02899 /**
02900   * @brief  Tx and Rx Transfer completed callback.
02901   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02902   *               the configuration information for SPI module.
02903   * @retval None
02904   */
02905 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02906 {
02907   /* Prevent unused argument(s) compilation warning */
02908   UNUSED(hspi);
02909
02910   /* NOTE : This function should not be modified, when the callback is needed,
02911             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02912    */
02913 }
02914
02915 /**
02916   * @brief  Tx Half Transfer completed callback.
02917   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02918   *               the configuration information for SPI module.
02919   * @retval None
02920   */
02921 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02922 {
02923   /* Prevent unused argument(s) compilation warning */
02924   UNUSED(hspi);
02925
02926   /* NOTE : This function should not be modified, when the callback is needed,
02927             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02928    */
02929 }
02930
02931 /**
02932   * @brief  Rx Half Transfer completed callback.
02933   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02934   *               the configuration information for SPI module.
02935   * @retval None
02936   */
02937 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02938 {
02939   /* Prevent unused argument(s) compilation warning */
02940   UNUSED(hspi);
02941
02942   /* NOTE : This function should not be modified, when the callback is needed,
02943             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02944    */
02945 }
02946
02947 /**
02948   * @brief  Tx and Rx Half Transfer callback.
02949   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02950   *               the configuration information for SPI module.
02951   * @retval None
02952   */
02953 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02954 {
02955   /* Prevent unused argument(s) compilation warning */
02956   UNUSED(hspi);
02957
02958   /* NOTE : This function should not be modified, when the callback is needed,
02959             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02960    */
02961 }
02962
02963 /**
02964   * @brief  SPI error callback.
02965   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02966   *               the configuration information for SPI module.
02967   * @retval None
02968   */
02969 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02970 {
02971   /* Prevent unused argument(s) compilation warning */
02972   UNUSED(hspi);
02973
02974   /* NOTE : This function should not be modified, when the callback is needed,
02975             the HAL_SPI_ErrorCallback should be implemented in the user file
02976    */
02977   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02978             and user can use HAL_SPI_GetError() API to check the latest error occurred
02979    */
02980 }
02981
02982 /**
02983   * @brief  SPI Abort Complete callback.
02984   * @param  hspi SPI handle.
02985   * @retval None
02986   */
02987 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02988 {
02989   /* Prevent unused argument(s) compilation warning */
02990   UNUSED(hspi);
02991
02992   /* NOTE : This function should not be modified, when the callback is needed,
02993             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02994    */
02995 }
02996
02997 /**
02998   * @}
02999   */
03000
03001 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
03002   * @brief   SPI control functions
03003   *
03004 @verbatim
03005  ===============================================================================
03006                       ##### Peripheral State and Errors functions #####
03007  ===============================================================================
03008     [..]
03009     This subsection provides a set of functions allowing to control the SPI.
03010      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
03011      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
03012 @endverbatim
03013   * @{
03014   */
03015
03016 /**
03017   * @brief  Return the SPI handle state.
03018   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03019   *               the configuration information for SPI module.
03020   * @retval SPI state
03021   */
03022 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
03023 {
03024   /* Return SPI handle state */
03025   return hspi->State;
03026 }
03027
03028 /**
03029   * @brief  Return the SPI error code.
03030   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03031   *               the configuration information for SPI module.
03032   * @retval SPI error code in bitmap format
03033   */
03034 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
03035 {
03036   /* Return SPI ErrorCode */
03037   return hspi->ErrorCode;
03038 }
03039
03040 /**
03041   * @}
03042   */
03043
03044 /**
03045   * @}
03046   */
03047
03048 /** @addtogroup SPI_Private_Functions
03049   * @brief   Private functions
03050   * @{
03051   */
03052
03053 /**
03054   * @brief  DMA SPI transmit process complete callback.
03055   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03056   *               the configuration information for the specified DMA module.
03057   * @retval None
03058   */
03059 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03060 {
03061   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03062   uint32_t tickstart;
03063
03064   /* Init tickstart for timeout management*/
03065   tickstart = HAL_GetTick();
03066
03067   /* DMA Normal Mode */
03068   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03069   {
03070     /* Disable ERR interrupt */
03071     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03072
03073     /* Disable Tx DMA Request */
03074     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
03075
03076     /* Check the end of the transaction */
03077     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03078     {
03079       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03080     }
03081
03082     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
03083     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
03084     {
03085       __HAL_SPI_CLEAR_OVRFLAG(hspi);
03086     }
03087
03088     hspi->TxXferCount = 0U;
03089     hspi->State = HAL_SPI_STATE_READY;
03090
03091     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03092     {
03093       /* Call user error callback */
03094 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03095       hspi->ErrorCallback(hspi);
03096 #else
03097       HAL_SPI_ErrorCallback(hspi);
03098 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03099       return;
03100     }
03101   }
03102   /* Call user Tx complete callback */
03103 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03104   hspi->TxCpltCallback(hspi);
03105 #else
03106   HAL_SPI_TxCpltCallback(hspi);
03107 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03108 }
03109
03110 /**
03111   * @brief  DMA SPI receive process complete callback.
03112   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03113   *               the configuration information for the specified DMA module.
03114   * @retval None
03115   */
03116 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03117 {
03118   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03119   uint32_t tickstart;
03120 #if (USE_SPI_CRC != 0U)
03121   __IO uint32_t tmpreg = 0U;
03122   __IO uint8_t  *ptmpreg8;
03123   __IO uint8_t  tmpreg8 = 0;
03124 #endif /* USE_SPI_CRC */
03125
03126   /* Init tickstart for timeout management*/
03127   tickstart = HAL_GetTick();
03128
03129   /* DMA Normal Mode */
03130   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03131   {
03132     /* Disable ERR interrupt */
03133     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03134
03135 #if (USE_SPI_CRC != 0U)
03136     /* CRC handling */
03137     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03138     {
03139       /* Wait until RXNE flag */
03140       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03141       {
03142         /* Error on the CRC reception */
03143         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03144       }
03145       /* Read CRC */
03146       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
03147       {
03148         /* Read 16bit CRC */
03149         tmpreg = READ_REG(hspi->Instance->DR);
03150         /* To avoid GCC warning */
03151         UNUSED(tmpreg);
03152       }
03153       else
03154       {
03155         /* Initialize the 8bit temporary pointer */
03156         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03157         /* Read 8bit CRC */
03158         tmpreg8 = *ptmpreg8;
03159         /* To avoid GCC warning */
03160         UNUSED(tmpreg8);
03161
03162         if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
03163         {
03164           if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03165           {
03166             /* Error on the CRC reception */
03167             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03168           }
03169           /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
03170           tmpreg8 = *ptmpreg8;
03171           /* To avoid GCC warning */
03172           UNUSED(tmpreg8);
03173         }
03174       }
03175     }
03176 #endif /* USE_SPI_CRC */
03177
03178     /* Check if we are in Master RX 2 line mode */
03179     if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
03180     {
03181       /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
03182       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03183     }
03184     else
03185     {
03186       /* Normal case */
03187       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03188     }
03189
03190     /* Check the end of the transaction */
03191     if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03192     {
03193       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
03194     }
03195
03196     hspi->RxXferCount = 0U;
03197     hspi->State = HAL_SPI_STATE_READY;
03198
03199 #if (USE_SPI_CRC != 0U)
03200     /* Check if CRC error occurred */
03201     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03202     {
03203       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03204       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03205     }
03206 #endif /* USE_SPI_CRC */
03207
03208     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03209     {
03210       /* Call user error callback */
03211 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03212       hspi->ErrorCallback(hspi);
03213 #else
03214       HAL_SPI_ErrorCallback(hspi);
03215 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03216       return;
03217     }
03218   }
03219   /* Call user Rx complete callback */
03220 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03221   hspi->RxCpltCallback(hspi);
03222 #else
03223   HAL_SPI_RxCpltCallback(hspi);
03224 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03225 }
03226
03227 /**
03228   * @brief  DMA SPI transmit receive process complete callback.
03229   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03230   *               the configuration information for the specified DMA module.
03231   * @retval None
03232   */
03233 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03234 {
03235   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03236   uint32_t tickstart;
03237 #if (USE_SPI_CRC != 0U)
03238   __IO uint32_t tmpreg = 0U;
03239   __IO uint8_t  *ptmpreg8;
03240   __IO uint8_t  tmpreg8 = 0;
03241 #endif /* USE_SPI_CRC */
03242
03243   /* Init tickstart for timeout management*/
03244   tickstart = HAL_GetTick();
03245
03246   /* DMA Normal Mode */
03247   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03248   {
03249     /* Disable ERR interrupt */
03250     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03251
03252 #if (USE_SPI_CRC != 0U)
03253     /* CRC handling */
03254     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03255     {
03256       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
03257       {
03258         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
03259                                           tickstart) != HAL_OK)
03260         {
03261           /* Error on the CRC reception */
03262           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03263         }
03264         /* Initialize the 8bit temporary pointer */
03265         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03266         /* Read 8bit CRC */
03267         tmpreg8 = *ptmpreg8;
03268         /* To avoid GCC warning */
03269         UNUSED(tmpreg8);
03270       }
03271       else
03272       {
03273         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03274         {
03275           /* Error on the CRC reception */
03276           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03277         }
03278         /* Read CRC to Flush DR and RXNE flag */
03279         tmpreg = READ_REG(hspi->Instance->DR);
03280         /* To avoid GCC warning */
03281         UNUSED(tmpreg);
03282       }
03283     }
03284 #endif /* USE_SPI_CRC */
03285
03286     /* Check the end of the transaction */
03287     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03288     {
03289       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03290     }
03291
03292     /* Disable Rx/Tx DMA Request */
03293     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03294
03295     hspi->TxXferCount = 0U;
03296     hspi->RxXferCount = 0U;
03297     hspi->State = HAL_SPI_STATE_READY;
03298
03299 #if (USE_SPI_CRC != 0U)
03300     /* Check if CRC error occurred */
03301     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03302     {
03303       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03304       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03305     }
03306 #endif /* USE_SPI_CRC */
03307
03308     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03309     {
03310       /* Call user error callback */
03311 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03312       hspi->ErrorCallback(hspi);
03313 #else
03314       HAL_SPI_ErrorCallback(hspi);
03315 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03316       return;
03317     }
03318   }
03319   /* Call user TxRx complete callback */
03320 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03321   hspi->TxRxCpltCallback(hspi);
03322 #else
03323   HAL_SPI_TxRxCpltCallback(hspi);
03324 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03325 }
03326
03327 /**
03328   * @brief  DMA SPI half transmit process complete callback.
03329   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03330   *               the configuration information for the specified DMA module.
03331   * @retval None
03332   */
03333 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
03334 {
03335   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03336
03337   /* Call user Tx half complete callback */
03338 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03339   hspi->TxHalfCpltCallback(hspi);
03340 #else
03341   HAL_SPI_TxHalfCpltCallback(hspi);
03342 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03343 }
03344
03345 /**
03346   * @brief  DMA SPI half receive process complete callback
03347   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03348   *               the configuration information for the specified DMA module.
03349   * @retval None
03350   */
03351 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
03352 {
03353   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03354
03355   /* Call user Rx half complete callback */
03356 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03357   hspi->RxHalfCpltCallback(hspi);
03358 #else
03359   HAL_SPI_RxHalfCpltCallback(hspi);
03360 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03361 }
03362
03363 /**
03364   * @brief  DMA SPI half transmit receive process complete callback.
03365   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03366   *               the configuration information for the specified DMA module.
03367   * @retval None
03368   */
03369 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03370 {
03371   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03372
03373   /* Call user TxRx half complete callback */
03374 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03375   hspi->TxRxHalfCpltCallback(hspi);
03376 #else
03377   HAL_SPI_TxRxHalfCpltCallback(hspi);
03378 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03379 }
03380
03381 /**
03382   * @brief  DMA SPI communication error callback.
03383   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03384   *               the configuration information for the specified DMA module.
03385   * @retval None
03386   */
03387 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
03388 {
03389   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03390
03391   /* Stop the disable DMA transfer on SPI side */
03392   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03393
03394   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
03395   hspi->State = HAL_SPI_STATE_READY;
03396   /* Call user error callback */
03397 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03398   hspi->ErrorCallback(hspi);
03399 #else
03400   HAL_SPI_ErrorCallback(hspi);
03401 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03402 }
03403
03404 /**
03405   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
03406   *         (To be called at end of DMA Abort procedure following error occurrence).
03407   * @param  hdma DMA handle.
03408   * @retval None
03409   */
03410 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03411 {
03412   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03413   hspi->RxXferCount = 0U;
03414   hspi->TxXferCount = 0U;
03415
03416   /* Call user error callback */
03417 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03418   hspi->ErrorCallback(hspi);
03419 #else
03420   HAL_SPI_ErrorCallback(hspi);
03421 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03422 }
03423
03424 /**
03425   * @brief  DMA SPI Tx communication abort callback, when initiated by user
03426   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03427   * @note   When this callback is executed, User Abort complete call back is called only if no
03428   *         Abort still ongoing for Rx DMA Handle.
03429   * @param  hdma DMA handle.
03430   * @retval None
03431   */
03432 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03433 {
03434   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03435
03436   hspi->hdmatx->XferAbortCallback = NULL;
03437
03438   /* Disable Tx DMA Request */
03439   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
03440
03441   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03442   {
03443     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03444   }
03445
03446   /* Disable SPI Peripheral */
03447   __HAL_SPI_DISABLE(hspi);
03448
03449   /* Empty the FRLVL fifo */
03450   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03451   {
03452     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03453   }
03454
03455   /* Check if an Abort process is still ongoing */
03456   if (hspi->hdmarx != NULL)
03457   {
03458     if (hspi->hdmarx->XferAbortCallback != NULL)
03459     {
03460       return;
03461     }
03462   }
03463
03464   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03465   hspi->RxXferCount = 0U;
03466   hspi->TxXferCount = 0U;
03467
03468   /* Check no error during Abort procedure */
03469   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03470   {
03471     /* Reset errorCode */
03472     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03473   }
03474
03475   /* Clear the Error flags in the SR register */
03476   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03477   __HAL_SPI_CLEAR_FREFLAG(hspi);
03478
03479   /* Restore hspi->State to Ready */
03480   hspi->State  = HAL_SPI_STATE_READY;
03481
03482   /* Call user Abort complete callback */
03483 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03484   hspi->AbortCpltCallback(hspi);
03485 #else
03486   HAL_SPI_AbortCpltCallback(hspi);
03487 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03488 }
03489
03490 /**
03491   * @brief  DMA SPI Rx communication abort callback, when initiated by user
03492   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03493   * @note   When this callback is executed, User Abort complete call back is called only if no
03494   *         Abort still ongoing for Tx DMA Handle.
03495   * @param  hdma DMA handle.
03496   * @retval None
03497   */
03498 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03499 {
03500   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03501
03502   /* Disable SPI Peripheral */
03503   __HAL_SPI_DISABLE(hspi);
03504
03505   hspi->hdmarx->XferAbortCallback = NULL;
03506
03507   /* Disable Rx DMA Request */
03508   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03509
03510   /* Control the BSY flag */
03511   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03512   {
03513     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03514   }
03515
03516   /* Empty the FRLVL fifo */
03517   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03518   {
03519     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03520   }
03521
03522   /* Check if an Abort process is still ongoing */
03523   if (hspi->hdmatx != NULL)
03524   {
03525     if (hspi->hdmatx->XferAbortCallback != NULL)
03526     {
03527       return;
03528     }
03529   }
03530
03531   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03532   hspi->RxXferCount = 0U;
03533   hspi->TxXferCount = 0U;
03534
03535   /* Check no error during Abort procedure */
03536   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03537   {
03538     /* Reset errorCode */
03539     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03540   }
03541
03542   /* Clear the Error flags in the SR register */
03543   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03544   __HAL_SPI_CLEAR_FREFLAG(hspi);
03545
03546   /* Restore hspi->State to Ready */
03547   hspi->State  = HAL_SPI_STATE_READY;
03548
03549   /* Call user Abort complete callback */
03550 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03551   hspi->AbortCpltCallback(hspi);
03552 #else
03553   HAL_SPI_AbortCpltCallback(hspi);
03554 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03555 }
03556
03557 /**
03558   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03559   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03560   *               the configuration information for SPI module.
03561   * @retval None
03562   */
03563 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03564 {
03565   /* Receive data in packing mode */
03566   if (hspi->RxXferCount > 1U)
03567   {
03568     *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03569     hspi->pRxBuffPtr += sizeof(uint16_t);
03570     hspi->RxXferCount -= 2U;
03571     if (hspi->RxXferCount == 1U)
03572     {
03573       /* Set RX Fifo threshold according the reception data length: 8bit */
03574       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03575     }
03576   }
03577   /* Receive data in 8 Bit mode */
03578   else
03579   {
03580     *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
03581     hspi->pRxBuffPtr++;
03582     hspi->RxXferCount--;
03583   }
03584
03585   /* Check end of the reception */
03586   if (hspi->RxXferCount == 0U)
03587   {
03588 #if (USE_SPI_CRC != 0U)
03589     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03590     {
03591       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03592       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
03593       return;
03594     }
03595 #endif /* USE_SPI_CRC */
03596
03597     /* Disable RXNE  and ERR interrupt */
03598     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03599
03600     if (hspi->TxXferCount == 0U)
03601     {
03602       SPI_CloseRxTx_ISR(hspi);
03603     }
03604   }
03605 }
03606
03607 #if (USE_SPI_CRC != 0U)
03608 /**
03609   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03610   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03611   *               the configuration information for SPI module.
03612   * @retval None
03613   */
03614 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03615 {
03616   __IO uint8_t  *ptmpreg8;
03617   __IO uint8_t  tmpreg8 = 0;
03618
03619   /* Initialize the 8bit temporary pointer */
03620   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03621   /* Read 8bit CRC to flush Data Register */
03622   tmpreg8 = *ptmpreg8;
03623   /* To avoid GCC warning */
03624   UNUSED(tmpreg8);
03625
03626   hspi->CRCSize--;
03627
03628   /* Check end of the reception */
03629   if (hspi->CRCSize == 0U)
03630   {
03631     /* Disable RXNE and ERR interrupt */
03632     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03633
03634     if (hspi->TxXferCount == 0U)
03635     {
03636       SPI_CloseRxTx_ISR(hspi);
03637     }
03638   }
03639 }
03640 #endif /* USE_SPI_CRC */
03641
03642 /**
03643   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
03644   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03645   *               the configuration information for SPI module.
03646   * @retval None
03647   */
03648 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03649 {
03650   /* Transmit data in packing Bit mode */
03651   if (hspi->TxXferCount >= 2U)
03652   {
03653     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03654     hspi->pTxBuffPtr += sizeof(uint16_t);
03655     hspi->TxXferCount -= 2U;
03656   }
03657   /* Transmit data in 8 Bit mode */
03658   else
03659   {
03660     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03661     hspi->pTxBuffPtr++;
03662     hspi->TxXferCount--;
03663   }
03664
03665   /* Check the end of the transmission */
03666   if (hspi->TxXferCount == 0U)
03667   {
03668 #if (USE_SPI_CRC != 0U)
03669     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03670     {
03671       /* Set CRC Next Bit to send CRC */
03672       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03673       /* Disable TXE interrupt */
03674       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03675       return;
03676     }
03677 #endif /* USE_SPI_CRC */
03678
03679     /* Disable TXE interrupt */
03680     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03681
03682     if (hspi->RxXferCount == 0U)
03683     {
03684       SPI_CloseRxTx_ISR(hspi);
03685     }
03686   }
03687 }
03688
03689 /**
03690   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
03691   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03692   *               the configuration information for SPI module.
03693   * @retval None
03694   */
03695 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03696 {
03697   /* Receive data in 16 Bit mode */
03698   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03699   hspi->pRxBuffPtr += sizeof(uint16_t);
03700   hspi->RxXferCount--;
03701
03702   if (hspi->RxXferCount == 0U)
03703   {
03704 #if (USE_SPI_CRC != 0U)
03705     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03706     {
03707       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
03708       return;
03709     }
03710 #endif /* USE_SPI_CRC */
03711
03712     /* Disable RXNE interrupt */
03713     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03714
03715     if (hspi->TxXferCount == 0U)
03716     {
03717       SPI_CloseRxTx_ISR(hspi);
03718     }
03719   }
03720 }
03721
03722 #if (USE_SPI_CRC != 0U)
03723 /**
03724   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
03725   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03726   *               the configuration information for SPI module.
03727   * @retval None
03728   */
03729 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03730 {
03731   __IO uint32_t tmpreg = 0U;
03732
03733   /* Read 16bit CRC to flush Data Register */
03734   tmpreg = READ_REG(hspi->Instance->DR);
03735   /* To avoid GCC warning */
03736   UNUSED(tmpreg);
03737
03738   /* Disable RXNE interrupt */
03739   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03740
03741   SPI_CloseRxTx_ISR(hspi);
03742 }
03743 #endif /* USE_SPI_CRC */
03744
03745 /**
03746   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
03747   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03748   *               the configuration information for SPI module.
03749   * @retval None
03750   */
03751 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03752 {
03753   /* Transmit data in 16 Bit mode */
03754   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03755   hspi->pTxBuffPtr += sizeof(uint16_t);
03756   hspi->TxXferCount--;
03757
03758   /* Enable CRC Transmission */
03759   if (hspi->TxXferCount == 0U)
03760   {
03761 #if (USE_SPI_CRC != 0U)
03762     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03763     {
03764       /* Set CRC Next Bit to send CRC */
03765       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03766       /* Disable TXE interrupt */
03767       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03768       return;
03769     }
03770 #endif /* USE_SPI_CRC */
03771
03772     /* Disable TXE interrupt */
03773     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03774
03775     if (hspi->RxXferCount == 0U)
03776     {
03777       SPI_CloseRxTx_ISR(hspi);
03778     }
03779   }
03780 }
03781
03782 #if (USE_SPI_CRC != 0U)
03783 /**
03784   * @brief  Manage the CRC 8-bit receive in Interrupt context.
03785   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03786   *               the configuration information for SPI module.
03787   * @retval None
03788   */
03789 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03790 {
03791   __IO uint8_t  *ptmpreg8;
03792   __IO uint8_t  tmpreg8 = 0;
03793
03794   /* Initialize the 8bit temporary pointer */
03795   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03796   /* Read 8bit CRC to flush Data Register */
03797   tmpreg8 = *ptmpreg8;
03798   /* To avoid GCC warning */
03799   UNUSED(tmpreg8);
03800
03801   hspi->CRCSize--;
03802
03803   if (hspi->CRCSize == 0U)
03804   {
03805     SPI_CloseRx_ISR(hspi);
03806   }
03807 }
03808 #endif /* USE_SPI_CRC */
03809
03810 /**
03811   * @brief  Manage the receive 8-bit in Interrupt context.
03812   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03813   *               the configuration information for SPI module.
03814   * @retval None
03815   */
03816 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03817 {
03818   *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
03819   hspi->pRxBuffPtr++;
03820   hspi->RxXferCount--;
03821
03822 #if (USE_SPI_CRC != 0U)
03823   /* Enable CRC Transmission */
03824   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03825   {
03826     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03827   }
03828 #endif /* USE_SPI_CRC */
03829
03830   if (hspi->RxXferCount == 0U)
03831   {
03832 #if (USE_SPI_CRC != 0U)
03833     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03834     {
03835       hspi->RxISR =  SPI_RxISR_8BITCRC;
03836       return;
03837     }
03838 #endif /* USE_SPI_CRC */
03839     SPI_CloseRx_ISR(hspi);
03840   }
03841 }
03842
03843 #if (USE_SPI_CRC != 0U)
03844 /**
03845   * @brief  Manage the CRC 16-bit receive in Interrupt context.
03846   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03847   *               the configuration information for SPI module.
03848   * @retval None
03849   */
03850 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03851 {
03852   __IO uint32_t tmpreg = 0U;
03853
03854   /* Read 16bit CRC to flush Data Register */
03855   tmpreg = READ_REG(hspi->Instance->DR);
03856   /* To avoid GCC warning */
03857   UNUSED(tmpreg);
03858
03859   /* Disable RXNE and ERR interrupt */
03860   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03861
03862   SPI_CloseRx_ISR(hspi);
03863 }
03864 #endif /* USE_SPI_CRC */
03865
03866 /**
03867   * @brief  Manage the 16-bit receive in Interrupt context.
03868   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03869   *               the configuration information for SPI module.
03870   * @retval None
03871   */
03872 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03873 {
03874   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03875   hspi->pRxBuffPtr += sizeof(uint16_t);
03876   hspi->RxXferCount--;
03877
03878 #if (USE_SPI_CRC != 0U)
03879   /* Enable CRC Transmission */
03880   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03881   {
03882     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03883   }
03884 #endif /* USE_SPI_CRC */
03885
03886   if (hspi->RxXferCount == 0U)
03887   {
03888 #if (USE_SPI_CRC != 0U)
03889     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03890     {
03891       hspi->RxISR = SPI_RxISR_16BITCRC;
03892       return;
03893     }
03894 #endif /* USE_SPI_CRC */
03895     SPI_CloseRx_ISR(hspi);
03896   }
03897 }
03898
03899 /**
03900   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03901   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03902   *               the configuration information for SPI module.
03903   * @retval None
03904   */
03905 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03906 {
03907   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03908   hspi->pTxBuffPtr++;
03909   hspi->TxXferCount--;
03910
03911   if (hspi->TxXferCount == 0U)
03912   {
03913 #if (USE_SPI_CRC != 0U)
03914     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03915     {
03916       /* Enable CRC Transmission */
03917       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03918     }
03919 #endif /* USE_SPI_CRC */
03920     SPI_CloseTx_ISR(hspi);
03921   }
03922 }
03923
03924 /**
03925   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03926   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03927   *               the configuration information for SPI module.
03928   * @retval None
03929   */
03930 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03931 {
03932   /* Transmit data in 16 Bit mode */
03933   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03934   hspi->pTxBuffPtr += sizeof(uint16_t);
03935   hspi->TxXferCount--;
03936
03937   if (hspi->TxXferCount == 0U)
03938   {
03939 #if (USE_SPI_CRC != 0U)
03940     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03941     {
03942       /* Enable CRC Transmission */
03943       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03944     }
03945 #endif /* USE_SPI_CRC */
03946     SPI_CloseTx_ISR(hspi);
03947   }
03948 }
03949
03950 /**
03951   * @brief  Handle SPI Communication Timeout.
03952   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03953   *              the configuration information for SPI module.
03954   * @param  Flag SPI flag to check
03955   * @param  State flag state to check
03956   * @param  Timeout Timeout duration
03957   * @param  Tickstart tick start value
03958   * @retval HAL status
03959   */
03960 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
03961                                                        uint32_t Timeout, uint32_t Tickstart)
03962 {
03963   __IO uint32_t count;
03964   uint32_t tmp_timeout;
03965   uint32_t tmp_tickstart;
03966
03967   /* Adjust Timeout value  in case of end of transfer */
03968   tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
03969   tmp_tickstart = HAL_GetTick();
03970
03971   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
03972   count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
03973
03974   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
03975   {
03976     if (Timeout != HAL_MAX_DELAY)
03977     {
03978       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
03979       {
03980         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03981            on both master and slave sides in order to resynchronize the master
03982            and slave for their respective CRC calculation */
03983
03984         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03985         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03986
03987         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03988                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03989         {
03990           /* Disable SPI peripheral */
03991           __HAL_SPI_DISABLE(hspi);
03992         }
03993
03994         /* Reset CRC Calculation */
03995         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03996         {
03997           SPI_RESET_CRC(hspi);
03998         }
03999
04000         hspi->State = HAL_SPI_STATE_READY;
04001
04002         /* Process Unlocked */
04003         __HAL_UNLOCK(hspi);
04004
04005         return HAL_TIMEOUT;
04006       }
04007       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
04008       if (count == 0U)
04009       {
04010         tmp_timeout = 0U;
04011       }
04012       count--;
04013     }
04014   }
04015
04016   return HAL_OK;
04017 }
04018
04019 /**
04020   * @brief  Handle SPI FIFO Communication Timeout.
04021   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04022   *              the configuration information for SPI module.
04023   * @param  Fifo Fifo to check
04024   * @param  State Fifo state to check
04025   * @param  Timeout Timeout duration
04026   * @param  Tickstart tick start value
04027   * @retval HAL status
04028   */
04029 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
04030                                                        uint32_t Timeout, uint32_t Tickstart)
04031 {
04032   __IO uint32_t count;
04033   uint32_t tmp_timeout;
04034   uint32_t tmp_tickstart;
04035   __IO uint8_t  *ptmpreg8;
04036   __IO uint8_t  tmpreg8 = 0;
04037
04038   /* Adjust Timeout value  in case of end of transfer */
04039   tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
04040   tmp_tickstart = HAL_GetTick();
04041
04042   /* Initialize the 8bit temporary pointer */
04043   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
04044
04045   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
04046   count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
04047
04048   while ((hspi->Instance->SR & Fifo) != State)
04049   {
04050     if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
04051     {
04052       /* Flush Data Register by a blank read */
04053       tmpreg8 = *ptmpreg8;
04054       /* To avoid GCC warning */
04055       UNUSED(tmpreg8);
04056     }
04057
04058     if (Timeout != HAL_MAX_DELAY)
04059     {
04060       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
04061       {
04062         /* Disable the SPI and reset the CRC: the CRC value should be cleared
04063            on both master and slave sides in order to resynchronize the master
04064            and slave for their respective CRC calculation */
04065
04066         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
04067         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
04068
04069         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
04070                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
04071         {
04072           /* Disable SPI peripheral */
04073           __HAL_SPI_DISABLE(hspi);
04074         }
04075
04076         /* Reset CRC Calculation */
04077         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
04078         {
04079           SPI_RESET_CRC(hspi);
04080         }
04081
04082         hspi->State = HAL_SPI_STATE_READY;
04083
04084         /* Process Unlocked */
04085         __HAL_UNLOCK(hspi);
04086
04087         return HAL_TIMEOUT;
04088       }
04089       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
04090       if (count == 0U)
04091       {
04092         tmp_timeout = 0U;
04093       }
04094       count--;
04095     }
04096   }
04097
04098   return HAL_OK;
04099 }
04100
04101 /**
04102   * @brief  Handle the check of the RX transaction complete.
04103   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04104   *               the configuration information for SPI module.
04105   * @param  Timeout Timeout duration
04106   * @param  Tickstart tick start value
04107   * @retval HAL status
04108   */
04109 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
04110 {
04111   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
04112                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
04113   {
04114     /* Disable SPI peripheral */
04115     __HAL_SPI_DISABLE(hspi);
04116   }
04117
04118   /* Control the BSY flag */
04119   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
04120   {
04121     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04122     return HAL_TIMEOUT;
04123   }
04124
04125   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
04126                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
04127   {
04128     /* Empty the FRLVL fifo */
04129     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04130     {
04131       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04132       return HAL_TIMEOUT;
04133     }
04134   }
04135   return HAL_OK;
04136 }
04137
04138 /**
04139   * @brief  Handle the check of the RXTX or TX transaction complete.
04140   * @param  hspi SPI handle
04141   * @param  Timeout Timeout duration
04142   * @param  Tickstart tick start value
04143   * @retval HAL status
04144   */
04145 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
04146 {
04147   /* Control if the TX fifo is empty */
04148   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04149   {
04150     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04151     return HAL_TIMEOUT;
04152   }
04153
04154   /* Control the BSY flag */
04155   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
04156   {
04157     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04158     return HAL_TIMEOUT;
04159   }
04160
04161   /* Control if the RX fifo is empty */
04162   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04163   {
04164     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04165     return HAL_TIMEOUT;
04166   }
04167
04168   return HAL_OK;
04169 }
04170
04171 /**
04172   * @brief  Handle the end of the RXTX transaction.
04173   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04174   *               the configuration information for SPI module.
04175   * @retval None
04176   */
04177 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
04178 {
04179   uint32_t tickstart;
04180
04181   /* Init tickstart for timeout management */
04182   tickstart = HAL_GetTick();
04183
04184   /* Disable ERR interrupt */
04185   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
04186
04187   /* Check the end of the transaction */
04188   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
04189   {
04190     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04191   }
04192
04193 #if (USE_SPI_CRC != 0U)
04194   /* Check if CRC error occurred */
04195   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
04196   {
04197     hspi->State = HAL_SPI_STATE_READY;
04198     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
04199     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
04200     /* Call user error callback */
04201 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04202     hspi->ErrorCallback(hspi);
04203 #else
04204     HAL_SPI_ErrorCallback(hspi);
04205 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04206   }
04207   else
04208   {
04209 #endif /* USE_SPI_CRC */
04210     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04211     {
04212       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
04213       {
04214         hspi->State = HAL_SPI_STATE_READY;
04215         /* Call user Rx complete callback */
04216 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04217         hspi->RxCpltCallback(hspi);
04218 #else
04219         HAL_SPI_RxCpltCallback(hspi);
04220 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04221       }
04222       else
04223       {
04224         hspi->State = HAL_SPI_STATE_READY;
04225         /* Call user TxRx complete callback */
04226 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04227         hspi->TxRxCpltCallback(hspi);
04228 #else
04229         HAL_SPI_TxRxCpltCallback(hspi);
04230 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04231       }
04232     }
04233     else
04234     {
04235       hspi->State = HAL_SPI_STATE_READY;
04236       /* Call user error callback */
04237 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04238       hspi->ErrorCallback(hspi);
04239 #else
04240       HAL_SPI_ErrorCallback(hspi);
04241 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04242     }
04243 #if (USE_SPI_CRC != 0U)
04244   }
04245 #endif /* USE_SPI_CRC */
04246 }
04247
04248 /**
04249   * @brief  Handle the end of the RX transaction.
04250   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04251   *               the configuration information for SPI module.
04252   * @retval None
04253   */
04254 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
04255 {
04256   /* Disable RXNE and ERR interrupt */
04257   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
04258
04259   /* Check the end of the transaction */
04260   if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04261   {
04262     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04263   }
04264   hspi->State = HAL_SPI_STATE_READY;
04265
04266 #if (USE_SPI_CRC != 0U)
04267   /* Check if CRC error occurred */
04268   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
04269   {
04270     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
04271     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
04272     /* Call user error callback */
04273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04274     hspi->ErrorCallback(hspi);
04275 #else
04276     HAL_SPI_ErrorCallback(hspi);
04277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04278   }
04279   else
04280   {
04281 #endif /* USE_SPI_CRC */
04282     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04283     {
04284       /* Call user Rx complete callback */
04285 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04286       hspi->RxCpltCallback(hspi);
04287 #else
04288       HAL_SPI_RxCpltCallback(hspi);
04289 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04290     }
04291     else
04292     {
04293       /* Call user error callback */
04294 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04295       hspi->ErrorCallback(hspi);
04296 #else
04297       HAL_SPI_ErrorCallback(hspi);
04298 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04299     }
04300 #if (USE_SPI_CRC != 0U)
04301   }
04302 #endif /* USE_SPI_CRC */
04303 }
04304
04305 /**
04306   * @brief  Handle the end of the TX transaction.
04307   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04308   *               the configuration information for SPI module.
04309   * @retval None
04310   */
04311 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
04312 {
04313   uint32_t tickstart;
04314
04315   /* Init tickstart for timeout management*/
04316   tickstart = HAL_GetTick();
04317
04318   /* Disable TXE and ERR interrupt */
04319   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
04320
04321   /* Check the end of the transaction */
04322   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
04323   {
04324     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04325   }
04326
04327   /* Clear overrun flag in 2 Lines communication mode because received is not read */
04328   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
04329   {
04330     __HAL_SPI_CLEAR_OVRFLAG(hspi);
04331   }
04332
04333   hspi->State = HAL_SPI_STATE_READY;
04334   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
04335   {
04336     /* Call user error callback */
04337 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04338     hspi->ErrorCallback(hspi);
04339 #else
04340     HAL_SPI_ErrorCallback(hspi);
04341 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04342   }
04343   else
04344   {
04345     /* Call user Rx complete callback */
04346 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04347     hspi->TxCpltCallback(hspi);
04348 #else
04349     HAL_SPI_TxCpltCallback(hspi);
04350 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04351   }
04352 }
04353
04354 /**
04355   * @brief  Handle abort a Rx transaction.
04356   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04357   *               the configuration information for SPI module.
04358   * @retval None
04359   */
04360 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
04361 {
04362   __IO uint32_t count;
04363
04364   /* Disable SPI Peripheral */
04365   __HAL_SPI_DISABLE(hspi);
04366
04367   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04368
04369   /* Disable RXNEIE interrupt */
04370   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04371
04372   /* Check RXNEIE is disabled */
04373   do
04374   {
04375     if (count == 0U)
04376     {
04377       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04378       break;
04379     }
04380     count--;
04381   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04382
04383   /* Control the BSY flag */
04384   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04385   {
04386     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04387   }
04388
04389   /* Empty the FRLVL fifo */
04390   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04391   {
04392     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04393   }
04394
04395   hspi->State = HAL_SPI_STATE_ABORT;
04396 }
04397
04398 /**
04399   * @brief  Handle abort a Tx or Rx/Tx transaction.
04400   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04401   *               the configuration information for SPI module.
04402   * @retval None
04403   */
04404 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
04405 {
04406   __IO uint32_t count;
04407
04408   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04409
04410   /* Disable TXEIE interrupt */
04411   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
04412
04413   /* Check TXEIE is disabled */
04414   do
04415   {
04416     if (count == 0U)
04417     {
04418       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04419       break;
04420     }
04421     count--;
04422   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
04423
04424   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04425   {
04426     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04427   }
04428
04429   /* Disable SPI Peripheral */
04430   __HAL_SPI_DISABLE(hspi);
04431
04432   /* Empty the FRLVL fifo */
04433   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04434   {
04435     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04436   }
04437
04438   /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
04439   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
04440   {
04441     /* Disable RXNEIE interrupt */
04442     CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04443
04444     /* Check RXNEIE is disabled */
04445     do
04446     {
04447       if (count == 0U)
04448       {
04449         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04450         break;
04451       }
04452       count--;
04453     } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04454
04455     /* Control the BSY flag */
04456     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04457     {
04458       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04459     }
04460
04461     /* Empty the FRLVL fifo */
04462     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04463     {
04464       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04465     }
04466   }
04467   hspi->State = HAL_SPI_STATE_ABORT;
04468 }
04469
04470 /**
04471   * @}
04472   */
04473
04474 #endif /* HAL_SPI_MODULE_ENABLED */
04475
04476 /**
04477   * @}
04478   */
04479
04480 /**
04481   * @}
04482   */
04483
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_spi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SPI_H
00021 #define STM32G4xx_HAL_SPI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SPI
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SPI_Exported_Types SPI Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  SPI Configuration Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00049                                      This parameter can be a value of @ref SPI_Mode */
00050
00051   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00052                                      This parameter can be a value of @ref SPI_Direction */
00053
00054   uint32_t DataSize;            /*!< Specifies the SPI data size.
00055                                      This parameter can be a value of @ref SPI_Data_Size */
00056
00057   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00058                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00059
00060   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00061                                      This parameter can be a value of @ref SPI_Clock_Phase */
00062
00063   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00064                                      hardware (NSS pin) or by software using the SSI bit.
00065                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00066
00067   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00068                                      used to configure the transmit and receive SCK clock.
00069                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00070                                      @note The communication clock is derived from the master
00071                                      clock. The slave clock does not need to be set. */
00072
00073   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00074                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00075
00076   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
00077                                      This parameter can be a value of @ref SPI_TI_mode */
00078
00079   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00080                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00081
00082   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00083                                      This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
00084
00085   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00086                                      CRC Length is only used with Data8 and Data16, not other data size
00087                                      This parameter can be a value of @ref SPI_CRC_length */
00088
00089   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00090                                      This parameter can be a value of @ref SPI_NSSP_Mode
00091                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00092                                      it takes effect only if the SPI interface is configured as Motorola SPI
00093                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00094                                      CPOL setting is ignored).. */
00095 } SPI_InitTypeDef;
00096
00097 /**
00098   * @brief  HAL SPI State structure definition
00099   */
00100 typedef enum
00101 {
00102   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00103   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00104   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00105   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00106   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00107   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00108   HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
00109   HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
00110 } HAL_SPI_StateTypeDef;
00111
00112 /**
00113   * @brief  SPI handle Structure definition
00114   */
00115 typedef struct __SPI_HandleTypeDef
00116 {
00117   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
00118
00119   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
00120
00121   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
00122
00123   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
00124
00125   __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
00126
00127   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
00128
00129   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
00130
00131   __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
00132
00133   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
00134
00135   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
00136
00137   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
00138
00139   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
00140
00141   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
00142
00143   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
00144
00145   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
00146
00147   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
00148
00149 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00150   void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
00151   void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
00152   void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
00153   void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
00154   void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
00155   void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
00156   void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
00157   void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
00158   void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
00159   void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
00160
00161 #endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
00162 } SPI_HandleTypeDef;
00163
00164 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00165 /**
00166   * @brief  HAL SPI Callback ID enumeration definition
00167   */
00168 typedef enum
00169 {
00170   HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
00171   HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
00172   HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
00173   HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
00174   HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
00175   HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
00176   HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
00177   HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
00178   HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
00179   HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
00180
00181 } HAL_SPI_CallbackIDTypeDef;
00182
00183 /**
00184   * @brief  HAL SPI Callback pointer definition
00185   */
00186 typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
00187
00188 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00189 /**
00190   * @}
00191   */
00192
00193 /* Exported constants --------------------------------------------------------*/
00194 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00195   * @{
00196   */
00197
00198 /** @defgroup SPI_Error_Code SPI Error Code
00199   * @{
00200   */
00201 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
00202 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
00203 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
00204 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
00205 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
00206 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
00207 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00208 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
00209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00210 #define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
00211 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup SPI_Mode SPI Mode
00217   * @{
00218   */
00219 #define SPI_MODE_SLAVE                  (0x00000000U)
00220 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_Direction SPI Direction Mode
00226   * @{
00227   */
00228 #define SPI_DIRECTION_2LINES            (0x00000000U)
00229 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00230 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_Data_Size SPI Data Size
00236   * @{
00237   */
00238 #define SPI_DATASIZE_4BIT               (0x00000300U)
00239 #define SPI_DATASIZE_5BIT               (0x00000400U)
00240 #define SPI_DATASIZE_6BIT               (0x00000500U)
00241 #define SPI_DATASIZE_7BIT               (0x00000600U)
00242 #define SPI_DATASIZE_8BIT               (0x00000700U)
00243 #define SPI_DATASIZE_9BIT               (0x00000800U)
00244 #define SPI_DATASIZE_10BIT              (0x00000900U)
00245 #define SPI_DATASIZE_11BIT              (0x00000A00U)
00246 #define SPI_DATASIZE_12BIT              (0x00000B00U)
00247 #define SPI_DATASIZE_13BIT              (0x00000C00U)
00248 #define SPI_DATASIZE_14BIT              (0x00000D00U)
00249 #define SPI_DATASIZE_15BIT              (0x00000E00U)
00250 #define SPI_DATASIZE_16BIT              (0x00000F00U)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00256   * @{
00257   */
00258 #define SPI_POLARITY_LOW                (0x00000000U)
00259 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00265   * @{
00266   */
00267 #define SPI_PHASE_1EDGE                 (0x00000000U)
00268 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00274   * @{
00275   */
00276 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00277 #define SPI_NSS_HARD_INPUT              (0x00000000U)
00278 #define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00284   * @{
00285   */
00286 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00287 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00293   * @{
00294   */
00295 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
00296 #define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
00297 #define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
00298 #define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
00299 #define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
00300 #define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
00301 #define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
00302 #define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00308   * @{
00309   */
00310 #define SPI_FIRSTBIT_MSB                (0x00000000U)
00311 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup SPI_TI_mode SPI TI Mode
00317   * @{
00318   */
00319 #define SPI_TIMODE_DISABLE              (0x00000000U)
00320 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00326   * @{
00327   */
00328 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
00329 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup SPI_CRC_length SPI CRC Length
00335   * @{
00336   * This parameter can be one of the following values:
00337   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00338   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00339   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00340   */
00341 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
00342 #define SPI_CRC_LENGTH_8BIT             (0x00000001U)
00343 #define SPI_CRC_LENGTH_16BIT            (0x00000002U)
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00349   * @{
00350   * This parameter can be one of the following values:
00351   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00352   *          RXNE event is generated if the FIFO
00353   *          level is greater or equal to 1/4(8-bits).
00354   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00355   *          level is greater or equal to 1/2(16 bits). */
00356 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00357 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00358 #define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00364   * @{
00365   */
00366 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00367 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00368 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup SPI_Flags_definition SPI Flags Definition
00374   * @{
00375   */
00376 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
00377 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
00378 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
00379 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
00380 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
00381 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
00382 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00383 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
00384 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
00385 #define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
00386                                          | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00392   * @{
00393   */
00394 #define SPI_FTLVL_EMPTY                 (0x00000000U)
00395 #define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
00396 #define SPI_FTLVL_HALF_FULL             (0x00001000U)
00397 #define SPI_FTLVL_FULL                  (0x00001800U)
00398
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00404   * @{
00405   */
00406 #define SPI_FRLVL_EMPTY                 (0x00000000U)
00407 #define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
00408 #define SPI_FRLVL_HALF_FULL             (0x00000400U)
00409 #define SPI_FRLVL_FULL                  (0x00000600U)
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /* Exported macros -----------------------------------------------------------*/
00419 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00420   * @{
00421   */
00422
00423 /** @brief  Reset SPI handle state.
00424   * @param  __HANDLE__ specifies the SPI Handle.
00425   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00426   * @retval None
00427   */
00428 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00429 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00430                                                                     (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
00431                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00432                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00433                                                                   } while(0)
00434 #else
00435 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00436 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00437
00438 /** @brief  Enable the specified SPI interrupts.
00439   * @param  __HANDLE__ specifies the SPI Handle.
00440   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00441   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00442   *         This parameter can be one of the following values:
00443   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00444   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00445   *            @arg SPI_IT_ERR: Error interrupt enable
00446   * @retval None
00447   */
00448 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00449
00450 /** @brief  Disable the specified SPI interrupts.
00451   * @param  __HANDLE__ specifies the SPI handle.
00452   *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
00453   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00454   *         This parameter can be one of the following values:
00455   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00456   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00457   *            @arg SPI_IT_ERR: Error interrupt enable
00458   * @retval None
00459   */
00460 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00461
00462 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00463   * @param  __HANDLE__ specifies the SPI Handle.
00464   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00465   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00466   *          This parameter can be one of the following values:
00467   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00468   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00469   *            @arg SPI_IT_ERR: Error interrupt enable
00470   * @retval The new state of __IT__ (TRUE or FALSE).
00471   */
00472 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
00473                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00474
00475 /** @brief  Check whether the specified SPI flag is set or not.
00476   * @param  __HANDLE__ specifies the SPI Handle.
00477   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00478   * @param  __FLAG__ specifies the flag to check.
00479   *         This parameter can be one of the following values:
00480   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00481   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00482   *            @arg SPI_FLAG_CRCERR: CRC error flag
00483   *            @arg SPI_FLAG_MODF: Mode fault flag
00484   *            @arg SPI_FLAG_OVR: Overrun flag
00485   *            @arg SPI_FLAG_BSY: Busy flag
00486   *            @arg SPI_FLAG_FRE: Frame format error flag
00487   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00488   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00489   * @retval The new state of __FLAG__ (TRUE or FALSE).
00490   */
00491 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00492
00493 /** @brief  Clear the SPI CRCERR pending flag.
00494   * @param  __HANDLE__ specifies the SPI Handle.
00495   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00496   * @retval None
00497   */
00498 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00499
00500 /** @brief  Clear the SPI MODF pending flag.
00501   * @param  __HANDLE__ specifies the SPI Handle.
00502   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00503   * @retval None
00504   */
00505 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
00506   do{                                                    \
00507     __IO uint32_t tmpreg_modf = 0x00U;                   \
00508     tmpreg_modf = (__HANDLE__)->Instance->SR;            \
00509     CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
00510     UNUSED(tmpreg_modf);                                 \
00511   } while(0U)
00512
00513 /** @brief  Clear the SPI OVR pending flag.
00514   * @param  __HANDLE__ specifies the SPI Handle.
00515   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00516   * @retval None
00517   */
00518 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00519   do{                                              \
00520     __IO uint32_t tmpreg_ovr = 0x00U;              \
00521     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
00522     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
00523     UNUSED(tmpreg_ovr);                            \
00524   } while(0U)
00525
00526 /** @brief  Clear the SPI FRE pending flag.
00527   * @param  __HANDLE__ specifies the SPI Handle.
00528   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00529   * @retval None
00530   */
00531 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
00532   do{                                              \
00533     __IO uint32_t tmpreg_fre = 0x00U;              \
00534     tmpreg_fre = (__HANDLE__)->Instance->SR;       \
00535     UNUSED(tmpreg_fre);                            \
00536   }while(0U)
00537
00538 /** @brief  Enable the SPI peripheral.
00539   * @param  __HANDLE__ specifies the SPI Handle.
00540   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00541   * @retval None
00542   */
00543 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00544
00545 /** @brief  Disable the SPI peripheral.
00546   * @param  __HANDLE__ specifies the SPI Handle.
00547   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00548   * @retval None
00549   */
00550 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00551
00552 /**
00553   * @}
00554   */
00555
00556 /* Private macros ------------------------------------------------------------*/
00557 /** @defgroup SPI_Private_Macros SPI Private Macros
00558   * @{
00559   */
00560
00561 /** @brief  Set the SPI transmit-only mode.
00562   * @param  __HANDLE__ specifies the SPI Handle.
00563   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00564   * @retval None
00565   */
00566 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00567
00568 /** @brief  Set the SPI receive-only mode.
00569   * @param  __HANDLE__ specifies the SPI Handle.
00570   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00571   * @retval None
00572   */
00573 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00574
00575 /** @brief  Reset the CRC calculation of the SPI.
00576   * @param  __HANDLE__ specifies the SPI Handle.
00577   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00578   * @retval None
00579   */
00580 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
00581                                        SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
00582
00583 /** @brief  Check whether the specified SPI flag is set or not.
00584   * @param  __SR__  copy of SPI SR register.
00585   * @param  __FLAG__ specifies the flag to check.
00586   *         This parameter can be one of the following values:
00587   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00588   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00589   *            @arg SPI_FLAG_CRCERR: CRC error flag
00590   *            @arg SPI_FLAG_MODF: Mode fault flag
00591   *            @arg SPI_FLAG_OVR: Overrun flag
00592   *            @arg SPI_FLAG_BSY: Busy flag
00593   *            @arg SPI_FLAG_FRE: Frame format error flag
00594   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00595   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00596   * @retval SET or RESET.
00597   */
00598 #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
00599                                           ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
00600
00601 /** @brief  Check whether the specified SPI Interrupt is set or not.
00602   * @param  __CR2__  copy of SPI CR2 register.
00603   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00604   *         This parameter can be one of the following values:
00605   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00606   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00607   *            @arg SPI_IT_ERR: Error interrupt enable
00608   * @retval SET or RESET.
00609   */
00610 #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
00611                                                      (__INTERRUPT__)) ? SET : RESET)
00612
00613 /** @brief  Checks if SPI Mode parameter is in allowed range.
00614   * @param  __MODE__ specifies the SPI Mode.
00615   *         This parameter can be a value of @ref SPI_Mode
00616   * @retval None
00617   */
00618 #define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \
00619                                     ((__MODE__) == SPI_MODE_MASTER))
00620
00621 /** @brief  Checks if SPI Direction Mode parameter is in allowed range.
00622   * @param  __MODE__ specifies the SPI Direction Mode.
00623   *         This parameter can be a value of @ref SPI_Direction
00624   * @retval None
00625   */
00626 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
00627                                     ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
00628                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00629
00630 /** @brief  Checks if SPI Direction Mode parameter is 2 lines.
00631   * @param  __MODE__ specifies the SPI Direction Mode.
00632   * @retval None
00633   */
00634 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
00635
00636 /** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
00637   * @param  __MODE__ specifies the SPI Direction Mode.
00638   * @retval None
00639   */
00640 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
00641                                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00642
00643 /** @brief  Checks if SPI Data Size parameter is in allowed range.
00644   * @param  __DATASIZE__ specifies the SPI Data Size.
00645   *         This parameter can be a value of @ref SPI_Data_Size
00646   * @retval None
00647   */
00648 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
00649                                        ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
00650                                        ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
00651                                        ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
00652                                        ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
00653                                        ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
00654                                        ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
00655                                        ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
00656                                        ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
00657                                        ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
00658                                        ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
00659                                        ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
00660                                        ((__DATASIZE__) == SPI_DATASIZE_4BIT))
00661
00662 /** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
00663   * @param  __CPOL__ specifies the SPI serial clock steady state.
00664   *         This parameter can be a value of @ref SPI_Clock_Polarity
00665   * @retval None
00666   */
00667 #define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \
00668                                     ((__CPOL__) == SPI_POLARITY_HIGH))
00669
00670 /** @brief  Checks if SPI Clock Phase parameter is in allowed range.
00671   * @param  __CPHA__ specifies the SPI Clock Phase.
00672   *         This parameter can be a value of @ref SPI_Clock_Phase
00673   * @retval None
00674   */
00675 #define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \
00676                                     ((__CPHA__) == SPI_PHASE_2EDGE))
00677
00678 /** @brief  Checks if SPI Slave Select parameter is in allowed range.
00679   * @param  __NSS__ specifies the SPI Slave Select management parameter.
00680   *         This parameter can be a value of @ref SPI_Slave_Select_management
00681   * @retval None
00682   */
00683 #define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \
00684                                     ((__NSS__) == SPI_NSS_HARD_INPUT) || \
00685                                     ((__NSS__) == SPI_NSS_HARD_OUTPUT))
00686
00687 /** @brief  Checks if SPI NSS Pulse parameter is in allowed range.
00688   * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.
00689   *         This parameter can be a value of @ref SPI_NSSP_Mode
00690   * @retval None
00691   */
00692 #define IS_SPI_NSSP(__NSSP__)      (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
00693                                     ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
00694
00695 /** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
00696   * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
00697   *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
00698   * @retval None
00699   */
00700 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
00701                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
00702                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
00703                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
00704                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
00705                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
00706                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
00707                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
00708
00709 /** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
00710   * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
00711   *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
00712   * @retval None
00713   */
00714 #define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \
00715                                     ((__BIT__) == SPI_FIRSTBIT_LSB))
00716
00717 /** @brief  Checks if SPI TI mode parameter is in allowed range.
00718   * @param  __MODE__ specifies the SPI TI mode.
00719   *         This parameter can be a value of @ref SPI_TI_mode
00720   * @retval None
00721   */
00722 #define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \
00723                                     ((__MODE__) == SPI_TIMODE_ENABLE))
00724
00725 /** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
00726   * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
00727   *         This parameter can be a value of @ref SPI_CRC_Calculation
00728   * @retval None
00729   */
00730 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
00731                                                  ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
00732
00733 /** @brief  Checks if SPI CRC length is in allowed range.
00734   * @param  __LENGTH__ specifies the SPI CRC length.
00735   *         This parameter can be a value of @ref SPI_CRC_length
00736   * @retval None
00737   */
00738 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
00739                                        ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)     || \
00740                                        ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
00741
00742 /** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
00743   * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
00744   *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
00745   * @retval None
00746   */
00747 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \
00748                                                ((__POLYNOMIAL__) <= 0xFFFFU) && \
00749                                               (((__POLYNOMIAL__)&0x1U) != 0U))
00750
00751 /** @brief  Checks if DMA handle is valid.
00752   * @param  __HANDLE__ specifies a DMA Handle.
00753   * @retval None
00754   */
00755 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
00756
00757 /**
00758   * @}
00759   */
00760
00761 /* Include SPI HAL Extended module */
00762 #include "stm32g4xx_hal_spi_ex.h"
00763
00764 /* Exported functions --------------------------------------------------------*/
00765 /** @addtogroup SPI_Exported_Functions
00766   * @{
00767   */
00768
00769 /** @addtogroup SPI_Exported_Functions_Group1
00770   * @{
00771   */
00772 /* Initialization/de-initialization functions  ********************************/
00773 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00774 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00775 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00776 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00777
00778 /* Callbacks Register/UnRegister functions  ***********************************/
00779 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00780 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
00781                                            pSPI_CallbackTypeDef pCallback);
00782 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
00783 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00784 /**
00785   * @}
00786   */
00787
00788 /** @addtogroup SPI_Exported_Functions_Group2
00789   * @{
00790   */
00791 /* I/O operation functions  ***************************************************/
00792 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00793 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00794 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00795                                           uint32_t Timeout);
00796 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00797 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00798 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00799                                              uint16_t Size);
00800 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00801 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00802 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00803                                               uint16_t Size);
00804 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00805 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00806 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00807 /* Transfer Abort functions */
00808 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00809 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00810
00811 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00812 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00813 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00814 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00815 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00816 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00817 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00818 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00819 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00820 /**
00821   * @}
00822   */
00823
00824 /** @addtogroup SPI_Exported_Functions_Group3
00825   * @{
00826   */
00827 /* Peripheral State and Error functions ***************************************/
00828 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00829 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00830 /**
00831   * @}
00832   */
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 #ifdef __cplusplus
00847 }
00848 #endif
00849
00850 #endif /* STM32G4xx_HAL_SPI_H */
00851
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_spi_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          SPI peripheral extended functionalities :
00008   *           + IO operation functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32g4xx_hal.h"
00025
00026 /** @addtogroup STM32G4xx_HAL_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup SPIEx SPIEx
00031   * @brief SPI Extended HAL module driver
00032   * @{
00033   */
00034 #ifdef HAL_SPI_MODULE_ENABLED
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private defines -----------------------------------------------------------*/
00038 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
00039   * @{
00040   */
00041 #define SPI_FIFO_SIZE       4UL
00042 /**
00043   * @}
00044   */
00045
00046 /* Private macros ------------------------------------------------------------*/
00047 /* Private variables ---------------------------------------------------------*/
00048 /* Private function prototypes -----------------------------------------------*/
00049 /* Exported functions --------------------------------------------------------*/
00050
00051 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00052   * @{
00053   */
00054
00055 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00056   *  @brief   Data transfers functions
00057   *
00058 @verbatim
00059   ==============================================================================
00060                       ##### IO operation functions #####
00061  ===============================================================================
00062  [..]
00063     This subsection provides a set of extended functions to manage the SPI
00064     data transfers.
00065
00066     (#) Rx data flush function:
00067         (++) HAL_SPIEx_FlushRxFifo()
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  Flush the RX fifo.
00075   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00076   *               the configuration information for the specified SPI module.
00077   * @retval HAL status
00078   */
00079 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
00080 {
00081   __IO uint32_t tmpreg;
00082   uint8_t  count = 0U;
00083   while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
00084   {
00085     count++;
00086     tmpreg = hspi->Instance->DR;
00087     UNUSED(tmpreg); /* To avoid GCC warning */
00088     if (count == SPI_FIFO_SIZE)
00089     {
00090       return HAL_TIMEOUT;
00091     }
00092   }
00093   return HAL_OK;
00094 }
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 #endif /* HAL_SPI_MODULE_ENABLED */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /**
00111   * @}
00112   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_spi_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_spi_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SPI_EX_H
00021 #define STM32G4xx_HAL_SPI_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SPIEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /* Exported macros -----------------------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup SPIEx_Exported_Functions
00043   * @{
00044   */
00045
00046 /* Initialization and de-initialization functions  ****************************/
00047 /* IO operation functions *****************************************************/
00048 /** @addtogroup SPIEx_Exported_Functions_Group1
00049   * @{
00050   */
00051 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
00052 /**
00053   * @}
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 #ifdef __cplusplus
00069 }
00070 #endif
00071
00072 #endif /* STM32G4xx_HAL_SPI_EX_H */
00073
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sram.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_sram.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @brief   SRAM HAL module driver.
00006   *          This file provides a generic firmware to drive SRAM memories
00007   *          mounted as external device.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   @verbatim
00021   ==============================================================================
00022                           ##### How to use this driver #####
00023   ==============================================================================
00024   [..]
00025     This driver is a generic layered driver which contains a set of APIs used to
00026     control SRAM memories. It uses the FMC layer functions to interface
00027     with SRAM devices.
00028     The following sequence should be followed to configure the FMC to interface
00029     with SRAM/PSRAM memories:
00030
00031    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00032           SRAM_HandleTypeDef  hsram; and:
00033
00034        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00035             values of the structure member.
00036
00037        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00038             base register instance for NOR or SRAM device
00039
00040        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00041             base register instance for NOR or SRAM extended mode
00042
00043    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00044        mode timings; for example:
00045           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00046       and fill its fields with the allowed values of the structure member.
00047
00048    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00049        performs the following sequence:
00050
00051        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00052        (##) Control register configuration using the FMC NORSRAM interface function
00053             FMC_NORSRAM_Init()
00054        (##) Timing register configuration using the FMC NORSRAM interface function
00055             FMC_NORSRAM_Timing_Init()
00056        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00057             FMC_NORSRAM_Extended_Timing_Init()
00058        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00059
00060    (#) At this stage you can perform read/write accesses from/to the memory connected
00061        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00062        following APIs:
00063        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00064        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00065
00066    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00067        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00068
00069    (#) You can continuously monitor the SRAM device HAL state by calling the function
00070        HAL_SRAM_GetState()
00071
00072        *** Callback registration ***
00073     =============================================
00074     [..]
00075       The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
00076       allows the user to configure dynamically the driver callbacks.
00077
00078       Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
00079       it allows to register following callbacks:
00080         (+) MspInitCallback    : SRAM MspInit.
00081         (+) MspDeInitCallback  : SRAM MspDeInit.
00082       This function takes as parameters the HAL peripheral handle, the Callback ID
00083       and a pointer to the user callback function.
00084
00085       Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
00086       weak (overridden) function. It allows to reset following callbacks:
00087         (+) MspInitCallback    : SRAM MspInit.
00088         (+) MspDeInitCallback  : SRAM MspDeInit.
00089       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00090
00091       By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
00092       all callbacks are reset to the corresponding legacy weak (overridden) functions.
00093       Exception done for MspInit and MspDeInit callbacks that are respectively
00094       reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
00095       and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
00096       If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
00097       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00098
00099       Callbacks can be registered/unregistered in READY state only.
00100       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00101       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00102       during the Init/DeInit.
00103       In that case first register the MspInit/MspDeInit user callbacks
00104       using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
00105       or HAL_SRAM_Init function.
00106
00107       When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
00108       not defined, the callback registering feature is not available
00109       and weak (overridden) callbacks are used.
00110
00111   @endverbatim
00112   ******************************************************************************
00113   */
00114
00115 /* Includes ------------------------------------------------------------------*/
00116 #include "stm32g4xx_hal.h"
00117
00118 #if defined(FMC_BANK1)
00119
00120 /** @addtogroup STM32G4xx_HAL_Driver
00121   * @{
00122   */
00123
00124 #ifdef HAL_SRAM_MODULE_ENABLED
00125
00126 /** @defgroup SRAM SRAM
00127   * @brief SRAM driver modules
00128   * @{
00129   */
00130
00131 /* Private typedef -----------------------------------------------------------*/
00132 /* Private define ------------------------------------------------------------*/
00133 /* Private macro -------------------------------------------------------------*/
00134 /* Private variables ---------------------------------------------------------*/
00135 /* Private function prototypes -----------------------------------------------*/
00136 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
00137   * @{
00138   */
00139 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
00140 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
00141 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported functions --------------------------------------------------------*/
00147
00148 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00149   * @{
00150   */
00151
00152 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00153   * @brief    Initialization and Configuration functions.
00154   *
00155   @verbatim
00156   ==============================================================================
00157            ##### SRAM Initialization and de_initialization functions #####
00158   ==============================================================================
00159     [..]  This section provides functions allowing to initialize/de-initialize
00160           the SRAM memory
00161
00162 @endverbatim
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Performs the SRAM device initialization sequence
00168   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00169   *                the configuration information for SRAM module.
00170   * @param  Timing Pointer to SRAM control timing structure
00171   * @param  ExtTiming Pointer to SRAM extended mode timing structure
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
00175                                 FMC_NORSRAM_TimingTypeDef *ExtTiming)
00176 {
00177   /* Check the SRAM handle parameter */
00178   if (hsram == NULL)
00179   {
00180     return HAL_ERROR;
00181   }
00182
00183   if (hsram->State == HAL_SRAM_STATE_RESET)
00184   {
00185     /* Allocate lock resource and initialize it */
00186     hsram->Lock = HAL_UNLOCKED;
00187
00188 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00189     if (hsram->MspInitCallback == NULL)
00190     {
00191       hsram->MspInitCallback = HAL_SRAM_MspInit;
00192     }
00193     hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
00194     hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00195
00196     /* Init the low level hardware */
00197     hsram->MspInitCallback(hsram);
00198 #else
00199     /* Initialize the low level hardware (MSP) */
00200     HAL_SRAM_MspInit(hsram);
00201 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
00202   }
00203
00204   /* Initialize SRAM control Interface */
00205   (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00206
00207   /* Initialize SRAM timing Interface */
00208   (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00209
00210   /* Initialize SRAM extended mode timing Interface */
00211   (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
00212                                          hsram->Init.ExtendedMode);
00213
00214   /* Enable the NORSRAM device */
00215   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00216
00217   /* Initialize the SRAM controller state */
00218   hsram->State = HAL_SRAM_STATE_READY;
00219
00220   return HAL_OK;
00221 }
00222
00223 /**
00224   * @brief  Performs the SRAM device De-initialization sequence.
00225   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00226   *                the configuration information for SRAM module.
00227   * @retval HAL status
00228   */
00229 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00230 {
00231 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00232   if (hsram->MspDeInitCallback == NULL)
00233   {
00234     hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00235   }
00236
00237   /* DeInit the low level hardware */
00238   hsram->MspDeInitCallback(hsram);
00239 #else
00240   /* De-Initialize the low level hardware (MSP) */
00241   HAL_SRAM_MspDeInit(hsram);
00242 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
00243
00244   /* Configure the SRAM registers with their reset values */
00245   (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00246
00247   /* Reset the SRAM controller state */
00248   hsram->State = HAL_SRAM_STATE_RESET;
00249
00250   /* Release Lock */
00251   __HAL_UNLOCK(hsram);
00252
00253   return HAL_OK;
00254 }
00255
00256 /**
00257   * @brief  SRAM MSP Init.
00258   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00259   *                the configuration information for SRAM module.
00260   * @retval None
00261   */
00262 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00263 {
00264   /* Prevent unused argument(s) compilation warning */
00265   UNUSED(hsram);
00266
00267   /* NOTE : This function Should not be modified, when the callback is needed,
00268             the HAL_SRAM_MspInit could be implemented in the user file
00269    */
00270 }
00271
00272 /**
00273   * @brief  SRAM MSP DeInit.
00274   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00275   *                the configuration information for SRAM module.
00276   * @retval None
00277   */
00278 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00279 {
00280   /* Prevent unused argument(s) compilation warning */
00281   UNUSED(hsram);
00282
00283   /* NOTE : This function Should not be modified, when the callback is needed,
00284             the HAL_SRAM_MspDeInit could be implemented in the user file
00285    */
00286 }
00287
00288 /**
00289   * @brief  DMA transfer complete callback.
00290   * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
00291   *                the configuration information for SRAM module.
00292   * @retval None
00293   */
00294 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00295 {
00296   /* Prevent unused argument(s) compilation warning */
00297   UNUSED(hdma);
00298
00299   /* NOTE : This function Should not be modified, when the callback is needed,
00300             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00301    */
00302 }
00303
00304 /**
00305   * @brief  DMA transfer complete error callback.
00306   * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
00307   *                the configuration information for SRAM module.
00308   * @retval None
00309   */
00310 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00311 {
00312   /* Prevent unused argument(s) compilation warning */
00313   UNUSED(hdma);
00314
00315   /* NOTE : This function Should not be modified, when the callback is needed,
00316             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00317    */
00318 }
00319
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00325   * @brief    Input Output and memory control functions
00326   *
00327   @verbatim
00328   ==============================================================================
00329                   ##### SRAM Input and Output functions #####
00330   ==============================================================================
00331   [..]
00332     This section provides functions allowing to use and control the SRAM memory
00333
00334 @endverbatim
00335   * @{
00336   */
00337
00338 /**
00339   * @brief  Reads 8-bit buffer from SRAM memory.
00340   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00341   *                the configuration information for SRAM module.
00342   * @param  pAddress Pointer to read start address
00343   * @param  pDstBuffer Pointer to destination buffer
00344   * @param  BufferSize Size of the buffer to read from memory
00345   * @retval HAL status
00346   */
00347 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
00348                                    uint32_t BufferSize)
00349 {
00350   uint32_t size;
00351   __IO uint8_t *psramaddress = (uint8_t *)pAddress;
00352   uint8_t *pdestbuff = pDstBuffer;
00353   HAL_SRAM_StateTypeDef state = hsram->State;
00354
00355   /* Check the SRAM controller state */
00356   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00357   {
00358     /* Process Locked */
00359     __HAL_LOCK(hsram);
00360
00361     /* Update the SRAM controller state */
00362     hsram->State = HAL_SRAM_STATE_BUSY;
00363
00364     /* Read data from memory */
00365     for (size = BufferSize; size != 0U; size--)
00366     {
00367       *pdestbuff = *psramaddress;
00368       pdestbuff++;
00369       psramaddress++;
00370     }
00371
00372     /* Update the SRAM controller state */
00373     hsram->State = state;
00374
00375     /* Process unlocked */
00376     __HAL_UNLOCK(hsram);
00377   }
00378   else
00379   {
00380     return HAL_ERROR;
00381   }
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Writes 8-bit buffer to SRAM memory.
00388   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00389   *                the configuration information for SRAM module.
00390   * @param  pAddress Pointer to write start address
00391   * @param  pSrcBuffer Pointer to source buffer to write
00392   * @param  BufferSize Size of the buffer to write to memory
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
00396                                     uint32_t BufferSize)
00397 {
00398   uint32_t size;
00399   __IO uint8_t *psramaddress = (uint8_t *)pAddress;
00400   uint8_t *psrcbuff = pSrcBuffer;
00401
00402   /* Check the SRAM controller state */
00403   if (hsram->State == HAL_SRAM_STATE_READY)
00404   {
00405     /* Process Locked */
00406     __HAL_LOCK(hsram);
00407
00408     /* Update the SRAM controller state */
00409     hsram->State = HAL_SRAM_STATE_BUSY;
00410
00411     /* Write data to memory */
00412     for (size = BufferSize; size != 0U; size--)
00413     {
00414       *psramaddress = *psrcbuff;
00415       psrcbuff++;
00416       psramaddress++;
00417     }
00418
00419     /* Update the SRAM controller state */
00420     hsram->State = HAL_SRAM_STATE_READY;
00421
00422     /* Process unlocked */
00423     __HAL_UNLOCK(hsram);
00424   }
00425   else
00426   {
00427     return HAL_ERROR;
00428   }
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief  Reads 16-bit buffer from SRAM memory.
00435   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00436   *                the configuration information for SRAM module.
00437   * @param  pAddress Pointer to read start address
00438   * @param  pDstBuffer Pointer to destination buffer
00439   * @param  BufferSize Size of the buffer to read from memory
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
00443                                     uint32_t BufferSize)
00444 {
00445   uint32_t size;
00446   __IO uint32_t *psramaddress = pAddress;
00447   uint16_t *pdestbuff = pDstBuffer;
00448   uint8_t limit;
00449   HAL_SRAM_StateTypeDef state = hsram->State;
00450
00451   /* Check the SRAM controller state */
00452   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00453   {
00454     /* Process Locked */
00455     __HAL_LOCK(hsram);
00456
00457     /* Update the SRAM controller state */
00458     hsram->State = HAL_SRAM_STATE_BUSY;
00459
00460     /* Check if the size is a 32-bits multiple */
00461     limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
00462
00463     /* Read data from memory */
00464     for (size = BufferSize; size != limit; size -= 2U)
00465     {
00466       *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
00467       pdestbuff++;
00468       *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
00469       pdestbuff++;
00470       psramaddress++;
00471     }
00472
00473     /* Read last 16-bits if size is not 32-bits multiple */
00474     if (limit != 0U)
00475     {
00476       *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
00477     }
00478
00479     /* Update the SRAM controller state */
00480     hsram->State = state;
00481
00482     /* Process unlocked */
00483     __HAL_UNLOCK(hsram);
00484   }
00485   else
00486   {
00487     return HAL_ERROR;
00488   }
00489
00490   return HAL_OK;
00491 }
00492
00493 /**
00494   * @brief  Writes 16-bit buffer to SRAM memory.
00495   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00496   *                the configuration information for SRAM module.
00497   * @param  pAddress Pointer to write start address
00498   * @param  pSrcBuffer Pointer to source buffer to write
00499   * @param  BufferSize Size of the buffer to write to memory
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
00503                                      uint32_t BufferSize)
00504 {
00505   uint32_t size;
00506   __IO uint32_t *psramaddress = pAddress;
00507   uint16_t *psrcbuff = pSrcBuffer;
00508   uint8_t limit;
00509
00510   /* Check the SRAM controller state */
00511   if (hsram->State == HAL_SRAM_STATE_READY)
00512   {
00513     /* Process Locked */
00514     __HAL_LOCK(hsram);
00515
00516     /* Update the SRAM controller state */
00517     hsram->State = HAL_SRAM_STATE_BUSY;
00518
00519     /* Check if the size is a 32-bits multiple */
00520     limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
00521
00522     /* Write data to memory */
00523     for (size = BufferSize; size != limit; size -= 2U)
00524     {
00525       *psramaddress = (uint32_t)(*psrcbuff);
00526       psrcbuff++;
00527       *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
00528       psrcbuff++;
00529       psramaddress++;
00530     }
00531
00532     /* Write last 16-bits if size is not 32-bits multiple */
00533     if (limit != 0U)
00534     {
00535       *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
00536     }
00537
00538     /* Update the SRAM controller state */
00539     hsram->State = HAL_SRAM_STATE_READY;
00540
00541     /* Process unlocked */
00542     __HAL_UNLOCK(hsram);
00543   }
00544   else
00545   {
00546     return HAL_ERROR;
00547   }
00548
00549   return HAL_OK;
00550 }
00551
00552 /**
00553   * @brief  Reads 32-bit buffer from SRAM memory.
00554   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00555   *                the configuration information for SRAM module.
00556   * @param  pAddress Pointer to read start address
00557   * @param  pDstBuffer Pointer to destination buffer
00558   * @param  BufferSize Size of the buffer to read from memory
00559   * @retval HAL status
00560   */
00561 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
00562                                     uint32_t BufferSize)
00563 {
00564   uint32_t size;
00565   __IO uint32_t *psramaddress = pAddress;
00566   uint32_t *pdestbuff = pDstBuffer;
00567   HAL_SRAM_StateTypeDef state = hsram->State;
00568
00569   /* Check the SRAM controller state */
00570   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00571   {
00572     /* Process Locked */
00573     __HAL_LOCK(hsram);
00574
00575     /* Update the SRAM controller state */
00576     hsram->State = HAL_SRAM_STATE_BUSY;
00577
00578     /* Read data from memory */
00579     for (size = BufferSize; size != 0U; size--)
00580     {
00581       *pdestbuff = *psramaddress;
00582       pdestbuff++;
00583       psramaddress++;
00584     }
00585
00586     /* Update the SRAM controller state */
00587     hsram->State = state;
00588
00589     /* Process unlocked */
00590     __HAL_UNLOCK(hsram);
00591   }
00592   else
00593   {
00594     return HAL_ERROR;
00595   }
00596
00597   return HAL_OK;
00598 }
00599
00600 /**
00601   * @brief  Writes 32-bit buffer to SRAM memory.
00602   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00603   *                the configuration information for SRAM module.
00604   * @param  pAddress Pointer to write start address
00605   * @param  pSrcBuffer Pointer to source buffer to write
00606   * @param  BufferSize Size of the buffer to write to memory
00607   * @retval HAL status
00608   */
00609 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
00610                                      uint32_t BufferSize)
00611 {
00612   uint32_t size;
00613   __IO uint32_t *psramaddress = pAddress;
00614   uint32_t *psrcbuff = pSrcBuffer;
00615
00616   /* Check the SRAM controller state */
00617   if (hsram->State == HAL_SRAM_STATE_READY)
00618   {
00619     /* Process Locked */
00620     __HAL_LOCK(hsram);
00621
00622     /* Update the SRAM controller state */
00623     hsram->State = HAL_SRAM_STATE_BUSY;
00624
00625     /* Write data to memory */
00626     for (size = BufferSize; size != 0U; size--)
00627     {
00628       *psramaddress = *psrcbuff;
00629       psrcbuff++;
00630       psramaddress++;
00631     }
00632
00633     /* Update the SRAM controller state */
00634     hsram->State = HAL_SRAM_STATE_READY;
00635
00636     /* Process unlocked */
00637     __HAL_UNLOCK(hsram);
00638   }
00639   else
00640   {
00641     return HAL_ERROR;
00642   }
00643
00644   return HAL_OK;
00645 }
00646
00647 /**
00648   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00649   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00650   *                the configuration information for SRAM module.
00651   * @param  pAddress Pointer to read start address
00652   * @param  pDstBuffer Pointer to destination buffer
00653   * @param  BufferSize Size of the buffer to read from memory
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
00657                                     uint32_t BufferSize)
00658 {
00659   HAL_StatusTypeDef status;
00660   HAL_SRAM_StateTypeDef state = hsram->State;
00661
00662   /* Check the SRAM controller state */
00663   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00664   {
00665     /* Process Locked */
00666     __HAL_LOCK(hsram);
00667
00668     /* Update the SRAM controller state */
00669     hsram->State = HAL_SRAM_STATE_BUSY;
00670
00671     /* Configure DMA user callbacks */
00672     if (state == HAL_SRAM_STATE_READY)
00673     {
00674       hsram->hdma->XferCpltCallback = SRAM_DMACplt;
00675     }
00676     else
00677     {
00678       hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
00679     }
00680     hsram->hdma->XferErrorCallback = SRAM_DMAError;
00681
00682     /* Enable the DMA Stream */
00683     status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00684
00685     /* Process unlocked */
00686     __HAL_UNLOCK(hsram);
00687   }
00688   else
00689   {
00690     status = HAL_ERROR;
00691   }
00692
00693   return status;
00694 }
00695
00696 /**
00697   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00698   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00699   *                the configuration information for SRAM module.
00700   * @param  pAddress Pointer to write start address
00701   * @param  pSrcBuffer Pointer to source buffer to write
00702   * @param  BufferSize Size of the buffer to write to memory
00703   * @retval HAL status
00704   */
00705 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
00706                                      uint32_t BufferSize)
00707 {
00708   HAL_StatusTypeDef status;
00709
00710   /* Check the SRAM controller state */
00711   if (hsram->State == HAL_SRAM_STATE_READY)
00712   {
00713     /* Process Locked */
00714     __HAL_LOCK(hsram);
00715
00716     /* Update the SRAM controller state */
00717     hsram->State = HAL_SRAM_STATE_BUSY;
00718
00719     /* Configure DMA user callbacks */
00720     hsram->hdma->XferCpltCallback = SRAM_DMACplt;
00721     hsram->hdma->XferErrorCallback = SRAM_DMAError;
00722
00723     /* Enable the DMA Stream */
00724     status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00725
00726     /* Process unlocked */
00727     __HAL_UNLOCK(hsram);
00728   }
00729   else
00730   {
00731     status = HAL_ERROR;
00732   }
00733
00734   return status;
00735 }
00736
00737 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00738 /**
00739   * @brief  Register a User SRAM Callback
00740   *         To be used to override the weak predefined callback
00741   * @param hsram : SRAM handle
00742   * @param CallbackId : ID of the callback to be registered
00743   *        This parameter can be one of the following values:
00744   *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
00745   *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
00746   * @param pCallback : pointer to the Callback function
00747   * @retval status
00748   */
00749 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
00750                                             pSRAM_CallbackTypeDef pCallback)
00751 {
00752   HAL_StatusTypeDef status = HAL_OK;
00753   HAL_SRAM_StateTypeDef state;
00754
00755   if (pCallback == NULL)
00756   {
00757     return HAL_ERROR;
00758   }
00759
00760   state = hsram->State;
00761   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
00762   {
00763     switch (CallbackId)
00764     {
00765       case HAL_SRAM_MSP_INIT_CB_ID :
00766         hsram->MspInitCallback = pCallback;
00767         break;
00768       case HAL_SRAM_MSP_DEINIT_CB_ID :
00769         hsram->MspDeInitCallback = pCallback;
00770         break;
00771       default :
00772         /* update return status */
00773         status =  HAL_ERROR;
00774         break;
00775     }
00776   }
00777   else
00778   {
00779     /* update return status */
00780     status =  HAL_ERROR;
00781   }
00782
00783   return status;
00784 }
00785
00786 /**
00787   * @brief  Unregister a User SRAM Callback
00788   *         SRAM Callback is redirected to the weak predefined callback
00789   * @param hsram : SRAM handle
00790   * @param CallbackId : ID of the callback to be unregistered
00791   *        This parameter can be one of the following values:
00792   *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
00793   *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
00794   *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
00795   *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
00796   * @retval status
00797   */
00798 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
00799 {
00800   HAL_StatusTypeDef status = HAL_OK;
00801   HAL_SRAM_StateTypeDef state;
00802
00803   state = hsram->State;
00804   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00805   {
00806     switch (CallbackId)
00807     {
00808       case HAL_SRAM_MSP_INIT_CB_ID :
00809         hsram->MspInitCallback = HAL_SRAM_MspInit;
00810         break;
00811       case HAL_SRAM_MSP_DEINIT_CB_ID :
00812         hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00813         break;
00814       case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
00815         hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
00816         break;
00817       case HAL_SRAM_DMA_XFER_ERR_CB_ID :
00818         hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00819         break;
00820       default :
00821         /* update return status */
00822         status =  HAL_ERROR;
00823         break;
00824     }
00825   }
00826   else if (state == HAL_SRAM_STATE_RESET)
00827   {
00828     switch (CallbackId)
00829     {
00830       case HAL_SRAM_MSP_INIT_CB_ID :
00831         hsram->MspInitCallback = HAL_SRAM_MspInit;
00832         break;
00833       case HAL_SRAM_MSP_DEINIT_CB_ID :
00834         hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
00835         break;
00836       default :
00837         /* update return status */
00838         status =  HAL_ERROR;
00839         break;
00840     }
00841   }
00842   else
00843   {
00844     /* update return status */
00845     status =  HAL_ERROR;
00846   }
00847
00848   return status;
00849 }
00850
00851 /**
00852   * @brief  Register a User SRAM Callback for DMA transfers
00853   *         To be used to override the weak predefined callback
00854   * @param hsram : SRAM handle
00855   * @param CallbackId : ID of the callback to be registered
00856   *        This parameter can be one of the following values:
00857   *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
00858   *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
00859   * @param pCallback : pointer to the Callback function
00860   * @retval status
00861   */
00862 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
00863                                                pSRAM_DmaCallbackTypeDef pCallback)
00864 {
00865   HAL_StatusTypeDef status = HAL_OK;
00866   HAL_SRAM_StateTypeDef state;
00867
00868   if (pCallback == NULL)
00869   {
00870     return HAL_ERROR;
00871   }
00872
00873   /* Process locked */
00874   __HAL_LOCK(hsram);
00875
00876   state = hsram->State;
00877   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
00878   {
00879     switch (CallbackId)
00880     {
00881       case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
00882         hsram->DmaXferCpltCallback = pCallback;
00883         break;
00884       case HAL_SRAM_DMA_XFER_ERR_CB_ID :
00885         hsram->DmaXferErrorCallback = pCallback;
00886         break;
00887       default :
00888         /* update return status */
00889         status =  HAL_ERROR;
00890         break;
00891     }
00892   }
00893   else
00894   {
00895     /* update return status */
00896     status =  HAL_ERROR;
00897   }
00898
00899   /* Release Lock */
00900   __HAL_UNLOCK(hsram);
00901   return status;
00902 }
00903 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
00904
00905 /**
00906   * @}
00907   */
00908
00909 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00910   *  @brief   Control functions
00911   *
00912 @verbatim
00913   ==============================================================================
00914                         ##### SRAM Control functions #####
00915   ==============================================================================
00916   [..]
00917     This subsection provides a set of functions allowing to control dynamically
00918     the SRAM interface.
00919
00920 @endverbatim
00921   * @{
00922   */
00923
00924 /**
00925   * @brief  Enables dynamically SRAM write operation.
00926   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00927   *                the configuration information for SRAM module.
00928   * @retval HAL status
00929   */
00930 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00931 {
00932   /* Check the SRAM controller state */
00933   if (hsram->State == HAL_SRAM_STATE_PROTECTED)
00934   {
00935     /* Process Locked */
00936     __HAL_LOCK(hsram);
00937
00938     /* Update the SRAM controller state */
00939     hsram->State = HAL_SRAM_STATE_BUSY;
00940
00941     /* Enable write operation */
00942     (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00943
00944     /* Update the SRAM controller state */
00945     hsram->State = HAL_SRAM_STATE_READY;
00946
00947     /* Process unlocked */
00948     __HAL_UNLOCK(hsram);
00949   }
00950   else
00951   {
00952     return HAL_ERROR;
00953   }
00954
00955   return HAL_OK;
00956 }
00957
00958 /**
00959   * @brief  Disables dynamically SRAM write operation.
00960   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
00961   *                the configuration information for SRAM module.
00962   * @retval HAL status
00963   */
00964 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00965 {
00966   /* Check the SRAM controller state */
00967   if (hsram->State == HAL_SRAM_STATE_READY)
00968   {
00969     /* Process Locked */
00970     __HAL_LOCK(hsram);
00971
00972     /* Update the SRAM controller state */
00973     hsram->State = HAL_SRAM_STATE_BUSY;
00974
00975     /* Disable write operation */
00976     (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00977
00978     /* Update the SRAM controller state */
00979     hsram->State = HAL_SRAM_STATE_PROTECTED;
00980
00981     /* Process unlocked */
00982     __HAL_UNLOCK(hsram);
00983   }
00984   else
00985   {
00986     return HAL_ERROR;
00987   }
00988
00989   return HAL_OK;
00990 }
00991
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00997   *  @brief   Peripheral State functions
00998   *
00999 @verbatim
01000   ==============================================================================
01001                       ##### SRAM State functions #####
01002   ==============================================================================
01003   [..]
01004     This subsection permits to get in run-time the status of the SRAM controller
01005     and the data flow.
01006
01007 @endverbatim
01008   * @{
01009   */
01010
01011 /**
01012   * @brief  Returns the SRAM controller state
01013   * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
01014   *                the configuration information for SRAM module.
01015   * @retval HAL state
01016   */
01017 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
01018 {
01019   return hsram->State;
01020 }
01021
01022 /**
01023   * @}
01024   */
01025
01026 /**
01027   * @}
01028   */
01029
01030 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
01031   * @{
01032   */
01033
01034 /**
01035   * @brief  DMA SRAM process complete callback.
01036   * @param  hdma : DMA handle
01037   * @retval None
01038   */
01039 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
01040 {
01041   SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
01042
01043   /* Disable the DMA channel */
01044   __HAL_DMA_DISABLE(hdma);
01045
01046   /* Update the SRAM controller state */
01047   hsram->State = HAL_SRAM_STATE_READY;
01048
01049 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01050   hsram->DmaXferCpltCallback(hdma);
01051 #else
01052   HAL_SRAM_DMA_XferCpltCallback(hdma);
01053 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
01054 }
01055
01056 /**
01057   * @brief  DMA SRAM process complete callback.
01058   * @param  hdma : DMA handle
01059   * @retval None
01060   */
01061 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
01062 {
01063   SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
01064
01065   /* Disable the DMA channel */
01066   __HAL_DMA_DISABLE(hdma);
01067
01068   /* Update the SRAM controller state */
01069   hsram->State = HAL_SRAM_STATE_PROTECTED;
01070
01071 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01072   hsram->DmaXferCpltCallback(hdma);
01073 #else
01074   HAL_SRAM_DMA_XferCpltCallback(hdma);
01075 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
01076 }
01077
01078 /**
01079   * @brief  DMA SRAM error callback.
01080   * @param  hdma : DMA handle
01081   * @retval None
01082   */
01083 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
01084 {
01085   SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
01086
01087   /* Disable the DMA channel */
01088   __HAL_DMA_DISABLE(hdma);
01089
01090   /* Update the SRAM controller state */
01091   hsram->State = HAL_SRAM_STATE_ERROR;
01092
01093 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
01094   hsram->DmaXferErrorCallback(hdma);
01095 #else
01096   HAL_SRAM_DMA_XferErrorCallback(hdma);
01097 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
01098 }
01099
01100 /**
01101   * @}
01102   */
01103
01104 /**
01105   * @}
01106   */
01107
01108 #endif /* HAL_SRAM_MODULE_ENABLED */
01109
01110 /**
01111   * @}
01112   */
01113
01114 #endif /* FMC_BANK1 */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_sram.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_sram.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SRAM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_SRAM_H
00021 #define STM32G4xx_HAL_SRAM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 #if defined(FMC_BANK1)
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32g4xx_ll_fmc.h"
00031
00032 /** @addtogroup STM32G4xx_HAL_Driver
00033   * @{
00034   */
00035 /** @addtogroup SRAM
00036   * @{
00037   */
00038
00039 /* Exported typedef ----------------------------------------------------------*/
00040
00041 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00042   * @{
00043   */
00044 /**
00045   * @brief  HAL SRAM State structures definition
00046   */
00047 typedef enum
00048 {
00049   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00050   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00051   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00052   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00053   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
00054
00055 } HAL_SRAM_StateTypeDef;
00056
00057 /**
00058   * @brief  SRAM handle Structure definition
00059   */
00060 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00061 typedef struct __SRAM_HandleTypeDef
00062 #else
00063 typedef struct
00064 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00065 {
00066   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00067
00068   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00069
00070   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00071
00072   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00073
00074   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00075
00076   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00077
00078 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00079   void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
00080   void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
00081   void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
00082   void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
00083 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00084 } SRAM_HandleTypeDef;
00085
00086 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00087 /**
00088   * @brief  HAL SRAM Callback ID enumeration definition
00089   */
00090 typedef enum
00091 {
00092   HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
00093   HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
00094   HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
00095   HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
00096 } HAL_SRAM_CallbackIDTypeDef;
00097
00098 /**
00099   * @brief  HAL SRAM Callback pointer definition
00100   */
00101 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
00102 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
00103 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /* Exported macro ------------------------------------------------------------*/
00110
00111 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00112   * @{
00113   */
00114
00115 /** @brief Reset SRAM handle state
00116   * @param  __HANDLE__ SRAM handle
00117   * @retval None
00118   */
00119 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00120 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
00121                                                                (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
00122                                                                (__HANDLE__)->MspInitCallback = NULL;       \
00123                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
00124                                                              } while(0)
00125 #else
00126 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00127 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Exported functions --------------------------------------------------------*/
00134 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00135   * @{
00136   */
00137
00138 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00139   * @{
00140   */
00141
00142 /* Initialization/de-initialization functions  ********************************/
00143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
00144                                 FMC_NORSRAM_TimingTypeDef *ExtTiming);
00145 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00146 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00147 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00148
00149 /**
00150   * @}
00151   */
00152
00153 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00154   * @{
00155   */
00156
00157 /* I/O operation functions  ***************************************************/
00158 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
00159                                    uint32_t BufferSize);
00160 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
00161                                     uint32_t BufferSize);
00162 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
00163                                     uint32_t BufferSize);
00164 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
00165                                      uint32_t BufferSize);
00166 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
00167                                     uint32_t BufferSize);
00168 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
00169                                      uint32_t BufferSize);
00170 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
00171                                     uint32_t BufferSize);
00172 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
00173                                      uint32_t BufferSize);
00174
00175 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00176 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00177
00178 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
00179 /* SRAM callback registering/unregistering */
00180 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
00181                                             pSRAM_CallbackTypeDef pCallback);
00182 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
00183 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
00184                                                pSRAM_DmaCallbackTypeDef pCallback);
00185 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00192   * @{
00193   */
00194
00195 /* SRAM Control functions  ****************************************************/
00196 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00197 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00198
00199 /**
00200   * @}
00201   */
00202
00203 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00204   * @{
00205   */
00206
00207 /* SRAM  State functions ******************************************************/
00208 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
00209
00210 /**
00211   * @}
00212   */
00213
00214 /**
00215   * @}
00216   */
00217
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 #endif /* FMC_BANK1 */
00227
00228 #ifdef __cplusplus
00229 }
00230 #endif
00231
00232 #endif /* STM32G4xx_HAL_SRAM_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_tim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer (TIM) peripheral:
00008   *           + TIM Time Base Initialization
00009   *           + TIM Time Base Start
00010   *           + TIM Time Base Start Interruption
00011   *           + TIM Time Base Start DMA
00012   *           + TIM Output Compare/PWM Initialization
00013   *           + TIM Output Compare/PWM Channel Configuration
00014   *           + TIM Output Compare/PWM  Start
00015   *           + TIM Output Compare/PWM  Start Interruption
00016   *           + TIM Output Compare/PWM Start DMA
00017   *           + TIM Input Capture Initialization
00018   *           + TIM Input Capture Channel Configuration
00019   *           + TIM Input Capture Start
00020   *           + TIM Input Capture Start Interruption
00021   *           + TIM Input Capture Start DMA
00022   *           + TIM One Pulse Initialization
00023   *           + TIM One Pulse Channel Configuration
00024   *           + TIM One Pulse Start
00025   *           + TIM Encoder Interface Initialization
00026   *           + TIM Encoder Interface Start
00027   *           + TIM Encoder Interface Start Interruption
00028   *           + TIM Encoder Interface Start DMA
00029   *           + Commutation Event configuration with Interruption and DMA
00030   *           + TIM OCRef clear configuration
00031   *           + TIM External Clock configuration
00032   ******************************************************************************
00033   * @attention
00034   *
00035   * Copyright (c) 2019 STMicroelectronics.
00036   * All rights reserved.
00037   *
00038   * This software is licensed under terms that can be found in the LICENSE file
00039   * in the root directory of this software component.
00040   * If no LICENSE file comes with this software, it is provided AS-IS.
00041   *
00042   ******************************************************************************
00043   @verbatim
00044   ==============================================================================
00045                       ##### TIMER Generic features #####
00046   ==============================================================================
00047   [..] The Timer features include:
00048        (#) 16-bit up, down, up/down auto-reload counter.
00049        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00050            counter clock frequency either by any factor between 1 and 65536.
00051        (#) Up to 4 independent channels for:
00052            (++) Input Capture
00053            (++) Output Compare
00054            (++) PWM generation (Edge and Center-aligned Mode)
00055            (++) One-pulse mode output
00056        (#) Synchronization circuit to control the timer with external signals and to interconnect
00057             several timers together.
00058        (#) Supports incremental encoder for positioning purposes
00059
00060             ##### How to use this driver #####
00061   ==============================================================================
00062     [..]
00063      (#) Initialize the TIM low level resources by implementing the following functions
00064          depending on the selected feature:
00065            (++) Time Base : HAL_TIM_Base_MspInit()
00066            (++) Input Capture : HAL_TIM_IC_MspInit()
00067            (++) Output Compare : HAL_TIM_OC_MspInit()
00068            (++) PWM generation : HAL_TIM_PWM_MspInit()
00069            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00070            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00071
00072      (#) Initialize the TIM low level resources :
00073         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00074         (##) TIM pins configuration
00075             (+++) Enable the clock for the TIM GPIOs using the following function:
00076              __HAL_RCC_GPIOx_CLK_ENABLE();
00077             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00078
00079      (#) The external Clock can be configured, if needed (the default clock is the
00080          internal clock from the APBx), using the following function:
00081          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00082          any start function.
00083
00084      (#) Configure the TIM in the desired functioning mode using one of the
00085        Initialization function of this driver:
00086        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00087        (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
00088             to use the Timer to generate an Output Compare signal.
00089        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00090             PWM signal.
00091        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00092             external signal.
00093        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00094             in One Pulse Mode.
00095        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00096
00097      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00098            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00099            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00100            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00101            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00102            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00103            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00104
00105      (#) The DMA Burst is managed with the two following functions:
00106          HAL_TIM_DMABurst_WriteStart()
00107          HAL_TIM_DMABurst_ReadStart()
00108
00109     *** Callback registration ***
00110   =============================================
00111
00112   [..]
00113   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
00114   allows the user to configure dynamically the driver callbacks.
00115
00116   [..]
00117   Use Function HAL_TIM_RegisterCallback() to register a callback.
00118   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00119   the Callback ID and a pointer to the user callback function.
00120
00121   [..]
00122   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
00123   weak function.
00124   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00125   and the Callback ID.
00126
00127   [..]
00128   These functions allow to register/unregister following callbacks:
00129     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
00130     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
00131     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
00132     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
00133     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
00134     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
00135     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
00136     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
00137     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
00138     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
00139     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
00140     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
00141     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
00142     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
00143     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
00144     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
00145     (+) TriggerCallback                   : TIM Trigger Callback.
00146     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
00147     (+) IC_CaptureCallback                : TIM Input Capture Callback.
00148     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
00149     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
00150     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
00151     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
00152     (+) ErrorCallback                     : TIM Error Callback.
00153     (+) CommutationCallback               : TIM Commutation Callback.
00154     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
00155     (+) BreakCallback                     : TIM Break Callback.
00156     (+) Break2Callback                    : TIM Break2 Callback.
00157     (+) EncoderIndexCallback              : TIM Encoder Index Callback.
00158     (+) DirectionChangeCallback           : TIM Direction Change Callback
00159     (+) IndexErrorCallback                : TIM Index Error Callback.
00160     (+) TransitionErrorCallback           : TIM Transition Error Callback
00161
00162   [..]
00163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
00164 all interrupt callbacks are set to the corresponding weak functions:
00165   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
00166
00167   [..]
00168   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00169   functionalities in the Init / DeInit only when these callbacks are null
00170   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
00171     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
00172
00173   [..]
00174     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
00175     Exception done MspInit / MspDeInit that can be registered / unregistered
00176     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
00177     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
00178   In that case first register the MspInit/MspDeInit user callbacks
00179       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
00180
00181   [..]
00182       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
00183       not defined, the callback registration feature is not available and all callbacks
00184       are set to the corresponding weak functions.
00185
00186   @endverbatim
00187   ******************************************************************************
00188   */
00189
00190 /* Includes ------------------------------------------------------------------*/
00191 #include "stm32g4xx_hal.h"
00192
00193 /** @addtogroup STM32G4xx_HAL_Driver
00194   * @{
00195   */
00196
00197 /** @defgroup TIM TIM
00198   * @brief TIM HAL module driver
00199   * @{
00200   */
00201
00202 #ifdef HAL_TIM_MODULE_ENABLED
00203
00204 /* Private typedef -----------------------------------------------------------*/
00205 /* Private define ------------------------------------------------------------*/
00206 /** @addtogroup TIM_Private_Constants
00207   * @{
00208   */
00209 #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
00210
00211 /**
00212   * @}
00213   */
00214 /* Private macros ------------------------------------------------------------*/
00215 /* Private variables ---------------------------------------------------------*/
00216 /* Private function prototypes -----------------------------------------------*/
00217 /** @addtogroup TIM_Private_Functions
00218   * @{
00219   */
00220 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00221 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00222 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00223 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00224 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00225 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00226 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00227                               uint32_t TIM_ICFilter);
00228 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00229 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00230                               uint32_t TIM_ICFilter);
00231 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00232                               uint32_t TIM_ICFilter);
00233 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
00234 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00235 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
00236 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
00237 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00238 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
00239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00240                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
00241 /**
00242   * @}
00243   */
00244 /* Exported functions --------------------------------------------------------*/
00245
00246 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00247   * @{
00248   */
00249
00250 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
00251   *  @brief    Time Base functions
00252   *
00253 @verbatim
00254   ==============================================================================
00255               ##### Time Base functions #####
00256   ==============================================================================
00257   [..]
00258     This section provides functions allowing to:
00259     (+) Initialize and configure the TIM base.
00260     (+) De-initialize the TIM base.
00261     (+) Start the Time Base.
00262     (+) Stop the Time Base.
00263     (+) Start the Time Base and enable interrupt.
00264     (+) Stop the Time Base and disable interrupt.
00265     (+) Start the Time Base and enable DMA transfer.
00266     (+) Stop the Time Base and disable DMA transfer.
00267
00268 @endverbatim
00269   * @{
00270   */
00271 /**
00272   * @brief  Initializes the TIM Time base Unit according to the specified
00273   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00274   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00275   *         requires a timer reset to avoid unexpected direction
00276   *         due to DIR bit readonly in center aligned mode.
00277   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
00278   * @param  htim TIM Base handle
00279   * @retval HAL status
00280   */
00281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00282 {
00283   /* Check the TIM handle allocation */
00284   if (htim == NULL)
00285   {
00286     return HAL_ERROR;
00287   }
00288
00289   /* Check the parameters */
00290   assert_param(IS_TIM_INSTANCE(htim->Instance));
00291   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00292   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00293   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00294   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00295
00296   if (htim->State == HAL_TIM_STATE_RESET)
00297   {
00298     /* Allocate lock resource and initialize it */
00299     htim->Lock = HAL_UNLOCKED;
00300
00301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00302     /* Reset interrupt callbacks to legacy weak callbacks */
00303     TIM_ResetCallback(htim);
00304
00305     if (htim->Base_MspInitCallback == NULL)
00306     {
00307       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
00308     }
00309     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00310     htim->Base_MspInitCallback(htim);
00311 #else
00312     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00313     HAL_TIM_Base_MspInit(htim);
00314 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00315   }
00316
00317   /* Set the TIM state */
00318   htim->State = HAL_TIM_STATE_BUSY;
00319
00320   /* Set the Time Base configuration */
00321   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00322
00323   /* Initialize the DMA burst operation state */
00324   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00325
00326   /* Initialize the TIM channels state */
00327   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00328   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00329
00330   /* Initialize the TIM state*/
00331   htim->State = HAL_TIM_STATE_READY;
00332
00333   return HAL_OK;
00334 }
00335
00336 /**
00337   * @brief  DeInitializes the TIM Base peripheral
00338   * @param  htim TIM Base handle
00339   * @retval HAL status
00340   */
00341 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00342 {
00343   /* Check the parameters */
00344   assert_param(IS_TIM_INSTANCE(htim->Instance));
00345
00346   htim->State = HAL_TIM_STATE_BUSY;
00347
00348   /* Disable the TIM Peripheral Clock */
00349   __HAL_TIM_DISABLE(htim);
00350
00351 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00352   if (htim->Base_MspDeInitCallback == NULL)
00353   {
00354     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
00355   }
00356   /* DeInit the low level hardware */
00357   htim->Base_MspDeInitCallback(htim);
00358 #else
00359   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00360   HAL_TIM_Base_MspDeInit(htim);
00361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00362
00363   /* Change the DMA burst operation state */
00364   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00365
00366   /* Change the TIM channels state */
00367   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00368   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00369
00370   /* Change TIM state */
00371   htim->State = HAL_TIM_STATE_RESET;
00372
00373   /* Release Lock */
00374   __HAL_UNLOCK(htim);
00375
00376   return HAL_OK;
00377 }
00378
00379 /**
00380   * @brief  Initializes the TIM Base MSP.
00381   * @param  htim TIM Base handle
00382   * @retval None
00383   */
00384 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00385 {
00386   /* Prevent unused argument(s) compilation warning */
00387   UNUSED(htim);
00388
00389   /* NOTE : This function should not be modified, when the callback is needed,
00390             the HAL_TIM_Base_MspInit could be implemented in the user file
00391    */
00392 }
00393
00394 /**
00395   * @brief  DeInitializes TIM Base MSP.
00396   * @param  htim TIM Base handle
00397   * @retval None
00398   */
00399 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00400 {
00401   /* Prevent unused argument(s) compilation warning */
00402   UNUSED(htim);
00403
00404   /* NOTE : This function should not be modified, when the callback is needed,
00405             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00406    */
00407 }
00408
00409
00410 /**
00411   * @brief  Starts the TIM Base generation.
00412   * @param  htim TIM Base handle
00413   * @retval HAL status
00414   */
00415 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00416 {
00417   uint32_t tmpsmcr;
00418
00419   /* Check the parameters */
00420   assert_param(IS_TIM_INSTANCE(htim->Instance));
00421
00422   /* Check the TIM state */
00423   if (htim->State != HAL_TIM_STATE_READY)
00424   {
00425     return HAL_ERROR;
00426   }
00427
00428   /* Set the TIM state */
00429   htim->State = HAL_TIM_STATE_BUSY;
00430
00431   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00432   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00433   {
00434     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00435     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00436     {
00437       __HAL_TIM_ENABLE(htim);
00438     }
00439   }
00440   else
00441   {
00442     __HAL_TIM_ENABLE(htim);
00443   }
00444
00445   /* Return function status */
00446   return HAL_OK;
00447 }
00448
00449 /**
00450   * @brief  Stops the TIM Base generation.
00451   * @param  htim TIM Base handle
00452   * @retval HAL status
00453   */
00454 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00455 {
00456   /* Check the parameters */
00457   assert_param(IS_TIM_INSTANCE(htim->Instance));
00458
00459   /* Disable the Peripheral */
00460   __HAL_TIM_DISABLE(htim);
00461
00462   /* Set the TIM state */
00463   htim->State = HAL_TIM_STATE_READY;
00464
00465   /* Return function status */
00466   return HAL_OK;
00467 }
00468
00469 /**
00470   * @brief  Starts the TIM Base generation in interrupt mode.
00471   * @param  htim TIM Base handle
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00475 {
00476   uint32_t tmpsmcr;
00477
00478   /* Check the parameters */
00479   assert_param(IS_TIM_INSTANCE(htim->Instance));
00480
00481   /* Check the TIM state */
00482   if (htim->State != HAL_TIM_STATE_READY)
00483   {
00484     return HAL_ERROR;
00485   }
00486
00487   /* Set the TIM state */
00488   htim->State = HAL_TIM_STATE_BUSY;
00489
00490   /* Enable the TIM Update interrupt */
00491   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00492
00493   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00494   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00495   {
00496     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00497     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00498     {
00499       __HAL_TIM_ENABLE(htim);
00500     }
00501   }
00502   else
00503   {
00504     __HAL_TIM_ENABLE(htim);
00505   }
00506
00507   /* Return function status */
00508   return HAL_OK;
00509 }
00510
00511 /**
00512   * @brief  Stops the TIM Base generation in interrupt mode.
00513   * @param  htim TIM Base handle
00514   * @retval HAL status
00515   */
00516 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00517 {
00518   /* Check the parameters */
00519   assert_param(IS_TIM_INSTANCE(htim->Instance));
00520
00521   /* Disable the TIM Update interrupt */
00522   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00523
00524   /* Disable the Peripheral */
00525   __HAL_TIM_DISABLE(htim);
00526
00527   /* Set the TIM state */
00528   htim->State = HAL_TIM_STATE_READY;
00529
00530   /* Return function status */
00531   return HAL_OK;
00532 }
00533
00534 /**
00535   * @brief  Starts the TIM Base generation in DMA mode.
00536   * @param  htim TIM Base handle
00537   * @param  pData The source Buffer address.
00538   * @param  Length The length of data to be transferred from memory to peripheral.
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
00542 {
00543   uint32_t tmpsmcr;
00544
00545   /* Check the parameters */
00546   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00547
00548   /* Set the TIM state */
00549   if (htim->State == HAL_TIM_STATE_BUSY)
00550   {
00551     return HAL_BUSY;
00552   }
00553   else if (htim->State == HAL_TIM_STATE_READY)
00554   {
00555     if ((pData == NULL) || (Length == 0U))
00556     {
00557       return HAL_ERROR;
00558     }
00559     else
00560     {
00561       htim->State = HAL_TIM_STATE_BUSY;
00562     }
00563   }
00564   else
00565   {
00566     return HAL_ERROR;
00567   }
00568
00569   /* Set the DMA Period elapsed callbacks */
00570   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00571   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
00572
00573   /* Set the DMA error callback */
00574   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00575
00576   /* Enable the DMA channel */
00577   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
00578                        Length) != HAL_OK)
00579   {
00580     /* Return error status */
00581     return HAL_ERROR;
00582   }
00583
00584   /* Enable the TIM Update DMA request */
00585   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00586
00587   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00588   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00589   {
00590     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00591     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00592     {
00593       __HAL_TIM_ENABLE(htim);
00594     }
00595   }
00596   else
00597   {
00598     __HAL_TIM_ENABLE(htim);
00599   }
00600
00601   /* Return function status */
00602   return HAL_OK;
00603 }
00604
00605 /**
00606   * @brief  Stops the TIM Base generation in DMA mode.
00607   * @param  htim TIM Base handle
00608   * @retval HAL status
00609   */
00610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00611 {
00612   /* Check the parameters */
00613   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00614
00615   /* Disable the TIM Update DMA request */
00616   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00617
00618   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
00619
00620   /* Disable the Peripheral */
00621   __HAL_TIM_DISABLE(htim);
00622
00623   /* Set the TIM state */
00624   htim->State = HAL_TIM_STATE_READY;
00625
00626   /* Return function status */
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @}
00632   */
00633
00634 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
00635   *  @brief    TIM Output Compare functions
00636   *
00637 @verbatim
00638   ==============================================================================
00639                   ##### TIM Output Compare functions #####
00640   ==============================================================================
00641   [..]
00642     This section provides functions allowing to:
00643     (+) Initialize and configure the TIM Output Compare.
00644     (+) De-initialize the TIM Output Compare.
00645     (+) Start the TIM Output Compare.
00646     (+) Stop the TIM Output Compare.
00647     (+) Start the TIM Output Compare and enable interrupt.
00648     (+) Stop the TIM Output Compare and disable interrupt.
00649     (+) Start the TIM Output Compare and enable DMA transfer.
00650     (+) Stop the TIM Output Compare and disable DMA transfer.
00651
00652 @endverbatim
00653   * @{
00654   */
00655 /**
00656   * @brief  Initializes the TIM Output Compare according to the specified
00657   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
00658   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00659   *         requires a timer reset to avoid unexpected direction
00660   *         due to DIR bit readonly in center aligned mode.
00661   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
00662   * @param  htim TIM Output Compare handle
00663   * @retval HAL status
00664   */
00665 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
00666 {
00667   /* Check the TIM handle allocation */
00668   if (htim == NULL)
00669   {
00670     return HAL_ERROR;
00671   }
00672
00673   /* Check the parameters */
00674   assert_param(IS_TIM_INSTANCE(htim->Instance));
00675   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00676   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00677   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00678   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00679
00680   if (htim->State == HAL_TIM_STATE_RESET)
00681   {
00682     /* Allocate lock resource and initialize it */
00683     htim->Lock = HAL_UNLOCKED;
00684
00685 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00686     /* Reset interrupt callbacks to legacy weak callbacks */
00687     TIM_ResetCallback(htim);
00688
00689     if (htim->OC_MspInitCallback == NULL)
00690     {
00691       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
00692     }
00693     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00694     htim->OC_MspInitCallback(htim);
00695 #else
00696     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00697     HAL_TIM_OC_MspInit(htim);
00698 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00699   }
00700
00701   /* Set the TIM state */
00702   htim->State = HAL_TIM_STATE_BUSY;
00703
00704   /* Init the base time for the Output Compare */
00705   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00706
00707   /* Initialize the DMA burst operation state */
00708   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00709
00710   /* Initialize the TIM channels state */
00711   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00712   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00713
00714   /* Initialize the TIM state*/
00715   htim->State = HAL_TIM_STATE_READY;
00716
00717   return HAL_OK;
00718 }
00719
00720 /**
00721   * @brief  DeInitializes the TIM peripheral
00722   * @param  htim TIM Output Compare handle
00723   * @retval HAL status
00724   */
00725 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00726 {
00727   /* Check the parameters */
00728   assert_param(IS_TIM_INSTANCE(htim->Instance));
00729
00730   htim->State = HAL_TIM_STATE_BUSY;
00731
00732   /* Disable the TIM Peripheral Clock */
00733   __HAL_TIM_DISABLE(htim);
00734
00735 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00736   if (htim->OC_MspDeInitCallback == NULL)
00737   {
00738     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
00739   }
00740   /* DeInit the low level hardware */
00741   htim->OC_MspDeInitCallback(htim);
00742 #else
00743   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00744   HAL_TIM_OC_MspDeInit(htim);
00745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00746
00747   /* Change the DMA burst operation state */
00748   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00749
00750   /* Change the TIM channels state */
00751   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00752   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00753
00754   /* Change TIM state */
00755   htim->State = HAL_TIM_STATE_RESET;
00756
00757   /* Release Lock */
00758   __HAL_UNLOCK(htim);
00759
00760   return HAL_OK;
00761 }
00762
00763 /**
00764   * @brief  Initializes the TIM Output Compare MSP.
00765   * @param  htim TIM Output Compare handle
00766   * @retval None
00767   */
00768 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00769 {
00770   /* Prevent unused argument(s) compilation warning */
00771   UNUSED(htim);
00772
00773   /* NOTE : This function should not be modified, when the callback is needed,
00774             the HAL_TIM_OC_MspInit could be implemented in the user file
00775    */
00776 }
00777
00778 /**
00779   * @brief  DeInitializes TIM Output Compare MSP.
00780   * @param  htim TIM Output Compare handle
00781   * @retval None
00782   */
00783 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00784 {
00785   /* Prevent unused argument(s) compilation warning */
00786   UNUSED(htim);
00787
00788   /* NOTE : This function should not be modified, when the callback is needed,
00789             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00790    */
00791 }
00792
00793 /**
00794   * @brief  Starts the TIM Output Compare signal generation.
00795   * @param  htim TIM Output Compare handle
00796   * @param  Channel TIM Channel to be enabled
00797   *          This parameter can be one of the following values:
00798   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00799   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00800   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00801   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00802   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00803   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00804   * @retval HAL status
00805   */
00806 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00807 {
00808   uint32_t tmpsmcr;
00809
00810   /* Check the parameters */
00811   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00812
00813   /* Check the TIM channel state */
00814   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00815   {
00816     return HAL_ERROR;
00817   }
00818
00819   /* Set the TIM channel state */
00820   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00821
00822   /* Enable the Output compare channel */
00823   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00824
00825   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00826   {
00827     /* Enable the main output */
00828     __HAL_TIM_MOE_ENABLE(htim);
00829   }
00830
00831   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00832   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00833   {
00834     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00835     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00836     {
00837       __HAL_TIM_ENABLE(htim);
00838     }
00839   }
00840   else
00841   {
00842     __HAL_TIM_ENABLE(htim);
00843   }
00844
00845   /* Return function status */
00846   return HAL_OK;
00847 }
00848
00849 /**
00850   * @brief  Stops the TIM Output Compare signal generation.
00851   * @param  htim TIM Output Compare handle
00852   * @param  Channel TIM Channel to be disabled
00853   *          This parameter can be one of the following values:
00854   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00855   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00856   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00857   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00858   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00859   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00860   * @retval HAL status
00861   */
00862 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00863 {
00864   /* Check the parameters */
00865   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00866
00867   /* Disable the Output compare channel */
00868   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00869
00870   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00871   {
00872     /* Disable the Main Output */
00873     __HAL_TIM_MOE_DISABLE(htim);
00874   }
00875
00876   /* Disable the Peripheral */
00877   __HAL_TIM_DISABLE(htim);
00878
00879   /* Set the TIM channel state */
00880   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00881
00882   /* Return function status */
00883   return HAL_OK;
00884 }
00885
00886 /**
00887   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00888   * @param  htim TIM Output Compare handle
00889   * @param  Channel TIM Channel to be enabled
00890   *          This parameter can be one of the following values:
00891   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00892   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00893   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00894   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00895   * @retval HAL status
00896   */
00897 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00898 {
00899   HAL_StatusTypeDef status = HAL_OK;
00900   uint32_t tmpsmcr;
00901
00902   /* Check the parameters */
00903   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
00904
00905   /* Check the TIM channel state */
00906   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00907   {
00908     return HAL_ERROR;
00909   }
00910
00911   /* Set the TIM channel state */
00912   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00913
00914   switch (Channel)
00915   {
00916     case TIM_CHANNEL_1:
00917     {
00918       /* Enable the TIM Capture/Compare 1 interrupt */
00919       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00920       break;
00921     }
00922
00923     case TIM_CHANNEL_2:
00924     {
00925       /* Enable the TIM Capture/Compare 2 interrupt */
00926       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00927       break;
00928     }
00929
00930     case TIM_CHANNEL_3:
00931     {
00932       /* Enable the TIM Capture/Compare 3 interrupt */
00933       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00934       break;
00935     }
00936
00937     case TIM_CHANNEL_4:
00938     {
00939       /* Enable the TIM Capture/Compare 4 interrupt */
00940       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00941       break;
00942     }
00943
00944     default:
00945       status = HAL_ERROR;
00946       break;
00947   }
00948
00949   if (status == HAL_OK)
00950   {
00951     /* Enable the Output compare channel */
00952     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00953
00954     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00955     {
00956       /* Enable the main output */
00957       __HAL_TIM_MOE_ENABLE(htim);
00958     }
00959
00960     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00961     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00962     {
00963       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00964       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00965       {
00966         __HAL_TIM_ENABLE(htim);
00967       }
00968     }
00969     else
00970     {
00971       __HAL_TIM_ENABLE(htim);
00972     }
00973   }
00974
00975   /* Return function status */
00976   return status;
00977 }
00978
00979 /**
00980   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00981   * @param  htim TIM Output Compare handle
00982   * @param  Channel TIM Channel to be disabled
00983   *          This parameter can be one of the following values:
00984   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00985   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00986   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00987   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00988   * @retval HAL status
00989   */
00990 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00991 {
00992   HAL_StatusTypeDef status = HAL_OK;
00993
00994   /* Check the parameters */
00995   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
00996
00997   switch (Channel)
00998   {
00999     case TIM_CHANNEL_1:
01000     {
01001       /* Disable the TIM Capture/Compare 1 interrupt */
01002       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01003       break;
01004     }
01005
01006     case TIM_CHANNEL_2:
01007     {
01008       /* Disable the TIM Capture/Compare 2 interrupt */
01009       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01010       break;
01011     }
01012
01013     case TIM_CHANNEL_3:
01014     {
01015       /* Disable the TIM Capture/Compare 3 interrupt */
01016       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01017       break;
01018     }
01019
01020     case TIM_CHANNEL_4:
01021     {
01022       /* Disable the TIM Capture/Compare 4 interrupt */
01023       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01024       break;
01025     }
01026
01027     default:
01028       status = HAL_ERROR;
01029       break;
01030   }
01031
01032   if (status == HAL_OK)
01033   {
01034     /* Disable the Output compare channel */
01035     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01036
01037     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01038     {
01039       /* Disable the Main Output */
01040       __HAL_TIM_MOE_DISABLE(htim);
01041     }
01042
01043     /* Disable the Peripheral */
01044     __HAL_TIM_DISABLE(htim);
01045
01046     /* Set the TIM channel state */
01047     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01048   }
01049
01050   /* Return function status */
01051   return status;
01052 }
01053
01054 /**
01055   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
01056   * @param  htim TIM Output Compare handle
01057   * @param  Channel TIM Channel to be enabled
01058   *          This parameter can be one of the following values:
01059   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01060   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01061   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01062   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01063   * @param  pData The source Buffer address.
01064   * @param  Length The length of data to be transferred from memory to TIM peripheral
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01068                                        uint16_t Length)
01069 {
01070   HAL_StatusTypeDef status = HAL_OK;
01071   uint32_t tmpsmcr;
01072
01073   /* Check the parameters */
01074   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01075
01076   /* Set the TIM channel state */
01077   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01078   {
01079     return HAL_BUSY;
01080   }
01081   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01082   {
01083     if ((pData == NULL) || (Length == 0U))
01084     {
01085       return HAL_ERROR;
01086     }
01087     else
01088     {
01089       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01090     }
01091   }
01092   else
01093   {
01094     return HAL_ERROR;
01095   }
01096
01097   switch (Channel)
01098   {
01099     case TIM_CHANNEL_1:
01100     {
01101       /* Set the DMA compare callbacks */
01102       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01103       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01104
01105       /* Set the DMA error callback */
01106       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01107
01108       /* Enable the DMA channel */
01109       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01110                            Length) != HAL_OK)
01111       {
01112         /* Return error status */
01113         return HAL_ERROR;
01114       }
01115
01116       /* Enable the TIM Capture/Compare 1 DMA request */
01117       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01118       break;
01119     }
01120
01121     case TIM_CHANNEL_2:
01122     {
01123       /* Set the DMA compare callbacks */
01124       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01125       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01126
01127       /* Set the DMA error callback */
01128       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01129
01130       /* Enable the DMA channel */
01131       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01132                            Length) != HAL_OK)
01133       {
01134         /* Return error status */
01135         return HAL_ERROR;
01136       }
01137
01138       /* Enable the TIM Capture/Compare 2 DMA request */
01139       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01140       break;
01141     }
01142
01143     case TIM_CHANNEL_3:
01144     {
01145       /* Set the DMA compare callbacks */
01146       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01147       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01148
01149       /* Set the DMA error callback */
01150       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01151
01152       /* Enable the DMA channel */
01153       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01154                            Length) != HAL_OK)
01155       {
01156         /* Return error status */
01157         return HAL_ERROR;
01158       }
01159       /* Enable the TIM Capture/Compare 3 DMA request */
01160       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01161       break;
01162     }
01163
01164     case TIM_CHANNEL_4:
01165     {
01166       /* Set the DMA compare callbacks */
01167       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01168       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01169
01170       /* Set the DMA error callback */
01171       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01172
01173       /* Enable the DMA channel */
01174       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01175                            Length) != HAL_OK)
01176       {
01177         /* Return error status */
01178         return HAL_ERROR;
01179       }
01180       /* Enable the TIM Capture/Compare 4 DMA request */
01181       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01182       break;
01183     }
01184
01185     default:
01186       status = HAL_ERROR;
01187       break;
01188   }
01189
01190   if (status == HAL_OK)
01191   {
01192     /* Enable the Output compare channel */
01193     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01194
01195     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01196     {
01197       /* Enable the main output */
01198       __HAL_TIM_MOE_ENABLE(htim);
01199     }
01200
01201     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01202     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01203     {
01204       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01205       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01206       {
01207         __HAL_TIM_ENABLE(htim);
01208       }
01209     }
01210     else
01211     {
01212       __HAL_TIM_ENABLE(htim);
01213     }
01214   }
01215
01216   /* Return function status */
01217   return status;
01218 }
01219
01220 /**
01221   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
01222   * @param  htim TIM Output Compare handle
01223   * @param  Channel TIM Channel to be disabled
01224   *          This parameter can be one of the following values:
01225   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01226   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01227   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01228   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01229   * @retval HAL status
01230   */
01231 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01232 {
01233   HAL_StatusTypeDef status = HAL_OK;
01234
01235   /* Check the parameters */
01236   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01237
01238   switch (Channel)
01239   {
01240     case TIM_CHANNEL_1:
01241     {
01242       /* Disable the TIM Capture/Compare 1 DMA request */
01243       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01244       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01245       break;
01246     }
01247
01248     case TIM_CHANNEL_2:
01249     {
01250       /* Disable the TIM Capture/Compare 2 DMA request */
01251       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01252       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01253       break;
01254     }
01255
01256     case TIM_CHANNEL_3:
01257     {
01258       /* Disable the TIM Capture/Compare 3 DMA request */
01259       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01260       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01261       break;
01262     }
01263
01264     case TIM_CHANNEL_4:
01265     {
01266       /* Disable the TIM Capture/Compare 4 interrupt */
01267       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01268       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01269       break;
01270     }
01271
01272     default:
01273       status = HAL_ERROR;
01274       break;
01275   }
01276
01277   if (status == HAL_OK)
01278   {
01279     /* Disable the Output compare channel */
01280     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01281
01282     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01283     {
01284       /* Disable the Main Output */
01285       __HAL_TIM_MOE_DISABLE(htim);
01286     }
01287
01288     /* Disable the Peripheral */
01289     __HAL_TIM_DISABLE(htim);
01290
01291     /* Set the TIM channel state */
01292     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01293   }
01294
01295   /* Return function status */
01296   return status;
01297 }
01298
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
01304   *  @brief    TIM PWM functions
01305   *
01306 @verbatim
01307   ==============================================================================
01308                           ##### TIM PWM functions #####
01309   ==============================================================================
01310   [..]
01311     This section provides functions allowing to:
01312     (+) Initialize and configure the TIM PWM.
01313     (+) De-initialize the TIM PWM.
01314     (+) Start the TIM PWM.
01315     (+) Stop the TIM PWM.
01316     (+) Start the TIM PWM and enable interrupt.
01317     (+) Stop the TIM PWM and disable interrupt.
01318     (+) Start the TIM PWM and enable DMA transfer.
01319     (+) Stop the TIM PWM and disable DMA transfer.
01320
01321 @endverbatim
01322   * @{
01323   */
01324 /**
01325   * @brief  Initializes the TIM PWM Time Base according to the specified
01326   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01327   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01328   *         requires a timer reset to avoid unexpected direction
01329   *         due to DIR bit readonly in center aligned mode.
01330   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
01331   * @param  htim TIM PWM handle
01332   * @retval HAL status
01333   */
01334 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01335 {
01336   /* Check the TIM handle allocation */
01337   if (htim == NULL)
01338   {
01339     return HAL_ERROR;
01340   }
01341
01342   /* Check the parameters */
01343   assert_param(IS_TIM_INSTANCE(htim->Instance));
01344   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01345   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01346   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
01347   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01348
01349   if (htim->State == HAL_TIM_STATE_RESET)
01350   {
01351     /* Allocate lock resource and initialize it */
01352     htim->Lock = HAL_UNLOCKED;
01353
01354 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01355     /* Reset interrupt callbacks to legacy weak callbacks */
01356     TIM_ResetCallback(htim);
01357
01358     if (htim->PWM_MspInitCallback == NULL)
01359     {
01360       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
01361     }
01362     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01363     htim->PWM_MspInitCallback(htim);
01364 #else
01365     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01366     HAL_TIM_PWM_MspInit(htim);
01367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01368   }
01369
01370   /* Set the TIM state */
01371   htim->State = HAL_TIM_STATE_BUSY;
01372
01373   /* Init the base time for the PWM */
01374   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01375
01376   /* Initialize the DMA burst operation state */
01377   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
01378
01379   /* Initialize the TIM channels state */
01380   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
01381   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
01382
01383   /* Initialize the TIM state*/
01384   htim->State = HAL_TIM_STATE_READY;
01385
01386   return HAL_OK;
01387 }
01388
01389 /**
01390   * @brief  DeInitializes the TIM peripheral
01391   * @param  htim TIM PWM handle
01392   * @retval HAL status
01393   */
01394 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01395 {
01396   /* Check the parameters */
01397   assert_param(IS_TIM_INSTANCE(htim->Instance));
01398
01399   htim->State = HAL_TIM_STATE_BUSY;
01400
01401   /* Disable the TIM Peripheral Clock */
01402   __HAL_TIM_DISABLE(htim);
01403
01404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01405   if (htim->PWM_MspDeInitCallback == NULL)
01406   {
01407     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
01408   }
01409   /* DeInit the low level hardware */
01410   htim->PWM_MspDeInitCallback(htim);
01411 #else
01412   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01413   HAL_TIM_PWM_MspDeInit(htim);
01414 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01415
01416   /* Change the DMA burst operation state */
01417   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
01418
01419   /* Change the TIM channels state */
01420   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
01421   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
01422
01423   /* Change TIM state */
01424   htim->State = HAL_TIM_STATE_RESET;
01425
01426   /* Release Lock */
01427   __HAL_UNLOCK(htim);
01428
01429   return HAL_OK;
01430 }
01431
01432 /**
01433   * @brief  Initializes the TIM PWM MSP.
01434   * @param  htim TIM PWM handle
01435   * @retval None
01436   */
01437 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01438 {
01439   /* Prevent unused argument(s) compilation warning */
01440   UNUSED(htim);
01441
01442   /* NOTE : This function should not be modified, when the callback is needed,
01443             the HAL_TIM_PWM_MspInit could be implemented in the user file
01444    */
01445 }
01446
01447 /**
01448   * @brief  DeInitializes TIM PWM MSP.
01449   * @param  htim TIM PWM handle
01450   * @retval None
01451   */
01452 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01453 {
01454   /* Prevent unused argument(s) compilation warning */
01455   UNUSED(htim);
01456
01457   /* NOTE : This function should not be modified, when the callback is needed,
01458             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01459    */
01460 }
01461
01462 /**
01463   * @brief  Starts the PWM signal generation.
01464   * @param  htim TIM handle
01465   * @param  Channel TIM Channels to be enabled
01466   *          This parameter can be one of the following values:
01467   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01468   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01469   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01470   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01471   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01472   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01473   * @retval HAL status
01474   */
01475 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01476 {
01477   uint32_t tmpsmcr;
01478
01479   /* Check the parameters */
01480   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01481
01482   /* Check the TIM channel state */
01483   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01484   {
01485     return HAL_ERROR;
01486   }
01487
01488   /* Set the TIM channel state */
01489   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01490
01491   /* Enable the Capture compare channel */
01492   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01493
01494   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01495   {
01496     /* Enable the main output */
01497     __HAL_TIM_MOE_ENABLE(htim);
01498   }
01499
01500   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01501   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01502   {
01503     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01504     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01505     {
01506       __HAL_TIM_ENABLE(htim);
01507     }
01508   }
01509   else
01510   {
01511     __HAL_TIM_ENABLE(htim);
01512   }
01513
01514   /* Return function status */
01515   return HAL_OK;
01516 }
01517
01518 /**
01519   * @brief  Stops the PWM signal generation.
01520   * @param  htim TIM PWM handle
01521   * @param  Channel TIM Channels to be disabled
01522   *          This parameter can be one of the following values:
01523   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01524   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01525   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01526   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01527   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01528   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01529   * @retval HAL status
01530   */
01531 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01532 {
01533   /* Check the parameters */
01534   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01535
01536   /* Disable the Capture compare channel */
01537   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01538
01539   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01540   {
01541     /* Disable the Main Output */
01542     __HAL_TIM_MOE_DISABLE(htim);
01543   }
01544
01545   /* Disable the Peripheral */
01546   __HAL_TIM_DISABLE(htim);
01547
01548   /* Set the TIM channel state */
01549   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01550
01551   /* Return function status */
01552   return HAL_OK;
01553 }
01554
01555 /**
01556   * @brief  Starts the PWM signal generation in interrupt mode.
01557   * @param  htim TIM PWM handle
01558   * @param  Channel TIM Channel to be enabled
01559   *          This parameter can be one of the following values:
01560   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01561   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01562   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01563   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01564   * @retval HAL status
01565   */
01566 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01567 {
01568   HAL_StatusTypeDef status = HAL_OK;
01569   uint32_t tmpsmcr;
01570
01571   /* Check the parameters */
01572   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01573
01574   /* Check the TIM channel state */
01575   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01576   {
01577     return HAL_ERROR;
01578   }
01579
01580   /* Set the TIM channel state */
01581   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01582
01583   switch (Channel)
01584   {
01585     case TIM_CHANNEL_1:
01586     {
01587       /* Enable the TIM Capture/Compare 1 interrupt */
01588       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01589       break;
01590     }
01591
01592     case TIM_CHANNEL_2:
01593     {
01594       /* Enable the TIM Capture/Compare 2 interrupt */
01595       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01596       break;
01597     }
01598
01599     case TIM_CHANNEL_3:
01600     {
01601       /* Enable the TIM Capture/Compare 3 interrupt */
01602       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01603       break;
01604     }
01605
01606     case TIM_CHANNEL_4:
01607     {
01608       /* Enable the TIM Capture/Compare 4 interrupt */
01609       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01610       break;
01611     }
01612
01613     default:
01614       status = HAL_ERROR;
01615       break;
01616   }
01617
01618   if (status == HAL_OK)
01619   {
01620     /* Enable the Capture compare channel */
01621     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01622
01623     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01624     {
01625       /* Enable the main output */
01626       __HAL_TIM_MOE_ENABLE(htim);
01627     }
01628
01629     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01630     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01631     {
01632       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01633       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01634       {
01635         __HAL_TIM_ENABLE(htim);
01636       }
01637     }
01638     else
01639     {
01640       __HAL_TIM_ENABLE(htim);
01641     }
01642   }
01643
01644   /* Return function status */
01645   return status;
01646 }
01647
01648 /**
01649   * @brief  Stops the PWM signal generation in interrupt mode.
01650   * @param  htim TIM PWM handle
01651   * @param  Channel TIM Channels to be disabled
01652   *          This parameter can be one of the following values:
01653   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01654   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01655   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01656   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01657   * @retval HAL status
01658   */
01659 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01660 {
01661   HAL_StatusTypeDef status = HAL_OK;
01662
01663   /* Check the parameters */
01664   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01665
01666   switch (Channel)
01667   {
01668     case TIM_CHANNEL_1:
01669     {
01670       /* Disable the TIM Capture/Compare 1 interrupt */
01671       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01672       break;
01673     }
01674
01675     case TIM_CHANNEL_2:
01676     {
01677       /* Disable the TIM Capture/Compare 2 interrupt */
01678       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01679       break;
01680     }
01681
01682     case TIM_CHANNEL_3:
01683     {
01684       /* Disable the TIM Capture/Compare 3 interrupt */
01685       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01686       break;
01687     }
01688
01689     case TIM_CHANNEL_4:
01690     {
01691       /* Disable the TIM Capture/Compare 4 interrupt */
01692       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01693       break;
01694     }
01695
01696     default:
01697       status = HAL_ERROR;
01698       break;
01699   }
01700
01701   if (status == HAL_OK)
01702   {
01703     /* Disable the Capture compare channel */
01704     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01705
01706     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01707     {
01708       /* Disable the Main Output */
01709       __HAL_TIM_MOE_DISABLE(htim);
01710     }
01711
01712     /* Disable the Peripheral */
01713     __HAL_TIM_DISABLE(htim);
01714
01715     /* Set the TIM channel state */
01716     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01717   }
01718
01719   /* Return function status */
01720   return status;
01721 }
01722
01723 /**
01724   * @brief  Starts the TIM PWM signal generation in DMA mode.
01725   * @param  htim TIM PWM handle
01726   * @param  Channel TIM Channels to be enabled
01727   *          This parameter can be one of the following values:
01728   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01729   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01730   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01731   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01732   * @param  pData The source Buffer address.
01733   * @param  Length The length of data to be transferred from memory to TIM peripheral
01734   * @retval HAL status
01735   */
01736 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01737                                         uint16_t Length)
01738 {
01739   HAL_StatusTypeDef status = HAL_OK;
01740   uint32_t tmpsmcr;
01741
01742   /* Check the parameters */
01743   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01744
01745   /* Set the TIM channel state */
01746   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01747   {
01748     return HAL_BUSY;
01749   }
01750   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01751   {
01752     if ((pData == NULL) || (Length == 0U))
01753     {
01754       return HAL_ERROR;
01755     }
01756     else
01757     {
01758       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01759     }
01760   }
01761   else
01762   {
01763     return HAL_ERROR;
01764   }
01765
01766   switch (Channel)
01767   {
01768     case TIM_CHANNEL_1:
01769     {
01770       /* Set the DMA compare callbacks */
01771       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01772       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01773
01774       /* Set the DMA error callback */
01775       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01776
01777       /* Enable the DMA channel */
01778       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01779                            Length) != HAL_OK)
01780       {
01781         /* Return error status */
01782         return HAL_ERROR;
01783       }
01784
01785       /* Enable the TIM Capture/Compare 1 DMA request */
01786       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01787       break;
01788     }
01789
01790     case TIM_CHANNEL_2:
01791     {
01792       /* Set the DMA compare callbacks */
01793       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01794       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01795
01796       /* Set the DMA error callback */
01797       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01798
01799       /* Enable the DMA channel */
01800       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01801                            Length) != HAL_OK)
01802       {
01803         /* Return error status */
01804         return HAL_ERROR;
01805       }
01806       /* Enable the TIM Capture/Compare 2 DMA request */
01807       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01808       break;
01809     }
01810
01811     case TIM_CHANNEL_3:
01812     {
01813       /* Set the DMA compare callbacks */
01814       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01815       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01816
01817       /* Set the DMA error callback */
01818       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01819
01820       /* Enable the DMA channel */
01821       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01822                            Length) != HAL_OK)
01823       {
01824         /* Return error status */
01825         return HAL_ERROR;
01826       }
01827       /* Enable the TIM Output Capture/Compare 3 request */
01828       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01829       break;
01830     }
01831
01832     case TIM_CHANNEL_4:
01833     {
01834       /* Set the DMA compare callbacks */
01835       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01836       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01837
01838       /* Set the DMA error callback */
01839       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01840
01841       /* Enable the DMA channel */
01842       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01843                            Length) != HAL_OK)
01844       {
01845         /* Return error status */
01846         return HAL_ERROR;
01847       }
01848       /* Enable the TIM Capture/Compare 4 DMA request */
01849       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01850       break;
01851     }
01852
01853     default:
01854       status = HAL_ERROR;
01855       break;
01856   }
01857
01858   if (status == HAL_OK)
01859   {
01860     /* Enable the Capture compare channel */
01861     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01862
01863     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01864     {
01865       /* Enable the main output */
01866       __HAL_TIM_MOE_ENABLE(htim);
01867     }
01868
01869     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01870     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01871     {
01872       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01873       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01874       {
01875         __HAL_TIM_ENABLE(htim);
01876       }
01877     }
01878     else
01879     {
01880       __HAL_TIM_ENABLE(htim);
01881     }
01882   }
01883
01884   /* Return function status */
01885   return status;
01886 }
01887
01888 /**
01889   * @brief  Stops the TIM PWM signal generation in DMA mode.
01890   * @param  htim TIM PWM handle
01891   * @param  Channel TIM Channels to be disabled
01892   *          This parameter can be one of the following values:
01893   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01894   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01895   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01896   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01897   * @retval HAL status
01898   */
01899 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01900 {
01901   HAL_StatusTypeDef status = HAL_OK;
01902
01903   /* Check the parameters */
01904   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
01905
01906   switch (Channel)
01907   {
01908     case TIM_CHANNEL_1:
01909     {
01910       /* Disable the TIM Capture/Compare 1 DMA request */
01911       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01912       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01913       break;
01914     }
01915
01916     case TIM_CHANNEL_2:
01917     {
01918       /* Disable the TIM Capture/Compare 2 DMA request */
01919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01920       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01921       break;
01922     }
01923
01924     case TIM_CHANNEL_3:
01925     {
01926       /* Disable the TIM Capture/Compare 3 DMA request */
01927       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01928       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01929       break;
01930     }
01931
01932     case TIM_CHANNEL_4:
01933     {
01934       /* Disable the TIM Capture/Compare 4 interrupt */
01935       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01936       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01937       break;
01938     }
01939
01940     default:
01941       status = HAL_ERROR;
01942       break;
01943   }
01944
01945   if (status == HAL_OK)
01946   {
01947     /* Disable the Capture compare channel */
01948     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01949
01950     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01951     {
01952       /* Disable the Main Output */
01953       __HAL_TIM_MOE_DISABLE(htim);
01954     }
01955
01956     /* Disable the Peripheral */
01957     __HAL_TIM_DISABLE(htim);
01958
01959     /* Set the TIM channel state */
01960     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01961   }
01962
01963   /* Return function status */
01964   return status;
01965 }
01966
01967 /**
01968   * @}
01969   */
01970
01971 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
01972   *  @brief    TIM Input Capture functions
01973   *
01974 @verbatim
01975   ==============================================================================
01976               ##### TIM Input Capture functions #####
01977   ==============================================================================
01978  [..]
01979    This section provides functions allowing to:
01980    (+) Initialize and configure the TIM Input Capture.
01981    (+) De-initialize the TIM Input Capture.
01982    (+) Start the TIM Input Capture.
01983    (+) Stop the TIM Input Capture.
01984    (+) Start the TIM Input Capture and enable interrupt.
01985    (+) Stop the TIM Input Capture and disable interrupt.
01986    (+) Start the TIM Input Capture and enable DMA transfer.
01987    (+) Stop the TIM Input Capture and disable DMA transfer.
01988
01989 @endverbatim
01990   * @{
01991   */
01992 /**
01993   * @brief  Initializes the TIM Input Capture Time base according to the specified
01994   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01995   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01996   *         requires a timer reset to avoid unexpected direction
01997   *         due to DIR bit readonly in center aligned mode.
01998   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
01999   * @param  htim TIM Input Capture handle
02000   * @retval HAL status
02001   */
02002 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
02003 {
02004   /* Check the TIM handle allocation */
02005   if (htim == NULL)
02006   {
02007     return HAL_ERROR;
02008   }
02009
02010   /* Check the parameters */
02011   assert_param(IS_TIM_INSTANCE(htim->Instance));
02012   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02013   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02014   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
02015   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02016
02017   if (htim->State == HAL_TIM_STATE_RESET)
02018   {
02019     /* Allocate lock resource and initialize it */
02020     htim->Lock = HAL_UNLOCKED;
02021
02022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02023     /* Reset interrupt callbacks to legacy weak callbacks */
02024     TIM_ResetCallback(htim);
02025
02026     if (htim->IC_MspInitCallback == NULL)
02027     {
02028       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
02029     }
02030     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02031     htim->IC_MspInitCallback(htim);
02032 #else
02033     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02034     HAL_TIM_IC_MspInit(htim);
02035 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02036   }
02037
02038   /* Set the TIM state */
02039   htim->State = HAL_TIM_STATE_BUSY;
02040
02041   /* Init the base time for the input capture */
02042   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02043
02044   /* Initialize the DMA burst operation state */
02045   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
02046
02047   /* Initialize the TIM channels state */
02048   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
02049   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
02050
02051   /* Initialize the TIM state*/
02052   htim->State = HAL_TIM_STATE_READY;
02053
02054   return HAL_OK;
02055 }
02056
02057 /**
02058   * @brief  DeInitializes the TIM peripheral
02059   * @param  htim TIM Input Capture handle
02060   * @retval HAL status
02061   */
02062 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
02063 {
02064   /* Check the parameters */
02065   assert_param(IS_TIM_INSTANCE(htim->Instance));
02066
02067   htim->State = HAL_TIM_STATE_BUSY;
02068
02069   /* Disable the TIM Peripheral Clock */
02070   __HAL_TIM_DISABLE(htim);
02071
02072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02073   if (htim->IC_MspDeInitCallback == NULL)
02074   {
02075     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
02076   }
02077   /* DeInit the low level hardware */
02078   htim->IC_MspDeInitCallback(htim);
02079 #else
02080   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
02081   HAL_TIM_IC_MspDeInit(htim);
02082 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02083
02084   /* Change the DMA burst operation state */
02085   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
02086
02087   /* Change the TIM channels state */
02088   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
02089   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
02090
02091   /* Change TIM state */
02092   htim->State = HAL_TIM_STATE_RESET;
02093
02094   /* Release Lock */
02095   __HAL_UNLOCK(htim);
02096
02097   return HAL_OK;
02098 }
02099
02100 /**
02101   * @brief  Initializes the TIM Input Capture MSP.
02102   * @param  htim TIM Input Capture handle
02103   * @retval None
02104   */
02105 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
02106 {
02107   /* Prevent unused argument(s) compilation warning */
02108   UNUSED(htim);
02109
02110   /* NOTE : This function should not be modified, when the callback is needed,
02111             the HAL_TIM_IC_MspInit could be implemented in the user file
02112    */
02113 }
02114
02115 /**
02116   * @brief  DeInitializes TIM Input Capture MSP.
02117   * @param  htim TIM handle
02118   * @retval None
02119   */
02120 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
02121 {
02122   /* Prevent unused argument(s) compilation warning */
02123   UNUSED(htim);
02124
02125   /* NOTE : This function should not be modified, when the callback is needed,
02126             the HAL_TIM_IC_MspDeInit could be implemented in the user file
02127    */
02128 }
02129
02130 /**
02131   * @brief  Starts the TIM Input Capture measurement.
02132   * @param  htim TIM Input Capture handle
02133   * @param  Channel TIM Channels to be enabled
02134   *          This parameter can be one of the following values:
02135   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02136   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02137   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02138   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02139   * @retval HAL status
02140   */
02141 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02142 {
02143   uint32_t tmpsmcr;
02144   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02145   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02146
02147   /* Check the parameters */
02148   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02149
02150   /* Check the TIM channel state */
02151   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
02152       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
02153   {
02154     return HAL_ERROR;
02155   }
02156
02157   /* Set the TIM channel state */
02158   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02159   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02160
02161   /* Enable the Input Capture channel */
02162   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02163
02164   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02165   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02166   {
02167     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02168     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02169     {
02170       __HAL_TIM_ENABLE(htim);
02171     }
02172   }
02173   else
02174   {
02175     __HAL_TIM_ENABLE(htim);
02176   }
02177
02178   /* Return function status */
02179   return HAL_OK;
02180 }
02181
02182 /**
02183   * @brief  Stops the TIM Input Capture measurement.
02184   * @param  htim TIM Input Capture handle
02185   * @param  Channel TIM Channels to be disabled
02186   *          This parameter can be one of the following values:
02187   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02188   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02189   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02190   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02191   * @retval HAL status
02192   */
02193 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02194 {
02195   /* Check the parameters */
02196   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02197
02198   /* Disable the Input Capture channel */
02199   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02200
02201   /* Disable the Peripheral */
02202   __HAL_TIM_DISABLE(htim);
02203
02204   /* Set the TIM channel state */
02205   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02206   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02207
02208   /* Return function status */
02209   return HAL_OK;
02210 }
02211
02212 /**
02213   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
02214   * @param  htim TIM Input Capture handle
02215   * @param  Channel TIM Channels to be enabled
02216   *          This parameter can be one of the following values:
02217   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02218   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02219   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02220   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02221   * @retval HAL status
02222   */
02223 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02224 {
02225   HAL_StatusTypeDef status = HAL_OK;
02226   uint32_t tmpsmcr;
02227
02228   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02229   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02230
02231   /* Check the parameters */
02232   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02233
02234   /* Check the TIM channel state */
02235   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
02236       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
02237   {
02238     return HAL_ERROR;
02239   }
02240
02241   /* Set the TIM channel state */
02242   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02243   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02244
02245   switch (Channel)
02246   {
02247     case TIM_CHANNEL_1:
02248     {
02249       /* Enable the TIM Capture/Compare 1 interrupt */
02250       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02251       break;
02252     }
02253
02254     case TIM_CHANNEL_2:
02255     {
02256       /* Enable the TIM Capture/Compare 2 interrupt */
02257       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02258       break;
02259     }
02260
02261     case TIM_CHANNEL_3:
02262     {
02263       /* Enable the TIM Capture/Compare 3 interrupt */
02264       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
02265       break;
02266     }
02267
02268     case TIM_CHANNEL_4:
02269     {
02270       /* Enable the TIM Capture/Compare 4 interrupt */
02271       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
02272       break;
02273     }
02274
02275     default:
02276       status = HAL_ERROR;
02277       break;
02278   }
02279
02280   if (status == HAL_OK)
02281   {
02282     /* Enable the Input Capture channel */
02283     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02284
02285     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02286     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02287     {
02288       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02289       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02290       {
02291         __HAL_TIM_ENABLE(htim);
02292       }
02293     }
02294     else
02295     {
02296       __HAL_TIM_ENABLE(htim);
02297     }
02298   }
02299
02300   /* Return function status */
02301   return status;
02302 }
02303
02304 /**
02305   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
02306   * @param  htim TIM Input Capture handle
02307   * @param  Channel TIM Channels to be disabled
02308   *          This parameter can be one of the following values:
02309   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02310   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02311   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02312   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02313   * @retval HAL status
02314   */
02315 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02316 {
02317   HAL_StatusTypeDef status = HAL_OK;
02318
02319   /* Check the parameters */
02320   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02321
02322   switch (Channel)
02323   {
02324     case TIM_CHANNEL_1:
02325     {
02326       /* Disable the TIM Capture/Compare 1 interrupt */
02327       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02328       break;
02329     }
02330
02331     case TIM_CHANNEL_2:
02332     {
02333       /* Disable the TIM Capture/Compare 2 interrupt */
02334       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02335       break;
02336     }
02337
02338     case TIM_CHANNEL_3:
02339     {
02340       /* Disable the TIM Capture/Compare 3 interrupt */
02341       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
02342       break;
02343     }
02344
02345     case TIM_CHANNEL_4:
02346     {
02347       /* Disable the TIM Capture/Compare 4 interrupt */
02348       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
02349       break;
02350     }
02351
02352     default:
02353       status = HAL_ERROR;
02354       break;
02355   }
02356
02357   if (status == HAL_OK)
02358   {
02359     /* Disable the Input Capture channel */
02360     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02361
02362     /* Disable the Peripheral */
02363     __HAL_TIM_DISABLE(htim);
02364
02365     /* Set the TIM channel state */
02366     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02367     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02368   }
02369
02370   /* Return function status */
02371   return status;
02372 }
02373
02374 /**
02375   * @brief  Starts the TIM Input Capture measurement in DMA mode.
02376   * @param  htim TIM Input Capture handle
02377   * @param  Channel TIM Channels to be enabled
02378   *          This parameter can be one of the following values:
02379   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02380   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02381   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02382   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02383   * @param  pData The destination Buffer address.
02384   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02385   * @retval HAL status
02386   */
02387 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
02388 {
02389   HAL_StatusTypeDef status = HAL_OK;
02390   uint32_t tmpsmcr;
02391
02392   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02393   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02394
02395   /* Check the parameters */
02396   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02397   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02398
02399   /* Set the TIM channel state */
02400   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
02401       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
02402   {
02403     return HAL_BUSY;
02404   }
02405   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
02406            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
02407   {
02408     if ((pData == NULL) || (Length == 0U))
02409     {
02410       return HAL_ERROR;
02411     }
02412     else
02413     {
02414       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02415       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02416     }
02417   }
02418   else
02419   {
02420     return HAL_ERROR;
02421   }
02422
02423   /* Enable the Input Capture channel */
02424   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02425
02426   switch (Channel)
02427   {
02428     case TIM_CHANNEL_1:
02429     {
02430       /* Set the DMA capture callbacks */
02431       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02432       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02433
02434       /* Set the DMA error callback */
02435       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02436
02437       /* Enable the DMA channel */
02438       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
02439                            Length) != HAL_OK)
02440       {
02441         /* Return error status */
02442         return HAL_ERROR;
02443       }
02444       /* Enable the TIM Capture/Compare 1 DMA request */
02445       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02446       break;
02447     }
02448
02449     case TIM_CHANNEL_2:
02450     {
02451       /* Set the DMA capture callbacks */
02452       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02453       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02454
02455       /* Set the DMA error callback */
02456       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02457
02458       /* Enable the DMA channel */
02459       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
02460                            Length) != HAL_OK)
02461       {
02462         /* Return error status */
02463         return HAL_ERROR;
02464       }
02465       /* Enable the TIM Capture/Compare 2  DMA request */
02466       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02467       break;
02468     }
02469
02470     case TIM_CHANNEL_3:
02471     {
02472       /* Set the DMA capture callbacks */
02473       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
02474       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02475
02476       /* Set the DMA error callback */
02477       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
02478
02479       /* Enable the DMA channel */
02480       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
02481                            Length) != HAL_OK)
02482       {
02483         /* Return error status */
02484         return HAL_ERROR;
02485       }
02486       /* Enable the TIM Capture/Compare 3  DMA request */
02487       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
02488       break;
02489     }
02490
02491     case TIM_CHANNEL_4:
02492     {
02493       /* Set the DMA capture callbacks */
02494       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
02495       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02496
02497       /* Set the DMA error callback */
02498       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
02499
02500       /* Enable the DMA channel */
02501       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
02502                            Length) != HAL_OK)
02503       {
02504         /* Return error status */
02505         return HAL_ERROR;
02506       }
02507       /* Enable the TIM Capture/Compare 4  DMA request */
02508       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
02509       break;
02510     }
02511
02512     default:
02513       status = HAL_ERROR;
02514       break;
02515   }
02516
02517   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02518   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02519   {
02520     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02521     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02522     {
02523       __HAL_TIM_ENABLE(htim);
02524     }
02525   }
02526   else
02527   {
02528     __HAL_TIM_ENABLE(htim);
02529   }
02530
02531   /* Return function status */
02532   return status;
02533 }
02534
02535 /**
02536   * @brief  Stops the TIM Input Capture measurement in DMA mode.
02537   * @param  htim TIM Input Capture handle
02538   * @param  Channel TIM Channels to be disabled
02539   *          This parameter can be one of the following values:
02540   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02541   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02542   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02543   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02544   * @retval HAL status
02545   */
02546 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02547 {
02548   HAL_StatusTypeDef status = HAL_OK;
02549
02550   /* Check the parameters */
02551   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
02552   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02553
02554   /* Disable the Input Capture channel */
02555   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02556
02557   switch (Channel)
02558   {
02559     case TIM_CHANNEL_1:
02560     {
02561       /* Disable the TIM Capture/Compare 1 DMA request */
02562       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02563       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
02564       break;
02565     }
02566
02567     case TIM_CHANNEL_2:
02568     {
02569       /* Disable the TIM Capture/Compare 2 DMA request */
02570       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02571       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
02572       break;
02573     }
02574
02575     case TIM_CHANNEL_3:
02576     {
02577       /* Disable the TIM Capture/Compare 3  DMA request */
02578       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
02579       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
02580       break;
02581     }
02582
02583     case TIM_CHANNEL_4:
02584     {
02585       /* Disable the TIM Capture/Compare 4  DMA request */
02586       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
02587       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
02588       break;
02589     }
02590
02591     default:
02592       status = HAL_ERROR;
02593       break;
02594   }
02595
02596   if (status == HAL_OK)
02597   {
02598     /* Disable the Peripheral */
02599     __HAL_TIM_DISABLE(htim);
02600
02601     /* Set the TIM channel state */
02602     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02603     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02604   }
02605
02606   /* Return function status */
02607   return status;
02608 }
02609 /**
02610   * @}
02611   */
02612
02613 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02614   *  @brief    TIM One Pulse functions
02615   *
02616 @verbatim
02617   ==============================================================================
02618                         ##### TIM One Pulse functions #####
02619   ==============================================================================
02620   [..]
02621     This section provides functions allowing to:
02622     (+) Initialize and configure the TIM One Pulse.
02623     (+) De-initialize the TIM One Pulse.
02624     (+) Start the TIM One Pulse.
02625     (+) Stop the TIM One Pulse.
02626     (+) Start the TIM One Pulse and enable interrupt.
02627     (+) Stop the TIM One Pulse and disable interrupt.
02628     (+) Start the TIM One Pulse and enable DMA transfer.
02629     (+) Stop the TIM One Pulse and disable DMA transfer.
02630
02631 @endverbatim
02632   * @{
02633   */
02634 /**
02635   * @brief  Initializes the TIM One Pulse Time Base according to the specified
02636   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
02637   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02638   *         requires a timer reset to avoid unexpected direction
02639   *         due to DIR bit readonly in center aligned mode.
02640   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
02641   * @note   When the timer instance is initialized in One Pulse mode, timer
02642   *         channels 1 and channel 2 are reserved and cannot be used for other
02643   *         purpose.
02644   * @param  htim TIM One Pulse handle
02645   * @param  OnePulseMode Select the One pulse mode.
02646   *         This parameter can be one of the following values:
02647   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
02648   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
02649   * @retval HAL status
02650   */
02651 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02652 {
02653   /* Check the TIM handle allocation */
02654   if (htim == NULL)
02655   {
02656     return HAL_ERROR;
02657   }
02658
02659   /* Check the parameters */
02660   assert_param(IS_TIM_INSTANCE(htim->Instance));
02661   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02662   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02663   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02664   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
02665   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02666
02667   if (htim->State == HAL_TIM_STATE_RESET)
02668   {
02669     /* Allocate lock resource and initialize it */
02670     htim->Lock = HAL_UNLOCKED;
02671
02672 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02673     /* Reset interrupt callbacks to legacy weak callbacks */
02674     TIM_ResetCallback(htim);
02675
02676     if (htim->OnePulse_MspInitCallback == NULL)
02677     {
02678       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
02679     }
02680     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02681     htim->OnePulse_MspInitCallback(htim);
02682 #else
02683     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02684     HAL_TIM_OnePulse_MspInit(htim);
02685 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02686   }
02687
02688   /* Set the TIM state */
02689   htim->State = HAL_TIM_STATE_BUSY;
02690
02691   /* Configure the Time base in the One Pulse Mode */
02692   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02693
02694   /* Reset the OPM Bit */
02695   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02696
02697   /* Configure the OPM Mode */
02698   htim->Instance->CR1 |= OnePulseMode;
02699
02700   /* Initialize the DMA burst operation state */
02701   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
02702
02703   /* Initialize the TIM channels state */
02704   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02705   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02706   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02707   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02708
02709   /* Initialize the TIM state*/
02710   htim->State = HAL_TIM_STATE_READY;
02711
02712   return HAL_OK;
02713 }
02714
02715 /**
02716   * @brief  DeInitializes the TIM One Pulse
02717   * @param  htim TIM One Pulse handle
02718   * @retval HAL status
02719   */
02720 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02721 {
02722   /* Check the parameters */
02723   assert_param(IS_TIM_INSTANCE(htim->Instance));
02724
02725   htim->State = HAL_TIM_STATE_BUSY;
02726
02727   /* Disable the TIM Peripheral Clock */
02728   __HAL_TIM_DISABLE(htim);
02729
02730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02731   if (htim->OnePulse_MspDeInitCallback == NULL)
02732   {
02733     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
02734   }
02735   /* DeInit the low level hardware */
02736   htim->OnePulse_MspDeInitCallback(htim);
02737 #else
02738   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02739   HAL_TIM_OnePulse_MspDeInit(htim);
02740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02741
02742   /* Change the DMA burst operation state */
02743   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
02744
02745   /* Set the TIM channel state */
02746   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
02747   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
02748   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
02749   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
02750
02751   /* Change TIM state */
02752   htim->State = HAL_TIM_STATE_RESET;
02753
02754   /* Release Lock */
02755   __HAL_UNLOCK(htim);
02756
02757   return HAL_OK;
02758 }
02759
02760 /**
02761   * @brief  Initializes the TIM One Pulse MSP.
02762   * @param  htim TIM One Pulse handle
02763   * @retval None
02764   */
02765 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02766 {
02767   /* Prevent unused argument(s) compilation warning */
02768   UNUSED(htim);
02769
02770   /* NOTE : This function should not be modified, when the callback is needed,
02771             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02772    */
02773 }
02774
02775 /**
02776   * @brief  DeInitializes TIM One Pulse MSP.
02777   * @param  htim TIM One Pulse handle
02778   * @retval None
02779   */
02780 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02781 {
02782   /* Prevent unused argument(s) compilation warning */
02783   UNUSED(htim);
02784
02785   /* NOTE : This function should not be modified, when the callback is needed,
02786             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02787    */
02788 }
02789
02790 /**
02791   * @brief  Starts the TIM One Pulse signal generation.
02792   * @note Though OutputChannel parameter is deprecated and ignored by the function
02793   *        it has been kept to avoid HAL_TIM API compatibility break.
02794   * @note The pulse output channel is determined when calling
02795   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02796   * @param  htim TIM One Pulse handle
02797   * @param  OutputChannel See note above
02798   * @retval HAL status
02799   */
02800 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02801 {
02802   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
02803   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
02804   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
02805   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
02806
02807   /* Prevent unused argument(s) compilation warning */
02808   UNUSED(OutputChannel);
02809
02810   /* Check the TIM channels state */
02811   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02812       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
02813       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02814       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
02815   {
02816     return HAL_ERROR;
02817   }
02818
02819   /* Set the TIM channels state */
02820   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02821   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02822   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02823   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02824
02825   /* Enable the Capture compare and the Input Capture channels
02826     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02827     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02828     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02829     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02830
02831     No need to enable the counter, it's enabled automatically by hardware
02832     (the counter starts in response to a stimulus and generate a pulse */
02833
02834   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02835   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02836
02837   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02838   {
02839     /* Enable the main output */
02840     __HAL_TIM_MOE_ENABLE(htim);
02841   }
02842
02843   /* Return function status */
02844   return HAL_OK;
02845 }
02846
02847 /**
02848   * @brief  Stops the TIM One Pulse signal generation.
02849   * @note Though OutputChannel parameter is deprecated and ignored by the function
02850   *        it has been kept to avoid HAL_TIM API compatibility break.
02851   * @note The pulse output channel is determined when calling
02852   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02853   * @param  htim TIM One Pulse handle
02854   * @param  OutputChannel See note above
02855   * @retval HAL status
02856   */
02857 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02858 {
02859   /* Prevent unused argument(s) compilation warning */
02860   UNUSED(OutputChannel);
02861
02862   /* Disable the Capture compare and the Input Capture channels
02863   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02864   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02865   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02866   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02867
02868   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02869   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02870
02871   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02872   {
02873     /* Disable the Main Output */
02874     __HAL_TIM_MOE_DISABLE(htim);
02875   }
02876
02877   /* Disable the Peripheral */
02878   __HAL_TIM_DISABLE(htim);
02879
02880   /* Set the TIM channels state */
02881   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02882   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02883   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02884   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02885
02886   /* Return function status */
02887   return HAL_OK;
02888 }
02889
02890 /**
02891   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02892   * @note Though OutputChannel parameter is deprecated and ignored by the function
02893   *        it has been kept to avoid HAL_TIM API compatibility break.
02894   * @note The pulse output channel is determined when calling
02895   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02896   * @param  htim TIM One Pulse handle
02897   * @param  OutputChannel See note above
02898   * @retval HAL status
02899   */
02900 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02901 {
02902   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
02903   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
02904   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
02905   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
02906
02907   /* Prevent unused argument(s) compilation warning */
02908   UNUSED(OutputChannel);
02909
02910   /* Check the TIM channels state */
02911   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02912       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
02913       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02914       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
02915   {
02916     return HAL_ERROR;
02917   }
02918
02919   /* Set the TIM channels state */
02920   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02921   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02922   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02923   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02924
02925   /* Enable the Capture compare and the Input Capture channels
02926     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02927     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02928     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02929     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02930
02931     No need to enable the counter, it's enabled automatically by hardware
02932     (the counter starts in response to a stimulus and generate a pulse */
02933
02934   /* Enable the TIM Capture/Compare 1 interrupt */
02935   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02936
02937   /* Enable the TIM Capture/Compare 2 interrupt */
02938   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02939
02940   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02941   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02942
02943   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02944   {
02945     /* Enable the main output */
02946     __HAL_TIM_MOE_ENABLE(htim);
02947   }
02948
02949   /* Return function status */
02950   return HAL_OK;
02951 }
02952
02953 /**
02954   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02955   * @note Though OutputChannel parameter is deprecated and ignored by the function
02956   *        it has been kept to avoid HAL_TIM API compatibility break.
02957   * @note The pulse output channel is determined when calling
02958   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02959   * @param  htim TIM One Pulse handle
02960   * @param  OutputChannel See note above
02961   * @retval HAL status
02962   */
02963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02964 {
02965   /* Prevent unused argument(s) compilation warning */
02966   UNUSED(OutputChannel);
02967
02968   /* Disable the TIM Capture/Compare 1 interrupt */
02969   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02970
02971   /* Disable the TIM Capture/Compare 2 interrupt */
02972   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02973
02974   /* Disable the Capture compare and the Input Capture channels
02975   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02976   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02977   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02978   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02979   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02980   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02981
02982   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02983   {
02984     /* Disable the Main Output */
02985     __HAL_TIM_MOE_DISABLE(htim);
02986   }
02987
02988   /* Disable the Peripheral */
02989   __HAL_TIM_DISABLE(htim);
02990
02991   /* Set the TIM channels state */
02992   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02993   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02994   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02995   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02996
02997   /* Return function status */
02998   return HAL_OK;
02999 }
03000
03001 /**
03002   * @}
03003   */
03004
03005 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
03006   *  @brief    TIM Encoder functions
03007   *
03008 @verbatim
03009   ==============================================================================
03010                           ##### TIM Encoder functions #####
03011   ==============================================================================
03012   [..]
03013     This section provides functions allowing to:
03014     (+) Initialize and configure the TIM Encoder.
03015     (+) De-initialize the TIM Encoder.
03016     (+) Start the TIM Encoder.
03017     (+) Stop the TIM Encoder.
03018     (+) Start the TIM Encoder and enable interrupt.
03019     (+) Stop the TIM Encoder and disable interrupt.
03020     (+) Start the TIM Encoder and enable DMA transfer.
03021     (+) Stop the TIM Encoder and disable DMA transfer.
03022
03023 @endverbatim
03024   * @{
03025   */
03026 /**
03027   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
03028   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
03029   *         requires a timer reset to avoid unexpected direction
03030   *         due to DIR bit readonly in center aligned mode.
03031   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
03032   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
03033   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
03034   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
03035   * @note   When the timer instance is initialized in Encoder mode, timer
03036   *         channels 1 and channel 2 are reserved and cannot be used for other
03037   *         purpose.
03038   * @param  htim TIM Encoder Interface handle
03039   * @param  sConfig TIM Encoder Interface configuration structure
03040   * @retval HAL status
03041   */
03042 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
03043 {
03044   uint32_t tmpsmcr;
03045   uint32_t tmpccmr1;
03046   uint32_t tmpccer;
03047
03048   /* Check the TIM handle allocation */
03049   if (htim == NULL)
03050   {
03051     return HAL_ERROR;
03052   }
03053
03054   /* Check the parameters */
03055   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03056   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
03057   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
03058   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
03059   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
03060   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
03061   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
03062   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
03063   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
03064   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
03065   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
03066   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
03067   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
03068   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
03069
03070   if (htim->State == HAL_TIM_STATE_RESET)
03071   {
03072     /* Allocate lock resource and initialize it */
03073     htim->Lock = HAL_UNLOCKED;
03074
03075 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03076     /* Reset interrupt callbacks to legacy weak callbacks */
03077     TIM_ResetCallback(htim);
03078
03079     if (htim->Encoder_MspInitCallback == NULL)
03080     {
03081       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
03082     }
03083     /* Init the low level hardware : GPIO, CLOCK, NVIC */
03084     htim->Encoder_MspInitCallback(htim);
03085 #else
03086     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
03087     HAL_TIM_Encoder_MspInit(htim);
03088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03089   }
03090
03091   /* Set the TIM state */
03092   htim->State = HAL_TIM_STATE_BUSY;
03093
03094   /* Reset the SMS and ECE bits */
03095   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
03096
03097   /* Configure the Time base in the Encoder Mode */
03098   TIM_Base_SetConfig(htim->Instance, &htim->Init);
03099
03100   /* Get the TIMx SMCR register value */
03101   tmpsmcr = htim->Instance->SMCR;
03102
03103   /* Get the TIMx CCMR1 register value */
03104   tmpccmr1 = htim->Instance->CCMR1;
03105
03106   /* Get the TIMx CCER register value */
03107   tmpccer = htim->Instance->CCER;
03108
03109   /* Set the encoder Mode */
03110   tmpsmcr |= sConfig->EncoderMode;
03111
03112   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
03113   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
03114   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
03115
03116   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
03117   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
03118   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
03119   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
03120   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
03121
03122   /* Set the TI1 and the TI2 Polarities */
03123   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
03124   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
03125   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
03126
03127   /* Write to TIMx SMCR */
03128   htim->Instance->SMCR = tmpsmcr;
03129
03130   /* Write to TIMx CCMR1 */
03131   htim->Instance->CCMR1 = tmpccmr1;
03132
03133   /* Write to TIMx CCER */
03134   htim->Instance->CCER = tmpccer;
03135
03136   /* Initialize the DMA burst operation state */
03137   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
03138
03139   /* Set the TIM channels state */
03140   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03141   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03142   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03143   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03144
03145   /* Initialize the TIM state*/
03146   htim->State = HAL_TIM_STATE_READY;
03147
03148   return HAL_OK;
03149 }
03150
03151
03152 /**
03153   * @brief  DeInitializes the TIM Encoder interface
03154   * @param  htim TIM Encoder Interface handle
03155   * @retval HAL status
03156   */
03157 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
03158 {
03159   /* Check the parameters */
03160   assert_param(IS_TIM_INSTANCE(htim->Instance));
03161
03162   htim->State = HAL_TIM_STATE_BUSY;
03163
03164   /* Disable the TIM Peripheral Clock */
03165   __HAL_TIM_DISABLE(htim);
03166
03167 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03168   if (htim->Encoder_MspDeInitCallback == NULL)
03169   {
03170     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
03171   }
03172   /* DeInit the low level hardware */
03173   htim->Encoder_MspDeInitCallback(htim);
03174 #else
03175   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
03176   HAL_TIM_Encoder_MspDeInit(htim);
03177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03178
03179   /* Change the DMA burst operation state */
03180   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
03181
03182   /* Set the TIM channels state */
03183   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
03184   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
03185   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
03186   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
03187
03188   /* Change TIM state */
03189   htim->State = HAL_TIM_STATE_RESET;
03190
03191   /* Release Lock */
03192   __HAL_UNLOCK(htim);
03193
03194   return HAL_OK;
03195 }
03196
03197 /**
03198   * @brief  Initializes the TIM Encoder Interface MSP.
03199   * @param  htim TIM Encoder Interface handle
03200   * @retval None
03201   */
03202 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
03203 {
03204   /* Prevent unused argument(s) compilation warning */
03205   UNUSED(htim);
03206
03207   /* NOTE : This function should not be modified, when the callback is needed,
03208             the HAL_TIM_Encoder_MspInit could be implemented in the user file
03209    */
03210 }
03211
03212 /**
03213   * @brief  DeInitializes TIM Encoder Interface MSP.
03214   * @param  htim TIM Encoder Interface handle
03215   * @retval None
03216   */
03217 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
03218 {
03219   /* Prevent unused argument(s) compilation warning */
03220   UNUSED(htim);
03221
03222   /* NOTE : This function should not be modified, when the callback is needed,
03223             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
03224    */
03225 }
03226
03227 /**
03228   * @brief  Starts the TIM Encoder Interface.
03229   * @param  htim TIM Encoder Interface handle
03230   * @param  Channel TIM Channels to be enabled
03231   *          This parameter can be one of the following values:
03232   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03233   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03234   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03235   * @retval HAL status
03236   */
03237 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
03238 {
03239   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03240   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03241   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03242   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03243
03244   /* Check the parameters */
03245   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03246
03247   /* Set the TIM channel(s) state */
03248   if (Channel == TIM_CHANNEL_1)
03249   {
03250     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03251         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
03252     {
03253       return HAL_ERROR;
03254     }
03255     else
03256     {
03257       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03258       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03259     }
03260   }
03261   else if (Channel == TIM_CHANNEL_2)
03262   {
03263     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03264         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03265     {
03266       return HAL_ERROR;
03267     }
03268     else
03269     {
03270       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03271       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03272     }
03273   }
03274   else
03275   {
03276     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03277         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03278         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03279         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03280     {
03281       return HAL_ERROR;
03282     }
03283     else
03284     {
03285       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03286       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03287       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03288       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03289     }
03290   }
03291
03292   /* Enable the encoder interface channels */
03293   switch (Channel)
03294   {
03295     case TIM_CHANNEL_1:
03296     {
03297       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03298       break;
03299     }
03300
03301     case TIM_CHANNEL_2:
03302     {
03303       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03304       break;
03305     }
03306
03307     default :
03308     {
03309       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03310       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03311       break;
03312     }
03313   }
03314   /* Enable the Peripheral */
03315   __HAL_TIM_ENABLE(htim);
03316
03317   /* Return function status */
03318   return HAL_OK;
03319 }
03320
03321 /**
03322   * @brief  Stops the TIM Encoder Interface.
03323   * @param  htim TIM Encoder Interface handle
03324   * @param  Channel TIM Channels to be disabled
03325   *          This parameter can be one of the following values:
03326   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03327   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03328   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03329   * @retval HAL status
03330   */
03331 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
03332 {
03333   /* Check the parameters */
03334   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03335
03336   /* Disable the Input Capture channels 1 and 2
03337     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03338   switch (Channel)
03339   {
03340     case TIM_CHANNEL_1:
03341     {
03342       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03343       break;
03344     }
03345
03346     case TIM_CHANNEL_2:
03347     {
03348       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03349       break;
03350     }
03351
03352     default :
03353     {
03354       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03355       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03356       break;
03357     }
03358   }
03359
03360   /* Disable the Peripheral */
03361   __HAL_TIM_DISABLE(htim);
03362
03363   /* Set the TIM channel(s) state */
03364   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03365   {
03366     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03367     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03368   }
03369   else
03370   {
03371     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03372     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03373     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03374     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03375   }
03376
03377   /* Return function status */
03378   return HAL_OK;
03379 }
03380
03381 /**
03382   * @brief  Starts the TIM Encoder Interface in interrupt mode.
03383   * @param  htim TIM Encoder Interface handle
03384   * @param  Channel TIM Channels to be enabled
03385   *          This parameter can be one of the following values:
03386   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03387   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03388   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03389   * @retval HAL status
03390   */
03391 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
03392 {
03393   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03394   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03395   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03396   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03397
03398   /* Check the parameters */
03399   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03400
03401   /* Set the TIM channel(s) state */
03402   if (Channel == TIM_CHANNEL_1)
03403   {
03404     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03405         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
03406     {
03407       return HAL_ERROR;
03408     }
03409     else
03410     {
03411       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03412       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03413     }
03414   }
03415   else if (Channel == TIM_CHANNEL_2)
03416   {
03417     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03418         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03419     {
03420       return HAL_ERROR;
03421     }
03422     else
03423     {
03424       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03425       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03426     }
03427   }
03428   else
03429   {
03430     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03431         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03432         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03433         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03434     {
03435       return HAL_ERROR;
03436     }
03437     else
03438     {
03439       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03440       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03441       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03442       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03443     }
03444   }
03445
03446   /* Enable the encoder interface channels */
03447   /* Enable the capture compare Interrupts 1 and/or 2 */
03448   switch (Channel)
03449   {
03450     case TIM_CHANNEL_1:
03451     {
03452       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03453       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
03454       break;
03455     }
03456
03457     case TIM_CHANNEL_2:
03458     {
03459       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03460       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
03461       break;
03462     }
03463
03464     default :
03465     {
03466       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03467       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03468       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
03469       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
03470       break;
03471     }
03472   }
03473
03474   /* Enable the Peripheral */
03475   __HAL_TIM_ENABLE(htim);
03476
03477   /* Return function status */
03478   return HAL_OK;
03479 }
03480
03481 /**
03482   * @brief  Stops the TIM Encoder Interface in interrupt mode.
03483   * @param  htim TIM Encoder Interface handle
03484   * @param  Channel TIM Channels to be disabled
03485   *          This parameter can be one of the following values:
03486   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03487   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03488   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03489   * @retval HAL status
03490   */
03491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
03492 {
03493   /* Check the parameters */
03494   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03495
03496   /* Disable the Input Capture channels 1 and 2
03497     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03498   if (Channel == TIM_CHANNEL_1)
03499   {
03500     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03501
03502     /* Disable the capture compare Interrupts 1 */
03503     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
03504   }
03505   else if (Channel == TIM_CHANNEL_2)
03506   {
03507     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03508
03509     /* Disable the capture compare Interrupts 2 */
03510     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
03511   }
03512   else
03513   {
03514     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03515     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03516
03517     /* Disable the capture compare Interrupts 1 and 2 */
03518     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
03519     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
03520   }
03521
03522   /* Disable the Peripheral */
03523   __HAL_TIM_DISABLE(htim);
03524
03525   /* Set the TIM channel(s) state */
03526   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03527   {
03528     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03529     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03530   }
03531   else
03532   {
03533     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03534     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03535     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03536     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03537   }
03538
03539   /* Return function status */
03540   return HAL_OK;
03541 }
03542
03543 /**
03544   * @brief  Starts the TIM Encoder Interface in DMA mode.
03545   * @param  htim TIM Encoder Interface handle
03546   * @param  Channel TIM Channels to be enabled
03547   *          This parameter can be one of the following values:
03548   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03549   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03550   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03551   * @param  pData1 The destination Buffer address for IC1.
03552   * @param  pData2 The destination Buffer address for IC2.
03553   * @param  Length The length of data to be transferred from TIM peripheral to memory.
03554   * @retval HAL status
03555   */
03556 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
03557                                             uint32_t *pData2, uint16_t Length)
03558 {
03559   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03560   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03561   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03562   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03563
03564   /* Check the parameters */
03565   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03566
03567   /* Set the TIM channel(s) state */
03568   if (Channel == TIM_CHANNEL_1)
03569   {
03570     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03571         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
03572     {
03573       return HAL_BUSY;
03574     }
03575     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03576              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
03577     {
03578       if ((pData1 == NULL) || (Length == 0U))
03579       {
03580         return HAL_ERROR;
03581       }
03582       else
03583       {
03584         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03585         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03586       }
03587     }
03588     else
03589     {
03590       return HAL_ERROR;
03591     }
03592   }
03593   else if (Channel == TIM_CHANNEL_2)
03594   {
03595     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
03596         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
03597     {
03598       return HAL_BUSY;
03599     }
03600     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
03601              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
03602     {
03603       if ((pData2 == NULL) || (Length == 0U))
03604       {
03605         return HAL_ERROR;
03606       }
03607       else
03608       {
03609         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03610         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03611       }
03612     }
03613     else
03614     {
03615       return HAL_ERROR;
03616     }
03617   }
03618   else
03619   {
03620     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03621         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
03622         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03623         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
03624     {
03625       return HAL_BUSY;
03626     }
03627     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03628              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
03629              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03630              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
03631     {
03632       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
03633       {
03634         return HAL_ERROR;
03635       }
03636       else
03637       {
03638         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03639         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03640         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03641         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03642       }
03643     }
03644     else
03645     {
03646       return HAL_ERROR;
03647     }
03648   }
03649
03650   switch (Channel)
03651   {
03652     case TIM_CHANNEL_1:
03653     {
03654       /* Set the DMA capture callbacks */
03655       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03656       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03657
03658       /* Set the DMA error callback */
03659       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03660
03661       /* Enable the DMA channel */
03662       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
03663                            Length) != HAL_OK)
03664       {
03665         /* Return error status */
03666         return HAL_ERROR;
03667       }
03668       /* Enable the TIM Input Capture DMA request */
03669       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03670
03671       /* Enable the Capture compare channel */
03672       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03673
03674       /* Enable the Peripheral */
03675       __HAL_TIM_ENABLE(htim);
03676
03677       break;
03678     }
03679
03680     case TIM_CHANNEL_2:
03681     {
03682       /* Set the DMA capture callbacks */
03683       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03684       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03685
03686       /* Set the DMA error callback */
03687       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
03688       /* Enable the DMA channel */
03689       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
03690                            Length) != HAL_OK)
03691       {
03692         /* Return error status */
03693         return HAL_ERROR;
03694       }
03695       /* Enable the TIM Input Capture  DMA request */
03696       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03697
03698       /* Enable the Capture compare channel */
03699       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03700
03701       /* Enable the Peripheral */
03702       __HAL_TIM_ENABLE(htim);
03703
03704       break;
03705     }
03706
03707     default:
03708     {
03709       /* Set the DMA capture callbacks */
03710       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03711       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03712
03713       /* Set the DMA error callback */
03714       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03715
03716       /* Enable the DMA channel */
03717       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
03718                            Length) != HAL_OK)
03719       {
03720         /* Return error status */
03721         return HAL_ERROR;
03722       }
03723
03724       /* Set the DMA capture callbacks */
03725       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03726       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03727
03728       /* Set the DMA error callback */
03729       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03730
03731       /* Enable the DMA channel */
03732       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
03733                            Length) != HAL_OK)
03734       {
03735         /* Return error status */
03736         return HAL_ERROR;
03737       }
03738
03739       /* Enable the TIM Input Capture  DMA request */
03740       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03741       /* Enable the TIM Input Capture  DMA request */
03742       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03743
03744       /* Enable the Capture compare channel */
03745       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03746       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03747
03748       /* Enable the Peripheral */
03749       __HAL_TIM_ENABLE(htim);
03750
03751       break;
03752     }
03753   }
03754
03755   /* Return function status */
03756   return HAL_OK;
03757 }
03758
03759 /**
03760   * @brief  Stops the TIM Encoder Interface in DMA mode.
03761   * @param  htim TIM Encoder Interface handle
03762   * @param  Channel TIM Channels to be enabled
03763   *          This parameter can be one of the following values:
03764   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03765   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03766   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03767   * @retval HAL status
03768   */
03769 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
03770 {
03771   /* Check the parameters */
03772   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03773
03774   /* Disable the Input Capture channels 1 and 2
03775     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03776   if (Channel == TIM_CHANNEL_1)
03777   {
03778     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03779
03780     /* Disable the capture compare DMA Request 1 */
03781     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03782     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03783   }
03784   else if (Channel == TIM_CHANNEL_2)
03785   {
03786     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03787
03788     /* Disable the capture compare DMA Request 2 */
03789     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03790     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03791   }
03792   else
03793   {
03794     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03795     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03796
03797     /* Disable the capture compare DMA Request 1 and 2 */
03798     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03799     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03800     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03801     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03802   }
03803
03804   /* Disable the Peripheral */
03805   __HAL_TIM_DISABLE(htim);
03806
03807   /* Set the TIM channel(s) state */
03808   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03809   {
03810     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03811     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03812   }
03813   else
03814   {
03815     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03816     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03817     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03818     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03819   }
03820
03821   /* Return function status */
03822   return HAL_OK;
03823 }
03824
03825 /**
03826   * @}
03827   */
03828 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
03829   *  @brief    TIM IRQ handler management
03830   *
03831 @verbatim
03832   ==============================================================================
03833                         ##### IRQ handler management #####
03834   ==============================================================================
03835   [..]
03836     This section provides Timer IRQ handler function.
03837
03838 @endverbatim
03839   * @{
03840   */
03841 /**
03842   * @brief  This function handles TIM interrupts requests.
03843   * @param  htim TIM  handle
03844   * @retval None
03845   */
03846 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
03847 {
03848   uint32_t itsource = htim->Instance->DIER;
03849   uint32_t itflag   = htim->Instance->SR;
03850
03851   /* Capture compare 1 event */
03852   if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
03853   {
03854     if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
03855     {
03856       {
03857         __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
03858         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03859
03860         /* Input capture event */
03861         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
03862         {
03863 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03864           htim->IC_CaptureCallback(htim);
03865 #else
03866           HAL_TIM_IC_CaptureCallback(htim);
03867 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03868         }
03869         /* Output compare event */
03870         else
03871         {
03872 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03873           htim->OC_DelayElapsedCallback(htim);
03874           htim->PWM_PulseFinishedCallback(htim);
03875 #else
03876           HAL_TIM_OC_DelayElapsedCallback(htim);
03877           HAL_TIM_PWM_PulseFinishedCallback(htim);
03878 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03879         }
03880         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03881       }
03882     }
03883   }
03884   /* Capture compare 2 event */
03885   if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
03886   {
03887     if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
03888     {
03889       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
03890       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03891       /* Input capture event */
03892       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
03893       {
03894 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03895         htim->IC_CaptureCallback(htim);
03896 #else
03897         HAL_TIM_IC_CaptureCallback(htim);
03898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03899       }
03900       /* Output compare event */
03901       else
03902       {
03903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03904         htim->OC_DelayElapsedCallback(htim);
03905         htim->PWM_PulseFinishedCallback(htim);
03906 #else
03907         HAL_TIM_OC_DelayElapsedCallback(htim);
03908         HAL_TIM_PWM_PulseFinishedCallback(htim);
03909 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03910       }
03911       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03912     }
03913   }
03914   /* Capture compare 3 event */
03915   if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
03916   {
03917     if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
03918     {
03919       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
03920       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03921       /* Input capture event */
03922       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
03923       {
03924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03925         htim->IC_CaptureCallback(htim);
03926 #else
03927         HAL_TIM_IC_CaptureCallback(htim);
03928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03929       }
03930       /* Output compare event */
03931       else
03932       {
03933 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03934         htim->OC_DelayElapsedCallback(htim);
03935         htim->PWM_PulseFinishedCallback(htim);
03936 #else
03937         HAL_TIM_OC_DelayElapsedCallback(htim);
03938         HAL_TIM_PWM_PulseFinishedCallback(htim);
03939 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03940       }
03941       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03942     }
03943   }
03944   /* Capture compare 4 event */
03945   if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
03946   {
03947     if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
03948     {
03949       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
03950       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03951       /* Input capture event */
03952       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
03953       {
03954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03955         htim->IC_CaptureCallback(htim);
03956 #else
03957         HAL_TIM_IC_CaptureCallback(htim);
03958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03959       }
03960       /* Output compare event */
03961       else
03962       {
03963 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03964         htim->OC_DelayElapsedCallback(htim);
03965         htim->PWM_PulseFinishedCallback(htim);
03966 #else
03967         HAL_TIM_OC_DelayElapsedCallback(htim);
03968         HAL_TIM_PWM_PulseFinishedCallback(htim);
03969 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03970       }
03971       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03972     }
03973   }
03974   /* TIM Update event */
03975   if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
03976   {
03977     if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
03978     {
03979       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
03980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03981       htim->PeriodElapsedCallback(htim);
03982 #else
03983       HAL_TIM_PeriodElapsedCallback(htim);
03984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03985     }
03986   }
03987   /* TIM Break input event */
03988   if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
03989       ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
03990   {
03991     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
03992     {
03993       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
03994 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03995       htim->BreakCallback(htim);
03996 #else
03997       HAL_TIMEx_BreakCallback(htim);
03998 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03999     }
04000   }
04001   /* TIM Break2 input event */
04002   if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
04003   {
04004     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
04005     {
04006       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
04007 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04008       htim->Break2Callback(htim);
04009 #else
04010       HAL_TIMEx_Break2Callback(htim);
04011 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04012     }
04013   }
04014   /* TIM Trigger detection event */
04015   if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
04016   {
04017     if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
04018     {
04019       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
04020 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04021       htim->TriggerCallback(htim);
04022 #else
04023       HAL_TIM_TriggerCallback(htim);
04024 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04025     }
04026   }
04027   /* TIM commutation event */
04028   if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
04029   {
04030     if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
04031     {
04032       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
04033 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04034       htim->CommutationCallback(htim);
04035 #else
04036       HAL_TIMEx_CommutCallback(htim);
04037 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04038     }
04039   }
04040   /* TIM Encoder index event */
04041   if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
04042   {
04043     if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
04044     {
04045       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
04046 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04047       htim->EncoderIndexCallback(htim);
04048 #else
04049       HAL_TIMEx_EncoderIndexCallback(htim);
04050 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04051     }
04052   }
04053   /* TIM Direction change event */
04054   if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
04055   {
04056     if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
04057     {
04058       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
04059 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04060       htim->DirectionChangeCallback(htim);
04061 #else
04062       HAL_TIMEx_DirectionChangeCallback(htim);
04063 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04064     }
04065   }
04066   /* TIM Index error event */
04067   if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
04068   {
04069     if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
04070     {
04071       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
04072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04073       htim->IndexErrorCallback(htim);
04074 #else
04075       HAL_TIMEx_IndexErrorCallback(htim);
04076 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04077     }
04078   }
04079   /* TIM Transition error event */
04080   if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
04081   {
04082     if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
04083     {
04084       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
04085 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04086       htim->TransitionErrorCallback(htim);
04087 #else
04088       HAL_TIMEx_TransitionErrorCallback(htim);
04089 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04090     }
04091   }
04092 }
04093
04094 /**
04095   * @}
04096   */
04097
04098 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
04099   *  @brief    TIM Peripheral Control functions
04100   *
04101 @verbatim
04102   ==============================================================================
04103                    ##### Peripheral Control functions #####
04104   ==============================================================================
04105  [..]
04106    This section provides functions allowing to:
04107       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
04108       (+) Configure External Clock source.
04109       (+) Configure Complementary channels, break features and dead time.
04110       (+) Configure Master and the Slave synchronization.
04111       (+) Configure the DMA Burst Mode.
04112
04113 @endverbatim
04114   * @{
04115   */
04116
04117 /**
04118   * @brief  Initializes the TIM Output Compare Channels according to the specified
04119   *         parameters in the TIM_OC_InitTypeDef.
04120   * @param  htim TIM Output Compare handle
04121   * @param  sConfig TIM Output Compare configuration structure
04122   * @param  Channel TIM Channels to configure
04123   *          This parameter can be one of the following values:
04124   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04125   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04126   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04127   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04128   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
04129   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
04130   * @retval HAL status
04131   */
04132 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
04133                                            const TIM_OC_InitTypeDef *sConfig,
04134                                            uint32_t Channel)
04135 {
04136   HAL_StatusTypeDef status = HAL_OK;
04137
04138   /* Check the parameters */
04139   assert_param(IS_TIM_CHANNELS(Channel));
04140   assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
04141   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
04142
04143   /* Process Locked */
04144   __HAL_LOCK(htim);
04145
04146   switch (Channel)
04147   {
04148     case TIM_CHANNEL_1:
04149     {
04150       /* Check the parameters */
04151       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04152
04153       /* Configure the TIM Channel 1 in Output Compare */
04154       TIM_OC1_SetConfig(htim->Instance, sConfig);
04155       break;
04156     }
04157
04158     case TIM_CHANNEL_2:
04159     {
04160       /* Check the parameters */
04161       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04162
04163       /* Configure the TIM Channel 2 in Output Compare */
04164       TIM_OC2_SetConfig(htim->Instance, sConfig);
04165       break;
04166     }
04167
04168     case TIM_CHANNEL_3:
04169     {
04170       /* Check the parameters */
04171       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04172
04173       /* Configure the TIM Channel 3 in Output Compare */
04174       TIM_OC3_SetConfig(htim->Instance, sConfig);
04175       break;
04176     }
04177
04178     case TIM_CHANNEL_4:
04179     {
04180       /* Check the parameters */
04181       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04182
04183       /* Configure the TIM Channel 4 in Output Compare */
04184       TIM_OC4_SetConfig(htim->Instance, sConfig);
04185       break;
04186     }
04187
04188     case TIM_CHANNEL_5:
04189     {
04190       /* Check the parameters */
04191       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
04192
04193       /* Configure the TIM Channel 5 in Output Compare */
04194       TIM_OC5_SetConfig(htim->Instance, sConfig);
04195       break;
04196     }
04197
04198     case TIM_CHANNEL_6:
04199     {
04200       /* Check the parameters */
04201       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
04202
04203       /* Configure the TIM Channel 6 in Output Compare */
04204       TIM_OC6_SetConfig(htim->Instance, sConfig);
04205       break;
04206     }
04207
04208     default:
04209       status = HAL_ERROR;
04210       break;
04211   }
04212
04213   __HAL_UNLOCK(htim);
04214
04215   return status;
04216 }
04217
04218 /**
04219   * @brief  Initializes the TIM Input Capture Channels according to the specified
04220   *         parameters in the TIM_IC_InitTypeDef.
04221   * @param  htim TIM IC handle
04222   * @param  sConfig TIM Input Capture configuration structure
04223   * @param  Channel TIM Channel to configure
04224   *          This parameter can be one of the following values:
04225   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04226   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04227   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04228   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04229   * @retval HAL status
04230   */
04231 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
04232 {
04233   HAL_StatusTypeDef status = HAL_OK;
04234
04235   /* Check the parameters */
04236   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04237   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
04238   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
04239   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
04240   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
04241
04242   /* Process Locked */
04243   __HAL_LOCK(htim);
04244
04245   if (Channel == TIM_CHANNEL_1)
04246   {
04247     /* TI1 Configuration */
04248     TIM_TI1_SetConfig(htim->Instance,
04249                       sConfig->ICPolarity,
04250                       sConfig->ICSelection,
04251                       sConfig->ICFilter);
04252
04253     /* Reset the IC1PSC Bits */
04254     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
04255
04256     /* Set the IC1PSC value */
04257     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
04258   }
04259   else if (Channel == TIM_CHANNEL_2)
04260   {
04261     /* TI2 Configuration */
04262     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04263
04264     TIM_TI2_SetConfig(htim->Instance,
04265                       sConfig->ICPolarity,
04266                       sConfig->ICSelection,
04267                       sConfig->ICFilter);
04268
04269     /* Reset the IC2PSC Bits */
04270     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
04271
04272     /* Set the IC2PSC value */
04273     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
04274   }
04275   else if (Channel == TIM_CHANNEL_3)
04276   {
04277     /* TI3 Configuration */
04278     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04279
04280     TIM_TI3_SetConfig(htim->Instance,
04281                       sConfig->ICPolarity,
04282                       sConfig->ICSelection,
04283                       sConfig->ICFilter);
04284
04285     /* Reset the IC3PSC Bits */
04286     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
04287
04288     /* Set the IC3PSC value */
04289     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
04290   }
04291   else if (Channel == TIM_CHANNEL_4)
04292   {
04293     /* TI4 Configuration */
04294     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04295
04296     TIM_TI4_SetConfig(htim->Instance,
04297                       sConfig->ICPolarity,
04298                       sConfig->ICSelection,
04299                       sConfig->ICFilter);
04300
04301     /* Reset the IC4PSC Bits */
04302     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
04303
04304     /* Set the IC4PSC value */
04305     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
04306   }
04307   else
04308   {
04309     status = HAL_ERROR;
04310   }
04311
04312   __HAL_UNLOCK(htim);
04313
04314   return status;
04315 }
04316
04317 /**
04318   * @brief  Initializes the TIM PWM  channels according to the specified
04319   *         parameters in the TIM_OC_InitTypeDef.
04320   * @param  htim TIM PWM handle
04321   * @param  sConfig TIM PWM configuration structure
04322   * @param  Channel TIM Channels to be configured
04323   *          This parameter can be one of the following values:
04324   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04325   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04326   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04327   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04328   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
04329   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
04330   * @retval HAL status
04331   */
04332 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
04333                                             const TIM_OC_InitTypeDef *sConfig,
04334                                             uint32_t Channel)
04335 {
04336   HAL_StatusTypeDef status = HAL_OK;
04337
04338   /* Check the parameters */
04339   assert_param(IS_TIM_CHANNELS(Channel));
04340   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
04341   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
04342   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
04343
04344   /* Process Locked */
04345   __HAL_LOCK(htim);
04346
04347   switch (Channel)
04348   {
04349     case TIM_CHANNEL_1:
04350     {
04351       /* Check the parameters */
04352       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04353
04354       /* Configure the Channel 1 in PWM mode */
04355       TIM_OC1_SetConfig(htim->Instance, sConfig);
04356
04357       /* Set the Preload enable bit for channel1 */
04358       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
04359
04360       /* Configure the Output Fast mode */
04361       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
04362       htim->Instance->CCMR1 |= sConfig->OCFastMode;
04363       break;
04364     }
04365
04366     case TIM_CHANNEL_2:
04367     {
04368       /* Check the parameters */
04369       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04370
04371       /* Configure the Channel 2 in PWM mode */
04372       TIM_OC2_SetConfig(htim->Instance, sConfig);
04373
04374       /* Set the Preload enable bit for channel2 */
04375       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
04376
04377       /* Configure the Output Fast mode */
04378       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
04379       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
04380       break;
04381     }
04382
04383     case TIM_CHANNEL_3:
04384     {
04385       /* Check the parameters */
04386       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04387
04388       /* Configure the Channel 3 in PWM mode */
04389       TIM_OC3_SetConfig(htim->Instance, sConfig);
04390
04391       /* Set the Preload enable bit for channel3 */
04392       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
04393
04394       /* Configure the Output Fast mode */
04395       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
04396       htim->Instance->CCMR2 |= sConfig->OCFastMode;
04397       break;
04398     }
04399
04400     case TIM_CHANNEL_4:
04401     {
04402       /* Check the parameters */
04403       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04404
04405       /* Configure the Channel 4 in PWM mode */
04406       TIM_OC4_SetConfig(htim->Instance, sConfig);
04407
04408       /* Set the Preload enable bit for channel4 */
04409       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
04410
04411       /* Configure the Output Fast mode */
04412       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
04413       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
04414       break;
04415     }
04416
04417     case TIM_CHANNEL_5:
04418     {
04419       /* Check the parameters */
04420       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
04421
04422       /* Configure the Channel 5 in PWM mode */
04423       TIM_OC5_SetConfig(htim->Instance, sConfig);
04424
04425       /* Set the Preload enable bit for channel5*/
04426       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
04427
04428       /* Configure the Output Fast mode */
04429       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
04430       htim->Instance->CCMR3 |= sConfig->OCFastMode;
04431       break;
04432     }
04433
04434     case TIM_CHANNEL_6:
04435     {
04436       /* Check the parameters */
04437       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
04438
04439       /* Configure the Channel 6 in PWM mode */
04440       TIM_OC6_SetConfig(htim->Instance, sConfig);
04441
04442       /* Set the Preload enable bit for channel6 */
04443       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
04444
04445       /* Configure the Output Fast mode */
04446       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
04447       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
04448       break;
04449     }
04450
04451     default:
04452       status = HAL_ERROR;
04453       break;
04454   }
04455
04456   __HAL_UNLOCK(htim);
04457
04458   return status;
04459 }
04460
04461 /**
04462   * @brief  Initializes the TIM One Pulse Channels according to the specified
04463   *         parameters in the TIM_OnePulse_InitTypeDef.
04464   * @param  htim TIM One Pulse handle
04465   * @param  sConfig TIM One Pulse configuration structure
04466   * @param  OutputChannel TIM output channel to configure
04467   *          This parameter can be one of the following values:
04468   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04469   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04470   * @param  InputChannel TIM input Channel to configure
04471   *          This parameter can be one of the following values:
04472   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04473   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04474   * @note  To output a waveform with a minimum delay user can enable the fast
04475   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
04476   *        output is forced in response to the edge detection on TIx input,
04477   *        without taking in account the comparison.
04478   * @retval HAL status
04479   */
04480 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
04481                                                  uint32_t OutputChannel,  uint32_t InputChannel)
04482 {
04483   HAL_StatusTypeDef status = HAL_OK;
04484   TIM_OC_InitTypeDef temp1;
04485
04486   /* Check the parameters */
04487   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
04488   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
04489
04490   if (OutputChannel != InputChannel)
04491   {
04492     /* Process Locked */
04493     __HAL_LOCK(htim);
04494
04495     htim->State = HAL_TIM_STATE_BUSY;
04496
04497     /* Extract the Output compare configuration from sConfig structure */
04498     temp1.OCMode = sConfig->OCMode;
04499     temp1.Pulse = sConfig->Pulse;
04500     temp1.OCPolarity = sConfig->OCPolarity;
04501     temp1.OCNPolarity = sConfig->OCNPolarity;
04502     temp1.OCIdleState = sConfig->OCIdleState;
04503     temp1.OCNIdleState = sConfig->OCNIdleState;
04504
04505     switch (OutputChannel)
04506     {
04507       case TIM_CHANNEL_1:
04508       {
04509         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04510
04511         TIM_OC1_SetConfig(htim->Instance, &temp1);
04512         break;
04513       }
04514
04515       case TIM_CHANNEL_2:
04516       {
04517         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04518
04519         TIM_OC2_SetConfig(htim->Instance, &temp1);
04520         break;
04521       }
04522
04523       default:
04524         status = HAL_ERROR;
04525         break;
04526     }
04527
04528     if (status == HAL_OK)
04529     {
04530       switch (InputChannel)
04531       {
04532         case TIM_CHANNEL_1:
04533         {
04534           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04535
04536           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
04537                             sConfig->ICSelection, sConfig->ICFilter);
04538
04539           /* Reset the IC1PSC Bits */
04540           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
04541
04542           /* Select the Trigger source */
04543           htim->Instance->SMCR &= ~TIM_SMCR_TS;
04544           htim->Instance->SMCR |= TIM_TS_TI1FP1;
04545
04546           /* Select the Slave Mode */
04547           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04548           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
04549           break;
04550         }
04551
04552         case TIM_CHANNEL_2:
04553         {
04554           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04555
04556           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
04557                             sConfig->ICSelection, sConfig->ICFilter);
04558
04559           /* Reset the IC2PSC Bits */
04560           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
04561
04562           /* Select the Trigger source */
04563           htim->Instance->SMCR &= ~TIM_SMCR_TS;
04564           htim->Instance->SMCR |= TIM_TS_TI2FP2;
04565
04566           /* Select the Slave Mode */
04567           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04568           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
04569           break;
04570         }
04571
04572         default:
04573           status = HAL_ERROR;
04574           break;
04575       }
04576     }
04577
04578     htim->State = HAL_TIM_STATE_READY;
04579
04580     __HAL_UNLOCK(htim);
04581
04582     return status;
04583   }
04584   else
04585   {
04586     return HAL_ERROR;
04587   }
04588 }
04589
04590 /**
04591   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
04592   * @param  htim TIM handle
04593   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
04594   *         This parameter can be one of the following values:
04595   *            @arg TIM_DMABASE_CR1
04596   *            @arg TIM_DMABASE_CR2
04597   *            @arg TIM_DMABASE_SMCR
04598   *            @arg TIM_DMABASE_DIER
04599   *            @arg TIM_DMABASE_SR
04600   *            @arg TIM_DMABASE_EGR
04601   *            @arg TIM_DMABASE_CCMR1
04602   *            @arg TIM_DMABASE_CCMR2
04603   *            @arg TIM_DMABASE_CCER
04604   *            @arg TIM_DMABASE_CNT
04605   *            @arg TIM_DMABASE_PSC
04606   *            @arg TIM_DMABASE_ARR
04607   *            @arg TIM_DMABASE_RCR
04608   *            @arg TIM_DMABASE_CCR1
04609   *            @arg TIM_DMABASE_CCR2
04610   *            @arg TIM_DMABASE_CCR3
04611   *            @arg TIM_DMABASE_CCR4
04612   *            @arg TIM_DMABASE_BDTR
04613   *            @arg TIM_DMABASE_CCMR3
04614   *            @arg TIM_DMABASE_CCR5
04615   *            @arg TIM_DMABASE_CCR6
04616   *            @arg TIM_DMABASE_DTR2
04617   *            @arg TIM_DMABASE_ECR
04618   *            @arg TIM_DMABASE_TISEL
04619   *            @arg TIM_DMABASE_AF1
04620   *            @arg TIM_DMABASE_AF2
04621   *            @arg TIM_DMABASE_OR
04622   * @param  BurstRequestSrc TIM DMA Request sources
04623   *         This parameter can be one of the following values:
04624   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04625   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04626   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04627   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04628   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04629   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04630   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04631   * @param  BurstBuffer The Buffer address.
04632   * @param  BurstLength DMA Burst length. This parameter can be one value
04633   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
04634   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04635   * @retval HAL status
04636   */
04637 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04638                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
04639                                               uint32_t  BurstLength)
04640 {
04641   HAL_StatusTypeDef status;
04642
04643   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
04644                                             ((BurstLength) >> 8U) + 1U);
04645
04646
04647
04648   return status;
04649 }
04650
04651 /**
04652   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
04653   * @param  htim TIM handle
04654   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
04655   *         This parameter can be one of the following values:
04656   *            @arg TIM_DMABASE_CR1
04657   *            @arg TIM_DMABASE_CR2
04658   *            @arg TIM_DMABASE_SMCR
04659   *            @arg TIM_DMABASE_DIER
04660   *            @arg TIM_DMABASE_SR
04661   *            @arg TIM_DMABASE_EGR
04662   *            @arg TIM_DMABASE_CCMR1
04663   *            @arg TIM_DMABASE_CCMR2
04664   *            @arg TIM_DMABASE_CCER
04665   *            @arg TIM_DMABASE_CNT
04666   *            @arg TIM_DMABASE_PSC
04667   *            @arg TIM_DMABASE_ARR
04668   *            @arg TIM_DMABASE_RCR
04669   *            @arg TIM_DMABASE_CCR1
04670   *            @arg TIM_DMABASE_CCR2
04671   *            @arg TIM_DMABASE_CCR3
04672   *            @arg TIM_DMABASE_CCR4
04673   *            @arg TIM_DMABASE_BDTR
04674   *            @arg TIM_DMABASE_CCMR3
04675   *            @arg TIM_DMABASE_CCR5
04676   *            @arg TIM_DMABASE_CCR6
04677   *            @arg TIM_DMABASE_DTR2
04678   *            @arg TIM_DMABASE_ECR
04679   *            @arg TIM_DMABASE_TISEL
04680   *            @arg TIM_DMABASE_AF1
04681   *            @arg TIM_DMABASE_AF2
04682   *            @arg TIM_DMABASE_OR
04683   * @param  BurstRequestSrc TIM DMA Request sources
04684   *         This parameter can be one of the following values:
04685   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04686   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04687   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04688   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04689   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04690   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04691   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04692   * @param  BurstBuffer The Buffer address.
04693   * @param  BurstLength DMA Burst length. This parameter can be one value
04694   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
04695   * @param  DataLength Data length. This parameter can be one value
04696   *         between 1 and 0xFFFF.
04697   * @retval HAL status
04698   */
04699 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04700                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
04701                                                    uint32_t  BurstLength,  uint32_t  DataLength)
04702 {
04703   HAL_StatusTypeDef status = HAL_OK;
04704
04705   /* Check the parameters */
04706   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
04707   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
04708   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04709   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
04710   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
04711
04712   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
04713   {
04714     return HAL_BUSY;
04715   }
04716   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
04717   {
04718     if ((BurstBuffer == NULL) && (BurstLength > 0U))
04719     {
04720       return HAL_ERROR;
04721     }
04722     else
04723     {
04724       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
04725     }
04726   }
04727   else
04728   {
04729     /* nothing to do */
04730   }
04731
04732   switch (BurstRequestSrc)
04733   {
04734     case TIM_DMA_UPDATE:
04735     {
04736       /* Set the DMA Period elapsed callbacks */
04737       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
04738       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
04739
04740       /* Set the DMA error callback */
04741       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
04742
04743       /* Enable the DMA channel */
04744       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
04745                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04746       {
04747         /* Return error status */
04748         return HAL_ERROR;
04749       }
04750       break;
04751     }
04752     case TIM_DMA_CC1:
04753     {
04754       /* Set the DMA compare callbacks */
04755       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
04756       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04757
04758       /* Set the DMA error callback */
04759       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
04760
04761       /* Enable the DMA channel */
04762       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
04763                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04764       {
04765         /* Return error status */
04766         return HAL_ERROR;
04767       }
04768       break;
04769     }
04770     case TIM_DMA_CC2:
04771     {
04772       /* Set the DMA compare callbacks */
04773       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
04774       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04775
04776       /* Set the DMA error callback */
04777       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
04778
04779       /* Enable the DMA channel */
04780       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
04781                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04782       {
04783         /* Return error status */
04784         return HAL_ERROR;
04785       }
04786       break;
04787     }
04788     case TIM_DMA_CC3:
04789     {
04790       /* Set the DMA compare callbacks */
04791       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
04792       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04793
04794       /* Set the DMA error callback */
04795       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
04796
04797       /* Enable the DMA channel */
04798       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
04799                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04800       {
04801         /* Return error status */
04802         return HAL_ERROR;
04803       }
04804       break;
04805     }
04806     case TIM_DMA_CC4:
04807     {
04808       /* Set the DMA compare callbacks */
04809       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
04810       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04811
04812       /* Set the DMA error callback */
04813       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04814
04815       /* Enable the DMA channel */
04816       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
04817                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04818       {
04819         /* Return error status */
04820         return HAL_ERROR;
04821       }
04822       break;
04823     }
04824     case TIM_DMA_COM:
04825     {
04826       /* Set the DMA commutation callbacks */
04827       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04828       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04829
04830       /* Set the DMA error callback */
04831       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04832
04833       /* Enable the DMA channel */
04834       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
04835                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04836       {
04837         /* Return error status */
04838         return HAL_ERROR;
04839       }
04840       break;
04841     }
04842     case TIM_DMA_TRIGGER:
04843     {
04844       /* Set the DMA trigger callbacks */
04845       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04846       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04847
04848       /* Set the DMA error callback */
04849       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04850
04851       /* Enable the DMA channel */
04852       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
04853                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04854       {
04855         /* Return error status */
04856         return HAL_ERROR;
04857       }
04858       break;
04859     }
04860     default:
04861       status = HAL_ERROR;
04862       break;
04863   }
04864
04865   if (status == HAL_OK)
04866   {
04867     /* Configure the DMA Burst Mode */
04868     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04869     /* Enable the TIM DMA Request */
04870     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04871   }
04872
04873   /* Return function status */
04874   return status;
04875 }
04876
04877 /**
04878   * @brief  Stops the TIM DMA Burst mode
04879   * @param  htim TIM handle
04880   * @param  BurstRequestSrc TIM DMA Request sources to disable
04881   * @retval HAL status
04882   */
04883 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04884 {
04885   HAL_StatusTypeDef status = HAL_OK;
04886
04887   /* Check the parameters */
04888   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04889
04890   /* Abort the DMA transfer (at least disable the DMA channel) */
04891   switch (BurstRequestSrc)
04892   {
04893     case TIM_DMA_UPDATE:
04894     {
04895       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04896       break;
04897     }
04898     case TIM_DMA_CC1:
04899     {
04900       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04901       break;
04902     }
04903     case TIM_DMA_CC2:
04904     {
04905       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04906       break;
04907     }
04908     case TIM_DMA_CC3:
04909     {
04910       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04911       break;
04912     }
04913     case TIM_DMA_CC4:
04914     {
04915       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04916       break;
04917     }
04918     case TIM_DMA_COM:
04919     {
04920       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04921       break;
04922     }
04923     case TIM_DMA_TRIGGER:
04924     {
04925       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04926       break;
04927     }
04928     default:
04929       status = HAL_ERROR;
04930       break;
04931   }
04932
04933   if (status == HAL_OK)
04934   {
04935     /* Disable the TIM Update DMA request */
04936     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04937
04938     /* Change the DMA burst operation state */
04939     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
04940   }
04941
04942   /* Return function status */
04943   return status;
04944 }
04945
04946 /**
04947   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04948   * @param  htim TIM handle
04949   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04950   *         This parameter can be one of the following values:
04951   *            @arg TIM_DMABASE_CR1
04952   *            @arg TIM_DMABASE_CR2
04953   *            @arg TIM_DMABASE_SMCR
04954   *            @arg TIM_DMABASE_DIER
04955   *            @arg TIM_DMABASE_SR
04956   *            @arg TIM_DMABASE_EGR
04957   *            @arg TIM_DMABASE_CCMR1
04958   *            @arg TIM_DMABASE_CCMR2
04959   *            @arg TIM_DMABASE_CCER
04960   *            @arg TIM_DMABASE_CNT
04961   *            @arg TIM_DMABASE_PSC
04962   *            @arg TIM_DMABASE_ARR
04963   *            @arg TIM_DMABASE_RCR
04964   *            @arg TIM_DMABASE_CCR1
04965   *            @arg TIM_DMABASE_CCR2
04966   *            @arg TIM_DMABASE_CCR3
04967   *            @arg TIM_DMABASE_CCR4
04968   *            @arg TIM_DMABASE_BDTR
04969   *            @arg TIM_DMABASE_CCMR3
04970   *            @arg TIM_DMABASE_CCR5
04971   *            @arg TIM_DMABASE_CCR6
04972   *            @arg TIM_DMABASE_DTR2
04973   *            @arg TIM_DMABASE_ECR
04974   *            @arg TIM_DMABASE_TISEL
04975   *            @arg TIM_DMABASE_AF1
04976   *            @arg TIM_DMABASE_AF2
04977   *            @arg TIM_DMABASE_OR
04978   * @param  BurstRequestSrc TIM DMA Request sources
04979   *         This parameter can be one of the following values:
04980   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04981   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04982   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04983   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04984   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04985   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04986   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04987   * @param  BurstBuffer The Buffer address.
04988   * @param  BurstLength DMA Burst length. This parameter can be one value
04989   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
04990   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04991   * @retval HAL status
04992   */
04993 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04994                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
04995 {
04996   HAL_StatusTypeDef status;
04997
04998   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
04999                                            ((BurstLength) >> 8U) + 1U);
05000
05001
05002   return status;
05003 }
05004
05005 /**
05006   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
05007   * @param  htim TIM handle
05008   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
05009   *         This parameter can be one of the following values:
05010   *            @arg TIM_DMABASE_CR1
05011   *            @arg TIM_DMABASE_CR2
05012   *            @arg TIM_DMABASE_SMCR
05013   *            @arg TIM_DMABASE_DIER
05014   *            @arg TIM_DMABASE_SR
05015   *            @arg TIM_DMABASE_EGR
05016   *            @arg TIM_DMABASE_CCMR1
05017   *            @arg TIM_DMABASE_CCMR2
05018   *            @arg TIM_DMABASE_CCER
05019   *            @arg TIM_DMABASE_CNT
05020   *            @arg TIM_DMABASE_PSC
05021   *            @arg TIM_DMABASE_ARR
05022   *            @arg TIM_DMABASE_RCR
05023   *            @arg TIM_DMABASE_CCR1
05024   *            @arg TIM_DMABASE_CCR2
05025   *            @arg TIM_DMABASE_CCR3
05026   *            @arg TIM_DMABASE_CCR4
05027   *            @arg TIM_DMABASE_BDTR
05028   *            @arg TIM_DMABASE_CCMR3
05029   *            @arg TIM_DMABASE_CCR5
05030   *            @arg TIM_DMABASE_CCR6
05031   *            @arg TIM_DMABASE_DTR2
05032   *            @arg TIM_DMABASE_ECR
05033   *            @arg TIM_DMABASE_TISEL
05034   *            @arg TIM_DMABASE_AF1
05035   *            @arg TIM_DMABASE_AF2
05036   *            @arg TIM_DMABASE_OR
05037   * @param  BurstRequestSrc TIM DMA Request sources
05038   *         This parameter can be one of the following values:
05039   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
05040   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
05041   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
05042   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
05043   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
05044   *            @arg TIM_DMA_COM: TIM Commutation DMA source
05045   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
05046   * @param  BurstBuffer The Buffer address.
05047   * @param  BurstLength DMA Burst length. This parameter can be one value
05048   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
05049   * @param  DataLength Data length. This parameter can be one value
05050   *         between 1 and 0xFFFF.
05051   * @retval HAL status
05052   */
05053 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
05054                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
05055                                                   uint32_t  BurstLength, uint32_t  DataLength)
05056 {
05057   HAL_StatusTypeDef status = HAL_OK;
05058
05059   /* Check the parameters */
05060   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
05061   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
05062   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
05063   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
05064   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
05065
05066   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
05067   {
05068     return HAL_BUSY;
05069   }
05070   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
05071   {
05072     if ((BurstBuffer == NULL) && (BurstLength > 0U))
05073     {
05074       return HAL_ERROR;
05075     }
05076     else
05077     {
05078       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
05079     }
05080   }
05081   else
05082   {
05083     /* nothing to do */
05084   }
05085   switch (BurstRequestSrc)
05086   {
05087     case TIM_DMA_UPDATE:
05088     {
05089       /* Set the DMA Period elapsed callbacks */
05090       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
05091       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
05092
05093       /* Set the DMA error callback */
05094       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
05095
05096       /* Enable the DMA channel */
05097       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05098                            DataLength) != HAL_OK)
05099       {
05100         /* Return error status */
05101         return HAL_ERROR;
05102       }
05103       break;
05104     }
05105     case TIM_DMA_CC1:
05106     {
05107       /* Set the DMA capture callbacks */
05108       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
05109       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05110
05111       /* Set the DMA error callback */
05112       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
05113
05114       /* Enable the DMA channel */
05115       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05116                            DataLength) != HAL_OK)
05117       {
05118         /* Return error status */
05119         return HAL_ERROR;
05120       }
05121       break;
05122     }
05123     case TIM_DMA_CC2:
05124     {
05125       /* Set the DMA capture callbacks */
05126       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
05127       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05128
05129       /* Set the DMA error callback */
05130       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
05131
05132       /* Enable the DMA channel */
05133       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05134                            DataLength) != HAL_OK)
05135       {
05136         /* Return error status */
05137         return HAL_ERROR;
05138       }
05139       break;
05140     }
05141     case TIM_DMA_CC3:
05142     {
05143       /* Set the DMA capture callbacks */
05144       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
05145       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05146
05147       /* Set the DMA error callback */
05148       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
05149
05150       /* Enable the DMA channel */
05151       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05152                            DataLength) != HAL_OK)
05153       {
05154         /* Return error status */
05155         return HAL_ERROR;
05156       }
05157       break;
05158     }
05159     case TIM_DMA_CC4:
05160     {
05161       /* Set the DMA capture callbacks */
05162       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
05163       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05164
05165       /* Set the DMA error callback */
05166       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
05167
05168       /* Enable the DMA channel */
05169       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05170                            DataLength) != HAL_OK)
05171       {
05172         /* Return error status */
05173         return HAL_ERROR;
05174       }
05175       break;
05176     }
05177     case TIM_DMA_COM:
05178     {
05179       /* Set the DMA commutation callbacks */
05180       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
05181       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
05182
05183       /* Set the DMA error callback */
05184       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
05185
05186       /* Enable the DMA channel */
05187       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05188                            DataLength) != HAL_OK)
05189       {
05190         /* Return error status */
05191         return HAL_ERROR;
05192       }
05193       break;
05194     }
05195     case TIM_DMA_TRIGGER:
05196     {
05197       /* Set the DMA trigger callbacks */
05198       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
05199       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
05200
05201       /* Set the DMA error callback */
05202       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
05203
05204       /* Enable the DMA channel */
05205       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05206                            DataLength) != HAL_OK)
05207       {
05208         /* Return error status */
05209         return HAL_ERROR;
05210       }
05211       break;
05212     }
05213     default:
05214       status = HAL_ERROR;
05215       break;
05216   }
05217
05218   if (status == HAL_OK)
05219   {
05220     /* Configure the DMA Burst Mode */
05221     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
05222
05223     /* Enable the TIM DMA Request */
05224     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
05225   }
05226
05227   /* Return function status */
05228   return status;
05229 }
05230
05231 /**
05232   * @brief  Stop the DMA burst reading
05233   * @param  htim TIM handle
05234   * @param  BurstRequestSrc TIM DMA Request sources to disable.
05235   * @retval HAL status
05236   */
05237 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
05238 {
05239   HAL_StatusTypeDef status = HAL_OK;
05240
05241   /* Check the parameters */
05242   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
05243
05244   /* Abort the DMA transfer (at least disable the DMA channel) */
05245   switch (BurstRequestSrc)
05246   {
05247     case TIM_DMA_UPDATE:
05248     {
05249       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
05250       break;
05251     }
05252     case TIM_DMA_CC1:
05253     {
05254       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
05255       break;
05256     }
05257     case TIM_DMA_CC2:
05258     {
05259       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
05260       break;
05261     }
05262     case TIM_DMA_CC3:
05263     {
05264       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
05265       break;
05266     }
05267     case TIM_DMA_CC4:
05268     {
05269       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
05270       break;
05271     }
05272     case TIM_DMA_COM:
05273     {
05274       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
05275       break;
05276     }
05277     case TIM_DMA_TRIGGER:
05278     {
05279       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
05280       break;
05281     }
05282     default:
05283       status = HAL_ERROR;
05284       break;
05285   }
05286
05287   if (status == HAL_OK)
05288   {
05289     /* Disable the TIM Update DMA request */
05290     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
05291
05292     /* Change the DMA burst operation state */
05293     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
05294   }
05295
05296   /* Return function status */
05297   return status;
05298 }
05299
05300 /**
05301   * @brief  Generate a software event
05302   * @param  htim TIM handle
05303   * @param  EventSource specifies the event source.
05304   *          This parameter can be one of the following values:
05305   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
05306   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
05307   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
05308   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
05309   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
05310   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
05311   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
05312   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
05313   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
05314   * @note   Basic timers can only generate an update event.
05315   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
05316   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
05317   *         only for timer instances supporting break input(s).
05318   * @retval HAL status
05319   */
05320
05321 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
05322 {
05323   /* Check the parameters */
05324   assert_param(IS_TIM_INSTANCE(htim->Instance));
05325   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
05326
05327   /* Process Locked */
05328   __HAL_LOCK(htim);
05329
05330   /* Change the TIM state */
05331   htim->State = HAL_TIM_STATE_BUSY;
05332
05333   /* Set the event sources */
05334   htim->Instance->EGR = EventSource;
05335
05336   /* Change the TIM state */
05337   htim->State = HAL_TIM_STATE_READY;
05338
05339   __HAL_UNLOCK(htim);
05340
05341   /* Return function status */
05342   return HAL_OK;
05343 }
05344
05345 /**
05346   * @brief  Configures the OCRef clear feature
05347   * @param  htim TIM handle
05348   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
05349   *         contains the OCREF clear feature and parameters for the TIM peripheral.
05350   * @param  Channel specifies the TIM Channel
05351   *          This parameter can be one of the following values:
05352   *            @arg TIM_CHANNEL_1: TIM Channel 1
05353   *            @arg TIM_CHANNEL_2: TIM Channel 2
05354   *            @arg TIM_CHANNEL_3: TIM Channel 3
05355   *            @arg TIM_CHANNEL_4: TIM Channel 4
05356   *            @arg TIM_CHANNEL_5: TIM Channel 5
05357   *            @arg TIM_CHANNEL_6: TIM Channel 6
05358   * @retval HAL status
05359   */
05360 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
05361                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
05362                                            uint32_t Channel)
05363 {
05364   HAL_StatusTypeDef status = HAL_OK;
05365
05366   /* Check the parameters */
05367   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
05368   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
05369
05370   /* Process Locked */
05371   __HAL_LOCK(htim);
05372
05373   htim->State = HAL_TIM_STATE_BUSY;
05374
05375   switch (sClearInputConfig->ClearInputSource)
05376   {
05377     case TIM_CLEARINPUTSOURCE_NONE:
05378     {
05379       /* Clear the OCREF clear selection bit and the the ETR Bits */
05380       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
05381       {
05382         CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
05383
05384         /* Clear TIMx_AF2_OCRSEL (reset value) */
05385         CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
05386       }
05387       else
05388       {
05389         CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
05390       }
05391       break;
05392     }
05393
05394     case TIM_CLEARINPUTSOURCE_COMP1:
05395     case TIM_CLEARINPUTSOURCE_COMP2:
05396     case TIM_CLEARINPUTSOURCE_COMP3:
05397     case TIM_CLEARINPUTSOURCE_COMP4:
05398 #if defined (COMP5)
05399     case TIM_CLEARINPUTSOURCE_COMP5:
05400 #endif /* COMP5 */
05401 #if defined (COMP6)
05402     case TIM_CLEARINPUTSOURCE_COMP6:
05403 #endif /* COMP6 */
05404 #if defined (COMP7)
05405     case TIM_CLEARINPUTSOURCE_COMP7:
05406 #endif /* COMP7 */
05407     {
05408       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
05409       {
05410         /* Clear the OCREF clear selection bit */
05411         CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
05412       }
05413
05414       /* Set the clear input source */
05415       MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
05416       break;
05417     }
05418
05419     case TIM_CLEARINPUTSOURCE_ETR:
05420     {
05421       /* Check the parameters */
05422       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
05423       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
05424       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
05425
05426       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
05427       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
05428       {
05429         htim->State = HAL_TIM_STATE_READY;
05430         __HAL_UNLOCK(htim);
05431         return HAL_ERROR;
05432       }
05433
05434       TIM_ETR_SetConfig(htim->Instance,
05435                         sClearInputConfig->ClearInputPrescaler,
05436                         sClearInputConfig->ClearInputPolarity,
05437                         sClearInputConfig->ClearInputFilter);
05438
05439       if (IS_TIM_OCCS_INSTANCE(htim->Instance))
05440       {
05441         /* Set the OCREF clear selection bit */
05442         SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
05443
05444         /* Clear TIMx_AF2_OCRSEL (reset value) */
05445         CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
05446       }
05447       break;
05448     }
05449
05450     default:
05451       status = HAL_ERROR;
05452       break;
05453   }
05454
05455   if (status == HAL_OK)
05456   {
05457     switch (Channel)
05458     {
05459       case TIM_CHANNEL_1:
05460       {
05461         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05462         {
05463           /* Enable the OCREF clear feature for Channel 1 */
05464           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
05465         }
05466         else
05467         {
05468           /* Disable the OCREF clear feature for Channel 1 */
05469           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
05470         }
05471         break;
05472       }
05473       case TIM_CHANNEL_2:
05474       {
05475         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05476         {
05477           /* Enable the OCREF clear feature for Channel 2 */
05478           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
05479         }
05480         else
05481         {
05482           /* Disable the OCREF clear feature for Channel 2 */
05483           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
05484         }
05485         break;
05486       }
05487       case TIM_CHANNEL_3:
05488       {
05489         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05490         {
05491           /* Enable the OCREF clear feature for Channel 3 */
05492           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
05493         }
05494         else
05495         {
05496           /* Disable the OCREF clear feature for Channel 3 */
05497           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
05498         }
05499         break;
05500       }
05501       case TIM_CHANNEL_4:
05502       {
05503         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05504         {
05505           /* Enable the OCREF clear feature for Channel 4 */
05506           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
05507         }
05508         else
05509         {
05510           /* Disable the OCREF clear feature for Channel 4 */
05511           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
05512         }
05513         break;
05514       }
05515       case TIM_CHANNEL_5:
05516       {
05517         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05518         {
05519           /* Enable the OCREF clear feature for Channel 5 */
05520           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
05521         }
05522         else
05523         {
05524           /* Disable the OCREF clear feature for Channel 5 */
05525           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
05526         }
05527         break;
05528       }
05529       case TIM_CHANNEL_6:
05530       {
05531         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05532         {
05533           /* Enable the OCREF clear feature for Channel 6 */
05534           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
05535         }
05536         else
05537         {
05538           /* Disable the OCREF clear feature for Channel 6 */
05539           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
05540         }
05541         break;
05542       }
05543       default:
05544         break;
05545     }
05546   }
05547
05548   htim->State = HAL_TIM_STATE_READY;
05549
05550   __HAL_UNLOCK(htim);
05551
05552   return status;
05553 }
05554
05555 /**
05556   * @brief   Configures the clock source to be used
05557   * @param  htim TIM handle
05558   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
05559   *         contains the clock source information for the TIM peripheral.
05560   * @retval HAL status
05561   */
05562 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
05563 {
05564   HAL_StatusTypeDef status = HAL_OK;
05565   uint32_t tmpsmcr;
05566
05567   /* Process Locked */
05568   __HAL_LOCK(htim);
05569
05570   htim->State = HAL_TIM_STATE_BUSY;
05571
05572   /* Check the parameters */
05573   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
05574
05575   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
05576   tmpsmcr = htim->Instance->SMCR;
05577   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
05578   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05579   htim->Instance->SMCR = tmpsmcr;
05580
05581   switch (sClockSourceConfig->ClockSource)
05582   {
05583     case TIM_CLOCKSOURCE_INTERNAL:
05584     {
05585       assert_param(IS_TIM_INSTANCE(htim->Instance));
05586       break;
05587     }
05588
05589     case TIM_CLOCKSOURCE_ETRMODE1:
05590     {
05591       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
05592       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
05593
05594       /* Check ETR input conditioning related parameters */
05595       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
05596       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05597       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05598
05599       /* Configure the ETR Clock source */
05600       TIM_ETR_SetConfig(htim->Instance,
05601                         sClockSourceConfig->ClockPrescaler,
05602                         sClockSourceConfig->ClockPolarity,
05603                         sClockSourceConfig->ClockFilter);
05604
05605       /* Select the External clock mode1 and the ETRF trigger */
05606       tmpsmcr = htim->Instance->SMCR;
05607       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
05608       /* Write to TIMx SMCR */
05609       htim->Instance->SMCR = tmpsmcr;
05610       break;
05611     }
05612
05613     case TIM_CLOCKSOURCE_ETRMODE2:
05614     {
05615       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
05616       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
05617
05618       /* Check ETR input conditioning related parameters */
05619       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
05620       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05621       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05622
05623       /* Configure the ETR Clock source */
05624       TIM_ETR_SetConfig(htim->Instance,
05625                         sClockSourceConfig->ClockPrescaler,
05626                         sClockSourceConfig->ClockPolarity,
05627                         sClockSourceConfig->ClockFilter);
05628       /* Enable the External clock mode2 */
05629       htim->Instance->SMCR |= TIM_SMCR_ECE;
05630       break;
05631     }
05632
05633     case TIM_CLOCKSOURCE_TI1:
05634     {
05635       /* Check whether or not the timer instance supports external clock mode 1 */
05636       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05637
05638       /* Check TI1 input conditioning related parameters */
05639       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05640       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05641
05642       TIM_TI1_ConfigInputStage(htim->Instance,
05643                                sClockSourceConfig->ClockPolarity,
05644                                sClockSourceConfig->ClockFilter);
05645       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
05646       break;
05647     }
05648
05649     case TIM_CLOCKSOURCE_TI2:
05650     {
05651       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
05652       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05653
05654       /* Check TI2 input conditioning related parameters */
05655       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05656       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05657
05658       TIM_TI2_ConfigInputStage(htim->Instance,
05659                                sClockSourceConfig->ClockPolarity,
05660                                sClockSourceConfig->ClockFilter);
05661       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
05662       break;
05663     }
05664
05665     case TIM_CLOCKSOURCE_TI1ED:
05666     {
05667       /* Check whether or not the timer instance supports external clock mode 1 */
05668       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05669
05670       /* Check TI1 input conditioning related parameters */
05671       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05672       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05673
05674       TIM_TI1_ConfigInputStage(htim->Instance,
05675                                sClockSourceConfig->ClockPolarity,
05676                                sClockSourceConfig->ClockFilter);
05677       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
05678       break;
05679     }
05680
05681     case TIM_CLOCKSOURCE_ITR0:
05682     case TIM_CLOCKSOURCE_ITR1:
05683     case TIM_CLOCKSOURCE_ITR2:
05684     case TIM_CLOCKSOURCE_ITR3:
05685 #if defined (TIM5)
05686     case TIM_CLOCKSOURCE_ITR4:
05687 #endif /* TIM5 */
05688     case TIM_CLOCKSOURCE_ITR5:
05689     case TIM_CLOCKSOURCE_ITR6:
05690     case TIM_CLOCKSOURCE_ITR7:
05691     case TIM_CLOCKSOURCE_ITR8:
05692 #if defined (TIM20)
05693     case TIM_CLOCKSOURCE_ITR9:
05694 #endif /* TIM20 */
05695 #if defined (HRTIM1)
05696     case TIM_CLOCKSOURCE_ITR10:
05697 #endif /* HRTIM1 */
05698     case TIM_CLOCKSOURCE_ITR11:
05699     {
05700       /* Check whether or not the timer instance supports internal trigger input */
05701       assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
05702
05703       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
05704       break;
05705     }
05706
05707     default:
05708       status = HAL_ERROR;
05709       break;
05710   }
05711   htim->State = HAL_TIM_STATE_READY;
05712
05713   __HAL_UNLOCK(htim);
05714
05715   return status;
05716 }
05717
05718 /**
05719   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
05720   *         or a XOR combination between CH1_input, CH2_input & CH3_input
05721   * @param  htim TIM handle.
05722   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
05723   *         output of a XOR gate.
05724   *          This parameter can be one of the following values:
05725   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
05726   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
05727   *            pins are connected to the TI1 input (XOR combination)
05728   * @retval HAL status
05729   */
05730 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
05731 {
05732   uint32_t tmpcr2;
05733
05734   /* Check the parameters */
05735   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
05736   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
05737
05738   /* Get the TIMx CR2 register value */
05739   tmpcr2 = htim->Instance->CR2;
05740
05741   /* Reset the TI1 selection */
05742   tmpcr2 &= ~TIM_CR2_TI1S;
05743
05744   /* Set the TI1 selection */
05745   tmpcr2 |= TI1_Selection;
05746
05747   /* Write to TIMxCR2 */
05748   htim->Instance->CR2 = tmpcr2;
05749
05750   return HAL_OK;
05751 }
05752
05753 /**
05754   * @brief  Configures the TIM in Slave mode
05755   * @param  htim TIM handle.
05756   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
05757   *         contains the selected trigger (internal trigger input, filtered
05758   *         timer input or external trigger input) and the Slave mode
05759   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
05760   * @retval HAL status
05761   */
05762 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
05763 {
05764   /* Check the parameters */
05765   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
05766   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
05767   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
05768
05769   __HAL_LOCK(htim);
05770
05771   htim->State = HAL_TIM_STATE_BUSY;
05772
05773   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
05774   {
05775     htim->State = HAL_TIM_STATE_READY;
05776     __HAL_UNLOCK(htim);
05777     return HAL_ERROR;
05778   }
05779
05780   /* Disable Trigger Interrupt */
05781   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
05782
05783   /* Disable Trigger DMA request */
05784   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
05785
05786   htim->State = HAL_TIM_STATE_READY;
05787
05788   __HAL_UNLOCK(htim);
05789
05790   return HAL_OK;
05791 }
05792
05793 /**
05794   * @brief  Configures the TIM in Slave mode in interrupt mode
05795   * @param  htim TIM handle.
05796   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
05797   *         contains the selected trigger (internal trigger input, filtered
05798   *         timer input or external trigger input) and the Slave mode
05799   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
05800   * @retval HAL status
05801   */
05802 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
05803                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
05804 {
05805   /* Check the parameters */
05806   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
05807   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
05808   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
05809
05810   __HAL_LOCK(htim);
05811
05812   htim->State = HAL_TIM_STATE_BUSY;
05813
05814   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
05815   {
05816     htim->State = HAL_TIM_STATE_READY;
05817     __HAL_UNLOCK(htim);
05818     return HAL_ERROR;
05819   }
05820
05821   /* Enable Trigger Interrupt */
05822   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
05823
05824   /* Disable Trigger DMA request */
05825   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
05826
05827   htim->State = HAL_TIM_STATE_READY;
05828
05829   __HAL_UNLOCK(htim);
05830
05831   return HAL_OK;
05832 }
05833
05834 /**
05835   * @brief  Read the captured value from Capture Compare unit
05836   * @param  htim TIM handle.
05837   * @param  Channel TIM Channels to be enabled
05838   *          This parameter can be one of the following values:
05839   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
05840   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
05841   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
05842   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
05843   * @retval Captured value
05844   */
05845 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
05846 {
05847   uint32_t tmpreg = 0U;
05848
05849   switch (Channel)
05850   {
05851     case TIM_CHANNEL_1:
05852     {
05853       /* Check the parameters */
05854       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05855
05856       /* Return the capture 1 value */
05857       tmpreg =  htim->Instance->CCR1;
05858
05859       break;
05860     }
05861     case TIM_CHANNEL_2:
05862     {
05863       /* Check the parameters */
05864       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05865
05866       /* Return the capture 2 value */
05867       tmpreg =   htim->Instance->CCR2;
05868
05869       break;
05870     }
05871
05872     case TIM_CHANNEL_3:
05873     {
05874       /* Check the parameters */
05875       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
05876
05877       /* Return the capture 3 value */
05878       tmpreg =   htim->Instance->CCR3;
05879
05880       break;
05881     }
05882
05883     case TIM_CHANNEL_4:
05884     {
05885       /* Check the parameters */
05886       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
05887
05888       /* Return the capture 4 value */
05889       tmpreg =   htim->Instance->CCR4;
05890
05891       break;
05892     }
05893
05894     default:
05895       break;
05896   }
05897
05898   return tmpreg;
05899 }
05900
05901 /**
05902   * @}
05903   */
05904
05905 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
05906   *  @brief    TIM Callbacks functions
05907   *
05908 @verbatim
05909   ==============================================================================
05910                         ##### TIM Callbacks functions #####
05911   ==============================================================================
05912  [..]
05913    This section provides TIM callback functions:
05914    (+) TIM Period elapsed callback
05915    (+) TIM Output Compare callback
05916    (+) TIM Input capture callback
05917    (+) TIM Trigger callback
05918    (+) TIM Error callback
05919    (+) TIM Index callback
05920    (+) TIM Direction change callback
05921    (+) TIM Index error callback
05922    (+) TIM Transition error callback
05923
05924 @endverbatim
05925   * @{
05926   */
05927
05928 /**
05929   * @brief  Period elapsed callback in non-blocking mode
05930   * @param  htim TIM handle
05931   * @retval None
05932   */
05933 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
05934 {
05935   /* Prevent unused argument(s) compilation warning */
05936   UNUSED(htim);
05937
05938   /* NOTE : This function should not be modified, when the callback is needed,
05939             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
05940    */
05941 }
05942
05943 /**
05944   * @brief  Period elapsed half complete callback in non-blocking mode
05945   * @param  htim TIM handle
05946   * @retval None
05947   */
05948 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
05949 {
05950   /* Prevent unused argument(s) compilation warning */
05951   UNUSED(htim);
05952
05953   /* NOTE : This function should not be modified, when the callback is needed,
05954             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
05955    */
05956 }
05957
05958 /**
05959   * @brief  Output Compare callback in non-blocking mode
05960   * @param  htim TIM OC handle
05961   * @retval None
05962   */
05963 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
05964 {
05965   /* Prevent unused argument(s) compilation warning */
05966   UNUSED(htim);
05967
05968   /* NOTE : This function should not be modified, when the callback is needed,
05969             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
05970    */
05971 }
05972
05973 /**
05974   * @brief  Input Capture callback in non-blocking mode
05975   * @param  htim TIM IC handle
05976   * @retval None
05977   */
05978 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
05979 {
05980   /* Prevent unused argument(s) compilation warning */
05981   UNUSED(htim);
05982
05983   /* NOTE : This function should not be modified, when the callback is needed,
05984             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
05985    */
05986 }
05987
05988 /**
05989   * @brief  Input Capture half complete callback in non-blocking mode
05990   * @param  htim TIM IC handle
05991   * @retval None
05992   */
05993 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
05994 {
05995   /* Prevent unused argument(s) compilation warning */
05996   UNUSED(htim);
05997
05998   /* NOTE : This function should not be modified, when the callback is needed,
05999             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
06000    */
06001 }
06002
06003 /**
06004   * @brief  PWM Pulse finished callback in non-blocking mode
06005   * @param  htim TIM handle
06006   * @retval None
06007   */
06008 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
06009 {
06010   /* Prevent unused argument(s) compilation warning */
06011   UNUSED(htim);
06012
06013   /* NOTE : This function should not be modified, when the callback is needed,
06014             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
06015    */
06016 }
06017
06018 /**
06019   * @brief  PWM Pulse finished half complete callback in non-blocking mode
06020   * @param  htim TIM handle
06021   * @retval None
06022   */
06023 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
06024 {
06025   /* Prevent unused argument(s) compilation warning */
06026   UNUSED(htim);
06027
06028   /* NOTE : This function should not be modified, when the callback is needed,
06029             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
06030    */
06031 }
06032
06033 /**
06034   * @brief  Hall Trigger detection callback in non-blocking mode
06035   * @param  htim TIM handle
06036   * @retval None
06037   */
06038 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
06039 {
06040   /* Prevent unused argument(s) compilation warning */
06041   UNUSED(htim);
06042
06043   /* NOTE : This function should not be modified, when the callback is needed,
06044             the HAL_TIM_TriggerCallback could be implemented in the user file
06045    */
06046 }
06047
06048 /**
06049   * @brief  Hall Trigger detection half complete callback in non-blocking mode
06050   * @param  htim TIM handle
06051   * @retval None
06052   */
06053 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
06054 {
06055   /* Prevent unused argument(s) compilation warning */
06056   UNUSED(htim);
06057
06058   /* NOTE : This function should not be modified, when the callback is needed,
06059             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
06060    */
06061 }
06062
06063 /**
06064   * @brief  Timer error callback in non-blocking mode
06065   * @param  htim TIM handle
06066   * @retval None
06067   */
06068 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
06069 {
06070   /* Prevent unused argument(s) compilation warning */
06071   UNUSED(htim);
06072
06073   /* NOTE : This function should not be modified, when the callback is needed,
06074             the HAL_TIM_ErrorCallback could be implemented in the user file
06075    */
06076 }
06077
06078 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06079 /**
06080   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
06081   * @param htim tim handle
06082   * @param CallbackID ID of the callback to be registered
06083   *        This parameter can be one of the following values:
06084   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
06085   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
06086   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
06087   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
06088   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
06089   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
06090   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
06091   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
06092   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
06093   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
06094   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
06095   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
06096   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
06097   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
06098   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
06099   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
06100   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
06101   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
06102   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
06103   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
06104   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
06105   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
06106   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
06107   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
06108   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
06109   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
06110   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
06111   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
06112   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
06113   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
06114   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
06115   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
06116   *          @param pCallback pointer to the callback function
06117   *          @retval status
06118   */
06119 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
06120                                            pTIM_CallbackTypeDef pCallback)
06121 {
06122   HAL_StatusTypeDef status = HAL_OK;
06123
06124   if (pCallback == NULL)
06125   {
06126     return HAL_ERROR;
06127   }
06128
06129   if (htim->State == HAL_TIM_STATE_READY)
06130   {
06131     switch (CallbackID)
06132     {
06133       case HAL_TIM_BASE_MSPINIT_CB_ID :
06134         htim->Base_MspInitCallback                 = pCallback;
06135         break;
06136
06137       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06138         htim->Base_MspDeInitCallback               = pCallback;
06139         break;
06140
06141       case HAL_TIM_IC_MSPINIT_CB_ID :
06142         htim->IC_MspInitCallback                   = pCallback;
06143         break;
06144
06145       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06146         htim->IC_MspDeInitCallback                 = pCallback;
06147         break;
06148
06149       case HAL_TIM_OC_MSPINIT_CB_ID :
06150         htim->OC_MspInitCallback                   = pCallback;
06151         break;
06152
06153       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06154         htim->OC_MspDeInitCallback                 = pCallback;
06155         break;
06156
06157       case HAL_TIM_PWM_MSPINIT_CB_ID :
06158         htim->PWM_MspInitCallback                  = pCallback;
06159         break;
06160
06161       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06162         htim->PWM_MspDeInitCallback                = pCallback;
06163         break;
06164
06165       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06166         htim->OnePulse_MspInitCallback             = pCallback;
06167         break;
06168
06169       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06170         htim->OnePulse_MspDeInitCallback           = pCallback;
06171         break;
06172
06173       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06174         htim->Encoder_MspInitCallback              = pCallback;
06175         break;
06176
06177       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06178         htim->Encoder_MspDeInitCallback            = pCallback;
06179         break;
06180
06181       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06182         htim->HallSensor_MspInitCallback           = pCallback;
06183         break;
06184
06185       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06186         htim->HallSensor_MspDeInitCallback         = pCallback;
06187         break;
06188
06189       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
06190         htim->PeriodElapsedCallback                = pCallback;
06191         break;
06192
06193       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
06194         htim->PeriodElapsedHalfCpltCallback        = pCallback;
06195         break;
06196
06197       case HAL_TIM_TRIGGER_CB_ID :
06198         htim->TriggerCallback                      = pCallback;
06199         break;
06200
06201       case HAL_TIM_TRIGGER_HALF_CB_ID :
06202         htim->TriggerHalfCpltCallback              = pCallback;
06203         break;
06204
06205       case HAL_TIM_IC_CAPTURE_CB_ID :
06206         htim->IC_CaptureCallback                   = pCallback;
06207         break;
06208
06209       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
06210         htim->IC_CaptureHalfCpltCallback           = pCallback;
06211         break;
06212
06213       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
06214         htim->OC_DelayElapsedCallback              = pCallback;
06215         break;
06216
06217       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
06218         htim->PWM_PulseFinishedCallback            = pCallback;
06219         break;
06220
06221       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
06222         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
06223         break;
06224
06225       case HAL_TIM_ERROR_CB_ID :
06226         htim->ErrorCallback                        = pCallback;
06227         break;
06228
06229       case HAL_TIM_COMMUTATION_CB_ID :
06230         htim->CommutationCallback                  = pCallback;
06231         break;
06232
06233       case HAL_TIM_COMMUTATION_HALF_CB_ID :
06234         htim->CommutationHalfCpltCallback          = pCallback;
06235         break;
06236
06237       case HAL_TIM_BREAK_CB_ID :
06238         htim->BreakCallback                        = pCallback;
06239         break;
06240
06241       case HAL_TIM_BREAK2_CB_ID :
06242         htim->Break2Callback                       = pCallback;
06243         break;
06244
06245       case HAL_TIM_ENCODER_INDEX_CB_ID :
06246         htim->EncoderIndexCallback                 = pCallback;
06247         break;
06248
06249       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
06250         htim->DirectionChangeCallback              = pCallback;
06251         break;
06252
06253       case HAL_TIM_INDEX_ERROR_CB_ID :
06254         htim->IndexErrorCallback                   = pCallback;
06255         break;
06256
06257       case HAL_TIM_TRANSITION_ERROR_CB_ID :
06258         htim->TransitionErrorCallback              = pCallback;
06259         break;
06260
06261       default :
06262         /* Return error status */
06263         status = HAL_ERROR;
06264         break;
06265     }
06266   }
06267   else if (htim->State == HAL_TIM_STATE_RESET)
06268   {
06269     switch (CallbackID)
06270     {
06271       case HAL_TIM_BASE_MSPINIT_CB_ID :
06272         htim->Base_MspInitCallback         = pCallback;
06273         break;
06274
06275       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06276         htim->Base_MspDeInitCallback       = pCallback;
06277         break;
06278
06279       case HAL_TIM_IC_MSPINIT_CB_ID :
06280         htim->IC_MspInitCallback           = pCallback;
06281         break;
06282
06283       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06284         htim->IC_MspDeInitCallback         = pCallback;
06285         break;
06286
06287       case HAL_TIM_OC_MSPINIT_CB_ID :
06288         htim->OC_MspInitCallback           = pCallback;
06289         break;
06290
06291       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06292         htim->OC_MspDeInitCallback         = pCallback;
06293         break;
06294
06295       case HAL_TIM_PWM_MSPINIT_CB_ID :
06296         htim->PWM_MspInitCallback          = pCallback;
06297         break;
06298
06299       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06300         htim->PWM_MspDeInitCallback        = pCallback;
06301         break;
06302
06303       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06304         htim->OnePulse_MspInitCallback     = pCallback;
06305         break;
06306
06307       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06308         htim->OnePulse_MspDeInitCallback   = pCallback;
06309         break;
06310
06311       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06312         htim->Encoder_MspInitCallback      = pCallback;
06313         break;
06314
06315       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06316         htim->Encoder_MspDeInitCallback    = pCallback;
06317         break;
06318
06319       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06320         htim->HallSensor_MspInitCallback   = pCallback;
06321         break;
06322
06323       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06324         htim->HallSensor_MspDeInitCallback = pCallback;
06325         break;
06326
06327       default :
06328         /* Return error status */
06329         status = HAL_ERROR;
06330         break;
06331     }
06332   }
06333   else
06334   {
06335     /* Return error status */
06336     status = HAL_ERROR;
06337   }
06338
06339   return status;
06340 }
06341
06342 /**
06343   * @brief  Unregister a TIM callback
06344   *         TIM callback is redirected to the weak predefined callback
06345   * @param htim tim handle
06346   * @param CallbackID ID of the callback to be unregistered
06347   *        This parameter can be one of the following values:
06348   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
06349   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
06350   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
06351   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
06352   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
06353   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
06354   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
06355   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
06356   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
06357   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
06358   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
06359   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
06360   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
06361   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
06362   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
06363   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
06364   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
06365   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
06366   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
06367   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
06368   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
06369   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
06370   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
06371   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
06372   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
06373   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
06374   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
06375   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
06376   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
06377   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
06378   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
06379   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
06380   *          @retval status
06381   */
06382 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
06383 {
06384   HAL_StatusTypeDef status = HAL_OK;
06385
06386   if (htim->State == HAL_TIM_STATE_READY)
06387   {
06388     switch (CallbackID)
06389     {
06390       case HAL_TIM_BASE_MSPINIT_CB_ID :
06391         /* Legacy weak Base MspInit Callback */
06392         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
06393         break;
06394
06395       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06396         /* Legacy weak Base Msp DeInit Callback */
06397         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
06398         break;
06399
06400       case HAL_TIM_IC_MSPINIT_CB_ID :
06401         /* Legacy weak IC Msp Init Callback */
06402         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
06403         break;
06404
06405       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06406         /* Legacy weak IC Msp DeInit Callback */
06407         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
06408         break;
06409
06410       case HAL_TIM_OC_MSPINIT_CB_ID :
06411         /* Legacy weak OC Msp Init Callback */
06412         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
06413         break;
06414
06415       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06416         /* Legacy weak OC Msp DeInit Callback */
06417         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
06418         break;
06419
06420       case HAL_TIM_PWM_MSPINIT_CB_ID :
06421         /* Legacy weak PWM Msp Init Callback */
06422         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
06423         break;
06424
06425       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06426         /* Legacy weak PWM Msp DeInit Callback */
06427         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
06428         break;
06429
06430       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06431         /* Legacy weak One Pulse Msp Init Callback */
06432         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
06433         break;
06434
06435       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06436         /* Legacy weak One Pulse Msp DeInit Callback */
06437         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
06438         break;
06439
06440       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06441         /* Legacy weak Encoder Msp Init Callback */
06442         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
06443         break;
06444
06445       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06446         /* Legacy weak Encoder Msp DeInit Callback */
06447         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
06448         break;
06449
06450       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06451         /* Legacy weak Hall Sensor Msp Init Callback */
06452         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
06453         break;
06454
06455       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06456         /* Legacy weak Hall Sensor Msp DeInit Callback */
06457         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
06458         break;
06459
06460       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
06461         /* Legacy weak Period Elapsed Callback */
06462         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
06463         break;
06464
06465       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
06466         /* Legacy weak Period Elapsed half complete Callback */
06467         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
06468         break;
06469
06470       case HAL_TIM_TRIGGER_CB_ID :
06471         /* Legacy weak Trigger Callback */
06472         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
06473         break;
06474
06475       case HAL_TIM_TRIGGER_HALF_CB_ID :
06476         /* Legacy weak Trigger half complete Callback */
06477         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
06478         break;
06479
06480       case HAL_TIM_IC_CAPTURE_CB_ID :
06481         /* Legacy weak IC Capture Callback */
06482         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
06483         break;
06484
06485       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
06486         /* Legacy weak IC Capture half complete Callback */
06487         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
06488         break;
06489
06490       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
06491         /* Legacy weak OC Delay Elapsed Callback */
06492         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
06493         break;
06494
06495       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
06496         /* Legacy weak PWM Pulse Finished Callback */
06497         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
06498         break;
06499
06500       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
06501         /* Legacy weak PWM Pulse Finished half complete Callback */
06502         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
06503         break;
06504
06505       case HAL_TIM_ERROR_CB_ID :
06506         /* Legacy weak Error Callback */
06507         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
06508         break;
06509
06510       case HAL_TIM_COMMUTATION_CB_ID :
06511         /* Legacy weak Commutation Callback */
06512         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
06513         break;
06514
06515       case HAL_TIM_COMMUTATION_HALF_CB_ID :
06516         /* Legacy weak Commutation half complete Callback */
06517         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
06518         break;
06519
06520       case HAL_TIM_BREAK_CB_ID :
06521         /* Legacy weak Break Callback */
06522         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
06523         break;
06524
06525       case HAL_TIM_BREAK2_CB_ID :
06526         /* Legacy weak Break2 Callback */
06527         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
06528         break;
06529
06530       case HAL_TIM_ENCODER_INDEX_CB_ID :
06531         /* Legacy weak Encoder Index Callback */
06532         htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
06533         break;
06534
06535       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
06536         /* Legacy weak Direction Change Callback */
06537         htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
06538         break;
06539
06540       case HAL_TIM_INDEX_ERROR_CB_ID :
06541         /* Legacy weak Index Error Callback */
06542         htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
06543         break;
06544
06545       case HAL_TIM_TRANSITION_ERROR_CB_ID :
06546         /* Legacy weak Transition Error Callback */
06547         htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
06548         break;
06549
06550       default :
06551         /* Return error status */
06552         status = HAL_ERROR;
06553         break;
06554     }
06555   }
06556   else if (htim->State == HAL_TIM_STATE_RESET)
06557   {
06558     switch (CallbackID)
06559     {
06560       case HAL_TIM_BASE_MSPINIT_CB_ID :
06561         /* Legacy weak Base MspInit Callback */
06562         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
06563         break;
06564
06565       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06566         /* Legacy weak Base Msp DeInit Callback */
06567         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
06568         break;
06569
06570       case HAL_TIM_IC_MSPINIT_CB_ID :
06571         /* Legacy weak IC Msp Init Callback */
06572         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
06573         break;
06574
06575       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06576         /* Legacy weak IC Msp DeInit Callback */
06577         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
06578         break;
06579
06580       case HAL_TIM_OC_MSPINIT_CB_ID :
06581         /* Legacy weak OC Msp Init Callback */
06582         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
06583         break;
06584
06585       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06586         /* Legacy weak OC Msp DeInit Callback */
06587         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
06588         break;
06589
06590       case HAL_TIM_PWM_MSPINIT_CB_ID :
06591         /* Legacy weak PWM Msp Init Callback */
06592         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
06593         break;
06594
06595       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06596         /* Legacy weak PWM Msp DeInit Callback */
06597         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
06598         break;
06599
06600       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06601         /* Legacy weak One Pulse Msp Init Callback */
06602         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
06603         break;
06604
06605       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06606         /* Legacy weak One Pulse Msp DeInit Callback */
06607         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
06608         break;
06609
06610       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06611         /* Legacy weak Encoder Msp Init Callback */
06612         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
06613         break;
06614
06615       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06616         /* Legacy weak Encoder Msp DeInit Callback */
06617         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
06618         break;
06619
06620       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06621         /* Legacy weak Hall Sensor Msp Init Callback */
06622         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
06623         break;
06624
06625       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06626         /* Legacy weak Hall Sensor Msp DeInit Callback */
06627         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
06628         break;
06629
06630       default :
06631         /* Return error status */
06632         status = HAL_ERROR;
06633         break;
06634     }
06635   }
06636   else
06637   {
06638     /* Return error status */
06639     status = HAL_ERROR;
06640   }
06641
06642   return status;
06643 }
06644 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06645
06646 /**
06647   * @}
06648   */
06649
06650 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
06651   *  @brief   TIM Peripheral State functions
06652   *
06653 @verbatim
06654   ==============================================================================
06655                         ##### Peripheral State functions #####
06656   ==============================================================================
06657     [..]
06658     This subsection permits to get in run-time the status of the peripheral
06659     and the data flow.
06660
06661 @endverbatim
06662   * @{
06663   */
06664
06665 /**
06666   * @brief  Return the TIM Base handle state.
06667   * @param  htim TIM Base handle
06668   * @retval HAL state
06669   */
06670 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
06671 {
06672   return htim->State;
06673 }
06674
06675 /**
06676   * @brief  Return the TIM OC handle state.
06677   * @param  htim TIM Output Compare handle
06678   * @retval HAL state
06679   */
06680 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
06681 {
06682   return htim->State;
06683 }
06684
06685 /**
06686   * @brief  Return the TIM PWM handle state.
06687   * @param  htim TIM handle
06688   * @retval HAL state
06689   */
06690 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
06691 {
06692   return htim->State;
06693 }
06694
06695 /**
06696   * @brief  Return the TIM Input Capture handle state.
06697   * @param  htim TIM IC handle
06698   * @retval HAL state
06699   */
06700 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
06701 {
06702   return htim->State;
06703 }
06704
06705 /**
06706   * @brief  Return the TIM One Pulse Mode handle state.
06707   * @param  htim TIM OPM handle
06708   * @retval HAL state
06709   */
06710 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
06711 {
06712   return htim->State;
06713 }
06714
06715 /**
06716   * @brief  Return the TIM Encoder Mode handle state.
06717   * @param  htim TIM Encoder Interface handle
06718   * @retval HAL state
06719   */
06720 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
06721 {
06722   return htim->State;
06723 }
06724
06725 /**
06726   * @brief  Return the TIM Encoder Mode handle state.
06727   * @param  htim TIM handle
06728   * @retval Active channel
06729   */
06730 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
06731 {
06732   return htim->Channel;
06733 }
06734
06735 /**
06736   * @brief  Return actual state of the TIM channel.
06737   * @param  htim TIM handle
06738   * @param  Channel TIM Channel
06739   *          This parameter can be one of the following values:
06740   *            @arg TIM_CHANNEL_1: TIM Channel 1
06741   *            @arg TIM_CHANNEL_2: TIM Channel 2
06742   *            @arg TIM_CHANNEL_3: TIM Channel 3
06743   *            @arg TIM_CHANNEL_4: TIM Channel 4
06744   *            @arg TIM_CHANNEL_5: TIM Channel 5
06745   *            @arg TIM_CHANNEL_6: TIM Channel 6
06746   * @retval TIM Channel state
06747   */
06748 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
06749 {
06750   HAL_TIM_ChannelStateTypeDef channel_state;
06751
06752   /* Check the parameters */
06753   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
06754
06755   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
06756
06757   return channel_state;
06758 }
06759
06760 /**
06761   * @brief  Return actual state of a DMA burst operation.
06762   * @param  htim TIM handle
06763   * @retval DMA burst state
06764   */
06765 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
06766 {
06767   /* Check the parameters */
06768   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
06769
06770   return htim->DMABurstState;
06771 }
06772
06773 /**
06774   * @}
06775   */
06776
06777 /**
06778   * @}
06779   */
06780
06781 /** @defgroup TIM_Private_Functions TIM Private Functions
06782   * @{
06783   */
06784
06785 /**
06786   * @brief  TIM DMA error callback
06787   * @param  hdma pointer to DMA handle.
06788   * @retval None
06789   */
06790 void TIM_DMAError(DMA_HandleTypeDef *hdma)
06791 {
06792   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06793
06794   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06795   {
06796     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06797     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06798   }
06799   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06800   {
06801     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06802     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06803   }
06804   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06805   {
06806     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06807     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06808   }
06809   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06810   {
06811     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06812     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06813   }
06814   else
06815   {
06816     htim->State = HAL_TIM_STATE_READY;
06817   }
06818
06819 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06820   htim->ErrorCallback(htim);
06821 #else
06822   HAL_TIM_ErrorCallback(htim);
06823 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06824
06825   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06826 }
06827
06828 /**
06829   * @brief  TIM DMA Delay Pulse complete callback.
06830   * @param  hdma pointer to DMA handle.
06831   * @retval None
06832   */
06833 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
06834 {
06835   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06836
06837   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06838   {
06839     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06840
06841     if (hdma->Init.Mode == DMA_NORMAL)
06842     {
06843       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06844     }
06845   }
06846   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06847   {
06848     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06849
06850     if (hdma->Init.Mode == DMA_NORMAL)
06851     {
06852       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06853     }
06854   }
06855   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06856   {
06857     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06858
06859     if (hdma->Init.Mode == DMA_NORMAL)
06860     {
06861       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06862     }
06863   }
06864   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06865   {
06866     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06867
06868     if (hdma->Init.Mode == DMA_NORMAL)
06869     {
06870       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06871     }
06872   }
06873   else
06874   {
06875     /* nothing to do */
06876   }
06877
06878 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06879   htim->PWM_PulseFinishedCallback(htim);
06880 #else
06881   HAL_TIM_PWM_PulseFinishedCallback(htim);
06882 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06883
06884   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06885 }
06886
06887 /**
06888   * @brief  TIM DMA Delay Pulse half complete callback.
06889   * @param  hdma pointer to DMA handle.
06890   * @retval None
06891   */
06892 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
06893 {
06894   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06895
06896   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06897   {
06898     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06899   }
06900   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06901   {
06902     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06903   }
06904   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06905   {
06906     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06907   }
06908   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06909   {
06910     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06911   }
06912   else
06913   {
06914     /* nothing to do */
06915   }
06916
06917 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06918   htim->PWM_PulseFinishedHalfCpltCallback(htim);
06919 #else
06920   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
06921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06922
06923   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06924 }
06925
06926 /**
06927   * @brief  TIM DMA Capture complete callback.
06928   * @param  hdma pointer to DMA handle.
06929   * @retval None
06930   */
06931 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
06932 {
06933   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06934
06935   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06936   {
06937     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06938
06939     if (hdma->Init.Mode == DMA_NORMAL)
06940     {
06941       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06942       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06943     }
06944   }
06945   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06946   {
06947     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06948
06949     if (hdma->Init.Mode == DMA_NORMAL)
06950     {
06951       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06952       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06953     }
06954   }
06955   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06956   {
06957     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06958
06959     if (hdma->Init.Mode == DMA_NORMAL)
06960     {
06961       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06962       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06963     }
06964   }
06965   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06966   {
06967     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06968
06969     if (hdma->Init.Mode == DMA_NORMAL)
06970     {
06971       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06972       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06973     }
06974   }
06975   else
06976   {
06977     /* nothing to do */
06978   }
06979
06980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06981   htim->IC_CaptureCallback(htim);
06982 #else
06983   HAL_TIM_IC_CaptureCallback(htim);
06984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06985
06986   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06987 }
06988
06989 /**
06990   * @brief  TIM DMA Capture half complete callback.
06991   * @param  hdma pointer to DMA handle.
06992   * @retval None
06993   */
06994 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
06995 {
06996   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06997
06998   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06999   {
07000     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
07001   }
07002   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
07003   {
07004     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
07005   }
07006   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
07007   {
07008     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
07009   }
07010   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
07011   {
07012     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
07013   }
07014   else
07015   {
07016     /* nothing to do */
07017   }
07018
07019 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07020   htim->IC_CaptureHalfCpltCallback(htim);
07021 #else
07022   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
07023 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07024
07025   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
07026 }
07027
07028 /**
07029   * @brief  TIM DMA Period Elapse complete callback.
07030   * @param  hdma pointer to DMA handle.
07031   * @retval None
07032   */
07033 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
07034 {
07035   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
07036
07037   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
07038   {
07039     htim->State = HAL_TIM_STATE_READY;
07040   }
07041
07042 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07043   htim->PeriodElapsedCallback(htim);
07044 #else
07045   HAL_TIM_PeriodElapsedCallback(htim);
07046 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07047 }
07048
07049 /**
07050   * @brief  TIM DMA Period Elapse half complete callback.
07051   * @param  hdma pointer to DMA handle.
07052   * @retval None
07053   */
07054 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
07055 {
07056   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
07057
07058 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07059   htim->PeriodElapsedHalfCpltCallback(htim);
07060 #else
07061   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
07062 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07063 }
07064
07065 /**
07066   * @brief  TIM DMA Trigger callback.
07067   * @param  hdma pointer to DMA handle.
07068   * @retval None
07069   */
07070 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
07071 {
07072   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
07073
07074   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
07075   {
07076     htim->State = HAL_TIM_STATE_READY;
07077   }
07078
07079 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07080   htim->TriggerCallback(htim);
07081 #else
07082   HAL_TIM_TriggerCallback(htim);
07083 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07084 }
07085
07086 /**
07087   * @brief  TIM DMA Trigger half complete callback.
07088   * @param  hdma pointer to DMA handle.
07089   * @retval None
07090   */
07091 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
07092 {
07093   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
07094
07095 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07096   htim->TriggerHalfCpltCallback(htim);
07097 #else
07098   HAL_TIM_TriggerHalfCpltCallback(htim);
07099 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07100 }
07101
07102 /**
07103   * @brief  Time Base configuration
07104   * @param  TIMx TIM peripheral
07105   * @param  Structure TIM Base configuration structure
07106   * @retval None
07107   */
07108 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
07109 {
07110   uint32_t tmpcr1;
07111   tmpcr1 = TIMx->CR1;
07112
07113   /* Set TIM Time Base Unit parameters ---------------------------------------*/
07114   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
07115   {
07116     /* Select the Counter Mode */
07117     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
07118     tmpcr1 |= Structure->CounterMode;
07119   }
07120
07121   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
07122   {
07123     /* Set the clock division */
07124     tmpcr1 &= ~TIM_CR1_CKD;
07125     tmpcr1 |= (uint32_t)Structure->ClockDivision;
07126   }
07127
07128   /* Set the auto-reload preload */
07129   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
07130
07131   TIMx->CR1 = tmpcr1;
07132
07133   /* Set the Autoreload value */
07134   TIMx->ARR = (uint32_t)Structure->Period ;
07135
07136   /* Set the Prescaler value */
07137   TIMx->PSC = Structure->Prescaler;
07138
07139   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
07140   {
07141     /* Set the Repetition Counter value */
07142     TIMx->RCR = Structure->RepetitionCounter;
07143   }
07144
07145   /* Generate an update event to reload the Prescaler
07146      and the repetition counter (only for advanced timer) value immediately */
07147   TIMx->EGR = TIM_EGR_UG;
07148
07149   /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
07150   if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
07151   {
07152     /* Clear the update flag */
07153     CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
07154   }
07155 }
07156
07157 /**
07158   * @brief  Timer Output Compare 1 configuration
07159   * @param  TIMx to select the TIM peripheral
07160   * @param  OC_Config The output configuration structure
07161   * @retval None
07162   */
07163 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07164 {
07165   uint32_t tmpccmrx;
07166   uint32_t tmpccer;
07167   uint32_t tmpcr2;
07168
07169   /* Get the TIMx CCER register value */
07170   tmpccer = TIMx->CCER;
07171
07172   /* Disable the Channel 1: Reset the CC1E Bit */
07173   TIMx->CCER &= ~TIM_CCER_CC1E;
07174
07175   /* Get the TIMx CR2 register value */
07176   tmpcr2 =  TIMx->CR2;
07177
07178   /* Get the TIMx CCMR1 register value */
07179   tmpccmrx = TIMx->CCMR1;
07180
07181   /* Reset the Output Compare Mode Bits */
07182   tmpccmrx &= ~TIM_CCMR1_OC1M;
07183   tmpccmrx &= ~TIM_CCMR1_CC1S;
07184   /* Select the Output Compare Mode */
07185   tmpccmrx |= OC_Config->OCMode;
07186
07187   /* Reset the Output Polarity level */
07188   tmpccer &= ~TIM_CCER_CC1P;
07189   /* Set the Output Compare Polarity */
07190   tmpccer |= OC_Config->OCPolarity;
07191
07192   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
07193   {
07194     /* Check parameters */
07195     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07196
07197     /* Reset the Output N Polarity level */
07198     tmpccer &= ~TIM_CCER_CC1NP;
07199     /* Set the Output N Polarity */
07200     tmpccer |= OC_Config->OCNPolarity;
07201     /* Reset the Output N State */
07202     tmpccer &= ~TIM_CCER_CC1NE;
07203   }
07204
07205   if (IS_TIM_BREAK_INSTANCE(TIMx))
07206   {
07207     /* Check parameters */
07208     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07209     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07210
07211     /* Reset the Output Compare and Output Compare N IDLE State */
07212     tmpcr2 &= ~TIM_CR2_OIS1;
07213     tmpcr2 &= ~TIM_CR2_OIS1N;
07214     /* Set the Output Idle state */
07215     tmpcr2 |= OC_Config->OCIdleState;
07216     /* Set the Output N Idle state */
07217     tmpcr2 |= OC_Config->OCNIdleState;
07218   }
07219
07220   /* Write to TIMx CR2 */
07221   TIMx->CR2 = tmpcr2;
07222
07223   /* Write to TIMx CCMR1 */
07224   TIMx->CCMR1 = tmpccmrx;
07225
07226   /* Set the Capture Compare Register value */
07227   TIMx->CCR1 = OC_Config->Pulse;
07228
07229   /* Write to TIMx CCER */
07230   TIMx->CCER = tmpccer;
07231 }
07232
07233 /**
07234   * @brief  Timer Output Compare 2 configuration
07235   * @param  TIMx to select the TIM peripheral
07236   * @param  OC_Config The output configuration structure
07237   * @retval None
07238   */
07239 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07240 {
07241   uint32_t tmpccmrx;
07242   uint32_t tmpccer;
07243   uint32_t tmpcr2;
07244
07245   /* Get the TIMx CCER register value */
07246   tmpccer = TIMx->CCER;
07247
07248   /* Disable the Channel 2: Reset the CC2E Bit */
07249   TIMx->CCER &= ~TIM_CCER_CC2E;
07250
07251   /* Get the TIMx CR2 register value */
07252   tmpcr2 =  TIMx->CR2;
07253
07254   /* Get the TIMx CCMR1 register value */
07255   tmpccmrx = TIMx->CCMR1;
07256
07257   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07258   tmpccmrx &= ~TIM_CCMR1_OC2M;
07259   tmpccmrx &= ~TIM_CCMR1_CC2S;
07260
07261   /* Select the Output Compare Mode */
07262   tmpccmrx |= (OC_Config->OCMode << 8U);
07263
07264   /* Reset the Output Polarity level */
07265   tmpccer &= ~TIM_CCER_CC2P;
07266   /* Set the Output Compare Polarity */
07267   tmpccer |= (OC_Config->OCPolarity << 4U);
07268
07269   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
07270   {
07271     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07272
07273     /* Reset the Output N Polarity level */
07274     tmpccer &= ~TIM_CCER_CC2NP;
07275     /* Set the Output N Polarity */
07276     tmpccer |= (OC_Config->OCNPolarity << 4U);
07277     /* Reset the Output N State */
07278     tmpccer &= ~TIM_CCER_CC2NE;
07279   }
07280
07281   if (IS_TIM_BREAK_INSTANCE(TIMx))
07282   {
07283     /* Check parameters */
07284     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07285     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07286
07287     /* Reset the Output Compare and Output Compare N IDLE State */
07288     tmpcr2 &= ~TIM_CR2_OIS2;
07289     tmpcr2 &= ~TIM_CR2_OIS2N;
07290     /* Set the Output Idle state */
07291     tmpcr2 |= (OC_Config->OCIdleState << 2U);
07292     /* Set the Output N Idle state */
07293     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
07294   }
07295
07296   /* Write to TIMx CR2 */
07297   TIMx->CR2 = tmpcr2;
07298
07299   /* Write to TIMx CCMR1 */
07300   TIMx->CCMR1 = tmpccmrx;
07301
07302   /* Set the Capture Compare Register value */
07303   TIMx->CCR2 = OC_Config->Pulse;
07304
07305   /* Write to TIMx CCER */
07306   TIMx->CCER = tmpccer;
07307 }
07308
07309 /**
07310   * @brief  Timer Output Compare 3 configuration
07311   * @param  TIMx to select the TIM peripheral
07312   * @param  OC_Config The output configuration structure
07313   * @retval None
07314   */
07315 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07316 {
07317   uint32_t tmpccmrx;
07318   uint32_t tmpccer;
07319   uint32_t tmpcr2;
07320
07321   /* Get the TIMx CCER register value */
07322   tmpccer = TIMx->CCER;
07323
07324   /* Disable the Channel 3: Reset the CC2E Bit */
07325   TIMx->CCER &= ~TIM_CCER_CC3E;
07326
07327   /* Get the TIMx CR2 register value */
07328   tmpcr2 =  TIMx->CR2;
07329
07330   /* Get the TIMx CCMR2 register value */
07331   tmpccmrx = TIMx->CCMR2;
07332
07333   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07334   tmpccmrx &= ~TIM_CCMR2_OC3M;
07335   tmpccmrx &= ~TIM_CCMR2_CC3S;
07336   /* Select the Output Compare Mode */
07337   tmpccmrx |= OC_Config->OCMode;
07338
07339   /* Reset the Output Polarity level */
07340   tmpccer &= ~TIM_CCER_CC3P;
07341   /* Set the Output Compare Polarity */
07342   tmpccer |= (OC_Config->OCPolarity << 8U);
07343
07344   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
07345   {
07346     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07347
07348     /* Reset the Output N Polarity level */
07349     tmpccer &= ~TIM_CCER_CC3NP;
07350     /* Set the Output N Polarity */
07351     tmpccer |= (OC_Config->OCNPolarity << 8U);
07352     /* Reset the Output N State */
07353     tmpccer &= ~TIM_CCER_CC3NE;
07354   }
07355
07356   if (IS_TIM_BREAK_INSTANCE(TIMx))
07357   {
07358     /* Check parameters */
07359     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07360     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07361
07362     /* Reset the Output Compare and Output Compare N IDLE State */
07363     tmpcr2 &= ~TIM_CR2_OIS3;
07364     tmpcr2 &= ~TIM_CR2_OIS3N;
07365     /* Set the Output Idle state */
07366     tmpcr2 |= (OC_Config->OCIdleState << 4U);
07367     /* Set the Output N Idle state */
07368     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
07369   }
07370
07371   /* Write to TIMx CR2 */
07372   TIMx->CR2 = tmpcr2;
07373
07374   /* Write to TIMx CCMR2 */
07375   TIMx->CCMR2 = tmpccmrx;
07376
07377   /* Set the Capture Compare Register value */
07378   TIMx->CCR3 = OC_Config->Pulse;
07379
07380   /* Write to TIMx CCER */
07381   TIMx->CCER = tmpccer;
07382 }
07383
07384 /**
07385   * @brief  Timer Output Compare 4 configuration
07386   * @param  TIMx to select the TIM peripheral
07387   * @param  OC_Config The output configuration structure
07388   * @retval None
07389   */
07390 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07391 {
07392   uint32_t tmpccmrx;
07393   uint32_t tmpccer;
07394   uint32_t tmpcr2;
07395
07396   /* Get the TIMx CCER register value */
07397   tmpccer = TIMx->CCER;
07398
07399   /* Disable the Channel 4: Reset the CC4E Bit */
07400   TIMx->CCER &= ~TIM_CCER_CC4E;
07401
07402   /* Get the TIMx CR2 register value */
07403   tmpcr2 =  TIMx->CR2;
07404
07405   /* Get the TIMx CCMR2 register value */
07406   tmpccmrx = TIMx->CCMR2;
07407
07408   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07409   tmpccmrx &= ~TIM_CCMR2_OC4M;
07410   tmpccmrx &= ~TIM_CCMR2_CC4S;
07411
07412   /* Select the Output Compare Mode */
07413   tmpccmrx |= (OC_Config->OCMode << 8U);
07414
07415   /* Reset the Output Polarity level */
07416   tmpccer &= ~TIM_CCER_CC4P;
07417   /* Set the Output Compare Polarity */
07418   tmpccer |= (OC_Config->OCPolarity << 12U);
07419
07420   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
07421   {
07422     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07423
07424     /* Reset the Output N Polarity level */
07425     tmpccer &= ~TIM_CCER_CC4NP;
07426     /* Set the Output N Polarity */
07427     tmpccer |= (OC_Config->OCNPolarity << 12U);
07428     /* Reset the Output N State */
07429     tmpccer &= ~TIM_CCER_CC4NE;
07430   }
07431
07432   if (IS_TIM_BREAK_INSTANCE(TIMx))
07433   {
07434     /* Check parameters */
07435     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07436     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07437
07438     /* Reset the Output Compare IDLE State */
07439     tmpcr2 &= ~TIM_CR2_OIS4;
07440     /* Reset the Output Compare N IDLE State */
07441     tmpcr2 &= ~TIM_CR2_OIS4N;
07442
07443     /* Set the Output Idle state */
07444     tmpcr2 |= (OC_Config->OCIdleState << 6U);
07445     /* Set the Output N Idle state */
07446     tmpcr2 |= (OC_Config->OCNIdleState << 6U);
07447   }
07448
07449   /* Write to TIMx CR2 */
07450   TIMx->CR2 = tmpcr2;
07451
07452   /* Write to TIMx CCMR2 */
07453   TIMx->CCMR2 = tmpccmrx;
07454
07455   /* Set the Capture Compare Register value */
07456   TIMx->CCR4 = OC_Config->Pulse;
07457
07458   /* Write to TIMx CCER */
07459   TIMx->CCER = tmpccer;
07460 }
07461
07462 /**
07463   * @brief  Timer Output Compare 5 configuration
07464   * @param  TIMx to select the TIM peripheral
07465   * @param  OC_Config The output configuration structure
07466   * @retval None
07467   */
07468 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
07469                               const TIM_OC_InitTypeDef *OC_Config)
07470 {
07471   uint32_t tmpccmrx;
07472   uint32_t tmpccer;
07473   uint32_t tmpcr2;
07474
07475   /* Get the TIMx CCER register value */
07476   tmpccer = TIMx->CCER;
07477
07478   /* Disable the output: Reset the CCxE Bit */
07479   TIMx->CCER &= ~TIM_CCER_CC5E;
07480
07481   /* Get the TIMx CR2 register value */
07482   tmpcr2 =  TIMx->CR2;
07483   /* Get the TIMx CCMR1 register value */
07484   tmpccmrx = TIMx->CCMR3;
07485
07486   /* Reset the Output Compare Mode Bits */
07487   tmpccmrx &= ~(TIM_CCMR3_OC5M);
07488   /* Select the Output Compare Mode */
07489   tmpccmrx |= OC_Config->OCMode;
07490
07491   /* Reset the Output Polarity level */
07492   tmpccer &= ~TIM_CCER_CC5P;
07493   /* Set the Output Compare Polarity */
07494   tmpccer |= (OC_Config->OCPolarity << 16U);
07495
07496   if (IS_TIM_BREAK_INSTANCE(TIMx))
07497   {
07498     /* Reset the Output Compare IDLE State */
07499     tmpcr2 &= ~TIM_CR2_OIS5;
07500     /* Set the Output Idle state */
07501     tmpcr2 |= (OC_Config->OCIdleState << 8U);
07502   }
07503   /* Write to TIMx CR2 */
07504   TIMx->CR2 = tmpcr2;
07505
07506   /* Write to TIMx CCMR3 */
07507   TIMx->CCMR3 = tmpccmrx;
07508
07509   /* Set the Capture Compare Register value */
07510   TIMx->CCR5 = OC_Config->Pulse;
07511
07512   /* Write to TIMx CCER */
07513   TIMx->CCER = tmpccer;
07514 }
07515
07516 /**
07517   * @brief  Timer Output Compare 6 configuration
07518   * @param  TIMx to select the TIM peripheral
07519   * @param  OC_Config The output configuration structure
07520   * @retval None
07521   */
07522 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
07523                               const TIM_OC_InitTypeDef *OC_Config)
07524 {
07525   uint32_t tmpccmrx;
07526   uint32_t tmpccer;
07527   uint32_t tmpcr2;
07528
07529   /* Get the TIMx CCER register value */
07530   tmpccer = TIMx->CCER;
07531
07532   /* Disable the output: Reset the CCxE Bit */
07533   TIMx->CCER &= ~TIM_CCER_CC6E;
07534
07535   /* Get the TIMx CR2 register value */
07536   tmpcr2 =  TIMx->CR2;
07537   /* Get the TIMx CCMR1 register value */
07538   tmpccmrx = TIMx->CCMR3;
07539
07540   /* Reset the Output Compare Mode Bits */
07541   tmpccmrx &= ~(TIM_CCMR3_OC6M);
07542   /* Select the Output Compare Mode */
07543   tmpccmrx |= (OC_Config->OCMode << 8U);
07544
07545   /* Reset the Output Polarity level */
07546   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
07547   /* Set the Output Compare Polarity */
07548   tmpccer |= (OC_Config->OCPolarity << 20U);
07549
07550   if (IS_TIM_BREAK_INSTANCE(TIMx))
07551   {
07552     /* Reset the Output Compare IDLE State */
07553     tmpcr2 &= ~TIM_CR2_OIS6;
07554     /* Set the Output Idle state */
07555     tmpcr2 |= (OC_Config->OCIdleState << 10U);
07556   }
07557
07558   /* Write to TIMx CR2 */
07559   TIMx->CR2 = tmpcr2;
07560
07561   /* Write to TIMx CCMR3 */
07562   TIMx->CCMR3 = tmpccmrx;
07563
07564   /* Set the Capture Compare Register value */
07565   TIMx->CCR6 = OC_Config->Pulse;
07566
07567   /* Write to TIMx CCER */
07568   TIMx->CCER = tmpccer;
07569 }
07570
07571 /**
07572   * @brief  Slave Timer configuration function
07573   * @param  htim TIM handle
07574   * @param  sSlaveConfig Slave timer configuration
07575   * @retval None
07576   */
07577 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
07578                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
07579 {
07580   HAL_StatusTypeDef status = HAL_OK;
07581   uint32_t tmpsmcr;
07582   uint32_t tmpccmr1;
07583   uint32_t tmpccer;
07584
07585   /* Get the TIMx SMCR register value */
07586   tmpsmcr = htim->Instance->SMCR;
07587
07588   /* Reset the Trigger Selection Bits */
07589   tmpsmcr &= ~TIM_SMCR_TS;
07590   /* Set the Input Trigger source */
07591   tmpsmcr |= sSlaveConfig->InputTrigger;
07592
07593   /* Reset the slave mode Bits */
07594   tmpsmcr &= ~TIM_SMCR_SMS;
07595   /* Set the slave mode */
07596   tmpsmcr |= sSlaveConfig->SlaveMode;
07597
07598   /* Write to TIMx SMCR */
07599   htim->Instance->SMCR = tmpsmcr;
07600
07601   /* Configure the trigger prescaler, filter, and polarity */
07602   switch (sSlaveConfig->InputTrigger)
07603   {
07604     case TIM_TS_ETRF:
07605     {
07606       /* Check the parameters */
07607       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
07608       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
07609       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07610       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07611       /* Configure the ETR Trigger source */
07612       TIM_ETR_SetConfig(htim->Instance,
07613                         sSlaveConfig->TriggerPrescaler,
07614                         sSlaveConfig->TriggerPolarity,
07615                         sSlaveConfig->TriggerFilter);
07616       break;
07617     }
07618
07619     case TIM_TS_TI1F_ED:
07620     {
07621       /* Check the parameters */
07622       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
07623       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07624
07625       if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
07626           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
07627       {
07628         return HAL_ERROR;
07629       }
07630
07631       /* Disable the Channel 1: Reset the CC1E Bit */
07632       tmpccer = htim->Instance->CCER;
07633       htim->Instance->CCER &= ~TIM_CCER_CC1E;
07634       tmpccmr1 = htim->Instance->CCMR1;
07635
07636       /* Set the filter */
07637       tmpccmr1 &= ~TIM_CCMR1_IC1F;
07638       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
07639
07640       /* Write to TIMx CCMR1 and CCER registers */
07641       htim->Instance->CCMR1 = tmpccmr1;
07642       htim->Instance->CCER = tmpccer;
07643       break;
07644     }
07645
07646     case TIM_TS_TI1FP1:
07647     {
07648       /* Check the parameters */
07649       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
07650       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07651       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07652
07653       /* Configure TI1 Filter and Polarity */
07654       TIM_TI1_ConfigInputStage(htim->Instance,
07655                                sSlaveConfig->TriggerPolarity,
07656                                sSlaveConfig->TriggerFilter);
07657       break;
07658     }
07659
07660     case TIM_TS_TI2FP2:
07661     {
07662       /* Check the parameters */
07663       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
07664       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07665       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07666
07667       /* Configure TI2 Filter and Polarity */
07668       TIM_TI2_ConfigInputStage(htim->Instance,
07669                                sSlaveConfig->TriggerPolarity,
07670                                sSlaveConfig->TriggerFilter);
07671       break;
07672     }
07673
07674     case TIM_TS_ITR0:
07675     case TIM_TS_ITR1:
07676     case TIM_TS_ITR2:
07677     case TIM_TS_ITR3:
07678 #if defined (TIM5)
07679     case TIM_TS_ITR4:
07680 #endif /* TIM5 */
07681     case TIM_TS_ITR5:
07682     case TIM_TS_ITR6:
07683     case TIM_TS_ITR7:
07684     case TIM_TS_ITR8:
07685 #if defined (TIM20)
07686     case TIM_TS_ITR9:
07687 #endif /* TIM20 */
07688 #if defined (HRTIM1)
07689     case TIM_TS_ITR10:
07690 #endif /* HRTIM1 */
07691     case TIM_TS_ITR11:
07692     {
07693       /* Check the parameter */
07694       assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
07695       break;
07696     }
07697
07698     default:
07699       status = HAL_ERROR;
07700       break;
07701   }
07702
07703   return status;
07704 }
07705
07706 /**
07707   * @brief  Configure the TI1 as Input.
07708   * @param  TIMx to select the TIM peripheral.
07709   * @param  TIM_ICPolarity The Input Polarity.
07710   *          This parameter can be one of the following values:
07711   *            @arg TIM_ICPOLARITY_RISING
07712   *            @arg TIM_ICPOLARITY_FALLING
07713   *            @arg TIM_ICPOLARITY_BOTHEDGE
07714   * @param  TIM_ICSelection specifies the input to be used.
07715   *          This parameter can be one of the following values:
07716   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
07717   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
07718   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
07719   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07720   *          This parameter must be a value between 0x00 and 0x0F.
07721   * @retval None
07722   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
07723   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
07724   *        protected against un-initialized filter and polarity values.
07725   */
07726 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07727                        uint32_t TIM_ICFilter)
07728 {
07729   uint32_t tmpccmr1;
07730   uint32_t tmpccer;
07731
07732   /* Disable the Channel 1: Reset the CC1E Bit */
07733   tmpccer = TIMx->CCER;
07734   TIMx->CCER &= ~TIM_CCER_CC1E;
07735   tmpccmr1 = TIMx->CCMR1;
07736
07737   /* Select the Input */
07738   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
07739   {
07740     tmpccmr1 &= ~TIM_CCMR1_CC1S;
07741     tmpccmr1 |= TIM_ICSelection;
07742   }
07743   else
07744   {
07745     tmpccmr1 |= TIM_CCMR1_CC1S_0;
07746   }
07747
07748   /* Set the filter */
07749   tmpccmr1 &= ~TIM_CCMR1_IC1F;
07750   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
07751
07752   /* Select the Polarity and set the CC1E Bit */
07753   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
07754   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
07755
07756   /* Write to TIMx CCMR1 and CCER registers */
07757   TIMx->CCMR1 = tmpccmr1;
07758   TIMx->CCER = tmpccer;
07759 }
07760
07761 /**
07762   * @brief  Configure the Polarity and Filter for TI1.
07763   * @param  TIMx to select the TIM peripheral.
07764   * @param  TIM_ICPolarity The Input Polarity.
07765   *          This parameter can be one of the following values:
07766   *            @arg TIM_ICPOLARITY_RISING
07767   *            @arg TIM_ICPOLARITY_FALLING
07768   *            @arg TIM_ICPOLARITY_BOTHEDGE
07769   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07770   *          This parameter must be a value between 0x00 and 0x0F.
07771   * @retval None
07772   */
07773 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
07774 {
07775   uint32_t tmpccmr1;
07776   uint32_t tmpccer;
07777
07778   /* Disable the Channel 1: Reset the CC1E Bit */
07779   tmpccer = TIMx->CCER;
07780   TIMx->CCER &= ~TIM_CCER_CC1E;
07781   tmpccmr1 = TIMx->CCMR1;
07782
07783   /* Set the filter */
07784   tmpccmr1 &= ~TIM_CCMR1_IC1F;
07785   tmpccmr1 |= (TIM_ICFilter << 4U);
07786
07787   /* Select the Polarity and set the CC1E Bit */
07788   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
07789   tmpccer |= TIM_ICPolarity;
07790
07791   /* Write to TIMx CCMR1 and CCER registers */
07792   TIMx->CCMR1 = tmpccmr1;
07793   TIMx->CCER = tmpccer;
07794 }
07795
07796 /**
07797   * @brief  Configure the TI2 as Input.
07798   * @param  TIMx to select the TIM peripheral
07799   * @param  TIM_ICPolarity The Input Polarity.
07800   *          This parameter can be one of the following values:
07801   *            @arg TIM_ICPOLARITY_RISING
07802   *            @arg TIM_ICPOLARITY_FALLING
07803   *            @arg TIM_ICPOLARITY_BOTHEDGE
07804   * @param  TIM_ICSelection specifies the input to be used.
07805   *          This parameter can be one of the following values:
07806   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
07807   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
07808   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
07809   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07810   *          This parameter must be a value between 0x00 and 0x0F.
07811   * @retval None
07812   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
07813   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
07814   *        protected against un-initialized filter and polarity values.
07815   */
07816 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07817                               uint32_t TIM_ICFilter)
07818 {
07819   uint32_t tmpccmr1;
07820   uint32_t tmpccer;
07821
07822   /* Disable the Channel 2: Reset the CC2E Bit */
07823   tmpccer = TIMx->CCER;
07824   TIMx->CCER &= ~TIM_CCER_CC2E;
07825   tmpccmr1 = TIMx->CCMR1;
07826
07827   /* Select the Input */
07828   tmpccmr1 &= ~TIM_CCMR1_CC2S;
07829   tmpccmr1 |= (TIM_ICSelection << 8U);
07830
07831   /* Set the filter */
07832   tmpccmr1 &= ~TIM_CCMR1_IC2F;
07833   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
07834
07835   /* Select the Polarity and set the CC2E Bit */
07836   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
07837   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
07838
07839   /* Write to TIMx CCMR1 and CCER registers */
07840   TIMx->CCMR1 = tmpccmr1 ;
07841   TIMx->CCER = tmpccer;
07842 }
07843
07844 /**
07845   * @brief  Configure the Polarity and Filter for TI2.
07846   * @param  TIMx to select the TIM peripheral.
07847   * @param  TIM_ICPolarity The Input Polarity.
07848   *          This parameter can be one of the following values:
07849   *            @arg TIM_ICPOLARITY_RISING
07850   *            @arg TIM_ICPOLARITY_FALLING
07851   *            @arg TIM_ICPOLARITY_BOTHEDGE
07852   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07853   *          This parameter must be a value between 0x00 and 0x0F.
07854   * @retval None
07855   */
07856 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
07857 {
07858   uint32_t tmpccmr1;
07859   uint32_t tmpccer;
07860
07861   /* Disable the Channel 2: Reset the CC2E Bit */
07862   tmpccer = TIMx->CCER;
07863   TIMx->CCER &= ~TIM_CCER_CC2E;
07864   tmpccmr1 = TIMx->CCMR1;
07865
07866   /* Set the filter */
07867   tmpccmr1 &= ~TIM_CCMR1_IC2F;
07868   tmpccmr1 |= (TIM_ICFilter << 12U);
07869
07870   /* Select the Polarity and set the CC2E Bit */
07871   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
07872   tmpccer |= (TIM_ICPolarity << 4U);
07873
07874   /* Write to TIMx CCMR1 and CCER registers */
07875   TIMx->CCMR1 = tmpccmr1 ;
07876   TIMx->CCER = tmpccer;
07877 }
07878
07879 /**
07880   * @brief  Configure the TI3 as Input.
07881   * @param  TIMx to select the TIM peripheral
07882   * @param  TIM_ICPolarity The Input Polarity.
07883   *          This parameter can be one of the following values:
07884   *            @arg TIM_ICPOLARITY_RISING
07885   *            @arg TIM_ICPOLARITY_FALLING
07886   *            @arg TIM_ICPOLARITY_BOTHEDGE
07887   * @param  TIM_ICSelection specifies the input to be used.
07888   *          This parameter can be one of the following values:
07889   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
07890   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
07891   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
07892   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07893   *          This parameter must be a value between 0x00 and 0x0F.
07894   * @retval None
07895   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
07896   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
07897   *        protected against un-initialized filter and polarity values.
07898   */
07899 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07900                               uint32_t TIM_ICFilter)
07901 {
07902   uint32_t tmpccmr2;
07903   uint32_t tmpccer;
07904
07905   /* Disable the Channel 3: Reset the CC3E Bit */
07906   tmpccer = TIMx->CCER;
07907   TIMx->CCER &= ~TIM_CCER_CC3E;
07908   tmpccmr2 = TIMx->CCMR2;
07909
07910   /* Select the Input */
07911   tmpccmr2 &= ~TIM_CCMR2_CC3S;
07912   tmpccmr2 |= TIM_ICSelection;
07913
07914   /* Set the filter */
07915   tmpccmr2 &= ~TIM_CCMR2_IC3F;
07916   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
07917
07918   /* Select the Polarity and set the CC3E Bit */
07919   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
07920   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
07921
07922   /* Write to TIMx CCMR2 and CCER registers */
07923   TIMx->CCMR2 = tmpccmr2;
07924   TIMx->CCER = tmpccer;
07925 }
07926
07927 /**
07928   * @brief  Configure the TI4 as Input.
07929   * @param  TIMx to select the TIM peripheral
07930   * @param  TIM_ICPolarity The Input Polarity.
07931   *          This parameter can be one of the following values:
07932   *            @arg TIM_ICPOLARITY_RISING
07933   *            @arg TIM_ICPOLARITY_FALLING
07934   *            @arg TIM_ICPOLARITY_BOTHEDGE
07935   * @param  TIM_ICSelection specifies the input to be used.
07936   *          This parameter can be one of the following values:
07937   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
07938   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
07939   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
07940   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07941   *          This parameter must be a value between 0x00 and 0x0F.
07942   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
07943   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
07944   *        protected against un-initialized filter and polarity values.
07945   * @retval None
07946   */
07947 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07948                               uint32_t TIM_ICFilter)
07949 {
07950   uint32_t tmpccmr2;
07951   uint32_t tmpccer;
07952
07953   /* Disable the Channel 4: Reset the CC4E Bit */
07954   tmpccer = TIMx->CCER;
07955   TIMx->CCER &= ~TIM_CCER_CC4E;
07956   tmpccmr2 = TIMx->CCMR2;
07957
07958   /* Select the Input */
07959   tmpccmr2 &= ~TIM_CCMR2_CC4S;
07960   tmpccmr2 |= (TIM_ICSelection << 8U);
07961
07962   /* Set the filter */
07963   tmpccmr2 &= ~TIM_CCMR2_IC4F;
07964   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
07965
07966   /* Select the Polarity and set the CC4E Bit */
07967   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
07968   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
07969
07970   /* Write to TIMx CCMR2 and CCER registers */
07971   TIMx->CCMR2 = tmpccmr2;
07972   TIMx->CCER = tmpccer ;
07973 }
07974
07975 /**
07976   * @brief  Selects the Input Trigger source
07977   * @param  TIMx to select the TIM peripheral
07978   * @param  InputTriggerSource The Input Trigger source.
07979   *          This parameter can be one of the following values:
07980   *            @arg TIM_TS_ITR0: Internal Trigger 0
07981   *            @arg TIM_TS_ITR1: Internal Trigger 1
07982   *            @arg TIM_TS_ITR2: Internal Trigger 2
07983   *            @arg TIM_TS_ITR3: Internal Trigger 3
07984   *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
07985   *            @arg TIM_TS_ITR5: Internal Trigger 5
07986   *            @arg TIM_TS_ITR6: Internal Trigger 6
07987   *            @arg TIM_TS_ITR7: Internal Trigger 7
07988   *            @arg TIM_TS_ITR8: Internal Trigger 8
07989   *            @arg TIM_TS_ITR9: Internal Trigger 9   (*)
07990   *            @arg TIM_TS_ITR10: Internal Trigger 10
07991   *            @arg TIM_TS_ITR11: Internal Trigger 11
07992   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
07993   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
07994   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
07995   *            @arg TIM_TS_ETRF: External Trigger input
07996   *
07997   *       (*)  Value not defined in all devices.
07998   *
07999   * @retval None
08000   */
08001 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
08002 {
08003   uint32_t tmpsmcr;
08004
08005   /* Get the TIMx SMCR register value */
08006   tmpsmcr = TIMx->SMCR;
08007   /* Reset the TS Bits */
08008   tmpsmcr &= ~TIM_SMCR_TS;
08009   /* Set the Input Trigger source and the slave mode*/
08010   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
08011   /* Write to TIMx SMCR */
08012   TIMx->SMCR = tmpsmcr;
08013 }
08014 /**
08015   * @brief  Configures the TIMx External Trigger (ETR).
08016   * @param  TIMx to select the TIM peripheral
08017   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
08018   *          This parameter can be one of the following values:
08019   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
08020   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
08021   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
08022   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
08023   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
08024   *          This parameter can be one of the following values:
08025   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
08026   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
08027   * @param  ExtTRGFilter External Trigger Filter.
08028   *          This parameter must be a value between 0x00 and 0x0F
08029   * @retval None
08030   */
08031 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
08032                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
08033 {
08034   uint32_t tmpsmcr;
08035
08036   tmpsmcr = TIMx->SMCR;
08037
08038   /* Reset the ETR Bits */
08039   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
08040
08041   /* Set the Prescaler, the Filter value and the Polarity */
08042   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
08043
08044   /* Write to TIMx SMCR */
08045   TIMx->SMCR = tmpsmcr;
08046 }
08047
08048 /**
08049   * @brief  Enables or disables the TIM Capture Compare Channel x.
08050   * @param  TIMx to select the TIM peripheral
08051   * @param  Channel specifies the TIM Channel
08052   *          This parameter can be one of the following values:
08053   *            @arg TIM_CHANNEL_1: TIM Channel 1
08054   *            @arg TIM_CHANNEL_2: TIM Channel 2
08055   *            @arg TIM_CHANNEL_3: TIM Channel 3
08056   *            @arg TIM_CHANNEL_4: TIM Channel 4
08057   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
08058   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
08059   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
08060   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
08061   * @retval None
08062   */
08063 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
08064 {
08065   uint32_t tmp;
08066
08067   /* Check the parameters */
08068   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
08069   assert_param(IS_TIM_CHANNELS(Channel));
08070
08071   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
08072
08073   /* Reset the CCxE Bit */
08074   TIMx->CCER &= ~tmp;
08075
08076   /* Set or reset the CCxE Bit */
08077   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
08078 }
08079
08080 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
08081 /**
08082   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
08083   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
08084   *                the configuration information for TIM module.
08085   * @retval None
08086   */
08087 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
08088 {
08089   /* Reset the TIM callback to the legacy weak callbacks */
08090   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
08091   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
08092   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
08093   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
08094   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
08095   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
08096   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
08097   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
08098   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
08099   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
08100   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
08101   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
08102   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
08103   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
08104   htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
08105   htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
08106   htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
08107   htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
08108 }
08109 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
08110
08111 /**
08112   * @}
08113   */
08114
08115 #endif /* HAL_TIM_MODULE_ENABLED */
08116 /**
08117   * @}
08118   */
08119
08120 /**
08121   * @}
08122   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_tim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_TIM_H
00021 #define STM32G4xx_HAL_TIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup TIM
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup TIM_Exported_Types TIM Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  TIM Time base Configuration Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00049                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00050                                    Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
00051
00052   uint32_t CounterMode;       /*!< Specifies the counter mode.
00053                                    This parameter can be a value of @ref TIM_Counter_Mode */
00054
00055   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00056                                    Auto-Reload Register at the next update event.
00057                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00058                                    (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(),
00059                                     __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
00060                                     __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */
00061
00062   uint32_t ClockDivision;     /*!< Specifies the clock division.
00063                                    This parameter can be a value of @ref TIM_ClockDivision */
00064
00065   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00066                                     reaches zero, an update event is generated and counting restarts
00067                                     from the RCR value (N).
00068                                     This means in PWM mode that (N+1) corresponds to:
00069                                         - the number of PWM periods in edge-aligned mode
00070                                         - the number of half PWM period in center-aligned mode
00071                                      GP timers: this parameter must be a number between Min_Data = 0x00 and
00072                                      Max_Data = 0xFF.
00073                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
00074                                      Max_Data = 0xFFFF. */
00075
00076   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00077                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00078 } TIM_Base_InitTypeDef;
00079
00080 /**
00081   * @brief  TIM Output Compare Configuration Structure definition
00082   */
00083 typedef struct
00084 {
00085   uint32_t OCMode;        /*!< Specifies the TIM mode.
00086                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00087
00088   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00089                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00090                                (or 0xFFEF if dithering is activated)
00091                                Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
00092                                Pulse value */
00093
00094   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00095                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00096
00097   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00098                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00099                                @note This parameter is valid only for timer instances supporting break feature. */
00100
00101   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
00102                                This parameter can be a value of @ref TIM_Output_Fast_State
00103                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00104
00105
00106   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00107                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00108                                @note This parameter is valid only for timer instances supporting break feature. */
00109
00110   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00111                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00112                                @note This parameter is valid only for timer instances supporting break feature. */
00113 } TIM_OC_InitTypeDef;
00114
00115 /**
00116   * @brief  TIM One Pulse Mode Configuration Structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t OCMode;        /*!< Specifies the TIM mode.
00121                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00122
00123   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00124                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00125                                (or 0xFFEF if dithering is activated)
00126                                Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
00127                                Pulse value */
00128
00129   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00130                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00131
00132   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00133                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00134                                @note This parameter is valid only for timer instances supporting break feature. */
00135
00136   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00137                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00138                                @note This parameter is valid only for timer instances supporting break feature. */
00139
00140   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00141                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00142                                @note This parameter is valid only for timer instances supporting break feature. */
00143
00144   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00145                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00146
00147   uint32_t ICSelection;   /*!< Specifies the input.
00148                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00149
00150   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00151                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00152 } TIM_OnePulse_InitTypeDef;
00153
00154 /**
00155   * @brief  TIM Input Capture Configuration Structure definition
00156   */
00157 typedef struct
00158 {
00159   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
00160                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00161
00162   uint32_t ICSelection;  /*!< Specifies the input.
00163                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00164
00165   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00166                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00167
00168   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00169                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00170 } TIM_IC_InitTypeDef;
00171
00172 /**
00173   * @brief  TIM Encoder Configuration Structure definition
00174   */
00175 typedef struct
00176 {
00177   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00178                                This parameter can be a value of @ref TIM_Encoder_Mode */
00179
00180   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00181                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00182
00183   uint32_t IC1Selection;  /*!< Specifies the input.
00184                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00185
00186   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00187                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00188
00189   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00190                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00191
00192   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00193                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00194
00195   uint32_t IC2Selection;  /*!< Specifies the input.
00196                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00197
00198   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00199                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00200
00201   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00202                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00203 } TIM_Encoder_InitTypeDef;
00204
00205 /**
00206   * @brief  Clock Configuration Handle Structure definition
00207   */
00208 typedef struct
00209 {
00210   uint32_t ClockSource;     /*!< TIM clock sources
00211                                  This parameter can be a value of @ref TIM_Clock_Source */
00212   uint32_t ClockPolarity;   /*!< TIM clock polarity
00213                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00214   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00215                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00216   uint32_t ClockFilter;     /*!< TIM clock filter
00217                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00218 } TIM_ClockConfigTypeDef;
00219
00220 /**
00221   * @brief  TIM Clear Input Configuration Handle Structure definition
00222   */
00223 typedef struct
00224 {
00225   uint32_t ClearInputState;      /*!< TIM clear Input state
00226                                       This parameter can be ENABLE or DISABLE */
00227   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00228                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00229   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00230                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00231   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00232                                       This parameter must be 0: When OCRef clear feature is used with ETR source,
00233                                       ETR prescaler must be off */
00234   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
00235                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00236 } TIM_ClearInputConfigTypeDef;
00237
00238 /**
00239   * @brief  TIM Master configuration Structure definition
00240   * @note   Advanced timers provide TRGO2 internal line which is redirected
00241   *         to the ADC
00242   */
00243 typedef struct
00244 {
00245   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00246                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
00247   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00248                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00249   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00250                                         This parameter can be a value of @ref TIM_Master_Slave_Mode
00251                                         @note When the Master/slave mode is enabled, the effect of
00252                                         an event on the trigger input (TRGI) is delayed to allow a
00253                                         perfect synchronization between the current timer and its
00254                                         slaves (through TRGO). It is not mandatory in case of timer
00255                                         synchronization mode. */
00256 } TIM_MasterConfigTypeDef;
00257
00258 /**
00259   * @brief  TIM Slave configuration Structure definition
00260   */
00261 typedef struct
00262 {
00263   uint32_t  SlaveMode;         /*!< Slave mode selection
00264                                     This parameter can be a value of @ref TIM_Slave_Mode */
00265   uint32_t  InputTrigger;      /*!< Input Trigger source
00266                                     This parameter can be a value of @ref TIM_Trigger_Selection */
00267   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00268                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
00269   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00270                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
00271   uint32_t  TriggerFilter;     /*!< Input trigger filter
00272                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00273
00274 } TIM_SlaveConfigTypeDef;
00275
00276 /**
00277   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00278   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00279   *        filter and polarity.
00280   */
00281 typedef struct
00282 {
00283   uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00284
00285   uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00286
00287   uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
00288
00289   uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00290
00291   uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00292
00293   uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
00294
00295   uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00296
00297   uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
00298
00299   uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00300
00301   uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
00302
00303   uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00304
00305   uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
00306
00307   uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00308
00309 } TIM_BreakDeadTimeConfigTypeDef;
00310
00311 /**
00312   * @brief  HAL State structures definition
00313   */
00314 typedef enum
00315 {
00316   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00317   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00318   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00319   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00320   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00321 } HAL_TIM_StateTypeDef;
00322
00323 /**
00324   * @brief  TIM Channel States definition
00325   */
00326 typedef enum
00327 {
00328   HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
00329   HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
00330   HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
00331 } HAL_TIM_ChannelStateTypeDef;
00332
00333 /**
00334   * @brief  DMA Burst States definition
00335   */
00336 typedef enum
00337 {
00338   HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
00339   HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
00340   HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
00341 } HAL_TIM_DMABurstStateTypeDef;
00342
00343 /**
00344   * @brief  HAL Active channel structures definition
00345   */
00346 typedef enum
00347 {
00348   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00349   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00350   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00351   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00352   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
00353   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
00354   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00355 } HAL_TIM_ActiveChannel;
00356
00357 /**
00358   * @brief  TIM Time Base Handle Structure definition
00359   */
00360 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00361 typedef struct __TIM_HandleTypeDef
00362 #else
00363 typedef struct
00364 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00365 {
00366   TIM_TypeDef                        *Instance;         /*!< Register base address                             */
00367   TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
00368   HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
00369   DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
00370                                                              This array is accessed by a @ref DMA_Handle_index */
00371   HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
00372   __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
00373   __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
00374   __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
00375   __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
00376
00377 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00378   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
00379   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
00380   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
00381   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
00382   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
00383   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
00384   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
00385   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
00386   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
00387   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
00388   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
00389   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
00390   void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
00391   void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
00392   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
00393   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
00394   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
00395   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
00396   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
00397   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
00398   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
00399   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
00400   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
00401   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
00402   void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
00403   void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
00404   void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
00405   void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
00406   void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Encoder Index Callback                              */
00407   void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Direction Change Callback                           */
00408   void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Index Error Callback                                */
00409   void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Transition Error Callback                           */
00410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00411 } TIM_HandleTypeDef;
00412
00413 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00414 /**
00415   * @brief  HAL TIM Callback ID enumeration definition
00416   */
00417 typedef enum
00418 {
00419   HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
00420   , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
00421   , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
00422   , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
00423   , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
00424   , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
00425   , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
00426   , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
00427   , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
00428   , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
00429   , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
00430   , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
00431   , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
00432   , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
00433   , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
00434   , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
00435   , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
00436   , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
00437   , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
00438   , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
00439   , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
00440   , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
00441   , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
00442   , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
00443   , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
00444   , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
00445   , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
00446   , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
00447   , HAL_TIM_ENCODER_INDEX_CB_ID           = 0x1CU   /*!< TIM Encoder Index Callback ID                              */
00448   , HAL_TIM_DIRECTION_CHANGE_CB_ID        = 0x1DU   /*!< TIM Direction Change Callback ID                           */
00449   , HAL_TIM_INDEX_ERROR_CB_ID             = 0x1EU   /*!< TIM Index Error Callback ID                                */
00450   , HAL_TIM_TRANSITION_ERROR_CB_ID        = 0x1FU   /*!< TIM Transition Error Callback ID                           */
00451 } HAL_TIM_CallbackIDTypeDef;
00452
00453 /**
00454   * @brief  HAL TIM Callback pointer definition
00455   */
00456 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
00457
00458 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00459
00460 /**
00461   * @}
00462   */
00463 /* End of exported types -----------------------------------------------------*/
00464
00465 /* Exported constants --------------------------------------------------------*/
00466 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00467   * @{
00468   */
00469
00470 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00471   * @{
00472   */
00473 #define TIM_CLEARINPUTSOURCE_NONE     0xFFFFFFFFU                               /*!< OCREF_CLR is disabled */
00474 #define TIM_CLEARINPUTSOURCE_ETR      0x00000001U                               /*!< OCREF_CLR is connected to ETRF input */
00475 #define TIM_CLEARINPUTSOURCE_COMP1    0x00000000U                               /*!< OCREF_CLR_INT is connected to COMP1 output */
00476 #define TIM_CLEARINPUTSOURCE_COMP2    TIM1_AF2_OCRSEL_0                         /*!< OCREF_CLR_INT is connected to COMP2 output */
00477 #define TIM_CLEARINPUTSOURCE_COMP3    TIM1_AF2_OCRSEL_1                         /*!< OCREF_CLR_INT is connected to COMP3 output */
00478 #define TIM_CLEARINPUTSOURCE_COMP4    (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)   /*!< OCREF_CLR_INT is connected to COMP4 output */
00479 #if defined (COMP5)
00480 #define TIM_CLEARINPUTSOURCE_COMP5    TIM1_AF2_OCRSEL_2                         /*!< OCREF_CLR_INT is connected to COMP5 output */
00481 #endif /* COMP5 */
00482 #if defined (COMP6)
00483 #define TIM_CLEARINPUTSOURCE_COMP6    (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0)   /*!< OCREF_CLR_INT is connected to COMP6 output */
00484 #endif /* COMP6 */
00485 #if defined (COMP7)
00486 #define TIM_CLEARINPUTSOURCE_COMP7    (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1)   /*!< OCREF_CLR_INT is connected to COMP7 output */
00487 #endif /* COMP7 */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00493   * @{
00494   */
00495 #define TIM_DMABASE_CR1                    0x00000000U
00496 #define TIM_DMABASE_CR2                    0x00000001U
00497 #define TIM_DMABASE_SMCR                   0x00000002U
00498 #define TIM_DMABASE_DIER                   0x00000003U
00499 #define TIM_DMABASE_SR                     0x00000004U
00500 #define TIM_DMABASE_EGR                    0x00000005U
00501 #define TIM_DMABASE_CCMR1                  0x00000006U
00502 #define TIM_DMABASE_CCMR2                  0x00000007U
00503 #define TIM_DMABASE_CCER                   0x00000008U
00504 #define TIM_DMABASE_CNT                    0x00000009U
00505 #define TIM_DMABASE_PSC                    0x0000000AU
00506 #define TIM_DMABASE_ARR                    0x0000000BU
00507 #define TIM_DMABASE_RCR                    0x0000000CU
00508 #define TIM_DMABASE_CCR1                   0x0000000DU
00509 #define TIM_DMABASE_CCR2                   0x0000000EU
00510 #define TIM_DMABASE_CCR3                   0x0000000FU
00511 #define TIM_DMABASE_CCR4                   0x00000010U
00512 #define TIM_DMABASE_BDTR                   0x00000011U
00513 #define TIM_DMABASE_CCR5                   0x00000012U
00514 #define TIM_DMABASE_CCR6                   0x00000013U
00515 #define TIM_DMABASE_CCMR3                  0x00000014U
00516 #define TIM_DMABASE_DTR2                   0x00000015U
00517 #define TIM_DMABASE_ECR                    0x00000016U
00518 #define TIM_DMABASE_TISEL                  0x00000017U
00519 #define TIM_DMABASE_AF1                    0x00000018U
00520 #define TIM_DMABASE_AF2                    0x00000019U
00521 #define TIM_DMABASE_OR                     0x0000001AU
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_Event_Source TIM Event Source
00527   * @{
00528   */
00529 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00530 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00531 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00532 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00533 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00534 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00535 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00536 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00537 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00543   * @{
00544   */
00545 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
00546 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
00547 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00553   * @{
00554   */
00555 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
00556 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00562   * @{
00563   */
00564 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
00565 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
00566 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
00567 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00573   * @{
00574   */
00575 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
00576 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
00577 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
00578 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
00579 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
00580 /**
00581   * @}
00582   */
00583
00584 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
00585   * @{
00586   */
00587 #define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
00588 #define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
00589 /**
00590   * @}
00591   */
00592
00593 /** @defgroup TIM_ClockDivision TIM Clock Division
00594   * @{
00595   */
00596 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
00597 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
00598 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00604   * @{
00605   */
00606 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
00607 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00613   * @{
00614   */
00615 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
00616 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
00617
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00623   * @{
00624   */
00625 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
00626 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
00627 /**
00628   * @}
00629   */
00630
00631 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00632   * @{
00633   */
00634 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
00635 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00641   * @{
00642   */
00643 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
00644 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
00645 /**
00646   * @}
00647   */
00648
00649 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00650   * @{
00651   */
00652 #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
00653 #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00659   * @{
00660   */
00661 #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
00662 #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00668   * @{
00669   */
00670 #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
00671 #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
00672 /**
00673   * @}
00674   */
00675
00676 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00677   * @{
00678   */
00679 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
00680 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
00681 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
00682 /**
00683   * @}
00684   */
00685
00686 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
00687   * @{
00688   */
00689 #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
00690 #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00696   * @{
00697   */
00698 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
00699 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
00700 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00706   * @{
00707   */
00708 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
00709 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
00710 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
00711 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
00712 /**
00713   * @}
00714   */
00715
00716 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00717   * @{
00718   */
00719 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
00720 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00726   * @{
00727   */
00728 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
00729 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
00730 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
00731 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction, x2 mode */
00732 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
00733 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2      (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
00734 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
00735 #define TIM_ENCODERMODE_X1_TI1                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
00736 #define TIM_ENCODERMODE_X1_TI2                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00742   * @{
00743   */
00744 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
00745 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
00746 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
00747 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
00748 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
00749 #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
00750 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
00751 #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
00752 #define TIM_IT_IDX                         TIM_DIER_IDXIE                       /*!< Index interrupt             */
00753 #define TIM_IT_DIR                         TIM_DIER_DIRIE                       /*!< Direction change interrupt  */
00754 #define TIM_IT_IERR                        TIM_DIER_IERRIE                      /*!< Index error interrupt       */
00755 #define TIM_IT_TERR                        TIM_DIER_TERRIE                      /*!< Transition error interrupt  */
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00761   * @{
00762   */
00763 #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
00764 #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup TIM_DMA_sources TIM DMA Sources
00770   * @{
00771   */
00772 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
00773 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
00774 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
00775 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
00776 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
00777 #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
00778 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection
00784   * @{
00785   */
00786 #define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
00787 #define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
00788 /**
00789   * @}
00790   */
00791
00792 /** @defgroup TIM_Flag_definition TIM Flag Definition
00793   * @{
00794   */
00795 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
00796 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
00797 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
00798 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
00799 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
00800 #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
00801 #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
00802 #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
00803 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
00804 #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
00805 #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
00806 #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
00807 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
00808 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
00809 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
00810 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
00811 #define TIM_FLAG_IDX                       TIM_SR_IDXF                          /*!< Encoder index flag            */
00812 #define TIM_FLAG_DIR                       TIM_SR_DIRF                          /*!< Direction change flag         */
00813 #define TIM_FLAG_IERR                      TIM_SR_IERRF                         /*!< Index error flag              */
00814 #define TIM_FLAG_TERR                      TIM_SR_TERRF                         /*!< Transition error flag         */
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup TIM_Channel TIM Channel
00820   * @{
00821   */
00822 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
00823 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
00824 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
00825 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
00826 #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
00827 #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
00828 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup TIM_Clock_Source TIM Clock Source
00834   * @{
00835   */
00836 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
00837 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
00838 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
00839 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
00840 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
00841 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
00842 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
00843 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
00844 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
00845 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
00846 #if defined (TIM5)
00847 #define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
00848 #endif /* TIM5 */
00849 #define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
00850 #define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
00851 #define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
00852 #define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
00853 #if defined (TIM20)
00854 #define TIM_CLOCKSOURCE_ITR9        TIM_TS_ITR9          /*!< External clock source mode 1 (ITR9)                   */
00855 #endif /* TIM20 */
00856 #define TIM_CLOCKSOURCE_ITR10       TIM_TS_ITR10         /*!< External clock source mode 1 (ITR10)                  */
00857 #define TIM_CLOCKSOURCE_ITR11       TIM_TS_ITR11         /*!< External clock source mode 1 (ITR11)                  */
00858 /**
00859   * @}
00860   */
00861
00862 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00863   * @{
00864   */
00865 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
00866 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
00867 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
00868 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00869 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00875   * @{
00876   */
00877 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
00878 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00879 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00880 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00881 /**
00882   * @}
00883   */
00884
00885 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00886   * @{
00887   */
00888 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
00889 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00895   * @{
00896   */
00897 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
00898 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00899 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00900 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00901 /**
00902   * @}
00903   */
00904
00905 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00906   * @{
00907   */
00908 #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00909 #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00910 /**
00911   * @}
00912   */
00913
00914 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00915   * @{
00916   */
00917 #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00918 #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00919 /**
00920   * @}
00921   */
00922 /** @defgroup TIM_Lock_level  TIM Lock level
00923   * @{
00924   */
00925 #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
00926 #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
00927 #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
00928 #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00934   * @{
00935   */
00936 #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
00937 #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00943   * @{
00944   */
00945 #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
00946 #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
00947 /**
00948   * @}
00949   */
00950
00951 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
00952   * @{
00953   */
00954 #define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
00955 #define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00961   * @{
00962   */
00963 #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
00964 #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
00965 /**
00966   * @}
00967   */
00968
00969 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00970   * @{
00971   */
00972 #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
00973 #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
00974 /**
00975   * @}
00976   */
00977
00978 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
00979   * @{
00980   */
00981 #define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
00982 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
00983 /**
00984   * @}
00985   */
00986
00987 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00988   * @{
00989   */
00990 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
00991 #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
00997   * @{
00998   */
00999 #define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
01000 #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
01001 #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
01002 #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
01003 /**
01004   * @}
01005   */
01006
01007 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
01008   * @{
01009   */
01010 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
01011 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
01012 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
01013 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
01014 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
01015 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
01016 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
01017 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
01018 #define TIM_TRGO_ENCODER_CLK      TIM_CR2_MMS_3                                    /*!< Encoder clock is used as trigger output(TRGO)                 */
01019 /**
01020   * @}
01021   */
01022
01023 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
01024   * @{
01025   */
01026 #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
01027 #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
01028 #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
01029 #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
01030 #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
01031 #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
01032 #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
01033 #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
01034 #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
01035 #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
01036 #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
01037 #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
01038 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
01039 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
01040 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
01041 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
01047   * @{
01048   */
01049 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
01050 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
01051 /**
01052   * @}
01053   */
01054
01055 /** @defgroup TIM_Slave_Mode TIM Slave mode
01056   * @{
01057   */
01058 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
01059 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
01060 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
01061 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
01062 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
01063 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
01064 #define TIM_SLAVEMODE_COMBINED_GATEDRESET    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)                  /*!< Combined gated + reset mode   */
01065 /**
01066   * @}
01067   */
01068
01069 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
01070   * @{
01071   */
01072 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
01073 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
01074 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
01075 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
01076 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
01077 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
01078 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
01079 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
01080 #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
01081 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
01082 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
01083 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
01084 #define TIM_OCMODE_ASYMMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
01085 #define TIM_OCMODE_ASYMMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
01086 #define TIM_OCMODE_PULSE_ON_COMPARE        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                     /*!< Pulse on compare (CH3&CH4 only)        */
01087 #define TIM_OCMODE_DIRECTION_OUTPUT        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)  /*!< Direction output (CH3&CH4 only)        */
01088 /**
01089   * @}
01090   */
01091
01092 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
01093   * @{
01094   */
01095 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
01096 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
01097 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
01098 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
01099 #if defined (TIM5)
01100 #define TIM_TS_ITR4          TIM_SMCR_TS_3                                                     /*!< Internal Trigger 4 (ITR9)              */
01101 #endif /* TIM5 */
01102 #define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
01103 #define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
01104 #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
01105 #define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
01106 #if defined (TIM20)
01107 #define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
01108 #endif /* TIM20 */
01109 #define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
01110 #define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
01111 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
01112 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
01113 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
01114 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
01115 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
01116 /**
01117   * @}
01118   */
01119
01120 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
01121   * @{
01122   */
01123 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
01124 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
01125 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01126 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01127 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01128 /**
01129   * @}
01130   */
01131
01132 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
01133   * @{
01134   */
01135 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
01136 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
01137 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
01138 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
01139 /**
01140   * @}
01141   */
01142
01143 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
01144   * @{
01145   */
01146 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
01147 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
01148 /**
01149   * @}
01150   */
01151
01152 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
01153   * @{
01154   */
01155 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
01156 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01157 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01158 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01159 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01160 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01161 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01162 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01163 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01164 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01165 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01166 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01167 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01168 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01169 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01170 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01171 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01172 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01173 #define TIM_DMABURSTLENGTH_19TRANSFERS     0x00001200U                          /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01174 #define TIM_DMABURSTLENGTH_20TRANSFERS     0x00001300U                          /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01175 #define TIM_DMABURSTLENGTH_21TRANSFERS     0x00001400U                          /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01176 #define TIM_DMABURSTLENGTH_22TRANSFERS     0x00001500U                          /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01177 #define TIM_DMABURSTLENGTH_23TRANSFERS     0x00001600U                          /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01178 #define TIM_DMABURSTLENGTH_24TRANSFERS     0x00001700U                          /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01179 #define TIM_DMABURSTLENGTH_25TRANSFERS     0x00001800U                          /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01180 #define TIM_DMABURSTLENGTH_26TRANSFERS     0x00001900U                          /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01181 /**
01182   * @}
01183   */
01184
01185 /** @defgroup DMA_Handle_index TIM DMA Handle Index
01186   * @{
01187   */
01188 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
01189 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
01190 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
01191 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
01192 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
01193 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
01194 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
01195 /**
01196   * @}
01197   */
01198
01199 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
01200   * @{
01201   */
01202 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
01203 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
01204 #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
01205 #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
01206 /**
01207   * @}
01208   */
01209
01210 /** @defgroup TIM_Break_System TIM Break System
01211   * @{
01212   */
01213 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */
01214 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */
01215 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
01216 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
01217 /**
01218   * @}
01219   */
01220
01221 /**
01222   * @}
01223   */
01224 /* End of exported constants -------------------------------------------------*/
01225
01226 /* Exported macros -----------------------------------------------------------*/
01227 /** @defgroup TIM_Exported_Macros TIM Exported Macros
01228   * @{
01229   */
01230
01231 /** @brief  Reset TIM handle state.
01232   * @param  __HANDLE__ TIM handle.
01233   * @retval None
01234   */
01235 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01236 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
01237                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
01238                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
01239                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
01240                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
01241                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
01242                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
01243                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
01244                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
01245                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
01246                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
01247                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
01248                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
01249                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;            \
01250                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
01251                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;            \
01252                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
01253                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;            \
01254                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
01255                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
01256                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
01257                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
01258                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
01259                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
01260                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
01261                                                       (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
01262                                                       (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
01263                                                      } while(0)
01264 #else
01265 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
01266                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
01267                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
01268                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
01269                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
01270                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
01271                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
01272                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
01273                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
01274                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
01275                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
01276                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
01277                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
01278                                                      } while(0)
01279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01280
01281 /**
01282   * @brief  Enable the TIM peripheral.
01283   * @param  __HANDLE__ TIM handle
01284   * @retval None
01285   */
01286 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01287
01288 /**
01289   * @brief  Enable the TIM main Output.
01290   * @param  __HANDLE__ TIM handle
01291   * @retval None
01292   */
01293 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01294
01295 /**
01296   * @brief  Disable the TIM peripheral.
01297   * @param  __HANDLE__ TIM handle
01298   * @retval None
01299   */
01300 #define __HAL_TIM_DISABLE(__HANDLE__) \
01301   do { \
01302     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01303     { \
01304       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01305       { \
01306         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01307       } \
01308     } \
01309   } while(0)
01310
01311 /**
01312   * @brief  Disable the TIM main Output.
01313   * @param  __HANDLE__ TIM handle
01314   * @retval None
01315   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
01316   *       disabled
01317   */
01318 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01319   do { \
01320     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01321     { \
01322       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01323       { \
01324         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01325       } \
01326     } \
01327   } while(0)
01328
01329 /**
01330   * @brief  Disable the TIM main Output.
01331   * @param  __HANDLE__ TIM handle
01332   * @retval None
01333   * @note The Main Output Enable of a timer instance is disabled unconditionally
01334   */
01335 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
01336
01337 /** @brief  Enable the specified TIM interrupt.
01338   * @param  __HANDLE__ specifies the TIM Handle.
01339   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
01340   *          This parameter can be one of the following values:
01341   *            @arg TIM_IT_UPDATE: Update interrupt
01342   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01343   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01344   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01345   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01346   *            @arg TIM_IT_COM:   Commutation interrupt
01347   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01348   *            @arg TIM_IT_BREAK: Break interrupt
01349   *            @arg TIM_IT_IDX: Index interrupt
01350   *            @arg TIM_IT_DIR: Direction change interrupt
01351   *            @arg TIM_IT_IERR: Index error interrupt
01352   *            @arg TIM_IT_TERR: Transition error interrupt
01353   * @retval None
01354   */
01355 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01356
01357 /** @brief  Disable the specified TIM interrupt.
01358   * @param  __HANDLE__ specifies the TIM Handle.
01359   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
01360   *          This parameter can be one of the following values:
01361   *            @arg TIM_IT_UPDATE: Update interrupt
01362   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01363   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01364   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01365   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01366   *            @arg TIM_IT_COM:   Commutation interrupt
01367   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01368   *            @arg TIM_IT_BREAK: Break interrupt
01369   *            @arg TIM_IT_IDX: Index interrupt
01370   *            @arg TIM_IT_DIR: Direction change interrupt
01371   *            @arg TIM_IT_IERR: Index error interrupt
01372   *            @arg TIM_IT_TERR: Transition error interrupt
01373   * @retval None
01374   */
01375 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01376
01377 /** @brief  Enable the specified DMA request.
01378   * @param  __HANDLE__ specifies the TIM Handle.
01379   * @param  __DMA__ specifies the TIM DMA request to enable.
01380   *          This parameter can be one of the following values:
01381   *            @arg TIM_DMA_UPDATE: Update DMA request
01382   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01383   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01384   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01385   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01386   *            @arg TIM_DMA_COM:   Commutation DMA request
01387   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01388   * @retval None
01389   */
01390 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01391
01392 /** @brief  Disable the specified DMA request.
01393   * @param  __HANDLE__ specifies the TIM Handle.
01394   * @param  __DMA__ specifies the TIM DMA request to disable.
01395   *          This parameter can be one of the following values:
01396   *            @arg TIM_DMA_UPDATE: Update DMA request
01397   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01398   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01399   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01400   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01401   *            @arg TIM_DMA_COM:   Commutation DMA request
01402   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01403   * @retval None
01404   */
01405 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01406
01407 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01408   * @param  __HANDLE__ specifies the TIM Handle.
01409   * @param  __FLAG__ specifies the TIM interrupt flag to check.
01410   *        This parameter can be one of the following values:
01411   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01412   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01413   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01414   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01415   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01416   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01417   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01418   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01419   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01420   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01421   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01422   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01423   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01424   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01425   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01426   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01427   *            @arg TIM_FLAG_IDX: Index interrupt flag
01428   *            @arg TIM_FLAG_DIR: Direction change interrupt flag
01429   *            @arg TIM_FLAG_IERR: Index error interrupt flag
01430   *            @arg TIM_FLAG_TERR: Transition error interrupt flag
01431   * @retval The new state of __FLAG__ (TRUE or FALSE).
01432   */
01433 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01434
01435 /** @brief  Clear the specified TIM interrupt flag.
01436   * @param  __HANDLE__ specifies the TIM Handle.
01437   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
01438   *        This parameter can be one of the following values:
01439   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01440   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01441   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01442   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01443   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01444   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01445   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01446   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01447   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01448   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01449   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01450   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01451   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01452   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01453   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01454   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01455   *            @arg TIM_FLAG_IDX: Index interrupt flag
01456   *            @arg TIM_FLAG_DIR: Direction change interrupt flag
01457   *            @arg TIM_FLAG_IERR: Index error interrupt flag
01458   *            @arg TIM_FLAG_TERR: Transition error interrupt flag
01459   * @retval The new state of __FLAG__ (TRUE or FALSE).
01460   */
01461 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01462
01463 /**
01464   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01465   * @param  __HANDLE__ TIM handle
01466   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
01467   *          This parameter can be one of the following values:
01468   *            @arg TIM_IT_UPDATE: Update interrupt
01469   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01470   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01471   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01472   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01473   *            @arg TIM_IT_COM:   Commutation interrupt
01474   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01475   *            @arg TIM_IT_BREAK: Break interrupt
01476   *            @arg TIM_IT_IDX: Index interrupt
01477   *            @arg TIM_IT_DIR: Direction change interrupt
01478   *            @arg TIM_IT_IERR: Index error interrupt
01479   *            @arg TIM_IT_TERR: Transition error interrupt
01480   * @retval The state of TIM_IT (SET or RESET).
01481   */
01482 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
01483                                                              == (__INTERRUPT__)) ? SET : RESET)
01484
01485 /** @brief Clear the TIM interrupt pending bits.
01486   * @param  __HANDLE__ TIM handle
01487   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01488   *          This parameter can be one of the following values:
01489   *            @arg TIM_IT_UPDATE: Update interrupt
01490   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01491   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01492   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01493   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01494   *            @arg TIM_IT_COM:   Commutation interrupt
01495   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01496   *            @arg TIM_IT_BREAK: Break interrupt
01497   *            @arg TIM_IT_IDX: Index interrupt
01498   *            @arg TIM_IT_DIR: Direction change interrupt
01499   *            @arg TIM_IT_IERR: Index error interrupt
01500   *            @arg TIM_IT_TERR: Transition error interrupt
01501   * @retval None
01502   */
01503 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01504
01505 /**
01506   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01507   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
01508   *       in an atomic way.
01509   * @param  __HANDLE__ TIM handle.
01510   * @retval None
01511 mode.
01512   */
01513 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
01514
01515 /**
01516   * @brief  Disable update interrupt flag (UIF) remapping.
01517   * @param  __HANDLE__ TIM handle.
01518   * @retval None
01519 mode.
01520   */
01521 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
01522
01523 /**
01524   * @brief  Get update interrupt flag (UIF) copy status.
01525   * @param  __COUNTER__ Counter value.
01526   * @retval The state of UIFCPY (TRUE or FALSE).
01527 mode.
01528   */
01529 #define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
01530
01531 /**
01532   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01533   * @param  __HANDLE__ TIM handle.
01534   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01535   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
01536   *       or Encoder mode.
01537   */
01538 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01539
01540 /**
01541   * @brief  Set the TIM Prescaler on runtime.
01542   * @param  __HANDLE__ TIM handle.
01543   * @param  __PRESC__ specifies the Prescaler new value.
01544   * @retval None
01545   */
01546 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01547
01548 /**
01549   * @brief  Set the TIM Counter Register value on runtime.
01550   * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
01551   *      case of 32 bits counter TIM instance.
01552   *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
01553   * @param  __HANDLE__ TIM handle.
01554   * @param  __COUNTER__ specifies the Counter register new value.
01555   * @retval None
01556   */
01557 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01558
01559 /**
01560   * @brief  Get the TIM Counter Register value on runtime.
01561   * @param  __HANDLE__ TIM handle.
01562   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01563   */
01564 #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
01565
01566 /**
01567   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01568   * @param  __HANDLE__ TIM handle.
01569   * @param  __AUTORELOAD__ specifies the Counter register new value.
01570   * @retval None
01571   */
01572 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01573   do{                                                    \
01574     (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01575     (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01576   } while(0)
01577
01578 /**
01579   * @brief  Get the TIM Autoreload Register value on runtime.
01580   * @param  __HANDLE__ TIM handle.
01581   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01582   */
01583 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
01584
01585 /**
01586   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01587   * @param  __HANDLE__ TIM handle.
01588   * @param  __CKD__ specifies the clock division value.
01589   *          This parameter can be one of the following value:
01590   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01591   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01592   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01593   * @retval None
01594   */
01595 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01596   do{                                                   \
01597     (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
01598     (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
01599     (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
01600   } while(0)
01601
01602 /**
01603   * @brief  Get the TIM Clock Division value on runtime.
01604   * @param  __HANDLE__ TIM handle.
01605   * @retval The clock division can be one of the following values:
01606   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01607   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01608   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01609   */
01610 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01611
01612 /**
01613   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
01614   *         function.
01615   * @param  __HANDLE__ TIM handle.
01616   * @param  __CHANNEL__ TIM Channels to be configured.
01617   *          This parameter can be one of the following values:
01618   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01619   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01620   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01621   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01622   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
01623   *          This parameter can be one of the following values:
01624   *            @arg TIM_ICPSC_DIV1: no prescaler
01625   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01626   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01627   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01628   * @retval None
01629   */
01630 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01631   do{                                                    \
01632     TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01633     TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01634   } while(0)
01635
01636 /**
01637   * @brief  Get the TIM Input Capture prescaler on runtime.
01638   * @param  __HANDLE__ TIM handle.
01639   * @param  __CHANNEL__ TIM Channels to be configured.
01640   *          This parameter can be one of the following values:
01641   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01642   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01643   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01644   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01645   * @retval The input capture prescaler can be one of the following values:
01646   *            @arg TIM_ICPSC_DIV1: no prescaler
01647   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01648   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01649   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01650   */
01651 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01652   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01653    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01654    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01655    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01656
01657 /**
01658   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01659   * @param  __HANDLE__ TIM handle.
01660   * @param  __CHANNEL__ TIM Channels to be configured.
01661   *          This parameter can be one of the following values:
01662   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01663   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01664   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01665   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01666   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01667   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01668   * @param  __COMPARE__ specifies the Capture Compare register new value.
01669   * @retval None
01670   */
01671 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01672   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01673    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01674    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01675    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01676    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01677    ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01678
01679 /**
01680   * @brief  Get the TIM Capture Compare Register value on runtime.
01681   * @param  __HANDLE__ TIM handle.
01682   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
01683   *          This parameter can be one of the following values:
01684   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01685   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01686   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01687   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01688   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01689   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01690   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01691   */
01692 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01693   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01694    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01695    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01696    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01697    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01698    ((__HANDLE__)->Instance->CCR6))
01699
01700 /**
01701   * @brief  Set the TIM Output compare preload.
01702   * @param  __HANDLE__ TIM handle.
01703   * @param  __CHANNEL__ TIM Channels to be configured.
01704   *          This parameter can be one of the following values:
01705   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01706   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01707   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01708   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01709   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01710   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01711   * @retval None
01712   */
01713 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01714   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
01715    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
01716    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
01717    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
01718    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
01719    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
01720
01721 /**
01722   * @brief  Reset the TIM Output compare preload.
01723   * @param  __HANDLE__ TIM handle.
01724   * @param  __CHANNEL__ TIM Channels to be configured.
01725   *          This parameter can be one of the following values:
01726   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01727   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01728   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01729   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01730   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01731   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01732   * @retval None
01733   */
01734 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01735   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
01736    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
01737    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
01738    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
01739    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
01740    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
01741
01742 /**
01743   * @brief  Enable fast mode for a given channel.
01744   * @param  __HANDLE__ TIM handle.
01745   * @param  __CHANNEL__ TIM Channels to be configured.
01746   *          This parameter can be one of the following values:
01747   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01748   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01749   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01750   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01751   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01752   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01753   * @note  When fast mode is enabled an active edge on the trigger input acts
01754   *        like a compare match on CCx output. Delay to sample the trigger
01755   *        input and to activate CCx output is reduced to 3 clock cycles.
01756   * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
01757   * @retval None
01758   */
01759 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01760   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
01761    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
01762    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
01763    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
01764    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
01765    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
01766
01767 /**
01768   * @brief  Disable fast mode for a given channel.
01769   * @param  __HANDLE__ TIM handle.
01770   * @param  __CHANNEL__ TIM Channels to be configured.
01771   *          This parameter can be one of the following values:
01772   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01773   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01774   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01775   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01776   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01777   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01778   * @note  When fast mode is disabled CCx output behaves normally depending
01779   *        on counter and CCRx values even when the trigger is ON. The minimum
01780   *        delay to activate CCx output when an active edge occurs on the
01781   *        trigger input is 5 clock cycles.
01782   * @retval None
01783   */
01784 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01785   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
01786    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
01787    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
01788    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
01789    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
01790    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
01791
01792 /**
01793   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01794   * @param  __HANDLE__ TIM handle.
01795   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
01796   *        overflow/underflow generates an update interrupt or DMA request (if
01797   *        enabled)
01798   * @retval None
01799   */
01800 #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
01801
01802 /**
01803   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01804   * @param  __HANDLE__ TIM handle.
01805   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
01806   *        following events generate an update interrupt or DMA request (if
01807   *        enabled):
01808   *           _ Counter overflow underflow
01809   *           _ Setting the UG bit
01810   *           _ Update generation through the slave mode controller
01811   * @retval None
01812   */
01813 #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
01814
01815 /**
01816   * @brief  Set the TIM Capture x input polarity on runtime.
01817   * @param  __HANDLE__ TIM handle.
01818   * @param  __CHANNEL__ TIM Channels to be configured.
01819   *          This parameter can be one of the following values:
01820   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01821   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01822   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01823   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01824   * @param  __POLARITY__ Polarity for TIx source
01825   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01826   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01827   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01828   * @retval None
01829   */
01830 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01831   do{                                                                     \
01832     TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01833     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01834   }while(0)
01835
01836 /** @brief  Select the Capture/compare DMA request source.
01837   * @param  __HANDLE__ specifies the TIM Handle.
01838   * @param  __CCDMA__ specifies Capture/compare DMA request source
01839   *          This parameter can be one of the following values:
01840   *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
01841   *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
01842   * @retval None
01843   */
01844 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
01845   MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
01846
01847 /**
01848   * @}
01849   */
01850 /* End of exported macros ----------------------------------------------------*/
01851
01852 /* Private constants ---------------------------------------------------------*/
01853 /** @defgroup TIM_Private_Constants TIM Private Constants
01854   * @{
01855   */
01856 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01857    channels have been disabled */
01858 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01859 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
01860 /**
01861   * @}
01862   */
01863 /* End of private constants --------------------------------------------------*/
01864
01865 /* Private macros ------------------------------------------------------------*/
01866 /** @defgroup TIM_Private_Macros TIM Private Macros
01867   * @{
01868   */
01869 #if defined(COMP5) && defined(COMP6) && defined(COMP7)
01870 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01871                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
01872                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
01873                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
01874                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4)    || \
01875                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5)    || \
01876                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6)    || \
01877                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7)    || \
01878                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01879 #else /* COMP5 && COMP6 && COMP7 */
01880 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01881                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
01882                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
01883                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
01884                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4)    || \
01885                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01886 #endif /* COMP5 && COMP6 && COMP7 */
01887
01888 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01889                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01890                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01891                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01892                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01893                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01894                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01895                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01896                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01897                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01898                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01899                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01900                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01901                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01902                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01903                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01904                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01905                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01906                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01907                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01908                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01909                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
01910                                    ((__BASE__) == TIM_DMABASE_AF2)   || \
01911                                    ((__BASE__) == TIM_DMABASE_TISEL) || \
01912                                    ((__BASE__) == TIM_DMABASE_DTR2)  || \
01913                                    ((__BASE__) == TIM_DMABASE_ECR)  || \
01914                                    ((__BASE__) == TIM_DMABASE_OR))
01915
01916 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01917
01918 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01919                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01920                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01921                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01922                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01923
01924 #define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
01925                                             ((__MODE__) == TIM_UIFREMAP_ENABLE))
01926
01927 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01928                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01929                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01930
01931 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01932                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01933
01934 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01935                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01936
01937 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01938                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01939
01940 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01941                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01942
01943 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01944                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01945
01946 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01947                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01948
01949 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
01950                                                       ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
01951
01952 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01953                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01954                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01955
01956 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01957                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01958                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01959
01960 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01961                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01962                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01963                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01964
01965 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
01966                                                        ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
01967                                                        ((__CHANNEL__) != (TIM_CHANNEL_6)))
01968
01969 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01970                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01971
01972 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1)                      || \
01973                                             ((__MODE__) == TIM_ENCODERMODE_TI2)                      || \
01974                                             ((__MODE__) == TIM_ENCODERMODE_TI12)                     || \
01975                                             ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2)    || \
01976                                             ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1)    || \
01977                                             ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2)      || \
01978                                             ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
01979                                             ((__MODE__) == TIM_ENCODERMODE_X1_TI1)                   || \
01980                                             ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
01981
01982 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01983
01984 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01985                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01986                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01987                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01988                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01989                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01990                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01991
01992 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01993                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01994
01995 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
01996                                                (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
01997                                                ((__PERIOD__) > 0U))
01998
01999 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
02000                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
02001                                                     ((__CHANNEL__) == TIM_CHANNEL_3) || \
02002                                                     ((__CHANNEL__) == TIM_CHANNEL_4))
02003
02004 #if defined(TIM5) && defined(TIM20)
02005 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
02006                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
02007                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
02008                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
02009                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
02010                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
02011                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
02012                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
02013                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
02014                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
02015                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)     || \
02016                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
02017                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
02018                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
02019                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
02020                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)     || \
02021                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)    || \
02022                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
02023 #elif defined(TIM5)
02024 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
02025                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
02026                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
02027                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
02028                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
02029                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
02030                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
02031                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
02032                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
02033                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
02034                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)     || \
02035                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
02036                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
02037                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
02038                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
02039                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
02040 #elif defined(TIM20)
02041 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
02042                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
02043                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
02044                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
02045                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
02046                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
02047                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
02048                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
02049                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
02050                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
02051                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
02052                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
02053                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
02054                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
02055                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)     || \
02056                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
02057 #else
02058 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
02059                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
02060                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
02061                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
02062                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
02063                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
02064                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
02065                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
02066                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
02067                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
02068                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
02069                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
02070                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
02071                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
02072                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
02073 #endif /* TIM5 && TIM20 */
02074
02075 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
02076                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
02077                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
02078                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
02079                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
02080
02081 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
02082                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
02083                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
02084                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
02085
02086 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
02087
02088 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
02089                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
02090
02091 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
02092                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
02093                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
02094                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
02095
02096 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
02097
02098 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
02099                                             ((__STATE__) == TIM_OSSR_DISABLE))
02100
02101 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
02102                                             ((__STATE__) == TIM_OSSI_DISABLE))
02103
02104 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
02105                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
02106                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
02107                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
02108
02109 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
02110
02111 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
02112                                             ((__STATE__) == TIM_BREAK_DISABLE))
02113
02114 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
02115                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
02116
02117 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
02118                                          ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
02119
02120
02121 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
02122                                             ((__STATE__) == TIM_BREAK2_DISABLE))
02123
02124 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
02125                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
02126
02127 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
02128                                           ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
02129
02130
02131 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
02132                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
02133
02134 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
02135
02136 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
02137                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
02138                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
02139                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
02140                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
02141                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
02142                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
02143                                         ((__SOURCE__) == TIM_TRGO_OC4REF) || \
02144                                         ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
02145
02146 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
02147                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
02148                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
02149                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
02150                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
02151                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
02152                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
02153                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
02154                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
02155                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
02156                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
02157                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
02158                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
02159                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
02160                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
02161                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
02162                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
02163
02164 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
02165                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
02166
02167 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)               || \
02168                                      ((__MODE__) == TIM_SLAVEMODE_RESET)                 || \
02169                                      ((__MODE__) == TIM_SLAVEMODE_GATED)                 || \
02170                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)               || \
02171                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)             || \
02172                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
02173                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
02174
02175 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
02176                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
02177                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
02178                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
02179                                    ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
02180                                    ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
02181
02182 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
02183                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
02184                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
02185                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
02186                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
02187                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
02188                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
02189                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
02190                                    ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT)   || \
02191                                    ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
02192
02193 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
02194                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
02195                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
02196                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
02197                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
02198
02199 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
02200                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
02201                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
02202                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
02203
02204 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
02205
02206 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
02207                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
02208
02209 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
02210                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
02211                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
02212                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
02213                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
02214                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
02215                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
02216                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
02217                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
02218                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
02219                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
02220                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
02221                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
02222                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
02223                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
02224                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
02225                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
02226                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
02227                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
02228                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
02229                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
02230                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
02231                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
02232                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
02233                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
02234                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
02235
02236 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
02237
02238 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
02239
02240 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
02241
02242 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
02243                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
02244                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
02245                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
02246
02247 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
02248                                                        ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
02249
02250 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
02251   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
02252    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
02253    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
02254    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
02255
02256 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
02257   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
02258    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
02259    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
02260    ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
02261
02262 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
02263   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
02264    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
02265    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
02266    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
02267
02268 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
02269   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
02270    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
02271    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
02272    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
02273
02274 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
02275   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
02276    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
02277    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
02278    ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
02279    ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
02280    (__HANDLE__)->ChannelState[5])
02281
02282 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
02283   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
02284    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
02285    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
02286    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
02287    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
02288    ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
02289
02290 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
02291                                                                        (__HANDLE__)->ChannelState[0]  = \
02292                                                                        (__CHANNEL_STATE__);  \
02293                                                                        (__HANDLE__)->ChannelState[1]  = \
02294                                                                        (__CHANNEL_STATE__);  \
02295                                                                        (__HANDLE__)->ChannelState[2]  = \
02296                                                                        (__CHANNEL_STATE__);  \
02297                                                                        (__HANDLE__)->ChannelState[3]  = \
02298                                                                        (__CHANNEL_STATE__);  \
02299                                                                        (__HANDLE__)->ChannelState[4]  = \
02300                                                                        (__CHANNEL_STATE__);  \
02301                                                                        (__HANDLE__)->ChannelState[5]  = \
02302                                                                        (__CHANNEL_STATE__);  \
02303                                                                      } while(0)
02304
02305 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
02306   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
02307    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
02308    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
02309    (__HANDLE__)->ChannelNState[3])
02310
02311 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
02312   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
02313    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
02314    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
02315    ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
02316
02317 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
02318                                                                          (__HANDLE__)->ChannelNState[0] = \
02319                                                                          (__CHANNEL_STATE__);  \
02320                                                                          (__HANDLE__)->ChannelNState[1] = \
02321                                                                          (__CHANNEL_STATE__);  \
02322                                                                          (__HANDLE__)->ChannelNState[2] = \
02323                                                                          (__CHANNEL_STATE__);  \
02324                                                                          (__HANDLE__)->ChannelNState[3] = \
02325                                                                          (__CHANNEL_STATE__);  \
02326                                                                        } while(0)
02327
02328 /**
02329   * @}
02330   */
02331 /* End of private macros -----------------------------------------------------*/
02332
02333 /* Include TIM HAL Extended module */
02334 #include "stm32g4xx_hal_tim_ex.h"
02335
02336 /* Exported functions --------------------------------------------------------*/
02337 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
02338   * @{
02339   */
02340
02341 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
02342   *  @brief   Time Base functions
02343   * @{
02344   */
02345 /* Time Base functions ********************************************************/
02346 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
02347 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
02348 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
02349 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
02350 /* Blocking mode: Polling */
02351 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
02352 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
02353 /* Non-Blocking mode: Interrupt */
02354 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
02355 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
02356 /* Non-Blocking mode: DMA */
02357 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
02358 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
02359 /**
02360   * @}
02361   */
02362
02363 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
02364   *  @brief   TIM Output Compare functions
02365   * @{
02366   */
02367 /* Timer Output Compare functions *********************************************/
02368 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
02369 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
02370 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
02371 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
02372 /* Blocking mode: Polling */
02373 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02374 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02375 /* Non-Blocking mode: Interrupt */
02376 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02377 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02378 /* Non-Blocking mode: DMA */
02379 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
02380                                        uint16_t Length);
02381 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02382 /**
02383   * @}
02384   */
02385
02386 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
02387   *  @brief   TIM PWM functions
02388   * @{
02389   */
02390 /* Timer PWM functions ********************************************************/
02391 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
02392 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
02393 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
02394 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
02395 /* Blocking mode: Polling */
02396 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02397 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02398 /* Non-Blocking mode: Interrupt */
02399 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02400 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02401 /* Non-Blocking mode: DMA */
02402 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
02403                                         uint16_t Length);
02404 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02405 /**
02406   * @}
02407   */
02408
02409 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
02410   *  @brief   TIM Input Capture functions
02411   * @{
02412   */
02413 /* Timer Input Capture functions **********************************************/
02414 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
02415 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
02416 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
02417 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
02418 /* Blocking mode: Polling */
02419 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02420 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02421 /* Non-Blocking mode: Interrupt */
02422 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02423 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02424 /* Non-Blocking mode: DMA */
02425 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02426 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02427 /**
02428   * @}
02429   */
02430
02431 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02432   *  @brief   TIM One Pulse functions
02433   * @{
02434   */
02435 /* Timer One Pulse functions **************************************************/
02436 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
02437 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
02438 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
02439 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
02440 /* Blocking mode: Polling */
02441 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02442 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02443 /* Non-Blocking mode: Interrupt */
02444 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02445 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02446 /**
02447   * @}
02448   */
02449
02450 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
02451   *  @brief   TIM Encoder functions
02452   * @{
02453   */
02454 /* Timer Encoder functions ****************************************************/
02455 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
02456 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
02457 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
02458 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
02459 /* Blocking mode: Polling */
02460 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02461 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02462 /* Non-Blocking mode: Interrupt */
02463 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02464 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02465 /* Non-Blocking mode: DMA */
02466 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02467                                             uint32_t *pData2, uint16_t Length);
02468 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02469 /**
02470   * @}
02471   */
02472
02473 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02474   *  @brief   IRQ handler management
02475   * @{
02476   */
02477 /* Interrupt Handler functions  ***********************************************/
02478 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
02479 /**
02480   * @}
02481   */
02482
02483 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
02484   *  @brief   Peripheral Control functions
02485   * @{
02486   */
02487 /* Control functions  *********************************************************/
02488 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
02489                                            uint32_t Channel);
02490 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
02491                                             uint32_t Channel);
02492 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
02493                                            uint32_t Channel);
02494 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
02495                                                  uint32_t OutputChannel,  uint32_t InputChannel);
02496 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
02497                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
02498                                            uint32_t Channel);
02499 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
02500 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
02501 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
02502 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
02503 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02504                                               uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
02505                                               uint32_t  BurstLength);
02506 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02507                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
02508                                                    uint32_t BurstLength,  uint32_t DataLength);
02509 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02510 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02511                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02512 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02513                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
02514                                                   uint32_t  BurstLength, uint32_t  DataLength);
02515 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02516 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
02517 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
02518 /**
02519   * @}
02520   */
02521
02522 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
02523   *  @brief   TIM Callbacks functions
02524   * @{
02525   */
02526 /* Callback in non blocking modes (Interrupt and DMA) *************************/
02527 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
02528 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
02529 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
02530 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
02531 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
02532 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
02533 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
02534 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
02535 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
02536 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
02537
02538 /* Callbacks Register/UnRegister functions  ***********************************/
02539 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02540 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
02541                                            pTIM_CallbackTypeDef pCallback);
02542 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
02543 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02544
02545 /**
02546   * @}
02547   */
02548
02549 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
02550   *  @brief  Peripheral State functions
02551   * @{
02552   */
02553 /* Peripheral State functions  ************************************************/
02554 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
02555 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
02556 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
02557 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
02558 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
02559 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
02560
02561 /* Peripheral Channel state functions  ************************************************/
02562 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
02563 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
02564 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
02565 /**
02566   * @}
02567   */
02568
02569 /**
02570   * @}
02571   */
02572 /* End of exported functions -------------------------------------------------*/
02573
02574 /* Private functions----------------------------------------------------------*/
02575 /** @defgroup TIM_Private_Functions TIM Private Functions
02576   * @{
02577   */
02578 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
02579 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
02580 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
02581 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
02582                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
02583
02584 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
02585 void TIM_DMAError(DMA_HandleTypeDef *hdma);
02586 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
02587 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
02588 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
02589
02590 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02591 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
02592 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02593
02594 /**
02595   * @}
02596   */
02597 /* End of private functions --------------------------------------------------*/
02598
02599 /**
02600   * @}
02601   */
02602
02603 /**
02604   * @}
02605   */
02606
02607 #ifdef __cplusplus
02608 }
02609 #endif
02610
02611 #endif /* STM32G4xx_HAL_TIM_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_tim_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer Extended peripheral:
00008   *           + Time Hall Sensor Interface Initialization
00009   *           + Time Hall Sensor Interface Start
00010   *           + Time Complementary signal break and dead time configuration
00011   *           + Time Master and Slave synchronization configuration
00012   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00013   *           + Time OCRef clear configuration
00014   *           + Timer remapping capabilities configuration
00015   *           + Timer encoder index configuration
00016   ******************************************************************************
00017   * @attention
00018   *
00019   * Copyright (c) 2019 STMicroelectronics.
00020   * All rights reserved.
00021   *
00022   * This software is licensed under terms that can be found in the LICENSE file
00023   * in the root directory of this software component.
00024   * If no LICENSE file comes with this software, it is provided AS-IS.
00025   *
00026   ******************************************************************************
00027   @verbatim
00028   ==============================================================================
00029                       ##### TIMER Extended features #####
00030   ==============================================================================
00031   [..]
00032     The Timer Extended features include:
00033     (#) Complementary outputs with programmable dead-time for :
00034         (++) Output Compare
00035         (++) PWM generation (Edge and Center-aligned Mode)
00036         (++) One-pulse mode output
00037     (#) Synchronization circuit to control the timer with external signals and to
00038         interconnect several timers together.
00039     (#) Break input to put the timer output signals in reset state or in a known state.
00040     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00041         positioning purposes
00042     (#) In case of Pulse on compare, configure pulse length and delay
00043     (#) Encoder index configuration
00044
00045             ##### How to use this driver #####
00046   ==============================================================================
00047     [..]
00048      (#) Initialize the TIM low level resources by implementing the following functions
00049          depending on the selected feature:
00050            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00051
00052      (#) Initialize the TIM low level resources :
00053         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00054         (##) TIM pins configuration
00055             (+++) Enable the clock for the TIM GPIOs using the following function:
00056               __HAL_RCC_GPIOx_CLK_ENABLE();
00057             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00058
00059      (#) The external Clock can be configured, if needed (the default clock is the
00060          internal clock from the APBx), using the following function:
00061          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00062          any start function.
00063
00064      (#) Configure the TIM in the desired functioning mode using one of the
00065          initialization function of this driver:
00066           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
00067                Timer Hall Sensor Interface and the commutation event with the corresponding
00068                Interrupt and DMA request if needed (Note that One Timer is used to interface
00069                with the Hall sensor Interface and another Timer should be used to use
00070                the commutation event).
00071      (#) In case of Pulse On Compare:
00072            (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
00073
00074
00075      (#) Activate the TIM peripheral using one of the start functions:
00076            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
00077                 HAL_TIMEx_OCN_Start_IT()
00078            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
00079                 HAL_TIMEx_PWMN_Start_IT()
00080            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00081            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
00082                 HAL_TIMEx_HallSensor_Start_IT().
00083
00084   @endverbatim
00085   ******************************************************************************
00086   */
00087
00088 /* Includes ------------------------------------------------------------------*/
00089 #include "stm32g4xx_hal.h"
00090
00091 /** @addtogroup STM32G4xx_HAL_Driver
00092   * @{
00093   */
00094
00095 /** @defgroup TIMEx TIMEx
00096   * @brief TIM Extended HAL module driver
00097   * @{
00098   */
00099
00100 #ifdef HAL_TIM_MODULE_ENABLED
00101
00102 /* Private typedef -----------------------------------------------------------*/
00103 /* Private define ------------------------------------------------------------*/
00104 /* Private constants ---------------------------------------------------------*/
00105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
00106   * @{
00107   */
00108 /* Timeout for break input rearm */
00109 #define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
00110 /**
00111   * @}
00112   */
00113 /* End of private constants --------------------------------------------------*/
00114
00115 /* Private macros ------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
00119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
00120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
00121
00122 /* Exported functions --------------------------------------------------------*/
00123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00124   * @{
00125   */
00126
00127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00128   * @brief    Timer Hall Sensor functions
00129   *
00130 @verbatim
00131   ==============================================================================
00132                       ##### Timer Hall Sensor functions #####
00133   ==============================================================================
00134   [..]
00135     This section provides functions allowing to:
00136     (+) Initialize and configure TIM HAL Sensor.
00137     (+) De-initialize TIM HAL Sensor.
00138     (+) Start the Hall Sensor Interface.
00139     (+) Stop the Hall Sensor Interface.
00140     (+) Start the Hall Sensor Interface and enable interrupts.
00141     (+) Stop the Hall Sensor Interface and disable interrupts.
00142     (+) Start the Hall Sensor Interface and enable DMA transfers.
00143     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00144
00145 @endverbatim
00146   * @{
00147   */
00148 /**
00149   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00150   * @note   When the timer instance is initialized in Hall Sensor Interface mode,
00151   *         timer channels 1 and channel 2 are reserved and cannot be used for
00152   *         other purpose.
00153   * @param  htim TIM Hall Sensor Interface handle
00154   * @param  sConfig TIM Hall Sensor configuration structure
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
00158 {
00159   TIM_OC_InitTypeDef OC_Config;
00160
00161   /* Check the TIM handle allocation */
00162   if (htim == NULL)
00163   {
00164     return HAL_ERROR;
00165   }
00166
00167   /* Check the parameters */
00168   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00169   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00170   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00171   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00172   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00173   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00174   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00175   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00176
00177   if (htim->State == HAL_TIM_STATE_RESET)
00178   {
00179     /* Allocate lock resource and initialize it */
00180     htim->Lock = HAL_UNLOCKED;
00181
00182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00183     /* Reset interrupt callbacks to legacy week callbacks */
00184     TIM_ResetCallback(htim);
00185
00186     if (htim->HallSensor_MspInitCallback == NULL)
00187     {
00188       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
00189     }
00190     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00191     htim->HallSensor_MspInitCallback(htim);
00192 #else
00193     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00194     HAL_TIMEx_HallSensor_MspInit(htim);
00195 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00196   }
00197
00198   /* Set the TIM state */
00199   htim->State = HAL_TIM_STATE_BUSY;
00200
00201   /* Configure the Time base in the Encoder Mode */
00202   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00203
00204   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00205   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00206
00207   /* Reset the IC1PSC Bits */
00208   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00209   /* Set the IC1PSC value */
00210   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00211
00212   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00213   htim->Instance->CR2 |= TIM_CR2_TI1S;
00214
00215   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00216   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00217   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00218
00219   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00220   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00221   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00222
00223   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00224   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00225   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00226   OC_Config.OCMode = TIM_OCMODE_PWM2;
00227   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00228   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00229   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00230   OC_Config.Pulse = sConfig->Commutation_Delay;
00231
00232   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00233
00234   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00235     register to 101 */
00236   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00237   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00238
00239   /* Initialize the DMA burst operation state */
00240   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00241
00242   /* Initialize the TIM channels state */
00243   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00244   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00245   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00246   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00247
00248   /* Initialize the TIM state*/
00249   htim->State = HAL_TIM_STATE_READY;
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  DeInitializes the TIM Hall Sensor interface
00256   * @param  htim TIM Hall Sensor Interface handle
00257   * @retval HAL status
00258   */
00259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00260 {
00261   /* Check the parameters */
00262   assert_param(IS_TIM_INSTANCE(htim->Instance));
00263
00264   htim->State = HAL_TIM_STATE_BUSY;
00265
00266   /* Disable the TIM Peripheral Clock */
00267   __HAL_TIM_DISABLE(htim);
00268
00269 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00270   if (htim->HallSensor_MspDeInitCallback == NULL)
00271   {
00272     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
00273   }
00274   /* DeInit the low level hardware */
00275   htim->HallSensor_MspDeInitCallback(htim);
00276 #else
00277   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00278   HAL_TIMEx_HallSensor_MspDeInit(htim);
00279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00280
00281   /* Change the DMA burst operation state */
00282   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00283
00284   /* Change the TIM channels state */
00285   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
00286   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
00287   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
00288   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
00289
00290   /* Change TIM state */
00291   htim->State = HAL_TIM_STATE_RESET;
00292
00293   /* Release Lock */
00294   __HAL_UNLOCK(htim);
00295
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Initializes the TIM Hall Sensor MSP.
00301   * @param  htim TIM Hall Sensor Interface handle
00302   * @retval None
00303   */
00304 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00305 {
00306   /* Prevent unused argument(s) compilation warning */
00307   UNUSED(htim);
00308
00309   /* NOTE : This function should not be modified, when the callback is needed,
00310             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00311    */
00312 }
00313
00314 /**
00315   * @brief  DeInitializes TIM Hall Sensor MSP.
00316   * @param  htim TIM Hall Sensor Interface handle
00317   * @retval None
00318   */
00319 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00320 {
00321   /* Prevent unused argument(s) compilation warning */
00322   UNUSED(htim);
00323
00324   /* NOTE : This function should not be modified, when the callback is needed,
00325             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00326    */
00327 }
00328
00329 /**
00330   * @brief  Starts the TIM Hall Sensor Interface.
00331   * @param  htim TIM Hall Sensor Interface handle
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00335 {
00336   uint32_t tmpsmcr;
00337   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00338   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
00339   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00340   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
00341
00342   /* Check the parameters */
00343   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00344
00345   /* Check the TIM channels state */
00346   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00347       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
00348       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00349       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
00350   {
00351     return HAL_ERROR;
00352   }
00353
00354   /* Set the TIM channels state */
00355   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00356   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00357   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00358   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00359
00360   /* Enable the Input Capture channel 1
00361   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00362   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00363   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00364
00365   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00366   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00367   {
00368     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00369     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00370     {
00371       __HAL_TIM_ENABLE(htim);
00372     }
00373   }
00374   else
00375   {
00376     __HAL_TIM_ENABLE(htim);
00377   }
00378
00379   /* Return function status */
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief  Stops the TIM Hall sensor Interface.
00385   * @param  htim TIM Hall Sensor Interface handle
00386   * @retval HAL status
00387   */
00388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00389 {
00390   /* Check the parameters */
00391   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00392
00393   /* Disable the Input Capture channels 1, 2 and 3
00394   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00395   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00396   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00397
00398   /* Disable the Peripheral */
00399   __HAL_TIM_DISABLE(htim);
00400
00401   /* Set the TIM channels state */
00402   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00403   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00404   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00405   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00406
00407   /* Return function status */
00408   return HAL_OK;
00409 }
00410
00411 /**
00412   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00413   * @param  htim TIM Hall Sensor Interface handle
00414   * @retval HAL status
00415   */
00416 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00417 {
00418   uint32_t tmpsmcr;
00419   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00420   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
00421   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00422   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
00423
00424   /* Check the parameters */
00425   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00426
00427   /* Check the TIM channels state */
00428   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00429       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
00430       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00431       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
00432   {
00433     return HAL_ERROR;
00434   }
00435
00436   /* Set the TIM channels state */
00437   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00438   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00439   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00440   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00441
00442   /* Enable the capture compare Interrupts 1 event */
00443   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00444
00445   /* Enable the Input Capture channel 1
00446   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00447   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00448   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00449
00450   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00451   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00452   {
00453     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00454     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00455     {
00456       __HAL_TIM_ENABLE(htim);
00457     }
00458   }
00459   else
00460   {
00461     __HAL_TIM_ENABLE(htim);
00462   }
00463
00464   /* Return function status */
00465   return HAL_OK;
00466 }
00467
00468 /**
00469   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00470   * @param  htim TIM Hall Sensor Interface handle
00471   * @retval HAL status
00472   */
00473 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00474 {
00475   /* Check the parameters */
00476   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00477
00478   /* Disable the Input Capture channel 1
00479   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00480   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00481   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00482
00483   /* Disable the capture compare Interrupts event */
00484   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00485
00486   /* Disable the Peripheral */
00487   __HAL_TIM_DISABLE(htim);
00488
00489   /* Set the TIM channels state */
00490   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00491   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00492   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00493   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00494
00495   /* Return function status */
00496   return HAL_OK;
00497 }
00498
00499 /**
00500   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00501   * @param  htim TIM Hall Sensor Interface handle
00502   * @param  pData The destination Buffer address.
00503   * @param  Length The length of data to be transferred from TIM peripheral to memory.
00504   * @retval HAL status
00505   */
00506 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00507 {
00508   uint32_t tmpsmcr;
00509   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00510   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00511
00512   /* Check the parameters */
00513   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00514
00515   /* Set the TIM channel state */
00516   if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
00517       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
00518   {
00519     return HAL_BUSY;
00520   }
00521   else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
00522            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
00523   {
00524     if ((pData == NULL) || (Length == 0U))
00525     {
00526       return HAL_ERROR;
00527     }
00528     else
00529     {
00530       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00531       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00532     }
00533   }
00534   else
00535   {
00536     return HAL_ERROR;
00537   }
00538
00539   /* Enable the Input Capture channel 1
00540   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00541   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00542   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00543
00544   /* Set the DMA Input Capture 1 Callbacks */
00545   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00546   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
00547   /* Set the DMA error callback */
00548   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00549
00550   /* Enable the DMA channel for Capture 1*/
00551   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
00552   {
00553     /* Return error status */
00554     return HAL_ERROR;
00555   }
00556   /* Enable the capture compare 1 Interrupt */
00557   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00558
00559   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00560   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00561   {
00562     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00563     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00564     {
00565       __HAL_TIM_ENABLE(htim);
00566     }
00567   }
00568   else
00569   {
00570     __HAL_TIM_ENABLE(htim);
00571   }
00572
00573   /* Return function status */
00574   return HAL_OK;
00575 }
00576
00577 /**
00578   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00579   * @param  htim TIM Hall Sensor Interface handle
00580   * @retval HAL status
00581   */
00582 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00583 {
00584   /* Check the parameters */
00585   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00586
00587   /* Disable the Input Capture channel 1
00588   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00589   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00590   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00591
00592
00593   /* Disable the capture compare Interrupts 1 event */
00594   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00595
00596   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00597
00598   /* Disable the Peripheral */
00599   __HAL_TIM_DISABLE(htim);
00600
00601   /* Set the TIM channel state */
00602   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00603   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00604
00605   /* Return function status */
00606   return HAL_OK;
00607 }
00608
00609 /**
00610   * @}
00611   */
00612
00613 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00614   *  @brief   Timer Complementary Output Compare functions
00615   *
00616 @verbatim
00617   ==============================================================================
00618               ##### Timer Complementary Output Compare functions #####
00619   ==============================================================================
00620   [..]
00621     This section provides functions allowing to:
00622     (+) Start the Complementary Output Compare/PWM.
00623     (+) Stop the Complementary Output Compare/PWM.
00624     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00625     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00626     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00627     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00628
00629 @endverbatim
00630   * @{
00631   */
00632
00633 /**
00634   * @brief  Starts the TIM Output Compare signal generation on the complementary
00635   *         output.
00636   * @param  htim TIM Output Compare handle
00637   * @param  Channel TIM Channel to be enabled
00638   *          This parameter can be one of the following values:
00639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00641   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00642   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00646 {
00647   uint32_t tmpsmcr;
00648
00649   /* Check the parameters */
00650   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00651
00652   /* Check the TIM complementary channel state */
00653   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00654   {
00655     return HAL_ERROR;
00656   }
00657
00658   /* Set the TIM complementary channel state */
00659   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00660
00661   /* Enable the Capture compare channel N */
00662   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00663
00664   /* Enable the Main Output */
00665   __HAL_TIM_MOE_ENABLE(htim);
00666
00667   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00668   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00669   {
00670     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00671     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00672     {
00673       __HAL_TIM_ENABLE(htim);
00674     }
00675   }
00676   else
00677   {
00678     __HAL_TIM_ENABLE(htim);
00679   }
00680
00681   /* Return function status */
00682   return HAL_OK;
00683 }
00684
00685 /**
00686   * @brief  Stops the TIM Output Compare signal generation on the complementary
00687   *         output.
00688   * @param  htim TIM handle
00689   * @param  Channel TIM Channel to be disabled
00690   *          This parameter can be one of the following values:
00691   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00692   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00693   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00694   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00698 {
00699   /* Check the parameters */
00700   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00701
00702   /* Disable the Capture compare channel N */
00703   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00704
00705   /* Disable the Main Output */
00706   __HAL_TIM_MOE_DISABLE(htim);
00707
00708   /* Disable the Peripheral */
00709   __HAL_TIM_DISABLE(htim);
00710
00711   /* Set the TIM complementary channel state */
00712   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00713
00714   /* Return function status */
00715   return HAL_OK;
00716 }
00717
00718 /**
00719   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00720   *         on the complementary output.
00721   * @param  htim TIM OC handle
00722   * @param  Channel TIM Channel to be enabled
00723   *          This parameter can be one of the following values:
00724   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00725   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00726   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00727   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00728   * @retval HAL status
00729   */
00730 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00731 {
00732   HAL_StatusTypeDef status = HAL_OK;
00733   uint32_t tmpsmcr;
00734
00735   /* Check the parameters */
00736   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00737
00738   /* Check the TIM complementary channel state */
00739   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00740   {
00741     return HAL_ERROR;
00742   }
00743
00744   /* Set the TIM complementary channel state */
00745   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00746
00747   switch (Channel)
00748   {
00749     case TIM_CHANNEL_1:
00750     {
00751       /* Enable the TIM Output Compare interrupt */
00752       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00753       break;
00754     }
00755
00756     case TIM_CHANNEL_2:
00757     {
00758       /* Enable the TIM Output Compare interrupt */
00759       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00760       break;
00761     }
00762
00763     case TIM_CHANNEL_3:
00764     {
00765       /* Enable the TIM Output Compare interrupt */
00766       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00767       break;
00768     }
00769
00770
00771     case TIM_CHANNEL_4:
00772     {
00773       /* Enable the TIM Output Compare interrupt */
00774       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00775       break;
00776     }
00777
00778     default:
00779       status = HAL_ERROR;
00780       break;
00781   }
00782
00783   if (status == HAL_OK)
00784   {
00785     /* Enable the TIM Break interrupt */
00786     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00787
00788     /* Enable the Capture compare channel N */
00789     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00790
00791     /* Enable the Main Output */
00792     __HAL_TIM_MOE_ENABLE(htim);
00793
00794     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00795     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00796     {
00797       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00798       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00799       {
00800         __HAL_TIM_ENABLE(htim);
00801       }
00802     }
00803     else
00804     {
00805       __HAL_TIM_ENABLE(htim);
00806     }
00807   }
00808
00809   /* Return function status */
00810   return status;
00811 }
00812
00813 /**
00814   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00815   *         on the complementary output.
00816   * @param  htim TIM Output Compare handle
00817   * @param  Channel TIM Channel to be disabled
00818   *          This parameter can be one of the following values:
00819   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00820   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00821   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00822   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00823   * @retval HAL status
00824   */
00825 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00826 {
00827   HAL_StatusTypeDef status = HAL_OK;
00828   uint32_t tmpccer;
00829
00830   /* Check the parameters */
00831   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00832
00833   switch (Channel)
00834   {
00835     case TIM_CHANNEL_1:
00836     {
00837       /* Disable the TIM Output Compare interrupt */
00838       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00839       break;
00840     }
00841
00842     case TIM_CHANNEL_2:
00843     {
00844       /* Disable the TIM Output Compare interrupt */
00845       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00846       break;
00847     }
00848
00849     case TIM_CHANNEL_3:
00850     {
00851       /* Disable the TIM Output Compare interrupt */
00852       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00853       break;
00854     }
00855
00856     case TIM_CHANNEL_4:
00857     {
00858       /* Disable the TIM Output Compare interrupt */
00859       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00860       break;
00861     }
00862
00863     default:
00864       status = HAL_ERROR;
00865       break;
00866   }
00867
00868   if (status == HAL_OK)
00869   {
00870     /* Disable the Capture compare channel N */
00871     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00872
00873     /* Disable the TIM Break interrupt (only if no more channel is active) */
00874     tmpccer = htim->Instance->CCER;
00875     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
00876     {
00877       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00878     }
00879
00880     /* Disable the Main Output */
00881     __HAL_TIM_MOE_DISABLE(htim);
00882
00883     /* Disable the Peripheral */
00884     __HAL_TIM_DISABLE(htim);
00885
00886     /* Set the TIM complementary channel state */
00887     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00888   }
00889
00890   /* Return function status */
00891   return status;
00892 }
00893
00894 /**
00895   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00896   *         on the complementary output.
00897   * @param  htim TIM Output Compare handle
00898   * @param  Channel TIM Channel to be enabled
00899   *          This parameter can be one of the following values:
00900   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00901   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00902   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00903   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00904   * @param  pData The source Buffer address.
00905   * @param  Length The length of data to be transferred from memory to TIM peripheral
00906   * @retval HAL status
00907   */
00908 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
00909                                           uint16_t Length)
00910 {
00911   HAL_StatusTypeDef status = HAL_OK;
00912   uint32_t tmpsmcr;
00913
00914   /* Check the parameters */
00915   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00916
00917   /* Set the TIM complementary channel state */
00918   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
00919   {
00920     return HAL_BUSY;
00921   }
00922   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
00923   {
00924     if ((pData == NULL) || (Length == 0U))
00925     {
00926       return HAL_ERROR;
00927     }
00928     else
00929     {
00930       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00931     }
00932   }
00933   else
00934   {
00935     return HAL_ERROR;
00936   }
00937
00938   switch (Channel)
00939   {
00940     case TIM_CHANNEL_1:
00941     {
00942       /* Set the DMA compare callbacks */
00943       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00944       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00945
00946       /* Set the DMA error callback */
00947       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
00948
00949       /* Enable the DMA channel */
00950       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
00951                            Length) != HAL_OK)
00952       {
00953         /* Return error status */
00954         return HAL_ERROR;
00955       }
00956       /* Enable the TIM Output Compare DMA request */
00957       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00958       break;
00959     }
00960
00961     case TIM_CHANNEL_2:
00962     {
00963       /* Set the DMA compare callbacks */
00964       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00965       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00966
00967       /* Set the DMA error callback */
00968       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
00969
00970       /* Enable the DMA channel */
00971       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
00972                            Length) != HAL_OK)
00973       {
00974         /* Return error status */
00975         return HAL_ERROR;
00976       }
00977       /* Enable the TIM Output Compare DMA request */
00978       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00979       break;
00980     }
00981
00982     case TIM_CHANNEL_3:
00983     {
00984       /* Set the DMA compare callbacks */
00985       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00986       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00987
00988       /* Set the DMA error callback */
00989       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
00990
00991       /* Enable the DMA channel */
00992       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
00993                            Length) != HAL_OK)
00994       {
00995         /* Return error status */
00996         return HAL_ERROR;
00997       }
00998       /* Enable the TIM Output Compare DMA request */
00999       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01000       break;
01001     }
01002
01003     case TIM_CHANNEL_4:
01004     {
01005       /* Set the DMA compare callbacks */
01006       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01007       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01008
01009       /* Set the DMA error callback */
01010       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
01011
01012       /* Enable the DMA channel */
01013       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01014                            Length) != HAL_OK)
01015       {
01016         /* Return error status */
01017         return HAL_ERROR;
01018       }
01019       /* Enable the TIM Output Compare DMA request */
01020       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01021       break;
01022     }
01023
01024     default:
01025       status = HAL_ERROR;
01026       break;
01027   }
01028
01029   if (status == HAL_OK)
01030   {
01031     /* Enable the Capture compare channel N */
01032     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01033
01034     /* Enable the Main Output */
01035     __HAL_TIM_MOE_ENABLE(htim);
01036
01037     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01038     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01039     {
01040       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01041       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01042       {
01043         __HAL_TIM_ENABLE(htim);
01044       }
01045     }
01046     else
01047     {
01048       __HAL_TIM_ENABLE(htim);
01049     }
01050   }
01051
01052   /* Return function status */
01053   return status;
01054 }
01055
01056 /**
01057   * @brief  Stops the TIM Output Compare signal generation in DMA mode
01058   *         on the complementary output.
01059   * @param  htim TIM Output Compare handle
01060   * @param  Channel TIM Channel to be disabled
01061   *          This parameter can be one of the following values:
01062   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01063   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01064   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01065   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01066   * @retval HAL status
01067   */
01068 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01069 {
01070   HAL_StatusTypeDef status = HAL_OK;
01071
01072   /* Check the parameters */
01073   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01074
01075   switch (Channel)
01076   {
01077     case TIM_CHANNEL_1:
01078     {
01079       /* Disable the TIM Output Compare DMA request */
01080       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01081       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01082       break;
01083     }
01084
01085     case TIM_CHANNEL_2:
01086     {
01087       /* Disable the TIM Output Compare DMA request */
01088       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01089       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01090       break;
01091     }
01092
01093     case TIM_CHANNEL_3:
01094     {
01095       /* Disable the TIM Output Compare DMA request */
01096       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01097       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01098       break;
01099     }
01100
01101     case TIM_CHANNEL_4:
01102     {
01103       /* Disable the TIM Output Compare interrupt */
01104       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01105       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01106       break;
01107     }
01108
01109     default:
01110       status = HAL_ERROR;
01111       break;
01112   }
01113
01114   if (status == HAL_OK)
01115   {
01116     /* Disable the Capture compare channel N */
01117     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01118
01119     /* Disable the Main Output */
01120     __HAL_TIM_MOE_DISABLE(htim);
01121
01122     /* Disable the Peripheral */
01123     __HAL_TIM_DISABLE(htim);
01124
01125     /* Set the TIM complementary channel state */
01126     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01127   }
01128
01129   /* Return function status */
01130   return status;
01131 }
01132
01133 /**
01134   * @}
01135   */
01136
01137 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
01138   * @brief    Timer Complementary PWM functions
01139   *
01140 @verbatim
01141   ==============================================================================
01142                  ##### Timer Complementary PWM functions #####
01143   ==============================================================================
01144   [..]
01145     This section provides functions allowing to:
01146     (+) Start the Complementary PWM.
01147     (+) Stop the Complementary PWM.
01148     (+) Start the Complementary PWM and enable interrupts.
01149     (+) Stop the Complementary PWM and disable interrupts.
01150     (+) Start the Complementary PWM and enable DMA transfers.
01151     (+) Stop the Complementary PWM and disable DMA transfers.
01152 @endverbatim
01153   * @{
01154   */
01155
01156 /**
01157   * @brief  Starts the PWM signal generation on the complementary output.
01158   * @param  htim TIM handle
01159   * @param  Channel TIM Channel to be enabled
01160   *          This parameter can be one of the following values:
01161   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01162   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01163   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01164   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01165   * @retval HAL status
01166   */
01167 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01168 {
01169   uint32_t tmpsmcr;
01170
01171   /* Check the parameters */
01172   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01173
01174   /* Check the TIM complementary channel state */
01175   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01176   {
01177     return HAL_ERROR;
01178   }
01179
01180   /* Set the TIM complementary channel state */
01181   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01182
01183   /* Enable the complementary PWM output  */
01184   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01185
01186   /* Enable the Main Output */
01187   __HAL_TIM_MOE_ENABLE(htim);
01188
01189   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01190   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01191   {
01192     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01193     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01194     {
01195       __HAL_TIM_ENABLE(htim);
01196     }
01197   }
01198   else
01199   {
01200     __HAL_TIM_ENABLE(htim);
01201   }
01202
01203   /* Return function status */
01204   return HAL_OK;
01205 }
01206
01207 /**
01208   * @brief  Stops the PWM signal generation on the complementary output.
01209   * @param  htim TIM handle
01210   * @param  Channel TIM Channel to be disabled
01211   *          This parameter can be one of the following values:
01212   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01213   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01214   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01215   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01216   * @retval HAL status
01217   */
01218 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01219 {
01220   /* Check the parameters */
01221   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01222
01223   /* Disable the complementary PWM output  */
01224   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01225
01226   /* Disable the Main Output */
01227   __HAL_TIM_MOE_DISABLE(htim);
01228
01229   /* Disable the Peripheral */
01230   __HAL_TIM_DISABLE(htim);
01231
01232   /* Set the TIM complementary channel state */
01233   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01234
01235   /* Return function status */
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @brief  Starts the PWM signal generation in interrupt mode on the
01241   *         complementary output.
01242   * @param  htim TIM handle
01243   * @param  Channel TIM Channel to be disabled
01244   *          This parameter can be one of the following values:
01245   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01246   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01247   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01248   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01249   * @retval HAL status
01250   */
01251 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01252 {
01253   HAL_StatusTypeDef status = HAL_OK;
01254   uint32_t tmpsmcr;
01255
01256   /* Check the parameters */
01257   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01258
01259   /* Check the TIM complementary channel state */
01260   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01261   {
01262     return HAL_ERROR;
01263   }
01264
01265   /* Set the TIM complementary channel state */
01266   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01267
01268   switch (Channel)
01269   {
01270     case TIM_CHANNEL_1:
01271     {
01272       /* Enable the TIM Capture/Compare 1 interrupt */
01273       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01274       break;
01275     }
01276
01277     case TIM_CHANNEL_2:
01278     {
01279       /* Enable the TIM Capture/Compare 2 interrupt */
01280       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01281       break;
01282     }
01283
01284     case TIM_CHANNEL_3:
01285     {
01286       /* Enable the TIM Capture/Compare 3 interrupt */
01287       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01288       break;
01289     }
01290
01291     case TIM_CHANNEL_4:
01292     {
01293       /* Enable the TIM Capture/Compare 4 interrupt */
01294       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01295       break;
01296     }
01297
01298     default:
01299       status = HAL_ERROR;
01300       break;
01301   }
01302
01303   if (status == HAL_OK)
01304   {
01305     /* Enable the TIM Break interrupt */
01306     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01307
01308     /* Enable the complementary PWM output  */
01309     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01310
01311     /* Enable the Main Output */
01312     __HAL_TIM_MOE_ENABLE(htim);
01313
01314     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01315     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01316     {
01317       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01318       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01319       {
01320         __HAL_TIM_ENABLE(htim);
01321       }
01322     }
01323     else
01324     {
01325       __HAL_TIM_ENABLE(htim);
01326     }
01327   }
01328
01329   /* Return function status */
01330   return status;
01331 }
01332
01333 /**
01334   * @brief  Stops the PWM signal generation in interrupt mode on the
01335   *         complementary output.
01336   * @param  htim TIM handle
01337   * @param  Channel TIM Channel to be disabled
01338   *          This parameter can be one of the following values:
01339   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01340   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01341   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01342   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01343   * @retval HAL status
01344   */
01345 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01346 {
01347   HAL_StatusTypeDef status = HAL_OK;
01348   uint32_t tmpccer;
01349
01350   /* Check the parameters */
01351   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01352
01353   switch (Channel)
01354   {
01355     case TIM_CHANNEL_1:
01356     {
01357       /* Disable the TIM Capture/Compare 1 interrupt */
01358       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01359       break;
01360     }
01361
01362     case TIM_CHANNEL_2:
01363     {
01364       /* Disable the TIM Capture/Compare 2 interrupt */
01365       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01366       break;
01367     }
01368
01369     case TIM_CHANNEL_3:
01370     {
01371       /* Disable the TIM Capture/Compare 3 interrupt */
01372       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01373       break;
01374     }
01375
01376     case TIM_CHANNEL_4:
01377     {
01378       /* Disable the TIM Capture/Compare 4 interrupt */
01379       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01380       break;
01381     }
01382
01383     default:
01384       status = HAL_ERROR;
01385       break;
01386   }
01387
01388   if (status == HAL_OK)
01389   {
01390     /* Disable the complementary PWM output  */
01391     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01392
01393     /* Disable the TIM Break interrupt (only if no more channel is active) */
01394     tmpccer = htim->Instance->CCER;
01395     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
01396     {
01397       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01398     }
01399
01400     /* Disable the Main Output */
01401     __HAL_TIM_MOE_DISABLE(htim);
01402
01403     /* Disable the Peripheral */
01404     __HAL_TIM_DISABLE(htim);
01405
01406     /* Set the TIM complementary channel state */
01407     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01408   }
01409
01410   /* Return function status */
01411   return status;
01412 }
01413
01414 /**
01415   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01416   *         complementary output
01417   * @param  htim TIM handle
01418   * @param  Channel TIM Channel to be enabled
01419   *          This parameter can be one of the following values:
01420   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01421   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01422   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01423   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01424   * @param  pData The source Buffer address.
01425   * @param  Length The length of data to be transferred from memory to TIM peripheral
01426   * @retval HAL status
01427   */
01428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01429                                            uint16_t Length)
01430 {
01431   HAL_StatusTypeDef status = HAL_OK;
01432   uint32_t tmpsmcr;
01433
01434   /* Check the parameters */
01435   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01436
01437   /* Set the TIM complementary channel state */
01438   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01439   {
01440     return HAL_BUSY;
01441   }
01442   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01443   {
01444     if ((pData == NULL) || (Length == 0U))
01445     {
01446       return HAL_ERROR;
01447     }
01448     else
01449     {
01450       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01451     }
01452   }
01453   else
01454   {
01455     return HAL_ERROR;
01456   }
01457
01458   switch (Channel)
01459   {
01460     case TIM_CHANNEL_1:
01461     {
01462       /* Set the DMA compare callbacks */
01463       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01464       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01465
01466       /* Set the DMA error callback */
01467       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
01468
01469       /* Enable the DMA channel */
01470       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01471                            Length) != HAL_OK)
01472       {
01473         /* Return error status */
01474         return HAL_ERROR;
01475       }
01476       /* Enable the TIM Capture/Compare 1 DMA request */
01477       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01478       break;
01479     }
01480
01481     case TIM_CHANNEL_2:
01482     {
01483       /* Set the DMA compare callbacks */
01484       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01485       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01486
01487       /* Set the DMA error callback */
01488       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
01489
01490       /* Enable the DMA channel */
01491       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01492                            Length) != HAL_OK)
01493       {
01494         /* Return error status */
01495         return HAL_ERROR;
01496       }
01497       /* Enable the TIM Capture/Compare 2 DMA request */
01498       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01499       break;
01500     }
01501
01502     case TIM_CHANNEL_3:
01503     {
01504       /* Set the DMA compare callbacks */
01505       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01506       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01507
01508       /* Set the DMA error callback */
01509       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
01510
01511       /* Enable the DMA channel */
01512       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01513                            Length) != HAL_OK)
01514       {
01515         /* Return error status */
01516         return HAL_ERROR;
01517       }
01518       /* Enable the TIM Capture/Compare 3 DMA request */
01519       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01520       break;
01521     }
01522
01523     case TIM_CHANNEL_4:
01524     {
01525       /* Set the DMA compare callbacks */
01526       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01527       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01528
01529       /* Set the DMA error callback */
01530       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
01531
01532       /* Enable the DMA channel */
01533       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01534                            Length) != HAL_OK)
01535       {
01536         /* Return error status */
01537         return HAL_ERROR;
01538       }
01539       /* Enable the TIM Capture/Compare 4 DMA request */
01540       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01541       break;
01542     }
01543
01544     default:
01545       status = HAL_ERROR;
01546       break;
01547   }
01548
01549   if (status == HAL_OK)
01550   {
01551     /* Enable the complementary PWM output  */
01552     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01553
01554     /* Enable the Main Output */
01555     __HAL_TIM_MOE_ENABLE(htim);
01556
01557     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01558     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01559     {
01560       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01561       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01562       {
01563         __HAL_TIM_ENABLE(htim);
01564       }
01565     }
01566     else
01567     {
01568       __HAL_TIM_ENABLE(htim);
01569     }
01570   }
01571
01572   /* Return function status */
01573   return status;
01574 }
01575
01576 /**
01577   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01578   *         output
01579   * @param  htim TIM handle
01580   * @param  Channel TIM Channel to be disabled
01581   *          This parameter can be one of the following values:
01582   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01583   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01584   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01585   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01586   * @retval HAL status
01587   */
01588 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01589 {
01590   HAL_StatusTypeDef status = HAL_OK;
01591
01592   /* Check the parameters */
01593   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01594
01595   switch (Channel)
01596   {
01597     case TIM_CHANNEL_1:
01598     {
01599       /* Disable the TIM Capture/Compare 1 DMA request */
01600       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01601       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01602       break;
01603     }
01604
01605     case TIM_CHANNEL_2:
01606     {
01607       /* Disable the TIM Capture/Compare 2 DMA request */
01608       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01609       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01610       break;
01611     }
01612
01613     case TIM_CHANNEL_3:
01614     {
01615       /* Disable the TIM Capture/Compare 3 DMA request */
01616       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01617       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01618       break;
01619     }
01620
01621     case TIM_CHANNEL_4:
01622     {
01623       /* Disable the TIM Capture/Compare 4 DMA request */
01624       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01625       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01626       break;
01627     }
01628
01629     default:
01630       status = HAL_ERROR;
01631       break;
01632   }
01633
01634   if (status == HAL_OK)
01635   {
01636     /* Disable the complementary PWM output */
01637     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01638
01639     /* Disable the Main Output */
01640     __HAL_TIM_MOE_DISABLE(htim);
01641
01642     /* Disable the Peripheral */
01643     __HAL_TIM_DISABLE(htim);
01644
01645     /* Set the TIM complementary channel state */
01646     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01647   }
01648
01649   /* Return function status */
01650   return status;
01651 }
01652
01653 /**
01654   * @}
01655   */
01656
01657 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01658   * @brief    Timer Complementary One Pulse functions
01659   *
01660 @verbatim
01661   ==============================================================================
01662                 ##### Timer Complementary One Pulse functions #####
01663   ==============================================================================
01664   [..]
01665     This section provides functions allowing to:
01666     (+) Start the Complementary One Pulse generation.
01667     (+) Stop the Complementary One Pulse.
01668     (+) Start the Complementary One Pulse and enable interrupts.
01669     (+) Stop the Complementary One Pulse and disable interrupts.
01670
01671 @endverbatim
01672   * @{
01673   */
01674
01675 /**
01676   * @brief  Starts the TIM One Pulse signal generation on the complementary
01677   *         output.
01678   * @note OutputChannel must match the pulse output channel chosen when calling
01679   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01680   * @param  htim TIM One Pulse handle
01681   * @param  OutputChannel pulse output channel to enable
01682   *          This parameter can be one of the following values:
01683   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01684   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01685   * @retval HAL status
01686   */
01687 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01688 {
01689   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01690   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
01691   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
01692   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
01693   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
01694
01695   /* Check the parameters */
01696   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01697
01698   /* Check the TIM channels state */
01699   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01700       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
01701       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01702       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
01703   {
01704     return HAL_ERROR;
01705   }
01706
01707   /* Set the TIM channels state */
01708   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01709   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01710   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01711   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01712
01713   /* Enable the complementary One Pulse output channel and the Input Capture channel */
01714   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01715   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
01716
01717   /* Enable the Main Output */
01718   __HAL_TIM_MOE_ENABLE(htim);
01719
01720   /* Return function status */
01721   return HAL_OK;
01722 }
01723
01724 /**
01725   * @brief  Stops the TIM One Pulse signal generation on the complementary
01726   *         output.
01727   * @note OutputChannel must match the pulse output channel chosen when calling
01728   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01729   * @param  htim TIM One Pulse handle
01730   * @param  OutputChannel pulse output channel to disable
01731   *          This parameter can be one of the following values:
01732   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01733   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01734   * @retval HAL status
01735   */
01736 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01737 {
01738   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01739
01740   /* Check the parameters */
01741   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01742
01743   /* Disable the complementary One Pulse output channel and the Input Capture channel */
01744   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01745   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
01746
01747   /* Disable the Main Output */
01748   __HAL_TIM_MOE_DISABLE(htim);
01749
01750   /* Disable the Peripheral */
01751   __HAL_TIM_DISABLE(htim);
01752
01753   /* Set the TIM  channels state */
01754   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01755   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01756   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01757   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01758
01759   /* Return function status */
01760   return HAL_OK;
01761 }
01762
01763 /**
01764   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01765   *         complementary channel.
01766   * @note OutputChannel must match the pulse output channel chosen when calling
01767   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01768   * @param  htim TIM One Pulse handle
01769   * @param  OutputChannel pulse output channel to enable
01770   *          This parameter can be one of the following values:
01771   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01772   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01773   * @retval HAL status
01774   */
01775 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01776 {
01777   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01778   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
01779   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
01780   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
01781   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
01782
01783   /* Check the parameters */
01784   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01785
01786   /* Check the TIM channels state */
01787   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01788       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
01789       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01790       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
01791   {
01792     return HAL_ERROR;
01793   }
01794
01795   /* Set the TIM channels state */
01796   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01797   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01798   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01799   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01800
01801   /* Enable the TIM Capture/Compare 1 interrupt */
01802   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01803
01804   /* Enable the TIM Capture/Compare 2 interrupt */
01805   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01806
01807   /* Enable the complementary One Pulse output channel and the Input Capture channel */
01808   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01809   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
01810
01811   /* Enable the Main Output */
01812   __HAL_TIM_MOE_ENABLE(htim);
01813
01814   /* Return function status */
01815   return HAL_OK;
01816 }
01817
01818 /**
01819   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01820   *         complementary channel.
01821   * @note OutputChannel must match the pulse output channel chosen when calling
01822   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01823   * @param  htim TIM One Pulse handle
01824   * @param  OutputChannel pulse output channel to disable
01825   *          This parameter can be one of the following values:
01826   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01827   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01828   * @retval HAL status
01829   */
01830 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01831 {
01832   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01833
01834   /* Check the parameters */
01835   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01836
01837   /* Disable the TIM Capture/Compare 1 interrupt */
01838   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01839
01840   /* Disable the TIM Capture/Compare 2 interrupt */
01841   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01842
01843   /* Disable the complementary One Pulse output channel and the Input Capture channel */
01844   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01845   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
01846
01847   /* Disable the Main Output */
01848   __HAL_TIM_MOE_DISABLE(htim);
01849
01850   /* Disable the Peripheral */
01851   __HAL_TIM_DISABLE(htim);
01852
01853   /* Set the TIM  channels state */
01854   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01855   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01856   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01857   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01858
01859   /* Return function status */
01860   return HAL_OK;
01861 }
01862
01863 /**
01864   * @}
01865   */
01866
01867 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01868   * @brief    Peripheral Control functions
01869   *
01870 @verbatim
01871   ==============================================================================
01872                     ##### Peripheral Control functions #####
01873   ==============================================================================
01874   [..]
01875     This section provides functions allowing to:
01876       (+) Configure the commutation event in case of use of the Hall sensor interface.
01877       (+) Configure Output channels for OC and PWM mode.
01878
01879       (+) Configure Complementary channels, break features and dead time.
01880       (+) Configure Master synchronization.
01881       (+) Configure timer remapping capabilities.
01882       (+) Select timer input source.
01883       (+) Enable or disable channel grouping.
01884       (+) Configure Pulse on compare.
01885       (+) Configure Encoder index.
01886
01887 @endverbatim
01888   * @{
01889   */
01890
01891 /**
01892   * @brief  Configure the TIM commutation event sequence.
01893   * @note  This function is mandatory to use the commutation event in order to
01894   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01895   *        the typical use of this feature is with the use of another Timer(interface Timer)
01896   *        configured in Hall sensor interface, this interface Timer will generate the
01897   *        commutation at its TRGO output (connected to Timer used in this function) each time
01898   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01899   * @param  htim TIM handle
01900   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01901   *          This parameter can be one of the following values:
01902   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01903   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01904   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01905   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01906   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
01907   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
01908   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
01909   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
01910   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
01911   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
01912   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
01913   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
01914   *            @arg TIM_TS_NONE: No trigger is needed
01915   *
01916   *         (*)  Value not defined in all devices.
01917   *
01918   * @param  CommutationSource the Commutation Event source
01919   *          This parameter can be one of the following values:
01920   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01921   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01922   * @retval HAL status
01923   */
01924 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01925                                               uint32_t  CommutationSource)
01926 {
01927   /* Check the parameters */
01928   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01929   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
01930
01931   __HAL_LOCK(htim);
01932
01933 #if defined(TIM5) && defined(TIM20)
01934   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01935       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01936       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
01937       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
01938       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
01939       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
01940 #elif defined(TIM5)
01941   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01942       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01943       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
01944       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
01945       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
01946 #elif defined(TIM20)
01947   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01948       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01949       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
01950       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
01951       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
01952 #else
01953   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
01954       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
01955       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
01956       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
01957       (InputTrigger == TIM_TS_ITR11))
01958 #endif /* TIM5 && TIM20 */
01959   {
01960     /* Select the Input trigger */
01961     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01962     htim->Instance->SMCR |= InputTrigger;
01963   }
01964
01965   /* Select the Capture Compare preload feature */
01966   htim->Instance->CR2 |= TIM_CR2_CCPC;
01967   /* Select the Commutation event source */
01968   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01969   htim->Instance->CR2 |= CommutationSource;
01970
01971   /* Disable Commutation Interrupt */
01972   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01973
01974   /* Disable Commutation DMA request */
01975   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01976
01977   __HAL_UNLOCK(htim);
01978
01979   return HAL_OK;
01980 }
01981
01982 /**
01983   * @brief  Configure the TIM commutation event sequence with interrupt.
01984   * @note  This function is mandatory to use the commutation event in order to
01985   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01986   *        the typical use of this feature is with the use of another Timer(interface Timer)
01987   *        configured in Hall sensor interface, this interface Timer will generate the
01988   *        commutation at its TRGO output (connected to Timer used in this function) each time
01989   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01990   * @param  htim TIM handle
01991   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01992   *          This parameter can be one of the following values:
01993   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01994   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01995   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01996   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01997   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
01998   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
01999   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
02000   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
02001   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
02002   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
02003   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
02004   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
02005   *            @arg TIM_TS_NONE: No trigger is needed
02006   *
02007   *         (*)  Value not defined in all devices.
02008   *
02009   * @param  CommutationSource the Commutation Event source
02010   *          This parameter can be one of the following values:
02011   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
02012   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
02013   * @retval HAL status
02014   */
02015 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
02016                                                  uint32_t  CommutationSource)
02017 {
02018   /* Check the parameters */
02019   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
02020   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
02021
02022   __HAL_LOCK(htim);
02023
02024 #if defined(TIM5) && defined(TIM20)
02025   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02026       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02027       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
02028       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
02029       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
02030       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
02031 #elif defined(TIM5)
02032   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02033       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02034       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
02035       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
02036       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
02037 #elif defined(TIM20)
02038   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02039       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02040       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
02041       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
02042       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
02043 #else
02044   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02045       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02046       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
02047       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
02048       (InputTrigger == TIM_TS_ITR11))
02049 #endif /* TIM5 && TIM20 */
02050   {
02051     /* Select the Input trigger */
02052     htim->Instance->SMCR &= ~TIM_SMCR_TS;
02053     htim->Instance->SMCR |= InputTrigger;
02054   }
02055
02056   /* Select the Capture Compare preload feature */
02057   htim->Instance->CR2 |= TIM_CR2_CCPC;
02058   /* Select the Commutation event source */
02059   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
02060   htim->Instance->CR2 |= CommutationSource;
02061
02062   /* Disable Commutation DMA request */
02063   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
02064
02065   /* Enable the Commutation Interrupt */
02066   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
02067
02068   __HAL_UNLOCK(htim);
02069
02070   return HAL_OK;
02071 }
02072
02073 /**
02074   * @brief  Configure the TIM commutation event sequence with DMA.
02075   * @note  This function is mandatory to use the commutation event in order to
02076   *        update the configuration at each commutation detection on the TRGI input of the Timer,
02077   *        the typical use of this feature is with the use of another Timer(interface Timer)
02078   *        configured in Hall sensor interface, this interface Timer will generate the
02079   *        commutation at its TRGO output (connected to Timer used in this function) each time
02080   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
02081   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
02082   * @param  htim TIM handle
02083   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
02084   *          This parameter can be one of the following values:
02085   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
02086   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
02087   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
02088   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
02089   *            @arg TIM_TS_ITR4: Internal trigger 4 selected   (*)
02090   *            @arg TIM_TS_ITR5: Internal trigger 5 selected
02091   *            @arg TIM_TS_ITR6: Internal trigger 6 selected
02092   *            @arg TIM_TS_ITR7: Internal trigger 7 selected
02093   *            @arg TIM_TS_ITR8: Internal trigger 8 selected
02094   *            @arg TIM_TS_ITR9: Internal trigger 9 selected   (*)
02095   *            @arg TIM_TS_ITR10: Internal trigger 10 selected
02096   *            @arg TIM_TS_ITR11: Internal trigger 11 selected
02097   *            @arg TIM_TS_NONE: No trigger is needed
02098   *
02099   *         (*)  Value not defined in all devices.
02100   *
02101   * @param  CommutationSource the Commutation Event source
02102   *          This parameter can be one of the following values:
02103   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
02104   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
02105   * @retval HAL status
02106   */
02107 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
02108                                                   uint32_t  CommutationSource)
02109 {
02110   /* Check the parameters */
02111   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
02112   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
02113
02114   __HAL_LOCK(htim);
02115
02116 #if defined(TIM5) && defined(TIM20)
02117   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02118       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02119       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
02120       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
02121       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR9) ||
02122       (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
02123 #elif defined(TIM5)
02124   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02125       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02126       (InputTrigger == TIM_TS_ITR4)  || (InputTrigger == TIM_TS_ITR5) ||
02127       (InputTrigger == TIM_TS_ITR6)  || (InputTrigger == TIM_TS_ITR7) ||
02128       (InputTrigger == TIM_TS_ITR8)  || (InputTrigger == TIM_TS_ITR11))
02129 #elif defined(TIM20)
02130   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02131       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02132       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
02133       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
02134       (InputTrigger == TIM_TS_ITR9)  || (InputTrigger == TIM_TS_ITR11))
02135 #else
02136   if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
02137       (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
02138       (InputTrigger == TIM_TS_ITR5)  || (InputTrigger == TIM_TS_ITR6) ||
02139       (InputTrigger == TIM_TS_ITR7)  || (InputTrigger == TIM_TS_ITR8) ||
02140       (InputTrigger == TIM_TS_ITR11))
02141 #endif /* TIM5 && TIM20 */
02142   {
02143     /* Select the Input trigger */
02144     htim->Instance->SMCR &= ~TIM_SMCR_TS;
02145     htim->Instance->SMCR |= InputTrigger;
02146   }
02147
02148   /* Select the Capture Compare preload feature */
02149   htim->Instance->CR2 |= TIM_CR2_CCPC;
02150   /* Select the Commutation event source */
02151   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
02152   htim->Instance->CR2 |= CommutationSource;
02153
02154   /* Enable the Commutation DMA Request */
02155   /* Set the DMA Commutation Callback */
02156   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
02157   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
02158   /* Set the DMA error callback */
02159   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
02160
02161   /* Disable Commutation Interrupt */
02162   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
02163
02164   /* Enable the Commutation DMA Request */
02165   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
02166
02167   __HAL_UNLOCK(htim);
02168
02169   return HAL_OK;
02170 }
02171
02172 /**
02173   * @brief  Configures the TIM in master mode.
02174   * @param  htim TIM handle.
02175   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
02176   *         contains the selected trigger output (TRGO) and the Master/Slave
02177   *         mode.
02178   * @retval HAL status
02179   */
02180 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
02181                                                         const TIM_MasterConfigTypeDef *sMasterConfig)
02182 {
02183   uint32_t tmpcr2;
02184   uint32_t tmpsmcr;
02185
02186   /* Check the parameters */
02187   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
02188   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
02189   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
02190
02191   /* Check input state */
02192   __HAL_LOCK(htim);
02193
02194   /* Change the handler state */
02195   htim->State = HAL_TIM_STATE_BUSY;
02196
02197   /* Get the TIMx CR2 register value */
02198   tmpcr2 = htim->Instance->CR2;
02199
02200   /* Get the TIMx SMCR register value */
02201   tmpsmcr = htim->Instance->SMCR;
02202
02203   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
02204   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
02205   {
02206     /* Check the parameters */
02207     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
02208
02209     /* Clear the MMS2 bits */
02210     tmpcr2 &= ~TIM_CR2_MMS2;
02211     /* Select the TRGO2 source*/
02212     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
02213   }
02214
02215   /* Reset the MMS Bits */
02216   tmpcr2 &= ~TIM_CR2_MMS;
02217   /* Select the TRGO source */
02218   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
02219
02220   /* Update TIMx CR2 */
02221   htim->Instance->CR2 = tmpcr2;
02222
02223   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02224   {
02225     /* Reset the MSM Bit */
02226     tmpsmcr &= ~TIM_SMCR_MSM;
02227     /* Set master mode */
02228     tmpsmcr |= sMasterConfig->MasterSlaveMode;
02229
02230     /* Update TIMx SMCR */
02231     htim->Instance->SMCR = tmpsmcr;
02232   }
02233
02234   /* Change the htim state */
02235   htim->State = HAL_TIM_STATE_READY;
02236
02237   __HAL_UNLOCK(htim);
02238
02239   return HAL_OK;
02240 }
02241
02242 /**
02243   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
02244   *         and the AOE(automatic output enable).
02245   * @param  htim TIM handle
02246   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
02247   *         contains the BDTR Register configuration  information for the TIM peripheral.
02248   * @note   Interrupts can be generated when an active level is detected on the
02249   *         break input, the break 2 input or the system break input. Break
02250   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
02251   * @retval HAL status
02252   */
02253 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02254                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
02255 {
02256   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
02257   uint32_t tmpbdtr = 0U;
02258
02259   /* Check the parameters */
02260   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02261   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
02262   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
02263   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
02264   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
02265   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
02266   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
02267   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
02268   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
02269   assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
02270
02271   /* Check input state */
02272   __HAL_LOCK(htim);
02273
02274   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02275      the OSSI State, the dead time value and the Automatic Output Enable Bit */
02276
02277   /* Set the BDTR bits */
02278   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
02279   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
02280   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
02281   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
02282   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
02283   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
02284   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
02285   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
02286   MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
02287
02288   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
02289   {
02290     /* Check the parameters */
02291     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
02292     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
02293     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
02294     assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
02295
02296     /* Set the BREAK2 input related BDTR bits */
02297     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
02298     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
02299     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
02300     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
02301   }
02302
02303   /* Set TIMx_BDTR */
02304   htim->Instance->BDTR = tmpbdtr;
02305
02306   __HAL_UNLOCK(htim);
02307
02308   return HAL_OK;
02309 }
02310
02311 /**
02312   * @brief  Configures the break input source.
02313   * @param  htim TIM handle.
02314   * @param  BreakInput Break input to configure
02315   *          This parameter can be one of the following values:
02316   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02317   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02318   * @param  sBreakInputConfig Break input source configuration
02319   * @retval HAL status
02320   */
02321 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
02322                                              uint32_t BreakInput,
02323                                              const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
02324 {
02325   HAL_StatusTypeDef status = HAL_OK;
02326   uint32_t tmporx;
02327   uint32_t bkin_enable_mask;
02328   uint32_t bkin_polarity_mask;
02329   uint32_t bkin_enable_bitpos;
02330   uint32_t bkin_polarity_bitpos;
02331
02332   /* Check the parameters */
02333   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02334   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02335   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
02336   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
02337   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
02338
02339   /* Check input state */
02340   __HAL_LOCK(htim);
02341
02342   switch (sBreakInputConfig->Source)
02343   {
02344     case TIM_BREAKINPUTSOURCE_BKIN:
02345     {
02346       bkin_enable_mask = TIM1_AF1_BKINE;
02347       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
02348       bkin_polarity_mask = TIM1_AF1_BKINP;
02349       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
02350       break;
02351     }
02352     case TIM_BREAKINPUTSOURCE_COMP1:
02353     {
02354       bkin_enable_mask = TIM1_AF1_BKCMP1E;
02355       bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
02356       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
02357       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
02358       break;
02359     }
02360     case TIM_BREAKINPUTSOURCE_COMP2:
02361     {
02362       bkin_enable_mask = TIM1_AF1_BKCMP2E;
02363       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
02364       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
02365       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
02366       break;
02367     }
02368     case TIM_BREAKINPUTSOURCE_COMP3:
02369     {
02370       bkin_enable_mask = TIM1_AF1_BKCMP3E;
02371       bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
02372       bkin_polarity_mask = TIM1_AF1_BKCMP3P;
02373       bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
02374       break;
02375     }
02376     case TIM_BREAKINPUTSOURCE_COMP4:
02377     {
02378       bkin_enable_mask = TIM1_AF1_BKCMP4E;
02379       bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
02380       bkin_polarity_mask = TIM1_AF1_BKCMP4P;
02381       bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
02382       break;
02383     }
02384 #if defined (COMP5)
02385     case TIM_BREAKINPUTSOURCE_COMP5:
02386     {
02387       bkin_enable_mask = TIM1_AF1_BKCMP5E;
02388       bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
02389       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
02390       bkin_polarity_mask = 0U;
02391       bkin_polarity_bitpos = 0U;
02392       break;
02393     }
02394 #endif /* COMP5 */
02395 #if defined (COMP6)
02396     case TIM_BREAKINPUTSOURCE_COMP6:
02397     {
02398       bkin_enable_mask = TIM1_AF1_BKCMP6E;
02399       bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
02400       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
02401       bkin_polarity_mask = 0U;
02402       bkin_polarity_bitpos = 0U;
02403       break;
02404     }
02405 #endif /* COMP7 */
02406 #if defined (COMP7)
02407     case TIM_BREAKINPUTSOURCE_COMP7:
02408     {
02409       bkin_enable_mask = TIM1_AF1_BKCMP7E;
02410       bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
02411       /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
02412       bkin_polarity_mask = 0U;
02413       bkin_polarity_bitpos = 0U;
02414       break;
02415     }
02416 #endif /* COMP7 */
02417
02418     default:
02419     {
02420       bkin_enable_mask = 0U;
02421       bkin_polarity_mask = 0U;
02422       bkin_enable_bitpos = 0U;
02423       bkin_polarity_bitpos = 0U;
02424       break;
02425     }
02426   }
02427
02428   switch (BreakInput)
02429   {
02430     case TIM_BREAKINPUT_BRK:
02431     {
02432       /* Get the TIMx_AF1 register value */
02433       tmporx = htim->Instance->AF1;
02434
02435       /* Enable the break input */
02436       tmporx &= ~bkin_enable_mask;
02437       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
02438
02439       /* Set the break input polarity */
02440       tmporx &= ~bkin_polarity_mask;
02441       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
02442
02443       /* Set TIMx_AF1 */
02444       htim->Instance->AF1 = tmporx;
02445       break;
02446     }
02447     case TIM_BREAKINPUT_BRK2:
02448     {
02449       /* Get the TIMx_AF2 register value */
02450       tmporx = htim->Instance->AF2;
02451
02452       /* Enable the break input */
02453       tmporx &= ~bkin_enable_mask;
02454       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
02455
02456       /* Set the break input polarity */
02457       tmporx &= ~bkin_polarity_mask;
02458       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
02459
02460       /* Set TIMx_AF2 */
02461       htim->Instance->AF2 = tmporx;
02462       break;
02463     }
02464     default:
02465       status = HAL_ERROR;
02466       break;
02467   }
02468
02469   __HAL_UNLOCK(htim);
02470
02471   return status;
02472 }
02473
02474 /**
02475   * @brief  Configures the TIMx Remapping input capabilities.
02476   * @param  htim TIM handle.
02477   * @param  Remap specifies the TIM remapping source.
02478   *         For TIM1, the parameter can take one of the following values:
02479   *            @arg TIM_TIM1_ETR_GPIO           TIM1 ETR is connected to GPIO
02480   *            @arg TIM_TIM1_ETR_COMP1          TIM1 ETR is connected to COMP1 output
02481   *            @arg TIM_TIM1_ETR_COMP2          TIM1 ETR is connected to COMP2 output
02482   *            @arg TIM_TIM1_ETR_COMP3          TIM1 ETR is connected to COMP3 output
02483   *            @arg TIM_TIM1_ETR_COMP4          TIM1 ETR is connected to COMP4 output
02484   *            @arg TIM_TIM1_ETR_COMP5          TIM1 ETR is connected to COMP5 output    (*)
02485   *            @arg TIM_TIM1_ETR_COMP6          TIM1 ETR is connected to COMP6 output    (*)
02486   *            @arg TIM_TIM1_ETR_COMP7          TIM1 ETR is connected to COMP7 output    (*)
02487   *            @arg TIM_TIM1_ETR_ADC1_AWD1      TIM1 ETR is connected to ADC1 AWD1
02488   *            @arg TIM_TIM1_ETR_ADC1_AWD2      TIM1 ETR is connected to ADC1 AWD2
02489   *            @arg TIM_TIM1_ETR_ADC1_AWD3      TIM1 ETR is connected to ADC1 AWD3
02490   *            @arg TIM_TIM1_ETR_ADC4_AWD1      TIM1 ETR is connected to ADC4 AWD1       (*)
02491   *            @arg TIM_TIM1_ETR_ADC4_AWD2      TIM1 ETR is connected to ADC4 AWD2       (*)
02492   *            @arg TIM_TIM1_ETR_ADC4_AWD3      TIM1 ETR is connected to ADC4 AWD3       (*)
02493   *
02494   *         For TIM2, the parameter can take one of the following values:
02495   *            @arg TIM_TIM2_ETR_GPIO           TIM2 ETR is connected to GPIO
02496   *            @arg TIM_TIM2_ETR_COMP1          TIM2 ETR is connected to COMP1 output
02497   *            @arg TIM_TIM2_ETR_COMP2          TIM2 ETR is connected to COMP2 output
02498   *            @arg TIM_TIM2_ETR_COMP3          TIM2 ETR is connected to COMP3 output
02499   *            @arg TIM_TIM2_ETR_COMP4          TIM2 ETR is connected to COMP4 output
02500   *            @arg TIM_TIM2_ETR_COMP5          TIM2 ETR is connected to COMP5 output    (*)
02501   *            @arg TIM_TIM2_ETR_COMP6          TIM2 ETR is connected to COMP6 output    (*)
02502   *            @arg TIM_TIM2_ETR_COMP7          TIM2 ETR is connected to COMP7 output    (*)
02503   *            @arg TIM_TIM2_ETR_TIM3_ETR       TIM2 ETR is connected to TIM3 ETR pin
02504   *            @arg TIM_TIM2_ETR_TIM4_ETR       TIM2 ETR is connected to TIM4 ETR pin
02505   *            @arg TIM_TIM2_ETR_TIM5_ETR       TIM2 ETR is connected to TIM5 ETR pin    (*)
02506   *            @arg TIM_TIM2_ETR_LSE
02507   *
02508   *         For TIM3, the parameter can take one of the following values:
02509   *            @arg TIM_TIM3_ETR_GPIO           TIM3 ETR is connected to GPIO
02510   *            @arg TIM_TIM3_ETR_COMP1          TIM3 ETR is connected to COMP1 output
02511   *            @arg TIM_TIM3_ETR_COMP2          TIM3 ETR is connected to COMP2 output
02512   *            @arg TIM_TIM3_ETR_COMP3          TIM3 ETR is connected to COMP3 output
02513   *            @arg TIM_TIM3_ETR_COMP4          TIM3 ETR is connected to COMP4 output
02514   *            @arg TIM_TIM3_ETR_COMP5          TIM3 ETR is connected to COMP5 output    (*)
02515   *            @arg TIM_TIM3_ETR_COMP6          TIM3 ETR is connected to COMP6 output    (*)
02516   *            @arg TIM_TIM3_ETR_COMP7          TIM3 ETR is connected to COMP7 output    (*)
02517   *            @arg TIM_TIM3_ETR_TIM2_ETR       TIM3 ETR is connected to TIM2 ETR pin
02518   *            @arg TIM_TIM3_ETR_TIM4_ETR       TIM3 ETR is connected to TIM4 ETR pin
02519   *            @arg TIM_TIM3_ETR_ADC2_AWD1      TIM3 ETR is connected to ADC2 AWD1
02520   *            @arg TIM_TIM3_ETR_ADC2_AWD2      TIM3 ETR is connected to ADC2 AWD2
02521   *            @arg TIM_TIM3_ETR_ADC2_AWD3      TIM3 ETR is connected to ADC2 AWD3
02522   *
02523   *         For TIM4, the parameter can take one of the following values:
02524   *            @arg TIM_TIM4_ETR_GPIO           TIM4 ETR is connected to GPIO
02525   *            @arg TIM_TIM4_ETR_COMP1          TIM4 ETR is connected to COMP1 output
02526   *            @arg TIM_TIM4_ETR_COMP2          TIM4 ETR is connected to COMP2 output
02527   *            @arg TIM_TIM4_ETR_COMP3          TIM4 ETR is connected to COMP3 output
02528   *            @arg TIM_TIM4_ETR_COMP4          TIM4 ETR is connected to COMP4 output
02529   *            @arg TIM_TIM4_ETR_COMP5          TIM4 ETR is connected to COMP5 output    (*)
02530   *            @arg TIM_TIM4_ETR_COMP6          TIM4 ETR is connected to COMP6 output    (*)
02531   *            @arg TIM_TIM4_ETR_COMP7          TIM4 ETR is connected to COMP7 output    (*)
02532   *            @arg TIM_TIM4_ETR_TIM3_ETR       TIM4 ETR is connected to TIM3 ETR pin
02533   *            @arg TIM_TIM4_ETR_TIM5_ETR       TIM4 ETR is connected to TIM5 ETR pin    (*)
02534   *
02535   *         For TIM5, the parameter can take one of the following values:       (**)
02536   *            @arg TIM_TIM5_ETR_GPIO           TIM5 ETR is connected to GPIO            (*)
02537   *            @arg TIM_TIM5_ETR_COMP1          TIM5 ETR is connected to COMP1 output    (*)
02538   *            @arg TIM_TIM5_ETR_COMP2          TIM5 ETR is connected to COMP2 output    (*)
02539   *            @arg TIM_TIM5_ETR_COMP3          TIM5 ETR is connected to COMP3 output    (*)
02540   *            @arg TIM_TIM5_ETR_COMP4          TIM5 ETR is connected to COMP4 output    (*)
02541   *            @arg TIM_TIM5_ETR_COMP5          TIM5 ETR is connected to COMP5 output    (*)
02542   *            @arg TIM_TIM5_ETR_COMP6          TIM5 ETR is connected to COMP6 output    (*)
02543   *            @arg TIM_TIM5_ETR_COMP7          TIM5 ETR is connected to COMP7 output    (*)
02544   *            @arg TIM_TIM5_ETR_TIM2_ETR       TIM5 ETR is connected to TIM2 ETR pin    (*)
02545   *            @arg TIM_TIM5_ETR_TIM3_ETR       TIM5 ETR is connected to TIM3 ETR pin    (*)
02546   *
02547   *         For TIM8, the parameter can take one of the following values:
02548   *            @arg TIM_TIM8_ETR_GPIO            TIM8 ETR is connected to GPIO
02549   *            @arg TIM_TIM8_ETR_COMP1           TIM8 ETR is connected to COMP1 output
02550   *            @arg TIM_TIM8_ETR_COMP2           TIM8 ETR is connected to COMP2 output
02551   *            @arg TIM_TIM8_ETR_COMP3           TIM8 ETR is connected to COMP3 output
02552   *            @arg TIM_TIM8_ETR_COMP4           TIM8 ETR is connected to COMP4 output
02553   *            @arg TIM_TIM8_ETR_COMP5           TIM8 ETR is connected to COMP5 output    (*)
02554   *            @arg TIM_TIM8_ETR_COMP6           TIM8 ETR is connected to COMP6 output    (*)
02555   *            @arg TIM_TIM8_ETR_COMP7           TIM8 ETR is connected to COMP7 output    (*)
02556   *            @arg TIM_TIM8_ETR_ADC2_AWD1       TIM8 ETR is connected to ADC2 AWD1
02557   *            @arg TIM_TIM8_ETR_ADC2_AWD2       TIM8 ETR is connected to ADC2 AWD2
02558   *            @arg TIM_TIM8_ETR_ADC2_AWD3       TIM8 ETR is connected to ADC2 AWD3
02559   *            @arg TIM_TIM8_ETR_ADC3_AWD1       TIM8 ETR is connected to ADC3 AWD1       (*)
02560   *            @arg TIM_TIM8_ETR_ADC3_AWD2       TIM8 ETR is connected to ADC3 AWD2       (*)
02561   *            @arg TIM_TIM8_ETR_ADC3_AWD3       TIM8 ETR is connected to ADC3 AWD3       (*)
02562   *
02563   *         For TIM20, the parameter can take one of the following values:       (**)
02564   *            @arg TIM_TIM20_ETR_GPIO            TIM20 ETR is connected to GPIO
02565   *            @arg TIM_TIM20_ETR_COMP1           TIM20 ETR is connected to COMP1 output  (*)
02566   *            @arg TIM_TIM20_ETR_COMP2           TIM20 ETR is connected to COMP2 output  (*)
02567   *            @arg TIM_TIM20_ETR_COMP3           TIM20 ETR is connected to COMP3 output  (*)
02568   *            @arg TIM_TIM20_ETR_COMP4           TIM20 ETR is connected to COMP4 output  (*)
02569   *            @arg TIM_TIM20_ETR_COMP5           TIM20 ETR is connected to COMP5 output  (*)
02570   *            @arg TIM_TIM20_ETR_COMP6           TIM20 ETR is connected to COMP6 output  (*)
02571   *            @arg TIM_TIM20_ETR_COMP7           TIM20 ETR is connected to COMP7 output  (*)
02572   *            @arg TIM_TIM20_ETR_ADC3_AWD1       TIM20 ETR is connected to ADC3 AWD1     (*)
02573   *            @arg TIM_TIM20_ETR_ADC3_AWD2       TIM20 ETR is connected to ADC3 AWD2     (*)
02574   *            @arg TIM_TIM20_ETR_ADC3_AWD3       TIM20 ETR is connected to ADC3 AWD3     (*)
02575   *            @arg TIM_TIM20_ETR_ADC5_AWD1       TIM20 ETR is connected to ADC5 AWD1     (*)
02576   *            @arg TIM_TIM20_ETR_ADC5_AWD2       TIM20 ETR is connected to ADC5 AWD2     (*)
02577   *            @arg TIM_TIM20_ETR_ADC5_AWD3       TIM20 ETR is connected to ADC5 AWD3     (*)
02578   *
02579   *         (*)  Value not defined in all devices. \n
02580   *         (**) Register not available in all devices.
02581   *
02582   * @retval HAL status
02583   */
02584 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02585 {
02586   /* Check parameters */
02587   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02588   assert_param(IS_TIM_REMAP(Remap));
02589
02590   __HAL_LOCK(htim);
02591
02592   MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
02593
02594   __HAL_UNLOCK(htim);
02595
02596   return HAL_OK;
02597 }
02598
02599 /**
02600   * @brief  Select the timer input source
02601   * @param  htim TIM handle.
02602   * @param  Channel specifies the TIM Channel
02603   *          This parameter can be one of the following values:
02604   *            @arg TIM_CHANNEL_1: TI1 input channel
02605   *            @arg TIM_CHANNEL_2: TI2 input channel
02606   *            @arg TIM_CHANNEL_3: TI3 input channel
02607   *            @arg TIM_CHANNEL_4: TI4 input channel
02608   * @param  TISelection specifies the timer input source
02609   *         For TIM1 this parameter can be one of the following values:
02610   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
02611   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
02612   *            @arg TIM_TIM1_TI1_COMP2:               TIM1 TI1 is connected to COMP2 output
02613   *            @arg TIM_TIM1_TI1_COMP3:               TIM1 TI1 is connected to COMP3 output
02614   *            @arg TIM_TIM1_TI1_COMP4:               TIM1 TI1 is connected to COMP4 output
02615   *
02616   *         For TIM2 this parameter can be one of the following values:
02617   *            @arg TIM_TIM2_TI1_GPIO:                TIM2 TI1 is connected to GPIO
02618   *            @arg TIM_TIM2_TI1_COMP1:               TIM2 TI1 is connected to COMP1 output
02619   *            @arg TIM_TIM2_TI1_COMP2:               TIM2 TI1 is connected to COMP2 output
02620   *            @arg TIM_TIM2_TI1_COMP3:               TIM2 TI1 is connected to COMP3 output
02621   *            @arg TIM_TIM2_TI1_COMP4:               TIM2 TI1 is connected to COMP4 output
02622   *            @arg TIM_TIM2_TI1_COMP5:               TIM2 TI1 is connected to COMP5 output     (*)
02623   *
02624   *            @arg TIM_TIM2_TI2_GPIO:                TIM1 TI2 is connected to GPIO
02625   *            @arg TIM_TIM2_TI2_COMP1:               TIM2 TI2 is connected to COMP1 output
02626   *            @arg TIM_TIM2_TI2_COMP2:               TIM2 TI2 is connected to COMP2 output
02627   *            @arg TIM_TIM2_TI2_COMP3:               TIM2 TI2 is connected to COMP3 output
02628   *            @arg TIM_TIM2_TI2_COMP4:               TIM2 TI2 is connected to COMP4 output
02629   *            @arg TIM_TIM2_TI2_COMP6:               TIM2 TI2 is connected to COMP6 output     (*)
02630   *
02631   *            @arg TIM_TIM2_TI3_GPIO:                TIM2 TI3 is connected to GPIO
02632   *            @arg TIM_TIM2_TI3_COMP4:               TIM2 TI3 is connected to COMP4 output
02633   *
02634   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
02635   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
02636   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
02637   *
02638   *         For TIM3 this parameter can be one of the following values:
02639   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
02640   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
02641   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
02642   *            @arg TIM_TIM3_TI1_COMP3:               TIM3 TI1 is connected to COMP3 output
02643   *            @arg TIM_TIM3_TI1_COMP4:               TIM3 TI1 is connected to COMP4 output
02644   *            @arg TIM_TIM3_TI1_COMP5:               TIM3 TI1 is connected to COMP5 output     (*)
02645   *            @arg TIM_TIM3_TI1_COMP6:               TIM3 TI1 is connected to COMP6 output     (*)
02646   *            @arg TIM_TIM3_TI1_COMP7:               TIM3 TI1 is connected to COMP7 output     (*)
02647   *
02648   *            @arg TIM_TIM3_TI2_GPIO:                TIM3 TI2 is connected to GPIO
02649   *            @arg TIM_TIM3_TI2_COMP1:               TIM3 TI2 is connected to COMP1 output
02650   *            @arg TIM_TIM3_TI2_COMP2:               TIM3 TI2 is connected to COMP2 output
02651   *            @arg TIM_TIM3_TI2_COMP3:               TIM3 TI2 is connected to COMP3 output
02652   *            @arg TIM_TIM3_TI2_COMP4:               TIM3 TI2 is connected to COMP4 output
02653   *            @arg TIM_TIM3_TI2_COMP5:               TIM3 TI2 is connected to COMP5 output     (*)
02654   *            @arg TIM_TIM3_TI2_COMP6:               TIM3 TI2 is connected to COMP6 output     (*)
02655   *            @arg TIM_TIM3_TI2_COMP7:               TIM3 TI2 is connected to COMP7 output     (*)
02656   *
02657   *            @arg TIM_TIM3_TI3_GPIO:                TIM3 TI3 is connected to GPIO
02658   *            @arg TIM_TIM3_TI3_COMP3:               TIM3 TI3 is connected to COMP3 output
02659   *
02660   *         For TIM4 this parameter can be one of the following values:
02661   *            @arg TIM_TIM4_TI1_GPIO:                TIM4 TI1 is connected to GPIO
02662   *            @arg TIM_TIM4_TI1_COMP1:               TIM4 TI1 is connected to COMP1 output
02663   *            @arg TIM_TIM4_TI1_COMP2:               TIM4 TI1 is connected to COMP2 output
02664   *            @arg TIM_TIM4_TI1_COMP3:               TIM4 TI1 is connected to COMP3 output
02665   *            @arg TIM_TIM4_TI1_COMP4:               TIM4 TI1 is connected to COMP4 output
02666   *            @arg TIM_TIM4_TI1_COMP5:               TIM4 TI1 is connected to COMP5 output     (*)
02667   *            @arg TIM_TIM4_TI1_COMP6:               TIM4 TI1 is connected to COMP6 output     (*)
02668   *            @arg TIM_TIM4_TI1_COMP7:               TIM4 TI1 is connected to COMP7 output     (*)
02669   *
02670   *            @arg TIM_TIM4_TI2_GPIO:                TIM4 TI2 is connected to GPIO
02671   *            @arg TIM_TIM4_TI2_COMP1:               TIM4 TI2 is connected to COMP1 output
02672   *            @arg TIM_TIM4_TI2_COMP2:               TIM4 TI2 is connected to COMP2 output
02673   *            @arg TIM_TIM4_TI2_COMP3:               TIM4 TI2 is connected to COMP3 output
02674   *            @arg TIM_TIM4_TI2_COMP4:               TIM4 TI2 is connected to COMP4 output
02675   *            @arg TIM_TIM4_TI2_COMP5:               TIM4 TI2 is connected to COMP5 output     (*)
02676   *            @arg TIM_TIM4_TI2_COMP6:               TIM4 TI2 is connected to COMP6 output     (*)
02677   *            @arg TIM_TIM4_TI2_COMP7:               TIM4 TI2 is connected to COMP7 output     (*)
02678   *
02679   *            @arg TIM_TIM4_TI3_GPIO:                TIM4 TI3 is connected to GPIO
02680   *            @arg TIM_TIM4_TI3_COMP5:               TIM4 TI3 is connected to COMP5 output     (*)
02681   *
02682   *            @arg TIM_TIM4_TI4_GPIO:                TIM4 TI4 is connected to GPIO
02683   *            @arg TIM_TIM4_TI4_COMP6:               TIM4 TI4 is connected to COMP6 output     (*)
02684   *
02685   *         For TIM5 this parameter can be one of the following values:    (**)
02686   *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
02687   *            @arg TIM_TIM5_TI1_LSI:                 TIM5 TI1 is connected to LSI clock        (*)
02688   *            @arg TIM_TIM5_TI1_LSE:                 TIM5 TI1 is connected to LSE clock        (*)
02689   *            @arg TIM_TIM5_TI1_RTC_WK:              TIM5 TI1 is connected to RTC Wakeup       (*)
02690   *            @arg TIM_TIM5_TI1_COMP1:               TIM5 TI1 is connected to COMP1 output     (*)
02691   *            @arg TIM_TIM5_TI1_COMP2:               TIM5 TI1 is connected to COMP2 output     (*)
02692   *            @arg TIM_TIM5_TI1_COMP3:               TIM5 TI1 is connected to COMP3 output     (*)
02693   *            @arg TIM_TIM5_TI1_COMP4:               TIM5 TI1 is connected to COMP4 output     (*)
02694   *            @arg TIM_TIM5_TI1_COMP5:               TIM5 TI1 is connected to COMP5 output     (*)
02695   *            @arg TIM_TIM5_TI1_COMP6:               TIM5 TI1 is connected to COMP6 output     (*)
02696   *            @arg TIM_TIM5_TI1_COMP7:               TIM5 TI1 is connected to COMP7 output     (*)
02697   *
02698   *            @arg TIM_TIM5_TI2_GPIO:                TIM5 TI2 is connected to GPIO
02699   *            @arg TIM_TIM5_TI2_COMP1:               TIM5 TI2 is connected to COMP1 output
02700   *            @arg TIM_TIM5_TI2_COMP2:               TIM5 TI2 is connected to COMP2 output
02701   *            @arg TIM_TIM5_TI2_COMP3:               TIM5 TI2 is connected to COMP3 output
02702   *            @arg TIM_TIM5_TI2_COMP4:               TIM5 TI2 is connected to COMP4 output
02703   *            @arg TIM_TIM5_TI2_COMP5:               TIM5 TI2 is connected to COMP5 output     (*)
02704   *            @arg TIM_TIM5_TI2_COMP6:               TIM5 TI2 is connected to COMP6 output     (*)
02705   *            @arg TIM_TIM5_TI2_COMP7:               TIM5 TI2 is connected to COMP7 output     (*)
02706   *
02707   *         For TIM8 this parameter can be one of the following values:
02708   *            @arg TIM_TIM8_TI1_GPIO:                TIM8 TI1 is connected to GPIO
02709   *            @arg TIM_TIM8_TI1_COMP1:               TIM8 TI1 is connected to COMP1 output
02710   *            @arg TIM_TIM8_TI1_COMP2:               TIM8 TI1 is connected to COMP2 output
02711   *            @arg TIM_TIM8_TI1_COMP3:               TIM8 TI1 is connected to COMP3 output
02712   *            @arg TIM_TIM8_TI1_COMP4:               TIM8 TI1 is connected to COMP4 output
02713   *
02714   *         For TIM15 this parameter can be one of the following values:
02715   *            @arg TIM_TIM15_TI1_GPIO:                TIM15 TI1 is connected to GPIO
02716   *            @arg TIM_TIM15_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
02717   *            @arg TIM_TIM15_TI1_COMP1:               TIM15 TI1 is connected to COMP1 output
02718   *            @arg TIM_TIM15_TI1_COMP2:               TIM15 TI1 is connected to COMP2 output
02719   *            @arg TIM_TIM15_TI1_COMP5:               TIM15 TI1 is connected to COMP5 output     (*)
02720   *            @arg TIM_TIM15_TI1_COMP7:               TIM15 TI1 is connected to COMP7 output     (*)
02721   *
02722   *            @arg TIM_TIM15_TI2_GPIO:                TIM15 TI2 is connected to GPIO
02723   *            @arg TIM_TIM15_TI2_COMP2:               TIM15 TI2 is connected to COMP2 output
02724   *            @arg TIM_TIM15_TI2_COMP3:               TIM15 TI2 is connected to COMP3 output
02725   *            @arg TIM_TIM15_TI2_COMP6:               TIM15 TI2 is connected to COMP6 output     (*)
02726   *            @arg TIM_TIM15_TI2_COMP7:               TIM15 TI2 is connected to COMP7 output     (*)
02727   *
02728   *         For TIM16 this parameter can be one of the following values:
02729   *            @arg TIM_TIM16_TI1_GPIO:                TIM16 TI1 is connected to GPIO
02730   *            @arg TIM_TIM16_TI1_COMP6:               TIM16 TI1 is connected to COMP6 output     (*)
02731   *            @arg TIM_TIM16_TI1_MCO:                 TIM15 TI1 is connected to MCO output
02732   *            @arg TIM_TIM16_TI1_HSE_32:              TIM15 TI1 is connected to HSE div 32
02733   *            @arg TIM_TIM16_TI1_RTC_WK:              TIM15 TI1 is connected to RTC wakeup
02734   *            @arg TIM_TIM16_TI1_LSE:                 TIM15 TI1 is connected to LSE clock
02735   *            @arg TIM_TIM16_TI1_LSI:                 TIM15 TI1 is connected to LSI clock
02736   *
02737   *         For TIM17 this parameter can be one of the following values:
02738   *            @arg TIM_TIM17_TI1_GPIO:                TIM17 TI1 is connected to GPIO
02739   *            @arg TIM_TIM17_TI1_COMP5:               TIM17 TI1 is connected to COMP5 output     (*)
02740   *            @arg TIM_TIM17_TI1_MCO:                 TIM17 TI1 is connected to MCO output
02741   *            @arg TIM_TIM17_TI1_HSE_32:              TIM17 TI1 is connected to HSE div 32
02742   *            @arg TIM_TIM17_TI1_RTC_WK:              TIM17 TI1 is connected to RTC wakeup
02743   *            @arg TIM_TIM17_TI1_LSE:                 TIM17 TI1 is connected to LSE clock
02744   *            @arg TIM_TIM17_TI1_LSI:                 TIM17 TI1 is connected to LSI clock
02745
02746   *         For TIM20 this parameter can be one of the following values:    (**)
02747   *            @arg TIM_TIM20_TI1_GPIO:                TIM20 TI1 is connected to GPIO
02748   *            @arg TIM_TIM20_TI1_COMP1:               TIM20 TI1 is connected to COMP1 output     (*)
02749   *            @arg TIM_TIM20_TI1_COMP2:               TIM20 TI1 is connected to COMP2 output     (*)
02750   *            @arg TIM_TIM20_TI1_COMP3:               TIM20 TI1 is connected to COMP3 output     (*)
02751   *            @arg TIM_TIM20_TI1_COMP4:               TIM20 TI1 is connected to COMP4 output     (*)
02752   *
02753   *         (*)  Value not defined in all devices. \n
02754   *         (**) Register not available in all devices.
02755   *
02756   * @retval HAL status
02757   */
02758 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
02759 {
02760   HAL_StatusTypeDef status = HAL_OK;
02761
02762   /* Check parameters */
02763   assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
02764   assert_param(IS_TIM_TISEL(TISelection));
02765
02766   __HAL_LOCK(htim);
02767
02768   switch (Channel)
02769   {
02770     case TIM_CHANNEL_1:
02771       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
02772
02773       /* If required, set OR bit to request HSE/32 clock */
02774       if (IS_TIM_HSE32_INSTANCE(htim->Instance))
02775       {
02776         SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
02777       }
02778       else
02779       {
02780         CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
02781       }
02782       break;
02783     case TIM_CHANNEL_2:
02784       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
02785       break;
02786     case TIM_CHANNEL_3:
02787       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
02788       break;
02789     case TIM_CHANNEL_4:
02790       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
02791       break;
02792     default:
02793       status = HAL_ERROR;
02794       break;
02795   }
02796
02797   __HAL_UNLOCK(htim);
02798
02799   return status;
02800 }
02801
02802 /**
02803   * @brief  Group channel 5 and channel 1, 2 or 3
02804   * @param  htim TIM handle.
02805   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
02806   *         This parameter can be any combination of the following values:
02807   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02808   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02809   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02810   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02811   * @retval HAL status
02812   */
02813 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02814 {
02815   /* Check parameters */
02816   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02817   assert_param(IS_TIM_GROUPCH5(Channels));
02818
02819   /* Process Locked */
02820   __HAL_LOCK(htim);
02821
02822   htim->State = HAL_TIM_STATE_BUSY;
02823
02824   /* Clear GC5Cx bit fields */
02825   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
02826
02827   /* Set GC5Cx bit fields */
02828   htim->Instance->CCR5 |= Channels;
02829
02830   /* Change the htim state */
02831   htim->State = HAL_TIM_STATE_READY;
02832
02833   __HAL_UNLOCK(htim);
02834
02835   return HAL_OK;
02836 }
02837
02838 /**
02839   * @brief  Disarm the designated break input (when it operates in bidirectional mode).
02840   * @param  htim TIM handle.
02841   * @param  BreakInput Break input to disarm
02842   *          This parameter can be one of the following values:
02843   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02844   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02845   * @note  The break input can be disarmed only when it is configured in
02846   *        bidirectional mode and when when MOE is reset.
02847   * @note  Purpose is to be able to have the input voltage back to high-state,
02848   *        whatever the time constant on the output .
02849   * @retval HAL status
02850   */
02851 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
02852 {
02853   HAL_StatusTypeDef status = HAL_OK;
02854   uint32_t tmpbdtr;
02855
02856   /* Check the parameters */
02857   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02858   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02859
02860   switch (BreakInput)
02861   {
02862     case TIM_BREAKINPUT_BRK:
02863     {
02864       /* Check initial conditions */
02865       tmpbdtr = READ_REG(htim->Instance->BDTR);
02866       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
02867           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
02868       {
02869         /* Break input BRK is disarmed */
02870         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
02871       }
02872       break;
02873     }
02874     case TIM_BREAKINPUT_BRK2:
02875     {
02876       /* Check initial conditions */
02877       tmpbdtr = READ_REG(htim->Instance->BDTR);
02878       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
02879           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
02880       {
02881         /* Break input BRK is disarmed */
02882         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
02883       }
02884       break;
02885     }
02886     default:
02887       status = HAL_ERROR;
02888       break;
02889   }
02890
02891   return status;
02892 }
02893
02894 /**
02895   * @brief  Arm the designated break input (when it operates in bidirectional mode).
02896   * @param  htim TIM handle.
02897   * @param  BreakInput Break input to arm
02898   *          This parameter can be one of the following values:
02899   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02900   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02901   * @note  Arming is possible at anytime, even if fault is present.
02902   * @note  Break input is automatically armed as soon as MOE bit is set.
02903   * @retval HAL status
02904   */
02905 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
02906 {
02907   HAL_StatusTypeDef status = HAL_OK;
02908   uint32_t tickstart;
02909
02910   /* Check the parameters */
02911   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02912   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02913
02914   switch (BreakInput)
02915   {
02916     case TIM_BREAKINPUT_BRK:
02917     {
02918       /* Check initial conditions */
02919       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
02920       {
02921         /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
02922         /* Init tickstart for timeout management */
02923         tickstart = HAL_GetTick();
02924         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
02925         {
02926           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
02927           {
02928             /* New check to avoid false timeout detection in case of preemption */
02929             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
02930             {
02931               return HAL_TIMEOUT;
02932             }
02933           }
02934         }
02935       }
02936       break;
02937     }
02938
02939     case TIM_BREAKINPUT_BRK2:
02940     {
02941       /* Check initial conditions */
02942       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
02943       {
02944         /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
02945         /* Init tickstart for timeout management */
02946         tickstart = HAL_GetTick();
02947         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
02948         {
02949           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
02950           {
02951             /* New check to avoid false timeout detection in case of preemption */
02952             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
02953             {
02954               return HAL_TIMEOUT;
02955             }
02956           }
02957         }
02958       }
02959       break;
02960     }
02961     default:
02962       status = HAL_ERROR;
02963       break;
02964   }
02965
02966   return status;
02967 }
02968
02969 /**
02970   * @brief  Enable dithering
02971   * @param  htim TIM handle
02972   * @note   Main usage is PWM mode
02973   * @note   This function must be called when timer is stopped or disabled (CEN =0)
02974   * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
02975   *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
02976   *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
02977   *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
02978   *           - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
02979   *             (corresponds to 4094 for the integer part and 15 for the dithered part).
02980   * @note   Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER()  __HAL_TIM_CALC_PULSE_DITHER()
02981   *         can be used to calculate period (ARR) and delay (CCRx) value.
02982   * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
02983   * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
02984   *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
02985   *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
02986   * @retval HAL status
02987   */
02988 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
02989 {
02990   /* Check the parameters */
02991   assert_param(IS_TIM_INSTANCE(htim->Instance));
02992
02993   SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
02994   return HAL_OK;
02995 }
02996
02997 /**
02998   * @brief  Disable dithering
02999   * @param  htim TIM handle
03000   * @note   This function must be called when timer is stopped or disabled (CEN =0)
03001   * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
03002   *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
03003   *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
03004   *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
03005   *           - ARR and CCRx values are limited to 0xFFEF in dithering mode
03006   *             (corresponds to 4094 for the integer part and 15 for the dithered part).
03007   * @note   Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
03008   *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
03009   *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
03010   * @retval HAL status
03011   */
03012 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
03013 {
03014   /* Check the parameters */
03015   assert_param(IS_TIM_INSTANCE(htim->Instance));
03016
03017   CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
03018   return HAL_OK;
03019 }
03020
03021 /**
03022   * @brief  Initializes the pulse on compare pulse width and pulse prescaler
03023   * @param  htim TIM Output Compare handle
03024   * @param  PulseWidthPrescaler  Pulse width prescaler
03025   *         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
03026   * @param  PulseWidth  Pulse width
03027   *         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
03028   * @retval HAL status
03029   */
03030 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
03031                                                     uint32_t PulseWidthPrescaler,
03032                                                     uint32_t PulseWidth)
03033 {
03034   uint32_t tmpecr;
03035
03036   /* Check the parameters */
03037   assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
03038   assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
03039   assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
03040
03041   /* Process Locked */
03042   __HAL_LOCK(htim);
03043
03044   /* Set the TIM state */
03045   htim->State = HAL_TIM_STATE_BUSY;
03046
03047   /* Get the TIMx ECR register value */
03048   tmpecr = htim->Instance->ECR;
03049   /* Reset the Pulse width prescaler and the Pulse width */
03050   tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
03051   /* Set the Pulse width prescaler and Pulse width*/
03052   tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
03053   tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
03054   /* Write to TIMx ECR */
03055   htim->Instance->ECR = tmpecr;
03056
03057   /* Change the TIM state */
03058   htim->State = HAL_TIM_STATE_READY;
03059
03060   /* Release Lock */
03061   __HAL_UNLOCK(htim);
03062
03063   return HAL_OK;
03064 }
03065
03066 /**
03067   * @brief  Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
03068   * @param  htim TIM handle
03069   * @param  Source Source of slave mode selection preload
03070   *         This parameter can be one of the following values:
03071   *            @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
03072   *            @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
03073   * @retval HAL status
03074   */
03075 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
03076 {
03077   /* Check the parameters */
03078   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
03079   assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
03080
03081   MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
03082   return HAL_OK;
03083 }
03084
03085 /**
03086   * @brief  Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
03087   * @param  htim TIM handle
03088   * @retval HAL status
03089   */
03090 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
03091 {
03092   /* Check the parameters */
03093   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
03094
03095   SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
03096   return HAL_OK;
03097 }
03098
03099 /**
03100   * @brief  Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
03101   * @param  htim TIM handle
03102   * @retval HAL status
03103   */
03104 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
03105 {
03106   /* Check the parameters */
03107   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
03108
03109   CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
03110   return HAL_OK;
03111 }
03112
03113 /**
03114   * @brief  Enable deadtime preload
03115   * @param  htim TIM handle
03116   * @retval HAL status
03117   */
03118 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
03119 {
03120   /* Check the parameters */
03121   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03122
03123   SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
03124   return HAL_OK;
03125 }
03126
03127 /**
03128   * @brief  Disable deadtime preload
03129   * @param  htim TIM handle
03130   * @retval HAL status
03131   */
03132 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
03133 {
03134   /* Check the parameters */
03135   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03136
03137   CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
03138   return HAL_OK;
03139 }
03140
03141 /**
03142   * @brief  Configure deadtime
03143   * @param  htim TIM handle
03144   * @param  Deadtime Deadtime value
03145   * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
03146   * @retval HAL status
03147   */
03148 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
03149 {
03150   /* Check the parameters */
03151   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03152   assert_param(IS_TIM_DEADTIME(Deadtime));
03153
03154   MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
03155   return HAL_OK;
03156 }
03157
03158 /**
03159   * @brief  Configure asymmetrical deadtime
03160   * @param  htim TIM handle
03161   * @param  FallingDeadtime Falling edge deadtime value
03162   * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
03163   * @retval HAL status
03164   */
03165 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
03166 {
03167   /* Check the parameters */
03168   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03169   assert_param(IS_TIM_DEADTIME(FallingDeadtime));
03170
03171   MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
03172   return HAL_OK;
03173 }
03174
03175 /**
03176   * @brief  Enable asymmetrical deadtime
03177   * @param  htim TIM handle
03178   * @retval HAL status
03179   */
03180 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
03181 {
03182   /* Check the parameters */
03183   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03184
03185   SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
03186   return HAL_OK;
03187 }
03188
03189 /**
03190   * @brief  Disable asymmetrical deadtime
03191   * @param  htim TIM handle
03192   * @retval HAL status
03193   */
03194 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
03195 {
03196   /* Check the parameters */
03197   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
03198
03199   CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
03200   return HAL_OK;
03201 }
03202
03203 /**
03204   * @brief  Configures the encoder index.
03205   * @note   warning in case of encoder mode clock plus direction
03206   *                    @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
03207   *         Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
03208   * @param  htim TIM handle.
03209   * @param  sEncoderIndexConfig Encoder index configuration
03210   * @retval HAL status
03211   */
03212 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
03213                                                TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
03214 {
03215   /* Check the parameters */
03216   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03217   assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
03218   assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
03219   assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
03220   assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
03221   assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
03222   assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
03223
03224   /* Process Locked */
03225   __HAL_LOCK(htim);
03226
03227   /* Configures the TIMx External Trigger (ETR) which is used as Index input */
03228   TIM_ETR_SetConfig(htim->Instance,
03229                     sEncoderIndexConfig->Prescaler,
03230                     sEncoderIndexConfig->Polarity,
03231                     sEncoderIndexConfig->Filter);
03232
03233   /* Configures the encoder index */
03234   MODIFY_REG(htim->Instance->ECR,
03235              TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
03236              (sEncoderIndexConfig->Direction |
03237               ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
03238               sEncoderIndexConfig->Position |
03239               TIM_ECR_IE));
03240
03241   __HAL_UNLOCK(htim);
03242
03243   return HAL_OK;
03244 }
03245
03246 /**
03247   * @brief  Enable encoder index
03248   * @param  htim TIM handle
03249   * @retval HAL status
03250   */
03251 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
03252 {
03253   /* Check the parameters */
03254   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03255
03256   SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
03257   return HAL_OK;
03258 }
03259
03260 /**
03261   * @brief  Disable encoder index
03262   * @param  htim TIM handle
03263   * @retval HAL status
03264   */
03265 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
03266 {
03267   /* Check the parameters */
03268   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03269
03270   CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
03271   return HAL_OK;
03272 }
03273
03274 /**
03275   * @brief  Enable encoder first index
03276   * @param  htim TIM handle
03277   * @retval HAL status
03278   */
03279 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
03280 {
03281   /* Check the parameters */
03282   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03283
03284   SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
03285   return HAL_OK;
03286 }
03287
03288 /**
03289   * @brief  Disable encoder first index
03290   * @param  htim TIM handle
03291   * @retval HAL status
03292   */
03293 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
03294 {
03295   /* Check the parameters */
03296   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03297
03298   CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
03299   return HAL_OK;
03300 }
03301
03302 /**
03303   * @}
03304   */
03305
03306 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
03307   * @brief    Extended Callbacks functions
03308   *
03309 @verbatim
03310   ==============================================================================
03311                     ##### Extended Callbacks functions #####
03312   ==============================================================================
03313   [..]
03314     This section provides Extended TIM callback functions:
03315     (+) Timer Commutation callback
03316     (+) Timer Break callback
03317
03318 @endverbatim
03319   * @{
03320   */
03321
03322 /**
03323   * @brief  Commutation callback in non-blocking mode
03324   * @param  htim TIM handle
03325   * @retval None
03326   */
03327 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
03328 {
03329   /* Prevent unused argument(s) compilation warning */
03330   UNUSED(htim);
03331
03332   /* NOTE : This function should not be modified, when the callback is needed,
03333             the HAL_TIMEx_CommutCallback could be implemented in the user file
03334    */
03335 }
03336 /**
03337   * @brief  Commutation half complete callback in non-blocking mode
03338   * @param  htim TIM handle
03339   * @retval None
03340   */
03341 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
03342 {
03343   /* Prevent unused argument(s) compilation warning */
03344   UNUSED(htim);
03345
03346   /* NOTE : This function should not be modified, when the callback is needed,
03347             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
03348    */
03349 }
03350
03351 /**
03352   * @brief  Break detection callback in non-blocking mode
03353   * @param  htim TIM handle
03354   * @retval None
03355   */
03356 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
03357 {
03358   /* Prevent unused argument(s) compilation warning */
03359   UNUSED(htim);
03360
03361   /* NOTE : This function should not be modified, when the callback is needed,
03362             the HAL_TIMEx_BreakCallback could be implemented in the user file
03363    */
03364 }
03365
03366 /**
03367   * @brief  Break2 detection callback in non blocking mode
03368   * @param  htim: TIM handle
03369   * @retval None
03370   */
03371 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
03372 {
03373   /* Prevent unused argument(s) compilation warning */
03374   UNUSED(htim);
03375
03376   /* NOTE : This function Should not be modified, when the callback is needed,
03377             the HAL_TIMEx_Break2Callback could be implemented in the user file
03378    */
03379 }
03380
03381 /**
03382   * @brief  Encoder index callback in non-blocking mode
03383   * @param  htim TIM handle
03384   * @retval None
03385   */
03386 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
03387 {
03388   /* Prevent unused argument(s) compilation warning */
03389   UNUSED(htim);
03390
03391   /* NOTE : This function should not be modified, when the callback is needed,
03392             the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
03393    */
03394 }
03395
03396 /**
03397   * @brief  Direction change callback in non-blocking mode
03398   * @param  htim TIM handle
03399   * @retval None
03400   */
03401 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
03402 {
03403   /* Prevent unused argument(s) compilation warning */
03404   UNUSED(htim);
03405
03406   /* NOTE : This function should not be modified, when the callback is needed,
03407             the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
03408    */
03409 }
03410
03411 /**
03412   * @brief  Index error callback in non-blocking mode
03413   * @param  htim TIM handle
03414   * @retval None
03415   */
03416 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
03417 {
03418   /* Prevent unused argument(s) compilation warning */
03419   UNUSED(htim);
03420
03421   /* NOTE : This function should not be modified, when the callback is needed,
03422             the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
03423    */
03424 }
03425
03426 /**
03427   * @brief  Transition error callback in non-blocking mode
03428   * @param  htim TIM handle
03429   * @retval None
03430   */
03431 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
03432 {
03433   /* Prevent unused argument(s) compilation warning */
03434   UNUSED(htim);
03435
03436   /* NOTE : This function should not be modified, when the callback is needed,
03437             the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
03438    */
03439 }
03440
03441 /**
03442   * @}
03443   */
03444
03445 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
03446   * @brief    Extended Peripheral State functions
03447   *
03448 @verbatim
03449   ==============================================================================
03450                 ##### Extended Peripheral State functions #####
03451   ==============================================================================
03452   [..]
03453     This subsection permits to get in run-time the status of the peripheral
03454     and the data flow.
03455
03456 @endverbatim
03457   * @{
03458   */
03459
03460 /**
03461   * @brief  Return the TIM Hall Sensor interface handle state.
03462   * @param  htim TIM Hall Sensor handle
03463   * @retval HAL state
03464   */
03465 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
03466 {
03467   return htim->State;
03468 }
03469
03470 /**
03471   * @brief  Return actual state of the TIM complementary channel.
03472   * @param  htim TIM handle
03473   * @param  ChannelN TIM Complementary channel
03474   *          This parameter can be one of the following values:
03475   *            @arg TIM_CHANNEL_1: TIM Channel 1
03476   *            @arg TIM_CHANNEL_2: TIM Channel 2
03477   *            @arg TIM_CHANNEL_3: TIM Channel 3
03478   *            @arg TIM_CHANNEL_4: TIM Channel 4
03479   * @retval TIM Complementary channel state
03480   */
03481 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
03482 {
03483   HAL_TIM_ChannelStateTypeDef channel_state;
03484
03485   /* Check the parameters */
03486   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
03487
03488   channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
03489
03490   return channel_state;
03491 }
03492 /**
03493   * @}
03494   */
03495
03496 /**
03497   * @}
03498   */
03499
03500 /* Private functions ---------------------------------------------------------*/
03501 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
03502   * @{
03503   */
03504
03505 /**
03506   * @brief  TIM DMA Commutation callback.
03507   * @param  hdma pointer to DMA handle.
03508   * @retval None
03509   */
03510 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
03511 {
03512   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03513
03514   /* Change the htim state */
03515   htim->State = HAL_TIM_STATE_READY;
03516
03517 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03518   htim->CommutationCallback(htim);
03519 #else
03520   HAL_TIMEx_CommutCallback(htim);
03521 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03522 }
03523
03524 /**
03525   * @brief  TIM DMA Commutation half complete callback.
03526   * @param  hdma pointer to DMA handle.
03527   * @retval None
03528   */
03529 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
03530 {
03531   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03532
03533   /* Change the htim state */
03534   htim->State = HAL_TIM_STATE_READY;
03535
03536 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03537   htim->CommutationHalfCpltCallback(htim);
03538 #else
03539   HAL_TIMEx_CommutHalfCpltCallback(htim);
03540 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03541 }
03542
03543
03544 /**
03545   * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
03546   * @param  hdma pointer to DMA handle.
03547   * @retval None
03548   */
03549 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
03550 {
03551   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03552
03553   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
03554   {
03555     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03556
03557     if (hdma->Init.Mode == DMA_NORMAL)
03558     {
03559       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03560     }
03561   }
03562   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
03563   {
03564     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03565
03566     if (hdma->Init.Mode == DMA_NORMAL)
03567     {
03568       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03569     }
03570   }
03571   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
03572   {
03573     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03574
03575     if (hdma->Init.Mode == DMA_NORMAL)
03576     {
03577       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
03578     }
03579   }
03580   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
03581   {
03582     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03583
03584     if (hdma->Init.Mode == DMA_NORMAL)
03585     {
03586       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
03587     }
03588   }
03589   else
03590   {
03591     /* nothing to do */
03592   }
03593
03594 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03595   htim->PWM_PulseFinishedCallback(htim);
03596 #else
03597   HAL_TIM_PWM_PulseFinishedCallback(htim);
03598 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03599
03600   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03601 }
03602
03603 /**
03604   * @brief  TIM DMA error callback (complementary channel)
03605   * @param  hdma pointer to DMA handle.
03606   * @retval None
03607   */
03608 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
03609 {
03610   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03611
03612   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
03613   {
03614     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03615     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03616   }
03617   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
03618   {
03619     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03620     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03621   }
03622   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
03623   {
03624     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03625     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
03626   }
03627   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
03628   {
03629     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03630     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
03631   }
03632   else
03633   {
03634     /* nothing to do */
03635   }
03636
03637 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03638   htim->ErrorCallback(htim);
03639 #else
03640   HAL_TIM_ErrorCallback(htim);
03641 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03642
03643   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03644 }
03645
03646 /**
03647   * @brief  Enables or disables the TIM Capture Compare Channel xN.
03648   * @param  TIMx to select the TIM peripheral
03649   * @param  Channel specifies the TIM Channel
03650   *          This parameter can be one of the following values:
03651   *            @arg TIM_CHANNEL_1: TIM Channel 1
03652   *            @arg TIM_CHANNEL_2: TIM Channel 2
03653   *            @arg TIM_CHANNEL_3: TIM Channel 3
03654   *            @arg TIM_CHANNEL_4: TIM Channel 4
03655   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
03656   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
03657   * @retval None
03658   */
03659 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
03660 {
03661   uint32_t tmp;
03662
03663   tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
03664
03665   /* Reset the CCxNE Bit */
03666   TIMx->CCER &=  ~tmp;
03667
03668   /* Set or reset the CCxNE Bit */
03669   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
03670 }
03671 /**
03672   * @}
03673   */
03674
03675 #endif /* HAL_TIM_MODULE_ENABLED */
03676 /**
03677   * @}
03678   */
03679
03680 /**
03681   * @}
03682   */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_tim_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_tim_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_TIM_EX_H
00021 #define STM32G4xx_HAL_TIM_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup TIMEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  TIM Hall sensor Configuration Structure definition
00045   */
00046
00047 typedef struct
00048 {
00049   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00050                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00051
00052   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00053                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00054
00055   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00056                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00057
00058   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00059                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00060 } TIM_HallSensor_InitTypeDef;
00061
00062 /**
00063   * @brief  TIM Break/Break2 input configuration
00064   */
00065 typedef struct
00066 {
00067   uint32_t Source;         /*!< Specifies the source of the timer break input.
00068                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00069   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00070                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00071   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00072                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
00073 } TIMEx_BreakInputConfigTypeDef;
00074
00075 /**
00076   * @brief  TIM Encoder index configuration
00077   */
00078 typedef struct
00079 {
00080   uint32_t Polarity;                  /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
00081
00082   uint32_t Prescaler;                 /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
00083
00084   uint32_t Filter;                    /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00085
00086   FunctionalState  FirstIndexEnable;  /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */
00087
00088   uint32_t Position;                  /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */
00089
00090   uint32_t Direction;                 /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */
00091
00092 } TIMEx_EncoderIndexConfigTypeDef;
00093
00094 /**
00095   * @}
00096   */
00097 /* End of exported types -----------------------------------------------------*/
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00101   * @{
00102   */
00103
00104 /** @defgroup TIMEx_Remap TIM Extended Remapping
00105   * @{
00106   */
00107 #define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
00108 #define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
00109 #define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
00110 #define TIM_TIM1_ETR_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
00111 #define TIM_TIM1_ETR_COMP4       TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
00112 #if defined(COMP5)
00113 #define TIM_TIM1_ETR_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
00114 #endif /* COMP5 */
00115 #if defined(COMP6)
00116 #define TIM_TIM1_ETR_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
00117 #endif /* COMP6 */
00118 #if defined(COMP7)
00119 #define TIM_TIM1_ETR_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
00120 #endif /* COMP7 */
00121 #define TIM_TIM1_ETR_ADC1_AWD1   TIM1_AF1_ETRSEL_3                                           /*!< ADC1 analog watchdog 1 */
00122 #define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ADC1 analog watchdog 2 */
00123 #define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ADC1 analog watchdog 3 */
00124 #if defined (ADC4)
00125 #define TIM_TIM1_ETR_ADC4_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
00126 #define TIM_TIM1_ETR_ADC4_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ADC4 analog watchdog 2 */
00127 #define TIM_TIM1_ETR_ADC4_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
00128 #endif /* ADC4 */
00129
00130 #define TIM_TIM2_ETR_GPIO         0x00000000U                                                /*!< ETR input is connected to GPIO */
00131 #define TIM_TIM2_ETR_COMP1        TIM1_AF1_ETRSEL_0                                          /*!< ETR input is connected to COMP1_OUT */
00132 #define TIM_TIM2_ETR_COMP2        TIM1_AF1_ETRSEL_1                                          /*!< ETR input is connected to COMP2_OUT */
00133 #define TIM_TIM2_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                    /*!< ETR input is connected to COMP3_OUT */
00134 #define TIM_TIM2_ETR_COMP4        TIM1_AF1_ETRSEL_2                                          /*!< ETR input is connected to COMP4_OUT */
00135 #if defined(COMP5)
00136 #define TIM_TIM2_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                    /*!< ETR input is connected to COMP5_OUT */
00137 #endif /* COMP5 */
00138 #if defined(COMP6)
00139 #define TIM_TIM2_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                    /*!< ETR input is connected to COMP6_OUT */
00140 #endif /* COMP6 */
00141 #if defined(COMP7)
00142 #define TIM_TIM2_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/*!< ETR input is connected to COMP7_OUT */
00143 #endif /* COMP7 */
00144 #define TIM_TIM2_ETR_TIM3_ETR     TIM1_AF1_ETRSEL_3                                          /*!< ETR input is connected to TIM3 ETR */
00145 #define TIM_TIM2_ETR_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                    /*!< ETR input is connected to TIM4 ETR */
00146 #if defined (TIM5)
00147 #define TIM_TIM2_ETR_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                    /*!< ETR input is connected to TIM5 ETR */
00148 #endif /* TIM5 */
00149 #define TIM_TIM2_ETR_LSE          (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
00150
00151 #define TIM_TIM3_ETR_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
00152 #define TIM_TIM3_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
00153 #define TIM_TIM3_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
00154 #define TIM_TIM3_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
00155 #define TIM_TIM3_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
00156 #if defined(COMP5)
00157 #define TIM_TIM3_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
00158 #endif /* COMP5 */
00159 #if defined(COMP6)
00160 #define TIM_TIM3_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
00161 #endif /* COMP6 */
00162 #if defined(COMP7)
00163 #define TIM_TIM3_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
00164 #endif /* COMP7 */
00165 #define TIM_TIM3_ETR_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
00166 #define TIM_TIM3_ETR_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
00167 #define TIM_TIM3_ETR_ADC2_AWD1    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
00168 #define TIM_TIM3_ETR_ADC2_AWD2    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ADC2 analog watchdog 2 */
00169 #define TIM_TIM3_ETR_ADC2_AWD3    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
00170
00171 #define TIM_TIM4_ETR_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
00172 #define TIM_TIM4_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
00173 #define TIM_TIM4_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
00174 #define TIM_TIM4_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
00175 #define TIM_TIM4_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
00176 #if defined(COMP5)
00177 #define TIM_TIM4_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
00178 #endif /* COMP5 */
00179 #if defined(COMP6)
00180 #define TIM_TIM4_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
00181 #endif /* COMP6 */
00182 #if defined(COMP7)
00183 #define TIM_TIM4_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
00184 #endif /* COMP7 */
00185 #define TIM_TIM4_ETR_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
00186 #if defined (TIM5)
00187 #define TIM_TIM4_ETR_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM5 ETR */
00188 #endif /* TIM5 */
00189
00190 #if defined (TIM5)
00191 #define TIM_TIM5_ETR_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
00192 #define TIM_TIM5_ETR_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
00193 #define TIM_TIM5_ETR_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
00194 #define TIM_TIM5_ETR_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
00195 #define TIM_TIM5_ETR_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
00196 #if defined(COMP5)
00197 #define TIM_TIM5_ETR_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
00198 #endif /* COMP5 */
00199 #if defined(COMP6)
00200 #define TIM_TIM5_ETR_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
00201 #endif /* COMP6 */
00202 #if defined(COMP7)
00203 #define TIM_TIM5_ETR_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
00204 #endif /* COMP7 */
00205 #define TIM_TIM5_ETR_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
00206 #define TIM_TIM5_ETR_TIM3_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM3 ETR */
00207 #endif /* TIM5 */
00208
00209 #define TIM_TIM8_ETR_GPIO        0x00000000U                                                  /*!< ETR input is connected to GPIO */
00210 #define TIM_TIM8_ETR_COMP1       TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
00211 #define TIM_TIM8_ETR_COMP2       TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
00212 #define TIM_TIM8_ETR_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
00213 #define TIM_TIM8_ETR_COMP4       TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
00214 #if defined(COMP5)
00215 #define TIM_TIM8_ETR_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
00216 #endif /* COMP5 */
00217 #if defined(COMP6)
00218 #define TIM_TIM8_ETR_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
00219 #endif /* COMP6 */
00220 #if defined(COMP7)
00221 #define TIM_TIM8_ETR_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
00222 #endif /* COMP7 */
00223 #define TIM_TIM8_ETR_ADC2_AWD1   TIM1_AF1_ETRSEL_3                                            /*!< ADC2 analog watchdog 1 */
00224 #define TIM_TIM8_ETR_ADC2_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC2 analog watchdog 2 */
00225 #define TIM_TIM8_ETR_ADC2_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC2 analog watchdog 3 */
00226 #if defined (ADC3)
00227 #define TIM_TIM8_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 1 */
00228 #define TIM_TIM8_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC3 analog watchdog 2 */
00229 #define TIM_TIM8_ETR_ADC3_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 3 */
00230 #endif /* ADC3 */
00231
00232 #if defined (TIM20)
00233 #define TIM_TIM20_ETR_GPIO       0x00000000U                                                 /*!< ETR input is connected to GPIO */
00234 #define TIM_TIM20_ETR_COMP1      TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
00235 #define TIM_TIM20_ETR_COMP2      TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
00236 #define TIM_TIM20_ETR_COMP3      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
00237 #define TIM_TIM20_ETR_COMP4      TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
00238 #if defined(COMP5)
00239 #define TIM_TIM20_ETR_COMP5      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
00240 #endif /* COMP5 */
00241 #if defined(COMP6)
00242 #define TIM_TIM20_ETR_COMP6      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
00243 #endif /* COMP6 */
00244 #if defined(COMP7)
00245 #define TIM_TIM20_ETR_COMP7      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
00246 #endif /* COMP7 */
00247 #define TIM_TIM20_ETR_ADC3_AWD1  TIM1_AF1_ETRSEL_3                                           /*!< ADC3 analog watchdog 1 */
00248 #define TIM_TIM20_ETR_ADC3_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ADC3 analog watchdog 2 */
00249 #define TIM_TIM20_ETR_ADC3_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ADC3 analog watchdog 3 */
00250 #if defined (ADC5)
00251 #define TIM_TIM20_ETR_ADC5_AWD1  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
00252 #define TIM_TIM20_ETR_ADC5_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ADC5 analog watchdog 2 */
00253 #define TIM_TIM20_ETR_ADC5_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
00254 #endif /* ADC5 */
00255 #endif /* TIM20 */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup TIMEx_Break_Input TIM Extended Break input
00261   * @{
00262   */
00263 #define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
00264 #define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
00270   * @{
00271   */
00272 #define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /*!< An external source (GPIO) is connected to the BKIN pin  */
00273 #define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /*!< The COMP1 output is connected to the break input */
00274 #define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /*!< The COMP2 output is connected to the break input */
00275 #define TIM_BREAKINPUTSOURCE_COMP3    0x00000008U                               /*!< The COMP3 output is connected to the break input */
00276 #define TIM_BREAKINPUTSOURCE_COMP4    0x00000010U                               /*!< The COMP4 output is connected to the break input */
00277 #if defined(COMP5)
00278 #define TIM_BREAKINPUTSOURCE_COMP5    0x00000020U                               /*!< The COMP5 output is connected to the break input */
00279 #endif /* COMP5 */
00280 #if defined(COMP6)
00281 #define TIM_BREAKINPUTSOURCE_COMP6    0x00000040U                               /*!< The COMP6 output is connected to the break input */
00282 #endif /* COMP6 */
00283 #if defined(COMP7)
00284 #define TIM_BREAKINPUTSOURCE_COMP7    0x00000080U                               /*!< The COMP7 output is connected to the break input */
00285 #endif /* COMP7 */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00291   * @{
00292   */
00293 #define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
00294 #define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
00300   * @{
00301   */
00302 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
00303 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
00309   * @{
00310   */
00311 #define TIM_TIM1_TI1_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
00312 #define TIM_TIM1_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
00313 #define TIM_TIM1_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM1 input 1 is connected to COMP2_OUT */
00314 #define TIM_TIM1_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM1 input 1 is connected to COMP3_OUT */
00315 #define TIM_TIM1_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM1 input 1 is connected to COMP4_OUT */
00316
00317
00318 #define TIM_TIM2_TI1_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
00319 #define TIM_TIM2_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
00320 #define TIM_TIM2_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM2 input 1 is connected to COMP2_OUT */
00321 #define TIM_TIM2_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP3_OUT */
00322 #define TIM_TIM2_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM2 input 1 is connected to COMP4_OUT */
00323 #if defined (COMP5)
00324 #define TIM_TIM2_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP5_OUT */
00325 #endif /* COMP5 */
00326
00327 #define TIM_TIM2_TI2_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
00328 #define TIM_TIM2_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP1_OUT */
00329 #define TIM_TIM2_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM2 input 2 is connected to COMP2_OUT */
00330 #define TIM_TIM2_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP3_OUT */
00331 #define TIM_TIM2_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM2 input 2 is connected to COMP4_OUT */
00332 #if defined (COMP6)
00333 #define TIM_TIM2_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP6_OUT */
00334 #endif /* COMP6 */
00335
00336 #define TIM_TIM2_TI3_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
00337 #define TIM_TIM2_TI3_COMP4  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP4_OUT */
00338
00339 #define TIM_TIM2_TI4_GPIO   0x00000000U                                       /*!< TIM2 input 4 is connected to GPIO */
00340 #define TIM_TIM2_TI4_COMP1  TIM_TISEL_TI4SEL_0                                /*!< TIM2 input 4 is connected to COMP1_OUT */
00341 #define TIM_TIM2_TI4_COMP2  TIM_TISEL_TI4SEL_1                                /*!< TIM2 input 4 is connected to COMP2_OUT */
00342
00343
00344 #define TIM_TIM3_TI1_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
00345 #define TIM_TIM3_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
00346 #define TIM_TIM3_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM3 input 1 is connected to COMP2_OUT */
00347 #define TIM_TIM3_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP3_OUT */
00348 #define TIM_TIM3_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM3 input 1 is connected to COMP4_OUT */
00349 #if defined (COMP5)
00350 #define TIM_TIM3_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP5_OUT */
00351 #endif /* COMP5 */
00352 #if defined (COMP6)
00353 #define TIM_TIM3_TI1_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM3 input 1 is connected to COMP6_OUT */
00354 #endif /* COMP6 */
00355 #if defined (COMP7)
00356 #define TIM_TIM3_TI1_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM3 input 1 is connected to COMP7_OUT */
00357 #endif /* COMP7 */
00358
00359 #define TIM_TIM3_TI2_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
00360 #define TIM_TIM3_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP1_OUT */
00361 #define TIM_TIM3_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM3 input 2 is connected to COMP2_OUT */
00362 #define TIM_TIM3_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP3_OUT */
00363 #define TIM_TIM3_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM3 input 2 is connected to COMP4_OUT */
00364 #if defined (COMP5)
00365 #define TIM_TIM3_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP5_OUT */
00366 #endif /* COMP5 */
00367 #if defined (COMP6)
00368 #define TIM_TIM3_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM3 input 2 is connected to COMP6_OUT */
00369 #endif /* COMP6 */
00370 #if defined (COMP7)
00371 #define TIM_TIM3_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM3 input 2 is connected to COMP7_OUT */
00372 #endif /* COMP7 */
00373
00374 #define TIM_TIM3_TI3_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
00375 #define TIM_TIM3_TI3_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
00376
00377
00378 #define TIM_TIM4_TI1_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
00379 #define TIM_TIM4_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
00380 #define TIM_TIM4_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM4 input 1 is connected to COMP2_OUT */
00381 #define TIM_TIM4_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP3_OUT */
00382 #define TIM_TIM4_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM4 input 1 is connected to COMP4_OUT */
00383 #if defined (COMP5)
00384 #define TIM_TIM4_TI1_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP5_OUT */
00385 #endif /* COMP5 */
00386 #if defined (COMP6)
00387 #define TIM_TIM4_TI1_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM4 input 1 is connected to COMP6_OUT */
00388 #endif /* COMP6 */
00389 #if defined (COMP7)
00390 #define TIM_TIM4_TI1_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM4 input 1 is connected to COMP7_OUT */
00391 #endif /* COMP7 */
00392
00393 #define TIM_TIM4_TI2_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
00394 #define TIM_TIM4_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP1_OUT */
00395 #define TIM_TIM4_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM4 input 2 is connected to COMP2_OUT */
00396 #define TIM_TIM4_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP3_OUT */
00397 #define TIM_TIM4_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM4 input 2 is connected to COMP4_OUT */
00398 #if defined (COMP5)
00399 #define TIM_TIM4_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP5_OUT */
00400 #endif /* COMP5 */
00401 #if defined (COMP6)
00402 #define TIM_TIM4_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM4 input 2 is connected to COMP6_OUT */
00403 #endif /* COMP6 */
00404 #if defined (COMP7)
00405 #define TIM_TIM4_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM4 input 2 is connected to COMP7_OUT */
00406 #endif /* COMP7 */
00407
00408 #define TIM_TIM4_TI3_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
00409 #if defined (COMP5)
00410 #define TIM_TIM4_TI3_COMP5  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP5_OUT */
00411 #endif /* COMP5 */
00412
00413 #define TIM_TIM4_TI4_GPIO   0x00000000U                                       /*!< TIM4 input 4 is connected to GPIO */
00414 #if defined (COMP6)
00415 #define TIM_TIM4_TI4_COMP6  TIM_TISEL_TI4SEL_0                                /*!< TIM4 input 4 is connected to COMP6_OUT */
00416 #endif /* COMP6 */
00417
00418
00419 #if defined(TIM5)
00420 #define TIM_TIM5_TI1_GPIO   0x00000000U                                       /*!< TIM5 input 1 is connected to GPIO */
00421 #define TIM_TIM5_TI1_LSI    TIM_TISEL_TI1SEL_0                                /*!< TIM5 input 1 is connected to LSI */
00422 #define TIM_TIM5_TI1_LSE    TIM_TISEL_TI1SEL_1                                /*!< TIM5 input 1 is connected to LSE */
00423 #define TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to RTC_WAKEUP */
00424 #define TIM_TIM5_TI1_COMP1  TIM_TISEL_TI1SEL_2                                /*!< TIM5 input 1 is connected to COMP1_OUT */
00425 #define TIM_TIM5_TI1_COMP2  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP2_OUT */
00426 #define TIM_TIM5_TI1_COMP3  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP3_OUT */
00427 #define TIM_TIM5_TI1_COMP4  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM5 input 1 is connected to COMP4_OUT */
00428 #if defined(COMP5)
00429 #define TIM_TIM5_TI1_COMP5  TIM_TISEL_TI1SEL_3                                /*!< TIM5 input 1 is connected to COMP5_OUT */
00430 #endif /* COMP5 */
00431 #if defined(COMP6)
00432 #define TIM_TIM5_TI1_COMP6  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP6_OUT */
00433 #endif /* COMP6 */
00434 #if defined(COMP7)
00435 #define TIM_TIM5_TI1_COMP7  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP7_OUT */
00436 #endif /* COMP7 */
00437
00438 #define TIM_TIM5_TI2_GPIO   0x00000000U                                       /*!< TIM5 input 2 is connected to GPIO */
00439 #define TIM_TIM5_TI2_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM5 input 2 is connected to COMP1_OUT */
00440 #define TIM_TIM5_TI2_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM5 input 2 is connected to COMP2_OUT */
00441 #define TIM_TIM5_TI2_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP3_OUT */
00442 #define TIM_TIM5_TI2_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM5 input 2 is connected to COMP4_OUT */
00443 #if defined(COMP5)
00444 #define TIM_TIM5_TI2_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP5_OUT */
00445 #endif /* COMP5 */
00446 #if defined(COMP6)
00447 #define TIM_TIM5_TI2_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM5 input 2 is connected to COMP6_OUT */
00448 #endif /* COMP6 */
00449 #if defined(COMP7)
00450 #define TIM_TIM5_TI2_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM5 input 2 is connected to COMP7_OUT */
00451 #endif /* COMP7 */
00452 #endif /* TIM5 */
00453
00454
00455 #define TIM_TIM8_TI1_GPIO   0x00000000U                                       /*!< TIM8 input 1 is connected to GPIO */
00456 #define TIM_TIM8_TI1_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM8 input 1 is connected to COMP1_OUT */
00457 #define TIM_TIM8_TI1_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM8 input 1 is connected to COMP2_OUT */
00458 #define TIM_TIM8_TI1_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM8 input 1 is connected to COMP3_OUT */
00459 #define TIM_TIM8_TI1_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM8 input 1 is connected to COMP4_OUT */
00460
00461
00462 #define TIM_TIM15_TI1_GPIO  0x00000000U                                       /*!< TIM15 input 1 is connected to GPIO */
00463 #define TIM_TIM15_TI1_LSE   TIM_TISEL_TI1SEL_0                                /*!< TIM15 input 1 is connected to LSE */
00464 #define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1                                /*!< TIM15 input 1 is connected to COMP1_OUT */
00465 #define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP2_OUT */
00466 #if defined (COMP5)
00467 #define TIM_TIM15_TI1_COMP5 TIM_TISEL_TI1SEL_2                                /*!< TIM15 input 1 is connected to COMP5_OUT */
00468 #endif /* COMP5 */
00469 #if defined(COMP7)
00470 #define TIM_TIM15_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP7_OUT */
00471 #endif /* COMP7 */
00472
00473 #define TIM_TIM15_TI2_GPIO  0x00000000U                                       /*!< TIM15 input 2 is connected to GPIO */
00474 #define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0                                /*!< TIM15 input 2 is connected to COMP2_OUT */
00475 #define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1                                /*!< TIM15 input 2 is connected to COMP3_OUT */
00476 #if defined (COMP6)
00477 #define TIM_TIM15_TI2_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM15 input 2 is connected to COMP6_OUT */
00478 #endif /* COMP6 */
00479 #if defined(COMP7)
00480 #define TIM_TIM15_TI2_COMP7 TIM_TISEL_TI2SEL_2                                /*!< TIM15 input 2 is connected to COMP7_OUT */
00481 #endif /* COMP7 */
00482
00483
00484 #define TIM_TIM16_TI1_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
00485 #if defined (COMP6)
00486 #define TIM_TIM16_TI1_COMP6   TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to COMP6_OUT */
00487 #endif /* COMP6 */
00488 #define TIM_TIM16_TI1_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to MCO */
00489 #define TIM_TIM16_TI1_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to HSE/32 */
00490 #define TIM_TIM16_TI1_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to RTC_WAKEUP */
00491 #define TIM_TIM16_TI1_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to LSE */
00492 #define TIM_TIM16_TI1_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to LSI */
00493
00494
00495 #define TIM_TIM17_TI1_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
00496 #if defined (COMP5)
00497 #define TIM_TIM17_TI1_COMP5   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to COMP5_OUT */
00498 #endif /* COMP5 */
00499 #define TIM_TIM17_TI1_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to MCO */
00500 #define TIM_TIM17_TI1_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to HSE/32 */
00501 #define TIM_TIM17_TI1_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to RTC_WAKEUP */
00502 #define TIM_TIM17_TI1_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to LSE */
00503 #define TIM_TIM17_TI1_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM17 input 1 is connected to LSI */
00504
00505
00506 #if defined (TIM20)
00507 #define TIM_TIM20_TI1_GPIO  0x00000000U                                      /*!< TIM20 input 1 is connected to GPIO */
00508 #define TIM_TIM20_TI1_COMP1 TIM_TISEL_TI1SEL_0                               /*!< TIM20 input 1 is connected to COMP1_OUT */
00509 #define TIM_TIM20_TI1_COMP2 TIM_TISEL_TI1SEL_1                               /*!< TIM20 input 1 is connected to COMP2_OUT */
00510 #define TIM_TIM20_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)        /*!< TIM20 input 1 is connected to COMP3_OUT */
00511 #define TIM_TIM20_TI1_COMP4 TIM_TISEL_TI1SEL_2                               /*!< TIM20 input 1 is connected to COMP4_OUT */
00512 #endif /* TIM20 */
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling
00518   * @{
00519   */
00520 #define TIM_SMS_PRELOAD_SOURCE_UPDATE     0x00000000U                            /*!< Prelaod of SMS bitfield is disabled */
00521 #define TIM_SMS_PRELOAD_SOURCE_INDEX      TIM_SMCR_SMSPS                         /*!< Preload of SMS bitfield is enabled  */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
00527   * @{
00528   */
00529 #define TIM_ENCODERINDEX_POSITION_00        0x00000000U                           /*!< Encoder index position is AB=00 */
00530 #define TIM_ENCODERINDEX_POSITION_01        TIM_ECR_IPOS_0                        /*!< Encoder index position is AB=01 */
00531 #define TIM_ENCODERINDEX_POSITION_10        TIM_ECR_IPOS_1                        /*!< Encoder index position is AB=10 */
00532 #define TIM_ENCODERINDEX_POSITION_11        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Encoder index position is AB=11 */
00533 #define TIM_ENCODERINDEX_POSITION_0         0x00000000U                           /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */
00534 #define TIM_ENCODERINDEX_POSITION_1         TIM_ECR_IPOS_0                        /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
00540   * @{
00541   */
00542 #define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U        /*!< Index resets the counter whatever the direction  */
00543 #define TIM_ENCODERINDEX_DIRECTION_UP      TIM_ECR_IDIR_0     /*!< Index resets the counter when up-counting only   */
00544 #define TIM_ENCODERINDEX_DIRECTION_DOWN    TIM_ECR_IDIR_1     /*!< Index resets the counter when down-counting only */
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
00550   * @{
00551   */
00552 #define TIM_ENCODERINDEX_POLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
00553 #define TIM_ENCODERINDEX_POLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler
00559   * @{
00560   */
00561 #define TIM_ENCODERINDEX_PRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
00562 #define TIM_ENCODERINDEX_PRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00563 #define TIM_ENCODERINDEX_PRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00564 #define TIM_ENCODERINDEX_PRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00565 /**
00566   * @}
00567   */
00568
00569 /**
00570   * @}
00571   */
00572 /* End of exported constants -------------------------------------------------*/
00573
00574 /* Exported macro ------------------------------------------------------------*/
00575 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00576   * @{
00577   */
00578
00579 /**
00580   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
00581   * @note   ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
00582   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00583   * @param  __CNTCLK__ counter clock frequency (in Hz)
00584   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
00585   */
00586 #define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
00587   ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
00588
00589 /**
00590   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
00591   * @note   ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
00592   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00593   * @param  __PSC__ prescaler
00594   * @param  __FREQ__ output signal frequency (in Hz)
00595   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
00596   */
00597 #define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
00598   (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
00599
00600 /**
00601   * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
00602   *         output signal frequency.
00603   * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
00604   * @note   This macro should be used only if dithering is already enabled
00605   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00606   * @param  __PSC__ prescaler
00607   * @param  __FREQ__ output signal frequency (in Hz)
00608   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65519)
00609   */
00610 #define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
00611   (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
00612   (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U
00613
00614 /**
00615   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
00616   *         active/inactive delay.
00617   * @note   ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
00618   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00619   * @param  __PSC__ prescaler
00620   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00621   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
00622   */
00623 #define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__)  \
00624   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
00625               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
00626
00627 /**
00628   * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
00629   *         output compare active/inactive delay.
00630   * @note   ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
00631   * @note   This macro should be used only if dithering is already enabled
00632   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00633   * @param  __PSC__ prescaler
00634   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00635   * @retval Compare value  (between Min_Data=0 and Max_Data=65519)
00636   */
00637 #define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
00638   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
00639               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
00640
00641 /**
00642   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
00643   *        (when the timer operates in one pulse mode).
00644   * @note   ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
00645   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00646   * @param  __PSC__ prescaler
00647   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00648   * @param  __PULSE__ pulse duration (in us)
00649   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
00650   */
00651 #define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
00652   ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
00653               + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
00654
00655 /**
00656   * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
00657   *         pulse duration (when the timer operates in one pulse mode).
00658   * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
00659   * @note   This macro should be used only if dithering is already enabled
00660   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00661   * @param  __PSC__ prescaler
00662   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00663   * @param  __PULSE__ pulse duration (in us)
00664   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65519)
00665   */
00666 #define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
00667   ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
00668               + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
00669
00670 /**
00671   * @}
00672   */
00673 /* End of exported macro -----------------------------------------------------*/
00674
00675 /* Private macro -------------------------------------------------------------*/
00676 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00677   * @{
00678   */
00679 #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
00680
00681 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00682                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00683
00684 #if defined (COMP5) && defined (COMP6) && defined (COMP7)
00685 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00686                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00687                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00688                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
00689                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \
00690                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \
00691                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \
00692                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7))
00693
00694
00695 #else
00696 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00697                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00698                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00699                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
00700                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))
00701
00702 #endif /* COMP5 && COMP6 && COMP7 */
00703 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00704                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00705
00706 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00707                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00708
00709 #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
00710
00711 #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
00712   (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
00713
00714 #if defined(TIM5) && defined(TIM20)
00715 #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
00716   ((((INSTANCE) == TIM1) &&                  \
00717     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00718      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00719      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00720      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00721      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00722      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00723      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00724      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00725      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00726      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00727      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00728      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00729      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00730      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00731      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00732      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00733    ||                                        \
00734    (((INSTANCE) == TIM2) &&                  \
00735     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00736      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00737      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00738      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00739      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00740      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00741      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00742      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00743      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00744      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00745      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00746      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00747      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00748      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00749      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00750      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
00751      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
00752    ||                                        \
00753    (((INSTANCE) == TIM3) &&                  \
00754     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00755      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00756      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00757      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00758      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00759      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00760      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00761      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00762      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00763      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00764      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00765      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00766      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00767      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00768      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00769      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00770    ||                                        \
00771    (((INSTANCE) == TIM4) &&                  \
00772     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00773      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00774      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00775      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00776      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00777      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00778      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00779      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00780      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00781      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00782      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00783      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00784      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00785      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00786      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00787      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00788    ||                                        \
00789    (((INSTANCE) == TIM5) &&                  \
00790     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00791      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00792      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00793      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00794      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00795      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00796      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00797      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00798      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00799      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00800      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00801      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00802      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00803      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00804      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00805      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00806    ||                                        \
00807    (((INSTANCE) == TIM8) &&                  \
00808     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00809      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00810      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00811      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00812      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00813      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00814      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00815      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00816      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00817      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00818      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00819      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00820      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00821      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00822      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00823      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00824    ||                                        \
00825    (((INSTANCE) == TIM15) &&                 \
00826     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00827      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00828      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00829      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00830      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00831      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00832      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00833      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00834      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00835      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00836      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00837      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00838      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
00839      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))            \
00840    ||                                        \
00841    (((INSTANCE) == TIM20) &&                 \
00842     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
00843      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
00844      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
00845      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
00846      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
00847      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
00848      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
00849      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
00850      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
00851      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
00852      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
00853      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
00854      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
00855      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
00856      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
00857      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))))
00858
00859 #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
00860   ((((INSTANCE) == TIM1) &&                  \
00861     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00862      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00863      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00864      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00865      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00866      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00867      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00868      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00869      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00870      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00871      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00872      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00873      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00874      ((__SELECTION__) == TIM_TS_ITR10)))             \
00875    ||                                        \
00876    (((INSTANCE) == TIM2) &&                  \
00877     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00878      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00879      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00880      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00881      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00882      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00883      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00884      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00885      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00886      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00887      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00888      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00889      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00890      ((__SELECTION__) == TIM_TS_ITR10)   ||          \
00891      ((__SELECTION__) == TIM_TS_ITR11)))             \
00892    ||                                        \
00893    (((INSTANCE) == TIM3) &&                  \
00894     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00895      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00896      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00897      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00898      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00899      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00900      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00901      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00902      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00903      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00904      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00905      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00906      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00907      ((__SELECTION__) == TIM_TS_ITR10)))             \
00908    ||                                        \
00909    (((INSTANCE) == TIM4) &&                  \
00910     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00911      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00912      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00913      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00914      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00915      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00916      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00917      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00918      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00919      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00920      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00921      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00922      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00923      ((__SELECTION__) == TIM_TS_ITR10)))             \
00924    ||                                        \
00925    (((INSTANCE) == TIM5) &&                  \
00926     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00927      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00928      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00929      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00930      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00931      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00932      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00933      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00934      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00935      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00936      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00937      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00938      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00939      ((__SELECTION__) == TIM_TS_ITR10)))             \
00940    ||                                        \
00941    (((INSTANCE) == TIM8) &&                  \
00942     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00943      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00944      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00945      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00946      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00947      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00948      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00949      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00950      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00951      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00952      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00953      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00954      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00955      ((__SELECTION__) == TIM_TS_ITR10)))             \
00956    ||                                        \
00957    (((INSTANCE) == TIM15) &&                 \
00958     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00959      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00960      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00961      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00962      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00963      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00964      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00965      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00966      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00967      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00968      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00969      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
00970      ((__SELECTION__) == TIM_TS_ITR10)))             \
00971    ||                                        \
00972    (((INSTANCE) == TIM20) &&                 \
00973     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
00974      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
00975      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
00976      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
00977      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
00978      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
00979      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
00980      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
00981      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
00982      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
00983      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
00984      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
00985      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
00986      ((__SELECTION__) == TIM_TS_ITR10))))
00987
00988 #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
00989   ((((INSTANCE) == TIM1) &&                  \
00990     (((__SELECTION__) == TIM_TS_ITR1) ||          \
00991      ((__SELECTION__) == TIM_TS_ITR2) ||          \
00992      ((__SELECTION__) == TIM_TS_ITR3) ||          \
00993      ((__SELECTION__) == TIM_TS_ITR4) ||          \
00994      ((__SELECTION__) == TIM_TS_ITR5) ||          \
00995      ((__SELECTION__) == TIM_TS_ITR6) ||          \
00996      ((__SELECTION__) == TIM_TS_ITR7) ||          \
00997      ((__SELECTION__) == TIM_TS_ITR8) ||          \
00998      ((__SELECTION__) == TIM_TS_ITR9) ||          \
00999      ((__SELECTION__) == TIM_TS_ITR10)||          \
01000      ((__SELECTION__) == TIM_TS_NONE)))           \
01001    ||                                        \
01002    (((INSTANCE) == TIM2) &&                  \
01003     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01004      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01005      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01006      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01007      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01008      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01009      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01010      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01011      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01012      ((__SELECTION__) == TIM_TS_ITR10)||          \
01013      ((__SELECTION__) == TIM_TS_ITR11)||          \
01014      ((__SELECTION__) == TIM_TS_NONE)))           \
01015    ||                                        \
01016    (((INSTANCE) == TIM3) &&                  \
01017     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01018      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01019      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01020      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01021      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01022      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01023      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01024      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01025      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01026      ((__SELECTION__) == TIM_TS_ITR10)||          \
01027      ((__SELECTION__) == TIM_TS_NONE)))           \
01028    ||                                        \
01029    (((INSTANCE) == TIM4) &&                  \
01030     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01031      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01032      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01033      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01034      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01035      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01036      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01037      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01038      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01039      ((__SELECTION__) == TIM_TS_ITR10)||          \
01040      ((__SELECTION__) == TIM_TS_NONE)))           \
01041    ||                                        \
01042    (((INSTANCE) == TIM5) &&                  \
01043     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01044      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01045      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01046      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01047      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01048      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01049      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01050      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01051      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01052      ((__SELECTION__) == TIM_TS_ITR10)||          \
01053      ((__SELECTION__) == TIM_TS_NONE)))           \
01054    ||                                        \
01055    (((INSTANCE) == TIM8) &&                  \
01056     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01057      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01058      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01059      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01060      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01061      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01062      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01063      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01064      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01065      ((__SELECTION__) == TIM_TS_ITR10)||          \
01066      ((__SELECTION__) == TIM_TS_NONE)))           \
01067    ||                                        \
01068    (((INSTANCE) == TIM15) &&                 \
01069     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01070      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01071      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01072      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01073      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01074      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01075      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01076      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01077      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01078      ((__SELECTION__) == TIM_TS_ITR10)||          \
01079      ((__SELECTION__) == TIM_TS_NONE)))           \
01080    ||                                        \
01081    (((INSTANCE) == TIM20) &&                 \
01082     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01083      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01084      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01085      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01086      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01087      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01088      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01089      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01090      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01091      ((__SELECTION__) == TIM_TS_ITR10)||          \
01092      ((__SELECTION__) == TIM_TS_NONE))))
01093
01094 #elif defined(TIM5)
01095 #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
01096   ((((INSTANCE) == TIM1) &&                  \
01097     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01098      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01099      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01100      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01101      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01102      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01103      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01104      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01105      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01106      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01107      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01108      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01109      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01110      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01111    ||                                        \
01112    (((INSTANCE) == TIM2) &&                  \
01113     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01114      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01115      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01116      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01117      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01118      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01119      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01120      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01121      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01122      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01123      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01124      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01125      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01126      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01127      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
01128    ||                                        \
01129    (((INSTANCE) == TIM3) &&                  \
01130     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01131      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01132      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01133      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01134      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01135      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01136      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01137      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01138      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01139      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01140      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01141      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01142      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01143      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01144    ||                                        \
01145    (((INSTANCE) == TIM4) &&                  \
01146     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01147      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01148      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01149      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01150      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01151      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01152      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01153      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01154      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01155      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01156      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01157      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01158      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01159      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01160    ||                                        \
01161    (((INSTANCE) == TIM5) &&                  \
01162     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01163      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01164      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01165      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01166      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01167      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01168      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01169      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01170      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01171      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01172      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01173      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01174      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01175      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01176    ||                                        \
01177    (((INSTANCE) == TIM8) &&                  \
01178     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01179      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01180      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01181      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01182      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01183      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01184      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01185      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01186      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01187      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01188      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01189      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01190      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01191      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01192    ||                                        \
01193    (((INSTANCE) == TIM15) &&                 \
01194     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01195      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01196      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01197      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01198      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01199      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01200      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01201      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01202      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
01203      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01204      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01205      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
01206
01207 #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
01208   ((((INSTANCE) == TIM1) &&                  \
01209     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01210      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01211      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01212      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01213      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01214      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01215      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01216      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01217      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01218      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01219      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01220      ((__SELECTION__) == TIM_TS_ITR8)))             \
01221    ||                                        \
01222    (((INSTANCE) == TIM2) &&                  \
01223     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01224      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01225      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01226      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01227      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01228      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01229      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01230      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01231      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01232      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01233      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01234      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01235      ((__SELECTION__) == TIM_TS_ITR11)))             \
01236    ||                                        \
01237    (((INSTANCE) == TIM3) &&                  \
01238     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01239      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01240      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01241      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01242      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01243      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01244      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01245      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01246      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01247      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01248      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01249      ((__SELECTION__) == TIM_TS_ITR8)))             \
01250    ||                                        \
01251    (((INSTANCE) == TIM4) &&                  \
01252     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01253      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01254      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01255      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01256      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01257      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01258      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01259      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01260      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01261      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01262      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01263      ((__SELECTION__) == TIM_TS_ITR8)))             \
01264    ||                                        \
01265    (((INSTANCE) == TIM5) &&                  \
01266     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01267      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01268      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01269      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01270      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01271      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01272      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01273      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01274      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01275      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01276      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01277      ((__SELECTION__) == TIM_TS_ITR8)))             \
01278    ||                                        \
01279    (((INSTANCE) == TIM8) &&                  \
01280     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01281      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01282      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01283      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01284      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01285      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01286      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01287      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01288      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01289      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01290      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01291      ((__SELECTION__) == TIM_TS_ITR8)))             \
01292    ||                                        \
01293    (((INSTANCE) == TIM15) &&                 \
01294     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01295      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01296      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01297      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01298      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01299      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01300      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01301      ((__SELECTION__) == TIM_TS_ITR4)    ||          \
01302      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01303      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01304      ((__SELECTION__) == TIM_TS_ITR8))))
01305
01306 #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
01307   ((((INSTANCE) == TIM1) &&                  \
01308     (((__SELECTION__) == TIM_TS_ITR1) ||          \
01309      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01310      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01311      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01312      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01313      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01314      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01315      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01316      ((__SELECTION__) == TIM_TS_NONE)))           \
01317    ||                                        \
01318    (((INSTANCE) == TIM2) &&                  \
01319     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01320      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01321      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01322      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01323      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01324      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01325      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01326      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01327      ((__SELECTION__) == TIM_TS_ITR11)||          \
01328      ((__SELECTION__) == TIM_TS_NONE)))           \
01329    ||                                        \
01330    (((INSTANCE) == TIM3) &&                  \
01331     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01332      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01333      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01334      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01335      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01336      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01337      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01338      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01339      ((__SELECTION__) == TIM_TS_NONE)))           \
01340    ||                                        \
01341    (((INSTANCE) == TIM4) &&                  \
01342     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01343      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01344      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01345      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01346      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01347      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01348      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01349      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01350      ((__SELECTION__) == TIM_TS_NONE)))           \
01351    ||                                        \
01352    (((INSTANCE) == TIM5) &&                  \
01353     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01354      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01355      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01356      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01357      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01358      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01359      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01360      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01361      ((__SELECTION__) == TIM_TS_NONE)))           \
01362    ||                                        \
01363    (((INSTANCE) == TIM8) &&                  \
01364     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01365      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01366      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01367      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01368      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01369      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01370      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01371      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01372      ((__SELECTION__) == TIM_TS_NONE)))           \
01373    ||                                        \
01374    (((INSTANCE) == TIM15) &&                 \
01375     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01376      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01377      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01378      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01379      ((__SELECTION__) == TIM_TS_ITR4) ||          \
01380      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01381      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01382      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01383      ((__SELECTION__) == TIM_TS_NONE))))
01384 #elif defined(TIM20)
01385 #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
01386   ((((INSTANCE) == TIM1) &&                  \
01387     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01388      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01389      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01390      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01391      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01392      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01393      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01394      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01395      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01396      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01397      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01398      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01399      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01400      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
01401    ||                                        \
01402    (((INSTANCE) == TIM2) &&                  \
01403     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01404      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01405      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01406      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01407      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01408      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01409      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01410      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01411      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01412      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01413      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01414      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01415      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01416      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
01417      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
01418    ||                                        \
01419    (((INSTANCE) == TIM3) &&                  \
01420     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01421      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01422      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01423      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01424      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01425      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01426      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01427      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01428      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01429      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01430      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01431      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01432      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01433      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
01434    ||                                        \
01435    (((INSTANCE) == TIM4) &&                  \
01436     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01437      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01438      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01439      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01440      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01441      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01442      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01443      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01444      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01445      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01446      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01447      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01448      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01449      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
01450    ||                                        \
01451    (((INSTANCE) == TIM8) &&                  \
01452     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01453      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01454      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01455      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01456      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01457      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01458      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01459      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01460      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01461      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01462      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01463      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01464      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01465      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
01466    ||                                        \
01467    (((INSTANCE) == TIM15) &&                 \
01468     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01469      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01470      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01471      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01472      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01473      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01474      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01475      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01476      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01477      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01478      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01479      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)))            \
01480    ||                                        \
01481    (((INSTANCE) == TIM20) &&                 \
01482     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01483      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01484      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01485      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01486      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01487      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01488      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01489      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01490      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01491      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01492      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01493      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01494      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01495      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
01496
01497 #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
01498   ((((INSTANCE) == TIM1) &&                  \
01499     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01500      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01501      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01502      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01503      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01504      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01505      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01506      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01507      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01508      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01509      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01510      ((__SELECTION__) == TIM_TS_ITR9)))             \
01511    ||                                        \
01512    (((INSTANCE) == TIM2) &&                  \
01513     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01514      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01515      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01516      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01517      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01518      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01519      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01520      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01521      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01522      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01523      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01524      ((__SELECTION__) == TIM_TS_ITR9)    ||          \
01525      ((__SELECTION__) == TIM_TS_ITR11)))             \
01526    ||                                        \
01527    (((INSTANCE) == TIM3) &&                  \
01528     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01529      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01530      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01531      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01532      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01533      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01534      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01535      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01536      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01537      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01538      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01539      ((__SELECTION__) == TIM_TS_ITR9)))             \
01540    ||                                        \
01541    (((INSTANCE) == TIM4) &&                  \
01542     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01543      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01544      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01545      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01546      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01547      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01548      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01549      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01550      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01551      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01552      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01553      ((__SELECTION__) == TIM_TS_ITR9)))             \
01554    ||                                       \
01555    (((INSTANCE) == TIM8) &&                  \
01556     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01557      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01558      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01559      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01560      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01561      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01562      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01563      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01564      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01565      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01566      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01567      ((__SELECTION__) == TIM_TS_ITR9)))             \
01568    ||                                        \
01569    (((INSTANCE) == TIM15) &&                 \
01570     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01571      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01572      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01573      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01574      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01575      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01576      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01577      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01578      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01579      ((__SELECTION__) == TIM_TS_ITR8)    ||          \
01580      ((__SELECTION__) == TIM_TS_ITR9)))             \
01581    ||                                        \
01582    (((INSTANCE) == TIM20) &&                 \
01583     (((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
01584      ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
01585      ((__SELECTION__) == TIM_TS_TI2FP2)  ||          \
01586      ((__SELECTION__) == TIM_TS_ETRF)    ||          \
01587      ((__SELECTION__) == TIM_TS_ITR0)    ||          \
01588      ((__SELECTION__) == TIM_TS_ITR1)    ||          \
01589      ((__SELECTION__) == TIM_TS_ITR2)    ||          \
01590      ((__SELECTION__) == TIM_TS_ITR3)    ||          \
01591      ((__SELECTION__) == TIM_TS_ITR5)    ||          \
01592      ((__SELECTION__) == TIM_TS_ITR6)    ||          \
01593      ((__SELECTION__) == TIM_TS_ITR7)    ||          \
01594      ((__SELECTION__) == TIM_TS_ITR8))))
01595
01596 #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
01597   ((((INSTANCE) == TIM1) &&                  \
01598     (((__SELECTION__) == TIM_TS_ITR1) ||          \
01599      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01600      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01601      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01602      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01603      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01604      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01605      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01606      ((__SELECTION__) == TIM_TS_NONE)))           \
01607    ||                                        \
01608    (((INSTANCE) == TIM2) &&                  \
01609     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01610      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01611      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01612      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01613      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01614      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01615      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01616      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01617      ((__SELECTION__) == TIM_TS_ITR11)||          \
01618      ((__SELECTION__) == TIM_TS_NONE)))           \
01619    ||                                        \
01620    (((INSTANCE) == TIM3) &&                  \
01621     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01622      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01623      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01624      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01625      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01626      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01627      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01628      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01629      ((__SELECTION__) == TIM_TS_NONE)))           \
01630    ||                                        \
01631    (((INSTANCE) == TIM4) &&                  \
01632     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01633      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01634      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01635      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01636      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01637      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01638      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01639      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01640      ((__SELECTION__) == TIM_TS_NONE)))           \
01641    ||                                        \
01642    (((INSTANCE) == TIM8) &&                  \
01643     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01644      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01645      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01646      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01647      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01648      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01649      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01650      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01651      ((__SELECTION__) == TIM_TS_NONE)))           \
01652    ||                                        \
01653    (((INSTANCE) == TIM15) &&                 \
01654     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01655      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01656      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01657      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01658      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01659      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01660      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01661      ((__SELECTION__) == TIM_TS_ITR9) ||          \
01662      ((__SELECTION__) == TIM_TS_NONE)))           \
01663    ||                                        \
01664    (((INSTANCE) == TIM20) &&                 \
01665     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01666      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01667      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01668      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01669      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01670      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01671      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01672      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01673      ((__SELECTION__) == TIM_TS_NONE))))
01674 #else
01675 #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
01676   ((((INSTANCE) == TIM1) &&                  \
01677     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01678      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01679      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01680      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01681      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01682      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01683      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01684      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01685      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01686      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01687      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01688      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01689      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01690    ||                                        \
01691    (((INSTANCE) == TIM2) &&                  \
01692     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01693      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01694      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01695      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01696      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01697      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01698      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01699      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01700      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01701      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01702      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01703      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01704      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
01705      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))            \
01706    ||                                        \
01707    (((INSTANCE) == TIM3) &&                  \
01708     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01709      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01710      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01711      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01712      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01713      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01714      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01715      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01716      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01717      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01718      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01719      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01720      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01721    ||                                        \
01722    (((INSTANCE) == TIM4) &&                  \
01723     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01724      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01725      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01726      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01727      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01728      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01729      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01730      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01731      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01732      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01733      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01734      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01735      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01736    ||                                        \
01737    (((INSTANCE) == TIM8) &&                  \
01738     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01739      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
01740      ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
01741      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01742      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01743      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01744      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01745      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01746      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01747      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01748      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
01749      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01750      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))            \
01751    ||                                        \
01752    (((INSTANCE) == TIM15) &&                 \
01753     (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
01754      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
01755      ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
01756      ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
01757      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
01758      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
01759      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
01760      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
01761      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
01762      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
01763      ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
01764
01765 #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
01766   ((((INSTANCE) == TIM1) &&                  \
01767     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01768      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01769      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01770      ((__SELECTION__) == TIM_TS_ETRF)    ||       \
01771      ((__SELECTION__) == TIM_TS_ITR1)    ||       \
01772      ((__SELECTION__) == TIM_TS_ITR2)    ||       \
01773      ((__SELECTION__) == TIM_TS_ITR3)    ||       \
01774      ((__SELECTION__) == TIM_TS_ITR5)    ||       \
01775      ((__SELECTION__) == TIM_TS_ITR6)    ||       \
01776      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01777      ((__SELECTION__) == TIM_TS_ITR8)))          \
01778    ||                                        \
01779    (((INSTANCE) == TIM2) &&                  \
01780     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01781      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01782      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01783      ((__SELECTION__) == TIM_TS_ETRF)    ||       \
01784      ((__SELECTION__) == TIM_TS_ITR0)    ||       \
01785      ((__SELECTION__) == TIM_TS_ITR2)    ||       \
01786      ((__SELECTION__) == TIM_TS_ITR3)    ||       \
01787      ((__SELECTION__) == TIM_TS_ITR5)    ||       \
01788      ((__SELECTION__) == TIM_TS_ITR6)    ||       \
01789      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01790      ((__SELECTION__) == TIM_TS_ITR8)    ||       \
01791      ((__SELECTION__) == TIM_TS_ITR11)))          \
01792    ||                                        \
01793    (((INSTANCE) == TIM3) &&                  \
01794     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01795      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01796      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01797      ((__SELECTION__) == TIM_TS_ETRF)    ||       \
01798      ((__SELECTION__) == TIM_TS_ITR0)    ||       \
01799      ((__SELECTION__) == TIM_TS_ITR1)    ||       \
01800      ((__SELECTION__) == TIM_TS_ITR3)    ||       \
01801      ((__SELECTION__) == TIM_TS_ITR5)    ||       \
01802      ((__SELECTION__) == TIM_TS_ITR6)    ||       \
01803      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01804      ((__SELECTION__) == TIM_TS_ITR8)))          \
01805    ||                                        \
01806    (((INSTANCE) == TIM4) &&                  \
01807     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01808      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01809      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01810      ((__SELECTION__) == TIM_TS_ETRF)    ||       \
01811      ((__SELECTION__) == TIM_TS_ITR0)    ||       \
01812      ((__SELECTION__) == TIM_TS_ITR1)    ||       \
01813      ((__SELECTION__) == TIM_TS_ITR2)    ||       \
01814      ((__SELECTION__) == TIM_TS_ITR5)    ||       \
01815      ((__SELECTION__) == TIM_TS_ITR6)    ||       \
01816      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01817      ((__SELECTION__) == TIM_TS_ITR8)))          \
01818    ||                                        \
01819    (((INSTANCE) == TIM8) &&                  \
01820     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01821      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01822      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01823      ((__SELECTION__) == TIM_TS_ETRF)    ||       \
01824      ((__SELECTION__) == TIM_TS_ITR0)    ||       \
01825      ((__SELECTION__) == TIM_TS_ITR1)    ||       \
01826      ((__SELECTION__) == TIM_TS_ITR2)    ||       \
01827      ((__SELECTION__) == TIM_TS_ITR3)    ||       \
01828      ((__SELECTION__) == TIM_TS_ITR6)    ||       \
01829      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01830      ((__SELECTION__) == TIM_TS_ITR8)))          \
01831    ||                                        \
01832    (((INSTANCE) == TIM15) &&                 \
01833     (((__SELECTION__) == TIM_TS_TI1F_ED) ||       \
01834      ((__SELECTION__) == TIM_TS_TI1FP1)  ||       \
01835      ((__SELECTION__) == TIM_TS_TI2FP2)  ||       \
01836      ((__SELECTION__) == TIM_TS_ITR0)    ||       \
01837      ((__SELECTION__) == TIM_TS_ITR1)    ||       \
01838      ((__SELECTION__) == TIM_TS_ITR2)    ||       \
01839      ((__SELECTION__) == TIM_TS_ITR3)    ||       \
01840      ((__SELECTION__) == TIM_TS_ITR5)    ||       \
01841      ((__SELECTION__) == TIM_TS_ITR7)    ||       \
01842      ((__SELECTION__) == TIM_TS_ITR8))))
01843
01844 #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
01845   ((((INSTANCE) == TIM1) &&                  \
01846     (((__SELECTION__) == TIM_TS_ITR1) ||          \
01847      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01848      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01849      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01850      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01851      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01852      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01853      ((__SELECTION__) == TIM_TS_NONE)))           \
01854    ||                                        \
01855    (((INSTANCE) == TIM2) &&                  \
01856     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01857      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01858      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01859      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01860      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01861      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01862      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01863      ((__SELECTION__) == TIM_TS_ITR11)||          \
01864      ((__SELECTION__) == TIM_TS_NONE)))           \
01865    ||                                        \
01866    (((INSTANCE) == TIM3) &&                  \
01867     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01868      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01869      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01870      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01871      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01872      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01873      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01874      ((__SELECTION__) == TIM_TS_NONE)))           \
01875    ||                                        \
01876    (((INSTANCE) == TIM4) &&                  \
01877     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01878      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01879      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01880      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01881      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01882      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01883      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01884      ((__SELECTION__) == TIM_TS_NONE)))           \
01885    ||                                        \
01886    (((INSTANCE) == TIM8) &&                  \
01887     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01888      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01889      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01890      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01891      ((__SELECTION__) == TIM_TS_ITR6) ||          \
01892      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01893      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01894      ((__SELECTION__) == TIM_TS_NONE)))           \
01895    ||                                        \
01896    (((INSTANCE) == TIM15) &&                 \
01897     (((__SELECTION__) == TIM_TS_ITR0) ||          \
01898      ((__SELECTION__) == TIM_TS_ITR1) ||          \
01899      ((__SELECTION__) == TIM_TS_ITR2) ||          \
01900      ((__SELECTION__) == TIM_TS_ITR3) ||          \
01901      ((__SELECTION__) == TIM_TS_ITR5) ||          \
01902      ((__SELECTION__) == TIM_TS_ITR7) ||          \
01903      ((__SELECTION__) == TIM_TS_ITR8) ||          \
01904      ((__SELECTION__) == TIM_TS_NONE))))
01905
01906 #endif /* TIM5 && TIM20 */
01907
01908 #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__)   \
01909   (IS_TIM_OC_MODE(__MODE__) \
01910    && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
01911        ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1)))
01912
01913 #define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__)  \
01914   (((__CHANNEL__) == TIM_CHANNEL_3) ||    \
01915    ((__CHANNEL__) == TIM_CHANNEL_4))
01916
01917 #define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE)  IS_TIM_CC3_INSTANCE(INSTANCE)
01918
01919 #define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__)    ((__WIDTH__) <= 0xFFU)
01920
01921 #define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__)    ((__PRESCALER__) <= 0x7U)
01922
01923 #define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__)    (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
01924                                                     || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
01925
01926 #define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__)        (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED)  || \
01927                                                            ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
01928
01929 #define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
01930                                                            ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
01931                                                            ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
01932                                                            ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
01933
01934 #define IS_TIM_ENCODERINDEX_FILTER(__FILTER__)            ((__FILTER__) <= 0xFUL)
01935
01936 #define IS_TIM_ENCODERINDEX_POSITION(__POSITION__)        (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
01937                                                            ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
01938                                                            ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
01939                                                            ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
01940                                                            ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0)  || \
01941                                                            ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
01942
01943 #define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__)      (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
01944                                                            ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP)      || \
01945                                                            ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
01946 /**
01947   * @}
01948   */
01949 /* End of private macro ------------------------------------------------------*/
01950
01951 /* Exported functions --------------------------------------------------------*/
01952 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
01953   * @{
01954   */
01955
01956 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
01957   *  @brief    Timer Hall Sensor functions
01958   * @{
01959   */
01960 /*  Timer Hall Sensor functions  **********************************************/
01961 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
01962 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
01963
01964 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
01965 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
01966
01967 /* Blocking mode: Polling */
01968 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
01969 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
01970 /* Non-Blocking mode: Interrupt */
01971 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
01972 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
01973 /* Non-Blocking mode: DMA */
01974 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01975 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
01976 /**
01977   * @}
01978   */
01979
01980 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
01981   *  @brief   Timer Complementary Output Compare functions
01982   * @{
01983   */
01984 /*  Timer Complementary Output Compare functions  *****************************/
01985 /* Blocking mode: Polling */
01986 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01987 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01988
01989 /* Non-Blocking mode: Interrupt */
01990 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01991 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01992
01993 /* Non-Blocking mode: DMA */
01994 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01995                                           uint16_t Length);
01996 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01997 /**
01998   * @}
01999   */
02000
02001 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
02002   *  @brief    Timer Complementary PWM functions
02003   * @{
02004   */
02005 /*  Timer Complementary PWM functions  ****************************************/
02006 /* Blocking mode: Polling */
02007 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02008 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02009
02010 /* Non-Blocking mode: Interrupt */
02011 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02012 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02013 /* Non-Blocking mode: DMA */
02014 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
02015                                            uint16_t Length);
02016 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02017 /**
02018   * @}
02019   */
02020
02021 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
02022   *  @brief    Timer Complementary One Pulse functions
02023   * @{
02024   */
02025 /*  Timer Complementary One Pulse functions  **********************************/
02026 /* Blocking mode: Polling */
02027 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02028 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02029
02030 /* Non-Blocking mode: Interrupt */
02031 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02032 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02033 /**
02034   * @}
02035   */
02036
02037 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
02038   *  @brief    Peripheral Control functions
02039   * @{
02040   */
02041 /* Extended Control functions  ************************************************/
02042 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
02043                                               uint32_t  CommutationSource);
02044 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
02045                                                  uint32_t  CommutationSource);
02046 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
02047                                                   uint32_t  CommutationSource);
02048 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
02049                                                         const TIM_MasterConfigTypeDef *sMasterConfig);
02050 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02051                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
02052 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
02053                                              const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
02054 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
02055 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
02056 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
02057
02058 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
02059 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
02060 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
02061 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
02062 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
02063                                                     uint32_t PulseWidth);
02064 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
02065 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
02066 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
02067 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
02068 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
02069 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
02070 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
02071 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
02072 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
02073 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
02074                                                TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
02075 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
02076 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
02077 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
02078 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
02079 /**
02080   * @}
02081   */
02082
02083 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02084   * @brief    Extended Callbacks functions
02085   * @{
02086   */
02087 /* Extended Callback **********************************************************/
02088 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
02089 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
02090 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
02091 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
02092 void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
02093 void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
02094 void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
02095 void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
02096 /**
02097   * @}
02098   */
02099
02100 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02101   * @brief    Extended Peripheral State functions
02102   * @{
02103   */
02104 /* Extended Peripheral State functions  ***************************************/
02105 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
02106 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
02107 /**
02108   * @}
02109   */
02110
02111 /**
02112   * @}
02113   */
02114 /* End of exported functions -------------------------------------------------*/
02115
02116 /* Private functions----------------------------------------------------------*/
02117 /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
02118   * @{
02119   */
02120 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
02121 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
02122 /**
02123   * @}
02124   */
02125 /* End of private functions --------------------------------------------------*/
02126
02127 /**
02128   * @}
02129   */
02130
02131 /**
02132   * @}
02133   */
02134
02135 #ifdef __cplusplus
02136 }
02137 #endif
02138
02139
02140 #endif /* STM32G4xx_HAL_TIM_EX_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_uart.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @brief   UART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2019 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025  ===============================================================================
00026                         ##### How to use this driver #####
00027  ===============================================================================
00028   [..]
00029     The UART HAL driver can be used as follows:
00030
00031     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00032     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00033         (++) Enable the USARTx interface clock.
00034         (++) UART pins configuration:
00035             (+++) Enable the clock for the UART GPIOs.
00036             (+++) Configure these UART pins as alternate function pull-up.
00037         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00038              and HAL_UART_Receive_IT() APIs):
00039             (+++) Configure the USARTx interrupt priority.
00040             (+++) Enable the NVIC USART IRQ handle.
00041         (++) UART interrupts handling:
00042               -@@-  The specific UART interrupts (Transmission complete interrupt,
00043                 RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
00044                 are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
00045                 inside the transmit and receive processes.
00046         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00047              and HAL_UART_Receive_DMA() APIs):
00048             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00049             (+++) Enable the DMAx interface clock.
00050             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00051             (+++) Configure the DMA Tx/Rx channel.
00052             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00053             (+++) Configure the priority and enable the NVIC for the transfer complete
00054                   interrupt on the DMA Tx/Rx channel.
00055
00056     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
00057         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00058
00059     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00060         in the huart handle AdvancedInit structure.
00061
00062     (#) For the UART asynchronous mode, initialize the UART registers by calling
00063         the HAL_UART_Init() API.
00064
00065     (#) For the UART Half duplex mode, initialize the UART registers by calling
00066         the HAL_HalfDuplex_Init() API.
00067
00068     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00069         by calling the HAL_LIN_Init() API.
00070
00071     (#) For the UART Multiprocessor mode, initialize the UART registers
00072         by calling the HAL_MultiProcessor_Init() API.
00073
00074     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00075         by calling the HAL_RS485Ex_Init() API.
00076
00077     [..]
00078     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00079         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00080         calling the customized HAL_UART_MspInit() API.
00081
00082     ##### Callback registration #####
00083     ==================================
00084
00085     [..]
00086     The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
00087     allows the user to configure dynamically the driver callbacks.
00088
00089     [..]
00090     Use Function HAL_UART_RegisterCallback() to register a user callback.
00091     Function HAL_UART_RegisterCallback() allows to register following callbacks:
00092     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00093     (+) TxCpltCallback            : Tx Complete Callback.
00094     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00095     (+) RxCpltCallback            : Rx Complete Callback.
00096     (+) ErrorCallback             : Error Callback.
00097     (+) AbortCpltCallback         : Abort Complete Callback.
00098     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00099     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00100     (+) WakeupCallback            : Wakeup Callback.
00101     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00102     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00103     (+) MspInitCallback           : UART MspInit.
00104     (+) MspDeInitCallback         : UART MspDeInit.
00105     This function takes as parameters the HAL peripheral handle, the Callback ID
00106     and a pointer to the user callback function.
00107
00108     [..]
00109     Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
00110     weak function.
00111     HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00112     and the Callback ID.
00113     This function allows to reset following callbacks:
00114     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00115     (+) TxCpltCallback            : Tx Complete Callback.
00116     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00117     (+) RxCpltCallback            : Rx Complete Callback.
00118     (+) ErrorCallback             : Error Callback.
00119     (+) AbortCpltCallback         : Abort Complete Callback.
00120     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00121     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00122     (+) WakeupCallback            : Wakeup Callback.
00123     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00124     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00125     (+) MspInitCallback           : UART MspInit.
00126     (+) MspDeInitCallback         : UART MspDeInit.
00127
00128     [..]
00129     For specific callback RxEventCallback, use dedicated registration/reset functions:
00130     respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
00131
00132     [..]
00133     By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
00134     all callbacks are set to the corresponding weak functions:
00135     examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
00136     Exception done for MspInit and MspDeInit functions that are respectively
00137     reset to the legacy weak functions in the HAL_UART_Init()
00138     and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
00139     If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
00140     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00141
00142     [..]
00143     Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
00144     Exception done MspInit/MspDeInit that can be registered/unregistered
00145     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
00146     MspInit/DeInit callbacks can be used during the Init/DeInit.
00147     In that case first register the MspInit/MspDeInit user callbacks
00148     using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
00149     or HAL_UART_Init() function.
00150
00151     [..]
00152     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
00153     not defined, the callback registration feature is not available
00154     and weak callbacks are used.
00155
00156
00157   @endverbatim
00158   ******************************************************************************
00159   */
00160
00161 /* Includes ------------------------------------------------------------------*/
00162 #include "stm32g4xx_hal.h"
00163
00164 /** @addtogroup STM32G4xx_HAL_Driver
00165   * @{
00166   */
00167
00168 /** @defgroup UART UART
00169   * @brief HAL UART module driver
00170   * @{
00171   */
00172
00173 #ifdef HAL_UART_MODULE_ENABLED
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @defgroup UART_Private_Constants UART Private Constants
00178   * @{
00179   */
00180 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
00181                                       USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00182
00183 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
00184                                       USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
00185
00186 #define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
00187 #define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
00188
00189 #define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
00190 #define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
00191 /**
00192   * @}
00193   */
00194
00195 /* Private macros ------------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @addtogroup UART_Private_Functions
00198   * @{
00199   */
00200 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00201 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00202 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00203 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00204 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00205 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00206 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00207 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00208 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00209 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00210 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00211 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00212 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
00213 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
00214 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00215 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00216 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00217 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
00218 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
00219 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00220 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00221 /**
00222   * @}
00223   */
00224
00225 /* Private variables ---------------------------------------------------------*/
00226 /** @addtogroup UART_Private_variables
00227   * @{
00228   */
00229 const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
00230 /**
00231   * @}
00232   */
00233
00234 /* Exported Constants --------------------------------------------------------*/
00235 /* Exported functions --------------------------------------------------------*/
00236
00237 /** @defgroup UART_Exported_Functions UART Exported Functions
00238   * @{
00239   */
00240
00241 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00242   *  @brief    Initialization and Configuration functions
00243   *
00244 @verbatim
00245 ===============================================================================
00246             ##### Initialization and Configuration functions #####
00247  ===============================================================================
00248     [..]
00249     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00250     in asynchronous mode.
00251       (+) For the asynchronous mode the parameters below can be configured:
00252         (++) Baud Rate
00253         (++) Word Length
00254         (++) Stop Bit
00255         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00256              in the data register is transmitted but is changed by the parity bit.
00257         (++) Hardware flow control
00258         (++) Receiver/transmitter modes
00259         (++) Over Sampling Method
00260         (++) One-Bit Sampling Method
00261       (+) For the asynchronous mode, the following advanced features can be configured as well:
00262         (++) TX and/or RX pin level inversion
00263         (++) data logical level inversion
00264         (++) RX and TX pins swap
00265         (++) RX overrun detection disabling
00266         (++) DMA disabling on RX error
00267         (++) MSB first on communication line
00268         (++) auto Baud rate detection
00269     [..]
00270     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00271     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00272     and UART multiprocessor mode configuration procedures (details for the procedures
00273     are available in reference manual).
00274
00275 @endverbatim
00276
00277   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00278   8-bit or 9-bit), the possible UART formats are listed in the
00279   following table.
00280
00281   Table 1. UART frame format.
00282     +-----------------------------------------------------------------------+
00283     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00284     |---------|---------|-----------|---------------------------------------|
00285     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00286     |---------|---------|-----------|---------------------------------------|
00287     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00288     |---------|---------|-----------|---------------------------------------|
00289     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00290     |---------|---------|-----------|---------------------------------------|
00291     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00292     |---------|---------|-----------|---------------------------------------|
00293     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00294     |---------|---------|-----------|---------------------------------------|
00295     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00296     +-----------------------------------------------------------------------+
00297
00298   * @{
00299   */
00300
00301 /**
00302   * @brief Initialize the UART mode according to the specified
00303   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00304   * @param huart UART handle.
00305   * @retval HAL status
00306   */
00307 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00308 {
00309   /* Check the UART handle allocation */
00310   if (huart == NULL)
00311   {
00312     return HAL_ERROR;
00313   }
00314
00315   if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00316   {
00317     /* Check the parameters */
00318     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00319   }
00320   else
00321   {
00322     /* Check the parameters */
00323     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00324   }
00325
00326   if (huart->gState == HAL_UART_STATE_RESET)
00327   {
00328     /* Allocate lock resource and initialize it */
00329     huart->Lock = HAL_UNLOCKED;
00330
00331 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00332     UART_InitCallbacksToDefault(huart);
00333
00334     if (huart->MspInitCallback == NULL)
00335     {
00336       huart->MspInitCallback = HAL_UART_MspInit;
00337     }
00338
00339     /* Init the low level hardware */
00340     huart->MspInitCallback(huart);
00341 #else
00342     /* Init the low level hardware : GPIO, CLOCK */
00343     HAL_UART_MspInit(huart);
00344 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00345   }
00346
00347   huart->gState = HAL_UART_STATE_BUSY;
00348
00349   __HAL_UART_DISABLE(huart);
00350
00351   /* Perform advanced settings configuration */
00352   /* For some items, configuration requires to be done prior TE and RE bits are set */
00353   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00354   {
00355     UART_AdvFeatureConfig(huart);
00356   }
00357
00358   /* Set the UART Communication parameters */
00359   if (UART_SetConfig(huart) == HAL_ERROR)
00360   {
00361     return HAL_ERROR;
00362   }
00363
00364   /* In asynchronous mode, the following bits must be kept cleared:
00365   - LINEN and CLKEN bits in the USART_CR2 register,
00366   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00367   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00368   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00369
00370   __HAL_UART_ENABLE(huart);
00371
00372   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00373   return (UART_CheckIdleState(huart));
00374 }
00375
00376 /**
00377   * @brief Initialize the half-duplex mode according to the specified
00378   *        parameters in the UART_InitTypeDef and creates the associated handle.
00379   * @param huart UART handle.
00380   * @retval HAL status
00381   */
00382 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00383 {
00384   /* Check the UART handle allocation */
00385   if (huart == NULL)
00386   {
00387     return HAL_ERROR;
00388   }
00389
00390   /* Check UART instance */
00391   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00392
00393   if (huart->gState == HAL_UART_STATE_RESET)
00394   {
00395     /* Allocate lock resource and initialize it */
00396     huart->Lock = HAL_UNLOCKED;
00397
00398 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00399     UART_InitCallbacksToDefault(huart);
00400
00401     if (huart->MspInitCallback == NULL)
00402     {
00403       huart->MspInitCallback = HAL_UART_MspInit;
00404     }
00405
00406     /* Init the low level hardware */
00407     huart->MspInitCallback(huart);
00408 #else
00409     /* Init the low level hardware : GPIO, CLOCK */
00410     HAL_UART_MspInit(huart);
00411 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00412   }
00413
00414   huart->gState = HAL_UART_STATE_BUSY;
00415
00416   __HAL_UART_DISABLE(huart);
00417
00418   /* Perform advanced settings configuration */
00419   /* For some items, configuration requires to be done prior TE and RE bits are set */
00420   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00421   {
00422     UART_AdvFeatureConfig(huart);
00423   }
00424
00425   /* Set the UART Communication parameters */
00426   if (UART_SetConfig(huart) == HAL_ERROR)
00427   {
00428     return HAL_ERROR;
00429   }
00430
00431   /* In half-duplex mode, the following bits must be kept cleared:
00432   - LINEN and CLKEN bits in the USART_CR2 register,
00433   - SCEN and IREN bits in the USART_CR3 register.*/
00434   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00435   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00436
00437   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00438   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00439
00440   __HAL_UART_ENABLE(huart);
00441
00442   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00443   return (UART_CheckIdleState(huart));
00444 }
00445
00446
00447 /**
00448   * @brief Initialize the LIN mode according to the specified
00449   *        parameters in the UART_InitTypeDef and creates the associated handle.
00450   * @param huart             UART handle.
00451   * @param BreakDetectLength Specifies the LIN break detection length.
00452   *        This parameter can be one of the following values:
00453   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00454   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00455   * @retval HAL status
00456   */
00457 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00458 {
00459   /* Check the UART handle allocation */
00460   if (huart == NULL)
00461   {
00462     return HAL_ERROR;
00463   }
00464
00465   /* Check the LIN UART instance */
00466   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00467   /* Check the Break detection length parameter */
00468   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00469
00470   /* LIN mode limited to 16-bit oversampling only */
00471   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
00472   {
00473     return HAL_ERROR;
00474   }
00475   /* LIN mode limited to 8-bit data length */
00476   if (huart->Init.WordLength != UART_WORDLENGTH_8B)
00477   {
00478     return HAL_ERROR;
00479   }
00480
00481   if (huart->gState == HAL_UART_STATE_RESET)
00482   {
00483     /* Allocate lock resource and initialize it */
00484     huart->Lock = HAL_UNLOCKED;
00485
00486 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00487     UART_InitCallbacksToDefault(huart);
00488
00489     if (huart->MspInitCallback == NULL)
00490     {
00491       huart->MspInitCallback = HAL_UART_MspInit;
00492     }
00493
00494     /* Init the low level hardware */
00495     huart->MspInitCallback(huart);
00496 #else
00497     /* Init the low level hardware : GPIO, CLOCK */
00498     HAL_UART_MspInit(huart);
00499 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00500   }
00501
00502   huart->gState = HAL_UART_STATE_BUSY;
00503
00504   __HAL_UART_DISABLE(huart);
00505
00506   /* Perform advanced settings configuration */
00507   /* For some items, configuration requires to be done prior TE and RE bits are set */
00508   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00509   {
00510     UART_AdvFeatureConfig(huart);
00511   }
00512
00513   /* Set the UART Communication parameters */
00514   if (UART_SetConfig(huart) == HAL_ERROR)
00515   {
00516     return HAL_ERROR;
00517   }
00518
00519   /* In LIN mode, the following bits must be kept cleared:
00520   - LINEN and CLKEN bits in the USART_CR2 register,
00521   - SCEN and IREN bits in the USART_CR3 register.*/
00522   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00523   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00524
00525   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00526   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00527
00528   /* Set the USART LIN Break detection length. */
00529   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00530
00531   __HAL_UART_ENABLE(huart);
00532
00533   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00534   return (UART_CheckIdleState(huart));
00535 }
00536
00537
00538 /**
00539   * @brief Initialize the multiprocessor mode according to the specified
00540   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00541   * @param huart        UART handle.
00542   * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
00543   * @param WakeUpMethod Specifies the UART wakeup method.
00544   *        This parameter can be one of the following values:
00545   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00546   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00547   * @note  If the user resorts to idle line detection wake up, the Address parameter
00548   *        is useless and ignored by the initialization function.
00549   * @note  If the user resorts to address mark wake up, the address length detection
00550   *        is configured by default to 4 bits only. For the UART to be able to
00551   *        manage 6-, 7- or 8-bit long addresses detection, the API
00552   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00553   *        HAL_MultiProcessor_Init().
00554   * @retval HAL status
00555   */
00556 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00557 {
00558   /* Check the UART handle allocation */
00559   if (huart == NULL)
00560   {
00561     return HAL_ERROR;
00562   }
00563
00564   /* Check the wake up method parameter */
00565   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00566
00567   if (huart->gState == HAL_UART_STATE_RESET)
00568   {
00569     /* Allocate lock resource and initialize it */
00570     huart->Lock = HAL_UNLOCKED;
00571
00572 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00573     UART_InitCallbacksToDefault(huart);
00574
00575     if (huart->MspInitCallback == NULL)
00576     {
00577       huart->MspInitCallback = HAL_UART_MspInit;
00578     }
00579
00580     /* Init the low level hardware */
00581     huart->MspInitCallback(huart);
00582 #else
00583     /* Init the low level hardware : GPIO, CLOCK */
00584     HAL_UART_MspInit(huart);
00585 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00586   }
00587
00588   huart->gState = HAL_UART_STATE_BUSY;
00589
00590   __HAL_UART_DISABLE(huart);
00591
00592   /* Perform advanced settings configuration */
00593   /* For some items, configuration requires to be done prior TE and RE bits are set */
00594   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00595   {
00596     UART_AdvFeatureConfig(huart);
00597   }
00598
00599   /* Set the UART Communication parameters */
00600   if (UART_SetConfig(huart) == HAL_ERROR)
00601   {
00602     return HAL_ERROR;
00603   }
00604
00605   /* In multiprocessor mode, the following bits must be kept cleared:
00606   - LINEN and CLKEN bits in the USART_CR2 register,
00607   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00608   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00609   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00610
00611   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00612   {
00613     /* If address mark wake up method is chosen, set the USART address node */
00614     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00615   }
00616
00617   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00618   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00619
00620   __HAL_UART_ENABLE(huart);
00621
00622   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00623   return (UART_CheckIdleState(huart));
00624 }
00625
00626
00627 /**
00628   * @brief DeInitialize the UART peripheral.
00629   * @param huart UART handle.
00630   * @retval HAL status
00631   */
00632 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00633 {
00634   /* Check the UART handle allocation */
00635   if (huart == NULL)
00636   {
00637     return HAL_ERROR;
00638   }
00639
00640   /* Check the parameters */
00641   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00642
00643   huart->gState = HAL_UART_STATE_BUSY;
00644
00645   __HAL_UART_DISABLE(huart);
00646
00647   huart->Instance->CR1 = 0x0U;
00648   huart->Instance->CR2 = 0x0U;
00649   huart->Instance->CR3 = 0x0U;
00650
00651 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00652   if (huart->MspDeInitCallback == NULL)
00653   {
00654     huart->MspDeInitCallback = HAL_UART_MspDeInit;
00655   }
00656   /* DeInit the low level hardware */
00657   huart->MspDeInitCallback(huart);
00658 #else
00659   /* DeInit the low level hardware */
00660   HAL_UART_MspDeInit(huart);
00661 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00662
00663   huart->ErrorCode = HAL_UART_ERROR_NONE;
00664   huart->gState = HAL_UART_STATE_RESET;
00665   huart->RxState = HAL_UART_STATE_RESET;
00666   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
00667   huart->RxEventType = HAL_UART_RXEVENT_TC;
00668
00669   __HAL_UNLOCK(huart);
00670
00671   return HAL_OK;
00672 }
00673
00674 /**
00675   * @brief Initialize the UART MSP.
00676   * @param huart UART handle.
00677   * @retval None
00678   */
00679 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00680 {
00681   /* Prevent unused argument(s) compilation warning */
00682   UNUSED(huart);
00683
00684   /* NOTE : This function should not be modified, when the callback is needed,
00685             the HAL_UART_MspInit can be implemented in the user file
00686    */
00687 }
00688
00689 /**
00690   * @brief DeInitialize the UART MSP.
00691   * @param huart UART handle.
00692   * @retval None
00693   */
00694 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00695 {
00696   /* Prevent unused argument(s) compilation warning */
00697   UNUSED(huart);
00698
00699   /* NOTE : This function should not be modified, when the callback is needed,
00700             the HAL_UART_MspDeInit can be implemented in the user file
00701    */
00702 }
00703
00704 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00705 /**
00706   * @brief  Register a User UART Callback
00707   *         To be used to override the weak predefined callback
00708   * @note   The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
00709   *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
00710   *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
00711   * @param  huart uart handle
00712   * @param  CallbackID ID of the callback to be registered
00713   *         This parameter can be one of the following values:
00714   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00715   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00716   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00717   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00718   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00719   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00720   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00721   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00722   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00723   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00724   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00725   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00726   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00727   * @param  pCallback pointer to the Callback function
00728   * @retval HAL status
00729   */
00730 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
00731                                             pUART_CallbackTypeDef pCallback)
00732 {
00733   HAL_StatusTypeDef status = HAL_OK;
00734
00735   if (pCallback == NULL)
00736   {
00737     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00738
00739     return HAL_ERROR;
00740   }
00741
00742   if (huart->gState == HAL_UART_STATE_READY)
00743   {
00744     switch (CallbackID)
00745     {
00746       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00747         huart->TxHalfCpltCallback = pCallback;
00748         break;
00749
00750       case HAL_UART_TX_COMPLETE_CB_ID :
00751         huart->TxCpltCallback = pCallback;
00752         break;
00753
00754       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00755         huart->RxHalfCpltCallback = pCallback;
00756         break;
00757
00758       case HAL_UART_RX_COMPLETE_CB_ID :
00759         huart->RxCpltCallback = pCallback;
00760         break;
00761
00762       case HAL_UART_ERROR_CB_ID :
00763         huart->ErrorCallback = pCallback;
00764         break;
00765
00766       case HAL_UART_ABORT_COMPLETE_CB_ID :
00767         huart->AbortCpltCallback = pCallback;
00768         break;
00769
00770       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00771         huart->AbortTransmitCpltCallback = pCallback;
00772         break;
00773
00774       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00775         huart->AbortReceiveCpltCallback = pCallback;
00776         break;
00777
00778       case HAL_UART_WAKEUP_CB_ID :
00779         huart->WakeupCallback = pCallback;
00780         break;
00781
00782       case HAL_UART_RX_FIFO_FULL_CB_ID :
00783         huart->RxFifoFullCallback = pCallback;
00784         break;
00785
00786       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00787         huart->TxFifoEmptyCallback = pCallback;
00788         break;
00789
00790       case HAL_UART_MSPINIT_CB_ID :
00791         huart->MspInitCallback = pCallback;
00792         break;
00793
00794       case HAL_UART_MSPDEINIT_CB_ID :
00795         huart->MspDeInitCallback = pCallback;
00796         break;
00797
00798       default :
00799         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00800
00801         status =  HAL_ERROR;
00802         break;
00803     }
00804   }
00805   else if (huart->gState == HAL_UART_STATE_RESET)
00806   {
00807     switch (CallbackID)
00808     {
00809       case HAL_UART_MSPINIT_CB_ID :
00810         huart->MspInitCallback = pCallback;
00811         break;
00812
00813       case HAL_UART_MSPDEINIT_CB_ID :
00814         huart->MspDeInitCallback = pCallback;
00815         break;
00816
00817       default :
00818         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00819
00820         status =  HAL_ERROR;
00821         break;
00822     }
00823   }
00824   else
00825   {
00826     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00827
00828     status =  HAL_ERROR;
00829   }
00830
00831   return status;
00832 }
00833
00834 /**
00835   * @brief  Unregister an UART Callback
00836   *         UART callaback is redirected to the weak predefined callback
00837   * @note   The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
00838   *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
00839   *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
00840   * @param  huart uart handle
00841   * @param  CallbackID ID of the callback to be unregistered
00842   *         This parameter can be one of the following values:
00843   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00844   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00845   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00846   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00847   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00848   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00849   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00850   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00851   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00852   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00853   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00854   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00855   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
00859 {
00860   HAL_StatusTypeDef status = HAL_OK;
00861
00862   if (HAL_UART_STATE_READY == huart->gState)
00863   {
00864     switch (CallbackID)
00865     {
00866       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00867         huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
00868         break;
00869
00870       case HAL_UART_TX_COMPLETE_CB_ID :
00871         huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
00872         break;
00873
00874       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00875         huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
00876         break;
00877
00878       case HAL_UART_RX_COMPLETE_CB_ID :
00879         huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
00880         break;
00881
00882       case HAL_UART_ERROR_CB_ID :
00883         huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
00884         break;
00885
00886       case HAL_UART_ABORT_COMPLETE_CB_ID :
00887         huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
00888         break;
00889
00890       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00891         huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
00892                                                                                   AbortTransmitCpltCallback          */
00893         break;
00894
00895       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00896         huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
00897                                                                                   AbortReceiveCpltCallback           */
00898         break;
00899
00900       case HAL_UART_WAKEUP_CB_ID :
00901         huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
00902         break;
00903
00904       case HAL_UART_RX_FIFO_FULL_CB_ID :
00905         huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
00906         break;
00907
00908       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00909         huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
00910         break;
00911
00912       case HAL_UART_MSPINIT_CB_ID :
00913         huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
00914         break;
00915
00916       case HAL_UART_MSPDEINIT_CB_ID :
00917         huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
00918         break;
00919
00920       default :
00921         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00922
00923         status =  HAL_ERROR;
00924         break;
00925     }
00926   }
00927   else if (HAL_UART_STATE_RESET == huart->gState)
00928   {
00929     switch (CallbackID)
00930     {
00931       case HAL_UART_MSPINIT_CB_ID :
00932         huart->MspInitCallback = HAL_UART_MspInit;
00933         break;
00934
00935       case HAL_UART_MSPDEINIT_CB_ID :
00936         huart->MspDeInitCallback = HAL_UART_MspDeInit;
00937         break;
00938
00939       default :
00940         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00941
00942         status =  HAL_ERROR;
00943         break;
00944     }
00945   }
00946   else
00947   {
00948     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00949
00950     status =  HAL_ERROR;
00951   }
00952
00953   return status;
00954 }
00955
00956 /**
00957   * @brief  Register a User UART Rx Event Callback
00958   *         To be used instead of the weak predefined callback
00959   * @param  huart     Uart handle
00960   * @param  pCallback Pointer to the Rx Event Callback function
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
00964 {
00965   HAL_StatusTypeDef status = HAL_OK;
00966
00967   if (pCallback == NULL)
00968   {
00969     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00970
00971     return HAL_ERROR;
00972   }
00973
00974   if (huart->RxState == HAL_UART_STATE_READY)
00975   {
00976     huart->RxEventCallback = pCallback;
00977   }
00978   else
00979   {
00980     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00981
00982     status =  HAL_ERROR;
00983   }
00984
00985   return status;
00986 }
00987
00988 /**
00989   * @brief  UnRegister the UART Rx Event Callback
00990   *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
00991   * @param  huart     Uart handle
00992   * @retval HAL status
00993   */
00994 HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
00995 {
00996   HAL_StatusTypeDef status = HAL_OK;
00997
00998   if (huart->RxState == HAL_UART_STATE_READY)
00999   {
01000     huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
01001   }
01002   else
01003   {
01004     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
01005
01006     status =  HAL_ERROR;
01007   }
01008
01009   return status;
01010 }
01011
01012 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01013
01014 /**
01015   * @}
01016   */
01017
01018 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
01019   * @brief UART Transmit/Receive functions
01020   *
01021 @verbatim
01022  ===============================================================================
01023                       ##### IO operation functions #####
01024  ===============================================================================
01025     This subsection provides a set of functions allowing to manage the UART asynchronous
01026     and Half duplex data transfers.
01027
01028     (#) There are two mode of transfer:
01029        (+) Blocking mode: The communication is performed in polling mode.
01030            The HAL status of all data processing is returned by the same function
01031            after finishing transfer.
01032        (+) Non-Blocking mode: The communication is performed using Interrupts
01033            or DMA, These API's return the HAL status.
01034            The end of the data processing will be indicated through the
01035            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
01036            using DMA mode.
01037            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
01038            will be executed respectively at the end of the transmit or Receive process
01039            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
01040
01041     (#) Blocking mode API's are :
01042         (+) HAL_UART_Transmit()
01043         (+) HAL_UART_Receive()
01044
01045     (#) Non-Blocking mode API's with Interrupt are :
01046         (+) HAL_UART_Transmit_IT()
01047         (+) HAL_UART_Receive_IT()
01048         (+) HAL_UART_IRQHandler()
01049
01050     (#) Non-Blocking mode API's with DMA are :
01051         (+) HAL_UART_Transmit_DMA()
01052         (+) HAL_UART_Receive_DMA()
01053         (+) HAL_UART_DMAPause()
01054         (+) HAL_UART_DMAResume()
01055         (+) HAL_UART_DMAStop()
01056
01057     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
01058         (+) HAL_UART_TxHalfCpltCallback()
01059         (+) HAL_UART_TxCpltCallback()
01060         (+) HAL_UART_RxHalfCpltCallback()
01061         (+) HAL_UART_RxCpltCallback()
01062         (+) HAL_UART_ErrorCallback()
01063
01064     (#) Non-Blocking mode transfers could be aborted using Abort API's :
01065         (+) HAL_UART_Abort()
01066         (+) HAL_UART_AbortTransmit()
01067         (+) HAL_UART_AbortReceive()
01068         (+) HAL_UART_Abort_IT()
01069         (+) HAL_UART_AbortTransmit_IT()
01070         (+) HAL_UART_AbortReceive_IT()
01071
01072     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
01073         (+) HAL_UART_AbortCpltCallback()
01074         (+) HAL_UART_AbortTransmitCpltCallback()
01075         (+) HAL_UART_AbortReceiveCpltCallback()
01076
01077     (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
01078         reception services:
01079         (+) HAL_UARTEx_RxEventCallback()
01080
01081     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
01082         Errors are handled as follows :
01083        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
01084            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
01085            in Interrupt mode reception .
01086            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
01087            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
01088            Transfer is kept ongoing on UART side.
01089            If user wants to abort it, Abort services should be called by user.
01090        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
01091            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
01092            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
01093            user callback is executed.
01094
01095     -@- In the Half duplex communication, it is forbidden to run the transmit
01096         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
01097
01098 @endverbatim
01099   * @{
01100   */
01101
01102 /**
01103   * @brief Send an amount of data in blocking mode.
01104   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01105   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01106   *         of u16 provided through pData.
01107   * @note When FIFO mode is enabled, writing a data in the TDR register adds one
01108   *       data to the TXFIFO. Write operations to the TDR register are performed
01109   *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
01110   *       TXE are mapped on the same bit-field.
01111   * @param huart   UART handle.
01112   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01113   * @param Size    Amount of data elements (u8 or u16) to be sent.
01114   * @param Timeout Timeout duration.
01115   * @retval HAL status
01116   */
01117 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
01118 {
01119   const uint8_t  *pdata8bits;
01120   const uint16_t *pdata16bits;
01121   uint32_t tickstart;
01122
01123   /* Check that a Tx process is not already ongoing */
01124   if (huart->gState == HAL_UART_STATE_READY)
01125   {
01126     if ((pData == NULL) || (Size == 0U))
01127     {
01128       return  HAL_ERROR;
01129     }
01130
01131     huart->ErrorCode = HAL_UART_ERROR_NONE;
01132     huart->gState = HAL_UART_STATE_BUSY_TX;
01133
01134     /* Init tickstart for timeout management */
01135     tickstart = HAL_GetTick();
01136
01137     huart->TxXferSize  = Size;
01138     huart->TxXferCount = Size;
01139
01140     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
01141     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01142     {
01143       pdata8bits  = NULL;
01144       pdata16bits = (const uint16_t *) pData;
01145     }
01146     else
01147     {
01148       pdata8bits  = pData;
01149       pdata16bits = NULL;
01150     }
01151
01152     while (huart->TxXferCount > 0U)
01153     {
01154       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01155       {
01156
01157         huart->gState = HAL_UART_STATE_READY;
01158
01159         return HAL_TIMEOUT;
01160       }
01161       if (pdata8bits == NULL)
01162       {
01163         huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
01164         pdata16bits++;
01165       }
01166       else
01167       {
01168         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
01169         pdata8bits++;
01170       }
01171       huart->TxXferCount--;
01172     }
01173
01174     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
01175     {
01176       huart->gState = HAL_UART_STATE_READY;
01177
01178       return HAL_TIMEOUT;
01179     }
01180
01181     /* At end of Tx process, restore huart->gState to Ready */
01182     huart->gState = HAL_UART_STATE_READY;
01183
01184     return HAL_OK;
01185   }
01186   else
01187   {
01188     return HAL_BUSY;
01189   }
01190 }
01191
01192 /**
01193   * @brief Receive an amount of data in blocking mode.
01194   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01195   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01196   *         of u16 available through pData.
01197   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
01198   *       is not empty. Read operations from the RDR register are performed when
01199   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
01200   *       RXNE are mapped on the same bit-field.
01201   * @param huart   UART handle.
01202   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01203   * @param Size    Amount of data elements (u8 or u16) to be received.
01204   * @param Timeout Timeout duration.
01205   * @retval HAL status
01206   */
01207 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01208 {
01209   uint8_t  *pdata8bits;
01210   uint16_t *pdata16bits;
01211   uint16_t uhMask;
01212   uint32_t tickstart;
01213
01214   /* Check that a Rx process is not already ongoing */
01215   if (huart->RxState == HAL_UART_STATE_READY)
01216   {
01217     if ((pData == NULL) || (Size == 0U))
01218     {
01219       return  HAL_ERROR;
01220     }
01221
01222     huart->ErrorCode = HAL_UART_ERROR_NONE;
01223     huart->RxState = HAL_UART_STATE_BUSY_RX;
01224     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01225
01226     /* Init tickstart for timeout management */
01227     tickstart = HAL_GetTick();
01228
01229     huart->RxXferSize  = Size;
01230     huart->RxXferCount = Size;
01231
01232     /* Computation of UART mask to apply to RDR register */
01233     UART_MASK_COMPUTATION(huart);
01234     uhMask = huart->Mask;
01235
01236     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
01237     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01238     {
01239       pdata8bits  = NULL;
01240       pdata16bits = (uint16_t *) pData;
01241     }
01242     else
01243     {
01244       pdata8bits  = pData;
01245       pdata16bits = NULL;
01246     }
01247
01248     /* as long as data have to be received */
01249     while (huart->RxXferCount > 0U)
01250     {
01251       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01252       {
01253         huart->RxState = HAL_UART_STATE_READY;
01254
01255         return HAL_TIMEOUT;
01256       }
01257       if (pdata8bits == NULL)
01258       {
01259         *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
01260         pdata16bits++;
01261       }
01262       else
01263       {
01264         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
01265         pdata8bits++;
01266       }
01267       huart->RxXferCount--;
01268     }
01269
01270     /* At end of Rx process, restore huart->RxState to Ready */
01271     huart->RxState = HAL_UART_STATE_READY;
01272
01273     return HAL_OK;
01274   }
01275   else
01276   {
01277     return HAL_BUSY;
01278   }
01279 }
01280
01281 /**
01282   * @brief Send an amount of data in interrupt mode.
01283   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01284   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01285   *         of u16 provided through pData.
01286   * @param huart UART handle.
01287   * @param pData Pointer to data buffer (u8 or u16 data elements).
01288   * @param Size  Amount of data elements (u8 or u16) to be sent.
01289   * @retval HAL status
01290   */
01291 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
01292 {
01293   /* Check that a Tx process is not already ongoing */
01294   if (huart->gState == HAL_UART_STATE_READY)
01295   {
01296     if ((pData == NULL) || (Size == 0U))
01297     {
01298       return HAL_ERROR;
01299     }
01300
01301     huart->pTxBuffPtr  = pData;
01302     huart->TxXferSize  = Size;
01303     huart->TxXferCount = Size;
01304     huart->TxISR       = NULL;
01305
01306     huart->ErrorCode = HAL_UART_ERROR_NONE;
01307     huart->gState = HAL_UART_STATE_BUSY_TX;
01308
01309     /* Configure Tx interrupt processing */
01310     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01311     {
01312       /* Set the Tx ISR function pointer according to the data word length */
01313       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01314       {
01315         huart->TxISR = UART_TxISR_16BIT_FIFOEN;
01316       }
01317       else
01318       {
01319         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
01320       }
01321
01322       /* Enable the TX FIFO threshold interrupt */
01323       ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01324     }
01325     else
01326     {
01327       /* Set the Tx ISR function pointer according to the data word length */
01328       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01329       {
01330         huart->TxISR = UART_TxISR_16BIT;
01331       }
01332       else
01333       {
01334         huart->TxISR = UART_TxISR_8BIT;
01335       }
01336
01337       /* Enable the Transmit Data Register Empty interrupt */
01338       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01339     }
01340
01341     return HAL_OK;
01342   }
01343   else
01344   {
01345     return HAL_BUSY;
01346   }
01347 }
01348
01349 /**
01350   * @brief Receive an amount of data in interrupt mode.
01351   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01352   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01353   *         of u16 available through pData.
01354   * @param huart UART handle.
01355   * @param pData Pointer to data buffer (u8 or u16 data elements).
01356   * @param Size  Amount of data elements (u8 or u16) to be received.
01357   * @retval HAL status
01358   */
01359 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01360 {
01361   /* Check that a Rx process is not already ongoing */
01362   if (huart->RxState == HAL_UART_STATE_READY)
01363   {
01364     if ((pData == NULL) || (Size == 0U))
01365     {
01366       return HAL_ERROR;
01367     }
01368
01369     /* Set Reception type to Standard reception */
01370     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01371
01372     if (!(IS_LPUART_INSTANCE(huart->Instance)))
01373     {
01374       /* Check that USART RTOEN bit is set */
01375       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
01376       {
01377         /* Enable the UART Receiver Timeout Interrupt */
01378         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
01379       }
01380     }
01381
01382     return (UART_Start_Receive_IT(huart, pData, Size));
01383   }
01384   else
01385   {
01386     return HAL_BUSY;
01387   }
01388 }
01389
01390 /**
01391   * @brief Send an amount of data in DMA mode.
01392   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01393   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01394   *         of u16 provided through pData.
01395   * @param huart UART handle.
01396   * @param pData Pointer to data buffer (u8 or u16 data elements).
01397   * @param Size  Amount of data elements (u8 or u16) to be sent.
01398   * @retval HAL status
01399   */
01400 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
01401 {
01402   /* Check that a Tx process is not already ongoing */
01403   if (huart->gState == HAL_UART_STATE_READY)
01404   {
01405     if ((pData == NULL) || (Size == 0U))
01406     {
01407       return HAL_ERROR;
01408     }
01409
01410     huart->pTxBuffPtr  = pData;
01411     huart->TxXferSize  = Size;
01412     huart->TxXferCount = Size;
01413
01414     huart->ErrorCode = HAL_UART_ERROR_NONE;
01415     huart->gState = HAL_UART_STATE_BUSY_TX;
01416
01417     if (huart->hdmatx != NULL)
01418     {
01419       /* Set the UART DMA transfer complete callback */
01420       huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
01421
01422       /* Set the UART DMA Half transfer complete callback */
01423       huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
01424
01425       /* Set the DMA error callback */
01426       huart->hdmatx->XferErrorCallback = UART_DMAError;
01427
01428       /* Set the DMA abort callback */
01429       huart->hdmatx->XferAbortCallback = NULL;
01430
01431       /* Enable the UART transmit DMA channel */
01432       if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
01433       {
01434         /* Set error code to DMA */
01435         huart->ErrorCode = HAL_UART_ERROR_DMA;
01436
01437         /* Restore huart->gState to ready */
01438         huart->gState = HAL_UART_STATE_READY;
01439
01440         return HAL_ERROR;
01441       }
01442     }
01443     /* Clear the TC flag in the ICR register */
01444     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
01445
01446     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01447     in the UART CR3 register */
01448     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01449
01450     return HAL_OK;
01451   }
01452   else
01453   {
01454     return HAL_BUSY;
01455   }
01456 }
01457
01458 /**
01459   * @brief Receive an amount of data in DMA mode.
01460   * @note   When the UART parity is enabled (PCE = 1), the received data contain
01461   *         the parity bit (MSB position).
01462   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01463   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01464   *         of u16 available through pData.
01465   * @param huart UART handle.
01466   * @param pData Pointer to data buffer (u8 or u16 data elements).
01467   * @param Size  Amount of data elements (u8 or u16) to be received.
01468   * @retval HAL status
01469   */
01470 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01471 {
01472   /* Check that a Rx process is not already ongoing */
01473   if (huart->RxState == HAL_UART_STATE_READY)
01474   {
01475     if ((pData == NULL) || (Size == 0U))
01476     {
01477       return HAL_ERROR;
01478     }
01479
01480     /* Set Reception type to Standard reception */
01481     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01482
01483     if (!(IS_LPUART_INSTANCE(huart->Instance)))
01484     {
01485       /* Check that USART RTOEN bit is set */
01486       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
01487       {
01488         /* Enable the UART Receiver Timeout Interrupt */
01489         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
01490       }
01491     }
01492
01493     return (UART_Start_Receive_DMA(huart, pData, Size));
01494   }
01495   else
01496   {
01497     return HAL_BUSY;
01498   }
01499 }
01500
01501 /**
01502   * @brief Pause the DMA Transfer.
01503   * @param huart UART handle.
01504   * @retval HAL status
01505   */
01506 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01507 {
01508   const HAL_UART_StateTypeDef gstate = huart->gState;
01509   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01510
01511   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01512       (gstate == HAL_UART_STATE_BUSY_TX))
01513   {
01514     /* Disable the UART DMA Tx request */
01515     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01516   }
01517   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01518       (rxstate == HAL_UART_STATE_BUSY_RX))
01519   {
01520     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01521     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01522     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01523
01524     /* Disable the UART DMA Rx request */
01525     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01526   }
01527
01528   return HAL_OK;
01529 }
01530
01531 /**
01532   * @brief Resume the DMA Transfer.
01533   * @param huart UART handle.
01534   * @retval HAL status
01535   */
01536 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01537 {
01538   if (huart->gState == HAL_UART_STATE_BUSY_TX)
01539   {
01540     /* Enable the UART DMA Tx request */
01541     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01542   }
01543   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
01544   {
01545     /* Clear the Overrun flag before resuming the Rx transfer */
01546     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01547
01548     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01549     if (huart->Init.Parity != UART_PARITY_NONE)
01550     {
01551       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01552     }
01553     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01554
01555     /* Enable the UART DMA Rx request */
01556     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01557   }
01558
01559   return HAL_OK;
01560 }
01561
01562 /**
01563   * @brief Stop the DMA Transfer.
01564   * @param huart UART handle.
01565   * @retval HAL status
01566   */
01567 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01568 {
01569   /* The Lock is not implemented on this API to allow the user application
01570      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01571      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01572      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01573      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01574      the stream and the corresponding call back is executed. */
01575
01576   const HAL_UART_StateTypeDef gstate = huart->gState;
01577   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01578
01579   /* Stop UART DMA Tx request if ongoing */
01580   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01581       (gstate == HAL_UART_STATE_BUSY_TX))
01582   {
01583     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01584
01585     /* Abort the UART DMA Tx channel */
01586     if (huart->hdmatx != NULL)
01587     {
01588       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01589       {
01590         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01591         {
01592           /* Set error code to DMA */
01593           huart->ErrorCode = HAL_UART_ERROR_DMA;
01594
01595           return HAL_TIMEOUT;
01596         }
01597       }
01598     }
01599
01600     UART_EndTxTransfer(huart);
01601   }
01602
01603   /* Stop UART DMA Rx request if ongoing */
01604   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01605       (rxstate == HAL_UART_STATE_BUSY_RX))
01606   {
01607     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01608
01609     /* Abort the UART DMA Rx channel */
01610     if (huart->hdmarx != NULL)
01611     {
01612       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01613       {
01614         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01615         {
01616           /* Set error code to DMA */
01617           huart->ErrorCode = HAL_UART_ERROR_DMA;
01618
01619           return HAL_TIMEOUT;
01620         }
01621       }
01622     }
01623
01624     UART_EndRxTransfer(huart);
01625   }
01626
01627   return HAL_OK;
01628 }
01629
01630 /**
01631   * @brief  Abort ongoing transfers (blocking mode).
01632   * @param  huart UART handle.
01633   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01634   *         This procedure performs following operations :
01635   *           - Disable UART Interrupts (Tx and Rx)
01636   *           - Disable the DMA transfer in the peripheral register (if enabled)
01637   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01638   *           - Set handle State to READY
01639   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01640   * @retval HAL status
01641   */
01642 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01643 {
01644   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01645   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
01646                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01647   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01648
01649   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01650   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01651   {
01652     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01653   }
01654
01655   /* Abort the UART DMA Tx channel if enabled */
01656   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01657   {
01658     /* Disable the UART DMA Tx request if enabled */
01659     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01660
01661     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01662     if (huart->hdmatx != NULL)
01663     {
01664       /* Set the UART DMA Abort callback to Null.
01665          No call back execution at end of DMA abort procedure */
01666       huart->hdmatx->XferAbortCallback = NULL;
01667
01668       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01669       {
01670         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01671         {
01672           /* Set error code to DMA */
01673           huart->ErrorCode = HAL_UART_ERROR_DMA;
01674
01675           return HAL_TIMEOUT;
01676         }
01677       }
01678     }
01679   }
01680
01681   /* Abort the UART DMA Rx channel if enabled */
01682   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01683   {
01684     /* Disable the UART DMA Rx request if enabled */
01685     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01686
01687     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01688     if (huart->hdmarx != NULL)
01689     {
01690       /* Set the UART DMA Abort callback to Null.
01691          No call back execution at end of DMA abort procedure */
01692       huart->hdmarx->XferAbortCallback = NULL;
01693
01694       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01695       {
01696         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01697         {
01698           /* Set error code to DMA */
01699           huart->ErrorCode = HAL_UART_ERROR_DMA;
01700
01701           return HAL_TIMEOUT;
01702         }
01703       }
01704     }
01705   }
01706
01707   /* Reset Tx and Rx transfer counters */
01708   huart->TxXferCount = 0U;
01709   huart->RxXferCount = 0U;
01710
01711   /* Clear the Error flags in the ICR register */
01712   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01713
01714   /* Flush the whole TX FIFO (if needed) */
01715   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01716   {
01717     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01718   }
01719
01720   /* Discard the received data */
01721   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01722
01723   /* Restore huart->gState and huart->RxState to Ready */
01724   huart->gState  = HAL_UART_STATE_READY;
01725   huart->RxState = HAL_UART_STATE_READY;
01726   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01727
01728   huart->ErrorCode = HAL_UART_ERROR_NONE;
01729
01730   return HAL_OK;
01731 }
01732
01733 /**
01734   * @brief  Abort ongoing Transmit transfer (blocking mode).
01735   * @param  huart UART handle.
01736   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01737   *         This procedure performs following operations :
01738   *           - Disable UART Interrupts (Tx)
01739   *           - Disable the DMA transfer in the peripheral register (if enabled)
01740   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01741   *           - Set handle State to READY
01742   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01743   * @retval HAL status
01744   */
01745 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01746 {
01747   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01748   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
01749   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01750
01751   /* Abort the UART DMA Tx channel if enabled */
01752   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01753   {
01754     /* Disable the UART DMA Tx request if enabled */
01755     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01756
01757     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01758     if (huart->hdmatx != NULL)
01759     {
01760       /* Set the UART DMA Abort callback to Null.
01761          No call back execution at end of DMA abort procedure */
01762       huart->hdmatx->XferAbortCallback = NULL;
01763
01764       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01765       {
01766         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01767         {
01768           /* Set error code to DMA */
01769           huart->ErrorCode = HAL_UART_ERROR_DMA;
01770
01771           return HAL_TIMEOUT;
01772         }
01773       }
01774     }
01775   }
01776
01777   /* Reset Tx transfer counter */
01778   huart->TxXferCount = 0U;
01779
01780   /* Flush the whole TX FIFO (if needed) */
01781   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01782   {
01783     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01784   }
01785
01786   /* Restore huart->gState to Ready */
01787   huart->gState = HAL_UART_STATE_READY;
01788
01789   return HAL_OK;
01790 }
01791
01792 /**
01793   * @brief  Abort ongoing Receive transfer (blocking mode).
01794   * @param  huart UART handle.
01795   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01796   *         This procedure performs following operations :
01797   *           - Disable UART Interrupts (Rx)
01798   *           - Disable the DMA transfer in the peripheral register (if enabled)
01799   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01800   *           - Set handle State to READY
01801   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01802   * @retval HAL status
01803   */
01804 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01805 {
01806   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
01807   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
01808   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01809
01810   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01811   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01812   {
01813     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01814   }
01815
01816   /* Abort the UART DMA Rx channel if enabled */
01817   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01818   {
01819     /* Disable the UART DMA Rx request if enabled */
01820     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01821
01822     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01823     if (huart->hdmarx != NULL)
01824     {
01825       /* Set the UART DMA Abort callback to Null.
01826          No call back execution at end of DMA abort procedure */
01827       huart->hdmarx->XferAbortCallback = NULL;
01828
01829       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01830       {
01831         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01832         {
01833           /* Set error code to DMA */
01834           huart->ErrorCode = HAL_UART_ERROR_DMA;
01835
01836           return HAL_TIMEOUT;
01837         }
01838       }
01839     }
01840   }
01841
01842   /* Reset Rx transfer counter */
01843   huart->RxXferCount = 0U;
01844
01845   /* Clear the Error flags in the ICR register */
01846   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01847
01848   /* Discard the received data */
01849   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01850
01851   /* Restore huart->RxState to Ready */
01852   huart->RxState = HAL_UART_STATE_READY;
01853   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01854
01855   return HAL_OK;
01856 }
01857
01858 /**
01859   * @brief  Abort ongoing transfers (Interrupt mode).
01860   * @param  huart UART handle.
01861   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01862   *         This procedure performs following operations :
01863   *           - Disable UART Interrupts (Tx and Rx)
01864   *           - Disable the DMA transfer in the peripheral register (if enabled)
01865   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01866   *           - Set handle State to READY
01867   *           - At abort completion, call user abort complete callback
01868   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01869   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01870   * @retval HAL status
01871   */
01872 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01873 {
01874   uint32_t abortcplt = 1U;
01875
01876   /* Disable interrupts */
01877   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
01878                                           USART_CR1_TXEIE_TXFNFIE));
01879   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01880
01881   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01882   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01883   {
01884     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01885   }
01886
01887   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01888      before any call to DMA Abort functions */
01889   /* DMA Tx Handle is valid */
01890   if (huart->hdmatx != NULL)
01891   {
01892     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01893        Otherwise, set it to NULL */
01894     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01895     {
01896       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01897     }
01898     else
01899     {
01900       huart->hdmatx->XferAbortCallback = NULL;
01901     }
01902   }
01903   /* DMA Rx Handle is valid */
01904   if (huart->hdmarx != NULL)
01905   {
01906     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01907        Otherwise, set it to NULL */
01908     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01909     {
01910       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01911     }
01912     else
01913     {
01914       huart->hdmarx->XferAbortCallback = NULL;
01915     }
01916   }
01917
01918   /* Abort the UART DMA Tx channel if enabled */
01919   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01920   {
01921     /* Disable DMA Tx at UART level */
01922     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01923
01924     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01925     if (huart->hdmatx != NULL)
01926     {
01927       /* UART Tx DMA Abort callback has already been initialised :
01928          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01929
01930       /* Abort DMA TX */
01931       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01932       {
01933         huart->hdmatx->XferAbortCallback = NULL;
01934       }
01935       else
01936       {
01937         abortcplt = 0U;
01938       }
01939     }
01940   }
01941
01942   /* Abort the UART DMA Rx channel if enabled */
01943   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01944   {
01945     /* Disable the UART DMA Rx request if enabled */
01946     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01947
01948     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01949     if (huart->hdmarx != NULL)
01950     {
01951       /* UART Rx DMA Abort callback has already been initialised :
01952          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01953
01954       /* Abort DMA RX */
01955       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01956       {
01957         huart->hdmarx->XferAbortCallback = NULL;
01958         abortcplt = 1U;
01959       }
01960       else
01961       {
01962         abortcplt = 0U;
01963       }
01964     }
01965   }
01966
01967   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01968   if (abortcplt == 1U)
01969   {
01970     /* Reset Tx and Rx transfer counters */
01971     huart->TxXferCount = 0U;
01972     huart->RxXferCount = 0U;
01973
01974     /* Clear ISR function pointers */
01975     huart->RxISR = NULL;
01976     huart->TxISR = NULL;
01977
01978     /* Reset errorCode */
01979     huart->ErrorCode = HAL_UART_ERROR_NONE;
01980
01981     /* Clear the Error flags in the ICR register */
01982     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01983
01984     /* Flush the whole TX FIFO (if needed) */
01985     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01986     {
01987       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01988     }
01989
01990     /* Discard the received data */
01991     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01992
01993     /* Restore huart->gState and huart->RxState to Ready */
01994     huart->gState  = HAL_UART_STATE_READY;
01995     huart->RxState = HAL_UART_STATE_READY;
01996     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01997
01998     /* As no DMA to be aborted, call directly user Abort complete callback */
01999 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02000     /* Call registered Abort complete callback */
02001     huart->AbortCpltCallback(huart);
02002 #else
02003     /* Call legacy weak Abort complete callback */
02004     HAL_UART_AbortCpltCallback(huart);
02005 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02006   }
02007
02008   return HAL_OK;
02009 }
02010
02011 /**
02012   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
02013   * @param  huart UART handle.
02014   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
02015   *         This procedure performs following operations :
02016   *           - Disable UART Interrupts (Tx)
02017   *           - Disable the DMA transfer in the peripheral register (if enabled)
02018   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02019   *           - Set handle State to READY
02020   *           - At abort completion, call user abort complete callback
02021   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02022   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02023   * @retval HAL status
02024   */
02025 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
02026 {
02027   /* Disable interrupts */
02028   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
02029   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
02030
02031   /* Abort the UART DMA Tx channel if enabled */
02032   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
02033   {
02034     /* Disable the UART DMA Tx request if enabled */
02035     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02036
02037     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
02038     if (huart->hdmatx != NULL)
02039     {
02040       /* Set the UART DMA Abort callback :
02041          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02042       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
02043
02044       /* Abort DMA TX */
02045       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
02046       {
02047         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
02048         huart->hdmatx->XferAbortCallback(huart->hdmatx);
02049       }
02050     }
02051     else
02052     {
02053       /* Reset Tx transfer counter */
02054       huart->TxXferCount = 0U;
02055
02056       /* Clear TxISR function pointers */
02057       huart->TxISR = NULL;
02058
02059       /* Restore huart->gState to Ready */
02060       huart->gState = HAL_UART_STATE_READY;
02061
02062       /* As no DMA to be aborted, call directly user Abort complete callback */
02063 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02064       /* Call registered Abort Transmit Complete Callback */
02065       huart->AbortTransmitCpltCallback(huart);
02066 #else
02067       /* Call legacy weak Abort Transmit Complete Callback */
02068       HAL_UART_AbortTransmitCpltCallback(huart);
02069 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02070     }
02071   }
02072   else
02073   {
02074     /* Reset Tx transfer counter */
02075     huart->TxXferCount = 0U;
02076
02077     /* Clear TxISR function pointers */
02078     huart->TxISR = NULL;
02079
02080     /* Flush the whole TX FIFO (if needed) */
02081     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
02082     {
02083       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
02084     }
02085
02086     /* Restore huart->gState to Ready */
02087     huart->gState = HAL_UART_STATE_READY;
02088
02089     /* As no DMA to be aborted, call directly user Abort complete callback */
02090 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02091     /* Call registered Abort Transmit Complete Callback */
02092     huart->AbortTransmitCpltCallback(huart);
02093 #else
02094     /* Call legacy weak Abort Transmit Complete Callback */
02095     HAL_UART_AbortTransmitCpltCallback(huart);
02096 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02097   }
02098
02099   return HAL_OK;
02100 }
02101
02102 /**
02103   * @brief  Abort ongoing Receive transfer (Interrupt mode).
02104   * @param  huart UART handle.
02105   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
02106   *         This procedure performs following operations :
02107   *           - Disable UART Interrupts (Rx)
02108   *           - Disable the DMA transfer in the peripheral register (if enabled)
02109   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02110   *           - Set handle State to READY
02111   *           - At abort completion, call user abort complete callback
02112   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02113   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02114   * @retval HAL status
02115   */
02116 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
02117 {
02118   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02119   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
02120   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02121
02122   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
02123   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
02124   {
02125     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
02126   }
02127
02128   /* Abort the UART DMA Rx channel if enabled */
02129   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02130   {
02131     /* Disable the UART DMA Rx request if enabled */
02132     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02133
02134     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
02135     if (huart->hdmarx != NULL)
02136     {
02137       /* Set the UART DMA Abort callback :
02138          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02139       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
02140
02141       /* Abort DMA RX */
02142       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02143       {
02144         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02145         huart->hdmarx->XferAbortCallback(huart->hdmarx);
02146       }
02147     }
02148     else
02149     {
02150       /* Reset Rx transfer counter */
02151       huart->RxXferCount = 0U;
02152
02153       /* Clear RxISR function pointer */
02154       huart->pRxBuffPtr = NULL;
02155
02156       /* Clear the Error flags in the ICR register */
02157       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02158
02159       /* Discard the received data */
02160       __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02161
02162       /* Restore huart->RxState to Ready */
02163       huart->RxState = HAL_UART_STATE_READY;
02164       huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02165
02166       /* As no DMA to be aborted, call directly user Abort complete callback */
02167 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02168       /* Call registered Abort Receive Complete Callback */
02169       huart->AbortReceiveCpltCallback(huart);
02170 #else
02171       /* Call legacy weak Abort Receive Complete Callback */
02172       HAL_UART_AbortReceiveCpltCallback(huart);
02173 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02174     }
02175   }
02176   else
02177   {
02178     /* Reset Rx transfer counter */
02179     huart->RxXferCount = 0U;
02180
02181     /* Clear RxISR function pointer */
02182     huart->pRxBuffPtr = NULL;
02183
02184     /* Clear the Error flags in the ICR register */
02185     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02186
02187     /* Restore huart->RxState to Ready */
02188     huart->RxState = HAL_UART_STATE_READY;
02189     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02190
02191     /* As no DMA to be aborted, call directly user Abort complete callback */
02192 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02193     /* Call registered Abort Receive Complete Callback */
02194     huart->AbortReceiveCpltCallback(huart);
02195 #else
02196     /* Call legacy weak Abort Receive Complete Callback */
02197     HAL_UART_AbortReceiveCpltCallback(huart);
02198 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02199   }
02200
02201   return HAL_OK;
02202 }
02203
02204 /**
02205   * @brief Handle UART interrupt request.
02206   * @param huart UART handle.
02207   * @retval None
02208   */
02209 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
02210 {
02211   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
02212   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
02213   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
02214
02215   uint32_t errorflags;
02216   uint32_t errorcode;
02217
02218   /* If no error occurs */
02219   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
02220   if (errorflags == 0U)
02221   {
02222     /* UART in mode Receiver ---------------------------------------------------*/
02223     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02224         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02225             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02226     {
02227       if (huart->RxISR != NULL)
02228       {
02229         huart->RxISR(huart);
02230       }
02231       return;
02232     }
02233   }
02234
02235   /* If some errors occur */
02236   if ((errorflags != 0U)
02237       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02238            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
02239   {
02240     /* UART parity error interrupt occurred -------------------------------------*/
02241     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02242     {
02243       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
02244
02245       huart->ErrorCode |= HAL_UART_ERROR_PE;
02246     }
02247
02248     /* UART frame error interrupt occurred --------------------------------------*/
02249     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02250     {
02251       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
02252
02253       huart->ErrorCode |= HAL_UART_ERROR_FE;
02254     }
02255
02256     /* UART noise error interrupt occurred --------------------------------------*/
02257     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02258     {
02259       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
02260
02261       huart->ErrorCode |= HAL_UART_ERROR_NE;
02262     }
02263
02264     /* UART Over-Run interrupt occurred -----------------------------------------*/
02265     if (((isrflags & USART_ISR_ORE) != 0U)
02266         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02267             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02268     {
02269       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
02270
02271       huart->ErrorCode |= HAL_UART_ERROR_ORE;
02272     }
02273
02274     /* UART Receiver Timeout interrupt occurred ---------------------------------*/
02275     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02276     {
02277       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
02278
02279       huart->ErrorCode |= HAL_UART_ERROR_RTO;
02280     }
02281
02282     /* Call UART Error Call back function if need be ----------------------------*/
02283     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
02284     {
02285       /* UART in mode Receiver --------------------------------------------------*/
02286       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02287           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02288               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02289       {
02290         if (huart->RxISR != NULL)
02291         {
02292           huart->RxISR(huart);
02293         }
02294       }
02295
02296       /* If Error is to be considered as blocking :
02297           - Receiver Timeout error in Reception
02298           - Overrun error in Reception
02299           - any error occurs in DMA mode reception
02300       */
02301       errorcode = huart->ErrorCode;
02302       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
02303           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
02304       {
02305         /* Blocking error : transfer is aborted
02306            Set the UART state ready to be able to start again the process,
02307            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
02308         UART_EndRxTransfer(huart);
02309
02310         /* Abort the UART DMA Rx channel if enabled */
02311         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02312         {
02313           /* Disable the UART DMA Rx request if enabled */
02314           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02315
02316           /* Abort the UART DMA Rx channel */
02317           if (huart->hdmarx != NULL)
02318           {
02319             /* Set the UART DMA Abort callback :
02320                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
02321             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
02322
02323             /* Abort DMA RX */
02324             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02325             {
02326               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02327               huart->hdmarx->XferAbortCallback(huart->hdmarx);
02328             }
02329           }
02330           else
02331           {
02332             /* Call user error callback */
02333 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02334             /*Call registered error callback*/
02335             huart->ErrorCallback(huart);
02336 #else
02337             /*Call legacy weak error callback*/
02338             HAL_UART_ErrorCallback(huart);
02339 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02340
02341           }
02342         }
02343         else
02344         {
02345           /* Call user error callback */
02346 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02347           /*Call registered error callback*/
02348           huart->ErrorCallback(huart);
02349 #else
02350           /*Call legacy weak error callback*/
02351           HAL_UART_ErrorCallback(huart);
02352 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02353         }
02354       }
02355       else
02356       {
02357         /* Non Blocking error : transfer could go on.
02358            Error is notified to user through user error callback */
02359 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02360         /*Call registered error callback*/
02361         huart->ErrorCallback(huart);
02362 #else
02363         /*Call legacy weak error callback*/
02364         HAL_UART_ErrorCallback(huart);
02365 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02366         huart->ErrorCode = HAL_UART_ERROR_NONE;
02367       }
02368     }
02369     return;
02370
02371   } /* End if some error occurs */
02372
02373   /* Check current reception Mode :
02374      If Reception till IDLE event has been selected : */
02375   if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
02376       && ((isrflags & USART_ISR_IDLE) != 0U)
02377       && ((cr1its & USART_ISR_IDLE) != 0U))
02378   {
02379     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
02380
02381     /* Check if DMA mode is enabled in UART */
02382     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02383     {
02384       /* DMA mode enabled */
02385       /* Check received length : If all expected data are received, do nothing,
02386          (DMA cplt callback will be called).
02387          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
02388       uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
02389       if ((nb_remaining_rx_data > 0U)
02390           && (nb_remaining_rx_data < huart->RxXferSize))
02391       {
02392         /* Reception is not complete */
02393         huart->RxXferCount = nb_remaining_rx_data;
02394
02395         /* In Normal mode, end DMA xfer and HAL UART Rx process*/
02396         if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
02397         {
02398           /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02399           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
02400           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02401
02402           /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02403              in the UART CR3 register */
02404           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02405
02406           /* At end of Rx process, restore huart->RxState to Ready */
02407           huart->RxState = HAL_UART_STATE_READY;
02408           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02409
02410           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
02411
02412           /* Last bytes received, so no need as the abort is immediate */
02413           (void)HAL_DMA_Abort(huart->hdmarx);
02414         }
02415
02416         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
02417            In this case, Rx Event type is Idle Event */
02418         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
02419
02420 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02421         /*Call registered Rx Event callback*/
02422         huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
02423 #else
02424         /*Call legacy weak Rx Event callback*/
02425         HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
02426 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
02427       }
02428       return;
02429     }
02430     else
02431     {
02432       /* DMA mode not enabled */
02433       /* Check received length : If all expected data are received, do nothing.
02434          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
02435       uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
02436       if ((huart->RxXferCount > 0U)
02437           && (nb_rx_data > 0U))
02438       {
02439         /* Disable the UART Parity Error Interrupt and RXNE interrupts */
02440         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02441
02442         /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
02443         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02444
02445         /* Rx process is completed, restore huart->RxState to Ready */
02446         huart->RxState = HAL_UART_STATE_READY;
02447         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02448
02449         /* Clear RxISR function pointer */
02450         huart->RxISR = NULL;
02451
02452         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
02453
02454         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
02455            In this case, Rx Event type is Idle Event */
02456         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
02457
02458 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02459         /*Call registered Rx complete callback*/
02460         huart->RxEventCallback(huart, nb_rx_data);
02461 #else
02462         /*Call legacy weak Rx Event callback*/
02463         HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
02464 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
02465       }
02466       return;
02467     }
02468   }
02469
02470   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
02471   if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
02472   {
02473     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
02474
02475     /* UART Rx state is not reset as a reception process might be ongoing.
02476        If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
02477
02478 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02479     /* Call registered Wakeup Callback */
02480     huart->WakeupCallback(huart);
02481 #else
02482     /* Call legacy weak Wakeup Callback */
02483     HAL_UARTEx_WakeupCallback(huart);
02484 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02485     return;
02486   }
02487
02488   /* UART in mode Transmitter ------------------------------------------------*/
02489   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02490       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02491           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02492   {
02493     if (huart->TxISR != NULL)
02494     {
02495       huart->TxISR(huart);
02496     }
02497     return;
02498   }
02499
02500   /* UART in mode Transmitter (transmission end) -----------------------------*/
02501   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02502   {
02503     UART_EndTransmit_IT(huart);
02504     return;
02505   }
02506
02507   /* UART TX Fifo Empty occurred ----------------------------------------------*/
02508   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02509   {
02510 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02511     /* Call registered Tx Fifo Empty Callback */
02512     huart->TxFifoEmptyCallback(huart);
02513 #else
02514     /* Call legacy weak Tx Fifo Empty Callback */
02515     HAL_UARTEx_TxFifoEmptyCallback(huart);
02516 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02517     return;
02518   }
02519
02520   /* UART RX Fifo Full occurred ----------------------------------------------*/
02521   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02522   {
02523 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02524     /* Call registered Rx Fifo Full Callback */
02525     huart->RxFifoFullCallback(huart);
02526 #else
02527     /* Call legacy weak Rx Fifo Full Callback */
02528     HAL_UARTEx_RxFifoFullCallback(huart);
02529 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02530     return;
02531   }
02532 }
02533
02534 /**
02535   * @brief Tx Transfer completed callback.
02536   * @param huart UART handle.
02537   * @retval None
02538   */
02539 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
02540 {
02541   /* Prevent unused argument(s) compilation warning */
02542   UNUSED(huart);
02543
02544   /* NOTE : This function should not be modified, when the callback is needed,
02545             the HAL_UART_TxCpltCallback can be implemented in the user file.
02546    */
02547 }
02548
02549 /**
02550   * @brief  Tx Half Transfer completed callback.
02551   * @param  huart UART handle.
02552   * @retval None
02553   */
02554 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
02555 {
02556   /* Prevent unused argument(s) compilation warning */
02557   UNUSED(huart);
02558
02559   /* NOTE: This function should not be modified, when the callback is needed,
02560            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
02561    */
02562 }
02563
02564 /**
02565   * @brief  Rx Transfer completed callback.
02566   * @param  huart UART handle.
02567   * @retval None
02568   */
02569 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
02570 {
02571   /* Prevent unused argument(s) compilation warning */
02572   UNUSED(huart);
02573
02574   /* NOTE : This function should not be modified, when the callback is needed,
02575             the HAL_UART_RxCpltCallback can be implemented in the user file.
02576    */
02577 }
02578
02579 /**
02580   * @brief  Rx Half Transfer completed callback.
02581   * @param  huart UART handle.
02582   * @retval None
02583   */
02584 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
02585 {
02586   /* Prevent unused argument(s) compilation warning */
02587   UNUSED(huart);
02588
02589   /* NOTE: This function should not be modified, when the callback is needed,
02590            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
02591    */
02592 }
02593
02594 /**
02595   * @brief  UART error callback.
02596   * @param  huart UART handle.
02597   * @retval None
02598   */
02599 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
02600 {
02601   /* Prevent unused argument(s) compilation warning */
02602   UNUSED(huart);
02603
02604   /* NOTE : This function should not be modified, when the callback is needed,
02605             the HAL_UART_ErrorCallback can be implemented in the user file.
02606    */
02607 }
02608
02609 /**
02610   * @brief  UART Abort Complete callback.
02611   * @param  huart UART handle.
02612   * @retval None
02613   */
02614 __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
02615 {
02616   /* Prevent unused argument(s) compilation warning */
02617   UNUSED(huart);
02618
02619   /* NOTE : This function should not be modified, when the callback is needed,
02620             the HAL_UART_AbortCpltCallback can be implemented in the user file.
02621    */
02622 }
02623
02624 /**
02625   * @brief  UART Abort Complete callback.
02626   * @param  huart UART handle.
02627   * @retval None
02628   */
02629 __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
02630 {
02631   /* Prevent unused argument(s) compilation warning */
02632   UNUSED(huart);
02633
02634   /* NOTE : This function should not be modified, when the callback is needed,
02635             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
02636    */
02637 }
02638
02639 /**
02640   * @brief  UART Abort Receive Complete callback.
02641   * @param  huart UART handle.
02642   * @retval None
02643   */
02644 __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
02645 {
02646   /* Prevent unused argument(s) compilation warning */
02647   UNUSED(huart);
02648
02649   /* NOTE : This function should not be modified, when the callback is needed,
02650             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
02651    */
02652 }
02653
02654 /**
02655   * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
02656   * @param  huart UART handle
02657   * @param  Size  Number of data available in application reception buffer (indicates a position in
02658   *               reception buffer until which, data are available)
02659   * @retval None
02660   */
02661 __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
02662 {
02663   /* Prevent unused argument(s) compilation warning */
02664   UNUSED(huart);
02665   UNUSED(Size);
02666
02667   /* NOTE : This function should not be modified, when the callback is needed,
02668             the HAL_UARTEx_RxEventCallback can be implemented in the user file.
02669    */
02670 }
02671
02672 /**
02673   * @}
02674   */
02675
02676 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
02677   *  @brief   UART control functions
02678   *
02679 @verbatim
02680  ===============================================================================
02681                       ##### Peripheral Control functions #####
02682  ===============================================================================
02683     [..]
02684     This subsection provides a set of functions allowing to control the UART.
02685      (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
02686      (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
02687      (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
02688      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
02689      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
02690      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
02691      (+) UART_SetConfig() API configures the UART peripheral
02692      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
02693      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
02694      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
02695      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
02696      (+) HAL_LIN_SendBreak() API transmits the break characters
02697 @endverbatim
02698   * @{
02699   */
02700
02701 /**
02702   * @brief  Update on the fly the receiver timeout value in RTOR register.
02703   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02704   *                    the configuration information for the specified UART module.
02705   * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
02706   *                     value must be less or equal to 0x0FFFFFFFF.
02707   * @retval None
02708   */
02709 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
02710 {
02711   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02712   {
02713     assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
02714     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
02715   }
02716 }
02717
02718 /**
02719   * @brief  Enable the UART receiver timeout feature.
02720   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02721   *                    the configuration information for the specified UART module.
02722   * @retval HAL status
02723   */
02724 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
02725 {
02726   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02727   {
02728     if (huart->gState == HAL_UART_STATE_READY)
02729     {
02730       /* Process Locked */
02731       __HAL_LOCK(huart);
02732
02733       huart->gState = HAL_UART_STATE_BUSY;
02734
02735       /* Set the USART RTOEN bit */
02736       SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02737
02738       huart->gState = HAL_UART_STATE_READY;
02739
02740       /* Process Unlocked */
02741       __HAL_UNLOCK(huart);
02742
02743       return HAL_OK;
02744     }
02745     else
02746     {
02747       return HAL_BUSY;
02748     }
02749   }
02750   else
02751   {
02752     return HAL_ERROR;
02753   }
02754 }
02755
02756 /**
02757   * @brief  Disable the UART receiver timeout feature.
02758   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02759   *                    the configuration information for the specified UART module.
02760   * @retval HAL status
02761   */
02762 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
02763 {
02764   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02765   {
02766     if (huart->gState == HAL_UART_STATE_READY)
02767     {
02768       /* Process Locked */
02769       __HAL_LOCK(huart);
02770
02771       huart->gState = HAL_UART_STATE_BUSY;
02772
02773       /* Clear the USART RTOEN bit */
02774       CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02775
02776       huart->gState = HAL_UART_STATE_READY;
02777
02778       /* Process Unlocked */
02779       __HAL_UNLOCK(huart);
02780
02781       return HAL_OK;
02782     }
02783     else
02784     {
02785       return HAL_BUSY;
02786     }
02787   }
02788   else
02789   {
02790     return HAL_ERROR;
02791   }
02792 }
02793
02794 /**
02795   * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
02796   *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
02797   * @param  huart UART handle.
02798   * @retval HAL status
02799   */
02800 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
02801 {
02802   __HAL_LOCK(huart);
02803
02804   huart->gState = HAL_UART_STATE_BUSY;
02805
02806   /* Enable USART mute mode by setting the MME bit in the CR1 register */
02807   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
02808
02809   huart->gState = HAL_UART_STATE_READY;
02810
02811   return (UART_CheckIdleState(huart));
02812 }
02813
02814 /**
02815   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
02816   *         as it may not have been in mute mode at this very moment).
02817   * @param  huart UART handle.
02818   * @retval HAL status
02819   */
02820 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
02821 {
02822   __HAL_LOCK(huart);
02823
02824   huart->gState = HAL_UART_STATE_BUSY;
02825
02826   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
02827   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
02828
02829   huart->gState = HAL_UART_STATE_READY;
02830
02831   return (UART_CheckIdleState(huart));
02832 }
02833
02834 /**
02835   * @brief Enter UART mute mode (means UART actually enters mute mode).
02836   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
02837   * @param huart UART handle.
02838   * @retval None
02839   */
02840 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
02841 {
02842   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
02843 }
02844
02845 /**
02846   * @brief  Enable the UART transmitter and disable the UART receiver.
02847   * @param  huart UART handle.
02848   * @retval HAL status
02849   */
02850 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
02851 {
02852   __HAL_LOCK(huart);
02853   huart->gState = HAL_UART_STATE_BUSY;
02854
02855   /* Clear TE and RE bits */
02856   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02857
02858   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
02859   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
02860
02861   huart->gState = HAL_UART_STATE_READY;
02862
02863   __HAL_UNLOCK(huart);
02864
02865   return HAL_OK;
02866 }
02867
02868 /**
02869   * @brief  Enable the UART receiver and disable the UART transmitter.
02870   * @param  huart UART handle.
02871   * @retval HAL status.
02872   */
02873 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
02874 {
02875   __HAL_LOCK(huart);
02876   huart->gState = HAL_UART_STATE_BUSY;
02877
02878   /* Clear TE and RE bits */
02879   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02880
02881   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
02882   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
02883
02884   huart->gState = HAL_UART_STATE_READY;
02885
02886   __HAL_UNLOCK(huart);
02887
02888   return HAL_OK;
02889 }
02890
02891
02892 /**
02893   * @brief  Transmit break characters.
02894   * @param  huart UART handle.
02895   * @retval HAL status
02896   */
02897 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
02898 {
02899   /* Check the parameters */
02900   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
02901
02902   __HAL_LOCK(huart);
02903
02904   huart->gState = HAL_UART_STATE_BUSY;
02905
02906   /* Send break characters */
02907   __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
02908
02909   huart->gState = HAL_UART_STATE_READY;
02910
02911   __HAL_UNLOCK(huart);
02912
02913   return HAL_OK;
02914 }
02915
02916 /**
02917   * @}
02918   */
02919
02920 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
02921   *  @brief   UART Peripheral State functions
02922   *
02923 @verbatim
02924   ==============================================================================
02925             ##### Peripheral State and Error functions #####
02926   ==============================================================================
02927     [..]
02928     This subsection provides functions allowing to :
02929       (+) Return the UART handle state.
02930       (+) Return the UART handle error code
02931
02932 @endverbatim
02933   * @{
02934   */
02935
02936 /**
02937   * @brief Return the UART handle state.
02938   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02939   *               the configuration information for the specified UART.
02940   * @retval HAL state
02941   */
02942 HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
02943 {
02944   uint32_t temp1;
02945   uint32_t temp2;
02946   temp1 = huart->gState;
02947   temp2 = huart->RxState;
02948
02949   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02950 }
02951
02952 /**
02953   * @brief  Return the UART handle error code.
02954   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02955   *               the configuration information for the specified UART.
02956   * @retval UART Error Code
02957   */
02958 uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
02959 {
02960   return huart->ErrorCode;
02961 }
02962 /**
02963   * @}
02964   */
02965
02966 /**
02967   * @}
02968   */
02969
02970 /** @defgroup UART_Private_Functions UART Private Functions
02971   * @{
02972   */
02973
02974 /**
02975   * @brief  Initialize the callbacks to their default values.
02976   * @param  huart UART handle.
02977   * @retval none
02978   */
02979 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02980 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
02981 {
02982   /* Init the UART Callback settings */
02983   huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02984   huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02985   huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02986   huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02987   huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02988   huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02989   huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02990   huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02991   huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
02992   huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02993   huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02994   huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
02995
02996 }
02997 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02998
02999 /**
03000   * @brief Configure the UART peripheral.
03001   * @param huart UART handle.
03002   * @retval HAL status
03003   */
03004 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
03005 {
03006   uint32_t tmpreg;
03007   uint16_t brrtemp;
03008   UART_ClockSourceTypeDef clocksource;
03009   uint32_t usartdiv;
03010   HAL_StatusTypeDef ret               = HAL_OK;
03011   uint32_t lpuart_ker_ck_pres;
03012   uint32_t pclk;
03013
03014   /* Check the parameters */
03015   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
03016   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
03017   if (UART_INSTANCE_LOWPOWER(huart))
03018   {
03019     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
03020   }
03021   else
03022   {
03023     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
03024     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
03025   }
03026
03027   assert_param(IS_UART_PARITY(huart->Init.Parity));
03028   assert_param(IS_UART_MODE(huart->Init.Mode));
03029   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
03030   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
03031   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
03032
03033   /*-------------------------- USART CR1 Configuration -----------------------*/
03034   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
03035   *  the UART Word Length, Parity, Mode and oversampling:
03036   *  set the M bits according to huart->Init.WordLength value
03037   *  set PCE and PS bits according to huart->Init.Parity value
03038   *  set TE and RE bits according to huart->Init.Mode value
03039   *  set OVER8 bit according to huart->Init.OverSampling value */
03040   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
03041   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
03042
03043   /*-------------------------- USART CR2 Configuration -----------------------*/
03044   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
03045   * to huart->Init.StopBits value */
03046   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
03047
03048   /*-------------------------- USART CR3 Configuration -----------------------*/
03049   /* Configure
03050   * - UART HardWare Flow Control: set CTSE and RTSE bits according
03051   *   to huart->Init.HwFlowCtl value
03052   * - one-bit sampling method versus three samples' majority rule according
03053   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
03054   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
03055
03056   if (!(UART_INSTANCE_LOWPOWER(huart)))
03057   {
03058     tmpreg |= huart->Init.OneBitSampling;
03059   }
03060   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
03061
03062   /*-------------------------- USART PRESC Configuration -----------------------*/
03063   /* Configure
03064   * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
03065   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
03066
03067   /*-------------------------- USART BRR Configuration -----------------------*/
03068   UART_GETCLOCKSOURCE(huart, clocksource);
03069
03070   /* Check LPUART instance */
03071   if (UART_INSTANCE_LOWPOWER(huart))
03072   {
03073     /* Retrieve frequency clock */
03074     switch (clocksource)
03075     {
03076       case UART_CLOCKSOURCE_PCLK1:
03077         pclk = HAL_RCC_GetPCLK1Freq();
03078         break;
03079       case UART_CLOCKSOURCE_HSI:
03080         pclk = (uint32_t) HSI_VALUE;
03081         break;
03082       case UART_CLOCKSOURCE_SYSCLK:
03083         pclk = HAL_RCC_GetSysClockFreq();
03084         break;
03085       case UART_CLOCKSOURCE_LSE:
03086         pclk = (uint32_t) LSE_VALUE;
03087         break;
03088       default:
03089         pclk = 0U;
03090         ret = HAL_ERROR;
03091         break;
03092     }
03093
03094     /* If proper clock source reported */
03095     if (pclk != 0U)
03096     {
03097       /* Compute clock after Prescaler */
03098       lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
03099
03100       /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
03101       if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
03102           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
03103       {
03104         ret = HAL_ERROR;
03105       }
03106       else
03107       {
03108         /* Check computed UsartDiv value is in allocated range
03109            (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
03110         usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03111         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
03112         {
03113           huart->Instance->BRR = usartdiv;
03114         }
03115         else
03116         {
03117           ret = HAL_ERROR;
03118         }
03119       } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
03120                 (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
03121     } /* if (pclk != 0) */
03122   }
03123   /* Check UART Over Sampling to set Baud Rate Register */
03124   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
03125   {
03126     switch (clocksource)
03127     {
03128       case UART_CLOCKSOURCE_PCLK1:
03129         pclk = HAL_RCC_GetPCLK1Freq();
03130         break;
03131       case UART_CLOCKSOURCE_PCLK2:
03132         pclk = HAL_RCC_GetPCLK2Freq();
03133         break;
03134       case UART_CLOCKSOURCE_HSI:
03135         pclk = (uint32_t) HSI_VALUE;
03136         break;
03137       case UART_CLOCKSOURCE_SYSCLK:
03138         pclk = HAL_RCC_GetSysClockFreq();
03139         break;
03140       case UART_CLOCKSOURCE_LSE:
03141         pclk = (uint32_t) LSE_VALUE;
03142         break;
03143       default:
03144         pclk = 0U;
03145         ret = HAL_ERROR;
03146         break;
03147     }
03148
03149     /* USARTDIV must be greater than or equal to 0d16 */
03150     if (pclk != 0U)
03151     {
03152       usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03153       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03154       {
03155         brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
03156         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
03157         huart->Instance->BRR = brrtemp;
03158       }
03159       else
03160       {
03161         ret = HAL_ERROR;
03162       }
03163     }
03164   }
03165   else
03166   {
03167     switch (clocksource)
03168     {
03169       case UART_CLOCKSOURCE_PCLK1:
03170         pclk = HAL_RCC_GetPCLK1Freq();
03171         break;
03172       case UART_CLOCKSOURCE_PCLK2:
03173         pclk = HAL_RCC_GetPCLK2Freq();
03174         break;
03175       case UART_CLOCKSOURCE_HSI:
03176         pclk = (uint32_t) HSI_VALUE;
03177         break;
03178       case UART_CLOCKSOURCE_SYSCLK:
03179         pclk = HAL_RCC_GetSysClockFreq();
03180         break;
03181       case UART_CLOCKSOURCE_LSE:
03182         pclk = (uint32_t) LSE_VALUE;
03183         break;
03184       default:
03185         pclk = 0U;
03186         ret = HAL_ERROR;
03187         break;
03188     }
03189
03190     if (pclk != 0U)
03191     {
03192       /* USARTDIV must be greater than or equal to 0d16 */
03193       usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03194       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03195       {
03196         huart->Instance->BRR = (uint16_t)usartdiv;
03197       }
03198       else
03199       {
03200         ret = HAL_ERROR;
03201       }
03202     }
03203   }
03204
03205   /* Initialize the number of data to process during RX/TX ISR execution */
03206   huart->NbTxDataToProcess = 1;
03207   huart->NbRxDataToProcess = 1;
03208
03209   /* Clear ISR function pointers */
03210   huart->RxISR = NULL;
03211   huart->TxISR = NULL;
03212
03213   return ret;
03214 }
03215
03216 /**
03217   * @brief Configure the UART peripheral advanced features.
03218   * @param huart UART handle.
03219   * @retval None
03220   */
03221 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
03222 {
03223   /* Check whether the set of advanced features to configure is properly set */
03224   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
03225
03226   /* if required, configure RX/TX pins swap */
03227   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
03228   {
03229     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
03230     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
03231   }
03232
03233   /* if required, configure TX pin active level inversion */
03234   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
03235   {
03236     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
03237     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
03238   }
03239
03240   /* if required, configure RX pin active level inversion */
03241   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
03242   {
03243     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
03244     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
03245   }
03246
03247   /* if required, configure data inversion */
03248   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
03249   {
03250     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
03251     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
03252   }
03253
03254   /* if required, configure RX overrun detection disabling */
03255   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
03256   {
03257     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
03258     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
03259   }
03260
03261   /* if required, configure DMA disabling on reception error */
03262   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
03263   {
03264     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
03265     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
03266   }
03267
03268   /* if required, configure auto Baud rate detection scheme */
03269   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
03270   {
03271     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
03272     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
03273     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
03274     /* set auto Baudrate detection parameters if detection is enabled */
03275     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
03276     {
03277       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
03278       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
03279     }
03280   }
03281
03282   /* if required, configure MSB first on communication line */
03283   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
03284   {
03285     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
03286     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
03287   }
03288 }
03289
03290 /**
03291   * @brief Check the UART Idle State.
03292   * @param huart UART handle.
03293   * @retval HAL status
03294   */
03295 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
03296 {
03297   uint32_t tickstart;
03298
03299   /* Initialize the UART ErrorCode */
03300   huart->ErrorCode = HAL_UART_ERROR_NONE;
03301
03302   /* Init tickstart for timeout management */
03303   tickstart = HAL_GetTick();
03304
03305   /* Check if the Transmitter is enabled */
03306   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
03307   {
03308     /* Wait until TEACK flag is set */
03309     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03310     {
03311       /* Disable TXE interrupt for the interrupt process */
03312       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
03313
03314       huart->gState = HAL_UART_STATE_READY;
03315
03316       __HAL_UNLOCK(huart);
03317
03318       /* Timeout occurred */
03319       return HAL_TIMEOUT;
03320     }
03321   }
03322
03323   /* Check if the Receiver is enabled */
03324   if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03325   {
03326     /* Wait until REACK flag is set */
03327     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03328     {
03329       /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
03330       interrupts for the interrupt process */
03331       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03332       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03333
03334       huart->RxState = HAL_UART_STATE_READY;
03335
03336       __HAL_UNLOCK(huart);
03337
03338       /* Timeout occurred */
03339       return HAL_TIMEOUT;
03340     }
03341   }
03342
03343   /* Initialize the UART State */
03344   huart->gState = HAL_UART_STATE_READY;
03345   huart->RxState = HAL_UART_STATE_READY;
03346   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03347   huart->RxEventType = HAL_UART_RXEVENT_TC;
03348
03349   __HAL_UNLOCK(huart);
03350
03351   return HAL_OK;
03352 }
03353
03354 /**
03355   * @brief  This function handles UART Communication Timeout. It waits
03356   *                  until a flag is no longer in the specified status.
03357   * @param huart     UART handle.
03358   * @param Flag      Specifies the UART flag to check
03359   * @param Status    The actual Flag status (SET or RESET)
03360   * @param Tickstart Tick start value
03361   * @param Timeout   Timeout duration
03362   * @retval HAL status
03363   */
03364 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
03365                                               uint32_t Tickstart, uint32_t Timeout)
03366 {
03367   /* Wait until flag is set */
03368   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
03369   {
03370     /* Check for the Timeout */
03371     if (Timeout != HAL_MAX_DELAY)
03372     {
03373       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
03374       {
03375
03376         return HAL_TIMEOUT;
03377       }
03378
03379       if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
03380       {
03381         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
03382         {
03383           /* Clear Overrun Error flag*/
03384           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
03385
03386           /* Blocking error : transfer is aborted
03387           Set the UART state ready to be able to start again the process,
03388           Disable Rx Interrupts if ongoing */
03389           UART_EndRxTransfer(huart);
03390
03391           huart->ErrorCode = HAL_UART_ERROR_ORE;
03392
03393           /* Process Unlocked */
03394           __HAL_UNLOCK(huart);
03395
03396           return HAL_ERROR;
03397         }
03398         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
03399         {
03400           /* Clear Receiver Timeout flag*/
03401           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
03402
03403           /* Blocking error : transfer is aborted
03404           Set the UART state ready to be able to start again the process,
03405           Disable Rx Interrupts if ongoing */
03406           UART_EndRxTransfer(huart);
03407
03408           huart->ErrorCode = HAL_UART_ERROR_RTO;
03409
03410           /* Process Unlocked */
03411           __HAL_UNLOCK(huart);
03412
03413           return HAL_TIMEOUT;
03414         }
03415       }
03416     }
03417   }
03418   return HAL_OK;
03419 }
03420
03421 /**
03422   * @brief  Start Receive operation in interrupt mode.
03423   * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
03424   * @note   When calling this function, parameters validity is considered as already checked,
03425   *         i.e. Rx State, buffer address, ...
03426   *         UART Handle is assumed as Locked.
03427   * @param  huart UART handle.
03428   * @param  pData Pointer to data buffer (u8 or u16 data elements).
03429   * @param  Size  Amount of data elements (u8 or u16) to be received.
03430   * @retval HAL status
03431   */
03432 HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
03433 {
03434   huart->pRxBuffPtr  = pData;
03435   huart->RxXferSize  = Size;
03436   huart->RxXferCount = Size;
03437   huart->RxISR       = NULL;
03438
03439   /* Computation of UART mask to apply to RDR register */
03440   UART_MASK_COMPUTATION(huart);
03441
03442   huart->ErrorCode = HAL_UART_ERROR_NONE;
03443   huart->RxState = HAL_UART_STATE_BUSY_RX;
03444
03445   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03446   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
03447
03448   /* Configure Rx interrupt processing */
03449   if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
03450   {
03451     /* Set the Rx ISR function pointer according to the data word length */
03452     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
03453     {
03454       huart->RxISR = UART_RxISR_16BIT_FIFOEN;
03455     }
03456     else
03457     {
03458       huart->RxISR = UART_RxISR_8BIT_FIFOEN;
03459     }
03460
03461     /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
03462     if (huart->Init.Parity != UART_PARITY_NONE)
03463     {
03464       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03465     }
03466     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
03467   }
03468   else
03469   {
03470     /* Set the Rx ISR function pointer according to the data word length */
03471     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
03472     {
03473       huart->RxISR = UART_RxISR_16BIT;
03474     }
03475     else
03476     {
03477       huart->RxISR = UART_RxISR_8BIT;
03478     }
03479
03480     /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
03481     if (huart->Init.Parity != UART_PARITY_NONE)
03482     {
03483       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
03484     }
03485     else
03486     {
03487       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03488     }
03489   }
03490   return HAL_OK;
03491 }
03492
03493 /**
03494   * @brief  Start Receive operation in DMA mode.
03495   * @note   This function could be called by all HAL UART API providing reception in DMA mode.
03496   * @note   When calling this function, parameters validity is considered as already checked,
03497   *         i.e. Rx State, buffer address, ...
03498   *         UART Handle is assumed as Locked.
03499   * @param  huart UART handle.
03500   * @param  pData Pointer to data buffer (u8 or u16 data elements).
03501   * @param  Size  Amount of data elements (u8 or u16) to be received.
03502   * @retval HAL status
03503   */
03504 HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
03505 {
03506   huart->pRxBuffPtr = pData;
03507   huart->RxXferSize = Size;
03508
03509   huart->ErrorCode = HAL_UART_ERROR_NONE;
03510   huart->RxState = HAL_UART_STATE_BUSY_RX;
03511
03512   if (huart->hdmarx != NULL)
03513   {
03514     /* Set the UART DMA transfer complete callback */
03515     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
03516
03517     /* Set the UART DMA Half transfer complete callback */
03518     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
03519
03520     /* Set the DMA error callback */
03521     huart->hdmarx->XferErrorCallback = UART_DMAError;
03522
03523     /* Set the DMA abort callback */
03524     huart->hdmarx->XferAbortCallback = NULL;
03525
03526     /* Enable the DMA channel */
03527     if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
03528     {
03529       /* Set error code to DMA */
03530       huart->ErrorCode = HAL_UART_ERROR_DMA;
03531
03532       /* Restore huart->RxState to ready */
03533       huart->RxState = HAL_UART_STATE_READY;
03534
03535       return HAL_ERROR;
03536     }
03537   }
03538
03539   /* Enable the UART Parity Error Interrupt */
03540   if (huart->Init.Parity != UART_PARITY_NONE)
03541   {
03542     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03543   }
03544
03545   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03546   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
03547
03548   /* Enable the DMA transfer for the receiver request by setting the DMAR bit
03549   in the UART CR3 register */
03550   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03551
03552   return HAL_OK;
03553 }
03554
03555
03556 /**
03557   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
03558   * @param  huart UART handle.
03559   * @retval None
03560   */
03561 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
03562 {
03563   /* Disable TXEIE, TCIE, TXFT interrupts */
03564   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
03565   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
03566
03567   /* At end of Tx process, restore huart->gState to Ready */
03568   huart->gState = HAL_UART_STATE_READY;
03569 }
03570
03571
03572 /**
03573   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
03574   * @param  huart UART handle.
03575   * @retval None
03576   */
03577 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
03578 {
03579   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
03580   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03581   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03582
03583   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
03584   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03585   {
03586     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
03587   }
03588
03589   /* At end of Rx process, restore huart->RxState to Ready */
03590   huart->RxState = HAL_UART_STATE_READY;
03591   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03592
03593   /* Reset RxIsr function pointer */
03594   huart->RxISR = NULL;
03595 }
03596
03597
03598 /**
03599   * @brief DMA UART transmit process complete callback.
03600   * @param hdma DMA handle.
03601   * @retval None
03602   */
03603 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03604 {
03605   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03606
03607   /* DMA Normal mode */
03608   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03609   {
03610     huart->TxXferCount = 0U;
03611
03612     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
03613        in the UART CR3 register */
03614     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
03615
03616     /* Enable the UART Transmit Complete Interrupt */
03617     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03618   }
03619   /* DMA Circular mode */
03620   else
03621   {
03622 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03623     /*Call registered Tx complete callback*/
03624     huart->TxCpltCallback(huart);
03625 #else
03626     /*Call legacy weak Tx complete callback*/
03627     HAL_UART_TxCpltCallback(huart);
03628 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03629   }
03630 }
03631
03632 /**
03633   * @brief DMA UART transmit process half complete callback.
03634   * @param hdma DMA handle.
03635   * @retval None
03636   */
03637 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
03638 {
03639   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03640
03641 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03642   /*Call registered Tx Half complete callback*/
03643   huart->TxHalfCpltCallback(huart);
03644 #else
03645   /*Call legacy weak Tx Half complete callback*/
03646   HAL_UART_TxHalfCpltCallback(huart);
03647 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03648 }
03649
03650 /**
03651   * @brief DMA UART receive process complete callback.
03652   * @param hdma DMA handle.
03653   * @retval None
03654   */
03655 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03656 {
03657   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03658
03659   /* DMA Normal mode */
03660   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03661   {
03662     huart->RxXferCount = 0U;
03663
03664     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
03665     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03666     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03667
03668     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
03669        in the UART CR3 register */
03670     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03671
03672     /* At end of Rx process, restore huart->RxState to Ready */
03673     huart->RxState = HAL_UART_STATE_READY;
03674
03675     /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
03676     if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03677     {
03678       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
03679     }
03680   }
03681
03682   /* Initialize type of RxEvent that correspond to RxEvent callback execution;
03683      In this case, Rx Event type is Transfer Complete */
03684   huart->RxEventType = HAL_UART_RXEVENT_TC;
03685
03686   /* Check current reception Mode :
03687      If Reception till IDLE event has been selected : use Rx Event callback */
03688   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03689   {
03690 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03691     /*Call registered Rx Event callback*/
03692     huart->RxEventCallback(huart, huart->RxXferSize);
03693 #else
03694     /*Call legacy weak Rx Event callback*/
03695     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
03696 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03697   }
03698   else
03699   {
03700     /* In other cases : use Rx Complete callback */
03701 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03702     /*Call registered Rx complete callback*/
03703     huart->RxCpltCallback(huart);
03704 #else
03705     /*Call legacy weak Rx complete callback*/
03706     HAL_UART_RxCpltCallback(huart);
03707 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03708   }
03709 }
03710
03711 /**
03712   * @brief DMA UART receive process half complete callback.
03713   * @param hdma DMA handle.
03714   * @retval None
03715   */
03716 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
03717 {
03718   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03719
03720   /* Initialize type of RxEvent that correspond to RxEvent callback execution;
03721      In this case, Rx Event type is Half Transfer */
03722   huart->RxEventType = HAL_UART_RXEVENT_HT;
03723
03724   /* Check current reception Mode :
03725      If Reception till IDLE event has been selected : use Rx Event callback */
03726   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03727   {
03728 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03729     /*Call registered Rx Event callback*/
03730     huart->RxEventCallback(huart, huart->RxXferSize / 2U);
03731 #else
03732     /*Call legacy weak Rx Event callback*/
03733     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
03734 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03735   }
03736   else
03737   {
03738     /* In other cases : use Rx Half Complete callback */
03739 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03740     /*Call registered Rx Half complete callback*/
03741     huart->RxHalfCpltCallback(huart);
03742 #else
03743     /*Call legacy weak Rx Half complete callback*/
03744     HAL_UART_RxHalfCpltCallback(huart);
03745 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03746   }
03747 }
03748
03749 /**
03750   * @brief DMA UART communication error callback.
03751   * @param hdma DMA handle.
03752   * @retval None
03753   */
03754 static void UART_DMAError(DMA_HandleTypeDef *hdma)
03755 {
03756   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03757
03758   const HAL_UART_StateTypeDef gstate = huart->gState;
03759   const HAL_UART_StateTypeDef rxstate = huart->RxState;
03760
03761   /* Stop UART DMA Tx request if ongoing */
03762   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
03763       (gstate == HAL_UART_STATE_BUSY_TX))
03764   {
03765     huart->TxXferCount = 0U;
03766     UART_EndTxTransfer(huart);
03767   }
03768
03769   /* Stop UART DMA Rx request if ongoing */
03770   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
03771       (rxstate == HAL_UART_STATE_BUSY_RX))
03772   {
03773     huart->RxXferCount = 0U;
03774     UART_EndRxTransfer(huart);
03775   }
03776
03777   huart->ErrorCode |= HAL_UART_ERROR_DMA;
03778
03779 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03780   /*Call registered error callback*/
03781   huart->ErrorCallback(huart);
03782 #else
03783   /*Call legacy weak error callback*/
03784   HAL_UART_ErrorCallback(huart);
03785 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03786 }
03787
03788 /**
03789   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
03790   *         (To be called at end of DMA Abort procedure following error occurrence).
03791   * @param  hdma DMA handle.
03792   * @retval None
03793   */
03794 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03795 {
03796   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03797   huart->RxXferCount = 0U;
03798   huart->TxXferCount = 0U;
03799
03800 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03801   /*Call registered error callback*/
03802   huart->ErrorCallback(huart);
03803 #else
03804   /*Call legacy weak error callback*/
03805   HAL_UART_ErrorCallback(huart);
03806 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03807 }
03808
03809 /**
03810   * @brief  DMA UART Tx communication abort callback, when initiated by user
03811   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03812   * @note   When this callback is executed, User Abort complete call back is called only if no
03813   *         Abort still ongoing for Rx DMA Handle.
03814   * @param  hdma DMA handle.
03815   * @retval None
03816   */
03817 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03818 {
03819   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03820
03821   huart->hdmatx->XferAbortCallback = NULL;
03822
03823   /* Check if an Abort process is still ongoing */
03824   if (huart->hdmarx != NULL)
03825   {
03826     if (huart->hdmarx->XferAbortCallback != NULL)
03827     {
03828       return;
03829     }
03830   }
03831
03832   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03833   huart->TxXferCount = 0U;
03834   huart->RxXferCount = 0U;
03835
03836   /* Reset errorCode */
03837   huart->ErrorCode = HAL_UART_ERROR_NONE;
03838
03839   /* Clear the Error flags in the ICR register */
03840   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03841
03842   /* Flush the whole TX FIFO (if needed) */
03843   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03844   {
03845     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03846   }
03847
03848   /* Restore huart->gState and huart->RxState to Ready */
03849   huart->gState  = HAL_UART_STATE_READY;
03850   huart->RxState = HAL_UART_STATE_READY;
03851   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03852
03853   /* Call user Abort complete callback */
03854 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03855   /* Call registered Abort complete callback */
03856   huart->AbortCpltCallback(huart);
03857 #else
03858   /* Call legacy weak Abort complete callback */
03859   HAL_UART_AbortCpltCallback(huart);
03860 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03861 }
03862
03863
03864 /**
03865   * @brief  DMA UART Rx communication abort callback, when initiated by user
03866   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03867   * @note   When this callback is executed, User Abort complete call back is called only if no
03868   *         Abort still ongoing for Tx DMA Handle.
03869   * @param  hdma DMA handle.
03870   * @retval None
03871   */
03872 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03873 {
03874   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03875
03876   huart->hdmarx->XferAbortCallback = NULL;
03877
03878   /* Check if an Abort process is still ongoing */
03879   if (huart->hdmatx != NULL)
03880   {
03881     if (huart->hdmatx->XferAbortCallback != NULL)
03882     {
03883       return;
03884     }
03885   }
03886
03887   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03888   huart->TxXferCount = 0U;
03889   huart->RxXferCount = 0U;
03890
03891   /* Reset errorCode */
03892   huart->ErrorCode = HAL_UART_ERROR_NONE;
03893
03894   /* Clear the Error flags in the ICR register */
03895   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03896
03897   /* Discard the received data */
03898   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03899
03900   /* Restore huart->gState and huart->RxState to Ready */
03901   huart->gState  = HAL_UART_STATE_READY;
03902   huart->RxState = HAL_UART_STATE_READY;
03903   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03904
03905   /* Call user Abort complete callback */
03906 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03907   /* Call registered Abort complete callback */
03908   huart->AbortCpltCallback(huart);
03909 #else
03910   /* Call legacy weak Abort complete callback */
03911   HAL_UART_AbortCpltCallback(huart);
03912 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03913 }
03914
03915
03916 /**
03917   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
03918   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
03919   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
03920   *         and leads to user Tx Abort Complete callback execution).
03921   * @param  hdma DMA handle.
03922   * @retval None
03923   */
03924 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03925 {
03926   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03927
03928   huart->TxXferCount = 0U;
03929
03930   /* Flush the whole TX FIFO (if needed) */
03931   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03932   {
03933     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03934   }
03935
03936   /* Restore huart->gState to Ready */
03937   huart->gState = HAL_UART_STATE_READY;
03938
03939   /* Call user Abort complete callback */
03940 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03941   /* Call registered Abort Transmit Complete Callback */
03942   huart->AbortTransmitCpltCallback(huart);
03943 #else
03944   /* Call legacy weak Abort Transmit Complete Callback */
03945   HAL_UART_AbortTransmitCpltCallback(huart);
03946 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03947 }
03948
03949 /**
03950   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
03951   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
03952   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
03953   *         and leads to user Rx Abort Complete callback execution).
03954   * @param  hdma DMA handle.
03955   * @retval None
03956   */
03957 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03958 {
03959   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03960
03961   huart->RxXferCount = 0U;
03962
03963   /* Clear the Error flags in the ICR register */
03964   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03965
03966   /* Discard the received data */
03967   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03968
03969   /* Restore huart->RxState to Ready */
03970   huart->RxState = HAL_UART_STATE_READY;
03971   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03972
03973   /* Call user Abort complete callback */
03974 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03975   /* Call registered Abort Receive Complete Callback */
03976   huart->AbortReceiveCpltCallback(huart);
03977 #else
03978   /* Call legacy weak Abort Receive Complete Callback */
03979   HAL_UART_AbortReceiveCpltCallback(huart);
03980 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03981 }
03982
03983 /**
03984   * @brief TX interrupt handler for 7 or 8 bits data word length .
03985   * @note   Function is called under interruption only, once
03986   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03987   * @param huart UART handle.
03988   * @retval None
03989   */
03990 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
03991 {
03992   /* Check that a Tx process is ongoing */
03993   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03994   {
03995     if (huart->TxXferCount == 0U)
03996     {
03997       /* Disable the UART Transmit Data Register Empty Interrupt */
03998       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
03999
04000       /* Enable the UART Transmit Complete Interrupt */
04001       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04002     }
04003     else
04004     {
04005       huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
04006       huart->pTxBuffPtr++;
04007       huart->TxXferCount--;
04008     }
04009   }
04010 }
04011
04012 /**
04013   * @brief TX interrupt handler for 9 bits data word length.
04014   * @note   Function is called under interruption only, once
04015   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04016   * @param huart UART handle.
04017   * @retval None
04018   */
04019 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
04020 {
04021   const uint16_t *tmp;
04022
04023   /* Check that a Tx process is ongoing */
04024   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04025   {
04026     if (huart->TxXferCount == 0U)
04027     {
04028       /* Disable the UART Transmit Data Register Empty Interrupt */
04029       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
04030
04031       /* Enable the UART Transmit Complete Interrupt */
04032       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04033     }
04034     else
04035     {
04036       tmp = (const uint16_t *) huart->pTxBuffPtr;
04037       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
04038       huart->pTxBuffPtr += 2U;
04039       huart->TxXferCount--;
04040     }
04041   }
04042 }
04043
04044 /**
04045   * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
04046   * @note   Function is called under interruption only, once
04047   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04048   * @param huart UART handle.
04049   * @retval None
04050   */
04051 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
04052 {
04053   uint16_t  nb_tx_data;
04054
04055   /* Check that a Tx process is ongoing */
04056   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04057   {
04058     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
04059     {
04060       if (huart->TxXferCount == 0U)
04061       {
04062         /* Disable the TX FIFO threshold interrupt */
04063         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
04064
04065         /* Enable the UART Transmit Complete Interrupt */
04066         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04067
04068         break; /* force exit loop */
04069       }
04070       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
04071       {
04072         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
04073         huart->pTxBuffPtr++;
04074         huart->TxXferCount--;
04075       }
04076       else
04077       {
04078         /* Nothing to do */
04079       }
04080     }
04081   }
04082 }
04083
04084 /**
04085   * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
04086   * @note   Function is called under interruption only, once
04087   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04088   * @param huart UART handle.
04089   * @retval None
04090   */
04091 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
04092 {
04093   const uint16_t *tmp;
04094   uint16_t  nb_tx_data;
04095
04096   /* Check that a Tx process is ongoing */
04097   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04098   {
04099     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
04100     {
04101       if (huart->TxXferCount == 0U)
04102       {
04103         /* Disable the TX FIFO threshold interrupt */
04104         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
04105
04106         /* Enable the UART Transmit Complete Interrupt */
04107         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04108
04109         break; /* force exit loop */
04110       }
04111       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
04112       {
04113         tmp = (const uint16_t *) huart->pTxBuffPtr;
04114         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
04115         huart->pTxBuffPtr += 2U;
04116         huart->TxXferCount--;
04117       }
04118       else
04119       {
04120         /* Nothing to do */
04121       }
04122     }
04123   }
04124 }
04125
04126 /**
04127   * @brief  Wrap up transmission in non-blocking mode.
04128   * @param  huart pointer to a UART_HandleTypeDef structure that contains
04129   *                the configuration information for the specified UART module.
04130   * @retval None
04131   */
04132 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
04133 {
04134   /* Disable the UART Transmit Complete Interrupt */
04135   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04136
04137   /* Tx process is ended, restore huart->gState to Ready */
04138   huart->gState = HAL_UART_STATE_READY;
04139
04140   /* Cleat TxISR function pointer */
04141   huart->TxISR = NULL;
04142
04143 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04144   /*Call registered Tx complete callback*/
04145   huart->TxCpltCallback(huart);
04146 #else
04147   /*Call legacy weak Tx complete callback*/
04148   HAL_UART_TxCpltCallback(huart);
04149 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04150 }
04151
04152 /**
04153   * @brief RX interrupt handler for 7 or 8 bits data word length .
04154   * @param huart UART handle.
04155   * @retval None
04156   */
04157 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
04158 {
04159   uint16_t uhMask = huart->Mask;
04160   uint16_t  uhdata;
04161
04162   /* Check that a Rx process is ongoing */
04163   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04164   {
04165     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04166     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
04167     huart->pRxBuffPtr++;
04168     huart->RxXferCount--;
04169
04170     if (huart->RxXferCount == 0U)
04171     {
04172       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
04173       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
04174
04175       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
04176       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
04177
04178       /* Rx process is completed, restore huart->RxState to Ready */
04179       huart->RxState = HAL_UART_STATE_READY;
04180
04181       /* Clear RxISR function pointer */
04182       huart->RxISR = NULL;
04183
04184       /* Initialize type of RxEvent to Transfer Complete */
04185       huart->RxEventType = HAL_UART_RXEVENT_TC;
04186
04187       if (!(IS_LPUART_INSTANCE(huart->Instance)))
04188       {
04189         /* Check that USART RTOEN bit is set */
04190         if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
04191         {
04192           /* Enable the UART Receiver Timeout Interrupt */
04193           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
04194         }
04195       }
04196
04197       /* Check current reception Mode :
04198          If Reception till IDLE event has been selected : */
04199       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04200       {
04201         /* Set reception type to Standard */
04202         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04203
04204         /* Disable IDLE interrupt */
04205         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04206
04207         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04208         {
04209           /* Clear IDLE Flag */
04210           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04211         }
04212
04213 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04214         /*Call registered Rx Event callback*/
04215         huart->RxEventCallback(huart, huart->RxXferSize);
04216 #else
04217         /*Call legacy weak Rx Event callback*/
04218         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04219 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04220       }
04221       else
04222       {
04223         /* Standard reception API called */
04224 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04225         /*Call registered Rx complete callback*/
04226         huart->RxCpltCallback(huart);
04227 #else
04228         /*Call legacy weak Rx complete callback*/
04229         HAL_UART_RxCpltCallback(huart);
04230 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04231       }
04232     }
04233   }
04234   else
04235   {
04236     /* Clear RXNE interrupt flag */
04237     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04238   }
04239 }
04240
04241 /**
04242   * @brief RX interrupt handler for 9 bits data word length .
04243   * @note   Function is called under interruption only, once
04244   *         interruptions have been enabled by HAL_UART_Receive_IT()
04245   * @param huart UART handle.
04246   * @retval None
04247   */
04248 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
04249 {
04250   uint16_t *tmp;
04251   uint16_t uhMask = huart->Mask;
04252   uint16_t  uhdata;
04253
04254   /* Check that a Rx process is ongoing */
04255   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04256   {
04257     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04258     tmp = (uint16_t *) huart->pRxBuffPtr ;
04259     *tmp = (uint16_t)(uhdata & uhMask);
04260     huart->pRxBuffPtr += 2U;
04261     huart->RxXferCount--;
04262
04263     if (huart->RxXferCount == 0U)
04264     {
04265       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
04266       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
04267
04268       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
04269       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
04270
04271       /* Rx process is completed, restore huart->RxState to Ready */
04272       huart->RxState = HAL_UART_STATE_READY;
04273
04274       /* Clear RxISR function pointer */
04275       huart->RxISR = NULL;
04276
04277       /* Initialize type of RxEvent to Transfer Complete */
04278       huart->RxEventType = HAL_UART_RXEVENT_TC;
04279
04280       if (!(IS_LPUART_INSTANCE(huart->Instance)))
04281       {
04282         /* Check that USART RTOEN bit is set */
04283         if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
04284         {
04285           /* Enable the UART Receiver Timeout Interrupt */
04286           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
04287         }
04288       }
04289
04290       /* Check current reception Mode :
04291          If Reception till IDLE event has been selected : */
04292       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04293       {
04294         /* Set reception type to Standard */
04295         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04296
04297         /* Disable IDLE interrupt */
04298         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04299
04300         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04301         {
04302           /* Clear IDLE Flag */
04303           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04304         }
04305
04306 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04307         /*Call registered Rx Event callback*/
04308         huart->RxEventCallback(huart, huart->RxXferSize);
04309 #else
04310         /*Call legacy weak Rx Event callback*/
04311         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04312 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04313       }
04314       else
04315       {
04316         /* Standard reception API called */
04317 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04318         /*Call registered Rx complete callback*/
04319         huart->RxCpltCallback(huart);
04320 #else
04321         /*Call legacy weak Rx complete callback*/
04322         HAL_UART_RxCpltCallback(huart);
04323 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04324       }
04325     }
04326   }
04327   else
04328   {
04329     /* Clear RXNE interrupt flag */
04330     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04331   }
04332 }
04333
04334 /**
04335   * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
04336   * @note   Function is called under interruption only, once
04337   *         interruptions have been enabled by HAL_UART_Receive_IT()
04338   * @param huart UART handle.
04339   * @retval None
04340   */
04341 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
04342 {
04343   uint16_t  uhMask = huart->Mask;
04344   uint16_t  uhdata;
04345   uint16_t  nb_rx_data;
04346   uint16_t  rxdatacount;
04347   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
04348   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
04349   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
04350
04351   /* Check that a Rx process is ongoing */
04352   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04353   {
04354     nb_rx_data = huart->NbRxDataToProcess;
04355     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
04356     {
04357       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04358       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
04359       huart->pRxBuffPtr++;
04360       huart->RxXferCount--;
04361       isrflags = READ_REG(huart->Instance->ISR);
04362
04363       /* If some non blocking errors occurred */
04364       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
04365       {
04366         /* UART parity error interrupt occurred -------------------------------------*/
04367         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
04368         {
04369           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
04370
04371           huart->ErrorCode |= HAL_UART_ERROR_PE;
04372         }
04373
04374         /* UART frame error interrupt occurred --------------------------------------*/
04375         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04376         {
04377           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
04378
04379           huart->ErrorCode |= HAL_UART_ERROR_FE;
04380         }
04381
04382         /* UART noise error interrupt occurred --------------------------------------*/
04383         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04384         {
04385           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
04386
04387           huart->ErrorCode |= HAL_UART_ERROR_NE;
04388         }
04389
04390         /* Call UART Error Call back function if need be ----------------------------*/
04391         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
04392         {
04393           /* Non Blocking error : transfer could go on.
04394           Error is notified to user through user error callback */
04395 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04396           /*Call registered error callback*/
04397           huart->ErrorCallback(huart);
04398 #else
04399           /*Call legacy weak error callback*/
04400           HAL_UART_ErrorCallback(huart);
04401 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04402           huart->ErrorCode = HAL_UART_ERROR_NONE;
04403         }
04404       }
04405
04406       if (huart->RxXferCount == 0U)
04407       {
04408         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04409         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04410
04411         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
04412            and RX FIFO Threshold interrupt */
04413         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04414
04415         /* Rx process is completed, restore huart->RxState to Ready */
04416         huart->RxState = HAL_UART_STATE_READY;
04417
04418         /* Clear RxISR function pointer */
04419         huart->RxISR = NULL;
04420
04421         /* Initialize type of RxEvent to Transfer Complete */
04422         huart->RxEventType = HAL_UART_RXEVENT_TC;
04423
04424         if (!(IS_LPUART_INSTANCE(huart->Instance)))
04425         {
04426           /* Check that USART RTOEN bit is set */
04427           if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
04428           {
04429             /* Enable the UART Receiver Timeout Interrupt */
04430             ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
04431           }
04432         }
04433
04434         /* Check current reception Mode :
04435            If Reception till IDLE event has been selected : */
04436         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04437         {
04438           /* Set reception type to Standard */
04439           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04440
04441           /* Disable IDLE interrupt */
04442           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04443
04444           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04445           {
04446             /* Clear IDLE Flag */
04447             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04448           }
04449
04450 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04451           /*Call registered Rx Event callback*/
04452           huart->RxEventCallback(huart, huart->RxXferSize);
04453 #else
04454           /*Call legacy weak Rx Event callback*/
04455           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04456 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04457         }
04458         else
04459         {
04460           /* Standard reception API called */
04461 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04462           /*Call registered Rx complete callback*/
04463           huart->RxCpltCallback(huart);
04464 #else
04465           /*Call legacy weak Rx complete callback*/
04466           HAL_UART_RxCpltCallback(huart);
04467 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04468         }
04469       }
04470     }
04471
04472     /* When remaining number of bytes to receive is less than the RX FIFO
04473     threshold, next incoming frames are processed as if FIFO mode was
04474     disabled (i.e. one interrupt per received frame).
04475     */
04476     rxdatacount = huart->RxXferCount;
04477     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04478     {
04479       /* Disable the UART RXFT interrupt*/
04480       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04481
04482       /* Update the RxISR function pointer */
04483       huart->RxISR = UART_RxISR_8BIT;
04484
04485       /* Enable the UART Data Register Not Empty interrupt */
04486       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04487     }
04488   }
04489   else
04490   {
04491     /* Clear RXNE interrupt flag */
04492     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04493   }
04494 }
04495
04496 /**
04497   * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
04498   * @note   Function is called under interruption only, once
04499   *         interruptions have been enabled by HAL_UART_Receive_IT()
04500   * @param huart UART handle.
04501   * @retval None
04502   */
04503 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
04504 {
04505   uint16_t *tmp;
04506   uint16_t  uhMask = huart->Mask;
04507   uint16_t  uhdata;
04508   uint16_t  nb_rx_data;
04509   uint16_t  rxdatacount;
04510   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
04511   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
04512   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
04513
04514   /* Check that a Rx process is ongoing */
04515   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04516   {
04517     nb_rx_data = huart->NbRxDataToProcess;
04518     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
04519     {
04520       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04521       tmp = (uint16_t *) huart->pRxBuffPtr ;
04522       *tmp = (uint16_t)(uhdata & uhMask);
04523       huart->pRxBuffPtr += 2U;
04524       huart->RxXferCount--;
04525       isrflags = READ_REG(huart->Instance->ISR);
04526
04527       /* If some non blocking errors occurred */
04528       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
04529       {
04530         /* UART parity error interrupt occurred -------------------------------------*/
04531         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
04532         {
04533           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
04534
04535           huart->ErrorCode |= HAL_UART_ERROR_PE;
04536         }
04537
04538         /* UART frame error interrupt occurred --------------------------------------*/
04539         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04540         {
04541           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
04542
04543           huart->ErrorCode |= HAL_UART_ERROR_FE;
04544         }
04545
04546         /* UART noise error interrupt occurred --------------------------------------*/
04547         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04548         {
04549           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
04550
04551           huart->ErrorCode |= HAL_UART_ERROR_NE;
04552         }
04553
04554         /* Call UART Error Call back function if need be ----------------------------*/
04555         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
04556         {
04557           /* Non Blocking error : transfer could go on.
04558           Error is notified to user through user error callback */
04559 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04560           /*Call registered error callback*/
04561           huart->ErrorCallback(huart);
04562 #else
04563           /*Call legacy weak error callback*/
04564           HAL_UART_ErrorCallback(huart);
04565 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04566           huart->ErrorCode = HAL_UART_ERROR_NONE;
04567         }
04568       }
04569
04570       if (huart->RxXferCount == 0U)
04571       {
04572         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04573         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04574
04575         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
04576            and RX FIFO Threshold interrupt */
04577         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04578
04579         /* Rx process is completed, restore huart->RxState to Ready */
04580         huart->RxState = HAL_UART_STATE_READY;
04581
04582         /* Clear RxISR function pointer */
04583         huart->RxISR = NULL;
04584
04585         /* Initialize type of RxEvent to Transfer Complete */
04586         huart->RxEventType = HAL_UART_RXEVENT_TC;
04587
04588         if (!(IS_LPUART_INSTANCE(huart->Instance)))
04589         {
04590           /* Check that USART RTOEN bit is set */
04591           if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
04592           {
04593             /* Enable the UART Receiver Timeout Interrupt */
04594             ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
04595           }
04596         }
04597
04598         /* Check current reception Mode :
04599            If Reception till IDLE event has been selected : */
04600         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04601         {
04602           /* Set reception type to Standard */
04603           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04604
04605           /* Disable IDLE interrupt */
04606           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04607
04608           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04609           {
04610             /* Clear IDLE Flag */
04611             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04612           }
04613
04614 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04615           /*Call registered Rx Event callback*/
04616           huart->RxEventCallback(huart, huart->RxXferSize);
04617 #else
04618           /*Call legacy weak Rx Event callback*/
04619           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04620 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04621         }
04622         else
04623         {
04624           /* Standard reception API called */
04625 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04626           /*Call registered Rx complete callback*/
04627           huart->RxCpltCallback(huart);
04628 #else
04629           /*Call legacy weak Rx complete callback*/
04630           HAL_UART_RxCpltCallback(huart);
04631 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04632         }
04633       }
04634     }
04635
04636     /* When remaining number of bytes to receive is less than the RX FIFO
04637     threshold, next incoming frames are processed as if FIFO mode was
04638     disabled (i.e. one interrupt per received frame).
04639     */
04640     rxdatacount = huart->RxXferCount;
04641     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04642     {
04643       /* Disable the UART RXFT interrupt*/
04644       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04645
04646       /* Update the RxISR function pointer */
04647       huart->RxISR = UART_RxISR_16BIT;
04648
04649       /* Enable the UART Data Register Not Empty interrupt */
04650       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04651     }
04652   }
04653   else
04654   {
04655     /* Clear RXNE interrupt flag */
04656     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04657   }
04658 }
04659
04660 /**
04661   * @}
04662   */
04663
04664 #endif /* HAL_UART_MODULE_ENABLED */
04665 /**
04666   * @}
04667   */
04668
04669 /**
04670   * @}
04671   */
04672
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_uart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_UART_H
00021 #define STM32G4xx_HAL_UART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UART
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup UART_Exported_Types UART Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief UART Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
00049                                          The baud rate register is computed using the following formula:
00050                                          LPUART:
00051                                          =======
00052                                          Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
00053                                          where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
00054                                          UART:
00055                                          =====
00056                                          - If oversampling is 16 or in LIN mode,
00057                                             Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
00058                                          - If oversampling is 8,
00059                                             Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
00060                                             ((huart->Init.BaudRate)))[15:4]
00061                                             Baud Rate Register[3] =  0
00062                                             Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
00063                                             ((huart->Init.BaudRate)))[3:0]) >> 1
00064                                          where uart_ker_ck_pres is the UART input clock divided by a prescaler */
00065
00066   uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
00067                                          This parameter can be a value of @ref UARTEx_Word_Length. */
00068
00069   uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
00070                                          This parameter can be a value of @ref UART_Stop_Bits. */
00071
00072   uint32_t Parity;                  /*!< Specifies the parity mode.
00073                                          This parameter can be a value of @ref UART_Parity
00074                                          @note When parity is enabled, the computed parity is inserted
00075                                                at the MSB position of the transmitted data (9th bit when
00076                                                the word length is set to 9 data bits; 8th bit when the
00077                                                word length is set to 8 data bits). */
00078
00079   uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00080                                          This parameter can be a value of @ref UART_Mode. */
00081
00082   uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
00083                                          or disabled.
00084                                          This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00085
00086   uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
00087                                          to achieve higher speed (up to f_PCLK/8).
00088                                          This parameter can be a value of @ref UART_Over_Sampling. */
00089
00090   uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
00091                                          Selecting the single sample method increases the receiver tolerance to clock
00092                                          deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00093
00094   uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
00095                                          This parameter can be a value of @ref UART_ClockPrescaler. */
00096
00097 } UART_InitTypeDef;
00098
00099 /**
00100   * @brief  UART Advanced Features initialization structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00105                                        Advanced Features may be initialized at the same time .
00106                                        This parameter can be a value of
00107                                        @ref UART_Advanced_Features_Initialization_Type. */
00108
00109   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00110                                        This parameter can be a value of @ref UART_Tx_Inv. */
00111
00112   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00113                                        This parameter can be a value of @ref UART_Rx_Inv. */
00114
00115   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00116                                        vs negative/inverted logic).
00117                                        This parameter can be a value of @ref UART_Data_Inv. */
00118
00119   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00120                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00121
00122   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00123                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00124
00125   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00126                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00127
00128   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00129                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
00130
00131   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00132                                        detection is carried out.
00133                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00134
00135   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00136                                        This parameter can be a value of @ref UART_MSB_First. */
00137 } UART_AdvFeatureInitTypeDef;
00138
00139 /**
00140   * @brief HAL UART State definition
00141   * @note  HAL UART State value is a combination of 2 different substates:
00142   *        gState and RxState (see @ref UART_State_Definition).
00143   *        - gState contains UART state information related to global Handle management
00144   *          and also information related to Tx operations.
00145   *          gState value coding follow below described bitmap :
00146   *          b7-b6  Error information
00147   *             00 : No Error
00148   *             01 : (Not Used)
00149   *             10 : Timeout
00150   *             11 : Error
00151   *          b5     Peripheral initialization status
00152   *             0  : Reset (Peripheral not initialized)
00153   *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
00154   *          b4-b3  (not used)
00155   *             xx : Should be set to 00
00156   *          b2     Intrinsic process state
00157   *             0  : Ready
00158   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00159   *          b1     (not used)
00160   *             x  : Should be set to 0
00161   *          b0     Tx state
00162   *             0  : Ready (no Tx operation ongoing)
00163   *             1  : Busy (Tx operation ongoing)
00164   *        - RxState contains information related to Rx operations.
00165   *          RxState value coding follow below described bitmap :
00166   *          b7-b6  (not used)
00167   *             xx : Should be set to 00
00168   *          b5     Peripheral initialization status
00169   *             0  : Reset (Peripheral not initialized)
00170   *             1  : Init done (Peripheral initialized)
00171   *          b4-b2  (not used)
00172   *            xxx : Should be set to 000
00173   *          b1     Rx state
00174   *             0  : Ready (no Rx operation ongoing)
00175   *             1  : Busy (Rx operation ongoing)
00176   *          b0     (not used)
00177   *             x  : Should be set to 0.
00178   */
00179 typedef uint32_t HAL_UART_StateTypeDef;
00180
00181 /**
00182   * @brief UART clock sources definition
00183   */
00184 typedef enum
00185 {
00186   UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
00187   UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
00188   UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
00189   UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
00190   UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00191   UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00192 } UART_ClockSourceTypeDef;
00193
00194 /**
00195   * @brief HAL UART Reception type definition
00196   * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
00197   *        This parameter can be a value of @ref UART_Reception_Type_Values :
00198   *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
00199   *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
00200   *           HAL_UART_RECEPTION_TORTO            = 0x02U,
00201   *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
00202   */
00203 typedef uint32_t HAL_UART_RxTypeTypeDef;
00204
00205 /**
00206   * @brief HAL UART Rx Event type definition
00207   * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
00208   *        leading to call of the RxEvent callback.
00209   *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
00210   *           HAL_UART_RXEVENT_TC                 = 0x00U,
00211   *           HAL_UART_RXEVENT_HT                 = 0x01U,
00212   *           HAL_UART_RXEVENT_IDLE               = 0x02U,
00213   */
00214 typedef uint32_t HAL_UART_RxEventTypeTypeDef;
00215
00216 /**
00217   * @brief  UART handle Structure definition
00218   */
00219 typedef struct __UART_HandleTypeDef
00220 {
00221   USART_TypeDef            *Instance;                /*!< UART registers base address        */
00222
00223   UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
00224
00225   UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
00226
00227   const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
00228
00229   uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
00230
00231   __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
00232
00233   uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
00234
00235   uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
00236
00237   __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
00238
00239   uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
00240
00241   uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
00242                                                           This parameter can be a value of @ref UARTEx_FIFO_mode. */
00243
00244   uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
00245
00246   uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
00247
00248   __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
00249
00250   __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
00251
00252   void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
00253
00254   void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
00255
00256   DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
00257
00258   DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
00259
00260   HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
00261
00262   __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
00263                                                           and also related to Tx operations. This parameter
00264                                                           can be a value of @ref HAL_UART_StateTypeDef */
00265
00266   __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
00267                                                           parameter can be a value of @ref HAL_UART_StateTypeDef */
00268
00269   __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
00270
00271 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00272   void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
00273   void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
00274   void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
00275   void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
00276   void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
00277   void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
00278   void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
00279   void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
00280   void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
00281   void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
00282   void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
00283   void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
00284
00285   void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
00286   void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
00287 #endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
00288
00289 } UART_HandleTypeDef;
00290
00291 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00292 /**
00293   * @brief  HAL UART Callback ID enumeration definition
00294   */
00295 typedef enum
00296 {
00297   HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
00298   HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
00299   HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
00300   HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
00301   HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
00302   HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
00303   HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
00304   HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
00305   HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
00306   HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
00307   HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
00308
00309   HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
00310   HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
00311
00312 } HAL_UART_CallbackIDTypeDef;
00313
00314 /**
00315   * @brief  HAL UART Callback pointer definition
00316   */
00317 typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
00318 typedef  void (*pUART_RxEventCallbackTypeDef)
00319 (struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
00320
00321 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00322
00323 /**
00324   * @}
00325   */
00326
00327 /* Exported constants --------------------------------------------------------*/
00328 /** @defgroup UART_Exported_Constants UART Exported Constants
00329   * @{
00330   */
00331
00332 /** @defgroup UART_State_Definition UART State Code Definition
00333   * @{
00334   */
00335 #define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
00336                                                           Value is allowed for gState and RxState */
00337 #define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
00338                                                           Value is allowed for gState and RxState */
00339 #define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
00340                                                           Value is allowed for gState only */
00341 #define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
00342                                                           Value is allowed for gState only */
00343 #define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
00344                                                           Value is allowed for RxState only */
00345 #define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
00346                                                           Not to be used for neither gState nor RxState.Value is result
00347                                                           of combination (Or) between gState and RxState values */
00348 #define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
00349                                                           Value is allowed for gState only */
00350 #define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
00351                                                           Value is allowed for gState only */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup UART_Error_Definition   UART Error Definition
00357   * @{
00358   */
00359 #define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
00360 #define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
00361 #define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
00362 #define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
00363 #define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
00364 #define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
00365 #define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
00366
00367 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00368 #define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
00369 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00375   * @{
00376   */
00377 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00378 #define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
00379 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00380 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup UART_Parity  UART Parity
00386   * @{
00387   */
00388 #define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
00389 #define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
00390 #define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00396   * @{
00397   */
00398 #define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
00399 #define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
00400 #define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
00401 #define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup UART_Mode UART Transfer Mode
00407   * @{
00408   */
00409 #define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
00410 #define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
00411 #define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup UART_State  UART State
00417   * @{
00418   */
00419 #define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
00420 #define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup UART_Over_Sampling UART Over Sampling
00426   * @{
00427   */
00428 #define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
00429 #define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00435   * @{
00436   */
00437 #define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
00438 #define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup UART_ClockPrescaler  UART Clock Prescaler
00444   * @{
00445   */
00446 #define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00447 #define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00448 #define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00449 #define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00450 #define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00451 #define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00452 #define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00453 #define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00454 #define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00455 #define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00456 #define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00457 #define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00463   * @{
00464   */
00465 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
00466                                                                               on start bit              */
00467 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
00468                                                                               on falling edge           */
00469 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
00470                                                                               on 0x7F frame detection   */
00471 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
00472                                                                               on 0x55 frame detection   */
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup UART_Receiver_Timeout UART Receiver Timeout
00478   * @{
00479   */
00480 #define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
00481 #define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
00482 /**
00483   * @}
00484   */
00485
00486 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00487   * @{
00488   */
00489 #define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
00490 #define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
00491 /**
00492   * @}
00493   */
00494
00495 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00496   * @{
00497   */
00498 #define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
00499 #define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup UART_DMA_Tx    UART DMA Tx
00505   * @{
00506   */
00507 #define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
00508 #define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup UART_DMA_Rx   UART DMA Rx
00514   * @{
00515   */
00516 #define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
00517 #define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00523   * @{
00524   */
00525 #define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
00526 #define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00532   * @{
00533   */
00534 #define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
00535 #define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
00536 /**
00537   * @}
00538   */
00539
00540 /** @defgroup UART_Request_Parameters UART Request Parameters
00541   * @{
00542   */
00543 #define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00544 #define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
00545 #define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
00546 #define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00547 #define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00553   * @{
00554   */
00555 #define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
00556 #define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
00557 #define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
00558 #define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
00559 #define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
00560 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
00561 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
00562 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
00563 #define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00569   * @{
00570   */
00571 #define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
00572 #define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00578   * @{
00579   */
00580 #define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
00581 #define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00587   * @{
00588   */
00589 #define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
00590 #define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00596   * @{
00597   */
00598 #define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
00599 #define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00605   * @{
00606   */
00607 #define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
00608 #define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
00609 /**
00610   * @}
00611   */
00612
00613 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00614   * @{
00615   */
00616 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
00617 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00623   * @{
00624   */
00625 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
00626 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
00627 /**
00628   * @}
00629   */
00630
00631 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00632   * @{
00633   */
00634 #define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
00635                                                                          first disable                      */
00636 #define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
00637                                                                          first enable                       */
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00643   * @{
00644   */
00645 #define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
00646 #define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00652   * @{
00653   */
00654 #define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
00655 #define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00661   * @{
00662   */
00663 #define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
00664 /**
00665   * @}
00666   */
00667
00668 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00669   * @{
00670   */
00671 #define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
00672 #define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
00673 #define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
00674                                                                          not empty or RXFIFO is not empty            */
00675 /**
00676   * @}
00677   */
00678
00679 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00680   * @{
00681   */
00682 #define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
00683 #define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
00684 /**
00685   * @}
00686   */
00687
00688 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00689   * @{
00690   */
00691 #define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
00692                                                           position in CR1 register */
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00698   * @{
00699   */
00700 #define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
00701                                                           position in CR1 register */
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00707   * @{
00708   */
00709 #define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00715   * @{
00716   */
00717 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup UART_Flags     UART Status Flags
00723   *        Elements values convention: 0xXXXX
00724   *           - 0xXXXX  : Flag mask in the ISR register
00725   * @{
00726   */
00727 #define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
00728 #define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
00729 #define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
00730 #define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
00731 #define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
00732 #define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
00733 #define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
00734 #define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
00735 #define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
00736 #define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
00737 #define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
00738 #define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
00739 #define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
00740 #define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
00741 #define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
00742 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
00743 #define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
00744 #define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
00745 #define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
00746 #define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
00747 #define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
00748 #define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
00749 #define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
00750 #define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
00751 #define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
00752 #define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
00753 #define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
00754 /**
00755   * @}
00756   */
00757
00758 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00759   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00760   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00761   *           - XX  : Interrupt source register (2bits)
00762   *                 - 01: CR1 register
00763   *                 - 10: CR2 register
00764   *                 - 11: CR3 register
00765   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00766   *        Elements values convention: 000000000XXYYYYYb
00767   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00768   *           - XX  : Interrupt source register (2bits)
00769   *                 - 01: CR1 register
00770   *                 - 10: CR2 register
00771   *                 - 11: CR3 register
00772   *        Elements values convention: 0000ZZZZ00000000b
00773   *           - ZZZZ  : Flag position in the ISR register(4bits)
00774   * @{
00775   */
00776 #define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
00777 #define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
00778 #define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
00779 #define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
00780 #define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
00781 #define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
00782 #define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
00783 #define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
00784 #define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
00785 #define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
00786 #define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
00787 #define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
00788 #define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
00789 #define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
00790 #define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
00791 #define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
00792
00793 #define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
00794
00795 #define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
00796 #define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
00797 #define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00803   * @{
00804   */
00805 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00806 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00807 #define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
00808 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00809 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00810 #define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
00811 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00812 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00813 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00814 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00815 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00816 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
00817 /**
00818   * @}
00819   */
00820
00821 /** @defgroup UART_Reception_Type_Values  UART Reception type values
00822   * @{
00823   */
00824 #define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
00825 #define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
00826 #define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
00827 #define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
00828 /**
00829   * @}
00830   */
00831
00832 /** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
00833   * @{
00834   */
00835 #define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
00836 #define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
00837 #define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 /* Exported macros -----------------------------------------------------------*/
00847 /** @defgroup UART_Exported_Macros UART Exported Macros
00848   * @{
00849   */
00850
00851 /** @brief  Reset UART handle states.
00852   * @param  __HANDLE__ UART handle.
00853   * @retval None
00854   */
00855 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00856 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00857                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00858                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00859                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00860                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00861                                                      } while(0U)
00862 #else
00863 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00864                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00865                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00866                                                      } while(0U)
00867 #endif /*USE_HAL_UART_REGISTER_CALLBACKS */
00868
00869 /** @brief  Flush the UART Data registers.
00870   * @param  __HANDLE__ specifies the UART Handle.
00871   * @retval None
00872   */
00873 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00874   do{                \
00875     SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00876     SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00877   }  while(0U)
00878
00879 /** @brief  Clear the specified UART pending flag.
00880   * @param  __HANDLE__ specifies the UART Handle.
00881   * @param  __FLAG__ specifies the flag to check.
00882   *          This parameter can be any combination of the following values:
00883   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00884   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00885   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00886   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00887   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00888   *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
00889   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00890   *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
00891   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
00892   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00893   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00894   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
00895   * @retval None
00896   */
00897 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00898
00899 /** @brief  Clear the UART PE pending flag.
00900   * @param  __HANDLE__ specifies the UART Handle.
00901   * @retval None
00902   */
00903 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00904
00905 /** @brief  Clear the UART FE pending flag.
00906   * @param  __HANDLE__ specifies the UART Handle.
00907   * @retval None
00908   */
00909 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00910
00911 /** @brief  Clear the UART NE pending flag.
00912   * @param  __HANDLE__ specifies the UART Handle.
00913   * @retval None
00914   */
00915 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00916
00917 /** @brief  Clear the UART ORE pending flag.
00918   * @param  __HANDLE__ specifies the UART Handle.
00919   * @retval None
00920   */
00921 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00922
00923 /** @brief  Clear the UART IDLE pending flag.
00924   * @param  __HANDLE__ specifies the UART Handle.
00925   * @retval None
00926   */
00927 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00928
00929 /** @brief  Clear the UART TX FIFO empty clear flag.
00930   * @param  __HANDLE__ specifies the UART Handle.
00931   * @retval None
00932   */
00933 #define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
00934
00935 /** @brief  Check whether the specified UART flag is set or not.
00936   * @param  __HANDLE__ specifies the UART Handle.
00937   * @param  __FLAG__ specifies the flag to check.
00938   *        This parameter can be one of the following values:
00939   *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
00940   *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
00941   *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
00942   *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
00943   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00944   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00945   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00946   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
00947   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00948   *            @arg @ref UART_FLAG_CMF   Character match flag
00949   *            @arg @ref UART_FLAG_BUSY  Busy flag
00950   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00951   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00952   *            @arg @ref UART_FLAG_CTS   CTS Change flag
00953   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00954   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00955   *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
00956   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00957   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00958   *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
00959   *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
00960   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00961   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00962   *            @arg @ref UART_FLAG_NE    Noise Error flag
00963   *            @arg @ref UART_FLAG_FE    Framing Error flag
00964   *            @arg @ref UART_FLAG_PE    Parity Error flag
00965   * @retval The new state of __FLAG__ (TRUE or FALSE).
00966   */
00967 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00968
00969 /** @brief  Enable the specified UART interrupt.
00970   * @param  __HANDLE__ specifies the UART Handle.
00971   * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
00972   *          This parameter can be one of the following values:
00973   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00974   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00975   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00976   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00977   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00978   *            @arg @ref UART_IT_CM    Character match interrupt
00979   *            @arg @ref UART_IT_CTS   CTS change interrupt
00980   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00981   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00982   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00983   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00984   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00985   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00986   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00987   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00988   *            @arg @ref UART_IT_PE    Parity Error interrupt
00989   *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
00990   * @retval None
00991   */
00992 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
00993                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
00994                                                            ((__HANDLE__)->Instance->CR1 |= (1U <<\
00995                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
00996                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
00997                                                            ((__HANDLE__)->Instance->CR2 |= (1U <<\
00998                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
00999                                                            ((__HANDLE__)->Instance->CR3 |= (1U <<\
01000                                                                ((__INTERRUPT__) & UART_IT_MASK))))
01001
01002 /** @brief  Disable the specified UART interrupt.
01003   * @param  __HANDLE__ specifies the UART Handle.
01004   * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
01005   *          This parameter can be one of the following values:
01006   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01007   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01008   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01009   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01010   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01011   *            @arg @ref UART_IT_CM    Character match interrupt
01012   *            @arg @ref UART_IT_CTS   CTS change interrupt
01013   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01014   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01015   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01016   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01017   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01018   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01019   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01020   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01021   *            @arg @ref UART_IT_PE    Parity Error interrupt
01022   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01023   * @retval None
01024   */
01025 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
01026                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
01027                                                            ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
01028                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
01029                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
01030                                                            ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
01031                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
01032                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
01033                                                                ((__INTERRUPT__) & UART_IT_MASK))))
01034
01035 /** @brief  Check whether the specified UART interrupt has occurred or not.
01036   * @param  __HANDLE__ specifies the UART Handle.
01037   * @param  __INTERRUPT__ specifies the UART interrupt to check.
01038   *          This parameter can be one of the following values:
01039   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01040   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01041   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01042   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01043   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01044   *            @arg @ref UART_IT_CM    Character match interrupt
01045   *            @arg @ref UART_IT_CTS   CTS change interrupt
01046   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01047   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01048   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01049   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01050   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01051   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01052   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01053   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01054   *            @arg @ref UART_IT_PE    Parity Error interrupt
01055   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01056   * @retval The new state of __INTERRUPT__ (SET or RESET).
01057   */
01058 #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
01059                                                         & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
01060
01061 /** @brief  Check whether the specified UART interrupt source is enabled or not.
01062   * @param  __HANDLE__ specifies the UART Handle.
01063   * @param  __INTERRUPT__ specifies the UART interrupt source to check.
01064   *          This parameter can be one of the following values:
01065   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01066   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01067   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01068   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01069   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01070   *            @arg @ref UART_IT_CM    Character match interrupt
01071   *            @arg @ref UART_IT_CTS   CTS change interrupt
01072   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01073   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01074   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01075   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01076   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01077   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01078   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01079   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01080   *            @arg @ref UART_IT_PE    Parity Error interrupt
01081   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01082   * @retval The new state of __INTERRUPT__ (SET or RESET).
01083   */
01084 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
01085                                                                 (__HANDLE__)->Instance->CR1 : \
01086                                                                 (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
01087                                                                  (__HANDLE__)->Instance->CR2 : \
01088                                                                  (__HANDLE__)->Instance->CR3)) & (1U <<\
01089                                                                      (((uint16_t)(__INTERRUPT__)) &\
01090                                                                       UART_IT_MASK)))  != RESET) ? SET : RESET)
01091
01092 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
01093   * @param  __HANDLE__ specifies the UART Handle.
01094   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
01095   *                       to clear the corresponding interrupt
01096   *          This parameter can be one of the following values:
01097   *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
01098   *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
01099   *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
01100   *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
01101   *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
01102   *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
01103   *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
01104   *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
01105   *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
01106   *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
01107   *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
01108   *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
01109   * @retval None
01110   */
01111 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
01112
01113 /** @brief  Set a specific UART request flag.
01114   * @param  __HANDLE__ specifies the UART Handle.
01115   * @param  __REQ__ specifies the request flag to set
01116   *          This parameter can be one of the following values:
01117   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
01118   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
01119   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
01120   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
01121   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
01122   * @retval None
01123   */
01124 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
01125
01126 /** @brief  Enable the UART one bit sample method.
01127   * @param  __HANDLE__ specifies the UART Handle.
01128   * @retval None
01129   */
01130 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
01131
01132 /** @brief  Disable the UART one bit sample method.
01133   * @param  __HANDLE__ specifies the UART Handle.
01134   * @retval None
01135   */
01136 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
01137
01138 /** @brief  Enable UART.
01139   * @param  __HANDLE__ specifies the UART Handle.
01140   * @retval None
01141   */
01142 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
01143
01144 /** @brief  Disable UART.
01145   * @param  __HANDLE__ specifies the UART Handle.
01146   * @retval None
01147   */
01148 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
01149
01150 /** @brief  Enable CTS flow control.
01151   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
01152   *         without need to call HAL_UART_Init() function.
01153   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01154   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01155   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01156   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01157   *           - macro could only be called when corresponding UART instance is disabled
01158   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01159   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01160   * @param  __HANDLE__ specifies the UART Handle.
01161   * @retval None
01162   */
01163 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
01164   do{                                                             \
01165     ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
01166     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
01167   } while(0U)
01168
01169 /** @brief  Disable CTS flow control.
01170   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
01171   *         without need to call HAL_UART_Init() function.
01172   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01173   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01174   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01175   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01176   *           - macro could only be called when corresponding UART instance is disabled
01177   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01178   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01179   * @param  __HANDLE__ specifies the UART Handle.
01180   * @retval None
01181   */
01182 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
01183   do{                                                              \
01184     ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
01185     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
01186   } while(0U)
01187
01188 /** @brief  Enable RTS flow control.
01189   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
01190   *         without need to call HAL_UART_Init() function.
01191   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01192   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01193   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01194   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01195   *           - macro could only be called when corresponding UART instance is disabled
01196   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01197   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01198   * @param  __HANDLE__ specifies the UART Handle.
01199   * @retval None
01200   */
01201 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
01202   do{                                                            \
01203     ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
01204     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
01205   } while(0U)
01206
01207 /** @brief  Disable RTS flow control.
01208   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01209   *         without need to call HAL_UART_Init() function.
01210   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01211   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01212   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01213   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01214   *           - macro could only be called when corresponding UART instance is disabled
01215   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01216   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01217   * @param  __HANDLE__ specifies the UART Handle.
01218   * @retval None
01219   */
01220 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
01221   do{                                                             \
01222     ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01223     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
01224   } while(0U)
01225 /**
01226   * @}
01227   */
01228
01229 /* Private macros --------------------------------------------------------*/
01230 /** @defgroup UART_Private_Macros   UART Private Macros
01231   * @{
01232   */
01233 /** @brief  Get UART clok division factor from clock prescaler value.
01234   * @param  __CLOCKPRESCALER__ UART prescaler value.
01235   * @retval UART clock division factor
01236   */
01237 #define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
01238   (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
01239    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
01240    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
01241    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
01242    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
01243    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
01244    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
01245    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
01246    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
01247    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
01248    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
01249    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
01250
01251 /** @brief  BRR division operation to set BRR register with LPUART.
01252   * @param  __PCLK__ LPUART clock.
01253   * @param  __BAUD__ Baud rate set by the user.
01254   * @param  __CLOCKPRESCALER__ UART prescaler value.
01255   * @retval Division result
01256   */
01257 #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
01258   ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
01259                (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
01260   )
01261
01262 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01263   * @param  __PCLK__ UART clock.
01264   * @param  __BAUD__ Baud rate set by the user.
01265   * @param  __CLOCKPRESCALER__ UART prescaler value.
01266   * @retval Division result
01267   */
01268 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
01269   (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
01270
01271 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01272   * @param  __PCLK__ UART clock.
01273   * @param  __BAUD__ Baud rate set by the user.
01274   * @param  __CLOCKPRESCALER__ UART prescaler value.
01275   * @retval Division result
01276   */
01277 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
01278   ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
01279
01280 /** @brief  Check whether or not UART instance is Low Power UART.
01281   * @param  __HANDLE__ specifies the UART Handle.
01282   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01283   */
01284 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
01285
01286 /** @brief  Check UART Baud rate.
01287   * @param  __BAUDRATE__ Baudrate specified by the user.
01288   *         The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz)
01289   *         divided by the smallest oversampling used on the USART (i.e. 8)
01290   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01291   */
01292 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
01293
01294 /** @brief  Check UART assertion time.
01295   * @param  __TIME__ 5-bit value assertion time.
01296   * @retval Test result (TRUE or FALSE).
01297   */
01298 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01299
01300 /** @brief  Check UART deassertion time.
01301   * @param  __TIME__ 5-bit value deassertion time.
01302   * @retval Test result (TRUE or FALSE).
01303   */
01304 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01305
01306 /**
01307   * @brief Ensure that UART frame number of stop bits is valid.
01308   * @param __STOPBITS__ UART frame number of stop bits.
01309   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01310   */
01311 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01312                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01313                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01314                                         ((__STOPBITS__) == UART_STOPBITS_2))
01315
01316 /**
01317   * @brief Ensure that LPUART frame number of stop bits is valid.
01318   * @param __STOPBITS__ LPUART frame number of stop bits.
01319   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01320   */
01321 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01322                                           ((__STOPBITS__) == UART_STOPBITS_2))
01323
01324 /**
01325   * @brief Ensure that UART frame parity is valid.
01326   * @param __PARITY__ UART frame parity.
01327   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01328   */
01329 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01330                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01331                                     ((__PARITY__) == UART_PARITY_ODD))
01332
01333 /**
01334   * @brief Ensure that UART hardware flow control is valid.
01335   * @param __CONTROL__ UART hardware flow control.
01336   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01337   */
01338 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01339   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01340    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01341    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01342    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01343
01344 /**
01345   * @brief Ensure that UART communication mode is valid.
01346   * @param __MODE__ UART communication mode.
01347   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01348   */
01349 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
01350
01351 /**
01352   * @brief Ensure that UART state is valid.
01353   * @param __STATE__ UART state.
01354   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01355   */
01356 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01357                                   ((__STATE__) == UART_STATE_ENABLE))
01358
01359 /**
01360   * @brief Ensure that UART oversampling is valid.
01361   * @param __SAMPLING__ UART oversampling.
01362   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01363   */
01364 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01365                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01366
01367 /**
01368   * @brief Ensure that UART frame sampling is valid.
01369   * @param __ONEBIT__ UART frame sampling.
01370   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01371   */
01372 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01373                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01374
01375 /**
01376   * @brief Ensure that UART auto Baud rate detection mode is valid.
01377   * @param __MODE__ UART auto Baud rate detection mode.
01378   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01379   */
01380 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01381                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01382                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01383                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01384
01385 /**
01386   * @brief Ensure that UART receiver timeout setting is valid.
01387   * @param __TIMEOUT__ UART receiver timeout setting.
01388   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01389   */
01390 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01391                                                 ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01392
01393 /** @brief  Check the receiver timeout value.
01394   * @note   The maximum UART receiver timeout value is 0xFFFFFF.
01395   * @param  __TIMEOUTVALUE__ receiver timeout value.
01396   * @retval Test result (TRUE or FALSE)
01397   */
01398 #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
01399
01400 /**
01401   * @brief Ensure that UART LIN state is valid.
01402   * @param __LIN__ UART LIN state.
01403   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01404   */
01405 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01406                                      ((__LIN__) == UART_LIN_ENABLE))
01407
01408 /**
01409   * @brief Ensure that UART LIN break detection length is valid.
01410   * @param __LENGTH__ UART LIN break detection length.
01411   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01412   */
01413 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01414                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01415
01416 /**
01417   * @brief Ensure that UART DMA TX state is valid.
01418   * @param __DMATX__ UART DMA TX state.
01419   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01420   */
01421 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01422                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01423
01424 /**
01425   * @brief Ensure that UART DMA RX state is valid.
01426   * @param __DMARX__ UART DMA RX state.
01427   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01428   */
01429 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01430                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01431
01432 /**
01433   * @brief Ensure that UART half-duplex state is valid.
01434   * @param __HDSEL__ UART half-duplex state.
01435   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01436   */
01437 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01438                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01439
01440 /**
01441   * @brief Ensure that UART wake-up method is valid.
01442   * @param __WAKEUP__ UART wake-up method .
01443   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01444   */
01445 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01446                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01447
01448 /**
01449   * @brief Ensure that UART request parameter is valid.
01450   * @param __PARAM__ UART request parameter.
01451   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01452   */
01453 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01454                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01455                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01456                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01457                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01458
01459 /**
01460   * @brief Ensure that UART advanced features initialization is valid.
01461   * @param __INIT__ UART advanced features initialization.
01462   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01463   */
01464 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01465                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01466                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01467                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01468                                                             UART_ADVFEATURE_SWAP_INIT              | \
01469                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01470                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01471                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01472                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01473
01474 /**
01475   * @brief Ensure that UART frame TX inversion setting is valid.
01476   * @param __TXINV__ UART frame TX inversion setting.
01477   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01478   */
01479 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01480                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01481
01482 /**
01483   * @brief Ensure that UART frame RX inversion setting is valid.
01484   * @param __RXINV__ UART frame RX inversion setting.
01485   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01486   */
01487 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01488                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01489
01490 /**
01491   * @brief Ensure that UART frame data inversion setting is valid.
01492   * @param __DATAINV__ UART frame data inversion setting.
01493   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01494   */
01495 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01496                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01497
01498 /**
01499   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01500   * @param __SWAP__ UART frame RX/TX pins swap setting.
01501   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01502   */
01503 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01504                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01505
01506 /**
01507   * @brief Ensure that UART frame overrun setting is valid.
01508   * @param __OVERRUN__ UART frame overrun setting.
01509   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01510   */
01511 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01512                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01513
01514 /**
01515   * @brief Ensure that UART auto Baud rate state is valid.
01516   * @param __AUTOBAUDRATE__ UART auto Baud rate state.
01517   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01518   */
01519 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
01520                                                             UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01521                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01522
01523 /**
01524   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01525   * @param __DMA__ UART DMA enabling or disabling on error setting.
01526   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01527   */
01528 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01529                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01530
01531 /**
01532   * @brief Ensure that UART frame MSB first setting is valid.
01533   * @param __MSBFIRST__ UART frame MSB first setting.
01534   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01535   */
01536 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01537                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01538
01539 /**
01540   * @brief Ensure that UART stop mode state is valid.
01541   * @param __STOPMODE__ UART stop mode state.
01542   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01543   */
01544 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01545                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01546
01547 /**
01548   * @brief Ensure that UART mute mode state is valid.
01549   * @param __MUTE__ UART mute mode state.
01550   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01551   */
01552 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01553                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01554
01555 /**
01556   * @brief Ensure that UART wake-up selection is valid.
01557   * @param __WAKE__ UART wake-up selection.
01558   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01559   */
01560 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
01561                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
01562                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01563
01564 /**
01565   * @brief Ensure that UART driver enable polarity is valid.
01566   * @param __POLARITY__ UART driver enable polarity.
01567   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01568   */
01569 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01570                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01571
01572 /**
01573   * @brief Ensure that UART Prescaler is valid.
01574   * @param __CLOCKPRESCALER__ UART Prescaler value.
01575   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01576   */
01577 #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
01578                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
01579                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
01580                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
01581                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
01582                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
01583                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
01584                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
01585                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
01586                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
01587                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
01588                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
01589
01590 /**
01591   * @}
01592   */
01593
01594 /* Include UART HAL Extended module */
01595 #include "stm32g4xx_hal_uart_ex.h"
01596
01597 /* Exported functions --------------------------------------------------------*/
01598 /** @addtogroup UART_Exported_Functions UART Exported Functions
01599   * @{
01600   */
01601
01602 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01603   * @{
01604   */
01605
01606 /* Initialization and de-initialization functions  ****************************/
01607 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01608 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01609 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01610 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01611 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
01612 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01613 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01614
01615 /* Callbacks Register/UnRegister functions  ***********************************/
01616 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01617 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
01618                                             pUART_CallbackTypeDef pCallback);
01619 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
01620
01621 HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
01622 HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
01623 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01624
01625 /**
01626   * @}
01627   */
01628
01629 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01630   * @{
01631   */
01632
01633 /* IO operation functions *****************************************************/
01634 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
01635 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01636 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
01637 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01638 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
01639 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01640 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01641 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01642 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01643 /* Transfer Abort functions */
01644 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01645 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01646 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01647 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01648 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01649 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01650
01651 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01652 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01653 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01654 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01655 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01656 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01657 void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
01658 void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
01659 void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
01660
01661 void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
01662
01663 /**
01664   * @}
01665   */
01666
01667 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01668   * @{
01669   */
01670
01671 /* Peripheral Control functions  ************************************************/
01672 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
01673 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
01674 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
01675
01676 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01677 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01678 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01679 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01680 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01681 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01682
01683 /**
01684   * @}
01685   */
01686
01687 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01688   * @{
01689   */
01690
01691 /* Peripheral State and Errors functions  **************************************************/
01692 HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
01693 uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
01694
01695 /**
01696   * @}
01697   */
01698
01699 /**
01700   * @}
01701   */
01702
01703 /* Private functions -----------------------------------------------------------*/
01704 /** @addtogroup UART_Private_Functions UART Private Functions
01705   * @{
01706   */
01707 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01708 void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
01709 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01710 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01711 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01712 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
01713                                               uint32_t Tickstart, uint32_t Timeout);
01714 void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01715 HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01716 HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01717
01718 /**
01719   * @}
01720   */
01721
01722 /* Private variables -----------------------------------------------------------*/
01723 /** @defgroup UART_Private_variables UART Private variables
01724   * @{
01725   */
01726 /* Prescaler Table used in BRR computation macros.
01727    Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
01728 extern const uint16_t UARTPrescTable[12];
01729 /**
01730   * @}
01731   */
01732
01733 /**
01734   * @}
01735   */
01736
01737 /**
01738   * @}
01739   */
01740
01741 #ifdef __cplusplus
01742 }
01743 #endif
01744
01745 #endif /* STM32G4xx_HAL_UART_H */
01746
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_uart_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended UART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                ##### UART peripheral extended features  #####
00026   ==============================================================================
00027
00028     (#) Declare a UART_HandleTypeDef handle structure.
00029
00030     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00031         by calling the HAL_RS485Ex_Init() API.
00032
00033     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00034
00035         -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
00036             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00037             configured prior starting RX/TX transfers.
00038
00039   @endverbatim
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g4xx_hal.h"
00045
00046 /** @addtogroup STM32G4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup UARTEx UARTEx
00051   * @brief UART Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_UART_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
00060   * @{
00061   */
00062 /* UART RX FIFO depth */
00063 #define RX_FIFO_DEPTH 8U
00064
00065 /* UART TX FIFO depth */
00066 #define TX_FIFO_DEPTH 8U
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00075   * @{
00076   */
00077 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00078 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart            UART handle.
00151   * @param Polarity         Select the driver enable polarity.
00152   *          This parameter can be one of the following values:
00153   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00154   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00155   * @param AssertionTime    Driver Enable assertion time:
00156   *       5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *       signal and the beginning of the start bit. It is expressed in sample time
00158   *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime  Driver Enable deassertion time:
00160   *       5-bit value defining the time between the end of the last stop bit, in a
00161   *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *       oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00167                                    uint32_t DeassertionTime)
00168 {
00169   uint32_t temp;
00170
00171   /* Check the UART handle allocation */
00172   if (huart == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176   /* Check the Driver Enable UART instance */
00177   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00178
00179   /* Check the Driver Enable polarity */
00180   assert_param(IS_UART_DE_POLARITY(Polarity));
00181
00182   /* Check the Driver Enable assertion time */
00183   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00184
00185   /* Check the Driver Enable deassertion time */
00186   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00187
00188   if (huart->gState == HAL_UART_STATE_RESET)
00189   {
00190     /* Allocate lock resource and initialize it */
00191     huart->Lock = HAL_UNLOCKED;
00192
00193 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00194     UART_InitCallbacksToDefault(huart);
00195
00196     if (huart->MspInitCallback == NULL)
00197     {
00198       huart->MspInitCallback = HAL_UART_MspInit;
00199     }
00200
00201     /* Init the low level hardware */
00202     huart->MspInitCallback(huart);
00203 #else
00204     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00205     HAL_UART_MspInit(huart);
00206 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00207   }
00208
00209   huart->gState = HAL_UART_STATE_BUSY;
00210
00211   /* Disable the Peripheral */
00212   __HAL_UART_DISABLE(huart);
00213
00214   /* Perform advanced settings configuration */
00215   /* For some items, configuration requires to be done prior TE and RE bits are set */
00216   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00217   {
00218     UART_AdvFeatureConfig(huart);
00219   }
00220
00221   /* Set the UART Communication parameters */
00222   if (UART_SetConfig(huart) == HAL_ERROR)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00228   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00229
00230   /* Set the Driver Enable polarity */
00231   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00232
00233   /* Set the Driver Enable assertion and deassertion times */
00234   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00235   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00236   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
00237
00238   /* Enable the Peripheral */
00239   __HAL_UART_ENABLE(huart);
00240
00241   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00242   return (UART_CheckIdleState(huart));
00243 }
00244
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
00250   *  @brief Extended functions
00251   *
00252 @verbatim
00253  ===============================================================================
00254                       ##### IO operation functions #####
00255  ===============================================================================
00256     This subsection provides a set of Wakeup and FIFO mode related callback functions.
00257
00258     (#) Wakeup from Stop mode Callback:
00259         (+) HAL_UARTEx_WakeupCallback()
00260
00261     (#) TX/RX Fifos Callbacks:
00262         (+) HAL_UARTEx_RxFifoFullCallback()
00263         (+) HAL_UARTEx_TxFifoEmptyCallback()
00264
00265 @endverbatim
00266   * @{
00267   */
00268
00269 /**
00270   * @brief UART wakeup from Stop mode callback.
00271   * @param huart UART handle.
00272   * @retval None
00273   */
00274 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00275 {
00276   /* Prevent unused argument(s) compilation warning */
00277   UNUSED(huart);
00278
00279   /* NOTE : This function should not be modified, when the callback is needed,
00280             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00281    */
00282 }
00283
00284 /**
00285   * @brief  UART RX Fifo full callback.
00286   * @param  huart UART handle.
00287   * @retval None
00288   */
00289 __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
00290 {
00291   /* Prevent unused argument(s) compilation warning */
00292   UNUSED(huart);
00293
00294   /* NOTE : This function should not be modified, when the callback is needed,
00295             the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
00296    */
00297 }
00298
00299 /**
00300   * @brief  UART TX Fifo empty callback.
00301   * @param  huart UART handle.
00302   * @retval None
00303   */
00304 __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
00305 {
00306   /* Prevent unused argument(s) compilation warning */
00307   UNUSED(huart);
00308
00309   /* NOTE : This function should not be modified, when the callback is needed,
00310             the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
00311    */
00312 }
00313
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00319   * @brief    Extended Peripheral Control functions
00320   *
00321 @verbatim
00322  ===============================================================================
00323                       ##### Peripheral Control functions #####
00324  ===============================================================================
00325     [..] This section provides the following functions:
00326      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00327          detection length to more than 4 bits for multiprocessor address mark wake up.
00328      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00329          trigger: address match, Start Bit detection or RXNE bit status.
00330      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00331      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00332      (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
00333      (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
00334      (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00335      (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00336
00337     [..] This subsection also provides a set of additional functions providing enhanced reception
00338     services to user. (For example, these functions allow application to handle use cases
00339     where number of data to be received is unknown).
00340
00341     (#) Compared to standard reception services which only consider number of received
00342         data elements as reception completion criteria, these functions also consider additional events
00343         as triggers for updating reception status to caller :
00344        (+) Detection of inactivity period (RX line has not been active for a given period).
00345           (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
00346                for 1 frame time, after last received byte.
00347           (++) RX inactivity detected by RTO, i.e. line has been in idle state
00348                for a programmable time, after last received byte.
00349        (+) Detection that a specific character has been received.
00350
00351     (#) There are two mode of transfer:
00352        (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
00353            or till IDLE event occurs. Reception is handled only during function execution.
00354            When function exits, no data reception could occur. HAL status and number of actually received data elements,
00355            are returned by function after finishing transfer.
00356        (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
00357            These API's return the HAL status.
00358            The end of the data processing will be indicated through the
00359            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
00360            The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
00361            The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
00362
00363     (#) Blocking mode API:
00364         (+) HAL_UARTEx_ReceiveToIdle()
00365
00366     (#) Non-Blocking mode API with Interrupt:
00367         (+) HAL_UARTEx_ReceiveToIdle_IT()
00368
00369     (#) Non-Blocking mode API with DMA:
00370         (+) HAL_UARTEx_ReceiveToIdle_DMA()
00371
00372 @endverbatim
00373   * @{
00374   */
00375
00376 /**
00377   * @brief By default in multiprocessor mode, when the wake up method is set
00378   *        to address mark, the UART handles only 4-bit long addresses detection;
00379   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00380   *        long).
00381   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00382   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00383   * @param huart         UART handle.
00384   * @param AddressLength This parameter can be one of the following values:
00385   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00386   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00390 {
00391   /* Check the UART handle allocation */
00392   if (huart == NULL)
00393   {
00394     return HAL_ERROR;
00395   }
00396
00397   /* Check the address length parameter */
00398   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00399
00400   huart->gState = HAL_UART_STATE_BUSY;
00401
00402   /* Disable the Peripheral */
00403   __HAL_UART_DISABLE(huart);
00404
00405   /* Set the address length */
00406   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00407
00408   /* Enable the Peripheral */
00409   __HAL_UART_ENABLE(huart);
00410
00411   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00412   return (UART_CheckIdleState(huart));
00413 }
00414
00415 /**
00416   * @brief Set Wakeup from Stop mode interrupt flag selection.
00417   * @note It is the application responsibility to enable the interrupt used as
00418   *       usart_wkup interrupt source before entering low-power mode.
00419   * @param huart           UART handle.
00420   * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
00421   *          This parameter can be one of the following values:
00422   *          @arg @ref UART_WAKEUP_ON_ADDRESS
00423   *          @arg @ref UART_WAKEUP_ON_STARTBIT
00424   *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00425   * @retval HAL status
00426   */
00427 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00428 {
00429   HAL_StatusTypeDef status = HAL_OK;
00430   uint32_t tickstart;
00431
00432   /* check the wake-up from stop mode UART instance */
00433   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00434   /* check the wake-up selection parameter */
00435   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00436
00437   /* Process Locked */
00438   __HAL_LOCK(huart);
00439
00440   huart->gState = HAL_UART_STATE_BUSY;
00441
00442   /* Disable the Peripheral */
00443   __HAL_UART_DISABLE(huart);
00444
00445   /* Set the wake-up selection scheme */
00446   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00447
00448   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00449   {
00450     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00451   }
00452
00453   /* Enable the Peripheral */
00454   __HAL_UART_ENABLE(huart);
00455
00456   /* Init tickstart for timeout management */
00457   tickstart = HAL_GetTick();
00458
00459   /* Wait until REACK flag is set */
00460   if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00461   {
00462     status = HAL_TIMEOUT;
00463   }
00464   else
00465   {
00466     /* Initialize the UART State */
00467     huart->gState = HAL_UART_STATE_READY;
00468   }
00469
00470   /* Process Unlocked */
00471   __HAL_UNLOCK(huart);
00472
00473   return status;
00474 }
00475
00476 /**
00477   * @brief Enable UART Stop Mode.
00478   * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
00479   * @param huart UART handle.
00480   * @retval HAL status
00481   */
00482 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00483 {
00484   /* Process Locked */
00485   __HAL_LOCK(huart);
00486
00487   /* Set UESM bit */
00488   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00489
00490   /* Process Unlocked */
00491   __HAL_UNLOCK(huart);
00492
00493   return HAL_OK;
00494 }
00495
00496 /**
00497   * @brief Disable UART Stop Mode.
00498   * @param huart UART handle.
00499   * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00502 {
00503   /* Process Locked */
00504   __HAL_LOCK(huart);
00505
00506   /* Clear UESM bit */
00507   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00508
00509   /* Process Unlocked */
00510   __HAL_UNLOCK(huart);
00511
00512   return HAL_OK;
00513 }
00514
00515 /**
00516   * @brief  Enable the FIFO mode.
00517   * @param huart      UART handle.
00518   * @retval HAL status
00519   */
00520 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
00521 {
00522   uint32_t tmpcr1;
00523
00524   /* Check parameters */
00525   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00526
00527   /* Process Locked */
00528   __HAL_LOCK(huart);
00529
00530   huart->gState = HAL_UART_STATE_BUSY;
00531
00532   /* Save actual UART configuration */
00533   tmpcr1 = READ_REG(huart->Instance->CR1);
00534
00535   /* Disable UART */
00536   __HAL_UART_DISABLE(huart);
00537
00538   /* Enable FIFO mode */
00539   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00540   huart->FifoMode = UART_FIFOMODE_ENABLE;
00541
00542   /* Restore UART configuration */
00543   WRITE_REG(huart->Instance->CR1, tmpcr1);
00544
00545   /* Determine the number of data to process during RX/TX ISR execution */
00546   UARTEx_SetNbDataToProcess(huart);
00547
00548   huart->gState = HAL_UART_STATE_READY;
00549
00550   /* Process Unlocked */
00551   __HAL_UNLOCK(huart);
00552
00553   return HAL_OK;
00554 }
00555
00556 /**
00557   * @brief  Disable the FIFO mode.
00558   * @param huart      UART handle.
00559   * @retval HAL status
00560   */
00561 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
00562 {
00563   uint32_t tmpcr1;
00564
00565   /* Check parameters */
00566   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00567
00568   /* Process Locked */
00569   __HAL_LOCK(huart);
00570
00571   huart->gState = HAL_UART_STATE_BUSY;
00572
00573   /* Save actual UART configuration */
00574   tmpcr1 = READ_REG(huart->Instance->CR1);
00575
00576   /* Disable UART */
00577   __HAL_UART_DISABLE(huart);
00578
00579   /* Enable FIFO mode */
00580   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00581   huart->FifoMode = UART_FIFOMODE_DISABLE;
00582
00583   /* Restore UART configuration */
00584   WRITE_REG(huart->Instance->CR1, tmpcr1);
00585
00586   huart->gState = HAL_UART_STATE_READY;
00587
00588   /* Process Unlocked */
00589   __HAL_UNLOCK(huart);
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @brief  Set the TXFIFO threshold.
00596   * @param huart      UART handle.
00597   * @param Threshold  TX FIFO threshold value
00598   *          This parameter can be one of the following values:
00599   *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
00600   *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
00601   *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
00602   *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
00603   *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
00604   *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
00605   * @retval HAL status
00606   */
00607 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00608 {
00609   uint32_t tmpcr1;
00610
00611   /* Check parameters */
00612   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00613   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
00614
00615   /* Process Locked */
00616   __HAL_LOCK(huart);
00617
00618   huart->gState = HAL_UART_STATE_BUSY;
00619
00620   /* Save actual UART configuration */
00621   tmpcr1 = READ_REG(huart->Instance->CR1);
00622
00623   /* Disable UART */
00624   __HAL_UART_DISABLE(huart);
00625
00626   /* Update TX threshold configuration */
00627   MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00628
00629   /* Determine the number of data to process during RX/TX ISR execution */
00630   UARTEx_SetNbDataToProcess(huart);
00631
00632   /* Restore UART configuration */
00633   WRITE_REG(huart->Instance->CR1, tmpcr1);
00634
00635   huart->gState = HAL_UART_STATE_READY;
00636
00637   /* Process Unlocked */
00638   __HAL_UNLOCK(huart);
00639
00640   return HAL_OK;
00641 }
00642
00643 /**
00644   * @brief  Set the RXFIFO threshold.
00645   * @param huart      UART handle.
00646   * @param Threshold  RX FIFO threshold value
00647   *          This parameter can be one of the following values:
00648   *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
00649   *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
00650   *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
00651   *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
00652   *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
00653   *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00657 {
00658   uint32_t tmpcr1;
00659
00660   /* Check the parameters */
00661   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00662   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
00663
00664   /* Process Locked */
00665   __HAL_LOCK(huart);
00666
00667   huart->gState = HAL_UART_STATE_BUSY;
00668
00669   /* Save actual UART configuration */
00670   tmpcr1 = READ_REG(huart->Instance->CR1);
00671
00672   /* Disable UART */
00673   __HAL_UART_DISABLE(huart);
00674
00675   /* Update RX threshold configuration */
00676   MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00677
00678   /* Determine the number of data to process during RX/TX ISR execution */
00679   UARTEx_SetNbDataToProcess(huart);
00680
00681   /* Restore UART configuration */
00682   WRITE_REG(huart->Instance->CR1, tmpcr1);
00683
00684   huart->gState = HAL_UART_STATE_READY;
00685
00686   /* Process Unlocked */
00687   __HAL_UNLOCK(huart);
00688
00689   return HAL_OK;
00690 }
00691
00692 /**
00693   * @brief Receive an amount of data in blocking mode till either the expected number of data
00694   *        is received or an IDLE event occurs.
00695   * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
00696   *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
00697   *        In this case, RxLen output parameter indicates number of data available in reception buffer.
00698   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00699   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00700   *        of uint16_t available through pData.
00701   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00702   *       is not empty. Read operations from the RDR register are performed when
00703   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
00704   *       RXNE are mapped on the same bit-field.
00705   * @param huart   UART handle.
00706   * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
00707   * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
00708   * @param RxLen   Number of data elements finally received
00709   *                (could be lower than Size, in case reception ends on IDLE event)
00710   * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
00711   * @retval HAL status
00712   */
00713 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
00714                                            uint32_t Timeout)
00715 {
00716   uint8_t  *pdata8bits;
00717   uint16_t *pdata16bits;
00718   uint16_t uhMask;
00719   uint32_t tickstart;
00720
00721   /* Check that a Rx process is not already ongoing */
00722   if (huart->RxState == HAL_UART_STATE_READY)
00723   {
00724     if ((pData == NULL) || (Size == 0U))
00725     {
00726       return  HAL_ERROR;
00727     }
00728
00729     huart->ErrorCode = HAL_UART_ERROR_NONE;
00730     huart->RxState = HAL_UART_STATE_BUSY_RX;
00731     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00732     huart->RxEventType = HAL_UART_RXEVENT_TC;
00733
00734     /* Init tickstart for timeout management */
00735     tickstart = HAL_GetTick();
00736
00737     huart->RxXferSize  = Size;
00738     huart->RxXferCount = Size;
00739
00740     /* Computation of UART mask to apply to RDR register */
00741     UART_MASK_COMPUTATION(huart);
00742     uhMask = huart->Mask;
00743
00744     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00745     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00746     {
00747       pdata8bits  = NULL;
00748       pdata16bits = (uint16_t *) pData;
00749     }
00750     else
00751     {
00752       pdata8bits  = pData;
00753       pdata16bits = NULL;
00754     }
00755
00756     /* Initialize output number of received elements */
00757     *RxLen = 0U;
00758
00759     /* as long as data have to be received */
00760     while (huart->RxXferCount > 0U)
00761     {
00762       /* Check if IDLE flag is set */
00763       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
00764       {
00765         /* Clear IDLE flag in ISR */
00766         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00767
00768         /* If Set, but no data ever received, clear flag without exiting loop */
00769         /* If Set, and data has already been received, this means Idle Event is valid : End reception */
00770         if (*RxLen > 0U)
00771         {
00772           huart->RxEventType = HAL_UART_RXEVENT_IDLE;
00773           huart->RxState = HAL_UART_STATE_READY;
00774
00775           return HAL_OK;
00776         }
00777       }
00778
00779       /* Check if RXNE flag is set */
00780       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
00781       {
00782         if (pdata8bits == NULL)
00783         {
00784           *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
00785           pdata16bits++;
00786         }
00787         else
00788         {
00789           *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00790           pdata8bits++;
00791         }
00792         /* Increment number of received elements */
00793         *RxLen += 1U;
00794         huart->RxXferCount--;
00795       }
00796
00797       /* Check for the Timeout */
00798       if (Timeout != HAL_MAX_DELAY)
00799       {
00800         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00801         {
00802           huart->RxState = HAL_UART_STATE_READY;
00803
00804           return HAL_TIMEOUT;
00805         }
00806       }
00807     }
00808
00809     /* Set number of received elements in output parameter : RxLen */
00810     *RxLen = huart->RxXferSize - huart->RxXferCount;
00811     /* At end of Rx process, restore huart->RxState to Ready */
00812     huart->RxState = HAL_UART_STATE_READY;
00813
00814     return HAL_OK;
00815   }
00816   else
00817   {
00818     return HAL_BUSY;
00819   }
00820 }
00821
00822 /**
00823   * @brief Receive an amount of data in interrupt mode till either the expected number of data
00824   *        is received or an IDLE event occurs.
00825   * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
00826   *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
00827   *        number of received data elements.
00828   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00829   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00830   *        of uint16_t available through pData.
00831   * @param huart UART handle.
00832   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
00833   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
00834   * @retval HAL status
00835   */
00836 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00837 {
00838   HAL_StatusTypeDef status = HAL_OK;
00839
00840   /* Check that a Rx process is not already ongoing */
00841   if (huart->RxState == HAL_UART_STATE_READY)
00842   {
00843     if ((pData == NULL) || (Size == 0U))
00844     {
00845       return HAL_ERROR;
00846     }
00847
00848     /* Set Reception type to reception till IDLE Event*/
00849     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00850     huart->RxEventType = HAL_UART_RXEVENT_TC;
00851
00852     (void)UART_Start_Receive_IT(huart, pData, Size);
00853
00854     if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
00855     {
00856       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00857       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
00858     }
00859     else
00860     {
00861       /* In case of errors already pending when reception is started,
00862          Interrupts may have already been raised and lead to reception abortion.
00863          (Overrun error for instance).
00864          In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
00865       status = HAL_ERROR;
00866     }
00867
00868     return status;
00869   }
00870   else
00871   {
00872     return HAL_BUSY;
00873   }
00874 }
00875
00876 /**
00877   * @brief Receive an amount of data in DMA mode till either the expected number
00878   *        of data is received or an IDLE event occurs.
00879   * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
00880   *        to DMA services, transferring automatically received data elements in user reception buffer and
00881   *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
00882   *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
00883   * @note  When the UART parity is enabled (PCE = 1), the received data contain
00884   *        the parity bit (MSB position).
00885   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00886   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00887   *        of uint16_t available through pData.
00888   * @param huart UART handle.
00889   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
00890   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
00891   * @retval HAL status
00892   */
00893 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00894 {
00895   HAL_StatusTypeDef status;
00896
00897   /* Check that a Rx process is not already ongoing */
00898   if (huart->RxState == HAL_UART_STATE_READY)
00899   {
00900     if ((pData == NULL) || (Size == 0U))
00901     {
00902       return HAL_ERROR;
00903     }
00904
00905     /* Set Reception type to reception till IDLE Event*/
00906     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00907     huart->RxEventType = HAL_UART_RXEVENT_TC;
00908
00909     status =  UART_Start_Receive_DMA(huart, pData, Size);
00910
00911     /* Check Rx process has been successfully started */
00912     if (status == HAL_OK)
00913     {
00914       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
00915       {
00916         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00917         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
00918       }
00919       else
00920       {
00921         /* In case of errors already pending when reception is started,
00922            Interrupts may have already been raised and lead to reception abortion.
00923            (Overrun error for instance).
00924            In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
00925         status = HAL_ERROR;
00926       }
00927     }
00928
00929     return status;
00930   }
00931   else
00932   {
00933     return HAL_BUSY;
00934   }
00935 }
00936
00937 /**
00938   * @brief Provide Rx Event type that has lead to RxEvent callback execution.
00939   * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
00940   *        of reception process is provided to application through calls of Rx Event callback (either default one
00941   *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
00942   *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
00943   *        to Rx Event callback execution.
00944   * @note  This function is expected to be called within the user implementation of Rx Event Callback,
00945   *        in order to provide the accurate value :
00946   *        In Interrupt Mode :
00947   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
00948   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
00949   *             received data is lower than expected one)
00950   *        In DMA Mode :
00951   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
00952   *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
00953   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
00954   *             received data is lower than expected one).
00955   *        In DMA mode, RxEvent callback could be called several times;
00956   *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
00957   *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
00958   * @param  huart UART handle.
00959   * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
00960   */
00961 HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
00962 {
00963   /* Return Rx Event type value, as stored in UART handle */
00964   return (huart->RxEventType);
00965 }
00966
00967 /**
00968   * @}
00969   */
00970
00971 /**
00972   * @}
00973   */
00974
00975 /** @addtogroup UARTEx_Private_Functions
00976   * @{
00977   */
00978
00979 /**
00980   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
00981   * @param huart           UART handle.
00982   * @param WakeUpSelection UART wake up from stop mode parameters.
00983   * @retval None
00984   */
00985 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00986 {
00987   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
00988
00989   /* Set the USART address length */
00990   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
00991
00992   /* Set the USART address node */
00993   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
00994 }
00995
00996 /**
00997   * @brief Calculate the number of data to process in RX/TX ISR.
00998   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00999   *       the UART configuration registers.
01000   * @param huart UART handle.
01001   * @retval None
01002   */
01003 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
01004 {
01005   uint8_t rx_fifo_depth;
01006   uint8_t tx_fifo_depth;
01007   uint8_t rx_fifo_threshold;
01008   uint8_t tx_fifo_threshold;
01009   static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
01010   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
01011
01012   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
01013   {
01014     huart->NbTxDataToProcess = 1U;
01015     huart->NbRxDataToProcess = 1U;
01016   }
01017   else
01018   {
01019     rx_fifo_depth = RX_FIFO_DEPTH;
01020     tx_fifo_depth = TX_FIFO_DEPTH;
01021     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
01022     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
01023     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
01024                                (uint16_t)denominator[tx_fifo_threshold];
01025     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
01026                                (uint16_t)denominator[rx_fifo_threshold];
01027   }
01028 }
01029 /**
01030   * @}
01031   */
01032
01033 #endif /* HAL_UART_MODULE_ENABLED */
01034
01035 /**
01036   * @}
01037   */
01038
01039 /**
01040   * @}
01041   */
01042
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_uart_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_uart_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_UART_EX_H
00021 #define STM32G4xx_HAL_UART_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UARTEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  UART wake up from stop mode parameters
00045   */
00046 typedef struct
00047 {
00048   uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
00049                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00050                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00051                                     be filled up. */
00052
00053   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00054                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00055
00056   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00057 } UART_WakeUpTypeDef;
00058
00059 /**
00060   * @}
00061   */
00062
00063 /* Exported constants --------------------------------------------------------*/
00064 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00065   * @{
00066   */
00067
00068 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00069   * @{
00070   */
00071 #define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
00072 #define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
00073 #define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
00079   * @{
00080   */
00081 #define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
00082 #define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
00088   * @brief    UART FIFO mode
00089   * @{
00090   */
00091 #define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
00092 #define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
00098   * @brief    UART TXFIFO threshold level
00099   * @{
00100   */
00101 #define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
00102 #define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
00103 #define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
00104 #define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
00105 #define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
00106 #define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
00112   * @brief    UART RXFIFO threshold level
00113   * @{
00114   */
00115 #define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
00116 #define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
00117 #define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
00118 #define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
00119 #define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
00120 #define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
00121 /**
00122   * @}
00123   */
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported macros -----------------------------------------------------------*/
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @addtogroup UARTEx_Exported_Functions
00132   * @{
00133   */
00134
00135 /** @addtogroup UARTEx_Exported_Functions_Group1
00136   * @{
00137   */
00138
00139 /* Initialization and de-initialization functions  ****************************/
00140 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00141                                    uint32_t DeassertionTime);
00142
00143 /**
00144   * @}
00145   */
00146
00147 /** @addtogroup UARTEx_Exported_Functions_Group2
00148   * @{
00149   */
00150
00151 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00152
00153 void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
00154 void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @addtogroup UARTEx_Exported_Functions_Group3
00161   * @{
00162   */
00163
00164 /* Peripheral Control functions  **********************************************/
00165 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00166 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00167 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00168
00169 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00170
00171 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
00172 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
00173 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00174 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00175
00176 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
00177                                            uint32_t Timeout);
00178 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00179 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00180
00181 HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
00182
00183
00184 /**
00185   * @}
00186   */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macros ------------------------------------------------------------*/
00193 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00194   * @{
00195   */
00196
00197 /** @brief  Report the UART clock source.
00198   * @param  __HANDLE__ specifies the UART Handle.
00199   * @param  __CLOCKSOURCE__ output variable.
00200   * @retval UART clocking source, written in __CLOCKSOURCE__.
00201   */
00202 #if defined(UART5)
00203 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00204   do {                                                        \
00205     if((__HANDLE__)->Instance == USART1)                      \
00206     {                                                         \
00207       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00208       {                                                       \
00209         case RCC_USART1CLKSOURCE_PCLK2:                       \
00210           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00211           break;                                              \
00212         case RCC_USART1CLKSOURCE_HSI:                         \
00213           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00214           break;                                              \
00215         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00216           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00217           break;                                              \
00218         case RCC_USART1CLKSOURCE_LSE:                         \
00219           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00220           break;                                              \
00221         default:                                              \
00222           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00223           break;                                              \
00224       }                                                       \
00225     }                                                         \
00226     else if((__HANDLE__)->Instance == USART2)                 \
00227     {                                                         \
00228       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00229       {                                                       \
00230         case RCC_USART2CLKSOURCE_PCLK1:                       \
00231           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00232           break;                                              \
00233         case RCC_USART2CLKSOURCE_HSI:                         \
00234           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00235           break;                                              \
00236         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00237           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00238           break;                                              \
00239         case RCC_USART2CLKSOURCE_LSE:                         \
00240           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00241           break;                                              \
00242         default:                                              \
00243           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00244           break;                                              \
00245       }                                                       \
00246     }                                                         \
00247     else if((__HANDLE__)->Instance == USART3)                 \
00248     {                                                         \
00249       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00250       {                                                       \
00251         case RCC_USART3CLKSOURCE_PCLK1:                       \
00252           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00253           break;                                              \
00254         case RCC_USART3CLKSOURCE_HSI:                         \
00255           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00256           break;                                              \
00257         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00258           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00259           break;                                              \
00260         case RCC_USART3CLKSOURCE_LSE:                         \
00261           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00262           break;                                              \
00263         default:                                              \
00264           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00265           break;                                              \
00266       }                                                       \
00267     }                                                         \
00268     else if((__HANDLE__)->Instance == UART4)                  \
00269     {                                                         \
00270       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00271       {                                                       \
00272         case RCC_UART4CLKSOURCE_PCLK1:                        \
00273           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00274           break;                                              \
00275         case RCC_UART4CLKSOURCE_HSI:                          \
00276           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00277           break;                                              \
00278         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00279           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00280           break;                                              \
00281         case RCC_UART4CLKSOURCE_LSE:                          \
00282           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00283           break;                                              \
00284         default:                                              \
00285           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00286           break;                                              \
00287       }                                                       \
00288     }                                                         \
00289     else if((__HANDLE__)->Instance == UART5)                  \
00290     {                                                         \
00291       switch(__HAL_RCC_GET_UART5_SOURCE())                    \
00292       {                                                       \
00293         case RCC_UART5CLKSOURCE_PCLK1:                        \
00294           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00295           break;                                              \
00296         case RCC_UART5CLKSOURCE_HSI:                          \
00297           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00298           break;                                              \
00299         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00300           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00301           break;                                              \
00302         case RCC_UART5CLKSOURCE_LSE:                          \
00303           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00304           break;                                              \
00305         default:                                              \
00306           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00307           break;                                              \
00308       }                                                       \
00309     }                                                         \
00310     else if((__HANDLE__)->Instance == LPUART1)                \
00311     {                                                         \
00312       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00313       {                                                       \
00314         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00315           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00316           break;                                              \
00317         case RCC_LPUART1CLKSOURCE_HSI:                        \
00318           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00319           break;                                              \
00320         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00321           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00322           break;                                              \
00323         case RCC_LPUART1CLKSOURCE_LSE:                        \
00324           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00325           break;                                              \
00326         default:                                              \
00327           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00328           break;                                              \
00329       }                                                       \
00330     }                                                         \
00331     else                                                      \
00332     {                                                         \
00333       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00334     }                                                         \
00335   } while(0U)
00336 #elif defined(UART4)
00337 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00338   do {                                                        \
00339     if((__HANDLE__)->Instance == USART1)                      \
00340     {                                                         \
00341       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00342       {                                                       \
00343         case RCC_USART1CLKSOURCE_PCLK2:                       \
00344           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00345           break;                                              \
00346         case RCC_USART1CLKSOURCE_HSI:                         \
00347           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00348           break;                                              \
00349         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00350           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00351           break;                                              \
00352         case RCC_USART1CLKSOURCE_LSE:                         \
00353           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00354           break;                                              \
00355         default:                                              \
00356           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00357           break;                                              \
00358       }                                                       \
00359     }                                                         \
00360     else if((__HANDLE__)->Instance == USART2)                 \
00361     {                                                         \
00362       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00363       {                                                       \
00364         case RCC_USART2CLKSOURCE_PCLK1:                       \
00365           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00366           break;                                              \
00367         case RCC_USART2CLKSOURCE_HSI:                         \
00368           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00369           break;                                              \
00370         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00371           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00372           break;                                              \
00373         case RCC_USART2CLKSOURCE_LSE:                         \
00374           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00375           break;                                              \
00376         default:                                              \
00377           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00378           break;                                              \
00379       }                                                       \
00380     }                                                         \
00381     else if((__HANDLE__)->Instance == USART3)                 \
00382     {                                                         \
00383       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00384       {                                                       \
00385         case RCC_USART3CLKSOURCE_PCLK1:                       \
00386           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00387           break;                                              \
00388         case RCC_USART3CLKSOURCE_HSI:                         \
00389           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00390           break;                                              \
00391         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00392           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00393           break;                                              \
00394         case RCC_USART3CLKSOURCE_LSE:                         \
00395           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00396           break;                                              \
00397         default:                                              \
00398           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00399           break;                                              \
00400       }                                                       \
00401     }                                                         \
00402     else if((__HANDLE__)->Instance == UART4)                  \
00403     {                                                         \
00404       switch(__HAL_RCC_GET_UART4_SOURCE())                    \
00405       {                                                       \
00406         case RCC_UART4CLKSOURCE_PCLK1:                        \
00407           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00408           break;                                              \
00409         case RCC_UART4CLKSOURCE_HSI:                          \
00410           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00411           break;                                              \
00412         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00413           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00414           break;                                              \
00415         case RCC_UART4CLKSOURCE_LSE:                          \
00416           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00417           break;                                              \
00418         default:                                              \
00419           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00420           break;                                              \
00421       }                                                       \
00422     }                                                         \
00423     else if((__HANDLE__)->Instance == LPUART1)                \
00424     {                                                         \
00425       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00426       {                                                       \
00427         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00428           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00429           break;                                              \
00430         case RCC_LPUART1CLKSOURCE_HSI:                        \
00431           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00432           break;                                              \
00433         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00434           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00435           break;                                              \
00436         case RCC_LPUART1CLKSOURCE_LSE:                        \
00437           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00438           break;                                              \
00439         default:                                              \
00440           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00441           break;                                              \
00442       }                                                       \
00443     }                                                         \
00444     else                                                      \
00445     {                                                         \
00446       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00447     }                                                         \
00448   } while(0U)
00449 #else
00450 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00451   do {                                                        \
00452     if((__HANDLE__)->Instance == USART1)                      \
00453     {                                                         \
00454       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00455       {                                                       \
00456         case RCC_USART1CLKSOURCE_PCLK2:                       \
00457           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00458           break;                                              \
00459         case RCC_USART1CLKSOURCE_HSI:                         \
00460           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00461           break;                                              \
00462         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00463           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00464           break;                                              \
00465         case RCC_USART1CLKSOURCE_LSE:                         \
00466           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00467           break;                                              \
00468         default:                                              \
00469           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00470           break;                                              \
00471       }                                                       \
00472     }                                                         \
00473     else if((__HANDLE__)->Instance == USART2)                 \
00474     {                                                         \
00475       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00476       {                                                       \
00477         case RCC_USART2CLKSOURCE_PCLK1:                       \
00478           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00479           break;                                              \
00480         case RCC_USART2CLKSOURCE_HSI:                         \
00481           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00482           break;                                              \
00483         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00484           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00485           break;                                              \
00486         case RCC_USART2CLKSOURCE_LSE:                         \
00487           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00488           break;                                              \
00489         default:                                              \
00490           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00491           break;                                              \
00492       }                                                       \
00493     }                                                         \
00494     else if((__HANDLE__)->Instance == USART3)                 \
00495     {                                                         \
00496       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00497       {                                                       \
00498         case RCC_USART3CLKSOURCE_PCLK1:                       \
00499           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00500           break;                                              \
00501         case RCC_USART3CLKSOURCE_HSI:                         \
00502           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00503           break;                                              \
00504         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00505           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00506           break;                                              \
00507         case RCC_USART3CLKSOURCE_LSE:                         \
00508           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00509           break;                                              \
00510         default:                                              \
00511           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00512           break;                                              \
00513       }                                                       \
00514     }                                                         \
00515     else if((__HANDLE__)->Instance == LPUART1)                \
00516     {                                                         \
00517       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00518       {                                                       \
00519         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00520           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00521           break;                                              \
00522         case RCC_LPUART1CLKSOURCE_HSI:                        \
00523           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00524           break;                                              \
00525         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00526           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00527           break;                                              \
00528         case RCC_LPUART1CLKSOURCE_LSE:                        \
00529           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00530           break;                                              \
00531         default:                                              \
00532           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00533           break;                                              \
00534       }                                                       \
00535     }                                                         \
00536     else                                                      \
00537     {                                                         \
00538       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00539     }                                                         \
00540   } while(0U)
00541 #endif /* UART5 */
00542
00543 /** @brief  Report the UART mask to apply to retrieve the received data
00544   *         according to the word length and to the parity bits activation.
00545   * @note   If PCE = 1, the parity bit is not included in the data extracted
00546   *         by the reception API().
00547   *         This masking operation is not carried out in the case of
00548   *         DMA transfers.
00549   * @param  __HANDLE__ specifies the UART Handle.
00550   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00551   */
00552 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00553   do {                                                                \
00554     if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
00555     {                                                                 \
00556       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00557       {                                                               \
00558         (__HANDLE__)->Mask = 0x01FFU ;                                \
00559       }                                                               \
00560       else                                                            \
00561       {                                                               \
00562         (__HANDLE__)->Mask = 0x00FFU ;                                \
00563       }                                                               \
00564     }                                                                 \
00565     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
00566     {                                                                 \
00567       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00568       {                                                               \
00569         (__HANDLE__)->Mask = 0x00FFU ;                                \
00570       }                                                               \
00571       else                                                            \
00572       {                                                               \
00573         (__HANDLE__)->Mask = 0x007FU ;                                \
00574       }                                                               \
00575     }                                                                 \
00576     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
00577     {                                                                 \
00578       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00579       {                                                               \
00580         (__HANDLE__)->Mask = 0x007FU ;                                \
00581       }                                                               \
00582       else                                                            \
00583       {                                                               \
00584         (__HANDLE__)->Mask = 0x003FU ;                                \
00585       }                                                               \
00586     }                                                                 \
00587     else                                                              \
00588     {                                                                 \
00589       (__HANDLE__)->Mask = 0x0000U;                                   \
00590     }                                                                 \
00591   } while(0U)
00592
00593 /**
00594   * @brief Ensure that UART frame length is valid.
00595   * @param __LENGTH__ UART frame length.
00596   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00597   */
00598 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00599                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00600                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00601
00602 /**
00603   * @brief Ensure that UART wake-up address length is valid.
00604   * @param __ADDRESS__ UART wake-up address length.
00605   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00606   */
00607 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00608                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00609
00610 /**
00611   * @brief Ensure that UART TXFIFO threshold level is valid.
00612   * @param __THRESHOLD__ UART TXFIFO threshold level.
00613   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00614   */
00615 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
00616                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
00617                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
00618                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
00619                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
00620                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
00621
00622 /**
00623   * @brief Ensure that UART RXFIFO threshold level is valid.
00624   * @param __THRESHOLD__ UART RXFIFO threshold level.
00625   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00626   */
00627 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
00628                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
00629                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
00630                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
00631                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
00632                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
00633
00634 /**
00635   * @}
00636   */
00637
00638 /* Private functions ---------------------------------------------------------*/
00639
00640 /**
00641   * @}
00642   */
00643
00644 /**
00645   * @}
00646   */
00647
00648 #ifdef __cplusplus
00649 }
00650 #endif
00651
00652 #endif /* STM32G4xx_HAL_UART_EX_H */
00653
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_usart.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00008   *          Peripheral (USART).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2019 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026  ===============================================================================
00027                         ##### How to use this driver #####
00028  ===============================================================================
00029     [..]
00030       The USART HAL driver can be used as follows:
00031
00032       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00033       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00034           (++) Enable the USARTx interface clock.
00035           (++) USART pins configuration:
00036             (+++) Enable the clock for the USART GPIOs.
00037             (+++) Configure these USART pins as alternate function pull-up.
00038           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00039                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00040             (+++) Configure the USARTx interrupt priority.
00041             (+++) Enable the NVIC USART IRQ handle.
00042             (++) USART interrupts handling:
00043               -@@-   The specific USART interrupts (Transmission complete interrupt,
00044                   RXNE interrupt and Error Interrupts) will be managed using the macros
00045                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00046           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00047                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00048             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00049             (+++) Enable the DMAx interface clock.
00050             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00051             (+++) Configure the DMA Tx/Rx channel.
00052             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00053             (+++) Configure the priority and enable the NVIC for the transfer
00054                   complete interrupt on the DMA Tx/Rx channel.
00055
00056       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
00057           (Receiver/Transmitter) in the husart handle Init structure.
00058
00059       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00060           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00061                by calling the customized HAL_USART_MspInit(&husart) API.
00062
00063     [..]
00064      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00065         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00066         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00067
00068     ##### Callback registration #####
00069     ==================================
00070
00071     [..]
00072     The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
00073     allows the user to configure dynamically the driver callbacks.
00074
00075     [..]
00076     Use Function HAL_USART_RegisterCallback() to register a user callback.
00077     Function HAL_USART_RegisterCallback() allows to register following callbacks:
00078     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00079     (+) TxCpltCallback            : Tx Complete Callback.
00080     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00081     (+) RxCpltCallback            : Rx Complete Callback.
00082     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00083     (+) ErrorCallback             : Error Callback.
00084     (+) AbortCpltCallback         : Abort Complete Callback.
00085     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00086     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00087     (+) MspInitCallback           : USART MspInit.
00088     (+) MspDeInitCallback         : USART MspDeInit.
00089     This function takes as parameters the HAL peripheral handle, the Callback ID
00090     and a pointer to the user callback function.
00091
00092     [..]
00093     Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
00094     weak function.
00095     HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00096     and the Callback ID.
00097     This function allows to reset following callbacks:
00098     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00099     (+) TxCpltCallback            : Tx Complete Callback.
00100     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00101     (+) RxCpltCallback            : Rx Complete Callback.
00102     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00103     (+) ErrorCallback             : Error Callback.
00104     (+) AbortCpltCallback         : Abort Complete Callback.
00105     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00106     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00107     (+) MspInitCallback           : USART MspInit.
00108     (+) MspDeInitCallback         : USART MspDeInit.
00109
00110     [..]
00111     By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
00112     all callbacks are set to the corresponding weak functions:
00113     examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
00114     Exception done for MspInit and MspDeInit functions that are respectively
00115     reset to the legacy weak functions in the HAL_USART_Init()
00116     and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
00117     If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
00118     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00119
00120     [..]
00121     Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
00122     Exception done MspInit/MspDeInit that can be registered/unregistered
00123     in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
00124     MspInit/DeInit callbacks can be used during the Init/DeInit.
00125     In that case first register the MspInit/MspDeInit user callbacks
00126     using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
00127     or HAL_USART_Init() function.
00128
00129     [..]
00130     When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
00131     not defined, the callback registration feature is not available
00132     and weak callbacks are used.
00133
00134
00135   @endverbatim
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32g4xx_hal.h"
00141
00142 /** @addtogroup STM32G4xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup USART USART
00147   * @brief HAL USART Synchronous module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_USART_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /** @defgroup USART_Private_Constants USART Private Constants
00156   * @{
00157   */
00158 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00159 #define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
00160 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
00161                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
00162                                               USART_CR1_FIFOEN ))                                  /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00163
00164 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
00165                                               USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
00166                                               USART_CR2_DIS_NSS))                                  /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00167
00168 #define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))             /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
00169
00170 #define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
00171 #define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
00172 /**
00173   * @}
00174   */
00175
00176 /* Private macros ------------------------------------------------------------*/
00177 /* Private variables ---------------------------------------------------------*/
00178 /* Private function prototypes -----------------------------------------------*/
00179 /** @addtogroup USART_Private_Functions
00180   * @{
00181   */
00182 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00183 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
00184 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00185 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00186 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00187 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00190 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00191 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00192 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00194 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
00195                                                       uint32_t Tickstart, uint32_t Timeout);
00196 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00197 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00198 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
00199 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
00200 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00201 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00202 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00203 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
00204 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
00205 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00206 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00207
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported functions --------------------------------------------------------*/
00214
00215 /** @defgroup USART_Exported_Functions USART Exported Functions
00216   * @{
00217   */
00218
00219 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00220   * @brief    Initialization and Configuration functions
00221   *
00222 @verbatim
00223  ===============================================================================
00224             ##### Initialization and Configuration functions #####
00225  ===============================================================================
00226     [..]
00227     This subsection provides a set of functions allowing to initialize the USART
00228     in asynchronous and in synchronous modes.
00229       (+) For the asynchronous mode only these parameters can be configured:
00230         (++) Baud Rate
00231         (++) Word Length
00232         (++) Stop Bit
00233         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00234              in the data register is transmitted but is changed by the parity bit.
00235         (++) USART polarity
00236         (++) USART phase
00237         (++) USART LastBit
00238         (++) Receiver/transmitter modes
00239
00240     [..]
00241     The HAL_USART_Init() function follows the USART  synchronous configuration
00242     procedure (details for the procedure are available in reference manual).
00243
00244 @endverbatim
00245
00246   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00247   8-bit or 9-bit), the possible USART formats are listed in the
00248   following table.
00249
00250     Table 1. USART frame format.
00251     +-----------------------------------------------------------------------+
00252     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00253     |---------|---------|-----------|---------------------------------------|
00254     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00255     |---------|---------|-----------|---------------------------------------|
00256     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00257     |---------|---------|-----------|---------------------------------------|
00258     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00259     |---------|---------|-----------|---------------------------------------|
00260     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00261     |---------|---------|-----------|---------------------------------------|
00262     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00263     |---------|---------|-----------|---------------------------------------|
00264     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00265     +-----------------------------------------------------------------------+
00266
00267   * @{
00268   */
00269
00270 /**
00271   * @brief  Initialize the USART mode according to the specified
00272   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00273   * @param  husart USART handle.
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00277 {
00278   /* Check the USART handle allocation */
00279   if (husart == NULL)
00280   {
00281     return HAL_ERROR;
00282   }
00283
00284   /* Check the parameters */
00285   assert_param(IS_USART_INSTANCE(husart->Instance));
00286
00287   if (husart->State == HAL_USART_STATE_RESET)
00288   {
00289     /* Allocate lock resource and initialize it */
00290     husart->Lock = HAL_UNLOCKED;
00291
00292 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00293     USART_InitCallbacksToDefault(husart);
00294
00295     if (husart->MspInitCallback == NULL)
00296     {
00297       husart->MspInitCallback = HAL_USART_MspInit;
00298     }
00299
00300     /* Init the low level hardware */
00301     husart->MspInitCallback(husart);
00302 #else
00303     /* Init the low level hardware : GPIO, CLOCK */
00304     HAL_USART_MspInit(husart);
00305 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00306   }
00307
00308   husart->State = HAL_USART_STATE_BUSY;
00309
00310   /* Disable the Peripheral */
00311   __HAL_USART_DISABLE(husart);
00312
00313   /* Set the Usart Communication parameters */
00314   if (USART_SetConfig(husart) == HAL_ERROR)
00315   {
00316     return HAL_ERROR;
00317   }
00318
00319   /* In Synchronous mode, the following bits must be kept cleared:
00320   - LINEN bit in the USART_CR2 register
00321   - HDSEL, SCEN and IREN bits in the USART_CR3 register.
00322   */
00323   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00324   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00325
00326   /* Enable the Peripheral */
00327   __HAL_USART_ENABLE(husart);
00328
00329   /* TEACK and/or REACK to check before moving husart->State to Ready */
00330   return (USART_CheckIdleState(husart));
00331 }
00332
00333 /**
00334   * @brief DeInitialize the USART peripheral.
00335   * @param  husart USART handle.
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00339 {
00340   /* Check the USART handle allocation */
00341   if (husart == NULL)
00342   {
00343     return HAL_ERROR;
00344   }
00345
00346   /* Check the parameters */
00347   assert_param(IS_USART_INSTANCE(husart->Instance));
00348
00349   husart->State = HAL_USART_STATE_BUSY;
00350
00351   husart->Instance->CR1 = 0x0U;
00352   husart->Instance->CR2 = 0x0U;
00353   husart->Instance->CR3 = 0x0U;
00354
00355 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00356   if (husart->MspDeInitCallback == NULL)
00357   {
00358     husart->MspDeInitCallback = HAL_USART_MspDeInit;
00359   }
00360   /* DeInit the low level hardware */
00361   husart->MspDeInitCallback(husart);
00362 #else
00363   /* DeInit the low level hardware */
00364   HAL_USART_MspDeInit(husart);
00365 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00366
00367   husart->ErrorCode = HAL_USART_ERROR_NONE;
00368   husart->State = HAL_USART_STATE_RESET;
00369
00370   /* Process Unlock */
00371   __HAL_UNLOCK(husart);
00372
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief Initialize the USART MSP.
00378   * @param husart USART handle.
00379   * @retval None
00380   */
00381 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00382 {
00383   /* Prevent unused argument(s) compilation warning */
00384   UNUSED(husart);
00385
00386   /* NOTE : This function should not be modified, when the callback is needed,
00387             the HAL_USART_MspInit can be implemented in the user file
00388    */
00389 }
00390
00391 /**
00392   * @brief DeInitialize the USART MSP.
00393   * @param husart USART handle.
00394   * @retval None
00395   */
00396 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00397 {
00398   /* Prevent unused argument(s) compilation warning */
00399   UNUSED(husart);
00400
00401   /* NOTE : This function should not be modified, when the callback is needed,
00402             the HAL_USART_MspDeInit can be implemented in the user file
00403    */
00404 }
00405
00406 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00407 /**
00408   * @brief  Register a User USART Callback
00409   *         To be used to override the weak predefined callback
00410   * @note   The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
00411   *         to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
00412   * @param  husart usart handle
00413   * @param  CallbackID ID of the callback to be registered
00414   *         This parameter can be one of the following values:
00415   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00416   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00417   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00418   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00419   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00420   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00421   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00422   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00423   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00424   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00425   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00426   * @param  pCallback pointer to the Callback function
00427   * @retval HAL status
00428 +  */
00429 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
00430                                              pUSART_CallbackTypeDef pCallback)
00431 {
00432   HAL_StatusTypeDef status = HAL_OK;
00433
00434   if (pCallback == NULL)
00435   {
00436     /* Update the error code */
00437     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00438
00439     return HAL_ERROR;
00440   }
00441
00442   if (husart->State == HAL_USART_STATE_READY)
00443   {
00444     switch (CallbackID)
00445     {
00446       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00447         husart->TxHalfCpltCallback = pCallback;
00448         break;
00449
00450       case HAL_USART_TX_COMPLETE_CB_ID :
00451         husart->TxCpltCallback = pCallback;
00452         break;
00453
00454       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00455         husart->RxHalfCpltCallback = pCallback;
00456         break;
00457
00458       case HAL_USART_RX_COMPLETE_CB_ID :
00459         husart->RxCpltCallback = pCallback;
00460         break;
00461
00462       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00463         husart->TxRxCpltCallback = pCallback;
00464         break;
00465
00466       case HAL_USART_ERROR_CB_ID :
00467         husart->ErrorCallback = pCallback;
00468         break;
00469
00470       case HAL_USART_ABORT_COMPLETE_CB_ID :
00471         husart->AbortCpltCallback = pCallback;
00472         break;
00473
00474       case HAL_USART_RX_FIFO_FULL_CB_ID :
00475         husart->RxFifoFullCallback = pCallback;
00476         break;
00477
00478       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00479         husart->TxFifoEmptyCallback = pCallback;
00480         break;
00481
00482       case HAL_USART_MSPINIT_CB_ID :
00483         husart->MspInitCallback = pCallback;
00484         break;
00485
00486       case HAL_USART_MSPDEINIT_CB_ID :
00487         husart->MspDeInitCallback = pCallback;
00488         break;
00489
00490       default :
00491         /* Update the error code */
00492         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00493
00494         /* Return error status */
00495         status =  HAL_ERROR;
00496         break;
00497     }
00498   }
00499   else if (husart->State == HAL_USART_STATE_RESET)
00500   {
00501     switch (CallbackID)
00502     {
00503       case HAL_USART_MSPINIT_CB_ID :
00504         husart->MspInitCallback = pCallback;
00505         break;
00506
00507       case HAL_USART_MSPDEINIT_CB_ID :
00508         husart->MspDeInitCallback = pCallback;
00509         break;
00510
00511       default :
00512         /* Update the error code */
00513         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00514
00515         /* Return error status */
00516         status =  HAL_ERROR;
00517         break;
00518     }
00519   }
00520   else
00521   {
00522     /* Update the error code */
00523     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00524
00525     /* Return error status */
00526     status =  HAL_ERROR;
00527   }
00528
00529   return status;
00530 }
00531
00532 /**
00533   * @brief  Unregister an USART Callback
00534   *         USART callaback is redirected to the weak predefined callback
00535   * @note   The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
00536   *         to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
00537   * @param  husart usart handle
00538   * @param  CallbackID ID of the callback to be unregistered
00539   *         This parameter can be one of the following values:
00540   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00541   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00542   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00543   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00544   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00545   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00546   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00547   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00548   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00549   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00550   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
00554 {
00555   HAL_StatusTypeDef status = HAL_OK;
00556
00557   if (HAL_USART_STATE_READY == husart->State)
00558   {
00559     switch (CallbackID)
00560     {
00561       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00562         husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback  */
00563         break;
00564
00565       case HAL_USART_TX_COMPLETE_CB_ID :
00566         husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback       */
00567         break;
00568
00569       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00570         husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback   */
00571         break;
00572
00573       case HAL_USART_RX_COMPLETE_CB_ID :
00574         husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback       */
00575         break;
00576
00577       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00578         husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback     */
00579         break;
00580
00581       case HAL_USART_ERROR_CB_ID :
00582         husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback        */
00583         break;
00584
00585       case HAL_USART_ABORT_COMPLETE_CB_ID :
00586         husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback    */
00587         break;
00588
00589       case HAL_USART_RX_FIFO_FULL_CB_ID :
00590         husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback   */
00591         break;
00592
00593       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00594         husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback  */
00595         break;
00596
00597       case HAL_USART_MSPINIT_CB_ID :
00598         husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback      */
00599         break;
00600
00601       case HAL_USART_MSPDEINIT_CB_ID :
00602         husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback    */
00603         break;
00604
00605       default :
00606         /* Update the error code */
00607         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00608
00609         /* Return error status */
00610         status =  HAL_ERROR;
00611         break;
00612     }
00613   }
00614   else if (HAL_USART_STATE_RESET == husart->State)
00615   {
00616     switch (CallbackID)
00617     {
00618       case HAL_USART_MSPINIT_CB_ID :
00619         husart->MspInitCallback = HAL_USART_MspInit;
00620         break;
00621
00622       case HAL_USART_MSPDEINIT_CB_ID :
00623         husart->MspDeInitCallback = HAL_USART_MspDeInit;
00624         break;
00625
00626       default :
00627         /* Update the error code */
00628         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00629
00630         /* Return error status */
00631         status =  HAL_ERROR;
00632         break;
00633     }
00634   }
00635   else
00636   {
00637     /* Update the error code */
00638     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00639
00640     /* Return error status */
00641     status =  HAL_ERROR;
00642   }
00643
00644   return status;
00645 }
00646 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00647
00648
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00654   * @brief   USART Transmit and Receive functions
00655   *
00656 @verbatim
00657  ===============================================================================
00658                       ##### IO operation functions #####
00659  ===============================================================================
00660     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00661     data transfers.
00662
00663     [..] The USART supports master mode only: it cannot receive or send data related to an input
00664          clock (SCLK is always an output).
00665
00666     [..]
00667
00668     (#) There are two modes of transfer:
00669         (++) Blocking mode: The communication is performed in polling mode.
00670              The HAL status of all data processing is returned by the same function
00671              after finishing transfer.
00672         (++) No-Blocking mode: The communication is performed using Interrupts
00673              or DMA, These API's return the HAL status.
00674              The end of the data processing will be indicated through the
00675              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00676              using DMA mode.
00677              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00678              will be executed respectively at the end of the transmit or Receive process
00679              The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00680
00681     (#) Blocking mode API's are :
00682         (++) HAL_USART_Transmit() in simplex mode
00683         (++) HAL_USART_Receive() in full duplex receive only
00684         (++) HAL_USART_TransmitReceive() in full duplex mode
00685
00686     (#) Non-Blocking mode API's with Interrupt are :
00687         (++) HAL_USART_Transmit_IT() in simplex mode
00688         (++) HAL_USART_Receive_IT() in full duplex receive only
00689         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00690         (++) HAL_USART_IRQHandler()
00691
00692     (#) No-Blocking mode API's  with DMA are :
00693         (++) HAL_USART_Transmit_DMA() in simplex mode
00694         (++) HAL_USART_Receive_DMA() in full duplex receive only
00695         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00696         (++) HAL_USART_DMAPause()
00697         (++) HAL_USART_DMAResume()
00698         (++) HAL_USART_DMAStop()
00699
00700     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00701         (++) HAL_USART_TxCpltCallback()
00702         (++) HAL_USART_RxCpltCallback()
00703         (++) HAL_USART_TxHalfCpltCallback()
00704         (++) HAL_USART_RxHalfCpltCallback()
00705         (++) HAL_USART_ErrorCallback()
00706         (++) HAL_USART_TxRxCpltCallback()
00707
00708     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00709         (++) HAL_USART_Abort()
00710         (++) HAL_USART_Abort_IT()
00711
00712     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00713         (++) HAL_USART_AbortCpltCallback()
00714
00715     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00716         Errors are handled as follows :
00717         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00718              to be evaluated by user : this concerns Frame Error,
00719              Parity Error or Noise Error in Interrupt mode reception .
00720              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
00721              error type, and HAL_USART_ErrorCallback() user callback is executed.
00722              Transfer is kept ongoing on USART side.
00723              If user wants to abort it, Abort services should be called by user.
00724         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00725              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00726              Error code is set to allow user to identify error type,
00727              and HAL_USART_ErrorCallback() user callback is executed.
00728
00729 @endverbatim
00730   * @{
00731   */
00732
00733 /**
00734   * @brief  Simplex send an amount of data in blocking mode.
00735   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00736   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
00737   *         of u16 provided through pTxData.
00738   * @param  husart USART handle.
00739   * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
00740   * @param  Size Amount of data elements (u8 or u16) to be sent.
00741   * @param  Timeout Timeout duration.
00742   * @retval HAL status
00743   */
00744 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
00745                                      uint32_t Timeout)
00746 {
00747   const uint8_t  *ptxdata8bits;
00748   const uint16_t *ptxdata16bits;
00749   uint32_t tickstart;
00750
00751   if (husart->State == HAL_USART_STATE_READY)
00752   {
00753     if ((pTxData == NULL) || (Size == 0U))
00754     {
00755       return  HAL_ERROR;
00756     }
00757
00758     /* Process Locked */
00759     __HAL_LOCK(husart);
00760
00761     husart->ErrorCode = HAL_USART_ERROR_NONE;
00762     husart->State = HAL_USART_STATE_BUSY_TX;
00763
00764     /* Init tickstart for timeout management */
00765     tickstart = HAL_GetTick();
00766
00767     husart->TxXferSize = Size;
00768     husart->TxXferCount = Size;
00769
00770     /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
00771     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00772     {
00773       ptxdata8bits  = NULL;
00774       ptxdata16bits = (const uint16_t *) pTxData;
00775     }
00776     else
00777     {
00778       ptxdata8bits  = pTxData;
00779       ptxdata16bits = NULL;
00780     }
00781
00782     /* Check the remaining data to be sent */
00783     while (husart->TxXferCount > 0U)
00784     {
00785       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00786       {
00787         return HAL_TIMEOUT;
00788       }
00789       if (ptxdata8bits == NULL)
00790       {
00791         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
00792         ptxdata16bits++;
00793       }
00794       else
00795       {
00796         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
00797         ptxdata8bits++;
00798       }
00799
00800       husart->TxXferCount--;
00801     }
00802
00803     if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00804     {
00805       return HAL_TIMEOUT;
00806     }
00807
00808     /* Clear Transmission Complete Flag */
00809     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00810
00811     /* Clear overrun flag and discard the received data */
00812     __HAL_USART_CLEAR_OREFLAG(husart);
00813     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
00814     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00815
00816     /* At end of Tx process, restore husart->State to Ready */
00817     husart->State = HAL_USART_STATE_READY;
00818
00819     /* Process Unlocked */
00820     __HAL_UNLOCK(husart);
00821
00822     return HAL_OK;
00823   }
00824   else
00825   {
00826     return HAL_BUSY;
00827   }
00828 }
00829
00830 /**
00831   * @brief Receive an amount of data in blocking mode.
00832   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00833   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00834   *         the received data is handled as a set of u16. In this case, Size must indicate the number
00835   *         of u16 available through pRxData.
00836   * @param husart USART handle.
00837   * @param pRxData Pointer to data buffer (u8 or u16 data elements).
00838   * @param Size Amount of data elements (u8 or u16) to be received.
00839   * @param Timeout Timeout duration.
00840   * @retval HAL status
00841   */
00842 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00843 {
00844   uint8_t  *prxdata8bits;
00845   uint16_t *prxdata16bits;
00846   uint16_t uhMask;
00847   uint32_t tickstart;
00848
00849   if (husart->State == HAL_USART_STATE_READY)
00850   {
00851     if ((pRxData == NULL) || (Size == 0U))
00852     {
00853       return  HAL_ERROR;
00854     }
00855
00856     /* Process Locked */
00857     __HAL_LOCK(husart);
00858
00859     husart->ErrorCode = HAL_USART_ERROR_NONE;
00860     husart->State = HAL_USART_STATE_BUSY_RX;
00861
00862     /* Init tickstart for timeout management */
00863     tickstart = HAL_GetTick();
00864
00865     husart->RxXferSize = Size;
00866     husart->RxXferCount = Size;
00867
00868     /* Computation of USART mask to apply to RDR register */
00869     USART_MASK_COMPUTATION(husart);
00870     uhMask = husart->Mask;
00871
00872     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00873     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00874     {
00875       prxdata8bits  = NULL;
00876       prxdata16bits = (uint16_t *) pRxData;
00877     }
00878     else
00879     {
00880       prxdata8bits  = pRxData;
00881       prxdata16bits = NULL;
00882     }
00883
00884     /* as long as data have to be received */
00885     while (husart->RxXferCount > 0U)
00886     {
00887       if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
00888       {
00889         /* Wait until TXE flag is set to send dummy byte in order to generate the
00890         * clock for the slave to send data.
00891         * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00892         * can be written for all the cases. */
00893         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00894         {
00895           return HAL_TIMEOUT;
00896         }
00897         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
00898       }
00899
00900       /* Wait for RXNE Flag */
00901       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00902       {
00903         return HAL_TIMEOUT;
00904       }
00905
00906       if (prxdata8bits == NULL)
00907       {
00908         *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
00909         prxdata16bits++;
00910       }
00911       else
00912       {
00913         *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
00914         prxdata8bits++;
00915       }
00916
00917       husart->RxXferCount--;
00918
00919     }
00920
00921     /* Clear SPI slave underrun flag and discard transmit data */
00922     if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
00923     {
00924       __HAL_USART_CLEAR_UDRFLAG(husart);
00925       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00926     }
00927
00928     /* At end of Rx process, restore husart->State to Ready */
00929     husart->State = HAL_USART_STATE_READY;
00930
00931     /* Process Unlocked */
00932     __HAL_UNLOCK(husart);
00933
00934     return HAL_OK;
00935   }
00936   else
00937   {
00938     return HAL_BUSY;
00939   }
00940 }
00941
00942 /**
00943   * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
00944   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00945   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
00946   *         of u16 available through pTxData and through pRxData.
00947   * @param  husart USART handle.
00948   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
00949   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
00950   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
00951   * @param  Timeout Timeout duration.
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00955                                             uint16_t Size, uint32_t Timeout)
00956 {
00957   uint8_t  *prxdata8bits;
00958   uint16_t *prxdata16bits;
00959   const uint8_t  *ptxdata8bits;
00960   const uint16_t *ptxdata16bits;
00961   uint16_t uhMask;
00962   uint16_t rxdatacount;
00963   uint32_t tickstart;
00964
00965   if (husart->State == HAL_USART_STATE_READY)
00966   {
00967     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00968     {
00969       return  HAL_ERROR;
00970     }
00971
00972     /* Process Locked */
00973     __HAL_LOCK(husart);
00974
00975     husart->ErrorCode = HAL_USART_ERROR_NONE;
00976     husart->State = HAL_USART_STATE_BUSY_RX;
00977
00978     /* Init tickstart for timeout management */
00979     tickstart = HAL_GetTick();
00980
00981     husart->RxXferSize = Size;
00982     husart->TxXferSize = Size;
00983     husart->TxXferCount = Size;
00984     husart->RxXferCount = Size;
00985
00986     /* Computation of USART mask to apply to RDR register */
00987     USART_MASK_COMPUTATION(husart);
00988     uhMask = husart->Mask;
00989
00990     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00991     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00992     {
00993       prxdata8bits  = NULL;
00994       ptxdata8bits  = NULL;
00995       ptxdata16bits = (const uint16_t *) pTxData;
00996       prxdata16bits = (uint16_t *) pRxData;
00997     }
00998     else
00999     {
01000       prxdata8bits  = pRxData;
01001       ptxdata8bits  = pTxData;
01002       ptxdata16bits = NULL;
01003       prxdata16bits = NULL;
01004     }
01005
01006     if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
01007     {
01008       /* Wait until TXE flag is set to send data */
01009       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01010       {
01011         return HAL_TIMEOUT;
01012       }
01013       if (ptxdata8bits == NULL)
01014       {
01015         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01016         ptxdata16bits++;
01017       }
01018       else
01019       {
01020         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01021         ptxdata8bits++;
01022       }
01023
01024       husart->TxXferCount--;
01025     }
01026
01027     /* Check the remain data to be sent */
01028     /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
01029     rxdatacount = husart->RxXferCount;
01030     while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
01031     {
01032       if (husart->TxXferCount > 0U)
01033       {
01034         /* Wait until TXE flag is set to send data */
01035         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01036         {
01037           return HAL_TIMEOUT;
01038         }
01039         if (ptxdata8bits == NULL)
01040         {
01041           husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01042           ptxdata16bits++;
01043         }
01044         else
01045         {
01046           husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01047           ptxdata8bits++;
01048         }
01049
01050         husart->TxXferCount--;
01051       }
01052
01053       if (husart->RxXferCount > 0U)
01054       {
01055         /* Wait for RXNE Flag */
01056         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01057         {
01058           return HAL_TIMEOUT;
01059         }
01060
01061         if (prxdata8bits == NULL)
01062         {
01063           *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
01064           prxdata16bits++;
01065         }
01066         else
01067         {
01068           *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
01069           prxdata8bits++;
01070         }
01071
01072         husart->RxXferCount--;
01073       }
01074       rxdatacount = husart->RxXferCount;
01075     }
01076
01077     /* At end of TxRx process, restore husart->State to Ready */
01078     husart->State = HAL_USART_STATE_READY;
01079
01080     /* Process Unlocked */
01081     __HAL_UNLOCK(husart);
01082
01083     return HAL_OK;
01084   }
01085   else
01086   {
01087     return HAL_BUSY;
01088   }
01089 }
01090
01091 /**
01092   * @brief  Send an amount of data in interrupt mode.
01093   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01094   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01095   *         of u16 provided through pTxData.
01096   * @param  husart USART handle.
01097   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01098   * @param  Size amount of data elements (u8 or u16) to be sent.
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
01102 {
01103   if (husart->State == HAL_USART_STATE_READY)
01104   {
01105     if ((pTxData == NULL) || (Size == 0U))
01106     {
01107       return HAL_ERROR;
01108     }
01109
01110     /* Process Locked */
01111     __HAL_LOCK(husart);
01112
01113     husart->pTxBuffPtr  = pTxData;
01114     husart->TxXferSize  = Size;
01115     husart->TxXferCount = Size;
01116     husart->TxISR       = NULL;
01117
01118     husart->ErrorCode = HAL_USART_ERROR_NONE;
01119     husart->State     = HAL_USART_STATE_BUSY_TX;
01120
01121     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
01122     are not managed by the USART Transmit Process to avoid the overrun interrupt
01123     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
01124     to benefit for the frame error and noise interrupts the usart mode should be
01125     configured only for transmit "USART_MODE_TX" */
01126
01127     /* Configure Tx interrupt processing */
01128     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01129     {
01130       /* Set the Tx ISR function pointer according to the data word length */
01131       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01132       {
01133         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01134       }
01135       else
01136       {
01137         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01138       }
01139
01140       /* Process Unlocked */
01141       __HAL_UNLOCK(husart);
01142
01143       /* Enable the TX FIFO threshold interrupt */
01144       __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
01145     }
01146     else
01147     {
01148       /* Set the Tx ISR function pointer according to the data word length */
01149       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01150       {
01151         husart->TxISR = USART_TxISR_16BIT;
01152       }
01153       else
01154       {
01155         husart->TxISR = USART_TxISR_8BIT;
01156       }
01157
01158       /* Process Unlocked */
01159       __HAL_UNLOCK(husart);
01160
01161       /* Enable the USART Transmit Data Register Empty Interrupt */
01162       __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
01163     }
01164
01165     return HAL_OK;
01166   }
01167   else
01168   {
01169     return HAL_BUSY;
01170   }
01171 }
01172
01173 /**
01174   * @brief Receive an amount of data in interrupt mode.
01175   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
01176   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01177   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01178   *         of u16 available through pRxData.
01179   * @param  husart USART handle.
01180   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01181   * @param  Size amount of data elements (u8 or u16) to be received.
01182   * @retval HAL status
01183   */
01184 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01185 {
01186   uint16_t nb_dummy_data;
01187
01188   if (husart->State == HAL_USART_STATE_READY)
01189   {
01190     if ((pRxData == NULL) || (Size == 0U))
01191     {
01192       return HAL_ERROR;
01193     }
01194
01195     /* Process Locked */
01196     __HAL_LOCK(husart);
01197
01198     husart->pRxBuffPtr  = pRxData;
01199     husart->RxXferSize  = Size;
01200     husart->RxXferCount = Size;
01201     husart->RxISR       = NULL;
01202
01203     USART_MASK_COMPUTATION(husart);
01204
01205     husart->ErrorCode = HAL_USART_ERROR_NONE;
01206     husart->State = HAL_USART_STATE_BUSY_RX;
01207
01208     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01209     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01210
01211     /* Configure Rx interrupt processing */
01212     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01213     {
01214       /* Set the Rx ISR function pointer according to the data word length */
01215       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01216       {
01217         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01218       }
01219       else
01220       {
01221         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01222       }
01223
01224       /* Process Unlocked */
01225       __HAL_UNLOCK(husart);
01226
01227       /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
01228       if (husart->Init.Parity != USART_PARITY_NONE)
01229       {
01230         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01231       }
01232       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
01233     }
01234     else
01235     {
01236       /* Set the Rx ISR function pointer according to the data word length */
01237       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01238       {
01239         husart->RxISR = USART_RxISR_16BIT;
01240       }
01241       else
01242       {
01243         husart->RxISR = USART_RxISR_8BIT;
01244       }
01245
01246       /* Process Unlocked */
01247       __HAL_UNLOCK(husart);
01248
01249       /* Enable the USART Parity Error and Data Register not empty Interrupts */
01250       if (husart->Init.Parity != USART_PARITY_NONE)
01251       {
01252         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01253       }
01254       else
01255       {
01256         SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01257       }
01258     }
01259
01260     if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
01261     {
01262       /* Send dummy data in order to generate the clock for the Slave to send the next data.
01263          When FIFO mode is disabled only one data must be transferred.
01264          When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
01265       */
01266       if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01267       {
01268         for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
01269         {
01270           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01271         }
01272       }
01273       else
01274       {
01275         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01276       }
01277     }
01278
01279     return HAL_OK;
01280   }
01281   else
01282   {
01283     return HAL_BUSY;
01284   }
01285 }
01286
01287 /**
01288   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
01289   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01290   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01291   *         of u16 available through pTxData and through pRxData.
01292   * @param  husart USART handle.
01293   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01294   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01295   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
01296   * @retval HAL status
01297   */
01298 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
01299                                                uint16_t Size)
01300 {
01301
01302   if (husart->State == HAL_USART_STATE_READY)
01303   {
01304     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01305     {
01306       return HAL_ERROR;
01307     }
01308
01309     /* Process Locked */
01310     __HAL_LOCK(husart);
01311
01312     husart->pRxBuffPtr = pRxData;
01313     husart->RxXferSize = Size;
01314     husart->RxXferCount = Size;
01315     husart->pTxBuffPtr = pTxData;
01316     husart->TxXferSize = Size;
01317     husart->TxXferCount = Size;
01318
01319     /* Computation of USART mask to apply to RDR register */
01320     USART_MASK_COMPUTATION(husart);
01321
01322     husart->ErrorCode = HAL_USART_ERROR_NONE;
01323     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01324
01325     /* Configure TxRx interrupt processing */
01326     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01327     {
01328       /* Set the Rx ISR function pointer according to the data word length */
01329       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01330       {
01331         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01332         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01333       }
01334       else
01335       {
01336         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01337         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01338       }
01339
01340       /* Process Locked */
01341       __HAL_UNLOCK(husart);
01342
01343       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01344       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01345
01346       if (husart->Init.Parity != USART_PARITY_NONE)
01347       {
01348         /* Enable the USART Parity Error interrupt  */
01349         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01350       }
01351
01352       /* Enable the TX and  RX FIFO Threshold interrupts */
01353       SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
01354     }
01355     else
01356     {
01357       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01358       {
01359         husart->TxISR = USART_TxISR_16BIT;
01360         husart->RxISR = USART_RxISR_16BIT;
01361       }
01362       else
01363       {
01364         husart->TxISR = USART_TxISR_8BIT;
01365         husart->RxISR = USART_RxISR_8BIT;
01366       }
01367
01368       /* Process Locked */
01369       __HAL_UNLOCK(husart);
01370
01371       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01372       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01373
01374       /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
01375       if (husart->Init.Parity != USART_PARITY_NONE)
01376       {
01377         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01378       }
01379       else
01380       {
01381         SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01382       }
01383
01384       /* Enable the USART Transmit Data Register Empty Interrupt */
01385       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01386     }
01387
01388     return HAL_OK;
01389   }
01390   else
01391   {
01392     return HAL_BUSY;
01393   }
01394 }
01395
01396 /**
01397   * @brief Send an amount of data in DMA mode.
01398   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01399   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01400   *         of u16 provided through pTxData.
01401   * @param  husart USART handle.
01402   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01403   * @param  Size amount of data elements (u8 or u16) to be sent.
01404   * @retval HAL status
01405   */
01406 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
01407 {
01408   HAL_StatusTypeDef status = HAL_OK;
01409   const uint32_t *tmp;
01410
01411   if (husart->State == HAL_USART_STATE_READY)
01412   {
01413     if ((pTxData == NULL) || (Size == 0U))
01414     {
01415       return HAL_ERROR;
01416     }
01417
01418     /* Process Locked */
01419     __HAL_LOCK(husart);
01420
01421     husart->pTxBuffPtr = pTxData;
01422     husart->TxXferSize = Size;
01423     husart->TxXferCount = Size;
01424
01425     husart->ErrorCode = HAL_USART_ERROR_NONE;
01426     husart->State = HAL_USART_STATE_BUSY_TX;
01427
01428     if (husart->hdmatx != NULL)
01429     {
01430       /* Set the USART DMA transfer complete callback */
01431       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01432
01433       /* Set the USART DMA Half transfer complete callback */
01434       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01435
01436       /* Set the DMA error callback */
01437       husart->hdmatx->XferErrorCallback = USART_DMAError;
01438
01439       /* Enable the USART transmit DMA channel */
01440       tmp = (const uint32_t *)&pTxData;
01441       status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01442     }
01443
01444     if (status == HAL_OK)
01445     {
01446       /* Clear the TC flag in the ICR register */
01447       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01448
01449       /* Process Unlocked */
01450       __HAL_UNLOCK(husart);
01451
01452       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01453          in the USART CR3 register */
01454       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01455
01456       return HAL_OK;
01457     }
01458     else
01459     {
01460       /* Set error code to DMA */
01461       husart->ErrorCode = HAL_USART_ERROR_DMA;
01462
01463       /* Process Unlocked */
01464       __HAL_UNLOCK(husart);
01465
01466       /* Restore husart->State to ready */
01467       husart->State = HAL_USART_STATE_READY;
01468
01469       return HAL_ERROR;
01470     }
01471   }
01472   else
01473   {
01474     return HAL_BUSY;
01475   }
01476 }
01477
01478 /**
01479   * @brief Receive an amount of data in DMA mode.
01480   * @note   When the USART parity is enabled (PCE = 1), the received data contain
01481   *         the parity bit (MSB position).
01482   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
01483   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01484   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01485   *         of u16 available through pRxData.
01486   * @param  husart USART handle.
01487   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01488   * @param  Size amount of data elements (u8 or u16) to be received.
01489   * @retval HAL status
01490   */
01491 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01492 {
01493   HAL_StatusTypeDef status = HAL_OK;
01494   uint32_t *tmp = (uint32_t *)&pRxData;
01495
01496   /* Check that a Rx process is not already ongoing */
01497   if (husart->State == HAL_USART_STATE_READY)
01498   {
01499     if ((pRxData == NULL) || (Size == 0U))
01500     {
01501       return HAL_ERROR;
01502     }
01503
01504     /* Process Locked */
01505     __HAL_LOCK(husart);
01506
01507     husart->pRxBuffPtr = pRxData;
01508     husart->RxXferSize = Size;
01509     husart->pTxBuffPtr = pRxData;
01510     husart->TxXferSize = Size;
01511
01512     husart->ErrorCode = HAL_USART_ERROR_NONE;
01513     husart->State = HAL_USART_STATE_BUSY_RX;
01514
01515     if (husart->hdmarx != NULL)
01516     {
01517       /* Set the USART DMA Rx transfer complete callback */
01518       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01519
01520       /* Set the USART DMA Half transfer complete callback */
01521       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01522
01523       /* Set the USART DMA Rx transfer error callback */
01524       husart->hdmarx->XferErrorCallback = USART_DMAError;
01525
01526       /* Enable the USART receive DMA channel */
01527       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01528     }
01529
01530     if ((status == HAL_OK) &&
01531         (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
01532     {
01533       /* Enable the USART transmit DMA channel: the transmit channel is used in order
01534          to generate in the non-blocking mode the clock to the slave device,
01535          this mode isn't a simplex receive mode but a full-duplex receive mode */
01536
01537       /* Set the USART DMA Tx Complete and Error callback to Null */
01538       if (husart->hdmatx != NULL)
01539       {
01540         husart->hdmatx->XferErrorCallback = NULL;
01541         husart->hdmatx->XferHalfCpltCallback = NULL;
01542         husart->hdmatx->XferCpltCallback = NULL;
01543         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01544       }
01545     }
01546
01547     if (status == HAL_OK)
01548     {
01549       /* Process Unlocked */
01550       __HAL_UNLOCK(husart);
01551
01552       if (husart->Init.Parity != USART_PARITY_NONE)
01553       {
01554         /* Enable the USART Parity Error Interrupt */
01555         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01556       }
01557
01558       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01559       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01560
01561       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01562          in the USART CR3 register */
01563       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01564
01565       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01566          in the USART CR3 register */
01567       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01568
01569       return HAL_OK;
01570     }
01571     else
01572     {
01573       if (husart->hdmarx != NULL)
01574       {
01575         status = HAL_DMA_Abort(husart->hdmarx);
01576       }
01577
01578       /* No need to check on error code */
01579       UNUSED(status);
01580
01581       /* Set error code to DMA */
01582       husart->ErrorCode = HAL_USART_ERROR_DMA;
01583
01584       /* Process Unlocked */
01585       __HAL_UNLOCK(husart);
01586
01587       /* Restore husart->State to ready */
01588       husart->State = HAL_USART_STATE_READY;
01589
01590       return HAL_ERROR;
01591     }
01592   }
01593   else
01594   {
01595     return HAL_BUSY;
01596   }
01597 }
01598
01599 /**
01600   * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01601   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01602   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01603   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01604   *         of u16 available through pTxData and through pRxData.
01605   * @param  husart USART handle.
01606   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01607   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01608   * @param  Size amount of data elements (u8 or u16) to be received/sent.
01609   * @retval HAL status
01610   */
01611 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
01612                                                 uint16_t Size)
01613 {
01614   HAL_StatusTypeDef status;
01615   const uint32_t *tmp;
01616
01617   if (husart->State == HAL_USART_STATE_READY)
01618   {
01619     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01620     {
01621       return HAL_ERROR;
01622     }
01623
01624     /* Process Locked */
01625     __HAL_LOCK(husart);
01626
01627     husart->pRxBuffPtr = pRxData;
01628     husart->RxXferSize = Size;
01629     husart->pTxBuffPtr = pTxData;
01630     husart->TxXferSize = Size;
01631
01632     husart->ErrorCode = HAL_USART_ERROR_NONE;
01633     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01634
01635     if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
01636     {
01637       /* Set the USART DMA Rx transfer complete callback */
01638       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01639
01640       /* Set the USART DMA Half transfer complete callback */
01641       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01642
01643       /* Set the USART DMA Tx transfer complete callback */
01644       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01645
01646       /* Set the USART DMA Half transfer complete callback */
01647       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01648
01649       /* Set the USART DMA Tx transfer error callback */
01650       husart->hdmatx->XferErrorCallback = USART_DMAError;
01651
01652       /* Set the USART DMA Rx transfer error callback */
01653       husart->hdmarx->XferErrorCallback = USART_DMAError;
01654
01655       /* Enable the USART receive DMA channel */
01656       tmp = (uint32_t *)&pRxData;
01657       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
01658
01659       /* Enable the USART transmit DMA channel */
01660       if (status == HAL_OK)
01661       {
01662         tmp = (const uint32_t *)&pTxData;
01663         status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01664       }
01665     }
01666     else
01667     {
01668       status = HAL_ERROR;
01669     }
01670
01671     if (status == HAL_OK)
01672     {
01673       /* Process Unlocked */
01674       __HAL_UNLOCK(husart);
01675
01676       if (husart->Init.Parity != USART_PARITY_NONE)
01677       {
01678         /* Enable the USART Parity Error Interrupt */
01679         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01680       }
01681
01682       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01683       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01684
01685       /* Clear the TC flag in the ICR register */
01686       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01687
01688       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01689          in the USART CR3 register */
01690       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01691
01692       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01693          in the USART CR3 register */
01694       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01695
01696       return HAL_OK;
01697     }
01698     else
01699     {
01700       if (husart->hdmarx != NULL)
01701       {
01702         status = HAL_DMA_Abort(husart->hdmarx);
01703       }
01704
01705       /* No need to check on error code */
01706       UNUSED(status);
01707
01708       /* Set error code to DMA */
01709       husart->ErrorCode = HAL_USART_ERROR_DMA;
01710
01711       /* Process Unlocked */
01712       __HAL_UNLOCK(husart);
01713
01714       /* Restore husart->State to ready */
01715       husart->State = HAL_USART_STATE_READY;
01716
01717       return HAL_ERROR;
01718     }
01719   }
01720   else
01721   {
01722     return HAL_BUSY;
01723   }
01724 }
01725
01726 /**
01727   * @brief Pause the DMA Transfer.
01728   * @param  husart USART handle.
01729   * @retval HAL status
01730   */
01731 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01732 {
01733   const HAL_USART_StateTypeDef state = husart->State;
01734
01735   /* Process Locked */
01736   __HAL_LOCK(husart);
01737
01738   if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
01739       (state == HAL_USART_STATE_BUSY_TX))
01740   {
01741     /* Disable the USART DMA Tx request */
01742     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01743   }
01744   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01745            (state == HAL_USART_STATE_BUSY_TX_RX))
01746   {
01747     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01748     {
01749       /* Disable the USART DMA Tx request */
01750       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01751     }
01752     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01753     {
01754       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01755       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01756       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01757
01758       /* Disable the USART DMA Rx request */
01759       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01760     }
01761   }
01762   else
01763   {
01764     /* Nothing to do */
01765   }
01766
01767   /* Process Unlocked */
01768   __HAL_UNLOCK(husart);
01769
01770   return HAL_OK;
01771 }
01772
01773 /**
01774   * @brief Resume the DMA Transfer.
01775   * @param  husart USART handle.
01776   * @retval HAL status
01777   */
01778 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01779 {
01780   const HAL_USART_StateTypeDef state = husart->State;
01781
01782   /* Process Locked */
01783   __HAL_LOCK(husart);
01784
01785   if (state == HAL_USART_STATE_BUSY_TX)
01786   {
01787     /* Enable the USART DMA Tx request */
01788     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01789   }
01790   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01791            (state == HAL_USART_STATE_BUSY_TX_RX))
01792   {
01793     /* Clear the Overrun flag before resuming the Rx transfer*/
01794     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01795
01796     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01797     if (husart->Init.Parity != USART_PARITY_NONE)
01798     {
01799       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01800     }
01801     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01802
01803     /* Enable the USART DMA Rx request  before the DMA Tx request */
01804     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01805
01806     /* Enable the USART DMA Tx request */
01807     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01808   }
01809   else
01810   {
01811     /* Nothing to do */
01812   }
01813
01814   /* Process Unlocked */
01815   __HAL_UNLOCK(husart);
01816
01817   return HAL_OK;
01818 }
01819
01820 /**
01821   * @brief Stop the DMA Transfer.
01822   * @param  husart USART handle.
01823   * @retval HAL status
01824   */
01825 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01826 {
01827   /* The Lock is not implemented on this API to allow the user application
01828      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01829      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01830      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01831      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01832      the stream and the corresponding call back is executed. */
01833
01834   /* Disable the USART Tx/Rx DMA requests */
01835   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01836   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01837
01838   /* Abort the USART DMA tx channel */
01839   if (husart->hdmatx != NULL)
01840   {
01841     if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01842     {
01843       if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01844       {
01845         /* Set error code to DMA */
01846         husart->ErrorCode = HAL_USART_ERROR_DMA;
01847
01848         return HAL_TIMEOUT;
01849       }
01850     }
01851   }
01852   /* Abort the USART DMA rx channel */
01853   if (husart->hdmarx != NULL)
01854   {
01855     if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01856     {
01857       if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01858       {
01859         /* Set error code to DMA */
01860         husart->ErrorCode = HAL_USART_ERROR_DMA;
01861
01862         return HAL_TIMEOUT;
01863       }
01864     }
01865   }
01866
01867   USART_EndTransfer(husart);
01868   husart->State = HAL_USART_STATE_READY;
01869
01870   return HAL_OK;
01871 }
01872
01873 /**
01874   * @brief  Abort ongoing transfers (blocking mode).
01875   * @param  husart USART handle.
01876   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01877   *         This procedure performs following operations :
01878   *           - Disable USART Interrupts (Tx and Rx)
01879   *           - Disable the DMA transfer in the peripheral register (if enabled)
01880   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01881   *           - Set handle State to READY
01882   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01883   * @retval HAL status
01884   */
01885 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01886 {
01887   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01888   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
01889                                     USART_CR1_TCIE));
01890   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01891
01892   /* Abort the USART DMA Tx channel if enabled */
01893   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01894   {
01895     /* Disable the USART DMA Tx request if enabled */
01896     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01897
01898     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01899     if (husart->hdmatx != NULL)
01900     {
01901       /* Set the USART DMA Abort callback to Null.
01902          No call back execution at end of DMA abort procedure */
01903       husart->hdmatx->XferAbortCallback = NULL;
01904
01905       if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01906       {
01907         if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01908         {
01909           /* Set error code to DMA */
01910           husart->ErrorCode = HAL_USART_ERROR_DMA;
01911
01912           return HAL_TIMEOUT;
01913         }
01914       }
01915     }
01916   }
01917
01918   /* Abort the USART DMA Rx channel if enabled */
01919   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01920   {
01921     /* Disable the USART DMA Rx request if enabled */
01922     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01923
01924     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01925     if (husart->hdmarx != NULL)
01926     {
01927       /* Set the USART DMA Abort callback to Null.
01928          No call back execution at end of DMA abort procedure */
01929       husart->hdmarx->XferAbortCallback = NULL;
01930
01931       if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01932       {
01933         if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01934         {
01935           /* Set error code to DMA */
01936           husart->ErrorCode = HAL_USART_ERROR_DMA;
01937
01938           return HAL_TIMEOUT;
01939         }
01940       }
01941     }
01942   }
01943
01944   /* Reset Tx and Rx transfer counters */
01945   husart->TxXferCount = 0U;
01946   husart->RxXferCount = 0U;
01947
01948   /* Clear the Error flags in the ICR register */
01949   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01950
01951   /* Flush the whole TX FIFO (if needed) */
01952   if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01953   {
01954     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
01955   }
01956
01957   /* Discard the received data */
01958   __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
01959
01960   /* Restore husart->State to Ready */
01961   husart->State  = HAL_USART_STATE_READY;
01962
01963   /* Reset Handle ErrorCode to No Error */
01964   husart->ErrorCode = HAL_USART_ERROR_NONE;
01965
01966   return HAL_OK;
01967 }
01968
01969 /**
01970   * @brief  Abort ongoing transfers (Interrupt mode).
01971   * @param  husart USART handle.
01972   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01973   *         This procedure performs following operations :
01974   *           - Disable USART Interrupts (Tx and Rx)
01975   *           - Disable the DMA transfer in the peripheral register (if enabled)
01976   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01977   *           - Set handle State to READY
01978   *           - At abort completion, call user abort complete callback
01979   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01980   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01981   * @retval HAL status
01982   */
01983 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01984 {
01985   uint32_t abortcplt = 1U;
01986
01987   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01988   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
01989                                     USART_CR1_TCIE));
01990   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01991
01992   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01993      before any call to DMA Abort functions */
01994   /* DMA Tx Handle is valid */
01995   if (husart->hdmatx != NULL)
01996   {
01997     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01998        Otherwise, set it to NULL */
01999     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02000     {
02001       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
02002     }
02003     else
02004     {
02005       husart->hdmatx->XferAbortCallback = NULL;
02006     }
02007   }
02008   /* DMA Rx Handle is valid */
02009   if (husart->hdmarx != NULL)
02010   {
02011     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
02012        Otherwise, set it to NULL */
02013     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02014     {
02015       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
02016     }
02017     else
02018     {
02019       husart->hdmarx->XferAbortCallback = NULL;
02020     }
02021   }
02022
02023   /* Abort the USART DMA Tx channel if enabled */
02024   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02025   {
02026     /* Disable DMA Tx at USART level */
02027     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02028
02029     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
02030     if (husart->hdmatx != NULL)
02031     {
02032       /* USART Tx DMA Abort callback has already been initialised :
02033          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02034
02035       /* Abort DMA TX */
02036       if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
02037       {
02038         husart->hdmatx->XferAbortCallback = NULL;
02039       }
02040       else
02041       {
02042         abortcplt = 0U;
02043       }
02044     }
02045   }
02046
02047   /* Abort the USART DMA Rx channel if enabled */
02048   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02049   {
02050     /* Disable the USART DMA Rx request if enabled */
02051     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02052
02053     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
02054     if (husart->hdmarx != NULL)
02055     {
02056       /* USART Rx DMA Abort callback has already been initialised :
02057          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02058
02059       /* Abort DMA RX */
02060       if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02061       {
02062         husart->hdmarx->XferAbortCallback = NULL;
02063         abortcplt = 1U;
02064       }
02065       else
02066       {
02067         abortcplt = 0U;
02068       }
02069     }
02070   }
02071
02072   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
02073   if (abortcplt == 1U)
02074   {
02075     /* Reset Tx and Rx transfer counters */
02076     husart->TxXferCount = 0U;
02077     husart->RxXferCount = 0U;
02078
02079     /* Reset errorCode */
02080     husart->ErrorCode = HAL_USART_ERROR_NONE;
02081
02082     /* Clear the Error flags in the ICR register */
02083     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02084
02085     /* Flush the whole TX FIFO (if needed) */
02086     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
02087     {
02088       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
02089     }
02090
02091     /* Discard the received data */
02092     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
02093
02094     /* Restore husart->State to Ready */
02095     husart->State  = HAL_USART_STATE_READY;
02096
02097     /* As no DMA to be aborted, call directly user Abort complete callback */
02098 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02099     /* Call registered Abort Complete Callback */
02100     husart->AbortCpltCallback(husart);
02101 #else
02102     /* Call legacy weak Abort Complete Callback */
02103     HAL_USART_AbortCpltCallback(husart);
02104 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02105   }
02106
02107   return HAL_OK;
02108 }
02109
02110 /**
02111   * @brief  Handle USART interrupt request.
02112   * @param  husart USART handle.
02113   * @retval None
02114   */
02115 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
02116 {
02117   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
02118   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
02119   uint32_t cr3its     = READ_REG(husart->Instance->CR3);
02120
02121   uint32_t errorflags;
02122   uint32_t errorcode;
02123
02124   /* If no error occurs */
02125   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
02126                                       USART_ISR_UDR));
02127   if (errorflags == 0U)
02128   {
02129     /* USART in mode Receiver ---------------------------------------------------*/
02130     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02131         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02132             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02133     {
02134       if (husart->RxISR != NULL)
02135       {
02136         husart->RxISR(husart);
02137       }
02138       return;
02139     }
02140   }
02141
02142   /* If some errors occur */
02143   if ((errorflags != 0U)
02144       && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02145           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
02146   {
02147     /* USART parity error interrupt occurred -------------------------------------*/
02148     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02149     {
02150       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
02151
02152       husart->ErrorCode |= HAL_USART_ERROR_PE;
02153     }
02154
02155     /* USART frame error interrupt occurred --------------------------------------*/
02156     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02157     {
02158       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
02159
02160       husart->ErrorCode |= HAL_USART_ERROR_FE;
02161     }
02162
02163     /* USART noise error interrupt occurred --------------------------------------*/
02164     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02165     {
02166       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
02167
02168       husart->ErrorCode |= HAL_USART_ERROR_NE;
02169     }
02170
02171     /* USART Over-Run interrupt occurred -----------------------------------------*/
02172     if (((isrflags & USART_ISR_ORE) != 0U)
02173         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02174             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02175     {
02176       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
02177
02178       husart->ErrorCode |= HAL_USART_ERROR_ORE;
02179     }
02180
02181     /* USART Receiver Timeout interrupt occurred ---------------------------------*/
02182     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02183     {
02184       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
02185
02186       husart->ErrorCode |= HAL_USART_ERROR_RTO;
02187     }
02188
02189     /* USART SPI slave underrun error interrupt occurred -------------------------*/
02190     if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02191     {
02192       /* Ignore SPI slave underrun errors when reception is going on */
02193       if (husart->State == HAL_USART_STATE_BUSY_RX)
02194       {
02195         __HAL_USART_CLEAR_UDRFLAG(husart);
02196         return;
02197       }
02198       else
02199       {
02200         __HAL_USART_CLEAR_UDRFLAG(husart);
02201         husart->ErrorCode |= HAL_USART_ERROR_UDR;
02202       }
02203     }
02204
02205     /* Call USART Error Call back function if need be --------------------------*/
02206     if (husart->ErrorCode != HAL_USART_ERROR_NONE)
02207     {
02208       /* USART in mode Receiver ---------------------------------------------------*/
02209       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02210           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02211               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02212       {
02213         if (husart->RxISR != NULL)
02214         {
02215           husart->RxISR(husart);
02216         }
02217       }
02218
02219       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
02220          consider error as blocking */
02221       errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
02222       if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
02223           (errorcode != 0U))
02224       {
02225         /* Blocking error : transfer is aborted
02226            Set the USART state ready to be able to start again the process,
02227            Disable Interrupts, and disable DMA requests, if ongoing */
02228         USART_EndTransfer(husart);
02229
02230         /* Abort the USART DMA Rx channel if enabled */
02231         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02232         {
02233           /* Disable the USART DMA Rx request if enabled */
02234           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
02235
02236           /* Abort the USART DMA Tx channel */
02237           if (husart->hdmatx != NULL)
02238           {
02239             /* Set the USART Tx DMA Abort callback to NULL : no callback
02240                executed at end of DMA abort procedure */
02241             husart->hdmatx->XferAbortCallback = NULL;
02242
02243             /* Abort DMA TX */
02244             (void)HAL_DMA_Abort_IT(husart->hdmatx);
02245           }
02246
02247           /* Abort the USART DMA Rx channel */
02248           if (husart->hdmarx != NULL)
02249           {
02250             /* Set the USART Rx DMA Abort callback :
02251                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
02252             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
02253
02254             /* Abort DMA RX */
02255             if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02256             {
02257               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
02258               husart->hdmarx->XferAbortCallback(husart->hdmarx);
02259             }
02260           }
02261           else
02262           {
02263             /* Call user error callback */
02264 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02265             /* Call registered Error Callback */
02266             husart->ErrorCallback(husart);
02267 #else
02268             /* Call legacy weak Error Callback */
02269             HAL_USART_ErrorCallback(husart);
02270 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02271           }
02272         }
02273         else
02274         {
02275           /* Call user error callback */
02276 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02277           /* Call registered Error Callback */
02278           husart->ErrorCallback(husart);
02279 #else
02280           /* Call legacy weak Error Callback */
02281           HAL_USART_ErrorCallback(husart);
02282 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02283         }
02284       }
02285       else
02286       {
02287         /* Non Blocking error : transfer could go on.
02288            Error is notified to user through user error callback */
02289 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02290         /* Call registered Error Callback */
02291         husart->ErrorCallback(husart);
02292 #else
02293         /* Call legacy weak Error Callback */
02294         HAL_USART_ErrorCallback(husart);
02295 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02296         husart->ErrorCode = HAL_USART_ERROR_NONE;
02297       }
02298     }
02299     return;
02300
02301   } /* End if some error occurs */
02302
02303
02304   /* USART in mode Transmitter ------------------------------------------------*/
02305   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02306       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02307           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02308   {
02309     if (husart->TxISR != NULL)
02310     {
02311       husart->TxISR(husart);
02312     }
02313     return;
02314   }
02315
02316   /* USART in mode Transmitter (transmission end) -----------------------------*/
02317   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02318   {
02319     USART_EndTransmit_IT(husart);
02320     return;
02321   }
02322
02323   /* USART TX Fifo Empty occurred ----------------------------------------------*/
02324   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02325   {
02326 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02327     /* Call registered Tx Fifo Empty Callback */
02328     husart->TxFifoEmptyCallback(husart);
02329 #else
02330     /* Call legacy weak Tx Fifo Empty Callback */
02331     HAL_USARTEx_TxFifoEmptyCallback(husart);
02332 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02333     return;
02334   }
02335
02336   /* USART RX Fifo Full occurred ----------------------------------------------*/
02337   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02338   {
02339 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02340     /* Call registered Rx Fifo Full Callback */
02341     husart->RxFifoFullCallback(husart);
02342 #else
02343     /* Call legacy weak Rx Fifo Full Callback */
02344     HAL_USARTEx_RxFifoFullCallback(husart);
02345 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02346     return;
02347   }
02348 }
02349
02350 /**
02351   * @brief Tx Transfer completed callback.
02352   * @param husart USART handle.
02353   * @retval None
02354   */
02355 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
02356 {
02357   /* Prevent unused argument(s) compilation warning */
02358   UNUSED(husart);
02359
02360   /* NOTE : This function should not be modified, when the callback is needed,
02361             the HAL_USART_TxCpltCallback can be implemented in the user file.
02362    */
02363 }
02364
02365 /**
02366   * @brief  Tx Half Transfer completed callback.
02367   * @param husart USART handle.
02368   * @retval None
02369   */
02370 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
02371 {
02372   /* Prevent unused argument(s) compilation warning */
02373   UNUSED(husart);
02374
02375   /* NOTE: This function should not be modified, when the callback is needed,
02376            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
02377    */
02378 }
02379
02380 /**
02381   * @brief  Rx Transfer completed callback.
02382   * @param husart USART handle.
02383   * @retval None
02384   */
02385 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
02386 {
02387   /* Prevent unused argument(s) compilation warning */
02388   UNUSED(husart);
02389
02390   /* NOTE: This function should not be modified, when the callback is needed,
02391            the HAL_USART_RxCpltCallback can be implemented in the user file.
02392    */
02393 }
02394
02395 /**
02396   * @brief Rx Half Transfer completed callback.
02397   * @param husart USART handle.
02398   * @retval None
02399   */
02400 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
02401 {
02402   /* Prevent unused argument(s) compilation warning */
02403   UNUSED(husart);
02404
02405   /* NOTE : This function should not be modified, when the callback is needed,
02406             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
02407    */
02408 }
02409
02410 /**
02411   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
02412   * @param husart USART handle.
02413   * @retval None
02414   */
02415 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
02416 {
02417   /* Prevent unused argument(s) compilation warning */
02418   UNUSED(husart);
02419
02420   /* NOTE : This function should not be modified, when the callback is needed,
02421             the HAL_USART_TxRxCpltCallback can be implemented in the user file
02422    */
02423 }
02424
02425 /**
02426   * @brief USART error callback.
02427   * @param husart USART handle.
02428   * @retval None
02429   */
02430 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
02431 {
02432   /* Prevent unused argument(s) compilation warning */
02433   UNUSED(husart);
02434
02435   /* NOTE : This function should not be modified, when the callback is needed,
02436             the HAL_USART_ErrorCallback can be implemented in the user file.
02437    */
02438 }
02439
02440 /**
02441   * @brief  USART Abort Complete callback.
02442   * @param  husart USART handle.
02443   * @retval None
02444   */
02445 __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
02446 {
02447   /* Prevent unused argument(s) compilation warning */
02448   UNUSED(husart);
02449
02450   /* NOTE : This function should not be modified, when the callback is needed,
02451             the HAL_USART_AbortCpltCallback can be implemented in the user file.
02452    */
02453 }
02454
02455 /**
02456   * @}
02457   */
02458
02459 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
02460   *  @brief   USART Peripheral State and Error functions
02461   *
02462 @verbatim
02463   ==============================================================================
02464             ##### Peripheral State and Error functions #####
02465   ==============================================================================
02466     [..]
02467     This subsection provides functions allowing to :
02468       (+) Return the USART handle state
02469       (+) Return the USART handle error code
02470
02471 @endverbatim
02472   * @{
02473   */
02474
02475
02476 /**
02477   * @brief Return the USART handle state.
02478   * @param husart pointer to a USART_HandleTypeDef structure that contains
02479   *              the configuration information for the specified USART.
02480   * @retval USART handle state
02481   */
02482 HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
02483 {
02484   return husart->State;
02485 }
02486
02487 /**
02488   * @brief Return the USART error code.
02489   * @param husart pointer to a USART_HandleTypeDef structure that contains
02490   *              the configuration information for the specified USART.
02491   * @retval USART handle Error Code
02492   */
02493 uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
02494 {
02495   return husart->ErrorCode;
02496 }
02497
02498 /**
02499   * @}
02500   */
02501
02502 /**
02503   * @}
02504   */
02505
02506 /** @defgroup USART_Private_Functions USART Private Functions
02507   * @{
02508   */
02509
02510 /**
02511   * @brief  Initialize the callbacks to their default values.
02512   * @param  husart USART handle.
02513   * @retval none
02514   */
02515 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02516 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
02517 {
02518   /* Init the USART Callback settings */
02519   husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02520   husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02521   husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02522   husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02523   husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
02524   husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02525   husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02526   husart->RxFifoFullCallback        = HAL_USARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02527   husart->TxFifoEmptyCallback       = HAL_USARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02528 }
02529 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02530
02531 /**
02532   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
02533   * @param  husart USART handle.
02534   * @retval None
02535   */
02536 static void USART_EndTransfer(USART_HandleTypeDef *husart)
02537 {
02538   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02539   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
02540                                     USART_CR1_TCIE));
02541   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02542
02543   /* At end of process, restore husart->State to Ready */
02544   husart->State = HAL_USART_STATE_READY;
02545 }
02546
02547 /**
02548   * @brief DMA USART transmit process complete callback.
02549   * @param  hdma DMA handle.
02550   * @retval None
02551   */
02552 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02553 {
02554   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02555
02556   /* DMA Normal mode */
02557   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02558   {
02559     husart->TxXferCount = 0U;
02560
02561     if (husart->State == HAL_USART_STATE_BUSY_TX)
02562     {
02563       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02564          in the USART CR3 register */
02565       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02566
02567       /* Enable the USART Transmit Complete Interrupt */
02568       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02569     }
02570   }
02571   /* DMA Circular mode */
02572   else
02573   {
02574     if (husart->State == HAL_USART_STATE_BUSY_TX)
02575     {
02576 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02577       /* Call registered Tx Complete Callback */
02578       husart->TxCpltCallback(husart);
02579 #else
02580       /* Call legacy weak Tx Complete Callback */
02581       HAL_USART_TxCpltCallback(husart);
02582 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02583     }
02584   }
02585 }
02586
02587 /**
02588   * @brief DMA USART transmit process half complete callback.
02589   * @param  hdma DMA handle.
02590   * @retval None
02591   */
02592 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02593 {
02594   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02595
02596 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02597   /* Call registered Tx Half Complete Callback */
02598   husart->TxHalfCpltCallback(husart);
02599 #else
02600   /* Call legacy weak Tx Half Complete Callback */
02601   HAL_USART_TxHalfCpltCallback(husart);
02602 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02603 }
02604
02605 /**
02606   * @brief DMA USART receive process complete callback.
02607   * @param  hdma DMA handle.
02608   * @retval None
02609   */
02610 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02611 {
02612   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02613
02614   /* DMA Normal mode */
02615   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02616   {
02617     husart->RxXferCount = 0U;
02618
02619     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02620     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02621     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02622
02623     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
02624        in USART CR3 register */
02625     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02626     /* similarly, disable the DMA TX transfer that was started to provide the
02627        clock to the slave device */
02628     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02629
02630     if (husart->State == HAL_USART_STATE_BUSY_RX)
02631     {
02632 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02633       /* Call registered Rx Complete Callback */
02634       husart->RxCpltCallback(husart);
02635 #else
02636       /* Call legacy weak Rx Complete Callback */
02637       HAL_USART_RxCpltCallback(husart);
02638 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02639     }
02640     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02641     else
02642     {
02643 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02644       /* Call registered Tx Rx Complete Callback */
02645       husart->TxRxCpltCallback(husart);
02646 #else
02647       /* Call legacy weak Tx Rx Complete Callback */
02648       HAL_USART_TxRxCpltCallback(husart);
02649 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02650     }
02651     husart->State = HAL_USART_STATE_READY;
02652   }
02653   /* DMA circular mode */
02654   else
02655   {
02656     if (husart->State == HAL_USART_STATE_BUSY_RX)
02657     {
02658 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02659       /* Call registered Rx Complete Callback */
02660       husart->RxCpltCallback(husart);
02661 #else
02662       /* Call legacy weak Rx Complete Callback */
02663       HAL_USART_RxCpltCallback(husart);
02664 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02665     }
02666     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02667     else
02668     {
02669 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02670       /* Call registered Tx Rx Complete Callback */
02671       husart->TxRxCpltCallback(husart);
02672 #else
02673       /* Call legacy weak Tx Rx Complete Callback */
02674       HAL_USART_TxRxCpltCallback(husart);
02675 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02676     }
02677   }
02678 }
02679
02680 /**
02681   * @brief DMA USART receive process half complete callback.
02682   * @param  hdma DMA handle.
02683   * @retval None
02684   */
02685 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02686 {
02687   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02688
02689 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02690   /* Call registered Rx Half Complete Callback */
02691   husart->RxHalfCpltCallback(husart);
02692 #else
02693   /* Call legacy weak Rx Half Complete Callback */
02694   HAL_USART_RxHalfCpltCallback(husart);
02695 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02696 }
02697
02698 /**
02699   * @brief DMA USART communication error callback.
02700   * @param  hdma DMA handle.
02701   * @retval None
02702   */
02703 static void USART_DMAError(DMA_HandleTypeDef *hdma)
02704 {
02705   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02706
02707   husart->RxXferCount = 0U;
02708   husart->TxXferCount = 0U;
02709   USART_EndTransfer(husart);
02710
02711   husart->ErrorCode |= HAL_USART_ERROR_DMA;
02712   husart->State = HAL_USART_STATE_READY;
02713
02714 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02715   /* Call registered Error Callback */
02716   husart->ErrorCallback(husart);
02717 #else
02718   /* Call legacy weak Error Callback */
02719   HAL_USART_ErrorCallback(husart);
02720 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02721 }
02722
02723 /**
02724   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
02725   *         (To be called at end of DMA Abort procedure following error occurrence).
02726   * @param  hdma DMA handle.
02727   * @retval None
02728   */
02729 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02730 {
02731   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02732   husart->RxXferCount = 0U;
02733   husart->TxXferCount = 0U;
02734
02735 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02736   /* Call registered Error Callback */
02737   husart->ErrorCallback(husart);
02738 #else
02739   /* Call legacy weak Error Callback */
02740   HAL_USART_ErrorCallback(husart);
02741 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02742 }
02743
02744 /**
02745   * @brief  DMA USART Tx communication abort callback, when initiated by user
02746   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02747   * @note   When this callback is executed, User Abort complete call back is called only if no
02748   *         Abort still ongoing for Rx DMA Handle.
02749   * @param  hdma DMA handle.
02750   * @retval None
02751   */
02752 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02753 {
02754   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02755
02756   husart->hdmatx->XferAbortCallback = NULL;
02757
02758   /* Check if an Abort process is still ongoing */
02759   if (husart->hdmarx != NULL)
02760   {
02761     if (husart->hdmarx->XferAbortCallback != NULL)
02762     {
02763       return;
02764     }
02765   }
02766
02767   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02768   husart->TxXferCount = 0U;
02769   husart->RxXferCount = 0U;
02770
02771   /* Reset errorCode */
02772   husart->ErrorCode = HAL_USART_ERROR_NONE;
02773
02774   /* Clear the Error flags in the ICR register */
02775   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02776
02777   /* Restore husart->State to Ready */
02778   husart->State = HAL_USART_STATE_READY;
02779
02780   /* Call user Abort complete callback */
02781 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02782   /* Call registered Abort Complete Callback */
02783   husart->AbortCpltCallback(husart);
02784 #else
02785   /* Call legacy weak Abort Complete Callback */
02786   HAL_USART_AbortCpltCallback(husart);
02787 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02788
02789 }
02790
02791
02792 /**
02793   * @brief  DMA USART Rx communication abort callback, when initiated by user
02794   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02795   * @note   When this callback is executed, User Abort complete call back is called only if no
02796   *         Abort still ongoing for Tx DMA Handle.
02797   * @param  hdma DMA handle.
02798   * @retval None
02799   */
02800 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02801 {
02802   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02803
02804   husart->hdmarx->XferAbortCallback = NULL;
02805
02806   /* Check if an Abort process is still ongoing */
02807   if (husart->hdmatx != NULL)
02808   {
02809     if (husart->hdmatx->XferAbortCallback != NULL)
02810     {
02811       return;
02812     }
02813   }
02814
02815   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02816   husart->TxXferCount = 0U;
02817   husart->RxXferCount = 0U;
02818
02819   /* Reset errorCode */
02820   husart->ErrorCode = HAL_USART_ERROR_NONE;
02821
02822   /* Clear the Error flags in the ICR register */
02823   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02824
02825   /* Restore husart->State to Ready */
02826   husart->State  = HAL_USART_STATE_READY;
02827
02828   /* Call user Abort complete callback */
02829 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02830   /* Call registered Abort Complete Callback */
02831   husart->AbortCpltCallback(husart);
02832 #else
02833   /* Call legacy weak Abort Complete Callback */
02834   HAL_USART_AbortCpltCallback(husart);
02835 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02836 }
02837
02838
02839 /**
02840   * @brief  Handle USART Communication Timeout. It waits
02841   *         until a flag is no longer in the specified status.
02842   * @param  husart USART handle.
02843   * @param  Flag Specifies the USART flag to check.
02844   * @param  Status the actual Flag status (SET or RESET).
02845   * @param  Tickstart Tick start value
02846   * @param  Timeout timeout duration.
02847   * @retval HAL status
02848   */
02849 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
02850                                                       uint32_t Tickstart, uint32_t Timeout)
02851 {
02852   /* Wait until flag is set */
02853   while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
02854   {
02855     /* Check for the Timeout */
02856     if (Timeout != HAL_MAX_DELAY)
02857     {
02858       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02859       {
02860         husart->State = HAL_USART_STATE_READY;
02861
02862         /* Process Unlocked */
02863         __HAL_UNLOCK(husart);
02864
02865         return HAL_TIMEOUT;
02866       }
02867     }
02868   }
02869   return HAL_OK;
02870 }
02871
02872 /**
02873   * @brief Configure the USART peripheral.
02874   * @param husart USART handle.
02875   * @retval HAL status
02876   */
02877 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
02878 {
02879   uint32_t tmpreg;
02880   USART_ClockSourceTypeDef clocksource;
02881   HAL_StatusTypeDef ret                = HAL_OK;
02882   uint16_t brrtemp;
02883   uint32_t usartdiv                    = 0x00000000;
02884   uint32_t pclk;
02885
02886   /* Check the parameters */
02887   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02888   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02889   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02890   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02891   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02892   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02893   assert_param(IS_USART_PARITY(husart->Init.Parity));
02894   assert_param(IS_USART_MODE(husart->Init.Mode));
02895   assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
02896
02897   /*-------------------------- USART CR1 Configuration -----------------------*/
02898   /* Clear M, PCE, PS, TE and RE bits and configure
02899   *  the USART Word Length, Parity and Mode:
02900   *  set the M bits according to husart->Init.WordLength value
02901   *  set PCE and PS bits according to husart->Init.Parity value
02902   *  set TE and RE bits according to husart->Init.Mode value
02903   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
02904   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
02905   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02906
02907   /*---------------------------- USART CR2 Configuration ---------------------*/
02908   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
02909    * set CPOL bit according to husart->Init.CLKPolarity value
02910    * set CPHA bit according to husart->Init.CLKPhase value
02911    * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
02912    * set STOP[13:12] bits according to husart->Init.StopBits value */
02913   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
02914   tmpreg |= (uint32_t)husart->Init.CLKLastBit;
02915   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
02916   tmpreg |= (uint32_t)husart->Init.StopBits;
02917   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02918
02919   /*-------------------------- USART PRESC Configuration -----------------------*/
02920   /* Configure
02921    * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
02922   MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
02923
02924   /*-------------------------- USART BRR Configuration -----------------------*/
02925   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
02926   USART_GETCLOCKSOURCE(husart, clocksource);
02927
02928   switch (clocksource)
02929   {
02930     case USART_CLOCKSOURCE_PCLK1:
02931       pclk = HAL_RCC_GetPCLK1Freq();
02932       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02933       break;
02934     case USART_CLOCKSOURCE_PCLK2:
02935       pclk = HAL_RCC_GetPCLK2Freq();
02936       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02937       break;
02938     case USART_CLOCKSOURCE_HSI:
02939       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02940       break;
02941     case USART_CLOCKSOURCE_SYSCLK:
02942       pclk = HAL_RCC_GetSysClockFreq();
02943       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02944       break;
02945     case USART_CLOCKSOURCE_LSE:
02946       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02947       break;
02948     default:
02949       ret = HAL_ERROR;
02950       break;
02951   }
02952
02953   /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
02954   if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
02955   {
02956     brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
02957     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02958     husart->Instance->BRR = brrtemp;
02959   }
02960   else
02961   {
02962     ret = HAL_ERROR;
02963   }
02964
02965   /* Initialize the number of data to process during RX/TX ISR execution */
02966   husart->NbTxDataToProcess = 1U;
02967   husart->NbRxDataToProcess = 1U;
02968
02969   /* Clear ISR function pointers */
02970   husart->RxISR   = NULL;
02971   husart->TxISR   = NULL;
02972
02973   return ret;
02974 }
02975
02976 /**
02977   * @brief Check the USART Idle State.
02978   * @param husart USART handle.
02979   * @retval HAL status
02980   */
02981 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
02982 {
02983   uint32_t tickstart;
02984
02985   /* Initialize the USART ErrorCode */
02986   husart->ErrorCode = HAL_USART_ERROR_NONE;
02987
02988   /* Init tickstart for timeout management */
02989   tickstart = HAL_GetTick();
02990
02991   /* Check if the Transmitter is enabled */
02992   if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02993   {
02994     /* Wait until TEACK flag is set */
02995     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02996     {
02997       /* Timeout occurred */
02998       return HAL_TIMEOUT;
02999     }
03000   }
03001   /* Check if the Receiver is enabled */
03002   if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03003   {
03004     /* Wait until REACK flag is set */
03005     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
03006     {
03007       /* Timeout occurred */
03008       return HAL_TIMEOUT;
03009     }
03010   }
03011
03012   /* Initialize the USART state*/
03013   husart->State = HAL_USART_STATE_READY;
03014
03015   /* Process Unlocked */
03016   __HAL_UNLOCK(husart);
03017
03018   return HAL_OK;
03019 }
03020
03021 /**
03022   * @brief  Simplex send an amount of data in non-blocking mode.
03023   * @note   Function called under interruption only, once
03024   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03025   * @note   The USART errors are not managed to avoid the overrun error.
03026   * @note   ISR function executed when FIFO mode is disabled and when the
03027   *         data word length is less than 9 bits long.
03028   * @param  husart USART handle.
03029   * @retval None
03030   */
03031 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
03032 {
03033   const HAL_USART_StateTypeDef state = husart->State;
03034
03035   /* Check that a Tx process is ongoing */
03036   if ((state == HAL_USART_STATE_BUSY_TX) ||
03037       (state == HAL_USART_STATE_BUSY_TX_RX))
03038   {
03039     if (husart->TxXferCount == 0U)
03040     {
03041       /* Disable the USART Transmit data register empty interrupt */
03042       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03043
03044       /* Enable the USART Transmit Complete Interrupt */
03045       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03046     }
03047     else
03048     {
03049       husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03050       husart->pTxBuffPtr++;
03051       husart->TxXferCount--;
03052     }
03053   }
03054 }
03055
03056 /**
03057   * @brief  Simplex send an amount of data in non-blocking mode.
03058   * @note   Function called under interruption only, once
03059   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03060   * @note   The USART errors are not managed to avoid the overrun error.
03061   * @note   ISR function executed when FIFO mode is disabled and when the
03062   *         data word length is 9 bits long.
03063   * @param  husart USART handle.
03064   * @retval None
03065   */
03066 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
03067 {
03068   const HAL_USART_StateTypeDef state = husart->State;
03069   const uint16_t *tmp;
03070
03071   if ((state == HAL_USART_STATE_BUSY_TX) ||
03072       (state == HAL_USART_STATE_BUSY_TX_RX))
03073   {
03074     if (husart->TxXferCount == 0U)
03075     {
03076       /* Disable the USART Transmit data register empty interrupt */
03077       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03078
03079       /* Enable the USART Transmit Complete Interrupt */
03080       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03081     }
03082     else
03083     {
03084       tmp = (const uint16_t *) husart->pTxBuffPtr;
03085       husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03086       husart->pTxBuffPtr += 2U;
03087       husart->TxXferCount--;
03088     }
03089   }
03090 }
03091
03092 /**
03093   * @brief  Simplex send an amount of data in non-blocking mode.
03094   * @note   Function called under interruption only, once
03095   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03096   * @note   The USART errors are not managed to avoid the overrun error.
03097   * @note   ISR function executed when FIFO mode is enabled and when the
03098   *         data word length is less than 9 bits long.
03099   * @param  husart USART handle.
03100   * @retval None
03101   */
03102 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03103 {
03104   const HAL_USART_StateTypeDef state = husart->State;
03105   uint16_t  nb_tx_data;
03106
03107   /* Check that a Tx process is ongoing */
03108   if ((state == HAL_USART_STATE_BUSY_TX) ||
03109       (state == HAL_USART_STATE_BUSY_TX_RX))
03110   {
03111     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03112     {
03113       if (husart->TxXferCount == 0U)
03114       {
03115         /* Disable the TX FIFO threshold interrupt */
03116         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03117
03118         /* Enable the USART Transmit Complete Interrupt */
03119         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03120
03121         break; /* force exit loop */
03122       }
03123       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03124       {
03125         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03126         husart->pTxBuffPtr++;
03127         husart->TxXferCount--;
03128       }
03129       else
03130       {
03131         /* Nothing to do */
03132       }
03133     }
03134   }
03135 }
03136
03137 /**
03138   * @brief  Simplex send an amount of data in non-blocking mode.
03139   * @note   Function called under interruption only, once
03140   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03141   * @note   The USART errors are not managed to avoid the overrun error.
03142   * @note   ISR function executed when FIFO mode is enabled and when the
03143   *         data word length is 9 bits long.
03144   * @param  husart USART handle.
03145   * @retval None
03146   */
03147 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03148 {
03149   const HAL_USART_StateTypeDef state = husart->State;
03150   const uint16_t *tmp;
03151   uint16_t  nb_tx_data;
03152
03153   /* Check that a Tx process is ongoing */
03154   if ((state == HAL_USART_STATE_BUSY_TX) ||
03155       (state == HAL_USART_STATE_BUSY_TX_RX))
03156   {
03157     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03158     {
03159       if (husart->TxXferCount == 0U)
03160       {
03161         /* Disable the TX FIFO threshold interrupt */
03162         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03163
03164         /* Enable the USART Transmit Complete Interrupt */
03165         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03166
03167         break; /* force exit loop */
03168       }
03169       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03170       {
03171         tmp = (const uint16_t *) husart->pTxBuffPtr;
03172         husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03173         husart->pTxBuffPtr += 2U;
03174         husart->TxXferCount--;
03175       }
03176       else
03177       {
03178         /* Nothing to do */
03179       }
03180     }
03181   }
03182 }
03183
03184 /**
03185   * @brief  Wraps up transmission in non-blocking mode.
03186   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
03187   *                the configuration information for the specified USART module.
03188   * @retval None
03189   */
03190 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
03191 {
03192   /* Disable the USART Transmit Complete Interrupt */
03193   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
03194
03195   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03196   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
03197
03198   /* Clear TxISR function pointer */
03199   husart->TxISR = NULL;
03200
03201   if (husart->State == HAL_USART_STATE_BUSY_TX)
03202   {
03203     /* Clear overrun flag and discard the received data */
03204     __HAL_USART_CLEAR_OREFLAG(husart);
03205     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03206
03207     /* Tx process is completed, restore husart->State to Ready */
03208     husart->State = HAL_USART_STATE_READY;
03209
03210 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03211     /* Call registered Tx Complete Callback */
03212     husart->TxCpltCallback(husart);
03213 #else
03214     /* Call legacy weak Tx Complete Callback */
03215     HAL_USART_TxCpltCallback(husart);
03216 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03217   }
03218   else if (husart->RxXferCount == 0U)
03219   {
03220     /* TxRx process is completed, restore husart->State to Ready */
03221     husart->State = HAL_USART_STATE_READY;
03222
03223 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03224     /* Call registered Tx Rx Complete Callback */
03225     husart->TxRxCpltCallback(husart);
03226 #else
03227     /* Call legacy weak Tx Rx Complete Callback */
03228     HAL_USART_TxRxCpltCallback(husart);
03229 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03230   }
03231   else
03232   {
03233     /* Nothing to do */
03234   }
03235 }
03236
03237
03238 /**
03239   * @brief  Simplex receive an amount of data in non-blocking mode.
03240   * @note   Function called under interruption only, once
03241   *         interruptions have been enabled by HAL_USART_Receive_IT().
03242   * @note   ISR function executed when FIFO mode is disabled and when the
03243   *         data word length is less than 9 bits long.
03244   * @param  husart USART handle
03245   * @retval None
03246   */
03247 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
03248 {
03249   const HAL_USART_StateTypeDef state = husart->State;
03250   uint16_t txdatacount;
03251   uint16_t uhMask = husart->Mask;
03252   uint32_t txftie;
03253
03254   if ((state == HAL_USART_STATE_BUSY_RX) ||
03255       (state == HAL_USART_STATE_BUSY_TX_RX))
03256   {
03257     *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
03258     husart->pRxBuffPtr++;
03259     husart->RxXferCount--;
03260
03261     if (husart->RxXferCount == 0U)
03262     {
03263       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03264       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03265
03266       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03267       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03268
03269       /* Clear RxISR function pointer */
03270       husart->RxISR = NULL;
03271
03272       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03273       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03274       txdatacount = husart->TxXferCount;
03275
03276       if (state == HAL_USART_STATE_BUSY_RX)
03277       {
03278         /* Clear SPI slave underrun flag and discard transmit data */
03279         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03280         {
03281           __HAL_USART_CLEAR_UDRFLAG(husart);
03282           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03283         }
03284
03285         /* Rx process is completed, restore husart->State to Ready */
03286         husart->State = HAL_USART_STATE_READY;
03287
03288 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03289         /* Call registered Rx Complete Callback */
03290         husart->RxCpltCallback(husart);
03291 #else
03292         /* Call legacy weak Rx Complete Callback */
03293         HAL_USART_RxCpltCallback(husart);
03294 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03295       }
03296       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03297                (txftie != USART_CR3_TXFTIE) &&
03298                (txdatacount == 0U))
03299       {
03300         /* TxRx process is completed, restore husart->State to Ready */
03301         husart->State = HAL_USART_STATE_READY;
03302
03303 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03304         /* Call registered Tx Rx Complete Callback */
03305         husart->TxRxCpltCallback(husart);
03306 #else
03307         /* Call legacy weak Tx Rx Complete Callback */
03308         HAL_USART_TxRxCpltCallback(husart);
03309 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03310       }
03311       else
03312       {
03313         /* Nothing to do */
03314       }
03315     }
03316     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03317              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03318     {
03319       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03320       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03321     }
03322     else
03323     {
03324       /* Nothing to do */
03325     }
03326   }
03327 }
03328
03329 /**
03330   * @brief  Simplex receive an amount of data in non-blocking mode.
03331   * @note   Function called under interruption only, once
03332   *         interruptions have been enabled by HAL_USART_Receive_IT().
03333   * @note   ISR function executed when FIFO mode is disabled and when the
03334   *         data word length is 9 bits long.
03335   * @param  husart USART handle
03336   * @retval None
03337   */
03338 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
03339 {
03340   const HAL_USART_StateTypeDef state = husart->State;
03341   uint16_t txdatacount;
03342   uint16_t *tmp;
03343   uint16_t uhMask = husart->Mask;
03344   uint32_t txftie;
03345
03346   if ((state == HAL_USART_STATE_BUSY_RX) ||
03347       (state == HAL_USART_STATE_BUSY_TX_RX))
03348   {
03349     tmp = (uint16_t *) husart->pRxBuffPtr;
03350     *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03351     husart->pRxBuffPtr += 2U;
03352     husart->RxXferCount--;
03353
03354     if (husart->RxXferCount == 0U)
03355     {
03356       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03357       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03358
03359       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03360       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03361
03362       /* Clear RxISR function pointer */
03363       husart->RxISR = NULL;
03364
03365       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03366       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03367       txdatacount = husart->TxXferCount;
03368
03369       if (state == HAL_USART_STATE_BUSY_RX)
03370       {
03371         /* Clear SPI slave underrun flag and discard transmit data */
03372         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03373         {
03374           __HAL_USART_CLEAR_UDRFLAG(husart);
03375           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03376         }
03377
03378         /* Rx process is completed, restore husart->State to Ready */
03379         husart->State = HAL_USART_STATE_READY;
03380
03381 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03382         /* Call registered Rx Complete Callback */
03383         husart->RxCpltCallback(husart);
03384 #else
03385         /* Call legacy weak Rx Complete Callback */
03386         HAL_USART_RxCpltCallback(husart);
03387 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03388       }
03389       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03390                (txftie != USART_CR3_TXFTIE) &&
03391                (txdatacount == 0U))
03392       {
03393         /* TxRx process is completed, restore husart->State to Ready */
03394         husart->State = HAL_USART_STATE_READY;
03395
03396 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03397         /* Call registered Tx Rx Complete Callback */
03398         husart->TxRxCpltCallback(husart);
03399 #else
03400         /* Call legacy weak Tx Rx Complete Callback */
03401         HAL_USART_TxRxCpltCallback(husart);
03402 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03403       }
03404       else
03405       {
03406         /* Nothing to do */
03407       }
03408     }
03409     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03410              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03411     {
03412       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03413       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03414     }
03415     else
03416     {
03417       /* Nothing to do */
03418     }
03419   }
03420 }
03421
03422 /**
03423   * @brief  Simplex receive an amount of data in non-blocking mode.
03424   * @note   Function called under interruption only, once
03425   *         interruptions have been enabled by HAL_USART_Receive_IT().
03426   * @note   ISR function executed when FIFO mode is enabled and when the
03427   *         data word length is less than 9 bits long.
03428   * @param  husart USART handle
03429   * @retval None
03430   */
03431 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03432 {
03433   HAL_USART_StateTypeDef state = husart->State;
03434   uint16_t txdatacount;
03435   uint16_t rxdatacount;
03436   uint16_t uhMask = husart->Mask;
03437   uint16_t nb_rx_data;
03438   uint32_t txftie;
03439
03440   /* Check that a Rx process is ongoing */
03441   if ((state == HAL_USART_STATE_BUSY_RX) ||
03442       (state == HAL_USART_STATE_BUSY_TX_RX))
03443   {
03444     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03445     {
03446       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03447       {
03448         *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
03449         husart->pRxBuffPtr++;
03450         husart->RxXferCount--;
03451
03452         if (husart->RxXferCount == 0U)
03453         {
03454           /* Disable the USART Parity Error Interrupt */
03455           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03456
03457           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
03458              and RX FIFO Threshold interrupt */
03459           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03460
03461           /* Clear RxISR function pointer */
03462           husart->RxISR = NULL;
03463
03464           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03465           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03466           txdatacount = husart->TxXferCount;
03467
03468           if (state == HAL_USART_STATE_BUSY_RX)
03469           {
03470             /* Clear SPI slave underrun flag and discard transmit data */
03471             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03472             {
03473               __HAL_USART_CLEAR_UDRFLAG(husart);
03474               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03475             }
03476
03477             /* Rx process is completed, restore husart->State to Ready */
03478             husart->State = HAL_USART_STATE_READY;
03479             state = HAL_USART_STATE_READY;
03480
03481 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03482             /* Call registered Rx Complete Callback */
03483             husart->RxCpltCallback(husart);
03484 #else
03485             /* Call legacy weak Rx Complete Callback */
03486             HAL_USART_RxCpltCallback(husart);
03487 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03488           }
03489           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03490                    (txftie != USART_CR3_TXFTIE) &&
03491                    (txdatacount == 0U))
03492           {
03493             /* TxRx process is completed, restore husart->State to Ready */
03494             husart->State = HAL_USART_STATE_READY;
03495             state = HAL_USART_STATE_READY;
03496
03497 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03498             /* Call registered Tx Rx Complete Callback */
03499             husart->TxRxCpltCallback(husart);
03500 #else
03501             /* Call legacy weak Tx Rx Complete Callback */
03502             HAL_USART_TxRxCpltCallback(husart);
03503 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03504           }
03505           else
03506           {
03507             /* Nothing to do */
03508           }
03509         }
03510         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03511                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03512         {
03513           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03514           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03515         }
03516         else
03517         {
03518           /* Nothing to do */
03519         }
03520       }
03521     }
03522
03523     /* When remaining number of bytes to receive is less than the RX FIFO
03524     threshold, next incoming frames are processed as if FIFO mode was
03525     disabled (i.e. one interrupt per received frame).
03526     */
03527     rxdatacount = husart->RxXferCount;
03528     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03529     {
03530       /* Disable the USART RXFT interrupt*/
03531       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03532
03533       /* Update the RxISR function pointer */
03534       husart->RxISR = USART_RxISR_8BIT;
03535
03536       /* Enable the USART Data Register Not Empty interrupt */
03537       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03538
03539       if ((husart->TxXferCount == 0U) &&
03540           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03541           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03542       {
03543         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03544         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03545       }
03546     }
03547   }
03548   else
03549   {
03550     /* Clear RXNE interrupt flag */
03551     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03552   }
03553 }
03554
03555 /**
03556   * @brief  Simplex receive an amount of data in non-blocking mode.
03557   * @note   Function called under interruption only, once
03558   *         interruptions have been enabled by HAL_USART_Receive_IT().
03559   * @note   ISR function executed when FIFO mode is enabled and when the
03560   *         data word length is 9 bits long.
03561   * @param  husart USART handle
03562   * @retval None
03563   */
03564 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03565 {
03566   HAL_USART_StateTypeDef state = husart->State;
03567   uint16_t txdatacount;
03568   uint16_t rxdatacount;
03569   uint16_t *tmp;
03570   uint16_t uhMask = husart->Mask;
03571   uint16_t nb_rx_data;
03572   uint32_t txftie;
03573
03574   /* Check that a Tx process is ongoing */
03575   if ((state == HAL_USART_STATE_BUSY_RX) ||
03576       (state == HAL_USART_STATE_BUSY_TX_RX))
03577   {
03578     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03579     {
03580       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03581       {
03582         tmp = (uint16_t *) husart->pRxBuffPtr;
03583         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03584         husart->pRxBuffPtr += 2U;
03585         husart->RxXferCount--;
03586
03587         if (husart->RxXferCount == 0U)
03588         {
03589           /* Disable the USART Parity Error Interrupt */
03590           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03591
03592           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
03593              and RX FIFO Threshold interrupt */
03594           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03595
03596           /* Clear RxISR function pointer */
03597           husart->RxISR = NULL;
03598
03599           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03600           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03601           txdatacount = husart->TxXferCount;
03602
03603           if (state == HAL_USART_STATE_BUSY_RX)
03604           {
03605             /* Clear SPI slave underrun flag and discard transmit data */
03606             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03607             {
03608               __HAL_USART_CLEAR_UDRFLAG(husart);
03609               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03610             }
03611
03612             /* Rx process is completed, restore husart->State to Ready */
03613             husart->State = HAL_USART_STATE_READY;
03614             state = HAL_USART_STATE_READY;
03615
03616 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03617             /* Call registered Rx Complete Callback */
03618             husart->RxCpltCallback(husart);
03619 #else
03620             /* Call legacy weak Rx Complete Callback */
03621             HAL_USART_RxCpltCallback(husart);
03622 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03623           }
03624           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03625                    (txftie != USART_CR3_TXFTIE) &&
03626                    (txdatacount == 0U))
03627           {
03628             /* TxRx process is completed, restore husart->State to Ready */
03629             husart->State = HAL_USART_STATE_READY;
03630             state = HAL_USART_STATE_READY;
03631
03632 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03633             /* Call registered Tx Rx Complete Callback */
03634             husart->TxRxCpltCallback(husart);
03635 #else
03636             /* Call legacy weak Tx Rx Complete Callback */
03637             HAL_USART_TxRxCpltCallback(husart);
03638 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03639           }
03640           else
03641           {
03642             /* Nothing to do */
03643           }
03644         }
03645         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03646                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03647         {
03648           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03649           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03650         }
03651         else
03652         {
03653           /* Nothing to do */
03654         }
03655       }
03656     }
03657
03658     /* When remaining number of bytes to receive is less than the RX FIFO
03659     threshold, next incoming frames are processed as if FIFO mode was
03660     disabled (i.e. one interrupt per received frame).
03661     */
03662     rxdatacount = husart->RxXferCount;
03663     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03664     {
03665       /* Disable the USART RXFT interrupt*/
03666       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03667
03668       /* Update the RxISR function pointer */
03669       husart->RxISR = USART_RxISR_16BIT;
03670
03671       /* Enable the USART Data Register Not Empty interrupt */
03672       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03673
03674       if ((husart->TxXferCount == 0U) &&
03675           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03676           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03677       {
03678         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03679         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03680       }
03681     }
03682   }
03683   else
03684   {
03685     /* Clear RXNE interrupt flag */
03686     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03687   }
03688 }
03689
03690 /**
03691   * @}
03692   */
03693
03694 #endif /* HAL_USART_MODULE_ENABLED */
03695 /**
03696   * @}
03697   */
03698
03699 /**
03700   * @}
03701   */
03702
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_usart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_USART_H
00021 #define STM32G4xx_HAL_USART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup USART
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup USART_Exported_Types USART Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief USART Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00049                                            The baud rate is computed using the following formula:
00050                                               Baud Rate Register[15:4] = ((2 * fclk_pres) /
00051                                               ((huart->Init.BaudRate)))[15:4]
00052                                               Baud Rate Register[3]    = 0
00053                                               Baud Rate Register[2:0]  =  (((2 * fclk_pres) /
00054                                               ((huart->Init.BaudRate)))[3:0]) >> 1
00055                                               where fclk_pres is the USART input clock frequency (fclk)
00056                                               divided by a prescaler.
00057                                            @note  Oversampling by 8 is systematically applied to
00058                                                   achieve high baud rates. */
00059
00060   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00061                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00062
00063   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00064                                            This parameter can be a value of @ref USART_Stop_Bits. */
00065
00066   uint32_t Parity;                   /*!< Specifies the parity mode.
00067                                            This parameter can be a value of @ref USART_Parity
00068                                            @note When parity is enabled, the computed parity is inserted
00069                                                  at the MSB position of the transmitted data (9th bit when
00070                                                  the word length is set to 9 data bits; 8th bit when the
00071                                                  word length is set to 8 data bits). */
00072
00073   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00074                                            This parameter can be a value of @ref USART_Mode. */
00075
00076   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00077                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00078
00079   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00080                                            This parameter can be a value of @ref USART_Clock_Phase. */
00081
00082   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00083                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00084                                            This parameter can be a value of @ref USART_Last_Bit. */
00085
00086   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00087                                            This parameter can be a value of @ref USART_ClockPrescaler. */
00088 } USART_InitTypeDef;
00089
00090 /**
00091   * @brief HAL USART State structures definition
00092   */
00093 typedef enum
00094 {
00095   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00096   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00097   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00098   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00099   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00100   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00101   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00102   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00103 } HAL_USART_StateTypeDef;
00104
00105 /**
00106   * @brief  USART clock sources definitions
00107   */
00108 typedef enum
00109 {
00110   USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
00111   USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
00112   USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00113   USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00114   USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00115   USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00116 } USART_ClockSourceTypeDef;
00117
00118 /**
00119   * @brief  USART handle Structure definition
00120   */
00121 typedef struct __USART_HandleTypeDef
00122 {
00123   USART_TypeDef                 *Instance;               /*!< USART registers base address        */
00124
00125   USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
00126
00127   const uint8_t                 *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
00128
00129   uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
00130
00131   __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
00132
00133   uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
00134
00135   uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
00136
00137   __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
00138
00139   uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
00140
00141   uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */
00142
00143   uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
00144
00145   uint32_t                      SlaveMode;               /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
00146                                                               of @ref USARTEx_Slave_Mode */
00147
00148   uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00149                                                               of @ref USARTEx_FIFO_mode. */
00150
00151   void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
00152
00153   void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
00154
00155   DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
00156
00157   DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
00158
00159   HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
00160
00161   __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
00162
00163   __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
00164
00165 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00166   void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
00167   void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
00168   void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
00169   void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
00170   void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
00171   void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
00172   void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
00173   void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */
00174   void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */
00175
00176   void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
00177   void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
00178 #endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
00179
00180 } USART_HandleTypeDef;
00181
00182 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00183 /**
00184   * @brief  HAL USART Callback ID enumeration definition
00185   */
00186 typedef enum
00187 {
00188   HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
00189   HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
00190   HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
00191   HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
00192   HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
00193   HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
00194   HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
00195   HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */
00196   HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */
00197
00198   HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
00199   HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
00200
00201 } HAL_USART_CallbackIDTypeDef;
00202
00203 /**
00204   * @brief  HAL USART Callback pointer definition
00205   */
00206 typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
00207
00208 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00209
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported constants --------------------------------------------------------*/
00215 /** @defgroup USART_Exported_Constants USART Exported Constants
00216   * @{
00217   */
00218
00219 /** @defgroup USART_Error_Definition   USART Error Definition
00220   * @{
00221   */
00222 #define HAL_USART_ERROR_NONE             (0x00000000U)    /*!< No error                  */
00223 #define HAL_USART_ERROR_PE               (0x00000001U)    /*!< Parity error              */
00224 #define HAL_USART_ERROR_NE               (0x00000002U)    /*!< Noise error               */
00225 #define HAL_USART_ERROR_FE               (0x00000004U)    /*!< Frame error               */
00226 #define HAL_USART_ERROR_ORE              (0x00000008U)    /*!< Overrun error             */
00227 #define HAL_USART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error        */
00228 #define HAL_USART_ERROR_UDR              (0x00000020U)    /*!< SPI slave underrun error  */
00229 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00230 #define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error    */
00231 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00232 #define  HAL_USART_ERROR_RTO              (0x00000080U)    /*!< Receiver Timeout error  */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00238   * @{
00239   */
00240 #define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
00241 #define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
00242 #define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
00243 #define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup USART_Parity    USART Parity
00249   * @{
00250   */
00251 #define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
00252 #define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
00253 #define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup USART_Mode   USART Mode
00259   * @{
00260   */
00261 #define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
00262 #define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
00263 #define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup USART_Clock  USART Clock
00269   * @{
00270   */
00271 #define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
00272 #define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00278   * @{
00279   */
00280 #define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
00281 #define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup USART_Clock_Phase   USART Clock Phase
00287   * @{
00288   */
00289 #define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
00290 #define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup USART_Last_Bit  USART Last Bit
00296   * @{
00297   */
00298 #define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
00299 #define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup USART_ClockPrescaler  USART Clock Prescaler
00305   * @{
00306   */
00307 #define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00308 #define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00309 #define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00310 #define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00311 #define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00312 #define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00313 #define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00314 #define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00315 #define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00316 #define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00317 #define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00318 #define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup USART_Request_Parameters  USART Request Parameters
00325   * @{
00326   */
00327 #define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00328 #define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup USART_Flags      USART Flags
00334   *        Elements values convention: 0xXXXX
00335   *           - 0xXXXX  : Flag mask in the ISR register
00336   * @{
00337   */
00338 #define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */
00339 #define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */
00340 #define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */
00341 #define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */
00342 #define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
00343 #define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
00344 #define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
00345 #define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */
00346 #define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */
00347 #define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */
00348 #define USART_FLAG_RTOF                     USART_ISR_RTOF          /*!< USART receiver timeout flag                */
00349 #define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
00350 #define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */
00351 #define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */
00352 #define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
00353 #define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
00354 #define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
00355 #define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
00356 #define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00362   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00363   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00364   *           - XX  : Interrupt source register (2bits)
00365   *                 - 01: CR1 register
00366   *                 - 10: CR2 register
00367   *                 - 11: CR3 register
00368   *           - ZZZZ  : Flag position in the ISR register(4bits)
00369   * @{
00370   */
00371
00372 #define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
00373 #define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
00374 #define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */
00375 #define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
00376 #define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
00377 #define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */
00378 #define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
00379 #define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
00380 #define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
00381 #define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
00382 #define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
00383 #define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */
00384 #define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */
00385 #define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */
00386 #define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00393   * @{
00394   */
00395 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
00396 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
00397 #define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */
00398 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
00399 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
00400 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
00401 #define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */
00402 #define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */
00403 #define USART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< USART receiver timeout clear flag  */
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00409   * @{
00410   */
00411 #define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
00412 #define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
00413 #define USART_CR_POS                              5U          /*!< USART control register position */
00414 #define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */
00415 #define USART_ISR_POS                             8U          /*!< USART ISR register position     */
00416 /**
00417   * @}
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 /* Exported macros -----------------------------------------------------------*/
00425 /** @defgroup USART_Exported_Macros USART Exported Macros
00426   * @{
00427   */
00428
00429 /** @brief Reset USART handle state.
00430   * @param  __HANDLE__ USART handle.
00431   * @retval None
00432   */
00433 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00434 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
00435                                                         (__HANDLE__)->State = HAL_USART_STATE_RESET; \
00436                                                         (__HANDLE__)->MspInitCallback = NULL;        \
00437                                                         (__HANDLE__)->MspDeInitCallback = NULL;      \
00438                                                       } while(0U)
00439 #else
00440 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00441 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00442
00443 /** @brief  Check whether the specified USART flag is set or not.
00444   * @param  __HANDLE__ specifies the USART Handle
00445   * @param  __FLAG__ specifies the flag to check.
00446   *        This parameter can be one of the following values:
00447   *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag
00448   *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag
00449   *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag
00450   *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag
00451   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00452   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00453   *            @arg @ref USART_FLAG_BUSY  Busy flag
00454   *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag
00455   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00456   *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
00457   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00458   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00459   *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
00460   *            @arg @ref USART_FLAG_RTOF  Receiver Timeout flag
00461   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00462   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00463   *            @arg @ref USART_FLAG_NE    Noise Error flag
00464   *            @arg @ref USART_FLAG_FE    Framing Error flag
00465   *            @arg @ref USART_FLAG_PE    Parity Error flag
00466   * @retval The new state of __FLAG__ (TRUE or FALSE).
00467   */
00468 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00469
00470 /** @brief  Clear the specified USART pending flag.
00471   * @param  __HANDLE__ specifies the USART Handle.
00472   * @param  __FLAG__ specifies the flag to check.
00473   *          This parameter can be any combination of the following values:
00474   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00475   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00476   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00477   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00478   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00479   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00480   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00481   *            @arg @ref USART_CLEAR_RTOF     Receiver Timeout clear flag
00482   *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag
00483   * @retval None
00484   */
00485 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00486
00487 /** @brief  Clear the USART PE pending flag.
00488   * @param  __HANDLE__ specifies the USART Handle.
00489   * @retval None
00490   */
00491 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00492
00493 /** @brief  Clear the USART FE pending flag.
00494   * @param  __HANDLE__ specifies the USART Handle.
00495   * @retval None
00496   */
00497 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00498
00499 /** @brief  Clear the USART NE pending flag.
00500   * @param  __HANDLE__ specifies the USART Handle.
00501   * @retval None
00502   */
00503 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00504
00505 /** @brief  Clear the USART ORE pending flag.
00506   * @param  __HANDLE__ specifies the USART Handle.
00507   * @retval None
00508   */
00509 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00510
00511 /** @brief  Clear the USART IDLE pending flag.
00512   * @param  __HANDLE__ specifies the USART Handle.
00513   * @retval None
00514   */
00515 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00516
00517 /** @brief  Clear the USART TX FIFO empty clear flag.
00518   * @param  __HANDLE__ specifies the USART Handle.
00519   * @retval None
00520   */
00521 #define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
00522
00523 /** @brief  Clear SPI slave underrun error flag.
00524   * @param  __HANDLE__ specifies the USART Handle.
00525   * @retval None
00526   */
00527 #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
00528
00529 /** @brief  Enable the specified USART interrupt.
00530   * @param  __HANDLE__ specifies the USART Handle.
00531   * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
00532   *          This parameter can be one of the following values:
00533   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00534   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00535   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00536   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00537   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00538   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00539   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00540   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00541   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00542   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00543   *            @arg @ref USART_IT_PE    Parity Error interrupt
00544   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00545   * @retval None
00546   */
00547 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
00548   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
00549    ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00550    ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
00551    ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00552    ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00553
00554 /** @brief  Disable the specified USART interrupt.
00555   * @param  __HANDLE__ specifies the USART Handle.
00556   * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
00557   *          This parameter can be one of the following values:
00558   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00559   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00560   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00561   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00562   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00563   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00564   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00565   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00566   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00567   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00568   *            @arg @ref USART_IT_PE    Parity Error interrupt
00569   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00570   * @retval None
00571   */
00572 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
00573   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
00574    ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00575    ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
00576    ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00577    ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00578
00579 /** @brief  Check whether the specified USART interrupt has occurred or not.
00580   * @param  __HANDLE__ specifies the USART Handle.
00581   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00582   *          This parameter can be one of the following values:
00583   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00584   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00585   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00586   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00587   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00588   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00589   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00590   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00591   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00592   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00593   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00594   *            @arg @ref USART_IT_NE    Noise Error interrupt
00595   *            @arg @ref USART_IT_FE    Framing Error interrupt
00596   *            @arg @ref USART_IT_PE    Parity Error interrupt
00597   * @retval The new state of __INTERRUPT__ (SET or RESET).
00598   */
00599 #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00600                                                          & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
00601                                                                       USART_ISR_POS))) != 0U) ? SET : RESET)
00602
00603 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00604   * @param  __HANDLE__ specifies the USART Handle.
00605   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00606   *          This parameter can be one of the following values:
00607   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00608   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00609   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00610   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00611   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00612   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00613   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00614   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00615   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00616   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00617   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00618   *            @arg @ref USART_IT_NE    Noise Error interrupt
00619   *            @arg @ref USART_IT_FE    Framing Error interrupt
00620   *            @arg @ref USART_IT_PE    Parity Error interrupt
00621   * @retval The new state of __INTERRUPT__ (SET or RESET).
00622   */
00623 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
00624                                                                  (__HANDLE__)->Instance->CR1 : \
00625                                                                  (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
00626                                                                   (__HANDLE__)->Instance->CR2 : \
00627                                                                   (__HANDLE__)->Instance->CR3)) & (0x01U <<\
00628                                                                       (((uint16_t)(__INTERRUPT__)) &\
00629                                                                        USART_IT_MASK)))  != 0U) ? SET : RESET)
00630
00631 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00632   * @param  __HANDLE__ specifies the USART Handle.
00633   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00634   *                       to clear the corresponding interrupt.
00635   *          This parameter can be one of the following values:
00636   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00637   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00638   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00639   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00640   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00641   *            @arg @ref USART_CLEAR_RTOF     Receiver timeout clear flag
00642   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00643   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00644   * @retval None
00645   */
00646 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00647
00648 /** @brief  Set a specific USART request flag.
00649   * @param  __HANDLE__ specifies the USART Handle.
00650   * @param  __REQ__ specifies the request flag to set.
00651   *          This parameter can be one of the following values:
00652   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00653   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00654   *
00655   * @retval None
00656   */
00657 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00658
00659 /** @brief  Enable the USART one bit sample method.
00660   * @param  __HANDLE__ specifies the USART Handle.
00661   * @retval None
00662   */
00663 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00664
00665 /** @brief  Disable the USART one bit sample method.
00666   * @param  __HANDLE__ specifies the USART Handle.
00667   * @retval None
00668   */
00669 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
00670
00671 /** @brief  Enable USART.
00672   * @param  __HANDLE__ specifies the USART Handle.
00673   * @retval None
00674   */
00675 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
00676
00677 /** @brief  Disable USART.
00678   * @param  __HANDLE__ specifies the USART Handle.
00679   * @retval None
00680   */
00681 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
00682
00683 /**
00684   * @}
00685   */
00686
00687 /* Private macros --------------------------------------------------------*/
00688 /** @defgroup USART_Private_Macros   USART Private Macros
00689   * @{
00690   */
00691
00692 /** @brief  Get USART clock division factor from clock prescaler value.
00693   * @param  __CLOCKPRESCALER__ USART prescaler value.
00694   * @retval USART clock division factor
00695   */
00696 #define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
00697   (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
00698    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
00699    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
00700    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
00701    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
00702    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
00703    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
00704    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
00705    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
00706    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
00707    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
00708    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
00709
00710 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
00711   * @param  __PCLK__ USART clock.
00712   * @param  __BAUD__ Baud rate set by the user.
00713   * @param  __CLOCKPRESCALER__ USART prescaler value.
00714   * @retval Division result
00715   */
00716 #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
00717   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
00718     + ((__BAUD__)/2U)) / (__BAUD__))
00719
00720 /** @brief  Report the USART clock source.
00721   * @param  __HANDLE__ specifies the USART Handle.
00722   * @param  __CLOCKSOURCE__ output variable.
00723   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00724   */
00725 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00726   do {                                                         \
00727     if((__HANDLE__)->Instance == USART1)                       \
00728     {                                                          \
00729       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00730       {                                                        \
00731         case RCC_USART1CLKSOURCE_PCLK2:                        \
00732           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00733           break;                                               \
00734         case RCC_USART1CLKSOURCE_HSI:                          \
00735           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00736           break;                                               \
00737         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00738           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00739           break;                                               \
00740         case RCC_USART1CLKSOURCE_LSE:                          \
00741           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00742           break;                                               \
00743         default:                                               \
00744           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00745           break;                                               \
00746       }                                                        \
00747     }                                                          \
00748     else if((__HANDLE__)->Instance == USART2)                  \
00749     {                                                          \
00750       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00751       {                                                        \
00752         case RCC_USART2CLKSOURCE_PCLK1:                        \
00753           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00754           break;                                               \
00755         case RCC_USART2CLKSOURCE_HSI:                          \
00756           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00757           break;                                               \
00758         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00759           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00760           break;                                               \
00761         case RCC_USART2CLKSOURCE_LSE:                          \
00762           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00763           break;                                               \
00764         default:                                               \
00765           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00766           break;                                               \
00767       }                                                        \
00768     }                                                          \
00769     else if((__HANDLE__)->Instance == USART3)                  \
00770     {                                                          \
00771       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00772       {                                                        \
00773         case RCC_USART3CLKSOURCE_PCLK1:                        \
00774           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00775           break;                                               \
00776         case RCC_USART3CLKSOURCE_HSI:                          \
00777           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00778           break;                                               \
00779         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00780           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00781           break;                                               \
00782         case RCC_USART3CLKSOURCE_LSE:                          \
00783           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00784           break;                                               \
00785         default:                                               \
00786           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00787           break;                                               \
00788       }                                                        \
00789     }                                                          \
00790     else                                                       \
00791     {                                                          \
00792       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00793     }                                                          \
00794   } while(0)
00795
00796 /** @brief  Check USART Baud rate.
00797   * @param  __BAUDRATE__ Baudrate specified by the user.
00798   *         The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz)
00799   *         divided by the smallest oversampling used on the USART (i.e. 8)
00800   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
00801 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
00802
00803 /**
00804   * @brief Ensure that USART frame number of stop bits is valid.
00805   * @param __STOPBITS__ USART frame number of stop bits.
00806   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00807   */
00808 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00809                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00810                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00811                                          ((__STOPBITS__) == USART_STOPBITS_2))
00812
00813 /**
00814   * @brief Ensure that USART frame parity is valid.
00815   * @param __PARITY__ USART frame parity.
00816   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00817   */
00818 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00819                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00820                                      ((__PARITY__) == USART_PARITY_ODD))
00821
00822 /**
00823   * @brief Ensure that USART communication mode is valid.
00824   * @param __MODE__ USART communication mode.
00825   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00826   */
00827 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00828
00829 /**
00830   * @brief Ensure that USART clock state is valid.
00831   * @param __CLOCK__ USART clock state.
00832   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00833   */
00834 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00835                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00836
00837 /**
00838   * @brief Ensure that USART frame polarity is valid.
00839   * @param __CPOL__ USART frame polarity.
00840   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00841   */
00842 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00843
00844 /**
00845   * @brief Ensure that USART frame phase is valid.
00846   * @param __CPHA__ USART frame phase.
00847   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00848   */
00849 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00850
00851 /**
00852   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00853   * @param __LASTBIT__ USART frame last bit clock pulse setting.
00854   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00855   */
00856 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00857                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00858
00859 /**
00860   * @brief Ensure that USART request parameter is valid.
00861   * @param __PARAM__ USART request parameter.
00862   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00863   */
00864 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00865                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00866
00867 /**
00868   * @brief Ensure that USART Prescaler is valid.
00869   * @param __CLOCKPRESCALER__ USART Prescaler value.
00870   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00871   */
00872 #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
00873                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
00874                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
00875                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
00876                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
00877                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
00878                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
00879                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
00880                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
00881                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
00882                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
00883                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
00884
00885 /**
00886   * @}
00887   */
00888
00889 /* Include USART HAL Extended module */
00890 #include "stm32g4xx_hal_usart_ex.h"
00891
00892 /* Exported functions --------------------------------------------------------*/
00893 /** @addtogroup USART_Exported_Functions USART Exported Functions
00894   * @{
00895   */
00896
00897 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00898   * @{
00899   */
00900
00901 /* Initialization and de-initialization functions  ****************************/
00902 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00903 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00904 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00905 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00906
00907 /* Callbacks Register/UnRegister functions  ***********************************/
00908 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00909 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
00910                                              pUSART_CallbackTypeDef pCallback);
00911 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
00912 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00913
00914 /**
00915   * @}
00916   */
00917
00918 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
00919   * @{
00920   */
00921
00922 /* IO operation functions *****************************************************/
00923 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
00924                                      uint32_t Timeout);
00925 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00926 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00927                                             uint16_t Size, uint32_t Timeout);
00928 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
00929 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00930 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00931                                                uint16_t Size);
00932 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
00933 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00934 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00935                                                 uint16_t Size);
00936 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00937 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00938 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00939 /* Transfer Abort functions */
00940 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
00941 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
00942
00943 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00944 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00945 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00946 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00947 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00948 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00949 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00950 void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
00951
00952 /**
00953   * @}
00954   */
00955
00956 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
00957   * @{
00958   */
00959
00960 /* Peripheral State and Error functions ***************************************/
00961 HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
00962 uint32_t               HAL_USART_GetError(const USART_HandleTypeDef *husart);
00963
00964 /**
00965   * @}
00966   */
00967
00968 /**
00969   * @}
00970   */
00971
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 #ifdef __cplusplus
00981 }
00982 #endif
00983
00984 #endif /* STM32G4xx_HAL_USART_H */
00985
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart_ex.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_usart_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_usart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended USART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
00008   *           + Peripheral Control functions
00009   *
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                ##### USART peripheral extended features  #####
00025   ==============================================================================
00026
00027     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00028
00029         -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
00030             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00031             configured prior starting RX/TX transfers.
00032
00033     (#) Slave mode enabling/disabling and NSS pin configuration.
00034
00035         -@- When USART operates in Slave mode, Slave mode must be enabled prior
00036             starting RX/TX transfers.
00037
00038   @endverbatim
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32g4xx_hal.h"
00044
00045 /** @addtogroup STM32G4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup USARTEx USARTEx
00050   * @brief USART Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_USART_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /** @defgroup USARTEx_Private_Constants USARTEx Private Constants
00058   * @{
00059   */
00060 /* USART RX FIFO depth */
00061 #define RX_FIFO_DEPTH 8U
00062
00063 /* USART TX FIFO depth */
00064 #define TX_FIFO_DEPTH 8U
00065 /**
00066   * @}
00067   */
00068
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /** @defgroup USARTEx_Private_Functions USARTEx Private Functions
00074   * @{
00075   */
00076 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported functions --------------------------------------------------------*/
00082
00083 /** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
00088   * @brief Extended USART Transmit/Receive functions
00089   *
00090 @verbatim
00091  ===============================================================================
00092                       ##### IO operation functions #####
00093  ===============================================================================
00094     This subsection provides a set of FIFO mode related callback functions.
00095
00096     (#) TX/RX Fifos Callbacks:
00097         (+) HAL_USARTEx_RxFifoFullCallback()
00098         (+) HAL_USARTEx_TxFifoEmptyCallback()
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  USART RX Fifo full callback.
00106   * @param  husart USART handle.
00107   * @retval None
00108   */
00109 __weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
00110 {
00111   /* Prevent unused argument(s) compilation warning */
00112   UNUSED(husart);
00113
00114   /* NOTE : This function should not be modified, when the callback is needed,
00115             the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
00116    */
00117 }
00118
00119 /**
00120   * @brief  USART TX Fifo empty callback.
00121   * @param  husart USART handle.
00122   * @retval None
00123   */
00124 __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
00125 {
00126   /* Prevent unused argument(s) compilation warning */
00127   UNUSED(husart);
00128
00129   /* NOTE : This function should not be modified, when the callback is needed,
00130             the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
00131    */
00132 }
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
00139   * @brief    Extended Peripheral Control functions
00140   *
00141 @verbatim
00142  ===============================================================================
00143                       ##### Peripheral Control functions #####
00144  ===============================================================================
00145     [..] This section provides the following functions:
00146      (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
00147      (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
00148      (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
00149      (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
00150      (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
00151      (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00152      (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00153
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Enable the SPI slave mode.
00161   * @note When the USART operates in SPI slave mode, it handles data flow using
00162   *       the serial interface clock derived from the external SCLK signal
00163   *       provided by the external master SPI device.
00164   * @note In SPI slave mode, the USART must be enabled before starting the master
00165   *       communications (or between frames while the clock is stable). Otherwise,
00166   *       if the USART slave is enabled while the master is in the middle of a
00167   *       frame, it will become desynchronized with the master.
00168   * @note The data register of the slave needs to be ready before the first edge
00169   *       of the communication clock or before the end of the ongoing communication,
00170   *       otherwise the SPI slave will transmit zeros.
00171   * @param husart      USART handle.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
00175 {
00176   uint32_t tmpcr1;
00177
00178   /* Check parameters */
00179   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00180
00181   /* Process Locked */
00182   __HAL_LOCK(husart);
00183
00184   husart->State = HAL_USART_STATE_BUSY;
00185
00186   /* Save actual USART configuration */
00187   tmpcr1 = READ_REG(husart->Instance->CR1);
00188
00189   /* Disable USART */
00190   __HAL_USART_DISABLE(husart);
00191
00192   /* In SPI slave mode mode, the following bits must be kept cleared:
00193   - LINEN and CLKEN bit in the USART_CR2 register
00194   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00195   CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00196   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00197
00198   /* Enable SPI slave mode */
00199   SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00200
00201   /* Restore USART configuration */
00202   WRITE_REG(husart->Instance->CR1, tmpcr1);
00203
00204   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00205
00206   husart->State = HAL_USART_STATE_READY;
00207
00208   /* Enable USART */
00209   __HAL_USART_ENABLE(husart);
00210
00211   /* Process Unlocked */
00212   __HAL_UNLOCK(husart);
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Disable the SPI slave mode.
00219   * @param husart      USART handle.
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
00223 {
00224   uint32_t tmpcr1;
00225
00226   /* Check parameters */
00227   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00228
00229   /* Process Locked */
00230   __HAL_LOCK(husart);
00231
00232   husart->State = HAL_USART_STATE_BUSY;
00233
00234   /* Save actual USART configuration */
00235   tmpcr1 = READ_REG(husart->Instance->CR1);
00236
00237   /* Disable USART */
00238   __HAL_USART_DISABLE(husart);
00239
00240   /* Disable SPI slave mode */
00241   CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00242
00243   /* Restore USART configuration */
00244   WRITE_REG(husart->Instance->CR1, tmpcr1);
00245
00246   husart->SlaveMode = USART_SLAVEMODE_DISABLE;
00247
00248   husart->State = HAL_USART_STATE_READY;
00249
00250   /* Process Unlocked */
00251   __HAL_UNLOCK(husart);
00252
00253   return HAL_OK;
00254 }
00255
00256 /**
00257   * @brief  Configure the Slave Select input pin (NSS).
00258   * @note Software NSS management: SPI slave will always be selected and NSS
00259   *       input pin will be ignored.
00260   * @note Hardware NSS management: the SPI slave selection depends on NSS
00261   *       input pin. The slave is selected when NSS is low and deselected when
00262   *       NSS is high.
00263   * @param husart      USART handle.
00264   * @param NSSConfig   NSS configuration.
00265   *          This parameter can be one of the following values:
00266   *            @arg @ref USART_NSS_HARD
00267   *            @arg @ref USART_NSS_SOFT
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
00271 {
00272   uint32_t tmpcr1;
00273
00274   /* Check parameters */
00275   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00276   assert_param(IS_USART_NSS(NSSConfig));
00277
00278   /* Process Locked */
00279   __HAL_LOCK(husart);
00280
00281   husart->State = HAL_USART_STATE_BUSY;
00282
00283   /* Save actual USART configuration */
00284   tmpcr1 = READ_REG(husart->Instance->CR1);
00285
00286   /* Disable USART */
00287   __HAL_USART_DISABLE(husart);
00288
00289   /* Program DIS_NSS bit in the USART_CR2 register */
00290   MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
00291
00292   /* Restore USART configuration */
00293   WRITE_REG(husart->Instance->CR1, tmpcr1);
00294
00295   husart->State = HAL_USART_STATE_READY;
00296
00297   /* Process Unlocked */
00298   __HAL_UNLOCK(husart);
00299
00300   return HAL_OK;
00301 }
00302
00303 /**
00304   * @brief  Enable the FIFO mode.
00305   * @param husart      USART handle.
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
00309 {
00310   uint32_t tmpcr1;
00311
00312   /* Check parameters */
00313   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00314
00315   /* Process Locked */
00316   __HAL_LOCK(husart);
00317
00318   husart->State = HAL_USART_STATE_BUSY;
00319
00320   /* Save actual USART configuration */
00321   tmpcr1 = READ_REG(husart->Instance->CR1);
00322
00323   /* Disable USART */
00324   __HAL_USART_DISABLE(husart);
00325
00326   /* Enable FIFO mode */
00327   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00328   husart->FifoMode = USART_FIFOMODE_ENABLE;
00329
00330   /* Restore USART configuration */
00331   WRITE_REG(husart->Instance->CR1, tmpcr1);
00332
00333   /* Determine the number of data to process during RX/TX ISR execution */
00334   USARTEx_SetNbDataToProcess(husart);
00335
00336   husart->State = HAL_USART_STATE_READY;
00337
00338   /* Process Unlocked */
00339   __HAL_UNLOCK(husart);
00340
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Disable the FIFO mode.
00346   * @param husart      USART handle.
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
00350 {
00351   uint32_t tmpcr1;
00352
00353   /* Check parameters */
00354   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00355
00356   /* Process Locked */
00357   __HAL_LOCK(husart);
00358
00359   husart->State = HAL_USART_STATE_BUSY;
00360
00361   /* Save actual USART configuration */
00362   tmpcr1 = READ_REG(husart->Instance->CR1);
00363
00364   /* Disable USART */
00365   __HAL_USART_DISABLE(husart);
00366
00367   /* Enable FIFO mode */
00368   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00369   husart->FifoMode = USART_FIFOMODE_DISABLE;
00370
00371   /* Restore USART configuration */
00372   WRITE_REG(husart->Instance->CR1, tmpcr1);
00373
00374   husart->State = HAL_USART_STATE_READY;
00375
00376   /* Process Unlocked */
00377   __HAL_UNLOCK(husart);
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  Set the TXFIFO threshold.
00384   * @param husart      USART handle.
00385   * @param Threshold  TX FIFO threshold value
00386   *          This parameter can be one of the following values:
00387   *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
00388   *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
00389   *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
00390   *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
00391   *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
00392   *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00396 {
00397   uint32_t tmpcr1;
00398
00399   /* Check parameters */
00400   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00401   assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
00402
00403   /* Process Locked */
00404   __HAL_LOCK(husart);
00405
00406   husart->State = HAL_USART_STATE_BUSY;
00407
00408   /* Save actual USART configuration */
00409   tmpcr1 = READ_REG(husart->Instance->CR1);
00410
00411   /* Disable USART */
00412   __HAL_USART_DISABLE(husart);
00413
00414   /* Update TX threshold configuration */
00415   MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00416
00417   /* Determine the number of data to process during RX/TX ISR execution */
00418   USARTEx_SetNbDataToProcess(husart);
00419
00420   /* Restore USART configuration */
00421   WRITE_REG(husart->Instance->CR1, tmpcr1);
00422
00423   husart->State = HAL_USART_STATE_READY;
00424
00425   /* Process Unlocked */
00426   __HAL_UNLOCK(husart);
00427
00428   return HAL_OK;
00429 }
00430
00431 /**
00432   * @brief  Set the RXFIFO threshold.
00433   * @param husart      USART handle.
00434   * @param Threshold  RX FIFO threshold value
00435   *          This parameter can be one of the following values:
00436   *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
00437   *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
00438   *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
00439   *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
00440   *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
00441   *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00445 {
00446   uint32_t tmpcr1;
00447
00448   /* Check the parameters */
00449   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00450   assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
00451
00452   /* Process Locked */
00453   __HAL_LOCK(husart);
00454
00455   husart->State = HAL_USART_STATE_BUSY;
00456
00457   /* Save actual USART configuration */
00458   tmpcr1 = READ_REG(husart->Instance->CR1);
00459
00460   /* Disable USART */
00461   __HAL_USART_DISABLE(husart);
00462
00463   /* Update RX threshold configuration */
00464   MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00465
00466   /* Determine the number of data to process during RX/TX ISR execution */
00467   USARTEx_SetNbDataToProcess(husart);
00468
00469   /* Restore USART configuration */
00470   WRITE_REG(husart->Instance->CR1, tmpcr1);
00471
00472   husart->State = HAL_USART_STATE_READY;
00473
00474   /* Process Unlocked */
00475   __HAL_UNLOCK(husart);
00476
00477   return HAL_OK;
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @addtogroup USARTEx_Private_Functions
00489   * @{
00490   */
00491
00492 /**
00493   * @brief Calculate the number of data to process in RX/TX ISR.
00494   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00495   *       the USART configuration registers.
00496   * @param husart USART handle.
00497   * @retval None
00498   */
00499 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
00500 {
00501   uint8_t rx_fifo_depth;
00502   uint8_t tx_fifo_depth;
00503   uint8_t rx_fifo_threshold;
00504   uint8_t tx_fifo_threshold;
00505   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00506   static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00507   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00508
00509   if (husart->FifoMode == USART_FIFOMODE_DISABLE)
00510   {
00511     husart->NbTxDataToProcess = 1U;
00512     husart->NbRxDataToProcess = 1U;
00513   }
00514   else
00515   {
00516     rx_fifo_depth = RX_FIFO_DEPTH;
00517     tx_fifo_depth = TX_FIFO_DEPTH;
00518     rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
00519                                             USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
00520     tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
00521                                             USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
00522     husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
00523                                 (uint16_t)denominator[tx_fifo_threshold];
00524     husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
00525                                 (uint16_t)denominator[rx_fifo_threshold];
00526   }
00527 }
00528 /**
00529   * @}
00530   */
00531
00532 #endif /* HAL_USART_MODULE_ENABLED */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_usart_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_usart_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_USART_EX_H
00021 #define STM32G4xx_HAL_USART_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup USARTEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00045   * @{
00046   */
00047 #define USART_WORDLENGTH_7B                  (USART_CR1_M1)   /*!< 7-bit long USART frame */
00048 #define USART_WORDLENGTH_8B                  (0x00000000U)    /*!< 8-bit long USART frame */
00049 #define USART_WORDLENGTH_9B                  (USART_CR1_M0)   /*!< 9-bit long USART frame */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
00055   * @{
00056   */
00057 #define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */
00058 #define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */
00059 /**
00060   * @}
00061   */
00062
00063
00064 /** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
00065   * @brief    USART SLAVE mode
00066   * @{
00067   */
00068 #define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */
00069 #define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode
00075   * @brief    USART FIFO  mode
00076   * @{
00077   */
00078 #define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00079 #define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
00085   * @brief    USART TXFIFO level
00086   * @{
00087   */
00088 #define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00089 #define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00090 #define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00091 #define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00092 #define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00093 #define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
00099   * @brief    USART RXFIFO level
00100   * @{
00101   */
00102 #define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00103 #define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00104 #define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00105 #define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00106 #define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00107 #define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Private macros ------------------------------------------------------------*/
00117 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00118   * @{
00119   */
00120
00121 /** @brief  Compute the USART mask to apply to retrieve the received data
00122   *         according to the word length and to the parity bits activation.
00123   * @note   If PCE = 1, the parity bit is not included in the data extracted
00124   *         by the reception API().
00125   *         This masking operation is not carried out in the case of
00126   *         DMA transfers.
00127   * @param  __HANDLE__ specifies the USART Handle.
00128   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00129   */
00130 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00131   do {                                                                \
00132     if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \
00133     {                                                                 \
00134       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00135       {                                                               \
00136         (__HANDLE__)->Mask = 0x01FFU;                                 \
00137       }                                                               \
00138       else                                                            \
00139       {                                                               \
00140         (__HANDLE__)->Mask = 0x00FFU;                                 \
00141       }                                                               \
00142     }                                                                 \
00143     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \
00144     {                                                                 \
00145       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00146       {                                                               \
00147         (__HANDLE__)->Mask = 0x00FFU;                                 \
00148       }                                                               \
00149       else                                                            \
00150       {                                                               \
00151         (__HANDLE__)->Mask = 0x007FU;                                 \
00152       }                                                               \
00153     }                                                                 \
00154     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \
00155     {                                                                 \
00156       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00157       {                                                               \
00158         (__HANDLE__)->Mask = 0x007FU;                                 \
00159       }                                                               \
00160       else                                                            \
00161       {                                                               \
00162         (__HANDLE__)->Mask = 0x003FU;                                 \
00163       }                                                               \
00164     }                                                                 \
00165     else                                                              \
00166     {                                                                 \
00167       (__HANDLE__)->Mask = 0x0000U;                                   \
00168     }                                                                 \
00169   } while(0U)
00170
00171 /**
00172   * @brief Ensure that USART frame length is valid.
00173   * @param __LENGTH__ USART frame length.
00174   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00175   */
00176 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00177                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00178                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00179
00180 /**
00181   * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
00182   * @param __NSS__ USART Negative Slave Select pin management.
00183   * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
00184   */
00185 #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
00186                                ((__NSS__) == USART_NSS_SOFT))
00187
00188 /**
00189   * @brief Ensure that USART Slave Mode is valid.
00190   * @param __STATE__ USART Slave Mode.
00191   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00192   */
00193 #define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
00194                                          ((__STATE__) == USART_SLAVEMODE_ENABLE))
00195
00196 /**
00197   * @brief Ensure that USART FIFO mode is valid.
00198   * @param __STATE__ USART FIFO mode.
00199   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00200   */
00201 #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
00202                                              ((__STATE__) == USART_FIFOMODE_ENABLE))
00203
00204 /**
00205   * @brief Ensure that USART TXFIFO threshold level is valid.
00206   * @param __THRESHOLD__ USART TXFIFO threshold level.
00207   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00208   */
00209 #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
00210                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
00211                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
00212                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
00213                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
00214                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
00215
00216 /**
00217   * @brief Ensure that USART RXFIFO threshold level is valid.
00218   * @param __THRESHOLD__ USART RXFIFO threshold level.
00219   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00220   */
00221 #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
00222                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
00223                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
00224                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
00225                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
00226                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported functions --------------------------------------------------------*/
00232 /** @addtogroup USARTEx_Exported_Functions
00233   * @{
00234   */
00235
00236 /** @addtogroup USARTEx_Exported_Functions_Group1
00237   * @{
00238   */
00239
00240 /* IO operation functions *****************************************************/
00241 void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
00242 void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @addtogroup USARTEx_Exported_Functions_Group2
00249   * @{
00250   */
00251
00252 /* Peripheral Control functions ***********************************************/
00253 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
00254 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
00255 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
00256 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
00257 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
00258 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00259 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00260
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 #ifdef __cplusplus
00278 }
00279 #endif
00280
00281 #endif /* STM32G4xx_HAL_USART_EX_H */
00282
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_wwdg.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_hal_wwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @brief   WWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Window Watchdog (WWDG) peripheral:
00008   *           + Initialization and Configuration functions
00009   *           + IO operation functions
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                       ##### WWDG Specific features #####
00024   ==============================================================================
00025   [..]
00026     Once enabled the WWDG generates a system reset on expiry of a programmed
00027     time period, unless the program refreshes the counter (T[6;0] downcounter)
00028     before reaching 0x3F value (i.e. a reset is generated when the counter
00029     value rolls down from 0x40 to 0x3F).
00030
00031     (+) An MCU reset is also generated if the counter value is refreshed
00032         before the counter has reached the refresh window value. This
00033         implies that the counter must be refreshed in a limited window.
00034     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00035     (+) If required by application, an Early Wakeup Interrupt can be triggered
00036         in order to be warned before WWDG expiration. The Early Wakeup Interrupt
00037         (EWI) can be used if specific safety operations or data logging must
00038         be performed before the actual reset is generated. When the downcounter
00039         reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
00040         line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
00041         disabled except by a system reset.
00042     (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
00043         reset occurs.
00044     (+) The WWDG counter input clock is derived from the APB clock divided
00045         by a programmable prescaler.
00046     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00047     (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
00048         where T[5;0] are the lowest 6 bits of Counter.
00049     (+) WWDG Counter refresh is allowed between the following limits :
00050         (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
00051         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
00052     (+) Typical values:
00053         (++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler:
00054              max timeout before reset: approximately 24.09us
00055         (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler
00056              dividing by 128:
00057              max timeout before reset: approximately 197.38ms
00058
00059                      ##### How to use this driver #####
00060   ==============================================================================
00061
00062     *** Common driver usage ***
00063     ===========================
00064
00065   [..]
00066     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00067     (+) Configure the WWDG prescaler, refresh window value, counter value and early
00068         interrupt status using HAL_WWDG_Init() function. This will automatically
00069         enable WWDG and start its downcounter. Time reference can be taken from
00070         function exit. Care must be taken to provide a counter value
00071         greater than 0x40 to prevent generation of immediate reset.
00072     (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
00073         generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
00074         triggered by the interrupt service routine, flag will be automatically
00075         cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
00076         can add his own code by customization of callback HAL_WWDG_WakeupCallback.
00077     (+) Then the application program must refresh the WWDG counter at regular
00078         intervals during normal operation to prevent an MCU reset, using
00079         HAL_WWDG_Refresh() function. This operation must occur only when
00080         the counter is lower than the refresh window value already programmed.
00081
00082     *** Callback registration ***
00083     =============================
00084
00085   [..]
00086     The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
00087     the user to configure dynamically the driver callbacks. Use Functions
00088     HAL_WWDG_RegisterCallback() to register a user callback.
00089
00090     (+) Function HAL_WWDG_RegisterCallback() allows to register following
00091         callbacks:
00092         (++) EwiCallback : callback for Early WakeUp Interrupt.
00093         (++) MspInitCallback : WWDG MspInit.
00094     This function takes as parameters the HAL peripheral handle, the Callback ID
00095     and a pointer to the user callback function.
00096
00097     (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
00098     the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
00099     takes as parameters the HAL peripheral handle and the Callback ID.
00100     This function allows to reset following callbacks:
00101         (++) EwiCallback : callback for  Early WakeUp Interrupt.
00102         (++) MspInitCallback : WWDG MspInit.
00103
00104     [..]
00105     When calling HAL_WWDG_Init function, callbacks are reset to the
00106     corresponding legacy weak (surcharged) functions:
00107     HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
00108     not been registered before.
00109
00110     [..]
00111     When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
00112     not defined, the callback registering feature is not available
00113     and weak (surcharged) callbacks are used.
00114
00115     *** WWDG HAL driver macros list ***
00116     ===================================
00117     [..]
00118       Below the list of available macros in WWDG HAL driver.
00119       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00120       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00121       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00122       (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
00123
00124   @endverbatim
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32g4xx_hal.h"
00129
00130 /** @addtogroup STM32G4xx_HAL_Driver
00131   * @{
00132   */
00133
00134 #ifdef HAL_WWDG_MODULE_ENABLED
00135 /** @defgroup WWDG WWDG
00136   * @brief WWDG HAL module driver.
00137   * @{
00138   */
00139
00140 /* Private typedef -----------------------------------------------------------*/
00141 /* Private define ------------------------------------------------------------*/
00142 /* Private macro -------------------------------------------------------------*/
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145 /* Exported functions --------------------------------------------------------*/
00146
00147 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00152   *  @brief    Initialization and Configuration functions.
00153   *
00154 @verbatim
00155   ==============================================================================
00156           ##### Initialization and Configuration functions #####
00157   ==============================================================================
00158   [..]
00159     This section provides functions allowing to:
00160       (+) Initialize and start the WWDG according to the specified parameters
00161           in the WWDG_InitTypeDef of associated handle.
00162       (+) Initialize the WWDG MSP.
00163
00164 @endverbatim
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Initialize the WWDG according to the specified.
00170   *         parameters in the WWDG_InitTypeDef of  associated handle.
00171   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00172   *                the configuration information for the specified WWDG module.
00173   * @retval HAL status
00174   */
00175 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00176 {
00177   /* Check the WWDG handle allocation */
00178   if (hwwdg == NULL)
00179   {
00180     return HAL_ERROR;
00181   }
00182
00183   /* Check the parameters */
00184   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00185   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00186   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00187   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00188   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00189
00190 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00191   /* Reset Callback pointers */
00192   if (hwwdg->EwiCallback == NULL)
00193   {
00194     hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00195   }
00196
00197   if (hwwdg->MspInitCallback == NULL)
00198   {
00199     hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00200   }
00201
00202   /* Init the low level hardware */
00203   hwwdg->MspInitCallback(hwwdg);
00204 #else
00205   /* Init the low level hardware */
00206   HAL_WWDG_MspInit(hwwdg);
00207 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00208
00209   /* Set WWDG Counter */
00210   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00211
00212   /* Set WWDG Prescaler and Window */
00213   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00214
00215   /* Return function status */
00216   return HAL_OK;
00217 }
00218
00219
00220 /**
00221   * @brief  Initialize the WWDG MSP.
00222   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00223   *                the configuration information for the specified WWDG module.
00224   * @note   When rewriting this function in user file, mechanism may be added
00225   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00226   *         again to change parameters.
00227   * @retval None
00228   */
00229 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00230 {
00231   /* Prevent unused argument(s) compilation warning */
00232   UNUSED(hwwdg);
00233
00234   /* NOTE: This function should not be modified, when the callback is needed,
00235            the HAL_WWDG_MspInit could be implemented in the user file
00236    */
00237 }
00238
00239
00240 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00241 /**
00242   * @brief  Register a User WWDG Callback
00243   *         To be used instead of the weak (surcharged) predefined callback
00244   * @param  hwwdg WWDG handle
00245   * @param  CallbackID ID of the callback to be registered
00246   *         This parameter can be one of the following values:
00247   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00248   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00249   * @param  pCallback pointer to the Callback function
00250   * @retval status
00251   */
00252 HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
00253                                             pWWDG_CallbackTypeDef pCallback)
00254 {
00255   HAL_StatusTypeDef status = HAL_OK;
00256
00257   if (pCallback == NULL)
00258   {
00259     status = HAL_ERROR;
00260   }
00261   else
00262   {
00263     switch (CallbackID)
00264     {
00265       case HAL_WWDG_EWI_CB_ID:
00266         hwwdg->EwiCallback = pCallback;
00267         break;
00268
00269       case HAL_WWDG_MSPINIT_CB_ID:
00270         hwwdg->MspInitCallback = pCallback;
00271         break;
00272
00273       default:
00274         status = HAL_ERROR;
00275         break;
00276     }
00277   }
00278
00279   return status;
00280 }
00281
00282
00283 /**
00284   * @brief  Unregister a WWDG Callback
00285   *         WWDG Callback is redirected to the weak (surcharged) predefined callback
00286   * @param  hwwdg WWDG handle
00287   * @param  CallbackID ID of the callback to be registered
00288   *         This parameter can be one of the following values:
00289   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00290   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00291   * @retval status
00292   */
00293 HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
00294 {
00295   HAL_StatusTypeDef status = HAL_OK;
00296
00297   switch (CallbackID)
00298   {
00299     case HAL_WWDG_EWI_CB_ID:
00300       hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00301       break;
00302
00303     case HAL_WWDG_MSPINIT_CB_ID:
00304       hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00305       break;
00306
00307     default:
00308       status = HAL_ERROR;
00309       break;
00310   }
00311
00312   return status;
00313 }
00314 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00321   *  @brief    IO operation functions
00322   *
00323 @verbatim
00324   ==============================================================================
00325                       ##### IO operation functions #####
00326   ==============================================================================
00327   [..]
00328     This section provides functions allowing to:
00329     (+) Refresh the WWDG.
00330     (+) Handle WWDG interrupt request and associated function callback.
00331
00332 @endverbatim
00333   * @{
00334   */
00335
00336 /**
00337   * @brief  Refresh the WWDG.
00338   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00339   *                the configuration information for the specified WWDG module.
00340   * @retval HAL status
00341   */
00342 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00343 {
00344   /* Write to WWDG CR the WWDG Counter value to refresh with */
00345   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00346
00347   /* Return function status */
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Handle WWDG interrupt request.
00353   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00354   *         or data logging must be performed before the actual reset is generated.
00355   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00356   *         EWIMode set to WWDG_EWI_ENABLE.
00357   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00358   *         generated and the corresponding Interrupt Service Routine (ISR) can
00359   *         be used to trigger specific actions (such as communications or data
00360   *         logging), before resetting the device.
00361   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00362   *                the configuration information for the specified WWDG module.
00363   * @retval None
00364   */
00365 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00366 {
00367   /* Check if Early Wakeup Interrupt is enable */
00368   if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00369   {
00370     /* Check if WWDG Early Wakeup Interrupt occurred */
00371     if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00372     {
00373       /* Clear the WWDG Early Wakeup flag */
00374       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00375
00376 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00377       /* Early Wakeup registered callback */
00378       hwwdg->EwiCallback(hwwdg);
00379 #else
00380       /* Early Wakeup callback */
00381       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00382 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00383     }
00384   }
00385 }
00386
00387
00388 /**
00389   * @brief  WWDG Early Wakeup callback.
00390   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00391   *                the configuration information for the specified WWDG module.
00392   * @retval None
00393   */
00394 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
00395 {
00396   /* Prevent unused argument(s) compilation warning */
00397   UNUSED(hwwdg);
00398
00399   /* NOTE: This function should not be modified, when the callback is needed,
00400            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00401    */
00402 }
00403
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 #endif /* HAL_WWDG_MODULE_ENABLED */
00413 /**
00414   * @}
00415   */
00416
00417 /**
00418   * @}
00419   */
00420
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_hal_wwdg.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_HAL_WWDG_H
00021 #define STM32G4xx_HAL_WWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx_hal_def.h"
00029
00030 /** @addtogroup STM32G4xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup WWDG
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039
00040 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  WWDG Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00050                                This parameter can be a value of @ref WWDG_Prescaler */
00051
00052   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00053                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00054
00055   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00056                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00057
00058   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
00059                                This parameter can be a value of @ref WWDG_EWI_Mode */
00060
00061 } WWDG_InitTypeDef;
00062
00063 /**
00064   * @brief  WWDG handle Structure definition
00065   */
00066 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00067 typedef struct __WWDG_HandleTypeDef
00068 #else
00069 typedef struct
00070 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00071 {
00072   WWDG_TypeDef      *Instance;  /*!< Register base address */
00073
00074   WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
00075
00076 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00077   void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);                  /*!< WWDG Early WakeUp Interrupt callback */
00078
00079   void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg);              /*!< WWDG Msp Init callback */
00080 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00081 } WWDG_HandleTypeDef;
00082
00083 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00084 /**
00085   * @brief  HAL WWDG common Callback ID enumeration definition
00086   */
00087 typedef enum
00088 {
00089   HAL_WWDG_EWI_CB_ID          = 0x00U,    /*!< WWDG EWI callback ID */
00090   HAL_WWDG_MSPINIT_CB_ID      = 0x01U,    /*!< WWDG MspInit callback ID */
00091 } HAL_WWDG_CallbackIDTypeDef;
00092
00093 /**
00094   * @brief  HAL WWDG Callback pointer definition
00095   */
00096 typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
00097
00098 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported constants --------------------------------------------------------*/
00104
00105 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00110   * @{
00111   */
00112 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00118   * @brief WWDG Flag definition
00119   * @{
00120   */
00121 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup WWDG_Prescaler WWDG Prescaler
00127   * @{
00128   */
00129 #define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
00130 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
00131 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
00132 #define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
00133 #define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */
00134 #define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */
00135 #define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */
00136 #define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00142   * @{
00143   */
00144 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00145 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Private macros ------------------------------------------------------------*/
00155
00156 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00157   * @{
00158   */
00159 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
00160                                              ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
00161                                              ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
00162                                              ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
00163                                              ((__PRESCALER__) == WWDG_PRESCALER_16) || \
00164                                              ((__PRESCALER__) == WWDG_PRESCALER_32) || \
00165                                              ((__PRESCALER__) == WWDG_PRESCALER_64) || \
00166                                              ((__PRESCALER__) == WWDG_PRESCALER_128))
00167
00168 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00169
00170 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00171
00172 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00173                                              ((__MODE__) == WWDG_EWI_DISABLE))
00174 /**
00175   * @}
00176   */
00177
00178
00179 /* Exported macros ------------------------------------------------------------*/
00180
00181 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00182   * @{
00183   */
00184
00185 /**
00186   * @brief  Enable the WWDG peripheral.
00187   * @param  __HANDLE__  WWDG handle
00188   * @retval None
00189   */
00190 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00191
00192 /**
00193   * @brief  Enable the WWDG early wakeup interrupt.
00194   * @param  __HANDLE__: WWDG handle
00195   * @param  __INTERRUPT__  specifies the interrupt to enable.
00196   *         This parameter can be one of the following values:
00197   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00198   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00199   * @retval None
00200   */
00201 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00202
00203 /**
00204   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00205   * @param  __HANDLE__  WWDG handle
00206   * @param  __INTERRUPT__  specifies the it to check.
00207   *        This parameter can be one of the following values:
00208   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00209   * @retval The new state of WWDG_FLAG (SET or RESET).
00210   */
00211 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00212
00213 /** @brief  Clear the WWDG interrupt pending bits.
00214   *         bits to clear the selected interrupt pending bits.
00215   * @param  __HANDLE__  WWDG handle
00216   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00217   *         This parameter can be one of the following values:
00218   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00219   */
00220 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00221
00222 /**
00223   * @brief  Check whether the specified WWDG flag is set or not.
00224   * @param  __HANDLE__  WWDG handle
00225   * @param  __FLAG__  specifies the flag to check.
00226   *         This parameter can be one of the following values:
00227   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00228   * @retval The new state of WWDG_FLAG (SET or RESET).
00229   */
00230 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00231
00232 /**
00233   * @brief  Clear the WWDG's pending flags.
00234   * @param  __HANDLE__  WWDG handle
00235   * @param  __FLAG__  specifies the flag to clear.
00236   *         This parameter can be one of the following values:
00237   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00238   * @retval None
00239   */
00240 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00241
00242 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00243   * @param  __HANDLE__  WWDG Handle.
00244   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00245   *         This parameter can be one of the following values:
00246   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00247   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00248   */
00249 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
00250                                                               & (__INTERRUPT__)) == (__INTERRUPT__))
00251
00252 /**
00253   * @}
00254   */
00255
00256 /* Exported functions --------------------------------------------------------*/
00257
00258 /** @addtogroup WWDG_Exported_Functions
00259   * @{
00260   */
00261
00262 /** @addtogroup WWDG_Exported_Functions_Group1
00263   * @{
00264   */
00265 /* Initialization/de-initialization functions  **********************************/
00266 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00267 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00268 /* Callbacks Register/UnRegister functions  ***********************************/
00269 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00270 HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
00271                                                 pWWDG_CallbackTypeDef pCallback);
00272 HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
00273 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup WWDG_Exported_Functions_Group2
00280   * @{
00281   */
00282 /* I/O operation functions ******************************************************/
00283 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00284 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00285 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 #ifdef __cplusplus
00303 }
00304 #endif
00305
00306 #endif /* STM32G4xx_HAL_WWDG_H */
00307
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_adc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_adc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @brief   ADC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_adc.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
00035
00036 /** @addtogroup ADC_LL ADC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup ADC_LL_Private_Constants
00044   * @{
00045   */
00046
00047 /* Definitions of ADC hardware constraints delays */
00048 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
00049 /*       not timeout values:                                                  */
00050 /*       Timeout values for ADC operations are dependent to device clock      */
00051 /*       configuration (system clock versus ADC clock),                       */
00052 /*       and therefore must be defined in user application.                   */
00053 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00054 /*       values definition.                                                   */
00055 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00056 /*       of device clock setting.                                             */
00057 /*       In user application, ADC timeout values should be defined with       */
00058 /*       temporal values, in function of device clock settings.               */
00059 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00060 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00061 /*          ADC prescaler 4.                                                  */
00062 /*           Ratio max = 512 *4 = 2048                                        */
00063 /*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
00064 /*          Highest CPU clock PLL (PLLR).                                     */
00065 /*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
00066 /*                     = 3968                                                 */
00067 /* Unit: CPU cycles.                                                          */
00068 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (3968UL)
00069 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00070 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00071
00072 /**
00073   * @}
00074   */
00075
00076 /* Private macros ------------------------------------------------------------*/
00077
00078 /** @addtogroup ADC_LL_Private_Macros
00079   * @{
00080   */
00081
00082 /* Check of parameters for configuration of ADC hierarchical scope:           */
00083 /* common to several ADC instances.                                           */
00084 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00085   (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                                \
00086    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00087    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
00088    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
00089    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
00090    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
00091    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
00092    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
00093    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
00094    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
00095    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
00096    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
00097    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
00098    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
00099    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
00100   )
00101
00102 /* Check of parameters for configuration of ADC hierarchical scope:           */
00103 /* ADC instance.                                                              */
00104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00105   (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
00106    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00107    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00108    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
00109   )
00110
00111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00112   (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
00113    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00114   )
00115
00116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00117   (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
00118    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00119   )
00120
00121 /* Check of parameters for configuration of ADC hierarchical scope:           */
00122 /* ADC group regular                                                          */
00123 #if defined(STM32G474xx) || defined(STM32G484xx)
00124 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00125   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00126    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00127    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00128    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00129    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00130    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00131    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00132    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00133    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
00134    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00135    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00136    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00137    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
00138    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
00139    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
00140    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
00141    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
00142    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)                \
00143    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)                \
00144    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)                \
00145    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)                \
00146    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)                \
00147    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)               \
00148    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
00149    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00150        && (                                                                    \
00151             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
00152          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
00153          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
00154          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
00155          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
00156          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
00157          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
00158          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
00159           )                                                                    \
00160       )                                                                        \
00161    || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
00162        && (                                                                    \
00163             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
00164          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
00165          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
00166          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
00167          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
00168          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
00169          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)          \
00170          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)          \
00171           )                                                                    \
00172       )                                                                        \
00173   )
00174 #elif defined(STM32G473xx) || defined(STM32G483xx)
00175 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00176   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00177    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00178    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00179    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00180    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00181    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00182    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00183    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00184    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00185    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
00186    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00187    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00188    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00189    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
00190    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
00191    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
00192    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
00193    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00194        && (                                                                    \
00195             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
00196          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
00197          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
00198          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
00199          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
00200          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
00201          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
00202          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
00203           )                                                                    \
00204       )                                                                        \
00205    || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
00206        && (                                                                    \
00207             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
00208          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
00209          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
00210          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
00211          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
00212          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
00213           )                                                                    \
00214       )                                                                        \
00215   )
00216 #elif defined(STM32G471xx)
00217 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00218   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00219    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00220    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00221    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00222    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00223    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00224    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00225    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00226    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00227    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
00228    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00229    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00230    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00231    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
00232    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00233        && (                                                                    \
00234             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
00235          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
00236          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
00237          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
00238          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
00239          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
00240           )                                                                    \
00241       )                                                                        \
00242    || (((__ADC_INSTANCE__) == ADC3) \
00243        && (                                                                    \
00244             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
00245          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
00246          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
00247          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
00248          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
00249          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
00250           )                                                                    \
00251       )                                                                        \
00252   )
00253 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
00254 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00255   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00256    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00257    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00258    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00259    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00260    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00261    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00262    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00263    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00264    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00265    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00266    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00267    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00268    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
00269    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00270    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00271    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00272    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
00273    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00274   )
00275 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00276 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00277   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00278    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00279    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00280    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00281    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00282    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00283    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00284    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00285    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
00286    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00287    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00288    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00289    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
00290    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
00291    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
00292    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
00293    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00294        && (                                                                    \
00295             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
00296          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
00297          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
00298          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
00299          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
00300          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
00301          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
00302          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
00303           )                                                                    \
00304       )                                                                        \
00305    || (((__ADC_INSTANCE__) == ADC3)                                            \
00306        && (                                                                    \
00307             ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
00308          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
00309          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
00310          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
00311          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
00312          || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
00313           )                                                                    \
00314       )                                                                        \
00315   )
00316 #endif /* STM32G4xx */
00317
00318 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00319   (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
00320    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00321   )
00322
00323 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00324   (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
00325    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
00326    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00327   )
00328
00329 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00330   (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
00331    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00332   )
00333
00334 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00335   (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
00336    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00337    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00338    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00339    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00340    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00341    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00342    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00343    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00344    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00345    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00346    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00347    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00348    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00349    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00350    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00351   )
00352
00353 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00354   (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
00355    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00356    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00357    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00358    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00359    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00360    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00361    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00362    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00363   )
00364
00365 /* Check of parameters for configuration of ADC hierarchical scope:           */
00366 /* ADC group injected                                                         */
00367 #if defined(STM32G474xx) || defined(STM32G484xx)
00368 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00369   (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
00370    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00371    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00372    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00373    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00374    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00375    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00376    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00377    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
00378    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00379    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00380    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00381    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00382    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
00383    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
00384    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
00385    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
00386    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)                \
00387    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)                \
00388    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)                \
00389    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)                \
00390    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)                \
00391    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)               \
00392    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
00393    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00394        && (                                                                    \
00395             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
00396          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
00397          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
00398          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
00399          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
00400          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
00401          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
00402           )                                                                    \
00403       )                                                                        \
00404    || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
00405        && (                                                                    \
00406             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
00407          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
00408          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
00409          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
00410          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
00411          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)          \
00412          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)          \
00413          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
00414           )                                                                    \
00415       )                                                                        \
00416   )
00417 #elif defined(STM32G473xx) || defined(STM32G483xx)
00418 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00419   (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
00420    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00421    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00422    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00423    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00424    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00425    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00426    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00427    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
00428    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00429    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00430    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00431    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00432    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
00433    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
00434    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
00435    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00436        && (                                                                    \
00437             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
00438          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
00439          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
00440          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
00441          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
00442          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
00443          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
00444           )                                                                    \
00445       )                                                                        \
00446    || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
00447        && (                                                                    \
00448             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
00449          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
00450          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
00451          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
00452          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
00453          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
00454           )                                                                    \
00455       )                                                                        \
00456   )
00457 #elif defined(STM32G471xx)
00458 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00459   (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
00460    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00461    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00462    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00463    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00464    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00465    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00466    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00467    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
00468    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00469    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00470    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00471    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00472    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
00473    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00474        && (                                                                    \
00475             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
00476          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
00477          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
00478          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
00479          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
00480          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
00481           )                                                                    \
00482       )                                                                        \
00483    || ((((__ADC_INSTANCE__) == ADC3)) \
00484        && (                                                                    \
00485             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
00486          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
00487          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
00488          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
00489          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
00490           )                                                                    \
00491       )                                                                        \
00492   )
00493 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
00494 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00495   (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
00496    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00497    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00498    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00499    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00500    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00501    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00502    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00503    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00504    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00505    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00506    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00507    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
00508    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00509    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00510    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00511    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00512    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)                 \
00513    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
00514    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00515   )
00516 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00517 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00518   (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
00519    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00520    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00521    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00522    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00523    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00524    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00525    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00526    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
00527    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00528    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00529    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00530    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00531    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
00532    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
00533    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
00534    || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
00535        && (                                                                    \
00536             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
00537          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
00538          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
00539          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
00540          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
00541          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
00542          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
00543           )                                                                    \
00544       )                                                                        \
00545    || ((((__ADC_INSTANCE__) == ADC3))                                          \
00546        && (                                                                    \
00547             ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
00548          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
00549          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
00550          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
00551          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
00552          || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
00553           )                                                                    \
00554       )                                                                        \
00555   )
00556 #endif /* STM32G4xx */
00557
00558 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
00559   (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
00560    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
00561    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
00562   )
00563
00564 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00565   (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
00566    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00567   )
00568
00569 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00570   (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
00571    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00572    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00573    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00574   )
00575
00576 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00577   (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
00578    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00579   )
00580
00581 #if defined(ADC_MULTIMODE_SUPPORT)
00582 /* Check of parameters for configuration of ADC hierarchical scope:           */
00583 /* multimode.                                                                 */
00584 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
00585   (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
00586    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
00587    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
00588    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
00589    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
00590    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
00591    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
00592    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
00593   )
00594
00595 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
00596   (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)                 \
00597    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
00598    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
00599    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
00600    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
00601   )
00602
00603 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
00604   (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)              \
00605    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
00606    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
00607    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
00608    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
00609    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
00610    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
00611    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
00612    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
00613    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
00614    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
00615    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
00616   )
00617
00618 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
00619   (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
00620    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
00621    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
00622   )
00623
00624 #endif /* ADC_MULTIMODE_SUPPORT */
00625 /**
00626   * @}
00627   */
00628
00629
00630 /* Private function prototypes -----------------------------------------------*/
00631
00632 /* Exported functions --------------------------------------------------------*/
00633 /** @addtogroup ADC_LL_Exported_Functions
00634   * @{
00635   */
00636
00637 /** @addtogroup ADC_LL_EF_Init
00638   * @{
00639   */
00640
00641 /**
00642   * @brief  De-initialize registers of all ADC instances belonging to
00643   *         the same ADC common instance to their default reset values.
00644   * @note   This function is performing a hard reset, using high level
00645   *         clock source RCC ADC reset.
00646   *         Caution: On this STM32 series, if several ADC instances are available
00647   *         on the selected device, RCC ADC reset will reset
00648   *         all ADC instances belonging to the common ADC instance.
00649   *         To de-initialize only 1 ADC instance, use
00650   *         function @ref LL_ADC_DeInit().
00651   * @param  ADCxy_COMMON ADC common instance
00652   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00653   * @retval An ErrorStatus enumeration value:
00654   *          - SUCCESS: ADC common registers are de-initialized
00655   *          - ERROR: not applicable
00656   */
00657 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
00658 {
00659   /* Check the parameters */
00660   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00661
00662   if (ADCxy_COMMON == ADC12_COMMON)
00663   {
00664     /* Force reset of ADC clock (core clock) */
00665     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
00666
00667     /* Release reset of ADC clock (core clock) */
00668     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
00669   }
00670 #if defined(ADC345_COMMON)
00671   else
00672   {
00673     /* Force reset of ADC clock (core clock) */
00674     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
00675
00676     /* Release reset of ADC clock (core clock) */
00677     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
00678   }
00679 #endif /* ADC345_COMMON */
00680
00681   return SUCCESS;
00682 }
00683
00684 /**
00685   * @brief  Initialize some features of ADC common parameters
00686   *         (all ADC instances belonging to the same ADC common instance)
00687   *         and multimode (for devices with several ADC instances available).
00688   * @note   The setting of ADC common parameters is conditioned to
00689   *         ADC instances state:
00690   *         All ADC instances belonging to the same ADC common instance
00691   *         must be disabled.
00692   * @param  ADCxy_COMMON ADC common instance
00693   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00694   * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00695   * @retval An ErrorStatus enumeration value:
00696   *          - SUCCESS: ADC common registers are initialized
00697   *          - ERROR: ADC common registers are not initialized
00698   */
00699 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
00700 {
00701   ErrorStatus status = SUCCESS;
00702
00703   /* Check the parameters */
00704   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00705   assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
00706
00707 #if defined(ADC_MULTIMODE_SUPPORT)
00708   assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
00709   if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00710   {
00711     assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
00712     assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
00713   }
00714 #endif /* ADC_MULTIMODE_SUPPORT */
00715
00716   /* Note: Hardware constraint (refer to description of functions             */
00717   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
00718   /*       On this STM32 series, setting of these features is conditioned to  */
00719   /*       ADC state:                                                         */
00720   /*       All ADC instances of the ADC common group must be disabled.        */
00721   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
00722   {
00723     /* Configuration of ADC hierarchical scope:                               */
00724     /*  - common to several ADC                                               */
00725     /*    (all ADC instances belonging to the same ADC common instance)       */
00726     /*    - Set ADC clock (conversion clock)                                  */
00727     /*  - multimode (if several ADC instances available on the                */
00728     /*    selected device)                                                    */
00729     /*    - Set ADC multimode configuration                                   */
00730     /*    - Set ADC multimode DMA transfer                                    */
00731     /*    - Set ADC multimode: delay between 2 sampling phases                */
00732 #if defined(ADC_MULTIMODE_SUPPORT)
00733     if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00734     {
00735       MODIFY_REG(ADCxy_COMMON->CCR,
00736                  ADC_CCR_CKMODE
00737                  | ADC_CCR_PRESC
00738                  | ADC_CCR_DUAL
00739                  | ADC_CCR_MDMA
00740                  | ADC_CCR_DELAY
00741                  ,
00742                  pADC_CommonInitStruct->CommonClock
00743                  | pADC_CommonInitStruct->Multimode
00744                  | pADC_CommonInitStruct->MultiDMATransfer
00745                  | pADC_CommonInitStruct->MultiTwoSamplingDelay
00746                 );
00747     }
00748     else
00749     {
00750       MODIFY_REG(ADCxy_COMMON->CCR,
00751                  ADC_CCR_CKMODE
00752                  | ADC_CCR_PRESC
00753                  | ADC_CCR_DUAL
00754                  | ADC_CCR_MDMA
00755                  | ADC_CCR_DELAY
00756                  ,
00757                  pADC_CommonInitStruct->CommonClock
00758                  | LL_ADC_MULTI_INDEPENDENT
00759                 );
00760     }
00761 #else
00762     LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
00763 #endif /* ADC_MULTIMODE_SUPPORT */
00764   }
00765   else
00766   {
00767     /* Initialization error: One or several ADC instances belonging to        */
00768     /* the same ADC common instance are not disabled.                         */
00769     status = ERROR;
00770   }
00771
00772   return status;
00773 }
00774
00775 /**
00776   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00777   * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00778   *                              whose fields will be set to default values.
00779   * @retval None
00780   */
00781 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
00782 {
00783   /* Set pADC_CommonInitStruct fields to default values */
00784   /* Set fields of ADC common */
00785   /* (all ADC instances belonging to the same ADC common instance) */
00786   pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00787
00788 #if defined(ADC_MULTIMODE_SUPPORT)
00789   /* Set fields of ADC multimode */
00790   pADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
00791   pADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
00792   pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
00793 #endif /* ADC_MULTIMODE_SUPPORT */
00794 }
00795
00796 /**
00797   * @brief  De-initialize registers of the selected ADC instance
00798   *         to their default reset values.
00799   * @note   To reset all ADC instances quickly (perform a hard reset),
00800   *         use function @ref LL_ADC_CommonDeInit().
00801   * @note   If this functions returns error status, it means that ADC instance
00802   *         is in an unknown state.
00803   *         In this case, perform a hard reset using high level
00804   *         clock source RCC ADC reset.
00805   *         Caution: On this STM32 series, if several ADC instances are available
00806   *         on the selected device, RCC ADC reset will reset
00807   *         all ADC instances belonging to the common ADC instance.
00808   *         Refer to function @ref LL_ADC_CommonDeInit().
00809   * @param  ADCx ADC instance
00810   * @retval An ErrorStatus enumeration value:
00811   *          - SUCCESS: ADC registers are de-initialized
00812   *          - ERROR: ADC registers are not de-initialized
00813   */
00814 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00815 {
00816   ErrorStatus status = SUCCESS;
00817
00818   __IO uint32_t timeout_cpu_cycles = 0UL;
00819
00820   /* Check the parameters */
00821   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00822
00823   /* Disable ADC instance if not already disabled.                            */
00824   if (LL_ADC_IsEnabled(ADCx) == 1UL)
00825   {
00826     /* Stop potential ADC conversion on going on ADC group regular.           */
00827     if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
00828     {
00829       if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
00830       {
00831         LL_ADC_REG_StopConversion(ADCx);
00832       }
00833     }
00834
00835     /* Stop potential ADC conversion on going on ADC group injected.          */
00836     if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
00837     {
00838       if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
00839       {
00840         LL_ADC_INJ_StopConversion(ADCx);
00841       }
00842     }
00843
00844     /* Wait for ADC conversions are effectively stopped                       */
00845     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00846     while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
00847             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
00848     {
00849       timeout_cpu_cycles--;
00850       if (timeout_cpu_cycles == 0UL)
00851       {
00852         /* Time-out error */
00853         status = ERROR;
00854         break;
00855       }
00856     }
00857
00858     /* Flush group injected contexts queue (register JSQR):                   */
00859     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
00860     /*       contexts queue is maintained with the last active context).      */
00861     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
00862
00863     /* Disable the ADC instance */
00864     LL_ADC_Disable(ADCx);
00865
00866     /* Wait for ADC instance is effectively disabled */
00867     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00868     while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
00869     {
00870       timeout_cpu_cycles--;
00871       if (timeout_cpu_cycles == 0UL)
00872       {
00873         /* Time-out error */
00874         status = ERROR;
00875         break;
00876       }
00877     }
00878   }
00879
00880   /* Check whether ADC state is compliant with expected state */
00881   if (READ_BIT(ADCx->CR,
00882                (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
00883                 | ADC_CR_ADDIS | ADC_CR_ADEN)
00884               )
00885       == 0UL)
00886   {
00887     /* ========== Reset ADC registers ========== */
00888     /* Reset register IER */
00889     CLEAR_BIT(ADCx->IER,
00890               (LL_ADC_IT_ADRDY
00891                | LL_ADC_IT_EOC
00892                | LL_ADC_IT_EOS
00893                | LL_ADC_IT_OVR
00894                | LL_ADC_IT_EOSMP
00895                | LL_ADC_IT_JEOC
00896                | LL_ADC_IT_JEOS
00897                | LL_ADC_IT_JQOVF
00898                | LL_ADC_IT_AWD1
00899                | LL_ADC_IT_AWD2
00900                | LL_ADC_IT_AWD3
00901               )
00902              );
00903
00904     /* Reset register ISR */
00905     SET_BIT(ADCx->ISR,
00906             (LL_ADC_FLAG_ADRDY
00907              | LL_ADC_FLAG_EOC
00908              | LL_ADC_FLAG_EOS
00909              | LL_ADC_FLAG_OVR
00910              | LL_ADC_FLAG_EOSMP
00911              | LL_ADC_FLAG_JEOC
00912              | LL_ADC_FLAG_JEOS
00913              | LL_ADC_FLAG_JQOVF
00914              | LL_ADC_FLAG_AWD1
00915              | LL_ADC_FLAG_AWD2
00916              | LL_ADC_FLAG_AWD3
00917             )
00918            );
00919
00920     /* Reset register CR */
00921     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
00922     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
00923     /*    access mode "read-set": no direct reset applicable.                 */
00924     /*  - Reset Calibration mode to default setting (single ended).           */
00925     /*  - Disable ADC internal voltage regulator.                             */
00926     /*  - Enable ADC deep power down.                                         */
00927     /*    Note: ADC internal voltage regulator disable and ADC deep power     */
00928     /*          down enable are conditioned to ADC state disabled:            */
00929     /*          already done above.                                           */
00930     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00931     SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
00932
00933     /* Reset register CFGR */
00934     MODIFY_REG(ADCx->CFGR,
00935                (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
00936                 | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
00937                 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
00938                 | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
00939                 | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
00940                 | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN),
00941                ADC_CFGR_JQDIS
00942               );
00943
00944     /* Reset register CFGR2 */
00945     CLEAR_BIT(ADCx->CFGR2,
00946               (ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
00947                | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
00948                | ADC_CFGR2_GCOMP
00949                | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
00950              );
00951
00952     /* Reset register SMPR1 */
00953     CLEAR_BIT(ADCx->SMPR1,
00954               (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
00955                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
00956                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
00957              );
00958
00959     /* Reset register SMPR2 */
00960     CLEAR_BIT(ADCx->SMPR2,
00961               (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
00962                | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
00963                | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
00964              );
00965
00966     /* Reset register TR1 */
00967     MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
00968
00969     /* Reset register TR2 */
00970     MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
00971
00972     /* Reset register TR3 */
00973     MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
00974
00975     /* Reset register SQR1 */
00976     CLEAR_BIT(ADCx->SQR1,
00977               (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
00978                | ADC_SQR1_SQ1 | ADC_SQR1_L)
00979              );
00980
00981     /* Reset register SQR2 */
00982     CLEAR_BIT(ADCx->SQR2,
00983               (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
00984                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
00985              );
00986
00987     /* Reset register SQR3 */
00988     CLEAR_BIT(ADCx->SQR3,
00989               (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
00990                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
00991              );
00992
00993     /* Reset register SQR4 */
00994     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00995
00996     /* Reset register JSQR */
00997     CLEAR_BIT(ADCx->JSQR,
00998               (ADC_JSQR_JL
00999                | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
01000                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
01001                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
01002              );
01003
01004     /* Reset register DR */
01005     /* Note: bits in access mode read only, no direct reset applicable */
01006
01007     /* Reset register OFR1 */
01008     CLEAR_BIT(ADCx->OFR1,
01009               ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
01010     /* Reset register OFR2 */
01011     CLEAR_BIT(ADCx->OFR2,
01012               ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
01013     /* Reset register OFR3 */
01014     CLEAR_BIT(ADCx->OFR3,
01015               ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
01016     /* Reset register OFR4 */
01017     CLEAR_BIT(ADCx->OFR4,
01018               ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
01019
01020     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
01021     /* Note: bits in access mode read only, no direct reset applicable */
01022
01023     /* Reset register AWD2CR */
01024     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
01025
01026     /* Reset register AWD3CR */
01027     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
01028
01029     /* Reset register DIFSEL */
01030     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
01031
01032     /* Reset register CALFACT */
01033     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
01034
01035     /* Reset register GCOMP */
01036     CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
01037   }
01038   else
01039   {
01040     /* ADC instance is in an unknown state */
01041     /* Need to performing a hard reset of ADC instance, using high level      */
01042     /* clock source RCC ADC reset.                                            */
01043     /* Caution: On this STM32 series, if several ADC instances are available  */
01044     /*          on the selected device, RCC ADC reset will reset              */
01045     /*          all ADC instances belonging to the common ADC instance.       */
01046     /* Caution: On this STM32 series, if several ADC instances are available  */
01047     /*          on the selected device, RCC ADC reset will reset              */
01048     /*          all ADC instances belonging to the common ADC instance.       */
01049     status = ERROR;
01050   }
01051
01052   return status;
01053 }
01054
01055 /**
01056   * @brief  Initialize some features of ADC instance.
01057   * @note   These parameters have an impact on ADC scope: ADC instance.
01058   *         Affects both group regular and group injected (availability
01059   *         of ADC group injected depends on STM32 series).
01060   *         Refer to corresponding unitary functions into
01061   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
01062   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01063   *         is conditioned to ADC state:
01064   *         ADC instance must be disabled.
01065   *         This condition is applied to all ADC features, for efficiency
01066   *         and compatibility over all STM32 series. However, the different
01067   *         features can be set under different ADC state conditions
01068   *         (setting possible with ADC enabled without conversion on going,
01069   *         ADC enabled with conversion on going, ...)
01070   *         Each feature can be updated afterwards with a unitary function
01071   *         and potentially with ADC in a different state than disabled,
01072   *         refer to description of each function for setting
01073   *         conditioned to ADC state.
01074   * @note   After using this function, some other features must be configured
01075   *         using LL unitary functions.
01076   *         The minimum configuration remaining to be done is:
01077   *          - Set ADC group regular or group injected sequencer:
01078   *            map channel on the selected sequencer rank.
01079   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01080   *          - Set ADC channel sampling time
01081   *            Refer to function LL_ADC_SetChannelSamplingTime();
01082   * @param  ADCx ADC instance
01083   * @param  pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01084   * @retval An ErrorStatus enumeration value:
01085   *          - SUCCESS: ADC registers are initialized
01086   *          - ERROR: ADC registers are not initialized
01087   */
01088 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
01089 {
01090   ErrorStatus status = SUCCESS;
01091
01092   /* Check the parameters */
01093   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01094
01095   assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
01096   assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
01097   assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
01098
01099   /* Note: Hardware constraint (refer to description of this function):       */
01100   /*       ADC instance must be disabled.                                     */
01101   if (LL_ADC_IsEnabled(ADCx) == 0UL)
01102   {
01103     /* Configuration of ADC hierarchical scope:                               */
01104     /*  - ADC instance                                                        */
01105     /*    - Set ADC data resolution                                           */
01106     /*    - Set ADC conversion data alignment                                 */
01107     /*    - Set ADC low power mode                                            */
01108     MODIFY_REG(ADCx->CFGR,
01109                ADC_CFGR_RES
01110                | ADC_CFGR_ALIGN
01111                | ADC_CFGR_AUTDLY
01112                ,
01113                pADC_InitStruct->Resolution
01114                | pADC_InitStruct->DataAlignment
01115                | pADC_InitStruct->LowPowerMode
01116               );
01117
01118   }
01119   else
01120   {
01121     /* Initialization error: ADC instance is not disabled. */
01122     status = ERROR;
01123   }
01124
01125   return status;
01126 }
01127
01128 /**
01129   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
01130   * @param  pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
01131   *                        whose fields will be set to default values.
01132   * @retval None
01133   */
01134 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
01135 {
01136   /* Set pADC_InitStruct fields to default values */
01137   /* Set fields of ADC instance */
01138   pADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
01139   pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
01140   pADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
01141
01142 }
01143
01144 /**
01145   * @brief  Initialize some features of ADC group regular.
01146   * @note   These parameters have an impact on ADC scope: ADC group regular.
01147   *         Refer to corresponding unitary functions into
01148   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01149   *         (functions with prefix "REG").
01150   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01151   *         is conditioned to ADC state:
01152   *         ADC instance must be disabled.
01153   *         This condition is applied to all ADC features, for efficiency
01154   *         and compatibility over all STM32 series. However, the different
01155   *         features can be set under different ADC state conditions
01156   *         (setting possible with ADC enabled without conversion on going,
01157   *         ADC enabled with conversion on going, ...)
01158   *         Each feature can be updated afterwards with a unitary function
01159   *         and potentially with ADC in a different state than disabled,
01160   *         refer to description of each function for setting
01161   *         conditioned to ADC state.
01162   * @note   After using this function, other features must be configured
01163   *         using LL unitary functions.
01164   *         The minimum configuration remaining to be done is:
01165   *          - Set ADC group regular or group injected sequencer:
01166   *            map channel on the selected sequencer rank.
01167   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
01168   *          - Set ADC channel sampling time
01169   *            Refer to function LL_ADC_SetChannelSamplingTime();
01170   * @param  ADCx ADC instance
01171   * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01172   * @retval An ErrorStatus enumeration value:
01173   *          - SUCCESS: ADC registers are initialized
01174   *          - ERROR: ADC registers are not initialized
01175   */
01176 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
01177 {
01178   ErrorStatus status = SUCCESS;
01179
01180   /* Check the parameters */
01181   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01182   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct->TriggerSource));
01183   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
01184   if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01185   {
01186     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
01187
01188     /* ADC group regular continuous mode and discontinuous mode                 */
01189     /* can not be enabled simultenaeously                                       */
01190     assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
01191                  || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
01192   }
01193   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
01194   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
01195   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
01196
01197   /* Note: Hardware constraint (refer to description of this function):       */
01198   /*       ADC instance must be disabled.                                     */
01199   if (LL_ADC_IsEnabled(ADCx) == 0UL)
01200   {
01201     /* Configuration of ADC hierarchical scope:                               */
01202     /*  - ADC group regular                                                   */
01203     /*    - Set ADC group regular trigger source                              */
01204     /*    - Set ADC group regular sequencer length                            */
01205     /*    - Set ADC group regular sequencer discontinuous mode                */
01206     /*    - Set ADC group regular continuous mode                             */
01207     /*    - Set ADC group regular conversion data transfer: no transfer or    */
01208     /*      transfer by DMA, and DMA requests mode                            */
01209     /*    - Set ADC group regular overrun behavior                            */
01210     /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
01211     /*       setting of trigger source to SW start.                           */
01212     if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01213     {
01214       MODIFY_REG(ADCx->CFGR,
01215                  ADC_CFGR_EXTSEL
01216                  | ADC_CFGR_EXTEN
01217                  | ADC_CFGR_DISCEN
01218                  | ADC_CFGR_DISCNUM
01219                  | ADC_CFGR_CONT
01220                  | ADC_CFGR_DMAEN
01221                  | ADC_CFGR_DMACFG
01222                  | ADC_CFGR_OVRMOD
01223                  ,
01224                  pADC_RegInitStruct->TriggerSource
01225                  | pADC_RegInitStruct->SequencerDiscont
01226                  | pADC_RegInitStruct->ContinuousMode
01227                  | pADC_RegInitStruct->DMATransfer
01228                  | pADC_RegInitStruct->Overrun
01229                 );
01230     }
01231     else
01232     {
01233       MODIFY_REG(ADCx->CFGR,
01234                  ADC_CFGR_EXTSEL
01235                  | ADC_CFGR_EXTEN
01236                  | ADC_CFGR_DISCEN
01237                  | ADC_CFGR_DISCNUM
01238                  | ADC_CFGR_CONT
01239                  | ADC_CFGR_DMAEN
01240                  | ADC_CFGR_DMACFG
01241                  | ADC_CFGR_OVRMOD
01242                  ,
01243                  pADC_RegInitStruct->TriggerSource
01244                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
01245                  | pADC_RegInitStruct->ContinuousMode
01246                  | pADC_RegInitStruct->DMATransfer
01247                  | pADC_RegInitStruct->Overrun
01248                 );
01249     }
01250
01251     /* Set ADC group regular sequencer length and scan direction */
01252     LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
01253   }
01254   else
01255   {
01256     /* Initialization error: ADC instance is not disabled. */
01257     status = ERROR;
01258   }
01259   return status;
01260 }
01261
01262 /**
01263   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
01264   * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
01265   *                            whose fields will be set to default values.
01266   * @retval None
01267   */
01268 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
01269 {
01270   /* Set pADC_RegInitStruct fields to default values */
01271   /* Set fields of ADC group regular */
01272   /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
01273   /*       setting of trigger source to SW start.                             */
01274   pADC_RegInitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
01275   pADC_RegInitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
01276   pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
01277   pADC_RegInitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
01278   pADC_RegInitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
01279   pADC_RegInitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
01280 }
01281
01282 /**
01283   * @brief  Initialize some features of ADC group injected.
01284   * @note   These parameters have an impact on ADC scope: ADC group injected.
01285   *         Refer to corresponding unitary functions into
01286   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
01287   *         (functions with prefix "INJ").
01288   * @note   The setting of these parameters by function @ref LL_ADC_Init()
01289   *         is conditioned to ADC state:
01290   *         ADC instance must be disabled.
01291   *         This condition is applied to all ADC features, for efficiency
01292   *         and compatibility over all STM32 series. However, the different
01293   *         features can be set under different ADC state conditions
01294   *         (setting possible with ADC enabled without conversion on going,
01295   *         ADC enabled with conversion on going, ...)
01296   *         Each feature can be updated afterwards with a unitary function
01297   *         and potentially with ADC in a different state than disabled,
01298   *         refer to description of each function for setting
01299   *         conditioned to ADC state.
01300   * @note   After using this function, other features must be configured
01301   *         using LL unitary functions.
01302   *         The minimum configuration remaining to be done is:
01303   *          - Set ADC group injected sequencer:
01304   *            map channel on the selected sequencer rank.
01305   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
01306   *          - Set ADC channel sampling time
01307   *            Refer to function LL_ADC_SetChannelSamplingTime();
01308   * @note   Caution if feature ADC group injected contexts queue is enabled
01309   *         (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
01310   *         using successively several times this function will appear as
01311   *         having no effect.
01312   *         To set several features of ADC group injected, use
01313   *         function @ref LL_ADC_INJ_ConfigQueueContext().
01314   * @param  ADCx ADC instance
01315   * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01316   * @retval An ErrorStatus enumeration value:
01317   *          - SUCCESS: ADC registers are initialized
01318   *          - ERROR: ADC registers are not initialized
01319   */
01320 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
01321 {
01322   ErrorStatus status = SUCCESS;
01323
01324   /* Check the parameters */
01325   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
01326   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource));
01327   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
01328   if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
01329   {
01330     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
01331   }
01332   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
01333
01334   /* Note: Hardware constraint (refer to description of this function):       */
01335   /*       ADC instance must be disabled.                                     */
01336   if (LL_ADC_IsEnabled(ADCx) == 0UL)
01337   {
01338     /* Configuration of ADC hierarchical scope:                               */
01339     /*  - ADC group injected                                                  */
01340     /*    - Set ADC group injected trigger source                             */
01341     /*    - Set ADC group injected sequencer length                           */
01342     /*    - Set ADC group injected sequencer discontinuous mode               */
01343     /*    - Set ADC group injected conversion trigger: independent or         */
01344     /*      from ADC group regular                                            */
01345     /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
01346     /*       setting of trigger source to SW start.                           */
01347     if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
01348     {
01349       MODIFY_REG(ADCx->CFGR,
01350                  ADC_CFGR_JDISCEN
01351                  | ADC_CFGR_JAUTO
01352                  ,
01353                  pADC_InjInitStruct->SequencerDiscont
01354                  | pADC_InjInitStruct->TrigAuto
01355                 );
01356     }
01357     else
01358     {
01359       MODIFY_REG(ADCx->CFGR,
01360                  ADC_CFGR_JDISCEN
01361                  | ADC_CFGR_JAUTO
01362                  ,
01363                  LL_ADC_REG_SEQ_DISCONT_DISABLE
01364                  | pADC_InjInitStruct->TrigAuto
01365                 );
01366     }
01367
01368     MODIFY_REG(ADCx->JSQR,
01369                ADC_JSQR_JEXTSEL
01370                | ADC_JSQR_JEXTEN
01371                | ADC_JSQR_JL
01372                ,
01373                pADC_InjInitStruct->TriggerSource
01374                | pADC_InjInitStruct->SequencerLength
01375               );
01376   }
01377   else
01378   {
01379     /* Initialization error: ADC instance is not disabled. */
01380     status = ERROR;
01381   }
01382   return status;
01383 }
01384
01385 /**
01386   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
01387   * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01388   *                            whose fields will be set to default values.
01389   * @retval None
01390   */
01391 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
01392 {
01393   /* Set pADC_InjInitStruct fields to default values */
01394   /* Set fields of ADC group injected */
01395   pADC_InjInitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
01396   pADC_InjInitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
01397   pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
01398   pADC_InjInitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
01399 }
01400
01401 /**
01402   * @}
01403   */
01404
01405 /**
01406   * @}
01407   */
01408
01409 /**
01410   * @}
01411   */
01412
01413 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
01414
01415 /**
01416   * @}
01417   */
01418
01419 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_adc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_adc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_ADC_H
00021 #define STM32G4xx_LL_ADC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
00035
00036 /** @defgroup ADC_LL ADC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00045   * @{
00046   */
00047
00048 /* Internal mask for ADC group regular sequencer:                             */
00049 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00050 /* - sequencer register offset                                                */
00051 /* - sequencer rank bits position into the selected register                  */
00052
00053 /* Internal register offset for ADC group regular sequencer configuration */
00054 /* (offset placed into a spare area of literal definition) */
00055 #define ADC_SQR1_REGOFFSET                 (0x00000000UL)
00056 #define ADC_SQR2_REGOFFSET                 (0x00000100UL)
00057 #define ADC_SQR3_REGOFFSET                 (0x00000200UL)
00058 #define ADC_SQR4_REGOFFSET                 (0x00000300UL)
00059
00060 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
00061                                             | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00062 #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
00063 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00064
00065 /* Definition of ADC group regular sequencer bits information to be inserted  */
00066 /* into ADC group regular sequencer ranks literals definition.                */
00067 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
00068 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
00069 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
00070 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
00071 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
00072 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
00073 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
00074 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
00075 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
00076 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
00077 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
00078 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
00079 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
00080 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
00081 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
00082 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
00083
00084
00085
00086 /* Internal mask for ADC group injected sequencer:                            */
00087 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00088 /* - data register offset                                                     */
00089 /* - sequencer rank bits position into the selected register                  */
00090
00091 /* Internal register offset for ADC group injected data register */
00092 /* (offset placed into a spare area of literal definition) */
00093 #define ADC_JDR1_REGOFFSET                 (0x00000000UL)
00094 #define ADC_JDR2_REGOFFSET                 (0x00000100UL)
00095 #define ADC_JDR3_REGOFFSET                 (0x00000200UL)
00096 #define ADC_JDR4_REGOFFSET                 (0x00000300UL)
00097
00098 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
00099                                             | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00100 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00101 #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
00102
00103 /* Definition of ADC group injected sequencer bits information to be inserted */
00104 /* into ADC group injected sequencer ranks literals definition.               */
00105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
00106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
00107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
00108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
00109
00110
00111
00112 /* Internal mask for ADC group regular trigger:                               */
00113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00114 /* - regular trigger source                                                   */
00115 /* - regular trigger edge                                                     */
00116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT      (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
00117                                                                  compatibility with some ADC on other STM32 series
00118                                                                  having this setting set by HW default value) */
00119
00120 /* Mask containing trigger source masks for each of possible                  */
00121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00123 #define ADC_REG_TRIG_SOURCE_MASK           (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
00124                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
00125                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
00126                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )
00127
00128 /* Mask containing trigger edge masks for each of possible                    */
00129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00130 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00131 #define ADC_REG_TRIG_EDGE_MASK             (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
00132                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
00133                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
00134                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )
00135
00136 /* Definition of ADC group regular trigger bits information.                  */
00137 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR_EXTSEL_Pos)
00138 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
00139
00140
00141
00142 /* Internal mask for ADC group injected trigger:                              */
00143 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00144 /* - injected trigger source                                                  */
00145 /* - injected trigger edge                                                    */
00146 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
00147                                                                   compatibility with some ADC on other STM32 series
00148                                                                   having this setting set by HW default value) */
00149
00150 /* Mask containing trigger source masks for each of possible                  */
00151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00153 #define ADC_INJ_TRIG_SOURCE_MASK           (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
00154                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
00155                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
00156                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
00157
00158 /* Mask containing trigger edge masks for each of possible                    */
00159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00160 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00161 #define ADC_INJ_TRIG_EDGE_MASK             (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
00162                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
00163                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
00164                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
00165
00166 /* Definition of ADC group injected trigger bits information.                 */
00167 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
00168 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
00169
00170
00171
00172
00173
00174
00175 /* Internal mask for ADC channel:                                             */
00176 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00177 /* - channel identifier defined by number                                     */
00178 /* - channel identifier defined by bitfield                                   */
00179 /* - channel differentiation between external channels (connected to          */
00180 /*   GPIO pins) and internal channels (connected to internal paths)           */
00181 /* - channel sampling time defined by SMPRx register offset                   */
00182 /*   and SMPx bits positions into SMPRx register                              */
00183 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00184 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
00186 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
00187                                             | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00188 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00189 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
00190   >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
00191
00192 /* Channel differentiation between external and internal channels */
00193 #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
00194 #define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
00195                                                              of different ADC internal channels mapped on same channel
00196                                                              number on different ADC instances */
00197 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00198
00199 /* Internal register offset for ADC channel sampling time configuration */
00200 /* (offset placed into a spare area of literal definition) */
00201 #define ADC_SMPR1_REGOFFSET                (0x00000000UL)
00202 #define ADC_SMPR2_REGOFFSET                (0x02000000UL)
00203 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00204 #define ADC_SMPRX_REGOFFSET_POS            (25UL)           /* Position of bits ADC_SMPRx_REGOFFSET
00205                                                                in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
00206
00207 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
00208 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
00209                                                                position in register */
00210
00211 /* Definition of channels ID number information to be inserted into           */
00212 /* channels literals definition.                                              */
00213 #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
00214 #define ADC_CHANNEL_1_NUMBER               (ADC_CFGR_AWD1CH_0)
00215 #define ADC_CHANNEL_2_NUMBER               (ADC_CFGR_AWD1CH_1)
00216 #define ADC_CHANNEL_3_NUMBER               (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00217 #define ADC_CHANNEL_4_NUMBER               (ADC_CFGR_AWD1CH_2)
00218 #define ADC_CHANNEL_5_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
00219 #define ADC_CHANNEL_6_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
00220 #define ADC_CHANNEL_7_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00221 #define ADC_CHANNEL_8_NUMBER               (ADC_CFGR_AWD1CH_3)
00222 #define ADC_CHANNEL_9_NUMBER               (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
00223 #define ADC_CHANNEL_10_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
00224 #define ADC_CHANNEL_11_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00225 #define ADC_CHANNEL_12_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
00226 #define ADC_CHANNEL_13_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
00227 #define ADC_CHANNEL_14_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
00228 #define ADC_CHANNEL_15_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
00229                                             ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00230 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4)
00231 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
00232 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
00233
00234 /* Definition of channels ID bitfield information to be inserted into         */
00235 /* channels literals definition.                                              */
00236 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00237 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00238 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00239 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00240 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00241 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00242 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00243 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00244 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00245 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00246 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00247 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00248 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00249 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00250 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00251 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00252 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00253 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00254 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00255
00256 /* Definition of channels sampling time information to be inserted into       */
00257 /* channels literals definition.                                              */
00258 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position         */
00259 /* in register.                                                               */
00260 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00261 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00262 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00263 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00264 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00265 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00266 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00267 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00268 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00269 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00270 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00271 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00272 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00273 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00274 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00275 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00276 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00277 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00278 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
00279
00280
00281 /* Internal mask for ADC mode single or differential ended:                   */
00282 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00283 /* the relevant bits for:                                                     */
00284 /* (concatenation of multiple bits used in different registers)               */
00285 /* - ADC calibration: calibration start, calibration factor get or set        */
00286 /* - ADC channels: set each ADC channel ending mode                           */
00287 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00288 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00289 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00290 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
00291                                            to perform of shift when single mode is selected, shift value out of
00292                                            channels bits range. */
00293 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
00294                                            mask of bit */
00295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)         /* Selection of 1 bit to discriminate differential mode:
00296                                            position of bit */
00297 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
00298                                            ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
00299
00300 /* Internal mask for ADC analog watchdog:                                     */
00301 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00302 /* (concatenation of multiple bits used in different analog watchdogs,        */
00303 /* (feature of several watchdogs not available on all STM32 series)).         */
00304 /* - analog watchdog 1: monitored channel defined by number,                  */
00305 /*   selection of ADC group (ADC groups regular and-or injected).             */
00306 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00307 /*   selection on groups.                                                     */
00308
00309 /* Internal register offset for ADC analog watchdog channel configuration */
00310 #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
00311 #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
00312 #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
00313
00314 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00315 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00316 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00317 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
00318
00319 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00320
00321 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00322 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00323 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00324
00325 #define ADC_AWD_CRX_REGOFFSET_POS          (20UL)                      /* Position of bits ADC_AWD_CRx_REGOFFSET
00326                                                                           in ADC_AWD_CRX_REGOFFSET_MASK */
00327
00328 /* Internal register offset for ADC analog watchdog threshold configuration */
00329 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00330 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00331 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00332 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00333 #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)      /* Position of bits ADC_SQRx_REGOFFSET
00334                                                                                in ADC_AWD_TRX_REGOFFSET_MASK */
00335 #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate
00336                                                                                threshold high: mask of bit */
00337 #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate
00338                                                                                threshold high: position of bit */
00339 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
00340                                                                                position to perform a shift of 4 ranks */
00341
00342 /* Internal mask for ADC offset:                                              */
00343 /* Internal register offset for ADC offset instance configuration */
00344 #define ADC_OFR1_REGOFFSET                 (0x00000000UL)
00345 #define ADC_OFR2_REGOFFSET                 (0x00000001UL)
00346 #define ADC_OFR3_REGOFFSET                 (0x00000002UL)
00347 #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
00348 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
00349                                             | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00350
00351
00352 /* ADC registers bits positions */
00353 #define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
00354 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
00355 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
00356 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
00357 #define ADC_TR1_HT1_BITOFFSET_POS          (ADC_TR1_HT1_Pos)
00358
00359
00360 /* ADC registers bits groups */
00361 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
00362                                             | ADC_CR_JADSTART | ADC_CR_JADSTP \
00363                                             | ADC_CR_ADSTART | ADC_CR_ADSTP)            /* ADC register CR bits with
00364                                            HW property "rs": Software can read as well as set this bit.
00365                                            Writing '0' has no effect on the bit value. */
00366
00367
00368 /* ADC internal channels related definitions */
00369 /* Internal voltage reference VrefInt */
00370 #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
00371                                            parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
00372                                            (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00373 #define VREFINT_CAL_VREF                   (3000UL)                     /* Analog voltage reference (Vref+) value
00374                                            with which VrefInt has been calibrated in production
00375                                            (tolerance: +-10 mV) (unit: mV). */
00376 /* Temperature sensor */
00377 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
00378                                            temperature sensor ADC raw data acquired at temperature  30 DegC
00379                                            (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00380 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
00381                                            temperature sensor ADC raw data acquired at temperature 110 DegC
00382                                            (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00383 #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Temperature at which temperature sensor
00384                                            has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
00385                                            (tolerance: +-5 DegC) (unit: DegC). */
00386 #define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Temperature at which temperature sensor
00387                                            has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
00388                                            (tolerance: +-5 DegC) (unit: DegC). */
00389 #define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference (Vref+) value
00390                                            with which temperature sensor has been calibrated in production
00391                                            (tolerance +-10 mV) (unit: mV). */
00392
00393 /**
00394   * @}
00395   */
00396
00397
00398 /* Private macros ------------------------------------------------------------*/
00399 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00400   * @{
00401   */
00402
00403 /**
00404   * @brief  Driver macro reserved for internal use: set a pointer to
00405   *         a register from a register basis from which an offset
00406   *         is applied.
00407   * @param  __REG__ Register basis from which the offset is applied.
00408   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00409   * @retval Pointer to register address
00410   */
00411 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00412   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00413
00414 /**
00415   * @}
00416   */
00417
00418
00419 /* Exported types ------------------------------------------------------------*/
00420 #if defined(USE_FULL_LL_DRIVER)
00421 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00422   * @{
00423   */
00424
00425 /**
00426   * @brief  Structure definition of some features of ADC common parameters
00427   *         and multimode
00428   *         (all ADC instances belonging to the same ADC common instance).
00429   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00430   *         is conditioned to ADC instances state (all ADC instances
00431   *         sharing the same ADC common instance):
00432   *         All ADC instances sharing the same ADC common instance must be
00433   *         disabled.
00434   */
00435 typedef struct
00436 {
00437   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00438                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00439                                              @note On this STM32 series, if ADC group injected is used, some clock ratio
00440                                                    constraints between ADC clock and AHB clock must be respected.
00441                                                    Refer to reference manual.
00442                                              This feature can be modified afterwards using unitary function
00443                                              @ref LL_ADC_SetCommonClock(). */
00444
00445 #if defined(ADC_MULTIMODE_SUPPORT)
00446   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode
00447                                              (for devices with several ADC instances).
00448                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
00449                                              This feature can be modified afterwards using unitary function
00450                                              @ref LL_ADC_SetMultimode(). */
00451
00452   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
00453                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
00454                                              This feature can be modified afterwards using unitary function
00455                                              @ref LL_ADC_SetMultiDMATransfer(). */
00456
00457   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
00458                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
00459                                              This feature can be modified afterwards using unitary function
00460                                              @ref LL_ADC_SetMultiTwoSamplingDelay(). */
00461 #endif /* ADC_MULTIMODE_SUPPORT */
00462
00463 } LL_ADC_CommonInitTypeDef;
00464
00465 /**
00466   * @brief  Structure definition of some features of ADC instance.
00467   * @note   These parameters have an impact on ADC scope: ADC instance.
00468   *         Affects both group regular and group injected (availability
00469   *         of ADC group injected depends on STM32 series).
00470   *         Refer to corresponding unitary functions into
00471   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00472   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00473   *         is conditioned to ADC state:
00474   *         ADC instance must be disabled.
00475   *         This condition is applied to all ADC features, for efficiency
00476   *         and compatibility over all STM32 series. However, the different
00477   *         features can be set under different ADC state conditions
00478   *         (setting possible with ADC enabled without conversion on going,
00479   *         ADC enabled with conversion on going, ...)
00480   *         Each feature can be updated afterwards with a unitary function
00481   *         and potentially with ADC in a different state than disabled,
00482   *         refer to description of each function for setting
00483   *         conditioned to ADC state.
00484   */
00485 typedef struct
00486 {
00487   uint32_t Resolution;                  /*!< Set ADC resolution.
00488                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00489                                              This feature can be modified afterwards using unitary function
00490                                              @ref LL_ADC_SetResolution(). */
00491
00492   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00493                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00494                                              This feature can be modified afterwards using unitary function
00495                                              @ref LL_ADC_SetDataAlignment(). */
00496
00497   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00498                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00499                                              This feature can be modified afterwards using unitary function
00500                                              @ref LL_ADC_SetLowPowerMode(). */
00501
00502 } LL_ADC_InitTypeDef;
00503
00504 /**
00505   * @brief  Structure definition of some features of ADC group regular.
00506   * @note   These parameters have an impact on ADC scope: ADC group regular.
00507   *         Refer to corresponding unitary functions into
00508   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00509   *         (functions with prefix "REG").
00510   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00511   *         is conditioned to ADC state:
00512   *         ADC instance must be disabled.
00513   *         This condition is applied to all ADC features, for efficiency
00514   *         and compatibility over all STM32 series. However, the different
00515   *         features can be set under different ADC state conditions
00516   *         (setting possible with ADC enabled without conversion on going,
00517   *         ADC enabled with conversion on going, ...)
00518   *         Each feature can be updated afterwards with a unitary function
00519   *         and potentially with ADC in a different state than disabled,
00520   *         refer to description of each function for setting
00521   *         conditioned to ADC state.
00522   */
00523 typedef struct
00524 {
00525   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or
00526                                              from external peripheral (timer event, external interrupt line).
00527                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00528                                              @note On this STM32 series, setting trigger source to external trigger also
00529                                                    set trigger polarity to rising edge(default setting for compatibility
00530                                                    with some ADC on other STM32 series having this setting set by HW
00531                                                    default value).
00532                                                    In case of need to modify trigger edge, use function
00533                                                    @ref LL_ADC_REG_SetTriggerEdge().
00534                                              This feature can be modified afterwards using unitary function
00535                                              @ref LL_ADC_REG_SetTriggerSource(). */
00536
00537   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00538                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00539                                              This feature can be modified afterwards using unitary function
00540                                              @ref LL_ADC_REG_SetSequencerLength(). */
00541
00542   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
00543                                              and scan conversions interrupted every selected number of ranks.
00544                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00545                                              @note This parameter has an effect only if group regular sequencer is
00546                                                     enabled (scan length of 2 ranks or more).
00547                                              This feature can be modified afterwards using unitary function
00548                                              @ref LL_ADC_REG_SetSequencerDiscont(). */
00549
00550   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
00551                                              conversions are performed in single mode (one conversion per trigger) or in
00552                                              continuous mode (after the first trigger, following conversions launched
00553                                              successively automatically).
00554                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00555                                              Note: It is not possible to enable both ADC group regular continuous mode
00556                                                    and discontinuous mode.
00557                                              This feature can be modified afterwards using unitary function
00558                                              @ref LL_ADC_REG_SetContinuousMode(). */
00559
00560   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer
00561                                              by DMA, and DMA requests mode.
00562                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00563                                              This feature can be modified afterwards using unitary function
00564                                              @ref LL_ADC_REG_SetDMATransfer(). */
00565
00566   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00567                                              data preserved or overwritten.
00568                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00569                                              This feature can be modified afterwards using unitary function
00570                                              @ref LL_ADC_REG_SetOverrun(). */
00571
00572 } LL_ADC_REG_InitTypeDef;
00573
00574 /**
00575   * @brief  Structure definition of some features of ADC group injected.
00576   * @note   These parameters have an impact on ADC scope: ADC group injected.
00577   *         Refer to corresponding unitary functions into
00578   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00579   *         (functions with prefix "INJ").
00580   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00581   *         is conditioned to ADC state:
00582   *         ADC instance must be disabled.
00583   *         This condition is applied to all ADC features, for efficiency
00584   *         and compatibility over all STM32 series. However, the different
00585   *         features can be set under different ADC state conditions
00586   *         (setting possible with ADC enabled without conversion on going,
00587   *         ADC enabled with conversion on going, ...)
00588   *         Each feature can be updated afterwards with a unitary function
00589   *         and potentially with ADC in a different state than disabled,
00590   *         refer to description of each function for setting
00591   *         conditioned to ADC state.
00592   */
00593 typedef struct
00594 {
00595   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start)
00596                                              or from external peripheral (timer event, external interrupt line).
00597                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00598                                              @note On this STM32 series, setting trigger source to external trigger also
00599                                                    set trigger polarity to rising edge (default setting for
00600                                                    compatibility with some ADC on other STM32 series having this
00601                                                    setting set by HW default value).
00602                                                    In case of need to modify trigger edge, use function
00603                                                    @ref LL_ADC_INJ_SetTriggerEdge().
00604                                              This feature can be modified afterwards using unitary function
00605                                              @ref LL_ADC_INJ_SetTriggerSource(). */
00606
00607   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00608                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00609                                              This feature can be modified afterwards using unitary function
00610                                              @ref LL_ADC_INJ_SetSequencerLength(). */
00611
00612   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
00613                                              and scan conversions interrupted every selected number of ranks.
00614                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00615                                              @note This parameter has an effect only if group injected sequencer is
00616                                                    enabled (scan length of 2 ranks or more).
00617                                              This feature can be modified afterwards using unitary function
00618                                              @ref LL_ADC_INJ_SetSequencerDiscont(). */
00619
00620   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group
00621                                              regular.
00622                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00623                                              Note: This parameter must be set to set to independent trigger if injected
00624                                                    trigger source is set to an external trigger.
00625                                              This feature can be modified afterwards using unitary function
00626                                              @ref LL_ADC_INJ_SetTrigAuto(). */
00627
00628 } LL_ADC_INJ_InitTypeDef;
00629
00630 /**
00631   * @}
00632   */
00633 #endif /* USE_FULL_LL_DRIVER */
00634
00635 /* Exported constants --------------------------------------------------------*/
00636 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00637   * @{
00638   */
00639
00640 /** @defgroup ADC_LL_EC_FLAG ADC flags
00641   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00642   * @{
00643   */
00644 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00645 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary
00646                                            conversion */
00647 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence
00648                                            conversions */
00649 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00650 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00651 #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary
00652                                                                    conversion */
00653 #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence
00654                                                                    conversions */
00655 #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue
00656                                                                    overflow */
00657 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00658 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00659 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00660 #if defined(ADC_MULTIMODE_SUPPORT)
00661 #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
00662 #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
00663 #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of
00664                                                                    unitary conversion */
00665 #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of
00666                                                                    unitary conversion */
00667 #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of
00668                                                                    sequence conversions */
00669 #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of
00670                                                                    sequence conversions */
00671 #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular
00672                                                                    overrun */
00673 #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular
00674                                                                    overrun */
00675 #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of
00676                                                                    sampling phase */
00677 #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of
00678                                                                    sampling phase */
00679 #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of
00680                                                                    unitary conversion */
00681 #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of
00682                                                                    unitary conversion */
00683 #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of
00684                                                                    sequence conversions */
00685 #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of
00686                                                                    sequence conversions */
00687 #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected
00688                                                                    contexts queue overflow */
00689 #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected
00690                                                                    contexts queue overflow */
00691 #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1
00692                                                                    of the ADC master */
00693 #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1
00694                                                                    of the ADC slave */
00695 #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2
00696                                                                    of the ADC master */
00697 #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2
00698                                                                    of the ADC slave */
00699 #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3
00700                                                                    of the ADC master */
00701 #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3
00702                                                                    of the ADC slave */
00703 #endif /* ADC_MULTIMODE_SUPPORT */
00704 /**
00705   * @}
00706   */
00707
00708 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00709   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00710   * @{
00711   */
00712 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00713 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary
00714                                                                    conversion */
00715 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence
00716                                                                    conversions */
00717 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00718 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling
00719                                                                    phase */
00720 #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary
00721                                                                    conversion */
00722 #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence
00723                                                                    conversions */
00724 #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue
00725                                                                    overflow */
00726 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00727 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00728 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00734   * @{
00735   */
00736 /* List of ADC registers intended to be used (most commonly) with             */
00737 /* DMA transfer.                                                              */
00738 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00739 #define LL_ADC_DMA_REG_REGULAR_DATA        (0x00000000UL)      /* ADC group regular conversion data register
00740                                            (corresponding to register DR) to be used with ADC configured in independent
00741                                            mode. Without DMA transfer, register accessed by LL function
00742                                            @ref LL_ADC_REG_ReadConversionData32() and other
00743                                            functions @ref LL_ADC_REG_ReadConversionDatax() */
00744 #if defined(ADC_MULTIMODE_SUPPORT)
00745 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI  (0x00000001UL)      /* ADC group regular conversion data register
00746                                            (corresponding to register CDR) to be used with ADC configured in multimode
00747                                            (available on STM32 devices with several ADC instances).
00748                                            Without DMA transfer, register accessed by LL function
00749                                            @ref LL_ADC_REG_ReadMultiConversionData32() */
00750 #endif /* ADC_MULTIMODE_SUPPORT */
00751 /**
00752   * @}
00753   */
00754
00755 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00756   * @{
00757   */
00758 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                    /*!< ADC synchronous clock derived from
00759                                            AHB clock without prescaler */
00760 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1)                    /*!< ADC synchronous clock derived from
00761                                            AHB clock with prescaler division by 2 */
00762 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
00763                                            AHB clock with prescaler division by 4 */
00764 #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                      /*!< ADC asynchronous clock without
00765                                            prescaler */
00766 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with
00767                                            prescaler division by 2 */
00768 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with
00769                                            prescaler division by 4 */
00770 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
00771                                            prescaler division by 6 */
00772 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2)                   /*!< ADC asynchronous clock with
00773                                            prescaler division by 8 */
00774 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
00775                                            prescaler division by 10 */
00776 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
00777                                            prescaler division by 12 */
00778 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
00779                                             | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
00780                                            prescaler division by 16  */
00781 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                   /*!< ADC asynchronous clock with
00782                                            prescaler division by 32 */
00783 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
00784                                            prescaler division by 64 */
00785 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
00786                                            prescaler division by 128 */
00787 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
00788                                             | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
00789                                            prescaler division by 256 */
00790 /**
00791   * @}
00792   */
00793
00794 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00795   * @{
00796   */
00797 /* Note: Other measurement paths to internal channels may be available        */
00798 /*       (connections to other peripherals).                                  */
00799 /*       If they are not listed below, they do not require any specific       */
00800 /*       path enable. In this case, Access to measurement path is done        */
00801 /*       only by selecting the corresponding ADC internal channel.            */
00802 #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)       /*!< ADC measurement paths all disabled */
00803 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)     /*!< ADC measurement path to internal channel VrefInt */
00804 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_VSENSESEL)  /*!< ADC measurement path to internal channel
00805                                                                      temperature sensor */
00806 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATSEL)    /*!< ADC measurement path to internal channel Vbat */
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00812   * @{
00813   */
00814 #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
00815 #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
00816 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
00817 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
00818 /**
00819   * @}
00820   */
00821
00822 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00823   * @{
00824   */
00825 #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)     /*!< ADC conversion data alignment: right aligned
00826                                            (alignment on data register LSB bit 0)*/
00827 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)   /*!< ADC conversion data alignment: left aligned
00828                                            (alignment on data register MSB bit 15)*/
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00834   * @{
00835   */
00836 #define LL_ADC_LP_MODE_NONE                (0x00000000UL)     /*!< No ADC low power mode activated */
00837 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)  /*!< ADC low power mode auto delay: Dynamic low power
00838                                            mode, ADC conversions are performed only when necessary
00839                                            (when previous ADC conversion data is read).
00840                                            See description with function @ref LL_ADC_SetLowPowerMode(). */
00841 /**
00842   * @}
00843   */
00844
00845 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset instance
00846   * @{
00847   */
00848 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
00849                                            to which the offset programmed will be applied (independently of channel
00850                                            mapped on ADC group regular or injected) */
00851 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
00852                                            to which the offset programmed will be applied (independently of channel
00853                                            mapped on ADC group regular or injected) */
00854 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
00855                                            to which the offset programmed will be applied (independently of channel
00856                                            mapped on ADC group regular or injected) */
00857 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
00858                                            to which the offset programmed will be applied (independently of channel
00859                                            mapped on ADC group regular or injected) */
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
00865   * @{
00866   */
00867 #define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled
00868                                            (setting offset instance wise) */
00869 #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled
00870                                            (setting offset instance wise) */
00871 /**
00872   * @}
00873   */
00874
00875 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
00876   * @{
00877   */
00878 #define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative */
00879 #define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
00880 /**
00881   * @}
00882   */
00883
00884 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
00885   * @{
00886   */
00887 #define LL_ADC_OFFSET_SATURATION_DISABLE   (0x00000000UL)     /*!< ADC offset saturation is disabled (among ADC
00888                                            selected offset instance 1, 2, 3 or 4) */
00889 #define LL_ADC_OFFSET_SATURATION_ENABLE    (ADC_OFR1_SATEN)   /*!< ADC offset saturation is enabled (among ADC
00890                                            selected offset instance 1, 2, 3 or 4) */
00891 /**
00892   * @}
00893   */
00894 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00895   * @{
00896   */
00897 #define LL_ADC_GROUP_REGULAR               (0x00000001UL)     /*!< ADC group regular (available on all STM32 devices) */
00898 #define LL_ADC_GROUP_INJECTED              (0x00000002UL)     /*!< ADC group injected (not available on all STM32
00899                                            devices)*/
00900 #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL)     /*!< ADC both groups regular and injected */
00901 /**
00902   * @}
00903   */
00904
00905 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00906   * @{
00907   */
00908 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP \
00909                                             | ADC_CHANNEL_0_BITFIELD)                       /*!< ADC channel ADCx_IN0 */
00910 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP \
00911                                             | ADC_CHANNEL_1_BITFIELD)                       /*!< ADC channel ADCx_IN1 */
00912 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP \
00913                                             | ADC_CHANNEL_2_BITFIELD)                       /*!< ADC channel ADCx_IN2 */
00914 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP \
00915                                             | ADC_CHANNEL_3_BITFIELD)                       /*!< ADC channel ADCx_IN3 */
00916 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP \
00917                                             | ADC_CHANNEL_4_BITFIELD)                       /*!< ADC channel ADCx_IN4 */
00918 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP \
00919                                             | ADC_CHANNEL_5_BITFIELD)                       /*!< ADC channel ADCx_IN5 */
00920 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP \
00921                                             | ADC_CHANNEL_6_BITFIELD)                       /*!< ADC channel ADCx_IN6 */
00922 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP \
00923                                             | ADC_CHANNEL_7_BITFIELD)                       /*!< ADC channel ADCx_IN7 */
00924 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP \
00925                                             | ADC_CHANNEL_8_BITFIELD)                       /*!< ADC channel ADCx_IN8 */
00926 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP \
00927                                             | ADC_CHANNEL_9_BITFIELD)                       /*!< ADC channel ADCx_IN9 */
00928 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
00929                                             | ADC_CHANNEL_10_BITFIELD)                      /*!< ADC channel ADCx_IN10 */
00930 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
00931                                             | ADC_CHANNEL_11_BITFIELD)                      /*!< ADC channel ADCx_IN11 */
00932 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
00933                                             | ADC_CHANNEL_12_BITFIELD)                      /*!< ADC channel ADCx_IN12 */
00934 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
00935                                             | ADC_CHANNEL_13_BITFIELD)                      /*!< ADC channel ADCx_IN13 */
00936 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
00937                                             | ADC_CHANNEL_14_BITFIELD)                      /*!< ADC channel ADCx_IN14 */
00938 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
00939                                             | ADC_CHANNEL_15_BITFIELD)                      /*!< ADC channel ADCx_IN15 */
00940 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
00941                                            ADC_CHANNEL_16_BITFIELD)                        /*!< ADC channel ADCx_IN16 */
00942 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
00943                                            ADC_CHANNEL_17_BITFIELD)                        /*!< ADC channel ADCx_IN17 */
00944 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
00945                                            ADC_CHANNEL_18_BITFIELD)                        /*!< ADC channel ADCx_IN18 */
00946 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00947                                            connected to VrefInt: Internal voltage reference.
00948                                            On this STM32 series, ADC channel available on all instances but ADC2. */
00949 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1     (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00950                                            connected to internal temperature sensor.
00951                                            On this STM32 series, ADC channel available only on ADC1 instance. */
00952 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5     (LL_ADC_CHANNEL_4  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00953                                            connected to internal temperature sensor.
00954                                            On this STM32 series, ADC channel available only on ADC5 instance.
00955                                            Refer to device datasheet for ADC5 availaibility */
00956 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00957                                            connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3
00958                                            to have channel voltage always below Vdda. On this STM32 series, ADC channel
00959                                            available on all ADC instances but ADC2 & ADC4. Refer to device datasheet
00960                                            for ADC4 availaibility */
00961 #define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00962                                            connected to OPAMP1 output.
00963                                            On this STM32 series, ADC channel available only on ADC1 instance. */
00964 #define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
00965                                            ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2
00966                                            output. On this STM32 series, ADC channel available only on ADC2 instance. */
00967 #define LL_ADC_CHANNEL_VOPAMP3_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
00968                                            ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
00969                                            output. On this STM32 series, ADC channel available only on ADC2 instance. */
00970 #define LL_ADC_CHANNEL_VOPAMP3_ADC3        (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
00971                                            ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
00972                                            output. On this STM32 series, ADC channel available only on ADC3 instance.
00973                                            Refer to device datasheet for ADC3 availability */
00974 #define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_5  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00975 connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance.
00976 Refer to device datasheet for ADC5 & OPAMP4 availability */
00977 #define LL_ADC_CHANNEL_VOPAMP5             (LL_ADC_CHANNEL_3  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
00978 connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance.
00979 Refer to device datasheet for ADC5 & OPAMP5 availability */
00980 #define LL_ADC_CHANNEL_VOPAMP6             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
00981                                            ADC_CHANNEL_ID_INTERNAL_CH_2)                    /*!< ADC internal channel
00982                                            connected to OPAMP6 output.
00983                                            On this STM32 series, ADC channel available only on ADC4 instance.
00984                                            Refer to device datasheet for ADC4 & OPAMP6 availability */
00985 /**
00986   * @}
00987   */
00988
00989 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00990   * @{
00991   */
00992 #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                        /*!< ADC group regular
00993                                            conversion trigger internal: SW start. */
00994 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
00995                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
00996                                            conversion trigger from external peripheral: TIM1 TRGO.
00997                                            Trigger edge set to rising edge (default setting). */
00998 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
00999                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01000                                            conversion trigger from external peripheral: TIM1 TRGO2.
01001                                            Trigger edge set to rising edge (default setting). */
01002 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular
01003                                            conversion trigger from external peripheral: TIM1 channel 1 event (capture
01004                                            compare: input capture or output capture).
01005                                            Trigger edge set to rising edge (default setting).
01006                                            Note: On this STM32 series, this trigger is available only on
01007                                            ADC1/2 instances */
01008 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
01009                                            conversion trigger from external peripheral: TIM1 channel 2 event (capture
01010                                            compare: input capture or output capture).
01011                                            Trigger edge set to rising edge (default setting).
01012                                            Note: On this STM32 series, this trigger is available only on
01013                                            ADC1/2 instances */
01014 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
01015                                            conversion trigger from external peripheral: TIM1 channel 3 event (capture
01016                                            compare: input capture or output capture).
01017                                            Trigger edge set to rising edge (default setting). */
01018 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
01019                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01020                                            conversion trigger from external peripheral: TIM2 TRGO.
01021                                            Trigger edge set to rising edge (default setting). */
01022 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
01023                                            ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01024                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
01025                                            conversion trigger from external peripheral: TIM2 channel 1 event (capture
01026                                            compare: input capture or output capture).
01027                                            Trigger edge set to rising edge (default setting).
01028                                            Note: On this STM32 series, this trigger is available only on
01029                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01030 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01031                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01032                                            conversion trigger from external peripheral: TIM2 channel 2 event (capture
01033                                            compare: input capture or output capture).
01034                                            Trigger edge set to rising edge (default setting).
01035                                            Note: On this STM32 series, this trigger is available only on
01036                                            ADC1/2 instances */
01037 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
01038                                            conversion trigger from external peripheral: TIM2 channel 3 event (capture
01039                                            compare: input capture or output capture).
01040                                            Trigger edge set to rising edge (default setting).
01041                                            Note: On this STM32 series, this trigger is available only on
01042                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01043 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
01044                                            conversion trigger from external peripheral: TIM3 TRGO.
01045                                            Trigger edge set to rising edge (default setting). */
01046 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular
01047                                            conversion trigger from external peripheral: TIM3 channel 1 event (capture
01048                                            compare: input capture or output capture).
01049                                            Trigger edge set to rising edge (default setting).
01050                                            Note: On this STM32 series, this trigger is available only on
01051                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01052 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
01053                                            ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01054                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01055                                            conversion trigger from external peripheral: TIM3 channel 4 event (capture
01056                                            compare: input capture or output capture).
01057                                            Trigger edge set to rising edge (default setting).
01058                                            Note: On this STM32 series, this trigger is available only on
01059                                            ADC1/2 instances */
01060 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
01061                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01062                                            conversion trigger from external peripheral: TIM4 TRGO.
01063                                            Trigger edge set to rising edge (default setting). */
01064 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
01065                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01066                                            conversion trigger from external peripheral: TIM4 channel 1 event (capture
01067                                            compare: input capture or output capture).
01068                                            Trigger edge set to rising edge (default setting).
01069                                            Note: On this STM32 series, this trigger is available only on
01070                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01071 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
01072                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01073                                            conversion trigger from external peripheral: TIM4 channel 4 event (capture
01074                                            compare: input capture or output capture).
01075                                            Trigger edge set to rising edge (default setting).
01076                                            Note: On this STM32 series, this trigger is available only on
01077                                            ADC1/2 instances */
01078 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
01079                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01080                                            conversion trigger from external peripheral: TIM6 TRGO.
01081                                            Trigger edge set to rising edge (default setting). */
01082 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01083                                            ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
01084                                            conversion trigger from external peripheral: TIM7 TRGO.
01085                                            Trigger edge set to rising edge (default setting). */
01086 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
01087                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01088                                            conversion trigger from external peripheral: TIM8 TRGO.
01089                                            Trigger edge set to rising edge (default setting). */
01090 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
01091                                            conversion trigger from external peripheral: TIM8 TRGO2.
01092                                            Trigger edge set to rising edge (default setting). */
01093 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01094                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01095                                            conversion trigger from external peripheral: TIM8 channel 1 event (capture
01096                                            compare: input capture or output capture).
01097                                            Trigger edge set to rising edge (default setting).
01098                                            Note: On this STM32 series, this trigger is available only on
01099                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01100 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
01101                                            ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01102                                            conversion trigger from external peripheral: TIM15 TRGO.
01103                                            Trigger edge set to rising edge (default setting). */
01104 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO     (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular
01105                                            conversion trigger from external peripheral: TIM20 TRGO.
01106                                            Trigger edge set to rising edge (default setting).
01107                                            Note: On this STM32 series, TIM20 is not available on all devices.
01108                                            Refer to device datasheet for more details */
01109 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \
01110                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01111                                            conversion trigger from external peripheral: TIM20 TRGO2.
01112                                            Trigger edge set to rising edge (default setting).
01113                                            Note: On this STM32 series, TIM20 is not available on all devices.
01114                                            Refer to device datasheet for more details */
01115 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
01116                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01117                                            conversion trigger from external peripheral: TIM20 channel 1 event (capture
01118                                            compare: input capture or output capture).
01119                                            Trigger edge set to rising edge (default setting).
01120                                            Note: On this STM32 series, TIM20 is not available on all devices.
01121                                            Refer to device datasheet for more details */
01122 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
01123                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01124                                            conversion trigger from external peripheral: TIM20 channel 2 event (capture
01125                                            compare: input capture or output capture).
01126                                            Trigger edge set to rising edge (default setting).
01127                                            Note: On this STM32 series, this trigger is available only on
01128                                            ADC1/2 instances, and TIM20 is not available on all devices.
01129                                            Refer to device datasheet for more details */
01130 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
01131                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01132                                            conversion trigger from external peripheral: TIM20 channel 3 event (capture
01133                                            compare: input capture or output capture).
01134                                            Trigger edge set to rising edge (default setting).
01135                                            Note: On this STM32 series, this trigger is available only on
01136                                            ADC1/2 instances, and TIM20 is not available on all devices.
01137                                            Refer to device datasheet for more details */
01138 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
01139                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01140                                            conversion trigger from external peripheral: HRTIMER ADC trigger 1 event.
01141                                            Trigger edge set to rising edge (default setting).
01142                                            Note: On this STM32 series, HRTIM is not available on all devices.
01143                                            Refer to device datasheet for more details */
01144 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
01145                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01146                                            conversion trigger from external peripheral: HRTIMER ADC trigger 2 event.
01147                                            Trigger edge set to rising edge (default setting).
01148                                            Note: On this STM32 series, this trigger is available only on
01149                                            ADC3/4/5 instances, and HRTIM is not available on all devices.
01150                                            Refer to device datasheet for more details */
01151 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
01152                                            ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01153                                            conversion trigger from external peripheral: HRTIMER ADC trigger 3 event.
01154                                            Trigger edge set to rising edge (default setting).
01155                                            Note: On this STM32 series, HRTIM is not available on all devices.
01156                                            Refer to device datasheet for more details */
01157 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
01158                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01159                                            conversion trigger from external peripheral: HRTIMER ADC trigger 4 event.
01160                                            Trigger edge set to rising edge (default setting).
01161                                            Note: On this STM32 series, this trigger is available only on
01162                                            ADC3/4/5 instances, and HRTIM is not available on all devices.
01163                                            Refer to device datasheet for more details */
01164 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
01165                                            ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01166                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01167                                            conversion trigger from external peripheral: HRTIMER ADC trigger 5 event.
01168                                            Trigger edge set to rising edge (default setting).
01169                                            Note: On this STM32 series, HRTIM is not available on all devices.
01170                                            Refer to device datasheet for more details */
01171 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01172                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01173                                            conversion trigger from external peripheral: HRTIMER ADC trigger 6 event.
01174                                            Trigger edge set to rising edge (default setting).
01175                                            Note: On this STM32 series, HRTIM is not available on all devices.
01176                                            Refer to device datasheet for more details */
01177 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01178                                            ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01179                                            conversion trigger from external peripheral: HRTIMER ADC trigger 7 event.
01180                                            Trigger edge set to rising edge (default setting).
01181                                            Note: On this STM32 series, HRTIM is not available on all devices.
01182                                            Refer to device datasheet for more details */
01183 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01184                                            ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01185                                            conversion trigger from external peripheral: HRTIMER ADC trigger 8 event.
01186                                            Trigger edge set to rising edge (default setting).
01187                                            Note: On this STM32 series, HRTIM is not available on all devices.
01188                                            Refer to device datasheet for more details */
01189 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01190                                            ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
01191                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01192                                            conversion trigger from external peripheral: HRTIMER ADC trigger 9 event.
01193                                            Trigger edge set to rising edge (default setting).
01194                                            Note: On this STM32 series, HRTIM is not available on all devices.
01195                                            Refer to device datasheet for more details */
01196 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01197                                            ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
01198                                            conversion trigger from external peripheral: HRTIMER ADC trigger 10 event.
01199                                            Trigger edge set to rising edge (default setting).
01200                                            Note: On this STM32 series, HRTIM is not available on all devices.
01201                                            Refer to device datasheet for more details */
01202 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
01203                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01204                                            conversion trigger from external peripheral: external interrupt line 11.
01205                                            Trigger edge set to rising edge (default setting).
01206                                            Note: On this STM32 series, this trigger is available only on
01207                                            ADC1/2 instances */
01208 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
01209                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01210                                            conversion trigger from external peripheral: external interrupt line 2.
01211                                            Trigger edge set to rising edge (default setting).
01212                                            Note: On this STM32 series, this trigger is available only on
01213                                            ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
01214 #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
01215                                            ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
01216                                            ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
01217                                            conversion trigger from external peripheral: LPTIMER OUT event.
01218                                            Trigger edge set to rising edge (default setting). */
01219 /**
01220   * @}
01221   */
01222
01223 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
01224   * @{
01225   */
01226 #define LL_ADC_REG_TRIG_EXT_RISING         (ADC_CFGR_EXTEN_0)                      /*!< ADC group regular conversion
01227                                            trigger polarity set to rising edge */
01228 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1)                      /*!< ADC group regular conversion
01229                                            trigger polarity set to falling edge */
01230 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion
01231                                            trigger polarity set to both rising and falling edges */
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
01237   * @{
01238   */
01239 #define LL_ADC_REG_SAMPLING_MODE_NORMAL               (0x00000000UL)       /*!< ADC conversions sampling phase duration
01240                                            is defined using  @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
01241 #define LL_ADC_REG_SAMPLING_MODE_BULB                 (ADC_CFGR2_BULB)     /*!< ADC conversions sampling phase starts
01242                                            immediately after end of conversion, and stops upon trigger event.
01243                                            Note: First conversion is using minimal sampling time
01244                                            (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
01245 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED    (ADC_CFGR2_SMPTRIG)  /*!< ADC conversions sampling phase is
01246                                            controlled by trigger events: trigger rising edge for start sampling,
01247                                            trigger falling edge for stop sampling and start conversion */
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
01253   * @{
01254   */
01255 #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)     /*!< ADC conversions performed in single mode:
01256                                            one conversion per trigger */
01257 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)    /*!< ADC conversions performed in continuous mode:
01258                                            after the first trigger, following conversions launched successively
01259                                            automatically */
01260 /**
01261   * @}
01262   */
01263
01264 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
01265   * @{
01266   */
01267 #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)     /*!< ADC conversions are not transferred by DMA */
01268 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA
01269                                            in limited mode (one shot mode): DMA transfer requests are stopped when
01270                                            number of DMA data transfers (number of ADC conversions) is reached.
01271                                            This ADC mode is intended to be used with DMA mode non-circular. */
01272 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversion data are
01273                                            transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
01274                                            whatever number of DMA data transferred (number of ADC conversions).
01275                                            This ADC mode is intended to be used with DMA mode circular. */
01276 /**
01277   * @}
01278   */
01279
01280 #if defined(ADC_SMPR1_SMPPLUS)
01281 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
01282   * @{
01283   */
01284 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000UL)      /*!< ADC sampling time let to default settings. */
01285 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
01286                                            cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
01287                                            with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
01288                                            on ADC groups regular or injected). */
01289 /**
01290   * @}
01291   */
01292 #endif /* ADC_SMPR1_SMPPLUS */
01293
01294 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
01295   * @{
01296   */
01297 #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)     /*!< ADC group regular behavior in case of overrun:
01298                                                                    data preserved */
01299 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)  /*!< ADC group regular behavior in case of overrun:
01300                                                                    data overwritten */
01301 /**
01302   * @}
01303   */
01304
01305 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
01306   * @{
01307   */
01308 #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                 /*!< ADC group regular sequencer disable
01309                                            (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
01310 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_SQR1_L_0)                 /*!< ADC group regular sequencer enable
01311                                            with 2 ranks in the sequence */
01312 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_SQR1_L_1)                 /*!< ADC group regular sequencer enable
01313                                            with 3 ranks in the sequence */
01314 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_SQR1_L_1 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
01315                                            with 4 ranks in the sequence */
01316 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_SQR1_L_2)                 /*!< ADC group regular sequencer enable
01317                                            with 5 ranks in the sequence */
01318 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
01319                                            with 6 ranks in the sequence */
01320 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
01321                                            with 7 ranks in the sequence */
01322 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
01323                                             | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
01324                                            with 8 ranks in the sequence */
01325 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3)                 /*!< ADC group regular sequencer enable
01326                                            with 9 ranks in the sequence */
01327 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
01328                                            with 10 ranks in the sequence */
01329 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)  /*!< ADC group regular sequencer enable
01330                                            with 11 ranks in the sequence */
01331 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
01332                                             | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
01333                                            with 12 ranks in the sequence */
01334 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)  /*!< ADC group regular sequencer enable
01335                                            with 13 ranks in the sequence */
01336 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
01337                                             | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
01338                                            with 14 ranks in the sequence */
01339 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
01340                                             | ADC_SQR1_L_1)                /*!< ADC group regular sequencerenable
01341                                            with 15 ranks in the sequence */
01342 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
01343                                             | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
01344                                                                               with 16 ranks in the sequence */
01345 /**
01346   * @}
01347   */
01348
01349 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
01350   * @{
01351   */
01352 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                          /*!< ADC group regular sequencer
01353                                            discontinuous mode disable */
01354 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
01355                                            discontinuous mode enable with sequence interruption every rank */
01356 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
01357                                            discontinuous mode enabled with sequence interruption every 2 ranks */
01358 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
01359                                            discontinuous mode enable with sequence interruption every 3 ranks */
01360 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
01361                                             | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
01362                                            discontinuous mode enable with sequence interruption every 4 ranks */
01363 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)   /*!< ADC group regular sequencer
01364                                            discontinuous mode enable with sequence interruption every 5 ranks */
01365 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
01366                                             | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
01367                                            discontinuous mode enable with sequence interruption every 6 ranks */
01368 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
01369                                             | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
01370                                            discontinuous mode enable with sequence interruption every 7 ranks */
01371 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
01372                                             | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
01373                                            discontinuous mode enable with sequence interruption every 8 ranks */
01374 /**
01375   * @}
01376   */
01377
01378 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
01379   * @{
01380   */
01381 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group
01382                                            regular sequencer rank 1 */
01383 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group
01384                                            regular sequencer rank 2 */
01385 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group
01386                                            regular sequencer rank 3 */
01387 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group
01388                                            regular sequencer rank 4 */
01389 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group
01390                                            regular sequencer rank 5 */
01391 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group
01392                                            regular sequencer rank 6 */
01393 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group
01394                                            regular sequencer rank 7 */
01395 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group
01396                                            regular sequencer rank 8 */
01397 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group
01398                                            regular sequencer rank 9 */
01399 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
01400                                            regular sequencer rank 10 */
01401 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
01402                                            regular sequencer rank 11 */
01403 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
01404                                            regular sequencer rank 12 */
01405 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
01406                                            regular sequencer rank 13 */
01407 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
01408                                            regular sequencer rank 14 */
01409 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
01410                                            regular sequencer rank 15 */
01411 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
01412                                            regular sequencer rank 16 */
01413 /**
01414   * @}
01415   */
01416
01417 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
01418   * @{
01419   */
01420 #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                        /*!< ADC group injected
01421                                            conversion trigger internal: SW start. */
01422 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                          /*!<
01423                                            ADC group injected conversion trigger from external peripheral: TIM1 TRGO.
01424                                            Trigger edge set to rising edge (default setting). */
01425 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01426                                            ADC group injected conversion trigger from external peripheral: TIM1 TRGO2.
01427                                            Trigger edge set to rising edge (default setting). */
01428 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
01429                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01430                                            ADC group injected conversion trigger from external peripheral: TIM1
01431                                            channel 3 event (capture compare: input capture or output capture).
01432                                            Trigger edge set to rising edge (default setting).
01433                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01434                                            instances. Refer to device datasheet for ADCx availaibility */
01435 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01436                                            ADC group injected conversion trigger from external peripheral: TIM1
01437                                            channel 4 event (capture compare: input capture or output capture).
01438                                            Trigger edge set to rising edge (default setting). */
01439 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01440                                            ADC group injected conversion trigger from external peripheral: TIM2 TRGO.
01441                                            Trigger edge set to rising edge (default setting). */
01442 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
01443                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01444                                            ADC group injected conversion trigger from external peripheral: TIM2
01445                                            channel 1 event (capture compare: input capture or output capture).
01446                                            Trigger edge set to rising edge (default setting).
01447                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01448                                            instances */
01449 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
01450                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01451                                            ADC group injected conversion trigger from external peripheral: TIM3 TRGO.
01452                                            Trigger edge set to rising edge (default setting). */
01453 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
01454                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01455                                            ADC group injected conversion trigger from external peripheral: TIM3
01456                                            channel 1 event (capture compare: input capture or output capture).
01457                                            Trigger edge set to rising edge (default setting).
01458                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01459                                            instances */
01460 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
01461                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01462                                            ADC group injected conversion trigger from external peripheral: TIM3
01463                                            channel 3 event (capture compare: input capture or output capture).
01464                                            Trigger edge set to rising edge (default setting).
01465                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01466                                            instances */
01467 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01468                                            ADC group injected conversion trigger from external peripheral: TIM3
01469                                            channel 4 event (capture compare: input capture or output capture).
01470                                            Trigger edge set to rising edge (default setting).
01471                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01472                                            instances */
01473 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
01474                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01475                                            ADC group injected conversion trigger from external peripheral: TIM4 TRGO.
01476                                            Trigger edge set to rising edge (default setting). */
01477 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01478                                            ADC group injected conversion trigger from external peripheral: TIM4
01479                                            channel 3 event (capture compare: input capture or output capture).
01480                                            Trigger edge set to rising edge (default setting).
01481                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01482                                            instances. Refer to device datasheet for ADCx availaibility */
01483 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
01484                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01485                                            ADC group injected conversion trigger from external peripheral: TIM4
01486                                            channel 4 event (capture compare: input capture or output capture).
01487                                            Trigger edge set to rising edge (default setting).
01488                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01489                                            instances. Refer to device datasheet for ADCx availaibility */
01490 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
01491                                            ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01492                                            ADC group injected conversion trigger from external peripheral: TIM6 TRGO.
01493                                            Trigger edge set to rising edge (default setting). */
01494 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01495                                            ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01496                                            ADC group injected conversion trigger from external peripheral: TIM7 TRGO.
01497                                            Trigger edge set to rising edge (default setting). */
01498 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
01499                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01500                                            ADC group injected conversion trigger from external peripheral: TIM8 TRGO.
01501                                            Trigger edge set to rising edge (default setting). */
01502 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
01503                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01504                                            ADC group injected conversion trigger from external peripheral: TIM8 TRGO2.
01505                                            Trigger edge set to rising edge (default setting). */
01506 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
01507                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01508                                            ADC group injected conversion trigger from external peripheral: TIM8
01509                                            channel 2 event (capture compare: input capture or output capture).
01510                                            Trigger edge set to rising edge (default setting).
01511                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01512                                            instances. Refer to device datasheet for ADCx availaibility */
01513 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
01514                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01515                                            ADC group injected conversion trigger from external peripheral: TIM8
01516                                            channel 4 event (capture compare: input capture or output capture).
01517                                            Trigger edge set to rising edge (default setting). */
01518 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
01519                                            ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01520                                            ADC group injected conversion trigger from external peripheral: TIM15 TRGO.
01521                                            Trigger edge set to rising edge (default setting). */
01522 #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01523                                            ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01524                                            ADC group injected conversion trigger from external peripheral: TIM8
01525                                            channel 4 event (capture compare: input capture or output capture).
01526                                            Trigger edge set to rising edge (default setting).
01527                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01528                                            instances */
01529 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
01530                                            ADC group injected conversion trigger from external peripheral: TIM20 TRGO.
01531                                            Trigger edge set to rising edge (default setting).
01532                                            Note: On this STM32 series, TIM20 is not available on all devices. Refer to
01533                                            device datasheet for more details */
01534 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
01535                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01536                                            ADC group injected conversion trigger from external peripheral: TIM20 TRGO2.
01537                                            Trigger edge set to rising edge (default setting).
01538                                            Note: On this STM32 series, TIM20 is not available on all devices. Refer to
01539                                            device datasheet for more details */
01540 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
01541                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01542                                            ADC group injected conversion trigger from external peripheral: TIM20
01543                                            channel 2 event (capture compare: input capture or output capture).
01544                                            Trigger edge set to rising edge (default setting).
01545                                            Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is
01546                                            not available on all devices. Refer to device datasheet for more details */
01547 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
01548                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01549                                            ADC group injected conversion trigger from external peripheral: TIM20
01550                                            channel 4 event (capture compare: input capture or output capture).
01551                                            Trigger edge set to rising edge (default setting).
01552                                            Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is
01553                                            not available on all devices. Refer to device datasheet for more details */
01554 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01555                                            ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01556                                            ADC group injected conversion trigger from external peripheral: HRTIMER
01557                                            ADC trigger 1 event. Trigger edge set to rising edge (default setting).
01558                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01559                                            instances, and HRTIM is not available on all devices. Refer to device
01560                                            datasheet for more details */
01561 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
01562                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01563                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01564                                            trigger 2 event. Trigger edge set to rising edge (default setting).
01565                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01566                                            device datasheet for more details */
01567 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01568                                            ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01569                                            ADC group injected conversion trigger from external peripheral: HRTIMER
01570                                            ADC trigger 3 event. Trigger edge set to rising edge (default setting).
01571                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01572                                            instances, and HRTIM is not available on all devices. Refer to device
01573                                            datasheet for more details */
01574 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
01575                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01576                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01577                                            trigger 4 event. Trigger edge set to rising edge (default setting).
01578                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01579                                            device datasheet for more details */
01580 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
01581                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01582                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01583                                            trigger 5 event. Trigger edge set to rising edge (default setting).
01584                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01585                                            device datasheet for more details */
01586 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
01587                                            ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01588                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01589                                            trigger 6 event. Trigger edge set to rising edge (default setting).
01590                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01591                                            device datasheet for more details */
01592 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
01593                                            ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01594                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01595                                            trigger 7 event. Trigger edge set to rising edge (default setting).
01596                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01597                                            device datasheet for more details */
01598 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01599                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01600                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01601                                            trigger 8 event. Trigger edge set to rising edge (default setting).
01602                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01603                                            device datasheet for more details */
01604 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01605                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01606                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01607                                            trigger 9 event. Trigger edge set to rising edge (default setting).
01608                                            Note: On this STM32 series, HRTIM is not available on all devices. Refer to
01609                                            device datasheet for more details */
01610 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01611                                            ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01612                                            ADC group injected conversion trigger from external peripheral: HRTIMER ADC
01613                                            trigger 10 event. Trigger edge set to rising edge (default setting).
01614                                            Note: On this STM32 series, HRTIM is not available on all devices.Refer to
01615                                            device datasheet for more details */
01616 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
01617                                            ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
01618                                            ADC group injected conversion trigger from external peripheral: external
01619                                            interrupt line 3. Trigger edge set to rising edge (default setting).
01620                                            Note: On this STM32 series, this trigger is available only on ADC3/4/5
01621                                            instances. Refer to device datasheet for ADCx availaibility */
01622 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
01623                                            ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
01624                                            ADC group injected conversion trigger from external peripheral: external
01625                                            interrupt line 15. Trigger edge set to rising edge (default setting).
01626                                            Note: On this STM32 series, this trigger is available only on ADC1/2
01627                                            instances. */
01628 #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
01629                                            ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
01630                                            ADC group injected conversion trigger from external peripheral: LPTIMER OUT
01631                                            event. Trigger edge set to rising edge (default setting). */
01632 /**
01633   * @}
01634   */
01635
01636 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
01637   * @{
01638   */
01639 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
01640                                            trigger polarity set to rising edge */
01641 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion
01642                                            trigger polarity set to falling edge */
01643 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
01644                                            trigger polarity set to both rising and falling edges */
01645 /**
01646   * @}
01647   */
01648
01649 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
01650   * @{
01651   */
01652 #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)     /*!< ADC group injected conversion trigger independent.
01653                                            Setting mandatory if ADC group injected injected trigger source is set to
01654                                            an external trigger. */
01655 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)   /*!< ADC group injected conversion trigger from ADC group
01656                                            regular. Setting compliant only with group injected trigger source set to
01657                                            SW start, without any further action on  ADC group injected conversion start
01658                                            or stop: in this case, ADC group injected is controlled only from ADC group
01659                                            regular. */
01660 /**
01661   * @}
01662   */
01663
01664 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
01665   * @{
01666   */
01667 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)   /* Group injected sequence context queue is enabled
01668                                            and can contain up to 2 contexts. When all contexts have been processed,
01669                                            the queue maintains the last context active perpetually. */
01670 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)   /* Group injected sequence context queue is enabled
01671                                            and can contain up to 2 contexts. When all contexts have been processed,
01672                                            the queue is empty and injected group triggers are disabled. */
01673 #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
01674                                            only 1 sequence can be configured and is active perpetually. */
01675 /**
01676   * @}
01677   */
01678
01679 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
01680   * @{
01681   */
01682 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable
01683                                            (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
01684 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
01685                                            with 2 ranks in the sequence */
01686 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable
01687                                            with 3 ranks in the sequence */
01688 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
01689                                            with 4 ranks in the sequence */
01690 /**
01691   * @}
01692   */
01693
01694 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
01695   * @{
01696   */
01697 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)     /*!< ADC group injected sequencer discontinuous mode
01698                                            disable */
01699 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
01700                                            enable with sequence interruption every rank */
01701 /**
01702   * @}
01703   */
01704
01705 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
01706   * @{
01707   */
01708 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET \
01709                                             | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
01710 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET \
01711                                             | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
01712 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET \
01713                                             | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
01714 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET \
01715                                             | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
01716 /**
01717   * @}
01718   */
01719
01720 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
01721   * @{
01722   */
01723 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)       /*!< Sampling time 2.5 ADC clock cycles */
01724 #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (ADC_SMPR2_SMP10_0)  /*!< Sampling time 6.5 ADC clock cycles */
01725 #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR2_SMP10_1)  /*!< Sampling time 12.5 ADC clock cycles */
01726 #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (ADC_SMPR2_SMP10_1 \
01727                                             | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
01728 #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2)  /*!< Sampling time 47.5 ADC clock cycles */
01729 #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2 \
01730                                             | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
01731 #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 \
01732                                             | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
01733 #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 \
01734                                             | ADC_SMPR2_SMP10_1 \
01735                                             | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
01736 /**
01737   * @}
01738   */
01739
01740 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
01741   * @{
01742   */
01743 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending
01744                                            set to single ended (literal also used to set calibration mode) */
01745 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending
01746                                            set to differential (literal also used to set calibration mode) */
01747 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
01748                                            set to both single ended and differential (literal used only to set
01749                                            calibration factors) */
01750 /**
01751   * @}
01752   */
01753
01754 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
01755   * @{
01756   */
01757 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK \
01758                                             | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
01759 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK \
01760                                             | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
01761 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK \
01762                                             | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
01763 /**
01764   * @}
01765   */
01766
01767 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
01768   * @{
01769   */
01770 #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                           /*!< ADC analog watchdog monitoring
01771                                            disabled */
01772 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK \
01773                                             | ADC_CFGR_AWD1EN)                       /*!< ADC analog watchdog monitoring
01774                                            of all channels, converted by group regular only */
01775 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK \
01776                                             | ADC_CFGR_JAWD1EN)                      /*!< ADC analog watchdog monitoring
01777                                            of all channels, converted by group injected only */
01778 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK \
01779                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)    /*!< ADC analog watchdog monitoring
01780                                            of all channels, converted by either group regular or injected */
01781 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
01782                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01783                                            of ADC channel ADCx_IN0, converted by group regular only */
01784 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
01785                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01786                                            of ADC channel ADCx_IN0, converted by group injected only */
01787 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
01788                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01789                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01790                                            of ADC channel ADCx_IN0, converted by either group regular or injected */
01791 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
01792                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01793                                            of ADC channel ADCx_IN1, converted by group regular only */
01794 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
01795                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01796                                            of ADC channel ADCx_IN1, converted by group injected only */
01797 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
01798                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01799                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01800                                            of ADC channel ADCx_IN1, converted by either group regular or injected */
01801 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
01802                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01803                                            of ADC channel ADCx_IN2, converted by group regular only */
01804 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
01805                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01806                                            of ADC channel ADCx_IN2, converted by group injected only */
01807 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
01808                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01809                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01810                                            of ADC channel ADCx_IN2, converted by either group regular or injected */
01811 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
01812                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01813                                            of ADC channel ADCx_IN3, converted by group regular only */
01814 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
01815                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01816                                            of ADC channel ADCx_IN3, converted by group injected only */
01817 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
01818                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01819                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01820                                            of ADC channel ADCx_IN3, converted by either group regular or injected */
01821 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
01822                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01823                                            of ADC channel ADCx_IN4, converted by group regular only */
01824 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
01825                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01826                                            of ADC channel ADCx_IN4, converted by group injected only */
01827 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
01828                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01829                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01830                                            of ADC channel ADCx_IN4, converted by either group regular or injected */
01831 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
01832                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01833                                            of ADC channel ADCx_IN5, converted by group regular only */
01834 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
01835                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01836                                            of ADC channel ADCx_IN5, converted by group injected only */
01837 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
01838                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01839                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01840                                            of ADC channel ADCx_IN5, converted by either group regular or injected */
01841 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
01842                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01843                                            of ADC channel ADCx_IN6, converted by group regular only */
01844 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
01845                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01846                                            of ADC channel ADCx_IN6, converted by group injected only */
01847 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
01848                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01849                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01850                                            of ADC channel ADCx_IN6, converted by either group regular or injected */
01851 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
01852                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01853                                            of ADC channel ADCx_IN7, converted by group regular only */
01854 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
01855                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01856                                            of ADC channel ADCx_IN7, converted by group injected only */
01857 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
01858                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01859                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01860                                            of ADC channel ADCx_IN7, converted by either group regular or injected */
01861 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
01862                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01863                                            of ADC channel ADCx_IN8, converted by group regular only */
01864 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
01865                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01866                                            of ADC channel ADCx_IN8, converted by group injected only */
01867 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
01868                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01869                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01870                                            of ADC channel ADCx_IN8, converted by either group regular or injected */
01871 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
01872                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01873                                            of ADC channel ADCx_IN9, converted by group regular only */
01874 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
01875                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01876                                            of ADC channel ADCx_IN9, converted by group injected only */
01877 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
01878                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01879                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01880                                            of ADC channel ADCx_IN9, converted by either group regular or injected */
01881 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
01882                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01883                                            of ADC channel ADCx_IN10, converted by group regular only */
01884 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
01885                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01886                                            of ADC channel ADCx_IN10, converted by group injected only */
01887 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
01888                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01889                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01890                                            of ADC channel ADCx_IN10, converted by either group regular or injected */
01891 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
01892                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01893                                            of ADC channel ADCx_IN11, converted by group regular only */
01894 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
01895                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01896                                            of ADC channel ADCx_IN11, converted by group injected only */
01897 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
01898                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01899                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01900                                            of ADC channel ADCx_IN11, converted by either group regular or injected */
01901 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
01902                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01903                                            of ADC channel ADCx_IN12, converted by group regular only */
01904 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
01905                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01906                                            of ADC channel ADCx_IN12, converted by group injected only */
01907 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
01908                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01909                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01910                                            of ADC channel ADCx_IN12, converted by either group regular or injected */
01911 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
01912                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01913                                            of ADC channel ADCx_IN13, converted by group regular only */
01914 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
01915                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01916                                            of ADC channel ADCx_IN13, converted by group injected only */
01917 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
01918                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01919                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01920                                            of ADC channel ADCx_IN13, converted by either group regular or injected */
01921 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
01922                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01923                                            of ADC channel ADCx_IN14, converted by group regular only */
01924 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
01925                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01926                                            of ADC channel ADCx_IN14, converted by group only */
01927 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
01928                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01929                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01930                                            of ADC channel ADCx_IN14, converted by either group regular or injected */
01931 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
01932                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01933                                            monitoring of ADC channel ADCx_IN15, converted by group regular only */
01934 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
01935                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01936                                            of ADC channel ADCx_IN15, converted by group injected only */
01937 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
01938                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01939                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01940                                            of ADC channel ADCx_IN15, converted by either group
01941                                            regular or injected */
01942 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
01943                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01944                                            of ADC channel ADCx_IN16, converted by group regular only */
01945 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
01946                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01947                                            of ADC channel ADCx_IN16, converted by group injected only */
01948 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
01949                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01950                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01951                                            of ADC channel ADCx_IN16, converted by either group regular or injected */
01952 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
01953                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01954                                            of ADC channel ADCx_IN17, converted by group regular only */
01955 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
01956                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01957                                            of ADC channel ADCx_IN17, converted by group injected only */
01958 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
01959                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01960                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01961                                            of ADC channel ADCx_IN17, converted by either group regular or injected */
01962 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
01963                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01964                                            of ADC channel ADCx_IN18, converted by group regular only */
01965 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
01966                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01967                                            of ADC channel ADCx_IN18, converted by group injected only */
01968 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
01969                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01970                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01971                                            of ADC channel ADCx_IN18, converted by either group regular or injected */
01972 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
01973                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01974                                            of ADC internal channel connected to VrefInt: Internal
01975                                            voltage reference, converted by group regular only */
01976 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
01977                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
01978                                            of ADC internal channel connected to VrefInt: Internal
01979                                            voltage reference, converted by group injected only */
01980 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
01981                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01982                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01983                                            of ADC internal channel connected to VrefInt: Internal
01984                                            voltage reference, converted by either group regular or injected */
01985 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
01986                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
01987                                            of ADC1 internal channel connected to internal temperature sensor,
01988                                            converted by group regular only */
01989 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
01990                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    /*!< ADC analog
01991                                            of ADC1 internal channel connected to internal temperature sensor,
01992                                            converted by group injected only */
01993 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
01994                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
01995                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
01996                                            of ADC1 internal channel connected to internal temperature sensor,
01997                                            converted by either group regular or injected */
01998 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
01999                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02000                                            of ADC5 internal channel connected to internal temperature sensor,
02001                                            converted by group regular only */
02002 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
02003                                             | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog
02004                                            of ADC5 internal channel connected to internal temperature sensor,
02005                                            converted by group injected only */
02006 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
02007                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02008                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02009                                            of ADC5 internal channel connected to internal temperature sensor,
02010                                            converted by either group regular or injected */
02011 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
02012                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02013                                            of ADC internal channel connected to Vbat/3: Vbat
02014                                            voltage through a divider ladder of factor 1/3 to have channel voltage always below
02015                                            Vdda, converted by group regular only */
02016 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
02017                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02018                                            of ADC internal channel connected to Vbat/3: Vbat
02019                                            voltage through a divider ladder of factor 1/3 to have channel voltage always below
02020                                            Vdda, converted by group injected only */
02021 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
02022                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02023                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02024                                            of ADC internal channel connected to Vbat/3: Vbat
02025                                            voltage through a divider ladder of factor 1/3 to have channel voltage always below
02026                                            Vdda */
02027 #define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
02028                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02029                                            of ADC internal channel connected to OPAMP1 output,
02030                                            channel specific to ADC1, converted by group regular only */
02031 #define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
02032                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02033                                            of ADC internal channel connected to OPAMP1 output,
02034                                            channel specific to ADC1, converted by group injected only */
02035 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
02036                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02037                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02038                                            of ADC internal channel connected to OPAMP1 output,
02039                                            channel specific to ADC1, converted by either group regular or injected */
02040 #define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
02041                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02042                                            channel specific to ADC2, converted by group regular only */
02043 #define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
02044                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02045                                            of ADC internal channel connected to OPAMP2 output,
02046                                            channel specific to ADC2, converted by group injected only */
02047 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
02048                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02049                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02050                                            of ADC internal channel connected to OPAMP2 output,
02051                                            channel specific to ADC2, converted by either group regular or injected */
02052 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
02053                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02054                                            of ADC internal channel connected to OPAMP3 output,
02055                                            channel specific to ADC2, converted by group regular only */
02056 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
02057                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02058                                            of ADC internal channel connected to OPAMP3 output,
02059                                            channel specific to ADC2, converted by group injected only */
02060 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
02061                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02062                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02063                                            of ADC internal channel connected to OPAMP3 output,
02064                                            channel specific to ADC2, converted by either group regular or injected */
02065 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
02066                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02067                                            of ADC internal channel connected to OPAMP3 output,
02068                                            channel specific to ADC3, converted by group regular only */
02069 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
02070                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02071                                            of ADC internal channel connected to OPAMP3 output,
02072                                            channel specific to ADC3, converted by group injected only */
02073 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
02074                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02075                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02076                                            of ADC internal channel connected to OPAMP3 output,
02077                                            channel specific to ADC3, converted by either group regular or injected */
02078 #define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
02079                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02080                                            of ADC internal channel connected to OPAMP4 output,
02081                                            channel specific to ADC5, converted by group regular only */
02082 #define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
02083                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02084                                            of ADC internal channel connected to OPAMP4 output,
02085                                            channel specific to ADC5, converted by group injected only */
02086 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
02087                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02088                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02089                                            of ADC internal channel connected to OPAMP4 output,
02090                                            channel specific to ADC5, converted by either group regular or injected */
02091 #define LL_ADC_AWD_CH_VOPAMP5_REG          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
02092                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02093                                            of ADC internal channel connected to OPAMP5 output,
02094                                            channel specific to ADC5, converted by group regular only */
02095 #define LL_ADC_AWD_CH_VOPAMP5_INJ          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
02096                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02097                                            of ADC internal channel connected to OPAMP5 output,
02098                                            channel specific to ADC5, converted by group injected only */
02099 #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
02100                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02101                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02102                                            of ADC internal channel connected to OPAMP5 output,
02103                                            channel specific to ADC5, converted by either group regular or injected */
02104 #define LL_ADC_AWD_CH_VOPAMP6_REG          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
02105                                             | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
02106                                            of ADC internal channel connected to OPAMP6 output,
02107                                            channel specific to ADC4, converted by group regular only */
02108 #define LL_ADC_AWD_CH_VOPAMP6_INJ          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
02109                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
02110                                            of ADC internal channel connected to OPAMP6 output,
02111                                            channel specific to ADC4, converted by group injected only */
02112 #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
02113                                             | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
02114                                             | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
02115                                            of ADC internal channel connected to OPAMP6 output,
02116                                            channel specific to ADC4, converted by either group regular or injected */
02117 /**
02118   * @}
02119   */
02120
02121 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
02122   * @{
02123   */
02124 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1)      /*!< ADC analog watchdog threshold high */
02125 #define LL_ADC_AWD_THRESHOLD_LOW           (ADC_TR1_LT1)      /*!< ADC analog watchdog threshold low */
02126 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 \
02127                                             | ADC_TR1_LT1)     /*!< ADC analog watchdog both thresholds high and low
02128                                            concatenated into the same data */
02129 /**
02130   * @}
02131   */
02132
02133 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
02134   * @{
02135   */
02136 #define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                          /*!< ADC analog watchdog no filtering,
02137                                            one out-of-window sample is needed to raise flag or interrupt */
02138 #define LL_ADC_AWD_FILTERING_2SAMPLES      (ADC_TR1_AWDFILT_0)                     /*!< ADC analog watchdog 2
02139                                            out-of-window samples are needed to raise flag or interrupt */
02140 #define LL_ADC_AWD_FILTERING_3SAMPLES      (ADC_TR1_AWDFILT_1)                     /*!< ADC analog watchdog 3
02141                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02142 #define LL_ADC_AWD_FILTERING_4SAMPLES      (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4
02143                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02144 #define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_TR1_AWDFILT_2)                     /*!< ADC analog watchdog 5
02145                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02146 #define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6
02147                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02148 #define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7
02149                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02150 #define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
02151                                             | ADC_TR1_AWDFILT_0)                    /*!< ADC analog watchdog 8
02152                                            consecutives out-of-window samples are needed to raise flag or interrupt */
02153 /**
02154   * @}
02155   */
02156
02157 /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
02158   * @{
02159   */
02160 #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                      /*!< ADC oversampling disabled. */
02161 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (ADC_CFGR2_ROVSE)                   /*!< ADC oversampling on conversions of
02162                                            ADC group regular. If group injected interrupts group regular:
02163                                            when ADC group injected is triggered, the oversampling on ADC group regular
02164                                            is temporary stopped and continued afterwards. */
02165 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
02166                                            ADC group regular. If group injected interrupts group regular:
02167                                            when ADC group injected is triggered, the oversampling on ADC group regular
02168                                            is resumed from start (oversampler buffer reset). */
02169 #define LL_ADC_OVS_GRP_INJECTED            (ADC_CFGR2_JOVSE)                   /*!< ADC oversampling on conversions of
02170                                            ADC group injected. */
02171 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
02172                                            both ADC groups regular and injected. If group injected interrupting group
02173                                            regular: when ADC group injected is triggered, the oversampling on ADC group
02174                                            regular is resumed from start (oversampler buffer reset). */
02175 /**
02176   * @}
02177   */
02178
02179 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
02180   * @{
02181   */
02182 #define LL_ADC_OVS_REG_CONT                (0x00000000UL)     /*!< ADC oversampling discontinuous mode: continuous mode
02183 (all conversions of oversampling ratio are done from 1 trigger) */
02184 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)  /*!< ADC oversampling discontinuous mode: discontinuous
02185                                            mode (each conversion of oversampling ratio needs a trigger) */
02186 /**
02187   * @}
02188   */
02189
02190 /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
02191   * @{
02192   */
02193 #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                        /*!< ADC oversampling ratio of 2
02194                                            (sum of conversions data computed to result as oversampling conversion data
02195                                            (before potential shift) */
02196 #define LL_ADC_OVS_RATIO_4                 (ADC_CFGR2_OVSR_0)                    /*!< ADC oversampling ratio of 4
02197                                            (sum of conversions data computed to result as oversampling conversion data
02198                                            (before potential shift) */
02199 #define LL_ADC_OVS_RATIO_8                 (ADC_CFGR2_OVSR_1)                    /*!< ADC oversampling ratio of 8
02200                                            (sum of conversions data computed to result as oversampling conversion data
02201                                            (before potential shift) */
02202 #define LL_ADC_OVS_RATIO_16                (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
02203                                            (sum of conversions data computed to result as oversampling conversion data
02204                                            (before potential shift) */
02205 #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2)                    /*!< ADC oversampling ratio of 32
02206                                            (sum of conversions data computed to result as oversampling conversion data
02207                                            (before potential shift) */
02208 #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
02209                                            (sum of conversions data computed to result as oversampling conversion data
02210                                            (before potential shift) */
02211 #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
02212                                            (sum of conversions data computed to result as oversampling conversion data
02213                                            (before potential shift) */
02214 #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
02215                                             | ADC_CFGR2_OVSR_0)                   /*!< ADC oversampling ratio of 256
02216                                            (sum of conversions data computed to result as oversampling conversion data
02217                                            (before potential shift) */
02218 /**
02219   * @}
02220   */
02221
02222 /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data right shift
02223   * @{
02224   */
02225 #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                        /*!< ADC oversampling no shift
02226                                            (sum of the ADC conversions data is not divided to result as oversampling
02227                                            conversion data) */
02228 #define LL_ADC_OVS_SHIFT_RIGHT_1           (ADC_CFGR2_OVSS_0)                    /*!< ADC oversampling right shift of 1
02229                                            (sum of the ADC conversions data (after OVS ratio) is divided by 2
02230                                            to result as oversampling conversion data) */
02231 #define LL_ADC_OVS_SHIFT_RIGHT_2           (ADC_CFGR2_OVSS_1)                    /*!< ADC oversampling right shift of 2
02232                                            (sum of the ADC conversions data (after OVS ratio) is divided by 4
02233                                            to result as oversampling conversion data) */
02234 #define LL_ADC_OVS_SHIFT_RIGHT_3           (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
02235                                            (sum of the ADC conversions data (after OVS ratio) is divided by 8
02236                                            to result as oversampling conversion data) */
02237 #define LL_ADC_OVS_SHIFT_RIGHT_4           (ADC_CFGR2_OVSS_2)                    /*!< ADC oversampling right shift of 4
02238                                            (sum of the ADC conversions data (after OVS ratio) is divided by 16
02239                                            to result as oversampling conversion data) */
02240 #define LL_ADC_OVS_SHIFT_RIGHT_5           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
02241                                            (sum of the ADC conversions data (after OVS ratio) is divided by 32
02242                                            to result as oversampling conversion data) */
02243 #define LL_ADC_OVS_SHIFT_RIGHT_6           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
02244                                            (sum of the ADC conversions data (after OVS ratio) is divided by 64
02245                                            to result as oversampling conversion data) */
02246 #define LL_ADC_OVS_SHIFT_RIGHT_7           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
02247                                             | ADC_CFGR2_OVSS_0)                   /*!< ADC oversampling right shift of 7
02248                                            (sum of the ADC conversions data (after OVS ratio) is divided by 128
02249                                            to result as oversampling conversion data) */
02250 #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3)                    /*!< ADC oversampling right shift of 8
02251                                            (sum of the ADC conversions data (after OVS ratio) is divided by 256
02252                                            to result as oversampling conversion data) */
02253 /**
02254   * @}
02255   */
02256
02257 #if defined(ADC_MULTIMODE_SUPPORT)
02258 /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
02259   * @{
02260   */
02261 #define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                    /*!< ADC dual mode disabled (ADC
02262                                            independent mode) */
02263 #define LL_ADC_MULTI_DUAL_REG_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
02264                                            simultaneous */
02265 #define LL_ADC_MULTI_DUAL_REG_INTERL       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
02266                                             | ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
02267                                            regular interleaved */
02268 #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
02269                                            simultaneous */
02270 #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
02271                                            alternate trigger. Works only with external triggers (not SW start) */
02272 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
02273                                            regular simultaneous + group injected simultaneous */
02274 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (ADC_CCR_DUAL_1)                  /*!< ADC dual mode enabled: Combined group
02275                                            regular simultaneous + group injected alternate trigger */
02276 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
02277                                            regular interleaved + group injected simultaneous */
02278 /**
02279   * @}
02280   */
02281
02282 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
02283   * @{
02284   */
02285 #define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                    /*!< ADC multimode group regular
02286                                              conversions are transferred by DMA: each ADC uses its own DMA channel,
02287                                              with its individual DMA transfer settings */
02288 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1)                  /*!< ADC multimode group regular
02289                                              conversions are transferred by DMA, one DMA channel for both ADC(DMA of
02290                                              ADC master), in limited mode (one shot mode): DMA transfer requests
02291                                              are stopped when number of DMA data transfers (number of ADC conversions)
02292                                              is reached. This ADC mode is intended to be used with DMA mode
02293                                              non-circular. Setting for ADC resolution of 12 and 10 bits */
02294 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
02295                                              conversions are transferred by DMA, one DMA channel for both ADC(DMA of
02296                                              ADC master), in limited mode (one shot mode): DMA transfer requests
02297                                              are stopped when number of DMA data transfers (number of ADC conversions)
02298                                              is reached. This ADC mode is intended to be used with DMA mode
02299                                              non-circular. Setting for ADC resolution of 8 and 6 bits */
02300 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
02301                                              conversions are transferred by DMA, one DMA channel for both ADC(DMA of
02302                                              ADC master), in unlimited mode: DMA transfer requests are unlimited,
02303                                              whatever number of DMA data transferred (number of ADC conversions).
02304                                              This ADC mode is intended to be used with DMA mode circular.
02305                                              Setting for ADC resolution of 12 and 10 bits */
02306 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
02307                                               | ADC_CCR_MDMA_0)                 /*!< ADC multimode group regular
02308                                              conversions are transferred by DMA, one DMA channel for both ADC (DMA of
02309                                              ADC master), in unlimited mode: DMA transfer requests are unlimited,
02310                                              whatever number of DMA data transferred (number of ADC conversions).
02311                                              This ADC mode is intended to be used with DMA mode circular.
02312                                              Setting for ADC resolution of 8 and 6 bits */
02313 /**
02314   * @}
02315   */
02316
02317 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
02318   * @{
02319   */
02320 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                      /*!< ADC multimode delay between two
02321                                            sampling phases: 1 ADC clock cycle */
02322 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (ADC_CCR_DELAY_0)                   /*!< ADC multimode delay between two
02323                                            sampling phases: 2 ADC clock cycles */
02324 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (ADC_CCR_DELAY_1)                   /*!< ADC multimode delay between two
02325                                            sampling phases: 3 ADC clock cycles */
02326 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
02327                                            sampling phases: 4 ADC clock cycles */
02328 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (ADC_CCR_DELAY_2)                   /*!< ADC multimode delay between two
02329                                            sampling phases: 5 ADC clock cycles */
02330 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
02331                                            sampling phases: 6 ADC clock cycles */
02332 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
02333                                            sampling phases: 7 ADC clock cycles */
02334 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
02335                                             | ADC_CCR_DELAY_0)                  /*!< ADC multimode delay between two
02336                                            sampling phases: 8 ADC clock cycles */
02337 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3)                   /*!< ADC multimode delay between two
02338                                            sampling phases: 9 ADC clock cycles */
02339 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
02340                                            sampling phases: 10 ADC clock cycles */
02341 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
02342                                            sampling phases: 11 ADC clock cycles */
02343 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
02344                                             | ADC_CCR_DELAY_0)                  /*!< ADC multimode delay between two
02345                                            sampling phases: 12 ADC clock cycles */
02346 /**
02347   * @}
02348   */
02349
02350 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
02351   * @{
02352   */
02353 #define LL_ADC_MULTI_MASTER                (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
02354                                            instances: ADC master */
02355 #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
02356                                            instances: ADC slave */
02357 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV \
02358                                             | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
02359                                            instances: both ADC master and ADC slave */
02360 /**
02361   * @}
02362   */
02363
02364 #endif /* ADC_MULTIMODE_SUPPORT */
02365
02366 /** @defgroup ADC_LL_EC_HELPER_MACRO  Definitions of constants used by helper macro
02367   * @{
02368   */
02369 #define LL_ADC_TEMPERATURE_CALC_ERROR      ((int16_t)0x7FFF)  /* Temperature calculation error using helper macro
02370                                                                  @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
02371                                                                  calibration parameters. This value is coded on 16 bits
02372                                                                  (to fit on signed word or double word) and corresponds
02373                                                                  to an inconsistent temperature value. */
02374 /**
02375   * @}
02376   */
02377
02378 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
02379   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
02380   *         not timeout values.
02381   *         For details on delays values, refer to descriptions in source code
02382   *         above each literal definition.
02383   * @{
02384   */
02385
02386 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
02387 /*       not timeout values.                                                  */
02388 /*       Timeout values for ADC operations are dependent to device clock      */
02389 /*       configuration (system clock versus ADC clock),                       */
02390 /*       and therefore must be defined in user application.                   */
02391 /*       Indications for estimation of ADC timeout delays, for this           */
02392 /*       STM32 series:                                                        */
02393 /*       - ADC calibration time: maximum delay is 112/fADC.                   */
02394 /*         (refer to device datasheet, parameter "tCAL")                      */
02395 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
02396 /*         (refer to device datasheet, parameter "tSTAB")                     */
02397 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
02398 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
02399 /*         cycles                                                             */
02400 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
02401 /*         configuration.                                                     */
02402 /*         (refer to device reference manual, section "Timing")               */
02403
02404 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
02405 /* Delay set to maximum value (refer to device datasheet,                     */
02406 /* parameter "tADCVREG_STUP").                                                */
02407 /* Unit: us                                                                   */
02408 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)           /*!< Delay for ADC stabilization time (ADC voltage
02409                                                               regulator start-up time) */
02410
02411 /* Delay for internal voltage reference stabilization time.                   */
02412 /* Delay set to maximum value (refer to device datasheet,                     */
02413 /* parameter "tstart_vrefint").                                               */
02414 /* Unit: us                                                                   */
02415 #define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)        /*!< Delay for internal voltage reference stabilization
02416                                                                    time */
02417
02418 /* Delay for temperature sensor stabilization time.                           */
02419 /* Literal set to maximum value (refer to device datasheet,                   */
02420 /* parameter "tSTART").                                                       */
02421 /* Unit: us                                                                   */
02422 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)        /*!< Delay for temperature sensor stabilization time */
02423 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)        /*!< Delay for temperature sensor buffer stabilization
02424                                                                    time (starting from ADC enable, refer to
02425                                                                    @ref LL_ADC_Enable()) */
02426
02427 /* Delay required between ADC end of calibration and ADC enable.              */
02428 /* Note: On this STM32 series, a minimum number of ADC clock cycles           */
02429 /*       are required between ADC end of calibration and ADC enable.          */
02430 /*       Wait time can be computed in user application by waiting for the     */
02431 /*       equivalent number of CPU cycles, by taking into account              */
02432 /*       ratio of CPU clock versus ADC clock prescalers.                      */
02433 /* Unit: ADC clock cycles.                                                    */
02434 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)        /*!< Delay required between ADC end of calibration
02435                                                                    and ADC enable */
02436
02437 /**
02438   * @}
02439   */
02440
02441 /**
02442   * @}
02443   */
02444
02445
02446 /* Exported macro ------------------------------------------------------------*/
02447 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
02448   * @{
02449   */
02450
02451 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
02452   * @{
02453   */
02454
02455 /**
02456   * @brief  Write a value in ADC register
02457   * @param  __INSTANCE__ ADC Instance
02458   * @param  __REG__ Register to be written
02459   * @param  __VALUE__ Value to be written in the register
02460   * @retval None
02461   */
02462 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
02463
02464 /**
02465   * @brief  Read a value in ADC register
02466   * @param  __INSTANCE__ ADC Instance
02467   * @param  __REG__ Register to be read
02468   * @retval Register value
02469   */
02470 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
02471 /**
02472   * @}
02473   */
02474
02475 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
02476   * @{
02477   */
02478
02479 /**
02480   * @brief  Helper macro to get ADC channel number in decimal format
02481   *         from literals LL_ADC_CHANNEL_x.
02482   * @note   Example:
02483   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
02484   *           will return decimal number "4".
02485   * @note   The input can be a value from functions where a channel
02486   *         number is returned, either defined with number
02487   *         or with bitfield (only one bit must be set).
02488   * @param  __CHANNEL__ This parameter can be one of the following values:
02489   *         @arg @ref LL_ADC_CHANNEL_0
02490   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
02491   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
02492   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
02493   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
02494   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
02495   *         @arg @ref LL_ADC_CHANNEL_6
02496   *         @arg @ref LL_ADC_CHANNEL_7
02497   *         @arg @ref LL_ADC_CHANNEL_8
02498   *         @arg @ref LL_ADC_CHANNEL_9
02499   *         @arg @ref LL_ADC_CHANNEL_10
02500   *         @arg @ref LL_ADC_CHANNEL_11
02501   *         @arg @ref LL_ADC_CHANNEL_12
02502   *         @arg @ref LL_ADC_CHANNEL_13
02503   *         @arg @ref LL_ADC_CHANNEL_14
02504   *         @arg @ref LL_ADC_CHANNEL_15
02505   *         @arg @ref LL_ADC_CHANNEL_16
02506   *         @arg @ref LL_ADC_CHANNEL_17
02507   *         @arg @ref LL_ADC_CHANNEL_18
02508   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02509   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02510   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02511   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02512   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02513   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02514   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02515   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02516   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02517   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02518   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02519   *
02520   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02521   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02522   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02523   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02524   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02525   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02526   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02527   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
02528   *             for more details.
02529   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
02530   *             convert in 12-bit resolution.
02531   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
02532   *             (fADC) to convert in 12-bit resolution.\n
02533   * @retval Value between Min_Data=0 and Max_Data=18
02534   */
02535 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
02536   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
02537    (                                                                                       \
02538        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
02539    )                                                                                       \
02540    :                                                                                       \
02541    (                                                                                       \
02542        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
02543    )                                                                                       \
02544   )
02545
02546 /**
02547   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
02548   *         from number in decimal format.
02549   * @note   Example:
02550   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
02551   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
02552   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
02553   * @retval Returned value can be one of the following values:
02554   *         @arg @ref LL_ADC_CHANNEL_0
02555   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
02556   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
02557   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
02558   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
02559   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
02560   *         @arg @ref LL_ADC_CHANNEL_6
02561   *         @arg @ref LL_ADC_CHANNEL_7
02562   *         @arg @ref LL_ADC_CHANNEL_8
02563   *         @arg @ref LL_ADC_CHANNEL_9
02564   *         @arg @ref LL_ADC_CHANNEL_10
02565   *         @arg @ref LL_ADC_CHANNEL_11
02566   *         @arg @ref LL_ADC_CHANNEL_12
02567   *         @arg @ref LL_ADC_CHANNEL_13
02568   *         @arg @ref LL_ADC_CHANNEL_14
02569   *         @arg @ref LL_ADC_CHANNEL_15
02570   *         @arg @ref LL_ADC_CHANNEL_16
02571   *         @arg @ref LL_ADC_CHANNEL_17
02572   *         @arg @ref LL_ADC_CHANNEL_18
02573   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02574   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02575   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02576   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02577   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02578   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02579   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02580   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02581   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02582   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02583   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02584   *
02585   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02586   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02587   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02588   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02589   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02590   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02591   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02592   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
02593   *             more details.
02594   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
02595   *             convert in 12-bit resolution.
02596   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
02597   *             (fADC) to convert in 12-bit resolution.\n
02598   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
02599   *                      comparison with internal channel parameter to be done
02600   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02601   */
02602 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \
02603   (((__DECIMAL_NB__) <= 9UL) ?                                                                          \
02604    (                                                                                                    \
02605        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
02606        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                              |          \
02607        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
02608    )                                                                                                    \
02609    :                                                                                                    \
02610    (                                                                                                    \
02611        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
02612        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       | \
02613        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
02614    )                                                                                                    \
02615   )
02616
02617 /**
02618   * @brief  Helper macro to determine whether the selected channel
02619   *         corresponds to literal definitions of driver.
02620   * @note   The different literal definitions of ADC channels are:
02621   *         - ADC internal channel:
02622   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
02623   *         - ADC external channel (channel connected to a GPIO pin):
02624   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
02625   * @note   The channel parameter must be a value defined from literal
02626   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
02627   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
02628   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
02629   *         must not be a value from functions where a channel number is
02630   *         returned from ADC registers,
02631   *         because internal and external channels share the same channel
02632   *         number in ADC registers. The differentiation is made only with
02633   *         parameters definitions of driver.
02634   * @param  __CHANNEL__ This parameter can be one of the following values:
02635   *         @arg @ref LL_ADC_CHANNEL_0
02636   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
02637   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
02638   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
02639   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
02640   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
02641   *         @arg @ref LL_ADC_CHANNEL_6
02642   *         @arg @ref LL_ADC_CHANNEL_7
02643   *         @arg @ref LL_ADC_CHANNEL_8
02644   *         @arg @ref LL_ADC_CHANNEL_9
02645   *         @arg @ref LL_ADC_CHANNEL_10
02646   *         @arg @ref LL_ADC_CHANNEL_11
02647   *         @arg @ref LL_ADC_CHANNEL_12
02648   *         @arg @ref LL_ADC_CHANNEL_13
02649   *         @arg @ref LL_ADC_CHANNEL_14
02650   *         @arg @ref LL_ADC_CHANNEL_15
02651   *         @arg @ref LL_ADC_CHANNEL_16
02652   *         @arg @ref LL_ADC_CHANNEL_17
02653   *         @arg @ref LL_ADC_CHANNEL_18
02654   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02655   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02656   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02657   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02658   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02659   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02660   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02661   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02662   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02663   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02664   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02665   *
02666   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02667   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02668   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02669   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02670   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02671   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02672   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02673   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
02674   *             for more details.
02675   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
02676   *             convert in 12-bit resolution.
02677   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
02678   *             (fADC) to convert in 12-bit resolution.\n
02679   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
02680                       connected to a GPIO pin).
02681   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
02682   */
02683 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
02684   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
02685
02686 /**
02687   * @brief  Helper macro to convert a channel defined from parameter
02688   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
02689   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
02690   *         to its equivalent parameter definition of a ADC external channel
02691   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
02692   * @note   The channel parameter can be, additionally to a value
02693   *         defined from parameter definition of a ADC internal channel
02694   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
02695   *         a value defined from parameter definition of
02696   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
02697   *         or a value from functions where a channel number is returned
02698   *         from ADC registers.
02699   * @param  __CHANNEL__ This parameter can be one of the following values:
02700   *         @arg @ref LL_ADC_CHANNEL_0
02701   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
02702   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
02703   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
02704   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
02705   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
02706   *         @arg @ref LL_ADC_CHANNEL_6
02707   *         @arg @ref LL_ADC_CHANNEL_7
02708   *         @arg @ref LL_ADC_CHANNEL_8
02709   *         @arg @ref LL_ADC_CHANNEL_9
02710   *         @arg @ref LL_ADC_CHANNEL_10
02711   *         @arg @ref LL_ADC_CHANNEL_11
02712   *         @arg @ref LL_ADC_CHANNEL_12
02713   *         @arg @ref LL_ADC_CHANNEL_13
02714   *         @arg @ref LL_ADC_CHANNEL_14
02715   *         @arg @ref LL_ADC_CHANNEL_15
02716   *         @arg @ref LL_ADC_CHANNEL_16
02717   *         @arg @ref LL_ADC_CHANNEL_17
02718   *         @arg @ref LL_ADC_CHANNEL_18
02719   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02720   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02721   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02722   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02723   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02724   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02725   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02726   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02727   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02728   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02729   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02730   *
02731   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02732   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02733   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02734   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02735   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02736   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02737   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02738   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
02739   *             for more details.
02740   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
02741   *             convert in 12-bit resolution.
02742   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
02743   *             (fADC) to convert in 12-bit resolution.\n
02744   * @retval Returned value can be one of the following values:
02745   *         @arg @ref LL_ADC_CHANNEL_0
02746   *         @arg @ref LL_ADC_CHANNEL_1
02747   *         @arg @ref LL_ADC_CHANNEL_2
02748   *         @arg @ref LL_ADC_CHANNEL_3
02749   *         @arg @ref LL_ADC_CHANNEL_4
02750   *         @arg @ref LL_ADC_CHANNEL_5
02751   *         @arg @ref LL_ADC_CHANNEL_6
02752   *         @arg @ref LL_ADC_CHANNEL_7
02753   *         @arg @ref LL_ADC_CHANNEL_8
02754   *         @arg @ref LL_ADC_CHANNEL_9
02755   *         @arg @ref LL_ADC_CHANNEL_10
02756   *         @arg @ref LL_ADC_CHANNEL_11
02757   *         @arg @ref LL_ADC_CHANNEL_12
02758   *         @arg @ref LL_ADC_CHANNEL_13
02759   *         @arg @ref LL_ADC_CHANNEL_14
02760   *         @arg @ref LL_ADC_CHANNEL_15
02761   *         @arg @ref LL_ADC_CHANNEL_16
02762   *         @arg @ref LL_ADC_CHANNEL_17
02763   *         @arg @ref LL_ADC_CHANNEL_18
02764   */
02765 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
02766   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
02767
02768 /**
02769   * @brief  Helper macro to determine whether the internal channel
02770   *         selected is available on the ADC instance selected.
02771   * @note   The channel parameter must be a value defined from parameter
02772   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
02773   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
02774   *         must not be a value defined from parameter definition of
02775   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
02776   *         or a value from functions where a channel number is
02777   *         returned from ADC registers,
02778   *         because internal and external channels share the same channel
02779   *         number in ADC registers. The differentiation is made only with
02780   *         parameters definitions of driver.
02781   * @param  __ADC_INSTANCE__ ADC instance
02782   * @param  __CHANNEL__ This parameter can be one of the following values:
02783   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02784   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02785   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02786   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02787   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02788   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02789   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02790   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02791   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02792   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02793   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02794   *
02795   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02796   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02797   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02798   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02799   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02800   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02801   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02802   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
02803   *             for more details.
02804   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
02805   *         Value "1" if the internal channel selected is available on the ADC instance selected.
02806   */
02807 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
02808 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
02809   ((((__ADC_INSTANCE__) == ADC1)                                               \
02810     &&(                                                                        \
02811        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
02812        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
02813        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02814        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02815       )                                                                        \
02816    )                                                                           \
02817    ||                                                                          \
02818    (((__ADC_INSTANCE__) == ADC2)                                               \
02819     &&(                                                                        \
02820        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
02821        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
02822       )                                                                        \
02823    )                                                                           \
02824    ||                                                                          \
02825    (((__ADC_INSTANCE__) == ADC3)                                               \
02826     &&(                                                                        \
02827        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
02828        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02829        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02830       )                                                                        \
02831    )                                                                           \
02832    ||                                                                          \
02833    (((__ADC_INSTANCE__) == ADC4)                                               \
02834     &&(                                                                        \
02835        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
02836        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02837       )                                                                        \
02838    )                                                                           \
02839    ||                                                                          \
02840    (((__ADC_INSTANCE__) == ADC5)                                               \
02841     &&(                                                                        \
02842        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5)         ||                    \
02843        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) ||                    \
02844        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)         ||                    \
02845        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02846        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02847       )                                                                        \
02848    )                                                                           \
02849   )
02850 #elif defined(STM32G471xx)
02851 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
02852   ((((__ADC_INSTANCE__) == ADC1)                                               \
02853     &&(                                                                        \
02854        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
02855        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
02856        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02857        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02858       )                                                                        \
02859    )                                                                           \
02860    ||                                                                          \
02861    (((__ADC_INSTANCE__) == ADC2)                                               \
02862     &&(                                                                        \
02863        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
02864        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
02865       )                                                                        \
02866    )                                                                           \
02867    ||                                                                          \
02868    (((__ADC_INSTANCE__) == ADC3)                                               \
02869     &&(                                                                        \
02870        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
02871        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02872        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02873       )                                                                        \
02874    )                                                                           \
02875   )
02876 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
02877 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
02878   ((((__ADC_INSTANCE__) == ADC1)                                               \
02879     &&(                                                                        \
02880        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
02881        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
02882        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02883        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02884       )                                                                        \
02885    )                                                                           \
02886    ||                                                                          \
02887    (((__ADC_INSTANCE__) == ADC2)                                               \
02888     &&(                                                                        \
02889        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
02890        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
02891       )                                                                        \
02892    )                                                                           \
02893   )
02894 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
02895 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
02896   ((((__ADC_INSTANCE__) == ADC1)                                               \
02897     &&(                                                                        \
02898        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
02899        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
02900        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
02901        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02902       )                                                                        \
02903    )                                                                           \
02904    ||                                                                          \
02905    (((__ADC_INSTANCE__) == ADC2)                                               \
02906     &&(                                                                        \
02907        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
02908        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
02909       )                                                                        \
02910    )                                                                           \
02911    ||                                                                          \
02912    (((__ADC_INSTANCE__) == ADC3)                                               \
02913     &&(                                                                        \
02914        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
02915        ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
02916        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
02917       )                                                                        \
02918    )                                                                           \
02919   )
02920 #endif /* STM32G4xx */
02921
02922 /**
02923   * @brief  Helper macro to define ADC analog watchdog parameter:
02924   *         define a single channel to monitor with analog watchdog
02925   *         from sequencer channel and groups definition.
02926   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
02927   *         Example:
02928   *           LL_ADC_SetAnalogWDMonitChannels(
02929   *             ADC1, LL_ADC_AWD1,
02930   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
02931   * @param  __CHANNEL__ This parameter can be one of the following values:
02932   *         @arg @ref LL_ADC_CHANNEL_0
02933   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
02934   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
02935   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
02936   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
02937   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
02938   *         @arg @ref LL_ADC_CHANNEL_6
02939   *         @arg @ref LL_ADC_CHANNEL_7
02940   *         @arg @ref LL_ADC_CHANNEL_8
02941   *         @arg @ref LL_ADC_CHANNEL_9
02942   *         @arg @ref LL_ADC_CHANNEL_10
02943   *         @arg @ref LL_ADC_CHANNEL_11
02944   *         @arg @ref LL_ADC_CHANNEL_12
02945   *         @arg @ref LL_ADC_CHANNEL_13
02946   *         @arg @ref LL_ADC_CHANNEL_14
02947   *         @arg @ref LL_ADC_CHANNEL_15
02948   *         @arg @ref LL_ADC_CHANNEL_16
02949   *         @arg @ref LL_ADC_CHANNEL_17
02950   *         @arg @ref LL_ADC_CHANNEL_18
02951   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
02952   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
02953   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
02954   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
02955   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
02956   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
02957   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
02958   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
02959   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
02960   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
02961   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
02962   *
02963   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
02964   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
02965   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
02966   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
02967   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
02968   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
02969   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
02970   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
02971   *             more details.
02972   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
02973   *             convert in 12-bit resolution.
02974   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
02975   *             (fADC) to convert in 12-bit resolution.\n
02976   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
02977   *                      comparison with internal channel parameter to be done
02978   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02979   * @param  __GROUP__ This parameter can be one of the following values:
02980   *         @arg @ref LL_ADC_GROUP_REGULAR
02981   *         @arg @ref LL_ADC_GROUP_INJECTED
02982   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
02983   * @retval Returned value can be one of the following values:
02984   *         @arg @ref LL_ADC_AWD_DISABLE
02985   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
02986   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
02987   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
02988   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
02989   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
02990   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
02991   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
02992   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
02993   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
02994   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
02995   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
02996   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
02997   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
02998   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
02999   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
03000   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
03001   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
03002   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
03003   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
03004   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
03005   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
03006   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
03007   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
03008   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
03009   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
03010   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
03011   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
03012   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
03013   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
03014   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
03015   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
03016   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
03017   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
03018   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
03019   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
03020   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
03021   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
03022   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
03023   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
03024   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
03025   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
03026   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
03027   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
03028   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
03029   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
03030   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
03031   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
03032   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
03033   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
03034   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
03035   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
03036   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
03037   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
03038   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
03039   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
03040   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
03041   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
03042   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
03043   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
03044   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
03045   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
03046   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
03047   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
03048   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
03049   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
03050   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
03051   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
03052   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
03053   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
03054   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
03055   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
03056   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
03057   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
03058   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
03059   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
03060   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
03061   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
03062   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
03063   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
03064   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
03065   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
03066   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
03067   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
03068   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
03069   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
03070   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
03071   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
03072   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
03073   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
03074   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
03075   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
03076   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
03077   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
03078   *
03079   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
03080   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
03081   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
03082   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
03083   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
03084   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
03085   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
03086   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
03087   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
03088   *             for more details.
03089   */
03090 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
03091   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
03092    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
03093    :                                                                                                      \
03094    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
03095    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
03096    :                                                                                                      \
03097    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
03098   )
03099
03100 /**
03101   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
03102   *         or low in function of ADC resolution, when ADC resolution is
03103   *         different of 12 bits.
03104   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
03105   *         or @ref LL_ADC_SetAnalogWDThresholds().
03106   *         Example, with a ADC resolution of 8 bits, to set the value of
03107   *         analog watchdog threshold high (on 8 bits):
03108   *           LL_ADC_SetAnalogWDThresholds
03109   *            (< ADCx param >,
03110   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
03111   *            );
03112   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03113   *         @arg @ref LL_ADC_RESOLUTION_12B
03114   *         @arg @ref LL_ADC_RESOLUTION_10B
03115   *         @arg @ref LL_ADC_RESOLUTION_8B
03116   *         @arg @ref LL_ADC_RESOLUTION_6B
03117   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
03118   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03119   */
03120 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
03121   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
03122
03123 /**
03124   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
03125   *         or low in function of ADC resolution, when ADC resolution is
03126   *         different of 12 bits.
03127   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
03128   *         Example, with a ADC resolution of 8 bits, to get the value of
03129   *         analog watchdog threshold high (on 8 bits):
03130   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
03131   *            (LL_ADC_RESOLUTION_8B,
03132   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
03133   *            );
03134   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03135   *         @arg @ref LL_ADC_RESOLUTION_12B
03136   *         @arg @ref LL_ADC_RESOLUTION_10B
03137   *         @arg @ref LL_ADC_RESOLUTION_8B
03138   *         @arg @ref LL_ADC_RESOLUTION_6B
03139   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
03140   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03141   */
03142 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
03143   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
03144
03145 /**
03146   * @brief  Helper macro to get the ADC analog watchdog threshold high
03147   *         or low from raw value containing both thresholds concatenated.
03148   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
03149   *         Example, to get analog watchdog threshold high from the register raw value:
03150   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
03151   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
03152   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
03153   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
03154   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
03155   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03156   */
03157 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)                            \
03158   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
03159    & LL_ADC_AWD_THRESHOLD_LOW)
03160
03161 /**
03162   * @brief  Helper macro to set the ADC calibration value with both single ended
03163   *         and differential modes calibration factors concatenated.
03164   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
03165   *         Example, to set calibration factors single ended to 0x55
03166   *         and differential ended to 0x2A:
03167   *           LL_ADC_SetCalibrationFactor(
03168   *             ADC1,
03169   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
03170   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
03171   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
03172   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
03173   */
03174 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
03175   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
03176
03177 #if defined(ADC_MULTIMODE_SUPPORT)
03178 /**
03179   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
03180   *         or ADC slave from raw value with both ADC conversion data concatenated.
03181   * @note   This macro is intended to be used when multimode transfer by DMA
03182   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
03183   *         In this case the transferred data need to processed with this macro
03184   *         to separate the conversion data of ADC master and ADC slave.
03185   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
03186   *         @arg @ref LL_ADC_MULTI_MASTER
03187   *         @arg @ref LL_ADC_MULTI_SLAVE
03188   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
03189   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03190   */
03191 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
03192   (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
03193 #endif /* ADC_MULTIMODE_SUPPORT */
03194
03195 #if defined(ADC_MULTIMODE_SUPPORT)
03196 /**
03197   * @brief  Helper macro to select, from a ADC instance, to which ADC instance
03198   *         it has a dependence in multimode (ADC master of the corresponding
03199   *         ADC common instance).
03200   * @note   In case of device with multimode available and a mix of
03201   *         ADC instances compliant and not compliant with multimode feature,
03202   *         ADC instances not compliant with multimode feature are
03203   *         considered as master instances (do not depend to
03204   *         any other ADC instance).
03205   * @param  __ADCx__ ADC instance
03206   * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
03207   */
03208 #if defined(ADC5)
03209 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
03210   ( ( ((__ADCx__) == ADC2)                                                     \
03211     )?                                                                         \
03212     (ADC1)                                                                     \
03213     :                                                                          \
03214     ( ( ((__ADCx__) == ADC4)                                                   \
03215       )?                                                                       \
03216       (ADC3)                                                                   \
03217       :                                                                        \
03218       (__ADCx__)                                                               \
03219     )                                                                          \
03220   )
03221 #else
03222 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
03223   ( ( ((__ADCx__) == ADC2)                                                     \
03224     )?                                                                         \
03225     (ADC1)                                                                     \
03226     :                                                                          \
03227     (__ADCx__)                                                                 \
03228   )
03229 #endif /* ADC5 */
03230 #endif /* ADC_MULTIMODE_SUPPORT */
03231
03232 /**
03233   * @brief  Helper macro to select the ADC common instance
03234   *         to which is belonging the selected ADC instance.
03235   * @note   ADC common register instance can be used for:
03236   *         - Set parameters common to several ADC instances
03237   *         - Multimode (for devices with several ADC instances)
03238   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
03239   * @param  __ADCx__ ADC instance
03240   * @retval ADC common register instance
03241   */
03242 #if defined(ADC345_COMMON)
03243 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
03244   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
03245     ? (                                                                        \
03246        (ADC12_COMMON)                                                          \
03247       )                                                                        \
03248       :                                                                        \
03249       (                                                                        \
03250        (ADC345_COMMON)                                                         \
03251       )                                                                        \
03252   )
03253 #else
03254 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)  (ADC12_COMMON)
03255 #endif /* ADC345_COMMON */
03256 /**
03257   * @brief  Helper macro to check if all ADC instances sharing the same
03258   *         ADC common instance are disabled.
03259   * @note   This check is required by functions with setting conditioned to
03260   *         ADC state:
03261   *         All ADC instances of the ADC common group must be disabled.
03262   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
03263   * @note   On devices with only 1 ADC common instance, parameter of this macro
03264   *         is useless and can be ignored (parameter kept for compatibility
03265   *         with devices featuring several ADC common instances).
03266   * @param  __ADCXY_COMMON__ ADC common instance
03267   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03268   * @retval Value "0" if all ADC instances sharing the same ADC common instance
03269   *         are disabled.
03270   *         Value "1" if at least one ADC instance sharing the same ADC common instance
03271   *         is enabled.
03272   */
03273 #if defined(ADC345_COMMON)
03274 #if defined(ADC4) &&  defined(ADC5)
03275 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
03276   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
03277     ? (                                                                        \
03278        (LL_ADC_IsEnabled(ADC1) |                                               \
03279         LL_ADC_IsEnabled(ADC2)  )                                              \
03280       )                                                                        \
03281       :                                                                        \
03282       (                                                                        \
03283        (LL_ADC_IsEnabled(ADC3) |                                               \
03284         LL_ADC_IsEnabled(ADC4) |                                               \
03285         LL_ADC_IsEnabled(ADC5)  )                                              \
03286       )                                                                        \
03287   )
03288 #else
03289 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
03290   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
03291     ? (                                                                        \
03292        (LL_ADC_IsEnabled(ADC1) |                                               \
03293         LL_ADC_IsEnabled(ADC2)  )                                              \
03294       )                                                                        \
03295       :                                                                        \
03296       (LL_ADC_IsEnabled(ADC3))                                                 \
03297   )
03298 #endif /* ADC4 && ADC5 */
03299 #else
03300 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
03301   (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
03302 #endif /* ADC345_COMMON */
03303
03304 /**
03305   * @brief  Helper macro to define the ADC conversion data full-scale digital
03306   *         value corresponding to the selected ADC resolution.
03307   * @note   ADC conversion data full-scale corresponds to voltage range
03308   *         determined by analog voltage references Vref+ and Vref-
03309   *         (refer to reference manual).
03310   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03311   *         @arg @ref LL_ADC_RESOLUTION_12B
03312   *         @arg @ref LL_ADC_RESOLUTION_10B
03313   *         @arg @ref LL_ADC_RESOLUTION_8B
03314   *         @arg @ref LL_ADC_RESOLUTION_6B
03315   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
03316   */
03317 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
03318   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
03319
03320 /**
03321   * @brief  Helper macro to convert the ADC conversion data from
03322   *         a resolution to another resolution.
03323   * @param  __DATA__ ADC conversion data to be converted
03324   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
03325   *         This parameter can be one of the following values:
03326   *         @arg @ref LL_ADC_RESOLUTION_12B
03327   *         @arg @ref LL_ADC_RESOLUTION_10B
03328   *         @arg @ref LL_ADC_RESOLUTION_8B
03329   *         @arg @ref LL_ADC_RESOLUTION_6B
03330   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
03331   *         This parameter can be one of the following values:
03332   *         @arg @ref LL_ADC_RESOLUTION_12B
03333   *         @arg @ref LL_ADC_RESOLUTION_10B
03334   *         @arg @ref LL_ADC_RESOLUTION_8B
03335   *         @arg @ref LL_ADC_RESOLUTION_6B
03336   * @retval ADC conversion data to the requested resolution
03337   */
03338 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
03339                                          __ADC_RESOLUTION_CURRENT__,\
03340                                          __ADC_RESOLUTION_TARGET__)          \
03341 (((__DATA__)                                                                 \
03342   << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
03343  >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
03344 )
03345
03346 /**
03347   * @brief  Helper macro to calculate the voltage (unit: mVolt)
03348   *         corresponding to a ADC conversion data (unit: digital value).
03349   * @note   Analog reference voltage (Vref+) must be either known from
03350   *         user board environment or can be calculated using ADC measurement
03351   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
03352   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
03353   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
03354   *                       (unit: digital value).
03355   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03356   *         @arg @ref LL_ADC_RESOLUTION_12B
03357   *         @arg @ref LL_ADC_RESOLUTION_10B
03358   *         @arg @ref LL_ADC_RESOLUTION_8B
03359   *         @arg @ref LL_ADC_RESOLUTION_6B
03360   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
03361   */
03362 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
03363                                       __ADC_DATA__,\
03364                                       __ADC_RESOLUTION__)                    \
03365 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
03366  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
03367 )
03368
03369 /**
03370   * @brief  Helper macro to calculate the voltage (unit: mVolt)
03371   *         corresponding to a ADC conversion data (unit: digital value) in
03372   *         differential ended mode.
03373   * @note   ADC data from ADC data register is unsigned and centered around
03374   *         middle code in. Converted voltage can be positive or negative
03375   *         depending on differential input voltages.
03376   * @note   Analog reference voltage (Vref+) must be either known from
03377   *         user board environment or can be calculated using ADC measurement
03378   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
03379   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
03380   * @param  __ADC_DATA__ ADC conversion data (unit: digital value).
03381   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03382   *         @arg @ref LL_ADC_RESOLUTION_12B
03383   *         @arg @ref LL_ADC_RESOLUTION_10B
03384   *         @arg @ref LL_ADC_RESOLUTION_8B
03385   *         @arg @ref LL_ADC_RESOLUTION_6B
03386   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
03387   */
03388 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
03389                                            __ADC_DATA__,\
03390                                            __ADC_RESOLUTION__)\
03391 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
03392  / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
03393  - (int32_t)(__VREFANALOG_VOLTAGE__))
03394
03395 /**
03396   * @brief  Helper macro to calculate analog reference voltage (Vref+)
03397   *         (unit: mVolt) from ADC conversion data of internal voltage
03398   *         reference VrefInt.
03399   * @note   Computation is using VrefInt calibration value
03400   *         stored in system memory for each device during production.
03401   * @note   This voltage depends on user board environment: voltage level
03402   *         connected to pin Vref+.
03403   *         On devices with small package, the pin Vref+ is not present
03404   *         and internally bonded to pin Vdda.
03405   * @note   On this STM32 series, calibration data of internal voltage reference
03406   *         VrefInt corresponds to a resolution of 12 bits,
03407   *         this is the recommended ADC resolution to convert voltage of
03408   *         internal voltage reference VrefInt.
03409   *         Otherwise, this macro performs the processing to scale
03410   *         ADC conversion data to 12 bits.
03411   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
03412   *         of internal voltage reference VrefInt (unit: digital value).
03413   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
03414   *         @arg @ref LL_ADC_RESOLUTION_12B
03415   *         @arg @ref LL_ADC_RESOLUTION_10B
03416   *         @arg @ref LL_ADC_RESOLUTION_8B
03417   *         @arg @ref LL_ADC_RESOLUTION_6B
03418   * @retval Analog reference voltage (unit: mV)
03419   */
03420 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
03421                                          __ADC_RESOLUTION__)                 \
03422 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
03423  / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
03424                                     (__ADC_RESOLUTION__),                    \
03425                                     LL_ADC_RESOLUTION_12B)                   \
03426 )
03427
03428 /**
03429   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
03430   *         from ADC conversion data of internal temperature sensor.
03431   * @note   Computation is using temperature sensor calibration values
03432   *         stored in system memory for each device during production.
03433   * @note   Calculation formula:
03434   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
03435   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
03436   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
03437   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
03438   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
03439   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
03440   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
03441   *                            TEMP_DEGC_CAL1 (calibrated in factory)
03442   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
03443   *                            TEMP_DEGC_CAL2 (calibrated in factory)
03444   *         Caution: Calculation relevancy under reserve that calibration
03445   *                  parameters are correct (address and data).
03446   *                  To calculate temperature using temperature sensor
03447   *                  datasheet typical values (generic values less, therefore
03448   *                  less accurate than calibrated values),
03449   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
03450   * @note   As calculation input, the analog reference voltage (Vref+) must be
03451   *         defined as it impacts the ADC LSB equivalent voltage.
03452   * @note   Analog reference voltage (Vref+) must be either known from
03453   *         user board environment or can be calculated using ADC measurement
03454   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
03455   * @note   On this STM32 series, calibration data of temperature sensor
03456   *         corresponds to a resolution of 12 bits,
03457   *         this is the recommended ADC resolution to convert voltage of
03458   *         temperature sensor.
03459   *         Otherwise, this macro performs the processing to scale
03460   *         ADC conversion data to 12 bits.
03461   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
03462   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
03463   *                                 temperature sensor (unit: digital value).
03464   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
03465   *                                 sensor voltage has been measured.
03466   *         This parameter can be one of the following values:
03467   *         @arg @ref LL_ADC_RESOLUTION_12B
03468   *         @arg @ref LL_ADC_RESOLUTION_10B
03469   *         @arg @ref LL_ADC_RESOLUTION_8B
03470   *         @arg @ref LL_ADC_RESOLUTION_6B
03471   * @retval Temperature (unit: degree Celsius)
03472   *         In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
03473   */
03474 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
03475                                   __TEMPSENSOR_ADC_DATA__,\
03476                                   __ADC_RESOLUTION__)\
03477 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ?       \
03478  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
03479                                                    (__ADC_RESOLUTION__),          \
03480                                                    LL_ADC_RESOLUTION_12B)         \
03481                   * (__VREFANALOG_VOLTAGE__))                                     \
03482                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
03483        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
03484     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
03485    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
03486   ) + TEMPSENSOR_CAL1_TEMP                                                        \
03487  )                                                                                \
03488  :                                                                                \
03489  ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR)                                         \
03490 )
03491
03492 /**
03493   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
03494   *         from ADC conversion data of internal temperature sensor.
03495   * @note   Computation is using temperature sensor typical values
03496   *         (refer to device datasheet).
03497   * @note   Calculation formula:
03498   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
03499   *                         / Avg_Slope + CALx_TEMP
03500   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
03501   *                                   (unit: digital value)
03502   *                Avg_Slope        = temperature sensor slope
03503   *                                   (unit: uV/Degree Celsius)
03504   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
03505   *                                   temperature CALx_TEMP (unit: mV)
03506   *         Caution: Calculation relevancy under reserve the temperature sensor
03507   *                  of the current device has characteristics in line with
03508   *                  datasheet typical values.
03509   *                  If temperature sensor calibration values are available on
03510   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
03511   *                  temperature calculation will be more accurate using
03512   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
03513   * @note   As calculation input, the analog reference voltage (Vref+) must be
03514   *         defined as it impacts the ADC LSB equivalent voltage.
03515   * @note   Analog reference voltage (Vref+) must be either known from
03516   *         user board environment or can be calculated using ADC measurement
03517   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
03518   * @note   ADC measurement data must correspond to a resolution of 12 bits
03519   *         (full scale digital value 4095). If not the case, the data must be
03520   *         preliminarily rescaled to an equivalent resolution of 12 bits.
03521   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value
03522   *                                       (unit: uV/DegCelsius).
03523   *                                       On STM32G4, refer to device datasheet parameter "Avg_Slope".
03524   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value
03525   *                                       (at temperature and Vref+ defined in parameters below) (unit: mV).
03526   *                                       On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
03527   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage
03528   *                                       (see parameter above) is corresponding (unit: mV)
03529   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) value (unit: mV)
03530   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
03531   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
03532   *         This parameter can be one of the following values:
03533   *         @arg @ref LL_ADC_RESOLUTION_12B
03534   *         @arg @ref LL_ADC_RESOLUTION_10B
03535   *         @arg @ref LL_ADC_RESOLUTION_8B
03536   *         @arg @ref LL_ADC_RESOLUTION_6B
03537   * @retval Temperature (unit: degree Celsius)
03538   */
03539 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
03540                                              __TEMPSENSOR_TYP_CALX_V__,\
03541                                              __TEMPSENSOR_CALX_TEMP__,\
03542                                              __VREFANALOG_VOLTAGE__,\
03543                                              __TEMPSENSOR_ADC_DATA__,\
03544                                              __ADC_RESOLUTION__)            \
03545 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
03546                / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
03547               * 1000UL)                                                     \
03548     -                                                                       \
03549     (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
03550               * 1000UL)                                                     \
03551    )                                                                        \
03552   ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
03553  ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
03554 )
03555
03556 /**
03557   * @}
03558   */
03559
03560 /**
03561   * @}
03562   */
03563
03564
03565 /* Exported functions --------------------------------------------------------*/
03566 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
03567   * @{
03568   */
03569
03570 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
03571   * @{
03572   */
03573 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
03574 /*       configuration of ADC instance, groups and multimode (if available):  */
03575 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
03576
03577 /**
03578   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
03579   *         ADC register address from ADC instance and a list of ADC registers
03580   *         intended to be used (most commonly) with DMA transfer.
03581   * @note   These ADC registers are data registers:
03582   *         when ADC conversion data is available in ADC data registers,
03583   *         ADC generates a DMA transfer request.
03584   * @note   This macro is intended to be used with LL DMA driver, refer to
03585   *         function "LL_DMA_ConfigAddresses()".
03586   *         Example:
03587   *           LL_DMA_ConfigAddresses(DMA1,
03588   *                                  LL_DMA_CHANNEL_1,
03589   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
03590   *                                  (uint32_t)&< array or variable >,
03591   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
03592   * @note   For devices with several ADC: in multimode, some devices
03593   *         use a different data register outside of ADC instance scope
03594   *         (common data register). This macro manages this register difference,
03595   *         only ADC instance has to be set as parameter.
03596   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
03597   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
03598   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
03599   * @param  ADCx ADC instance
03600   * @param  Register This parameter can be one of the following values:
03601   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
03602   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
03603   *
03604   *         (1) Available on devices with several ADC instances.
03605   * @retval ADC register address
03606   */
03607 #if defined(ADC_MULTIMODE_SUPPORT)
03608 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
03609 {
03610   uint32_t data_reg_addr;
03611
03612   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
03613   {
03614     /* Retrieve address of register DR */
03615     data_reg_addr = (uint32_t) &(ADCx->DR);
03616   }
03617   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
03618   {
03619     /* Retrieve address of register CDR */
03620     data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
03621   }
03622
03623   return data_reg_addr;
03624 }
03625 #else
03626 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
03627 {
03628   /* Prevent unused argument(s) compilation warning */
03629   (void)(Register);
03630
03631   /* Retrieve address of register DR */
03632   return (uint32_t) &(ADCx->DR);
03633 }
03634 #endif /* ADC_MULTIMODE_SUPPORT */
03635
03636 /**
03637   * @}
03638   */
03639
03640 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
03641   *           ADC instances
03642   * @{
03643   */
03644
03645 /**
03646   * @brief  Set parameter common to several ADC: Clock source and prescaler.
03647   * @note   On this STM32 series, if ADC group injected is used, some
03648   *         clock ratio constraints between ADC clock and AHB clock
03649   *         must be respected.
03650   *         Refer to reference manual.
03651   * @note   On this STM32 series, setting of this feature is conditioned to
03652   *         ADC state:
03653   *         All ADC instances of the ADC common group must be disabled.
03654   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
03655   *         ADC instance or by using helper macro helper macro
03656   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
03657   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
03658   *         CCR      PRESC          LL_ADC_SetCommonClock
03659   * @param  ADCxy_COMMON ADC common instance
03660   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03661   * @param  CommonClock This parameter can be one of the following values:
03662   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
03663   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
03664   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
03665   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
03666   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
03667   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
03668   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
03669   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
03670   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
03671   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
03672   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
03673   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
03674   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
03675   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
03676   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
03677   * @retval None
03678   */
03679 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
03680 {
03681   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
03682 }
03683
03684 /**
03685   * @brief  Get parameter common to several ADC: Clock source and prescaler.
03686   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
03687   *         CCR      PRESC          LL_ADC_GetCommonClock
03688   * @param  ADCxy_COMMON ADC common instance
03689   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03690   * @retval Returned value can be one of the following values:
03691   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
03692   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
03693   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
03694   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
03695   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
03696   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
03697   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
03698   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
03699   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
03700   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
03701   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
03702   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
03703   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
03704   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
03705   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
03706   */
03707 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
03708 {
03709   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
03710 }
03711
03712 /**
03713   * @brief  Set parameter common to several ADC: measurement path to
03714   *         internal channels (VrefInt, temperature sensor, ...).
03715   *         Configure all paths (overwrite current configuration).
03716   * @note   One or several values can be selected.
03717   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
03718   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
03719   *         The values not selected are removed from configuration.
03720   * @note   Stabilization time of measurement path to internal channel:
03721   *         After enabling internal paths, before starting ADC conversion,
03722   *         a delay is required for internal voltage reference and
03723   *         temperature sensor stabilization time.
03724   *         Refer to device datasheet.
03725   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
03726   *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
03727   *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
03728   * @note   ADC internal channel sampling time constraint:
03729   *         For ADC conversion of internal channels,
03730   *         a sampling time minimum value is required.
03731   *         Refer to device datasheet.
03732   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
03733   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalCh\n
03734   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalCh
03735   * @param  ADCxy_COMMON ADC common instance
03736   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03737   * @param  PathInternal This parameter can be a combination of the following values:
03738   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
03739   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
03740   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
03741   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
03742   * @retval None
03743   */
03744 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
03745 {
03746   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
03747 }
03748
03749 /**
03750   * @brief  Set parameter common to several ADC: measurement path to
03751   *         internal channels (VrefInt, temperature sensor, ...).
03752   *         Add paths to the current configuration.
03753   * @note   One or several values can be selected.
03754   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
03755   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
03756   * @note   Stabilization time of measurement path to internal channel:
03757   *         After enabling internal paths, before starting ADC conversion,
03758   *         a delay is required for internal voltage reference and
03759   *         temperature sensor stabilization time.
03760   *         Refer to device datasheet.
03761   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
03762   *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
03763   *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
03764   * @note   ADC internal channel sampling time constraint:
03765   *         For ADC conversion of internal channels,
03766   *         a sampling time minimum value is required.
03767   *         Refer to device datasheet.
03768   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
03769   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChAdd\n
03770   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChAdd
03771   * @param  ADCxy_COMMON ADC common instance
03772   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03773   * @param  PathInternal This parameter can be a combination of the following values:
03774   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
03775   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
03776   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
03777   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
03778   * @retval None
03779   */
03780 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
03781 {
03782   SET_BIT(ADCxy_COMMON->CCR, PathInternal);
03783 }
03784
03785 /**
03786   * @brief  Set parameter common to several ADC: measurement path to
03787   *         internal channels (VrefInt, temperature sensor, ...).
03788   *         Remove paths to the current configuration.
03789   * @note   One or several values can be selected.
03790   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
03791   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
03792   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
03793   *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChRem\n
03794   *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChRem
03795   * @param  ADCxy_COMMON ADC common instance
03796   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03797   * @param  PathInternal This parameter can be a combination of the following values:
03798   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
03799   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
03800   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
03801   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
03802   * @retval None
03803   */
03804 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
03805 {
03806   CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
03807 }
03808
03809 /**
03810   * @brief  Get parameter common to several ADC: measurement path to internal
03811   *         channels (VrefInt, temperature sensor, ...).
03812   * @note   One or several values can be selected.
03813   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
03814   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
03815   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
03816   *         CCR      VSENSESEL      LL_ADC_GetCommonPathInternalCh\n
03817   *         CCR      VBATSEL        LL_ADC_GetCommonPathInternalCh
03818   * @param  ADCxy_COMMON ADC common instance
03819   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03820   * @retval Returned value can be a combination of the following values:
03821   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
03822   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
03823   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
03824   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
03825   */
03826 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
03827 {
03828   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
03829 }
03830
03831 /**
03832   * @}
03833   */
03834
03835 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
03836   * @{
03837   */
03838
03839 /**
03840   * @brief  Set ADC calibration factor in the mode single-ended
03841   *         or differential (for devices with differential mode available).
03842   * @note   This function is intended to set calibration parameters
03843   *         without having to perform a new calibration using
03844   *         @ref LL_ADC_StartCalibration().
03845   * @note   For devices with differential mode available:
03846   *         Calibration of offset is specific to each of
03847   *         single-ended and differential modes
03848   *         (calibration factor must be specified for each of these
03849   *         differential modes, if used afterwards and if the application
03850   *         requires their calibration).
03851   * @note   In case of setting calibration factors of both modes single ended
03852   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
03853   *         both calibration factors must be concatenated.
03854   *         To perform this processing, use helper macro
03855   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
03856   * @note   On this STM32 series, setting of this feature is conditioned to
03857   *         ADC state:
03858   *         ADC must be enabled, without calibration on going, without conversion
03859   *         on going on group regular.
03860   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
03861   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
03862   * @param  ADCx ADC instance
03863   * @param  SingleDiff This parameter can be one of the following values:
03864   *         @arg @ref LL_ADC_SINGLE_ENDED
03865   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
03866   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
03867   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
03868   * @retval None
03869   */
03870 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
03871 {
03872   MODIFY_REG(ADCx->CALFACT,
03873              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
03874              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
03875                                     >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
03876                                    & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
03877 }
03878
03879 /**
03880   * @brief  Get ADC calibration factor in the mode single-ended
03881   *         or differential (for devices with differential mode available).
03882   * @note   Calibration factors are set by hardware after performing
03883   *         a calibration run using function @ref LL_ADC_StartCalibration().
03884   * @note   For devices with differential mode available:
03885   *         Calibration of offset is specific to each of
03886   *         single-ended and differential modes
03887   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
03888   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
03889   * @param  ADCx ADC instance
03890   * @param  SingleDiff This parameter can be one of the following values:
03891   *         @arg @ref LL_ADC_SINGLE_ENDED
03892   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
03893   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
03894   */
03895 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
03896 {
03897   /* Retrieve bits with position in register depending on parameter           */
03898   /* "SingleDiff".                                                            */
03899   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
03900   /* containing other bits reserved for other purpose.                        */
03901   return (uint32_t)(READ_BIT(ADCx->CALFACT,
03902                              (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
03903                     >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
03904                         ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
03905 }
03906
03907 /**
03908   * @brief  Set ADC resolution.
03909   *         Refer to reference manual for alignments formats
03910   *         dependencies to ADC resolutions.
03911   * @note   On this STM32 series, setting of this feature is conditioned to
03912   *         ADC state:
03913   *         ADC must be disabled or enabled without conversion on going
03914   *         on either groups regular or injected.
03915   * @rmtoll CFGR     RES            LL_ADC_SetResolution
03916   * @param  ADCx ADC instance
03917   * @param  Resolution This parameter can be one of the following values:
03918   *         @arg @ref LL_ADC_RESOLUTION_12B
03919   *         @arg @ref LL_ADC_RESOLUTION_10B
03920   *         @arg @ref LL_ADC_RESOLUTION_8B
03921   *         @arg @ref LL_ADC_RESOLUTION_6B
03922   * @retval None
03923   */
03924 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
03925 {
03926   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
03927 }
03928
03929 /**
03930   * @brief  Get ADC resolution.
03931   *         Refer to reference manual for alignments formats
03932   *         dependencies to ADC resolutions.
03933   * @rmtoll CFGR     RES            LL_ADC_GetResolution
03934   * @param  ADCx ADC instance
03935   * @retval Returned value can be one of the following values:
03936   *         @arg @ref LL_ADC_RESOLUTION_12B
03937   *         @arg @ref LL_ADC_RESOLUTION_10B
03938   *         @arg @ref LL_ADC_RESOLUTION_8B
03939   *         @arg @ref LL_ADC_RESOLUTION_6B
03940   */
03941 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
03942 {
03943   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
03944 }
03945
03946 /**
03947   * @brief  Set ADC conversion data alignment.
03948   * @note   Refer to reference manual for alignments formats
03949   *         dependencies to ADC resolutions.
03950   * @note   On this STM32 series, setting of this feature is conditioned to
03951   *         ADC state:
03952   *         ADC must be disabled or enabled without conversion on going
03953   *         on either groups regular or injected.
03954   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
03955   * @param  ADCx ADC instance
03956   * @param  DataAlignment This parameter can be one of the following values:
03957   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
03958   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
03959   * @retval None
03960   */
03961 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
03962 {
03963   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
03964 }
03965
03966 /**
03967   * @brief  Get ADC conversion data alignment.
03968   * @note   Refer to reference manual for alignments formats
03969   *         dependencies to ADC resolutions.
03970   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
03971   * @param  ADCx ADC instance
03972   * @retval Returned value can be one of the following values:
03973   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
03974   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
03975   */
03976 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
03977 {
03978   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
03979 }
03980
03981 /**
03982   * @brief  Set ADC low power mode.
03983   * @note   Description of ADC low power modes:
03984   *         - ADC low power mode "auto wait": Dynamic low power mode,
03985   *           ADC conversions occurrences are limited to the minimum necessary
03986   *           in order to reduce power consumption.
03987   *           New ADC conversion starts only when the previous
03988   *           unitary conversion data (for ADC group regular)
03989   *           or previous sequence conversions data (for ADC group injected)
03990   *           has been retrieved by user software.
03991   *           In the meantime, ADC remains idle: does not performs any
03992   *           other conversion.
03993   *           This mode allows to automatically adapt the ADC conversions
03994   *           triggers to the speed of the software that reads the data.
03995   *           Moreover, this avoids risk of overrun for low frequency
03996   *           applications.
03997   *           How to use this low power mode:
03998   *           - It is not recommended to use with interruption or DMA
03999   *             since these modes have to clear immediately the EOC flag
04000   *             (by CPU to free the IRQ pending event or by DMA).
04001   *             Auto wait will work but fort a very short time, discarding
04002   *             its intended benefit (except specific case of high load of CPU
04003   *             or DMA transfers which can justify usage of auto wait).
04004   *           - Do use with polling: 1. Start conversion,
04005   *             2. Later on, when conversion data is needed: poll for end of
04006   *             conversion  to ensure that conversion is completed and
04007   *             retrieve ADC conversion data. This will trig another
04008   *             ADC conversion start.
04009   * @note   With ADC low power mode "auto wait", the ADC conversion data read
04010   *         is corresponding to previous ADC conversion start, independently
04011   *         of delay during which ADC was idle.
04012   *         Therefore, the ADC conversion data may be outdated: does not
04013   *         correspond to the current voltage level on the selected
04014   *         ADC channel.
04015   * @note   On this STM32 series, setting of this feature is conditioned to
04016   *         ADC state:
04017   *         ADC must be disabled or enabled without conversion on going
04018   *         on either groups regular or injected.
04019   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
04020   * @param  ADCx ADC instance
04021   * @param  LowPowerMode This parameter can be one of the following values:
04022   *         @arg @ref LL_ADC_LP_MODE_NONE
04023   *         @arg @ref LL_ADC_LP_AUTOWAIT
04024   * @retval None
04025   */
04026 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
04027 {
04028   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
04029 }
04030
04031 /**
04032   * @brief  Get ADC low power mode:
04033   * @note   Description of ADC low power modes:
04034   *         - ADC low power mode "auto wait": Dynamic low power mode,
04035   *           ADC conversions occurrences are limited to the minimum necessary
04036   *           in order to reduce power consumption.
04037   *           New ADC conversion starts only when the previous
04038   *           unitary conversion data (for ADC group regular)
04039   *           or previous sequence conversions data (for ADC group injected)
04040   *           has been retrieved by user software.
04041   *           In the meantime, ADC remains idle: does not performs any
04042   *           other conversion.
04043   *           This mode allows to automatically adapt the ADC conversions
04044   *           triggers to the speed of the software that reads the data.
04045   *           Moreover, this avoids risk of overrun for low frequency
04046   *           applications.
04047   *           How to use this low power mode:
04048   *           - It is not recommended to use with interruption or DMA
04049   *             since these modes have to clear immediately the EOC flag
04050   *             (by CPU to free the IRQ pending event or by DMA).
04051   *             Auto wait will work but fort a very short time, discarding
04052   *             its intended benefit (except specific case of high load of CPU
04053   *             or DMA transfers which can justify usage of auto wait).
04054   *           - Do use with polling: 1. Start conversion,
04055   *             2. Later on, when conversion data is needed: poll for end of
04056   *             conversion  to ensure that conversion is completed and
04057   *             retrieve ADC conversion data. This will trig another
04058   *             ADC conversion start.
04059   * @note   With ADC low power mode "auto wait", the ADC conversion data read
04060   *         is corresponding to previous ADC conversion start, independently
04061   *         of delay during which ADC was idle.
04062   *         Therefore, the ADC conversion data may be outdated: does not
04063   *         correspond to the current voltage level on the selected
04064   *         ADC channel.
04065   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
04066   * @param  ADCx ADC instance
04067   * @retval Returned value can be one of the following values:
04068   *         @arg @ref LL_ADC_LP_MODE_NONE
04069   *         @arg @ref LL_ADC_LP_AUTOWAIT
04070   */
04071 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
04072 {
04073   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
04074 }
04075
04076 /**
04077   * @brief  Set ADC selected offset instance 1, 2, 3 or 4.
04078   * @note   This function set the 2 items of offset configuration:
04079   *         - ADC channel to which the offset programmed will be applied
04080   *           (independently of channel mapped on ADC group regular
04081   *           or group injected)
04082   *         - Offset level (offset to be subtracted from the raw
04083   *           converted data).
04084   * @note   Caution: Offset format is dependent to ADC resolution:
04085   *         offset has to be left-aligned on bit 11, the LSB (right bits)
04086   *         are set to 0.
04087   * @note   This function enables the offset, by default. It can be forced
04088   *         to disable state using function LL_ADC_SetOffsetState().
04089   * @note   If a channel is mapped on several offsets numbers, only the offset
04090   *         with the lowest value is considered for the subtraction.
04091   * @note   On this STM32 series, setting of this feature is conditioned to
04092   *         ADC state:
04093   *         ADC must be disabled or enabled without conversion on going
04094   *         on either groups regular or injected.
04095   * @note   On STM32G4, some fast channels are available: fast analog inputs
04096   *         coming from GPIO pads (ADC_IN1..5).
04097   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
04098   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
04099   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
04100   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
04101   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
04102   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
04103   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
04104   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
04105   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
04106   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
04107   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
04108   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
04109   * @param  ADCx ADC instance
04110   * @param  Offsety This parameter can be one of the following values:
04111   *         @arg @ref LL_ADC_OFFSET_1
04112   *         @arg @ref LL_ADC_OFFSET_2
04113   *         @arg @ref LL_ADC_OFFSET_3
04114   *         @arg @ref LL_ADC_OFFSET_4
04115   * @param  Channel This parameter can be one of the following values:
04116   *         @arg @ref LL_ADC_CHANNEL_0
04117   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
04118   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
04119   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
04120   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
04121   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
04122   *         @arg @ref LL_ADC_CHANNEL_6
04123   *         @arg @ref LL_ADC_CHANNEL_7
04124   *         @arg @ref LL_ADC_CHANNEL_8
04125   *         @arg @ref LL_ADC_CHANNEL_9
04126   *         @arg @ref LL_ADC_CHANNEL_10
04127   *         @arg @ref LL_ADC_CHANNEL_11
04128   *         @arg @ref LL_ADC_CHANNEL_12
04129   *         @arg @ref LL_ADC_CHANNEL_13
04130   *         @arg @ref LL_ADC_CHANNEL_14
04131   *         @arg @ref LL_ADC_CHANNEL_15
04132   *         @arg @ref LL_ADC_CHANNEL_16
04133   *         @arg @ref LL_ADC_CHANNEL_17
04134   *         @arg @ref LL_ADC_CHANNEL_18
04135   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
04136   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
04137   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
04138   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
04139   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
04140   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
04141   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
04142   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
04143   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
04144   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
04145   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
04146   *
04147   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
04148   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
04149   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
04150   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
04151   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
04152   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
04153   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
04154   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
04155   *             for more details.
04156   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
04157   *             convert in 12-bit resolution.
04158   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
04159   *             (fADC) to convert in 12-bit resolution.\n
04160   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
04161   * @retval None
04162   */
04163 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
04164 {
04165   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04166
04167   MODIFY_REG(*preg,
04168              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
04169              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
04170 }
04171
04172 /**
04173   * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
04174   *         Channel to which the offset programmed will be applied
04175   *         (independently of channel mapped on ADC group regular
04176   *         or group injected)
04177   * @note   Usage of the returned channel number:
04178   *         - To reinject this channel into another function LL_ADC_xxx:
04179   *           the returned channel number is only partly formatted on definition
04180   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04181   *           with parts of literals LL_ADC_CHANNEL_x or using
04182   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04183   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04184   *           as parameter for another function.
04185   *         - To get the channel number in decimal format:
04186   *           process the returned value with the helper macro
04187   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04188   * @note   On STM32G4, some fast channels are available: fast analog inputs
04189   *         coming from GPIO pads (ADC_IN1..5).
04190   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
04191   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
04192   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
04193   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
04194   * @param  ADCx ADC instance
04195   * @param  Offsety This parameter can be one of the following values:
04196   *         @arg @ref LL_ADC_OFFSET_1
04197   *         @arg @ref LL_ADC_OFFSET_2
04198   *         @arg @ref LL_ADC_OFFSET_3
04199   *         @arg @ref LL_ADC_OFFSET_4
04200   * @retval Returned value can be one of the following values:
04201   *         @arg @ref LL_ADC_CHANNEL_0
04202   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
04203   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
04204   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
04205   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
04206   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
04207   *         @arg @ref LL_ADC_CHANNEL_6
04208   *         @arg @ref LL_ADC_CHANNEL_7
04209   *         @arg @ref LL_ADC_CHANNEL_8
04210   *         @arg @ref LL_ADC_CHANNEL_9
04211   *         @arg @ref LL_ADC_CHANNEL_10
04212   *         @arg @ref LL_ADC_CHANNEL_11
04213   *         @arg @ref LL_ADC_CHANNEL_12
04214   *         @arg @ref LL_ADC_CHANNEL_13
04215   *         @arg @ref LL_ADC_CHANNEL_14
04216   *         @arg @ref LL_ADC_CHANNEL_15
04217   *         @arg @ref LL_ADC_CHANNEL_16
04218   *         @arg @ref LL_ADC_CHANNEL_17
04219   *         @arg @ref LL_ADC_CHANNEL_18
04220   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
04221   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
04222   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
04223   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
04224   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
04225   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
04226   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
04227   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
04228   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
04229   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
04230   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
04231   *
04232   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
04233   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
04234   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
04235   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
04236   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
04237   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
04238   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
04239   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
04240   *             more details.
04241   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
04242   *             convert in 12-bit resolution.
04243   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
04244   *             (fADC) to convert in 12-bit resolution.\n
04245   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
04246   *                      comparison with internal channel parameter to be done
04247   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
04248   */
04249 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
04250 {
04251   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04252
04253   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
04254 }
04255
04256 /**
04257   * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
04258   *         Offset level (offset to be subtracted from the raw
04259   *         converted data).
04260   * @note   Caution: Offset format is dependent to ADC resolution:
04261   *         offset has to be left-aligned on bit 11, the LSB (right bits)
04262   *         are set to 0.
04263   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
04264   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
04265   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
04266   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
04267   * @param  ADCx ADC instance
04268   * @param  Offsety This parameter can be one of the following values:
04269   *         @arg @ref LL_ADC_OFFSET_1
04270   *         @arg @ref LL_ADC_OFFSET_2
04271   *         @arg @ref LL_ADC_OFFSET_3
04272   *         @arg @ref LL_ADC_OFFSET_4
04273   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
04274   */
04275 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
04276 {
04277   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04278
04279   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
04280 }
04281
04282 /**
04283   * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
04284   *         force offset state disable or enable
04285   *         without modifying offset channel or offset value.
04286   * @note   This function should be needed only in case of offset to be
04287   *         enabled-disabled dynamically, and should not be needed in other cases:
04288   *         function LL_ADC_SetOffset() automatically enables the offset.
04289   * @note   On this STM32 series, setting of this feature is conditioned to
04290   *         ADC state:
04291   *         ADC must be disabled or enabled without conversion on going
04292   *         on either groups regular or injected.
04293   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
04294   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
04295   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
04296   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
04297   * @param  ADCx ADC instance
04298   * @param  Offsety This parameter can be one of the following values:
04299   *         @arg @ref LL_ADC_OFFSET_1
04300   *         @arg @ref LL_ADC_OFFSET_2
04301   *         @arg @ref LL_ADC_OFFSET_3
04302   *         @arg @ref LL_ADC_OFFSET_4
04303   * @param  OffsetState This parameter can be one of the following values:
04304   *         @arg @ref LL_ADC_OFFSET_DISABLE
04305   *         @arg @ref LL_ADC_OFFSET_ENABLE
04306   * @retval None
04307   */
04308 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
04309 {
04310   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04311
04312   MODIFY_REG(*preg,
04313              ADC_OFR1_OFFSET1_EN,
04314              OffsetState);
04315 }
04316
04317 /**
04318   * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
04319   *         offset state disabled or enabled.
04320   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
04321   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
04322   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
04323   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
04324   * @param  ADCx ADC instance
04325   * @param  Offsety This parameter can be one of the following values:
04326   *         @arg @ref LL_ADC_OFFSET_1
04327   *         @arg @ref LL_ADC_OFFSET_2
04328   *         @arg @ref LL_ADC_OFFSET_3
04329   *         @arg @ref LL_ADC_OFFSET_4
04330   * @retval Returned value can be one of the following values:
04331   *         @arg @ref LL_ADC_OFFSET_DISABLE
04332   *         @arg @ref LL_ADC_OFFSET_ENABLE
04333   */
04334 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
04335 {
04336   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04337
04338   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
04339 }
04340
04341 /**
04342   * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
04343   *         choose offset sign.
04344   * @note   On this STM32 series, setting of this feature is conditioned to
04345   *         ADC state:
04346   *         ADC must be disabled or enabled without conversion on going
04347   *         on either groups regular or injected.
04348   * @rmtoll OFR1     OFFSETPOS      LL_ADC_SetOffsetSign\n
04349   *         OFR2     OFFSETPOS      LL_ADC_SetOffsetSign\n
04350   *         OFR3     OFFSETPOS      LL_ADC_SetOffsetSign\n
04351   *         OFR4     OFFSETPOS      LL_ADC_SetOffsetSign
04352   * @param  ADCx ADC instance
04353   * @param  Offsety This parameter can be one of the following values:
04354   *         @arg @ref LL_ADC_OFFSET_1
04355   *         @arg @ref LL_ADC_OFFSET_2
04356   *         @arg @ref LL_ADC_OFFSET_3
04357   *         @arg @ref LL_ADC_OFFSET_4
04358   * @param  OffsetSign This parameter can be one of the following values:
04359   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
04360   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
04361   * @retval None
04362   */
04363 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
04364 {
04365   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04366
04367   MODIFY_REG(*preg,
04368              ADC_OFR1_OFFSETPOS,
04369              OffsetSign);
04370 }
04371
04372 /**
04373   * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
04374   *         offset sign if positive or negative.
04375   * @rmtoll OFR1     OFFSETPOS      LL_ADC_GetOffsetSign\n
04376   *         OFR2     OFFSETPOS      LL_ADC_GetOffsetSign\n
04377   *         OFR3     OFFSETPOS      LL_ADC_GetOffsetSign\n
04378   *         OFR4     OFFSETPOS      LL_ADC_GetOffsetSign
04379   * @param  ADCx ADC instance
04380   * @param  Offsety This parameter can be one of the following values:
04381   *         @arg @ref LL_ADC_OFFSET_1
04382   *         @arg @ref LL_ADC_OFFSET_2
04383   *         @arg @ref LL_ADC_OFFSET_3
04384   *         @arg @ref LL_ADC_OFFSET_4
04385   * @retval Returned value can be one of the following values:
04386   *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
04387   *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
04388   */
04389 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
04390 {
04391   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04392
04393   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
04394 }
04395
04396 /**
04397   * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
04398   *         choose offset saturation mode.
04399   * @note   On this STM32 series, setting of this feature is conditioned to
04400   *         ADC state:
04401   *         ADC must be disabled or enabled without conversion on going
04402   *         on either groups regular or injected.
04403   * @rmtoll OFR1     SATEN          LL_ADC_SetOffsetSaturation\n
04404   *         OFR2     SATEN          LL_ADC_SetOffsetSaturation\n
04405   *         OFR3     SATEN          LL_ADC_SetOffsetSaturation\n
04406   *         OFR4     SATEN          LL_ADC_SetOffsetSaturation
04407   * @param  ADCx ADC instance
04408   * @param  Offsety This parameter can be one of the following values:
04409   *         @arg @ref LL_ADC_OFFSET_1
04410   *         @arg @ref LL_ADC_OFFSET_2
04411   *         @arg @ref LL_ADC_OFFSET_3
04412   *         @arg @ref LL_ADC_OFFSET_4
04413   * @param  OffsetSaturation This parameter can be one of the following values:
04414   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
04415   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
04416   * @retval None
04417   */
04418 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
04419 {
04420   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04421
04422   MODIFY_REG(*preg,
04423              ADC_OFR1_SATEN,
04424              OffsetSaturation);
04425 }
04426
04427 /**
04428   * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
04429   *         offset saturation if enabled or disabled.
04430   * @rmtoll OFR1     SATEN          LL_ADC_GetOffsetSaturation\n
04431   *         OFR2     SATEN          LL_ADC_GetOffsetSaturation\n
04432   *         OFR3     SATEN          LL_ADC_GetOffsetSaturation\n
04433   *         OFR4     SATEN          LL_ADC_GetOffsetSaturation
04434   * @param  ADCx ADC instance
04435   * @param  Offsety This parameter can be one of the following values:
04436   *         @arg @ref LL_ADC_OFFSET_1
04437   *         @arg @ref LL_ADC_OFFSET_2
04438   *         @arg @ref LL_ADC_OFFSET_3
04439   *         @arg @ref LL_ADC_OFFSET_4
04440   * @retval Returned value can be one of the following values:
04441   *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
04442   *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
04443   */
04444 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
04445 {
04446   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
04447
04448   return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
04449 }
04450
04451 /**
04452   * @brief  Set ADC gain compensation.
04453   * @note   This function set the gain compensation coefficient
04454   *         that is applied to raw converted data using the formula:
04455   *           DATA = DATA(raw) * (gain compensation coef) / 4096
04456   * @note   This function enables the gain compensation if given
04457   *         coefficient is above 0, otherwise it disables it.
04458   * @note   Gain compensation when enabled is applied to all channels.
04459   * @note   On this STM32 series, setting of this feature is conditioned to
04460   *         ADC state:
04461   *         ADC must be disabled or enabled without conversion on going
04462   *         on either groups regular or injected.
04463   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
04464   *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
04465   * @param  ADCx ADC instance
04466   * @param  GainCompensation This parameter can be:
04467   *         0           Gain compensation will be disabled and value set to 0
04468   *         1 -> 16393  Gain compensation will be enabled with specified value
04469   * @retval None
04470   */
04471 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
04472 {
04473   MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
04474   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
04475 }
04476
04477 /**
04478   * @brief  Get the ADC gain compensation value
04479   * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
04480   *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
04481   * @param  ADCx ADC instance
04482   * @retval Returned value can be:
04483   *         0           Gain compensation is disabled
04484   *         1 -> 16393  Gain compensation is enabled with returned value
04485   */
04486 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
04487 {
04488   return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ?
04489           READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
04490 }
04491
04492 #if defined(ADC_SMPR1_SMPPLUS)
04493 /**
04494   * @brief  Set ADC sampling time common configuration impacting
04495   *         settings of sampling time channel wise.
04496   * @note   On this STM32 series, setting of this feature is conditioned to
04497   *         ADC state:
04498   *         ADC must be disabled or enabled without conversion on going
04499   *         on either groups regular or injected.
04500   * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
04501   * @param  ADCx ADC instance
04502   * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
04503   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
04504   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
04505   * @retval None
04506   */
04507 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
04508 {
04509   MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
04510 }
04511
04512 /**
04513   * @brief  Get ADC sampling time common configuration impacting
04514   *         settings of sampling time channel wise.
04515   * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
04516   * @param  ADCx ADC instance
04517   * @retval Returned value can be one of the following values:
04518   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
04519   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
04520   */
04521 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
04522 {
04523   return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
04524 }
04525 #endif /* ADC_SMPR1_SMPPLUS */
04526
04527 /**
04528   * @}
04529   */
04530
04531 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
04532   * @{
04533   */
04534
04535 /**
04536   * @brief  Set ADC group regular conversion trigger source:
04537   *         internal (SW start) or from external peripheral (timer event,
04538   *         external interrupt line).
04539   * @note   On this STM32 series, setting trigger source to external trigger
04540   *         also set trigger polarity to rising edge
04541   *         (default setting for compatibility with some ADC on other
04542   *         STM32 series having this setting set by HW default value).
04543   *         In case of need to modify trigger edge, use
04544   *         function @ref LL_ADC_REG_SetTriggerEdge().
04545   * @note   Availability of parameters of trigger sources from timer
04546   *         depends on timers availability on the selected device.
04547   * @note   On this STM32 series, setting of this feature is conditioned to
04548   *         ADC state:
04549   *         ADC must be disabled or enabled without conversion on going
04550   *         on group regular.
04551   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
04552   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
04553   * @param  ADCx ADC instance
04554   * @param  TriggerSource This parameter can be one of the following values:
04555   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
04556   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
04557   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
04558   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
04559   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
04560   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
04561   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
04562   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
04563   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
04564   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
04565   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
04566   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
04567   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
04568   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
04569   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
04570   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
04571   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
04572   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
04573   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
04574   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
04575   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
04576   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
04577   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
04578   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
04579   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
04580   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
04581   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
04582   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
04583   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
04584   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
04585   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
04586   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
04587   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
04588   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
04589   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
04590   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
04591   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
04592   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
04593   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
04594   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
04595   *
04596   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
04597   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
04598   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
04599   *             more details.
04600   * @retval None
04601   */
04602 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
04603 {
04604   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
04605 }
04606
04607 /**
04608   * @brief  Get ADC group regular conversion trigger source:
04609   *         internal (SW start) or from external peripheral (timer event,
04610   *         external interrupt line).
04611   * @note   To determine whether group regular trigger source is
04612   *         internal (SW start) or external, without detail
04613   *         of which peripheral is selected as external trigger,
04614   *         (equivalent to
04615   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
04616   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
04617   * @note   Availability of parameters of trigger sources from timer
04618   *         depends on timers availability on the selected device.
04619   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
04620   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
04621   * @param  ADCx ADC instance
04622   * @retval Returned value can be one of the following values:
04623   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
04624   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
04625   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
04626   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
04627   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
04628   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
04629   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
04630   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
04631   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
04632   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
04633   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
04634   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
04635   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
04636   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
04637   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
04638   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
04639   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
04640   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
04641   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
04642   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
04643   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
04644   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
04645   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
04646   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
04647   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
04648   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
04649   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
04650   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
04651   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
04652   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
04653   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
04654   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
04655   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
04656   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
04657   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
04658   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
04659   *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
04660   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
04661   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
04662   *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
04663   *
04664   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
04665   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
04666   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
04667   *             more details.
04668   */
04669 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
04670 {
04671   __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
04672
04673   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
04674   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
04675   uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
04676
04677   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
04678   /* to match with triggers literals definition.                              */
04679   return ((trigger_source
04680            & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
04681           | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
04682          );
04683 }
04684
04685 /**
04686   * @brief  Get ADC group regular conversion trigger source internal (SW start)
04687   *         or external.
04688   * @note   In case of group regular trigger source set to external trigger,
04689   *         to determine which peripheral is selected as external trigger,
04690   *         use function @ref LL_ADC_REG_GetTriggerSource().
04691   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
04692   * @param  ADCx ADC instance
04693   * @retval Value "0" if trigger source external trigger
04694   *         Value "1" if trigger source SW start.
04695   */
04696 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
04697 {
04698   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
04699 }
04700
04701 /**
04702   * @brief  Set ADC group regular conversion trigger polarity.
04703   * @note   Applicable only for trigger source set to external trigger.
04704   * @note   On this STM32 series, setting of this feature is conditioned to
04705   *         ADC state:
04706   *         ADC must be disabled or enabled without conversion on going
04707   *         on group regular.
04708   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
04709   * @param  ADCx ADC instance
04710   * @param  ExternalTriggerEdge This parameter can be one of the following values:
04711   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
04712   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
04713   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
04714   * @retval None
04715   */
04716 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
04717 {
04718   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
04719 }
04720
04721 /**
04722   * @brief  Get ADC group regular conversion trigger polarity.
04723   * @note   Applicable only for trigger source set to external trigger.
04724   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
04725   * @param  ADCx ADC instance
04726   * @retval Returned value can be one of the following values:
04727   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
04728   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
04729   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
04730   */
04731 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
04732 {
04733   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
04734 }
04735
04736 /**
04737   * @brief  Set ADC sampling mode.
04738   * @note   This function set the ADC conversion sampling mode
04739   * @note   This mode applies to regular group only.
04740   * @note   Set sampling mode is applied to all conversion of regular group.
04741   * @note   On this STM32 series, setting of this feature is conditioned to
04742   *         ADC state:
04743   *         ADC must be disabled or enabled without conversion on going
04744   *         on group regular.
04745   * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
04746   *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
04747   * @param  ADCx ADC instance
04748   * @param  SamplingMode This parameter can be one of the following values:
04749   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
04750   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
04751   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
04752   * @retval None
04753   */
04754 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
04755 {
04756   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
04757 }
04758
04759 /**
04760   * @brief  Get the ADC sampling mode
04761   * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
04762   *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
04763   * @param  ADCx ADC instance
04764   * @retval Returned value can be one of the following values:
04765   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
04766   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
04767   *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
04768   */
04769 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
04770 {
04771   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
04772 }
04773
04774 /**
04775   * @brief  Set ADC group regular sequencer length and scan direction.
04776   * @note   Description of ADC group regular sequencer features:
04777   *         - For devices with sequencer fully configurable
04778   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
04779   *           sequencer length and each rank affectation to a channel
04780   *           are configurable.
04781   *           This function performs configuration of:
04782   *           - Sequence length: Number of ranks in the scan sequence.
04783   *           - Sequence direction: Unless specified in parameters, sequencer
04784   *             scan direction is forward (from rank 1 to rank n).
04785   *           Sequencer ranks are selected using
04786   *           function "LL_ADC_REG_SetSequencerRanks()".
04787   *         - For devices with sequencer not fully configurable
04788   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
04789   *           sequencer length and each rank affectation to a channel
04790   *           are defined by channel number.
04791   *           This function performs configuration of:
04792   *           - Sequence length: Number of ranks in the scan sequence is
04793   *             defined by number of channels set in the sequence,
04794   *             rank of each channel is fixed by channel HW number.
04795   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
04796   *           - Sequence direction: Unless specified in parameters, sequencer
04797   *             scan direction is forward (from lowest channel number to
04798   *             highest channel number).
04799   *           Sequencer ranks are selected using
04800   *           function "LL_ADC_REG_SetSequencerChannels()".
04801   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
04802   *         ADC conversion on only 1 channel.
04803   * @note   On this STM32 series, setting of this feature is conditioned to
04804   *         ADC state:
04805   *         ADC must be disabled or enabled without conversion on going
04806   *         on group regular.
04807   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
04808   * @param  ADCx ADC instance
04809   * @param  SequencerNbRanks This parameter can be one of the following values:
04810   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
04811   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
04812   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
04813   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
04814   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
04815   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
04816   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
04817   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
04818   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
04819   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
04820   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
04821   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
04822   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
04823   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
04824   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
04825   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
04826   * @retval None
04827   */
04828 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
04829 {
04830   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
04831 }
04832
04833 /**
04834   * @brief  Get ADC group regular sequencer length and scan direction.
04835   * @note   Description of ADC group regular sequencer features:
04836   *         - For devices with sequencer fully configurable
04837   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
04838   *           sequencer length and each rank affectation to a channel
04839   *           are configurable.
04840   *           This function retrieves:
04841   *           - Sequence length: Number of ranks in the scan sequence.
04842   *           - Sequence direction: Unless specified in parameters, sequencer
04843   *             scan direction is forward (from rank 1 to rank n).
04844   *           Sequencer ranks are selected using
04845   *           function "LL_ADC_REG_SetSequencerRanks()".
04846   *         - For devices with sequencer not fully configurable
04847   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
04848   *           sequencer length and each rank affectation to a channel
04849   *           are defined by channel number.
04850   *           This function retrieves:
04851   *           - Sequence length: Number of ranks in the scan sequence is
04852   *             defined by number of channels set in the sequence,
04853   *             rank of each channel is fixed by channel HW number.
04854   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
04855   *           - Sequence direction: Unless specified in parameters, sequencer
04856   *             scan direction is forward (from lowest channel number to
04857   *             highest channel number).
04858   *           Sequencer ranks are selected using
04859   *           function "LL_ADC_REG_SetSequencerChannels()".
04860   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
04861   *         ADC conversion on only 1 channel.
04862   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
04863   * @param  ADCx ADC instance
04864   * @retval Returned value can be one of the following values:
04865   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
04866   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
04867   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
04868   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
04869   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
04870   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
04871   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
04872   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
04873   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
04874   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
04875   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
04876   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
04877   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
04878   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
04879   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
04880   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
04881   */
04882 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
04883 {
04884   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
04885 }
04886
04887 /**
04888   * @brief  Set ADC group regular sequencer discontinuous mode:
04889   *         sequence subdivided and scan conversions interrupted every selected
04890   *         number of ranks.
04891   * @note   It is not possible to enable both ADC group regular
04892   *         continuous mode and sequencer discontinuous mode.
04893   * @note   It is not possible to enable both ADC auto-injected mode
04894   *         and ADC group regular sequencer discontinuous mode.
04895   * @note   On this STM32 series, setting of this feature is conditioned to
04896   *         ADC state:
04897   *         ADC must be disabled or enabled without conversion on going
04898   *         on group regular.
04899   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
04900   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
04901   * @param  ADCx ADC instance
04902   * @param  SeqDiscont This parameter can be one of the following values:
04903   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
04904   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
04905   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
04906   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
04907   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
04908   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
04909   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
04910   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
04911   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
04912   * @retval None
04913   */
04914 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
04915 {
04916   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
04917 }
04918
04919 /**
04920   * @brief  Get ADC group regular sequencer discontinuous mode:
04921   *         sequence subdivided and scan conversions interrupted every selected
04922   *         number of ranks.
04923   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
04924   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
04925   * @param  ADCx ADC instance
04926   * @retval Returned value can be one of the following values:
04927   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
04928   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
04929   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
04930   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
04931   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
04932   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
04933   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
04934   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
04935   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
04936   */
04937 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
04938 {
04939   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
04940 }
04941
04942 /**
04943   * @brief  Set ADC group regular sequence: channel on the selected
04944   *         scan sequence rank.
04945   * @note   This function performs configuration of:
04946   *         - Channels ordering into each rank of scan sequence:
04947   *           whatever channel can be placed into whatever rank.
04948   * @note   On this STM32 series, ADC group regular sequencer is
04949   *         fully configurable: sequencer length and each rank
04950   *         affectation to a channel are configurable.
04951   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
04952   * @note   Depending on devices and packages, some channels may not be available.
04953   *         Refer to device datasheet for channels availability.
04954   * @note   On this STM32 series, to measure internal channels (VrefInt,
04955   *         TempSensor, ...), measurement paths to internal channels must be
04956   *         enabled separately.
04957   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
04958   * @note   On this STM32 series, setting of this feature is conditioned to
04959   *         ADC state:
04960   *         ADC must be disabled or enabled without conversion on going
04961   *         on group regular.
04962   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
04963   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
04964   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
04965   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
04966   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
04967   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
04968   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
04969   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
04970   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
04971   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
04972   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
04973   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
04974   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
04975   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
04976   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
04977   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
04978   * @param  ADCx ADC instance
04979   * @param  Rank This parameter can be one of the following values:
04980   *         @arg @ref LL_ADC_REG_RANK_1
04981   *         @arg @ref LL_ADC_REG_RANK_2
04982   *         @arg @ref LL_ADC_REG_RANK_3
04983   *         @arg @ref LL_ADC_REG_RANK_4
04984   *         @arg @ref LL_ADC_REG_RANK_5
04985   *         @arg @ref LL_ADC_REG_RANK_6
04986   *         @arg @ref LL_ADC_REG_RANK_7
04987   *         @arg @ref LL_ADC_REG_RANK_8
04988   *         @arg @ref LL_ADC_REG_RANK_9
04989   *         @arg @ref LL_ADC_REG_RANK_10
04990   *         @arg @ref LL_ADC_REG_RANK_11
04991   *         @arg @ref LL_ADC_REG_RANK_12
04992   *         @arg @ref LL_ADC_REG_RANK_13
04993   *         @arg @ref LL_ADC_REG_RANK_14
04994   *         @arg @ref LL_ADC_REG_RANK_15
04995   *         @arg @ref LL_ADC_REG_RANK_16
04996   * @param  Channel This parameter can be one of the following values:
04997   *         @arg @ref LL_ADC_CHANNEL_0
04998   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
04999   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
05000   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
05001   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
05002   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
05003   *         @arg @ref LL_ADC_CHANNEL_6
05004   *         @arg @ref LL_ADC_CHANNEL_7
05005   *         @arg @ref LL_ADC_CHANNEL_8
05006   *         @arg @ref LL_ADC_CHANNEL_9
05007   *         @arg @ref LL_ADC_CHANNEL_10
05008   *         @arg @ref LL_ADC_CHANNEL_11
05009   *         @arg @ref LL_ADC_CHANNEL_12
05010   *         @arg @ref LL_ADC_CHANNEL_13
05011   *         @arg @ref LL_ADC_CHANNEL_14
05012   *         @arg @ref LL_ADC_CHANNEL_15
05013   *         @arg @ref LL_ADC_CHANNEL_16
05014   *         @arg @ref LL_ADC_CHANNEL_17
05015   *         @arg @ref LL_ADC_CHANNEL_18
05016   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
05017   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
05018   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
05019   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
05020   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
05021   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
05022   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
05023   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
05024   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
05025   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
05026   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
05027   *
05028   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
05029   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
05030   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
05031   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
05032   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
05033   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
05034   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
05035   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
05036   *             for more details.
05037   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
05038   *             convert in 12-bit resolution.
05039   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
05040   *             (fADC) to convert in 12-bit resolution.\n
05041   * @retval None
05042   */
05043 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
05044 {
05045   /* Set bits with content of parameter "Channel" with bits position          */
05046   /* in register and register position depending on parameter "Rank".         */
05047   /* Parameters "Rank" and "Channel" are used with masks because containing   */
05048   /* other bits reserved for other purpose.                                   */
05049   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
05050                                              ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
05051
05052   MODIFY_REG(*preg,
05053              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
05054              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05055              << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
05056 }
05057
05058 /**
05059   * @brief  Get ADC group regular sequence: channel on the selected
05060   *         scan sequence rank.
05061   * @note   On this STM32 series, ADC group regular sequencer is
05062   *         fully configurable: sequencer length and each rank
05063   *         affectation to a channel are configurable.
05064   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
05065   * @note   Depending on devices and packages, some channels may not be available.
05066   *         Refer to device datasheet for channels availability.
05067   * @note   Usage of the returned channel number:
05068   *         - To reinject this channel into another function LL_ADC_xxx:
05069   *           the returned channel number is only partly formatted on definition
05070   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
05071   *           with parts of literals LL_ADC_CHANNEL_x or using
05072   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05073   *           Then the selected literal LL_ADC_CHANNEL_x can be used
05074   *           as parameter for another function.
05075   *         - To get the channel number in decimal format:
05076   *           process the returned value with the helper macro
05077   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05078   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
05079   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
05080   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
05081   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
05082   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
05083   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
05084   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
05085   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
05086   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
05087   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
05088   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
05089   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
05090   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
05091   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
05092   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
05093   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
05094   * @param  ADCx ADC instance
05095   * @param  Rank This parameter can be one of the following values:
05096   *         @arg @ref LL_ADC_REG_RANK_1
05097   *         @arg @ref LL_ADC_REG_RANK_2
05098   *         @arg @ref LL_ADC_REG_RANK_3
05099   *         @arg @ref LL_ADC_REG_RANK_4
05100   *         @arg @ref LL_ADC_REG_RANK_5
05101   *         @arg @ref LL_ADC_REG_RANK_6
05102   *         @arg @ref LL_ADC_REG_RANK_7
05103   *         @arg @ref LL_ADC_REG_RANK_8
05104   *         @arg @ref LL_ADC_REG_RANK_9
05105   *         @arg @ref LL_ADC_REG_RANK_10
05106   *         @arg @ref LL_ADC_REG_RANK_11
05107   *         @arg @ref LL_ADC_REG_RANK_12
05108   *         @arg @ref LL_ADC_REG_RANK_13
05109   *         @arg @ref LL_ADC_REG_RANK_14
05110   *         @arg @ref LL_ADC_REG_RANK_15
05111   *         @arg @ref LL_ADC_REG_RANK_16
05112   * @retval Returned value can be one of the following values:
05113   *         @arg @ref LL_ADC_CHANNEL_0
05114   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
05115   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
05116   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
05117   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
05118   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
05119   *         @arg @ref LL_ADC_CHANNEL_6
05120   *         @arg @ref LL_ADC_CHANNEL_7
05121   *         @arg @ref LL_ADC_CHANNEL_8
05122   *         @arg @ref LL_ADC_CHANNEL_9
05123   *         @arg @ref LL_ADC_CHANNEL_10
05124   *         @arg @ref LL_ADC_CHANNEL_11
05125   *         @arg @ref LL_ADC_CHANNEL_12
05126   *         @arg @ref LL_ADC_CHANNEL_13
05127   *         @arg @ref LL_ADC_CHANNEL_14
05128   *         @arg @ref LL_ADC_CHANNEL_15
05129   *         @arg @ref LL_ADC_CHANNEL_16
05130   *         @arg @ref LL_ADC_CHANNEL_17
05131   *         @arg @ref LL_ADC_CHANNEL_18
05132   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
05133   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
05134   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
05135   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
05136   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
05137   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
05138   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
05139   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
05140   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
05141   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
05142   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
05143   *
05144   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
05145   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
05146   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
05147   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
05148   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
05149   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
05150   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
05151   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
05152   *             more details.
05153   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
05154   *             convert in 12-bit resolution.
05155   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
05156   *             (fADC) to convert in 12-bit resolution.\n
05157   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
05158   *                      comparison with internal channel parameter to be done
05159   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
05160   */
05161 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
05162 {
05163   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
05164                                                    ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
05165
05166   return (uint32_t)((READ_BIT(*preg,
05167                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
05168                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
05169                    );
05170 }
05171
05172 /**
05173   * @brief  Set ADC continuous conversion mode on ADC group regular.
05174   * @note   Description of ADC continuous conversion mode:
05175   *         - single mode: one conversion per trigger
05176   *         - continuous mode: after the first trigger, following
05177   *           conversions launched successively automatically.
05178   * @note   It is not possible to enable both ADC group regular
05179   *         continuous mode and sequencer discontinuous mode.
05180   * @note   On this STM32 series, setting of this feature is conditioned to
05181   *         ADC state:
05182   *         ADC must be disabled or enabled without conversion on going
05183   *         on group regular.
05184   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
05185   * @param  ADCx ADC instance
05186   * @param  Continuous This parameter can be one of the following values:
05187   *         @arg @ref LL_ADC_REG_CONV_SINGLE
05188   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
05189   * @retval None
05190   */
05191 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
05192 {
05193   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
05194 }
05195
05196 /**
05197   * @brief  Get ADC continuous conversion mode on ADC group regular.
05198   * @note   Description of ADC continuous conversion mode:
05199   *         - single mode: one conversion per trigger
05200   *         - continuous mode: after the first trigger, following
05201   *           conversions launched successively automatically.
05202   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
05203   * @param  ADCx ADC instance
05204   * @retval Returned value can be one of the following values:
05205   *         @arg @ref LL_ADC_REG_CONV_SINGLE
05206   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
05207   */
05208 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
05209 {
05210   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
05211 }
05212
05213 /**
05214   * @brief  Set ADC group regular conversion data transfer: no transfer or
05215   *         transfer by DMA, and DMA requests mode.
05216   * @note   If transfer by DMA selected, specifies the DMA requests
05217   *         mode:
05218   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05219   *           when number of DMA data transfers (number of
05220   *           ADC conversions) is reached.
05221   *           This ADC mode is intended to be used with DMA mode non-circular.
05222   *         - Unlimited mode: DMA transfer requests are unlimited,
05223   *           whatever number of DMA data transfers (number of
05224   *           ADC conversions).
05225   *           This ADC mode is intended to be used with DMA mode circular.
05226   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05227   *         mode non-circular:
05228   *         when DMA transfers size will be reached, DMA will stop transfers of
05229   *         ADC conversions data ADC will raise an overrun error
05230   *        (overrun flag and interruption if enabled).
05231   * @note   For devices with several ADC instances: ADC multimode DMA
05232   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
05233   * @note   To configure DMA source address (peripheral address),
05234   *         use function @ref LL_ADC_DMA_GetRegAddr().
05235   * @note   On this STM32 series, setting of this feature is conditioned to
05236   *         ADC state:
05237   *         ADC must be disabled or enabled without conversion on going
05238   *         on either groups regular or injected.
05239   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
05240   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
05241   * @param  ADCx ADC instance
05242   * @param  DMATransfer This parameter can be one of the following values:
05243   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
05244   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
05245   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
05246   * @retval None
05247   */
05248 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
05249 {
05250   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
05251 }
05252
05253 /**
05254   * @brief  Get ADC group regular conversion data transfer: no transfer or
05255   *         transfer by DMA, and DMA requests mode.
05256   * @note   If transfer by DMA selected, specifies the DMA requests
05257   *         mode:
05258   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05259   *           when number of DMA data transfers (number of
05260   *           ADC conversions) is reached.
05261   *           This ADC mode is intended to be used with DMA mode non-circular.
05262   *         - Unlimited mode: DMA transfer requests are unlimited,
05263   *           whatever number of DMA data transfers (number of
05264   *           ADC conversions).
05265   *           This ADC mode is intended to be used with DMA mode circular.
05266   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05267   *         mode non-circular:
05268   *         when DMA transfers size will be reached, DMA will stop transfers of
05269   *         ADC conversions data ADC will raise an overrun error
05270   *         (overrun flag and interruption if enabled).
05271   * @note   For devices with several ADC instances: ADC multimode DMA
05272   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
05273   * @note   To configure DMA source address (peripheral address),
05274   *         use function @ref LL_ADC_DMA_GetRegAddr().
05275   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
05276   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
05277   * @param  ADCx ADC instance
05278   * @retval Returned value can be one of the following values:
05279   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
05280   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
05281   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
05282   */
05283 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
05284 {
05285   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
05286 }
05287
05288 /**
05289   * @brief  Set ADC group regular behavior in case of overrun:
05290   *         data preserved or overwritten.
05291   * @note   Compatibility with devices without feature overrun:
05292   *         other devices without this feature have a behavior
05293   *         equivalent to data overwritten.
05294   *         The default setting of overrun is data preserved.
05295   *         Therefore, for compatibility with all devices, parameter
05296   *         overrun should be set to data overwritten.
05297   * @note   On this STM32 series, setting of this feature is conditioned to
05298   *         ADC state:
05299   *         ADC must be disabled or enabled without conversion on going
05300   *         on group regular.
05301   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
05302   * @param  ADCx ADC instance
05303   * @param  Overrun This parameter can be one of the following values:
05304   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
05305   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
05306   * @retval None
05307   */
05308 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
05309 {
05310   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
05311 }
05312
05313 /**
05314   * @brief  Get ADC group regular behavior in case of overrun:
05315   *         data preserved or overwritten.
05316   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
05317   * @param  ADCx ADC instance
05318   * @retval Returned value can be one of the following values:
05319   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
05320   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
05321   */
05322 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
05323 {
05324   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
05325 }
05326
05327 /**
05328   * @}
05329   */
05330
05331 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
05332   * @{
05333   */
05334
05335 /**
05336   * @brief  Set ADC group injected conversion trigger source:
05337   *         internal (SW start) or from external peripheral (timer event,
05338   *         external interrupt line).
05339   * @note   On this STM32 series, setting trigger source to external trigger
05340   *         also set trigger polarity to rising edge
05341   *         (default setting for compatibility with some ADC on other
05342   *         STM32 series having this setting set by HW default value).
05343   *         In case of need to modify trigger edge, use
05344   *         function @ref LL_ADC_INJ_SetTriggerEdge().
05345   * @note   Availability of parameters of trigger sources from timer
05346   *         depends on timers availability on the selected device.
05347   * @note   On this STM32 series, setting of this feature is conditioned to
05348   *         ADC state:
05349   *         ADC must not be disabled. Can be enabled with or without conversion
05350   *         on going on either groups regular or injected.
05351   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
05352   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
05353   * @param  ADCx ADC instance
05354   * @param  TriggerSource This parameter can be one of the following values:
05355   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
05356   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
05357   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
05358   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
05359   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
05360   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
05361   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
05362   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
05363   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
05364   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
05365   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
05366   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
05367   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
05368   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
05369   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
05370   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
05371   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
05372   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
05373   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
05374   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
05375   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
05376   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
05377   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
05378   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
05379   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
05380   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
05381   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
05382   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
05383   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
05384   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
05385   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
05386   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
05387   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
05388   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
05389   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
05390   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
05391   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
05392   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
05393   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
05394   *
05395   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
05396   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
05397   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
05398   *             more details.
05399   * @retval None
05400   */
05401 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
05402 {
05403   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
05404 }
05405
05406 /**
05407   * @brief  Get ADC group injected conversion trigger source:
05408   *         internal (SW start) or from external peripheral (timer event,
05409   *         external interrupt line).
05410   * @note   To determine whether group injected trigger source is
05411   *         internal (SW start) or external, without detail
05412   *         of which peripheral is selected as external trigger,
05413   *         (equivalent to
05414   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
05415   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
05416   * @note   Availability of parameters of trigger sources from timer
05417   *         depends on timers availability on the selected device.
05418   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
05419   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
05420   * @param  ADCx ADC instance
05421   * @retval Returned value can be one of the following values:
05422   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
05423   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
05424   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
05425   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
05426   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
05427   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
05428   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
05429   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
05430   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
05431   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
05432   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
05433   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
05434   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
05435   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
05436   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
05437   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
05438   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
05439   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
05440   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
05441   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
05442   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
05443   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
05444   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
05445   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
05446   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
05447   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
05448   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
05449   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
05450   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
05451   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
05452   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
05453   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
05454   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
05455   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
05456   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
05457   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
05458   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
05459   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
05460   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
05461   *
05462   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
05463   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
05464   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
05465   *             more details.
05466   */
05467 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
05468 {
05469   __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
05470
05471   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
05472   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
05473   uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
05474
05475   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
05476   /* to match with triggers literals definition.                              */
05477   return ((trigger_source
05478            & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
05479           | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
05480          );
05481 }
05482
05483 /**
05484   * @brief  Get ADC group injected conversion trigger source internal (SW start)
05485             or external
05486   * @note   In case of group injected trigger source set to external trigger,
05487   *         to determine which peripheral is selected as external trigger,
05488   *         use function @ref LL_ADC_INJ_GetTriggerSource.
05489   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
05490   * @param  ADCx ADC instance
05491   * @retval Value "0" if trigger source external trigger
05492   *         Value "1" if trigger source SW start.
05493   */
05494 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
05495 {
05496   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
05497 }
05498
05499 /**
05500   * @brief  Set ADC group injected conversion trigger polarity.
05501   *         Applicable only for trigger source set to external trigger.
05502   * @note   On this STM32 series, setting of this feature is conditioned to
05503   *         ADC state:
05504   *         ADC must not be disabled. Can be enabled with or without conversion
05505   *         on going on either groups regular or injected.
05506   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
05507   * @param  ADCx ADC instance
05508   * @param  ExternalTriggerEdge This parameter can be one of the following values:
05509   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
05510   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
05511   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
05512   * @retval None
05513   */
05514 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
05515 {
05516   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
05517 }
05518
05519 /**
05520   * @brief  Get ADC group injected conversion trigger polarity.
05521   *         Applicable only for trigger source set to external trigger.
05522   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
05523   * @param  ADCx ADC instance
05524   * @retval Returned value can be one of the following values:
05525   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
05526   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
05527   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
05528   */
05529 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
05530 {
05531   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
05532 }
05533
05534 /**
05535   * @brief  Set ADC group injected sequencer length and scan direction.
05536   * @note   This function performs configuration of:
05537   *         - Sequence length: Number of ranks in the scan sequence.
05538   *         - Sequence direction: Unless specified in parameters, sequencer
05539   *           scan direction is forward (from rank 1 to rank n).
05540   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
05541   *         ADC conversion on only 1 channel.
05542   * @note   On this STM32 series, setting of this feature is conditioned to
05543   *         ADC state:
05544   *         ADC must not be disabled. Can be enabled with or without conversion
05545   *         on going on either groups regular or injected.
05546   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
05547   * @param  ADCx ADC instance
05548   * @param  SequencerNbRanks This parameter can be one of the following values:
05549   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
05550   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
05551   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
05552   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
05553   * @retval None
05554   */
05555 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
05556 {
05557   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
05558 }
05559
05560 /**
05561   * @brief  Get ADC group injected sequencer length and scan direction.
05562   * @note   This function retrieves:
05563   *         - Sequence length: Number of ranks in the scan sequence.
05564   *         - Sequence direction: Unless specified in parameters, sequencer
05565   *           scan direction is forward (from rank 1 to rank n).
05566   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
05567   *         ADC conversion on only 1 channel.
05568   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
05569   * @param  ADCx ADC instance
05570   * @retval Returned value can be one of the following values:
05571   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
05572   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
05573   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
05574   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
05575   */
05576 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
05577 {
05578   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
05579 }
05580
05581 /**
05582   * @brief  Set ADC group injected sequencer discontinuous mode:
05583   *         sequence subdivided and scan conversions interrupted every selected
05584   *         number of ranks.
05585   * @note   It is not possible to enable both ADC group injected
05586   *         auto-injected mode and sequencer discontinuous mode.
05587   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
05588   * @param  ADCx ADC instance
05589   * @param  SeqDiscont This parameter can be one of the following values:
05590   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
05591   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
05592   * @retval None
05593   */
05594 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
05595 {
05596   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
05597 }
05598
05599 /**
05600   * @brief  Get ADC group injected sequencer discontinuous mode:
05601   *         sequence subdivided and scan conversions interrupted every selected
05602   *         number of ranks.
05603   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
05604   * @param  ADCx ADC instance
05605   * @retval Returned value can be one of the following values:
05606   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
05607   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
05608   */
05609 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
05610 {
05611   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
05612 }
05613
05614 /**
05615   * @brief  Set ADC group injected sequence: channel on the selected
05616   *         sequence rank.
05617   * @note   Depending on devices and packages, some channels may not be available.
05618   *         Refer to device datasheet for channels availability.
05619   * @note   On this STM32 series, to measure internal channels (VrefInt,
05620   *         TempSensor, ...), measurement paths to internal channels must be
05621   *         enabled separately.
05622   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
05623   * @note   On STM32G4, some fast channels are available: fast analog inputs
05624   *         coming from GPIO pads (ADC_IN1..5).
05625   * @note   On this STM32 series, setting of this feature is conditioned to
05626   *         ADC state:
05627   *         ADC must not be disabled. Can be enabled with or without conversion
05628   *         on going on either groups regular or injected.
05629   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
05630   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
05631   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
05632   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
05633   * @param  ADCx ADC instance
05634   * @param  Rank This parameter can be one of the following values:
05635   *         @arg @ref LL_ADC_INJ_RANK_1
05636   *         @arg @ref LL_ADC_INJ_RANK_2
05637   *         @arg @ref LL_ADC_INJ_RANK_3
05638   *         @arg @ref LL_ADC_INJ_RANK_4
05639   * @param  Channel This parameter can be one of the following values:
05640   *         @arg @ref LL_ADC_CHANNEL_0
05641   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
05642   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
05643   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
05644   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
05645   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
05646   *         @arg @ref LL_ADC_CHANNEL_6
05647   *         @arg @ref LL_ADC_CHANNEL_7
05648   *         @arg @ref LL_ADC_CHANNEL_8
05649   *         @arg @ref LL_ADC_CHANNEL_9
05650   *         @arg @ref LL_ADC_CHANNEL_10
05651   *         @arg @ref LL_ADC_CHANNEL_11
05652   *         @arg @ref LL_ADC_CHANNEL_12
05653   *         @arg @ref LL_ADC_CHANNEL_13
05654   *         @arg @ref LL_ADC_CHANNEL_14
05655   *         @arg @ref LL_ADC_CHANNEL_15
05656   *         @arg @ref LL_ADC_CHANNEL_16
05657   *         @arg @ref LL_ADC_CHANNEL_17
05658   *         @arg @ref LL_ADC_CHANNEL_18
05659   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
05660   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
05661   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
05662   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
05663   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
05664   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
05665   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
05666   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
05667   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
05668   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
05669   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
05670   *
05671   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
05672   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
05673   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
05674   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
05675   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
05676   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
05677   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
05678   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
05679   *             for more details.
05680   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
05681   *             convert in 12-bit resolution.
05682   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
05683   *             (fADC) to convert in 12-bit resolution.\n
05684   * @retval None
05685   */
05686 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
05687 {
05688   /* Set bits with content of parameter "Channel" with bits position          */
05689   /* in register depending on parameter "Rank".                               */
05690   /* Parameters "Rank" and "Channel" are used with masks because containing   */
05691   /* other bits reserved for other purpose.                                   */
05692   MODIFY_REG(ADCx->JSQR,
05693              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05694              << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
05695              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05696              << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
05697 }
05698
05699 /**
05700   * @brief  Get ADC group injected sequence: channel on the selected
05701   *         sequence rank.
05702   * @note   Depending on devices and packages, some channels may not be available.
05703   *         Refer to device datasheet for channels availability.
05704   * @note   Usage of the returned channel number:
05705   *         - To reinject this channel into another function LL_ADC_xxx:
05706   *           the returned channel number is only partly formatted on definition
05707   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
05708   *           with parts of literals LL_ADC_CHANNEL_x or using
05709   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05710   *           Then the selected literal LL_ADC_CHANNEL_x can be used
05711   *           as parameter for another function.
05712   *         - To get the channel number in decimal format:
05713   *           process the returned value with the helper macro
05714   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
05715   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
05716   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
05717   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
05718   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
05719   * @param  ADCx ADC instance
05720   * @param  Rank This parameter can be one of the following values:
05721   *         @arg @ref LL_ADC_INJ_RANK_1
05722   *         @arg @ref LL_ADC_INJ_RANK_2
05723   *         @arg @ref LL_ADC_INJ_RANK_3
05724   *         @arg @ref LL_ADC_INJ_RANK_4
05725   * @retval Returned value can be one of the following values:
05726   *         @arg @ref LL_ADC_CHANNEL_0
05727   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
05728   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
05729   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
05730   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
05731   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
05732   *         @arg @ref LL_ADC_CHANNEL_6
05733   *         @arg @ref LL_ADC_CHANNEL_7
05734   *         @arg @ref LL_ADC_CHANNEL_8
05735   *         @arg @ref LL_ADC_CHANNEL_9
05736   *         @arg @ref LL_ADC_CHANNEL_10
05737   *         @arg @ref LL_ADC_CHANNEL_11
05738   *         @arg @ref LL_ADC_CHANNEL_12
05739   *         @arg @ref LL_ADC_CHANNEL_13
05740   *         @arg @ref LL_ADC_CHANNEL_14
05741   *         @arg @ref LL_ADC_CHANNEL_15
05742   *         @arg @ref LL_ADC_CHANNEL_16
05743   *         @arg @ref LL_ADC_CHANNEL_17
05744   *         @arg @ref LL_ADC_CHANNEL_18
05745   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
05746   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
05747   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
05748   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
05749   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
05750   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
05751   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
05752   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
05753   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
05754   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
05755   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
05756   *
05757   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
05758   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
05759   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
05760   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
05761   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
05762   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
05763   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
05764   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
05765   *             more details.
05766   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
05767   *             convert in 12-bit resolution.
05768   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
05769   *             (fADC) to convert in 12-bit resolution.\n
05770   *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
05771   *                      comparison with internal channel parameter to be done
05772   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
05773   */
05774 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
05775 {
05776   return (uint32_t)((READ_BIT(ADCx->JSQR,
05777                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05778                               << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
05779                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
05780                    );
05781 }
05782
05783 /**
05784   * @brief  Set ADC group injected conversion trigger:
05785   *         independent or from ADC group regular.
05786   * @note   This mode can be used to extend number of data registers
05787   *         updated after one ADC conversion trigger and with data
05788   *         permanently kept (not erased by successive conversions of scan of
05789   *         ADC sequencer ranks), up to 5 data registers:
05790   *         1 data register on ADC group regular, 4 data registers
05791   *         on ADC group injected.
05792   * @note   If ADC group injected injected trigger source is set to an
05793   *         external trigger, this feature must be must be set to
05794   *         independent trigger.
05795   *         ADC group injected automatic trigger is compliant only with
05796   *         group injected trigger source set to SW start, without any
05797   *         further action on  ADC group injected conversion start or stop:
05798   *         in this case, ADC group injected is controlled only
05799   *         from ADC group regular.
05800   * @note   It is not possible to enable both ADC group injected
05801   *         auto-injected mode and sequencer discontinuous mode.
05802   * @note   On this STM32 series, setting of this feature is conditioned to
05803   *         ADC state:
05804   *         ADC must be disabled or enabled without conversion on going
05805   *         on either groups regular or injected.
05806   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
05807   * @param  ADCx ADC instance
05808   * @param  TrigAuto This parameter can be one of the following values:
05809   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
05810   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
05811   * @retval None
05812   */
05813 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
05814 {
05815   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
05816 }
05817
05818 /**
05819   * @brief  Get ADC group injected conversion trigger:
05820   *         independent or from ADC group regular.
05821   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
05822   * @param  ADCx ADC instance
05823   * @retval Returned value can be one of the following values:
05824   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
05825   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
05826   */
05827 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
05828 {
05829   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
05830 }
05831
05832 /**
05833   * @brief  Set ADC group injected contexts queue mode.
05834   * @note   A context is a setting of group injected sequencer:
05835   *         - group injected trigger
05836   *         - sequencer length
05837   *         - sequencer ranks
05838   *         If contexts queue is disabled:
05839   *         - only 1 sequence can be configured
05840   *           and is active perpetually.
05841   *         If contexts queue is enabled:
05842   *         - up to 2 contexts can be queued
05843   *           and are checked in and out as a FIFO stack (first-in, first-out).
05844   *         - If a new context is set when queues is full, error is triggered
05845   *           by interruption "Injected Queue Overflow".
05846   *         - Two behaviors are possible when all contexts have been processed:
05847   *           the contexts queue can maintain the last context active perpetually
05848   *           or can be empty and injected group triggers are disabled.
05849   *         - Triggers can be only external (not internal SW start)
05850   *         - Caution: The sequence must be fully configured in one time
05851   *           (one write of register JSQR makes a check-in of a new context
05852   *           into the queue).
05853   *           Therefore functions to set separately injected trigger and
05854   *           sequencer channels cannot be used, register JSQR must be set
05855   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
05856   * @note   This parameter can be modified only when no conversion is on going
05857   *         on either groups regular or injected.
05858   * @note   A modification of the context mode (bit JQDIS) causes the contexts
05859   *         queue to be flushed and the register JSQR is cleared.
05860   * @note   On this STM32 series, setting of this feature is conditioned to
05861   *         ADC state:
05862   *         ADC must be disabled or enabled without conversion on going
05863   *         on either groups regular or injected.
05864   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
05865   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
05866   * @param  ADCx ADC instance
05867   * @param  QueueMode This parameter can be one of the following values:
05868   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
05869   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
05870   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
05871   * @retval None
05872   */
05873 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
05874 {
05875   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
05876 }
05877
05878 /**
05879   * @brief  Get ADC group injected context queue mode.
05880   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
05881   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
05882   * @param  ADCx ADC instance
05883   * @retval Returned value can be one of the following values:
05884   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
05885   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
05886   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
05887   */
05888 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
05889 {
05890   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
05891 }
05892
05893 /**
05894   * @brief  Set one context on ADC group injected that will be checked in
05895   *         contexts queue.
05896   * @note   A context is a setting of group injected sequencer:
05897   *         - group injected trigger
05898   *         - sequencer length
05899   *         - sequencer ranks
05900   *         This function is intended to be used when contexts queue is enabled,
05901   *         because the sequence must be fully configured in one time
05902   *         (functions to set separately injected trigger and sequencer channels
05903   *         cannot be used):
05904   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
05905   * @note   In the contexts queue, only the active context can be read.
05906   *         The parameters of this function can be read using functions:
05907   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
05908   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
05909   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
05910   * @note   On this STM32 series, to measure internal channels (VrefInt,
05911   *         TempSensor, ...), measurement paths to internal channels must be
05912   *         enabled separately.
05913   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
05914   * @note   On STM32G4, some fast channels are available: fast analog inputs
05915   *         coming from GPIO pads (ADC_IN1..5).
05916   * @note   On this STM32 series, setting of this feature is conditioned to
05917   *         ADC state:
05918   *         ADC must not be disabled. Can be enabled with or without conversion
05919   *         on going on either groups regular or injected.
05920   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
05921   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
05922   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
05923   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
05924   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
05925   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
05926   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
05927   * @param  ADCx ADC instance
05928   * @param  TriggerSource This parameter can be one of the following values:
05929   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
05930   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
05931   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
05932   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
05933   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
05934   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
05935   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
05936   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
05937   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
05938   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
05939   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
05940   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
05941   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
05942   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
05943   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
05944   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
05945   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
05946   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
05947   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
05948   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
05949   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
05950   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
05951   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
05952   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
05953   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
05954   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
05955   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
05956   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
05957   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
05958   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
05959   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
05960   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
05961   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
05962   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
05963   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
05964   *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
05965   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
05966   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
05967   *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
05968   *
05969   *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
05970   *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
05971   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
05972   *             more details.
05973   * @param  ExternalTriggerEdge This parameter can be one of the following values:
05974   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
05975   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
05976   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
05977   *
05978   *         Note: This parameter is discarded in case of SW start:
05979   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
05980   * @param  SequencerNbRanks This parameter can be one of the following values:
05981   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
05982   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
05983   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
05984   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
05985   * @param  Rank1_Channel This parameter can be one of the following values:
05986   *         @arg @ref LL_ADC_CHANNEL_0
05987   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
05988   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
05989   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
05990   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
05991   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
05992   *         @arg @ref LL_ADC_CHANNEL_6
05993   *         @arg @ref LL_ADC_CHANNEL_7
05994   *         @arg @ref LL_ADC_CHANNEL_8
05995   *         @arg @ref LL_ADC_CHANNEL_9
05996   *         @arg @ref LL_ADC_CHANNEL_10
05997   *         @arg @ref LL_ADC_CHANNEL_11
05998   *         @arg @ref LL_ADC_CHANNEL_12
05999   *         @arg @ref LL_ADC_CHANNEL_13
06000   *         @arg @ref LL_ADC_CHANNEL_14
06001   *         @arg @ref LL_ADC_CHANNEL_15
06002   *         @arg @ref LL_ADC_CHANNEL_16
06003   *         @arg @ref LL_ADC_CHANNEL_17
06004   *         @arg @ref LL_ADC_CHANNEL_18
06005   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06006   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06007   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06008   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06009   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06010   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06011   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06012   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06013   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06014   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06015   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06016   *
06017   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06018   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06019   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06020   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06021   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06022   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06023   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06024   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06025   *             for more details.
06026   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06027   *             convert in 12-bit resolution.
06028   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06029   *             (fADC) to convert in 12-bit resolution.\n
06030   * @param  Rank2_Channel This parameter can be one of the following values:
06031   *         @arg @ref LL_ADC_CHANNEL_0
06032   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
06033   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
06034   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
06035   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
06036   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
06037   *         @arg @ref LL_ADC_CHANNEL_6
06038   *         @arg @ref LL_ADC_CHANNEL_7
06039   *         @arg @ref LL_ADC_CHANNEL_8
06040   *         @arg @ref LL_ADC_CHANNEL_9
06041   *         @arg @ref LL_ADC_CHANNEL_10
06042   *         @arg @ref LL_ADC_CHANNEL_11
06043   *         @arg @ref LL_ADC_CHANNEL_12
06044   *         @arg @ref LL_ADC_CHANNEL_13
06045   *         @arg @ref LL_ADC_CHANNEL_14
06046   *         @arg @ref LL_ADC_CHANNEL_15
06047   *         @arg @ref LL_ADC_CHANNEL_16
06048   *         @arg @ref LL_ADC_CHANNEL_17
06049   *         @arg @ref LL_ADC_CHANNEL_18
06050   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06051   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06052   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06053   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06054   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06055   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06056   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06057   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06058   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06059   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06060   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06061   *
06062   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06063   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06064   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06065   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06066   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06067   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06068   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06069   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06070   *             for more details.
06071   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06072   *             convert in 12-bit resolution.
06073   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06074   *             (fADC) to convert in 12-bit resolution.\n
06075   * @param  Rank3_Channel This parameter can be one of the following values:
06076   *         @arg @ref LL_ADC_CHANNEL_0
06077   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
06078   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
06079   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
06080   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
06081   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
06082   *         @arg @ref LL_ADC_CHANNEL_6
06083   *         @arg @ref LL_ADC_CHANNEL_7
06084   *         @arg @ref LL_ADC_CHANNEL_8
06085   *         @arg @ref LL_ADC_CHANNEL_9
06086   *         @arg @ref LL_ADC_CHANNEL_10
06087   *         @arg @ref LL_ADC_CHANNEL_11
06088   *         @arg @ref LL_ADC_CHANNEL_12
06089   *         @arg @ref LL_ADC_CHANNEL_13
06090   *         @arg @ref LL_ADC_CHANNEL_14
06091   *         @arg @ref LL_ADC_CHANNEL_15
06092   *         @arg @ref LL_ADC_CHANNEL_16
06093   *         @arg @ref LL_ADC_CHANNEL_17
06094   *         @arg @ref LL_ADC_CHANNEL_18
06095   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06096   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06097   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06098   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06099   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06100   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06101   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06102   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06103   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06104   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06105   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06106   *
06107   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06108   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06109   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06110   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06111   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06112   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06113   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06114   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06115   *             for more details.
06116   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06117   *             convert in 12-bit resolution.
06118   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06119   *             (fADC) to convert in 12-bit resolution.\n
06120   * @param  Rank4_Channel This parameter can be one of the following values:
06121   *         @arg @ref LL_ADC_CHANNEL_0
06122   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
06123   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
06124   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
06125   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
06126   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
06127   *         @arg @ref LL_ADC_CHANNEL_6
06128   *         @arg @ref LL_ADC_CHANNEL_7
06129   *         @arg @ref LL_ADC_CHANNEL_8
06130   *         @arg @ref LL_ADC_CHANNEL_9
06131   *         @arg @ref LL_ADC_CHANNEL_10
06132   *         @arg @ref LL_ADC_CHANNEL_11
06133   *         @arg @ref LL_ADC_CHANNEL_12
06134   *         @arg @ref LL_ADC_CHANNEL_13
06135   *         @arg @ref LL_ADC_CHANNEL_14
06136   *         @arg @ref LL_ADC_CHANNEL_15
06137   *         @arg @ref LL_ADC_CHANNEL_16
06138   *         @arg @ref LL_ADC_CHANNEL_17
06139   *         @arg @ref LL_ADC_CHANNEL_18
06140   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06141   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06142   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06143   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06144   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06145   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06146   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06147   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06148   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06149   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06150   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06151   *
06152   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06153   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06154   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06155   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06156   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06157   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06158   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06159   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06160   *             for more details.
06161   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06162   *             convert in 12-bit resolution.
06163   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06164   *             (fADC) to convert in 12-bit resolution.\n
06165   * @retval None
06166   */
06167 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
06168                                                    uint32_t TriggerSource,
06169                                                    uint32_t ExternalTriggerEdge,
06170                                                    uint32_t SequencerNbRanks,
06171                                                    uint32_t Rank1_Channel,
06172                                                    uint32_t Rank2_Channel,
06173                                                    uint32_t Rank3_Channel,
06174                                                    uint32_t Rank4_Channel)
06175 {
06176   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
06177   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
06178   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
06179   /* because containing other bits reserved for other purpose.                */
06180   /* If parameter "TriggerSource" is set to SW start, then parameter          */
06181   /* "ExternalTriggerEdge" is discarded.                                      */
06182   uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
06183   MODIFY_REG(ADCx->JSQR,
06184              ADC_JSQR_JEXTSEL |
06185              ADC_JSQR_JEXTEN  |
06186              ADC_JSQR_JSQ4    |
06187              ADC_JSQR_JSQ3    |
06188              ADC_JSQR_JSQ2    |
06189              ADC_JSQR_JSQ1    |
06190              ADC_JSQR_JL,
06191              (TriggerSource & ADC_JSQR_JEXTSEL)          |
06192              (ExternalTriggerEdge * (is_trigger_not_sw)) |
06193              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
06194               << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
06195              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
06196               << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
06197              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
06198               << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
06199              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
06200               << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
06201              SequencerNbRanks
06202             );
06203 }
06204
06205 /**
06206   * @}
06207   */
06208
06209 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
06210   * @{
06211   */
06212
06213 /**
06214   * @brief  Set sampling time of the selected ADC channel
06215   *         Unit: ADC clock cycles.
06216   * @note   On this device, sampling time is on channel scope: independently
06217   *         of channel mapped on ADC group regular or injected.
06218   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
06219   *         converted:
06220   *         sampling time constraints must be respected (sampling time can be
06221   *         adjusted in function of ADC clock frequency and sampling time
06222   *         setting).
06223   *         Refer to device datasheet for timings values (parameters TS_vrefint,
06224   *         TS_temp, ...).
06225   * @note   Conversion time is the addition of sampling time and processing time.
06226   *         On this STM32 series, ADC processing time is:
06227   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
06228   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
06229   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
06230   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
06231   * @note   In case of ADC conversion of internal channel (VrefInt,
06232   *         temperature sensor, ...), a sampling time minimum value
06233   *         is required.
06234   *         Refer to device datasheet.
06235   * @note   On this STM32 series, setting of this feature is conditioned to
06236   *         ADC state:
06237   *         ADC must be disabled or enabled without conversion on going
06238   *         on either groups regular or injected.
06239   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
06240   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
06241   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
06242   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
06243   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
06244   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
06245   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
06246   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
06247   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
06248   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
06249   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
06250   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
06251   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
06252   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
06253   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
06254   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
06255   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
06256   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
06257   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
06258   * @param  ADCx ADC instance
06259   * @param  Channel This parameter can be one of the following values:
06260   *         @arg @ref LL_ADC_CHANNEL_0
06261   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
06262   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
06263   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
06264   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
06265   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
06266   *         @arg @ref LL_ADC_CHANNEL_6
06267   *         @arg @ref LL_ADC_CHANNEL_7
06268   *         @arg @ref LL_ADC_CHANNEL_8
06269   *         @arg @ref LL_ADC_CHANNEL_9
06270   *         @arg @ref LL_ADC_CHANNEL_10
06271   *         @arg @ref LL_ADC_CHANNEL_11
06272   *         @arg @ref LL_ADC_CHANNEL_12
06273   *         @arg @ref LL_ADC_CHANNEL_13
06274   *         @arg @ref LL_ADC_CHANNEL_14
06275   *         @arg @ref LL_ADC_CHANNEL_15
06276   *         @arg @ref LL_ADC_CHANNEL_16
06277   *         @arg @ref LL_ADC_CHANNEL_17
06278   *         @arg @ref LL_ADC_CHANNEL_18
06279   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06280   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06281   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06282   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06283   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06284   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06285   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06286   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06287   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06288   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06289   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06290   *
06291   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06292   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06293   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06294   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06295   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06296   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06297   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06298   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06299   *             for more details.
06300   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06301   *             convert in 12-bit resolution.
06302   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06303   *             (fADC) to convert in 12-bit resolution.\n
06304   * @param  SamplingTime This parameter can be one of the following values:
06305   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
06306   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
06307   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
06308   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
06309   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
06310   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
06311   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
06312   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
06313   *
06314   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
06315   *             can be replaced by 3.5 ADC clock cycles.
06316   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
06317   * @retval None
06318   */
06319 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
06320 {
06321   /* Set bits with content of parameter "SamplingTime" with bits position     */
06322   /* in register and register position depending on parameter "Channel".      */
06323   /* Parameter "Channel" is used with masks because containing                */
06324   /* other bits reserved for other purpose.                                   */
06325   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
06326                                              ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
06327
06328   MODIFY_REG(*preg,
06329              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
06330              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
06331 }
06332
06333 /**
06334   * @brief  Get sampling time of the selected ADC channel
06335   *         Unit: ADC clock cycles.
06336   * @note   On this device, sampling time is on channel scope: independently
06337   *         of channel mapped on ADC group regular or injected.
06338   * @note   Conversion time is the addition of sampling time and processing time.
06339   *         On this STM32 series, ADC processing time is:
06340   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
06341   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
06342   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
06343   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
06344   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
06345   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
06346   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
06347   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
06348   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
06349   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
06350   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
06351   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
06352   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
06353   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
06354   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
06355   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
06356   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
06357   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
06358   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
06359   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
06360   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
06361   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
06362   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
06363   * @param  ADCx ADC instance
06364   * @param  Channel This parameter can be one of the following values:
06365   *         @arg @ref LL_ADC_CHANNEL_0
06366   *         @arg @ref LL_ADC_CHANNEL_1                 (8)
06367   *         @arg @ref LL_ADC_CHANNEL_2                 (8)
06368   *         @arg @ref LL_ADC_CHANNEL_3                 (8)
06369   *         @arg @ref LL_ADC_CHANNEL_4                 (8)
06370   *         @arg @ref LL_ADC_CHANNEL_5                 (8)
06371   *         @arg @ref LL_ADC_CHANNEL_6
06372   *         @arg @ref LL_ADC_CHANNEL_7
06373   *         @arg @ref LL_ADC_CHANNEL_8
06374   *         @arg @ref LL_ADC_CHANNEL_9
06375   *         @arg @ref LL_ADC_CHANNEL_10
06376   *         @arg @ref LL_ADC_CHANNEL_11
06377   *         @arg @ref LL_ADC_CHANNEL_12
06378   *         @arg @ref LL_ADC_CHANNEL_13
06379   *         @arg @ref LL_ADC_CHANNEL_14
06380   *         @arg @ref LL_ADC_CHANNEL_15
06381   *         @arg @ref LL_ADC_CHANNEL_16
06382   *         @arg @ref LL_ADC_CHANNEL_17
06383   *         @arg @ref LL_ADC_CHANNEL_18
06384   *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
06385   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
06386   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
06387   *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
06388   *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
06389   *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
06390   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
06391   *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
06392   *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
06393   *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
06394   *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
06395   *
06396   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06397   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06398   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06399   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06400   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06401   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06402   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06403   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06404   *             for more details.
06405   *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
06406   *             convert in 12-bit resolution.
06407   *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
06408   *             (fADC) to convert in 12-bit resolution.\n
06409   * @retval Returned value can be one of the following values:
06410   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
06411   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
06412   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
06413   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
06414   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
06415   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
06416   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
06417   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
06418   *
06419   *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
06420   *             can be replaced by 3.5 ADC clock cycles.
06421   *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
06422   */
06423 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
06424 {
06425   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
06426                                                                  >> ADC_SMPRX_REGOFFSET_POS));
06427
06428   return (uint32_t)(READ_BIT(*preg,
06429                              ADC_SMPR1_SMP0
06430                              << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
06431                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
06432                    );
06433 }
06434
06435 /**
06436   * @brief  Set mode single-ended or differential input of the selected
06437   *         ADC channel.
06438   * @note   Channel ending is on channel scope: independently of channel mapped
06439   *         on ADC group regular or injected.
06440   *         In differential mode: Differential measurement is carried out
06441   *         between the selected channel 'i' (positive input) and
06442   *         channel 'i+1' (negative input). Only channel 'i' has to be
06443   *         configured, channel 'i+1' is configured automatically.
06444   * @note   Refer to Reference Manual to ensure the selected channel is
06445   *         available in differential mode.
06446   *         For example, internal channels (VrefInt, TempSensor, ...) are
06447   *         not available in differential mode.
06448   * @note   When configuring a channel 'i' in differential mode,
06449   *         the channel 'i+1' is not usable separately.
06450   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
06451   *         configuration:
06452   *         - ADC1: Channels 12, 15, 16, 17 and 18
06453   *         - ADC2: Channels 15, 17 and 18
06454   *         - ADC3: Channels 12, 16, 17 and 18            (1)
06455   *         - ADC4: Channels 16, 17 and 18                (1)
06456   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
06457   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
06458   *             for more details.
06459   * @note   For ADC channels configured in differential mode, both inputs
06460   *         should be biased at (Vref+)/2 +/-200mV.
06461   *         (Vref+ is the analog voltage reference)
06462   * @note   On this STM32 series, setting of this feature is conditioned to
06463   *         ADC state:
06464   *         ADC must be ADC disabled.
06465   * @note   One or several values can be selected.
06466   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
06467   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
06468   * @param  ADCx ADC instance
06469   * @param  Channel This parameter can be one of the following values:
06470   *         @arg @ref LL_ADC_CHANNEL_1
06471   *         @arg @ref LL_ADC_CHANNEL_2
06472   *         @arg @ref LL_ADC_CHANNEL_3
06473   *         @arg @ref LL_ADC_CHANNEL_4
06474   *         @arg @ref LL_ADC_CHANNEL_5
06475   *         @arg @ref LL_ADC_CHANNEL_6
06476   *         @arg @ref LL_ADC_CHANNEL_7
06477   *         @arg @ref LL_ADC_CHANNEL_8
06478   *         @arg @ref LL_ADC_CHANNEL_9
06479   *         @arg @ref LL_ADC_CHANNEL_10
06480   *         @arg @ref LL_ADC_CHANNEL_11
06481   *         @arg @ref LL_ADC_CHANNEL_12
06482   *         @arg @ref LL_ADC_CHANNEL_13
06483   *         @arg @ref LL_ADC_CHANNEL_14
06484   *         @arg @ref LL_ADC_CHANNEL_15
06485   * @param  SingleDiff This parameter can be a combination of the following values:
06486   *         @arg @ref LL_ADC_SINGLE_ENDED
06487   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
06488   * @retval None
06489   */
06490 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
06491 {
06492   /* Bits of channels in single or differential mode are set only for         */
06493   /* differential mode (for single mode, mask of bits allowed to be set is    */
06494   /* shifted out of range of bits of channels in single or differential mode. */
06495   MODIFY_REG(ADCx->DIFSEL,
06496              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
06497              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
06498              & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
06499 }
06500
06501 /**
06502   * @brief  Get mode single-ended or differential input of the selected
06503   *         ADC channel.
06504   * @note   When configuring a channel 'i' in differential mode,
06505   *         the channel 'i+1' is not usable separately.
06506   *         Therefore, to ensure a channel is configured in single-ended mode,
06507   *         the configuration of channel itself and the channel 'i-1' must be
06508   *         read back (to ensure that the selected channel channel has not been
06509   *         configured in differential mode by the previous channel).
06510   * @note   Refer to Reference Manual to ensure the selected channel is
06511   *         available in differential mode.
06512   *         For example, internal channels (VrefInt, TempSensor, ...) are
06513   *         not available in differential mode.
06514   * @note   When configuring a channel 'i' in differential mode,
06515   *         the channel 'i+1' is not usable separately.
06516   * @note   On STM32G4, some channels are internally fixed to single-ended inputs
06517   *         configuration:
06518   *         - ADC1: Channels 12, 15, 16, 17 and 18
06519   *         - ADC2: Channels 15, 17 and 18
06520   *         - ADC3: Channels 12, 16, 17 and 18            (1)
06521   *         - ADC4: Channels 16, 17 and 18                (1)
06522   *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
06523   *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
06524   *             for more details.
06525   * @note   One or several values can be selected. In this case, the value
06526   *         returned is null if all channels are in single ended-mode.
06527   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
06528   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
06529   * @param  ADCx ADC instance
06530   * @param  Channel This parameter can be a combination of the following values:
06531   *         @arg @ref LL_ADC_CHANNEL_1
06532   *         @arg @ref LL_ADC_CHANNEL_2
06533   *         @arg @ref LL_ADC_CHANNEL_3
06534   *         @arg @ref LL_ADC_CHANNEL_4
06535   *         @arg @ref LL_ADC_CHANNEL_5
06536   *         @arg @ref LL_ADC_CHANNEL_6
06537   *         @arg @ref LL_ADC_CHANNEL_7
06538   *         @arg @ref LL_ADC_CHANNEL_8
06539   *         @arg @ref LL_ADC_CHANNEL_9
06540   *         @arg @ref LL_ADC_CHANNEL_10
06541   *         @arg @ref LL_ADC_CHANNEL_11
06542   *         @arg @ref LL_ADC_CHANNEL_12
06543   *         @arg @ref LL_ADC_CHANNEL_13
06544   *         @arg @ref LL_ADC_CHANNEL_14
06545   *         @arg @ref LL_ADC_CHANNEL_15
06546   * @retval 0: channel in single-ended mode, else: channel in differential mode
06547   */
06548 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
06549 {
06550   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
06551 }
06552
06553 /**
06554   * @}
06555   */
06556
06557 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
06558   * @{
06559   */
06560
06561 /**
06562   * @brief  Set ADC analog watchdog monitored channels:
06563   *         a single channel, multiple channels or all channels,
06564   *         on ADC groups regular and-or injected.
06565   * @note   Once monitored channels are selected, analog watchdog
06566   *         is enabled.
06567   * @note   In case of need to define a single channel to monitor
06568   *         with analog watchdog from sequencer channel definition,
06569   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
06570   * @note   On this STM32 series, there are 2 kinds of analog watchdog
06571   *         instance:
06572   *         - AWD standard (instance AWD1):
06573   *           - channels monitored: can monitor 1 channel or all channels.
06574   *           - groups monitored: ADC groups regular and-or injected.
06575   *           - resolution: resolution is not limited (corresponds to
06576   *             ADC resolution configured).
06577   *         - AWD flexible (instances AWD2, AWD3):
06578   *           - channels monitored: flexible on channels monitored, selection is
06579   *             channel wise, from from 1 to all channels.
06580   *             Specificity of this analog watchdog: Multiple channels can
06581   *             be selected. For example:
06582   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
06583   *           - groups monitored: not selection possible (monitoring on both
06584   *             groups regular and injected).
06585   *             Channels selected are monitored on groups regular and injected:
06586   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
06587   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
06588   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
06589   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
06590   *             the 2 LSB are ignored.
06591   * @note   On this STM32 series, setting of this feature is conditioned to
06592   *         ADC state:
06593   *         ADC must be disabled or enabled without conversion on going
06594   *         on either groups regular or injected.
06595   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
06596   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
06597   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
06598   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
06599   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
06600   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
06601   * @param  ADCx ADC instance
06602   * @param  AWDy This parameter can be one of the following values:
06603   *         @arg @ref LL_ADC_AWD1
06604   *         @arg @ref LL_ADC_AWD2
06605   *         @arg @ref LL_ADC_AWD3
06606   * @param  AWDChannelGroup This parameter can be one of the following values:
06607   *         @arg @ref LL_ADC_AWD_DISABLE
06608   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
06609   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
06610   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
06611   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
06612   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
06613   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
06614   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
06615   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
06616   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
06617   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
06618   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
06619   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
06620   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
06621   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
06622   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
06623   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
06624   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
06625   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
06626   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
06627   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
06628   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
06629   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
06630   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
06631   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
06632   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
06633   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
06634   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
06635   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
06636   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
06637   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
06638   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
06639   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
06640   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
06641   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
06642   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
06643   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
06644   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
06645   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
06646   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
06647   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
06648   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
06649   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
06650   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
06651   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
06652   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
06653   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
06654   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
06655   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
06656   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
06657   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
06658   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
06659   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
06660   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
06661   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
06662   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
06663   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
06664   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
06665   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
06666   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
06667   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
06668   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
06669   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
06670   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
06671   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
06672   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
06673   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
06674   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
06675   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
06676   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
06677   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
06678   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
06679   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
06680   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
06681   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
06682   *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
06683   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
06684   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
06685   *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
06686   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
06687   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
06688   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
06689   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
06690   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
06691   *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
06692   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
06693   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
06694   *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
06695   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
06696   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
06697   *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
06698   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
06699   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
06700   *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
06701   *
06702   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
06703   *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
06704   *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
06705   *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
06706   *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
06707   *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
06708   *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
06709   *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
06710   *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
06711   *             for more details.
06712   * @retval None
06713   */
06714 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
06715 {
06716   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
06717   /* in register and register position depending on parameter "AWDy".         */
06718   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
06719   /* containing other bits reserved for other purpose.                        */
06720   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
06721                                              ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
06722                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
06723                                                 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
06724
06725   MODIFY_REG(*preg,
06726              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
06727              AWDChannelGroup & AWDy);
06728 }
06729
06730 /**
06731   * @brief  Get ADC analog watchdog monitored channel.
06732   * @note   Usage of the returned channel number:
06733   *         - To reinject this channel into another function LL_ADC_xxx:
06734   *           the returned channel number is only partly formatted on definition
06735   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
06736   *           with parts of literals LL_ADC_CHANNEL_x or using
06737   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
06738   *           Then the selected literal LL_ADC_CHANNEL_x can be used
06739   *           as parameter for another function.
06740   *         - To get the channel number in decimal format:
06741   *           process the returned value with the helper macro
06742   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
06743   *           Applicable only when the analog watchdog is set to monitor
06744   *           one channel.
06745   * @note   On this STM32 series, there are 2 kinds of analog watchdog
06746   *         instance:
06747   *         - AWD standard (instance AWD1):
06748   *           - channels monitored: can monitor 1 channel or all channels.
06749   *           - groups monitored: ADC groups regular and-or injected.
06750   *           - resolution: resolution is not limited (corresponds to
06751   *             ADC resolution configured).
06752   *         - AWD flexible (instances AWD2, AWD3):
06753   *           - channels monitored: flexible on channels monitored, selection is
06754   *             channel wise, from from 1 to all channels.
06755   *             Specificity of this analog watchdog: Multiple channels can
06756   *             be selected. For example:
06757   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
06758   *           - groups monitored: not selection possible (monitoring on both
06759   *             groups regular and injected).
06760   *             Channels selected are monitored on groups regular and injected:
06761   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
06762   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
06763   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
06764   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
06765   *             the 2 LSB are ignored.
06766   * @note   On this STM32 series, setting of this feature is conditioned to
06767   *         ADC state:
06768   *         ADC must be disabled or enabled without conversion on going
06769   *         on either groups regular or injected.
06770   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
06771   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
06772   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
06773   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
06774   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
06775   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
06776   * @param  ADCx ADC instance
06777   * @param  AWDy This parameter can be one of the following values:
06778   *         @arg @ref LL_ADC_AWD1
06779   *         @arg @ref LL_ADC_AWD2 (1)
06780   *         @arg @ref LL_ADC_AWD3 (1)
06781   *
06782   *         (1) On this AWD number, monitored channel can be retrieved
06783   *             if only 1 channel is programmed (or none or all channels).
06784   *             This function cannot retrieve monitored channel if
06785   *             multiple channels are programmed simultaneously
06786   *             by bitfield.
06787   * @retval Returned value can be one of the following values:
06788   *         @arg @ref LL_ADC_AWD_DISABLE
06789   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
06790   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
06791   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
06792   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
06793   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
06794   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
06795   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
06796   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
06797   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
06798   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
06799   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
06800   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
06801   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
06802   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
06803   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
06804   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
06805   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
06806   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
06807   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
06808   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
06809   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
06810   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
06811   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
06812   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
06813   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
06814   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
06815   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
06816   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
06817   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
06818   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
06819   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
06820   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
06821   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
06822   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
06823   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
06824   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
06825   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
06826   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
06827   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
06828   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
06829   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
06830   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
06831   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
06832   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
06833   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
06834   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
06835   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
06836   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
06837   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
06838   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
06839   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
06840   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
06841   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
06842   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
06843   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
06844   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
06845   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
06846   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
06847   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
06848   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
06849   *
06850   *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
06851   */
06852 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
06853 {
06854   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
06855                                                    ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
06856                                                    + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
06857                                                       * ADC_AWD_CR12_REGOFFSETGAP_VAL));
06858
06859   uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
06860
06861   /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled       */
06862   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
06863   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
06864   /* or a single channel.                                                     */
06865   if (analog_wd_monit_channels != 0UL)
06866   {
06867     if (AWDy == LL_ADC_AWD1)
06868     {
06869       if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
06870       {
06871         /* AWD monitoring a group of channels */
06872         analog_wd_monit_channels = ((analog_wd_monit_channels
06873                                      | (ADC_AWD_CR23_CHANNEL_MASK)
06874                                     )
06875                                     & (~(ADC_CFGR_AWD1CH))
06876                                    );
06877       }
06878       else
06879       {
06880         /* AWD monitoring a single channel */
06881         analog_wd_monit_channels = (analog_wd_monit_channels
06882                                     | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
06883                                    );
06884       }
06885     }
06886     else
06887     {
06888       if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
06889       {
06890         /* AWD monitoring a group of channels */
06891         analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
06892                                     | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
06893                                    );
06894       }
06895       else
06896       {
06897         /* AWD monitoring a single channel */
06898         /* AWD monitoring a group of channels */
06899         analog_wd_monit_channels = (analog_wd_monit_channels
06900                                     | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
06901                                     | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
06902                                    );
06903       }
06904     }
06905   }
06906
06907   return analog_wd_monit_channels;
06908 }
06909
06910 /**
06911   * @brief  Set ADC analog watchdog thresholds value of both thresholds
06912   *         high and low.
06913   * @note   If value of only one threshold high or low must be set,
06914   *         use function @ref LL_ADC_SetAnalogWDThresholds().
06915   * @note   In case of ADC resolution different of 12 bits,
06916   *         analog watchdog thresholds data require a specific shift.
06917   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
06918   * @note   On this STM32 series, there are 2 kinds of analog watchdog
06919   *         instance:
06920   *         - AWD standard (instance AWD1):
06921   *           - channels monitored: can monitor 1 channel or all channels.
06922   *           - groups monitored: ADC groups regular and-or injected.
06923   *           - resolution: resolution is not limited (corresponds to
06924   *             ADC resolution configured).
06925   *         - AWD flexible (instances AWD2, AWD3):
06926   *           - channels monitored: flexible on channels monitored, selection is
06927   *             channel wise, from from 1 to all channels.
06928   *             Specificity of this analog watchdog: Multiple channels can
06929   *             be selected. For example:
06930   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
06931   *           - groups monitored: not selection possible (monitoring on both
06932   *             groups regular and injected).
06933   *             Channels selected are monitored on groups regular and injected:
06934   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
06935   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
06936   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
06937   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
06938   *             the 2 LSB are ignored.
06939   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
06940   *         impacted: the comparison of analog watchdog thresholds is done on
06941   *         oversampling final computation (after ratio and shift application):
06942   *         ADC data register bitfield [15:4] (12 most significant bits).
06943   *         Examples:
06944   *         - Oversampling ratio and shift selected to have ADC conversion data
06945   *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
06946   *           ADC analog watchdog thresholds must be divided by 16.
06947   *         - Oversampling ratio and shift selected to have ADC conversion data
06948   *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
06949   *           ADC analog watchdog thresholds must be divided by 4.
06950   *         - Oversampling ratio and shift selected to have ADC conversion data
06951   *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
06952   *           ADC analog watchdog thresholds match directly to ADC data register.
06953   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
06954   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
06955   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
06956   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
06957   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
06958   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
06959   * @param  ADCx ADC instance
06960   * @param  AWDy This parameter can be one of the following values:
06961   *         @arg @ref LL_ADC_AWD1
06962   *         @arg @ref LL_ADC_AWD2
06963   *         @arg @ref LL_ADC_AWD3
06964   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
06965   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
06966   * @retval None
06967   */
06968 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
06969                                                      uint32_t AWDThresholdLowValue)
06970 {
06971   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
06972   /* position in register and register position depending on parameter        */
06973   /* "AWDy".                                                                  */
06974   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
06975   /* containing other bits reserved for other purpose.                        */
06976   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
06977                                              ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
06978
06979   MODIFY_REG(*preg,
06980              ADC_TR1_HT1 | ADC_TR1_LT1,
06981              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
06982 }
06983
06984 /**
06985   * @brief  Set ADC analog watchdog threshold value of threshold
06986   *         high or low.
06987   * @note   If values of both thresholds high or low must be set,
06988   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
06989   * @note   In case of ADC resolution different of 12 bits,
06990   *         analog watchdog thresholds data require a specific shift.
06991   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
06992   * @note   On this STM32 series, there are 2 kinds of analog watchdog
06993   *         instance:
06994   *         - AWD standard (instance AWD1):
06995   *           - channels monitored: can monitor 1 channel or all channels.
06996   *           - groups monitored: ADC groups regular and-or injected.
06997   *           - resolution: resolution is not limited (corresponds to
06998   *             ADC resolution configured).
06999   *         - AWD flexible (instances AWD2, AWD3):
07000   *           - channels monitored: flexible on channels monitored, selection is
07001   *             channel wise, from from 1 to all channels.
07002   *             Specificity of this analog watchdog: Multiple channels can
07003   *             be selected. For example:
07004   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
07005   *           - groups monitored: not selection possible (monitoring on both
07006   *             groups regular and injected).
07007   *             Channels selected are monitored on groups regular and injected:
07008   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
07009   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
07010   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
07011   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
07012   *             the 2 LSB are ignored.
07013   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
07014   *         impacted: the comparison of analog watchdog thresholds is done on
07015   *         oversampling final computation (after ratio and shift application):
07016   *         ADC data register bitfield [15:4] (12 most significant bits).
07017   *         Examples:
07018   *         - Oversampling ratio and shift selected to have ADC conversion data
07019   *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
07020   *           ADC analog watchdog thresholds must be divided by 16.
07021   *         - Oversampling ratio and shift selected to have ADC conversion data
07022   *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
07023   *           ADC analog watchdog thresholds must be divided by 4.
07024   *         - Oversampling ratio and shift selected to have ADC conversion data
07025   *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
07026   *           ADC analog watchdog thresholds match directly to ADC data register.
07027   * @note   On this STM32 series, setting of this feature is not conditioned to
07028   *         ADC state:
07029   *         ADC can be disabled, enabled with or without conversion on going
07030   *         on either ADC groups regular or injected.
07031   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
07032   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
07033   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
07034   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
07035   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
07036   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
07037   * @param  ADCx ADC instance
07038   * @param  AWDy This parameter can be one of the following values:
07039   *         @arg @ref LL_ADC_AWD1
07040   *         @arg @ref LL_ADC_AWD2
07041   *         @arg @ref LL_ADC_AWD3
07042   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
07043   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
07044   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
07045   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
07046   * @retval None
07047   */
07048 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
07049                                                   uint32_t AWDThresholdValue)
07050 {
07051   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
07052   /* position in register and register position depending on parameters       */
07053   /* "AWDThresholdsHighLow" and "AWDy".                                       */
07054   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
07055   /* containing other bits reserved for other purpose.                        */
07056   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
07057                                              ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
07058
07059   MODIFY_REG(*preg,
07060              AWDThresholdsHighLow,
07061              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
07062 }
07063
07064 /**
07065   * @brief  Get ADC analog watchdog threshold value of threshold high,
07066   *         threshold low or raw data with ADC thresholds high and low
07067   *         concatenated.
07068   * @note   If raw data with ADC thresholds high and low is retrieved,
07069   *         the data of each threshold high or low can be isolated
07070   *         using helper macro:
07071   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
07072   * @note   In case of ADC resolution different of 12 bits,
07073   *         analog watchdog thresholds data require a specific shift.
07074   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
07075   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
07076   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
07077   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
07078   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
07079   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
07080   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
07081   * @param  ADCx ADC instance
07082   * @param  AWDy This parameter can be one of the following values:
07083   *         @arg @ref LL_ADC_AWD1
07084   *         @arg @ref LL_ADC_AWD2
07085   *         @arg @ref LL_ADC_AWD3
07086   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
07087   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
07088   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
07089   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
07090   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
07091   */
07092 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
07093                                                       uint32_t AWDy, uint32_t AWDThresholdsHighLow)
07094 {
07095   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
07096                                                    ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
07097
07098   return (uint32_t)(READ_BIT(*preg,
07099                              (AWDThresholdsHighLow | ADC_TR1_LT1))
07100                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
07101                         & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
07102 }
07103
07104 /**
07105   * @brief  Set ADC analog watchdog filtering configuration
07106   * @note   On this STM32 series, setting of this feature is conditioned to
07107   *         ADC state:
07108   *         ADC must be disabled or enabled without conversion on going
07109   *         on either groups regular or injected.
07110   * @note   On this STM32 series, this feature is only available on first
07111   *         analog watchdog (AWD1)
07112   * @rmtoll TR1      AWDFILT        LL_ADC_SetAWDFilteringConfiguration
07113   * @param  ADCx ADC instance
07114   * @param  AWDy This parameter can be one of the following values:
07115   *         @arg @ref LL_ADC_AWD1
07116   * @param  FilteringConfig This parameter can be one of the following values:
07117   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
07118   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
07119   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
07120   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
07121   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
07122   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
07123   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
07124   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
07125   * @retval None
07126   */
07127 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
07128 {
07129   /* Prevent unused argument(s) compilation warning */
07130   (void)(AWDy);
07131   MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
07132 }
07133
07134 /**
07135   * @brief  Get ADC analog watchdog filtering configuration
07136   * @note   On this STM32 series, this feature is only available on first
07137   *         analog watchdog (AWD1)
07138   * @rmtoll TR1      AWDFILT        LL_ADC_GetAWDFilteringConfiguration
07139   * @param  ADCx ADC instance
07140   * @param  AWDy This parameter can be one of the following values:
07141   *         @arg @ref LL_ADC_AWD1
07142   * @retval Returned value can be:
07143   *         @arg @ref LL_ADC_AWD_FILTERING_NONE
07144   *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
07145   *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
07146   *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
07147   *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
07148   *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
07149   *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
07150   *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
07151   */
07152 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
07153 {
07154   /* Prevent unused argument(s) compilation warning */
07155   (void)(AWDy);
07156   return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
07157 }
07158
07159 /**
07160   * @}
07161   */
07162
07163 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
07164   * @{
07165   */
07166
07167 /**
07168   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
07169   *         (availability of ADC group injected depends on STM32 series).
07170   * @note   If both groups regular and injected are selected,
07171   *         specify behavior of ADC group injected interrupting
07172   *         group regular: when ADC group injected is triggered,
07173   *         the oversampling on ADC group regular is either
07174   *         temporary stopped and continued, or resumed from start
07175   *         (oversampler buffer reset).
07176   * @note   On this STM32 series, setting of this feature is conditioned to
07177   *         ADC state:
07178   *         ADC must be disabled or enabled without conversion on going
07179   *         on either groups regular or injected.
07180   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
07181   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
07182   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
07183   * @param  ADCx ADC instance
07184   * @param  OvsScope This parameter can be one of the following values:
07185   *         @arg @ref LL_ADC_OVS_DISABLE
07186   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
07187   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
07188   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
07189   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
07190   * @retval None
07191   */
07192 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
07193 {
07194   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
07195 }
07196
07197 /**
07198   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
07199   *         (availability of ADC group injected depends on STM32 series).
07200   * @note   If both groups regular and injected are selected,
07201   *         specify behavior of ADC group injected interrupting
07202   *         group regular: when ADC group injected is triggered,
07203   *         the oversampling on ADC group regular is either
07204   *         temporary stopped and continued, or resumed from start
07205   *         (oversampler buffer reset).
07206   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
07207   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
07208   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
07209   * @param  ADCx ADC instance
07210   * @retval Returned value can be one of the following values:
07211   *         @arg @ref LL_ADC_OVS_DISABLE
07212   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
07213   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
07214   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
07215   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
07216   */
07217 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
07218 {
07219   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
07220 }
07221
07222 /**
07223   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
07224   *         on the selected ADC group.
07225   * @note   Number of oversampled conversions are done either in:
07226   *         - continuous mode (all conversions of oversampling ratio
07227   *           are done from 1 trigger)
07228   *         - discontinuous mode (each conversion of oversampling ratio
07229   *           needs a trigger)
07230   * @note   On this STM32 series, setting of this feature is conditioned to
07231   *         ADC state:
07232   *         ADC must be disabled or enabled without conversion on going
07233   *         on group regular.
07234   * @note   On this STM32 series, oversampling discontinuous mode
07235   *         (triggered mode) can be used only when oversampling is
07236   *         set on group regular only and in resumed mode.
07237   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
07238   * @param  ADCx ADC instance
07239   * @param  OverSamplingDiscont This parameter can be one of the following values:
07240   *         @arg @ref LL_ADC_OVS_REG_CONT
07241   *         @arg @ref LL_ADC_OVS_REG_DISCONT
07242   * @retval None
07243   */
07244 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
07245 {
07246   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
07247 }
07248
07249 /**
07250   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
07251   *         on the selected ADC group.
07252   * @note   Number of oversampled conversions are done either in:
07253   *         - continuous mode (all conversions of oversampling ratio
07254   *           are done from 1 trigger)
07255   *         - discontinuous mode (each conversion of oversampling ratio
07256   *           needs a trigger)
07257   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
07258   * @param  ADCx ADC instance
07259   * @retval Returned value can be one of the following values:
07260   *         @arg @ref LL_ADC_OVS_REG_CONT
07261   *         @arg @ref LL_ADC_OVS_REG_DISCONT
07262   */
07263 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
07264 {
07265   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
07266 }
07267
07268 /**
07269   * @brief  Set ADC oversampling
07270   *         (impacting both ADC groups regular and injected)
07271   * @note   This function set the 2 items of oversampling configuration:
07272   *         - ratio
07273   *         - shift
07274   * @note   On this STM32 series, setting of this feature is conditioned to
07275   *         ADC state:
07276   *         ADC must be disabled or enabled without conversion on going
07277   *         on either groups regular or injected.
07278   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
07279   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
07280   * @param  ADCx ADC instance
07281   * @param  Ratio This parameter can be one of the following values:
07282   *         @arg @ref LL_ADC_OVS_RATIO_2
07283   *         @arg @ref LL_ADC_OVS_RATIO_4
07284   *         @arg @ref LL_ADC_OVS_RATIO_8
07285   *         @arg @ref LL_ADC_OVS_RATIO_16
07286   *         @arg @ref LL_ADC_OVS_RATIO_32
07287   *         @arg @ref LL_ADC_OVS_RATIO_64
07288   *         @arg @ref LL_ADC_OVS_RATIO_128
07289   *         @arg @ref LL_ADC_OVS_RATIO_256
07290   * @param  Shift This parameter can be one of the following values:
07291   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
07292   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
07293   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
07294   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
07295   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
07296   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
07297   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
07298   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
07299   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
07300   * @retval None
07301   */
07302 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
07303 {
07304   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
07305 }
07306
07307 /**
07308   * @brief  Get ADC oversampling ratio
07309   *        (impacting both ADC groups regular and injected)
07310   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
07311   * @param  ADCx ADC instance
07312   * @retval Ratio This parameter can be one of the following values:
07313   *         @arg @ref LL_ADC_OVS_RATIO_2
07314   *         @arg @ref LL_ADC_OVS_RATIO_4
07315   *         @arg @ref LL_ADC_OVS_RATIO_8
07316   *         @arg @ref LL_ADC_OVS_RATIO_16
07317   *         @arg @ref LL_ADC_OVS_RATIO_32
07318   *         @arg @ref LL_ADC_OVS_RATIO_64
07319   *         @arg @ref LL_ADC_OVS_RATIO_128
07320   *         @arg @ref LL_ADC_OVS_RATIO_256
07321   */
07322 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
07323 {
07324   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
07325 }
07326
07327 /**
07328   * @brief  Get ADC oversampling shift
07329   *        (impacting both ADC groups regular and injected)
07330   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
07331   * @param  ADCx ADC instance
07332   * @retval Shift This parameter can be one of the following values:
07333   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
07334   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
07335   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
07336   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
07337   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
07338   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
07339   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
07340   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
07341   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
07342   */
07343 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
07344 {
07345   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
07346 }
07347
07348 /**
07349   * @}
07350   */
07351
07352 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
07353   * @{
07354   */
07355
07356 #if defined(ADC_MULTIMODE_SUPPORT)
07357 /**
07358   * @brief  Set ADC multimode configuration to operate in independent mode
07359   *         or multimode (for devices with several ADC instances).
07360   * @note   If multimode configuration: the selected ADC instance is
07361   *         either master or slave depending on hardware.
07362   *         Refer to reference manual.
07363   * @note   On this STM32 series, setting of this feature is conditioned to
07364   *         ADC state:
07365   *         All ADC instances of the ADC common group must be disabled.
07366   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
07367   *         ADC instance or by using helper macro
07368   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
07369   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
07370   * @param  ADCxy_COMMON ADC common instance
07371   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07372   * @param  Multimode This parameter can be one of the following values:
07373   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
07374   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
07375   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
07376   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
07377   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
07378   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
07379   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
07380   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
07381   * @retval None
07382   */
07383 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
07384 {
07385   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
07386 }
07387
07388 /**
07389   * @brief  Get ADC multimode configuration to operate in independent mode
07390   *         or multimode (for devices with several ADC instances).
07391   * @note   If multimode configuration: the selected ADC instance is
07392   *         either master or slave depending on hardware.
07393   *         Refer to reference manual.
07394   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
07395   * @param  ADCxy_COMMON ADC common instance
07396   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07397   * @retval Returned value can be one of the following values:
07398   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
07399   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
07400   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
07401   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
07402   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
07403   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
07404   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
07405   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
07406   */
07407 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
07408 {
07409   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
07410 }
07411
07412 /**
07413   * @brief  Set ADC multimode conversion data transfer: no transfer
07414   *         or transfer by DMA.
07415   * @note   If ADC multimode transfer by DMA is not selected:
07416   *         each ADC uses its own DMA channel, with its individual
07417   *         DMA transfer settings.
07418   *         If ADC multimode transfer by DMA is selected:
07419   *         One DMA channel is used for both ADC (DMA of ADC master)
07420   *         Specifies the DMA requests mode:
07421   *         - Limited mode (One shot mode): DMA transfer requests are stopped
07422   *           when number of DMA data transfers (number of
07423   *           ADC conversions) is reached.
07424   *           This ADC mode is intended to be used with DMA mode non-circular.
07425   *         - Unlimited mode: DMA transfer requests are unlimited,
07426   *           whatever number of DMA data transfers (number of
07427   *           ADC conversions).
07428   *           This ADC mode is intended to be used with DMA mode circular.
07429   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
07430   *         mode non-circular:
07431   *         when DMA transfers size will be reached, DMA will stop transfers of
07432   *         ADC conversions data ADC will raise an overrun error
07433   *         (overrun flag and interruption if enabled).
07434   * @note   How to retrieve multimode conversion data:
07435   *         Whatever multimode transfer by DMA setting: using function
07436   *         @ref LL_ADC_REG_ReadMultiConversionData32().
07437   *         If ADC multimode transfer by DMA is selected: conversion data
07438   *         is a raw data with ADC master and slave concatenated.
07439   *         A macro is available to get the conversion data of
07440   *         ADC master or ADC slave: see helper macro
07441   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
07442   * @note   On this STM32 series, setting of this feature is conditioned to
07443   *         ADC state:
07444   *         All ADC instances of the ADC common group must be disabled
07445   *         or enabled without conversion on going on group regular.
07446   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
07447   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
07448   * @param  ADCxy_COMMON ADC common instance
07449   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07450   * @param  MultiDMATransfer This parameter can be one of the following values:
07451   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
07452   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
07453   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
07454   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
07455   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
07456   * @retval None
07457   */
07458 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
07459 {
07460   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
07461 }
07462
07463 /**
07464   * @brief  Get ADC multimode conversion data transfer: no transfer
07465   *         or transfer by DMA.
07466   * @note   If ADC multimode transfer by DMA is not selected:
07467   *         each ADC uses its own DMA channel, with its individual
07468   *         DMA transfer settings.
07469   *         If ADC multimode transfer by DMA is selected:
07470   *         One DMA channel is used for both ADC (DMA of ADC master)
07471   *         Specifies the DMA requests mode:
07472   *         - Limited mode (One shot mode): DMA transfer requests are stopped
07473   *           when number of DMA data transfers (number of
07474   *           ADC conversions) is reached.
07475   *           This ADC mode is intended to be used with DMA mode non-circular.
07476   *         - Unlimited mode: DMA transfer requests are unlimited,
07477   *           whatever number of DMA data transfers (number of
07478   *           ADC conversions).
07479   *           This ADC mode is intended to be used with DMA mode circular.
07480   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
07481   *         mode non-circular:
07482   *         when DMA transfers size will be reached, DMA will stop transfers of
07483   *         ADC conversions data ADC will raise an overrun error
07484   *         (overrun flag and interruption if enabled).
07485   * @note   How to retrieve multimode conversion data:
07486   *         Whatever multimode transfer by DMA setting: using function
07487   *         @ref LL_ADC_REG_ReadMultiConversionData32().
07488   *         If ADC multimode transfer by DMA is selected: conversion data
07489   *         is a raw data with ADC master and slave concatenated.
07490   *         A macro is available to get the conversion data of
07491   *         ADC master or ADC slave: see helper macro
07492   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
07493   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
07494   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
07495   * @param  ADCxy_COMMON ADC common instance
07496   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07497   * @retval Returned value can be one of the following values:
07498   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
07499   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
07500   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
07501   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
07502   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
07503   */
07504 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
07505 {
07506   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
07507 }
07508
07509 /**
07510   * @brief  Set ADC multimode delay between 2 sampling phases.
07511   * @note   The sampling delay range depends on ADC resolution:
07512   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
07513   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
07514   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
07515   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
07516   * @note   On this STM32 series, setting of this feature is conditioned to
07517   *         ADC state:
07518   *         All ADC instances of the ADC common group must be disabled.
07519   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
07520   *         ADC instance or by using helper macro helper macro
07521   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
07522   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
07523   * @param  ADCxy_COMMON ADC common instance
07524   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07525   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
07526   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
07527   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
07528   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
07529   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
07530   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
07531   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
07532   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
07533   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
07534   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
07535   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
07536   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
07537   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
07538   *
07539   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
07540   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
07541   *         (3) Parameter available only if ADC resolution is 12 bits.
07542   * @retval None
07543   */
07544 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
07545 {
07546   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
07547 }
07548
07549 /**
07550   * @brief  Get ADC multimode delay between 2 sampling phases.
07551   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
07552   * @param  ADCxy_COMMON ADC common instance
07553   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
07554   * @retval Returned value can be one of the following values:
07555   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
07556   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
07557   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
07558   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
07559   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
07560   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
07561   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
07562   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
07563   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
07564   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
07565   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
07566   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
07567   *
07568   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
07569   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
07570   *         (3) Parameter available only if ADC resolution is 12 bits.
07571   */
07572 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
07573 {
07574   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
07575 }
07576 #endif /* ADC_MULTIMODE_SUPPORT */
07577
07578 /**
07579   * @}
07580   */
07581 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
07582   * @{
07583   */
07584
07585 /**
07586   * @brief  Put ADC instance in deep power down state.
07587   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
07588   *         state, the internal analog calibration is lost. After exiting from
07589   *         deep power down, calibration must be relaunched or calibration factor
07590   *         (preliminarily saved) must be set back into calibration register.
07591   * @note   On this STM32 series, setting of this feature is conditioned to
07592   *         ADC state:
07593   *         ADC must be ADC disabled.
07594   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
07595   * @param  ADCx ADC instance
07596   * @retval None
07597   */
07598 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
07599 {
07600   /* Note: Write register with some additional bits forced to state reset     */
07601   /*       instead of modifying only the selected bit for this function,      */
07602   /*       to not interfere with bits with HW property "rs".                  */
07603   MODIFY_REG(ADCx->CR,
07604              ADC_CR_BITS_PROPERTY_RS,
07605              ADC_CR_DEEPPWD);
07606 }
07607
07608 /**
07609   * @brief  Disable ADC deep power down mode.
07610   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
07611   *         state, the internal analog calibration is lost. After exiting from
07612   *         deep power down, calibration must be relaunched or calibration factor
07613   *         (preliminarily saved) must be set back into calibration register.
07614   * @note   On this STM32 series, setting of this feature is conditioned to
07615   *         ADC state:
07616   *         ADC must be ADC disabled.
07617   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
07618   * @param  ADCx ADC instance
07619   * @retval None
07620   */
07621 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
07622 {
07623   /* Note: Write register with some additional bits forced to state reset     */
07624   /*       instead of modifying only the selected bit for this function,      */
07625   /*       to not interfere with bits with HW property "rs".                  */
07626   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
07627 }
07628
07629 /**
07630   * @brief  Get the selected ADC instance deep power down state.
07631   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
07632   * @param  ADCx ADC instance
07633   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
07634   */
07635 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
07636 {
07637   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
07638 }
07639
07640 /**
07641   * @brief  Enable ADC instance internal voltage regulator.
07642   * @note   On this STM32 series, after ADC internal voltage regulator enable,
07643   *         a delay for ADC internal voltage regulator stabilization
07644   *         is required before performing a ADC calibration or ADC enable.
07645   *         Refer to device datasheet, parameter tADCVREG_STUP.
07646   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
07647   * @note   On this STM32 series, setting of this feature is conditioned to
07648   *         ADC state:
07649   *         ADC must be ADC disabled.
07650   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
07651   * @param  ADCx ADC instance
07652   * @retval None
07653   */
07654 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
07655 {
07656   /* Note: Write register with some additional bits forced to state reset     */
07657   /*       instead of modifying only the selected bit for this function,      */
07658   /*       to not interfere with bits with HW property "rs".                  */
07659   MODIFY_REG(ADCx->CR,
07660              ADC_CR_BITS_PROPERTY_RS,
07661              ADC_CR_ADVREGEN);
07662 }
07663
07664 /**
07665   * @brief  Disable ADC internal voltage regulator.
07666   * @note   On this STM32 series, setting of this feature is conditioned to
07667   *         ADC state:
07668   *         ADC must be ADC disabled.
07669   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
07670   * @param  ADCx ADC instance
07671   * @retval None
07672   */
07673 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
07674 {
07675   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
07676 }
07677
07678 /**
07679   * @brief  Get the selected ADC instance internal voltage regulator state.
07680   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
07681   * @param  ADCx ADC instance
07682   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
07683   */
07684 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
07685 {
07686   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
07687 }
07688
07689 /**
07690   * @brief  Enable the selected ADC instance.
07691   * @note   On this STM32 series, after ADC enable, a delay for
07692   *         ADC internal analog stabilization is required before performing a
07693   *         ADC conversion start.
07694   *         Refer to device datasheet, parameter tSTAB.
07695   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
07696   *         is enabled and when conversion clock is active.
07697   *         (not only core clock: this ADC has a dual clock domain)
07698   * @note   On this STM32 series, setting of this feature is conditioned to
07699   *         ADC state:
07700   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
07701   * @rmtoll CR       ADEN           LL_ADC_Enable
07702   * @param  ADCx ADC instance
07703   * @retval None
07704   */
07705 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
07706 {
07707   /* Note: Write register with some additional bits forced to state reset     */
07708   /*       instead of modifying only the selected bit for this function,      */
07709   /*       to not interfere with bits with HW property "rs".                  */
07710   MODIFY_REG(ADCx->CR,
07711              ADC_CR_BITS_PROPERTY_RS,
07712              ADC_CR_ADEN);
07713 }
07714
07715 /**
07716   * @brief  Disable the selected ADC instance.
07717   * @note   On this STM32 series, setting of this feature is conditioned to
07718   *         ADC state:
07719   *         ADC must be not disabled. Must be enabled without conversion on going
07720   *         on either groups regular or injected.
07721   * @rmtoll CR       ADDIS          LL_ADC_Disable
07722   * @param  ADCx ADC instance
07723   * @retval None
07724   */
07725 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
07726 {
07727   /* Note: Write register with some additional bits forced to state reset     */
07728   /*       instead of modifying only the selected bit for this function,      */
07729   /*       to not interfere with bits with HW property "rs".                  */
07730   MODIFY_REG(ADCx->CR,
07731              ADC_CR_BITS_PROPERTY_RS,
07732              ADC_CR_ADDIS);
07733 }
07734
07735 /**
07736   * @brief  Get the selected ADC instance enable state.
07737   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
07738   *         is enabled and when conversion clock is active.
07739   *         (not only core clock: this ADC has a dual clock domain)
07740   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
07741   * @param  ADCx ADC instance
07742   * @retval 0: ADC is disabled, 1: ADC is enabled.
07743   */
07744 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
07745 {
07746   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
07747 }
07748
07749 /**
07750   * @brief  Get the selected ADC instance disable state.
07751   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
07752   * @param  ADCx ADC instance
07753   * @retval 0: no ADC disable command on going.
07754   */
07755 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
07756 {
07757   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
07758 }
07759
07760 /**
07761   * @brief  Start ADC calibration in the mode single-ended
07762   *         or differential (for devices with differential mode available).
07763   * @note   On this STM32 series, a minimum number of ADC clock cycles
07764   *         are required between ADC end of calibration and ADC enable.
07765   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
07766   * @note   For devices with differential mode available:
07767   *         Calibration of offset is specific to each of
07768   *         single-ended and differential modes
07769   *         (calibration run must be performed for each of these
07770   *         differential modes, if used afterwards and if the application
07771   *         requires their calibration).
07772   * @note   On this STM32 series, setting of this feature is conditioned to
07773   *         ADC state:
07774   *         ADC must be ADC disabled.
07775   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
07776   *         CR       ADCALDIF       LL_ADC_StartCalibration
07777   * @param  ADCx ADC instance
07778   * @param  SingleDiff This parameter can be one of the following values:
07779   *         @arg @ref LL_ADC_SINGLE_ENDED
07780   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
07781   * @retval None
07782   */
07783 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
07784 {
07785   /* Note: Write register with some additional bits forced to state reset     */
07786   /*       instead of modifying only the selected bit for this function,      */
07787   /*       to not interfere with bits with HW property "rs".                  */
07788   MODIFY_REG(ADCx->CR,
07789              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
07790              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
07791 }
07792
07793 /**
07794   * @brief  Get ADC calibration state.
07795   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
07796   * @param  ADCx ADC instance
07797   * @retval 0: calibration complete, 1: calibration in progress.
07798   */
07799 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
07800 {
07801   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
07802 }
07803
07804 /**
07805   * @}
07806   */
07807
07808 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
07809   * @{
07810   */
07811
07812 /**
07813   * @brief  Start ADC group regular conversion.
07814   * @note   On this STM32 series, this function is relevant for both
07815   *         internal trigger (SW start) and external trigger:
07816   *         - If ADC trigger has been set to software start, ADC conversion
07817   *           starts immediately.
07818   *         - If ADC trigger has been set to external trigger, ADC conversion
07819   *           will start at next trigger event (on the selected trigger edge)
07820   *           following the ADC start conversion command.
07821   * @note   On this STM32 series, setting of this feature is conditioned to
07822   *         ADC state:
07823   *         ADC must be enabled without conversion on going on group regular,
07824   *         without conversion stop command on going on group regular,
07825   *         without ADC disable command on going.
07826   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
07827   * @param  ADCx ADC instance
07828   * @retval None
07829   */
07830 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
07831 {
07832   /* Note: Write register with some additional bits forced to state reset     */
07833   /*       instead of modifying only the selected bit for this function,      */
07834   /*       to not interfere with bits with HW property "rs".                  */
07835   MODIFY_REG(ADCx->CR,
07836              ADC_CR_BITS_PROPERTY_RS,
07837              ADC_CR_ADSTART);
07838 }
07839
07840 /**
07841   * @brief  Stop ADC group regular conversion.
07842   * @note   On this STM32 series, setting of this feature is conditioned to
07843   *         ADC state:
07844   *         ADC must be enabled with conversion on going on group regular,
07845   *         without ADC disable command on going.
07846   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
07847   * @param  ADCx ADC instance
07848   * @retval None
07849   */
07850 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
07851 {
07852   /* Note: Write register with some additional bits forced to state reset     */
07853   /*       instead of modifying only the selected bit for this function,      */
07854   /*       to not interfere with bits with HW property "rs".                  */
07855   MODIFY_REG(ADCx->CR,
07856              ADC_CR_BITS_PROPERTY_RS,
07857              ADC_CR_ADSTP);
07858 }
07859
07860 /**
07861   * @brief  Get ADC group regular conversion state.
07862   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
07863   * @param  ADCx ADC instance
07864   * @retval 0: no conversion is on going on ADC group regular.
07865   */
07866 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
07867 {
07868   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
07869 }
07870
07871 /**
07872   * @brief  Get ADC group regular command of conversion stop state
07873   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
07874   * @param  ADCx ADC instance
07875   * @retval 0: no command of conversion stop is on going on ADC group regular.
07876   */
07877 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
07878 {
07879   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
07880 }
07881
07882 /**
07883   * @brief  Start ADC sampling phase for sampling time trigger mode
07884   * @note   This function is relevant only when
07885   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
07886   *           using @ref LL_ADC_REG_SetSamplingMode
07887   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
07888   * @note   On this STM32 series, setting of this feature is conditioned to
07889   *         ADC state:
07890   *         ADC must be enabled without conversion on going on group regular,
07891   *         without conversion stop command on going on group regular,
07892   *         without ADC disable command on going.
07893   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
07894   * @param  ADCx ADC instance
07895   * @retval None
07896   */
07897 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
07898 {
07899   SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
07900 }
07901
07902 /**
07903   * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
07904   * @note   This function is relevant only when
07905   *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
07906   *           using @ref LL_ADC_REG_SetSamplingMode
07907   *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
07908   *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
07909   *           the sampling phase
07910   * @note   On this STM32 series, setting of this feature is conditioned to
07911   *         ADC state:
07912   *         ADC must be enabled without conversion on going on group regular,
07913   *         without conversion stop command on going on group regular,
07914   *         without ADC disable command on going.
07915   * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
07916   * @param  ADCx ADC instance
07917   * @retval None
07918   */
07919 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
07920 {
07921   CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
07922 }
07923
07924 /**
07925   * @brief  Get ADC group regular conversion data, range fit for
07926   *         all ADC configurations: all ADC resolutions and
07927   *         all oversampling increased data width (for devices
07928   *         with feature oversampling).
07929   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
07930   * @param  ADCx ADC instance
07931   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
07932   */
07933 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
07934 {
07935   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
07936 }
07937
07938 /**
07939   * @brief  Get ADC group regular conversion data, range fit for
07940   *         ADC resolution 12 bits.
07941   * @note   For devices with feature oversampling: Oversampling
07942   *         can increase data width, function for extended range
07943   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
07944   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
07945   * @param  ADCx ADC instance
07946   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
07947   */
07948 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
07949 {
07950   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
07951 }
07952
07953 /**
07954   * @brief  Get ADC group regular conversion data, range fit for
07955   *         ADC resolution 10 bits.
07956   * @note   For devices with feature oversampling: Oversampling
07957   *         can increase data width, function for extended range
07958   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
07959   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
07960   * @param  ADCx ADC instance
07961   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
07962   */
07963 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
07964 {
07965   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
07966 }
07967
07968 /**
07969   * @brief  Get ADC group regular conversion data, range fit for
07970   *         ADC resolution 8 bits.
07971   * @note   For devices with feature oversampling: Oversampling
07972   *         can increase data width, function for extended range
07973   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
07974   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
07975   * @param  ADCx ADC instance
07976   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
07977   */
07978 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
07979 {
07980   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
07981 }
07982
07983 /**
07984   * @brief  Get ADC group regular conversion data, range fit for
07985   *         ADC resolution 6 bits.
07986   * @note   For devices with feature oversampling: Oversampling
07987   *         can increase data width, function for extended range
07988   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
07989   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
07990   * @param  ADCx ADC instance
07991   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
07992   */
07993 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
07994 {
07995   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
07996 }
07997
07998 #if defined(ADC_MULTIMODE_SUPPORT)
07999 /**
08000   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
08001   *         or raw data with ADC master and slave concatenated.
08002   * @note   If raw data with ADC master and slave concatenated is retrieved,
08003   *         a macro is available to get the conversion data of
08004   *         ADC master or ADC slave: see helper macro
08005   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
08006   *         (however this macro is mainly intended for multimode
08007   *         transfer by DMA, because this function can do the same
08008   *         by getting multimode conversion data of ADC master or ADC slave
08009   *         separately).
08010   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
08011   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
08012   * @param  ADCxy_COMMON ADC common instance
08013   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08014   * @param  ConversionData This parameter can be one of the following values:
08015   *         @arg @ref LL_ADC_MULTI_MASTER
08016   *         @arg @ref LL_ADC_MULTI_SLAVE
08017   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
08018   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
08019   */
08020 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
08021                                                               uint32_t ConversionData)
08022 {
08023   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
08024                              ConversionData)
08025                     >> (POSITION_VAL(ConversionData) & 0x1FUL)
08026                    );
08027 }
08028 #endif /* ADC_MULTIMODE_SUPPORT */
08029
08030 /**
08031   * @}
08032   */
08033
08034 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
08035   * @{
08036   */
08037
08038 /**
08039   * @brief  Start ADC group injected conversion.
08040   * @note   On this STM32 series, this function is relevant for both
08041   *         internal trigger (SW start) and external trigger:
08042   *         - If ADC trigger has been set to software start, ADC conversion
08043   *           starts immediately.
08044   *         - If ADC trigger has been set to external trigger, ADC conversion
08045   *           will start at next trigger event (on the selected trigger edge)
08046   *           following the ADC start conversion command.
08047   * @note   On this STM32 series, setting of this feature is conditioned to
08048   *         ADC state:
08049   *         ADC must be enabled without conversion on going on group injected,
08050   *         without conversion stop command on going on group injected,
08051   *         without ADC disable command on going.
08052   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
08053   * @param  ADCx ADC instance
08054   * @retval None
08055   */
08056 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
08057 {
08058   /* Note: Write register with some additional bits forced to state reset     */
08059   /*       instead of modifying only the selected bit for this function,      */
08060   /*       to not interfere with bits with HW property "rs".                  */
08061   MODIFY_REG(ADCx->CR,
08062              ADC_CR_BITS_PROPERTY_RS,
08063              ADC_CR_JADSTART);
08064 }
08065
08066 /**
08067   * @brief  Stop ADC group injected conversion.
08068   * @note   On this STM32 series, setting of this feature is conditioned to
08069   *         ADC state:
08070   *         ADC must be enabled with conversion on going on group injected,
08071   *         without ADC disable command on going.
08072   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
08073   * @param  ADCx ADC instance
08074   * @retval None
08075   */
08076 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
08077 {
08078   /* Note: Write register with some additional bits forced to state reset     */
08079   /*       instead of modifying only the selected bit for this function,      */
08080   /*       to not interfere with bits with HW property "rs".                  */
08081   MODIFY_REG(ADCx->CR,
08082              ADC_CR_BITS_PROPERTY_RS,
08083              ADC_CR_JADSTP);
08084 }
08085
08086 /**
08087   * @brief  Get ADC group injected conversion state.
08088   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
08089   * @param  ADCx ADC instance
08090   * @retval 0: no conversion is on going on ADC group injected.
08091   */
08092 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
08093 {
08094   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
08095 }
08096
08097 /**
08098   * @brief  Get ADC group injected command of conversion stop state
08099   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
08100   * @param  ADCx ADC instance
08101   * @retval 0: no command of conversion stop is on going on ADC group injected.
08102   */
08103 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
08104 {
08105   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
08106 }
08107
08108 /**
08109   * @brief  Get ADC group injected conversion data, range fit for
08110   *         all ADC configurations: all ADC resolutions and
08111   *         all oversampling increased data width (for devices
08112   *         with feature oversampling).
08113   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
08114   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
08115   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
08116   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
08117   * @param  ADCx ADC instance
08118   * @param  Rank This parameter can be one of the following values:
08119   *         @arg @ref LL_ADC_INJ_RANK_1
08120   *         @arg @ref LL_ADC_INJ_RANK_2
08121   *         @arg @ref LL_ADC_INJ_RANK_3
08122   *         @arg @ref LL_ADC_INJ_RANK_4
08123   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
08124   */
08125 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
08126 {
08127   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
08128                                                    ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
08129
08130   return (uint32_t)(READ_BIT(*preg,
08131                              ADC_JDR1_JDATA)
08132                    );
08133 }
08134
08135 /**
08136   * @brief  Get ADC group injected conversion data, range fit for
08137   *         ADC resolution 12 bits.
08138   * @note   For devices with feature oversampling: Oversampling
08139   *         can increase data width, function for extended range
08140   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
08141   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
08142   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
08143   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
08144   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
08145   * @param  ADCx ADC instance
08146   * @param  Rank This parameter can be one of the following values:
08147   *         @arg @ref LL_ADC_INJ_RANK_1
08148   *         @arg @ref LL_ADC_INJ_RANK_2
08149   *         @arg @ref LL_ADC_INJ_RANK_3
08150   *         @arg @ref LL_ADC_INJ_RANK_4
08151   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
08152   */
08153 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
08154 {
08155   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
08156                                                    ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
08157
08158   return (uint16_t)(READ_BIT(*preg,
08159                              ADC_JDR1_JDATA)
08160                    );
08161 }
08162
08163 /**
08164   * @brief  Get ADC group injected conversion data, range fit for
08165   *         ADC resolution 10 bits.
08166   * @note   For devices with feature oversampling: Oversampling
08167   *         can increase data width, function for extended range
08168   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
08169   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
08170   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
08171   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
08172   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
08173   * @param  ADCx ADC instance
08174   * @param  Rank This parameter can be one of the following values:
08175   *         @arg @ref LL_ADC_INJ_RANK_1
08176   *         @arg @ref LL_ADC_INJ_RANK_2
08177   *         @arg @ref LL_ADC_INJ_RANK_3
08178   *         @arg @ref LL_ADC_INJ_RANK_4
08179   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
08180   */
08181 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
08182 {
08183   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
08184                                                    ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
08185
08186   return (uint16_t)(READ_BIT(*preg,
08187                              ADC_JDR1_JDATA)
08188                    );
08189 }
08190
08191 /**
08192   * @brief  Get ADC group injected conversion data, range fit for
08193   *         ADC resolution 8 bits.
08194   * @note   For devices with feature oversampling: Oversampling
08195   *         can increase data width, function for extended range
08196   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
08197   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
08198   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
08199   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
08200   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
08201   * @param  ADCx ADC instance
08202   * @param  Rank This parameter can be one of the following values:
08203   *         @arg @ref LL_ADC_INJ_RANK_1
08204   *         @arg @ref LL_ADC_INJ_RANK_2
08205   *         @arg @ref LL_ADC_INJ_RANK_3
08206   *         @arg @ref LL_ADC_INJ_RANK_4
08207   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
08208   */
08209 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
08210 {
08211   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
08212                                                    ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
08213
08214   return (uint8_t)(READ_BIT(*preg,
08215                             ADC_JDR1_JDATA)
08216                   );
08217 }
08218
08219 /**
08220   * @brief  Get ADC group injected conversion data, range fit for
08221   *         ADC resolution 6 bits.
08222   * @note   For devices with feature oversampling: Oversampling
08223   *         can increase data width, function for extended range
08224   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
08225   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
08226   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
08227   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
08228   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
08229   * @param  ADCx ADC instance
08230   * @param  Rank This parameter can be one of the following values:
08231   *         @arg @ref LL_ADC_INJ_RANK_1
08232   *         @arg @ref LL_ADC_INJ_RANK_2
08233   *         @arg @ref LL_ADC_INJ_RANK_3
08234   *         @arg @ref LL_ADC_INJ_RANK_4
08235   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
08236   */
08237 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
08238 {
08239   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
08240                                                    ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
08241
08242   return (uint8_t)(READ_BIT(*preg,
08243                             ADC_JDR1_JDATA)
08244                   );
08245 }
08246
08247 /**
08248   * @}
08249   */
08250
08251 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
08252   * @{
08253   */
08254
08255 /**
08256   * @brief  Get flag ADC ready.
08257   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
08258   *         is enabled and when conversion clock is active.
08259   *         (not only core clock: this ADC has a dual clock domain)
08260   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
08261   * @param  ADCx ADC instance
08262   * @retval State of bit (1 or 0).
08263   */
08264 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
08265 {
08266   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
08267 }
08268
08269 /**
08270   * @brief  Get flag ADC group regular end of unitary conversion.
08271   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
08272   * @param  ADCx ADC instance
08273   * @retval State of bit (1 or 0).
08274   */
08275 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
08276 {
08277   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
08278 }
08279
08280 /**
08281   * @brief  Get flag ADC group regular end of sequence conversions.
08282   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
08283   * @param  ADCx ADC instance
08284   * @retval State of bit (1 or 0).
08285   */
08286 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
08287 {
08288   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
08289 }
08290
08291 /**
08292   * @brief  Get flag ADC group regular overrun.
08293   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
08294   * @param  ADCx ADC instance
08295   * @retval State of bit (1 or 0).
08296   */
08297 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
08298 {
08299   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
08300 }
08301
08302 /**
08303   * @brief  Get flag ADC group regular end of sampling phase.
08304   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
08305   * @param  ADCx ADC instance
08306   * @retval State of bit (1 or 0).
08307   */
08308 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
08309 {
08310   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
08311 }
08312
08313 /**
08314   * @brief  Get flag ADC group injected end of unitary conversion.
08315   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
08316   * @param  ADCx ADC instance
08317   * @retval State of bit (1 or 0).
08318   */
08319 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
08320 {
08321   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
08322 }
08323
08324 /**
08325   * @brief  Get flag ADC group injected end of sequence conversions.
08326   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
08327   * @param  ADCx ADC instance
08328   * @retval State of bit (1 or 0).
08329   */
08330 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
08331 {
08332   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
08333 }
08334
08335 /**
08336   * @brief  Get flag ADC group injected contexts queue overflow.
08337   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
08338   * @param  ADCx ADC instance
08339   * @retval State of bit (1 or 0).
08340   */
08341 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
08342 {
08343   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
08344 }
08345
08346 /**
08347   * @brief  Get flag ADC analog watchdog 1 flag
08348   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
08349   * @param  ADCx ADC instance
08350   * @retval State of bit (1 or 0).
08351   */
08352 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
08353 {
08354   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
08355 }
08356
08357 /**
08358   * @brief  Get flag ADC analog watchdog 2.
08359   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
08360   * @param  ADCx ADC instance
08361   * @retval State of bit (1 or 0).
08362   */
08363 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
08364 {
08365   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
08366 }
08367
08368 /**
08369   * @brief  Get flag ADC analog watchdog 3.
08370   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
08371   * @param  ADCx ADC instance
08372   * @retval State of bit (1 or 0).
08373   */
08374 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
08375 {
08376   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
08377 }
08378
08379 /**
08380   * @brief  Clear flag ADC ready.
08381   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
08382   *         is enabled and when conversion clock is active.
08383   *         (not only core clock: this ADC has a dual clock domain)
08384   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
08385   * @param  ADCx ADC instance
08386   * @retval None
08387   */
08388 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
08389 {
08390   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
08391 }
08392
08393 /**
08394   * @brief  Clear flag ADC group regular end of unitary conversion.
08395   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
08396   * @param  ADCx ADC instance
08397   * @retval None
08398   */
08399 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
08400 {
08401   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
08402 }
08403
08404 /**
08405   * @brief  Clear flag ADC group regular end of sequence conversions.
08406   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
08407   * @param  ADCx ADC instance
08408   * @retval None
08409   */
08410 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
08411 {
08412   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
08413 }
08414
08415 /**
08416   * @brief  Clear flag ADC group regular overrun.
08417   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
08418   * @param  ADCx ADC instance
08419   * @retval None
08420   */
08421 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
08422 {
08423   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
08424 }
08425
08426 /**
08427   * @brief  Clear flag ADC group regular end of sampling phase.
08428   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
08429   * @param  ADCx ADC instance
08430   * @retval None
08431   */
08432 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
08433 {
08434   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
08435 }
08436
08437 /**
08438   * @brief  Clear flag ADC group injected end of unitary conversion.
08439   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
08440   * @param  ADCx ADC instance
08441   * @retval None
08442   */
08443 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
08444 {
08445   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
08446 }
08447
08448 /**
08449   * @brief  Clear flag ADC group injected end of sequence conversions.
08450   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
08451   * @param  ADCx ADC instance
08452   * @retval None
08453   */
08454 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
08455 {
08456   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
08457 }
08458
08459 /**
08460   * @brief  Clear flag ADC group injected contexts queue overflow.
08461   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
08462   * @param  ADCx ADC instance
08463   * @retval None
08464   */
08465 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
08466 {
08467   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
08468 }
08469
08470 /**
08471   * @brief  Clear flag ADC analog watchdog 1.
08472   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
08473   * @param  ADCx ADC instance
08474   * @retval None
08475   */
08476 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
08477 {
08478   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
08479 }
08480
08481 /**
08482   * @brief  Clear flag ADC analog watchdog 2.
08483   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
08484   * @param  ADCx ADC instance
08485   * @retval None
08486   */
08487 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
08488 {
08489   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
08490 }
08491
08492 /**
08493   * @brief  Clear flag ADC analog watchdog 3.
08494   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
08495   * @param  ADCx ADC instance
08496   * @retval None
08497   */
08498 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
08499 {
08500   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
08501 }
08502
08503 #if defined(ADC_MULTIMODE_SUPPORT)
08504 /**
08505   * @brief  Get flag multimode ADC ready of the ADC master.
08506   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
08507   * @param  ADCxy_COMMON ADC common instance
08508   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08509   * @retval State of bit (1 or 0).
08510   */
08511 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
08512 {
08513   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
08514 }
08515
08516 /**
08517   * @brief  Get flag multimode ADC ready of the ADC slave.
08518   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
08519   * @param  ADCxy_COMMON ADC common instance
08520   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08521   * @retval State of bit (1 or 0).
08522   */
08523 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
08524 {
08525   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
08526 }
08527
08528 /**
08529   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
08530   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
08531   * @param  ADCxy_COMMON ADC common instance
08532   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08533   * @retval State of bit (1 or 0).
08534   */
08535 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
08536 {
08537   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
08538 }
08539
08540 /**
08541   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
08542   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
08543   * @param  ADCxy_COMMON ADC common instance
08544   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08545   * @retval State of bit (1 or 0).
08546   */
08547 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
08548 {
08549   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
08550 }
08551
08552 /**
08553   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
08554   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
08555   * @param  ADCxy_COMMON ADC common instance
08556   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08557   * @retval State of bit (1 or 0).
08558   */
08559 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
08560 {
08561   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
08562 }
08563
08564 /**
08565   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
08566   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
08567   * @param  ADCxy_COMMON ADC common instance
08568   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08569   * @retval State of bit (1 or 0).
08570   */
08571 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
08572 {
08573   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
08574 }
08575
08576 /**
08577   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
08578   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
08579   * @param  ADCxy_COMMON ADC common instance
08580   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08581   * @retval State of bit (1 or 0).
08582   */
08583 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
08584 {
08585   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
08586 }
08587
08588 /**
08589   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
08590   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
08591   * @param  ADCxy_COMMON ADC common instance
08592   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08593   * @retval State of bit (1 or 0).
08594   */
08595 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
08596 {
08597   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
08598 }
08599
08600 /**
08601   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
08602   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
08603   * @param  ADCxy_COMMON ADC common instance
08604   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08605   * @retval State of bit (1 or 0).
08606   */
08607 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
08608 {
08609   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
08610 }
08611
08612 /**
08613   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
08614   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
08615   * @param  ADCxy_COMMON ADC common instance
08616   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08617   * @retval State of bit (1 or 0).
08618   */
08619 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
08620 {
08621   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
08622 }
08623
08624 /**
08625   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
08626   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
08627   * @param  ADCxy_COMMON ADC common instance
08628   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08629   * @retval State of bit (1 or 0).
08630   */
08631 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
08632 {
08633   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
08634 }
08635
08636 /**
08637   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
08638   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
08639   * @param  ADCxy_COMMON ADC common instance
08640   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08641   * @retval State of bit (1 or 0).
08642   */
08643 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
08644 {
08645   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
08646 }
08647
08648 /**
08649   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
08650   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
08651   * @param  ADCxy_COMMON ADC common instance
08652   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08653   * @retval State of bit (1 or 0).
08654   */
08655 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
08656 {
08657   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
08658 }
08659
08660 /**
08661   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
08662   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
08663   * @param  ADCxy_COMMON ADC common instance
08664   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08665   * @retval State of bit (1 or 0).
08666   */
08667 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
08668 {
08669   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
08670 }
08671
08672 /**
08673   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
08674   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
08675   * @param  ADCxy_COMMON ADC common instance
08676   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08677   * @retval State of bit (1 or 0).
08678   */
08679 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
08680 {
08681   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
08682 }
08683
08684 /**
08685   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
08686   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
08687   * @param  ADCxy_COMMON ADC common instance
08688   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08689   * @retval State of bit (1 or 0).
08690   */
08691 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
08692 {
08693   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
08694 }
08695
08696 /**
08697   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
08698   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
08699   * @param  ADCxy_COMMON ADC common instance
08700   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08701   * @retval State of bit (1 or 0).
08702   */
08703 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
08704 {
08705   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
08706 }
08707
08708 /**
08709   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
08710   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
08711   * @param  ADCxy_COMMON ADC common instance
08712   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08713   * @retval State of bit (1 or 0).
08714   */
08715 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
08716 {
08717   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
08718 }
08719
08720 /**
08721   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
08722   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
08723   * @param  ADCxy_COMMON ADC common instance
08724   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08725   * @retval State of bit (1 or 0).
08726   */
08727 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
08728 {
08729   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
08730 }
08731
08732 /**
08733   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
08734   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
08735   * @param  ADCxy_COMMON ADC common instance
08736   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08737   * @retval State of bit (1 or 0).
08738   */
08739 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
08740 {
08741   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
08742 }
08743
08744 /**
08745   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
08746   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
08747   * @param  ADCxy_COMMON ADC common instance
08748   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08749   * @retval State of bit (1 or 0).
08750   */
08751 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
08752 {
08753   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
08754 }
08755
08756 /**
08757   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
08758   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
08759   * @param  ADCxy_COMMON ADC common instance
08760   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
08761   * @retval State of bit (1 or 0).
08762   */
08763 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
08764 {
08765   return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
08766 }
08767 #endif /* ADC_MULTIMODE_SUPPORT */
08768
08769 /**
08770   * @}
08771   */
08772
08773 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
08774   * @{
08775   */
08776
08777 /**
08778   * @brief  Enable ADC ready.
08779   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
08780   * @param  ADCx ADC instance
08781   * @retval None
08782   */
08783 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
08784 {
08785   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
08786 }
08787
08788 /**
08789   * @brief  Enable interruption ADC group regular end of unitary conversion.
08790   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
08791   * @param  ADCx ADC instance
08792   * @retval None
08793   */
08794 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
08795 {
08796   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
08797 }
08798
08799 /**
08800   * @brief  Enable interruption ADC group regular end of sequence conversions.
08801   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
08802   * @param  ADCx ADC instance
08803   * @retval None
08804   */
08805 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
08806 {
08807   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
08808 }
08809
08810 /**
08811   * @brief  Enable ADC group regular interruption overrun.
08812   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
08813   * @param  ADCx ADC instance
08814   * @retval None
08815   */
08816 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
08817 {
08818   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
08819 }
08820
08821 /**
08822   * @brief  Enable interruption ADC group regular end of sampling.
08823   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
08824   * @param  ADCx ADC instance
08825   * @retval None
08826   */
08827 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
08828 {
08829   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
08830 }
08831
08832 /**
08833   * @brief  Enable interruption ADC group injected end of unitary conversion.
08834   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
08835   * @param  ADCx ADC instance
08836   * @retval None
08837   */
08838 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
08839 {
08840   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
08841 }
08842
08843 /**
08844   * @brief  Enable interruption ADC group injected end of sequence conversions.
08845   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
08846   * @param  ADCx ADC instance
08847   * @retval None
08848   */
08849 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
08850 {
08851   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
08852 }
08853
08854 /**
08855   * @brief  Enable interruption ADC group injected context queue overflow.
08856   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
08857   * @param  ADCx ADC instance
08858   * @retval None
08859   */
08860 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
08861 {
08862   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
08863 }
08864
08865 /**
08866   * @brief  Enable interruption ADC analog watchdog 1.
08867   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
08868   * @param  ADCx ADC instance
08869   * @retval None
08870   */
08871 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
08872 {
08873   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
08874 }
08875
08876 /**
08877   * @brief  Enable interruption ADC analog watchdog 2.
08878   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
08879   * @param  ADCx ADC instance
08880   * @retval None
08881   */
08882 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
08883 {
08884   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
08885 }
08886
08887 /**
08888   * @brief  Enable interruption ADC analog watchdog 3.
08889   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
08890   * @param  ADCx ADC instance
08891   * @retval None
08892   */
08893 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
08894 {
08895   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
08896 }
08897
08898 /**
08899   * @brief  Disable interruption ADC ready.
08900   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
08901   * @param  ADCx ADC instance
08902   * @retval None
08903   */
08904 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
08905 {
08906   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
08907 }
08908
08909 /**
08910   * @brief  Disable interruption ADC group regular end of unitary conversion.
08911   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
08912   * @param  ADCx ADC instance
08913   * @retval None
08914   */
08915 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
08916 {
08917   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
08918 }
08919
08920 /**
08921   * @brief  Disable interruption ADC group regular end of sequence conversions.
08922   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
08923   * @param  ADCx ADC instance
08924   * @retval None
08925   */
08926 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
08927 {
08928   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
08929 }
08930
08931 /**
08932   * @brief  Disable interruption ADC group regular overrun.
08933   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
08934   * @param  ADCx ADC instance
08935   * @retval None
08936   */
08937 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
08938 {
08939   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
08940 }
08941
08942 /**
08943   * @brief  Disable interruption ADC group regular end of sampling.
08944   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
08945   * @param  ADCx ADC instance
08946   * @retval None
08947   */
08948 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
08949 {
08950   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
08951 }
08952
08953 /**
08954   * @brief  Disable interruption ADC group regular end of unitary conversion.
08955   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
08956   * @param  ADCx ADC instance
08957   * @retval None
08958   */
08959 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
08960 {
08961   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
08962 }
08963
08964 /**
08965   * @brief  Disable interruption ADC group injected end of sequence conversions.
08966   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
08967   * @param  ADCx ADC instance
08968   * @retval None
08969   */
08970 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
08971 {
08972   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
08973 }
08974
08975 /**
08976   * @brief  Disable interruption ADC group injected context queue overflow.
08977   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
08978   * @param  ADCx ADC instance
08979   * @retval None
08980   */
08981 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
08982 {
08983   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
08984 }
08985
08986 /**
08987   * @brief  Disable interruption ADC analog watchdog 1.
08988   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
08989   * @param  ADCx ADC instance
08990   * @retval None
08991   */
08992 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
08993 {
08994   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
08995 }
08996
08997 /**
08998   * @brief  Disable interruption ADC analog watchdog 2.
08999   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
09000   * @param  ADCx ADC instance
09001   * @retval None
09002   */
09003 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
09004 {
09005   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
09006 }
09007
09008 /**
09009   * @brief  Disable interruption ADC analog watchdog 3.
09010   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
09011   * @param  ADCx ADC instance
09012   * @retval None
09013   */
09014 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
09015 {
09016   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
09017 }
09018
09019 /**
09020   * @brief  Get state of interruption ADC ready
09021   *         (0: interrupt disabled, 1: interrupt enabled).
09022   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
09023   * @param  ADCx ADC instance
09024   * @retval State of bit (1 or 0).
09025   */
09026 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
09027 {
09028   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
09029 }
09030
09031 /**
09032   * @brief  Get state of interruption ADC group regular end of unitary conversion
09033   *         (0: interrupt disabled, 1: interrupt enabled).
09034   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
09035   * @param  ADCx ADC instance
09036   * @retval State of bit (1 or 0).
09037   */
09038 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
09039 {
09040   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
09041 }
09042
09043 /**
09044   * @brief  Get state of interruption ADC group regular end of sequence conversions
09045   *         (0: interrupt disabled, 1: interrupt enabled).
09046   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
09047   * @param  ADCx ADC instance
09048   * @retval State of bit (1 or 0).
09049   */
09050 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
09051 {
09052   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
09053 }
09054
09055 /**
09056   * @brief  Get state of interruption ADC group regular overrun
09057   *         (0: interrupt disabled, 1: interrupt enabled).
09058   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
09059   * @param  ADCx ADC instance
09060   * @retval State of bit (1 or 0).
09061   */
09062 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
09063 {
09064   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
09065 }
09066
09067 /**
09068   * @brief  Get state of interruption ADC group regular end of sampling
09069   *         (0: interrupt disabled, 1: interrupt enabled).
09070   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
09071   * @param  ADCx ADC instance
09072   * @retval State of bit (1 or 0).
09073   */
09074 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
09075 {
09076   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
09077 }
09078
09079 /**
09080   * @brief  Get state of interruption ADC group injected end of unitary conversion
09081   *         (0: interrupt disabled, 1: interrupt enabled).
09082   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
09083   * @param  ADCx ADC instance
09084   * @retval State of bit (1 or 0).
09085   */
09086 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
09087 {
09088   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
09089 }
09090
09091 /**
09092   * @brief  Get state of interruption ADC group injected end of sequence conversions
09093   *         (0: interrupt disabled, 1: interrupt enabled).
09094   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
09095   * @param  ADCx ADC instance
09096   * @retval State of bit (1 or 0).
09097   */
09098 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
09099 {
09100   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
09101 }
09102
09103 /**
09104   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
09105   *         (0: interrupt disabled, 1: interrupt enabled).
09106   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
09107   * @param  ADCx ADC instance
09108   * @retval State of bit (1 or 0).
09109   */
09110 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
09111 {
09112   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
09113 }
09114
09115 /**
09116   * @brief  Get state of interruption ADC analog watchdog 1
09117   *         (0: interrupt disabled, 1: interrupt enabled).
09118   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
09119   * @param  ADCx ADC instance
09120   * @retval State of bit (1 or 0).
09121   */
09122 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
09123 {
09124   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
09125 }
09126
09127 /**
09128   * @brief  Get state of interruption Get ADC analog watchdog 2
09129   *         (0: interrupt disabled, 1: interrupt enabled).
09130   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
09131   * @param  ADCx ADC instance
09132   * @retval State of bit (1 or 0).
09133   */
09134 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
09135 {
09136   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
09137 }
09138
09139 /**
09140   * @brief  Get state of interruption Get ADC analog watchdog 3
09141   *         (0: interrupt disabled, 1: interrupt enabled).
09142   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
09143   * @param  ADCx ADC instance
09144   * @retval State of bit (1 or 0).
09145   */
09146 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
09147 {
09148   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
09149 }
09150
09151 /**
09152   * @}
09153   */
09154
09155 #if defined(USE_FULL_LL_DRIVER)
09156 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
09157   * @{
09158   */
09159
09160 /* Initialization of some features of ADC common parameters and multimode */
09161 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
09162 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
09163 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
09164
09165 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
09166 /* (availability of ADC group injected depends on STM32 series) */
09167 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
09168
09169 /* Initialization of some features of ADC instance */
09170 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
09171 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
09172
09173 /* Initialization of some features of ADC instance and ADC group regular */
09174 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
09175 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
09176
09177 /* Initialization of some features of ADC instance and ADC group injected */
09178 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
09179 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
09180
09181 /**
09182   * @}
09183   */
09184 #endif /* USE_FULL_LL_DRIVER */
09185
09186 /**
09187   * @}
09188   */
09189
09190 /**
09191   * @}
09192   */
09193
09194 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
09195
09196 /**
09197   * @}
09198   */
09199
09200 #ifdef __cplusplus
09201 }
09202 #endif
09203
09204 #endif /* STM32G4xx_LL_ADC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_bus.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_bus.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of BUS LL module.
00006
00007   @verbatim
00008                       ##### RCC Limitations #####
00009   ==============================================================================
00010     [..]
00011       A delay between an RCC peripheral clock enable and the effective peripheral
00012       enabling should be taken into account in order to manage the peripheral read/write
00013       from/to registers.
00014       (+) This delay depends on the peripheral mapping.
00015         (++) AHB & APB peripherals, 1 dummy read is necessary
00016
00017     [..]
00018       Workarounds:
00019       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00020           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * Copyright (c) 2019 STMicroelectronics.
00027   * All rights reserved.
00028   *
00029   * This software is licensed under terms that can be found in the LICENSE file in
00030   * the root directory of this software component.
00031   * If no LICENSE file comes with this software, it is provided AS-IS.
00032   ******************************************************************************
00033   */
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef STM32G4xx_LL_BUS_H
00037 #define STM32G4xx_LL_BUS_H
00038
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g4xx.h"
00045
00046 /** @addtogroup STM32G4xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined(RCC)
00051
00052 /** @defgroup BUS_LL BUS
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058
00059 /* Private constants ---------------------------------------------------------*/
00060
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 /* Exported constants --------------------------------------------------------*/
00065 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00070   * @{
00071   */
00072 #define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
00073 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
00074 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
00075 #define LL_AHB1_GRP1_PERIPH_DMAMUX1        RCC_AHB1ENR_DMAMUX1EN
00076 #define LL_AHB1_GRP1_PERIPH_CORDIC         RCC_AHB1ENR_CORDICEN
00077 #define LL_AHB1_GRP1_PERIPH_FMAC           RCC_AHB1ENR_FMACEN
00078 #define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHB1ENR_FLASHEN
00079 #define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN
00080 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
00086   * @{
00087   */
00088 #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
00089 #define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN
00090 #define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN
00091 #define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN
00092 #define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN
00093 #define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN
00094 #define LL_AHB2_GRP1_PERIPH_GPIOF          RCC_AHB2ENR_GPIOFEN
00095 #define LL_AHB2_GRP1_PERIPH_GPIOG          RCC_AHB2ENR_GPIOGEN
00096 #define LL_AHB2_GRP1_PERIPH_CCM            RCC_AHB2SMENR_CCMSMEN
00097 #define LL_AHB2_GRP1_PERIPH_SRAM2          RCC_AHB2SMENR_SRAM2SMEN
00098 #define LL_AHB2_GRP1_PERIPH_ADC12          RCC_AHB2ENR_ADC12EN
00099 #if defined(ADC345_COMMON)
00100 #define LL_AHB2_GRP1_PERIPH_ADC345         RCC_AHB2ENR_ADC345EN
00101 #endif /* ADC345_COMMON */
00102 #define LL_AHB2_GRP1_PERIPH_DAC1           RCC_AHB2ENR_DAC1EN
00103 #if defined(DAC2)
00104 #define LL_AHB2_GRP1_PERIPH_DAC2           RCC_AHB2ENR_DAC2EN
00105 #endif /* DAC2 */
00106 #define LL_AHB2_GRP1_PERIPH_DAC3           RCC_AHB2ENR_DAC3EN
00107 #if defined(DAC4)
00108 #define LL_AHB2_GRP1_PERIPH_DAC4           RCC_AHB2ENR_DAC4EN
00109 #endif /* DAC4 */
00110 #if defined(AES)
00111 #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
00112 #endif /* AES */
00113 #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
00119   * @{
00120   */
00121 #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
00122 #if defined(FMC_Bank1_R)
00123 #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
00124 #endif /* FMC_Bank1_R */
00125 #if defined(QUADSPI)
00126 #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
00127 #endif /* QUADSPI */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00133   * @{
00134   */
00135 #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
00136 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
00137 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN
00138 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN
00139 #if defined(TIM5)
00140 #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN
00141 #endif /* TIM5 */
00142 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN
00143 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN
00144 #define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN
00145 #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN
00146 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
00147 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
00148 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN
00149 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN
00150 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN
00151 #if defined(UART4)
00152 #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN
00153 #endif /* UART4 */
00154 #if defined(UART5)
00155 #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN
00156 #endif /* UART5 */
00157 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
00158 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN
00159 #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBEN
00160 #if defined(FDCAN1)
00161 #define LL_APB1_GRP1_PERIPH_FDCAN          RCC_APB1ENR1_FDCANEN
00162 #endif /* FDCAN1 */
00163 #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR1_PWREN
00164 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
00165 #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
00166 /**
00167   * @}
00168   */
00169
00170
00171 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
00172   * @{
00173   */
00174 #define LL_APB1_GRP2_PERIPH_ALL            0xFFFFFFFFU
00175 #define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN
00176 #if defined(I2C4)
00177 #define LL_APB1_GRP2_PERIPH_I2C4           RCC_APB1ENR2_I2C4EN
00178 #endif /* I2C4 */
00179 #define LL_APB1_GRP2_PERIPH_UCPD1         RCC_APB1ENR2_UCPD1EN
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00185   * @{
00186   */
00187 #define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
00188 #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
00189 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00190 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00191 #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
00192 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00193 #if defined(SPI4)
00194 #define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
00195 #endif /* SPI4 */
00196 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
00197 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00198 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00199 #if defined(TIM20)
00200 #define LL_APB2_GRP1_PERIPH_TIM20          RCC_APB2ENR_TIM20EN
00201 #endif /* TIM20 */
00202 #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
00203 #if defined(HRTIM1)
00204 #define LL_APB2_GRP1_PERIPH_HRTIM1         RCC_APB2ENR_HRTIM1EN
00205 #endif /* HRTIM1 */
00206 /**
00207   * @}
00208   */
00209
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported macro ------------------------------------------------------------*/
00215 /* Exported functions --------------------------------------------------------*/
00216 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00217   * @{
00218   */
00219
00220 /** @defgroup BUS_LL_EF_AHB1 AHB1
00221   * @{
00222   */
00223
00224 /**
00225   * @brief  Enable AHB1 peripherals clock.
00226   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
00227   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
00228   *         AHB1ENR      DMAMMUXEN     LL_AHB1_GRP1_EnableClock\n
00229   *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_EnableClock\n
00230   *         AHB1ENR      FMACEN        LL_AHB1_GRP1_EnableClock\n
00231   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_EnableClock\n
00232   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock
00233   * @param  Periphs This parameter can be a combination of the following values:
00234   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00235   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00236   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00237   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00238   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00239   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00240   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00241   * @retval None
00242   */
00243 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00244 {
00245   __IO uint32_t tmpreg;
00246   SET_BIT(RCC->AHB1ENR, Periphs);
00247   /* Delay after an RCC peripheral clock enabling */
00248   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
00249   (void)tmpreg;
00250 }
00251
00252 /**
00253   * @brief  Check if AHB1 peripheral clock is enabled or not
00254   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00255   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00256   *         AHB1ENR      DMAMUXEN      LL_AHB1_GRP1_IsEnabledClock\n
00257   *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_IsEnabledClock\n
00258   *         AHB1ENR      FMACEN        LL_AHB1_GRP1_IsEnabledClock\n
00259   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
00260   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock
00261   * @param  Periphs This parameter can be a combination of the following values:
00262   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00263   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00264   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00265   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00266   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00267   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00268   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00269   * @retval State of Periphs (1 or 0).
00270   */
00271 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00272 {
00273   return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
00274 }
00275
00276 /**
00277   * @brief  Disable AHB1 peripherals clock.
00278   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
00279   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
00280   *         AHB1ENR      DMAMUXEN      LL_AHB1_GRP1_DisableClock\n
00281   *         AHB1ENR      CORDICEN      LL_AHB1_GRP1_DisableClock\n
00282   *         AHB1ENR      FMACEN        LL_AHB1_GRP1_DisableClock\n
00283   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_DisableClock\n
00284   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock
00285   * @param  Periphs This parameter can be a combination of the following values:
00286   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00287   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00288   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00289   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00290   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00291   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00292   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00296 {
00297   CLEAR_BIT(RCC->AHB1ENR, Periphs);
00298 }
00299
00300 /**
00301   * @brief  Force AHB1 peripherals reset.
00302   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
00303   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
00304   *         AHB1RSTR     DMAMUXRST     LL_AHB1_GRP1_ForceReset\n
00305   *         AHB1RSTR     CORDICRST     LL_AHB1_GRP1_ForceReset\n
00306   *         AHB1RSTR     FMACRST       LL_AHB1_GRP1_ForceReset\n
00307   *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ForceReset\n
00308   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset
00309   * @param  Periphs This parameter can be a combination of the following values:
00310   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00311   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00312   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00313   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00314   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00315   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00316   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00317   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00321 {
00322   SET_BIT(RCC->AHB1RSTR, Periphs);
00323 }
00324
00325 /**
00326   * @brief  Release AHB1 peripherals reset.
00327   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
00328   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
00329   *         AHB1RSTR     DMAMUXRST     LL_AHB1_GRP1_ReleaseReset\n
00330   *         AHB1RSTR     CORDICRST     LL_AHB1_GRP1_ReleaseReset\n
00331   *         AHB1RSTR     FMACRST       LL_AHB1_GRP1_ReleaseReset\n
00332   *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
00333   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset
00334   * @param  Periphs This parameter can be a combination of the following values:
00335   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00336   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00337   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00338   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00339   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00340   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00341   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00342   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00343   * @retval None
00344   */
00345 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00346 {
00347   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
00348 }
00349
00350 /**
00351   * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
00352   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00353   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00354   *         AHB1SMENR    DMAMUXSMEN    LL_AHB1_GRP1_EnableClockStopSleep\n
00355   *         AHB1SMENR    CORDICSMEN    LL_AHB1_GRP1_EnableClockStopSleep\n
00356   *         AHB1SMENR    FMACSMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00357   *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
00358   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00359   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep
00360   * @param  Periphs This parameter can be a combination of the following values:
00361   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00362   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00363   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00364   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00365   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00366   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00367   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00368   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00369   * @retval None
00370   */
00371 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
00372 {
00373   __IO uint32_t tmpreg;
00374   SET_BIT(RCC->AHB1SMENR, Periphs);
00375   /* Delay after an RCC peripheral clock enabling */
00376   tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
00377   (void)tmpreg;
00378 }
00379
00380 /**
00381   * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
00382   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00383   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00384   *         AHB1SMENR    DMAMUXSMEN    LL_AHB1_GRP1_DisableClockStopSleep\n
00385   *         AHB1SMENR    CORDICSMEN    LL_AHB1_GRP1_DisableClockStopSleep\n
00386   *         AHB1SMENR    FMACSMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00387   *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00388   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00389   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep
00390   * @param  Periphs This parameter can be a combination of the following values:
00391   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00392   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00393   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00394   *         @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
00395   *         @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
00396   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00397   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00398   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00399   * @retval None
00400   */
00401 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
00402 {
00403   CLEAR_BIT(RCC->AHB1SMENR, Periphs);
00404 }
00405
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup BUS_LL_EF_AHB2 AHB2
00411   * @{
00412   */
00413
00414 /**
00415   * @brief  Enable AHB2 peripherals clock.
00416   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n
00417   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n
00418   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n
00419   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n
00420   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n
00421   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_EnableClock\n
00422   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_EnableClock\n
00423   *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_EnableClock\n
00424   *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_EnableClock\n
00425   *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_EnableClock\n
00426   *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_EnableClock\n
00427   *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_EnableClock\n
00428   *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_EnableClock\n
00429   *         AHB2ENR      AESEN         LL_AHB2_GRP1_EnableClock\n
00430   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock
00431   * @param  Periphs This parameter can be a combination of the following values:
00432   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00433   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00434   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00435   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00436   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00437   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00438   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00439   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00440   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00441   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00442   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00443   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00444   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00445   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00446   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00447   *
00448   *         (*) value not defined in all devices.
00449   * @retval None
00450   */
00451 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
00452 {
00453   __IO uint32_t tmpreg;
00454   SET_BIT(RCC->AHB2ENR, Periphs);
00455   /* Delay after an RCC peripheral clock enabling */
00456   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
00457   (void)tmpreg;
00458 }
00459
00460 /**
00461   * @brief  Check if AHB2 peripheral clock is enabled or not
00462   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n
00463   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n
00464   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n
00465   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n
00466   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n
00467   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_IsEnabledClock\n
00468   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_IsEnabledClock\n
00469   *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_IsEnabledClock\n
00470   *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_IsEnabledClock\n
00471   *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_IsEnabledClock\n
00472   *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_IsEnabledClock\n
00473   *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_IsEnabledClock\n
00474   *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_IsEnabledClock\n
00475   *         AHB2ENR      AESEN         LL_AHB2_GRP1_IsEnabledClock\n
00476   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock
00477   * @param  Periphs This parameter can be a combination of the following values:
00478   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00479   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00480   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00481   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00482   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00483   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00484   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00485   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00486   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00487   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00488   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00489   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00490   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00491   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00492   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00493   *
00494   *         (*) value not defined in all devices.
00495   * @retval State of Periphs (1 or 0).
00496   */
00497 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
00498 {
00499   return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
00500 }
00501
00502 /**
00503   * @brief  Disable AHB2 peripherals clock.
00504   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n
00505   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n
00506   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n
00507   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n
00508   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n
00509   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_DisableClock\n
00510   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_DisableClock\n
00511   *         AHB2ENR      ADC12EN       LL_AHB2_GRP1_DisableClock\n
00512   *         AHB2ENR      ADC345EN      LL_AHB2_GRP1_DisableClock\n
00513   *         AHB2ENR      DAC1EN        LL_AHB2_GRP1_DisableClock\n
00514   *         AHB2ENR      DAC2EN        LL_AHB2_GRP1_DisableClock\n
00515   *         AHB2ENR      DAC3EN        LL_AHB2_GRP1_DisableClock\n
00516   *         AHB2ENR      DAC4EN        LL_AHB2_GRP1_DisableClock\n
00517   *         AHB2ENR      AESEN         LL_AHB2_GRP1_DisableClock\n
00518   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock
00519   * @param  Periphs This parameter can be a combination of the following values:
00520   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00521   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00522   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00523   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00524   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00525   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00526   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00527   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00528   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00529   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00530   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00531   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00532   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00533   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00534   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00535   *
00536   *         (*) value not defined in all devices.
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
00540 {
00541   CLEAR_BIT(RCC->AHB2ENR, Periphs);
00542 }
00543
00544 /**
00545   * @brief  Force AHB2 peripherals reset.
00546   * @rmtoll AHB2RSTR      GPIOARST       LL_AHB2_GRP1_ForceReset\n
00547   *         AHB2RSTR      GPIOBRST       LL_AHB2_GRP1_ForceReset\n
00548   *         AHB2RSTR      GPIOCRST       LL_AHB2_GRP1_ForceReset\n
00549   *         AHB2RSTR      GPIODRST       LL_AHB2_GRP1_ForceReset\n
00550   *         AHB2RSTR      GPIOERST       LL_AHB2_GRP1_ForceReset\n
00551   *         AHB2RSTR      GPIOFRST       LL_AHB2_GRP1_ForceReset\n
00552   *         AHB2RSTR      GPIOGRST       LL_AHB2_GRP1_ForceReset\n
00553   *         AHB2RSTR      ADC12RST       LL_AHB2_GRP1_ForceReset\n
00554   *         AHB2RSTR      ADC345RST      LL_AHB2_GRP1_ForceReset\n
00555   *         AHB2RSTR      DAC1RST        LL_AHB2_GRP1_ForceReset\n
00556   *         AHB2RSTR      DAC2RST        LL_AHB2_GRP1_ForceReset\n
00557   *         AHB2RSTR      DAC3RST        LL_AHB2_GRP1_ForceReset\n
00558   *         AHB2RSTR      DAC4RST        LL_AHB2_GRP1_ForceReset\n
00559   *         AHB2RSTR      AESRST         LL_AHB2_GRP1_ForceReset\n
00560   *         AHB2RSTR      RNGRST         LL_AHB2_GRP1_ForceReset
00561   * @param  Periphs This parameter can be a combination of the following values:
00562   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00563   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00564   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00565   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00566   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00567   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00568   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00569   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00570   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00571   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00572   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00573   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00574   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00575   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00576   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00577   *
00578   *         (*) value not defined in all devices.
00579   * @retval None
00580   */
00581 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
00582 {
00583   SET_BIT(RCC->AHB2RSTR, Periphs);
00584 }
00585
00586 /**
00587   * @brief  Release AHB2 peripherals reset.
00588   * @rmtoll AHB2RSTR      GPIOARST       LL_AHB2_GRP1_ReleaseReset\n
00589   *         AHB2RSTR      GPIOBRST       LL_AHB2_GRP1_ReleaseReset\n
00590   *         AHB2RSTR      GPIOCRST       LL_AHB2_GRP1_ReleaseReset\n
00591   *         AHB2RSTR      GPIODRST       LL_AHB2_GRP1_ReleaseReset\n
00592   *         AHB2RSTR      GPIOERST       LL_AHB2_GRP1_ReleaseReset\n
00593   *         AHB2RSTR      GPIOFRST       LL_AHB2_GRP1_ReleaseReset\n
00594   *         AHB2RSTR      GPIOGRST       LL_AHB2_GRP1_ReleaseReset\n
00595   *         AHB2RSTR      ADC12RST       LL_AHB2_GRP1_ReleaseReset\n
00596   *         AHB2RSTR      ADC345RST      LL_AHB2_GRP1_ReleaseReset\n
00597   *         AHB2RSTR      DAC1RST        LL_AHB2_GRP1_ReleaseReset\n
00598   *         AHB2RSTR      DAC2RST        LL_AHB2_GRP1_ReleaseReset\n
00599   *         AHB2RSTR      DAC3RST        LL_AHB2_GRP1_ReleaseReset\n
00600   *         AHB2RSTR      DAC4RST        LL_AHB2_GRP1_ReleaseReset\n
00601   *         AHB2RSTR      AESRST         LL_AHB2_GRP1_ReleaseReset\n
00602   *         AHB2RSTR      RNGRST         LL_AHB2_GRP1_ReleaseReset
00603   * @param  Periphs This parameter can be a combination of the following values:
00604   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00605   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00606   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00607   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00608   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00609   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00610   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00611   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00612   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00613   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00614   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00615   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00616   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00617   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00618   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00619   *
00620   *         (*) value not defined in all devices.
00621   * @retval None
00622   */
00623 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
00624 {
00625   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
00626 }
00627
00628 /**
00629   * @brief  Enable AHB2 peripheral clocks in Sleep and Stop modes
00630   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00631   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00632   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00633   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00634   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00635   *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00636   *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00637   *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00638   *         AHB2SMENR    CCMSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
00639   *         AHB2SMENR    ADC12SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00640   *         AHB2SMENR    ADC345SMEN    LL_AHB2_GRP1_EnableClockStopSleep\n
00641   *         AHB2SMENR    DAC1SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
00642   *         AHB2SMENR    DAC2SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
00643   *         AHB2SMENR    DAC3SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
00644   *         AHB2SMENR    DAC4SMEN      LL_AHB2_GRP1_EnableClockStopSleep\n
00645   *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
00646   *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_EnableClockStopSleep
00647   * @param  Periphs This parameter can be a combination of the following values:
00648   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00649   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00650   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00651   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00652   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00653   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00654   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00655   *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
00656   *         @arg @ref LL_AHB2_GRP1_PERIPH_CCM
00657   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00658   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00659   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00660   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00661   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00662   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00663   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00664   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00665   *
00666   *         (*) value not defined in all devices.
00667   * @retval None
00668   */
00669 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
00670 {
00671   __IO uint32_t tmpreg;
00672   SET_BIT(RCC->AHB2SMENR, Periphs);
00673   /* Delay after an RCC peripheral clock enabling */
00674   tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
00675   (void)tmpreg;
00676 }
00677
00678 /**
00679   * @brief  Disable AHB2 peripheral clocks in Sleep and Stop modes
00680   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00681   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00682   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00683   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00684   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00685   *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00686   *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00687   *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00688   *         AHB2SMENR    CCMSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
00689   *         AHB2SMENR    ADC12SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00690   *         AHB2SMENR    ADC345SMEN    LL_AHB2_GRP1_DisableClockStopSleep\n
00691   *         AHB2SMENR    DAC1SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
00692   *         AHB2SMENR    DAC2SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
00693   *         AHB2SMENR    DAC3SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
00694   *         AHB2SMENR    DAC4SMEN      LL_AHB2_GRP1_DisableClockStopSleep\n
00695   *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
00696   *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_DisableClockStopSleep
00697   * @param  Periphs This parameter can be a combination of the following values:
00698   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00699   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00700   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00701   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00702   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00703   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
00704   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
00705   *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
00706   *         @arg @ref LL_AHB2_GRP1_PERIPH_CCM
00707   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
00708   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
00709   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
00710   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
00711   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
00712   *         @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
00713   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00714   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00715   *
00716   *         (*) value not defined in all devices.
00717   * @retval None
00718   */
00719 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
00720 {
00721   CLEAR_BIT(RCC->AHB2SMENR, Periphs);
00722 }
00723
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup BUS_LL_EF_AHB3 AHB3
00729   * @{
00730   */
00731
00732 /**
00733   * @brief  Enable AHB3 peripherals clock.
00734   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
00735   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
00736   * @param  Periphs This parameter can be a combination of the following values:
00737   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00738   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00739   *
00740   *         (*) value not defined in all devices.
00741   * @retval None
00742   */
00743 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
00744 {
00745   __IO uint32_t tmpreg;
00746   SET_BIT(RCC->AHB3ENR, Periphs);
00747   /* Delay after an RCC peripheral clock enabling */
00748   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
00749   (void)tmpreg;
00750 }
00751
00752 /**
00753   * @brief  Check if AHB3 peripheral clock is enabled or not
00754   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
00755   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
00756   * @param  Periphs This parameter can be a combination of the following values:
00757   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00758   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00759   *
00760   *         (*) value not defined in all devices.
00761   * @retval State of Periphs (1 or 0).
00762   */
00763 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
00764 {
00765   return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
00766 }
00767
00768 /**
00769   * @brief  Disable AHB3 peripherals clock.
00770   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
00771   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
00772   * @param  Periphs This parameter can be a combination of the following values:
00773   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00774   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00775   *
00776   *         (*) value not defined in all devices.
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
00780 {
00781   CLEAR_BIT(RCC->AHB3ENR, Periphs);
00782 }
00783
00784 /**
00785   * @brief  Force AHB3 peripherals reset.
00786   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
00787   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
00788   * @param  Periphs This parameter can be a combination of the following values:
00789   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
00790   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00791   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00792   *
00793   *         (*) value not defined in all devices.
00794   * @retval None
00795   */
00796 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
00797 {
00798   SET_BIT(RCC->AHB3RSTR, Periphs);
00799 }
00800
00801 /**
00802   * @brief  Release AHB3 peripherals reset.
00803   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
00804   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
00805   * @param  Periphs This parameter can be a combination of the following values:
00806   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
00807   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00808   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00809   *
00810   *         (*) value not defined in all devices.
00811   * @retval None
00812   */
00813 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
00814 {
00815   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
00816 }
00817
00818 /**
00819   * @brief  Enable AHB3 peripheral clocks in Sleep and Stop modes
00820   * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_EnableClockStopSleep\n
00821   *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_EnableClockStopSleep
00822   * @param  Periphs This parameter can be a combination of the following values:
00823   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC  (*)
00824   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00825   *
00826   *         (*) value not defined in all devices.
00827   * @retval None
00828   */
00829 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
00830 {
00831   __IO uint32_t tmpreg;
00832   SET_BIT(RCC->AHB3SMENR, Periphs);
00833   /* Delay after an RCC peripheral clock enabling */
00834   tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
00835   (void)tmpreg;
00836 }
00837
00838 /**
00839   * @brief  Disable AHB3 peripheral clocks in Sleep and Stop modes
00840   * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_DisableClockStopSleep\n
00841   *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_DisableClockStopSleep
00842   * @param  Periphs This parameter can be a combination of the following values:
00843   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00844   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
00845   *
00846   *         (*) value not defined in all devices.
00847   * @retval None
00848   */
00849 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
00850 {
00851   CLEAR_BIT(RCC->AHB3SMENR, Periphs);
00852 }
00853
00854 /**
00855   * @}
00856   */
00857
00858 /** @defgroup BUS_LL_EF_APB1 APB1
00859   * @{
00860   */
00861
00862 /**
00863   * @brief  Enable APB1 peripherals clock.
00864   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n
00865   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_EnableClock\n
00866   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_EnableClock\n
00867   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_EnableClock\n
00868   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_EnableClock\n
00869   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_EnableClock\n
00870   *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n
00871   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n
00872   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n
00873   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n
00874   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_EnableClock\n
00875   *         APB1ENR1     USART2EN      LL_APB1_GRP1_EnableClock\n
00876   *         APB1ENR1     USART3EN      LL_APB1_GRP1_EnableClock\n
00877   *         APB1ENR1     UART4EN       LL_APB1_GRP1_EnableClock\n
00878   *         APB1ENR1     UART5EN       LL_APB1_GRP1_EnableClock\n
00879   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n
00880   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_EnableClock\n
00881   *         APB1ENR1     USBEN         LL_APB1_GRP1_EnableClock\n
00882   *         APB1ENR1     FDCANEN       LL_APB1_GRP1_EnableClock\n
00883   *         APB1ENR1     PWREN         LL_APB1_GRP1_EnableClock\n
00884   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n
00885   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock
00886   * @param  Periphs This parameter can be a combination of the following values:
00887   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00888   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00889   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
00890   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00891   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00892   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
00893   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
00894   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
00895   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00896   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00897   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
00898   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00899   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00900   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00901   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00902   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00903   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00904   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
00905   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
00906   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00907   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00908   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00909   *
00910   *         (*) value not defined in all devices.
00911   * @retval None
00912   */
00913 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00914 {
00915   __IO uint32_t tmpreg;
00916   SET_BIT(RCC->APB1ENR1, Periphs);
00917   /* Delay after an RCC peripheral clock enabling */
00918   tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
00919   (void)tmpreg;
00920 }
00921
00922 /**
00923   * @brief  Enable APB1 peripherals clock.
00924   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n
00925   *         APB1ENR2     I2C4EN        LL_APB1_GRP2_EnableClock\n
00926   *         APB1ENR2     UCPD1EN       LL_APB1_GRP2_EnableClock
00927   * @param  Periphs This parameter can be a combination of the following values:
00928   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
00929   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
00930   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
00931   *
00932   *         (*) value not defined in all devices.
00933   * @retval None
00934   */
00935 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
00936 {
00937   __IO uint32_t tmpreg;
00938   SET_BIT(RCC->APB1ENR2, Periphs);
00939   /* Delay after an RCC peripheral clock enabling */
00940   tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
00941   (void)tmpreg;
00942 }
00943
00944 /**
00945   * @brief  Check if APB1 peripheral clock is enabled or not
00946   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00947   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
00948   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
00949   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
00950   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
00951   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
00952   *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
00953   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
00954   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
00955   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00956   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
00957   *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
00958   *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
00959   *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
00960   *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
00961   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00962   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
00963   *         APB1ENR1     USBEN         LL_APB1_GRP1_IsEnabledClock\n
00964   *         APB1ENR1     FDCANEN       LL_APB1_GRP1_IsEnabledClock\n
00965   *         APB1ENR1     PWREN         LL_APB1_GRP1_IsEnabledClock\n
00966   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
00967   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
00968   * @param  Periphs This parameter can be a combination of the following values:
00969   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00970   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00971   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
00972   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00973   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00974   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
00975   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
00976   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
00977   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00978   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00979   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
00980   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00981   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
00982   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00983   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00984   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00985   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00986   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
00987   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
00988   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00989   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00990   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00991   *
00992   *         (*) value not defined in all devices.
00993   * @retval State of Periphs (1 or 0).
00994   */
00995 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00996 {
00997   return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
00998 }
00999
01000 /**
01001   * @brief  Check if APB1 peripheral clock is enabled or not
01002   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n
01003   *         APB1ENR2     I2C4EN        LL_APB1_GRP2_IsEnabledClock\n
01004   *         APB1ENR2     UCPD1EN       LL_APB1_GRP2_IsEnabledClock
01005   * @param  Periphs This parameter can be a combination of the following values:
01006   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01007   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01008   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
01009   *
01010   *         (*) value not defined in all devices.
01011   * @retval State of Periphs (1 or 0).
01012   */
01013 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
01014 {
01015   return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
01016 }
01017
01018 /**
01019   * @brief  Disable APB1 peripherals clock.
01020   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n
01021   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_DisableClock\n
01022   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_DisableClock\n
01023   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_DisableClock\n
01024   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_DisableClock\n
01025   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_DisableClock\n
01026   *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n
01027   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n
01028   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_DisableClock\n
01029   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n
01030   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_DisableClock\n
01031   *         APB1ENR1     USART2EN      LL_APB1_GRP1_DisableClock\n
01032   *         APB1ENR1     USART3EN      LL_APB1_GRP1_DisableClock\n
01033   *         APB1ENR1     UART4EN       LL_APB1_GRP1_DisableClock\n
01034   *         APB1ENR1     UART5EN       LL_APB1_GRP1_DisableClock\n
01035   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n
01036   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_DisableClock\n
01037   *         APB1ENR1     USBEN         LL_APB1_GRP1_DisableClock\n
01038   *         APB1ENR1     FDCANEN       LL_APB1_GRP1_DisableClock\n
01039   *         APB1ENR1     PWREN         LL_APB1_GRP1_DisableClock\n
01040   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n
01041   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock
01042   * @param  Periphs This parameter can be a combination of the following values:
01043   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01044   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01045   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01046   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01047   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01048   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01049   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01050   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
01051   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01052   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01053   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01054   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01055   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01056   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01057   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01058   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01059   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01060   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01061   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
01062   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01063   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01064   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01065   *
01066   *         (*) value not defined in all devices.
01067   * @retval None
01068   */
01069 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
01070 {
01071   CLEAR_BIT(RCC->APB1ENR1, Periphs);
01072 }
01073
01074 /**
01075   * @brief  Disable APB1 peripherals clock.
01076   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n
01077   *         APB1ENR2     I2C4EN        LL_APB1_GRP2_DisableClock\n
01078   *         APB1ENR2     UCPD1EN      LL_APB1_GRP2_DisableClock
01079   * @param  Periphs This parameter can be a combination of the following values:
01080   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01081   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01082   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
01083   *
01084   *         (*) value not defined in all devices.
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
01088 {
01089   CLEAR_BIT(RCC->APB1ENR2, Periphs);
01090 }
01091
01092 /**
01093   * @brief  Force APB1 peripherals reset.
01094   * @rmtoll APB1RSTR1     TIM2RST        LL_APB1_GRP1_ForceReset\n
01095   *         APB1RSTR1     TIM3RST        LL_APB1_GRP1_ForceReset\n
01096   *         APB1RSTR1     TIM4RST        LL_APB1_GRP1_ForceReset\n
01097   *         APB1RSTR1     TIM5RST        LL_APB1_GRP1_ForceReset\n
01098   *         APB1RSTR1     TIM6RST        LL_APB1_GRP1_ForceReset\n
01099   *         APB1RSTR1     TIM7RST        LL_APB1_GRP1_ForceReset\n
01100   *         APB1RSTR1     CRSRST         LL_APB1_GRP1_ForceReset\n
01101   *         APB1RSTR1     SPI2RST        LL_APB1_GRP1_ForceReset\n
01102   *         APB1RSTR1     SPI3RST        LL_APB1_GRP1_ForceReset\n
01103   *         APB1RSTR1     USART2RST      LL_APB1_GRP1_ForceReset\n
01104   *         APB1RSTR1     USART3RST      LL_APB1_GRP1_ForceReset\n
01105   *         APB1RSTR1     UART4RST       LL_APB1_GRP1_ForceReset\n
01106   *         APB1RSTR1     UART5RST       LL_APB1_GRP1_ForceReset\n
01107   *         APB1RSTR1     I2C1RST        LL_APB1_GRP1_ForceReset\n
01108   *         APB1RSTR1     I2C2RST        LL_APB1_GRP1_ForceReset\n
01109   *         APB1RSTR1     USBRST         LL_APB1_GRP1_ForceReset\n
01110   *         APB1RSTR1     FDCANRST       LL_APB1_GRP1_ForceReset\n
01111   *         APB1RSTR1     PWRRST         LL_APB1_GRP1_ForceReset\n
01112   *         APB1RSTR1     I2C3RST        LL_APB1_GRP1_ForceReset\n
01113   *         APB1RSTR1     LPTIM1RST      LL_APB1_GRP1_ForceReset
01114   * @param  Periphs This parameter can be a combination of the following values:
01115   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01116   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01117   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01118   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01119   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01120   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01121   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01122   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01123   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01124   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01125   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01126   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01127   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01128   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01129   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01130   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01131   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
01132   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01133   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01134   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01135   *
01136   *         (*) value not defined in all devices.
01137   * @retval None
01138   */
01139 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
01140 {
01141   SET_BIT(RCC->APB1RSTR1, Periphs);
01142 }
01143
01144 /**
01145   * @brief  Force APB1 peripherals reset.
01146   * @rmtoll APB1RSTR2     LPUART1RST     LL_APB1_GRP2_ForceReset\n
01147   *         APB1RSTR2     I2C4RST        LL_APB1_GRP2_ForceReset\n
01148   *         APB1RSTR2     UCPD1RST       LL_APB1_GRP2_ForceReset
01149   * @param  Periphs This parameter can be a combination of the following values:
01150   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01151   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01152   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
01153   *
01154   *         (*) value not defined in all devices.
01155   * @retval None
01156   */
01157 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
01158 {
01159   SET_BIT(RCC->APB1RSTR2, Periphs);
01160 }
01161
01162 /**
01163   * @brief  Release APB1 peripherals reset.
01164   * @rmtoll APB1RSTR1     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
01165   *         APB1RSTR1     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
01166   *         APB1RSTR1     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
01167   *         APB1RSTR1     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
01168   *         APB1RSTR1     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
01169   *         APB1RSTR1     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
01170   *         APB1RSTR1     CRSRST         LL_APB1_GRP1_ReleaseReset\n
01171   *         APB1RSTR1     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
01172   *         APB1RSTR1     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
01173   *         APB1RSTR1     USART2RST      LL_APB1_GRP1_ReleaseReset\n
01174   *         APB1RSTR1     USART3RST      LL_APB1_GRP1_ReleaseReset\n
01175   *         APB1RSTR1     UART4RST       LL_APB1_GRP1_ReleaseReset\n
01176   *         APB1RSTR1     UART5RST       LL_APB1_GRP1_ReleaseReset\n
01177   *         APB1RSTR1     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
01178   *         APB1RSTR1     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
01179   *         APB1RSTR1     USBRST         LL_APB1_GRP1_ReleaseReset\n
01180   *         APB1RSTR1     FDCANRST       LL_APB1_GRP1_ReleaseReset\n
01181   *         APB1RSTR1     PWRRST         LL_APB1_GRP1_ReleaseReset\n
01182   *         APB1RSTR1     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
01183   *         APB1RSTR1     LPTIM1RST      LL_APB1_GRP1_ReleaseReset
01184   * @param  Periphs This parameter can be a combination of the following values:
01185   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01186   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01187   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01188   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01189   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01190   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01191   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01192   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01193   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01194   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01195   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01196   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01197   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01198   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01199   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01200   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01201   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
01202   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01203   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01204   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01205   *
01206   *         (*) value not defined in all devices.
01207   * @retval None
01208   */
01209 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
01210 {
01211   CLEAR_BIT(RCC->APB1RSTR1, Periphs);
01212 }
01213
01214 /**
01215   * @brief  Release APB1 peripherals reset.
01216   * @rmtoll APB1RSTR2     LPUART1RST     LL_APB1_GRP2_ReleaseReset\n
01217   *         APB1RSTR2     I2C4RST        LL_APB1_GRP2_ReleaseReset\n
01218   *         APB1RSTR2     UCPD1RST       LL_APB1_GRP2_ReleaseReset
01219   * @param  Periphs This parameter can be a combination of the following values:
01220   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01221   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01222   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
01223   *
01224   *         (*) value not defined in all devices.
01225   * @retval None
01226   */
01227 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
01228 {
01229   CLEAR_BIT(RCC->APB1RSTR2, Periphs);
01230 }
01231
01232 /**
01233   * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
01234   * @rmtoll APB1SMENR1     TIM2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01235   *         APB1SMENR1     TIM3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01236   *         APB1SMENR1     TIM4SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01237   *         APB1SMENR1     TIM5SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01238   *         APB1SMENR1     TIM6SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01239   *         APB1SMENR1     TIM7SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01240   *         APB1SMENR1     CRSSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
01241   *         APB1SMENR1     RTCAPBSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01242   *         APB1SMENR1     WWDGSMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01243   *         APB1SMENR1     SPI2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01244   *         APB1SMENR1     SPI3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01245   *         APB1SMENR1     USART2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01246   *         APB1SMENR1     USART3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01247   *         APB1SMENR1     UART4SMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01248   *         APB1SMENR1     UART5SMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01249   *         APB1SMENR1     I2C1SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01250   *         APB1SMENR1     I2C2SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01251   *         APB1SMENR1     USBSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
01252   *         APB1SMENR1     FDCANSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01253   *         APB1SMENR1     PWRSMEN         LL_APB1_GRP1_EnableClockStopSleep\n
01254   *         APB1SMENR1     I2C3SMEN        LL_APB1_GRP1_EnableClockStopSleep\n
01255   *         APB1SMENR1     LPTIM1SMEN      LL_APB1_GRP1_EnableClockStopSleep
01256   * @param  Periphs This parameter can be a combination of the following values:
01257   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01258   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01259   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01260   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01261   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01262   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01263   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01264   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
01265   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01266   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01267   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01268   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01269   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01270   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01271   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01272   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01273   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01274   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01275   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
01276   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01277   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01278   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01279   *
01280   *         (*) value not defined in all devices.
01281   * @retval None
01282   */
01283 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
01284 {
01285   __IO uint32_t tmpreg;
01286   SET_BIT(RCC->APB1SMENR1, Periphs);
01287   /* Delay after an RCC peripheral clock enabling */
01288   tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
01289   (void)tmpreg;
01290 }
01291
01292 /**
01293   * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
01294   * @rmtoll APB1SMENR2     LPUART1SMEN     LL_APB1_GRP2_EnableClockStopSleep\n
01295   *         APB1SMENR2     I2C4SMEN        LL_APB1_GRP2_EnableClockStopSleep\n
01296   *         APB1SMENR2     UCPD1SMEN       LL_APB1_GRP2_EnableClockStopSleep
01297   * @param  Periphs This parameter can be a combination of the following values:
01298   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01299   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01300   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
01301   *
01302   *         (*) value not defined in all devices.
01303   * @retval None
01304   */
01305 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
01306 {
01307   __IO uint32_t tmpreg;
01308   SET_BIT(RCC->APB1SMENR2, Periphs);
01309   /* Delay after an RCC peripheral clock enabling */
01310   tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
01311   (void)tmpreg;
01312 }
01313
01314 /**
01315   * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
01316   * @rmtoll APB1SMENR1     TIM2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01317   *         APB1SMENR1     TIM3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01318   *         APB1SMENR1     TIM4SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01319   *         APB1SMENR1     TIM5SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01320   *         APB1SMENR1     TIM6SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01321   *         APB1SMENR1     TIM7SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01322   *         APB1SMENR1     CRSSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
01323   *         APB1SMENR1     RTCAPBSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01324   *         APB1SMENR1     WWDGSMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01325   *         APB1SMENR1     SPI2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01326   *         APB1SMENR1     SPI3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01327   *         APB1SMENR1     USART2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01328   *         APB1SMENR1     USART3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01329   *         APB1SMENR1     UART4SMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01330   *         APB1SMENR1     UART5SMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01331   *         APB1SMENR1     I2C1SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01332   *         APB1SMENR1     I2C2SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01333   *         APB1SMENR1     USBSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
01334   *         APB1SMENR1     FDCANSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01335   *         APB1SMENR1     PWRSMEN         LL_APB1_GRP1_DisableClockStopSleep\n
01336   *         APB1SMENR1     I2C3SMEN        LL_APB1_GRP1_DisableClockStopSleep\n
01337   *         APB1SMENR1     LPTIM1SMEN      LL_APB1_GRP1_DisableClockStopSleep
01338   * @param  Periphs This parameter can be a combination of the following values:
01339   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01340   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
01341   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
01342   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01343   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01344   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01345   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01346   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
01347   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01348   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01349   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01350   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01351   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
01352   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01353   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01354   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01355   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
01356   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01357   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
01358   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01359   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01360   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01361   *
01362   *         (*) value not defined in all devices.
01363   * @retval None
01364   */
01365 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
01366 {
01367   CLEAR_BIT(RCC->APB1SMENR1, Periphs);
01368 }
01369
01370 /**
01371   * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
01372   * @rmtoll APB1SMENR2     LPUART1SMEN     LL_APB1_GRP2_DisableClockStopSleep\n
01373   *         APB1SMENR2     I2C4SMEN        LL_APB1_GRP2_DisableClockStopSleep\n
01374   *         APB1SMENR2     UCPD1SMEN      LL_APB1_GRP2_DisableClockStopSleep
01375   * @param  Periphs This parameter can be a combination of the following values:
01376   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01377   *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
01378   *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
01379   *
01380   *         (*) value not defined in all devices.
01381   * @retval None
01382   */
01383 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
01384 {
01385   CLEAR_BIT(RCC->APB1SMENR2, Periphs);
01386 }
01387
01388 /**
01389   * @}
01390   */
01391
01392 /** @defgroup BUS_LL_EF_APB2 APB2
01393   * @{
01394   */
01395
01396 /**
01397   * @brief  Enable APB2 peripherals clock.
01398   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
01399   *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
01400   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
01401   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
01402   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
01403   *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
01404   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
01405   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
01406   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
01407   *         APB2ENR      TIM20EN       LL_APB2_GRP1_EnableClock\n
01408   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
01409   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_EnableClock
01410   * @param  Periphs This parameter can be a combination of the following values:
01411   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01412   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01413   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01414   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01415   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01416   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01417   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01418   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01419   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01420   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01421   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01422   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01423   *
01424   *         (*) value not defined in all devices.
01425   * @retval None
01426   */
01427 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
01428 {
01429   __IO uint32_t tmpreg;
01430   SET_BIT(RCC->APB2ENR, Periphs);
01431   /* Delay after an RCC peripheral clock enabling */
01432   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
01433   (void)tmpreg;
01434 }
01435
01436 /**
01437   * @brief  Check if APB2 peripheral clock is enabled or not
01438   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
01439   *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
01440   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
01441   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
01442   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
01443   *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
01444   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
01445   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
01446   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
01447   *         APB2ENR      TIM20EN       LL_APB2_GRP1_IsEnabledClock\n
01448   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
01449   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_IsEnabledClock
01450   * @param  Periphs This parameter can be a combination of the following values:
01451   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01452   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01453   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01454   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01455   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01456   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01457   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01458   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01459   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01460   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01461   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01462   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01463   *
01464   *         (*) value not defined in all devices.
01465   * @retval State of Periphs (1 or 0).
01466   */
01467 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
01468 {
01469   return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
01470 }
01471
01472 /**
01473   * @brief  Disable APB2 peripherals clock.
01474   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
01475   *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
01476   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
01477   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
01478   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
01479   *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
01480   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
01481   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
01482   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
01483   *         APB2ENR      TIM20EN       LL_APB2_GRP1_DisableClock\n
01484   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
01485   *         APB2ENR      HRTIM1EN      LL_APB2_GRP1_DisableClock
01486   * @param  Periphs This parameter can be a combination of the following values:
01487   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01488   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01489   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01490   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01491   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01492   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01493   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01494   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01495   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01496   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01497   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01498   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01499   *
01500   *         (*) value not defined in all devices.
01501   * @retval None
01502   */
01503 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
01504 {
01505   CLEAR_BIT(RCC->APB2ENR, Periphs);
01506 }
01507
01508 /**
01509   * @brief  Force APB2 peripherals reset.
01510   * @rmtoll APB2RSTR      SYSCFGRST      LL_APB2_GRP1_ForceReset\n
01511   *         APB2RSTR      TIM1RST        LL_APB2_GRP1_ForceReset\n
01512   *         APB2RSTR      SPI1RST        LL_APB2_GRP1_ForceReset\n
01513   *         APB2RSTR      TIM8RST        LL_APB2_GRP1_ForceReset\n
01514   *         APB2RSTR      USART1RST      LL_APB2_GRP1_ForceReset\n
01515   *         APB2RSTR      SPI4RST        LL_APB2_GRP1_ForceReset\n
01516   *         APB2RSTR      TIM15RST       LL_APB2_GRP1_ForceReset\n
01517   *         APB2RSTR      TIM16RST       LL_APB2_GRP1_ForceReset\n
01518   *         APB2RSTR      TIM17RST       LL_APB2_GRP1_ForceReset\n
01519   *         APB2RSTR      TIM20RST       LL_APB2_GRP1_ForceReset\n
01520   *         APB2RSTR      SAI1RST        LL_APB2_GRP1_ForceReset\n
01521   *         APB2RSTR      HRTIM1RST      LL_APB2_GRP1_ForceReset
01522   * @param  Periphs This parameter can be a combination of the following values:
01523   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01524   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01525   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01526   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01527   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01528   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01529   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01530   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01531   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01532   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01533   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01534   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01535   *
01536   *         (*) value not defined in all devices.
01537   * @retval None
01538   */
01539 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
01540 {
01541   SET_BIT(RCC->APB2RSTR, Periphs);
01542 }
01543
01544 /**
01545   * @brief  Release APB2 peripherals reset.
01546   * @rmtoll APB2RSTR      SYSCFGRST      LL_APB2_GRP1_ForceReset\n
01547   *         APB2RSTR      TIM1RST        LL_APB2_GRP1_ForceReset\n
01548   *         APB2RSTR      SPI1RST        LL_APB2_GRP1_ForceReset\n
01549   *         APB2RSTR      TIM8RST        LL_APB2_GRP1_ForceReset\n
01550   *         APB2RSTR      USART1RST      LL_APB2_GRP1_ForceReset\n
01551   *         APB2RSTR      SPI4RST        LL_APB2_GRP1_ForceReset\n
01552   *         APB2RSTR      TIM15RST       LL_APB2_GRP1_ForceReset\n
01553   *         APB2RSTR      TIM16RST       LL_APB2_GRP1_ForceReset\n
01554   *         APB2RSTR      TIM17RST       LL_APB2_GRP1_ForceReset\n
01555   *         APB2RSTR      TIM20RST       LL_APB2_GRP1_ForceReset\n
01556   *         APB2RSTR      SAI1RST        LL_APB2_GRP1_ForceReset\n
01557   *         APB2RSTR      HRTIM1RST      LL_APB2_GRP1_ForceReset
01558   * @param  Periphs This parameter can be a combination of the following values:
01559   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01560   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01561   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01562   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01563   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01564   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01565   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01566   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01567   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01568   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01569   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01570   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01571   *
01572   *         (*) value not defined in all devices.
01573   * @retval None
01574   */
01575 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01576 {
01577   CLEAR_BIT(RCC->APB2RSTR, Periphs);
01578 }
01579
01580 /**
01581   * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
01582   * @rmtoll APB2SMENR      SYSCFGSMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01583   *         APB2SMENR      TIM1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
01584   *         APB2SMENR      SPI1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
01585   *         APB2SMENR      TIM8SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
01586   *         APB2SMENR      USART1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01587   *         APB2SMENR      SPI4SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
01588   *         APB2SMENR      TIM15SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
01589   *         APB2SMENR      TIM16SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
01590   *         APB2SMENR      TIM17SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
01591   *         APB2SMENR      TIM20SMEN       LL_APB2_GRP1_EnableClockStopSleep\n
01592   *         APB2SMENR      SAI1SMEN        LL_APB2_GRP1_EnableClockStopSleep\n
01593   *         APB2SMENR      HRTIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep
01594   * @param  Periphs This parameter can be a combination of the following values:
01595   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01596   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01597   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01598   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01599   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01600   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01601   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01602   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01603   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01604   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01605   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01606   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01607   *
01608   *         (*) value not defined in all devices.
01609   * @retval None
01610   */
01611 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
01612 {
01613   __IO uint32_t tmpreg;
01614   SET_BIT(RCC->APB2SMENR, Periphs);
01615   /* Delay after an RCC peripheral clock enabling */
01616   tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
01617   (void)tmpreg;
01618 }
01619
01620 /**
01621   * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
01622   * @rmtoll APB2SMENR      SYSCFGSMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01623   *         APB2SMENR      TIM1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
01624   *         APB2SMENR      SPI1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
01625   *         APB2SMENR      TIM8SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
01626   *         APB2SMENR      USART1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01627   *         APB2SMENR      SPI4SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
01628   *         APB2SMENR      TIM15SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
01629   *         APB2SMENR      TIM16SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
01630   *         APB2SMENR      TIM17SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
01631   *         APB2SMENR      TIM20SMEN       LL_APB2_GRP1_DisableClockStopSleep\n
01632   *         APB2SMENR      SAI1SMEN        LL_APB2_GRP1_DisableClockStopSleep\n
01633   *         APB2SMENR      HRTIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep
01634   * @param  Periphs This parameter can be a combination of the following values:
01635   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01636   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01637   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01638   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
01639   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01640   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
01641   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01642   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01643   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01644   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
01645   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01646   *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
01647   *
01648   *         (*) value not defined in all devices.
01649   * @retval None
01650   */
01651 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
01652 {
01653   CLEAR_BIT(RCC->APB2SMENR, Periphs);
01654 }
01655
01656 /**
01657   * @}
01658   */
01659
01660
01661 /**
01662   * @}
01663   */
01664
01665 /**
01666   * @}
01667   */
01668
01669 #endif /* defined(RCC) */
01670
01671 /**
01672   * @}
01673   */
01674
01675 #ifdef __cplusplus
01676 }
01677 #endif
01678
01679 #endif /* STM32G4xx_LL_BUS_H */
01680
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_comp.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_comp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32g4xx_ll_comp.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034
00035
00036 /** @addtogroup COMP_LL COMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /** @addtogroup COMP_LL_Private_Macros
00046   * @{
00047   */
00048
00049 /* Check of parameters for configuration of COMP hierarchical scope:          */
00050 /* COMP instance.                                                             */
00051
00052 /* Note: On this STM32 series, comparator input plus parameters are           */
00053 /*       the same on all COMP instances.                                      */
00054 /*       However, comparator instance kept as macro parameter for             */
00055 /*       compatibility with other STM32 families.                             */
00056 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00057   (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                                \
00058    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00059   )
00060 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00061 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00062   (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)  ||                   \
00063    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)  ||                  \
00064    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)  ||                  \
00065    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)     ||                  \
00066    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)         ||                  \
00067    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)         ||                  \
00068    (((__COMP_INSTANCE__) == COMP1)                        &&                  \
00069     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00070      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
00071    )                                                      ||                  \
00072    (((__COMP_INSTANCE__) == COMP2)                        &&                  \
00073     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)  ||                   \
00074      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
00075    )                                                      ||                  \
00076    (((__COMP_INSTANCE__) == COMP3)                        &&                  \
00077     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00078      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
00079    )                                                      ||                  \
00080    (((__COMP_INSTANCE__) == COMP4)                        &&                  \
00081     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00082      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
00083    )                                                      ||                  \
00084    (((__COMP_INSTANCE__) == COMP5)                        &&                  \
00085     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)  ||                   \
00086      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1))                       \
00087    )                                                      ||                  \
00088    (((__COMP_INSTANCE__) == COMP6)                        &&                  \
00089     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1)  ||                   \
00090      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH2))                       \
00091    )                                                      ||                  \
00092    (((__COMP_INSTANCE__) == COMP7)                        &&                  \
00093     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1)  ||                   \
00094      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1))                       \
00095    ))
00096 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
00097 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00098   (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)  ||                   \
00099    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)  ||                   \
00100    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)  ||                   \
00101    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)     ||                   \
00102    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)         ||                   \
00103    ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)         ||                   \
00104    (((__COMP_INSTANCE__) == COMP1)                        &&                   \
00105     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00106      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
00107    )                                                      ||                   \
00108    (((__COMP_INSTANCE__) == COMP2)                        &&                   \
00109     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)  ||                   \
00110      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
00111    )                                                      ||                   \
00112    (((__COMP_INSTANCE__) == COMP3)                        &&                   \
00113     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00114      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1))                       \
00115    )                                                      ||                   \
00116    (((__COMP_INSTANCE__) == COMP4)                        &&                   \
00117     (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)  ||                   \
00118      ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2))                       \
00119    ))
00120 #endif
00121
00122 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00123   (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                         \
00124    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_10MV)                      \
00125    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_20MV)                      \
00126    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_30MV)                      \
00127    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_40MV)                      \
00128    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_50MV)                      \
00129    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_60MV)                      \
00130    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_70MV)                      \
00131   )
00132
00133 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00134   (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                           \
00135    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00136   )
00137
00138 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00139 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
00140   ((((__INSTANCE__) == COMP1) &&                                                  \
00141     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00142      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||     \
00143      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||     \
00144      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||     \
00145      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1)))       \
00146    ||                                                                             \
00147    (((__INSTANCE__) == COMP2) &&                                                  \
00148     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00149      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||     \
00150      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||     \
00151      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||     \
00152      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)))       \
00153    ||                                                                             \
00154    (((__INSTANCE__) == COMP3) &&                                                  \
00155     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00156      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||     \
00157      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||     \
00158      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||     \
00159      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3)))       \
00160    ||                                                                             \
00161    (((__INSTANCE__) == COMP4) &&                                                  \
00162     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00163      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||     \
00164      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||     \
00165      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||     \
00166      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)))      \
00167    ||                                                                             \
00168    (((__INSTANCE__) == COMP5) &&                                                  \
00169     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00170      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5)  ||     \
00171      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5)  ||     \
00172      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5)  ||     \
00173      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5)))       \
00174    ||                                                                             \
00175    (((__INSTANCE__) == COMP6) &&                                                  \
00176     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00177      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6)  ||     \
00178      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6)  ||     \
00179      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6)  ||     \
00180      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6)))      \
00181    ||                                                                             \
00182    (((__INSTANCE__) == COMP7) &&                                                  \
00183     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00184      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7)  ||     \
00185      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7)  ||     \
00186      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7)  ||     \
00187      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7)))      \
00188    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5)             \
00189    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)             \
00190    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3)              \
00191   )
00192 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
00193 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
00194   ((((__INSTANCE__) == COMP1) &&                                                  \
00195     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00196      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||     \
00197      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||     \
00198      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||     \
00199      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1)))       \
00200    ||                                                                             \
00201    (((__INSTANCE__) == COMP2) &&                                                  \
00202     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00203      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||     \
00204      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||     \
00205      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||     \
00206      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)))       \
00207    ||                                                                             \
00208    (((__INSTANCE__) == COMP3) &&                                                  \
00209     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00210      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||     \
00211      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||     \
00212      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||     \
00213      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3)))       \
00214    ||                                                                             \
00215    (((__INSTANCE__) == COMP4) &&                                                  \
00216     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00217      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||     \
00218      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||     \
00219      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||     \
00220      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)))      \
00221    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)             \
00222    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3)              \
00223   )
00224 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
00225 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
00226   ((((__INSTANCE__) == COMP1) &&                                                  \
00227     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00228      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||     \
00229      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||     \
00230      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||     \
00231      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1)))       \
00232    ||                                                                             \
00233    (((__INSTANCE__) == COMP2) &&                                                  \
00234     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00235      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||     \
00236      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||     \
00237      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||     \
00238      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)))       \
00239    ||                                                                             \
00240    (((__INSTANCE__) == COMP3) &&                                                  \
00241     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00242      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||     \
00243      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||     \
00244      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||     \
00245      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3)))       \
00246    ||                                                                             \
00247    (((__INSTANCE__) == COMP4) &&                                                  \
00248     (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)            ||     \
00249      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||     \
00250      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||     \
00251      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||     \
00252      ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4)))      \
00253    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5)             \
00254    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1)             \
00255    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3)              \
00256   )
00257 #endif
00258 /**
00259   * @}
00260   */
00261
00262
00263 /* Private function prototypes -----------------------------------------------*/
00264
00265 /* Exported functions --------------------------------------------------------*/
00266 /** @addtogroup COMP_LL_Exported_Functions
00267   * @{
00268   */
00269
00270 /** @addtogroup COMP_LL_EF_Init
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  De-initialize registers of the selected COMP instance
00276   *         to their default reset values.
00277   * @note   If comparator is locked, de-initialization by software is
00278   *         not possible.
00279   *         The only way to unlock the comparator is a device hardware reset.
00280   * @param  COMPx COMP instance
00281   * @retval An ErrorStatus enumeration value:
00282   *          - SUCCESS: COMP registers are de-initialized
00283   *          - ERROR: COMP registers are not de-initialized
00284   */
00285 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00286 {
00287   ErrorStatus status = SUCCESS;
00288
00289   /* Check the parameters */
00290   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00291
00292   /* Note: Hardware constraint (refer to description of this function):       */
00293   /*       COMP instance must not be locked.                                  */
00294   if (LL_COMP_IsLocked(COMPx) == 0UL)
00295   {
00296     LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL);
00297
00298   }
00299   else
00300   {
00301     /* Comparator instance is locked: de-initialization by software is         */
00302     /* not possible.                                                           */
00303     /* The only way to unlock the comparator is a device hardware reset.       */
00304     status = ERROR;
00305   }
00306
00307   return status;
00308 }
00309
00310 /**
00311   * @brief  Initialize some features of COMP instance.
00312   * @note   This function configures features of the selected COMP instance.
00313   *         Some features are also available at scope COMP common instance
00314   *         (common to several COMP instances).
00315   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00316   * @param  COMPx COMP instance
00317   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00318   * @retval An ErrorStatus enumeration value:
00319   *          - SUCCESS: COMP registers are initialized
00320   *          - ERROR: COMP registers are not initialized
00321   */
00322 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
00323 {
00324   ErrorStatus status = SUCCESS;
00325
00326   /* Check the parameters */
00327   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00328   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00329   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00330   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00331   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00332   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
00333
00334   /* Note: Hardware constraint (refer to description of this function)        */
00335   /*       COMP instance must not be locked.                                  */
00336   if (LL_COMP_IsLocked(COMPx) == 0UL)
00337   {
00338     /* Configuration of comparator instance :                                 */
00339     /*  - InputPlus                                                           */
00340     /*  - InputMinus                                                          */
00341     /*  - InputHysteresis                                                     */
00342     /*  - OutputPolarity                                                      */
00343     /*  - OutputBlankingSource                                                */
00344     MODIFY_REG(COMPx->CSR,
00345                COMP_CSR_INPSEL
00346                | COMP_CSR_SCALEN
00347                | COMP_CSR_BRGEN
00348                | COMP_CSR_INMSEL
00349                | COMP_CSR_HYST
00350                | COMP_CSR_POLARITY
00351                | COMP_CSR_BLANKING
00352                ,
00353                COMP_InitStruct->InputPlus
00354                | COMP_InitStruct->InputMinus
00355                | COMP_InitStruct->InputHysteresis
00356                | COMP_InitStruct->OutputPolarity
00357                | COMP_InitStruct->OutputBlankingSource
00358               );
00359
00360   }
00361   else
00362   {
00363     /* Initialization error: COMP instance is locked.                         */
00364     status = ERROR;
00365   }
00366
00367   return status;
00368 }
00369
00370 /**
00371   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00372   * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00373   *                        whose fields will be set to default values.
00374   * @retval None
00375   */
00376 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00377 {
00378   /* Set COMP_InitStruct fields to default values */
00379   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00380   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00381   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00382   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00383   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00384 }
00385
00386 /**
00387   * @}
00388   */
00389
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397
00398
00399
00400 /**
00401   * @}
00402   */
00403
00404 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_comp.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_comp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_COMP_H
00021 #define STM32G4xx_LL_COMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034
00035
00036 /** @defgroup COMP_LL COMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @defgroup COMP_LL_Private_Macros COMP Private Macros
00046   * @{
00047   */
00048
00049 /**
00050   * @}
00051   */
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 #if defined(USE_FULL_LL_DRIVER)
00055 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00056   * @{
00057   */
00058
00059 /**
00060   * @brief  Structure definition of some features of COMP instance.
00061   */
00062 typedef struct
00063 {
00064   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00065                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00066                                              This feature can be modified afterwards using unitary function
00067                                              @ref LL_COMP_SetInputPlus(). */
00068
00069   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00070                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00071                                              This feature can be modified afterwards using unitary function
00072                                               @ref LL_COMP_SetInputMinus(). */
00073
00074   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00075                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00076                                              This feature can be modified afterwards using unitary function
00077                                              @ref LL_COMP_SetInputHysteresis(). */
00078
00079   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00080                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00081                                              This feature can be modified afterwards using unitary function
00082                                              @ref LL_COMP_SetOutputPolarity(). */
00083
00084   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00085                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00086                                              This feature can be modified afterwards using unitary function
00087                                              @ref LL_COMP_SetOutputBlankingSource(). */
00088
00089 } LL_COMP_InitTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094 #endif /* USE_FULL_LL_DRIVER */
00095
00096 /* Exported constants --------------------------------------------------------*/
00097 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00102   * @{
00103   */
00104 #define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                          /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00105 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL)                       /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00111   * @{
00112   */
00113 #define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
00114 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
00115 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
00116 #define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00117 #define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
00118 #define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
00119 #define LL_COMP_INPUT_MINUS_DAC2_CH1    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
00120 #define LL_COMP_INPUT_MINUS_DAC3_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
00121 #define LL_COMP_INPUT_MINUS_DAC3_CH2    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
00122 #define LL_COMP_INPUT_MINUS_DAC4_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
00123 #define LL_COMP_INPUT_MINUS_DAC4_CH2    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
00124 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00125 #define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00132   * @{
00133   */
00134 #define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                                       /*!< No hysteresis */
00135 #define LL_COMP_HYSTERESIS_10MV         (                                    COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
00136 #define LL_COMP_HYSTERESIS_20MV         (                  COMP_CSR_HYST_1                  ) /*!< Hysteresis level 20mV */
00137 #define LL_COMP_HYSTERESIS_30MV         (                  COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
00138 #define LL_COMP_HYSTERESIS_40MV         (COMP_CSR_HYST_2                                    ) /*!< Hysteresis level 40mV */
00139 #define LL_COMP_HYSTERESIS_50MV         (COMP_CSR_HYST_2                   | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
00140 #define LL_COMP_HYSTERESIS_60MV         (COMP_CSR_HYST_2 | COMP_CSR_HYST_1                  ) /*!< Hysteresis level 60mV */
00141 #define LL_COMP_HYSTERESIS_70MV         (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
00142 #define LL_COMP_HYSTERESIS_LOW          LL_COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
00143 #define LL_COMP_HYSTERESIS_MEDIUM       LL_COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
00144 #define LL_COMP_HYSTERESIS_HIGH         LL_COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00150   * @{
00151   */
00152 #define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00153 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00159   * @{
00160   */
00161 #define LL_COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00162 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
00163 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
00164 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
00165 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
00166 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
00167 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
00168 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
00169 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
00170 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
00171 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
00172 #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
00173 #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
00174 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
00175 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
00176 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
00177 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
00178 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
00179 #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
00180 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
00181 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
00182 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
00183 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
00184 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
00185 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
00186 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
00187 #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
00188 #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
00189 #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
00190 #define LL_COMP_BLANKINGSRC_TIM20_OC5       (COMP_CSR_BLANKING_2 |                       COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances). Note: For TIM20 instance availability, please refer to datasheet */
00191 #define LL_COMP_BLANKINGSRC_TIM15_OC1       (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances). */
00192 #define LL_COMP_BLANKINGSRC_TIM4_OC3        (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances). */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00199   * @{
00200   */
00201 #define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)          /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00202 #define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)          /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00208   * @note   Only COMP peripheral HW delays are defined in COMP LL driver driver,
00209   *         not timeout values.
00210   *         For details on delays values, refer to descriptions in source code
00211   *         above each literal definition.
00212   * @{
00213   */
00214
00215 /* Delay for comparator startup time.                                         */
00216 /* Note: Delay required to reach propagation delay specification.             */
00217 /* Literal set to maximum value (refer to device datasheet,                   */
00218 /* parameter "tSTART").                                                       */
00219 /* Unit: us                                                                   */
00220 #define LL_COMP_DELAY_STARTUP_US          (  5UL) /*!< Delay for COMP startup time */
00221
00222 /* Delay for comparator voltage scaler stabilization time.                    */
00223 /* Note: Voltage scaler is used when selecting comparator input               */
00224 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00225 /* Literal set to maximum value (refer to device datasheet,                   */
00226 /* parameter "tSTART_SCALER").                                                */
00227 /* Unit: us                                                                   */
00228 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
00229
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /* Exported macro ------------------------------------------------------------*/
00239 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00240   * @{
00241   */
00242 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00243   * @{
00244   */
00245
00246 /**
00247   * @brief  Write a value in COMP register
00248   * @param  __INSTANCE__ comparator instance
00249   * @param  __REG__ Register to be written
00250   * @param  __VALUE__ Value to be written in the register
00251   * @retval None
00252   */
00253 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00254
00255 /**
00256   * @brief  Read a value in COMP register
00257   * @param  __INSTANCE__ comparator instance
00258   * @param  __REG__ Register to be read
00259   * @retval Register value
00260   */
00261 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00267   * @{
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /* Exported functions --------------------------------------------------------*/
00279 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00280   * @{
00281   */
00282
00283 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00284   * @{
00285   */
00286
00287 /**
00288   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00289   * @note   In case of comparator input selected to be connected to IO:
00290   *         GPIO pins are specific to each comparator instance.
00291   *         Refer to description of parameters or to reference manual.
00292   * @note   On this STM32 series, scaler bridge is configurable:
00293   *         to optimize power consumption, this function enables the
00294   *         voltage scaler bridge only when required
00295   *         (when selecting comparator input based on VrefInt: VrefInt or
00296   *         subdivision of VrefInt).
00297   *         - For scaler bridge power consumption values,
00298   *           refer to device datasheet, parameter "IDDA(SCALER)".
00299   *         - Voltage scaler requires a delay for voltage stabilization.
00300   *           Refer to device datasheet, parameter "tSTART_SCALER".
00301   *         - Scaler bridge is common for all comparator instances,
00302   *           therefore if at least one of the comparator instance
00303   *           is requiring the scaler bridge, it remains enabled.
00304   * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
00305   *         CSR      INPSEL         LL_COMP_ConfigInputs\n
00306   *         CSR      BRGEN          LL_COMP_ConfigInputs\n
00307   *         CSR      SCALEN         LL_COMP_ConfigInputs
00308   * @param  COMPx Comparator instance
00309   * @param  InputMinus This parameter can be one of the following values:
00310   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00311   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00312   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00313   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00314   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
00315   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
00316   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
00317   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
00318   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
00319   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
00320   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
00321   *         (a,b...) Only available for COMPa, COMPb...
00322   *                  For COMPx & DACx instances availability, please refer to datasheet
00323   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00324   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00325   * @param  InputPlus This parameter can be one of the following values:
00326   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00327   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00328   * @retval None
00329   */
00330 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00331 {
00332   MODIFY_REG(COMPx->CSR,
00333              COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
00334              InputMinus | InputPlus);
00335 }
00336
00337 /**
00338   * @brief  Set comparator input plus (non-inverting).
00339   * @note   In case of comparator input selected to be connected to IO:
00340   *         GPIO pins are specific to each comparator instance.
00341   *         Refer to description of parameters or to reference manual.
00342   * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
00343   * @param  COMPx Comparator instance
00344   * @param  InputPlus This parameter can be one of the following values:
00345   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00346   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00347   * @retval None
00348   */
00349 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00350 {
00351   MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
00352 }
00353
00354 /**
00355   * @brief  Get comparator input plus (non-inverting).
00356   * @note   In case of comparator input selected to be connected to IO:
00357   *         GPIO pins are specific to each comparator instance.
00358   *         Refer to description of parameters or to reference manual.
00359   * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
00360   * @param  COMPx Comparator instance
00361   * @retval Returned value can be one of the following values:
00362   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00363   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00364   */
00365 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx)
00366 {
00367   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
00368 }
00369
00370 /**
00371   * @brief  Set comparator input minus (inverting).
00372   * @note   In case of comparator input selected to be connected to IO:
00373   *         GPIO pins are specific to each comparator instance.
00374   *         Refer to description of parameters or to reference manual.
00375   * @note   On this STM32 series, scaler bridge is configurable:
00376   *         to optimize power consumption, this function enables the
00377   *         voltage scaler bridge only when required
00378   *         (when selecting comparator input based on VrefInt: VrefInt or
00379   *         subdivision of VrefInt).
00380   *         - For scaler bridge power consumption values,
00381   *           refer to device datasheet, parameter "IDDA(SCALER)".
00382   *         - Voltage scaler requires a delay for voltage stabilization.
00383   *           Refer to device datasheet, parameter "tSTART_SCALER".
00384   *         - Scaler bridge is common for all comparator instances,
00385   *           therefore if at least one of the comparator instance
00386   *           is requiring the scaler bridge, it remains enabled.
00387   * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
00388   *         CSR      BRGEN          LL_COMP_SetInputMinus\n
00389   *         CSR      SCALEN         LL_COMP_SetInputMinus
00390   * @param  COMPx Comparator instance
00391   * @param  InputMinus This parameter can be one of the following values:
00392   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00393   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00394   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00395   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00396   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
00397   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
00398   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
00399   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
00400   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
00401   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
00402   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
00403   *         (a,b...) Only available for COMPa, COMPb...
00404   *                  For COMPx & DACx instances availability, please refer to datasheet
00405   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00406   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00407   * @retval None
00408   */
00409 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00410 {
00411   MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
00412 }
00413
00414 /**
00415   * @brief  Get comparator input minus (inverting).
00416   * @note   In case of comparator input selected to be connected to IO:
00417   *         GPIO pins are specific to each comparator instance.
00418   *         Refer to description of parameters or to reference manual.
00419   * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
00420   *         CSR      BRGEN          LL_COMP_GetInputMinus\n
00421   *         CSR      SCALEN         LL_COMP_GetInputMinus
00422   * @param  COMPx Comparator instance
00423   * @retval Returned value can be one of the following values:
00424   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00425   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00426   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00427   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00428   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
00429   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
00430   *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
00431   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
00432   *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
00433   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
00434   *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
00435   *         (a,b...) Only available for COMPa, COMPb...
00436   *                  For COMPx & DACx instances availability, please refer to datasheet
00437   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00438   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00439   */
00440 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx)
00441 {
00442   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
00443 }
00444
00445 /**
00446   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
00447   * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
00448   * @param  COMPx Comparator instance
00449   * @param  InputHysteresis This parameter can be one of the following values:
00450   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00451   *         @arg @ref LL_COMP_HYSTERESIS_10MV
00452   *         @arg @ref LL_COMP_HYSTERESIS_20MV
00453   *         @arg @ref LL_COMP_HYSTERESIS_30MV
00454   *         @arg @ref LL_COMP_HYSTERESIS_40MV
00455   *         @arg @ref LL_COMP_HYSTERESIS_50MV
00456   *         @arg @ref LL_COMP_HYSTERESIS_60MV
00457   *         @arg @ref LL_COMP_HYSTERESIS_70MV
00458   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00459   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00460   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00461   * @retval None
00462   */
00463 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
00464 {
00465   MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
00466 }
00467
00468 /**
00469   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
00470   * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
00471   * @param  COMPx Comparator instance
00472   * @retval Returned value can be one of the following values:
00473   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00474   *         @arg @ref LL_COMP_HYSTERESIS_10MV
00475   *         @arg @ref LL_COMP_HYSTERESIS_20MV
00476   *         @arg @ref LL_COMP_HYSTERESIS_30MV
00477   *         @arg @ref LL_COMP_HYSTERESIS_40MV
00478   *         @arg @ref LL_COMP_HYSTERESIS_50MV
00479   *         @arg @ref LL_COMP_HYSTERESIS_60MV
00480   *         @arg @ref LL_COMP_HYSTERESIS_70MV
00481   */
00482 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx)
00483 {
00484   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
00485 }
00486
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
00492   * @{
00493   */
00494
00495 /**
00496   * @brief  Set comparator instance output polarity.
00497   * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
00498   * @param  COMPx Comparator instance
00499   * @param  OutputPolarity This parameter can be one of the following values:
00500   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00501   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00502   * @retval None
00503   */
00504 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
00505 {
00506   MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
00507 }
00508
00509 /**
00510   * @brief  Get comparator instance output polarity.
00511   * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
00512   * @param  COMPx Comparator instance
00513   * @retval Returned value can be one of the following values:
00514   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00515   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00516   */
00517 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx)
00518 {
00519   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
00520 }
00521
00522 /**
00523   * @brief  Set comparator instance blanking source.
00524   * @note   Blanking source may be specific to each comparator instance.
00525   *         Refer to description of parameters or to reference manual.
00526   * @note   Availability of parameters of blanking source from timer
00527   *         depends on timers availability on the selected device.
00528   * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
00529   * @param  COMPx Comparator instance
00530   * @param  BlankingSource This parameter can be one of the following values:
00531   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00532   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
00533   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
00534   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
00535   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
00536   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
00537   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
00538   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
00539   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
00540   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
00541   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
00542   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
00543   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
00544   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
00545   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
00546   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
00547   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
00548   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
00549   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
00550   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
00551   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
00552   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
00553   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
00554   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
00555   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
00556   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
00557   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
00558   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
00559   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
00560   *         @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
00561   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
00562   *         @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
00563   *
00564   *         On STM32G4 series, blanking sources are linked to COMP instance (except
00565   *         those without COMPx suffix that are common to all instances)
00566   *         Note: For COMPx & TIMx instances availability, please refer to datasheet
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
00570 {
00571   MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
00572 }
00573
00574 /**
00575   * @brief  Get comparator instance blanking source.
00576   * @note   Availability of parameters of blanking source from timer
00577   *         depends on timers availability on the selected device.
00578   * @note   Blanking source may be specific to each comparator instance.
00579   *         Refer to description of parameters or to reference manual.
00580   * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
00581   * @param  COMPx Comparator instance
00582   * @retval Returned value can be one of the following values:
00583   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00584   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
00585   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
00586   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
00587   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
00588   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
00589   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
00590   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
00591   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
00592   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
00593   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
00594   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
00595   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
00596   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
00597   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
00598   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
00599   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
00600   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
00601   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
00602   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
00603   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
00604   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
00605   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
00606   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
00607   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
00608   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
00609   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
00610   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
00611   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
00612   *         @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
00613   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
00614   *         @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
00615   *
00616   *         On STM32G4 series, blanking sources are linked to COMP instance (except
00617   *         those without COMPx suffix that are common to all instances)
00618   *         Note: For COMPx & TIMx instances availability, please refer to datasheet
00619   */
00620 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx)
00621 {
00622   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
00623 }
00624
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
00630   * @{
00631   */
00632
00633 /**
00634   * @brief  Enable comparator instance.
00635   * @note   After enable from off state, comparator requires a delay
00636   *         to reach reach propagation delay specification.
00637   *         Refer to device datasheet, parameter "tSTART".
00638   * @rmtoll CSR      EN             LL_COMP_Enable
00639   * @param  COMPx Comparator instance
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
00643 {
00644   SET_BIT(COMPx->CSR, COMP_CSR_EN);
00645 }
00646
00647 /**
00648   * @brief  Disable comparator instance.
00649   * @rmtoll CSR      EN             LL_COMP_Disable
00650   * @param  COMPx Comparator instance
00651   * @retval None
00652   */
00653 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
00654 {
00655   CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
00656 }
00657
00658 /**
00659   * @brief  Get comparator enable state
00660   *         (0: COMP is disabled, 1: COMP is enabled)
00661   * @rmtoll CSR      EN             LL_COMP_IsEnabled
00662   * @param  COMPx Comparator instance
00663   * @retval State of bit (1 or 0).
00664   */
00665 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx)
00666 {
00667   return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
00668 }
00669
00670 /**
00671   * @brief  Lock comparator instance.
00672   * @note   Once locked, comparator configuration can be accessed in read-only.
00673   * @note   The only way to unlock the comparator is a device hardware reset.
00674   * @rmtoll CSR      LOCK           LL_COMP_Lock
00675   * @param  COMPx Comparator instance
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
00679 {
00680   SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
00681 }
00682
00683 /**
00684   * @brief  Get comparator lock state
00685   *         (0: COMP is unlocked, 1: COMP is locked).
00686   * @note   Once locked, comparator configuration can be accessed in read-only.
00687   * @note   The only way to unlock the comparator is a device hardware reset.
00688   * @rmtoll CSR      LOCK           LL_COMP_IsLocked
00689   * @param  COMPx Comparator instance
00690   * @retval State of bit (1 or 0).
00691   */
00692 __STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx)
00693 {
00694   return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
00695 }
00696
00697 /**
00698   * @brief  Read comparator instance output level.
00699   * @note   On this STM32 series, comparator 'value' is taken before
00700   *         polarity and blanking are applied, thus:
00701   *          - Comparator output is low when the input plus
00702   *            is at a lower voltage than the input minus
00703   *          - Comparator output is high when the input plus
00704   *            is at a higher voltage than the input minus
00705   * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
00706   * @param  COMPx Comparator instance
00707   * @retval Returned value can be one of the following values:
00708   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
00709   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
00710   */
00711 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx)
00712 {
00713   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
00714                     >> COMP_CSR_VALUE_Pos);
00715 }
00716
00717 /**
00718   * @}
00719   */
00720
00721 #if defined(USE_FULL_LL_DRIVER)
00722 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
00723   * @{
00724   */
00725
00726 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
00727 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct);
00728 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
00729
00730 /**
00731   * @}
00732   */
00733 #endif /* USE_FULL_LL_DRIVER */
00734
00735 /**
00736   * @}
00737   */
00738
00739 /**
00740   * @}
00741   */
00742
00743 /**
00744   * @}
00745   */
00746
00747
00748
00749 /**
00750   * @}
00751   */
00752
00753 #ifdef __cplusplus
00754 }
00755 #endif
00756
00757 #endif /* STM32G4xx_LL_COMP_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cordic.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_cordic.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_cordic.c
00004   * @author  MCD Application Team
00005   * @brief   CORDIC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_cordic.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined(CORDIC)
00034
00035 /** @addtogroup CORDIC_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /* Private function prototypes -----------------------------------------------*/
00044
00045 /* Exported functions --------------------------------------------------------*/
00046 /** @addtogroup CORDIC_LL_Exported_Functions
00047   * @{
00048   */
00049
00050 /** @addtogroup CORDIC_LL_EF_Init
00051   * @{
00052   */
00053
00054 /**
00055   * @brief  De-Initialize CORDIC peripheral registers to their default reset values.
00056   * @param  CORDICx CORDIC Instance
00057   * @retval An ErrorStatus enumeration value:
00058   *          - SUCCESS: CORDIC registers are de-initialized
00059   *          - ERROR: CORDIC registers are not de-initialized
00060   */
00061 ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx)
00062 {
00063   ErrorStatus status = SUCCESS;
00064
00065   /* Check the parameters */
00066   assert_param(IS_CORDIC_ALL_INSTANCE(CORDICx));
00067
00068   if (CORDICx == CORDIC)
00069   {
00070     /* Force CORDIC reset */
00071     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CORDIC);
00072
00073     /* Release CORDIC reset */
00074     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CORDIC);
00075   }
00076   else
00077   {
00078     status = ERROR;
00079   }
00080
00081   return (status);
00082 }
00083
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 #endif /* defined(CORDIC) */
00097
00098 /**
00099   * @}
00100   */
00101
00102 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cordic.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_cordic.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_cordic.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORDIC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_CORDIC_H
00021 #define STM32G4xx_LL_CORDIC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(CORDIC)
00035
00036 /** @defgroup CORDIC_LL CORDIC
00037   * @{
00038   */
00039
00040 /* Private variables ---------------------------------------------------------*/
00041
00042 /* Private constants ---------------------------------------------------------*/
00043
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047
00048 /* Exported constants --------------------------------------------------------*/
00049 /** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines
00054   * @brief    Flags defines which can be used with LL_CORDIC_ReadReg function.
00055   * @{
00056   */
00057 #define LL_CORDIC_FLAG_RRDY                CORDIC_CSR_RRDY
00058 /**
00059   * @}
00060   */
00061
00062 /** @defgroup CORDIC_LL_EC_IT IT Defines
00063   * @brief    IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.
00064   * @{
00065   */
00066 #define LL_CORDIC_IT_IEN                   CORDIC_CSR_IEN            /*!< Result Ready interrupt enable */
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION
00072   * @{
00073   */
00074 #define LL_CORDIC_FUNCTION_COSINE          (0x00000000U)                                                          /*!< Cosine */
00075 #define LL_CORDIC_FUNCTION_SINE            ((uint32_t)(CORDIC_CSR_FUNC_0))                                        /*!< Sine */
00076 #define LL_CORDIC_FUNCTION_PHASE           ((uint32_t)(CORDIC_CSR_FUNC_1))                                        /*!< Phase */
00077 #define LL_CORDIC_FUNCTION_MODULUS         ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))                    /*!< Modulus */
00078 #define LL_CORDIC_FUNCTION_ARCTANGENT      ((uint32_t)(CORDIC_CSR_FUNC_2))                                        /*!< Arctangent */
00079 #define LL_CORDIC_FUNCTION_HCOSINE         ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0))                    /*!< Hyperbolic Cosine */
00080 #define LL_CORDIC_FUNCTION_HSINE           ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1))                    /*!< Hyperbolic Sine */
00081 #define LL_CORDIC_FUNCTION_HARCTANGENT     ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
00082 #define LL_CORDIC_FUNCTION_NATURALLOG      ((uint32_t)(CORDIC_CSR_FUNC_3))                                        /*!< Natural Logarithm */
00083 #define LL_CORDIC_FUNCTION_SQUAREROOT      ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0))                    /*!< Square Root */
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup CORDIC_LL_EC_PRECISION PRECISION
00089   * @{
00090   */
00091 #define LL_CORDIC_PRECISION_1CYCLE         ((uint32_t)(CORDIC_CSR_PRECISION_0))
00092 #define LL_CORDIC_PRECISION_2CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_1))
00093 #define LL_CORDIC_PRECISION_3CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00094 #define LL_CORDIC_PRECISION_4CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_2))
00095 #define LL_CORDIC_PRECISION_5CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
00096 #define LL_CORDIC_PRECISION_6CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
00097 #define LL_CORDIC_PRECISION_7CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_2\
00098                                                        | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00099 #define LL_CORDIC_PRECISION_8CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_3))
00100 #define LL_CORDIC_PRECISION_9CYCLES        ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
00101 #define LL_CORDIC_PRECISION_10CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
00102 #define LL_CORDIC_PRECISION_11CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3\
00103                                                        | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
00104 #define LL_CORDIC_PRECISION_12CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
00105 #define LL_CORDIC_PRECISION_13CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3\
00106                                                        | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
00107 #define LL_CORDIC_PRECISION_14CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3\
00108                                                        | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
00109 #define LL_CORDIC_PRECISION_15CYCLES       ((uint32_t)(CORDIC_CSR_PRECISION_3\
00110                                                        | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
00111                                                        | CORDIC_CSR_PRECISION_0))
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup CORDIC_LL_EC_SCALE SCALE
00117   * @{
00118   */
00119 #define LL_CORDIC_SCALE_0                  (0x00000000U)
00120 #define LL_CORDIC_SCALE_1                  ((uint32_t)(CORDIC_CSR_SCALE_0))
00121 #define LL_CORDIC_SCALE_2                  ((uint32_t)(CORDIC_CSR_SCALE_1))
00122 #define LL_CORDIC_SCALE_3                  ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
00123 #define LL_CORDIC_SCALE_4                  ((uint32_t)(CORDIC_CSR_SCALE_2))
00124 #define LL_CORDIC_SCALE_5                  ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
00125 #define LL_CORDIC_SCALE_6                  ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
00126 #define LL_CORDIC_SCALE_7                  ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
00132   * @{
00133   */
00134 #define LL_CORDIC_NBWRITE_1                (0x00000000U)             /*!< One 32-bits write containing either only one
00135                                                                           32-bit data input (Q1.31 format), or two
00136                                                                           16-bit data input (Q1.15 format) packed
00137                                                                           in one 32 bits Data */
00138 #define LL_CORDIC_NBWRITE_2                CORDIC_CSR_NARGS          /*!< Two 32-bit write containing two 32-bits data input
00139                                                                           (Q1.31 format) */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORDIC_LL_EC_NBREAD NBREAD
00145   * @{
00146   */
00147 #define LL_CORDIC_NBREAD_1                 (0x00000000U)             /*!< One 32-bits read containing either only one
00148                                                                           32-bit data output (Q1.31 format), or two
00149                                                                           16-bit data output (Q1.15 format) packed
00150                                                                           in one 32 bits Data */
00151 #define LL_CORDIC_NBREAD_2                 CORDIC_CSR_NRES           /*!< Two 32-bit Data containing two 32-bits data output
00152                                                                           (Q1.31 format) */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup CORDIC_LL_EC_INSIZE INSIZE
00158   * @{
00159   */
00160 #define LL_CORDIC_INSIZE_32BITS            (0x00000000U)             /*!< 32 bits input data size (Q1.31 format) */
00161 #define LL_CORDIC_INSIZE_16BITS            CORDIC_CSR_ARGSIZE        /*!< 16 bits input data size (Q1.15 format) */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE
00167   * @{
00168   */
00169 #define LL_CORDIC_OUTSIZE_32BITS           (0x00000000U)             /*!< 32 bits output data size (Q1.31 format) */
00170 #define LL_CORDIC_OUTSIZE_16BITS           CORDIC_CSR_RESSIZE        /*!< 16 bits output data size (Q1.15 format) */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data
00176   * @{
00177   */
00178 #define LL_CORDIC_DMA_REG_DATA_IN          (0x00000000U)             /*!< Get address of input data register */
00179 #define LL_CORDIC_DMA_REG_DATA_OUT         (0x00000001U)             /*!< Get address of output data register */
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macro ------------------------------------------------------------*/
00189 /** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros
00190   * @{
00191   */
00192
00193 /** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros
00194   * @{
00195   */
00196
00197 /**
00198   * @brief  Write a value in CORDIC register.
00199   * @param  __INSTANCE__ CORDIC Instance
00200   * @param  __REG__ Register to be written
00201   * @param  __VALUE__ Value to be written in the register
00202   * @retval None
00203   */
00204 #define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00205
00206 /**
00207   * @brief  Read a value in CORDIC register.
00208   * @param  __INSTANCE__ CORDIC Instance
00209   * @param  __REG__ Register to be read
00210   * @retval Register value
00211   */
00212 #define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220
00221
00222 /* Exported functions --------------------------------------------------------*/
00223
00224 /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
00225   * @{
00226   */
00227
00228 /** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions
00229   * @{
00230   */
00231
00232 /**
00233   * @brief  Configure the CORDIC processing.
00234   * @note   This function set all parameters of CORDIC processing.
00235   *         These parameters can also be set individually using
00236   *         dedicated functions:
00237   *         - @ref LL_CORDIC_SetFunction()
00238   *         - @ref LL_CORDIC_SetPrecision()
00239   *         - @ref LL_CORDIC_SetScale()
00240   *         - @ref LL_CORDIC_SetNbWrite()
00241   *         - @ref LL_CORDIC_SetNbRead()
00242   *         - @ref LL_CORDIC_SetInSize()
00243   *         - @ref LL_CORDIC_SetOutSize()
00244   * @rmtoll CSR          FUNC          LL_CORDIC_Config\n
00245   *         CSR          PRECISION     LL_CORDIC_Config\n
00246   *         CSR          SCALE         LL_CORDIC_Config\n
00247   *         CSR          NARGS         LL_CORDIC_Config\n
00248   *         CSR          NRES          LL_CORDIC_Config\n
00249   *         CSR          ARGSIZE       LL_CORDIC_Config\n
00250   *         CSR          RESIZE        LL_CORDIC_Config
00251   * @param  CORDICx CORDIC instance
00252   * @param  Function parameter can be one of the following values:
00253   *         @arg @ref LL_CORDIC_FUNCTION_COSINE
00254   *         @arg @ref LL_CORDIC_FUNCTION_SINE
00255   *         @arg @ref LL_CORDIC_FUNCTION_PHASE
00256   *         @arg @ref LL_CORDIC_FUNCTION_MODULUS
00257   *         @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
00258   *         @arg @ref LL_CORDIC_FUNCTION_HCOSINE
00259   *         @arg @ref LL_CORDIC_FUNCTION_HSINE
00260   *         @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
00261   *         @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
00262   *         @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
00263   * @param  Precision parameter can be one of the following values:
00264   *         @arg @ref LL_CORDIC_PRECISION_1CYCLE
00265   *         @arg @ref LL_CORDIC_PRECISION_2CYCLES
00266   *         @arg @ref LL_CORDIC_PRECISION_3CYCLES
00267   *         @arg @ref LL_CORDIC_PRECISION_4CYCLES
00268   *         @arg @ref LL_CORDIC_PRECISION_5CYCLES
00269   *         @arg @ref LL_CORDIC_PRECISION_6CYCLES
00270   *         @arg @ref LL_CORDIC_PRECISION_7CYCLES
00271   *         @arg @ref LL_CORDIC_PRECISION_8CYCLES
00272   *         @arg @ref LL_CORDIC_PRECISION_9CYCLES
00273   *         @arg @ref LL_CORDIC_PRECISION_10CYCLES
00274   *         @arg @ref LL_CORDIC_PRECISION_11CYCLES
00275   *         @arg @ref LL_CORDIC_PRECISION_12CYCLES
00276   *         @arg @ref LL_CORDIC_PRECISION_13CYCLES
00277   *         @arg @ref LL_CORDIC_PRECISION_14CYCLES
00278   *         @arg @ref LL_CORDIC_PRECISION_15CYCLES
00279   * @param  Scale parameter can be one of the following values:
00280   *         @arg @ref LL_CORDIC_SCALE_0
00281   *         @arg @ref LL_CORDIC_SCALE_1
00282   *         @arg @ref LL_CORDIC_SCALE_2
00283   *         @arg @ref LL_CORDIC_SCALE_3
00284   *         @arg @ref LL_CORDIC_SCALE_4
00285   *         @arg @ref LL_CORDIC_SCALE_5
00286   *         @arg @ref LL_CORDIC_SCALE_6
00287   *         @arg @ref LL_CORDIC_SCALE_7
00288   * @param  NbWrite parameter can be one of the following values:
00289   *         @arg @ref LL_CORDIC_NBWRITE_1
00290   *         @arg @ref LL_CORDIC_NBWRITE_2
00291   * @param  NbRead parameter can be one of the following values:
00292   *         @arg @ref LL_CORDIC_NBREAD_1
00293   *         @arg @ref LL_CORDIC_NBREAD_2
00294   * @param  InSize parameter can be one of the following values:
00295   *         @arg @ref LL_CORDIC_INSIZE_32BITS
00296   *         @arg @ref LL_CORDIC_INSIZE_16BITS
00297   * @param  OutSize parameter can be one of the following values:
00298   *         @arg @ref LL_CORDIC_OUTSIZE_32BITS
00299   *         @arg @ref LL_CORDIC_OUTSIZE_16BITS
00300   * @retval None
00301   */
00302 __STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
00303                                       uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
00304 {
00305   MODIFY_REG(CORDICx->CSR,
00306              CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
00307              CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE,
00308              Function | Precision | Scale |
00309              NbWrite | NbRead | InSize | OutSize);
00310 }
00311
00312 /**
00313   * @brief  Configure function.
00314   * @rmtoll CSR          FUNC          LL_CORDIC_SetFunction
00315   * @param  CORDICx CORDIC Instance
00316   * @param  Function parameter can be one of the following values:
00317   *         @arg @ref LL_CORDIC_FUNCTION_COSINE
00318   *         @arg @ref LL_CORDIC_FUNCTION_SINE
00319   *         @arg @ref LL_CORDIC_FUNCTION_PHASE
00320   *         @arg @ref LL_CORDIC_FUNCTION_MODULUS
00321   *         @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
00322   *         @arg @ref LL_CORDIC_FUNCTION_HCOSINE
00323   *         @arg @ref LL_CORDIC_FUNCTION_HSINE
00324   *         @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
00325   *         @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
00326   *         @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
00327   * @retval None
00328   */
00329 __STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
00330 {
00331   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function);
00332 }
00333
00334 /**
00335   * @brief  Return function.
00336   * @rmtoll CSR          FUNC          LL_CORDIC_GetFunction
00337   * @param  CORDICx CORDIC Instance
00338   * @retval Returned value can be one of the following values:
00339   *         @arg @ref LL_CORDIC_FUNCTION_COSINE
00340   *         @arg @ref LL_CORDIC_FUNCTION_SINE
00341   *         @arg @ref LL_CORDIC_FUNCTION_PHASE
00342   *         @arg @ref LL_CORDIC_FUNCTION_MODULUS
00343   *         @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
00344   *         @arg @ref LL_CORDIC_FUNCTION_HCOSINE
00345   *         @arg @ref LL_CORDIC_FUNCTION_HSINE
00346   *         @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
00347   *         @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
00348   *         @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
00349   */
00350 __STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx)
00351 {
00352   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
00353 }
00354
00355 /**
00356   * @brief  Configure precision in cycles number.
00357   * @rmtoll CSR          PRECISION     LL_CORDIC_SetPrecision
00358   * @param  CORDICx CORDIC Instance
00359   * @param  Precision parameter can be one of the following values:
00360   *         @arg @ref LL_CORDIC_PRECISION_1CYCLE
00361   *         @arg @ref LL_CORDIC_PRECISION_2CYCLES
00362   *         @arg @ref LL_CORDIC_PRECISION_3CYCLES
00363   *         @arg @ref LL_CORDIC_PRECISION_4CYCLES
00364   *         @arg @ref LL_CORDIC_PRECISION_5CYCLES
00365   *         @arg @ref LL_CORDIC_PRECISION_6CYCLES
00366   *         @arg @ref LL_CORDIC_PRECISION_7CYCLES
00367   *         @arg @ref LL_CORDIC_PRECISION_8CYCLES
00368   *         @arg @ref LL_CORDIC_PRECISION_9CYCLES
00369   *         @arg @ref LL_CORDIC_PRECISION_10CYCLES
00370   *         @arg @ref LL_CORDIC_PRECISION_11CYCLES
00371   *         @arg @ref LL_CORDIC_PRECISION_12CYCLES
00372   *         @arg @ref LL_CORDIC_PRECISION_13CYCLES
00373   *         @arg @ref LL_CORDIC_PRECISION_14CYCLES
00374   *         @arg @ref LL_CORDIC_PRECISION_15CYCLES
00375   * @retval None
00376   */
00377 __STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
00378 {
00379   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision);
00380 }
00381
00382 /**
00383   * @brief  Return precision in cycles number.
00384   * @rmtoll CSR          PRECISION     LL_CORDIC_GetPrecision
00385   * @param  CORDICx CORDIC Instance
00386   * @retval Returned value can be one of the following values:
00387   *         @arg @ref LL_CORDIC_PRECISION_1CYCLE
00388   *         @arg @ref LL_CORDIC_PRECISION_2CYCLES
00389   *         @arg @ref LL_CORDIC_PRECISION_3CYCLES
00390   *         @arg @ref LL_CORDIC_PRECISION_4CYCLES
00391   *         @arg @ref LL_CORDIC_PRECISION_5CYCLES
00392   *         @arg @ref LL_CORDIC_PRECISION_6CYCLES
00393   *         @arg @ref LL_CORDIC_PRECISION_7CYCLES
00394   *         @arg @ref LL_CORDIC_PRECISION_8CYCLES
00395   *         @arg @ref LL_CORDIC_PRECISION_9CYCLES
00396   *         @arg @ref LL_CORDIC_PRECISION_10CYCLES
00397   *         @arg @ref LL_CORDIC_PRECISION_11CYCLES
00398   *         @arg @ref LL_CORDIC_PRECISION_12CYCLES
00399   *         @arg @ref LL_CORDIC_PRECISION_13CYCLES
00400   *         @arg @ref LL_CORDIC_PRECISION_14CYCLES
00401   *         @arg @ref LL_CORDIC_PRECISION_15CYCLES
00402   */
00403 __STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx)
00404 {
00405   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
00406 }
00407
00408 /**
00409   * @brief  Configure scaling factor.
00410   * @rmtoll CSR          SCALE         LL_CORDIC_SetScale
00411   * @param  CORDICx CORDIC Instance
00412   * @param  Scale parameter can be one of the following values:
00413   *         @arg @ref LL_CORDIC_SCALE_0
00414   *         @arg @ref LL_CORDIC_SCALE_1
00415   *         @arg @ref LL_CORDIC_SCALE_2
00416   *         @arg @ref LL_CORDIC_SCALE_3
00417   *         @arg @ref LL_CORDIC_SCALE_4
00418   *         @arg @ref LL_CORDIC_SCALE_5
00419   *         @arg @ref LL_CORDIC_SCALE_6
00420   *         @arg @ref LL_CORDIC_SCALE_7
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
00424 {
00425   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale);
00426 }
00427
00428 /**
00429   * @brief  Return scaling factor.
00430   * @rmtoll CSR          SCALE         LL_CORDIC_GetScale
00431   * @param  CORDICx CORDIC Instance
00432   * @retval Returned value can be one of the following values:
00433   *         @arg @ref LL_CORDIC_SCALE_0
00434   *         @arg @ref LL_CORDIC_SCALE_1
00435   *         @arg @ref LL_CORDIC_SCALE_2
00436   *         @arg @ref LL_CORDIC_SCALE_3
00437   *         @arg @ref LL_CORDIC_SCALE_4
00438   *         @arg @ref LL_CORDIC_SCALE_5
00439   *         @arg @ref LL_CORDIC_SCALE_6
00440   *         @arg @ref LL_CORDIC_SCALE_7
00441   */
00442 __STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx)
00443 {
00444   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
00445 }
00446
00447 /**
00448   * @brief  Configure number of 32-bit write expected for one calculation.
00449   * @rmtoll CSR          NARGS         LL_CORDIC_SetNbWrite
00450   * @param  CORDICx CORDIC Instance
00451   * @param  NbWrite parameter can be one of the following values:
00452   *         @arg @ref LL_CORDIC_NBWRITE_1
00453   *         @arg @ref LL_CORDIC_NBWRITE_2
00454   * @retval None
00455   */
00456 __STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
00457 {
00458   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite);
00459 }
00460
00461 /**
00462   * @brief  Return number of 32-bit write expected for one calculation.
00463   * @rmtoll CSR          NARGS         LL_CORDIC_GetNbWrite
00464   * @param  CORDICx CORDIC Instance
00465   * @retval Returned value can be one of the following values:
00466   *         @arg @ref LL_CORDIC_NBWRITE_1
00467   *         @arg @ref LL_CORDIC_NBWRITE_2
00468   */
00469 __STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx)
00470 {
00471   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
00472 }
00473
00474 /**
00475   * @brief  Configure number of 32-bit read expected after one calculation.
00476   * @rmtoll CSR          NRES          LL_CORDIC_SetNbRead
00477   * @param  CORDICx CORDIC Instance
00478   * @param  NbRead parameter can be one of the following values:
00479   *         @arg @ref LL_CORDIC_NBREAD_1
00480   *         @arg @ref LL_CORDIC_NBREAD_2
00481   * @retval None
00482   */
00483 __STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
00484 {
00485   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead);
00486 }
00487
00488 /**
00489   * @brief  Return number of 32-bit read expected after one calculation.
00490   * @rmtoll CSR          NRES          LL_CORDIC_GetNbRead
00491   * @param  CORDICx CORDIC Instance
00492   * @retval Returned value can be one of the following values:
00493   *         @arg @ref LL_CORDIC_NBREAD_1
00494   *         @arg @ref LL_CORDIC_NBREAD_2
00495   */
00496 __STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx)
00497 {
00498   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
00499 }
00500
00501 /**
00502   * @brief  Configure width of input data.
00503   * @rmtoll CSR          ARGSIZE       LL_CORDIC_SetInSize
00504   * @param  CORDICx CORDIC Instance
00505   * @param  InSize parameter can be one of the following values:
00506   *         @arg @ref LL_CORDIC_INSIZE_32BITS
00507   *         @arg @ref LL_CORDIC_INSIZE_16BITS
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
00511 {
00512   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize);
00513 }
00514
00515 /**
00516   * @brief  Return width of input data.
00517   * @rmtoll CSR          ARGSIZE       LL_CORDIC_GetInSize
00518   * @param  CORDICx CORDIC Instance
00519   * @retval Returned value can be one of the following values:
00520   *         @arg @ref LL_CORDIC_INSIZE_32BITS
00521   *         @arg @ref LL_CORDIC_INSIZE_16BITS
00522   */
00523 __STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx)
00524 {
00525   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
00526 }
00527
00528 /**
00529   * @brief  Configure width of output data.
00530   * @rmtoll CSR          RESIZE       LL_CORDIC_SetOutSize
00531   * @param  CORDICx CORDIC Instance
00532   * @param  OutSize parameter can be one of the following values:
00533   *         @arg @ref LL_CORDIC_OUTSIZE_32BITS
00534   *         @arg @ref LL_CORDIC_OUTSIZE_16BITS
00535   * @retval None
00536   */
00537 __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
00538 {
00539   MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize);
00540 }
00541
00542 /**
00543   * @brief  Return width of output data.
00544   * @rmtoll CSR          RESIZE       LL_CORDIC_GetOutSize
00545   * @param  CORDICx CORDIC Instance
00546   * @retval Returned value can be one of the following values:
00547   *         @arg @ref LL_CORDIC_OUTSIZE_32BITS
00548   *         @arg @ref LL_CORDIC_OUTSIZE_16BITS
00549   */
00550 __STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx)
00551 {
00552   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
00553 }
00554
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup CORDIC_LL_EF_IT_Management IT_Management
00560   * @{
00561   */
00562
00563 /**
00564   * @brief  Enable CORDIC result ready interrupt
00565   * @rmtoll CSR          IEN           LL_CORDIC_EnableIT
00566   * @param  CORDICx CORDIC Instance
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
00570 {
00571   SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
00572 }
00573
00574 /**
00575   * @brief  Disable CORDIC result ready interrupt
00576   * @rmtoll CSR          IEN           LL_CORDIC_DisableIT
00577   * @param  CORDICx CORDIC Instance
00578   * @retval None
00579   */
00580 __STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
00581 {
00582   CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
00583 }
00584
00585 /**
00586   * @brief  Check CORDIC result ready interrupt state.
00587   * @rmtoll CSR          IEN           LL_CORDIC_IsEnabledIT
00588   * @param  CORDICx CORDIC Instance
00589   * @retval State of bit (1 or 0).
00590   */
00591 __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx)
00592 {
00593   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
00594 }
00595
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management
00601   * @{
00602   */
00603
00604 /**
00605   * @brief  Enable CORDIC DMA read channel request.
00606   * @rmtoll CSR          DMAREN        LL_CORDIC_EnableDMAReq_RD
00607   * @param  CORDICx CORDIC Instance
00608   * @retval None
00609   */
00610 __STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
00611 {
00612   SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
00613 }
00614
00615 /**
00616   * @brief  Disable CORDIC DMA read channel request.
00617   * @rmtoll CSR          DMAREN        LL_CORDIC_DisableDMAReq_RD
00618   * @param  CORDICx CORDIC Instance
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
00622 {
00623   CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
00624 }
00625
00626 /**
00627   * @brief  Check CORDIC DMA read channel request state.
00628   * @rmtoll CSR          DMAREN        LL_CORDIC_IsEnabledDMAReq_RD
00629   * @param  CORDICx CORDIC Instance
00630   * @retval State of bit (1 or 0).
00631   */
00632 __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx)
00633 {
00634   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
00635 }
00636
00637 /**
00638   * @brief  Enable CORDIC DMA write channel request.
00639   * @rmtoll CSR          DMAWEN        LL_CORDIC_EnableDMAReq_WR
00640   * @param  CORDICx CORDIC Instance
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
00644 {
00645   SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
00646 }
00647
00648 /**
00649   * @brief  Disable CORDIC DMA write channel request.
00650   * @rmtoll CSR          DMAWEN        LL_CORDIC_DisableDMAReq_WR
00651   * @param  CORDICx CORDIC Instance
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
00655 {
00656   CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
00657 }
00658
00659 /**
00660   * @brief  Check CORDIC DMA write channel request state.
00661   * @rmtoll CSR          DMAWEN        LL_CORDIC_IsEnabledDMAReq_WR
00662   * @param  CORDICx CORDIC Instance
00663   * @retval State of bit (1 or 0).
00664   */
00665 __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx)
00666 {
00667   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
00668 }
00669
00670 /**
00671   * @brief  Get the CORDIC data register address used for DMA transfer.
00672   * @rmtoll RDATA        RES           LL_CORDIC_DMA_GetRegAddr\n
00673   * @rmtoll WDATA        ARG           LL_CORDIC_DMA_GetRegAddr
00674   * @param  CORDICx CORDIC Instance
00675   * @param  Direction parameter can be one of the following values:
00676   *         @arg @ref LL_CORDIC_DMA_REG_DATA_IN
00677   *         @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
00678   * @retval Address of data register
00679   */
00680 __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction)
00681 {
00682   uint32_t data_reg_addr;
00683
00684   if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
00685   {
00686     /* return address of RDATA register */
00687     data_reg_addr = (uint32_t) &(CORDICx->RDATA);
00688   }
00689   else
00690   {
00691     /* return address of WDATA register */
00692     data_reg_addr = (uint32_t) &(CORDICx->WDATA);
00693   }
00694
00695   return data_reg_addr;
00696 }
00697
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management
00703   * @{
00704   */
00705
00706 /**
00707   * @brief  Check CORDIC result ready flag state.
00708   * @rmtoll CSR          RRDY          LL_CORDIC_IsActiveFlag_RRDY
00709   * @param  CORDICx CORDIC Instance
00710   * @retval State of bit (1 or 0).
00711   */
00712 __STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx)
00713 {
00714   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
00715 }
00716
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup CORDIC_LL_EF_Data_Management Data_Management
00722   * @{
00723   */
00724
00725 /**
00726   * @brief  Write 32-bit input data for the CORDIC processing.
00727   * @rmtoll WDATA        ARG           LL_CORDIC_WriteData
00728   * @param  CORDICx CORDIC Instance
00729   * @param  InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
00733 {
00734   WRITE_REG(CORDICx->WDATA, InData);
00735 }
00736
00737 /**
00738   * @brief  Return 32-bit output data of CORDIC processing.
00739   * @rmtoll RDATA        RES           LL_CORDIC_ReadData
00740   * @param  CORDICx CORDIC Instance
00741   * @retval 32-bit output data of CORDIC processing.
00742   */
00743 __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx)
00744 {
00745   return (uint32_t)(READ_REG(CORDICx->RDATA));
00746 }
00747
00748 /**
00749   * @}
00750   */
00751
00752
00753
00754 #if defined(USE_FULL_LL_DRIVER)
00755 /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
00756   * @{
00757   */
00758 ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx);
00759
00760 /**
00761   * @}
00762   */
00763 #endif /* USE_FULL_LL_DRIVER */
00764
00765 /**
00766   * @}
00767   */
00768
00769 /**
00770   * @}
00771   */
00772
00773 #endif /* defined(CORDIC) */
00774
00775 /**
00776   * @}
00777   */
00778
00779 #ifdef __cplusplus
00780 }
00781 #endif
00782
00783 #endif /* STM32G4xx_LL_CORDIC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_cortex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_cortex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021     [..]
00022     The LL CORTEX driver contains a set of generic APIs that can be
00023     used by user:
00024       (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
00025           functions
00026       (+) Low power mode configuration (SCB register of Cortex-MCU)
00027       (+) MPU API to configure and enable regions
00028       (+) API to access to MCU info (CPUID register)
00029       (+) API to enable fault handler (SHCSR accesses)
00030
00031   @endverbatim
00032   */
00033
00034 /* Define to prevent recursive inclusion -------------------------------------*/
00035 #ifndef __STM32G4xx_LL_CORTEX_H
00036 #define __STM32G4xx_LL_CORTEX_H
00037
00038 #ifdef __cplusplus
00039 extern "C" {
00040 #endif
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32g4xx.h"
00044
00045 /** @addtogroup STM32G4xx_LL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup CORTEX_LL CORTEX
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055
00056 /* Private constants ---------------------------------------------------------*/
00057
00058 /* Private macros ------------------------------------------------------------*/
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00063   * @{
00064   */
00065
00066 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00067   * @{
00068   */
00069 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00070 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00076   * @{
00077   */
00078 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00079 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00080 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00081 /**
00082   * @}
00083   */
00084
00085 #if __MPU_PRESENT
00086
00087 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00088   * @{
00089   */
00090 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
00091 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00092 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00093 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00099   * @{
00100   */
00101 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
00102 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
00103 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
00104 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
00105 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
00106 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
00107 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
00108 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00114   * @{
00115   */
00116 #define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
00117 #define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
00118 #define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
00119 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00120 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00121 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00122 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00123 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00124 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00125 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00126 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00127 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00128 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00129 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00130 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00131 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00132 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00133 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00134 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00135 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00136 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00149   * @{
00150   */
00151 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
00152 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00153 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00154 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00155 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00156 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00162   * @{
00163   */
00164 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00165 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00166 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00167 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00173   * @{
00174   */
00175 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
00176 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00182   * @{
00183   */
00184 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00185 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00191   * @{
00192   */
00193 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00194 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00200   * @{
00201   */
00202 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00203 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
00204 /**
00205   * @}
00206   */
00207 #endif /* __MPU_PRESENT */
00208 /**
00209   * @}
00210   */
00211
00212 /* Exported macro ------------------------------------------------------------*/
00213
00214 /* Exported functions --------------------------------------------------------*/
00215 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00216   * @{
00217   */
00218
00219 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00220   * @{
00221   */
00222
00223 /**
00224   * @brief  This function checks if the Systick counter flag is active or not.
00225   * @note   It can be used in timeout function on application side.
00226   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00227   * @retval State of bit (1 or 0).
00228   */
00229 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00230 {
00231   return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
00232 }
00233
00234 /**
00235   * @brief  Configures the SysTick clock source
00236   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00237   * @param  Source This parameter can be one of the following values:
00238   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00239   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00240   * @retval None
00241   */
00242 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00243 {
00244   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00245   {
00246     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00247   }
00248   else
00249   {
00250     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00251   }
00252 }
00253
00254 /**
00255   * @brief  Get the SysTick clock source
00256   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00257   * @retval Returned value can be one of the following values:
00258   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00259   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00260   */
00261 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00262 {
00263   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00264 }
00265
00266 /**
00267   * @brief  Enable SysTick exception request
00268   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00272 {
00273   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00274 }
00275
00276 /**
00277   * @brief  Disable SysTick exception request
00278   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00279   * @retval None
00280   */
00281 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00282 {
00283   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00284 }
00285
00286 /**
00287   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00288   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00289   * @retval State of bit (1 or 0).
00290   */
00291 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00292 {
00293   return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
00294 }
00295
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00301   * @{
00302   */
00303
00304 /**
00305   * @brief  Processor uses sleep as its low power mode
00306   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00307   * @retval None
00308   */
00309 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00310 {
00311   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00312   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00313 }
00314
00315 /**
00316   * @brief  Processor uses deep sleep as its low power mode
00317   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00321 {
00322   /* Set SLEEPDEEP bit of Cortex System Control Register */
00323   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00324 }
00325
00326 /**
00327   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00328   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00329   *         empty main application.
00330   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00331   * @retval None
00332   */
00333 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00334 {
00335   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00336   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00337 }
00338
00339 /**
00340   * @brief  Do not sleep when returning to Thread mode.
00341   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00342   * @retval None
00343   */
00344 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00345 {
00346   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00347   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00348 }
00349
00350 /**
00351   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00352   *         processor.
00353   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00354   * @retval None
00355   */
00356 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00357 {
00358   /* Set SEVEONPEND bit of Cortex System Control Register */
00359   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00360 }
00361
00362 /**
00363   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00364   *         excluded
00365   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00366   * @retval None
00367   */
00368 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00369 {
00370   /* Clear SEVEONPEND bit of Cortex System Control Register */
00371   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00372 }
00373
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00379   * @{
00380   */
00381
00382 /**
00383   * @brief  Enable a fault in System handler control register (SHCSR)
00384   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00385   * @param  Fault This parameter can be a combination of the following values:
00386   *         @arg @ref LL_HANDLER_FAULT_USG
00387   *         @arg @ref LL_HANDLER_FAULT_BUS
00388   *         @arg @ref LL_HANDLER_FAULT_MEM
00389   * @retval None
00390   */
00391 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00392 {
00393   /* Enable the system handler fault */
00394   SET_BIT(SCB->SHCSR, Fault);
00395 }
00396
00397 /**
00398   * @brief  Disable a fault in System handler control register (SHCSR)
00399   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00400   * @param  Fault This parameter can be a combination of the following values:
00401   *         @arg @ref LL_HANDLER_FAULT_USG
00402   *         @arg @ref LL_HANDLER_FAULT_BUS
00403   *         @arg @ref LL_HANDLER_FAULT_MEM
00404   * @retval None
00405   */
00406 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00407 {
00408   /* Disable the system handler fault */
00409   CLEAR_BIT(SCB->SHCSR, Fault);
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00417   * @{
00418   */
00419
00420 /**
00421   * @brief  Get Implementer code
00422   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00423   * @retval Value should be equal to 0x41 for ARM
00424   */
00425 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00426 {
00427   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00428 }
00429
00430 /**
00431   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00432   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00433   * @retval Value between 0 and 255 (0x0: revision 0)
00434   */
00435 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00436 {
00437   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00438 }
00439
00440 /**
00441   * @brief  Get Architecture number
00442   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
00443   * @retval Value should be equal to 0xF for Cortex-M4 devices
00444   */
00445 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
00446 {
00447   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00448 }
00449
00450 /**
00451   * @brief  Get Part number
00452   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00453   * @retval Value should be equal to 0xC24 for Cortex-M4
00454   */
00455 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00456 {
00457   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00458 }
00459
00460 /**
00461   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00462   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00463   * @retval Value between 0 and 255 (0x1: patch 1)
00464   */
00465 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00466 {
00467   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00468 }
00469
00470 /**
00471   * @}
00472   */
00473
00474 #if __MPU_PRESENT
00475 /** @defgroup CORTEX_LL_EF_MPU MPU
00476   * @{
00477   */
00478
00479 /**
00480   * @brief  Enable MPU with input options
00481   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00482   * @param  Options This parameter can be one of the following values:
00483   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00484   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00485   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00486   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00487   * @retval None
00488   */
00489 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00490 {
00491   /* Enable the MPU*/
00492   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00493   /* Ensure MPU settings take effects */
00494   __DSB();
00495   /* Sequence instruction fetches using update settings */
00496   __ISB();
00497 }
00498
00499 /**
00500   * @brief  Disable MPU
00501   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00502   * @retval None
00503   */
00504 __STATIC_INLINE void LL_MPU_Disable(void)
00505 {
00506   /* Make sure outstanding transfers are done */
00507   __DMB();
00508   /* Disable MPU*/
00509   WRITE_REG(MPU->CTRL, 0U);
00510 }
00511
00512 /**
00513   * @brief  Check if MPU is enabled or not
00514   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00515   * @retval State of bit (1 or 0).
00516   */
00517 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00518 {
00519   return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
00520 }
00521
00522 /**
00523   * @brief  Enable a MPU region
00524   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00525   * @param  Region This parameter can be one of the following values:
00526   *         @arg @ref LL_MPU_REGION_NUMBER0
00527   *         @arg @ref LL_MPU_REGION_NUMBER1
00528   *         @arg @ref LL_MPU_REGION_NUMBER2
00529   *         @arg @ref LL_MPU_REGION_NUMBER3
00530   *         @arg @ref LL_MPU_REGION_NUMBER4
00531   *         @arg @ref LL_MPU_REGION_NUMBER5
00532   *         @arg @ref LL_MPU_REGION_NUMBER6
00533   *         @arg @ref LL_MPU_REGION_NUMBER7
00534   * @retval None
00535   */
00536 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00537 {
00538   /* Set Region number */
00539   WRITE_REG(MPU->RNR, Region);
00540   /* Enable the MPU region */
00541   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00542 }
00543
00544 /**
00545   * @brief  Configure and enable a region
00546   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00547   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00548   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00549   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00550   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00551   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00552   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00553   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00554   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00555   * @param  Region This parameter can be one of the following values:
00556   *         @arg @ref LL_MPU_REGION_NUMBER0
00557   *         @arg @ref LL_MPU_REGION_NUMBER1
00558   *         @arg @ref LL_MPU_REGION_NUMBER2
00559   *         @arg @ref LL_MPU_REGION_NUMBER3
00560   *         @arg @ref LL_MPU_REGION_NUMBER4
00561   *         @arg @ref LL_MPU_REGION_NUMBER5
00562   *         @arg @ref LL_MPU_REGION_NUMBER6
00563   *         @arg @ref LL_MPU_REGION_NUMBER7
00564   * @param  Address Value of region base address
00565   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00566   * @param  Attributes This parameter can be a combination of the following values:
00567   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00568   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00569   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00570   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00571   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00572   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00573   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00574   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00575   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00576   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00577   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00578   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00579   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00583 {
00584   /* Set Region number */
00585   WRITE_REG(MPU->RNR, Region);
00586   /* Set base address */
00587   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00588   /* Configure MPU */
00589   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
00590 }
00591
00592 /**
00593   * @brief  Disable a region
00594   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00595   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00596   * @param  Region This parameter can be one of the following values:
00597   *         @arg @ref LL_MPU_REGION_NUMBER0
00598   *         @arg @ref LL_MPU_REGION_NUMBER1
00599   *         @arg @ref LL_MPU_REGION_NUMBER2
00600   *         @arg @ref LL_MPU_REGION_NUMBER3
00601   *         @arg @ref LL_MPU_REGION_NUMBER4
00602   *         @arg @ref LL_MPU_REGION_NUMBER5
00603   *         @arg @ref LL_MPU_REGION_NUMBER6
00604   *         @arg @ref LL_MPU_REGION_NUMBER7
00605   * @retval None
00606   */
00607 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00608 {
00609   /* Set Region number */
00610   WRITE_REG(MPU->RNR, Region);
00611   /* Disable the MPU region */
00612   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00613 }
00614
00615 /**
00616   * @}
00617   */
00618
00619 #endif /* __MPU_PRESENT */
00620 /**
00621   * @}
00622   */
00623
00624 /**
00625   * @}
00626   */
00627
00628 /**
00629   * @}
00630   */
00631
00632 #ifdef __cplusplus
00633 }
00634 #endif
00635
00636 #endif /* __STM32G4xx_LL_CORTEX_H */
00637
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_crc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_crc.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (CRC)
00035
00036 /** @addtogroup CRC_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Private function prototypes -----------------------------------------------*/
00045
00046 /* Exported functions --------------------------------------------------------*/
00047 /** @addtogroup CRC_LL_Exported_Functions
00048   * @{
00049   */
00050
00051 /** @addtogroup CRC_LL_EF_Init
00052   * @{
00053   */
00054
00055 /**
00056   * @brief  De-initialize CRC registers (Registers restored to their default values).
00057   * @param  CRCx CRC Instance
00058   * @retval An ErrorStatus enumeration value:
00059   *          - SUCCESS: CRC registers are de-initialized
00060   *          - ERROR: CRC registers are not de-initialized
00061   */
00062 ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
00063 {
00064   ErrorStatus status = SUCCESS;
00065
00066   /* Check the parameters */
00067   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00068
00069   if (CRCx == CRC)
00070   {
00071     /* Force CRC reset */
00072     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
00073
00074     /* Release CRC reset */
00075     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
00076   }
00077   else
00078   {
00079     status = ERROR;
00080   }
00081
00082   return (status);
00083 }
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 #endif /* defined (CRC) */
00098
00099 /**
00100   * @}
00101   */
00102
00103 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_CRC_H
00021 #define STM32G4xx_LL_CRC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(CRC)
00035
00036 /** @defgroup CRC_LL CRC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00052   * @{
00053   */
00054 #define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
00055 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00056 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00057 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00058 /**
00059   * @}
00060   */
00061
00062 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00063   * @{
00064   */
00065 #define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
00066 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00067 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00068 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00074   * @{
00075   */
00076 #define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
00077 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00083   * @brief    Normal representation of this polynomial value is
00084   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00085   * @{
00086   */
00087 #define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00093   * @{
00094   */
00095 #define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported macro ------------------------------------------------------------*/
00105 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00106   * @{
00107   */
00108
00109 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Write a value in CRC register
00115   * @param  __INSTANCE__ CRC Instance
00116   * @param  __REG__ Register to be written
00117   * @param  __VALUE__ Value to be written in the register
00118   * @retval None
00119   */
00120 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
00121
00122 /**
00123   * @brief  Read a value in CRC register
00124   * @param  __INSTANCE__ CRC Instance
00125   * @param  __REG__ Register to be read
00126   * @retval Register value
00127   */
00128 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137
00138 /* Exported functions --------------------------------------------------------*/
00139 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00140   * @{
00141   */
00142
00143 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Reset the CRC calculation unit.
00149   * @note   If Programmable Initial CRC value feature
00150   *         is available, also set the Data Register to the value stored in the
00151   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00152   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00153   * @param  CRCx CRC Instance
00154   * @retval None
00155   */
00156 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00157 {
00158   SET_BIT(CRCx->CR, CRC_CR_RESET);
00159 }
00160
00161 /**
00162   * @brief  Configure size of the polynomial.
00163   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00164   * @param  CRCx CRC Instance
00165   * @param  PolySize This parameter can be one of the following values:
00166   *         @arg @ref LL_CRC_POLYLENGTH_32B
00167   *         @arg @ref LL_CRC_POLYLENGTH_16B
00168   *         @arg @ref LL_CRC_POLYLENGTH_8B
00169   *         @arg @ref LL_CRC_POLYLENGTH_7B
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00173 {
00174   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00175 }
00176
00177 /**
00178   * @brief  Return size of the polynomial.
00179   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00180   * @param  CRCx CRC Instance
00181   * @retval Returned value can be one of the following values:
00182   *         @arg @ref LL_CRC_POLYLENGTH_32B
00183   *         @arg @ref LL_CRC_POLYLENGTH_16B
00184   *         @arg @ref LL_CRC_POLYLENGTH_8B
00185   *         @arg @ref LL_CRC_POLYLENGTH_7B
00186   */
00187 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
00188 {
00189   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00190 }
00191
00192 /**
00193   * @brief  Configure the reversal of the bit order of the input data
00194   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00195   * @param  CRCx CRC Instance
00196   * @param  ReverseMode This parameter can be one of the following values:
00197   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00198   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00199   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00200   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00204 {
00205   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00206 }
00207
00208 /**
00209   * @brief  Return type of reversal for input data bit order
00210   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00211   * @param  CRCx CRC Instance
00212   * @retval Returned value can be one of the following values:
00213   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00214   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00215   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00217   */
00218 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
00219 {
00220   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00221 }
00222
00223 /**
00224   * @brief  Configure the reversal of the bit order of the Output data
00225   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00226   * @param  CRCx CRC Instance
00227   * @param  ReverseMode This parameter can be one of the following values:
00228   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00229   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00230   * @retval None
00231   */
00232 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00233 {
00234   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00235 }
00236
00237 /**
00238   * @brief  Return type of reversal of the bit order of the Output data
00239   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00240   * @param  CRCx CRC Instance
00241   * @retval Returned value can be one of the following values:
00242   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00243   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00244   */
00245 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
00246 {
00247   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00248 }
00249
00250 /**
00251   * @brief  Initialize the Programmable initial CRC value.
00252   * @note   If the CRC size is less than 32 bits, the least significant bits
00253   *         are used to write the correct value
00254   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00255   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00256   * @param  CRCx CRC Instance
00257   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00261 {
00262   WRITE_REG(CRCx->INIT, InitCrc);
00263 }
00264
00265 /**
00266   * @brief  Return current Initial CRC value.
00267   * @note   If the CRC size is less than 32 bits, the least significant bits
00268   *         are used to read the correct value
00269   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00270   * @param  CRCx CRC Instance
00271   * @retval Value programmed in Programmable initial CRC value register
00272   */
00273 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
00274 {
00275   return (uint32_t)(READ_REG(CRCx->INIT));
00276 }
00277
00278 /**
00279   * @brief  Initialize the Programmable polynomial value
00280   *         (coefficients of the polynomial to be used for CRC calculation).
00281   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00282   * @note   Please check Reference Manual and existing Errata Sheets,
00283   *         regarding possible limitations for Polynomial values usage.
00284   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00285   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00286   * @param  CRCx CRC Instance
00287   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00291 {
00292   WRITE_REG(CRCx->POL, PolynomCoef);
00293 }
00294
00295 /**
00296   * @brief  Return current Programmable polynomial value
00297   * @note   Please check Reference Manual and existing Errata Sheets,
00298   *         regarding possible limitations for Polynomial values usage.
00299   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00300   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00301   * @param  CRCx CRC Instance
00302   * @retval Value programmed in Programmable Polynomial value register
00303   */
00304 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
00305 {
00306   return (uint32_t)(READ_REG(CRCx->POL));
00307 }
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00314   * @{
00315   */
00316
00317 /**
00318   * @brief  Write given 32-bit data to the CRC calculator
00319   * @rmtoll DR           DR            LL_CRC_FeedData32
00320   * @param  CRCx CRC Instance
00321   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00322   * @retval None
00323   */
00324 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00325 {
00326   WRITE_REG(CRCx->DR, InData);
00327 }
00328
00329 /**
00330   * @brief  Write given 16-bit data to the CRC calculator
00331   * @rmtoll DR           DR            LL_CRC_FeedData16
00332   * @param  CRCx CRC Instance
00333   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00334   * @retval None
00335   */
00336 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00337 {
00338   __IO uint16_t *pReg;
00339
00340   pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
00341   *pReg = InData;
00342 }
00343
00344 /**
00345   * @brief  Write given 8-bit data to the CRC calculator
00346   * @rmtoll DR           DR            LL_CRC_FeedData8
00347   * @param  CRCx CRC Instance
00348   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00352 {
00353   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00354 }
00355
00356 /**
00357   * @brief  Return current CRC calculation result. 32 bits value is returned.
00358   * @rmtoll DR           DR            LL_CRC_ReadData32
00359   * @param  CRCx CRC Instance
00360   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00361   */
00362 __STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
00363 {
00364   return (uint32_t)(READ_REG(CRCx->DR));
00365 }
00366
00367 /**
00368   * @brief  Return current CRC calculation result. 16 bits value is returned.
00369   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00370   * @rmtoll DR           DR            LL_CRC_ReadData16
00371   * @param  CRCx CRC Instance
00372   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00373   */
00374 __STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
00375 {
00376   return (uint16_t)READ_REG(CRCx->DR);
00377 }
00378
00379 /**
00380   * @brief  Return current CRC calculation result. 8 bits value is returned.
00381   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00382   * @rmtoll DR           DR            LL_CRC_ReadData8
00383   * @param  CRCx CRC Instance
00384   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00385   */
00386 __STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
00387 {
00388   return (uint8_t)READ_REG(CRCx->DR);
00389 }
00390
00391 /**
00392   * @brief  Return current CRC calculation result. 7 bits value is returned.
00393   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00394   * @rmtoll DR           DR            LL_CRC_ReadData7
00395   * @param  CRCx CRC Instance
00396   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00397   */
00398 __STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
00399 {
00400   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00401 }
00402
00403 /**
00404   * @brief  Return data stored in the Independent Data(IDR) register.
00405   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00406   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00407   * @param  CRCx CRC Instance
00408   * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
00409   */
00410 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
00411 {
00412   return (uint32_t)(READ_REG(CRCx->IDR));
00413 }
00414
00415 /**
00416   * @brief  Store data in the Independent Data(IDR) register.
00417   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00418   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00419   * @param  CRCx CRC Instance
00420   * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00424 {
00425   *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
00426 }
00427 /**
00428   * @}
00429   */
00430
00431 #if defined(USE_FULL_LL_DRIVER)
00432 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00433   * @{
00434   */
00435
00436 ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
00437
00438 /**
00439   * @}
00440   */
00441 #endif /* USE_FULL_LL_DRIVER */
00442
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 #endif /* defined(CRC) */
00452
00453 /**
00454   * @}
00455   */
00456
00457 #ifdef __cplusplus
00458 }
00459 #endif
00460
00461 #endif /* STM32G4xx_LL_CRC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crs.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_crs.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   CRS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_crs.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 /** @addtogroup STM32G4xx_LL_Driver
00025   * @{
00026   */
00027
00028 #if defined(CRS)
00029
00030 /** @defgroup CRS_LL CRS
00031   * @{
00032   */
00033
00034 /* Private types -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 /* Private constants ---------------------------------------------------------*/
00037 /* Private macros ------------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039
00040 /* Exported functions --------------------------------------------------------*/
00041 /** @addtogroup CRS_LL_Exported_Functions
00042   * @{
00043   */
00044
00045 /** @addtogroup CRS_LL_EF_Init
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  De-Initializes CRS peripheral registers to their default reset values.
00051   * @retval An ErrorStatus enumeration value:
00052   *          - SUCCESS: CRS registers are de-initialized
00053   *          - ERROR: not applicable
00054   */
00055 ErrorStatus LL_CRS_DeInit(void)
00056 {
00057   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
00058   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
00059
00060   return  SUCCESS;
00061 }
00062
00063
00064
00065 /**
00066   * @}
00067   */
00068
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 #endif /* defined(CRS) */
00078
00079 /**
00080   * @}
00081   */
00082
00083 #endif /* USE_FULL_LL_DRIVER */
00084
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_crs.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_crs.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_LL_CRS_H
00021 #define __STM32G4xx_LL_CRS_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(CRS)
00035
00036 /** @defgroup CRS_LL CRS
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00052   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00053   * @{
00054   */
00055 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00056 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00057 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00058 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00059 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00060 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00061 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup CRS_LL_EC_IT IT Defines
00067   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00068   * @{
00069   */
00070 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00071 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00072 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00073 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00079   * @{
00080   */
00081 #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
00082 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00083 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00084 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00085 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00086 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00087 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00088 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00094   * @{
00095   */
00096 #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal source GPIO */
00097 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00098 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00104   * @{
00105   */
00106 #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
00107 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00113   * @{
00114   */
00115 #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
00116 #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00122   * @{
00123   */
00124 /**
00125   * @brief Reset value of the RELOAD field
00126   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00127   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00128   */
00129 #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
00130
00131 /**
00132   * @brief Reset value of Frequency error limit.
00133   */
00134 #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
00135
00136 /**
00137   * @brief Reset value of the HSI48 Calibration field
00138   * @note The default value is 64, which corresponds to the middle of the trimming interval.
00139   *       The trimming step is specified in the product datasheet.
00140   *       A higher TRIM value corresponds to a higher output frequency
00141   */
00142 #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x40U)
00143 /**
00144   * @}
00145   */
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported macro ------------------------------------------------------------*/
00151 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00152   * @{
00153   */
00154
00155 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Write a value in CRS register
00161   * @param  __INSTANCE__ CRS Instance
00162   * @param  __REG__ Register to be written
00163   * @param  __VALUE__ Value to be written in the register
00164   * @retval None
00165   */
00166 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00167
00168 /**
00169   * @brief  Read a value in CRS register
00170   * @param  __INSTANCE__ CRS Instance
00171   * @param  __REG__ Register to be read
00172   * @retval Register value
00173   */
00174 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00180   * @{
00181   */
00182
00183 /**
00184   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00185   * @note   The RELOAD value should be selected according to the ratio between
00186   *         the target frequency and the frequency of the synchronization source after
00187   *         prescaling. It is then decreased by one in order to reach the expected
00188   *         synchronization on the zero value. The formula is the following:
00189   *              RELOAD = (fTARGET / fSYNC) -1
00190   * @param  __FTARGET__ Target frequency (value in Hz)
00191   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00192   * @retval Reload value (in Hz)
00193   */
00194 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /* Exported functions --------------------------------------------------------*/
00205 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00206   * @{
00207   */
00208
00209 /** @defgroup CRS_LL_EF_Configuration Configuration
00210   * @{
00211   */
00212
00213 /**
00214   * @brief  Enable Frequency error counter
00215   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00216   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00217   * @retval None
00218   */
00219 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00220 {
00221   SET_BIT(CRS->CR, CRS_CR_CEN);
00222 }
00223
00224 /**
00225   * @brief  Disable Frequency error counter
00226   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00227   * @retval None
00228   */
00229 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00230 {
00231   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00232 }
00233
00234 /**
00235   * @brief  Check if Frequency error counter is enabled or not
00236   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00237   * @retval State of bit (1 or 0).
00238   */
00239 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00240 {
00241   return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
00242 }
00243
00244 /**
00245   * @brief  Enable Automatic trimming counter
00246   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00247   * @retval None
00248   */
00249 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00250 {
00251   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00252 }
00253
00254 /**
00255   * @brief  Disable Automatic trimming counter
00256   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00257   * @retval None
00258   */
00259 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00260 {
00261   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00262 }
00263
00264 /**
00265   * @brief  Check if Automatic trimming is enabled or not
00266   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00267   * @retval State of bit (1 or 0).
00268   */
00269 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00270 {
00271   return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
00272 }
00273
00274 /**
00275   * @brief  Set HSI48 oscillator smooth trimming
00276   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00277   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00278   * @param  Value a number between Min_Data = 0 and Max_Data = 63
00279   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00283 {
00284   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
00285 }
00286
00287 /**
00288   * @brief  Get HSI48 oscillator smooth trimming
00289   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00290   * @retval a number between Min_Data = 0 and Max_Data = 63
00291   */
00292 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00293 {
00294   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
00295 }
00296
00297 /**
00298   * @brief  Set counter reload value
00299   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00300   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00301   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
00302   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00303   * @retval None
00304   */
00305 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00306 {
00307   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00308 }
00309
00310 /**
00311   * @brief  Get counter reload value
00312   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00313   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00314   */
00315 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00316 {
00317   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00318 }
00319
00320 /**
00321   * @brief  Set frequency error limit
00322   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00323   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00324   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
00325   * @retval None
00326   */
00327 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00328 {
00329   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
00330 }
00331
00332 /**
00333   * @brief  Get frequency error limit
00334   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00335   * @retval A number between Min_Data = 0 and Max_Data = 255
00336   */
00337 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00338 {
00339   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
00340 }
00341
00342 /**
00343   * @brief  Set division factor for SYNC signal
00344   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00345   * @param  Divider This parameter can be one of the following values:
00346   *         @arg @ref LL_CRS_SYNC_DIV_1
00347   *         @arg @ref LL_CRS_SYNC_DIV_2
00348   *         @arg @ref LL_CRS_SYNC_DIV_4
00349   *         @arg @ref LL_CRS_SYNC_DIV_8
00350   *         @arg @ref LL_CRS_SYNC_DIV_16
00351   *         @arg @ref LL_CRS_SYNC_DIV_32
00352   *         @arg @ref LL_CRS_SYNC_DIV_64
00353   *         @arg @ref LL_CRS_SYNC_DIV_128
00354   * @retval None
00355   */
00356 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00357 {
00358   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00359 }
00360
00361 /**
00362   * @brief  Get division factor for SYNC signal
00363   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00364   * @retval Returned value can be one of the following values:
00365   *         @arg @ref LL_CRS_SYNC_DIV_1
00366   *         @arg @ref LL_CRS_SYNC_DIV_2
00367   *         @arg @ref LL_CRS_SYNC_DIV_4
00368   *         @arg @ref LL_CRS_SYNC_DIV_8
00369   *         @arg @ref LL_CRS_SYNC_DIV_16
00370   *         @arg @ref LL_CRS_SYNC_DIV_32
00371   *         @arg @ref LL_CRS_SYNC_DIV_64
00372   *         @arg @ref LL_CRS_SYNC_DIV_128
00373   */
00374 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00375 {
00376   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00377 }
00378
00379 /**
00380   * @brief  Set SYNC signal source
00381   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00382   * @param  Source This parameter can be one of the following values:
00383   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00384   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00385   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00386   * @retval None
00387   */
00388 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00389 {
00390   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00391 }
00392
00393 /**
00394   * @brief  Get SYNC signal source
00395   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00396   * @retval Returned value can be one of the following values:
00397   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00398   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00399   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00400   */
00401 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00402 {
00403   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00404 }
00405
00406 /**
00407   * @brief  Set input polarity for the SYNC signal source
00408   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00409   * @param  Polarity This parameter can be one of the following values:
00410   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00411   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00415 {
00416   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00417 }
00418
00419 /**
00420   * @brief  Get input polarity for the SYNC signal source
00421   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00422   * @retval Returned value can be one of the following values:
00423   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00424   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00425   */
00426 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00427 {
00428   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00429 }
00430
00431 /**
00432   * @brief  Configure CRS for the synchronization
00433   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00434   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00435   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00436   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00437   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00438   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00439   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
00440   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00441   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00442   * @param  Settings This parameter can be a combination of the following values:
00443   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00444   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00445   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00446   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
00450                                                   uint32_t ReloadValue, uint32_t Settings)
00451 {
00452   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00453   MODIFY_REG(CRS->CFGR,
00454              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
00455              ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
00456 }
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00463   * @{
00464   */
00465
00466 /**
00467   * @brief  Generate software SYNC event
00468   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00472 {
00473   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00474 }
00475
00476 /**
00477   * @brief  Get the frequency error direction latched in the time of the last
00478   * SYNC event
00479   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00480   * @retval Returned value can be one of the following values:
00481   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00482   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00483   */
00484 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00485 {
00486   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00487 }
00488
00489 /**
00490   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00491   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00492   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00493   */
00494 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00495 {
00496   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
00497 }
00498
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00504   * @{
00505   */
00506
00507 /**
00508   * @brief  Check if SYNC event OK signal occurred or not
00509   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00510   * @retval State of bit (1 or 0).
00511   */
00512 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00513 {
00514   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
00515 }
00516
00517 /**
00518   * @brief  Check if SYNC warning signal occurred or not
00519   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00520   * @retval State of bit (1 or 0).
00521   */
00522 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00523 {
00524   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
00525 }
00526
00527 /**
00528   * @brief  Check if Synchronization or trimming error signal occurred or not
00529   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00530   * @retval State of bit (1 or 0).
00531   */
00532 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00533 {
00534   return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
00535 }
00536
00537 /**
00538   * @brief  Check if Expected SYNC signal occurred or not
00539   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00540   * @retval State of bit (1 or 0).
00541   */
00542 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00543 {
00544   return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
00545 }
00546
00547 /**
00548   * @brief  Check if SYNC error signal occurred or not
00549   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00550   * @retval State of bit (1 or 0).
00551   */
00552 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00553 {
00554   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
00555 }
00556
00557 /**
00558   * @brief  Check if SYNC missed error signal occurred or not
00559   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00560   * @retval State of bit (1 or 0).
00561   */
00562 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00563 {
00564   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
00565 }
00566
00567 /**
00568   * @brief  Check if Trimming overflow or underflow occurred or not
00569   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00570   * @retval State of bit (1 or 0).
00571   */
00572 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00573 {
00574   return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
00575 }
00576
00577 /**
00578   * @brief  Clear the SYNC event OK flag
00579   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00583 {
00584   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00585 }
00586
00587 /**
00588   * @brief  Clear the  SYNC warning flag
00589   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00590   * @retval None
00591   */
00592 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00593 {
00594   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00595 }
00596
00597 /**
00598   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
00599   * the ERR flag
00600   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00601   * @retval None
00602   */
00603 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00604 {
00605   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00606 }
00607
00608 /**
00609   * @brief  Clear Expected SYNC flag
00610   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00611   * @retval None
00612   */
00613 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00614 {
00615   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00616 }
00617
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00623   * @{
00624   */
00625
00626 /**
00627   * @brief  Enable SYNC event OK interrupt
00628   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00629   * @retval None
00630   */
00631 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00632 {
00633   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00634 }
00635
00636 /**
00637   * @brief  Disable SYNC event OK interrupt
00638   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00639   * @retval None
00640   */
00641 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00642 {
00643   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00644 }
00645
00646 /**
00647   * @brief  Check if SYNC event OK interrupt is enabled or not
00648   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00649   * @retval State of bit (1 or 0).
00650   */
00651 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00652 {
00653   return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
00654 }
00655
00656 /**
00657   * @brief  Enable SYNC warning interrupt
00658   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00659   * @retval None
00660   */
00661 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00662 {
00663   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00664 }
00665
00666 /**
00667   * @brief  Disable SYNC warning interrupt
00668   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00669   * @retval None
00670   */
00671 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00672 {
00673   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00674 }
00675
00676 /**
00677   * @brief  Check if SYNC warning interrupt is enabled or not
00678   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00679   * @retval State of bit (1 or 0).
00680   */
00681 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00682 {
00683   return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
00684 }
00685
00686 /**
00687   * @brief  Enable Synchronization or trimming error interrupt
00688   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00689   * @retval None
00690   */
00691 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00692 {
00693   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00694 }
00695
00696 /**
00697   * @brief  Disable Synchronization or trimming error interrupt
00698   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00699   * @retval None
00700   */
00701 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00702 {
00703   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00704 }
00705
00706 /**
00707   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00708   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00709   * @retval State of bit (1 or 0).
00710   */
00711 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00712 {
00713   return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
00714 }
00715
00716 /**
00717   * @brief  Enable Expected SYNC interrupt
00718   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00719   * @retval None
00720   */
00721 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00722 {
00723   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00724 }
00725
00726 /**
00727   * @brief  Disable Expected SYNC interrupt
00728   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00729   * @retval None
00730   */
00731 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00732 {
00733   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00734 }
00735
00736 /**
00737   * @brief  Check if Expected SYNC interrupt is enabled or not
00738   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00739   * @retval State of bit (1 or 0).
00740   */
00741 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00742 {
00743   return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
00744 }
00745
00746 /**
00747   * @}
00748   */
00749
00750 #if defined(USE_FULL_LL_DRIVER)
00751 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00752   * @{
00753   */
00754
00755 ErrorStatus LL_CRS_DeInit(void);
00756
00757 /**
00758   * @}
00759   */
00760 #endif /* USE_FULL_LL_DRIVER */
00761
00762 /**
00763   * @}
00764   */
00765
00766 /**
00767   * @}
00768   */
00769
00770 #endif /* defined(CRS) */
00771
00772 /**
00773   * @}
00774   */
00775
00776 #ifdef __cplusplus
00777 }
00778 #endif
00779
00780 #endif /* __STM32G4xx_LL_CRS_H */
00781
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dac.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_dac.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_dac.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00035
00036 /** @addtogroup DAC_LL DAC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /** @addtogroup DAC_LL_Private_Macros
00046   * @{
00047   */
00048 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
00049 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                       \
00050   (((__DACX__) == DAC2) ?                                                  \
00051    ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                 \
00052    :                                                                       \
00053    (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                \
00054     ||  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2))                           \
00055   )
00056 #else
00057 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                       \
00058   (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                 \
00059    ||  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                             \
00060   )
00061 #endif /* #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
00062
00063 #if defined(STM32G474xx) || defined(STM32G484xx)
00064 #define IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__)                       \
00065   (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
00066    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
00067    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
00068    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
00069    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
00070    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                           \
00071    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
00072    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
00073    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG1)                       \
00074    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG2)                       \
00075    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG3)                       \
00076    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG4)                       \
00077    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG5)                       \
00078    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG6)                       \
00079    || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
00080        : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
00081    || (((__DACX__) == DAC1) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO1))\
00082    || (((__DACX__) == DAC2) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO2))\
00083    || (((__DACX__) == DAC3) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO3))\
00084    || (((__DACX__) == DAC4) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO1))\
00085   )
00086 #else
00087 #define IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__)                       \
00088   (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
00089    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
00090    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
00091    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
00092    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
00093    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                           \
00094    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
00095    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
00096    || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
00097        : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
00098   )
00099 #endif /* STM32G474xx || STM32G484xx */
00100
00101 #if defined(STM32G474xx) || defined(STM32G484xx)
00102 #define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__)                      \
00103   (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
00104    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
00105    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
00106    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
00107    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
00108    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE10)                          \
00109    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
00110    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
00111    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1)                      \
00112    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2)                      \
00113    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3)                      \
00114    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4)                      \
00115    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5)                      \
00116    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6)                      \
00117    || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
00118        : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
00119   )
00120 #else
00121 #define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__)                      \
00122   (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                                    \
00123    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                            \
00124    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                           \
00125    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                            \
00126    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                            \
00127    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE10)                          \
00128    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                            \
00129    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                            \
00130    || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)    \
00131        : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO))                       \
00132   )
00133 #endif /* STM32G474xx || STM32G484xx */
00134
00135 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
00136   (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
00137    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00138    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00139    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH) \
00140   )
00141
00142 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)      \
00143   ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                                   \
00144      && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                                 \
00145          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                           \
00146          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                           \
00147          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                           \
00148          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                           \
00149          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                           \
00150          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                           \
00151          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                           \
00152          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                           \
00153          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                           \
00154          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                          \
00155          || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                         \
00156     )                                                                                                         \
00157     ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                              \
00158        && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                                 \
00159            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                              \
00160            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                              \
00161            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                             \
00162            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                             \
00163            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                             \
00164            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                            \
00165            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                            \
00166            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                            \
00167            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                           \
00168            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                           \
00169            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                          \
00170       )                                                                                                       \
00171     ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH)                              \
00172        && (((__WAVE_AUTO_GENERATION_CONFIG__) & ~(DAC_STR1_STINCDATA1|DAC_STR1_STDIR1|DAC_STR1_STRSTDATA1))   \
00173            == 0UL)                                                                                            \
00174       )                                                                                                       \
00175   )
00176
00177 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00178   (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                        \
00179    || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
00180   )
00181
00182 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
00183   (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                     \
00184    || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
00185   )
00186
00187 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
00188   (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                            \
00189    || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
00190   )
00191
00192 /**
00193   * @}
00194   */
00195
00196
00197 /* Private function prototypes -----------------------------------------------*/
00198
00199 /* Exported functions --------------------------------------------------------*/
00200 /** @addtogroup DAC_LL_Exported_Functions
00201   * @{
00202   */
00203
00204 /** @addtogroup DAC_LL_EF_Init
00205   * @{
00206   */
00207
00208 /**
00209   * @brief  De-initialize registers of the selected DAC instance
00210   *         to their default reset values.
00211   * @param  DACx DAC instance
00212   * @retval An ErrorStatus enumeration value:
00213   *          - SUCCESS: DAC registers are de-initialized
00214   *          - ERROR: not applicable
00215   */
00216 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx)
00217 {
00218   /* Check the parameters */
00219   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00220
00221 #ifdef DAC1
00222   if (DACx == DAC1)
00223   {
00224     /* Force reset of DAC clock */
00225     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_DAC1);
00226
00227     /* Release reset of DAC clock */
00228     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC1);
00229   }
00230 #endif /* DAC1 */
00231 #ifdef DAC2
00232   if (DACx == DAC2)
00233   {
00234     /* Force reset of DAC clock */
00235     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_DAC2);
00236
00237     /* Release reset of DAC clock */
00238     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC2);
00239   }
00240 #endif /* DAC2 */
00241 #ifdef DAC3
00242   if (DACx == DAC3)
00243   {
00244     /* Force reset of DAC clock */
00245     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_DAC3);
00246
00247     /* Release reset of DAC clock */
00248     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC3);
00249   }
00250 #endif /* DAC3 */
00251 #ifdef DAC4
00252   if (DACx == DAC4)
00253   {
00254     /* Force reset of DAC clock */
00255     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_DAC4);
00256
00257     /* Release reset of DAC clock */
00258     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC4);
00259   }
00260 #endif /* DAC4 */
00261
00262   return SUCCESS;
00263 }
00264
00265 /**
00266   * @brief  Initialize some features of DAC channel.
00267   * @note   @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
00268   *         Leaving it ready to be enabled and output:
00269   *         a level by calling one of
00270   *           @ref LL_DAC_ConvertData12RightAligned
00271   *           @ref LL_DAC_ConvertData12LeftAligned
00272   *           @ref LL_DAC_ConvertData8RightAligned
00273   *         or one of the supported autogenerated wave.
00274   * @note   This function allows configuration of:
00275   *          - Output mode
00276   *          - Trigger
00277   *          - Wave generation
00278   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00279   *         is conditioned to DAC state:
00280   *         DAC channel must be disabled.
00281   * @param  DACx DAC instance
00282   * @param  DAC_Channel This parameter can be one of the following values:
00283   *         @arg @ref LL_DAC_CHANNEL_1
00284   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00285   *
00286   *         (1) On this STM32 series, parameter not available on all instances.
00287   *             Refer to device datasheet for channels availability.
00288   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00289   * @retval An ErrorStatus enumeration value:
00290   *          - SUCCESS: DAC registers are initialized
00291   *          - ERROR: DAC registers are not initialized
00292   */
00293 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
00294 {
00295   ErrorStatus status = SUCCESS;
00296
00297   /* Check the parameters */
00298   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00299   assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
00300   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DACx, DAC_InitStruct->TriggerSource));
00301   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00302   assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
00303   assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
00304   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00305   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00306   {
00307     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
00308                                                   DAC_InitStruct->WaveAutoGenerationConfig));
00309   }
00310
00311   /* Note: Hardware constraint (refer to description of this function)        */
00312   /*       DAC instance must be disabled.                                     */
00313   if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
00314   {
00315     /* Configuration of DAC channel:                                          */
00316     /*  - TriggerSource                                                       */
00317     /*  - WaveAutoGeneration                                                  */
00318     /*  - OutputBuffer                                                        */
00319     /*  - OutputConnection                                                    */
00320     /*  - OutputMode                                                          */
00321     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00322     {
00323       if (DAC_InitStruct->WaveAutoGeneration == LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH)
00324       {
00325         assert_param(IS_LL_DAC_TRIGGER_SOURCE2(DACx, DAC_InitStruct->TriggerSource2));
00326
00327         MODIFY_REG(DACx->CR,
00328                    DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00329                    DAC_InitStruct->WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00330                   );
00331
00332         MODIFY_REG(DACx->STMODR,
00333                    (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00334                    (
00335                      ((DAC_InitStruct->TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos)
00336                      | ((DAC_InitStruct->TriggerSource2 >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos)
00337                    ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00338                   );
00339
00340         WRITE_REG(*(__DAC_PTR_REG_OFFSET(DACx->STR1,
00341                                          (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
00342                                          DAC_REG_STRX_REGOFFSET_MASK_POSBIT0)),
00343                   DAC_InitStruct->WaveAutoGenerationConfig);
00344       }
00345       else
00346       {
00347         MODIFY_REG(DACx->CR,
00348                    (DAC_CR_TSEL1
00349                     | DAC_CR_WAVE1
00350                     | DAC_CR_MAMP1
00351                    ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00352                    ,
00353                    (DAC_InitStruct->TriggerSource
00354                     | DAC_InitStruct->WaveAutoGeneration
00355                     | DAC_InitStruct->WaveAutoGenerationConfig
00356                    ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00357                   );
00358       }
00359     }
00360     else
00361     {
00362       MODIFY_REG(DACx->CR,
00363                  (DAC_CR_TSEL1
00364                   | DAC_CR_WAVE1
00365                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00366                  ,
00367                  (DAC_InitStruct->TriggerSource
00368                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00369                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00370                 );
00371     }
00372     MODIFY_REG(DACx->MCR,
00373                (DAC_MCR_MODE1_1
00374                 | DAC_MCR_MODE1_0
00375                 | DAC_MCR_MODE1_2
00376                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00377                ,
00378                (DAC_InitStruct->OutputBuffer
00379                 | DAC_InitStruct->OutputConnection
00380                 | DAC_InitStruct->OutputMode
00381                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00382               );
00383   }
00384   else
00385   {
00386     /* Initialization error: DAC instance is not disabled.                    */
00387     status = ERROR;
00388   }
00389   return status;
00390 }
00391
00392 /**
00393   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00394   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00395   *                       whose fields will be set to default values.
00396   * @retval None
00397   */
00398 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00399 {
00400   /* Set DAC_InitStruct fields to default values */
00401   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00402   DAC_InitStruct->TriggerSource2           = LL_DAC_TRIG_SOFTWARE;
00403   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00404   /* Note: Parameter discarded if wave auto generation is disabled,           */
00405   /*       set anyway to its default value.                                   */
00406   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00407   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00408   DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
00409   DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
00425
00426 /**
00427   * @}
00428   */
00429
00430 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dac.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_dac.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_DAC_H
00021 #define STM32G4xx_LL_DAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
00035
00036 /** @defgroup DAC_LL DAC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00045   * @{
00046   */
00047
00048 /* Internal masks for DAC channels definition */
00049 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00050 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR    */
00051 /* - channel bits position into register SWTRIG                               */
00052 /* - channel bits position into register SWTRIGB                              */
00053 /* - channel register offset of data holding register DHRx                    */
00054 /* - channel register offset of data output register DORx                     */
00055 /* - channel register offset of sample-and-hold sample time register SHSRx    */
00056 /* - channel register offset of sawtooth register STRx                        */
00057 #define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers
00058                                                 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
00059 #define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers
00060                                                 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
00061 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00062
00063 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
00064 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
00065 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00066
00067 #define DAC_SWTRB_CH1                  (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
00068 #define DAC_SWTRB_CH2                  (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
00069 #define DAC_SWTRB_CHX_MASK             (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
00070
00071 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
00072 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
00073                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
00074 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
00075                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
00076
00077 #define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
00078                                                                   DHR12Rx channel 1 (shifted left of 28 bits)   */
00079 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
00080                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
00081 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
00082                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
00083
00084 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
00085 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
00086 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
00087 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK\
00088                                         | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00089
00090 #define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
00091
00092 #define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus
00093                                                                   DORx channel 2 (shifted left of 5 bits)    */
00094 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00095
00096 #define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
00097 #define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus
00098                                                                   SHSRx channel 2 (shifted left of 6 bits)    */
00099 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
00100
00101 #define DAC_REG_STR1_REGOFFSET         0x00000000UL            /* Register STRx channel 1 taken as reference  */
00102 #define DAC_REG_STR2_REGOFFSET         0x00000080UL            /* Register offset of STRx channel 1 versus
00103                                                                   STRx channel 2 (shifted left of 7 bits)     */
00104 #define DAC_REG_STRX_REGOFFSET_MASK   (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
00105
00106 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
00107                                                                    DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
00108 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted
00109                                                                    to position 0                                    */
00110 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted
00111                                                                    to position 0                                    */
00112 #define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of STRx registers offset when shifted
00113                                                                    to position 0                                    */
00114
00115 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx
00116                                                                    channel 1 or 2 versus DHR12Rx channel 1
00117                                                                    (shifted left of 28 bits)                   */
00118 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx
00119                                                                    channel 1 or 2 versus DHR12Rx channel 1
00120                                                                    (shifted left of 20 bits)                   */
00121 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx
00122                                                                    channel 1 or 2 versus DHR12Rx channel 1
00123                                                                    (shifted left of 24 bits)                   */
00124 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx
00125                                                                    channel 1 or 2 versus DORx channel 1
00126                                                                    (shifted left of 5 bits)                    */
00127 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx
00128                                                                    channel 1 or 2 versus SHSRx channel 1
00129                                                                    (shifted left of 6 bits)                    */
00130 #define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS               7UL  /* Position of bits register offset of STRx
00131                                                                    channel 1 or 2 versus STRx channel 1
00132                                                                    (shifted left of 7 bits)                    */
00133
00134 /* DAC registers bits positions */
00135 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
00136 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
00137 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
00138
00139 /* Miscellaneous data */
00140 #define DAC_DIGITAL_SCALE_12BITS                  4095UL   /* Full-scale digital value with a resolution of 12
00141                                                               bits (voltage range determined by analog voltage
00142                                                               references Vref+ and Vref-, refer to reference manual) */
00143
00144 /**
00145   * @}
00146   */
00147
00148
00149 /* Private macros ------------------------------------------------------------*/
00150 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00151   * @{
00152   */
00153
00154 /**
00155   * @brief  Driver macro reserved for internal use: set a pointer to
00156   *         a register from a register basis from which an offset
00157   *         is applied.
00158   * @param  __REG__ Register basis from which the offset is applied.
00159   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00160   * @retval Pointer to register address
00161   */
00162 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00163   ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00164
00165 /**
00166   * @}
00167   */
00168
00169
00170 /* Exported types ------------------------------------------------------------*/
00171 #if defined(USE_FULL_LL_DRIVER)
00172 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00173   * @{
00174   */
00175
00176 /**
00177   * @brief  Structure definition of some features of DAC instance.
00178   */
00179 typedef struct
00180 {
00181   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel:
00182                                              internal (SW start) or from external peripheral
00183                                              (timer event, external interrupt line).
00184                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00185
00186                                              This feature can be modified afterwards using unitary
00187                                              function @ref LL_DAC_SetTriggerSource().
00188                                              @note If waveform automatic generation mode is set to sawtooth,
00189                                              this parameter is used as sawtooth RESET trigger */
00190
00191   uint32_t TriggerSource2;              /*!< Set the conversion secondary trigger source for the selected DAC channel:
00192                                              internal (SW start) or from external peripheral
00193                                              (timer event, external interrupt line).
00194                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00195
00196                                              This feature can be modified afterwards using unitary
00197                                              function @ref LL_DAC_SetTriggerSource2().
00198                                              @note If waveform automatic generation mode is set to sawtooth,
00199                                              this parameter is used as sawtooth step trigger */
00200
00201   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00202                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00203
00204                                              This feature can be modified afterwards using unitary
00205                                              function @ref LL_DAC_SetWaveAutoGeneration(). */
00206
00207   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00208                                              If waveform automatic generation mode is set to noise, this parameter
00209                                              can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00210                                              If waveform automatic generation mode is set to triangle,
00211                                              this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00212                                              If waveform automatic generation mode is set to sawtooth, this parameter
00213                                              host the sawtooth configuration: polarity, reset data, increment data.
00214                                              Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
00215                                              @note If waveform automatic generation mode is disabled,
00216                                               this parameter is discarded.
00217
00218                                              This feature can be modified afterwards using unitary
00219                                              function @ref LL_DAC_SetWaveNoiseLFSR(),
00220                                              @ref LL_DAC_SetWaveTriangleAmplitude(),
00221                                              @ref LL_DAC_SetWaveSawtoothPolarity(),
00222                                              @ref LL_DAC_SetWaveSawtoothResetData()
00223                                              or @ref LL_DAC_SetWaveSawtoothStepData(),
00224                                              depending on the wave automatic generation selected. */
00225
00226   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00227                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00228
00229                                              This feature can be modified afterwards using unitary
00230                                              function @ref LL_DAC_SetOutputBuffer(). */
00231
00232   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
00233                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
00234
00235                                              This feature can be modified afterwards using unitary
00236                                              function @ref LL_DAC_SetOutputConnection(). */
00237
00238   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC
00239                                              channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
00240
00241                                              This feature can be modified afterwards using unitary
00242                                              function @ref LL_DAC_SetOutputMode(). */
00243 } LL_DAC_InitTypeDef;
00244
00245 /**
00246   * @}
00247   */
00248 #endif /* USE_FULL_LL_DRIVER */
00249
00250 /* Exported constants --------------------------------------------------------*/
00251 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00252   * @{
00253   */
00254
00255 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00256   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00257   * @{
00258   */
00259 /* DAC channel 1 flags */
00260 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00261 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
00262 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
00263 #define LL_DAC_FLAG_DAC1RDY                (DAC_SR_DAC1RDY)   /*!< DAC channel 1 flag ready */
00264 #define LL_DAC_FLAG_DORSTAT1               (DAC_SR_DORSTAT1)  /*!< DAC channel 1 flag output register */
00265
00266 /* DAC channel 2 flags */
00267 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00268 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
00269 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
00270 #define LL_DAC_FLAG_DAC2RDY                (DAC_SR_DAC2RDY)   /*!< DAC channel 2 flag ready */
00271 #define LL_DAC_FLAG_DORSTAT2               (DAC_SR_DORSTAT2)  /*!< DAC channel 2 flag output register */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup DAC_LL_EC_IT DAC interruptions
00278   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00279   * @{
00280   */
00281 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00282
00283 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00290   * @{
00291   */
00292 #define LL_DAC_CHANNEL_1                   (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
00293 #define LL_DAC_CHANNEL_2                   (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
00299   * @brief    High frequency interface mode defines that can be used
00300   *           with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
00301   * @{
00302   */
00303 #define LL_DAC_HIGH_FREQ_MODE_DISABLE         0x00000000UL       /*!< High frequency interface mode disabled */
00304 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ     (DAC_MCR_HFSEL_0)  /*!< High frequency interface mode compatible to AHB>80MHz enabled */
00305 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ    (DAC_MCR_HFSEL_1)  /*!< High frequency interface mode compatible to AHB>160MHz enabled */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
00311   * @{
00312   */
00313 #define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */
00314 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00320   * @{
00321   */
00322 #define LL_DAC_TRIG_SOFTWARE                  0x00000000UL                                                        /*!< DAC (all) channel conversion trigger internal (SW start) */
00323 #define LL_DAC_TRIG_EXT_TIM1_TRGO             (                                                   DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
00324 #define LL_DAC_TRIG_EXT_TIM8_TRGO             (                                                   DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
00325 #define LL_DAC_TRIG_EXT_TIM7_TRGO             (                                  DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
00326 #define LL_DAC_TRIG_EXT_TIM15_TRGO            (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
00327 #define LL_DAC_TRIG_EXT_TIM2_TRGO             (                 DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
00328 #define LL_DAC_TRIG_EXT_TIM4_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
00329 #define LL_DAC_TRIG_EXT_EXTI_LINE9            (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
00330 #define LL_DAC_TRIG_EXT_EXTI_LINE10           (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
00331 #define LL_DAC_TRIG_EXT_TIM6_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
00332 #define LL_DAC_TRIG_EXT_TIM3_TRGO             (DAC_CR_TSEL1_3                                                   ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
00333 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1       (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00334 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00335 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2       (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00336 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00337 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3       (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00338 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00339 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00340 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00341 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00342 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00343 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00344 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00345 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00346 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
00347 #define LL_DAC_TRIG_EXT_HRTIM_TRGO3           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00353   * @{
00354   */
00355 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
00356 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00357 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00358 #define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00364   * @{
00365   */
00366 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00367 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00368 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00369 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00370 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00371 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00372 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00373 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00374 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00375 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00376 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00377 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00383   * @{
00384   */
00385 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00386 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00387 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00388 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00389 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00390 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00391 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00392 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00393 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00394 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00395 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00396 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
00402   * @{
00403   */
00404 #define LL_DAC_SAWTOOTH_POLARITY_DECREMENT          0x00000000UL            /*!< Sawtooth wave generation, polarity is decrement */
00405 #define LL_DAC_SAWTOOTH_POLARITY_INCREMENT          (DAC_STR1_STDIR1)       /*!< Sawtooth wave generation, polarity is increment */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
00411   * @{
00412   */
00413 #define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */
00414 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00420   * @{
00421   */
00422 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00423 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
00429   * @{
00430   */
00431 #define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */
00432 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
00438   * @{
00439   */
00440 #define LL_DAC_SIGNED_FORMAT_DISABLE       0x00000000UL            /*!< The selected DAC channel data format is not signed */
00441 #define LL_DAC_SIGNED_FORMAT_ENABLE        (DAC_MCR_SINFORMAT1)    /*!< The selected DAC channel data format is signed */
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00447   * @{
00448   */
00449 #define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
00450 #define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00456   * @{
00457   */
00458 /* List of DAC registers intended to be used (most commonly) with             */
00459 /* DMA transfer.                                                              */
00460 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00461 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
00462 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
00463 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00469   * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
00470   *         not timeout values.
00471   *         For details on delays values, refer to descriptions in source code
00472   *         above each literal definition.
00473   * @{
00474   */
00475
00476 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00477 /* (transition from disable to enable).                                       */
00478 /* Note: DAC channel startup time depends on board application environment:   */
00479 /*       impedance connected to DAC channel output.                           */
00480 /*       The delay below is specified under conditions:                       */
00481 /*        - voltage maximum transition (lowest to highest value)              */
00482 /*        - until voltage reaches final value +-1LSB                          */
00483 /*        - DAC channel output buffer enabled                                 */
00484 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00485 /* Literal set to maximum value (refer to device datasheet,                   */
00486 /* parameter "tWAKEUP").                                                      */
00487 /* Unit: us                                                                   */
00488 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00489
00490 /* Delay for DAC channel voltage settling time.                               */
00491 /* Note: DAC channel startup time depends on board application environment:   */
00492 /*       impedance connected to DAC channel output.                           */
00493 /*       The delay below is specified under conditions:                       */
00494 /*        - voltage maximum transition (lowest to highest value)              */
00495 /*        - until voltage reaches final value +-1LSB                          */
00496 /*        - DAC channel output buffer enabled                                 */
00497 /*        - load impedance of 5kOhm min, 50pF max                             */
00498 /* Literal set to maximum value (refer to device datasheet,                   */
00499 /* parameter "tSETTLING").                                                    */
00500 /* Unit: us                                                                   */
00501 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */
00502
00503 /**
00504   * @}
00505   */
00506
00507 /**
00508   * @}
00509   */
00510
00511 /* Exported macro ------------------------------------------------------------*/
00512 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00513   * @{
00514   */
00515
00516 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00517   * @{
00518   */
00519
00520 /**
00521   * @brief  Write a value in DAC register
00522   * @param  __INSTANCE__ DAC Instance
00523   * @param  __REG__ Register to be written
00524   * @param  __VALUE__ Value to be written in the register
00525   * @retval None
00526   */
00527 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00528
00529 /**
00530   * @brief  Read a value in DAC register
00531   * @param  __INSTANCE__ DAC Instance
00532   * @param  __REG__ Register to be read
00533   * @retval Register value
00534   */
00535 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00536
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00542   * @{
00543   */
00544
00545 /**
00546   * @brief  Helper macro to get DAC channel number in decimal format
00547   *         from literals LL_DAC_CHANNEL_x.
00548   *         Example:
00549   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00550   *            will return decimal number "1".
00551   * @note   The input can be a value from functions where a channel
00552   *         number is returned.
00553   * @param  __CHANNEL__ This parameter can be one of the following values:
00554   *         @arg @ref LL_DAC_CHANNEL_1
00555   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00556   *
00557   *         (1) On this STM32 series, parameter not available on all instances.
00558   *             Refer to device datasheet for channels availability.
00559   * @retval 1...2
00560   */
00561 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00562   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00563
00564 /**
00565   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00566   *         from number in decimal format.
00567   *         Example:
00568   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00569   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00570   * @note  If the input parameter does not correspond to a DAC channel,
00571   *        this macro returns value '0'.
00572   * @param  __DECIMAL_NB__ 1...2
00573   * @retval Returned value can be one of the following values:
00574   *         @arg @ref LL_DAC_CHANNEL_1
00575   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00576   *
00577   *         (1) On this STM32 series, parameter not available on all instances.
00578   *             Refer to device datasheet for channels availability.
00579   */
00580 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
00581   (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1  ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
00582
00583 /**
00584   * @brief  Helper macro to define the DAC conversion data full-scale digital
00585   *         value corresponding to the selected DAC resolution.
00586   * @note   DAC conversion data full-scale corresponds to voltage range
00587   *         determined by analog voltage references Vref+ and Vref-
00588   *         (refer to reference manual).
00589   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00590   *         @arg @ref LL_DAC_RESOLUTION_12B
00591   *         @arg @ref LL_DAC_RESOLUTION_8B
00592   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00593   */
00594 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00595   ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
00596
00597 /**
00598   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00599   *         value) corresponding to a voltage (unit: mVolt).
00600   * @note   This helper macro is intended to provide input data in voltage
00601   *         rather than digital value,
00602   *         to be used with LL DAC functions such as
00603   *         @ref LL_DAC_ConvertData12RightAligned().
00604   * @note   Analog reference voltage (Vref+) must be either known from
00605   *         user board environment or can be calculated using ADC measurement
00606   *         and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00607   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00608   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00609   *                         (unit: mVolt).
00610   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00611   *         @arg @ref LL_DAC_RESOLUTION_12B
00612   *         @arg @ref LL_DAC_RESOLUTION_8B
00613   * @retval DAC conversion data (unit: digital value)
00614   */
00615 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)     \
00616   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                                      \
00617    / (__VREFANALOG_VOLTAGE__)                                                                          \
00618   )
00619
00620 /**
00621   * @brief  Helper macro to format sawtooth wave generation configuration
00622   *         value to be filled into WaveAutoGenerationConfig  parameter of @ref LL_DAC_InitTypeDef.
00623   * @note   This helper will format information to fit in DAC_STRx register.
00624   * @param  __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
00625   * @param  __RESET_DATA__ sawtooth reset data.
00626   * @param  __STEP_DATA__ sawtooth step data
00627   * @retval Sawtooth configuration organized in DAC_STRx compatible format.
00628   */
00629 #define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__)               \
00630   ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk)                          \
00631     | ((__POLARITY__) & DAC_STR1_STDIR1_Msk)                                                          \
00632     | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk)                       \
00633   )
00634
00635 /**
00636   * @}
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643
00644 /* Exported functions --------------------------------------------------------*/
00645 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00646   * @{
00647   */
00648 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
00649   * @{
00650   */
00651 /**
00652   * @brief  Set the high frequency interface mode for the selected DAC instance
00653   * @rmtoll MCR      HFSEL          LL_DAC_SetHighFrequencyMode
00654   * @param  DACx DAC instance
00655   * @param  HighFreqMode This parameter can be one of the following values:
00656   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
00657   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
00658   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
00659   * @retval None
00660   */
00661 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
00662 {
00663   MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
00664 }
00665
00666 /**
00667   * @brief  Get the high frequency interface mode for the selected DAC instance
00668   * @rmtoll MCR      HFSEL          LL_DAC_GetHighFrequencyMode
00669   * @param  DACx DAC instance
00670   * @retval Returned value can be one of the following values:
00671   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
00672   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
00673   *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
00674   */
00675 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
00676 {
00677   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
00678 }
00679 /**
00680   * @}
00681   */
00682
00683
00684 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00685   * @{
00686   */
00687
00688 /**
00689   * @brief  Set the operating mode for the selected DAC channel:
00690   *         calibration or normal operating mode.
00691   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
00692   *         CR       CEN2           LL_DAC_SetMode
00693   * @param  DACx DAC instance
00694   * @param  DAC_Channel This parameter can be one of the following values:
00695   *         @arg @ref LL_DAC_CHANNEL_1
00696   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00697   *
00698   *         (1) On this STM32 series, parameter not available on all instances.
00699   *             Refer to device datasheet for channels availability.
00700   * @param  ChannelMode This parameter can be one of the following values:
00701   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00702   *         @arg @ref LL_DAC_MODE_CALIBRATION
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
00706 {
00707   MODIFY_REG(DACx->CR,
00708              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00709              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00710 }
00711
00712 /**
00713   * @brief  Get the operating mode for the selected DAC channel:
00714   *         calibration or normal operating mode.
00715   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
00716   *         CR       CEN2           LL_DAC_GetMode
00717   * @param  DACx DAC instance
00718   * @param  DAC_Channel This parameter can be one of the following values:
00719   *         @arg @ref LL_DAC_CHANNEL_1
00720   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00721   *
00722   *         (1) On this STM32 series, parameter not available on all instances.
00723   *             Refer to device datasheet for channels availability.
00724   * @retval Returned value can be one of the following values:
00725   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00726   *         @arg @ref LL_DAC_MODE_CALIBRATION
00727   */
00728 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
00729 {
00730   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00731                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00732                    );
00733 }
00734
00735 /**
00736   * @brief  Set the offset trimming value for the selected DAC channel.
00737   *         Trimming has an impact when output buffer is enabled
00738   *         and is intended to replace factory calibration default values.
00739   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
00740   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
00741   * @param  DACx DAC instance
00742   * @param  DAC_Channel This parameter can be one of the following values:
00743   *         @arg @ref LL_DAC_CHANNEL_1
00744   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00745   *
00746   *         (1) On this STM32 series, parameter not available on all instances.
00747   *             Refer to device datasheet for channels availability.
00748   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00749   * @retval None
00750   */
00751 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
00752 {
00753   MODIFY_REG(DACx->CCR,
00754              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00755              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00756 }
00757
00758 /**
00759   * @brief  Get the offset trimming value for the selected DAC channel.
00760   *         Trimming has an impact when output buffer is enabled
00761   *         and is intended to replace factory calibration default values.
00762   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
00763   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
00764   * @param  DACx DAC instance
00765   * @param  DAC_Channel This parameter can be one of the following values:
00766   *         @arg @ref LL_DAC_CHANNEL_1
00767   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00768   *
00769   *         (1) On this STM32 series, parameter not available on all instances.
00770   *             Refer to device datasheet for channels availability.
00771   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00772   */
00773 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
00774 {
00775   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00776                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00777                    );
00778 }
00779
00780 /**
00781   * @brief  Set the conversion trigger source for the selected DAC channel.
00782   * @note   For conversion trigger source to be effective, DAC trigger
00783   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00784   * @note   To set conversion trigger source, DAC channel must be disabled.
00785   *         Otherwise, the setting is discarded.
00786   * @note   Availability of parameters of trigger sources from timer
00787   *         depends on timers availability on the selected device.
00788   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00789   *         CR       TSEL2          LL_DAC_SetTriggerSource
00790   * @param  DACx DAC instance
00791   * @param  DAC_Channel This parameter can be one of the following values:
00792   *         @arg @ref LL_DAC_CHANNEL_1
00793   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00794   *
00795   *         (1) On this STM32 series, parameter not available on all instances.
00796   *             Refer to device datasheet for channels availability.
00797   * @param  TriggerSource This parameter can be one of the following values:
00798   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00799   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
00800   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
00801   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00802   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00803   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00804   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00805   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00806   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00807   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00808   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
00809   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
00810   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
00811   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
00812   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
00813   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
00814   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
00815   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
00816   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
00817   *
00818   *         (1) On this STM32 series, parameter only available on DAC3.
00819   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
00820   *         (3) On this STM32 series, parameter only available on DAC1&4.
00821   *         (4) On this STM32 series, parameter only available on DAC2.
00822   *          Refer to device datasheet for DACx instances availability.
00823   *         (5) On this STM32 series, parameter not available on all devices.
00824   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
00825   * @retval None
00826   */
00827 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00828 {
00829   MODIFY_REG(DACx->CR,
00830              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00831              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00832 }
00833
00834 /**
00835   * @brief  Get the conversion trigger source for the selected DAC channel.
00836   * @note   For conversion trigger source to be effective, DAC trigger
00837   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00838   * @note   Availability of parameters of trigger sources from timer
00839   *         depends on timers availability on the selected device.
00840   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00841   *         CR       TSEL2          LL_DAC_GetTriggerSource
00842   * @param  DACx DAC instance
00843   * @param  DAC_Channel This parameter can be one of the following values:
00844   *         @arg @ref LL_DAC_CHANNEL_1
00845   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00846   *
00847   *         (1) On this STM32 series, parameter not available on all instances.
00848   *             Refer to device datasheet for channels availability.
00849   * @retval Returned value can be one of the following values:
00850   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00851   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
00852   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
00853   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00854   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00855   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00856   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00857   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00858   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00859   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00860   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
00861   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
00862   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
00863   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
00864   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
00865   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
00866   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
00867   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
00868   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
00869   *
00870   *         (1) On this STM32 series, parameter only available on DAC3.
00871   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
00872   *         (3) On this STM32 series, parameter only available on DAC1&4.
00873   *         (4) On this STM32 series, parameter only available on DAC2.
00874   *          Refer to device datasheet for DACx instances availability.
00875   *         (5) On this STM32 series, parameter not available on all devices.
00876   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
00877   */
00878 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
00879 {
00880   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00881                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00882                    );
00883 }
00884
00885 /**
00886   * @brief  Set the waveform automatic generation mode
00887   *         for the selected DAC channel.
00888   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00889   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00890   * @param  DACx DAC instance
00891   * @param  DAC_Channel This parameter can be one of the following values:
00892   *         @arg @ref LL_DAC_CHANNEL_1
00893   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00894   *
00895   *         (1) On this STM32 series, parameter not available on all instances.
00896   *             Refer to device datasheet for channels availability.
00897   * @param  WaveAutoGeneration This parameter can be one of the following values:
00898   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00899   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00900   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00901   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
00902   * @retval None
00903   */
00904 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00905 {
00906   MODIFY_REG(DACx->CR,
00907              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00908              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00909 }
00910
00911 /**
00912   * @brief  Get the waveform automatic generation mode
00913   *         for the selected DAC channel.
00914   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00915   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00916   * @param  DACx DAC instance
00917   * @param  DAC_Channel This parameter can be one of the following values:
00918   *         @arg @ref LL_DAC_CHANNEL_1
00919   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00920   *
00921   *         (1) On this STM32 series, parameter not available on all instances.
00922   *             Refer to device datasheet for channels availability.
00923   * @retval Returned value can be one of the following values:
00924   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00925   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00926   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00927   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
00928   */
00929 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
00930 {
00931   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00932                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00933                    );
00934 }
00935
00936 /**
00937   * @brief  Set the noise waveform generation for the selected DAC channel:
00938   *         Noise mode and parameters LFSR (linear feedback shift register).
00939   * @note   For wave generation to be effective, DAC channel
00940   *         wave generation mode must be enabled using
00941   *         function @ref LL_DAC_SetWaveAutoGeneration().
00942   * @note   This setting can be set when the selected DAC channel is disabled
00943   *         (otherwise, the setting operation is ignored).
00944   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00945   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00946   * @param  DACx DAC instance
00947   * @param  DAC_Channel This parameter can be one of the following values:
00948   *         @arg @ref LL_DAC_CHANNEL_1
00949   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00950   *
00951   *         (1) On this STM32 series, parameter not available on all instances.
00952   *             Refer to device datasheet for channels availability.
00953   * @param  NoiseLFSRMask This parameter can be one of the following values:
00954   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00955   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00956   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00957   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00958   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00959   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00960   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00961   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00962   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00963   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00964   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00965   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00966   * @retval None
00967   */
00968 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00969 {
00970   MODIFY_REG(DACx->CR,
00971              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00972              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00973 }
00974
00975 /**
00976   * @brief  Get the noise waveform generation for the selected DAC channel:
00977   *         Noise mode and parameters LFSR (linear feedback shift register).
00978   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00979   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00980   * @param  DACx DAC instance
00981   * @param  DAC_Channel This parameter can be one of the following values:
00982   *         @arg @ref LL_DAC_CHANNEL_1
00983   *         @arg @ref LL_DAC_CHANNEL_2 (1)
00984   *
00985   *         (1) On this STM32 series, parameter not available on all instances.
00986   *             Refer to device datasheet for channels availability.
00987   * @retval Returned value can be one of the following values:
00988   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00989   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00990   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00991   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00992   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00993   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00994   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00995   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00996   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00997   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00998   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00999   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
01000   */
01001 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01002 {
01003   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01004                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01005                    );
01006 }
01007
01008 /**
01009   * @brief  Set the triangle waveform generation for the selected DAC channel:
01010   *         triangle mode and amplitude.
01011   * @note   For wave generation to be effective, DAC channel
01012   *         wave generation mode must be enabled using
01013   *         function @ref LL_DAC_SetWaveAutoGeneration().
01014   * @note   This setting can be set when the selected DAC channel is disabled
01015   *         (otherwise, the setting operation is ignored).
01016   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
01017   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
01018   * @param  DACx DAC instance
01019   * @param  DAC_Channel This parameter can be one of the following values:
01020   *         @arg @ref LL_DAC_CHANNEL_1
01021   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01022   *
01023   *         (1) On this STM32 series, parameter not available on all instances.
01024   *             Refer to device datasheet for channels availability.
01025   * @param  TriangleAmplitude This parameter can be one of the following values:
01026   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
01027   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
01028   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
01029   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
01030   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
01031   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
01032   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
01033   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
01034   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
01035   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
01036   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
01037   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
01038   * @retval None
01039   */
01040 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
01041                                                      uint32_t TriangleAmplitude)
01042 {
01043   MODIFY_REG(DACx->CR,
01044              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01045              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01046 }
01047
01048 /**
01049   * @brief  Get the triangle waveform generation for the selected DAC channel:
01050   *         triangle mode and amplitude.
01051   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
01052   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
01053   * @param  DACx DAC instance
01054   * @param  DAC_Channel This parameter can be one of the following values:
01055   *         @arg @ref LL_DAC_CHANNEL_1
01056   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01057   *
01058   *         (1) On this STM32 series, parameter not available on all instances.
01059   *             Refer to device datasheet for channels availability.
01060   * @retval Returned value can be one of the following values:
01061   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
01062   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
01063   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
01064   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
01065   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
01066   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
01067   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
01068   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
01069   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
01070   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
01071   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
01072   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
01073   */
01074 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01075 {
01076   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01077                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01078                    );
01079 }
01080
01081 /**
01082   * @brief  Set the swatooth waveform generation polarity.
01083   * @note   For wave generation to be effective, DAC channel
01084   *         wave generation mode must be enabled using
01085   *         function @ref LL_DAC_SetWaveAutoGeneration().
01086   * @note   This setting can be set when the selected DAC channel is disabled
01087   *         (otherwise, the setting operation is ignored).
01088   * @rmtoll STR1     STDIR1         LL_DAC_SetWaveSawtoothPolarity\n
01089   *         STR2     STDIR2         LL_DAC_SetWaveSawtoothPolarity
01090   * @param  DACx DAC instance
01091   * @param  DAC_Channel This parameter can be one of the following values:
01092   *         @arg @ref LL_DAC_CHANNEL_1
01093   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01094   *
01095   *         (1) On this STM32 series, parameter not available on all instances.
01096   *             Refer to device datasheet for channels availability.
01097   * @param  Polarity This parameter can be one of the following values:
01098   *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
01099   *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
01100   * @retval None
01101   */
01102 __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
01103 {
01104   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01105                                              (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
01106                                              DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01107
01108   MODIFY_REG(*preg,
01109              DAC_STR1_STDIR1,
01110              Polarity);
01111 }
01112
01113 /**
01114   * @brief  Get the sawtooth waveform generation polarity.
01115   * @rmtoll STR1     STDIR1         LL_DAC_GetWaveSawtoothPolarity\n
01116   *         STR2     STDIR2         LL_DAC_GetWaveSawtoothPolarity
01117   * @param  DACx DAC instance
01118   * @param  DAC_Channel This parameter can be one of the following values:
01119   *         @arg @ref LL_DAC_CHANNEL_1
01120   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01121   *
01122   *         (1) On this STM32 series, parameter not available on all instances.
01123   *             Refer to device datasheet for channels availability.
01124   * @retval Returned value can be one of the following values:
01125   *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
01126   *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
01127   */
01128 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01129 {
01130   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01131                                                    (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
01132                                                    & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01133
01134   return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
01135 }
01136
01137 /**
01138   * @brief  Set the swatooth waveform generation reset data.
01139   * @note   For wave generation to be effective, DAC channel
01140   *         wave generation mode must be enabled using
01141   *         function @ref LL_DAC_SetWaveAutoGeneration().
01142   * @note   This setting can be set when the selected DAC channel is disabled
01143   *         (otherwise, the setting operation is ignored).
01144   * @rmtoll STR1     STRSTDATA1     LL_DAC_SetWaveSawtoothResetData\n
01145   *         STR2     STRSTDATA2     LL_DAC_SetWaveSawtoothResetData
01146   * @param  DACx DAC instance
01147   * @param  DAC_Channel This parameter can be one of the following values:
01148   *         @arg @ref LL_DAC_CHANNEL_1
01149   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01150   *
01151   *         (1) On this STM32 series, parameter not available on all instances.
01152   *             Refer to device datasheet for channels availability.
01153   * @param  ResetData This parameter is the sawtooth reset value.
01154   *         Range is from 0 to DAC full range 4095 (0xFFF)
01155   * @retval None
01156   */
01157 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
01158 {
01159   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01160                                              (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
01161                                              DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01162
01163   MODIFY_REG(*preg,
01164              DAC_STR1_STRSTDATA1,
01165              ResetData << DAC_STR1_STRSTDATA1_Pos);
01166 }
01167
01168 /**
01169   * @brief  Get the sawtooth waveform generation reset data.
01170   * @rmtoll STR1     STRSTDATA1     LL_DAC_GetWaveSawtoothResetData\n
01171   *         STR2     STRSTDATA2     LL_DAC_GetWaveSawtoothResetData
01172   * @param  DACx DAC instance
01173   * @param  DAC_Channel This parameter can be one of the following values:
01174   *         @arg @ref LL_DAC_CHANNEL_1
01175   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01176   *
01177   *         (1) On this STM32 series, parameter not available on all instances.
01178   *             Refer to device datasheet for channels availability.
01179   * @retval Returned value is the sawtooth reset value.
01180   *         Range is from 0 to DAC full range 4095 (0xFFF)
01181   */
01182 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01183 {
01184   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01185                                                    (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
01186                                                    & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01187
01188   return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
01189 }
01190
01191 /**
01192   * @brief  Set the sawtooth waveform generation step data.
01193   * @note   For wave generation to be effective, DAC channel
01194   *         wave generation mode must be enabled using
01195   *         function @ref LL_DAC_SetWaveAutoGeneration().
01196   * @note   This setting can be set when the selected DAC channel is disabled
01197   *         (otherwise, the setting operation is ignored).
01198   * @rmtoll STR1     STINCDATA1     LL_DAC_SetWaveSawtoothStepData\n
01199   *         STR2     STINCDATA2     LL_DAC_SetWaveSawtoothStepData
01200   * @param  DACx DAC instance
01201   * @param  DAC_Channel This parameter can be one of the following values:
01202   *         @arg @ref LL_DAC_CHANNEL_1
01203   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01204   *
01205   *         (1) On this STM32 series, parameter not available on all instances.
01206   *             Refer to device datasheet for channels availability.
01207   * @param  StepData This parameter is the sawtooth step value.
01208   *         12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
01209   *         Step value step is 1/16 = 0.0625
01210   *         Step value range is 0.0000 to 4095.9375 (0xFFF.F)
01211   * @retval None
01212   */
01213 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
01214 {
01215   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01216                                              (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
01217                                              DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01218
01219   MODIFY_REG(*preg,
01220              DAC_STR1_STINCDATA1,
01221              StepData << DAC_STR1_STINCDATA1_Pos);
01222 }
01223
01224 /**
01225   * @brief  Get the sawtooth waveform generation step data.
01226   * @rmtoll STR1     STINCDATA1     LL_DAC_GetWaveSawtoothStepData\n
01227   *         STR2     STINCDATA2     LL_DAC_GetWaveSawtoothStepData
01228   * @param  DACx DAC instance
01229   * @param  DAC_Channel This parameter can be one of the following values:
01230   *         @arg @ref LL_DAC_CHANNEL_1
01231   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01232   *
01233   *         (1) On this STM32 series, parameter not available on all instances.
01234   *             Refer to device datasheet for channels availability.
01235   * @retval Returned value is the sawtooth step value.
01236   *         12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
01237   *         Step value step is 1/16 = 0.0625
01238   *         Step value range is 0.0000 to 4095.9375 (0xFFF.F)
01239   */
01240 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01241 {
01242   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
01243                                                    (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
01244                                                    & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
01245
01246   return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
01247 }
01248
01249 /**
01250   * @brief  Set the sawtooth waveform generation reset trigger source.
01251   * @note   For wave generation to be effective, DAC channel
01252   *         wave generation mode must be enabled using
01253   *         function @ref LL_DAC_SetWaveAutoGeneration().
01254   * @note   This setting can be set when the selected DAC channel is disabled
01255   *         (otherwise, the setting operation is ignored).
01256   * @rmtoll STMODR   STRSTTRIGSEL1  LL_DAC_SetWaveSawtoothResetTriggerSource\n
01257   *         STMODR   STRSTTRIGSEL2  LL_DAC_SetWaveSawtoothResetTriggerSource
01258   * @param  DACx DAC instance
01259   * @param  DAC_Channel This parameter can be one of the following values:
01260   *         @arg @ref LL_DAC_CHANNEL_1
01261   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01262   *
01263   *         (1) On this STM32 series, parameter not available on all instances.
01264   *             Refer to device datasheet for channels availability.
01265   * @param  TriggerSource This parameter can be one of the following values:
01266   *         @arg @ref LL_DAC_TRIG_SOFTWARE
01267   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
01268   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
01269   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
01270   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
01271   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
01272   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
01273   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
01274   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
01275   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
01276   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
01277   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
01278   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
01279   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
01280   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
01281   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
01282   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
01283   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
01284   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
01285   *
01286   *         (1) On this STM32 series, parameter only available on DAC3.
01287   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
01288   *         (3) On this STM32 series, parameter only available on DAC1&4.
01289   *         (4) On this STM32 series, parameter only available on DAC2.
01290   *          Refer to device datasheet for DACx instances availability.
01291   *         (5) On this STM32 series, parameter not available on all devices.
01292   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
01293   * @retval None
01294   */
01295 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
01296                                                               uint32_t TriggerSource)
01297 {
01298   MODIFY_REG(DACx->STMODR,
01299              DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01300              (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos)
01301               << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01302 }
01303
01304 /**
01305   * @brief  Get the sawtooth waveform generation reset trigger source.
01306   * @rmtoll STMODR   STRSTTRIGSEL1  LL_DAC_GetWaveSawtoothResetTriggerSource\n
01307   *         STMODR   STRSTTRIGSEL2  LL_DAC_GetWaveSawtoothResetTriggerSource
01308   * @param  DACx DAC instance
01309   * @param  DAC_Channel This parameter can be one of the following values:
01310   *         @arg @ref LL_DAC_CHANNEL_1
01311   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01312   *
01313   *         (1) On this STM32 series, parameter not available on all instances.
01314   *             Refer to device datasheet for channels availability.
01315   * @retval Returned value can be one of the following values:
01316   *         @arg @ref LL_DAC_TRIG_SOFTWARE
01317   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
01318   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
01319   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
01320   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
01321   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
01322   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
01323   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
01324   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
01325   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
01326   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
01327   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
01328   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
01329   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
01330   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
01331   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
01332   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
01333   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
01334   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
01335   *
01336   *         (1) On this STM32 series, parameter only available on DAC3.
01337   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
01338   *         (3) On this STM32 series, parameter only available on DAC1&4.
01339   *         (4) On this STM32 series, parameter only available on DAC2.
01340   *          Refer to device datasheet for DACx instances availability.
01341   *         (5) On this STM32 series, parameter not available on all devices.
01342   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
01343   */
01344 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01345 {
01346   return (uint32_t)((READ_BIT(DACx->STMODR,
01347                               DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01348                              )
01349                      >> (DAC_STMODR_STRSTTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01350                     ) << DAC_CR_TSEL1_Pos);
01351 }
01352
01353 /**
01354   * @brief  Set the swatooth waveform generation step trigger source.
01355   * @note   For wave generation to be effective, DAC channel
01356   *         wave generation mode must be enabled using
01357   *         function @ref LL_DAC_SetWaveAutoGeneration().
01358   * @note   This setting can be set when the selected DAC channel is disabled
01359   *         (otherwise, the setting operation is ignored).
01360   * @rmtoll STMODR   STINCTRIGSEL1  LL_DAC_SetWaveSawtoothStepTriggerSource\n
01361   *         STMODR   STINCTRIGSEL2  LL_DAC_SetWaveSawtoothStepTriggerSource
01362   * @param  DACx DAC instance
01363   * @param  DAC_Channel This parameter can be one of the following values:
01364   *         @arg @ref LL_DAC_CHANNEL_1
01365   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01366   *
01367   *         (1) On this STM32 series, parameter not available on all instances.
01368   *             Refer to device datasheet for channels availability.
01369   * @param  TriggerSource This parameter can be one of the following values:
01370   *         @arg @ref LL_DAC_TRIG_SOFTWARE
01371   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
01372   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
01373   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
01374   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
01375   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
01376   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
01377   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
01378   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
01379   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
01380   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1      (3)
01381   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2      (3)
01382   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3      (3)
01383   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4      (3)
01384   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5      (3)
01385   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6      (3)
01386   *
01387   *         (1) On this STM32 series, parameter only available on DAC3.
01388   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
01389   *          Refer to device datasheet for DACx instances availability.
01390   *         (3) On this STM32 series, parameter not available on all devices.
01391   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
01392   * @retval None
01393   */
01394 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
01395                                                              uint32_t TriggerSource)
01396 {
01397   MODIFY_REG(DACx->STMODR,
01398              DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01399              (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos)
01400               << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01401              ));
01402 }
01403
01404 /**
01405   * @brief  Get the sawtooth waveform generation step trigger source.
01406   * @rmtoll STMODR   STINCTRIGSEL1  LL_DAC_GetWaveSawtoothStepTriggerSource\n
01407   *         STMODR   STINCTRIGSEL2  LL_DAC_GetWaveSawtoothStepTriggerSource
01408   * @param  DACx DAC instance
01409   * @param  DAC_Channel This parameter can be one of the following values:
01410   *         @arg @ref LL_DAC_CHANNEL_1
01411   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01412   *
01413   *         (1) On this STM32 series, parameter not available on all instances.
01414   *             Refer to device datasheet for channels availability.
01415   * @retval Returned value can be one of the following values:
01416   *         @arg @ref LL_DAC_TRIG_SOFTWARE
01417   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
01418   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
01419   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
01420   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
01421   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
01422   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
01423   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
01424   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
01425   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
01426   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1      (3)
01427   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2      (3)
01428   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3      (3)
01429   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4      (3)
01430   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5      (3)
01431   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6      (3)
01432   *
01433   *         (1) On this STM32 series, parameter only available on DAC3.
01434   *         (2) On this STM32 series, parameter only available on DAC1/2/4.
01435   *          Refer to device datasheet for DACx instances availability.
01436   *         (3) On this STM32 series, parameter not available on all devices.
01437   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
01438   */
01439 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01440 {
01441   return (uint32_t)((READ_BIT(DACx->STMODR,
01442                               DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01443                              )
01444                      >> (DAC_STMODR_STINCTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01445                     ) << DAC_CR_TSEL1_Pos);
01446 }
01447
01448 /**
01449   * @brief  Set the output for the selected DAC channel.
01450   * @note   This function set several features:
01451   *         - mode normal or sample-and-hold
01452   *         - buffer
01453   *         - connection to GPIO or internal path.
01454   *         These features can also be set individually using
01455   *         dedicated functions:
01456   *         - @ref LL_DAC_SetOutputBuffer()
01457   *         - @ref LL_DAC_SetOutputMode()
01458   *         - @ref LL_DAC_SetOutputConnection()
01459   * @note   On this STM32 series, output connection depends on output mode
01460   *         (normal or sample and hold) and output buffer state.
01461   *         - if output connection is set to internal path and output buffer
01462   *           is enabled (whatever output mode):
01463   *           output connection is also connected to GPIO pin
01464   *           (both connections to GPIO pin and internal path).
01465   *         - if output connection is set to GPIO pin, output buffer
01466   *           is disabled, output mode set to sample and hold:
01467   *           output connection is also connected to internal path
01468   *           (both connections to GPIO pin and internal path).
01469   * @note   Mode sample-and-hold requires an external capacitor
01470   *         to be connected between DAC channel output and ground.
01471   *         Capacitor value depends on load on DAC channel output and
01472   *         sample-and-hold timings configured.
01473   *         As indication, capacitor typical value is 100nF
01474   *         (refer to device datasheet, parameter "CSH").
01475   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
01476   *         CR       MODE2          LL_DAC_ConfigOutput
01477   * @param  DACx DAC instance
01478   * @param  DAC_Channel This parameter can be one of the following values:
01479   *         @arg @ref LL_DAC_CHANNEL_1
01480   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01481   *
01482   *         (1) On this STM32 series, parameter not available on all instances.
01483   *             Refer to device datasheet for channels availability.
01484   * @param  OutputMode This parameter can be one of the following values:
01485   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
01486   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
01487   * @param  OutputBuffer This parameter can be one of the following values:
01488   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01489   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01490   * @param  OutputConnection This parameter can be one of the following values:
01491   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01492   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01493   * @retval None
01494   */
01495 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
01496                                          uint32_t OutputBuffer, uint32_t OutputConnection)
01497 {
01498   MODIFY_REG(DACx->MCR,
01499              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01500              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01501 }
01502
01503 /**
01504   * @brief  Set the output mode normal or sample-and-hold
01505   *         for the selected DAC channel.
01506   * @note   Mode sample-and-hold requires an external capacitor
01507   *         to be connected between DAC channel output and ground.
01508   *         Capacitor value depends on load on DAC channel output and
01509   *         sample-and-hold timings configured.
01510   *         As indication, capacitor typical value is 100nF
01511   *         (refer to device datasheet, parameter "CSH").
01512   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
01513   *         CR       MODE2          LL_DAC_SetOutputMode
01514   * @param  DACx DAC instance
01515   * @param  DAC_Channel This parameter can be one of the following values:
01516   *         @arg @ref LL_DAC_CHANNEL_1
01517   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01518   *
01519   *         (1) On this STM32 series, parameter not available on all instances.
01520   *             Refer to device datasheet for channels availability.
01521   * @param  OutputMode This parameter can be one of the following values:
01522   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
01523   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
01524   * @retval None
01525   */
01526 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
01527 {
01528   MODIFY_REG(DACx->MCR,
01529              (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01530              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01531 }
01532
01533 /**
01534   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
01535   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
01536   *         CR       MODE2          LL_DAC_GetOutputMode
01537   * @param  DACx DAC instance
01538   * @param  DAC_Channel This parameter can be one of the following values:
01539   *         @arg @ref LL_DAC_CHANNEL_1
01540   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01541   *
01542   *         (1) On this STM32 series, parameter not available on all instances.
01543   *             Refer to device datasheet for channels availability.
01544   * @retval Returned value can be one of the following values:
01545   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
01546   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
01547   */
01548 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01549 {
01550   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01551                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01552                    );
01553 }
01554
01555 /**
01556   * @brief  Set the output buffer for the selected DAC channel.
01557   * @note   On this STM32 series, when buffer is enabled, its offset can be
01558   *         trimmed: factory calibration default values can be
01559   *         replaced by user trimming values, using function
01560   *         @ref LL_DAC_SetTrimmingValue().
01561   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
01562   *         CR       MODE2          LL_DAC_SetOutputBuffer
01563   * @param  DACx DAC instance
01564   * @param  DAC_Channel This parameter can be one of the following values:
01565   *         @arg @ref LL_DAC_CHANNEL_1
01566   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01567   *
01568   *         (1) On this STM32 series, parameter not available on all instances.
01569   *             Refer to device datasheet for channels availability.
01570   * @param  OutputBuffer This parameter can be one of the following values:
01571   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01572   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01573   * @retval None
01574   */
01575 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
01576 {
01577   MODIFY_REG(DACx->MCR,
01578              (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01579              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01580 }
01581
01582 /**
01583   * @brief  Get the output buffer state for the selected DAC channel.
01584   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
01585   *         CR       MODE2          LL_DAC_GetOutputBuffer
01586   * @param  DACx DAC instance
01587   * @param  DAC_Channel This parameter can be one of the following values:
01588   *         @arg @ref LL_DAC_CHANNEL_1
01589   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01590   *
01591   *         (1) On this STM32 series, parameter not available on all instances.
01592   *             Refer to device datasheet for channels availability.
01593   * @retval Returned value can be one of the following values:
01594   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01595   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01596   */
01597 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01598 {
01599   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01600                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01601                    );
01602 }
01603
01604 /**
01605   * @brief  Set the output connection for the selected DAC channel.
01606   * @note   On this STM32 series, output connection depends on output mode (normal or
01607   *         sample and hold) and output buffer state.
01608   *         - if output connection is set to internal path and output buffer
01609   *           is enabled (whatever output mode):
01610   *           output connection is also connected to GPIO pin
01611   *           (both connections to GPIO pin and internal path).
01612   *         - if output connection is set to GPIO pin, output buffer
01613   *           is disabled, output mode set to sample and hold:
01614   *           output connection is also connected to internal path
01615   *           (both connections to GPIO pin and internal path).
01616   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
01617   *         CR       MODE2          LL_DAC_SetOutputConnection
01618   * @param  DACx DAC instance
01619   * @param  DAC_Channel This parameter can be one of the following values:
01620   *         @arg @ref LL_DAC_CHANNEL_1
01621   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01622   *
01623   *         (1) On this STM32 series, parameter not available on all instances.
01624   *             Refer to device datasheet for channels availability.
01625   * @param  OutputConnection This parameter can be one of the following values:
01626   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01627   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01628   * @retval None
01629   */
01630 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
01631 {
01632   MODIFY_REG(DACx->MCR,
01633              (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01634              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01635 }
01636
01637 /**
01638   * @brief  Get the output connection for the selected DAC channel.
01639   * @note   On this STM32 series, output connection depends on output mode (normal or
01640   *         sample and hold) and output buffer state.
01641   *         - if output connection is set to internal path and output buffer
01642   *           is enabled (whatever output mode):
01643   *           output connection is also connected to GPIO pin
01644   *           (both connections to GPIO pin and internal path).
01645   *         - if output connection is set to GPIO pin, output buffer
01646   *           is disabled, output mode set to sample and hold:
01647   *           output connection is also connected to internal path
01648   *           (both connections to GPIO pin and internal path).
01649   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
01650   *         CR       MODE2          LL_DAC_GetOutputConnection
01651   * @param  DACx DAC instance
01652   * @param  DAC_Channel This parameter can be one of the following values:
01653   *         @arg @ref LL_DAC_CHANNEL_1
01654   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01655   *
01656   *         (1) On this STM32 series, parameter not available on all instances.
01657   *             Refer to device datasheet for channels availability.
01658   * @retval Returned value can be one of the following values:
01659   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01660   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01661   */
01662 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01663 {
01664   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01665                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01666                    );
01667 }
01668
01669 /**
01670   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01671   *         sample time
01672   * @note   Sample time must be set when DAC channel is disabled
01673   *         or during DAC operation when DAC channel flag BWSTx is reset,
01674   *         otherwise the setting is ignored.
01675   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
01676   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
01677   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
01678   * @param  DACx DAC instance
01679   * @param  DAC_Channel This parameter can be one of the following values:
01680   *         @arg @ref LL_DAC_CHANNEL_1
01681   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01682   *
01683   *         (1) On this STM32 series, parameter not available on all instances.
01684   *             Refer to device datasheet for channels availability.
01685   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
01686   * @retval None
01687   */
01688 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
01689 {
01690   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
01691                                              & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01692
01693   MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
01694 }
01695
01696 /**
01697   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01698   *         sample time
01699   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
01700   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
01701   * @param  DACx DAC instance
01702   * @param  DAC_Channel This parameter can be one of the following values:
01703   *         @arg @ref LL_DAC_CHANNEL_1
01704   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01705   *
01706   *         (1) On this STM32 series, parameter not available on all instances.
01707   *             Refer to device datasheet for channels availability.
01708   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01709   */
01710 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01711 {
01712   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
01713                                                    & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01714
01715   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
01716 }
01717
01718 /**
01719   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01720   *         hold time
01721   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
01722   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
01723   * @param  DACx DAC instance
01724   * @param  DAC_Channel This parameter can be one of the following values:
01725   *         @arg @ref LL_DAC_CHANNEL_1
01726   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01727   *
01728   *         (1) On this STM32 series, parameter not available on all instances.
01729   *             Refer to device datasheet for channels availability.
01730   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
01731   * @retval None
01732   */
01733 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
01734 {
01735   MODIFY_REG(DACx->SHHR,
01736              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01737              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01738 }
01739
01740 /**
01741   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01742   *         hold time
01743   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
01744   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
01745   * @param  DACx DAC instance
01746   * @param  DAC_Channel This parameter can be one of the following values:
01747   *         @arg @ref LL_DAC_CHANNEL_1
01748   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01749   *
01750   *         (1) On this STM32 series, parameter not available on all instances.
01751   *             Refer to device datasheet for channels availability.
01752   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01753   */
01754 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01755 {
01756   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01757                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01758                    );
01759 }
01760
01761 /**
01762   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01763   *         refresh time
01764   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
01765   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
01766   * @param  DACx DAC instance
01767   * @param  DAC_Channel This parameter can be one of the following values:
01768   *         @arg @ref LL_DAC_CHANNEL_1
01769   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01770   *
01771   *         (1) On this STM32 series, parameter not available on all instances.
01772   *             Refer to device datasheet for channels availability.
01773   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
01774   * @retval None
01775   */
01776 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
01777 {
01778   MODIFY_REG(DACx->SHRR,
01779              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01780              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01781 }
01782
01783 /**
01784   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01785   *         refresh time
01786   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
01787   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
01788   * @param  DACx DAC instance
01789   * @param  DAC_Channel This parameter can be one of the following values:
01790   *         @arg @ref LL_DAC_CHANNEL_1
01791   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01792   *
01793   *         (1) On this STM32 series, parameter not available on all instances.
01794   *             Refer to device datasheet for channels availability.
01795   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01796   */
01797 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01798 {
01799   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01800                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01801                    );
01802 }
01803
01804 /**
01805   * @brief  Set the signed format for the selected DAC channel.
01806   * @note   On this STM32 series, signed format can be used to inject
01807   *         Q1.15, Q1.11, Q1.7 signed format data to DAC.
01808   *         Ex when using 12bits data format (Q1.11 is used):
01809   *             0x800 will output 0v level
01810   *             0xFFF will output mid-scale level
01811   *             0x000 will output mid-scale level
01812   *             0x7FF will output full-scale level
01813   * @rmtoll MCR      SINFORMAT1     LL_DAC_SetSignedFormat\n
01814   *         MCR      SINFORMAT2     LL_DAC_SetSignedFormat
01815   * @param  DACx DAC instance
01816   * @param  DAC_Channel This parameter can be one of the following values:
01817   *         @arg @ref LL_DAC_CHANNEL_1
01818   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01819   *
01820   *         (1) On this STM32 series, parameter not available on all instances.
01821   *             Refer to device datasheet for channels availability.
01822   * @param  SignedFormat This parameter can be one of the following values:
01823   *         @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
01824   *         @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
01825   * @retval None
01826   */
01827 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
01828 {
01829   MODIFY_REG(DACx->MCR,
01830              DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01831              SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01832 }
01833
01834 /**
01835   * @brief  Get the signed format state for the selected DAC channel.
01836   * @rmtoll MCR      SINFORMAT1     LL_DAC_GetSignedFormat\n
01837   *         MCR      SINFORMAT2     LL_DAC_GetSignedFormat
01838   * @param  DACx DAC instance
01839   * @param  DAC_Channel This parameter can be one of the following values:
01840   *         @arg @ref LL_DAC_CHANNEL_1
01841   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01842   *
01843   *         (1) On this STM32 series, parameter not available on all instances.
01844   *             Refer to device datasheet for channels availability.
01845   * @retval Returned value can be one of the following values:
01846   *         @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
01847   *         @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
01848   */
01849 __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01850 {
01851   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01852                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01853                    );
01854 }
01855
01856 /**
01857   * @}
01858   */
01859
01860 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
01861   * @{
01862   */
01863
01864 /**
01865   * @brief  Enable DAC DMA transfer request of the selected channel.
01866   * @note   To configure DMA source address (peripheral address),
01867   *         use function @ref LL_DAC_DMA_GetRegAddr().
01868   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
01869   *         CR       DMAEN2         LL_DAC_EnableDMAReq
01870   * @param  DACx DAC instance
01871   * @param  DAC_Channel This parameter can be one of the following values:
01872   *         @arg @ref LL_DAC_CHANNEL_1
01873   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01874   *
01875   *         (1) On this STM32 series, parameter not available on all instances.
01876   *             Refer to device datasheet for channels availability.
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01880 {
01881   SET_BIT(DACx->CR,
01882           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01883 }
01884
01885 /**
01886   * @brief  Disable DAC DMA transfer request of the selected channel.
01887   * @note   To configure DMA source address (peripheral address),
01888   *         use function @ref LL_DAC_DMA_GetRegAddr().
01889   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
01890   *         CR       DMAEN2         LL_DAC_DisableDMAReq
01891   * @param  DACx DAC instance
01892   * @param  DAC_Channel This parameter can be one of the following values:
01893   *         @arg @ref LL_DAC_CHANNEL_1
01894   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01895   *
01896   *         (1) On this STM32 series, parameter not available on all instances.
01897   *             Refer to device datasheet for channels availability.
01898   * @retval None
01899   */
01900 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01901 {
01902   CLEAR_BIT(DACx->CR,
01903             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01904 }
01905
01906 /**
01907   * @brief  Get DAC DMA transfer request state of the selected channel.
01908   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
01909   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
01910   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
01911   * @param  DACx DAC instance
01912   * @param  DAC_Channel This parameter can be one of the following values:
01913   *         @arg @ref LL_DAC_CHANNEL_1
01914   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01915   *
01916   *         (1) On this STM32 series, parameter not available on all instances.
01917   *             Refer to device datasheet for channels availability.
01918   * @retval State of bit (1 or 0).
01919   */
01920 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01921 {
01922   return ((READ_BIT(DACx->CR,
01923                     DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01924            == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01925 }
01926
01927 /**
01928   * @brief  Enable DAC DMA Double data mode of the selected channel.
01929   * @rmtoll MCR      DMADOUBLE1     LL_DAC_EnableDMADoubleDataMode\n
01930   *         MCR      DMADOUBLE2     LL_DAC_EnableDMADoubleDataMode
01931   * @param  DACx DAC instance
01932   * @param  DAC_Channel This parameter can be one of the following values:
01933   *         @arg @ref LL_DAC_CHANNEL_1
01934   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01935   *
01936   *         (1) On this STM32 series, parameter not available on all instances.
01937   *             Refer to device datasheet for channels availability.
01938   * @retval None
01939   */
01940 __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01941 {
01942   SET_BIT(DACx->MCR,
01943           DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01944 }
01945
01946 /**
01947   * @brief  Disable DAC DMA Double data mode of the selected channel.
01948   * @rmtoll MCR      DMADOUBLE1     LL_DAC_DisableDMADoubleDataMode\n
01949   *         MCR      DMADOUBLE2     LL_DAC_DisableDMADoubleDataMode
01950   * @param  DACx DAC instance
01951   * @param  DAC_Channel This parameter can be one of the following values:
01952   *         @arg @ref LL_DAC_CHANNEL_1
01953   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01954   *
01955   *         (1) On this STM32 series, parameter not available on all instances.
01956   *             Refer to device datasheet for channels availability.
01957   * @retval None
01958   */
01959 __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01960 {
01961   CLEAR_BIT(DACx->MCR,
01962             DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01963 }
01964
01965 /**
01966   * @brief  Get DAC DMA double data mode state of the selected channel.
01967   *         (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
01968   * @rmtoll MCR      DMADOUBLE1     LL_DAC_IsDMADoubleDataModeEnabled\n
01969   *         MCR      DMADOUBLE2     LL_DAC_IsDMADoubleDataModeEnabled
01970   * @param  DACx DAC instance
01971   * @param  DAC_Channel This parameter can be one of the following values:
01972   *         @arg @ref LL_DAC_CHANNEL_1
01973   *         @arg @ref LL_DAC_CHANNEL_2 (1)
01974   *
01975   *         (1) On this STM32 series, parameter not available on all instances.
01976   *             Refer to device datasheet for channels availability.
01977   * @retval State of bit (1 or 0).
01978   */
01979 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
01980 {
01981   return ((READ_BIT(DACx->MCR,
01982                     DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01983            == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01984 }
01985
01986 /**
01987   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
01988   *         DAC register address from DAC instance and a list of DAC registers
01989   *         intended to be used (most commonly) with DMA transfer.
01990   * @note   These DAC registers are data holding registers:
01991   *         when DAC conversion is requested, DAC generates a DMA transfer
01992   *         request to have data available in DAC data holding registers.
01993   * @note   This macro is intended to be used with LL DMA driver, refer to
01994   *         function "LL_DMA_ConfigAddresses()".
01995   *         Example:
01996   *           LL_DMA_ConfigAddresses(DMA1,
01997   *                                  LL_DMA_CHANNEL_1,
01998   *                                  (uint32_t)&< array or variable >,
01999   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
02000   *                                  LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
02001   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
02002   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
02003   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
02004   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
02005   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
02006   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
02007   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
02008   * @param  DACx DAC instance
02009   * @param  DAC_Channel This parameter can be one of the following values:
02010   *         @arg @ref LL_DAC_CHANNEL_1
02011   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02012   *
02013   *         (1) On this STM32 series, parameter not available on all instances.
02014   *             Refer to device datasheet for channels availability.
02015   * @param  Register This parameter can be one of the following values:
02016   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
02017   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
02018   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
02019   * @retval DAC register address
02020   */
02021 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
02022 {
02023   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
02024   /* DAC channel selected.                                                    */
02025   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
02026                                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
02027 }
02028 /**
02029   * @}
02030   */
02031
02032 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
02033   * @{
02034   */
02035
02036 /**
02037   * @brief  Enable DAC selected channel.
02038   * @rmtoll CR       EN1            LL_DAC_Enable\n
02039   *         CR       EN2            LL_DAC_Enable
02040   * @note   After enable from off state, DAC channel requires a delay
02041   *         for output voltage to reach accuracy +/- 1 LSB.
02042   *         Refer to device datasheet, parameter "tWAKEUP".
02043   * @param  DACx DAC instance
02044   * @param  DAC_Channel This parameter can be one of the following values:
02045   *         @arg @ref LL_DAC_CHANNEL_1
02046   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02047   *
02048   *         (1) On this STM32 series, parameter not available on all instances.
02049   *             Refer to device datasheet for channels availability.
02050   * @retval None
02051   */
02052 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02053 {
02054   SET_BIT(DACx->CR,
02055           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
02056 }
02057
02058 /**
02059   * @brief  Disable DAC selected channel.
02060   * @rmtoll CR       EN1            LL_DAC_Disable\n
02061   *         CR       EN2            LL_DAC_Disable
02062   * @param  DACx DAC instance
02063   * @param  DAC_Channel This parameter can be one of the following values:
02064   *         @arg @ref LL_DAC_CHANNEL_1
02065   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02066   *
02067   *         (1) On this STM32 series, parameter not available on all instances.
02068   *             Refer to device datasheet for channels availability.
02069   * @retval None
02070   */
02071 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02072 {
02073   CLEAR_BIT(DACx->CR,
02074             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
02075 }
02076
02077 /**
02078   * @brief  Get DAC enable state of the selected channel.
02079   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
02080   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
02081   *         CR       EN2            LL_DAC_IsEnabled
02082   * @param  DACx DAC instance
02083   * @param  DAC_Channel This parameter can be one of the following values:
02084   *         @arg @ref LL_DAC_CHANNEL_1
02085   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02086   *
02087   *         (1) On this STM32 series, parameter not available on all instances.
02088   *             Refer to device datasheet for channels availability.
02089   * @retval State of bit (1 or 0).
02090   */
02091 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
02092 {
02093   return ((READ_BIT(DACx->CR,
02094                     DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
02095            == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
02096 }
02097
02098 /**
02099   * @brief  Get DAC ready for conversion state of the selected channel.
02100   *         (0: DAC channel is not ready, 1: DAC channel is ready)
02101   * @rmtoll SR       DAC1RDY        LL_DAC_IsReady\n
02102   *         SR       DAC2RDY        LL_DAC_IsReady
02103   * @param  DACx DAC instance
02104   * @param  DAC_Channel This parameter can be one of the following values:
02105   *         @arg @ref LL_DAC_CHANNEL_1
02106   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02107   *
02108   *         (1) On this STM32 series, parameter not available on all instances.
02109   *             Refer to device datasheet for channels availability.
02110   * @retval State of bit (1 or 0).
02111   */
02112 __STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
02113 {
02114   return ((READ_BIT(DACx->SR,
02115                     DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
02116            == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
02117 }
02118
02119 /**
02120   * @brief  Enable DAC trigger of the selected channel.
02121   * @note   - If DAC trigger is disabled, DAC conversion is performed
02122   *           automatically once the data holding register is updated,
02123   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
02124   *           @ref LL_DAC_ConvertData12RightAligned(), ...
02125   *         - If DAC trigger is enabled, DAC conversion is performed
02126   *           only when a hardware of software trigger event is occurring.
02127   *           Select trigger source using
02128   *           function @ref LL_DAC_SetTriggerSource().
02129   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
02130   *         CR       TEN2           LL_DAC_EnableTrigger
02131   * @param  DACx DAC instance
02132   * @param  DAC_Channel This parameter can be one of the following values:
02133   *         @arg @ref LL_DAC_CHANNEL_1
02134   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02135   *
02136   *         (1) On this STM32 series, parameter not available on all instances.
02137   *             Refer to device datasheet for channels availability.
02138   * @retval None
02139   */
02140 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02141 {
02142   SET_BIT(DACx->CR,
02143           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
02144 }
02145
02146 /**
02147   * @brief  Disable DAC trigger of the selected channel.
02148   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
02149   *         CR       TEN2           LL_DAC_DisableTrigger
02150   * @param  DACx DAC instance
02151   * @param  DAC_Channel This parameter can be one of the following values:
02152   *         @arg @ref LL_DAC_CHANNEL_1
02153   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02154   *
02155   *         (1) On this STM32 series, parameter not available on all instances.
02156   *             Refer to device datasheet for channels availability.
02157   * @retval None
02158   */
02159 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02160 {
02161   CLEAR_BIT(DACx->CR,
02162             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
02163 }
02164
02165 /**
02166   * @brief  Get DAC trigger state of the selected channel.
02167   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
02168   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
02169   *         CR       TEN2           LL_DAC_IsTriggerEnabled
02170   * @param  DACx DAC instance
02171   * @param  DAC_Channel This parameter can be one of the following values:
02172   *         @arg @ref LL_DAC_CHANNEL_1
02173   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02174   *
02175   *         (1) On this STM32 series, parameter not available on all instances.
02176   *             Refer to device datasheet for channels availability.
02177   * @retval State of bit (1 or 0).
02178   */
02179 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
02180 {
02181   return ((READ_BIT(DACx->CR,
02182                     DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
02183            == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
02184 }
02185
02186 /**
02187   * @brief  Trig DAC conversion by software for the selected DAC channel.
02188   * @note   Preliminarily, DAC trigger must be set to software trigger
02189   *         using function
02190   *           @ref LL_DAC_Init()
02191   *           @ref LL_DAC_SetTriggerSource()
02192   *           @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
02193   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
02194   *         and DAC trigger must be enabled using
02195   *         function @ref LL_DAC_EnableTrigger().
02196   *
02197   *           (1) In case, Sawtooth wave generation has been configured.
02198   * @note   For devices featuring DAC with 2 channels: this function
02199   *         can perform a SW start of both DAC channels simultaneously.
02200   *         Two channels can be selected as parameter.
02201   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
02202   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
02203   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
02204   * @param  DACx DAC instance
02205   * @param  DAC_Channel  This parameter can a combination of the following values:
02206   *         @arg @ref LL_DAC_CHANNEL_1
02207   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02208   *
02209   *         (1) On this STM32 series, parameter not available on all instances.
02210   *             Refer to device datasheet for channels availability.
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02214 {
02215   SET_BIT(DACx->SWTRIGR,
02216           (DAC_Channel & DAC_SWTR_CHX_MASK));
02217 }
02218
02219 /**
02220   * @brief  Trig DAC conversion by secondary software trigger for the selected DAC channel.
02221   * @note   Preliminarily, DAC secondary trigger must be set to software trigger
02222   *         using function
02223   *           @ref LL_DAC_Init()
02224   *           @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
02225   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
02226   *         and DAC trigger must be enabled using
02227   *         function @ref LL_DAC_EnableTrigger().
02228   *
02229   *           (1) In case, Sawtooth wave generation has been configured.
02230   * @note   For devices featuring DAC with 2 channels: this function
02231   *         can perform a SW start of both DAC channels simultaneously.
02232   *         Two channels can be selected as parameter.
02233   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
02234   * @rmtoll SWTRIGR  SWTRIGB1       LL_DAC_TrigSWConversion2\n
02235   *         SWTRIGR  SWTRIGB2       LL_DAC_TrigSWConversion2
02236   * @param  DACx DAC instance
02237   * @param  DAC_Channel  This parameter can a combination of the following values:
02238   *         @arg @ref LL_DAC_CHANNEL_1
02239   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02240   *
02241   *         (1) On this STM32 series, parameter not available on all instances.
02242   *             Refer to device datasheet for channels availability.
02243   * @retval None
02244   */
02245 __STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Channel)
02246 {
02247   SET_BIT(DACx->SWTRIGR,
02248           (DAC_Channel & DAC_SWTRB_CHX_MASK));
02249 }
02250
02251 /**
02252   * @brief  Set the data to be loaded in the data holding register
02253   *         in format 12 bits left alignment (LSB aligned on bit 0),
02254   *         for the selected DAC channel.
02255   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
02256   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
02257   * @param  DACx DAC instance
02258   * @param  DAC_Channel This parameter can be one of the following values:
02259   *         @arg @ref LL_DAC_CHANNEL_1
02260   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02261   *
02262   *         (1) On this STM32 series, parameter not available on all instances.
02263   *             Refer to device datasheet for channels availability.
02264   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
02265   * @retval None
02266   */
02267 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
02268 {
02269   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
02270                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
02271
02272   MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
02273 }
02274
02275 /**
02276   * @brief  Set the data to be loaded in the data holding register
02277   *         in format 12 bits left alignment (MSB aligned on bit 15),
02278   *         for the selected DAC channel.
02279   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
02280   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
02281   * @param  DACx DAC instance
02282   * @param  DAC_Channel This parameter can be one of the following values:
02283   *         @arg @ref LL_DAC_CHANNEL_1
02284   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02285   *
02286   *         (1) On this STM32 series, parameter not available on all instances.
02287   *             Refer to device datasheet for channels availability.
02288   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
02289   * @retval None
02290   */
02291 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
02292 {
02293   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
02294                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
02295
02296   MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
02297 }
02298
02299 /**
02300   * @brief  Set the data to be loaded in the data holding register
02301   *         in format 8 bits left alignment (LSB aligned on bit 0),
02302   *         for the selected DAC channel.
02303   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
02304   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
02305   * @param  DACx DAC instance
02306   * @param  DAC_Channel This parameter can be one of the following values:
02307   *         @arg @ref LL_DAC_CHANNEL_1
02308   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02309   *
02310   *         (1) On this STM32 series, parameter not available on all instances.
02311   *             Refer to device datasheet for channels availability.
02312   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02313   * @retval None
02314   */
02315 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
02316 {
02317   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
02318                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
02319
02320   MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
02321 }
02322
02323
02324 /**
02325   * @brief  Set the data to be loaded in the data holding register
02326   *         in format 12 bits left alignment (LSB aligned on bit 0),
02327   *         for both DAC channels.
02328   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
02329   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
02330   * @param  DACx DAC instance
02331   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
02332   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
02333   * @retval None
02334   */
02335 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
02336                                                           uint32_t DataChannel2)
02337 {
02338   MODIFY_REG(DACx->DHR12RD,
02339              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
02340              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
02341 }
02342
02343 /**
02344   * @brief  Set the data to be loaded in the data holding register
02345   *         in format 12 bits left alignment (MSB aligned on bit 15),
02346   *         for both DAC channels.
02347   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
02348   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
02349   * @param  DACx DAC instance
02350   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
02351   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
02352   * @retval None
02353   */
02354 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
02355                                                          uint32_t DataChannel2)
02356 {
02357   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
02358   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
02359   /*       the 4 LSB must be taken into account for the shift value.          */
02360   MODIFY_REG(DACx->DHR12LD,
02361              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
02362              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
02363 }
02364
02365 /**
02366   * @brief  Set the data to be loaded in the data holding register
02367   *         in format 8 bits left alignment (LSB aligned on bit 0),
02368   *         for both DAC channels.
02369   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
02370   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
02371   * @param  DACx DAC instance
02372   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
02373   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
02374   * @retval None
02375   */
02376 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
02377                                                          uint32_t DataChannel2)
02378 {
02379   MODIFY_REG(DACx->DHR8RD,
02380              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
02381              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
02382 }
02383
02384
02385 /**
02386   * @brief  Retrieve output data currently generated for the selected DAC channel.
02387   * @note   Whatever alignment and resolution settings
02388   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
02389   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
02390   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
02391   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
02392   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
02393   * @param  DACx DAC instance
02394   * @param  DAC_Channel This parameter can be one of the following values:
02395   *         @arg @ref LL_DAC_CHANNEL_1
02396   *         @arg @ref LL_DAC_CHANNEL_2 (1)
02397   *
02398   *         (1) On this STM32 series, parameter not available on all instances.
02399   *             Refer to device datasheet for channels availability.
02400   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02401   */
02402 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
02403 {
02404   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
02405                                                    & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
02406
02407   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
02408 }
02409
02410 /**
02411   * @}
02412   */
02413
02414 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
02415   * @{
02416   */
02417
02418 /**
02419   * @brief  Get DAC calibration offset flag for DAC channel 1
02420   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
02421   * @param  DACx DAC instance
02422   * @retval State of bit (1 or 0).
02423   */
02424 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
02425 {
02426   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
02427 }
02428
02429
02430 /**
02431   * @brief  Get DAC calibration offset flag for DAC channel 2
02432   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
02433   * @param  DACx DAC instance
02434   * @retval State of bit (1 or 0).
02435   */
02436 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
02437 {
02438   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
02439 }
02440
02441
02442 /**
02443   * @brief  Get DAC busy writing sample time flag for DAC channel 1
02444   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
02445   * @param  DACx DAC instance
02446   * @retval State of bit (1 or 0).
02447   */
02448 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
02449 {
02450   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
02451 }
02452
02453 /**
02454   * @brief  Get DAC busy writing sample time flag for DAC channel 2
02455   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
02456   * @param  DACx DAC instance
02457   * @retval State of bit (1 or 0).
02458   */
02459 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
02460 {
02461   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
02462 }
02463
02464
02465 /**
02466   * @brief  Get DAC ready status flag for DAC channel 1
02467   * @rmtoll SR       DAC1RDY        LL_DAC_IsActiveFlag_DAC1RDY
02468   * @param  DACx DAC instance
02469   * @retval State of bit (1 or 0).
02470   */
02471 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx)
02472 {
02473   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
02474 }
02475
02476
02477 /**
02478   * @brief  Get DAC ready status flag for DAC channel 2
02479   * @rmtoll SR       DAC2RDY        LL_DAC_IsActiveFlag_DAC2RDY
02480   * @param  DACx DAC instance
02481   * @retval State of bit (1 or 0).
02482   */
02483 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx)
02484 {
02485   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
02486 }
02487
02488
02489 /**
02490   * @brief  Get DAC output register status flag for DAC channel 1
02491   * @rmtoll SR       DORSTAT1       LL_DAC_IsActiveFlag_DORSTAT1
02492   * @param  DACx DAC instance
02493   * @retval State of bit (1 or 0).
02494   */
02495 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx)
02496 {
02497   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
02498 }
02499
02500
02501 /**
02502   * @brief  Get DAC output register status flag for DAC channel 2
02503   * @rmtoll SR       DORSTAT2       LL_DAC_IsActiveFlag_DORSTAT2
02504   * @param  DACx DAC instance
02505   * @retval State of bit (1 or 0).
02506   */
02507 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx)
02508 {
02509   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
02510 }
02511
02512 /**
02513   * @brief  Get DAC underrun flag for DAC channel 1
02514   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
02515   * @param  DACx DAC instance
02516   * @retval State of bit (1 or 0).
02517   */
02518 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
02519 {
02520   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
02521 }
02522
02523
02524 /**
02525   * @brief  Get DAC underrun flag for DAC channel 2
02526   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
02527   * @param  DACx DAC instance
02528   * @retval State of bit (1 or 0).
02529   */
02530 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
02531 {
02532   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
02533 }
02534
02535
02536 /**
02537   * @brief  Clear DAC underrun flag for DAC channel 1
02538   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
02539   * @param  DACx DAC instance
02540   * @retval None
02541   */
02542 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
02543 {
02544   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
02545 }
02546
02547
02548 /**
02549   * @brief  Clear DAC underrun flag for DAC channel 2
02550   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
02551   * @param  DACx DAC instance
02552   * @retval None
02553   */
02554 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
02555 {
02556   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
02557 }
02558
02559
02560 /**
02561   * @}
02562   */
02563
02564 /** @defgroup DAC_LL_EF_IT_Management IT management
02565   * @{
02566   */
02567
02568 /**
02569   * @brief  Enable DMA underrun interrupt for DAC channel 1
02570   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
02571   * @param  DACx DAC instance
02572   * @retval None
02573   */
02574 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
02575 {
02576   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
02577 }
02578
02579
02580 /**
02581   * @brief  Enable DMA underrun interrupt for DAC channel 2
02582   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
02583   * @param  DACx DAC instance
02584   * @retval None
02585   */
02586 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
02587 {
02588   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
02589 }
02590
02591
02592 /**
02593   * @brief  Disable DMA underrun interrupt for DAC channel 1
02594   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
02595   * @param  DACx DAC instance
02596   * @retval None
02597   */
02598 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
02599 {
02600   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
02601 }
02602
02603
02604 /**
02605   * @brief  Disable DMA underrun interrupt for DAC channel 2
02606   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
02607   * @param  DACx DAC instance
02608   * @retval None
02609   */
02610 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
02611 {
02612   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
02613 }
02614
02615
02616 /**
02617   * @brief  Get DMA underrun interrupt for DAC channel 1
02618   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
02619   * @param  DACx DAC instance
02620   * @retval State of bit (1 or 0).
02621   */
02622 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
02623 {
02624   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
02625 }
02626
02627
02628 /**
02629   * @brief  Get DMA underrun interrupt for DAC channel 2
02630   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
02631   * @param  DACx DAC instance
02632   * @retval State of bit (1 or 0).
02633   */
02634 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
02635 {
02636   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
02637 }
02638
02639
02640 /**
02641   * @}
02642   */
02643
02644 #if defined(USE_FULL_LL_DRIVER)
02645 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
02646   * @{
02647   */
02648
02649 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
02650 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
02651 void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
02652
02653 /**
02654   * @}
02655   */
02656 #endif /* USE_FULL_LL_DRIVER */
02657
02658 /**
02659   * @}
02660   */
02661
02662 /**
02663   * @}
02664   */
02665
02666 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
02667
02668 /**
02669   * @}
02670   */
02671
02672 #ifdef __cplusplus
02673 }
02674 #endif
02675
02676 #endif /* STM32G4xx_LL_DAC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dma.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_dma.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32g4xx_ll_dma.h"
00023 #include "stm32g4xx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMA1) || defined (DMA2)
00035
00036 /** @defgroup DMA_LL DMA
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup DMA_LL_Private_Macros
00045   * @{
00046   */
00047 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00048                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00049                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00050
00051 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00052                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00053
00054 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00055                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00056
00057 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00058                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00059
00060 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00061                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00062                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00063
00064 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00065                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00066                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00067
00068 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
00069
00070 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= 115U)
00071
00072 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00073                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00074                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00075                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00076
00077 #if defined (DMA1_Channel8)
00078 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00079                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00080                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00081                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00082                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00083                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00084                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00085                                                               ((CHANNEL) == LL_DMA_CHANNEL_7) || \
00086                                                               ((CHANNEL) == LL_DMA_CHANNEL_8))) || \
00087                                                             (((INSTANCE) == DMA2) && \
00088                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00089                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00090                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00091                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00092                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00093                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00094                                                               ((CHANNEL) == LL_DMA_CHANNEL_7) || \
00095                                                               ((CHANNEL) == LL_DMA_CHANNEL_8))))
00096 #elif defined (DMA1_Channel6)
00097 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00098                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00099                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00100                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00101                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00102                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00103                                                               ((CHANNEL) == LL_DMA_CHANNEL_6))) || \
00104                                                             (((INSTANCE) == DMA2) && \
00105                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00106                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00107                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00108                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00109                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00110                                                               ((CHANNEL) == LL_DMA_CHANNEL_6))))
00111 #endif /* DMA1_Channel8 */
00112 /**
00113   * @}
00114   */
00115
00116 /* Private function prototypes -----------------------------------------------*/
00117
00118 /* Exported functions --------------------------------------------------------*/
00119 /** @addtogroup DMA_LL_Exported_Functions
00120   * @{
00121   */
00122
00123 /** @addtogroup DMA_LL_EF_Init
00124   * @{
00125   */
00126
00127 /**
00128   * @brief  De-initialize the DMA registers to their default reset values.
00129   * @param  DMAx DMAx Instance
00130   * @param  Channel This parameter can be one of the following values:
00131   *         @arg @ref LL_DMA_CHANNEL_1
00132   *         @arg @ref LL_DMA_CHANNEL_2
00133   *         @arg @ref LL_DMA_CHANNEL_3
00134   *         @arg @ref LL_DMA_CHANNEL_4
00135   *         @arg @ref LL_DMA_CHANNEL_5
00136   *         @arg @ref LL_DMA_CHANNEL_6
00137   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00138   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00139   *         @arg @ref LL_DMA_CHANNEL_ALL
00140   *         (*) Not on all G4 devices
00141   * @retval An ErrorStatus enumeration value:
00142   *          - SUCCESS: DMA registers are de-initialized
00143   *          - ERROR: DMA registers are not de-initialized
00144   */
00145 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00146 {
00147   DMA_Channel_TypeDef *tmp;
00148   ErrorStatus status = SUCCESS;
00149
00150   /* Check the DMA Instance DMAx and Channel parameters*/
00151   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
00152
00153   if (Channel == LL_DMA_CHANNEL_ALL)
00154   {
00155     if (DMAx == DMA1)
00156     {
00157       /* Force reset of DMA clock */
00158       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00159
00160       /* Release reset of DMA clock */
00161       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00162     }
00163     else if (DMAx == DMA2)
00164     {
00165       /* Force reset of DMA clock */
00166       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
00167
00168       /* Release reset of DMA clock */
00169       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
00170     }
00171     else
00172     {
00173       status = ERROR;
00174     }
00175   }
00176   else
00177   {
00178     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00179
00180     /* Disable the selected DMAx_Channely */
00181     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
00182
00183     /* Reset DMAx_Channely control register */
00184     WRITE_REG(tmp->CCR, 0U);
00185
00186     /* Reset DMAx_Channely remaining bytes register */
00187     WRITE_REG(tmp->CNDTR, 0U);
00188
00189     /* Reset DMAx_Channely peripheral address register */
00190     WRITE_REG(tmp->CPAR, 0U);
00191
00192     /* Reset DMAx_Channely memory address register */
00193     WRITE_REG(tmp->CMAR, 0U);
00194
00195     /* Reset Request register field for DMAx Channel */
00196     LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
00197
00198     if (Channel == LL_DMA_CHANNEL_1)
00199     {
00200       /* Reset interrupt pending bits for DMAx Channel1 */
00201       LL_DMA_ClearFlag_GI1(DMAx);
00202     }
00203     else if (Channel == LL_DMA_CHANNEL_2)
00204     {
00205       /* Reset interrupt pending bits for DMAx Channel2 */
00206       LL_DMA_ClearFlag_GI2(DMAx);
00207     }
00208     else if (Channel == LL_DMA_CHANNEL_3)
00209     {
00210       /* Reset interrupt pending bits for DMAx Channel3 */
00211       LL_DMA_ClearFlag_GI3(DMAx);
00212     }
00213     else if (Channel == LL_DMA_CHANNEL_4)
00214     {
00215       /* Reset interrupt pending bits for DMAx Channel4 */
00216       LL_DMA_ClearFlag_GI4(DMAx);
00217     }
00218     else if (Channel == LL_DMA_CHANNEL_5)
00219     {
00220       /* Reset interrupt pending bits for DMAx Channel5 */
00221       LL_DMA_ClearFlag_GI5(DMAx);
00222     }
00223
00224     else if (Channel == LL_DMA_CHANNEL_6)
00225     {
00226       /* Reset interrupt pending bits for DMAx Channel6 */
00227       LL_DMA_ClearFlag_GI6(DMAx);
00228     }
00229 #if defined (DMA1_Channel7)
00230     else if (Channel == LL_DMA_CHANNEL_7)
00231     {
00232       /* Reset interrupt pending bits for DMAx Channel7 */
00233       LL_DMA_ClearFlag_GI7(DMAx);
00234     }
00235 #endif /* DMA1_Channel7 */
00236 #if defined (DMA1_Channel8)
00237     else if (Channel == LL_DMA_CHANNEL_8)
00238     {
00239       /* Reset interrupt pending bits for DMAx Channel8 */
00240       LL_DMA_ClearFlag_GI8(DMAx);
00241     }
00242 #endif /* DMA1_Channel8 */
00243     else
00244     {
00245       status = ERROR;
00246     }
00247   }
00248
00249   return (uint32_t)status;
00250 }
00251
00252 /**
00253   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00254   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00255   *         @arg @ref __LL_DMA_GET_INSTANCE
00256   *         @arg @ref __LL_DMA_GET_CHANNEL
00257   * @param  DMAx DMAx Instance
00258   * @param  Channel This parameter can be one of the following values:
00259   *         @arg @ref LL_DMA_CHANNEL_1
00260   *         @arg @ref LL_DMA_CHANNEL_2
00261   *         @arg @ref LL_DMA_CHANNEL_3
00262   *         @arg @ref LL_DMA_CHANNEL_4
00263   *         @arg @ref LL_DMA_CHANNEL_5
00264   *         @arg @ref LL_DMA_CHANNEL_6
00265   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00266   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00267   *         (*) Not on all G4 devices
00268   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00269   * @retval An ErrorStatus enumeration value:
00270   *          - SUCCESS: DMA registers are initialized
00271   *          - ERROR: Not applicable
00272   */
00273 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00274 {
00275   /* Check the DMA Instance DMAx and Channel parameters*/
00276   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00277
00278   /* Check the DMA parameters from DMA_InitStruct */
00279   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00280   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00281   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00282   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00283   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00284   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00285   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00286   assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
00287   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00288
00289   /*---------------------------- DMAx CCR Configuration ------------------------
00290    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00291    *                          peripheral and memory increment mode,
00292    *                          data size alignment and  priority level with parameters :
00293    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00294    * - Mode:           DMA_CCR_CIRC bit
00295    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00296    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00297    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00298    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00299    * - Priority:               DMA_CCR_PL[1:0] bits
00300    */
00301   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
00302                         DMA_InitStruct->Mode                   | \
00303                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00304                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00305                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00306                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00307                         DMA_InitStruct->Priority);
00308
00309   /*-------------------------- DMAx CMAR Configuration -------------------------
00310    * Configure the memory or destination base address with parameter :
00311    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00312    */
00313   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00314
00315   /*-------------------------- DMAx CPAR Configuration -------------------------
00316    * Configure the peripheral or source base address with parameter :
00317    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00318    */
00319   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00320
00321   /*--------------------------- DMAx CNDTR Configuration -----------------------
00322    * Configure the peripheral base address with parameter :
00323    * - NbData: DMA_CNDTR_NDT[15:0] bits
00324    */
00325   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00326
00327   /*--------------------------- DMAMUXx CCR Configuration ----------------------
00328    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
00329    * - PeriphRequest: DMA_CxCR[7:0] bits
00330    */
00331   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
00332
00333   return (uint32_t)SUCCESS;
00334 }
00335
00336 /**
00337   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00338   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00339   * @retval None
00340   */
00341 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00342 {
00343   /* Set DMA_InitStruct fields to default values */
00344   DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
00345   DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
00346   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00347   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00348   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00349   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00350   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00351   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00352   DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
00353   DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
00354   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00355 }
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 #endif /* DMA1 || DMA2 */
00370
00371 /**
00372   * @}
00373   */
00374
00375 #endif /* USE_FULL_LL_DRIVER */
00376
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dma.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_dma.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_LL_DMA_H
00021 #define __STM32G4xx_LL_DMA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029 #include "stm32g4xx_ll_dmamux.h"
00030
00031 /** @addtogroup STM32G4xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (DMA1) || defined (DMA2)
00036
00037 /** @defgroup DMA_LL DMA
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00044   * @{
00045   */
00046 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
00047 static const uint8_t CHANNEL_OFFSET_TAB[] =
00048 {
00049   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
00050   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
00051   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
00052   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
00053   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
00054   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
00055 #if defined (DMA1_Channel7)
00056   ,
00057   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
00058 #endif /* DMA1_Channel7 */
00059 #if defined (DMA1_Channel8)
00060   ,
00061   (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
00062 #endif /* DMA1_Channel8 */
00063 };
00064 /**
00065   * @}
00066   */
00067
00068 /* Private constants ---------------------------------------------------------*/
00069 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
00070   * @{
00071   */
00072 /* Define used to get CSELR register offset */
00073 #define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
00074
00075 /* Defines used for the bit position in the register and perform offsets */
00076 #define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
00077 /**
00078   * @}
00079   */
00080
00081 /* Private macros ------------------------------------------------------------*/
00082 #if defined(USE_FULL_LL_DRIVER)
00083 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00084   * @{
00085   */
00086 /**
00087   * @}
00088   */
00089 #endif /*USE_FULL_LL_DRIVER*/
00090
00091 /* Exported types ------------------------------------------------------------*/
00092 #if defined(USE_FULL_LL_DRIVER)
00093 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00094   * @{
00095   */
00096 typedef struct
00097 {
00098   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00099                                         or as Source base address in case of memory to memory transfer direction.
00100
00101                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00102
00103   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00104                                         or as Destination base address in case of memory to memory transfer direction.
00105
00106                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00107
00108   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00109                                         from memory to memory or from peripheral to memory.
00110                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00111
00112                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00113
00114   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00115                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00116                                         @note: The circular buffer mode cannot be used if the memory to memory
00117                                                data transfer direction is configured on the selected Channel
00118
00119                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00120
00121   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00122                                         is incremented or not.
00123                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00124
00125                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00126
00127   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00128                                         is incremented or not.
00129                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00130
00131                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00132
00133   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00134                                         in case of memory to memory transfer direction.
00135                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00136
00137                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00138
00139   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00140                                         in case of memory to memory transfer direction.
00141                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00142
00143                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00144
00145   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00146                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00147                                         or MemorySize parameters depending in the transfer direction.
00148                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00149
00150                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00151
00152   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00153                                         This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
00154
00155                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
00156
00157   uint32_t Priority;               /*!< Specifies the channel priority level.
00158                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00159
00160                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00161
00162 } LL_DMA_InitTypeDef;
00163 /**
00164   * @}
00165   */
00166 #endif /*USE_FULL_LL_DRIVER*/
00167
00168 /* Exported constants --------------------------------------------------------*/
00169 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00170   * @{
00171   */
00172 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00173   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00174   * @{
00175   */
00176 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00177 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00178 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00179 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00180 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00181 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00182 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00183 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00184 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00185 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00186 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00187 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00188 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00189 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00190 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00191 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00192 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00193 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00194 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00195 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00196 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00197 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00198 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00199 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00200 #if defined (DMA1_Channel7)
00201 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00202 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00203 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00204 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00205 #endif /* DMA1_Channel7 */
00206 #if defined (DMA1_Channel8)
00207 #define LL_DMA_IFCR_CGIF8                 DMA_IFCR_CGIF8        /*!< Channel 8 global flag            */
00208 #define LL_DMA_IFCR_CTCIF8                DMA_IFCR_CTCIF8       /*!< Channel 8 transfer complete flag */
00209 #define LL_DMA_IFCR_CHTIF8                DMA_IFCR_CHTIF8       /*!< Channel 8 half transfer flag     */
00210 #define LL_DMA_IFCR_CTEIF8                DMA_IFCR_CTEIF8       /*!< Channel 8 transfer error flag    */
00211 #endif /* DMA1_Channel8 */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00217   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00218   * @{
00219   */
00220 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00221 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00222 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00223 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00224 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00225 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00226 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00227 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00228 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00229 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00230 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00231 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00232 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00233 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00234 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00235 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00236 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00237 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00238 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00239 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00240 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00241 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00242 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00243 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00244 #if defined (DMA1_Channel7)
00245 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00246 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00247 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00248 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00249 #endif /* DMA1_Channel7 */
00250 #if defined (DMA1_Channel8)
00251 #define LL_DMA_ISR_GIF8                   DMA_ISR_GIF8          /*!< Channel 8 global flag            */
00252 #define LL_DMA_ISR_TCIF8                  DMA_ISR_TCIF8         /*!< Channel 8 transfer complete flag */
00253 #define LL_DMA_ISR_HTIF8                  DMA_ISR_HTIF8         /*!< Channel 8 half transfer flag     */
00254 #define LL_DMA_ISR_TEIF8                  DMA_ISR_TEIF8         /*!< Channel 8 transfer error flag    */
00255 #endif /* DMA1_Channel8 */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup DMA_LL_EC_IT IT Defines
00261   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00262   * @{
00263   */
00264 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00265 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00266 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00272   * @{
00273   */
00274 #define LL_DMA_CHANNEL_1                  0x00000000U /*!< DMA Channel 1 */
00275 #define LL_DMA_CHANNEL_2                  0x00000001U /*!< DMA Channel 2 */
00276 #define LL_DMA_CHANNEL_3                  0x00000002U /*!< DMA Channel 3 */
00277 #define LL_DMA_CHANNEL_4                  0x00000003U /*!< DMA Channel 4 */
00278 #define LL_DMA_CHANNEL_5                  0x00000004U /*!< DMA Channel 5 */
00279 #define LL_DMA_CHANNEL_6                  0x00000005U /*!< DMA Channel 6 */
00280 #if defined (DMA1_Channel7)
00281 #define LL_DMA_CHANNEL_7                  0x00000006U /*!< DMA Channel 7 */
00282 #endif /* DMA1_Channel7 */
00283 #if defined (DMA1_Channel8)
00284 #define LL_DMA_CHANNEL_8                  0x00000007U /*!< DMA Channel 8 */
00285 #endif /* DMA1_Channel8 */
00286 #if defined(USE_FULL_LL_DRIVER)
00287 #define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00288 #endif /*USE_FULL_LL_DRIVER*/
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00294   * @{
00295   */
00296 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
00297 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00298 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup DMA_LL_EC_MODE Transfer mode
00304   * @{
00305   */
00306 #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
00307 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00313   * @{
00314   */
00315 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00316 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00322   * @{
00323   */
00324 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00325 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00331   * @{
00332   */
00333 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
00334 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00335 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00341   * @{
00342   */
00343 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
00344 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00345 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00351   * @{
00352   */
00353 #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
00354 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00355 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00356 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macro ------------------------------------------------------------*/
00366 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00367   * @{
00368   */
00369
00370 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00371   * @{
00372   */
00373 /**
00374   * @brief  Write a value in DMA register
00375   * @param  __INSTANCE__ DMA Instance
00376   * @param  __REG__ Register to be written
00377   * @param  __VALUE__ Value to be written in the register
00378   * @retval None
00379   */
00380 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00381
00382 /**
00383   * @brief  Read a value in DMA register
00384   * @param  __INSTANCE__ DMA Instance
00385   * @param  __REG__ Register to be read
00386   * @retval Register value
00387   */
00388 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00394   * @{
00395   */
00396 /**
00397   * @brief  Convert DMAx_Channely into DMAx
00398   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00399   * @retval DMAx
00400   */
00401 #if defined (DMA1_Channel8)
00402 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00403   (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ?  DMA2 : DMA1)
00404 #else
00405 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00406   (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ?  DMA2 : DMA1)
00407 #endif /* DMA1_Channel8 */
00408 /**
00409   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00410   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00411   * @retval LL_DMA_CHANNEL_y
00412   */
00413 #if defined (DMA1_Channel8)
00414 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00415   (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00416    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00417    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00418    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00419    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00420    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00421    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00422    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00423    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00424    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00425    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00426    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
00427    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
00428    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
00429    LL_DMA_CHANNEL_8)
00430 #else
00431 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00432   (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00433    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00434    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00435    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00436    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00437    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00438    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00439    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00440    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00441    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00442    LL_DMA_CHANNEL_6)
00443 #endif /* DMA1_Channel8 */
00444
00445 /**
00446   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00447   * @param  __DMA_INSTANCE__ DMAx
00448   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00449   * @retval DMAx_Channely
00450   */
00451 #if defined (DMA1_Channel8)
00452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00453   ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00454    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00455    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00456    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00457    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00458    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00459    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00460    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00461    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00462    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00463    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00464    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
00465    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
00466    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
00467    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
00468    DMA2_Channel8)
00469 #else
00470 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00471   ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00472    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00473    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00474    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00475    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00476    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00477    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00478    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00479    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00480    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00481    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00482    DMA2_Channel6)
00483 #endif /* DMA1_Channel8 */
00484
00485 /**
00486   * @}
00487   */
00488
00489 /**
00490   * @}
00491   */
00492
00493 /* Exported functions --------------------------------------------------------*/
00494 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00495   * @{
00496   */
00497
00498 /** @defgroup DMA_LL_EF_Configuration Configuration
00499   * @{
00500   */
00501 /**
00502   * @brief  Enable DMA channel.
00503   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00504   * @param  DMAx DMAx Instance
00505   * @param  Channel This parameter can be one of the following values:
00506   *         @arg @ref LL_DMA_CHANNEL_1
00507   *         @arg @ref LL_DMA_CHANNEL_2
00508   *         @arg @ref LL_DMA_CHANNEL_3
00509   *         @arg @ref LL_DMA_CHANNEL_4
00510   *         @arg @ref LL_DMA_CHANNEL_5
00511   *         @arg @ref LL_DMA_CHANNEL_6
00512   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00513   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00514   *         (*) Not on all G4 devices
00515   * @retval None
00516   */
00517 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00518 {
00519   uint32_t dma_base_addr = (uint32_t)DMAx;
00520   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
00521 }
00522
00523 /**
00524   * @brief  Disable DMA channel.
00525   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00526   * @param  DMAx DMAx Instance
00527   * @param  Channel This parameter can be one of the following values:
00528   *         @arg @ref LL_DMA_CHANNEL_1
00529   *         @arg @ref LL_DMA_CHANNEL_2
00530   *         @arg @ref LL_DMA_CHANNEL_3
00531   *         @arg @ref LL_DMA_CHANNEL_4
00532   *         @arg @ref LL_DMA_CHANNEL_5
00533   *         @arg @ref LL_DMA_CHANNEL_6
00534   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00535   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00536   *         (*) Not on all G4 devices
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00540 {
00541   uint32_t dma_base_addr = (uint32_t)DMAx;
00542   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
00543 }
00544
00545 /**
00546   * @brief  Check if DMA channel is enabled or disabled.
00547   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00548   * @param  DMAx DMAx Instance
00549   * @param  Channel This parameter can be one of the following values:
00550   *         @arg @ref LL_DMA_CHANNEL_1
00551   *         @arg @ref LL_DMA_CHANNEL_2
00552   *         @arg @ref LL_DMA_CHANNEL_3
00553   *         @arg @ref LL_DMA_CHANNEL_4
00554   *         @arg @ref LL_DMA_CHANNEL_5
00555   *         @arg @ref LL_DMA_CHANNEL_6
00556   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00557   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00558   *         (*) Not on all G4 devices
00559   * @retval State of bit (1 or 0).
00560   */
00561 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00562 {
00563   uint32_t dma_base_addr = (uint32_t)DMAx;
00564   return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00565                     DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
00566 }
00567
00568 /**
00569   * @brief  Configure all parameters link to DMA transfer.
00570   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00571   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00572   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00573   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00574   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00575   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00576   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00577   *         CCR          PL            LL_DMA_ConfigTransfer
00578   * @param  DMAx DMAx Instance
00579   * @param  Channel This parameter can be one of the following values:
00580   *         @arg @ref LL_DMA_CHANNEL_1
00581   *         @arg @ref LL_DMA_CHANNEL_2
00582   *         @arg @ref LL_DMA_CHANNEL_3
00583   *         @arg @ref LL_DMA_CHANNEL_4
00584   *         @arg @ref LL_DMA_CHANNEL_5
00585   *         @arg @ref LL_DMA_CHANNEL_6
00586   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00587   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00588   *         (*) Not on all G4 devices
00589   * @param  Configuration This parameter must be a combination of all the following values:
00590   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00591   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00592   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00593   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00594   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00595   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00596   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00597   * @retval None
00598   */
00599 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00600 {
00601   uint32_t dma_base_addr = (uint32_t)DMAx;
00602   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00603              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00604              Configuration);
00605 }
00606
00607 /**
00608   * @brief  Set Data transfer direction (read from peripheral or from memory).
00609   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00610   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00611   * @param  DMAx DMAx Instance
00612   * @param  Channel This parameter can be one of the following values:
00613   *         @arg @ref LL_DMA_CHANNEL_1
00614   *         @arg @ref LL_DMA_CHANNEL_2
00615   *         @arg @ref LL_DMA_CHANNEL_3
00616   *         @arg @ref LL_DMA_CHANNEL_4
00617   *         @arg @ref LL_DMA_CHANNEL_5
00618   *         @arg @ref LL_DMA_CHANNEL_6
00619   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00620   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00621   *         (*) Not on all G4 devices
00622   * @param  Direction This parameter can be one of the following values:
00623   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00624   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00625   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00626   * @retval None
00627   */
00628 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00629 {
00630   uint32_t dma_base_addr = (uint32_t)DMAx;
00631   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00632              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00633 }
00634
00635 /**
00636   * @brief  Get Data transfer direction (read from peripheral or from memory).
00637   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00638   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00639   * @param  DMAx DMAx Instance
00640   * @param  Channel This parameter can be one of the following values:
00641   *         @arg @ref LL_DMA_CHANNEL_1
00642   *         @arg @ref LL_DMA_CHANNEL_2
00643   *         @arg @ref LL_DMA_CHANNEL_3
00644   *         @arg @ref LL_DMA_CHANNEL_4
00645   *         @arg @ref LL_DMA_CHANNEL_5
00646   *         @arg @ref LL_DMA_CHANNEL_6
00647   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00648   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00649   *         (*) Not on all G4 devices
00650   * @retval Returned value can be one of the following values:
00651   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00652   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00653   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00654   */
00655 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00656 {
00657   uint32_t dma_base_addr = (uint32_t)DMAx;
00658   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00659                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00660 }
00661
00662 /**
00663   * @brief  Set DMA mode circular or normal.
00664   * @note The circular buffer mode cannot be used if the memory-to-memory
00665   * data transfer is configured on the selected Channel.
00666   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00667   * @param  DMAx DMAx Instance
00668   * @param  Channel This parameter can be one of the following values:
00669   *         @arg @ref LL_DMA_CHANNEL_1
00670   *         @arg @ref LL_DMA_CHANNEL_2
00671   *         @arg @ref LL_DMA_CHANNEL_3
00672   *         @arg @ref LL_DMA_CHANNEL_4
00673   *         @arg @ref LL_DMA_CHANNEL_5
00674   *         @arg @ref LL_DMA_CHANNEL_6
00675   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00676   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00677   *         (*) Not on all G4 devices
00678   * @param  Mode This parameter can be one of the following values:
00679   *         @arg @ref LL_DMA_MODE_NORMAL
00680   *         @arg @ref LL_DMA_MODE_CIRCULAR
00681   * @retval None
00682   */
00683 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00684 {
00685   uint32_t dma_base_addr = (uint32_t)DMAx;
00686   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC,
00687              Mode);
00688 }
00689
00690 /**
00691   * @brief  Get DMA mode circular or normal.
00692   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00693   * @param  DMAx DMAx Instance
00694   * @param  Channel This parameter can be one of the following values:
00695   *         @arg @ref LL_DMA_CHANNEL_1
00696   *         @arg @ref LL_DMA_CHANNEL_2
00697   *         @arg @ref LL_DMA_CHANNEL_3
00698   *         @arg @ref LL_DMA_CHANNEL_4
00699   *         @arg @ref LL_DMA_CHANNEL_5
00700   *         @arg @ref LL_DMA_CHANNEL_6
00701   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00702   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00703   *         (*) Not on all G4 devices
00704   * @retval Returned value can be one of the following values:
00705   *         @arg @ref LL_DMA_MODE_NORMAL
00706   *         @arg @ref LL_DMA_MODE_CIRCULAR
00707   */
00708 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00709 {
00710   uint32_t dma_base_addr = (uint32_t)DMAx;
00711   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00712                    DMA_CCR_CIRC));
00713 }
00714
00715 /**
00716   * @brief  Set Peripheral increment mode.
00717   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00718   * @param  DMAx DMAx Instance
00719   * @param  Channel This parameter can be one of the following values:
00720   *         @arg @ref LL_DMA_CHANNEL_1
00721   *         @arg @ref LL_DMA_CHANNEL_2
00722   *         @arg @ref LL_DMA_CHANNEL_3
00723   *         @arg @ref LL_DMA_CHANNEL_4
00724   *         @arg @ref LL_DMA_CHANNEL_5
00725   *         @arg @ref LL_DMA_CHANNEL_6
00726   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00727   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00728   *         (*) Not on all G4 devices
00729   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00730   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00731   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00732   * @retval None
00733   */
00734 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00735 {
00736   uint32_t dma_base_addr = (uint32_t)DMAx;
00737   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC,
00738              PeriphOrM2MSrcIncMode);
00739 }
00740
00741 /**
00742   * @brief  Get Peripheral increment mode.
00743   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00744   * @param  DMAx DMAx Instance
00745   * @param  Channel This parameter can be one of the following values:
00746   *         @arg @ref LL_DMA_CHANNEL_1
00747   *         @arg @ref LL_DMA_CHANNEL_2
00748   *         @arg @ref LL_DMA_CHANNEL_3
00749   *         @arg @ref LL_DMA_CHANNEL_4
00750   *         @arg @ref LL_DMA_CHANNEL_5
00751   *         @arg @ref LL_DMA_CHANNEL_6
00752   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00753   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00754   *         (*) Not on all G4 devices
00755   * @retval Returned value can be one of the following values:
00756   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00757   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00758   */
00759 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00760 {
00761   uint32_t dma_base_addr = (uint32_t)DMAx;
00762   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00763                    DMA_CCR_PINC));
00764 }
00765
00766 /**
00767   * @brief  Set Memory increment mode.
00768   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00769   * @param  DMAx DMAx Instance
00770   * @param  Channel This parameter can be one of the following values:
00771   *         @arg @ref LL_DMA_CHANNEL_1
00772   *         @arg @ref LL_DMA_CHANNEL_2
00773   *         @arg @ref LL_DMA_CHANNEL_3
00774   *         @arg @ref LL_DMA_CHANNEL_4
00775   *         @arg @ref LL_DMA_CHANNEL_5
00776   *         @arg @ref LL_DMA_CHANNEL_6
00777   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00778   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00779   *         (*) Not on all G4 devices
00780   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00781   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00782   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00783   * @retval None
00784   */
00785 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00786 {
00787   uint32_t dma_base_addr = (uint32_t)DMAx;
00788   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC,
00789              MemoryOrM2MDstIncMode);
00790 }
00791
00792 /**
00793   * @brief  Get Memory increment mode.
00794   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00795   * @param  DMAx DMAx Instance
00796   * @param  Channel This parameter can be one of the following values:
00797   *         @arg @ref LL_DMA_CHANNEL_1
00798   *         @arg @ref LL_DMA_CHANNEL_2
00799   *         @arg @ref LL_DMA_CHANNEL_3
00800   *         @arg @ref LL_DMA_CHANNEL_4
00801   *         @arg @ref LL_DMA_CHANNEL_5
00802   *         @arg @ref LL_DMA_CHANNEL_6
00803   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00804   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00805   *         (*) Not on all G4 devices
00806   * @retval Returned value can be one of the following values:
00807   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00808   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00809   */
00810 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00811 {
00812   uint32_t dma_base_addr = (uint32_t)DMAx;
00813   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00814                    DMA_CCR_MINC));
00815 }
00816
00817 /**
00818   * @brief  Set Peripheral size.
00819   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00820   * @param  DMAx DMAx Instance
00821   * @param  Channel This parameter can be one of the following values:
00822   *         @arg @ref LL_DMA_CHANNEL_1
00823   *         @arg @ref LL_DMA_CHANNEL_2
00824   *         @arg @ref LL_DMA_CHANNEL_3
00825   *         @arg @ref LL_DMA_CHANNEL_4
00826   *         @arg @ref LL_DMA_CHANNEL_5
00827   *         @arg @ref LL_DMA_CHANNEL_6
00828   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00829   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00830   *         (*) Not on all G4 devices
00831   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00832   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00833   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00834   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00838 {
00839   uint32_t dma_base_addr = (uint32_t)DMAx;
00840   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE,
00841              PeriphOrM2MSrcDataSize);
00842 }
00843
00844 /**
00845   * @brief  Get Peripheral size.
00846   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00847   * @param  DMAx DMAx Instance
00848   * @param  Channel This parameter can be one of the following values:
00849   *         @arg @ref LL_DMA_CHANNEL_1
00850   *         @arg @ref LL_DMA_CHANNEL_2
00851   *         @arg @ref LL_DMA_CHANNEL_3
00852   *         @arg @ref LL_DMA_CHANNEL_4
00853   *         @arg @ref LL_DMA_CHANNEL_5
00854   *         @arg @ref LL_DMA_CHANNEL_6
00855   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00856   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00857   *         (*) Not on all G4 devices
00858   * @retval Returned value can be one of the following values:
00859   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00860   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00861   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00862   */
00863 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00864 {
00865   uint32_t dma_base_addr = (uint32_t)DMAx;
00866   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00867                    DMA_CCR_PSIZE));
00868 }
00869
00870 /**
00871   * @brief  Set Memory size.
00872   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00873   * @param  DMAx DMAx Instance
00874   * @param  Channel This parameter can be one of the following values:
00875   *         @arg @ref LL_DMA_CHANNEL_1
00876   *         @arg @ref LL_DMA_CHANNEL_2
00877   *         @arg @ref LL_DMA_CHANNEL_3
00878   *         @arg @ref LL_DMA_CHANNEL_4
00879   *         @arg @ref LL_DMA_CHANNEL_5
00880   *         @arg @ref LL_DMA_CHANNEL_6
00881   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00882   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00883   *         (*) Not on all G4 devices
00884   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00885   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00886   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00887   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00891 {
00892   uint32_t dma_base_addr = (uint32_t)DMAx;
00893   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE,
00894              MemoryOrM2MDstDataSize);
00895 }
00896
00897 /**
00898   * @brief  Get Memory size.
00899   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00900   * @param  DMAx DMAx Instance
00901   * @param  Channel This parameter can be one of the following values:
00902   *         @arg @ref LL_DMA_CHANNEL_1
00903   *         @arg @ref LL_DMA_CHANNEL_2
00904   *         @arg @ref LL_DMA_CHANNEL_3
00905   *         @arg @ref LL_DMA_CHANNEL_4
00906   *         @arg @ref LL_DMA_CHANNEL_5
00907   *         @arg @ref LL_DMA_CHANNEL_6
00908   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00909   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00910   *         (*) Not on all G4 devices
00911   * @retval Returned value can be one of the following values:
00912   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00913   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00914   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00915   */
00916 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00917 {
00918   uint32_t dma_base_addr = (uint32_t)DMAx;
00919   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00920                    DMA_CCR_MSIZE));
00921 }
00922
00923 /**
00924   * @brief  Set Channel priority level.
00925   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00926   * @param  DMAx DMAx Instance
00927   * @param  Channel This parameter can be one of the following values:
00928   *         @arg @ref LL_DMA_CHANNEL_1
00929   *         @arg @ref LL_DMA_CHANNEL_2
00930   *         @arg @ref LL_DMA_CHANNEL_3
00931   *         @arg @ref LL_DMA_CHANNEL_4
00932   *         @arg @ref LL_DMA_CHANNEL_5
00933   *         @arg @ref LL_DMA_CHANNEL_6
00934   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00935   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00936   *         (*) Not on all G4 devices
00937   * @param  Priority This parameter can be one of the following values:
00938   *         @arg @ref LL_DMA_PRIORITY_LOW
00939   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00940   *         @arg @ref LL_DMA_PRIORITY_HIGH
00941   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00945 {
00946   uint32_t dma_base_addr = (uint32_t)DMAx;
00947   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL,
00948              Priority);
00949 }
00950
00951 /**
00952   * @brief  Get Channel priority level.
00953   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00954   * @param  DMAx DMAx Instance
00955   * @param  Channel This parameter can be one of the following values:
00956   *         @arg @ref LL_DMA_CHANNEL_1
00957   *         @arg @ref LL_DMA_CHANNEL_2
00958   *         @arg @ref LL_DMA_CHANNEL_3
00959   *         @arg @ref LL_DMA_CHANNEL_4
00960   *         @arg @ref LL_DMA_CHANNEL_5
00961   *         @arg @ref LL_DMA_CHANNEL_6
00962   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00963   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00964   *         (*) Not on all G4 devices
00965   * @retval Returned value can be one of the following values:
00966   *         @arg @ref LL_DMA_PRIORITY_LOW
00967   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00968   *         @arg @ref LL_DMA_PRIORITY_HIGH
00969   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00970   */
00971 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00972 {
00973   uint32_t dma_base_addr = (uint32_t)DMAx;
00974   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
00975                    DMA_CCR_PL));
00976 }
00977
00978 /**
00979   * @brief  Set Number of data to transfer.
00980   * @note   This action has no effect if
00981   *         channel is enabled.
00982   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00983   * @param  DMAx DMAx Instance
00984   * @param  Channel This parameter can be one of the following values:
00985   *         @arg @ref LL_DMA_CHANNEL_1
00986   *         @arg @ref LL_DMA_CHANNEL_2
00987   *         @arg @ref LL_DMA_CHANNEL_3
00988   *         @arg @ref LL_DMA_CHANNEL_4
00989   *         @arg @ref LL_DMA_CHANNEL_5
00990   *         @arg @ref LL_DMA_CHANNEL_6
00991   *         @arg @ref LL_DMA_CHANNEL_7 (*)
00992   *         @arg @ref LL_DMA_CHANNEL_8 (*)
00993   *         (*) Not on all G4 devices
00994   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00995   * @retval None
00996   */
00997 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00998 {
00999   uint32_t dma_base_addr = (uint32_t)DMAx;
01000   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
01001              DMA_CNDTR_NDT, NbData);
01002 }
01003
01004 /**
01005   * @brief  Get Number of data to transfer.
01006   * @note   Once the channel is enabled, the return value indicate the
01007   *         remaining bytes to be transmitted.
01008   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
01009   * @param  DMAx DMAx Instance
01010   * @param  Channel This parameter can be one of the following values:
01011   *         @arg @ref LL_DMA_CHANNEL_1
01012   *         @arg @ref LL_DMA_CHANNEL_2
01013   *         @arg @ref LL_DMA_CHANNEL_3
01014   *         @arg @ref LL_DMA_CHANNEL_4
01015   *         @arg @ref LL_DMA_CHANNEL_5
01016   *         @arg @ref LL_DMA_CHANNEL_6
01017   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01018   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01019   *         (*) Not on all G4 devices
01020   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01021   */
01022 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
01023 {
01024   uint32_t dma_base_addr = (uint32_t)DMAx;
01025   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
01026                    DMA_CNDTR_NDT));
01027 }
01028
01029 /**
01030   * @brief  Configure the Source and Destination addresses.
01031   * @note   This API must not be called when the DMA channel is enabled.
01032   * @note   Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
01033   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
01034   *         CMAR         MA            LL_DMA_ConfigAddresses
01035   * @param  DMAx DMAx Instance
01036   * @param  Channel This parameter can be one of the following values:
01037   *         @arg @ref LL_DMA_CHANNEL_1
01038   *         @arg @ref LL_DMA_CHANNEL_2
01039   *         @arg @ref LL_DMA_CHANNEL_3
01040   *         @arg @ref LL_DMA_CHANNEL_4
01041   *         @arg @ref LL_DMA_CHANNEL_5
01042   *         @arg @ref LL_DMA_CHANNEL_6
01043   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01044   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01045   *         (*) Not on all G4 devices
01046   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01047   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01048   * @param  Direction This parameter can be one of the following values:
01049   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
01050   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
01051   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
01052   * @retval None
01053   */
01054 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
01055                                             uint32_t DstAddress, uint32_t Direction)
01056 {
01057   uint32_t dma_base_addr = (uint32_t)DMAx;
01058
01059   /* Direction Memory to Periph */
01060   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
01061   {
01062     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress);
01063     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress);
01064   }
01065   /* Direction Periph to Memory and Memory to Memory */
01066   else
01067   {
01068     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress);
01069     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress);
01070   }
01071 }
01072
01073 /**
01074   * @brief  Set the Memory address.
01075   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01076   * @note   This API must not be called when the DMA channel is enabled.
01077   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
01078   * @param  DMAx DMAx Instance
01079   * @param  Channel This parameter can be one of the following values:
01080   *         @arg @ref LL_DMA_CHANNEL_1
01081   *         @arg @ref LL_DMA_CHANNEL_2
01082   *         @arg @ref LL_DMA_CHANNEL_3
01083   *         @arg @ref LL_DMA_CHANNEL_4
01084   *         @arg @ref LL_DMA_CHANNEL_5
01085   *         @arg @ref LL_DMA_CHANNEL_6
01086   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01087   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01088   *         (*) Not on all G4 devices
01089   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01090   * @retval None
01091   */
01092 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01093 {
01094   uint32_t dma_base_addr = (uint32_t)DMAx;
01095   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
01096 }
01097
01098 /**
01099   * @brief  Set the Peripheral address.
01100   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01101   * @note   This API must not be called when the DMA channel is enabled.
01102   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
01103   * @param  DMAx DMAx Instance
01104   * @param  Channel This parameter can be one of the following values:
01105   *         @arg @ref LL_DMA_CHANNEL_1
01106   *         @arg @ref LL_DMA_CHANNEL_2
01107   *         @arg @ref LL_DMA_CHANNEL_3
01108   *         @arg @ref LL_DMA_CHANNEL_4
01109   *         @arg @ref LL_DMA_CHANNEL_5
01110   *         @arg @ref LL_DMA_CHANNEL_6
01111   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01112   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01113   *         (*) Not on all G4 devices
01114   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01115   * @retval None
01116   */
01117 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01118 {
01119   uint32_t dma_base_addr = (uint32_t)DMAx;
01120   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress);
01121 }
01122
01123 /**
01124   * @brief  Get Memory address.
01125   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01126   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01127   * @param  DMAx DMAx Instance
01128   * @param  Channel This parameter can be one of the following values:
01129   *         @arg @ref LL_DMA_CHANNEL_1
01130   *         @arg @ref LL_DMA_CHANNEL_2
01131   *         @arg @ref LL_DMA_CHANNEL_3
01132   *         @arg @ref LL_DMA_CHANNEL_4
01133   *         @arg @ref LL_DMA_CHANNEL_5
01134   *         @arg @ref LL_DMA_CHANNEL_6
01135   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01136   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01137   *         (*) Not on all G4 devices
01138   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01139   */
01140 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01141 {
01142   uint32_t dma_base_addr = (uint32_t)DMAx;
01143   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
01144 }
01145
01146 /**
01147   * @brief  Get Peripheral address.
01148   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01149   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01150   * @param  DMAx DMAx Instance
01151   * @param  Channel This parameter can be one of the following values:
01152   *         @arg @ref LL_DMA_CHANNEL_1
01153   *         @arg @ref LL_DMA_CHANNEL_2
01154   *         @arg @ref LL_DMA_CHANNEL_3
01155   *         @arg @ref LL_DMA_CHANNEL_4
01156   *         @arg @ref LL_DMA_CHANNEL_5
01157   *         @arg @ref LL_DMA_CHANNEL_6
01158   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01159   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01160   *         (*) Not on all G4 devices
01161   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01162   */
01163 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01164 {
01165   uint32_t dma_base_addr = (uint32_t)DMAx;
01166   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
01167 }
01168
01169 /**
01170   * @brief  Set the Memory to Memory Source address.
01171   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01172   * @note   This API must not be called when the DMA channel is enabled.
01173   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01174   * @param  DMAx DMAx Instance
01175   * @param  Channel This parameter can be one of the following values:
01176   *         @arg @ref LL_DMA_CHANNEL_1
01177   *         @arg @ref LL_DMA_CHANNEL_2
01178   *         @arg @ref LL_DMA_CHANNEL_3
01179   *         @arg @ref LL_DMA_CHANNEL_4
01180   *         @arg @ref LL_DMA_CHANNEL_5
01181   *         @arg @ref LL_DMA_CHANNEL_6
01182   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01183   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01184   *         (*) Not on all G4 devices
01185   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01186   * @retval None
01187   */
01188 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01189 {
01190   uint32_t dma_base_addr = (uint32_t)DMAx;
01191   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress);
01192 }
01193
01194 /**
01195   * @brief  Set the Memory to Memory Destination address.
01196   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01197   * @note   This API must not be called when the DMA channel is enabled.
01198   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01199   * @param  DMAx DMAx Instance
01200   * @param  Channel This parameter can be one of the following values:
01201   *         @arg @ref LL_DMA_CHANNEL_1
01202   *         @arg @ref LL_DMA_CHANNEL_2
01203   *         @arg @ref LL_DMA_CHANNEL_3
01204   *         @arg @ref LL_DMA_CHANNEL_4
01205   *         @arg @ref LL_DMA_CHANNEL_5
01206   *         @arg @ref LL_DMA_CHANNEL_6
01207   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01208   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01209   *         (*) Not on all G4 devices
01210   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01211   * @retval None
01212   */
01213 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01214 {
01215   uint32_t dma_base_addr = (uint32_t)DMAx;
01216   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
01217 }
01218
01219 /**
01220   * @brief  Get the Memory to Memory Source address.
01221   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01222   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01223   * @param  DMAx DMAx Instance
01224   * @param  Channel This parameter can be one of the following values:
01225   *         @arg @ref LL_DMA_CHANNEL_1
01226   *         @arg @ref LL_DMA_CHANNEL_2
01227   *         @arg @ref LL_DMA_CHANNEL_3
01228   *         @arg @ref LL_DMA_CHANNEL_4
01229   *         @arg @ref LL_DMA_CHANNEL_5
01230   *         @arg @ref LL_DMA_CHANNEL_6
01231   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01232   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01233   *         (*) Not on all G4 devices
01234   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01235   */
01236 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01237 {
01238   uint32_t dma_base_addr = (uint32_t)DMAx;
01239   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
01240 }
01241
01242 /**
01243   * @brief  Get the Memory to Memory Destination address.
01244   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01245   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01246   * @param  DMAx DMAx Instance
01247   * @param  Channel This parameter can be one of the following values:
01248   *         @arg @ref LL_DMA_CHANNEL_1
01249   *         @arg @ref LL_DMA_CHANNEL_2
01250   *         @arg @ref LL_DMA_CHANNEL_3
01251   *         @arg @ref LL_DMA_CHANNEL_4
01252   *         @arg @ref LL_DMA_CHANNEL_5
01253   *         @arg @ref LL_DMA_CHANNEL_6
01254   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01255   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01256   *         (*) Not on all G4 devices
01257   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01258   */
01259 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01260 {
01261   uint32_t dma_base_addr = (uint32_t)DMAx;
01262   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
01263 }
01264
01265 /**
01266   * @brief  Set DMA request for DMA instance on Channel x.
01267   * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
01268   * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
01269   *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
01270   *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
01271   *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
01272   *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
01273   *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
01274   *         CSELR        C7S           LL_DMA_SetPeriphRequest
01275   * @param  DMAx DMAx Instance
01276   * @param  Channel This parameter can be one of the following values:
01277   *         @arg @ref LL_DMA_CHANNEL_1
01278   *         @arg @ref LL_DMA_CHANNEL_2
01279   *         @arg @ref LL_DMA_CHANNEL_3
01280   *         @arg @ref LL_DMA_CHANNEL_4
01281   *         @arg @ref LL_DMA_CHANNEL_5
01282   *         @arg @ref LL_DMA_CHANNEL_6
01283   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01284   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01285   *         (*) Not on all G4 devices
01286   * @param  PeriphRequest This parameter can be one of the following values:
01287   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01288   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01289   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01290   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01291   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01292   *         @arg @ref LL_DMAMUX_REQ_ADC1
01293   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
01294   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
01295   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
01296   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
01297   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01298   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01299   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01300   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01301   *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
01302   *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
01303   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01304   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01305   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
01306   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
01307   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
01308   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
01309   *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
01310   *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
01311   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01312   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01313   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
01314   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
01315   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
01316   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
01317   *         @arg @ref LL_DMAMUX_REQ_UART4_RX
01318   *         @arg @ref LL_DMAMUX_REQ_UART4_TX
01319   *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
01320   *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
01321   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01322   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01323   *         @arg @ref LL_DMAMUX_REQ_ADC2
01324   *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
01325   *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
01326   *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
01327   *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
01328   *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
01329   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01330   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01331   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01332   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01333   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01334   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
01335   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
01336   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
01337   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
01338   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
01339   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
01340   *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
01341   *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
01342   *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
01343   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01344   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01345   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01346   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01347   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01348   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
01349   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
01350   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
01351   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
01352   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
01353   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
01354   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
01355   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
01356   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
01357   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
01358   *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
01359   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
01360   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
01361   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
01362   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
01363   *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
01364   *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
01365   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
01366   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
01367   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
01368   *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
01369   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01370   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01371   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01372   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01373   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
01374   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
01375   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
01376   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
01377   *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
01378   *         @arg @ref LL_DMAMUX_REQ_AES_IN
01379   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
01380   *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
01381   *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
01382   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
01383   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
01384   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
01385   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
01386   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
01387   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
01388   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
01389   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
01390   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
01391   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
01392   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
01393   *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
01394   *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
01395   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
01396   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
01397   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
01398   *         @arg @ref LL_DMAMUX_REQ_FMAC_READ
01399   *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
01400   *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
01401   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
01402   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
01403   *         (*) Not on all G4 devices
01404   * @retval None
01405   */
01406 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
01407 {
01408   uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
01409   MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
01410 }
01411
01412 /**
01413   * @brief  Get DMA request for DMA instance on Channel x.
01414   * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
01415   *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
01416   *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
01417   *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
01418   *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
01419   *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
01420   *         CSELR        C7S           LL_DMA_GetPeriphRequest
01421   * @param  DMAx DMAx Instance
01422   * @param  Channel This parameter can be one of the following values:
01423   *         @arg @ref LL_DMA_CHANNEL_1
01424   *         @arg @ref LL_DMA_CHANNEL_2
01425   *         @arg @ref LL_DMA_CHANNEL_3
01426   *         @arg @ref LL_DMA_CHANNEL_4
01427   *         @arg @ref LL_DMA_CHANNEL_5
01428   *         @arg @ref LL_DMA_CHANNEL_6
01429   *         @arg @ref LL_DMA_CHANNEL_7 (*)
01430   *         @arg @ref LL_DMA_CHANNEL_8 (*)
01431   *         (*) Not on all G4 devices
01432   * @retval Returned value can be one of the following values:
01433   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01434   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01435   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01436   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01437   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01438   *         @arg @ref LL_DMAMUX_REQ_ADC1
01439   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
01440   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
01441   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
01442   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
01443   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01444   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01445   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01446   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01447   *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
01448   *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
01449   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01450   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01451   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
01452   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
01453   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
01454   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
01455   *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
01456   *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
01457   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01458   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01459   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
01460   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
01461   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
01462   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
01463   *         @arg @ref LL_DMAMUX_REQ_UART4_RX
01464   *         @arg @ref LL_DMAMUX_REQ_UART4_TX
01465   *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
01466   *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
01467   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01468   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01469   *         @arg @ref LL_DMAMUX_REQ_ADC2
01470   *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
01471   *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
01472   *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
01473   *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
01474   *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
01475   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01476   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01477   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01478   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01479   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01480   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
01481   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
01482   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
01483   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
01484   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
01485   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
01486   *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
01487   *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
01488   *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
01489   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01490   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01491   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01492   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01493   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01494   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
01495   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
01496   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
01497   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
01498   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
01499   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
01500   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
01501   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
01502   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
01503   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
01504   *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
01505   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
01506   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
01507   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
01508   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
01509   *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
01510   *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
01511   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
01512   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
01513   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
01514   *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
01515   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01516   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01517   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01518   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01519   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
01520   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
01521   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
01522   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
01523   *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
01524   *         @arg @ref LL_DMAMUX_REQ_AES_IN
01525   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
01526   *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
01527   *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
01528   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
01529   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
01530   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
01531   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
01532   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
01533   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
01534   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
01535   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
01536   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
01537   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
01538   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
01539   *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
01540   *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
01541   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
01542   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
01543   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
01544   *         @arg @ref LL_DMAMUX_REQ_FMAC_READ
01545   *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
01546   *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
01547   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
01548   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
01549   *         (*) Not on all G4 devices
01550   */
01551 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
01552 {
01553   uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
01554   return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
01555 }
01556
01557 /**
01558   * @}
01559   */
01560
01561 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01562   * @{
01563   */
01564
01565 /**
01566   * @brief  Get Channel 1 global interrupt flag.
01567   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01568   * @param  DMAx DMAx Instance
01569   * @retval State of bit (1 or 0).
01570   */
01571 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01572 {
01573   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
01574 }
01575
01576 /**
01577   * @brief  Get Channel 2 global interrupt flag.
01578   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01579   * @param  DMAx DMAx Instance
01580   * @retval State of bit (1 or 0).
01581   */
01582 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01583 {
01584   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
01585 }
01586
01587 /**
01588   * @brief  Get Channel 3 global interrupt flag.
01589   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01590   * @param  DMAx DMAx Instance
01591   * @retval State of bit (1 or 0).
01592   */
01593 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01594 {
01595   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
01596 }
01597
01598 /**
01599   * @brief  Get Channel 4 global interrupt flag.
01600   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01601   * @param  DMAx DMAx Instance
01602   * @retval State of bit (1 or 0).
01603   */
01604 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01605 {
01606   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
01607 }
01608
01609 /**
01610   * @brief  Get Channel 5 global interrupt flag.
01611   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01612   * @param  DMAx DMAx Instance
01613   * @retval State of bit (1 or 0).
01614   */
01615 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01616 {
01617   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
01618 }
01619
01620 /**
01621   * @brief  Get Channel 6 global interrupt flag.
01622   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01623   * @param  DMAx DMAx Instance
01624   * @retval State of bit (1 or 0).
01625   */
01626 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01627 {
01628   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
01629 }
01630
01631 #if defined (DMA1_Channel7)
01632 /**
01633   * @brief  Get Channel 7 global interrupt flag.
01634   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01635   * @param  DMAx DMAx Instance
01636   * @retval State of bit (1 or 0).
01637   */
01638 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01639 {
01640   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
01641 }
01642 #endif /* DMA1_Channel7 */
01643
01644 #if defined (DMA1_Channel8)
01645 /**
01646   * @brief  Get Channel 8 global interrupt flag.
01647   * @rmtoll ISR          GIF8          LL_DMA_IsActiveFlag_GI8
01648   * @param  DMAx DMAx Instance
01649   * @retval State of bit (1 or 0).
01650   */
01651 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
01652 {
01653   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
01654 }
01655 #endif /* DMA1_Channel8 */
01656
01657 /**
01658   * @brief  Get Channel 1 transfer complete flag.
01659   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01660   * @param  DMAx DMAx Instance
01661   * @retval State of bit (1 or 0).
01662   */
01663 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01664 {
01665   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
01666 }
01667
01668 /**
01669   * @brief  Get Channel 2 transfer complete flag.
01670   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01671   * @param  DMAx DMAx Instance
01672   * @retval State of bit (1 or 0).
01673   */
01674 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01675 {
01676   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
01677 }
01678
01679 /**
01680   * @brief  Get Channel 3 transfer complete flag.
01681   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01682   * @param  DMAx DMAx Instance
01683   * @retval State of bit (1 or 0).
01684   */
01685 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01686 {
01687   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
01688 }
01689
01690 /**
01691   * @brief  Get Channel 4 transfer complete flag.
01692   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01693   * @param  DMAx DMAx Instance
01694   * @retval State of bit (1 or 0).
01695   */
01696 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01697 {
01698   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
01699 }
01700
01701 /**
01702   * @brief  Get Channel 5 transfer complete flag.
01703   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01704   * @param  DMAx DMAx Instance
01705   * @retval State of bit (1 or 0).
01706   */
01707 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01708 {
01709   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
01710 }
01711
01712 /**
01713   * @brief  Get Channel 6 transfer complete flag.
01714   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01715   * @param  DMAx DMAx Instance
01716   * @retval State of bit (1 or 0).
01717   */
01718 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01719 {
01720   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
01721 }
01722
01723 #if defined (DMA1_Channel7)
01724 /**
01725   * @brief  Get Channel 7 transfer complete flag.
01726   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01727   * @param  DMAx DMAx Instance
01728   * @retval State of bit (1 or 0).
01729   */
01730 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01731 {
01732   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
01733 }
01734 #endif /* DMA1_Channel7 */
01735
01736 #if defined (DMA1_Channel8)
01737 /**
01738   * @brief  Get Channel 8 transfer complete flag.
01739   * @rmtoll ISR          TCIF8         LL_DMA_IsActiveFlag_TC8
01740   * @param  DMAx DMAx Instance
01741   * @retval State of bit (1 or 0).
01742   */
01743 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
01744 {
01745   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
01746 }
01747 #endif /* DMA1_Channel8 */
01748
01749 /**
01750   * @brief  Get Channel 1 half transfer flag.
01751   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01752   * @param  DMAx DMAx Instance
01753   * @retval State of bit (1 or 0).
01754   */
01755 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01756 {
01757   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
01758 }
01759
01760 /**
01761   * @brief  Get Channel 2 half transfer flag.
01762   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01763   * @param  DMAx DMAx Instance
01764   * @retval State of bit (1 or 0).
01765   */
01766 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01767 {
01768   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
01769 }
01770
01771 /**
01772   * @brief  Get Channel 3 half transfer flag.
01773   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01774   * @param  DMAx DMAx Instance
01775   * @retval State of bit (1 or 0).
01776   */
01777 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01778 {
01779   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
01780 }
01781
01782 /**
01783   * @brief  Get Channel 4 half transfer flag.
01784   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01785   * @param  DMAx DMAx Instance
01786   * @retval State of bit (1 or 0).
01787   */
01788 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01789 {
01790   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
01791 }
01792
01793 /**
01794   * @brief  Get Channel 5 half transfer flag.
01795   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01796   * @param  DMAx DMAx Instance
01797   * @retval State of bit (1 or 0).
01798   */
01799 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01800 {
01801   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
01802 }
01803
01804 /**
01805   * @brief  Get Channel 6 half transfer flag.
01806   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01807   * @param  DMAx DMAx Instance
01808   * @retval State of bit (1 or 0).
01809   */
01810 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01811 {
01812   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
01813 }
01814
01815 #if defined (DMA1_Channel8)
01816 /**
01817   * @brief  Get Channel 7 half transfer flag.
01818   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01819   * @param  DMAx DMAx Instance
01820   * @retval State of bit (1 or 0).
01821   */
01822 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01823 {
01824   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
01825 }
01826 #endif /* DMA1_Channel7 */
01827
01828 #if defined (DMA1_Channel8)
01829 /**
01830   * @brief  Get Channel 8 half transfer flag.
01831   * @rmtoll ISR          HTIF8         LL_DMA_IsActiveFlag_HT8
01832   * @param  DMAx DMAx Instance
01833   * @retval State of bit (1 or 0).
01834   */
01835 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
01836 {
01837   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
01838 }
01839 #endif /* DMA1_Channel8 */
01840
01841 /**
01842   * @brief  Get Channel 1 transfer error flag.
01843   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01844   * @param  DMAx DMAx Instance
01845   * @retval State of bit (1 or 0).
01846   */
01847 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01848 {
01849   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
01850 }
01851
01852 /**
01853   * @brief  Get Channel 2 transfer error flag.
01854   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01855   * @param  DMAx DMAx Instance
01856   * @retval State of bit (1 or 0).
01857   */
01858 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01859 {
01860   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
01861 }
01862
01863 /**
01864   * @brief  Get Channel 3 transfer error flag.
01865   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01866   * @param  DMAx DMAx Instance
01867   * @retval State of bit (1 or 0).
01868   */
01869 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01870 {
01871   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
01872 }
01873
01874 /**
01875   * @brief  Get Channel 4 transfer error flag.
01876   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01877   * @param  DMAx DMAx Instance
01878   * @retval State of bit (1 or 0).
01879   */
01880 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01881 {
01882   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
01883 }
01884
01885 /**
01886   * @brief  Get Channel 5 transfer error flag.
01887   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01888   * @param  DMAx DMAx Instance
01889   * @retval State of bit (1 or 0).
01890   */
01891 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01892 {
01893   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
01894 }
01895
01896 /**
01897   * @brief  Get Channel 6 transfer error flag.
01898   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01899   * @param  DMAx DMAx Instance
01900   * @retval State of bit (1 or 0).
01901   */
01902 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01903 {
01904   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
01905 }
01906
01907 #if defined (DMA1_Channel7)
01908 /**
01909   * @brief  Get Channel 7 transfer error flag.
01910   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01911   * @param  DMAx DMAx Instance
01912   * @retval State of bit (1 or 0).
01913   */
01914 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01915 {
01916   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
01917 }
01918 #endif /* DMA1_Channel7 */
01919
01920 #if defined (DMA1_Channel8)
01921 /**
01922   * @brief  Get Channel 8 transfer error flag.
01923   * @rmtoll ISR          TEIF8         LL_DMA_IsActiveFlag_TE8
01924   * @param  DMAx DMAx Instance
01925   * @retval State of bit (1 or 0).
01926   */
01927 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
01928 {
01929   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
01930 }
01931 #endif /* DMA1_Channel8 */
01932
01933 /**
01934   * @brief  Clear Channel 1 global interrupt flag.
01935   * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
01936     Instead clear specific flags transfer complete, half transfer & transfer
01937     error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
01938     LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
01939   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01940   * @param  DMAx DMAx Instance
01941   * @retval None
01942   */
01943 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01944 {
01945   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
01946 }
01947
01948 /**
01949   * @brief  Clear Channel 2 global interrupt flag.
01950   * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
01951     Instead clear specific flags transfer complete, half transfer & transfer
01952     error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
01953     LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
01954   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01955   * @param  DMAx DMAx Instance
01956   * @retval None
01957   */
01958 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01959 {
01960   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
01961 }
01962
01963 /**
01964   * @brief  Clear Channel 3 global interrupt flag.
01965   * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
01966     Instead clear specific flags transfer complete, half transfer & transfer
01967     error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
01968     LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
01969   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01970   * @param  DMAx DMAx Instance
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01974 {
01975   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
01976 }
01977
01978 /**
01979   * @brief  Clear Channel 4 global interrupt flag.
01980   * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
01981     Instead clear specific flags transfer complete, half transfer & transfer
01982     error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
01983     LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
01984   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01985   * @param  DMAx DMAx Instance
01986   * @retval None
01987   */
01988 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01989 {
01990   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
01991 }
01992
01993 /**
01994   * @brief  Clear Channel 5 global interrupt flag.
01995   * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
01996     Instead clear specific flags transfer complete, half transfer & transfer
01997     error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
01998     LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
01999   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
02000   * @param  DMAx DMAx Instance
02001   * @retval None
02002   */
02003 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
02004 {
02005   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
02006 }
02007
02008 /**
02009   * @brief  Clear Channel 6 global interrupt flag.
02010   * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
02011     Instead clear specific flags transfer complete, half transfer & transfer
02012     error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
02013     LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
02014   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
02015   * @param  DMAx DMAx Instance
02016   * @retval None
02017   */
02018 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
02019 {
02020   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
02021 }
02022
02023 #if defined (DMA1_Channel7)
02024 /**
02025   * @brief  Clear Channel 7 global interrupt flag.
02026   * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
02027     Instead clear specific flags transfer complete, half transfer & transfer
02028     error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
02029     LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
02030   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
02031   * @param  DMAx DMAx Instance
02032   * @retval None
02033   */
02034 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
02035 {
02036   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
02037 }
02038 #endif /* DMA1_Channel7 */
02039
02040 #if defined (DMA1_Channel8)
02041 /**
02042   * @brief  Clear Channel 8 global interrupt flag.
02043   * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
02044     Instead clear specific flags transfer complete, half transfer & transfer
02045     error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
02046     LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
02047   * @rmtoll IFCR         CGIF8         LL_DMA_ClearFlag_GI8
02048   * @param  DMAx DMAx Instance
02049   * @retval None
02050   */
02051 __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
02052 {
02053   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
02054 }
02055 #endif /* DMA1_Channel8 */
02056
02057 /**
02058   * @brief  Clear Channel 1  transfer complete flag.
02059   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
02060   * @param  DMAx DMAx Instance
02061   * @retval None
02062   */
02063 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
02064 {
02065   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
02066 }
02067
02068 /**
02069   * @brief  Clear Channel 2  transfer complete flag.
02070   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
02071   * @param  DMAx DMAx Instance
02072   * @retval None
02073   */
02074 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
02075 {
02076   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
02077 }
02078
02079 /**
02080   * @brief  Clear Channel 3  transfer complete flag.
02081   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
02082   * @param  DMAx DMAx Instance
02083   * @retval None
02084   */
02085 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
02086 {
02087   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
02088 }
02089
02090 /**
02091   * @brief  Clear Channel 4  transfer complete flag.
02092   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
02093   * @param  DMAx DMAx Instance
02094   * @retval None
02095   */
02096 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
02097 {
02098   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
02099 }
02100
02101 /**
02102   * @brief  Clear Channel 5  transfer complete flag.
02103   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
02104   * @param  DMAx DMAx Instance
02105   * @retval None
02106   */
02107 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
02108 {
02109   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
02110 }
02111
02112 /**
02113   * @brief  Clear Channel 6  transfer complete flag.
02114   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
02115   * @param  DMAx DMAx Instance
02116   * @retval None
02117   */
02118 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
02119 {
02120   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
02121 }
02122
02123 #if defined (DMA1_Channel7)
02124 /**
02125   * @brief  Clear Channel 7  transfer complete flag.
02126   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
02127   * @param  DMAx DMAx Instance
02128   * @retval None
02129   */
02130 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
02131 {
02132   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
02133 }
02134 #endif /* DMA1_Channel7 */
02135
02136 #if defined (DMA1_Channel8)
02137 /**
02138   * @brief  Clear Channel 8  transfer complete flag.
02139   * @rmtoll IFCR         CTCIF8        LL_DMA_ClearFlag_TC8
02140   * @param  DMAx DMAx Instance
02141   * @retval None
02142   */
02143 __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
02144 {
02145   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
02146 }
02147 #endif /* DMA1_Channel8 */
02148
02149 /**
02150   * @brief  Clear Channel 1  half transfer flag.
02151   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
02152   * @param  DMAx DMAx Instance
02153   * @retval None
02154   */
02155 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
02156 {
02157   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
02158 }
02159
02160 /**
02161   * @brief  Clear Channel 2  half transfer flag.
02162   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
02163   * @param  DMAx DMAx Instance
02164   * @retval None
02165   */
02166 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
02167 {
02168   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
02169 }
02170
02171 /**
02172   * @brief  Clear Channel 3  half transfer flag.
02173   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
02174   * @param  DMAx DMAx Instance
02175   * @retval None
02176   */
02177 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
02178 {
02179   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
02180 }
02181
02182 /**
02183   * @brief  Clear Channel 4  half transfer flag.
02184   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
02185   * @param  DMAx DMAx Instance
02186   * @retval None
02187   */
02188 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
02189 {
02190   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
02191 }
02192
02193 /**
02194   * @brief  Clear Channel 5  half transfer flag.
02195   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
02196   * @param  DMAx DMAx Instance
02197   * @retval None
02198   */
02199 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
02200 {
02201   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
02202 }
02203
02204 /**
02205   * @brief  Clear Channel 6  half transfer flag.
02206   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
02207   * @param  DMAx DMAx Instance
02208   * @retval None
02209   */
02210 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
02211 {
02212   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
02213 }
02214
02215 #if defined (DMA1_Channel7)
02216 /**
02217   * @brief  Clear Channel 7  half transfer flag.
02218   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
02219   * @param  DMAx DMAx Instance
02220   * @retval None
02221   */
02222 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
02223 {
02224   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
02225 }
02226 #endif /* DMA1_Channel7 */
02227
02228 #if defined (DMA1_Channel8)
02229 /**
02230   * @brief  Clear Channel 8  half transfer flag.
02231   * @rmtoll IFCR         CHTIF8        LL_DMA_ClearFlag_HT8
02232   * @param  DMAx DMAx Instance
02233   * @retval None
02234   */
02235 __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
02236 {
02237   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
02238 }
02239 #endif /* DMA1_Channel8 */
02240
02241 /**
02242   * @brief  Clear Channel 1 transfer error flag.
02243   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
02244   * @param  DMAx DMAx Instance
02245   * @retval None
02246   */
02247 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
02248 {
02249   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
02250 }
02251
02252 /**
02253   * @brief  Clear Channel 2 transfer error flag.
02254   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
02255   * @param  DMAx DMAx Instance
02256   * @retval None
02257   */
02258 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
02259 {
02260   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
02261 }
02262
02263 /**
02264   * @brief  Clear Channel 3 transfer error flag.
02265   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
02266   * @param  DMAx DMAx Instance
02267   * @retval None
02268   */
02269 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
02270 {
02271   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
02272 }
02273
02274 /**
02275   * @brief  Clear Channel 4 transfer error flag.
02276   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
02277   * @param  DMAx DMAx Instance
02278   * @retval None
02279   */
02280 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
02281 {
02282   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
02283 }
02284
02285 /**
02286   * @brief  Clear Channel 5 transfer error flag.
02287   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
02288   * @param  DMAx DMAx Instance
02289   * @retval None
02290   */
02291 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
02292 {
02293   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
02294 }
02295
02296 /**
02297   * @brief  Clear Channel 6 transfer error flag.
02298   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
02299   * @param  DMAx DMAx Instance
02300   * @retval None
02301   */
02302 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
02303 {
02304   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
02305 }
02306
02307 #if defined (DMA1_Channel7)
02308 /**
02309   * @brief  Clear Channel 7 transfer error flag.
02310   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
02311   * @param  DMAx DMAx Instance
02312   * @retval None
02313   */
02314 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
02315 {
02316   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
02317 }
02318 #endif /* DMA1_Channel7 */
02319
02320 #if defined (DMA1_Channel8)
02321 /**
02322   * @brief  Clear Channel 8 transfer error flag.
02323   * @rmtoll IFCR         CTEIF8        LL_DMA_ClearFlag_TE8
02324   * @param  DMAx DMAx Instance
02325   * @retval None
02326   */
02327 __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
02328 {
02329   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
02330 }
02331 #endif /* DMA1_Channel8 */
02332
02333 /**
02334   * @}
02335   */
02336
02337 /** @defgroup DMA_LL_EF_IT_Management IT_Management
02338   * @{
02339   */
02340 /**
02341   * @brief  Enable Transfer complete interrupt.
02342   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
02343   * @param  DMAx DMAx Instance
02344   * @param  Channel This parameter can be one of the following values:
02345   *         @arg @ref LL_DMA_CHANNEL_1
02346   *         @arg @ref LL_DMA_CHANNEL_2
02347   *         @arg @ref LL_DMA_CHANNEL_3
02348   *         @arg @ref LL_DMA_CHANNEL_4
02349   *         @arg @ref LL_DMA_CHANNEL_5
02350   *         @arg @ref LL_DMA_CHANNEL_6
02351   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02352   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02353   *         (*) Not on all G4 devices
02354   * @retval None
02355   */
02356 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02357 {
02358   uint32_t dma_base_addr = (uint32_t)DMAx;
02359   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
02360 }
02361
02362 /**
02363   * @brief  Enable Half transfer interrupt.
02364   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
02365   * @param  DMAx DMAx Instance
02366   * @param  Channel This parameter can be one of the following values:
02367   *         @arg @ref LL_DMA_CHANNEL_1
02368   *         @arg @ref LL_DMA_CHANNEL_2
02369   *         @arg @ref LL_DMA_CHANNEL_3
02370   *         @arg @ref LL_DMA_CHANNEL_4
02371   *         @arg @ref LL_DMA_CHANNEL_5
02372   *         @arg @ref LL_DMA_CHANNEL_6
02373   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02374   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02375   *         (*) Not on all G4 devices
02376   * @retval None
02377   */
02378 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02379 {
02380   uint32_t dma_base_addr = (uint32_t)DMAx;
02381   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
02382 }
02383
02384 /**
02385   * @brief  Enable Transfer error interrupt.
02386   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
02387   * @param  DMAx DMAx Instance
02388   * @param  Channel This parameter can be one of the following values:
02389   *         @arg @ref LL_DMA_CHANNEL_1
02390   *         @arg @ref LL_DMA_CHANNEL_2
02391   *         @arg @ref LL_DMA_CHANNEL_3
02392   *         @arg @ref LL_DMA_CHANNEL_4
02393   *         @arg @ref LL_DMA_CHANNEL_5
02394   *         @arg @ref LL_DMA_CHANNEL_6
02395   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02396   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02397   *         (*) Not on all G4 devices
02398   * @retval None
02399   */
02400 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02401 {
02402   uint32_t dma_base_addr = (uint32_t)DMAx;
02403   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
02404 }
02405
02406 /**
02407   * @brief  Disable Transfer complete interrupt.
02408   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
02409   * @param  DMAx DMAx Instance
02410   * @param  Channel This parameter can be one of the following values:
02411   *         @arg @ref LL_DMA_CHANNEL_1
02412   *         @arg @ref LL_DMA_CHANNEL_2
02413   *         @arg @ref LL_DMA_CHANNEL_3
02414   *         @arg @ref LL_DMA_CHANNEL_4
02415   *         @arg @ref LL_DMA_CHANNEL_5
02416   *         @arg @ref LL_DMA_CHANNEL_6
02417   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02418   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02419   *         (*) Not on all G4 devices
02420   * @retval None
02421   */
02422 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02423 {
02424   uint32_t dma_base_addr = (uint32_t)DMAx;
02425   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
02426 }
02427
02428 /**
02429   * @brief  Disable Half transfer interrupt.
02430   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
02431   * @param  DMAx DMAx Instance
02432   * @param  Channel This parameter can be one of the following values:
02433   *         @arg @ref LL_DMA_CHANNEL_1
02434   *         @arg @ref LL_DMA_CHANNEL_2
02435   *         @arg @ref LL_DMA_CHANNEL_3
02436   *         @arg @ref LL_DMA_CHANNEL_4
02437   *         @arg @ref LL_DMA_CHANNEL_5
02438   *         @arg @ref LL_DMA_CHANNEL_6
02439   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02440   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02441   *         (*) Not on all G4 devices
02442   * @retval None
02443   */
02444 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02445 {
02446   uint32_t dma_base_addr = (uint32_t)DMAx;
02447   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
02448 }
02449
02450 /**
02451   * @brief  Disable Transfer error interrupt.
02452   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
02453   * @param  DMAx DMAx Instance
02454   * @param  Channel This parameter can be one of the following values:
02455   *         @arg @ref LL_DMA_CHANNEL_1
02456   *         @arg @ref LL_DMA_CHANNEL_2
02457   *         @arg @ref LL_DMA_CHANNEL_3
02458   *         @arg @ref LL_DMA_CHANNEL_4
02459   *         @arg @ref LL_DMA_CHANNEL_5
02460   *         @arg @ref LL_DMA_CHANNEL_6
02461   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02462   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02463   *         (*) Not on all G4 devices
02464   * @retval None
02465   */
02466 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02467 {
02468   uint32_t dma_base_addr = (uint32_t)DMAx;
02469   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
02470 }
02471
02472 /**
02473   * @brief  Check if Transfer complete Interrupt is enabled.
02474   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
02475   * @param  DMAx DMAx Instance
02476   * @param  Channel This parameter can be one of the following values:
02477   *         @arg @ref LL_DMA_CHANNEL_1
02478   *         @arg @ref LL_DMA_CHANNEL_2
02479   *         @arg @ref LL_DMA_CHANNEL_3
02480   *         @arg @ref LL_DMA_CHANNEL_4
02481   *         @arg @ref LL_DMA_CHANNEL_5
02482   *         @arg @ref LL_DMA_CHANNEL_6
02483   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02484   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02485   *         (*) Not on all G4 devices
02486   * @retval State of bit (1 or 0).
02487   */
02488 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02489 {
02490   uint32_t dma_base_addr = (uint32_t)DMAx;
02491   return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
02492                     DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
02493 }
02494
02495 /**
02496   * @brief  Check if Half transfer Interrupt is enabled.
02497   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
02498   * @param  DMAx DMAx Instance
02499   * @param  Channel This parameter can be one of the following values:
02500   *         @arg @ref LL_DMA_CHANNEL_1
02501   *         @arg @ref LL_DMA_CHANNEL_2
02502   *         @arg @ref LL_DMA_CHANNEL_3
02503   *         @arg @ref LL_DMA_CHANNEL_4
02504   *         @arg @ref LL_DMA_CHANNEL_5
02505   *         @arg @ref LL_DMA_CHANNEL_6
02506   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02507   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02508   *         (*) Not on all G4 devices
02509   * @retval State of bit (1 or 0).
02510   */
02511 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02512 {
02513   uint32_t dma_base_addr = (uint32_t)DMAx;
02514   return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
02515                     DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
02516 }
02517
02518 /**
02519   * @brief  Check if Transfer error Interrupt is enabled.
02520   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
02521   * @param  DMAx DMAx Instance
02522   * @param  Channel This parameter can be one of the following values:
02523   *         @arg @ref LL_DMA_CHANNEL_1
02524   *         @arg @ref LL_DMA_CHANNEL_2
02525   *         @arg @ref LL_DMA_CHANNEL_3
02526   *         @arg @ref LL_DMA_CHANNEL_4
02527   *         @arg @ref LL_DMA_CHANNEL_5
02528   *         @arg @ref LL_DMA_CHANNEL_6
02529   *         @arg @ref LL_DMA_CHANNEL_7 (*)
02530   *         @arg @ref LL_DMA_CHANNEL_8 (*)
02531   *         (*) Not on all G4 devices
02532   * @retval State of bit (1 or 0).
02533   */
02534 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02535 {
02536   uint32_t dma_base_addr = (uint32_t)DMAx;
02537   return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
02538                     DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
02539 }
02540
02541 /**
02542   * @}
02543   */
02544
02545 #if defined(USE_FULL_LL_DRIVER)
02546 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
02547   * @{
02548   */
02549
02550 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
02551 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
02552 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
02553
02554 /**
02555   * @}
02556   */
02557 #endif /* USE_FULL_LL_DRIVER */
02558
02559 /**
02560   * @}
02561   */
02562
02563 /**
02564   * @}
02565   */
02566
02567 #endif /* DMA1 || DMA2 */
02568
02569 /**
02570   * @}
02571   */
02572
02573 #ifdef __cplusplus
02574 }
02575 #endif
02576
02577 #endif /* __STM32G4xx_LL_DMA_H */
02578
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_dmamux.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_dmamux.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_dmamux.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMAMUX LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_LL_DMAMUX_H
00021 #define __STM32G4xx_LL_DMAMUX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMAMUX1)
00035
00036 /** @defgroup DMAMUX_LL DMAMUX
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
00044   * @{
00045   */
00046 /* Define used to get DMAMUX CCR register size */
00047 #define DMAMUX_CCR_SIZE                   0x00000004U
00048
00049 /* Define used to get DMAMUX RGCR register size */
00050 #define DMAMUX_RGCR_SIZE                  0x00000004U
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056 /** @defgroup DMAMUX_LL_Private_Macros DMAMUX Private Macros
00057   * @{
00058   */
00059 #define UNUSED(X) (void)X
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
00067   * @{
00068   */
00069 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
00070   * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
00071   * @{
00072   */
00073 #define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00074 #define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00075 #define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00076 #define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00077 #define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00078 #define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00079 #define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00080 #define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00081 #define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00082 #define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00083 #define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00084 #define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00085 #define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
00086 #define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
00087 #define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14 */
00088 #define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15 */
00089 #define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
00090 #define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
00091 #define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
00092 #define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
00098   * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
00099   * @{
00100   */
00101 #define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00102 #define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00103 #define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00104 #define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00105 #define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00106 #define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00107 #define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00108 #define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00109 #define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00110 #define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00111 #define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00112 #define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00113 #define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
00114 #define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
00115 #define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14 */
00116 #define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15 */
00117 #define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
00118 #define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
00119 #define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
00120 #define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup DMAMUX_LL_EC_IT IT Defines
00126   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
00127   * @{
00128   */
00129 #define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */
00130 #define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
00136   * @{
00137   */
00138 #define LL_DMAMUX_REQ_MEM2MEM         0x00000000U  /*!< Memory to memory transfer  */
00139 #define LL_DMAMUX_REQ_GENERATOR0      0x00000001U  /*!< DMAMUX request generator 0 */
00140 #define LL_DMAMUX_REQ_GENERATOR1      0x00000002U  /*!< DMAMUX request generator 1 */
00141 #define LL_DMAMUX_REQ_GENERATOR2      0x00000003U  /*!< DMAMUX request generator 2 */
00142 #define LL_DMAMUX_REQ_GENERATOR3      0x00000004U  /*!< DMAMUX request generator 3 */
00143 #define LL_DMAMUX_REQ_ADC1            0x00000005U  /*!< DMAMUX ADC1 request        */
00144 #define LL_DMAMUX_REQ_DAC1_CH1        0x00000006U  /*!< DMAMUX DAC1 CH1 request    */
00145 #define LL_DMAMUX_REQ_DAC1_CH2        0x00000007U  /*!< DMAMUX DAC1 CH2 request    */
00146 #define LL_DMAMUX_REQ_TIM6_UP         0x00000008U  /*!< DMAMUX TIM6 UP request     */
00147 #define LL_DMAMUX_REQ_TIM7_UP         0x00000009U  /*!< DMAMUX TIM7 UP request     */
00148 #define LL_DMAMUX_REQ_SPI1_RX         0x0000000AU  /*!< DMAMUX SPI1 RX request     */
00149 #define LL_DMAMUX_REQ_SPI1_TX         0x0000000BU  /*!< DMAMUX SPI1 TX request     */
00150 #define LL_DMAMUX_REQ_SPI2_RX         0x0000000CU  /*!< DMAMUX SPI2 RX request     */
00151 #define LL_DMAMUX_REQ_SPI2_TX         0x0000000DU  /*!< DMAMUX SPI2 TX request     */
00152 #define LL_DMAMUX_REQ_SPI3_RX         0x0000000EU  /*!< DMAMUX SPI3 RX request     */
00153 #define LL_DMAMUX_REQ_SPI3_TX         0x0000000FU  /*!< DMAMUX SPI3 TX request     */
00154 #define LL_DMAMUX_REQ_I2C1_RX         0x00000010U  /*!< DMAMUX I2C1 RX request     */
00155 #define LL_DMAMUX_REQ_I2C1_TX         0x00000011U  /*!< DMAMUX I2C1 TX request     */
00156 #define LL_DMAMUX_REQ_I2C2_RX         0x00000012U  /*!< DMAMUX I2C2 RX request     */
00157 #define LL_DMAMUX_REQ_I2C2_TX         0x00000013U  /*!< DMAMUX I2C2 TX request     */
00158 #define LL_DMAMUX_REQ_I2C3_RX         0x00000014U  /*!< DMAMUX I2C3 RX request     */
00159 #define LL_DMAMUX_REQ_I2C3_TX         0x00000015U  /*!< DMAMUX I2C3 TX request     */
00160 #define LL_DMAMUX_REQ_I2C4_RX         0x00000016U  /*!< DMAMUX I2C4 RX request     */
00161 #define LL_DMAMUX_REQ_I2C4_TX         0x00000017U  /*!< DMAMUX I2C4 TX request     */
00162 #define LL_DMAMUX_REQ_USART1_RX       0x00000018U  /*!< DMAMUX USART1 RX request   */
00163 #define LL_DMAMUX_REQ_USART1_TX       0x00000019U  /*!< DMAMUX USART1 TX request   */
00164 #define LL_DMAMUX_REQ_USART2_RX       0x0000001AU  /*!< DMAMUX USART2 RX request   */
00165 #define LL_DMAMUX_REQ_USART2_TX       0x0000001BU  /*!< DMAMUX USART2 TX request   */
00166 #define LL_DMAMUX_REQ_USART3_RX       0x0000001CU  /*!< DMAMUX USART3 RX request   */
00167 #define LL_DMAMUX_REQ_USART3_TX       0x0000001DU  /*!< DMAMUX USART3 TX request   */
00168 #define LL_DMAMUX_REQ_UART4_RX        0x0000001EU  /*!< DMAMUX UART4 RX request    */
00169 #define LL_DMAMUX_REQ_UART4_TX        0x0000001FU  /*!< DMAMUX UART4 TX request    */
00170 #define LL_DMAMUX_REQ_UART5_RX        0x00000020U  /*!< DMAMUX UART5 RX request    */
00171 #define LL_DMAMUX_REQ_UART5_TX        0x00000021U  /*!< DMAMUX UART5 TX request    */
00172 #define LL_DMAMUX_REQ_LPUART1_RX      0x00000022U  /*!< DMAMUX LPUART1 RX request  */
00173 #define LL_DMAMUX_REQ_LPUART1_TX      0x00000023U  /*!< DMAMUX LPUART1 TX request  */
00174 #define LL_DMAMUX_REQ_ADC2            0x00000024U  /*!< DMAMUX ADC2 request        */
00175 #define LL_DMAMUX_REQ_ADC3            0x00000025U  /*!< DMAMUX ADC3 request        */
00176 #define LL_DMAMUX_REQ_ADC4            0x00000026U  /*!< DMAMUX ADC4 request        */
00177 #define LL_DMAMUX_REQ_ADC5            0x00000027U  /*!< DMAMUX ADC5 request        */
00178 #define LL_DMAMUX_REQ_QSPI            0x00000028U  /*!< DMAMUX QSPI request        */
00179 #define LL_DMAMUX_REQ_DAC2_CH1        0x00000029U  /*!< DMAMUX DAC2 CH1 request    */
00180 #define LL_DMAMUX_REQ_TIM1_CH1        0x0000002AU  /*!< DMAMUX TIM1 CH1 request    */
00181 #define LL_DMAMUX_REQ_TIM1_CH2        0x0000002BU  /*!< DMAMUX TIM1 CH2 request    */
00182 #define LL_DMAMUX_REQ_TIM1_CH3        0x0000002CU  /*!< DMAMUX TIM1 CH3 request    */
00183 #define LL_DMAMUX_REQ_TIM1_CH4        0x0000002DU  /*!< DMAMUX TIM1 CH4 request    */
00184 #define LL_DMAMUX_REQ_TIM1_UP         0x0000002EU  /*!< DMAMUX TIM1 UP request     */
00185 #define LL_DMAMUX_REQ_TIM1_TRIG       0x0000002FU  /*!< DMAMUX TIM1 TRIG request   */
00186 #define LL_DMAMUX_REQ_TIM1_COM        0x00000030U  /*!< DMAMUX TIM1 COM request    */
00187 #define LL_DMAMUX_REQ_TIM8_CH1        0x00000031U  /*!< DMAMUX TIM8 CH1 request    */
00188 #define LL_DMAMUX_REQ_TIM8_CH2        0x00000032U  /*!< DMAMUX TIM8 CH2 request    */
00189 #define LL_DMAMUX_REQ_TIM8_CH3        0x00000033U  /*!< DMAMUX TIM8 CH3 request    */
00190 #define LL_DMAMUX_REQ_TIM8_CH4        0x00000034U  /*!< DMAMUX TIM8 CH4 request    */
00191 #define LL_DMAMUX_REQ_TIM8_UP         0x00000035U  /*!< DMAMUX TIM8 UP request     */
00192 #define LL_DMAMUX_REQ_TIM8_TRIG       0x00000036U  /*!< DMAMUX TIM8 TRIG request   */
00193 #define LL_DMAMUX_REQ_TIM8_COM        0x00000037U  /*!< DMAMUX TIM8 COM request    */
00194 #define LL_DMAMUX_REQ_TIM2_CH1        0x00000038U  /*!< DMAMUX TIM2 CH1 request    */
00195 #define LL_DMAMUX_REQ_TIM2_CH2        0x00000039U  /*!< DMAMUX TIM2 CH2 request    */
00196 #define LL_DMAMUX_REQ_TIM2_CH3        0x0000003AU  /*!< DMAMUX TIM2 CH3 request    */
00197 #define LL_DMAMUX_REQ_TIM2_CH4        0x0000003BU  /*!< DMAMUX TIM2 CH4 request    */
00198 #define LL_DMAMUX_REQ_TIM2_UP         0x0000003CU  /*!< DMAMUX TIM2 UP request     */
00199 #define LL_DMAMUX_REQ_TIM3_CH1        0x0000003DU  /*!< DMAMUX TIM3 CH1 request    */
00200 #define LL_DMAMUX_REQ_TIM3_CH2        0x0000003EU  /*!< DMAMUX TIM3 CH2 request    */
00201 #define LL_DMAMUX_REQ_TIM3_CH3        0x0000003FU  /*!< DMAMUX TIM3 CH3 request    */
00202 #define LL_DMAMUX_REQ_TIM3_CH4        0x00000040U  /*!< DMAMUX TIM3 CH4 request    */
00203 #define LL_DMAMUX_REQ_TIM3_UP         0x00000041U  /*!< DMAMUX TIM3 UP request     */
00204 #define LL_DMAMUX_REQ_TIM3_TRIG       0x00000042U  /*!< DMAMUX TIM3 TRIG request   */
00205 #define LL_DMAMUX_REQ_TIM4_CH1        0x00000043U  /*!< DMAMUX TIM4 CH1 request    */
00206 #define LL_DMAMUX_REQ_TIM4_CH2        0x00000044U  /*!< DMAMUX TIM4 CH2 request    */
00207 #define LL_DMAMUX_REQ_TIM4_CH3        0x00000045U  /*!< DMAMUX TIM4 CH3 request    */
00208 #define LL_DMAMUX_REQ_TIM4_CH4        0x00000046U  /*!< DMAMUX TIM4 CH4 request    */
00209 #define LL_DMAMUX_REQ_TIM4_UP         0x00000047U  /*!< DMAMUX TIM4 UP request     */
00210 #define LL_DMAMUX_REQ_TIM5_CH1        0x00000048U  /*!< DMAMUX TIM5 CH1 request    */
00211 #define LL_DMAMUX_REQ_TIM5_CH2        0x00000049U  /*!< DMAMUX TIM5 CH2 request    */
00212 #define LL_DMAMUX_REQ_TIM5_CH3        0x0000004AU  /*!< DMAMUX TIM5 CH3 request    */
00213 #define LL_DMAMUX_REQ_TIM5_CH4        0x0000004BU  /*!< DMAMUX TIM5 CH4 request    */
00214 #define LL_DMAMUX_REQ_TIM5_UP         0x0000004CU  /*!< DMAMUX TIM5 UP request     */
00215 #define LL_DMAMUX_REQ_TIM5_TRIG       0x0000004DU  /*!< DMAMUX TIM5 TRIG request   */
00216 #define LL_DMAMUX_REQ_TIM15_CH1       0x0000004EU  /*!< DMAMUX TIM15 CH1 request   */
00217 #define LL_DMAMUX_REQ_TIM15_UP        0x0000004FU  /*!< DMAMUX TIM15 UP request    */
00218 #define LL_DMAMUX_REQ_TIM15_TRIG      0x00000050U  /*!< DMAMUX TIM15 TRIG request  */
00219 #define LL_DMAMUX_REQ_TIM15_COM       0x00000051U  /*!< DMAMUX TIM15 COM request   */
00220 #define LL_DMAMUX_REQ_TIM16_CH1       0x00000052U  /*!< DMAMUX TIM16 CH1 request   */
00221 #define LL_DMAMUX_REQ_TIM16_UP        0x00000053U  /*!< DMAMUX TIM16 UP request    */
00222 #define LL_DMAMUX_REQ_TIM17_CH1       0x00000054U  /*!< DMAMUX TIM17 CH1 request   */
00223 #define LL_DMAMUX_REQ_TIM17_UP        0x00000055U  /*!< DMAMUX TIM17 UP request    */
00224 #define LL_DMAMUX_REQ_TIM20_CH1       0x00000056U  /*!< DMAMUX TIM20 CH1 request   */
00225 #define LL_DMAMUX_REQ_TIM20_CH2       0x00000057U  /*!< DMAMUX TIM20 CH2 request   */
00226 #define LL_DMAMUX_REQ_TIM20_CH3       0x00000058U  /*!< DMAMUX TIM20 CH3 request   */
00227 #define LL_DMAMUX_REQ_TIM20_CH4       0x00000059U  /*!< DMAMUX TIM20 CH4 request   */
00228 #define LL_DMAMUX_REQ_TIM20_UP        0x0000005AU  /*!< DMAMUX TIM20 UP request    */
00229 #define LL_DMAMUX_REQ_AES_IN          0x0000005BU  /*!< DMAMUX AES_IN request      */
00230 #define LL_DMAMUX_REQ_AES_OUT         0x0000005CU  /*!< DMAMUX AES_OUT request     */
00231 #define LL_DMAMUX_REQ_TIM20_TRIG      0x0000005DU  /*!< DMAMUX TIM20 TRIG request  */
00232 #define LL_DMAMUX_REQ_TIM20_COM       0x0000005EU  /*!< DMAMUX TIM20 COM request   */
00233 #define LL_DMAMUX_REQ_HRTIM1_M        0x0000005FU  /*!< DMAMUX HRTIM M request     */
00234 #define LL_DMAMUX_REQ_HRTIM1_A        0x00000060U  /*!< DMAMUX HRTIM A request     */
00235 #define LL_DMAMUX_REQ_HRTIM1_B        0x00000061U  /*!< DMAMUX HRTIM B request     */
00236 #define LL_DMAMUX_REQ_HRTIM1_C        0x00000062U  /*!< DMAMUX HRTIM C request     */
00237 #define LL_DMAMUX_REQ_HRTIM1_D        0x00000063U  /*!< DMAMUX HRTIM D request     */
00238 #define LL_DMAMUX_REQ_HRTIM1_E        0x00000064U  /*!< DMAMUX HRTIM E request     */
00239 #define LL_DMAMUX_REQ_HRTIM1_F        0x00000065U  /*!< DMAMUX HRTIM F request     */
00240 #define LL_DMAMUX_REQ_DAC3_CH1        0x00000066U  /*!< DMAMUX DAC3 CH1 request    */
00241 #define LL_DMAMUX_REQ_DAC3_CH2        0x00000067U  /*!< DMAMUX DAC3 CH2 request    */
00242 #define LL_DMAMUX_REQ_DAC4_CH1        0x00000068U  /*!< DMAMUX DAC4 CH1 request    */
00243 #define LL_DMAMUX_REQ_DAC4_CH2        0x00000069U  /*!< DMAMUX DAC4 CH2 request    */
00244 #define LL_DMAMUX_REQ_SPI4_RX         0x0000006AU  /*!< DMAMUX SPI4 RX request     */
00245 #define LL_DMAMUX_REQ_SPI4_TX         0x0000006BU  /*!< DMAMUX SPI4 TX request     */
00246 #define LL_DMAMUX_REQ_SAI1_A          0x0000006CU  /*!< DMAMUX SAI1 A request      */
00247 #define LL_DMAMUX_REQ_SAI1_B          0x0000006DU  /*!< DMAMUX SAI1 B request      */
00248 #define LL_DMAMUX_REQ_FMAC_READ       0x0000006EU  /*!< DMAMUX FMAC READ request   */
00249 #define LL_DMAMUX_REQ_FMAC_WRITE      0x0000006FU  /*!< DMAMUX FMAC WRITE request  */
00250 #define LL_DMAMUX_REQ_CORDIC_READ     0x00000070U  /*!< DMAMUX CORDIC READ request */
00251 #define LL_DMAMUX_REQ_CORDIC_WRITE    0x00000071U  /*!< DMAMUX CORDIC WRITE request*/
00252 #define LL_DMAMUX_REQ_UCPD1_RX        0x00000072U  /*!< DMAMUX USBPD1_RX request   */
00253 #define LL_DMAMUX_REQ_UCPD1_TX        0x00000073U  /*!< DMAMUX USBPD1_TX request   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
00260   * @{
00261   */
00262 #define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */
00263 #define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */
00264 #define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */
00265 #define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */
00266 #define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */
00267 #define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */
00268 #define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */
00269 #define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA1 Channel 8  */
00270 #define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 1  */
00271 #define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 2  */
00272 #define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 3 */
00273 #define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
00274 #define LL_DMAMUX_CHANNEL_12              0x0000000CU               /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
00275 #define LL_DMAMUX_CHANNEL_13              0x0000000DU               /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
00276 #define LL_DMAMUX_CHANNEL_14              0x0000000EU               /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
00277 #define LL_DMAMUX_CHANNEL_15              0x0000000FU               /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
00283   * @{
00284   */
00285 #define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */
00286 #define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */
00287 #define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */
00288 #define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
00294   * @{
00295   */
00296 #define LL_DMAMUX_SYNC_EXTI_LINE0      0x00000000U                                                                                     /*!< Synchronization signal from EXTI Line0  */
00297 #define LL_DMAMUX_SYNC_EXTI_LINE1      DMAMUX_CxCR_SYNC_ID_0                                                                           /*!< Synchronization signal from EXTI Line1  */
00298 #define LL_DMAMUX_SYNC_EXTI_LINE2      DMAMUX_CxCR_SYNC_ID_1                                                                           /*!< Synchronization signal from EXTI Line2  */
00299 #define LL_DMAMUX_SYNC_EXTI_LINE3      (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0)                                                  /*!< Synchronization signal from EXTI Line3  */
00300 #define LL_DMAMUX_SYNC_EXTI_LINE4      DMAMUX_CxCR_SYNC_ID_2                                                                           /*!< Synchronization signal from EXTI Line4  */
00301 #define LL_DMAMUX_SYNC_EXTI_LINE5      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line5  */
00302 #define LL_DMAMUX_SYNC_EXTI_LINE6      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line6  */
00303 #define LL_DMAMUX_SYNC_EXTI_LINE7      (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line7  */
00304 #define LL_DMAMUX_SYNC_EXTI_LINE8      DMAMUX_CxCR_SYNC_ID_3                                                                           /*!< Synchronization signal from EXTI Line8  */
00305 #define LL_DMAMUX_SYNC_EXTI_LINE9      (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line9  */
00306 #define LL_DMAMUX_SYNC_EXTI_LINE10     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line10 */
00307 #define LL_DMAMUX_SYNC_EXTI_LINE11     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line11 */
00308 #define LL_DMAMUX_SYNC_EXTI_LINE12     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from EXTI Line12 */
00309 #define LL_DMAMUX_SYNC_EXTI_LINE13     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line13 */
00310 #define LL_DMAMUX_SYNC_EXTI_LINE14     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from EXTI Line14 */
00311 #define LL_DMAMUX_SYNC_EXTI_LINE15     (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
00312 #define LL_DMAMUX_SYNC_DMAMUX_CH0      DMAMUX_CxCR_SYNC_ID_4                                                                           /*!< Synchronization signal from DMAMUX channel0 Event */
00313 #define LL_DMAMUX_SYNC_DMAMUX_CH1      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from DMAMUX channel1 Event */
00314 #define LL_DMAMUX_SYNC_DMAMUX_CH2      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from DMAMUX channel2 Event */
00315 #define LL_DMAMUX_SYNC_DMAMUX_CH3      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from DMAMUX channel3 Event */
00316 #define LL_DMAMUX_SYNC_LPTIM1_OUT      (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from LPTIM1 Output */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
00322   * @{
00323   */
00324 #define LL_DMAMUX_REQ_GEN_0           0x00000000U
00325 #define LL_DMAMUX_REQ_GEN_1           0x00000001U
00326 #define LL_DMAMUX_REQ_GEN_2           0x00000002U
00327 #define LL_DMAMUX_REQ_GEN_3           0x00000003U
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
00333   * @{
00334   */
00335 #define LL_DMAMUX_REQ_GEN_NO_EVENT                  0x00000000U                                  /*!< No external DMA request  generation */
00336 #define LL_DMAMUX_REQ_GEN_POL_RISING                DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */
00337 #define LL_DMAMUX_REQ_GEN_POL_FALLING               DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */
00338 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING        (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
00344   * @{
00345   */
00346 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0      0x00000000U                                                                                     /*!< Request signal generation from EXTI Line0  */
00347 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1      DMAMUX_RGxCR_SIG_ID_0                                                                           /*!< Request signal generation from EXTI Line1  */
00348 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2      DMAMUX_RGxCR_SIG_ID_1                                                                           /*!< Request signal generation from EXTI Line2  */
00349 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3      (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)                                                  /*!< Request signal generation from EXTI Line3  */
00350 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4      DMAMUX_RGxCR_SIG_ID_2                                                                           /*!< Request signal generation from EXTI Line4  */
00351 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line5  */
00352 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line6  */
00353 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line7  */
00354 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8      DMAMUX_RGxCR_SIG_ID_3                                                                           /*!< Request signal generation from EXTI Line8  */
00355 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9      (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line9  */
00356 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line10 */
00357 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line11 */
00358 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from EXTI Line12 */
00359 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line13 */
00360 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from EXTI Line14 */
00361 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
00362 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      DMAMUX_RGxCR_SIG_ID_4                                                                           /*!< Request signal generation from DMAMUX channel0 Event */
00363 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from DMAMUX channel1 Event */
00364 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from DMAMUX channel2 Event */
00365 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from DMAMUX channel3 Event */
00366 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from LPTIM1 Output */
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /* Exported macro ------------------------------------------------------------*/
00376 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
00377   * @{
00378   */
00379 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
00380   * @{
00381   */
00382 /**
00383   * @brief  Write a value in DMAMUX register
00384   * @param  __INSTANCE__ DMAMUX Instance
00385   * @param  __REG__ Register to be written
00386   * @param  __VALUE__ Value to be written in the register
00387   * @retval None
00388   */
00389 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00390
00391 /**
00392   * @brief  Read a value in DMAMUX register
00393   * @param  __INSTANCE__ DMAMUX Instance
00394   * @param  __REG__ Register to be read
00395   * @retval Register value
00396   */
00397 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00398 /**
00399   * @}
00400   */
00401
00402 /**
00403   * @}
00404   */
00405
00406 /* Exported functions --------------------------------------------------------*/
00407 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
00408   * @{
00409   */
00410
00411 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
00412   * @{
00413   */
00414 /**
00415   * @brief  Set DMAMUX request ID for DMAMUX Channel x.
00416   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
00417   *         DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
00418   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
00419   * @param  DMAMUXx DMAMUXx Instance
00420   * @param  Channel This parameter can be one of the following values:
00421   *         @arg @ref LL_DMAMUX_CHANNEL_0
00422   *         @arg @ref LL_DMAMUX_CHANNEL_1
00423   *         @arg @ref LL_DMAMUX_CHANNEL_2
00424   *         @arg @ref LL_DMAMUX_CHANNEL_3
00425   *         @arg @ref LL_DMAMUX_CHANNEL_4
00426   *         @arg @ref LL_DMAMUX_CHANNEL_5
00427   *         @arg @ref LL_DMAMUX_CHANNEL_6
00428   *         @arg @ref LL_DMAMUX_CHANNEL_7
00429   *         @arg @ref LL_DMAMUX_CHANNEL_8
00430   *         @arg @ref LL_DMAMUX_CHANNEL_9
00431   *         @arg @ref LL_DMAMUX_CHANNEL_10
00432   *         @arg @ref LL_DMAMUX_CHANNEL_11
00433   *         @arg @ref LL_DMAMUX_CHANNEL_12
00434   *         @arg @ref LL_DMAMUX_CHANNEL_13
00435   *         @arg @ref LL_DMAMUX_CHANNEL_14
00436   *         @arg @ref LL_DMAMUX_CHANNEL_15
00437   * @param  Request This parameter can be one of the following values:
00438   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00439   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00440   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00441   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00442   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00443   *         @arg @ref LL_DMAMUX_REQ_ADC1
00444   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
00445   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
00446   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
00447   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
00448   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00449   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00450   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00451   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00452   *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
00453   *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
00454   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00455   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00456   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
00457   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
00458   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
00459   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
00460   *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
00461   *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
00462   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00463   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00464   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
00465   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
00466   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
00467   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
00468   *         @arg @ref LL_DMAMUX_REQ_UART4_RX
00469   *         @arg @ref LL_DMAMUX_REQ_UART4_TX
00470   *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
00471   *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
00472   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00473   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00474   *         @arg @ref LL_DMAMUX_REQ_ADC2
00475   *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
00476   *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
00477   *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
00478   *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
00479   *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
00480   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00481   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00482   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00483   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00484   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00485   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
00486   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
00487   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
00488   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
00489   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
00490   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
00491   *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
00492   *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
00493   *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
00494   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00495   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00496   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00497   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00498   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00499   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
00500   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
00501   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
00502   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
00503   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
00504   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
00505   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
00506   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
00507   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
00508   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
00509   *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
00510   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
00511   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
00512   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
00513   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
00514   *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
00515   *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
00516   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
00517   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
00518   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
00519   *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
00520   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00521   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00522   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00523   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00524   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
00525   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
00526   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
00527   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
00528   *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
00529   *         @arg @ref LL_DMAMUX_REQ_AES_IN
00530   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
00531   *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
00532   *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
00533   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
00534   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
00535   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
00536   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
00537   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
00538   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
00539   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
00540   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
00541   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
00542   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
00543   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
00544   *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
00545   *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
00546   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
00547   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
00548   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
00549   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
00550   *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
00551   *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
00552   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
00553   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
00554   *         (*) Not on all G4 devices
00555   * @retval None
00556   */
00557 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
00558 {
00559   (void)(DMAMUXx);
00560   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
00561 }
00562
00563 /**
00564   * @brief  Get DMAMUX request ID for DMAMUX Channel x.
00565   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
00566   *         DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
00567   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
00568   * @param  DMAMUXx DMAMUXx Instance
00569   * @param  Channel This parameter can be one of the following values:
00570   *         @arg @ref LL_DMAMUX_CHANNEL_0
00571   *         @arg @ref LL_DMAMUX_CHANNEL_1
00572   *         @arg @ref LL_DMAMUX_CHANNEL_2
00573   *         @arg @ref LL_DMAMUX_CHANNEL_3
00574   *         @arg @ref LL_DMAMUX_CHANNEL_4
00575   *         @arg @ref LL_DMAMUX_CHANNEL_5
00576   *         @arg @ref LL_DMAMUX_CHANNEL_6
00577   *         @arg @ref LL_DMAMUX_CHANNEL_7
00578   *         @arg @ref LL_DMAMUX_CHANNEL_8
00579   *         @arg @ref LL_DMAMUX_CHANNEL_9
00580   *         @arg @ref LL_DMAMUX_CHANNEL_10
00581   *         @arg @ref LL_DMAMUX_CHANNEL_11
00582   *         @arg @ref LL_DMAMUX_CHANNEL_12
00583   *         @arg @ref LL_DMAMUX_CHANNEL_13
00584   *         @arg @ref LL_DMAMUX_CHANNEL_14
00585   *         @arg @ref LL_DMAMUX_CHANNEL_15
00586   *         (*) Not on all G4 devices
00587   * @retval Returned value can be one of the following values:
00588   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00589   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00590   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00591   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00592   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00593   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00594   *         @arg @ref LL_DMAMUX_REQ_ADC1
00595   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
00596   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
00597   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
00598   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
00599   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00600   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00601   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00602   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00603   *         @arg @ref LL_DMAMUX_REQ_SPI3_RX
00604   *         @arg @ref LL_DMAMUX_REQ_SPI3_TX
00605   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00606   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00607   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
00608   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
00609   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
00610   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
00611   *         @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
00612   *         @arg @ref LL_DMAMUX_REQ_I2C4_TX
00613   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00614   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00615   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
00616   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
00617   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
00618   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
00619   *         @arg @ref LL_DMAMUX_REQ_UART4_RX
00620   *         @arg @ref LL_DMAMUX_REQ_UART4_TX
00621   *         @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
00622   *         @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
00623   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00624   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00625   *         @arg @ref LL_DMAMUX_REQ_ADC2
00626   *         @arg @ref LL_DMAMUX_REQ_ADC3 (*)
00627   *         @arg @ref LL_DMAMUX_REQ_ADC4 (*)
00628   *         @arg @ref LL_DMAMUX_REQ_ADC5 (*)
00629   *         @arg @ref LL_DMAMUX_REQ_QSPI (*)
00630   *         @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
00631   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00632   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00633   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00634   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00635   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00636   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
00637   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
00638   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1
00639   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2
00640   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3
00641   *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4
00642   *         @arg @ref LL_DMAMUX_REQ_TIM8_UP
00643   *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
00644   *         @arg @ref LL_DMAMUX_REQ_TIM8_COM
00645   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00646   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00647   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00648   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00649   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00650   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
00651   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
00652   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
00653   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
00654   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
00655   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
00656   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1
00657   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2
00658   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3
00659   *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4
00660   *         @arg @ref LL_DMAMUX_REQ_TIM4_UP
00661   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
00662   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
00663   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
00664   *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
00665   *         @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
00666   *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
00667   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
00668   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
00669   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
00670   *         @arg @ref LL_DMAMUX_REQ_TIM15_COM
00671   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00672   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00673   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00674   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00675   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
00676   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
00677   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
00678   *         @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
00679   *         @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
00680   *         @arg @ref LL_DMAMUX_REQ_AES_IN
00681   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
00682   *         @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
00683   *         @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
00684   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
00685   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
00686   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
00687   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
00688   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
00689   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
00690   *         @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
00691   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH1
00692   *         @arg @ref LL_DMAMUX_REQ_DAC3_CH2
00693   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
00694   *         @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
00695   *         @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
00696   *         @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
00697   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
00698   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
00699   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
00700   *         @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
00701   *         @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
00702   *         @arg @ref LL_DMAMUX_REQ_CORDIC_READ
00703   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
00704   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
00705   *         (*) Not on all G4 devices
00706   */
00707 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00708 {
00709   (void)(DMAMUXx);
00710   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
00711 }
00712
00713 /**
00714   * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00715   * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
00716   * @param  DMAMUXx DMAMUXx Instance
00717   * @param  Channel This parameter can be one of the following values:
00718   *         @arg @ref LL_DMAMUX_CHANNEL_0
00719   *         @arg @ref LL_DMAMUX_CHANNEL_1
00720   *         @arg @ref LL_DMAMUX_CHANNEL_2
00721   *         @arg @ref LL_DMAMUX_CHANNEL_3
00722   *         @arg @ref LL_DMAMUX_CHANNEL_4
00723   *         @arg @ref LL_DMAMUX_CHANNEL_5
00724   *         @arg @ref LL_DMAMUX_CHANNEL_6
00725   *         @arg @ref LL_DMAMUX_CHANNEL_7
00726   *         @arg @ref LL_DMAMUX_CHANNEL_8
00727   *         @arg @ref LL_DMAMUX_CHANNEL_9
00728   *         @arg @ref LL_DMAMUX_CHANNEL_10
00729   *         @arg @ref LL_DMAMUX_CHANNEL_11
00730   *         @arg @ref LL_DMAMUX_CHANNEL_12
00731   *         @arg @ref LL_DMAMUX_CHANNEL_13
00732   *         @arg @ref LL_DMAMUX_CHANNEL_14
00733   *         @arg @ref LL_DMAMUX_CHANNEL_15
00734   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
00738 {
00739   (void)(DMAMUXx);
00740   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
00741 }
00742
00743 /**
00744   * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00745   * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
00746   * @param  DMAMUXx DMAMUXx Instance
00747   * @param  Channel This parameter can be one of the following values:
00748   *         @arg @ref LL_DMAMUX_CHANNEL_0
00749   *         @arg @ref LL_DMAMUX_CHANNEL_1
00750   *         @arg @ref LL_DMAMUX_CHANNEL_2
00751   *         @arg @ref LL_DMAMUX_CHANNEL_3
00752   *         @arg @ref LL_DMAMUX_CHANNEL_4
00753   *         @arg @ref LL_DMAMUX_CHANNEL_5
00754   *         @arg @ref LL_DMAMUX_CHANNEL_6
00755   *         @arg @ref LL_DMAMUX_CHANNEL_7
00756   *         @arg @ref LL_DMAMUX_CHANNEL_8
00757   *         @arg @ref LL_DMAMUX_CHANNEL_9
00758   *         @arg @ref LL_DMAMUX_CHANNEL_10
00759   *         @arg @ref LL_DMAMUX_CHANNEL_11
00760   *         @arg @ref LL_DMAMUX_CHANNEL_12
00761   *         @arg @ref LL_DMAMUX_CHANNEL_13
00762   *         @arg @ref LL_DMAMUX_CHANNEL_14
00763   *         @arg @ref LL_DMAMUX_CHANNEL_15
00764   * @retval Between Min_Data = 1 and Max_Data = 32
00765   */
00766 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00767 {
00768   (void)(DMAMUXx);
00769   return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
00770 }
00771
00772 /**
00773   * @brief  Set the polarity of the signal on which the DMA request is synchronized.
00774   * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
00775   * @param  DMAMUXx DMAMUXx Instance
00776   * @param  Channel This parameter can be one of the following values:
00777   *         @arg @ref LL_DMAMUX_CHANNEL_0
00778   *         @arg @ref LL_DMAMUX_CHANNEL_1
00779   *         @arg @ref LL_DMAMUX_CHANNEL_2
00780   *         @arg @ref LL_DMAMUX_CHANNEL_3
00781   *         @arg @ref LL_DMAMUX_CHANNEL_4
00782   *         @arg @ref LL_DMAMUX_CHANNEL_5
00783   *         @arg @ref LL_DMAMUX_CHANNEL_6
00784   *         @arg @ref LL_DMAMUX_CHANNEL_7
00785   *         @arg @ref LL_DMAMUX_CHANNEL_8
00786   *         @arg @ref LL_DMAMUX_CHANNEL_9
00787   *         @arg @ref LL_DMAMUX_CHANNEL_10
00788   *         @arg @ref LL_DMAMUX_CHANNEL_11
00789   *         @arg @ref LL_DMAMUX_CHANNEL_12
00790   *         @arg @ref LL_DMAMUX_CHANNEL_13
00791   *         @arg @ref LL_DMAMUX_CHANNEL_14
00792   *         @arg @ref LL_DMAMUX_CHANNEL_15
00793   * @param  Polarity This parameter can be one of the following values:
00794   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00795   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00796   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00797   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
00801 {
00802   (void)(DMAMUXx);
00803   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
00804 }
00805
00806 /**
00807   * @brief  Get the polarity of the signal on which the DMA request is synchronized.
00808   * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
00809   * @param  DMAMUXx DMAMUXx Instance
00810   * @param  Channel This parameter can be one of the following values:
00811   *         @arg @ref LL_DMAMUX_CHANNEL_0
00812   *         @arg @ref LL_DMAMUX_CHANNEL_1
00813   *         @arg @ref LL_DMAMUX_CHANNEL_2
00814   *         @arg @ref LL_DMAMUX_CHANNEL_3
00815   *         @arg @ref LL_DMAMUX_CHANNEL_4
00816   *         @arg @ref LL_DMAMUX_CHANNEL_5
00817   *         @arg @ref LL_DMAMUX_CHANNEL_6
00818   *         @arg @ref LL_DMAMUX_CHANNEL_7
00819   *         @arg @ref LL_DMAMUX_CHANNEL_8
00820   *         @arg @ref LL_DMAMUX_CHANNEL_9
00821   *         @arg @ref LL_DMAMUX_CHANNEL_10
00822   *         @arg @ref LL_DMAMUX_CHANNEL_11
00823   *         @arg @ref LL_DMAMUX_CHANNEL_12
00824   *         @arg @ref LL_DMAMUX_CHANNEL_13
00825   *         @arg @ref LL_DMAMUX_CHANNEL_14
00826   *         @arg @ref LL_DMAMUX_CHANNEL_15
00827   * @retval Returned value can be one of the following values:
00828   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00829   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00830   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00831   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00832   */
00833 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00834 {
00835   (void)(DMAMUXx);
00836   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
00837 }
00838
00839 /**
00840   * @brief  Enable the Event Generation on DMAMUX channel x.
00841   * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
00842   * @param  DMAMUXx DMAMUXx Instance
00843   * @param  Channel This parameter can be one of the following values:
00844   *         @arg @ref LL_DMAMUX_CHANNEL_0
00845   *         @arg @ref LL_DMAMUX_CHANNEL_1
00846   *         @arg @ref LL_DMAMUX_CHANNEL_2
00847   *         @arg @ref LL_DMAMUX_CHANNEL_3
00848   *         @arg @ref LL_DMAMUX_CHANNEL_4
00849   *         @arg @ref LL_DMAMUX_CHANNEL_5
00850   *         @arg @ref LL_DMAMUX_CHANNEL_6
00851   *         @arg @ref LL_DMAMUX_CHANNEL_7
00852   *         @arg @ref LL_DMAMUX_CHANNEL_8
00853   *         @arg @ref LL_DMAMUX_CHANNEL_9
00854   *         @arg @ref LL_DMAMUX_CHANNEL_10
00855   *         @arg @ref LL_DMAMUX_CHANNEL_11
00856   *         @arg @ref LL_DMAMUX_CHANNEL_12
00857   *         @arg @ref LL_DMAMUX_CHANNEL_13
00858   *         @arg @ref LL_DMAMUX_CHANNEL_14
00859   *         @arg @ref LL_DMAMUX_CHANNEL_15
00860   * @retval None
00861   */
00862 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00863 {
00864   (void)(DMAMUXx);
00865   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00866 }
00867
00868 /**
00869   * @brief  Disable the Event Generation on DMAMUX channel x.
00870   * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
00871   * @param  DMAMUXx DMAMUXx Instance
00872   * @param  Channel This parameter can be one of the following values:
00873   *         @arg @ref LL_DMAMUX_CHANNEL_0
00874   *         @arg @ref LL_DMAMUX_CHANNEL_1
00875   *         @arg @ref LL_DMAMUX_CHANNEL_2
00876   *         @arg @ref LL_DMAMUX_CHANNEL_3
00877   *         @arg @ref LL_DMAMUX_CHANNEL_4
00878   *         @arg @ref LL_DMAMUX_CHANNEL_5
00879   *         @arg @ref LL_DMAMUX_CHANNEL_6
00880   *         @arg @ref LL_DMAMUX_CHANNEL_7
00881   *         @arg @ref LL_DMAMUX_CHANNEL_8
00882   *         @arg @ref LL_DMAMUX_CHANNEL_9
00883   *         @arg @ref LL_DMAMUX_CHANNEL_10
00884   *         @arg @ref LL_DMAMUX_CHANNEL_11
00885   *         @arg @ref LL_DMAMUX_CHANNEL_12
00886   *         @arg @ref LL_DMAMUX_CHANNEL_13
00887   *         @arg @ref LL_DMAMUX_CHANNEL_14
00888   *         @arg @ref LL_DMAMUX_CHANNEL_15
00889   * @retval None
00890   */
00891 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00892 {
00893   (void)(DMAMUXx);
00894   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00895 }
00896
00897 /**
00898   * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
00899   * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
00900   * @param  DMAMUXx DMAMUXx Instance
00901   * @param  Channel This parameter can be one of the following values:
00902   *         @arg @ref LL_DMAMUX_CHANNEL_0
00903   *         @arg @ref LL_DMAMUX_CHANNEL_1
00904   *         @arg @ref LL_DMAMUX_CHANNEL_2
00905   *         @arg @ref LL_DMAMUX_CHANNEL_3
00906   *         @arg @ref LL_DMAMUX_CHANNEL_4
00907   *         @arg @ref LL_DMAMUX_CHANNEL_5
00908   *         @arg @ref LL_DMAMUX_CHANNEL_6
00909   *         @arg @ref LL_DMAMUX_CHANNEL_7
00910   *         @arg @ref LL_DMAMUX_CHANNEL_8
00911   *         @arg @ref LL_DMAMUX_CHANNEL_9
00912   *         @arg @ref LL_DMAMUX_CHANNEL_10
00913   *         @arg @ref LL_DMAMUX_CHANNEL_11
00914   *         @arg @ref LL_DMAMUX_CHANNEL_12
00915   *         @arg @ref LL_DMAMUX_CHANNEL_13
00916   *         @arg @ref LL_DMAMUX_CHANNEL_14
00917   *         @arg @ref LL_DMAMUX_CHANNEL_15
00918   * @retval State of bit (1 or 0).
00919   */
00920 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00921 {
00922   (void)(DMAMUXx);
00923   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
00924 }
00925
00926 /**
00927   * @brief  Enable the synchronization mode.
00928   * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
00929   * @param  DMAMUXx DMAMUXx Instance
00930   * @param  Channel This parameter can be one of the following values:
00931   *         @arg @ref LL_DMAMUX_CHANNEL_0
00932   *         @arg @ref LL_DMAMUX_CHANNEL_1
00933   *         @arg @ref LL_DMAMUX_CHANNEL_2
00934   *         @arg @ref LL_DMAMUX_CHANNEL_3
00935   *         @arg @ref LL_DMAMUX_CHANNEL_4
00936   *         @arg @ref LL_DMAMUX_CHANNEL_5
00937   *         @arg @ref LL_DMAMUX_CHANNEL_6
00938   *         @arg @ref LL_DMAMUX_CHANNEL_7
00939   *         @arg @ref LL_DMAMUX_CHANNEL_8
00940   *         @arg @ref LL_DMAMUX_CHANNEL_9
00941   *         @arg @ref LL_DMAMUX_CHANNEL_10
00942   *         @arg @ref LL_DMAMUX_CHANNEL_11
00943   *         @arg @ref LL_DMAMUX_CHANNEL_12
00944   *         @arg @ref LL_DMAMUX_CHANNEL_13
00945   *         @arg @ref LL_DMAMUX_CHANNEL_14
00946   *         @arg @ref LL_DMAMUX_CHANNEL_15
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00950 {
00951   (void)(DMAMUXx);
00952   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00953 }
00954
00955 /**
00956   * @brief  Disable the synchronization mode.
00957   * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
00958   * @param  DMAMUXx DMAMUXx Instance
00959   * @param  Channel This parameter can be one of the following values:
00960   *         @arg @ref LL_DMAMUX_CHANNEL_0
00961   *         @arg @ref LL_DMAMUX_CHANNEL_1
00962   *         @arg @ref LL_DMAMUX_CHANNEL_2
00963   *         @arg @ref LL_DMAMUX_CHANNEL_3
00964   *         @arg @ref LL_DMAMUX_CHANNEL_4
00965   *         @arg @ref LL_DMAMUX_CHANNEL_5
00966   *         @arg @ref LL_DMAMUX_CHANNEL_6
00967   *         @arg @ref LL_DMAMUX_CHANNEL_7
00968   *         @arg @ref LL_DMAMUX_CHANNEL_8
00969   *         @arg @ref LL_DMAMUX_CHANNEL_9
00970   *         @arg @ref LL_DMAMUX_CHANNEL_10
00971   *         @arg @ref LL_DMAMUX_CHANNEL_11
00972   *         @arg @ref LL_DMAMUX_CHANNEL_12
00973   *         @arg @ref LL_DMAMUX_CHANNEL_13
00974   *         @arg @ref LL_DMAMUX_CHANNEL_14
00975   *         @arg @ref LL_DMAMUX_CHANNEL_15
00976   * @retval None
00977   */
00978 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00979 {
00980   (void)(DMAMUXx);
00981   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00982 }
00983
00984 /**
00985   * @brief  Check if the synchronization mode is enabled or disabled.
00986   * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
00987   * @param  DMAMUXx DMAMUXx Instance
00988   * @param  Channel This parameter can be one of the following values:
00989   *         @arg @ref LL_DMAMUX_CHANNEL_0
00990   *         @arg @ref LL_DMAMUX_CHANNEL_1
00991   *         @arg @ref LL_DMAMUX_CHANNEL_2
00992   *         @arg @ref LL_DMAMUX_CHANNEL_3
00993   *         @arg @ref LL_DMAMUX_CHANNEL_4
00994   *         @arg @ref LL_DMAMUX_CHANNEL_5
00995   *         @arg @ref LL_DMAMUX_CHANNEL_6
00996   *         @arg @ref LL_DMAMUX_CHANNEL_7
00997   *         @arg @ref LL_DMAMUX_CHANNEL_8
00998   *         @arg @ref LL_DMAMUX_CHANNEL_9
00999   *         @arg @ref LL_DMAMUX_CHANNEL_10
01000   *         @arg @ref LL_DMAMUX_CHANNEL_11
01001   *         @arg @ref LL_DMAMUX_CHANNEL_12
01002   *         @arg @ref LL_DMAMUX_CHANNEL_13
01003   *         @arg @ref LL_DMAMUX_CHANNEL_14
01004   *         @arg @ref LL_DMAMUX_CHANNEL_15
01005   * @retval State of bit (1 or 0).
01006   */
01007 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01008 {
01009   (void)(DMAMUXx);
01010   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
01011 }
01012
01013 /**
01014   * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
01015   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
01016   * @param  DMAMUXx DMAMUXx Instance
01017   * @param  Channel This parameter can be one of the following values:
01018   *         @arg @ref LL_DMAMUX_CHANNEL_0
01019   *         @arg @ref LL_DMAMUX_CHANNEL_1
01020   *         @arg @ref LL_DMAMUX_CHANNEL_2
01021   *         @arg @ref LL_DMAMUX_CHANNEL_3
01022   *         @arg @ref LL_DMAMUX_CHANNEL_4
01023   *         @arg @ref LL_DMAMUX_CHANNEL_5
01024   *         @arg @ref LL_DMAMUX_CHANNEL_6
01025   *         @arg @ref LL_DMAMUX_CHANNEL_7
01026   *         @arg @ref LL_DMAMUX_CHANNEL_8
01027   *         @arg @ref LL_DMAMUX_CHANNEL_9
01028   *         @arg @ref LL_DMAMUX_CHANNEL_10
01029   *         @arg @ref LL_DMAMUX_CHANNEL_11
01030   *         @arg @ref LL_DMAMUX_CHANNEL_12
01031   *         @arg @ref LL_DMAMUX_CHANNEL_13
01032   *         @arg @ref LL_DMAMUX_CHANNEL_14
01033   *         @arg @ref LL_DMAMUX_CHANNEL_15
01034   * @param  SyncID This parameter can be one of the following values:
01035   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
01036   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
01037   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
01038   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
01039   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
01040   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
01041   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
01042   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
01043   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
01044   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
01045   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
01046   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
01047   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
01048   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
01049   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
01050   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
01051   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
01052   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
01053   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
01054   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
01055   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
01056   * @retval None
01057   */
01058 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
01059 {
01060   (void)(DMAMUXx);
01061   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
01062 }
01063
01064 /**
01065   * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
01066   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
01067   * @param  DMAMUXx DMAMUXx Instance
01068   * @param  Channel This parameter can be one of the following values:
01069   *         @arg @ref LL_DMAMUX_CHANNEL_0
01070   *         @arg @ref LL_DMAMUX_CHANNEL_1
01071   *         @arg @ref LL_DMAMUX_CHANNEL_2
01072   *         @arg @ref LL_DMAMUX_CHANNEL_3
01073   *         @arg @ref LL_DMAMUX_CHANNEL_4
01074   *         @arg @ref LL_DMAMUX_CHANNEL_5
01075   *         @arg @ref LL_DMAMUX_CHANNEL_6
01076   *         @arg @ref LL_DMAMUX_CHANNEL_7
01077   *         @arg @ref LL_DMAMUX_CHANNEL_8
01078   *         @arg @ref LL_DMAMUX_CHANNEL_9
01079   *         @arg @ref LL_DMAMUX_CHANNEL_10
01080   *         @arg @ref LL_DMAMUX_CHANNEL_11
01081   *         @arg @ref LL_DMAMUX_CHANNEL_12
01082   *         @arg @ref LL_DMAMUX_CHANNEL_13
01083   *         @arg @ref LL_DMAMUX_CHANNEL_14
01084   *         @arg @ref LL_DMAMUX_CHANNEL_15
01085   * @retval Returned value can be one of the following values:
01086   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
01087   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
01088   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
01089   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
01090   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
01091   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
01092   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
01093   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
01094   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
01095   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
01096   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
01097   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
01098   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
01099   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
01100   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
01101   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
01102   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
01103   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
01104   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
01105   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
01106   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
01107   */
01108 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01109 {
01110   (void)(DMAMUXx);
01111   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
01112 }
01113
01114 /**
01115   * @brief  Enable the Request Generator.
01116   * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
01117   * @param  DMAMUXx DMAMUXx Instance
01118   * @param  RequestGenChannel This parameter can be one of the following values:
01119   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01120   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01121   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01122   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01126 {
01127   (void)(DMAMUXx);
01128   SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
01129 }
01130
01131 /**
01132   * @brief  Disable the Request Generator.
01133   * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
01134   * @param  DMAMUXx DMAMUXx Instance
01135   * @param  RequestGenChannel This parameter can be one of the following values:
01136   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01137   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01138   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01139   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01143 {
01144   (void)(DMAMUXx);
01145   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
01146 }
01147
01148 /**
01149   * @brief  Check if the Request Generator is enabled or disabled.
01150   * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
01151   * @param  DMAMUXx DMAMUXx Instance
01152   * @param  RequestGenChannel This parameter can be one of the following values:
01153   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01154   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01155   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01156   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01157   * @retval State of bit (1 or 0).
01158   */
01159 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01160 {
01161   (void)(DMAMUXx);
01162   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
01163 }
01164
01165 /**
01166   * @brief  Set the polarity of the signal on which the DMA request is generated.
01167   * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
01168   * @param  DMAMUXx DMAMUXx Instance
01169   * @param  RequestGenChannel This parameter can be one of the following values:
01170   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01171   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01172   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01173   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01174   * @param  Polarity This parameter can be one of the following values:
01175   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01176   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01177   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01178   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01179   * @retval None
01180   */
01181 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01182                                                      uint32_t Polarity)
01183 {
01184   UNUSED(DMAMUXx);
01185   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01186                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
01187 }
01188
01189 /**
01190   * @brief  Get the polarity of the signal on which the DMA request is generated.
01191   * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
01192   * @param  DMAMUXx DMAMUXx Instance
01193   * @param  RequestGenChannel This parameter can be one of the following values:
01194   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01195   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01196   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01197   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01198   * @retval Returned value can be one of the following values:
01199   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01200   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01201   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01202   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01203   */
01204 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01205 {
01206   UNUSED(DMAMUXx);
01207   return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01208                                                              (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
01209 }
01210
01211 /**
01212   * @brief  Set the number of DMA request that will be autorized after a generation event.
01213   * @note   This field can only be written when Generator is disabled.
01214   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
01215   * @param  DMAMUXx DMAMUXx Instance
01216   * @param  RequestGenChannel This parameter can be one of the following values:
01217   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01218   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01219   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01220   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01221   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
01222   * @retval None
01223   */
01224 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01225                                                uint32_t RequestNb)
01226 {
01227   UNUSED(DMAMUXx);
01228   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01229                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
01230 }
01231
01232 /**
01233   * @brief  Get the number of DMA request that will be autorized after a generation event.
01234   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
01235   * @param  DMAMUXx DMAMUXx Instance
01236   * @param  RequestGenChannel This parameter can be one of the following values:
01237   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01238   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01239   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01240   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01241   * @retval Between Min_Data = 1 and Max_Data = 32
01242   */
01243 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01244 {
01245   UNUSED(DMAMUXx);
01246   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01247                                                               (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
01248 }
01249
01250 /**
01251   * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
01252   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
01253   * @param  DMAMUXx DMAMUXx Instance
01254   * @param  RequestGenChannel This parameter can be one of the following values:
01255   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01256   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01257   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01258   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01259   * @param  RequestSignalID This parameter can be one of the following values:
01260   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01261   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01262   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01263   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01264   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01265   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01266   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01267   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01268   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01269   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01270   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01271   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01272   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01273   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01274   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01275   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01276   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01277   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01278   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
01279   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
01280   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01281   * @retval None
01282   */
01283 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01284                                                   uint32_t RequestSignalID)
01285 {
01286   UNUSED(DMAMUXx);
01287   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01288                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
01289 }
01290
01291 /**
01292   * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
01293   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
01294   * @param  DMAMUXx DMAMUXx Instance
01295   * @param  RequestGenChannel This parameter can be one of the following values:
01296   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01297   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01298   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01299   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01300   * @retval Returned value can be one of the following values:
01301   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01302   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01303   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01304   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01305   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01306   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01307   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01308   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01309   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01310   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01311   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01312   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01313   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01314   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01315   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01316   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01317   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01318   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01319   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
01320   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
01321   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01322   */
01323 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01324 {
01325   UNUSED(DMAMUXx);
01326   return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01327                                                              (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
01328 }
01329
01330 /**
01331   * @}
01332   */
01333
01334 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
01335   * @{
01336   */
01337
01338 /**
01339   * @brief  Get Synchronization Event Overrun Flag Channel 0.
01340   * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
01341   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01342   * @retval State of bit (1 or 0).
01343   */
01344 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01345 {
01346   UNUSED(DMAMUXx);
01347   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
01348 }
01349
01350 /**
01351   * @brief  Get Synchronization Event Overrun Flag Channel 1.
01352   * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
01353   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01354   * @retval State of bit (1 or 0).
01355   */
01356 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01357 {
01358   UNUSED(DMAMUXx);
01359   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
01360 }
01361
01362 /**
01363   * @brief  Get Synchronization Event Overrun Flag Channel 2.
01364   * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
01365   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01366   * @retval State of bit (1 or 0).
01367   */
01368 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01369 {
01370   UNUSED(DMAMUXx);
01371   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
01372 }
01373
01374 /**
01375   * @brief  Get Synchronization Event Overrun Flag Channel 3.
01376   * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
01377   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01378   * @retval State of bit (1 or 0).
01379   */
01380 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01381 {
01382   UNUSED(DMAMUXx);
01383   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
01384 }
01385
01386 /**
01387   * @brief  Get Synchronization Event Overrun Flag Channel 4.
01388   * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
01389   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01390   * @retval State of bit (1 or 0).
01391   */
01392 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01393 {
01394   UNUSED(DMAMUXx);
01395   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
01396 }
01397
01398 /**
01399   * @brief  Get Synchronization Event Overrun Flag Channel 5.
01400   * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
01401   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01402   * @retval State of bit (1 or 0).
01403   */
01404 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01405 {
01406   UNUSED(DMAMUXx);
01407   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
01408 }
01409
01410 /**
01411   * @brief  Get Synchronization Event Overrun Flag Channel 6.
01412   * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
01413   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01414   * @retval State of bit (1 or 0).
01415   */
01416 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01417 {
01418   UNUSED(DMAMUXx);
01419   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
01420 }
01421
01422 /**
01423   * @brief  Get Synchronization Event Overrun Flag Channel 7.
01424   * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
01425   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01426   * @retval State of bit (1 or 0).
01427   */
01428 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01429 {
01430   UNUSED(DMAMUXx);
01431   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
01432 }
01433
01434 /**
01435   * @brief  Get Synchronization Event Overrun Flag Channel 8.
01436   * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
01437   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01438   * @retval State of bit (1 or 0).
01439   */
01440 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01441 {
01442   UNUSED(DMAMUXx);
01443   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
01444 }
01445
01446 /**
01447   * @brief  Get Synchronization Event Overrun Flag Channel 9.
01448   * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
01449   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01450   * @retval State of bit (1 or 0).
01451   */
01452 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01453 {
01454   UNUSED(DMAMUXx);
01455   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
01456 }
01457
01458 /**
01459   * @brief  Get Synchronization Event Overrun Flag Channel 10.
01460   * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
01461   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01462   * @retval State of bit (1 or 0).
01463   */
01464 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01465 {
01466   UNUSED(DMAMUXx);
01467   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
01468 }
01469
01470 /**
01471   * @brief  Get Synchronization Event Overrun Flag Channel 11.
01472   * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
01473   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01474   * @retval State of bit (1 or 0).
01475   */
01476 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01477 {
01478   UNUSED(DMAMUXx);
01479   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
01480 }
01481
01482 #if defined (DMAMUX_CSR_SOF12)
01483 /**
01484   * @brief  Get Synchronization Event Overrun Flag Channel 12.
01485   * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
01486   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01487   * @retval State of bit (1 or 0).
01488   */
01489 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
01490 {
01491   UNUSED(DMAMUXx);
01492   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
01493 }
01494 #endif /* DMAMUX_CSR_SOF12 */
01495
01496 #if defined (DMAMUX_CSR_SOF13)
01497 /**
01498   * @brief  Get Synchronization Event Overrun Flag Channel 13.
01499   * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
01500   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01501   * @retval State of bit (1 or 0).
01502   */
01503 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
01504 {
01505   UNUSED(DMAMUXx);
01506   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
01507 }
01508 #endif /* DMAMUX_CSR_SOF13 */
01509
01510 #if defined (DMAMUX_CSR_SOF14)
01511 /**
01512   * @brief  Get Synchronization Event Overrun Flag Channel 14.
01513   * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO14
01514   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01515   * @retval State of bit (1 or 0).
01516   */
01517 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
01518 {
01519   UNUSED(DMAMUXx);
01520   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
01521 }
01522 #endif /* DMAMUX_CSR_SOF14 */
01523
01524 #if defined (DMAMUX_CSR_SOF15)
01525 /**
01526   * @brief  Get Synchronization Event Overrun Flag Channel 15.
01527   * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO15
01528   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01529   * @retval State of bit (1 or 0).
01530   */
01531 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
01532 {
01533   UNUSED(DMAMUXx);
01534   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
01535 }
01536 #endif /* DMAMUX_CSR_SOF15 */
01537
01538 /**
01539   * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
01540   * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
01541   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01542   * @retval State of bit (1 or 0).
01543   */
01544 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01545 {
01546   UNUSED(DMAMUXx);
01547   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
01548 }
01549
01550 /**
01551   * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
01552   * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
01553   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01554   * @retval State of bit (1 or 0).
01555   */
01556 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01557 {
01558   UNUSED(DMAMUXx);
01559   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
01560 }
01561
01562 /**
01563   * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
01564   * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
01565   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01566   * @retval State of bit (1 or 0).
01567   */
01568 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01569 {
01570   UNUSED(DMAMUXx);
01571   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
01572 }
01573
01574 /**
01575   * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
01576   * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
01577   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01578   * @retval State of bit (1 or 0).
01579   */
01580 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01581 {
01582   UNUSED(DMAMUXx);
01583   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
01584 }
01585
01586 /**
01587   * @brief  Clear Synchronization Event Overrun Flag Channel 0.
01588   * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
01589   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01590   * @retval None
01591   */
01592 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01593 {
01594   UNUSED(DMAMUXx);
01595   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
01596 }
01597
01598 /**
01599   * @brief  Clear Synchronization Event Overrun Flag Channel 1.
01600   * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
01601   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01602   * @retval None
01603   */
01604 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01605 {
01606   UNUSED(DMAMUXx);
01607   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
01608 }
01609
01610 /**
01611   * @brief  Clear Synchronization Event Overrun Flag Channel 2.
01612   * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
01613   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01614   * @retval None
01615   */
01616 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01617 {
01618   UNUSED(DMAMUXx);
01619   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
01620 }
01621
01622 /**
01623   * @brief  Clear Synchronization Event Overrun Flag Channel 3.
01624   * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
01625   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01626   * @retval None
01627   */
01628 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01629 {
01630   UNUSED(DMAMUXx);
01631   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
01632 }
01633
01634 /**
01635   * @brief  Clear Synchronization Event Overrun Flag Channel 4.
01636   * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
01637   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01638   * @retval None
01639   */
01640 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01641 {
01642   UNUSED(DMAMUXx);
01643   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
01644 }
01645
01646 /**
01647   * @brief  Clear Synchronization Event Overrun Flag Channel 5.
01648   * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
01649   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01650   * @retval None
01651   */
01652 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01653 {
01654   UNUSED(DMAMUXx);
01655   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
01656 }
01657
01658 /**
01659   * @brief  Clear Synchronization Event Overrun Flag Channel 6.
01660   * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
01661   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01662   * @retval None
01663   */
01664 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01665 {
01666   UNUSED(DMAMUXx);
01667   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
01668 }
01669
01670 /**
01671   * @brief  Clear Synchronization Event Overrun Flag Channel 7.
01672   * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
01673   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01677 {
01678   UNUSED(DMAMUXx);
01679   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
01680 }
01681
01682 /**
01683   * @brief  Clear Synchronization Event Overrun Flag Channel 8.
01684   * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
01685   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01686   * @retval None
01687   */
01688 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01689 {
01690   UNUSED(DMAMUXx);
01691   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
01692 }
01693
01694 /**
01695   * @brief  Clear Synchronization Event Overrun Flag Channel 9.
01696   * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
01697   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01698   * @retval None
01699   */
01700 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01701 {
01702   UNUSED(DMAMUXx);
01703   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
01704 }
01705
01706 /**
01707   * @brief  Clear Synchronization Event Overrun Flag Channel 10.
01708   * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
01709   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01710   * @retval None
01711   */
01712 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01713 {
01714   UNUSED(DMAMUXx);
01715   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
01716 }
01717
01718 /**
01719   * @brief  Clear Synchronization Event Overrun Flag Channel 11.
01720   * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
01721   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01725 {
01726   UNUSED(DMAMUXx);
01727   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
01728 }
01729
01730 #if defined (DMAMUX_CFR_CSOF12)
01731 /**
01732   * @brief  Clear Synchronization Event Overrun Flag Channel 12.
01733   * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
01734   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
01738 {
01739   UNUSED(DMAMUXx);
01740   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
01741 }
01742 #endif /* DMAMUX_CFR_CSOF12 */
01743
01744 #if defined (DMAMUX_CFR_CSOF13)
01745 /**
01746   * @brief  Clear Synchronization Event Overrun Flag Channel 13.
01747   * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
01748   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01749   * @retval None
01750   */
01751 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
01752 {
01753   UNUSED(DMAMUXx);
01754   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
01755 }
01756 #endif /* DMAMUX_CFR_CSOF13 */
01757
01758 #if defined (DMAMUX_CFR_CSOF14)
01759 /**
01760   * @brief  Clear Synchronization Event Overrun Flag Channel 14.
01761   * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
01762   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01763   * @retval None
01764   */
01765 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
01766 {
01767   UNUSED(DMAMUXx);
01768   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14);
01769 }
01770 #endif /* DMAMUX_CFR_CSOF14 */
01771
01772 #if defined (DMAMUX_CFR_CSOF15)
01773 /**
01774   * @brief  Clear Synchronization Event Overrun Flag Channel 15.
01775   * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
01776   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01777   * @retval None
01778   */
01779 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
01780 {
01781   UNUSED(DMAMUXx);
01782   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15);
01783 }
01784 #endif /* DMAMUX_CFR_CSOF15 */
01785
01786 /**
01787   * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
01788   * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
01789   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01790   * @retval None
01791   */
01792 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01793 {
01794   UNUSED(DMAMUXx);
01795   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
01796 }
01797
01798 /**
01799   * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
01800   * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
01801   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01802   * @retval None
01803   */
01804 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01805 {
01806   UNUSED(DMAMUXx);
01807   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
01808 }
01809
01810 /**
01811   * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
01812   * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
01813   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01814   * @retval None
01815   */
01816 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01817 {
01818   UNUSED(DMAMUXx);
01819   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
01820 }
01821
01822 /**
01823   * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
01824   * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
01825   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01826   * @retval None
01827   */
01828 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01829 {
01830   UNUSED(DMAMUXx);
01831   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
01832 }
01833
01834 /**
01835   * @}
01836   */
01837
01838 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
01839   * @{
01840   */
01841
01842 /**
01843   * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01844   * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
01845   * @param  DMAMUXx DMAMUXx Instance
01846   * @param  Channel This parameter can be one of the following values:
01847   *         @arg @ref LL_DMAMUX_CHANNEL_0
01848   *         @arg @ref LL_DMAMUX_CHANNEL_1
01849   *         @arg @ref LL_DMAMUX_CHANNEL_2
01850   *         @arg @ref LL_DMAMUX_CHANNEL_3
01851   *         @arg @ref LL_DMAMUX_CHANNEL_4
01852   *         @arg @ref LL_DMAMUX_CHANNEL_5
01853   *         @arg @ref LL_DMAMUX_CHANNEL_6
01854   *         @arg @ref LL_DMAMUX_CHANNEL_7
01855   *         @arg @ref LL_DMAMUX_CHANNEL_8
01856   *         @arg @ref LL_DMAMUX_CHANNEL_9
01857   *         @arg @ref LL_DMAMUX_CHANNEL_10
01858   *         @arg @ref LL_DMAMUX_CHANNEL_11
01859   *         @arg @ref LL_DMAMUX_CHANNEL_12
01860   *         @arg @ref LL_DMAMUX_CHANNEL_13
01861   *         @arg @ref LL_DMAMUX_CHANNEL_14
01862   *         @arg @ref LL_DMAMUX_CHANNEL_15
01863   * @retval None
01864   */
01865 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01866 {
01867   (void)(DMAMUXx);
01868   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01869 }
01870
01871 /**
01872   * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01873   * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
01874   * @param  DMAMUXx DMAMUXx Instance
01875   * @param  Channel This parameter can be one of the following values:
01876   *         @arg @ref LL_DMAMUX_CHANNEL_0
01877   *         @arg @ref LL_DMAMUX_CHANNEL_1
01878   *         @arg @ref LL_DMAMUX_CHANNEL_2
01879   *         @arg @ref LL_DMAMUX_CHANNEL_3
01880   *         @arg @ref LL_DMAMUX_CHANNEL_4
01881   *         @arg @ref LL_DMAMUX_CHANNEL_5
01882   *         @arg @ref LL_DMAMUX_CHANNEL_6
01883   *         @arg @ref LL_DMAMUX_CHANNEL_7
01884   *         @arg @ref LL_DMAMUX_CHANNEL_8
01885   *         @arg @ref LL_DMAMUX_CHANNEL_9
01886   *         @arg @ref LL_DMAMUX_CHANNEL_10
01887   *         @arg @ref LL_DMAMUX_CHANNEL_11
01888   *         @arg @ref LL_DMAMUX_CHANNEL_12
01889   *         @arg @ref LL_DMAMUX_CHANNEL_13
01890   *         @arg @ref LL_DMAMUX_CHANNEL_14
01891   *         @arg @ref LL_DMAMUX_CHANNEL_15
01892   * @retval None
01893   */
01894 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01895 {
01896   (void)(DMAMUXx);
01897   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01898 }
01899
01900 /**
01901   * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01902   * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
01903   * @param  DMAMUXx DMAMUXx Instance
01904   * @param  Channel This parameter can be one of the following values:
01905   *         @arg @ref LL_DMAMUX_CHANNEL_0
01906   *         @arg @ref LL_DMAMUX_CHANNEL_1
01907   *         @arg @ref LL_DMAMUX_CHANNEL_2
01908   *         @arg @ref LL_DMAMUX_CHANNEL_3
01909   *         @arg @ref LL_DMAMUX_CHANNEL_4
01910   *         @arg @ref LL_DMAMUX_CHANNEL_5
01911   *         @arg @ref LL_DMAMUX_CHANNEL_6
01912   *         @arg @ref LL_DMAMUX_CHANNEL_7
01913   *         @arg @ref LL_DMAMUX_CHANNEL_8
01914   *         @arg @ref LL_DMAMUX_CHANNEL_9
01915   *         @arg @ref LL_DMAMUX_CHANNEL_10
01916   *         @arg @ref LL_DMAMUX_CHANNEL_11
01917   *         @arg @ref LL_DMAMUX_CHANNEL_12
01918   *         @arg @ref LL_DMAMUX_CHANNEL_13
01919   *         @arg @ref LL_DMAMUX_CHANNEL_14
01920   *         @arg @ref LL_DMAMUX_CHANNEL_15
01921   * @retval State of bit (1 or 0).
01922   */
01923 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01924 {
01925   (void)(DMAMUXx);
01926   return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
01927 }
01928
01929 /**
01930   * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01931   * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
01932   * @param  DMAMUXx DMAMUXx Instance
01933   * @param  RequestGenChannel This parameter can be one of the following values:
01934   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01935   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01936   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01937   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01938   * @retval None
01939   */
01940 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01941 {
01942   UNUSED(DMAMUXx);
01943   SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01944                                                     (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
01945 }
01946
01947 /**
01948   * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01949   * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
01950   * @param  DMAMUXx DMAMUXx Instance
01951   * @param  RequestGenChannel This parameter can be one of the following values:
01952   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01953   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01954   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01955   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01956   * @retval None
01957   */
01958 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01959 {
01960   UNUSED(DMAMUXx);
01961   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01962                                                       (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
01963 }
01964
01965 /**
01966   * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01967   * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
01968   * @param  DMAMUXx DMAMUXx Instance
01969   * @param  RequestGenChannel This parameter can be one of the following values:
01970   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01971   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01972   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01973   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01974   * @retval State of bit (1 or 0).
01975   */
01976 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01977 {
01978   UNUSED(DMAMUXx);
01979   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01980                                                               (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
01981 }
01982
01983 /**
01984   * @}
01985   */
01986
01987 /**
01988   * @}
01989   */
01990
01991 /**
01992   * @}
01993   */
01994
01995 #endif /* DMAMUX1 */
01996
01997 /**
01998   * @}
01999   */
02000
02001 #ifdef __cplusplus
02002 }
02003 #endif
02004
02005 #endif /* __STM32G4xx_LL_DMAMUX_H */
02006
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_exti.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_exti.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_exti.h"
00022 #ifdef  USE_FULL_ASSERT
00023 #include "stm32_assert.h"
00024 #else
00025 #define assert_param(expr) ((void)0U)
00026 #endif /* USE_FULL_ASSERT */
00027
00028 /** @addtogroup STM32G4xx_LL_Driver
00029   * @{
00030   */
00031
00032 #if defined (EXTI)
00033
00034 /** @defgroup EXTI_LL EXTI
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /** @addtogroup EXTI_LL_Private_Macros
00043   * @{
00044   */
00045
00046 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00047 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00048
00049 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00050                                                       || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00051                                                       || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00052
00053
00054 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00055                                                       || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00056                                                       || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00057                                                       || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00058
00059 /**
00060   * @}
00061   */
00062
00063 /* Private function prototypes -----------------------------------------------*/
00064
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup EXTI_LL_Exported_Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup EXTI_LL_EF_Init
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  De-initialize the EXTI registers to their default reset values.
00076   * @retval An ErrorStatus enumeration value:
00077   *          - 0x00: EXTI registers are de-initialized
00078   */
00079 uint32_t LL_EXTI_DeInit(void)
00080 {
00081   /* Interrupt mask register set to default reset values */
00082   LL_EXTI_WriteReg(IMR1,   0x1F840000U);
00083   /* Event mask register set to default reset values */
00084   LL_EXTI_WriteReg(EMR1,   0x00000000U);
00085   /* Rising Trigger selection register set to default reset values */
00086   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
00087   /* Falling Trigger selection register set to default reset values */
00088   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
00089   /* Software interrupt event register set to default reset values */
00090   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
00091   /* Pending register clear */
00092   LL_EXTI_WriteReg(PR1,    0x007DFFFFU);
00093
00094   /* Interrupt mask register 2 set to default reset values */
00095 #if defined(LL_EXTI_LINE_32) && defined(LL_EXTI_LINE_33) && defined(LL_EXTI_LINE_35) && defined(LL_EXTI_LINE_42)
00096   LL_EXTI_WriteReg(IMR2,        0x0000043CU);
00097 #else
00098   LL_EXTI_WriteReg(IMR2,        0x00000034U);
00099 #endif /* LL_EXTI_LINE_xx */
00100   /* Event mask register 2 set to default reset values */
00101   LL_EXTI_WriteReg(EMR2,        0x00000000U);
00102   /* Rising Trigger selection register 2 set to default reset values */
00103   LL_EXTI_WriteReg(RTSR2,       0x00000000U);
00104   /* Falling Trigger selection register 2 set to default reset values */
00105   LL_EXTI_WriteReg(FTSR2,       0x00000000U);
00106   /* Software interrupt event register 2 set to default reset values */
00107   LL_EXTI_WriteReg(SWIER2,      0x00000000U);
00108   /* Pending register 2 clear */
00109   LL_EXTI_WriteReg(PR2,         0x00000078U);
00110
00111   return 0x00u;
00112 }
00113
00114 /**
00115   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00116   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00117   * @retval An ErrorStatus enumeration value:
00118   *          - 0x00: EXTI registers are initialized
00119   *          - any other value : wrong configuration
00120   */
00121 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00122 {
00123   uint32_t status = 0x00u;
00124
00125   /* Check the parameters */
00126   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00127   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00128   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00129   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00130
00131   /* ENABLE LineCommand */
00132   if (EXTI_InitStruct->LineCommand != DISABLE)
00133   {
00134     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00135
00136     /* Configure EXTI Lines in range from 0 to 31 */
00137     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00138     {
00139       switch (EXTI_InitStruct->Mode)
00140       {
00141         case LL_EXTI_MODE_IT:
00142           /* First Disable Event on provided Lines */
00143           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00144           /* Then Enable IT on provided Lines */
00145           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00146           break;
00147         case LL_EXTI_MODE_EVENT:
00148           /* First Disable IT on provided Lines */
00149           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00150           /* Then Enable Event on provided Lines */
00151           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00152           break;
00153         case LL_EXTI_MODE_IT_EVENT:
00154           /* Directly Enable IT on provided Lines */
00155           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00156           /* Directly Enable Event on provided Lines */
00157           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00158           break;
00159         default:
00160           status = 0x01u;
00161           break;
00162       }
00163       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00164       {
00165         switch (EXTI_InitStruct->Trigger)
00166         {
00167           case LL_EXTI_TRIGGER_RISING:
00168             /* First Disable Falling Trigger on provided Lines */
00169             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00170             /* Then Enable Rising Trigger on provided Lines */
00171             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00172             break;
00173           case LL_EXTI_TRIGGER_FALLING:
00174             /* First Disable Rising Trigger on provided Lines */
00175             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00176             /* Then Enable Falling Trigger on provided Lines */
00177             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00178             break;
00179           case LL_EXTI_TRIGGER_RISING_FALLING:
00180             /* Enable Rising Trigger on provided Lines */
00181             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00182             /* Enable Falling Trigger on provided Lines */
00183             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00184             break;
00185           default:
00186             status |= 0x02u;
00187             break;
00188         }
00189       }
00190     }
00191     /* Configure EXTI Lines in range from 32 to 63 */
00192     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00193     {
00194       switch (EXTI_InitStruct->Mode)
00195       {
00196         case LL_EXTI_MODE_IT:
00197           /* First Disable Event on provided Lines */
00198           LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00199           /* Then Enable IT on provided Lines */
00200           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00201           break;
00202         case LL_EXTI_MODE_EVENT:
00203           /* First Disable IT on provided Lines */
00204           LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00205           /* Then Enable Event on provided Lines */
00206           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00207           break;
00208         case LL_EXTI_MODE_IT_EVENT:
00209           /* Directly Enable IT on provided Lines */
00210           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00211           /* Directly Enable IT on provided Lines */
00212           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00213           break;
00214         default:
00215           status |= 0x04u;
00216           break;
00217       }
00218       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00219       {
00220         switch (EXTI_InitStruct->Trigger)
00221         {
00222           case LL_EXTI_TRIGGER_RISING:
00223             /* First Disable Falling Trigger on provided Lines */
00224             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00225             /* Then Enable IT on provided Lines */
00226             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00227             break;
00228           case LL_EXTI_TRIGGER_FALLING:
00229             /* First Disable Rising Trigger on provided Lines */
00230             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00231             /* Then Enable Falling Trigger on provided Lines */
00232             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00233             break;
00234           case LL_EXTI_TRIGGER_RISING_FALLING:
00235             /* Enable Rising Trigger on provided Lines */
00236             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00237             /* Enable Falling Trigger on provided Lines */
00238             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00239             break;
00240           default:
00241             status |= 0x05u;
00242             break;
00243         }
00244       }
00245     }
00246   }
00247   /* DISABLE LineCommand */
00248   else
00249   {
00250     /* De-configure IT EXTI Lines in range from 0 to 31 */
00251     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00252     /* De-configure Event EXTI Lines in range from 0 to 31 */
00253     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00254     /* De-configure IT EXTI Lines in range from 32 to 63 */
00255     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00256     /* De-configure Event EXTI Lines in range from 32 to 63 */
00257     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00258   }
00259
00260   return status;
00261 }
00262
00263 /**
00264   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00265   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00266   * @retval None
00267   */
00268 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00269 {
00270   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00271   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00272   EXTI_InitStruct->LineCommand    = DISABLE;
00273   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00274   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00275 }
00276
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 #endif /* defined (EXTI) */
00290
00291 /**
00292   * @}
00293   */
00294
00295 #endif /* USE_FULL_LL_DRIVER */
00296
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_exti.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_exti.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_LL_EXTI_H
00021 #define __STM32G4xx_LL_EXTI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (EXTI)
00035
00036 /** @defgroup EXTI_LL EXTI
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private Macros ------------------------------------------------------------*/
00044 #if defined(USE_FULL_LL_DRIVER)
00045 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00046   * @{
00047   */
00048 /**
00049   * @}
00050   */
00051 #endif /*USE_FULL_LL_DRIVER*/
00052 /* Exported types ------------------------------------------------------------*/
00053 #if defined(USE_FULL_LL_DRIVER)
00054 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00055   * @{
00056   */
00057 typedef struct
00058 {
00059
00060   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00061                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00062
00063   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00064                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00065
00066   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00067                                      This parameter can be set either to ENABLE or DISABLE */
00068
00069   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00070                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00071
00072   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00073                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00074 } LL_EXTI_InitTypeDef;
00075
00076 /**
00077   * @}
00078   */
00079 #endif /*USE_FULL_LL_DRIVER*/
00080
00081 /* Exported constants --------------------------------------------------------*/
00082 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00083   * @{
00084   */
00085
00086 /** @defgroup EXTI_LL_EC_LINE LINE
00087   * @{
00088   */
00089 #define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
00090 #define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
00091 #define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
00092 #define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
00093 #define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
00094 #define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
00095 #define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
00096 #define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
00097 #define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
00098 #define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
00099 #define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
00100 #define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
00101 #define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
00102 #define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
00103 #define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
00104 #define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
00105 #if defined(EXTI_IMR1_IM16)
00106 #define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
00107 #endif /* EXTI_IMR1_IM16 */
00108 #define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
00109 #if defined(EXTI_IMR1_IM18)
00110 #define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
00111 #endif /* EXTI_IMR1_IM18 */
00112 #define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
00113 #if defined(EXTI_IMR1_IM20)
00114 #define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
00115 #endif /* EXTI_IMR1_IM20 */
00116 #if defined(EXTI_IMR1_IM21)
00117 #define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
00118 #endif /* EXTI_IMR1_IM21 */
00119 #if defined(EXTI_IMR1_IM22)
00120 #define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
00121 #endif /* EXTI_IMR1_IM22 */
00122 #define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
00123 #if defined(EXTI_IMR1_IM24)
00124 #define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
00125 #endif /* EXTI_IMR1_IM24 */
00126 #if defined(EXTI_IMR1_IM25)
00127 #define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
00128 #endif /* EXTI_IMR1_IM25 */
00129 #if defined(EXTI_IMR1_IM26)
00130 #define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
00131 #endif /* EXTI_IMR1_IM26 */
00132 #if defined(EXTI_IMR1_IM27)
00133 #define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
00134 #endif /* EXTI_IMR1_IM27 */
00135 #if defined(EXTI_IMR1_IM28)
00136 #define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
00137 #endif /* EXTI_IMR1_IM28 */
00138 #if defined(EXTI_IMR1_IM29)
00139 #define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
00140 #endif /* EXTI_IMR1_IM29 */
00141 #if defined(EXTI_IMR1_IM30)
00142 #define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
00143 #endif /* EXTI_IMR1_IM30 */
00144 #if defined(EXTI_IMR1_IM31)
00145 #define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
00146 #endif /* EXTI_IMR1_IM31 */
00147 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
00148
00149 #if defined(EXTI_IMR2_IM32)
00150 #define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
00151 #endif /* EXTI_IMR2_IM32 */
00152 #if defined(EXTI_IMR2_IM33)
00153 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00154 #endif /* EXTI_IMR2_IM33 */
00155 #if defined(EXTI_IMR2_IM34)
00156 #define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
00157 #endif /* EXTI_IMR2_IM34 */
00158 #if defined(EXTI_IMR2_IM35)
00159 #define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
00160 #endif /* EXTI_IMR2_IM35 */
00161 #if defined(EXTI_IMR2_IM36)
00162 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00163 #endif /* EXTI_IMR2_IM36 */
00164 #if defined(EXTI_IMR2_IM37)
00165 #define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
00166 #endif /* EXTI_IMR2_IM37 */
00167 #if defined(EXTI_IMR2_IM38)
00168 #define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
00169 #endif /* EXTI_IMR2_IM38 */
00170 #if defined(EXTI_IMR2_IM39)
00171 #define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
00172 #endif /* EXTI_IMR2_IM39 */
00173 #if defined(EXTI_IMR2_IM40)
00174 #define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
00175 #endif /* EXTI_IMR2_IM40 */
00176 #if defined(EXTI_IMR2_IM41)
00177 #define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
00178 #endif /* EXTI_IMR2_IM41 */
00179 #if defined(EXTI_IMR2_IM42)
00180 #define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
00181 #endif /* EXTI_IMR2_IM42 */
00182 #define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
00183
00184
00185 #define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
00186
00187 #if defined(USE_FULL_LL_DRIVER)
00188 #define LL_EXTI_LINE_NONE              0x00000000U             /*!< None Extended line */
00189 #endif /*USE_FULL_LL_DRIVER*/
00190
00191 /**
00192   * @}
00193   */
00194 #if defined(USE_FULL_LL_DRIVER)
00195
00196 /** @defgroup EXTI_LL_EC_MODE Mode
00197   * @{
00198   */
00199 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00200 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00201 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00207   * @{
00208   */
00209 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00210 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00211 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00212 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00213
00214 /**
00215   * @}
00216   */
00217
00218
00219 #endif /*USE_FULL_LL_DRIVER*/
00220
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Exported macro ------------------------------------------------------------*/
00227 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00228   * @{
00229   */
00230
00231 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Write a value in EXTI register
00237   * @param  __REG__ Register to be written
00238   * @param  __VALUE__ Value to be written in the register
00239   * @retval None
00240   */
00241 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00242
00243 /**
00244   * @brief  Read a value in EXTI register
00245   * @param  __REG__ Register to be read
00246   * @retval Register value
00247   */
00248 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00249 /**
00250   * @}
00251   */
00252
00253
00254 /**
00255   * @}
00256   */
00257
00258
00259
00260 /* Exported functions --------------------------------------------------------*/
00261 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00262   * @{
00263   */
00264 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00265   * @{
00266   */
00267
00268 /**
00269   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00270   * @note The reset value for the direct or internal lines (see RM)
00271   *       is set to 1 in order to enable the interrupt by default.
00272   *       Bits are set automatically at Power on.
00273   * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
00274   * @param  ExtiLine This parameter can be one of the following values:
00275   *         @arg @ref LL_EXTI_LINE_0
00276   *         @arg @ref LL_EXTI_LINE_1
00277   *         @arg @ref LL_EXTI_LINE_2
00278   *         @arg @ref LL_EXTI_LINE_3
00279   *         @arg @ref LL_EXTI_LINE_4
00280   *         @arg @ref LL_EXTI_LINE_5
00281   *         @arg @ref LL_EXTI_LINE_6
00282   *         @arg @ref LL_EXTI_LINE_7
00283   *         @arg @ref LL_EXTI_LINE_8
00284   *         @arg @ref LL_EXTI_LINE_9
00285   *         @arg @ref LL_EXTI_LINE_10
00286   *         @arg @ref LL_EXTI_LINE_11
00287   *         @arg @ref LL_EXTI_LINE_12
00288   *         @arg @ref LL_EXTI_LINE_13
00289   *         @arg @ref LL_EXTI_LINE_14
00290   *         @arg @ref LL_EXTI_LINE_15
00291   *         @arg @ref LL_EXTI_LINE_16
00292   *         @arg @ref LL_EXTI_LINE_17
00293   *         @arg @ref LL_EXTI_LINE_18
00294   *         @arg @ref LL_EXTI_LINE_19
00295   *         @arg @ref LL_EXTI_LINE_20
00296   *         @arg @ref LL_EXTI_LINE_21
00297   *         @arg @ref LL_EXTI_LINE_22
00298   *         @arg @ref LL_EXTI_LINE_23
00299   *         @arg @ref LL_EXTI_LINE_24
00300   *         @arg @ref LL_EXTI_LINE_25
00301   *         @arg @ref LL_EXTI_LINE_26
00302   *         @arg @ref LL_EXTI_LINE_27
00303   *         @arg @ref LL_EXTI_LINE_28
00304   *         @arg @ref LL_EXTI_LINE_29
00305   *         @arg @ref LL_EXTI_LINE_30
00306   *         @arg @ref LL_EXTI_LINE_31 (*)
00307   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00308   * @note   (*): Available in some devices
00309   * @note   Please check each device line mapping for EXTI Line availability
00310   * @retval None
00311   */
00312 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00313 {
00314   SET_BIT(EXTI->IMR1, ExtiLine);
00315 }
00316 /**
00317   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00318   * @note The reset value for the direct lines (lines from 32 to 34, line
00319   *       39) is set to 1 in order to enable the interrupt by default.
00320   *       Bits are set automatically at Power on.
00321   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00322   * @param  ExtiLine This parameter can be one of the following values:
00323   *         @arg @ref LL_EXTI_LINE_32 (*)
00324   *         @arg @ref LL_EXTI_LINE_33 (*)
00325   *         @arg @ref LL_EXTI_LINE_34
00326   *         @arg @ref LL_EXTI_LINE_35 (*)
00327   *         @arg @ref LL_EXTI_LINE_36
00328   *         @arg @ref LL_EXTI_LINE_37
00329   *         @arg @ref LL_EXTI_LINE_38
00330   *         @arg @ref LL_EXTI_LINE_39
00331   *         @arg @ref LL_EXTI_LINE_40
00332   *         @arg @ref LL_EXTI_LINE_41
00333   *         @arg @ref LL_EXTI_LINE_42(*)
00334   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00335   * @note   (*): Available in some devices
00336   * @retval None
00337   */
00338 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00339 {
00340   SET_BIT(EXTI->IMR2, ExtiLine);
00341 }
00342
00343 /**
00344   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00345   * @note The reset value for the direct or internal lines (see RM)
00346   *       is set to 1 in order to enable the interrupt by default.
00347   *       Bits are set automatically at Power on.
00348   * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
00349   * @param  ExtiLine This parameter can be one of the following values:
00350   *         @arg @ref LL_EXTI_LINE_0
00351   *         @arg @ref LL_EXTI_LINE_1
00352   *         @arg @ref LL_EXTI_LINE_2
00353   *         @arg @ref LL_EXTI_LINE_3
00354   *         @arg @ref LL_EXTI_LINE_4
00355   *         @arg @ref LL_EXTI_LINE_5
00356   *         @arg @ref LL_EXTI_LINE_6
00357   *         @arg @ref LL_EXTI_LINE_7
00358   *         @arg @ref LL_EXTI_LINE_8
00359   *         @arg @ref LL_EXTI_LINE_9
00360   *         @arg @ref LL_EXTI_LINE_10
00361   *         @arg @ref LL_EXTI_LINE_11
00362   *         @arg @ref LL_EXTI_LINE_12
00363   *         @arg @ref LL_EXTI_LINE_13
00364   *         @arg @ref LL_EXTI_LINE_14
00365   *         @arg @ref LL_EXTI_LINE_15
00366   *         @arg @ref LL_EXTI_LINE_16
00367   *         @arg @ref LL_EXTI_LINE_17
00368   *         @arg @ref LL_EXTI_LINE_18
00369   *         @arg @ref LL_EXTI_LINE_19
00370   *         @arg @ref LL_EXTI_LINE_20
00371   *         @arg @ref LL_EXTI_LINE_21
00372   *         @arg @ref LL_EXTI_LINE_22
00373   *         @arg @ref LL_EXTI_LINE_23
00374   *         @arg @ref LL_EXTI_LINE_24
00375   *         @arg @ref LL_EXTI_LINE_25
00376   *         @arg @ref LL_EXTI_LINE_26
00377   *         @arg @ref LL_EXTI_LINE_27
00378   *         @arg @ref LL_EXTI_LINE_28
00379   *         @arg @ref LL_EXTI_LINE_29
00380   *         @arg @ref LL_EXTI_LINE_30
00381   *         @arg @ref LL_EXTI_LINE_31
00382   *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
00383   * @note   (*): Available in some devices
00384   * @note   Please check each device line mapping for EXTI Line availability
00385   * @retval None
00386   */
00387 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00388 {
00389   CLEAR_BIT(EXTI->IMR1, ExtiLine);
00390 }
00391
00392 /**
00393   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00394   * @note The reset value for the direct lines (lines from 32 to 34, line
00395   *       39) is set to 1 in order to enable the interrupt by default.
00396   *       Bits are set automatically at Power on.
00397   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00398   * @param  ExtiLine This parameter can be one of the following values:
00399   *         @arg @ref LL_EXTI_LINE_32 (*)
00400   *         @arg @ref LL_EXTI_LINE_33 (*)
00401   *         @arg @ref LL_EXTI_LINE_34
00402   *         @arg @ref LL_EXTI_LINE_35 (*)
00403   *         @arg @ref LL_EXTI_LINE_36
00404   *         @arg @ref LL_EXTI_LINE_37
00405   *         @arg @ref LL_EXTI_LINE_38
00406   *         @arg @ref LL_EXTI_LINE_39
00407   *         @arg @ref LL_EXTI_LINE_40
00408   *         @arg @ref LL_EXTI_LINE_41
00409   *         @arg @ref LL_EXTI_LINE_42(*)
00410   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00411   * @note   (*): Available in some devices
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00415 {
00416   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00417 }
00418
00419 /**
00420   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00421   * @note The reset value for the direct or internal lines (see RM)
00422   *       is set to 1 in order to enable the interrupt by default.
00423   *       Bits are set automatically at Power on.
00424   * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
00425   * @param  ExtiLine This parameter can be one of the following values:
00426   *         @arg @ref LL_EXTI_LINE_0
00427   *         @arg @ref LL_EXTI_LINE_1
00428   *         @arg @ref LL_EXTI_LINE_2
00429   *         @arg @ref LL_EXTI_LINE_3
00430   *         @arg @ref LL_EXTI_LINE_4
00431   *         @arg @ref LL_EXTI_LINE_5
00432   *         @arg @ref LL_EXTI_LINE_6
00433   *         @arg @ref LL_EXTI_LINE_7
00434   *         @arg @ref LL_EXTI_LINE_8
00435   *         @arg @ref LL_EXTI_LINE_9
00436   *         @arg @ref LL_EXTI_LINE_10
00437   *         @arg @ref LL_EXTI_LINE_11
00438   *         @arg @ref LL_EXTI_LINE_12
00439   *         @arg @ref LL_EXTI_LINE_13
00440   *         @arg @ref LL_EXTI_LINE_14
00441   *         @arg @ref LL_EXTI_LINE_15
00442   *         @arg @ref LL_EXTI_LINE_16
00443   *         @arg @ref LL_EXTI_LINE_17
00444   *         @arg @ref LL_EXTI_LINE_18
00445   *         @arg @ref LL_EXTI_LINE_19
00446   *         @arg @ref LL_EXTI_LINE_20
00447   *         @arg @ref LL_EXTI_LINE_21
00448   *         @arg @ref LL_EXTI_LINE_22
00449   *         @arg @ref LL_EXTI_LINE_23
00450   *         @arg @ref LL_EXTI_LINE_24
00451   *         @arg @ref LL_EXTI_LINE_25
00452   *         @arg @ref LL_EXTI_LINE_26
00453   *         @arg @ref LL_EXTI_LINE_27
00454   *         @arg @ref LL_EXTI_LINE_28
00455   *         @arg @ref LL_EXTI_LINE_29
00456   *         @arg @ref LL_EXTI_LINE_30
00457   *         @arg @ref LL_EXTI_LINE_31 (*)
00458   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00459   * @note   (*): Available in some devices
00460   * @note   Please check each device line mapping for EXTI Line availability
00461   * @retval State of bit (1 or 0).
00462   */
00463 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00464 {
00465   return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00466 }
00467
00468 /**
00469   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00470   * @note The reset value for the direct lines (lines from 32 to 34, line
00471   *       39) is set to 1 in order to enable the interrupt by default.
00472   *       Bits are set automatically at Power on.
00473   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00474   * @param  ExtiLine This parameter can be one of the following values:
00475   *         @arg @ref LL_EXTI_LINE_32 (*)
00476   *         @arg @ref LL_EXTI_LINE_33 (*)
00477   *         @arg @ref LL_EXTI_LINE_34
00478   *         @arg @ref LL_EXTI_LINE_35 (*)
00479   *         @arg @ref LL_EXTI_LINE_36
00480   *         @arg @ref LL_EXTI_LINE_37
00481   *         @arg @ref LL_EXTI_LINE_38
00482   *         @arg @ref LL_EXTI_LINE_39
00483   *         @arg @ref LL_EXTI_LINE_40
00484   *         @arg @ref LL_EXTI_LINE_41
00485   *         @arg @ref LL_EXTI_LINE_42(*)
00486   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00487   * @note   (*): Available in some devices
00488   * @retval State of bit (1 or 0).
00489   */
00490 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00491 {
00492   return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00493 }
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00500   * @{
00501   */
00502
00503 /**
00504   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00505   * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
00506   * @param  ExtiLine This parameter can be one of the following values:
00507   *         @arg @ref LL_EXTI_LINE_0
00508   *         @arg @ref LL_EXTI_LINE_1
00509   *         @arg @ref LL_EXTI_LINE_2
00510   *         @arg @ref LL_EXTI_LINE_3
00511   *         @arg @ref LL_EXTI_LINE_4
00512   *         @arg @ref LL_EXTI_LINE_5
00513   *         @arg @ref LL_EXTI_LINE_6
00514   *         @arg @ref LL_EXTI_LINE_7
00515   *         @arg @ref LL_EXTI_LINE_8
00516   *         @arg @ref LL_EXTI_LINE_9
00517   *         @arg @ref LL_EXTI_LINE_10
00518   *         @arg @ref LL_EXTI_LINE_11
00519   *         @arg @ref LL_EXTI_LINE_12
00520   *         @arg @ref LL_EXTI_LINE_13
00521   *         @arg @ref LL_EXTI_LINE_14
00522   *         @arg @ref LL_EXTI_LINE_15
00523   *         @arg @ref LL_EXTI_LINE_16
00524   *         @arg @ref LL_EXTI_LINE_17
00525   *         @arg @ref LL_EXTI_LINE_18
00526   *         @arg @ref LL_EXTI_LINE_19
00527   *         @arg @ref LL_EXTI_LINE_20
00528   *         @arg @ref LL_EXTI_LINE_21
00529   *         @arg @ref LL_EXTI_LINE_22
00530   *         @arg @ref LL_EXTI_LINE_23
00531   *         @arg @ref LL_EXTI_LINE_24
00532   *         @arg @ref LL_EXTI_LINE_25
00533   *         @arg @ref LL_EXTI_LINE_26
00534   *         @arg @ref LL_EXTI_LINE_27
00535   *         @arg @ref LL_EXTI_LINE_28
00536   *         @arg @ref LL_EXTI_LINE_29
00537   *         @arg @ref LL_EXTI_LINE_30
00538   *         @arg @ref LL_EXTI_LINE_31
00539   *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
00540   * @note   (*): Available in some devices
00541   * @note   Please check each device line mapping for EXTI Line availability
00542   * @retval None
00543   */
00544 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00545 {
00546   SET_BIT(EXTI->EMR1, ExtiLine);
00547
00548 }
00549
00550 /**
00551   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
00552   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
00553   * @param  ExtiLine This parameter can be a combination of the following values:
00554   *         @arg @ref LL_EXTI_LINE_32 (*)
00555   *         @arg @ref LL_EXTI_LINE_33 (*)
00556   *         @arg @ref LL_EXTI_LINE_34
00557   *         @arg @ref LL_EXTI_LINE_35 (*)
00558   *         @arg @ref LL_EXTI_LINE_36
00559   *         @arg @ref LL_EXTI_LINE_37
00560   *         @arg @ref LL_EXTI_LINE_38
00561   *         @arg @ref LL_EXTI_LINE_39
00562   *         @arg @ref LL_EXTI_LINE_40
00563   *         @arg @ref LL_EXTI_LINE_41
00564   *         @arg @ref LL_EXTI_LINE_42(*)
00565   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00566   * @note   (*): Available in some devices
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00570 {
00571   SET_BIT(EXTI->EMR2, ExtiLine);
00572 }
00573
00574 /**
00575   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00576   * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
00577   * @param  ExtiLine This parameter can be one of the following values:
00578   *         @arg @ref LL_EXTI_LINE_0
00579   *         @arg @ref LL_EXTI_LINE_1
00580   *         @arg @ref LL_EXTI_LINE_2
00581   *         @arg @ref LL_EXTI_LINE_3
00582   *         @arg @ref LL_EXTI_LINE_4
00583   *         @arg @ref LL_EXTI_LINE_5
00584   *         @arg @ref LL_EXTI_LINE_6
00585   *         @arg @ref LL_EXTI_LINE_7
00586   *         @arg @ref LL_EXTI_LINE_8
00587   *         @arg @ref LL_EXTI_LINE_9
00588   *         @arg @ref LL_EXTI_LINE_10
00589   *         @arg @ref LL_EXTI_LINE_11
00590   *         @arg @ref LL_EXTI_LINE_12
00591   *         @arg @ref LL_EXTI_LINE_13
00592   *         @arg @ref LL_EXTI_LINE_14
00593   *         @arg @ref LL_EXTI_LINE_15
00594   *         @arg @ref LL_EXTI_LINE_16
00595   *         @arg @ref LL_EXTI_LINE_17
00596   *         @arg @ref LL_EXTI_LINE_18
00597   *         @arg @ref LL_EXTI_LINE_19
00598   *         @arg @ref LL_EXTI_LINE_20
00599   *         @arg @ref LL_EXTI_LINE_21
00600   *         @arg @ref LL_EXTI_LINE_22
00601   *         @arg @ref LL_EXTI_LINE_23
00602   *         @arg @ref LL_EXTI_LINE_24
00603   *         @arg @ref LL_EXTI_LINE_25
00604   *         @arg @ref LL_EXTI_LINE_26
00605   *         @arg @ref LL_EXTI_LINE_27
00606   *         @arg @ref LL_EXTI_LINE_28
00607   *         @arg @ref LL_EXTI_LINE_29
00608   *         @arg @ref LL_EXTI_LINE_30
00609   *         @arg @ref LL_EXTI_LINE_31 (*)
00610   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00611   * @note   (*): Available in some devices
00612   * @note   Please check each device line mapping for EXTI Line availability
00613   * @retval None
00614   */
00615 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00616 {
00617   CLEAR_BIT(EXTI->EMR1, ExtiLine);
00618 }
00619
00620 /**
00621   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
00622   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
00623   * @param  ExtiLine This parameter can be a combination of the following values:
00624   *         @arg @ref LL_EXTI_LINE_32 (*)
00625   *         @arg @ref LL_EXTI_LINE_33 (*)
00626   *         @arg @ref LL_EXTI_LINE_34
00627   *         @arg @ref LL_EXTI_LINE_35 (*)
00628   *         @arg @ref LL_EXTI_LINE_36
00629   *         @arg @ref LL_EXTI_LINE_37
00630   *         @arg @ref LL_EXTI_LINE_38
00631   *         @arg @ref LL_EXTI_LINE_39
00632   *         @arg @ref LL_EXTI_LINE_40
00633   *         @arg @ref LL_EXTI_LINE_41
00634   *         @arg @ref LL_EXTI_LINE_42(*)
00635   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00636   * @note   (*): Available in some devices
00637   * @retval None
00638   */
00639 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00640 {
00641   CLEAR_BIT(EXTI->EMR2, ExtiLine);
00642 }
00643
00644 /**
00645   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00646   * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
00647   * @param  ExtiLine This parameter can be one of the following values:
00648   *         @arg @ref LL_EXTI_LINE_0
00649   *         @arg @ref LL_EXTI_LINE_1
00650   *         @arg @ref LL_EXTI_LINE_2
00651   *         @arg @ref LL_EXTI_LINE_3
00652   *         @arg @ref LL_EXTI_LINE_4
00653   *         @arg @ref LL_EXTI_LINE_5
00654   *         @arg @ref LL_EXTI_LINE_6
00655   *         @arg @ref LL_EXTI_LINE_7
00656   *         @arg @ref LL_EXTI_LINE_8
00657   *         @arg @ref LL_EXTI_LINE_9
00658   *         @arg @ref LL_EXTI_LINE_10
00659   *         @arg @ref LL_EXTI_LINE_11
00660   *         @arg @ref LL_EXTI_LINE_12
00661   *         @arg @ref LL_EXTI_LINE_13
00662   *         @arg @ref LL_EXTI_LINE_14
00663   *         @arg @ref LL_EXTI_LINE_15
00664   *         @arg @ref LL_EXTI_LINE_16
00665   *         @arg @ref LL_EXTI_LINE_17
00666   *         @arg @ref LL_EXTI_LINE_18
00667   *         @arg @ref LL_EXTI_LINE_19
00668   *         @arg @ref LL_EXTI_LINE_20
00669   *         @arg @ref LL_EXTI_LINE_21
00670   *         @arg @ref LL_EXTI_LINE_22
00671   *         @arg @ref LL_EXTI_LINE_23
00672   *         @arg @ref LL_EXTI_LINE_24
00673   *         @arg @ref LL_EXTI_LINE_25
00674   *         @arg @ref LL_EXTI_LINE_26
00675   *         @arg @ref LL_EXTI_LINE_27
00676   *         @arg @ref LL_EXTI_LINE_28
00677   *         @arg @ref LL_EXTI_LINE_29
00678   *         @arg @ref LL_EXTI_LINE_30
00679   *         @arg @ref LL_EXTI_LINE_31
00680   *         @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
00681   * @note   (*): Available in some devices
00682   * @note   Please check each device line mapping for EXTI Line availability
00683   * @retval State of bit (1 or 0).
00684   */
00685 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00686 {
00687   return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00688
00689 }
00690
00691 /**
00692   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
00693   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
00694   * @param  ExtiLine This parameter can be a combination of the following values:
00695   *         @arg @ref LL_EXTI_LINE_32 (*)
00696   *         @arg @ref LL_EXTI_LINE_33 (*)
00697   *         @arg @ref LL_EXTI_LINE_34
00698   *         @arg @ref LL_EXTI_LINE_35 (*)
00699   *         @arg @ref LL_EXTI_LINE_36
00700   *         @arg @ref LL_EXTI_LINE_37
00701   *         @arg @ref LL_EXTI_LINE_38
00702   *         @arg @ref LL_EXTI_LINE_39
00703   *         @arg @ref LL_EXTI_LINE_40
00704   *         @arg @ref LL_EXTI_LINE_41
00705   *         @arg @ref LL_EXTI_LINE_42(*)
00706   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00707   * @note   (*): Available in some devices
00708   * @retval State of bit (1 or 0).
00709   */
00710 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00711 {
00712   return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00713 }
00714
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00720   * @{
00721   */
00722
00723 /**
00724   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00725   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00726   *       generated on these lines. If a rising edge on a configurable interrupt
00727   *       line occurs during a write operation in the EXTI_RTSR register, the
00728   *       pending bit is not set.
00729   *       Rising and falling edge triggers can be set for
00730   *       the same interrupt line. In this case, both generate a trigger
00731   *       condition.
00732   * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
00733   * @param  ExtiLine This parameter can be a combination of the following values:
00734   *         @arg @ref LL_EXTI_LINE_0
00735   *         @arg @ref LL_EXTI_LINE_1
00736   *         @arg @ref LL_EXTI_LINE_2
00737   *         @arg @ref LL_EXTI_LINE_3
00738   *         @arg @ref LL_EXTI_LINE_4
00739   *         @arg @ref LL_EXTI_LINE_5
00740   *         @arg @ref LL_EXTI_LINE_6
00741   *         @arg @ref LL_EXTI_LINE_7
00742   *         @arg @ref LL_EXTI_LINE_8
00743   *         @arg @ref LL_EXTI_LINE_9
00744   *         @arg @ref LL_EXTI_LINE_10
00745   *         @arg @ref LL_EXTI_LINE_11
00746   *         @arg @ref LL_EXTI_LINE_12
00747   *         @arg @ref LL_EXTI_LINE_13
00748   *         @arg @ref LL_EXTI_LINE_14
00749   *         @arg @ref LL_EXTI_LINE_15
00750   *         @arg @ref LL_EXTI_LINE_16
00751   *         @arg @ref LL_EXTI_LINE_18
00752   *         @arg @ref LL_EXTI_LINE_19
00753   *         @arg @ref LL_EXTI_LINE_20
00754   *         @arg @ref LL_EXTI_LINE_21
00755   *         @arg @ref LL_EXTI_LINE_22
00756   *         @arg @ref LL_EXTI_LINE_29
00757   *         @arg @ref LL_EXTI_LINE_30
00758   *         @arg @ref LL_EXTI_LINE_31 (*)
00759   * @note   (*): Available in some devices
00760   * @note   Please check each device line mapping for EXTI Line availability
00761   * @retval None
00762   */
00763 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00764 {
00765   SET_BIT(EXTI->RTSR1, ExtiLine);
00766
00767 }
00768
00769 /**
00770   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00771   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00772   *       generated on these lines. If a rising edge on a configurable interrupt
00773   *       line occurs during a write operation in the EXTI_RTSR register, the
00774   *       pending bit is not set.Rising and falling edge triggers can be set for
00775   *       the same interrupt line. In this case, both generate a trigger
00776   *       condition.
00777   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
00778   * @param  ExtiLine This parameter can be a combination of the following values:
00779   *         @arg @ref LL_EXTI_LINE_32 (*)
00780   *         @arg @ref LL_EXTI_LINE_33 (*)
00781   *         @arg @ref LL_EXTI_LINE_38
00782   *         @arg @ref LL_EXTI_LINE_39
00783   *         @arg @ref LL_EXTI_LINE_40
00784   *         @arg @ref LL_EXTI_LINE_41
00785   * @note   (*): Available in some devices
00786   * @retval None
00787   */
00788 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
00789 {
00790   SET_BIT(EXTI->RTSR2, ExtiLine);
00791 }
00792
00793 /**
00794   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00795   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00796   *       generated on these lines. If a rising edge on a configurable interrupt
00797   *       line occurs during a write operation in the EXTI_RTSR register, the
00798   *       pending bit is not set.
00799   *       Rising and falling edge triggers can be set for
00800   *       the same interrupt line. In this case, both generate a trigger
00801   *       condition.
00802   * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
00803   * @param  ExtiLine This parameter can be a combination of the following values:
00804   *         @arg @ref LL_EXTI_LINE_0
00805   *         @arg @ref LL_EXTI_LINE_1
00806   *         @arg @ref LL_EXTI_LINE_2
00807   *         @arg @ref LL_EXTI_LINE_3
00808   *         @arg @ref LL_EXTI_LINE_4
00809   *         @arg @ref LL_EXTI_LINE_5
00810   *         @arg @ref LL_EXTI_LINE_6
00811   *         @arg @ref LL_EXTI_LINE_7
00812   *         @arg @ref LL_EXTI_LINE_8
00813   *         @arg @ref LL_EXTI_LINE_9
00814   *         @arg @ref LL_EXTI_LINE_10
00815   *         @arg @ref LL_EXTI_LINE_11
00816   *         @arg @ref LL_EXTI_LINE_12
00817   *         @arg @ref LL_EXTI_LINE_13
00818   *         @arg @ref LL_EXTI_LINE_14
00819   *         @arg @ref LL_EXTI_LINE_15
00820   *         @arg @ref LL_EXTI_LINE_16
00821   *         @arg @ref LL_EXTI_LINE_18
00822   *         @arg @ref LL_EXTI_LINE_19
00823   *         @arg @ref LL_EXTI_LINE_20
00824   *         @arg @ref LL_EXTI_LINE_21
00825   *         @arg @ref LL_EXTI_LINE_22
00826   *         @arg @ref LL_EXTI_LINE_29
00827   *         @arg @ref LL_EXTI_LINE_30
00828   *         @arg @ref LL_EXTI_LINE_31 (*)
00829   * @note   (*): Available in some devices
00830   * @note   Please check each device line mapping for EXTI Line availability
00831   * @retval None
00832   */
00833 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
00834 {
00835   CLEAR_BIT(EXTI->RTSR1, ExtiLine);
00836
00837 }
00838
00839 /**
00840   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00841   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00842   *       generated on these lines. If a rising edge on a configurable interrupt
00843   *       line occurs during a write operation in the EXTI_RTSR register, the
00844   *       pending bit is not set.
00845   *       Rising and falling edge triggers can be set for
00846   *       the same interrupt line. In this case, both generate a trigger
00847   *       condition.
00848   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
00849   * @param  ExtiLine This parameter can be a combination of the following values:
00850   *         @arg @ref LL_EXTI_LINE_32 (*)
00851   *         @arg @ref LL_EXTI_LINE_33 (*)
00852   *         @arg @ref LL_EXTI_LINE_38
00853   *         @arg @ref LL_EXTI_LINE_39
00854   *         @arg @ref LL_EXTI_LINE_40
00855   *         @arg @ref LL_EXTI_LINE_41
00856   * @note   (*): Available in some devices
00857   * @retval None
00858   */
00859 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
00860 {
00861   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
00862 }
00863
00864 /**
00865   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
00866   * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
00867   * @param  ExtiLine This parameter can be a combination of the following values:
00868   *         @arg @ref LL_EXTI_LINE_0
00869   *         @arg @ref LL_EXTI_LINE_1
00870   *         @arg @ref LL_EXTI_LINE_2
00871   *         @arg @ref LL_EXTI_LINE_3
00872   *         @arg @ref LL_EXTI_LINE_4
00873   *         @arg @ref LL_EXTI_LINE_5
00874   *         @arg @ref LL_EXTI_LINE_6
00875   *         @arg @ref LL_EXTI_LINE_7
00876   *         @arg @ref LL_EXTI_LINE_8
00877   *         @arg @ref LL_EXTI_LINE_9
00878   *         @arg @ref LL_EXTI_LINE_10
00879   *         @arg @ref LL_EXTI_LINE_11
00880   *         @arg @ref LL_EXTI_LINE_12
00881   *         @arg @ref LL_EXTI_LINE_13
00882   *         @arg @ref LL_EXTI_LINE_14
00883   *         @arg @ref LL_EXTI_LINE_15
00884   *         @arg @ref LL_EXTI_LINE_16
00885   *         @arg @ref LL_EXTI_LINE_18
00886   *         @arg @ref LL_EXTI_LINE_19
00887   *         @arg @ref LL_EXTI_LINE_20
00888   *         @arg @ref LL_EXTI_LINE_21
00889   *         @arg @ref LL_EXTI_LINE_22
00890   *         @arg @ref LL_EXTI_LINE_29
00891   *         @arg @ref LL_EXTI_LINE_30
00892   *         @arg @ref LL_EXTI_LINE_31 (*)
00893   * @note   (*): Available in some devices
00894   * @note   Please check each device line mapping for EXTI Line availability
00895   * @retval State of bit (1 or 0).
00896   */
00897 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
00898 {
00899   return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00900 }
00901
00902 /**
00903   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
00904   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
00905   * @param  ExtiLine This parameter can be a combination of the following values:
00906   *         @arg @ref LL_EXTI_LINE_32 (*)
00907   *         @arg @ref LL_EXTI_LINE_33 (*)
00908   *         @arg @ref LL_EXTI_LINE_38
00909   *         @arg @ref LL_EXTI_LINE_39
00910   *         @arg @ref LL_EXTI_LINE_40
00911   *         @arg @ref LL_EXTI_LINE_41
00912   * @note   (*): Available in some devices
00913   * @retval State of bit (1 or 0).
00914   */
00915 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
00916 {
00917   return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00918 }
00919
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
00925   * @{
00926   */
00927
00928 /**
00929   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00930   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00931   *       generated on these lines. If a falling edge on a configurable interrupt
00932   *       line occurs during a write operation in the EXTI_FTSR register, the
00933   *       pending bit is not set.
00934   *       Rising and falling edge triggers can be set for
00935   *       the same interrupt line. In this case, both generate a trigger
00936   *       condition.
00937   * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
00938   * @param  ExtiLine This parameter can be a combination of the following values:
00939   *         @arg @ref LL_EXTI_LINE_0
00940   *         @arg @ref LL_EXTI_LINE_1
00941   *         @arg @ref LL_EXTI_LINE_2
00942   *         @arg @ref LL_EXTI_LINE_3
00943   *         @arg @ref LL_EXTI_LINE_4
00944   *         @arg @ref LL_EXTI_LINE_5
00945   *         @arg @ref LL_EXTI_LINE_6
00946   *         @arg @ref LL_EXTI_LINE_7
00947   *         @arg @ref LL_EXTI_LINE_8
00948   *         @arg @ref LL_EXTI_LINE_9
00949   *         @arg @ref LL_EXTI_LINE_10
00950   *         @arg @ref LL_EXTI_LINE_11
00951   *         @arg @ref LL_EXTI_LINE_12
00952   *         @arg @ref LL_EXTI_LINE_13
00953   *         @arg @ref LL_EXTI_LINE_14
00954   *         @arg @ref LL_EXTI_LINE_15
00955   *         @arg @ref LL_EXTI_LINE_16
00956   *         @arg @ref LL_EXTI_LINE_18
00957   *         @arg @ref LL_EXTI_LINE_19
00958   *         @arg @ref LL_EXTI_LINE_20
00959   *         @arg @ref LL_EXTI_LINE_21
00960   *         @arg @ref LL_EXTI_LINE_22
00961   *         @arg @ref LL_EXTI_LINE_29
00962   *         @arg @ref LL_EXTI_LINE_30
00963   *         @arg @ref LL_EXTI_LINE_31 (*)
00964   * @note   (*): Available in some devices
00965   * @note   Please check each device line mapping for EXTI Line availability
00966   * @retval None
00967   */
00968 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
00969 {
00970   SET_BIT(EXTI->FTSR1, ExtiLine);
00971 }
00972
00973 /**
00974   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00975   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00976   *       generated on these lines. If a Falling edge on a configurable interrupt
00977   *       line occurs during a write operation in the EXTI_FTSR register, the
00978   *       pending bit is not set.
00979   *       Rising and falling edge triggers can be set for
00980   *       the same interrupt line. In this case, both generate a trigger
00981   *       condition.
00982   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
00983   * @param  ExtiLine This parameter can be a combination of the following values:
00984   *         @arg @ref LL_EXTI_LINE_32 (*)
00985   *         @arg @ref LL_EXTI_LINE_33 (*)
00986   *         @arg @ref LL_EXTI_LINE_38
00987   *         @arg @ref LL_EXTI_LINE_39
00988   *         @arg @ref LL_EXTI_LINE_40
00989   *         @arg @ref LL_EXTI_LINE_41
00990   * @note   (*): Available in some devices
00991   * @retval None
00992   */
00993 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
00994 {
00995   SET_BIT(EXTI->FTSR2, ExtiLine);
00996 }
00997
00998 /**
00999   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
01000   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01001   *       generated on these lines. If a Falling edge on a configurable interrupt
01002   *       line occurs during a write operation in the EXTI_FTSR register, the
01003   *       pending bit is not set.
01004   *       Rising and falling edge triggers can be set for the same interrupt line.
01005   *       In this case, both generate a trigger condition.
01006   * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
01007   * @param  ExtiLine This parameter can be a combination of the following values:
01008   *         @arg @ref LL_EXTI_LINE_0
01009   *         @arg @ref LL_EXTI_LINE_1
01010   *         @arg @ref LL_EXTI_LINE_2
01011   *         @arg @ref LL_EXTI_LINE_3
01012   *         @arg @ref LL_EXTI_LINE_4
01013   *         @arg @ref LL_EXTI_LINE_5
01014   *         @arg @ref LL_EXTI_LINE_6
01015   *         @arg @ref LL_EXTI_LINE_7
01016   *         @arg @ref LL_EXTI_LINE_8
01017   *         @arg @ref LL_EXTI_LINE_9
01018   *         @arg @ref LL_EXTI_LINE_10
01019   *         @arg @ref LL_EXTI_LINE_11
01020   *         @arg @ref LL_EXTI_LINE_12
01021   *         @arg @ref LL_EXTI_LINE_13
01022   *         @arg @ref LL_EXTI_LINE_14
01023   *         @arg @ref LL_EXTI_LINE_15
01024   *         @arg @ref LL_EXTI_LINE_16
01025   *         @arg @ref LL_EXTI_LINE_18
01026   *         @arg @ref LL_EXTI_LINE_19
01027   *         @arg @ref LL_EXTI_LINE_20
01028   *         @arg @ref LL_EXTI_LINE_21
01029   *         @arg @ref LL_EXTI_LINE_22
01030   *         @arg @ref LL_EXTI_LINE_29
01031   *         @arg @ref LL_EXTI_LINE_30
01032   *         @arg @ref LL_EXTI_LINE_31 (*)
01033   * @note   (*): Available in some devices
01034   * @note   Please check each device line mapping for EXTI Line availability
01035   * @retval None
01036   */
01037 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
01038 {
01039   CLEAR_BIT(EXTI->FTSR1, ExtiLine);
01040 }
01041
01042 /**
01043   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
01044   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01045   *       generated on these lines. If a Falling edge on a configurable interrupt
01046   *       line occurs during a write operation in the EXTI_FTSR register, the
01047   *       pending bit is not set.
01048   *       Rising and falling edge triggers can be set for the same interrupt line.
01049   *       In this case, both generate a trigger condition.
01050   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
01051   * @param  ExtiLine This parameter can be a combination of the following values:
01052   *         @arg @ref LL_EXTI_LINE_32 (*)
01053   *         @arg @ref LL_EXTI_LINE_33 (*)
01054   *         @arg @ref LL_EXTI_LINE_38
01055   *         @arg @ref LL_EXTI_LINE_39
01056   *         @arg @ref LL_EXTI_LINE_40
01057   *         @arg @ref LL_EXTI_LINE_41
01058   * @note   (*): Available in some devices
01059   * @retval None
01060   */
01061 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
01062 {
01063   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
01064 }
01065
01066 /**
01067   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
01068   * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
01069   * @param  ExtiLine This parameter can be a combination of the following values:
01070   *         @arg @ref LL_EXTI_LINE_0
01071   *         @arg @ref LL_EXTI_LINE_1
01072   *         @arg @ref LL_EXTI_LINE_2
01073   *         @arg @ref LL_EXTI_LINE_3
01074   *         @arg @ref LL_EXTI_LINE_4
01075   *         @arg @ref LL_EXTI_LINE_5
01076   *         @arg @ref LL_EXTI_LINE_6
01077   *         @arg @ref LL_EXTI_LINE_7
01078   *         @arg @ref LL_EXTI_LINE_8
01079   *         @arg @ref LL_EXTI_LINE_9
01080   *         @arg @ref LL_EXTI_LINE_10
01081   *         @arg @ref LL_EXTI_LINE_11
01082   *         @arg @ref LL_EXTI_LINE_12
01083   *         @arg @ref LL_EXTI_LINE_13
01084   *         @arg @ref LL_EXTI_LINE_14
01085   *         @arg @ref LL_EXTI_LINE_15
01086   *         @arg @ref LL_EXTI_LINE_16
01087   *         @arg @ref LL_EXTI_LINE_18
01088   *         @arg @ref LL_EXTI_LINE_19
01089   *         @arg @ref LL_EXTI_LINE_20
01090   *         @arg @ref LL_EXTI_LINE_21
01091   *         @arg @ref LL_EXTI_LINE_22
01092   *         @arg @ref LL_EXTI_LINE_29
01093   *         @arg @ref LL_EXTI_LINE_30
01094   *         @arg @ref LL_EXTI_LINE_31 (*)
01095   * @note   (*): Available in some devices
01096   * @note   Please check each device line mapping for EXTI Line availability
01097   * @retval State of bit (1 or 0).
01098   */
01099 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
01100 {
01101   return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01102 }
01103
01104 /**
01105   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
01106   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
01107   * @param  ExtiLine This parameter can be a combination of the following values:
01108   *         @arg @ref LL_EXTI_LINE_32 (*)
01109   *         @arg @ref LL_EXTI_LINE_33 (*)
01110   *         @arg @ref LL_EXTI_LINE_38
01111   *         @arg @ref LL_EXTI_LINE_39
01112   *         @arg @ref LL_EXTI_LINE_40
01113   *         @arg @ref LL_EXTI_LINE_41
01114   * @note   (*): Available in some devices
01115   * @retval State of bit (1 or 0).
01116   */
01117 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
01118 {
01119   return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01120 }
01121
01122 /**
01123   * @}
01124   */
01125
01126 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
01127   * @{
01128   */
01129
01130 /**
01131   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
01132   * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
01133   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
01134   *       resulting in an interrupt request generation.
01135   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
01136   *       register (by writing a 1 into the bit)
01137   * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
01138   * @param  ExtiLine This parameter can be a combination of the following values:
01139   *         @arg @ref LL_EXTI_LINE_0
01140   *         @arg @ref LL_EXTI_LINE_1
01141   *         @arg @ref LL_EXTI_LINE_2
01142   *         @arg @ref LL_EXTI_LINE_3
01143   *         @arg @ref LL_EXTI_LINE_4
01144   *         @arg @ref LL_EXTI_LINE_5
01145   *         @arg @ref LL_EXTI_LINE_6
01146   *         @arg @ref LL_EXTI_LINE_7
01147   *         @arg @ref LL_EXTI_LINE_8
01148   *         @arg @ref LL_EXTI_LINE_9
01149   *         @arg @ref LL_EXTI_LINE_10
01150   *         @arg @ref LL_EXTI_LINE_11
01151   *         @arg @ref LL_EXTI_LINE_12
01152   *         @arg @ref LL_EXTI_LINE_13
01153   *         @arg @ref LL_EXTI_LINE_14
01154   *         @arg @ref LL_EXTI_LINE_15
01155   *         @arg @ref LL_EXTI_LINE_16
01156   *         @arg @ref LL_EXTI_LINE_18
01157   *         @arg @ref LL_EXTI_LINE_19
01158   *         @arg @ref LL_EXTI_LINE_20
01159   *         @arg @ref LL_EXTI_LINE_21
01160   *         @arg @ref LL_EXTI_LINE_22
01161   *         @arg @ref LL_EXTI_LINE_29
01162   *         @arg @ref LL_EXTI_LINE_30
01163   *         @arg @ref LL_EXTI_LINE_31 (*)
01164   * @note   (*): Available in some devices
01165   * @note   Please check each device line mapping for EXTI Line availability
01166   * @retval None
01167   */
01168 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
01169 {
01170   SET_BIT(EXTI->SWIER1, ExtiLine);
01171 }
01172
01173 /**
01174   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
01175   * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
01176   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
01177   *       resulting in an interrupt request generation.
01178   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
01179   *       register (by writing a 1 into the bit)
01180   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
01181   * @param  ExtiLine This parameter can be a combination of the following values:
01182   *         @arg @ref LL_EXTI_LINE_32 (*)
01183   *         @arg @ref LL_EXTI_LINE_33 (*)
01184   *         @arg @ref LL_EXTI_LINE_38
01185   *         @arg @ref LL_EXTI_LINE_39
01186   *         @arg @ref LL_EXTI_LINE_40
01187   *         @arg @ref LL_EXTI_LINE_41
01188   * @note   (*): Available in some devices
01189   * @retval None
01190   */
01191 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
01192 {
01193   SET_BIT(EXTI->SWIER2, ExtiLine);
01194 }
01195
01196 /**
01197   * @}
01198   */
01199
01200 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
01201   * @{
01202   */
01203
01204 /**
01205   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
01206   * @note This bit is set when the selected edge event arrives on the interrupt
01207   *       line. This bit is cleared by writing a 1 to the bit.
01208   * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
01209   * @param  ExtiLine This parameter can be a combination of the following values:
01210   *         @arg @ref LL_EXTI_LINE_0
01211   *         @arg @ref LL_EXTI_LINE_1
01212   *         @arg @ref LL_EXTI_LINE_2
01213   *         @arg @ref LL_EXTI_LINE_3
01214   *         @arg @ref LL_EXTI_LINE_4
01215   *         @arg @ref LL_EXTI_LINE_5
01216   *         @arg @ref LL_EXTI_LINE_6
01217   *         @arg @ref LL_EXTI_LINE_7
01218   *         @arg @ref LL_EXTI_LINE_8
01219   *         @arg @ref LL_EXTI_LINE_9
01220   *         @arg @ref LL_EXTI_LINE_10
01221   *         @arg @ref LL_EXTI_LINE_11
01222   *         @arg @ref LL_EXTI_LINE_12
01223   *         @arg @ref LL_EXTI_LINE_13
01224   *         @arg @ref LL_EXTI_LINE_14
01225   *         @arg @ref LL_EXTI_LINE_15
01226   *         @arg @ref LL_EXTI_LINE_16
01227   *         @arg @ref LL_EXTI_LINE_18
01228   *         @arg @ref LL_EXTI_LINE_19
01229   *         @arg @ref LL_EXTI_LINE_20
01230   *         @arg @ref LL_EXTI_LINE_21
01231   *         @arg @ref LL_EXTI_LINE_22
01232   *         @arg @ref LL_EXTI_LINE_29
01233   *         @arg @ref LL_EXTI_LINE_30
01234   *         @arg @ref LL_EXTI_LINE_31 (*)
01235   * @note   (*): Available in some devices
01236   * @note   Please check each device line mapping for EXTI Line availability
01237   * @retval State of bit (1 or 0).
01238   */
01239 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
01240 {
01241   return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01242 }
01243
01244 /**
01245   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
01246   * @note This bit is set when the selected edge event arrives on the interrupt
01247   *       line. This bit is cleared by writing a 1 to the bit.
01248   * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
01249   * @param  ExtiLine This parameter can be a combination of the following values:
01250   *         @arg @ref LL_EXTI_LINE_32 (*)
01251   *         @arg @ref LL_EXTI_LINE_33 (*)
01252   *         @arg @ref LL_EXTI_LINE_38
01253   *         @arg @ref LL_EXTI_LINE_39
01254   *         @arg @ref LL_EXTI_LINE_40
01255   *         @arg @ref LL_EXTI_LINE_41
01256   * @note   (*): Available in some devices
01257   * @retval State of bit (1 or 0).
01258   */
01259 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
01260 {
01261   return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01262 }
01263
01264 /**
01265   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
01266   * @note This bit is set when the selected edge event arrives on the interrupt
01267   *       line. This bit is cleared by writing a 1 to the bit.
01268   * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
01269   * @param  ExtiLine This parameter can be a combination of the following values:
01270   *         @arg @ref LL_EXTI_LINE_0
01271   *         @arg @ref LL_EXTI_LINE_1
01272   *         @arg @ref LL_EXTI_LINE_2
01273   *         @arg @ref LL_EXTI_LINE_3
01274   *         @arg @ref LL_EXTI_LINE_4
01275   *         @arg @ref LL_EXTI_LINE_5
01276   *         @arg @ref LL_EXTI_LINE_6
01277   *         @arg @ref LL_EXTI_LINE_7
01278   *         @arg @ref LL_EXTI_LINE_8
01279   *         @arg @ref LL_EXTI_LINE_9
01280   *         @arg @ref LL_EXTI_LINE_10
01281   *         @arg @ref LL_EXTI_LINE_11
01282   *         @arg @ref LL_EXTI_LINE_12
01283   *         @arg @ref LL_EXTI_LINE_13
01284   *         @arg @ref LL_EXTI_LINE_14
01285   *         @arg @ref LL_EXTI_LINE_15
01286   *         @arg @ref LL_EXTI_LINE_16
01287   *         @arg @ref LL_EXTI_LINE_18
01288   *         @arg @ref LL_EXTI_LINE_19
01289   *         @arg @ref LL_EXTI_LINE_20
01290   *         @arg @ref LL_EXTI_LINE_21
01291   *         @arg @ref LL_EXTI_LINE_22
01292   *         @arg @ref LL_EXTI_LINE_29
01293   *         @arg @ref LL_EXTI_LINE_30
01294   *         @arg @ref LL_EXTI_LINE_31 (*)
01295   * @note   (*): Available in some devices
01296   * @note   Please check each device line mapping for EXTI Line availability
01297   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01298   */
01299 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
01300 {
01301   return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
01302 }
01303
01304 /**
01305   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
01306   * @note This bit is set when the selected edge event arrives on the interrupt
01307   *       line. This bit is cleared by writing a 1 to the bit.
01308   * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
01309   * @param  ExtiLine This parameter can be a combination of the following values:
01310   *         @arg @ref LL_EXTI_LINE_32 (*)
01311   *         @arg @ref LL_EXTI_LINE_33 (*)
01312   *         @arg @ref LL_EXTI_LINE_38
01313   *         @arg @ref LL_EXTI_LINE_39
01314   *         @arg @ref LL_EXTI_LINE_40
01315   *         @arg @ref LL_EXTI_LINE_41
01316   * @note   (*): Available in some devices
01317   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01318   */
01319 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
01320 {
01321   return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
01322 }
01323
01324 /**
01325   * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
01326   * @note This bit is set when the selected edge event arrives on the interrupt
01327   *       line. This bit is cleared by writing a 1 to the bit.
01328   * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
01329   * @param  ExtiLine This parameter can be a combination of the following values:
01330   *         @arg @ref LL_EXTI_LINE_0
01331   *         @arg @ref LL_EXTI_LINE_1
01332   *         @arg @ref LL_EXTI_LINE_2
01333   *         @arg @ref LL_EXTI_LINE_3
01334   *         @arg @ref LL_EXTI_LINE_4
01335   *         @arg @ref LL_EXTI_LINE_5
01336   *         @arg @ref LL_EXTI_LINE_6
01337   *         @arg @ref LL_EXTI_LINE_7
01338   *         @arg @ref LL_EXTI_LINE_8
01339   *         @arg @ref LL_EXTI_LINE_9
01340   *         @arg @ref LL_EXTI_LINE_10
01341   *         @arg @ref LL_EXTI_LINE_11
01342   *         @arg @ref LL_EXTI_LINE_12
01343   *         @arg @ref LL_EXTI_LINE_13
01344   *         @arg @ref LL_EXTI_LINE_14
01345   *         @arg @ref LL_EXTI_LINE_15
01346   *         @arg @ref LL_EXTI_LINE_16
01347   *         @arg @ref LL_EXTI_LINE_18
01348   *         @arg @ref LL_EXTI_LINE_19
01349   *         @arg @ref LL_EXTI_LINE_20
01350   *         @arg @ref LL_EXTI_LINE_21
01351   *         @arg @ref LL_EXTI_LINE_22
01352   *         @arg @ref LL_EXTI_LINE_29
01353   *         @arg @ref LL_EXTI_LINE_30
01354   *         @arg @ref LL_EXTI_LINE_31 (*)
01355   * @note   (*): Available in some devices
01356   * @note   Please check each device line mapping for EXTI Line availability
01357   * @retval None
01358   */
01359 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
01360 {
01361   WRITE_REG(EXTI->PR1, ExtiLine);
01362 }
01363
01364 /**
01365   * @brief  Clear ExtLine Flags for  Lines in range 32 to 63
01366   * @note This bit is set when the selected edge event arrives on the interrupt
01367   *       line. This bit is cleared by writing a 1 to the bit.
01368   * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
01369   * @param  ExtiLine This parameter can be a combination of the following values:
01370   *         @arg @ref LL_EXTI_LINE_32 (*)
01371   *         @arg @ref LL_EXTI_LINE_33 (*)
01372   *         @arg @ref LL_EXTI_LINE_38
01373   *         @arg @ref LL_EXTI_LINE_39
01374   *         @arg @ref LL_EXTI_LINE_40
01375   *         @arg @ref LL_EXTI_LINE_41
01376   * @note   (*): Available in some devices
01377   * @retval None
01378   */
01379 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
01380 {
01381   WRITE_REG(EXTI->PR2, ExtiLine);
01382 }
01383
01384 /**
01385   * @}
01386   */
01387
01388 #if defined(USE_FULL_LL_DRIVER)
01389 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
01390   * @{
01391   */
01392
01393 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01394 uint32_t LL_EXTI_DeInit(void);
01395 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01396
01397
01398 /**
01399   * @}
01400   */
01401 #endif /* USE_FULL_LL_DRIVER */
01402
01403 /**
01404   * @}
01405   */
01406
01407 /**
01408   * @}
01409   */
01410
01411 #endif /* EXTI */
01412
01413 /**
01414   * @}
01415   */
01416
01417 #ifdef __cplusplus
01418 }
01419 #endif
01420
01421 #endif /* __STM32G4xx_LL_EXTI_H */
01422
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_fmac.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_fmac.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_fmac.c
00004   * @author  MCD Application Team
00005   * @brief   Header for stm32g4xx_ll_fmac.c module
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_fmac.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #ifdef USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined(FMAC)
00034
00035 /** @addtogroup FMAC_LL
00036   * @{
00037   */
00038
00039 /* Private typedef -----------------------------------------------------------*/
00040 /* Private defines -----------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Global variables ----------------------------------------------------------*/
00044 /* Private function prototypes -----------------------------------------------*/
00045 /* Functions Definition ------------------------------------------------------*/
00046 /** @addtogroup FMAC_LL_Exported_Functions
00047   * @{
00048   */
00049
00050 /** @addtogroup FMAC_LL_EF_Init
00051   * @{
00052   */
00053
00054 /**
00055   * @brief  Initialize FMAC peripheral registers to their default reset values.
00056   * @param  FMACx FMAC Instance
00057   * @retval ErrorStatus enumeration value:
00058   *          - SUCCESS: FMAC registers are initialized
00059   *          - ERROR: FMAC registers are not initialized
00060   */
00061 ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx)
00062 {
00063   ErrorStatus status = SUCCESS;
00064
00065   /* Check the parameters */
00066   assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
00067
00068   if (FMACx == FMAC)
00069   {
00070     /* Perform the reset */
00071     LL_FMAC_EnableReset(FMACx);
00072
00073     /* Wait until flag is reset */
00074     while (LL_FMAC_IsEnabledReset(FMACx) != 0UL)
00075     {
00076     }
00077   }
00078   else
00079   {
00080     status = ERROR;
00081   }
00082
00083   return (status);
00084 }
00085
00086 /**
00087   * @brief  De-Initialize FMAC peripheral registers to their default reset values.
00088   * @param  FMACx FMAC Instance
00089   * @retval An ErrorStatus enumeration value:
00090   *          - SUCCESS: FMAC registers are de-initialized
00091   *          - ERROR: FMAC registers are not de-initialized
00092   */
00093 ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx)
00094 {
00095   ErrorStatus status = SUCCESS;
00096
00097   /* Check the parameters */
00098   assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
00099
00100   if (FMACx == FMAC)
00101   {
00102     /* Force FMAC reset */
00103     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_FMAC);
00104
00105     /* Release FMAC reset */
00106     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_FMAC);
00107   }
00108   else
00109   {
00110     status = ERROR;
00111   }
00112
00113   return (status);
00114 }
00115
00116
00117
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129
00130 #endif /* defined(FMAC) */
00131
00132 /**
00133   * @}
00134   */
00135
00136 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_fmac.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_fmac.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_fmac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FMAC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_FMAC_H
00021 #define STM32G4xx_LL_FMAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(FMAC)
00035
00036 /** @defgroup FMAC_LL FMAC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /* Exported constants --------------------------------------------------------*/
00043 /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
00044   * @{
00045   */
00046
00047 /** @defgroup FMAC_LL_EC_GET_FLAG Get Flag Defines
00048   * @brief    Flag defines which can be used with LL_FMAC_ReadReg function
00049   * @{
00050   */
00051 #define LL_FMAC_SR_SAT                     FMAC_SR_SAT    /*!< Saturation Error Flag
00052                                                                (this helps in debugging a filter)                     */
00053 #define LL_FMAC_SR_UNFL                    FMAC_SR_UNFL   /*!< Underflow Error Flag                                   */
00054 #define LL_FMAC_SR_OVFL                    FMAC_SR_OVFL   /*!< Overflow Error Flag                                    */
00055 #define LL_FMAC_SR_X1FULL                  FMAC_SR_X1FULL /*!< X1 Buffer Full Flag                                    */
00056 #define LL_FMAC_SR_YEMPTY                  FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag                                    */
00057 /**
00058   * @}
00059   */
00060
00061 /** @defgroup FMAC_LL_EC_IT IT Defines
00062   * @brief    IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
00063   * @{
00064   */
00065 #define LL_FMAC_CR_SATIEN                  FMAC_CR_SATIEN  /*!< Saturation Error Interrupt Enable
00066                                                                 (this helps in debugging a filter)                    */
00067 #define LL_FMAC_CR_UNFLIEN                 FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable                      */
00068 #define LL_FMAC_CR_OVFLIEN                 FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable                       */
00069 #define LL_FMAC_CR_WIEN                    FMAC_CR_WIEN    /*!< Write Interrupt Enable                                */
00070 #define LL_FMAC_CR_RIEN                    FMAC_CR_RIEN    /*!< Read Interrupt Enable                                 */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup FMAC_LL_EC_WM FMAC watermarks
00076   * @brief    Watermark defines that can be used for buffer full (input) or buffer empty (output)
00077   * @{
00078   */
00079 #define LL_FMAC_WM_0_THRESHOLD_1           0x00000000U /*!< Buffer full/empty flag set if there
00080                                                             is less than 1 free/unread space.                         */
00081 #define LL_FMAC_WM_1_THRESHOLD_2           0x01000000U /*!< Buffer full/empty flag set if there
00082                                                             are less than 2 free/unread spaces.                       */
00083 #define LL_FMAC_WM_2_THRESHOLD_4           0x02000000U /*!< Buffer full/empty flag set if there
00084                                                             are less than 4 free/unread spaces.                       */
00085 #define LL_FMAC_WM_3_THRESHOLD_8           0x03000000U /*!< Buffer full/empty flag set if there
00086                                                             are less than 8 free/empty spaces.                        */
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup FMAC_LL_EC_FUNC FMAC functions
00092   * @{
00093   */
00094 #define LL_FMAC_FUNC_LOAD_X1               (FMAC_PARAM_FUNC_0)                        /*!< Load X1 buffer             */
00095 #define LL_FMAC_FUNC_LOAD_X2               (FMAC_PARAM_FUNC_1)                        /*!< Load X2 buffer             */
00096 #define LL_FMAC_FUNC_LOAD_Y                (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)    /*!< Load Y buffer              */
00097 #define LL_FMAC_FUNC_CONVO_FIR             (FMAC_PARAM_FUNC_3)                        /*!< Convolution (FIR filter)   */
00098 #define LL_FMAC_FUNC_IIR_DIRECT_FORM_1     (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)    /*!< IIR filter (direct form 1) */
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
00104   * @{
00105   */
00106 #define LL_FMAC_PROCESSING_STOP            0x00U /*!< Stop FMAC Processing                                            */
00107 #define LL_FMAC_PROCESSING_START           0x01U /*!< Start FMAC Processing                                           */
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* External variables --------------------------------------------------------*/
00117 /* Exported macros -----------------------------------------------------------*/
00118 /** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
00119   * @{
00120   */
00121
00122 /** @defgroup FMAC_LL_EM_WRITE_READ Common Write and read registers Macros
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  Write a value in FMAC register
00128   * @param  __INSTANCE__ FMAC Instance
00129   * @param  __REG__ Register to be written
00130   * @param  __VALUE__ Value to be written in the register
00131   * @retval None
00132   */
00133 #define LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00134
00135 /**
00136   * @brief  Read a value in FMAC register
00137   * @param  __INSTANCE__ FMAC Instance
00138   * @param  __REG__ Register to be read
00139   * @retval Register value
00140   */
00141 #define LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00142 /**
00143   * @}
00144   */
00145
00146 /**
00147   * @}
00148   */
00149
00150
00151 /* Exported functions --------------------------------------------------------*/
00152
00153 /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
00154   * @{
00155   */
00156
00157 /** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Configure X1 full watermark.
00163   * @rmtoll X1BUFCFG     FULL_WM       LL_FMAC_SetX1FullWatermark
00164   * @param  FMACx FMAC instance
00165   * @param  Watermark This parameter can be one of the following values:
00166   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00167   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00168   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00169   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
00173 {
00174   MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark);
00175 }
00176
00177 /**
00178   * @brief  Return X1 full watermark.
00179   * @rmtoll X1BUFCFG     FULL_WM       LL_FMAC_GetX1FullWatermark
00180   * @param  FMACx FMAC instance
00181   * @retval uint32_t Returned value can be one of the following values:
00182   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00183   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00184   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00185   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00186   */
00187 __STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx)
00188 {
00189   return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
00190 }
00191
00192 /**
00193   * @brief  Configure X1 buffer size.
00194   * @rmtoll X1BUFCFG     X1_BUF_SIZE   LL_FMAC_SetX1BufferSize
00195   * @param  FMACx FMAC instance
00196   * @param  BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
00197   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00198   * @retval None
00199   */
00200 __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
00201 {
00202   MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
00203 }
00204
00205 /**
00206   * @brief  Return X1 buffer size.
00207   * @rmtoll X1BUFCFG     X1_BUF_SIZE   LL_FMAC_GetX1BufferSize
00208   * @param  FMACx FMAC instance
00209   * @retval uint8_t Number of 16-bit words allocated to the input buffer
00210   *                 (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
00211   */
00212 __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx)
00213 {
00214   return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
00215 }
00216
00217 /**
00218   * @brief  Configure X1 base.
00219   * @rmtoll X1BUFCFG     X1_BASE       LL_FMAC_SetX1Base
00220   * @param  FMACx FMAC instance
00221   * @param  Base Base address of the input buffer (X1) within the internal memory.
00222   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00223   * @retval None
00224   */
00225 __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
00226 {
00227   MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos);
00228 }
00229
00230 /**
00231   * @brief  Return X1 base.
00232   * @rmtoll X1BUFCFG     X1_BASE       LL_FMAC_GetX1Base
00233   * @param  FMACx FMAC instance
00234   * @retval uint8_t Base address of the input buffer (X1) within the internal memory
00235   *                      (value between Min_Data=0x00 and Max_Data=0xFF).
00236   */
00237 __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx)
00238 {
00239   return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
00240 }
00241
00242 /**
00243   * @brief  Configure X2 buffer size.
00244   * @rmtoll X2BUFCFG     X2_BUF_SIZE   LL_FMAC_SetX2BufferSize
00245   * @param  FMACx FMAC instance
00246   * @param  BufferSize Number of 16-bit words allocated to the coefficient buffer.
00247   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00248   * @retval None
00249   */
00250 __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
00251 {
00252   MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
00253 }
00254
00255 /**
00256   * @brief  Return X2 buffer size.
00257   * @rmtoll X2BUFCFG     X2_BUF_SIZE   LL_FMAC_GetX2BufferSize
00258   * @param  FMACx FMAC instance
00259   * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
00260   *                 (value between Min_Data=0x01 and Max_Data=0xFF).
00261   */
00262 __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx)
00263 {
00264   return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
00265 }
00266
00267 /**
00268   * @brief  Configure X2 base.
00269   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_SetX2Base
00270   * @param  FMACx FMAC instance
00271   * @param  Base Base address of the coefficient buffer (X2) within the internal memory.
00272   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00273   * @retval None
00274   */
00275 __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
00276 {
00277   MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos);
00278 }
00279
00280 /**
00281   * @brief  Return X2 base.
00282   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_GetX2Base
00283   * @param  FMACx FMAC instance
00284   * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
00285   *                      (value between Min_Data=0x00 and Max_Data=0xFF).
00286   */
00287 __STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx)
00288 {
00289   return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
00290 }
00291
00292 /**
00293   * @brief  Configure Y empty watermark.
00294   * @rmtoll YBUFCFG      EMPTY_WM      LL_FMAC_SetYEmptyWatermark
00295   * @param  FMACx FMAC instance
00296   * @param  Watermark This parameter can be one of the following values:
00297   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00298   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00299   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00300   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00301   * @retval None
00302   */
00303 __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
00304 {
00305   MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark);
00306 }
00307
00308 /**
00309   * @brief  Return Y empty watermark.
00310   * @rmtoll YBUFCFG      EMPTY_WM      LL_FMAC_GetYEmptyWatermark
00311   * @param  FMACx FMAC instance
00312   * @retval uint32_t Returned value can be one of the following values:
00313   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00314   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00315   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00316   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00317   */
00318 __STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx)
00319 {
00320   return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
00321 }
00322
00323 /**
00324   * @brief  Configure Y buffer size.
00325   * @rmtoll YBUFCFG      Y_BUF_SIZE    LL_FMAC_SetYBufferSize
00326   * @param  FMACx FMAC instance
00327   * @param  BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
00328   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00329   * @retval None
00330   */
00331 __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
00332 {
00333   MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
00334 }
00335
00336 /**
00337   * @brief  Return Y buffer size.
00338   * @rmtoll YBUFCFG      Y_BUF_SIZE    LL_FMAC_GetYBufferSize
00339   * @param  FMACx FMAC instance
00340   * @retval uint8_t Number of 16-bit words allocated to the output buffer
00341   *                (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
00342   */
00343 __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx)
00344 {
00345   return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
00346 }
00347
00348 /**
00349   * @brief  Configure Y base.
00350   * @rmtoll YBUFCFG      Y_BASE        LL_FMAC_SetYBase
00351   * @param  FMACx FMAC instance
00352   * @param  Base Base address of the output buffer (Y) within the internal memory.
00353   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00354   * @retval None
00355   */
00356 __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
00357 {
00358   MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos);
00359 }
00360
00361 /**
00362   * @brief  Return Y base.
00363   * @rmtoll YBUFCFG      Y_BASE        LL_FMAC_GetYBase
00364   * @param  FMACx FMAC instance
00365   * @retval uint8_t Base address of the output buffer (Y) within the internal memory
00366   *                      (value between Min_Data=0x00 and Max_Data=0xFF).
00367   */
00368 __STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx)
00369 {
00370   return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
00371 }
00372
00373 /**
00374   * @brief  Start FMAC processing.
00375   * @rmtoll PARAM        START         LL_FMAC_EnableStart
00376   * @param  FMACx FMAC instance
00377   * @retval None
00378   */
00379 __STATIC_INLINE void LL_FMAC_EnableStart(FMAC_TypeDef *FMACx)
00380 {
00381   SET_BIT(FMACx->PARAM, FMAC_PARAM_START);
00382 }
00383
00384 /**
00385   * @brief  Stop FMAC processing.
00386   * @rmtoll PARAM        START         LL_FMAC_DisableStart
00387   * @param  FMACx FMAC instance
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
00391 {
00392   CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START);
00393 }
00394
00395 /**
00396   * @brief  Check the state of FMAC processing.
00397   * @rmtoll PARAM        START         LL_FMAC_IsEnabledStart
00398   * @param  FMACx FMAC instance
00399   * @retval uint32_t State of bit (1 or 0).
00400   */
00401 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx)
00402 {
00403   return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
00404 }
00405
00406 /**
00407   * @brief  Configure function.
00408   * @rmtoll PARAM        FUNC          LL_FMAC_SetFunction
00409   * @param  FMACx FMAC instance
00410   * @param  Function This parameter can be one of the following values:
00411   *         @arg @ref LL_FMAC_FUNC_LOAD_X1
00412   *         @arg @ref LL_FMAC_FUNC_LOAD_X2
00413   *         @arg @ref LL_FMAC_FUNC_LOAD_Y
00414   *         @arg @ref LL_FMAC_FUNC_CONVO_FIR
00415   *         @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
00416   * @retval None
00417   */
00418 __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
00419 {
00420   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function);
00421 }
00422
00423 /**
00424   * @brief  Return function.
00425   * @rmtoll PARAM        FUNC          LL_FMAC_GetFunction
00426   * @param  FMACx FMAC instance
00427   * @retval uint32_t Returned value can be one of the following values:
00428   *         @arg @ref LL_FMAC_FUNC_LOAD_X1
00429   *         @arg @ref LL_FMAC_FUNC_LOAD_X2
00430   *         @arg @ref LL_FMAC_FUNC_LOAD_Y
00431   *         @arg @ref LL_FMAC_FUNC_CONVO_FIR
00432   *         @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
00433   */
00434 __STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx)
00435 {
00436   return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
00437 }
00438
00439 /**
00440   * @brief  Configure input parameter R.
00441   * @rmtoll PARAM        R             LL_FMAC_SetParamR
00442   * @param  FMACx FMAC instance
00443   * @param  Param Parameter R (gain, etc.).
00444   *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00445   * @retval None
00446   */
00447 __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
00448 {
00449   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos);
00450 }
00451
00452 /**
00453   * @brief  Return input parameter R.
00454   * @rmtoll PARAM        R             LL_FMAC_GetParamR
00455   * @param  FMACx FMAC instance
00456   * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
00457   */
00458 __STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx)
00459 {
00460   return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
00461 }
00462
00463 /**
00464   * @brief  Configure input parameter Q.
00465   * @rmtoll PARAM        Q             LL_FMAC_SetParamQ
00466   * @param  FMACx FMAC instance
00467   * @param  Param Parameter Q (vector length, etc.).
00468   *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
00472 {
00473   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos);
00474 }
00475
00476 /**
00477   * @brief  Return input parameter Q.
00478   * @rmtoll PARAM        Q             LL_FMAC_GetParamQ
00479   * @param  FMACx FMAC instance
00480   * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
00481   */
00482 __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx)
00483 {
00484   return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
00485 }
00486
00487 /**
00488   * @brief  Configure input parameter P.
00489   * @rmtoll PARAM        P             LL_FMAC_SetParamP
00490   * @param  FMACx FMAC instance
00491   * @param  Param Parameter P (vector length, number of filter taps, etc.).
00492   *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00493   * @retval None
00494   */
00495 __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
00496 {
00497   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
00498 }
00499
00500 /**
00501   * @brief  Return input parameter P.
00502   * @rmtoll PARAM        P             LL_FMAC_GetParamP
00503   * @param  FMACx FMAC instance
00504   * @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
00505   *                 (value between Min_Data=0x00 and Max_Data=0xFF).
00506   */
00507 __STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx)
00508 {
00509   return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
00510 }
00511
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup FMAC_LL_EF_Reset_Management Reset_Management
00517   * @{
00518   */
00519
00520 /**
00521   * @brief  Start the FMAC reset.
00522   * @rmtoll CR           RESET         LL_FMAC_EnableReset
00523   * @param  FMACx FMAC instance
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
00527 {
00528   SET_BIT(FMACx->CR, FMAC_CR_RESET);
00529 }
00530
00531 /**
00532   * @brief  Check the state of the FMAC reset.
00533   * @rmtoll CR           RESET         LL_FMAC_IsEnabledReset
00534   * @param  FMACx FMAC instance
00535   * @retval uint32_t State of bit (1 or 0).
00536   */
00537 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx)
00538 {
00539   return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
00540 }
00541
00542 /**
00543   * @}
00544   */
00545
00546 /** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
00547   * @{
00548   */
00549
00550 /**
00551   * @brief  Enable Clipping.
00552   * @rmtoll CR           CLIPEN        LL_FMAC_EnableClipping
00553   * @param  FMACx FMAC instance
00554   * @retval None
00555   */
00556 __STATIC_INLINE void LL_FMAC_EnableClipping(FMAC_TypeDef *FMACx)
00557 {
00558   SET_BIT(FMACx->CR, FMAC_CR_CLIPEN);
00559 }
00560
00561 /**
00562   * @brief  Disable Clipping.
00563   * @rmtoll CR           CLIPEN        LL_FMAC_DisableClipping
00564   * @param  FMACx FMAC instance
00565   * @retval None
00566   */
00567 __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
00568 {
00569   CLEAR_BIT(FMACx->CR, FMAC_CR_CLIPEN);
00570 }
00571
00572 /**
00573   * @brief  Check Clipping State.
00574   * @rmtoll CR           CLIPEN        LL_FMAC_IsEnabledClipping
00575   * @param  FMACx FMAC instance
00576   * @retval uint32_t State of bit (1 or 0).
00577   */
00578 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx)
00579 {
00580   return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
00581 }
00582
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup FMAC_LL_EF_DMA_Management DMA_Management
00588   * @{
00589   */
00590
00591 /**
00592   * @brief  Enable FMAC DMA write channel request.
00593   * @rmtoll CR           DMAWEN        LL_FMAC_EnableDMAReq_WRITE
00594   * @param  FMACx FMAC instance
00595   * @retval None
00596   */
00597 __STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE(FMAC_TypeDef *FMACx)
00598 {
00599   SET_BIT(FMACx->CR, FMAC_CR_DMAWEN);
00600 }
00601
00602 /**
00603   * @brief  Disable FMAC DMA write channel request.
00604   * @rmtoll CR           DMAWEN        LL_FMAC_DisableDMAReq_WRITE
00605   * @param  FMACx FMAC instance
00606   * @retval None
00607   */
00608 __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
00609 {
00610   CLEAR_BIT(FMACx->CR, FMAC_CR_DMAWEN);
00611 }
00612
00613 /**
00614   * @brief  Check FMAC DMA write channel request state.
00615   * @rmtoll CR           DMAWEN        LL_FMAC_IsEnabledDMAReq_WRITE
00616   * @param  FMACx FMAC instance
00617   * @retval uint32_t State of bit (1 or 0).
00618   */
00619 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx)
00620 {
00621   return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
00622 }
00623
00624 /**
00625   * @brief  Enable FMAC DMA read channel request.
00626   * @rmtoll CR           DMAREN        LL_FMAC_EnableDMAReq_READ
00627   * @param  FMACx FMAC instance
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_FMAC_EnableDMAReq_READ(FMAC_TypeDef *FMACx)
00631 {
00632   SET_BIT(FMACx->CR, FMAC_CR_DMAREN);
00633 }
00634
00635 /**
00636   * @brief  Disable FMAC DMA read channel request.
00637   * @rmtoll CR           DMAREN        LL_FMAC_DisableDMAReq_READ
00638   * @param  FMACx FMAC instance
00639   * @retval None
00640   */
00641 __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
00642 {
00643   CLEAR_BIT(FMACx->CR, FMAC_CR_DMAREN);
00644 }
00645
00646 /**
00647   * @brief  Check FMAC DMA read channel request state.
00648   * @rmtoll CR           DMAREN        LL_FMAC_IsEnabledDMAReq_READ
00649   * @param  FMACx FMAC instance
00650   * @retval uint32_t State of bit (1 or 0).
00651   */
00652 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx)
00653 {
00654   return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
00655 }
00656
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup FMAC_LL_EF_IT_Management IT_Management
00662   * @{
00663   */
00664
00665 /**
00666   * @brief  Enable FMAC saturation error interrupt.
00667   * @rmtoll CR           SATIEN        LL_FMAC_EnableIT_SAT
00668   * @param  FMACx FMAC instance
00669   * @retval None
00670   */
00671 __STATIC_INLINE void LL_FMAC_EnableIT_SAT(FMAC_TypeDef *FMACx)
00672 {
00673   SET_BIT(FMACx->CR, FMAC_CR_SATIEN);
00674 }
00675
00676 /**
00677   * @brief  Disable FMAC saturation error interrupt.
00678   * @rmtoll CR           SATIEN        LL_FMAC_DisableIT_SAT
00679   * @param  FMACx FMAC instance
00680   * @retval None
00681   */
00682 __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
00683 {
00684   CLEAR_BIT(FMACx->CR, FMAC_CR_SATIEN);
00685 }
00686
00687 /**
00688   * @brief  Check FMAC saturation error interrupt state.
00689   * @rmtoll CR           SATIEN        LL_FMAC_IsEnabledIT_SAT
00690   * @param  FMACx FMAC instance
00691   * @retval uint32_t State of bit (1 or 0).
00692   */
00693 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx)
00694 {
00695   return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
00696 }
00697
00698 /**
00699   * @brief  Enable FMAC underflow error interrupt.
00700   * @rmtoll CR           UNFLIEN       LL_FMAC_EnableIT_UNFL
00701   * @param  FMACx FMAC instance
00702   * @retval None
00703   */
00704 __STATIC_INLINE void LL_FMAC_EnableIT_UNFL(FMAC_TypeDef *FMACx)
00705 {
00706   SET_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
00707 }
00708
00709 /**
00710   * @brief  Disable FMAC underflow error interrupt.
00711   * @rmtoll CR           UNFLIEN       LL_FMAC_DisableIT_UNFL
00712   * @param  FMACx FMAC instance
00713   * @retval None
00714   */
00715 __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
00716 {
00717   CLEAR_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
00718 }
00719
00720 /**
00721   * @brief  Check FMAC underflow error interrupt state.
00722   * @rmtoll CR           UNFLIEN       LL_FMAC_IsEnabledIT_UNFL
00723   * @param  FMACx FMAC instance
00724   * @retval uint32_t State of bit (1 or 0).
00725   */
00726 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx)
00727 {
00728   return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
00729 }
00730
00731 /**
00732   * @brief  Enable FMAC overflow error interrupt.
00733   * @rmtoll CR           OVFLIEN       LL_FMAC_EnableIT_OVFL
00734   * @param  FMACx FMAC instance
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_FMAC_EnableIT_OVFL(FMAC_TypeDef *FMACx)
00738 {
00739   SET_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
00740 }
00741
00742 /**
00743   * @brief  Disable FMAC overflow error interrupt.
00744   * @rmtoll CR           OVFLIEN       LL_FMAC_DisableIT_OVFL
00745   * @param  FMACx FMAC instance
00746   * @retval None
00747   */
00748 __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
00749 {
00750   CLEAR_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
00751 }
00752
00753 /**
00754   * @brief  Check FMAC overflow error interrupt state.
00755   * @rmtoll CR           OVFLIEN       LL_FMAC_IsEnabledIT_OVFL
00756   * @param  FMACx FMAC instance
00757   * @retval uint32_t State of bit (1 or 0).
00758   */
00759 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx)
00760 {
00761   return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
00762 }
00763
00764 /**
00765   * @brief  Enable FMAC write interrupt.
00766   * @rmtoll CR           WIEN          LL_FMAC_EnableIT_WR
00767   * @param  FMACx FMAC instance
00768   * @retval None
00769   */
00770 __STATIC_INLINE void LL_FMAC_EnableIT_WR(FMAC_TypeDef *FMACx)
00771 {
00772   SET_BIT(FMACx->CR, FMAC_CR_WIEN);
00773 }
00774
00775 /**
00776   * @brief  Disable FMAC write interrupt.
00777   * @rmtoll CR           WIEN          LL_FMAC_DisableIT_WR
00778   * @param  FMACx FMAC instance
00779   * @retval None
00780   */
00781 __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
00782 {
00783   CLEAR_BIT(FMACx->CR, FMAC_CR_WIEN);
00784 }
00785
00786 /**
00787   * @brief  Check FMAC write interrupt state.
00788   * @rmtoll CR           WIEN          LL_FMAC_IsEnabledIT_WR
00789   * @param  FMACx FMAC instance
00790   * @retval uint32_t State of bit (1 or 0).
00791   */
00792 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx)
00793 {
00794   return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
00795 }
00796
00797 /**
00798   * @brief  Enable FMAC read interrupt.
00799   * @rmtoll CR           RIEN          LL_FMAC_EnableIT_RD
00800   * @param  FMACx FMAC instance
00801   * @retval None
00802   */
00803 __STATIC_INLINE void LL_FMAC_EnableIT_RD(FMAC_TypeDef *FMACx)
00804 {
00805   SET_BIT(FMACx->CR, FMAC_CR_RIEN);
00806 }
00807
00808 /**
00809   * @brief  Disable FMAC read interrupt.
00810   * @rmtoll CR           RIEN          LL_FMAC_DisableIT_RD
00811   * @param  FMACx FMAC instance
00812   * @retval None
00813   */
00814 __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
00815 {
00816   CLEAR_BIT(FMACx->CR, FMAC_CR_RIEN);
00817 }
00818
00819 /**
00820   * @brief  Check FMAC read interrupt state.
00821   * @rmtoll CR           RIEN          LL_FMAC_IsEnabledIT_RD
00822   * @param  FMACx FMAC instance
00823   * @retval uint32_t State of bit (1 or 0).
00824   */
00825 __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx)
00826 {
00827   return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
00828 }
00829
00830 /**
00831   * @}
00832   */
00833
00834 /** @defgroup FMAC_LL_EF_FLAG_Management FLAG_Management
00835   * @{
00836   */
00837
00838 /**
00839   * @brief  Check FMAC saturation error flag state.
00840   * @rmtoll SR           SAT           LL_FMAC_IsActiveFlag_SAT
00841   * @param  FMACx FMAC instance
00842   * @retval uint32_t State of bit (1 or 0).
00843   */
00844 __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx)
00845 {
00846   return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
00847 }
00848
00849 /**
00850   * @brief  Check FMAC underflow error flag state.
00851   * @rmtoll SR           UNFL          LL_FMAC_IsActiveFlag_UNFL
00852   * @param  FMACx FMAC instance
00853   * @retval uint32_t State of bit (1 or 0).
00854   */
00855 __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx)
00856 {
00857   return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
00858 }
00859
00860 /**
00861   * @brief  Check FMAC overflow error flag state.
00862   * @rmtoll SR           OVFL          LL_FMAC_IsActiveFlag_OVFL
00863   * @param  FMACx FMAC instance
00864   * @retval uint32_t State of bit (1 or 0).
00865   */
00866 __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx)
00867 {
00868   return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
00869 }
00870
00871 /**
00872   * @brief  Check FMAC X1 buffer full flag state.
00873   * @rmtoll SR           X1FULL        LL_FMAC_IsActiveFlag_X1FULL
00874   * @param  FMACx FMAC instance
00875   * @retval uint32_t State of bit (1 or 0).
00876   */
00877 __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx)
00878 {
00879   return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
00880 }
00881
00882 /**
00883   * @brief  Check FMAC Y buffer empty flag state.
00884   * @rmtoll SR           YEMPTY        LL_FMAC_IsActiveFlag_YEMPTY
00885   * @param  FMACx FMAC instance
00886   * @retval uint32_t State of bit (1 or 0).
00887   */
00888 __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx)
00889 {
00890   return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
00891 }
00892
00893 /**
00894   * @}
00895   */
00896
00897 /** @defgroup FMAC_LL_EF_Data_Management Data_Management
00898   * @{
00899   */
00900
00901 /**
00902   * @brief  Write 16-bit input data for the FMAC processing.
00903   * @rmtoll WDATA        WDATA         LL_FMAC_WriteData
00904   * @param  FMACx FMAC instance
00905   * @param  InData 16-bit value to be provided as input data for FMAC processing.
00906   *                This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00907   * @retval None
00908   */
00909 __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
00910 {
00911   WRITE_REG(FMACx->WDATA, InData);
00912 }
00913
00914 /**
00915   * @brief  Return 16-bit output data of FMAC processing.
00916   * @rmtoll RDATA        RDATA         LL_FMAC_ReadData
00917   * @param  FMACx FMAC instance
00918   * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
00919   */
00920 __STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx)
00921 {
00922   return (uint16_t)(READ_REG(FMACx->RDATA));
00923 }
00924
00925 /**
00926   * @}
00927   */
00928
00929 /** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
00930   * @{
00931   */
00932
00933 /**
00934   * @brief  Configure memory for X1 buffer.
00935   * @rmtoll X1BUFCFG     FULL_WM       LL_FMAC_ConfigX1\n
00936   *         X1BUFCFG     X1_BASE       LL_FMAC_ConfigX1\n
00937   *         X1BUFCFG     X1_BUF_SIZE   LL_FMAC_ConfigX1
00938   * @param  FMACx FMAC instance
00939   * @param  Watermark This parameter can be one of the following values:
00940   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00941   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00942   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00943   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00944   * @param  Base Base address of the input buffer (X1) within the internal memory.
00945   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00946   * @param  BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
00947   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00948   * @retval None
00949   */
00950 __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
00951 {
00952   MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
00953              Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
00954              (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
00955 }
00956
00957 /**
00958   * @brief  Configure memory for X2 buffer.
00959   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_ConfigX2\n
00960   *         X2BUFCFG     X2_BUF_SIZE   LL_FMAC_ConfigX2
00961   * @param  FMACx FMAC instance
00962   * @param  Base Base address of the coefficient buffer (X2) within the internal memory.
00963   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00964   * @param  BufferSize Number of 16-bit words allocated to the coefficient buffer.
00965   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00966   * @retval None
00967   */
00968 __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
00969 {
00970   MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
00971              (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
00972              (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
00973 }
00974
00975 /**
00976   * @brief  Configure memory for Y buffer.
00977   * @rmtoll YBUFCFG      EMPTY_WM      LL_FMAC_ConfigY\n
00978   *         YBUFCFG      Y_BASE        LL_FMAC_ConfigY\n
00979   *         YBUFCFG      Y_BUF_SIZE    LL_FMAC_ConfigY
00980   * @param  FMACx FMAC instance
00981   * @param  Watermark This parameter can be one of the following values:
00982   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
00983   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
00984   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
00985   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
00986   * @param  Base Base address of the output buffer (Y) within the internal memory.
00987   *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
00988   * @param  BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
00989   *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
00993 {
00994   MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
00995              Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
00996              (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
00997 }
00998
00999 /**
01000   * @brief  Configure the FMAC processing.
01001   * @rmtoll PARAM        START         LL_FMAC_ConfigFunc\n
01002   *         PARAM        FUNC          LL_FMAC_ConfigFunc\n
01003   *         PARAM        P             LL_FMAC_ConfigFunc\n
01004   *         PARAM        Q             LL_FMAC_ConfigFunc\n
01005   *         PARAM        R             LL_FMAC_ConfigFunc
01006   * @param  FMACx FMAC instance
01007   * @param  Start This parameter can be one of the following values:
01008   *         @arg @ref LL_FMAC_PROCESSING_STOP
01009   *         @arg @ref LL_FMAC_PROCESSING_START
01010   * @param  Function This parameter can be one of the following values:
01011   *         @arg @ref LL_FMAC_FUNC_LOAD_X1
01012   *         @arg @ref LL_FMAC_FUNC_LOAD_X2
01013   *         @arg @ref LL_FMAC_FUNC_LOAD_Y
01014   *         @arg @ref LL_FMAC_FUNC_CONVO_FIR
01015   *         @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
01016   * @param  ParamP Parameter P (vector length, number of filter taps, etc.).
01017   *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01018   * @param  ParamQ Parameter Q (vector length, etc.).
01019   *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01020   * @param  ParamR Parameter R (gain, etc.).
01021   *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01022   * @retval None
01023   */
01024 __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
01025                                         uint8_t ParamQ, uint8_t ParamR)
01026 {
01027   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
01028              (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
01029              (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
01030 }
01031
01032 /**
01033   * @}
01034   */
01035
01036
01037
01038 #if defined(USE_FULL_LL_DRIVER)
01039 /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
01040   * @{
01041   */
01042 ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
01043 ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx);
01044
01045
01046 /**
01047   * @}
01048   */
01049 #endif /* USE_FULL_LL_DRIVER */
01050
01051 /**
01052   * @}
01053   */
01054
01055 /**
01056   * @}
01057   */
01058
01059 #endif /* defined(FMAC) */
01060
01061 /**
01062   * @}
01063   */
01064
01065 #ifdef __cplusplus
01066 }
01067 #endif
01068
01069 #endif /* STM32G4xx_LL_FMAC_H */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_gpio.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_gpio.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
00034
00035 /** @addtogroup GPIO_LL
00036   * @{
00037   */
00038 /** MISRA C:2012 deviation rule has been granted for following rules:
00039   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00040   * range of the shift operator in following API :
00041   * LL_GPIO_Init
00042   */
00043
00044 /* Private types -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private constants ---------------------------------------------------------*/
00047 /* Private macros ------------------------------------------------------------*/
00048 /** @addtogroup GPIO_LL_Private_Macros
00049   * @{
00050   */
00051 #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00052
00053 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00054                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00055                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00056                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00057
00058 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00059                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00060
00061 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00062                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00063                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
00064                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
00065
00066 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00067                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00068                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00069
00070 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00071                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00072                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00073                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00074                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00075                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00076                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00077                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00078                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00079                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00080                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
00081                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
00082                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
00083                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
00084                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
00085                                             ((__VALUE__) == LL_GPIO_AF_15 ))
00086 /**
00087   * @}
00088   */
00089
00090 /* Private function prototypes -----------------------------------------------*/
00091
00092 /* Exported functions --------------------------------------------------------*/
00093 /** @addtogroup GPIO_LL_Exported_Functions
00094   * @{
00095   */
00096
00097 /** @addtogroup GPIO_LL_EF_Init
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00103   * @param  GPIOx GPIO Port
00104   * @retval An ErrorStatus enumeration value:
00105   *          - SUCCESS: GPIO registers are de-initialized
00106   *          - ERROR:   Wrong GPIO Port
00107   */
00108 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00109 {
00110   ErrorStatus status = SUCCESS;
00111
00112   /* Check the parameters */
00113   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00114
00115   /* Force and Release reset on clock of GPIOx Port */
00116   if (GPIOx == GPIOA)
00117   {
00118     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00119     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00120   }
00121   else if (GPIOx == GPIOB)
00122   {
00123     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00124     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00125   }
00126   else if (GPIOx == GPIOC)
00127   {
00128     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00129     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00130   }
00131   else if (GPIOx == GPIOD)
00132   {
00133     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00134     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00135   }
00136   else if (GPIOx == GPIOE)
00137   {
00138     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00139     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00140   }
00141   else if (GPIOx == GPIOF)
00142   {
00143     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);
00144     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);
00145   }
00146   else if (GPIOx == GPIOG)
00147   {
00148     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);
00149     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);
00150   }
00151   else
00152   {
00153     status = ERROR;
00154   }
00155
00156   return (status);
00157 }
00158
00159 /**
00160   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00161   * @param  GPIOx GPIO Port
00162   * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00163   *         that contains the configuration information for the specified GPIO peripheral.
00164   * @retval An ErrorStatus enumeration value:
00165   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00166   *          - ERROR:   Not applicable
00167   */
00168 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00169 {
00170   uint32_t pinpos;
00171   uint32_t currentpin;
00172
00173   /* Check the parameters */
00174   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00175   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00176   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00177   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00178
00179   /* ------------------------- Configure the port pins ---------------- */
00180   /* Initialize  pinpos on first pin set */
00181   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00182
00183   /* Configure the port pins */
00184   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
00185   {
00186     /* Get current io position */
00187     currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
00188
00189     if (currentpin != 0x00u)
00190     {
00191       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00192       {
00193         /* Check Speed mode parameters */
00194         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00195
00196         /* Speed mode configuration */
00197         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00198
00199         /* Check Output mode parameters */
00200         assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00201
00202         /* Output mode configuration*/
00203         LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00204       }
00205
00206       /* Pull-up Pull down resistor configuration*/
00207       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00208
00209       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00210       {
00211         /* Check Alternate parameter */
00212         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00213
00214         /* Speed mode configuration */
00215         if (currentpin < LL_GPIO_PIN_8)
00216         {
00217           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00218         }
00219         else
00220         {
00221           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00222         }
00223       }
00224
00225       /* Pin Mode configuration */
00226       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00227     }
00228     pinpos++;
00229   }
00230   return (SUCCESS);
00231 }
00232
00233 /**
00234   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00235   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00236   *                          whose fields will be set to default values.
00237   * @retval None
00238   */
00239
00240 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00241 {
00242   /* Reset GPIO init structure parameters values */
00243   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00244   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00245   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00246   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00247   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00248   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00249 }
00250
00251 /**
00252   * @}
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 /**
00260   * @}
00261   */
00262
00263 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
00264
00265 /**
00266   * @}
00267   */
00268
00269 #endif /* USE_FULL_LL_DRIVER */
00270
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_gpio.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_GPIO_H
00021 #define STM32G4xx_LL_GPIO_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
00035
00036 /** @defgroup GPIO_LL GPIO
00037   * @{
00038   */
00039 /** MISRA C:2012 deviation rule has been granted for following rules:
00040   * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
00041   * which may be out of array bounds [..,UNKNOWN] in following APIs:
00042   * LL_GPIO_GetAFPin_0_7
00043   * LL_GPIO_SetAFPin_0_7
00044   * LL_GPIO_SetAFPin_8_15
00045   * LL_GPIO_GetAFPin_8_15
00046   */
00047
00048 /* Private types -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private constants ---------------------------------------------------------*/
00051 /* Private macros ------------------------------------------------------------*/
00052 #if defined(USE_FULL_LL_DRIVER)
00053 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00054   * @{
00055   */
00056
00057 /**
00058   * @}
00059   */
00060 #endif /*USE_FULL_LL_DRIVER*/
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00065   * @{
00066   */
00067
00068 /**
00069   * @brief LL GPIO Init Structure definition
00070   */
00071 typedef struct
00072 {
00073   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00074                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00075
00076   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00077                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00078
00079                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00080
00081   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00082                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00083
00084                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00085
00086   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00087                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00088
00089                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00090
00091   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00092                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00093
00094                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00095
00096   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00097                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00098
00099                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00100 } LL_GPIO_InitTypeDef;
00101
00102 /**
00103   * @}
00104   */
00105 #endif /* USE_FULL_LL_DRIVER */
00106
00107 /* Exported constants --------------------------------------------------------*/
00108 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00109   * @{
00110   */
00111
00112 /** @defgroup GPIO_LL_EC_PIN PIN
00113   * @{
00114   */
00115 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
00116 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
00117 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
00118 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
00119 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
00120 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
00121 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
00122 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
00123 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
00124 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
00125 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
00126 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
00127 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
00128 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
00129 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
00130 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
00131 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
00132                                            GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
00133                                            GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
00134                                            GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
00135                                            GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
00136                                            GPIO_BSRR_BS15) /*!< Select all pins */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup GPIO_LL_EC_MODE Mode
00142   * @{
00143   */
00144 #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
00145 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
00146 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
00147 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00153   * @{
00154   */
00155 #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
00156 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00162   * @{
00163   */
00164 #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
00165 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
00166 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
00167 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
00168 /**
00169   * @}
00170   */
00171 #define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
00172 #define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
00173 #define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
00174 #define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
00175
00176 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00177   * @{
00178   */
00179 #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
00180 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
00181 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup GPIO_LL_EC_AF Alternate Function
00187   * @{
00188   */
00189 #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
00190 #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
00191 #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
00192 #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
00193 #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
00194 #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
00195 #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
00196 #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
00197 #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
00198 #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
00199 #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
00200 #define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
00201 #define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
00202 #define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
00203 #define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
00204 #define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
00205 /**
00206   * @}
00207   */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported macro ------------------------------------------------------------*/
00214 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00215   * @{
00216   */
00217
00218 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Write a value in GPIO register
00224   * @param  __INSTANCE__ GPIO Instance
00225   * @param  __REG__ Register to be written
00226   * @param  __VALUE__ Value to be written in the register
00227   * @retval None
00228   */
00229 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00230
00231 /**
00232   * @brief  Read a value in GPIO register
00233   * @param  __INSTANCE__ GPIO Instance
00234   * @param  __REG__ Register to be read
00235   * @retval Register value
00236   */
00237 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /* Exported functions --------------------------------------------------------*/
00247 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00248   * @{
00249   */
00250
00251 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00252   * @{
00253   */
00254
00255 /**
00256   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00257   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00258   * @note   Warning: only one pin can be passed as parameter.
00259   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00260   * @param  GPIOx GPIO Port
00261   * @param  Pin This parameter can be one of the following values:
00262   *         @arg @ref LL_GPIO_PIN_0
00263   *         @arg @ref LL_GPIO_PIN_1
00264   *         @arg @ref LL_GPIO_PIN_2
00265   *         @arg @ref LL_GPIO_PIN_3
00266   *         @arg @ref LL_GPIO_PIN_4
00267   *         @arg @ref LL_GPIO_PIN_5
00268   *         @arg @ref LL_GPIO_PIN_6
00269   *         @arg @ref LL_GPIO_PIN_7
00270   *         @arg @ref LL_GPIO_PIN_8
00271   *         @arg @ref LL_GPIO_PIN_9
00272   *         @arg @ref LL_GPIO_PIN_10
00273   *         @arg @ref LL_GPIO_PIN_11
00274   *         @arg @ref LL_GPIO_PIN_12
00275   *         @arg @ref LL_GPIO_PIN_13
00276   *         @arg @ref LL_GPIO_PIN_14
00277   *         @arg @ref LL_GPIO_PIN_15
00278   * @param  Mode This parameter can be one of the following values:
00279   *         @arg @ref LL_GPIO_MODE_INPUT
00280   *         @arg @ref LL_GPIO_MODE_OUTPUT
00281   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00282   *         @arg @ref LL_GPIO_MODE_ANALOG
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00286 {
00287   MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
00288 }
00289
00290 /**
00291   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00292   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00293   * @note   Warning: only one pin can be passed as parameter.
00294   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00295   * @param  GPIOx GPIO Port
00296   * @param  Pin This parameter can be one of the following values:
00297   *         @arg @ref LL_GPIO_PIN_0
00298   *         @arg @ref LL_GPIO_PIN_1
00299   *         @arg @ref LL_GPIO_PIN_2
00300   *         @arg @ref LL_GPIO_PIN_3
00301   *         @arg @ref LL_GPIO_PIN_4
00302   *         @arg @ref LL_GPIO_PIN_5
00303   *         @arg @ref LL_GPIO_PIN_6
00304   *         @arg @ref LL_GPIO_PIN_7
00305   *         @arg @ref LL_GPIO_PIN_8
00306   *         @arg @ref LL_GPIO_PIN_9
00307   *         @arg @ref LL_GPIO_PIN_10
00308   *         @arg @ref LL_GPIO_PIN_11
00309   *         @arg @ref LL_GPIO_PIN_12
00310   *         @arg @ref LL_GPIO_PIN_13
00311   *         @arg @ref LL_GPIO_PIN_14
00312   *         @arg @ref LL_GPIO_PIN_15
00313   * @retval Returned value can be one of the following values:
00314   *         @arg @ref LL_GPIO_MODE_INPUT
00315   *         @arg @ref LL_GPIO_MODE_OUTPUT
00316   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00317   *         @arg @ref LL_GPIO_MODE_ANALOG
00318   */
00319 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00320 {
00321   return (uint32_t)(READ_BIT(GPIOx->MODER,
00322                              (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00323 }
00324
00325 /**
00326   * @brief  Configure gpio output type for several pins on dedicated port.
00327   * @note   Output type as to be set when gpio pin is in output or
00328   *         alternate modes. Possible type are Push-pull or Open-drain.
00329   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00330   * @param  GPIOx GPIO Port
00331   * @param  PinMask This parameter can be a combination of the following values:
00332   *         @arg @ref LL_GPIO_PIN_0
00333   *         @arg @ref LL_GPIO_PIN_1
00334   *         @arg @ref LL_GPIO_PIN_2
00335   *         @arg @ref LL_GPIO_PIN_3
00336   *         @arg @ref LL_GPIO_PIN_4
00337   *         @arg @ref LL_GPIO_PIN_5
00338   *         @arg @ref LL_GPIO_PIN_6
00339   *         @arg @ref LL_GPIO_PIN_7
00340   *         @arg @ref LL_GPIO_PIN_8
00341   *         @arg @ref LL_GPIO_PIN_9
00342   *         @arg @ref LL_GPIO_PIN_10
00343   *         @arg @ref LL_GPIO_PIN_11
00344   *         @arg @ref LL_GPIO_PIN_12
00345   *         @arg @ref LL_GPIO_PIN_13
00346   *         @arg @ref LL_GPIO_PIN_14
00347   *         @arg @ref LL_GPIO_PIN_15
00348   *         @arg @ref LL_GPIO_PIN_ALL
00349   * @param  OutputType This parameter can be one of the following values:
00350   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00351   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00352   * @retval None
00353   */
00354 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00355 {
00356   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00357 }
00358
00359 /**
00360   * @brief  Return gpio output type for several pins on dedicated port.
00361   * @note   Output type as to be set when gpio pin is in output or
00362   *         alternate modes. Possible type are Push-pull or Open-drain.
00363   * @note   Warning: only one pin can be passed as parameter.
00364   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00365   * @param  GPIOx GPIO Port
00366   * @param  Pin This parameter can be one of the following values:
00367   *         @arg @ref LL_GPIO_PIN_0
00368   *         @arg @ref LL_GPIO_PIN_1
00369   *         @arg @ref LL_GPIO_PIN_2
00370   *         @arg @ref LL_GPIO_PIN_3
00371   *         @arg @ref LL_GPIO_PIN_4
00372   *         @arg @ref LL_GPIO_PIN_5
00373   *         @arg @ref LL_GPIO_PIN_6
00374   *         @arg @ref LL_GPIO_PIN_7
00375   *         @arg @ref LL_GPIO_PIN_8
00376   *         @arg @ref LL_GPIO_PIN_9
00377   *         @arg @ref LL_GPIO_PIN_10
00378   *         @arg @ref LL_GPIO_PIN_11
00379   *         @arg @ref LL_GPIO_PIN_12
00380   *         @arg @ref LL_GPIO_PIN_13
00381   *         @arg @ref LL_GPIO_PIN_14
00382   *         @arg @ref LL_GPIO_PIN_15
00383   *         @arg @ref LL_GPIO_PIN_ALL
00384   * @retval Returned value can be one of the following values:
00385   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00386   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00387   */
00388 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00389 {
00390   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
00391 }
00392
00393 /**
00394   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00395   * @note   I/O speed can be Low, Medium, Fast or High speed.
00396   * @note   Warning: only one pin can be passed as parameter.
00397   * @note   Refer to datasheet for frequency specifications and the power
00398   *         supply and load conditions for each speed.
00399   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00400   * @param  GPIOx GPIO Port
00401   * @param  Pin This parameter can be one of the following values:
00402   *         @arg @ref LL_GPIO_PIN_0
00403   *         @arg @ref LL_GPIO_PIN_1
00404   *         @arg @ref LL_GPIO_PIN_2
00405   *         @arg @ref LL_GPIO_PIN_3
00406   *         @arg @ref LL_GPIO_PIN_4
00407   *         @arg @ref LL_GPIO_PIN_5
00408   *         @arg @ref LL_GPIO_PIN_6
00409   *         @arg @ref LL_GPIO_PIN_7
00410   *         @arg @ref LL_GPIO_PIN_8
00411   *         @arg @ref LL_GPIO_PIN_9
00412   *         @arg @ref LL_GPIO_PIN_10
00413   *         @arg @ref LL_GPIO_PIN_11
00414   *         @arg @ref LL_GPIO_PIN_12
00415   *         @arg @ref LL_GPIO_PIN_13
00416   *         @arg @ref LL_GPIO_PIN_14
00417   *         @arg @ref LL_GPIO_PIN_15
00418   * @param  Speed This parameter can be one of the following values:
00419   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00420   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00421   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00422   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00423   * @retval None
00424   */
00425 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00426 {
00427   MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
00428              (Speed << (POSITION_VAL(Pin) * 2U)));
00429 }
00430
00431 /**
00432   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00433   * @note   I/O speed can be Low, Medium, Fast or High speed.
00434   * @note   Warning: only one pin can be passed as parameter.
00435   * @note   Refer to datasheet for frequency specifications and the power
00436   *         supply and load conditions for each speed.
00437   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00438   * @param  GPIOx GPIO Port
00439   * @param  Pin This parameter can be one of the following values:
00440   *         @arg @ref LL_GPIO_PIN_0
00441   *         @arg @ref LL_GPIO_PIN_1
00442   *         @arg @ref LL_GPIO_PIN_2
00443   *         @arg @ref LL_GPIO_PIN_3
00444   *         @arg @ref LL_GPIO_PIN_4
00445   *         @arg @ref LL_GPIO_PIN_5
00446   *         @arg @ref LL_GPIO_PIN_6
00447   *         @arg @ref LL_GPIO_PIN_7
00448   *         @arg @ref LL_GPIO_PIN_8
00449   *         @arg @ref LL_GPIO_PIN_9
00450   *         @arg @ref LL_GPIO_PIN_10
00451   *         @arg @ref LL_GPIO_PIN_11
00452   *         @arg @ref LL_GPIO_PIN_12
00453   *         @arg @ref LL_GPIO_PIN_13
00454   *         @arg @ref LL_GPIO_PIN_14
00455   *         @arg @ref LL_GPIO_PIN_15
00456   * @retval Returned value can be one of the following values:
00457   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00458   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00459   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00460   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00461   */
00462 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00463 {
00464   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
00465                              (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00466 }
00467
00468 /**
00469   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00470   * @note   Warning: only one pin can be passed as parameter.
00471   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00472   * @param  GPIOx GPIO Port
00473   * @param  Pin This parameter can be one of the following values:
00474   *         @arg @ref LL_GPIO_PIN_0
00475   *         @arg @ref LL_GPIO_PIN_1
00476   *         @arg @ref LL_GPIO_PIN_2
00477   *         @arg @ref LL_GPIO_PIN_3
00478   *         @arg @ref LL_GPIO_PIN_4
00479   *         @arg @ref LL_GPIO_PIN_5
00480   *         @arg @ref LL_GPIO_PIN_6
00481   *         @arg @ref LL_GPIO_PIN_7
00482   *         @arg @ref LL_GPIO_PIN_8
00483   *         @arg @ref LL_GPIO_PIN_9
00484   *         @arg @ref LL_GPIO_PIN_10
00485   *         @arg @ref LL_GPIO_PIN_11
00486   *         @arg @ref LL_GPIO_PIN_12
00487   *         @arg @ref LL_GPIO_PIN_13
00488   *         @arg @ref LL_GPIO_PIN_14
00489   *         @arg @ref LL_GPIO_PIN_15
00490   * @param  Pull This parameter can be one of the following values:
00491   *         @arg @ref LL_GPIO_PULL_NO
00492   *         @arg @ref LL_GPIO_PULL_UP
00493   *         @arg @ref LL_GPIO_PULL_DOWN
00494   * @retval None
00495   */
00496 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00497 {
00498   MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
00499 }
00500
00501 /**
00502   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00503   * @note   Warning: only one pin can be passed as parameter.
00504   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00505   * @param  GPIOx GPIO Port
00506   * @param  Pin This parameter can be one of the following values:
00507   *         @arg @ref LL_GPIO_PIN_0
00508   *         @arg @ref LL_GPIO_PIN_1
00509   *         @arg @ref LL_GPIO_PIN_2
00510   *         @arg @ref LL_GPIO_PIN_3
00511   *         @arg @ref LL_GPIO_PIN_4
00512   *         @arg @ref LL_GPIO_PIN_5
00513   *         @arg @ref LL_GPIO_PIN_6
00514   *         @arg @ref LL_GPIO_PIN_7
00515   *         @arg @ref LL_GPIO_PIN_8
00516   *         @arg @ref LL_GPIO_PIN_9
00517   *         @arg @ref LL_GPIO_PIN_10
00518   *         @arg @ref LL_GPIO_PIN_11
00519   *         @arg @ref LL_GPIO_PIN_12
00520   *         @arg @ref LL_GPIO_PIN_13
00521   *         @arg @ref LL_GPIO_PIN_14
00522   *         @arg @ref LL_GPIO_PIN_15
00523   * @retval Returned value can be one of the following values:
00524   *         @arg @ref LL_GPIO_PULL_NO
00525   *         @arg @ref LL_GPIO_PULL_UP
00526   *         @arg @ref LL_GPIO_PULL_DOWN
00527   */
00528 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00529 {
00530   return (uint32_t)(READ_BIT(GPIOx->PUPDR,
00531                              (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00532 }
00533
00534 /**
00535   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00536   * @note   Possible values are from AF0 to AF15 depending on target.
00537   * @note   Warning: only one pin can be passed as parameter.
00538   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00539   * @param  GPIOx GPIO Port
00540   * @param  Pin This parameter can be one of the following values:
00541   *         @arg @ref LL_GPIO_PIN_0
00542   *         @arg @ref LL_GPIO_PIN_1
00543   *         @arg @ref LL_GPIO_PIN_2
00544   *         @arg @ref LL_GPIO_PIN_3
00545   *         @arg @ref LL_GPIO_PIN_4
00546   *         @arg @ref LL_GPIO_PIN_5
00547   *         @arg @ref LL_GPIO_PIN_6
00548   *         @arg @ref LL_GPIO_PIN_7
00549   * @param  Alternate This parameter can be one of the following values:
00550   *         @arg @ref LL_GPIO_AF_0
00551   *         @arg @ref LL_GPIO_AF_1
00552   *         @arg @ref LL_GPIO_AF_2
00553   *         @arg @ref LL_GPIO_AF_3
00554   *         @arg @ref LL_GPIO_AF_4
00555   *         @arg @ref LL_GPIO_AF_5
00556   *         @arg @ref LL_GPIO_AF_6
00557   *         @arg @ref LL_GPIO_AF_7
00558   *         @arg @ref LL_GPIO_AF_8
00559   *         @arg @ref LL_GPIO_AF_9
00560   *         @arg @ref LL_GPIO_AF_10
00561   *         @arg @ref LL_GPIO_AF_11
00562   *         @arg @ref LL_GPIO_AF_12
00563   *         @arg @ref LL_GPIO_AF_13
00564   *         @arg @ref LL_GPIO_AF_14
00565   *         @arg @ref LL_GPIO_AF_15
00566   * @retval None
00567   */
00568 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00569 {
00570   MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
00571              (Alternate << (POSITION_VAL(Pin) * 4U)));
00572 }
00573
00574 /**
00575   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00576   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00577   * @param  GPIOx GPIO Port
00578   * @param  Pin This parameter can be one of the following values:
00579   *         @arg @ref LL_GPIO_PIN_0
00580   *         @arg @ref LL_GPIO_PIN_1
00581   *         @arg @ref LL_GPIO_PIN_2
00582   *         @arg @ref LL_GPIO_PIN_3
00583   *         @arg @ref LL_GPIO_PIN_4
00584   *         @arg @ref LL_GPIO_PIN_5
00585   *         @arg @ref LL_GPIO_PIN_6
00586   *         @arg @ref LL_GPIO_PIN_7
00587   * @retval Returned value can be one of the following values:
00588   *         @arg @ref LL_GPIO_AF_0
00589   *         @arg @ref LL_GPIO_AF_1
00590   *         @arg @ref LL_GPIO_AF_2
00591   *         @arg @ref LL_GPIO_AF_3
00592   *         @arg @ref LL_GPIO_AF_4
00593   *         @arg @ref LL_GPIO_AF_5
00594   *         @arg @ref LL_GPIO_AF_6
00595   *         @arg @ref LL_GPIO_AF_7
00596   *         @arg @ref LL_GPIO_AF_8
00597   *         @arg @ref LL_GPIO_AF_9
00598   *         @arg @ref LL_GPIO_AF_10
00599   *         @arg @ref LL_GPIO_AF_11
00600   *         @arg @ref LL_GPIO_AF_12
00601   *         @arg @ref LL_GPIO_AF_13
00602   *         @arg @ref LL_GPIO_AF_14
00603   *         @arg @ref LL_GPIO_AF_15
00604   */
00605 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00606 {
00607   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00608                              (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00609 }
00610
00611 /**
00612   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00613   * @note   Possible values are from AF0 to AF15 depending on target.
00614   * @note   Warning: only one pin can be passed as parameter.
00615   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00616   * @param  GPIOx GPIO Port
00617   * @param  Pin This parameter can be one of the following values:
00618   *         @arg @ref LL_GPIO_PIN_8
00619   *         @arg @ref LL_GPIO_PIN_9
00620   *         @arg @ref LL_GPIO_PIN_10
00621   *         @arg @ref LL_GPIO_PIN_11
00622   *         @arg @ref LL_GPIO_PIN_12
00623   *         @arg @ref LL_GPIO_PIN_13
00624   *         @arg @ref LL_GPIO_PIN_14
00625   *         @arg @ref LL_GPIO_PIN_15
00626   * @param  Alternate This parameter can be one of the following values:
00627   *         @arg @ref LL_GPIO_AF_0
00628   *         @arg @ref LL_GPIO_AF_1
00629   *         @arg @ref LL_GPIO_AF_2
00630   *         @arg @ref LL_GPIO_AF_3
00631   *         @arg @ref LL_GPIO_AF_4
00632   *         @arg @ref LL_GPIO_AF_5
00633   *         @arg @ref LL_GPIO_AF_6
00634   *         @arg @ref LL_GPIO_AF_7
00635   *         @arg @ref LL_GPIO_AF_8
00636   *         @arg @ref LL_GPIO_AF_9
00637   *         @arg @ref LL_GPIO_AF_10
00638   *         @arg @ref LL_GPIO_AF_11
00639   *         @arg @ref LL_GPIO_AF_12
00640   *         @arg @ref LL_GPIO_AF_13
00641   *         @arg @ref LL_GPIO_AF_14
00642   *         @arg @ref LL_GPIO_AF_15
00643   * @retval None
00644   */
00645 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00646 {
00647   MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
00648              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
00649 }
00650
00651 /**
00652   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00653   * @note   Possible values are from AF0 to AF15 depending on target.
00654   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00655   * @param  GPIOx GPIO Port
00656   * @param  Pin This parameter can be one of the following values:
00657   *         @arg @ref LL_GPIO_PIN_8
00658   *         @arg @ref LL_GPIO_PIN_9
00659   *         @arg @ref LL_GPIO_PIN_10
00660   *         @arg @ref LL_GPIO_PIN_11
00661   *         @arg @ref LL_GPIO_PIN_12
00662   *         @arg @ref LL_GPIO_PIN_13
00663   *         @arg @ref LL_GPIO_PIN_14
00664   *         @arg @ref LL_GPIO_PIN_15
00665   * @retval Returned value can be one of the following values:
00666   *         @arg @ref LL_GPIO_AF_0
00667   *         @arg @ref LL_GPIO_AF_1
00668   *         @arg @ref LL_GPIO_AF_2
00669   *         @arg @ref LL_GPIO_AF_3
00670   *         @arg @ref LL_GPIO_AF_4
00671   *         @arg @ref LL_GPIO_AF_5
00672   *         @arg @ref LL_GPIO_AF_6
00673   *         @arg @ref LL_GPIO_AF_7
00674   *         @arg @ref LL_GPIO_AF_8
00675   *         @arg @ref LL_GPIO_AF_9
00676   *         @arg @ref LL_GPIO_AF_10
00677   *         @arg @ref LL_GPIO_AF_11
00678   *         @arg @ref LL_GPIO_AF_12
00679   *         @arg @ref LL_GPIO_AF_13
00680   *         @arg @ref LL_GPIO_AF_14
00681   *         @arg @ref LL_GPIO_AF_15
00682   */
00683 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00684 {
00685   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00686                              (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
00687 }
00688
00689
00690 /**
00691   * @brief  Lock configuration of several pins for a dedicated port.
00692   * @note   When the lock sequence has been applied on a port bit, the
00693   *         value of this port bit can no longer be modified until the
00694   *         next reset.
00695   * @note   Each lock bit freezes a specific configuration register
00696   *         (control and alternate function registers).
00697   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00698   * @param  GPIOx GPIO Port
00699   * @param  PinMask This parameter can be a combination of the following values:
00700   *         @arg @ref LL_GPIO_PIN_0
00701   *         @arg @ref LL_GPIO_PIN_1
00702   *         @arg @ref LL_GPIO_PIN_2
00703   *         @arg @ref LL_GPIO_PIN_3
00704   *         @arg @ref LL_GPIO_PIN_4
00705   *         @arg @ref LL_GPIO_PIN_5
00706   *         @arg @ref LL_GPIO_PIN_6
00707   *         @arg @ref LL_GPIO_PIN_7
00708   *         @arg @ref LL_GPIO_PIN_8
00709   *         @arg @ref LL_GPIO_PIN_9
00710   *         @arg @ref LL_GPIO_PIN_10
00711   *         @arg @ref LL_GPIO_PIN_11
00712   *         @arg @ref LL_GPIO_PIN_12
00713   *         @arg @ref LL_GPIO_PIN_13
00714   *         @arg @ref LL_GPIO_PIN_14
00715   *         @arg @ref LL_GPIO_PIN_15
00716   *         @arg @ref LL_GPIO_PIN_ALL
00717   * @retval None
00718   */
00719 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00720 {
00721   __IO uint32_t temp;
00722   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00723   WRITE_REG(GPIOx->LCKR, PinMask);
00724   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00725   /* Read LCKR register. This read is mandatory to complete key lock sequence */
00726   temp = READ_REG(GPIOx->LCKR);
00727   (void) temp;
00728 }
00729
00730 /**
00731   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00732   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00733   * @param  GPIOx GPIO Port
00734   * @param  PinMask This parameter can be a combination of the following values:
00735   *         @arg @ref LL_GPIO_PIN_0
00736   *         @arg @ref LL_GPIO_PIN_1
00737   *         @arg @ref LL_GPIO_PIN_2
00738   *         @arg @ref LL_GPIO_PIN_3
00739   *         @arg @ref LL_GPIO_PIN_4
00740   *         @arg @ref LL_GPIO_PIN_5
00741   *         @arg @ref LL_GPIO_PIN_6
00742   *         @arg @ref LL_GPIO_PIN_7
00743   *         @arg @ref LL_GPIO_PIN_8
00744   *         @arg @ref LL_GPIO_PIN_9
00745   *         @arg @ref LL_GPIO_PIN_10
00746   *         @arg @ref LL_GPIO_PIN_11
00747   *         @arg @ref LL_GPIO_PIN_12
00748   *         @arg @ref LL_GPIO_PIN_13
00749   *         @arg @ref LL_GPIO_PIN_14
00750   *         @arg @ref LL_GPIO_PIN_15
00751   *         @arg @ref LL_GPIO_PIN_ALL
00752   * @retval State of bit (1 or 0).
00753   */
00754 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00755 {
00756   return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
00757 }
00758
00759 /**
00760   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00761   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00762   * @param  GPIOx GPIO Port
00763   * @retval State of bit (1 or 0).
00764   */
00765 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00766 {
00767   return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
00768 }
00769
00770 /**
00771   * @}
00772   */
00773
00774 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00775   * @{
00776   */
00777
00778 /**
00779   * @brief  Return full input data register value for a dedicated port.
00780   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00781   * @param  GPIOx GPIO Port
00782   * @retval Input data register value of port
00783   */
00784 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00785 {
00786   return (uint32_t)(READ_REG(GPIOx->IDR));
00787 }
00788
00789 /**
00790   * @brief  Return if input data level for several pins of dedicated port is high or low.
00791   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00792   * @param  GPIOx GPIO Port
00793   * @param  PinMask This parameter can be a combination of the following values:
00794   *         @arg @ref LL_GPIO_PIN_0
00795   *         @arg @ref LL_GPIO_PIN_1
00796   *         @arg @ref LL_GPIO_PIN_2
00797   *         @arg @ref LL_GPIO_PIN_3
00798   *         @arg @ref LL_GPIO_PIN_4
00799   *         @arg @ref LL_GPIO_PIN_5
00800   *         @arg @ref LL_GPIO_PIN_6
00801   *         @arg @ref LL_GPIO_PIN_7
00802   *         @arg @ref LL_GPIO_PIN_8
00803   *         @arg @ref LL_GPIO_PIN_9
00804   *         @arg @ref LL_GPIO_PIN_10
00805   *         @arg @ref LL_GPIO_PIN_11
00806   *         @arg @ref LL_GPIO_PIN_12
00807   *         @arg @ref LL_GPIO_PIN_13
00808   *         @arg @ref LL_GPIO_PIN_14
00809   *         @arg @ref LL_GPIO_PIN_15
00810   *         @arg @ref LL_GPIO_PIN_ALL
00811   * @retval State of bit (1 or 0).
00812   */
00813 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00814 {
00815   return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
00816 }
00817
00818 /**
00819   * @brief  Write output data register for the port.
00820   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00821   * @param  GPIOx GPIO Port
00822   * @param  PortValue Level value for each pin of the port
00823   * @retval None
00824   */
00825 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00826 {
00827   WRITE_REG(GPIOx->ODR, PortValue);
00828 }
00829
00830 /**
00831   * @brief  Return full output data register value for a dedicated port.
00832   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00833   * @param  GPIOx GPIO Port
00834   * @retval Output data register value of port
00835   */
00836 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00837 {
00838   return (uint32_t)(READ_REG(GPIOx->ODR));
00839 }
00840
00841 /**
00842   * @brief  Return if input data level for several pins of dedicated port is high or low.
00843   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00844   * @param  GPIOx GPIO Port
00845   * @param  PinMask This parameter can be a combination of the following values:
00846   *         @arg @ref LL_GPIO_PIN_0
00847   *         @arg @ref LL_GPIO_PIN_1
00848   *         @arg @ref LL_GPIO_PIN_2
00849   *         @arg @ref LL_GPIO_PIN_3
00850   *         @arg @ref LL_GPIO_PIN_4
00851   *         @arg @ref LL_GPIO_PIN_5
00852   *         @arg @ref LL_GPIO_PIN_6
00853   *         @arg @ref LL_GPIO_PIN_7
00854   *         @arg @ref LL_GPIO_PIN_8
00855   *         @arg @ref LL_GPIO_PIN_9
00856   *         @arg @ref LL_GPIO_PIN_10
00857   *         @arg @ref LL_GPIO_PIN_11
00858   *         @arg @ref LL_GPIO_PIN_12
00859   *         @arg @ref LL_GPIO_PIN_13
00860   *         @arg @ref LL_GPIO_PIN_14
00861   *         @arg @ref LL_GPIO_PIN_15
00862   *         @arg @ref LL_GPIO_PIN_ALL
00863   * @retval State of bit (1 or 0).
00864   */
00865 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00866 {
00867   return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
00868 }
00869
00870 /**
00871   * @brief  Set several pins to high level on dedicated gpio port.
00872   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00873   * @param  GPIOx GPIO Port
00874   * @param  PinMask This parameter can be a combination of the following values:
00875   *         @arg @ref LL_GPIO_PIN_0
00876   *         @arg @ref LL_GPIO_PIN_1
00877   *         @arg @ref LL_GPIO_PIN_2
00878   *         @arg @ref LL_GPIO_PIN_3
00879   *         @arg @ref LL_GPIO_PIN_4
00880   *         @arg @ref LL_GPIO_PIN_5
00881   *         @arg @ref LL_GPIO_PIN_6
00882   *         @arg @ref LL_GPIO_PIN_7
00883   *         @arg @ref LL_GPIO_PIN_8
00884   *         @arg @ref LL_GPIO_PIN_9
00885   *         @arg @ref LL_GPIO_PIN_10
00886   *         @arg @ref LL_GPIO_PIN_11
00887   *         @arg @ref LL_GPIO_PIN_12
00888   *         @arg @ref LL_GPIO_PIN_13
00889   *         @arg @ref LL_GPIO_PIN_14
00890   *         @arg @ref LL_GPIO_PIN_15
00891   *         @arg @ref LL_GPIO_PIN_ALL
00892   * @retval None
00893   */
00894 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00895 {
00896   WRITE_REG(GPIOx->BSRR, PinMask);
00897 }
00898
00899 /**
00900   * @brief  Set several pins to low level on dedicated gpio port.
00901   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00902   * @param  GPIOx GPIO Port
00903   * @param  PinMask This parameter can be a combination of the following values:
00904   *         @arg @ref LL_GPIO_PIN_0
00905   *         @arg @ref LL_GPIO_PIN_1
00906   *         @arg @ref LL_GPIO_PIN_2
00907   *         @arg @ref LL_GPIO_PIN_3
00908   *         @arg @ref LL_GPIO_PIN_4
00909   *         @arg @ref LL_GPIO_PIN_5
00910   *         @arg @ref LL_GPIO_PIN_6
00911   *         @arg @ref LL_GPIO_PIN_7
00912   *         @arg @ref LL_GPIO_PIN_8
00913   *         @arg @ref LL_GPIO_PIN_9
00914   *         @arg @ref LL_GPIO_PIN_10
00915   *         @arg @ref LL_GPIO_PIN_11
00916   *         @arg @ref LL_GPIO_PIN_12
00917   *         @arg @ref LL_GPIO_PIN_13
00918   *         @arg @ref LL_GPIO_PIN_14
00919   *         @arg @ref LL_GPIO_PIN_15
00920   *         @arg @ref LL_GPIO_PIN_ALL
00921   * @retval None
00922   */
00923 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00924 {
00925   WRITE_REG(GPIOx->BRR, PinMask);
00926 }
00927
00928 /**
00929   * @brief  Toggle data value for several pin of dedicated port.
00930   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00931   * @param  GPIOx GPIO Port
00932   * @param  PinMask This parameter can be a combination of the following values:
00933   *         @arg @ref LL_GPIO_PIN_0
00934   *         @arg @ref LL_GPIO_PIN_1
00935   *         @arg @ref LL_GPIO_PIN_2
00936   *         @arg @ref LL_GPIO_PIN_3
00937   *         @arg @ref LL_GPIO_PIN_4
00938   *         @arg @ref LL_GPIO_PIN_5
00939   *         @arg @ref LL_GPIO_PIN_6
00940   *         @arg @ref LL_GPIO_PIN_7
00941   *         @arg @ref LL_GPIO_PIN_8
00942   *         @arg @ref LL_GPIO_PIN_9
00943   *         @arg @ref LL_GPIO_PIN_10
00944   *         @arg @ref LL_GPIO_PIN_11
00945   *         @arg @ref LL_GPIO_PIN_12
00946   *         @arg @ref LL_GPIO_PIN_13
00947   *         @arg @ref LL_GPIO_PIN_14
00948   *         @arg @ref LL_GPIO_PIN_15
00949   *         @arg @ref LL_GPIO_PIN_ALL
00950   * @retval None
00951   */
00952 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00953 {
00954   uint32_t odr = READ_REG(GPIOx->ODR);
00955   WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
00956 }
00957
00958 /**
00959   * @}
00960   */
00961
00962 #if defined(USE_FULL_LL_DRIVER)
00963 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
00964   * @{
00965   */
00966
00967 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
00968 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
00969 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
00970
00971 /**
00972   * @}
00973   */
00974 #endif /* USE_FULL_LL_DRIVER */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /**
00981   * @}
00982   */
00983
00984 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
00985 /**
00986   * @}
00987   */
00988
00989 #ifdef __cplusplus
00990 }
00991 #endif
00992
00993 #endif /* STM32G4xx_LL_GPIO_H */
00994
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_hrtim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_hrtim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_hrtim.c
00004   * @author  MCD Application Team
00005   * @brief   HRTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_hrtim.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (HRTIM1)
00035
00036 /** @addtogroup HRTIM_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Private function prototypes -----------------------------------------------*/
00045 /* Exported functions --------------------------------------------------------*/
00046 /** @addtogroup HRTIM_LL_Exported_Functions
00047   * @{
00048   */
00049 /**
00050   * @brief  Set HRTIM instance registers to their reset values.
00051   * @param  HRTIMx High Resolution Timer instance
00052   * @retval ErrorStatus enumeration value:
00053   *          - SUCCESS: HRTIMx registers are de-initialized
00054   *          - ERROR: invalid HRTIMx instance
00055   */
00056 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
00057 {
00058   ErrorStatus result = SUCCESS;
00059
00060   /* Check the parameters */
00061   assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
00062   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
00063   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
00064   return result;
00065 }
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 #endif /* HRTIM1 */
00075
00076 /**
00077   * @}
00078   */
00079
00080 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:28 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_hrtim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_hrtim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_hrtim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HRTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_HRTIM_H
00021 #define STM32G4xx_LL_HRTIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (HRTIM1)
00035
00036 /** @defgroup HRTIM_LL HRTIM
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
00043   * @{
00044   */
00045 static const uint16_t REG_OFFSET_TAB_TIMER[] =
00046 {
00047   0x00U,   /* 0: MASTER  */
00048   0x80U,   /* 1: TIMER A */
00049   0x100U,  /* 2: TIMER B */
00050   0x180U,  /* 3: TIMER C */
00051   0x200U,  /* 4: TIMER D */
00052   0x280U,  /* 5: TIMER E */
00053   0x300U,  /* 6: TIMER F */
00054 };
00055
00056 static const uint8_t REG_OFFSET_TAB_ADCER[] =
00057 {
00058   0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_ADC1R */
00059   0x04U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_ADC2R */
00060   0x08U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_ADC3R */
00061   0x0CU,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_ADC4R */
00062   0x3CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCER */
00063   0x3CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCER */
00064   0x3CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCER */
00065   0x3CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCER */
00066   0x3CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCER */
00067   0x3CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
00068 };
00069
00070 static const uint8_t REG_OFFSET_TAB_ADCUR[] =
00071 {
00072   0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_CR1   */
00073   0x00U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_CR1   */
00074   0x00U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_CR1   */
00075   0x00U,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_CR1   */
00076   0x7CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCUR */
00077   0x7CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCUR */
00078   0x7CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCUR */
00079   0x7CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCUR */
00080   0x7CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCUR */
00081   0x7CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
00082 };
00083
00084 static const uint8_t REG_SHIFT_TAB_ADCER[] =
00085 {
00086   0,   /* LL_HRTIM_ADCTRIG_1  */
00087   0,   /* LL_HRTIM_ADCTRIG_2  */
00088   0,   /* LL_HRTIM_ADCTRIG_3  */
00089   0,   /* LL_HRTIM_ADCTRIG_4  */
00090   0,   /* LL_HRTIM_ADCTRIG_5  */
00091   5,   /* LL_HRTIM_ADCTRIG_6  */
00092   10,  /* LL_HRTIM_ADCTRIG_7  */
00093   16,  /* LL_HRTIM_ADCTRIG_8  */
00094   21,  /* LL_HRTIM_ADCTRIG_9  */
00095   26   /* LL_HRTIM_ADCTRIG_10 */
00096 };
00097
00098 static const uint8_t REG_SHIFT_TAB_ADCUR[] =
00099 {
00100   16,   /* LL_HRTIM_ADCTRIG_1  */
00101   19,   /* LL_HRTIM_ADCTRIG_2  */
00102   22,   /* LL_HRTIM_ADCTRIG_3  */
00103   25,   /* LL_HRTIM_ADCTRIG_4  */
00104   0,    /* LL_HRTIM_ADCTRIG_5  */
00105   4,    /* LL_HRTIM_ADCTRIG_6  */
00106   8,    /* LL_HRTIM_ADCTRIG_7  */
00107   12,   /* LL_HRTIM_ADCTRIG_8  */
00108   16,   /* LL_HRTIM_ADCTRIG_9  */
00109   20    /* LL_HRTIM_ADCTRIG_10 */
00110 };
00111
00112 static const uint32_t REG_MASK_TAB_ADCER[] =
00113 {
00114   0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_1  */
00115   0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_2  */
00116   0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_3  */
00117   0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_4  */
00118   0x0000001FU,   /* LL_HRTIM_ADCTRIG_5  */
00119   0x000003E0U,   /* LL_HRTIM_ADCTRIG_6  */
00120   0x00007C00U,   /* LL_HRTIM_ADCTRIG_7  */
00121   0x001F0000U,   /* LL_HRTIM_ADCTRIG_8  */
00122   0x03E00000U,   /* LL_HRTIM_ADCTRIG_9  */
00123   0x7C000000U    /* LL_HRTIM_ADCTRIG_10 */
00124 };
00125
00126 static const uint32_t REG_MASK_TAB_ADCUR[] =
00127 {
00128   0x00070000U,   /* LL_HRTIM_ADCTRIG_1  */
00129   0x00380000U,   /* LL_HRTIM_ADCTRIG_2  */
00130   0x01C00000U,   /* LL_HRTIM_ADCTRIG_3  */
00131   0x0E000000U,   /* LL_HRTIM_ADCTRIG_4  */
00132   0x00000007U,   /* LL_HRTIM_ADCTRIG_5  */
00133   0x00000070U,   /* LL_HRTIM_ADCTRIG_6  */
00134   0x00000700U,   /* LL_HRTIM_ADCTRIG_7  */
00135   0x00007000U,   /* LL_HRTIM_ADCTRIG_8  */
00136   0x00070000U,   /* LL_HRTIM_ADCTRIG_9  */
00137   0x00700000U    /* LL_HRTIM_ADCTRIG_10 */
00138 };
00139
00140 static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
00141 {
00142   0U,    /* 0: HRTIM_ADC1R  */
00143   6U,    /* 1: HRTIM_ADC2R  */
00144   12U,   /* 2: HRTIM_ADC3R  */
00145   18U,   /* 3: HRTIM_ADC4R  */
00146   24U,   /* 4: HRTIM_ADC5R  */
00147   32U,   /* 5: HRTIM_ADC6R  */
00148   38U,   /* 6: HRTIM_ADC7R  */
00149   44U,   /* 7: HRTIM_ADC8R  */
00150   50U,   /* 8: HRTIM_ADC9R  */
00151   56U    /* 9: HRTIM_ADC10R */
00152 };
00153
00154 static const uint16_t REG_OFFSET_TAB_SETxR[] =
00155 {
00156   0x00U,   /* 0: TA1 */
00157   0x08U,   /* 1: TA2 */
00158   0x80U,   /* 2: TB1 */
00159   0x88U,   /* 3: TB2 */
00160   0x100U,  /* 4: TC1 */
00161   0x108U,  /* 5: TC2 */
00162   0x180U,  /* 6: TD1 */
00163   0x188U,  /* 7: TD2 */
00164   0x200U,  /* 8: TE1 */
00165   0x208U,  /* 9: TE2 */
00166   0x280U,  /* 10: TF1 */
00167   0x288U   /* 11: TF2 */
00168 };
00169
00170 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
00171 {
00172   0x00U,   /*  0: TA1 */
00173   0x00U,   /*  1: TA2 */
00174   0x80U,   /*  2: TB1 */
00175   0x80U,   /*  3: TB2 */
00176   0x100U,  /*  4: TC1 */
00177   0x100U,  /*  5: TC2 */
00178   0x180U,  /*  6: TD1 */
00179   0x180U,  /*  7: TD2 */
00180   0x200U,  /*  8: TE1 */
00181   0x200U,  /*  9: TE2 */
00182   0x280U,  /* 10: TF1 */
00183   0x280U   /* 11: TF2 */
00184 };
00185
00186 static const uint8_t REG_OFFSET_TAB_EECR[] =
00187 {
00188   0x00U, /* LL_HRTIM_EVENT_1 */
00189   0x00U, /* LL_HRTIM_EVENT_2 */
00190   0x00U, /* LL_HRTIM_EVENT_3 */
00191   0x00U, /* LL_HRTIM_EVENT_4 */
00192   0x00U, /* LL_HRTIM_EVENT_5 */
00193   0x04U, /* LL_HRTIM_EVENT_6 */
00194   0x04U, /* LL_HRTIM_EVENT_7 */
00195   0x04U, /* LL_HRTIM_EVENT_8 */
00196   0x04U, /* LL_HRTIM_EVENT_9 */
00197   0x04U  /* LL_HRTIM_EVENT_10 */
00198 };
00199
00200 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
00201 {
00202   0x00U, /* LL_HRTIM_FAULT_1 */
00203   0x00U, /* LL_HRTIM_FAULT_2 */
00204   0x00U, /* LL_HRTIM_FAULT_3 */
00205   0x00U, /* LL_HRTIM_FAULT_4 */
00206   0x04U, /* LL_HRTIM_FAULT_5 */
00207   0x04U  /* LL_HRTIM_FAULT_6 */
00208 };
00209
00210 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
00211 {
00212   0x20000000U,  /* 0: MASTER  */
00213   0x01FF0000U,  /* 1: TIMER A */
00214   0x01FF0000U,  /* 2: TIMER B */
00215   0x01FF0000U,  /* 3: TIMER C */
00216   0x01FF0000U,  /* 4: TIMER D */
00217   0x01FF0000U,  /* 5: TIMER E */
00218   0x01FF0000U,  /* 5: TIMER E */
00219   0x01FF0000U   /* 6: TIMER F */
00220 };
00221
00222 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
00223 {
00224   12U, /* 0: MASTER  */
00225   0U,  /* 1: TIMER A */
00226   0U,  /* 2: TIMER B  */
00227   0U,  /* 3: TIMER C */
00228   0U,  /* 4: TIMER D  */
00229   0U,  /* 5: TIMER E */
00230   0U   /* 6: TIMER F */
00231 };
00232
00233 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
00234 {
00235   0U,  /* LL_HRTIM_EVENT_1  */
00236   6U,  /* LL_HRTIM_EVENT_2  */
00237   12U, /* LL_HRTIM_EVENT_3  */
00238   18U, /* LL_HRTIM_EVENT_4  */
00239   24U, /* LL_HRTIM_EVENT_5  */
00240   0U,  /* LL_HRTIM_EVENT_6  */
00241   6U,  /* LL_HRTIM_EVENT_7  */
00242   12U, /* LL_HRTIM_EVENT_8  */
00243   18U, /* LL_HRTIM_EVENT_9  */
00244   24U  /* LL_HRTIM_EVENT_10 */
00245 };
00246
00247 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
00248 {
00249   HRTIM_MCR_BRSTDMA,   /* 0: MASTER  */
00250   HRTIM_TIMCR_UPDGAT,  /* 1: TIMER A */
00251   HRTIM_TIMCR_UPDGAT,  /* 2: TIMER B  */
00252   HRTIM_TIMCR_UPDGAT,  /* 3: TIMER C */
00253   HRTIM_TIMCR_UPDGAT,  /* 4: TIMER D  */
00254   HRTIM_TIMCR_UPDGAT,  /* 5: TIMER E */
00255   HRTIM_TIMCR_UPDGAT   /* 6: TIMER F */
00256 };
00257
00258 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
00259 {
00260   2U, /* 0: MASTER  */
00261   0U, /* 1: TIMER A */
00262   0U, /* 2: TIMER B  */
00263   0U, /* 3: TIMER C */
00264   0U, /* 4: TIMER D  */
00265   0U, /* 5: TIMER E */
00266   0U  /* 6: TIMER F */
00267 };
00268
00269 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
00270 {
00271   0U,  /* 0: TA1  */
00272   16U, /* 1: TA2 */
00273   0U,  /* 2: TB1  */
00274   16U, /* 3: TB2 */
00275   0U,  /* 4: TC1  */
00276   16U, /* 5: TC2 */
00277   0U,  /* 6: TD1  */
00278   16U, /* 7: TD2 */
00279   0U,  /* 8: TE1  */
00280   16U, /* 9: TE2 */
00281   0U,  /* 10: TF1  */
00282   16U  /* 11: TF2 */
00283 };
00284
00285 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
00286 {
00287   0U,  /* 0: TA1  */
00288   1U,  /* 1: TA2 */
00289   0U,  /* 2: TB1  */
00290   1U,  /* 3: TB2 */
00291   0U,  /* 4: TC1  */
00292   1U,  /* 5: TC2 */
00293   0U,  /* 6: TD1  */
00294   1U,  /* 7: TD2 */
00295   0U,  /* 8: TE1  */
00296   1U,  /* 9: TE2 */
00297   0U,  /* 10: TF1  */
00298   1U   /* 11: TF2 */
00299 };
00300
00301 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
00302 {
00303   0U,   /* LL_HRTIM_FAULT_1 */
00304   8U,   /* LL_HRTIM_FAULT_2 */
00305   16U,  /* LL_HRTIM_FAULT_3 */
00306   24U,  /* LL_HRTIM_FAULT_4 */
00307   0U,   /* LL_HRTIM_FAULT_5 */
00308   8U    /* LL_HRTIM_FAULT_6 */
00309 };
00310
00311 static const uint8_t REG_SHIFT_TAB_FLTxF[] =
00312 {
00313   0U,   /* LL_HRTIM_FAULT_1 */
00314   8U,   /* LL_HRTIM_FAULT_2 */
00315   16U,  /* LL_HRTIM_FAULT_3 */
00316   24U,  /* LL_HRTIM_FAULT_4 */
00317   32U,  /* LL_HRTIM_FAULT_5 */
00318   40U   /* LL_HRTIM_FAULT_6 */
00319 };
00320
00321 static const uint8_t REG_SHIFT_TAB_FLTxCNT[] =
00322 {
00323   2U,   /* LL_HRTIM_FAULT_1 */
00324   10U,  /* LL_HRTIM_FAULT_2 */
00325   18U,  /* LL_HRTIM_FAULT_3 */
00326   26U,  /* LL_HRTIM_FAULT_4 */
00327   2U,   /* LL_HRTIM_FAULT_5 */
00328   10U   /* LL_HRTIM_FAULT_6 */
00329 };
00330
00331 static const uint8_t REG_SHIFT_TAB_FLTx[] =
00332 {
00333   0,  /* LL_HRTIM_FAULT_1 */
00334   1,  /* LL_HRTIM_FAULT_2 */
00335   2,  /* LL_HRTIM_FAULT_3 */
00336   3,  /* LL_HRTIM_FAULT_4 */
00337   4,  /* LL_HRTIM_FAULT_5 */
00338   5   /* LL_HRTIM_FAULT_6 */
00339 };
00340
00341 static const uint8_t REG_SHIFT_TAB_INTLVD[] =
00342 {
00343   0U,  /* 0: MASTER  */
00344   1U,  /* 1: TIMER A */
00345   1U,  /* 2: TIMER B */
00346   1U,  /* 3: TIMER C */
00347   1U,  /* 4: TIMER D */
00348   1U,  /* 5: TIMER E */
00349   1U,  /* 6: TIMER F */
00350 };
00351
00352 static const uint32_t REG_MASK_TAB_INTLVD[] =
00353 {
00354   0x000000E0U,  /* 0: MASTER  */
00355   0x000001A0U,  /* 1: TIMER A */
00356   0x000001A0U,  /* 2: TIMER B */
00357   0x000001A0U,  /* 3: TIMER C */
00358   0x000001A0U,  /* 4: TIMER D */
00359   0x000001A0U,  /* 5: TIMER E */
00360   0x000001A0U,  /* 6: TIMER F */
00361 };
00362
00363 static const uint8_t REG_SHIFT_TAB_CPT[] =
00364 {
00365   12U,  /* 1: TIMER A */
00366   16U,  /* 2: TIMER B */
00367   20U,  /* 3: TIMER C */
00368   24U,  /* 4: TIMER D */
00369   28U,  /* 5: TIMER E */
00370   32U,  /* 6: TIMER F */
00371 };
00372
00373 static const uint32_t REG_MASK_TAB_CPT[] =
00374 {
00375   0xFFFF0000U,  /* 1: TIMER A */
00376   0xFFF0F000U,  /* 2: TIMER B */
00377   0xFF0FF000U,  /* 3: TIMER C */
00378   0xF0FFF000U,  /* 4: TIMER D */
00379   0x0FFFF000U,  /* 5: TIMER E */
00380   0xFFFFF000U,  /* 6: TIMER F */
00381 };
00382
00383 /**
00384   * @}
00385   */
00386
00387
00388 /* Private constants ---------------------------------------------------------*/
00389 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
00390   * @{
00391   */
00392 #define HRTIM_CR1_UDIS_MASK   ((uint32_t)(HRTIM_CR1_MUDIS  |\
00393                                           HRTIM_CR1_TAUDIS |\
00394                                           HRTIM_CR1_TBUDIS |\
00395                                           HRTIM_CR1_TCUDIS |\
00396                                           HRTIM_CR1_TDUDIS |\
00397                                           HRTIM_CR1_TEUDIS |\
00398                                           HRTIM_CR1_TFUDIS))
00399
00400 #define HRTIM_CR2_SWUPD_MASK   ((uint32_t)(HRTIM_CR2_MSWU |\
00401                                            HRTIM_CR2_TASWU |\
00402                                            HRTIM_CR2_TBSWU |\
00403                                            HRTIM_CR2_TCSWU |\
00404                                            HRTIM_CR2_TDSWU |\
00405                                            HRTIM_CR2_TESWU |\
00406                                            HRTIM_CR2_TFSWU))
00407
00408 #define HRTIM_CR2_SWAP_MASK   ((uint32_t)(HRTIM_CR2_SWPA |\
00409                                           HRTIM_CR2_SWPB |\
00410                                           HRTIM_CR2_SWPC |\
00411                                           HRTIM_CR2_SWPD |\
00412                                           HRTIM_CR2_SWPE |\
00413                                           HRTIM_CR2_SWPF))
00414
00415 #define HRTIM_CR2_SWRST_MASK   ((uint32_t)(HRTIM_CR2_MRST |\
00416                                            HRTIM_CR2_TARST |\
00417                                            HRTIM_CR2_TBRST |\
00418                                            HRTIM_CR2_TCRST |\
00419                                            HRTIM_CR2_TDRST |\
00420                                            HRTIM_CR2_TERST |\
00421                                            HRTIM_CR2_TFRST))
00422
00423 #define HRTIM_OENR_OEN_MASK   ((uint32_t)(HRTIM_OENR_TA1OEN |\
00424                                           HRTIM_OENR_TA2OEN |\
00425                                           HRTIM_OENR_TB1OEN |\
00426                                           HRTIM_OENR_TB2OEN |\
00427                                           HRTIM_OENR_TC1OEN |\
00428                                           HRTIM_OENR_TC2OEN |\
00429                                           HRTIM_OENR_TD1OEN |\
00430                                           HRTIM_OENR_TD2OEN |\
00431                                           HRTIM_OENR_TE1OEN |\
00432                                           HRTIM_OENR_TE2OEN |\
00433                                           HRTIM_OENR_TF1OEN |\
00434                                           HRTIM_OENR_TF2OEN))
00435
00436 #define HRTIM_OENR_ODIS_MASK  ((uint32_t)(HRTIM_ODISR_TA1ODIS  |\
00437                                           HRTIM_ODISR_TA2ODIS  |\
00438                                           HRTIM_ODISR_TB1ODIS  |\
00439                                           HRTIM_ODISR_TB2ODIS  |\
00440                                           HRTIM_ODISR_TC1ODIS  |\
00441                                           HRTIM_ODISR_TC2ODIS  |\
00442                                           HRTIM_ODISR_TD1ODIS  |\
00443                                           HRTIM_ODISR_TD2ODIS  |\
00444                                           HRTIM_ODISR_TE1ODIS  |\
00445                                           HRTIM_ODISR_TE2ODIS  |\
00446                                           HRTIM_ODISR_TF1ODIS  |\
00447                                           HRTIM_ODISR_TF2ODIS))
00448
00449 #define HRTIM_OUT_CONFIG_MASK  ((uint32_t)(HRTIM_OUTR_POL1   |\
00450                                            HRTIM_OUTR_IDLM1  |\
00451                                            HRTIM_OUTR_IDLES1 |\
00452                                            HRTIM_OUTR_FAULT1 |\
00453                                            HRTIM_OUTR_CHP1   |\
00454                                            HRTIM_OUTR_DIDL1))
00455
00456 #define HRTIM_EE_CONFIG_MASK   ((uint32_t)(HRTIM_EECR1_EE1SRC |\
00457                                            HRTIM_EECR1_EE1POL |\
00458                                            HRTIM_EECR1_EE1SNS |\
00459                                            HRTIM_EECR1_EE1FAST))
00460
00461 #define HRTIM_FLT_CONFIG_MASK   ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
00462                                             HRTIM_FLTINR1_FLT1SRC_0 ))
00463
00464 #define HRTIM_FLT_SRC_1_MASK   ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
00465                                            HRTIM_FLTINR2_FLT5SRC_1 |\
00466                                            HRTIM_FLTINR2_FLT4SRC_1 |\
00467                                            HRTIM_FLTINR2_FLT3SRC_1 |\
00468                                            HRTIM_FLTINR2_FLT2SRC_1 |\
00469                                            HRTIM_FLTINR2_FLT1SRC_1))
00470
00471 #define HRTIM_BM_CONFIG_MASK   ((uint32_t)( HRTIM_BMCR_BMPRSC |\
00472                                             HRTIM_BMCR_BMCLK  |\
00473                                             HRTIM_BMCR_BMOM))
00474
00475 /**
00476   * @}
00477   */
00478
00479
00480 /* Private macros ------------------------------------------------------------*/
00481 /* Exported types ------------------------------------------------------------*/
00482 /* Exported constants --------------------------------------------------------*/
00483 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
00484   * @{
00485   */
00486
00487 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
00488   * @brief    Flags defines which can be used with LL_HRTIM_ReadReg function
00489   * @{
00490   */
00491 #define LL_HRTIM_ISR_FLT1                  HRTIM_ISR_FLT1
00492 #define LL_HRTIM_ISR_FLT2                  HRTIM_ISR_FLT2
00493 #define LL_HRTIM_ISR_FLT3                  HRTIM_ISR_FLT3
00494 #define LL_HRTIM_ISR_FLT4                  HRTIM_ISR_FLT4
00495 #define LL_HRTIM_ISR_FLT5                  HRTIM_ISR_FLT5
00496 #define LL_HRTIM_ISR_FLT6                  HRTIM_ISR_FLT6
00497 #define LL_HRTIM_ISR_SYSFLT                HRTIM_ISR_SYSFLT
00498 #define LL_HRTIM_ISR_DLLRDY                HRTIM_ISR_DLLRDY
00499 #define LL_HRTIM_ISR_BMPER                 HRTIM_ISR_BMPER
00500
00501 #define LL_HRTIM_MISR_MCMP1                HRTIM_MISR_MCMP1
00502 #define LL_HRTIM_MISR_MCMP2                HRTIM_MISR_MCMP2
00503 #define LL_HRTIM_MISR_MCMP3                HRTIM_MISR_MCMP3
00504 #define LL_HRTIM_MISR_MCMP4                HRTIM_MISR_MCMP4
00505 #define LL_HRTIM_MISR_MREP                 HRTIM_MISR_MREP
00506 #define LL_HRTIM_MISR_SYNC                 HRTIM_MISR_SYNC
00507 #define LL_HRTIM_MISR_MUPD                 HRTIM_MISR_MUPD
00508
00509 #define LL_HRTIM_TIMISR_CMP1               HRTIM_TIMISR_CMP1
00510 #define LL_HRTIM_TIMISR_CMP2               HRTIM_TIMISR_CMP2
00511 #define LL_HRTIM_TIMISR_CMP3               HRTIM_TIMISR_CMP3
00512 #define LL_HRTIM_TIMISR_CMP4               HRTIM_TIMISR_CMP4
00513 #define LL_HRTIM_TIMISR_REP                HRTIM_TIMISR_REP
00514 #define LL_HRTIM_TIMISR_UPD                HRTIM_TIMISR_UPD
00515 #define LL_HRTIM_TIMISR_CPT1               HRTIM_TIMISR_CPT1
00516 #define LL_HRTIM_TIMISR_CPT2               HRTIM_TIMISR_CPT2
00517 #define LL_HRTIM_TIMISR_SET1               HRTIM_TIMISR_SET1
00518 #define LL_HRTIM_TIMISR_RST1               HRTIM_TIMISR_RST1
00519 #define LL_HRTIM_TIMISR_SET2               HRTIM_TIMISR_SET2
00520 #define LL_HRTIM_TIMISR_RST2               HRTIM_TIMISR_RST2
00521 #define LL_HRTIM_TIMISR_RST                HRTIM_TIMISR_RST
00522 #define LL_HRTIM_TIMISR_DLYPRT             HRTIM_TIMISR_DLYPRT
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup HRTIM_LL_EC_IT IT Defines
00528   * @brief    IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
00529   * @{
00530   */
00531 #define LL_HRTIM_IER_FLT1IE                HRTIM_IER_FLT1IE
00532 #define LL_HRTIM_IER_FLT2IE                HRTIM_IER_FLT2IE
00533 #define LL_HRTIM_IER_FLT3IE                HRTIM_IER_FLT3IE
00534 #define LL_HRTIM_IER_FLT4IE                HRTIM_IER_FLT4IE
00535 #define LL_HRTIM_IER_FLT5IE                HRTIM_IER_FLT5IE
00536 #define LL_HRTIM_IER_FLT6IE                HRTIM_IER_FLT6IE
00537 #define LL_HRTIM_IER_SYSFLTIE              HRTIM_IER_SYSFLTIE
00538 #define LL_HRTIM_IER_DLLRDYIE              HRTIM_IER_DLLRDYIE
00539 #define LL_HRTIM_IER_BMPERIE               HRTIM_IER_BMPERIE
00540
00541 #define LL_HRTIM_MDIER_MCMP1IE             HRTIM_MDIER_MCMP1IE
00542 #define LL_HRTIM_MDIER_MCMP2IE             HRTIM_MDIER_MCMP2IE
00543 #define LL_HRTIM_MDIER_MCMP3IE             HRTIM_MDIER_MCMP3IE
00544 #define LL_HRTIM_MDIER_MCMP4IE             HRTIM_MDIER_MCMP4IE
00545 #define LL_HRTIM_MDIER_MREPIE              HRTIM_MDIER_MREPIE
00546 #define LL_HRTIM_MDIER_SYNCIE              HRTIM_MDIER_SYNCIE
00547 #define LL_HRTIM_MDIER_MUPDIE              HRTIM_MDIER_MUPDIE
00548
00549 #define LL_HRTIM_TIMDIER_CMP1IE            HRTIM_TIMDIER_CMP1IE
00550 #define LL_HRTIM_TIMDIER_CMP2IE            HRTIM_TIMDIER_CMP2IE
00551 #define LL_HRTIM_TIMDIER_CMP3IE            HRTIM_TIMDIER_CMP3IE
00552 #define LL_HRTIM_TIMDIER_CMP4IE            HRTIM_TIMDIER_CMP4IE
00553 #define LL_HRTIM_TIMDIER_REPIE             HRTIM_TIMDIER_REPIE
00554 #define LL_HRTIM_TIMDIER_UPDIE             HRTIM_TIMDIER_UPDIE
00555 #define LL_HRTIM_TIMDIER_CPT1IE            HRTIM_TIMDIER_CPT1IE
00556 #define LL_HRTIM_TIMDIER_CPT2IE            HRTIM_TIMDIER_CPT2IE
00557 #define LL_HRTIM_TIMDIER_SET1IE            HRTIM_TIMDIER_SET1IE
00558 #define LL_HRTIM_TIMDIER_RST1IE            HRTIM_TIMDIER_RST1IE
00559 #define LL_HRTIM_TIMDIER_SET2IE            HRTIM_TIMDIER_SET2IE
00560 #define LL_HRTIM_TIMDIER_RST2IE            HRTIM_TIMDIER_RST2IE
00561 #define LL_HRTIM_TIMDIER_RSTIE             HRTIM_TIMDIER_RSTIE
00562 #define LL_HRTIM_TIMDIER_DLYPRTIE          HRTIM_TIMDIER_DLYPRTIE
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC  SYNCHRONIZATION INPUT SOURCE
00568   * @{
00569   * @brief Constants defining defining the synchronization input source.
00570   */
00571 #define LL_HRTIM_SYNCIN_SRC_NONE            0x00000000U                      /*!< HRTIM is not synchronized and runs in standalone mode */
00572 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT       (HRTIM_MCR_SYNC_IN_1)                        /*!< The HRTIM is synchronized with the on-chip timer */
00573 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
00574 /**
00575   * @}
00576   */
00577
00578 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC  SYNCHRONIZATION OUTPUT SOURCE
00579   * @{
00580   * @brief Constants defining the source and event to be sent on the synchronization output.
00581   */
00582 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
00583 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
00584 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
00585 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY  SYNCHRONIZATION OUTPUT POLARITY
00591   * @{
00592   * @brief Constants defining the routing and conditioning of the synchronization output event.
00593   */
00594 #define LL_HRTIM_SYNCOUT_DISABLED     0x00000000U                         /*!< Synchronization output event is disabled */
00595 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
00596 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup HRTIM_LL_EC_TIMER  TIMER ID
00602   * @{
00603   * @brief Constants identifying a timing unit.
00604   */
00605 #define LL_HRTIM_TIMER_NONE                0U   /*!< Master timer identifier */
00606 #define LL_HRTIM_TIMER_MASTER              HRTIM_MCR_MCEN   /*!< Master timer identifier */
00607 #define LL_HRTIM_TIMER_A                   HRTIM_MCR_TACEN  /*!< Timer A identifier */
00608 #define LL_HRTIM_TIMER_B                   HRTIM_MCR_TBCEN  /*!< Timer B identifier */
00609 #define LL_HRTIM_TIMER_C                   HRTIM_MCR_TCCEN  /*!< Timer C identifier */
00610 #define LL_HRTIM_TIMER_D                   HRTIM_MCR_TDCEN  /*!< Timer D identifier */
00611 #define LL_HRTIM_TIMER_E                   HRTIM_MCR_TECEN  /*!< Timer E identifier */
00612 #define LL_HRTIM_TIMER_F                   HRTIM_MCR_TFCEN  /*!< Timer F identifier */
00613
00614 #define LL_HRTIM_TIMER_X                  (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
00615                                            HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
00616                                            HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
00617 #define LL_HRTIM_TIMER_ALL                (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
00618
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup HRTIM_LL_EC_OUTPUT  OUTPUT ID
00624   * @{
00625   * @brief Constants identifying an HRTIM output.
00626   */
00627 #define LL_HRTIM_OUTPUT_TA1                HRTIM_OENR_TA1OEN  /*!< Timer A - Output 1 identifier */
00628 #define LL_HRTIM_OUTPUT_TA2                HRTIM_OENR_TA2OEN  /*!< Timer A - Output 2 identifier */
00629 #define LL_HRTIM_OUTPUT_TB1                HRTIM_OENR_TB1OEN  /*!< Timer B - Output 1 identifier */
00630 #define LL_HRTIM_OUTPUT_TB2                HRTIM_OENR_TB2OEN  /*!< Timer B - Output 2 identifier */
00631 #define LL_HRTIM_OUTPUT_TC1                HRTIM_OENR_TC1OEN  /*!< Timer C - Output 1 identifier */
00632 #define LL_HRTIM_OUTPUT_TC2                HRTIM_OENR_TC2OEN  /*!< Timer C - Output 2 identifier */
00633 #define LL_HRTIM_OUTPUT_TD1                HRTIM_OENR_TD1OEN  /*!< Timer D - Output 1 identifier */
00634 #define LL_HRTIM_OUTPUT_TD2                HRTIM_OENR_TD2OEN  /*!< Timer D - Output 2 identifier */
00635 #define LL_HRTIM_OUTPUT_TE1                HRTIM_OENR_TE1OEN  /*!< Timer E - Output 1 identifier */
00636 #define LL_HRTIM_OUTPUT_TE2                HRTIM_OENR_TE2OEN  /*!< Timer E - Output 2 identifier */
00637 #define LL_HRTIM_OUTPUT_TF1                HRTIM_OENR_TF1OEN  /*!< Timer F - Output 1 identifier */
00638 #define LL_HRTIM_OUTPUT_TF2                HRTIM_OENR_TF2OEN  /*!< Timer F - Output 2 identifier */
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup HRTIM_LL_EC_COMPAREUNIT  COMPARE UNIT ID
00644   * @{
00645   * @brief Constants identifying a compare unit.
00646   */
00647 #define LL_HRTIM_COMPAREUNIT_2             HRTIM_TIMCR_DELCMP2  /*!< Compare unit 2 identifier */
00648 #define LL_HRTIM_COMPAREUNIT_4             HRTIM_TIMCR_DELCMP4  /*!< Compare unit 4 identifier */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT  CAPTURE UNIT ID
00654   * @{
00655   * @brief Constants identifying a capture unit.
00656   */
00657 #define LL_HRTIM_CAPTUREUNIT_1             0  /*!< Capture unit 1 identifier */
00658 #define LL_HRTIM_CAPTUREUNIT_2             1  /*!< Capture unit 2 identifier */
00659 /**
00660   * @}
00661   */
00662
00663 /** @defgroup HRTIM_LL_EC_FAULT  FAULT ID
00664   * @{
00665   * @brief Constants identifying a fault channel.
00666   */
00667 #define LL_HRTIM_FAULT_1      HRTIM_FLTR_FLT1EN     /*!< Fault channel 1 identifier */
00668 #define LL_HRTIM_FAULT_2      HRTIM_FLTR_FLT2EN     /*!< Fault channel 2 identifier */
00669 #define LL_HRTIM_FAULT_3      HRTIM_FLTR_FLT3EN     /*!< Fault channel 3 identifier */
00670 #define LL_HRTIM_FAULT_4      HRTIM_FLTR_FLT4EN     /*!< Fault channel 4 identifier */
00671 #define LL_HRTIM_FAULT_5      HRTIM_FLTR_FLT5EN     /*!< Fault channel 5 identifier */
00672 #define LL_HRTIM_FAULT_6      HRTIM_FLTR_FLT6EN     /*!< Fault channel 6 identifier */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup HRTIM_LL_EC_EVENT  EXTERNAL EVENT ID
00678   * @{
00679   * @brief Constants identifying an external event channel.
00680   */
00681 #define LL_HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier */
00682 #define LL_HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier */
00683 #define LL_HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier */
00684 #define LL_HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier */
00685 #define LL_HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier */
00686 #define LL_HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier */
00687 #define LL_HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier */
00688 #define LL_HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier */
00689 #define LL_HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier */
00690 #define LL_HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier */
00691 /**
00692   * @}
00693   */
00694
00695 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE  OUTPUT STATE
00696   * @{
00697   * @brief Constants defining the state of an HRTIM output.
00698   */
00699 #define LL_HRTIM_OUTPUTSTATE_IDLE          ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
00700 #define LL_HRTIM_OUTPUTSTATE_RUN           ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
00701 #define LL_HRTIM_OUTPUTSTATE_FAULT         ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup HRTIM_LL_EC_ADCTRIG  ADC TRIGGER
00707   * @{
00708   * @brief Constants identifying an ADC trigger.
00709   */
00710 #define LL_HRTIM_ADCTRIG_1              ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
00711 #define LL_HRTIM_ADCTRIG_2              ((uint32_t)0x00000001U)  /*!< ADC trigger 2 identifier */
00712 #define LL_HRTIM_ADCTRIG_3              ((uint32_t)0x00000002U)  /*!< ADC trigger 3 identifier */
00713 #define LL_HRTIM_ADCTRIG_4              ((uint32_t)0x00000003U)  /*!< ADC trigger 4 identifier */
00714 #define LL_HRTIM_ADCTRIG_5              ((uint32_t)0x00000004U)  /*!< ADC trigger 5 identifier */
00715 #define LL_HRTIM_ADCTRIG_6              ((uint32_t)0x00000005U)  /*!< ADC trigger 6 identifier */
00716 #define LL_HRTIM_ADCTRIG_7              ((uint32_t)0x00000006U)  /*!< ADC trigger 7 identifier */
00717 #define LL_HRTIM_ADCTRIG_8              ((uint32_t)0x00000007U)  /*!< ADC trigger 8 identifier */
00718 #define LL_HRTIM_ADCTRIG_9              ((uint32_t)0x00000008U)  /*!< ADC trigger 9 identifier */
00719 #define LL_HRTIM_ADCTRIG_10             ((uint32_t)0x00000009U)  /*!< ADC trigger 10 identifier */
00720 /**
00721   * @}
00722   */
00723
00724 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
00725   * @{
00726   * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
00727   */
00728 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER  0x00000000U  /*!< HRTIM_ADCxR register update is triggered by the Master timer */
00729 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U  /*!< HRTIM_ADCxR register update is triggered by the Timer A */
00730 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U  /*!< HRTIM_ADCxR register update is triggered by the Timer B */
00731 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U  /*!< HRTIM_ADCxR register update is triggered by the Timer C */
00732 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U  /*!< HRTIM_ADCxR register update is triggered by the Timer D */
00733 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U  /*!< HRTIM_ADCxR register update is triggered by the Timer E */
00734 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U  /*!< HRTIM_ADCxR register update is triggered by the Timer F */
00735 /**
00736   * @}
00737   */
00738
00739 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13  ADC TRIGGER 1/3 SOURCE
00740   * @{
00741   * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
00742   */
00743 #define LL_HRTIM_ADCTRIG_SRC13_NONE           0x00000000U              /*!< No ADC trigger event */
00744 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1          HRTIM_ADC1R_AD1MC1       /*!< ADC Trigger on master compare 1 */
00745 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2          HRTIM_ADC1R_AD1MC2       /*!< ADC Trigger on master compare 2 */
00746 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3          HRTIM_ADC1R_AD1MC3       /*!< ADC Trigger on master compare 3 */
00747 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4          HRTIM_ADC1R_AD1MC4       /*!< ADC Trigger on master compare 4 */
00748 #define LL_HRTIM_ADCTRIG_SRC13_MPER           HRTIM_ADC1R_AD1MPER      /*!< ADC Trigger on master period */
00749 #define LL_HRTIM_ADCTRIG_SRC13_EEV1           HRTIM_ADC1R_AD1EEV1      /*!< ADC Trigger on external event 1 */
00750 #define LL_HRTIM_ADCTRIG_SRC13_EEV2           HRTIM_ADC1R_AD1EEV2      /*!< ADC Trigger on external event 2 */
00751 #define LL_HRTIM_ADCTRIG_SRC13_EEV3           HRTIM_ADC1R_AD1EEV3      /*!< ADC Trigger on external event 3 */
00752 #define LL_HRTIM_ADCTRIG_SRC13_EEV4           HRTIM_ADC1R_AD1EEV4      /*!< ADC Trigger on external event 4 */
00753 #define LL_HRTIM_ADCTRIG_SRC13_EEV5           HRTIM_ADC1R_AD1EEV5      /*!< ADC Trigger on external event 5 */
00754 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2       HRTIM_ADC1R_AD1TFC2      /*!< ADC Trigger on Timer F compare 2 */
00755 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3       HRTIM_ADC1R_AD1TAC3      /*!< ADC Trigger on Timer A compare 3 */
00756 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4       HRTIM_ADC1R_AD1TAC4      /*!< ADC Trigger on Timer A compare 4 */
00757 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER        HRTIM_ADC1R_AD1TAPER     /*!< ADC Trigger on Timer A period */
00758 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST        HRTIM_ADC1R_AD1TARST     /*!< ADC Trigger on Timer A reset */
00759 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3       HRTIM_ADC1R_AD1TFC3      /*!< ADC Trigger on Timer F compare 3 */
00760 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3       HRTIM_ADC1R_AD1TBC3      /*!< ADC Trigger on Timer B compare 3 */
00761 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4       HRTIM_ADC1R_AD1TBC4      /*!< ADC Trigger on Timer B compare 4 */
00762 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER        HRTIM_ADC1R_AD1TBPER     /*!< ADC Trigger on Timer B period */
00763 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST        HRTIM_ADC1R_AD1TBRST     /*!< ADC Trigger on Timer B reset */
00764 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4       HRTIM_ADC1R_AD1TFC4      /*!< ADC Trigger on Timer F compare 4 */
00765 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3       HRTIM_ADC1R_AD1TCC3      /*!< ADC Trigger on Timer C compare 3 */
00766 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4       HRTIM_ADC1R_AD1TCC4      /*!< ADC Trigger on Timer C compare 4 */
00767 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER        HRTIM_ADC1R_AD1TCPER     /*!< ADC Trigger on Timer C period */
00768 #define LL_HRTIM_ADCTRIG_SRC13_TIMFPER        HRTIM_ADC1R_AD1TFPER     /*!< ADC Trigger on Timer F period */
00769 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3       HRTIM_ADC1R_AD1TDC3      /*!< ADC Trigger on Timer D compare 3 */
00770 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4       HRTIM_ADC1R_AD1TDC4      /*!< ADC Trigger on Timer D compare 4 */
00771 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER        HRTIM_ADC1R_AD1TDPER     /*!< ADC Trigger on Timer D period */
00772 #define LL_HRTIM_ADCTRIG_SRC13_TIMFRST        HRTIM_ADC1R_AD1TFRST     /*!< ADC Trigger on Timer F reset */
00773 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3       HRTIM_ADC1R_AD1TEC3      /*!< ADC Trigger on Timer E compare 3 */
00774 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4       HRTIM_ADC1R_AD1TEC4      /*!< ADC Trigger on Timer E compare 4 */
00775 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER        HRTIM_ADC1R_AD1TEPER     /*!< ADC Trigger on Timer E period */
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24  ADC TRIGGER 2/4 SOURCE
00781   * @{
00782   * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
00783   */
00784 #define LL_HRTIM_ADCTRIG_SRC24_NONE           0x00000000U            /*!< No ADC trigger event */
00785 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1          HRTIM_ADC2R_AD2MC1     /*!< ADC Trigger on master compare 1 */
00786 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2          HRTIM_ADC2R_AD2MC2     /*!< ADC Trigger on master compare 2 */
00787 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3          HRTIM_ADC2R_AD2MC3     /*!< ADC Trigger on master compare 3 */
00788 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4          HRTIM_ADC2R_AD2MC4     /*!< ADC Trigger on master compare 4 */
00789 #define LL_HRTIM_ADCTRIG_SRC24_MPER           HRTIM_ADC2R_AD2MPER    /*!< ADC Trigger on master period */
00790 #define LL_HRTIM_ADCTRIG_SRC24_EEV6           HRTIM_ADC2R_AD2EEV6    /*!< ADC Trigger on external event 6 */
00791 #define LL_HRTIM_ADCTRIG_SRC24_EEV7           HRTIM_ADC2R_AD2EEV7    /*!< ADC Trigger on external event 7 */
00792 #define LL_HRTIM_ADCTRIG_SRC24_EEV8           HRTIM_ADC2R_AD2EEV8    /*!< ADC Trigger on external event 8 */
00793 #define LL_HRTIM_ADCTRIG_SRC24_EEV9           HRTIM_ADC2R_AD2EEV9    /*!< ADC Trigger on external event 9 */
00794 #define LL_HRTIM_ADCTRIG_SRC24_EEV10          HRTIM_ADC2R_AD2EEV10   /*!< ADC Trigger on external event 10 */
00795 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2       HRTIM_ADC2R_AD2TAC2    /*!< ADC Trigger on Timer A compare 2 */
00796 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2       HRTIM_ADC2R_AD2TFC2    /*!< ADC Trigger on Timer F compare 2 */
00797 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4       HRTIM_ADC2R_AD2TAC4    /*!< ADC Trigger on Timer A compare 4 */
00798 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER        HRTIM_ADC2R_AD2TAPER   /*!< ADC Trigger on Timer A period */
00799 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2       HRTIM_ADC2R_AD2TBC2    /*!< ADC Trigger on Timer B compare 2 */
00800 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3       HRTIM_ADC2R_AD2TFC3    /*!< ADC Trigger on Timer F compare 3 */
00801 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4       HRTIM_ADC2R_AD2TBC4    /*!< ADC Trigger on Timer B compare 4 */
00802 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER        HRTIM_ADC2R_AD2TBPER   /*!< ADC Trigger on Timer B period */
00803 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2       HRTIM_ADC2R_AD2TCC2    /*!< ADC Trigger on Timer C compare 2 */
00804 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4       HRTIM_ADC2R_AD2TFC4    /*!< ADC Trigger on Timer F compare 4 */
00805 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4       HRTIM_ADC2R_AD2TCC4    /*!< ADC Trigger on Timer C compare 4 */
00806 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER        HRTIM_ADC2R_AD2TCPER   /*!< ADC Trigger on Timer C period */
00807 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST        HRTIM_ADC2R_AD2TCRST   /*!< ADC Trigger on Timer C reset */
00808 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2       HRTIM_ADC2R_AD2TDC2    /*!< ADC Trigger on Timer D compare 2 */
00809 #define LL_HRTIM_ADCTRIG_SRC24_TIMFPER        HRTIM_ADC2R_AD2TFPER   /*!< ADC Trigger on Timer F period */
00810 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4       HRTIM_ADC2R_AD2TDC4    /*!< ADC Trigger on Timer D compare 4 */
00811 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER        HRTIM_ADC2R_AD2TDPER   /*!< ADC Trigger on Timer D period */
00812 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST        HRTIM_ADC2R_AD2TDRST   /*!< ADC Trigger on Timer D reset */
00813 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2       HRTIM_ADC2R_AD2TEC2    /*!< ADC Trigger on Timer E compare 2 */
00814 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3       HRTIM_ADC2R_AD2TEC3    /*!< ADC Trigger on Timer E compare 3 */
00815 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4       HRTIM_ADC2R_AD2TEC4    /*!< ADC Trigger on Timer E compare 4 */
00816 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST        HRTIM_ADC2R_AD2TERST   /*!< ADC Trigger on Timer E reset */
00817 /**
00818   * @}
00819   */
00820
00821 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
00822   * @{
00823   * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
00824   */
00825 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP1        (uint32_t)0x00                        /*!<  ADC extended Trigger on Master Compare 1 */
00826 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP2        (uint32_t)0x01                        /*!<  ADC extended Trigger on Master Compare 2 */
00827 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP3        (uint32_t)0x02                        /*!<  ADC extended Trigger on Master Compare 3 */
00828 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP4        (uint32_t)0x03                        /*!<  ADC extended Trigger on Master Compare 4 */
00829 #define LL_HRTIM_ADCTRIG_SRC6810_MPER         (uint32_t)0x04                        /*!<  ADC extended Trigger on Master Period */
00830 #define LL_HRTIM_ADCTRIG_SRC6810_EEV6         (uint32_t)0x05                        /*!<  ADC extended Trigger on External Event 6 */
00831 #define LL_HRTIM_ADCTRIG_SRC6810_EEV7         (uint32_t)0x06                        /*!<  ADC extended Trigger on External Event 7 */
00832 #define LL_HRTIM_ADCTRIG_SRC6810_EEV8         (uint32_t)0x07                        /*!<  ADC extended Trigger on External Event 8 */
00833 #define LL_HRTIM_ADCTRIG_SRC6810_EEV9         (uint32_t)0x08                        /*!<  ADC extended Trigger on External Event 9 */
00834 #define LL_HRTIM_ADCTRIG_SRC6810_EEV10        (uint32_t)0x09                        /*!<  ADC extended Trigger on External Event 10 */
00835 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2    (uint32_t)0x0A                        /*!<  ADC extended Trigger on Timer A Compare 2 */
00836 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4    (uint32_t)0x0B                        /*!<  ADC extended Trigger on Timer A Compare 4 */
00837 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER     (uint32_t)0x0C                        /*!<  ADC extended Trigger on Timer A Period */
00838 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2    (uint32_t)0x0D                        /*!<  ADC extended Trigger on Timer B Compare 2 */
00839 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4    (uint32_t)0x0E                        /*!<  ADC extended Trigger on Timer B Compare 4 */
00840 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER     (uint32_t)0x0F                        /*!<  ADC extended Trigger on Timer B Period */
00841 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2    (uint32_t)0x10                        /*!<  ADC extended Trigger on Timer C Compare 2 */
00842 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4    (uint32_t)0x11                        /*!<  ADC extended Trigger on Timer C Compare 4 */
00843 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER     (uint32_t)0x12                        /*!<  ADC extended Trigger on Timer C Period */
00844 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST     (uint32_t)0x13                        /*!<  ADC extended Trigger on Timer C Reset and counter roll-over */
00845 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2    (uint32_t)0x14                        /*!<  ADC extended Trigger on Timer D Compare 2 */
00846 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4    (uint32_t)0x15                        /*!<  ADC extended Trigger on Timer D Compare 4 */
00847 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER     (uint32_t)0x16                        /*!<  ADC extended Trigger on Timer D Period */
00848 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST     (uint32_t)0x17                        /*!<  ADC extended Trigger on Timer D Reset and counter roll-over */
00849 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2    (uint32_t)0x18                        /*!<  ADC extended Trigger on Timer E Compare 2 */
00850 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3    (uint32_t)0x19                        /*!<  ADC extended Trigger on Timer E Compare 3 */
00851 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4    (uint32_t)0x1A                        /*!<  ADC extended Trigger on Timer E Compare 4 */
00852 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST     (uint32_t)0x1B                        /*!<  ADC extended Trigger on Timer E Reset and counter roll-over */
00853 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2    (uint32_t)0x1C                        /*!<  ADC extended Trigger on Timer F Compare 2 */
00854 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3    (uint32_t)0x1D                        /*!<  ADC extended Trigger on Timer F Compare 3 */
00855 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4    (uint32_t)0x1E                        /*!<  ADC extended Trigger on Timer F Compare 4 */
00856 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER     (uint32_t)0x1F                        /*!<  ADC extended Trigger on Timer F Period */
00857 /**
00858   * @}
00859   */
00860
00861 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
00862   * @{
00863   * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
00864   */
00865 #define LL_HRTIM_ADCTRIG_SRC579_MCMP1           (uint32_t)0x00                        /*!<  ADC extended Trigger on Master Compare 1 */
00866 #define LL_HRTIM_ADCTRIG_SRC579_MCMP2           (uint32_t)0x01                        /*!<  ADC extended Trigger on Master Compare 2 */
00867 #define LL_HRTIM_ADCTRIG_SRC579_MCMP3           (uint32_t)0x02                        /*!<  ADC extended Trigger on Master Compare 3 */
00868 #define LL_HRTIM_ADCTRIG_SRC579_MCMP4           (uint32_t)0x03                        /*!<  ADC extended Trigger on Master Compare 4 */
00869 #define LL_HRTIM_ADCTRIG_SRC579_MPER            (uint32_t)0x04                        /*!<  ADC extended Trigger on Master Period */
00870 #define LL_HRTIM_ADCTRIG_SRC579_EEV1            (uint32_t)0x05                        /*!<  ADC extended Trigger on External Event 1 */
00871 #define LL_HRTIM_ADCTRIG_SRC579_EEV2            (uint32_t)0x06                        /*!<  ADC extended Trigger on External Event 2 */
00872 #define LL_HRTIM_ADCTRIG_SRC579_EEV3            (uint32_t)0x07                        /*!<  ADC extended Trigger on External Event 3 */
00873 #define LL_HRTIM_ADCTRIG_SRC579_EEV4            (uint32_t)0x08                        /*!<  ADC extended Trigger on External Event 4 */
00874 #define LL_HRTIM_ADCTRIG_SRC579_EEV5            (uint32_t)0x09                        /*!<  ADC extended Trigger on External Event 5 */
00875 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3       (uint32_t)0x0A                        /*!<  ADC extended Trigger on Timer A Compare 3 */
00876 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4       (uint32_t)0x0B                        /*!<  ADC extended Trigger on Timer A Compare 4 */
00877 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER        (uint32_t)0x0C                        /*!<  ADC extended Trigger on Timer A Period */
00878 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST        (uint32_t)0x0D                        /*!<  ADC extended Trigger on Timer A Period */
00879 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3       (uint32_t)0x0E                        /*!<  ADC extended Trigger on Timer B Compare 3 */
00880 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4       (uint32_t)0x0F                        /*!<  ADC extended Trigger on Timer B Compare 4 */
00881 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER        (uint32_t)0x10                        /*!<  ADC extended Trigger on Timer B Period */
00882 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST        (uint32_t)0x11                        /*!<  ADC extended Trigger on Timer B Reset and counter roll-over */
00883 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3       (uint32_t)0x12                        /*!<  ADC extended Trigger on Timer C Compare 3 */
00884 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4       (uint32_t)0x13                        /*!<  ADC extended Trigger on Timer C Compare 4 */
00885 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER        (uint32_t)0x14                        /*!<  ADC extended Trigger on Timer C Period */
00886 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3       (uint32_t)0x15                        /*!<  ADC extended Trigger on Timer D Compare 3 */
00887 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4       (uint32_t)0x16                        /*!<  ADC extended Trigger on Timer D Compare 4 */
00888 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER        (uint32_t)0x17                        /*!<  ADC extended Trigger on Timer D Period */
00889 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3       (uint32_t)0x18                        /*!<  ADC extended Trigger on Timer E Compare 3 */
00890 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4       (uint32_t)0x19                        /*!<  ADC extended Trigger on Timer E Compare 4 */
00891 #define LL_HRTIM_ADCTRIG_SRC579_TIME_PER        (uint32_t)0x1A                        /*!<  ADC extended Trigger on Timer E Period */
00892 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2       (uint32_t)0x1B                        /*!<  ADC extended Trigger on Timer F Compare 2 */
00893 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3       (uint32_t)0x1C                        /*!<  ADC extended Trigger on Timer F Compare 3 */
00894 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4       (uint32_t)0x1D                        /*!<  ADC extended Trigger on Timer F Compare 4 */
00895 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER        (uint32_t)0x1E                        /*!<  ADC extended Trigger on Timer F Period */
00896 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST        (uint32_t)0x1F                        /*!<  ADC extended Trigger on Timer F Reset and counter roll-over */
00897 /**
00898   * @}
00899   */
00900
00901 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE  DLL CALIBRATION MODE
00902   * @{
00903   * @brief Constants defining the DLL calibration mode.
00904   */
00905 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT   0x00000000U            /*!<Calibration is performed only once */
00906 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS   HRTIM_DLLCR_CALEN      /*!<Calibration is performed periodically */
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE  DLL CALIBRATION RATE
00912   * @{
00913   * @brief Constants defining the DLL calibration periods (in micro seconds).
00914   */
00915 #define LL_HRTIM_DLLCALIBRATION_RATE_0         0x00000000U                                    /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
00916 #define LL_HRTIM_DLLCALIBRATION_RATE_1         (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
00917 #define LL_HRTIM_DLLCALIBRATION_RATE_2         (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
00918 #define LL_HRTIM_DLLCALIBRATION_RATE_3         (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
00919 /**
00920   * @}
00921   */
00922
00923 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO  PRESCALER RATIO
00924   * @{
00925   * @brief Constants defining timer high-resolution clock prescaler ratio.
00926   */
00927 #define LL_HRTIM_PRESCALERRATIO_MUL32      0x00000000U              /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)      */
00928 #define LL_HRTIM_PRESCALERRATIO_MUL16      ((uint32_t)0x00000001U)  /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)      */
00929 #define LL_HRTIM_PRESCALERRATIO_MUL8       ((uint32_t)0x00000002U)  /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)      */
00930 #define LL_HRTIM_PRESCALERRATIO_MUL4       ((uint32_t)0x00000003U)  /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)      */
00931 #define LL_HRTIM_PRESCALERRATIO_MUL2       ((uint32_t)0x00000004U)  /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)      */
00932 #define LL_HRTIM_PRESCALERRATIO_DIV1       ((uint32_t)0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */
00933 #define LL_HRTIM_PRESCALERRATIO_DIV2       ((uint32_t)0x00000006U)  /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */
00934 #define LL_HRTIM_PRESCALERRATIO_DIV4       ((uint32_t)0x00000007U)  /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup HRTIM_LL_EC_MODE  COUNTER MODE
00940   * @{
00941   * @brief Constants defining timer counter operating mode.
00942   */
00943 #define LL_HRTIM_MODE_CONTINUOUS           ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
00944 #define LL_HRTIM_MODE_SINGLESHOT           0x00000000U              /*!< The timer operates in non retriggerable single-shot mode */
00945 #define LL_HRTIM_MODE_RETRIGGERABLE        ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup HRTIM_LL_EC_DACTRIG  DAC TRIGGER
00951   * @{
00952   * @brief Constants defining on which output the DAC synchronization event is sent.
00953   */
00954 #define LL_HRTIM_DACTRIG_NONE           0x00000000U                     /*!< No DAC synchronization event generated */
00955 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1   (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
00956 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2   (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
00957 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3   (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
00958 /**
00959   * @}
00960   */
00961
00962 /** @defgroup HRTIM_LL_EC_UPDATETRIG  UPDATE TRIGGER
00963   * @{
00964   * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
00965   */
00966 #define LL_HRTIM_UPDATETRIG_NONE        0x00000000U            /*!< Register update is disabled */
00967 #define LL_HRTIM_UPDATETRIG_MASTER      HRTIM_TIMCR_MSTU       /*!< Register update is triggered by the master timer update */
00968 #define LL_HRTIM_UPDATETRIG_TIMER_A     HRTIM_TIMCR_TAU        /*!< Register update is triggered by the timer A update */
00969 #define LL_HRTIM_UPDATETRIG_TIMER_B     HRTIM_TIMCR_TBU        /*!< Register update is triggered by the timer B update */
00970 #define LL_HRTIM_UPDATETRIG_TIMER_C     HRTIM_TIMCR_TCU        /*!< Register update is triggered by the timer C update*/
00971 #define LL_HRTIM_UPDATETRIG_TIMER_D     HRTIM_TIMCR_TDU        /*!< Register update is triggered by the timer D update */
00972 #define LL_HRTIM_UPDATETRIG_TIMER_E     HRTIM_TIMCR_TEU        /*!< Register update is triggered by the timer E update */
00973 #define LL_HRTIM_UPDATETRIG_TIMER_F     HRTIM_TIMCR_TFU        /*!< Register update is triggered by the timer F update */
00974 #define LL_HRTIM_UPDATETRIG_REPETITION  HRTIM_TIMCR_TREPU      /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
00975 #define LL_HRTIM_UPDATETRIG_RESET       HRTIM_TIMCR_TRSTU      /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup HRTIM_LL_EC_UPDATEGATING  UPDATE GATING
00981   * @{
00982   * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
00983   */
00984 #define LL_HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                               /*!< Update done independently from the DMA burst transfer completion */
00985 #define LL_HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
00986 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
00987 #define LL_HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
00988 #define LL_HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
00989 #define LL_HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
00990 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1 */
00991 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
00992 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
00993 /**
00994   * @}
00995   */
00996
00997 /** @defgroup HRTIM_LL_EC_COMPAREMODE  COMPARE MODE
00998   * @{
00999   * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
01000   */
01001 #define LL_HRTIM_COMPAREMODE_REGULAR          0x00000000U                         /*!< standard compare mode */
01002 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT  (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
01003 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1       (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
01004 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3       (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
01005 /**
01006   * @}
01007   */
01008
01009 /** @defgroup HRTIM_LL_EC_RESETTRIG  RESET TRIGGER
01010   * @{
01011   * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
01012   */
01013 #define LL_HRTIM_RESETTRIG_NONE        0x00000000U            /*!< No counter reset trigger */
01014 #define LL_HRTIM_RESETTRIG_UPDATE      HRTIM_RSTR_UPDATE      /*!< The timer counter is reset upon update event */
01015 #define LL_HRTIM_RESETTRIG_CMP2        HRTIM_RSTR_CMP2        /*!< The timer counter is reset upon Timer Compare 2 event */
01016 #define LL_HRTIM_RESETTRIG_CMP4        HRTIM_RSTR_CMP4        /*!< The timer counter is reset upon Timer Compare 4 event */
01017 #define LL_HRTIM_RESETTRIG_MASTER_PER  HRTIM_RSTR_MSTPER      /*!< The timer counter is reset upon master timer period event */
01018 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1     /*!< The timer counter is reset upon master timer Compare 1 event */
01019 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2     /*!< The timer counter is reset upon master timer Compare 2 event */
01020 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3     /*!< The timer counter is reset upon master timer Compare 3 event */
01021 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4     /*!< The timer counter is reset upon master timer Compare 4 event */
01022 #define LL_HRTIM_RESETTRIG_EEV_1       HRTIM_RSTR_EXTEVNT1    /*!< The timer counter is reset upon external event 1 */
01023 #define LL_HRTIM_RESETTRIG_EEV_2       HRTIM_RSTR_EXTEVNT2    /*!< The timer counter is reset upon external event 2 */
01024 #define LL_HRTIM_RESETTRIG_EEV_3       HRTIM_RSTR_EXTEVNT3    /*!< The timer counter is reset upon external event 3 */
01025 #define LL_HRTIM_RESETTRIG_EEV_4       HRTIM_RSTR_EXTEVNT4    /*!< The timer counter is reset upon external event 4 */
01026 #define LL_HRTIM_RESETTRIG_EEV_5       HRTIM_RSTR_EXTEVNT5    /*!< The timer counter is reset upon external event 5 */
01027 #define LL_HRTIM_RESETTRIG_EEV_6       HRTIM_RSTR_EXTEVNT6    /*!< The timer counter is reset upon external event 6 */
01028 #define LL_HRTIM_RESETTRIG_EEV_7       HRTIM_RSTR_EXTEVNT7    /*!< The timer counter is reset upon external event 7 */
01029 #define LL_HRTIM_RESETTRIG_EEV_8       HRTIM_RSTR_EXTEVNT8    /*!< The timer counter is reset upon external event 8 */
01030 #define LL_HRTIM_RESETTRIG_EEV_9       HRTIM_RSTR_EXTEVNT9    /*!< The timer counter is reset upon external event 9 */
01031 #define LL_HRTIM_RESETTRIG_EEV_10      HRTIM_RSTR_EXTEVNT10   /*!< The timer counter is reset upon external event 10 */
01032 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
01033 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
01034 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
01035 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
01036 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
01037 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
01038 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
01039 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
01040 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
01041 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
01042 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
01043 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
01044 #define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
01045 #define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
01046 /**
01047   * @}
01048   */
01049
01050 /** @defgroup HRTIM_LL_EC_CAPTURETRIG  CAPTURE TRIGGER
01051   * @{
01052   * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
01053   */
01054 #define LL_HRTIM_CAPTURETRIG_NONE       (uint64_t)0                               /*!< Capture trigger is disabled */
01055 #define LL_HRTIM_CAPTURETRIG_SW         (uint64_t)HRTIM_CPT1CR_SWCPT              /*!< The sw event triggers the Capture */
01056 #define LL_HRTIM_CAPTURETRIG_UPDATE     (uint64_t)HRTIM_CPT1CR_UPDCPT             /*!< The update event triggers the Capture */
01057 #define LL_HRTIM_CAPTURETRIG_EEV_1      (uint64_t)HRTIM_CPT1CR_EXEV1CPT           /*!< The External event 1 triggers the Capture */
01058 #define LL_HRTIM_CAPTURETRIG_EEV_2      (uint64_t)HRTIM_CPT1CR_EXEV2CPT           /*!< The External event 2 triggers the Capture */
01059 #define LL_HRTIM_CAPTURETRIG_EEV_3      (uint64_t)HRTIM_CPT1CR_EXEV3CPT           /*!< The External event 3 triggers the Capture */
01060 #define LL_HRTIM_CAPTURETRIG_EEV_4      (uint64_t)HRTIM_CPT1CR_EXEV4CPT           /*!< The External event 4 triggers the Capture */
01061 #define LL_HRTIM_CAPTURETRIG_EEV_5      (uint64_t)HRTIM_CPT1CR_EXEV5CPT           /*!< The External event 5 triggers the Capture */
01062 #define LL_HRTIM_CAPTURETRIG_EEV_6      (uint64_t)HRTIM_CPT1CR_EXEV6CPT           /*!< The External event 6 triggers the Capture */
01063 #define LL_HRTIM_CAPTURETRIG_EEV_7      (uint64_t)HRTIM_CPT1CR_EXEV7CPT           /*!< The External event 7 triggers the Capture */
01064 #define LL_HRTIM_CAPTURETRIG_EEV_8      (uint64_t)HRTIM_CPT1CR_EXEV8CPT           /*!< The External event 8 triggers the Capture */
01065 #define LL_HRTIM_CAPTURETRIG_EEV_9      (uint64_t)HRTIM_CPT1CR_EXEV9CPT           /*!< The External event 9 triggers the Capture */
01066 #define LL_HRTIM_CAPTURETRIG_EEV_10     (uint64_t)HRTIM_CPT1CR_EXEV10CPT          /*!< The External event 10 triggers the Capture */
01067 #define LL_HRTIM_CAPTURETRIG_TA1_SET     (uint64_t)(HRTIM_CPT1CR_TA1SET   ) <<32  /*!< Capture is triggered by TA1 output inactive to active transition */
01068 #define LL_HRTIM_CAPTURETRIG_TA1_RESET   (uint64_t)(HRTIM_CPT1CR_TA1RST   ) <<32  /*!< Capture is triggered by TA1 output active to inactive transition */
01069 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32  /*!< Timer A Compare 1 triggers Capture */
01070 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32  /*!< Timer A Compare 2 triggers Capture */
01071 #define LL_HRTIM_CAPTURETRIG_TB1_SET     (uint64_t)(HRTIM_CPT1CR_TB1SET   ) <<32  /*!< Capture is triggered by TB1 output inactive to active transition */
01072 #define LL_HRTIM_CAPTURETRIG_TB1_RESET   (uint64_t)(HRTIM_CPT1CR_TB1RST   ) <<32  /*!< Capture is triggered by TB1 output active to inactive transition */
01073 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32  /*!< Timer B Compare 1 triggers Capture */
01074 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32  /*!< Timer B Compare 2 triggers Capture */
01075 #define LL_HRTIM_CAPTURETRIG_TC1_SET     (uint64_t)(HRTIM_CPT1CR_TC1SET   ) <<32  /*!< Capture is triggered by TC1 output inactive to active transition */
01076 #define LL_HRTIM_CAPTURETRIG_TC1_RESET   (uint64_t)(HRTIM_CPT1CR_TC1RST   ) <<32  /*!< Capture is triggered by TC1 output active to inactive transition */
01077 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32  /*!< Timer C Compare 1 triggers Capture */
01078 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32  /*!< Timer C Compare 2 triggers Capture */
01079 #define LL_HRTIM_CAPTURETRIG_TD1_SET     (uint64_t)(HRTIM_CPT1CR_TD1SET   ) <<32  /*!< Capture is triggered by TD1 output inactive to active transition */
01080 #define LL_HRTIM_CAPTURETRIG_TD1_RESET   (uint64_t)(HRTIM_CPT1CR_TD1RST   ) <<32  /*!< Capture is triggered by TD1 output active to inactive transition */
01081 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32  /*!< Timer D Compare 1 triggers Capture */
01082 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32  /*!< Timer D Compare 2 triggers Capture */
01083 #define LL_HRTIM_CAPTURETRIG_TE1_SET     (uint64_t)(HRTIM_CPT1CR_TE1SET   ) <<32  /*!< Capture is triggered by TE1 output inactive to active transition */
01084 #define LL_HRTIM_CAPTURETRIG_TE1_RESET   (uint64_t)(HRTIM_CPT1CR_TE1RST   ) <<32  /*!< Capture is triggered by TE1 output active to inactive transition */
01085 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32  /*!< Timer E Compare 1 triggers Capture */
01086 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32  /*!< Timer E Compare 2 triggers Capture */
01087 #define LL_HRTIM_CAPTURETRIG_TF1_SET     (uint64_t)(HRTIM_CPT1CR_TF1SET   ) <<32  /*!< Capture is triggered by TF1 output inactive to active transition */
01088 #define LL_HRTIM_CAPTURETRIG_TF1_RESET   (uint64_t)(HRTIM_CPT1CR_TF1RST   ) <<32  /*!< Capture is triggered by TF1 output active to inactive transition */
01089 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32  /*!< Timer F Compare 1 triggers Capture */
01090 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32  /*!< Timer F Compare 2 triggers Capture */
01091 /**
01092   * @}
01093   */
01094
01095 /** @defgroup HRTIM_LL_EC_DLYPRT  DELAYED PROTECTION (DLYPRT) MODE
01096   * @{
01097   * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
01098   */
01099 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6  0x00000000U                                            /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
01100 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
01101 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
01102 #define LL_HRTIM_DLYPRT_BALANCED_EEV6   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Balanced Idle on external Event 6 */
01103 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7  (HRTIM_OUTR_DLYPRT_2)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
01104 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
01105 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
01106 #define LL_HRTIM_DLYPRT_BALANCED_EEV7   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
01107
01108 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8  0x00000000U                                             /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
01109 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
01110 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
01111 #define LL_HRTIM_DLYPRT_BALANCED_EEV8   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Balanced Idle on external Event 8 */
01112 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9  (HRTIM_OUTR_DLYPRT_2)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
01113 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
01114 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
01115 #define LL_HRTIM_DLYPRT_BALANCED_EEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)   /*!< Timers D, E: Balanced Idle on external Event 9 */
01116 /**
01117   * @}
01118   */
01119
01120 /** @defgroup HRTIM_LL_EC_BURSTMODE  BURST MODE
01121   * @{
01122   * @brief Constants defining how the timer behaves during a burst mode operation.
01123   */
01124 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
01125 #define LL_HRTIM_BURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */
01126 /**
01127   * @}
01128   */
01129
01130 /** @defgroup HRTIM_LL_EC_BURSTDMA  BURST DMA
01131   * @{
01132   * @brief Constants defining the registers that can be written during a burst DMA operation.
01133   */
01134 #define LL_HRTIM_BURSTDMA_NONE     0x00000000U               /*!< No register is updated by Burst DMA accesses */
01135 #define LL_HRTIM_BURSTDMA_MCR      (HRTIM_BDMUPR_MCR)        /*!< MCR register is updated by Burst DMA accesses */
01136 #define LL_HRTIM_BURSTDMA_MICR     (HRTIM_BDMUPR_MICR)       /*!< MICR register is updated by Burst DMA accesses */
01137 #define LL_HRTIM_BURSTDMA_MDIER    (HRTIM_BDMUPR_MDIER)      /*!< MDIER register is updated by Burst DMA accesses */
01138 #define LL_HRTIM_BURSTDMA_MCNT     (HRTIM_BDMUPR_MCNT)       /*!< MCNTR register is updated by Burst DMA accesses */
01139 #define LL_HRTIM_BURSTDMA_MPER     (HRTIM_BDMUPR_MPER)       /*!< MPER register is updated by Burst DMA accesses */
01140 #define LL_HRTIM_BURSTDMA_MREP     (HRTIM_BDMUPR_MREP)       /*!< MREPR register is updated by Burst DMA accesses */
01141 #define LL_HRTIM_BURSTDMA_MCMP1    (HRTIM_BDMUPR_MCMP1)      /*!< MCMP1R register is updated by Burst DMA accesses */
01142 #define LL_HRTIM_BURSTDMA_MCMP2    (HRTIM_BDMUPR_MCMP2)      /*!< MCMP2R register is updated by Burst DMA accesses */
01143 #define LL_HRTIM_BURSTDMA_MCMP3    (HRTIM_BDMUPR_MCMP3)      /*!< MCMP3R register is updated by Burst DMA accesses */
01144 #define LL_HRTIM_BURSTDMA_MCMP4    (HRTIM_BDMUPR_MCMP4)      /*!< MCMP4R register is updated by Burst DMA accesses */
01145 #define LL_HRTIM_BURSTDMA_TIMMCR   (HRTIM_BDTUPR_TIMCR)      /*!< TIMxCR register is updated by Burst DMA accesses */
01146 #define LL_HRTIM_BURSTDMA_TIMICR   (HRTIM_BDTUPR_TIMICR)     /*!< TIMxICR register is updated by Burst DMA accesses */
01147 #define LL_HRTIM_BURSTDMA_TIMDIER  (HRTIM_BDTUPR_TIMDIER)    /*!< TIMxDIER register is updated by Burst DMA accesses */
01148 #define LL_HRTIM_BURSTDMA_TIMCNT   (HRTIM_BDTUPR_TIMCNT)     /*!< CNTxCR register is updated by Burst DMA accesses */
01149 #define LL_HRTIM_BURSTDMA_TIMPER   (HRTIM_BDTUPR_TIMPER)     /*!< PERxR register is updated by Burst DMA accesses */
01150 #define LL_HRTIM_BURSTDMA_TIMREP   (HRTIM_BDTUPR_TIMREP)     /*!< REPxR register is updated by Burst DMA accesses */
01151 #define LL_HRTIM_BURSTDMA_TIMCMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< CMP1xR register is updated by Burst DMA accesses */
01152 #define LL_HRTIM_BURSTDMA_TIMCMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< CMP2xR register is updated by Burst DMA accesses */
01153 #define LL_HRTIM_BURSTDMA_TIMCMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< CMP3xR register is updated by Burst DMA accesses */
01154 #define LL_HRTIM_BURSTDMA_TIMCMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< CMP4xR register is updated by Burst DMA accesses */
01155 #define LL_HRTIM_BURSTDMA_TIMDTR   (HRTIM_BDTUPR_TIMDTR)     /*!< DTxR register is updated by Burst DMA accesses */
01156 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
01157 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
01158 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
01159 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
01160 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
01161 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
01162 #define LL_HRTIM_BURSTDMA_TIMRSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
01163 #define LL_HRTIM_BURSTDMA_TIMCHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
01164 #define LL_HRTIM_BURSTDMA_TIMOUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
01165 #define LL_HRTIM_BURSTDMA_TIMFLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
01166 #define LL_HRTIM_BURSTDMA_CR2      (HRTIM_BDTUPR_TIMCR2)     /*!< TIMxCR2 register is updated by Burst DMA accesses */
01167 #define LL_HRTIM_BURSTDMA_EEFR3    (HRTIM_BDTUPR_TIMEEFR3)   /*!< EEFxR3 register is updated by Burst DMA accesses */
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup HRTIM_LL_EC_CPPSTAT  CURRENT PUSH-PULL STATUS
01173   * @{
01174   * @brief Constants defining on which output the signal is currently applied in push-pull mode.
01175   */
01176 #define LL_HRTIM_CPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
01177 #define LL_HRTIM_CPPSTAT_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
01178 /**
01179   * @}
01180   */
01181
01182 /** @defgroup HRTIM_LL_EC_IPPSTAT  IDLE PUSH-PULL STATUS
01183   * @{
01184   * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
01185   */
01186 #define LL_HRTIM_IPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U)    /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
01187 #define LL_HRTIM_IPPSTAT_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
01188 /**
01189   * @}
01190   */
01191
01192 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
01193   * @{
01194   * @brief Constants defining the event filtering applied to external events by a timer.
01195   */
01196 #define LL_HRTIM_EEFLTR_NONE                            (0x00000000U)
01197 #define LL_HRTIM_EEFLTR_BLANKINGCMP1                    (HRTIM_EEFR1_EE1FLTR_0)                                                   /*!< Blanking from counter reset/roll-over to Compare 1U */
01198 #define LL_HRTIM_EEFLTR_BLANKINGCMP2                    (HRTIM_EEFR1_EE1FLTR_1)                                                   /*!< Blanking from counter reset/roll-over to Compare 2U */
01199 #define LL_HRTIM_EEFLTR_BLANKINGCMP3                    (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from counter reset/roll-over to Compare 3U */
01200 #define LL_HRTIM_EEFLTR_BLANKINGCMP4                    (HRTIM_EEFR1_EE1FLTR_2)                                                   /*!< Blanking from counter reset/roll-over to Compare 4U */
01201 /* Blanking Filter for TIMER A */
01202 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01203 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01204 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01205 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01206 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01207 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01208 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01209 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01210 /* Blanking Filter for TIMER B */
01211 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01212 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01213 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01214 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01215 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01216 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01217 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01218 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01219 /* Blanking Filter for TIMER C */
01220 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01221 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01222 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01223 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01224 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01225 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01226 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01227 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01228 /* Blanking Filter for TIMER D */
01229 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01230 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01231 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01232 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01233 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01234 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01235 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01236 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01237 /* Blanking Filter for TIMER E */
01238 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01239 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01240 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01241 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01242 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01243 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01244 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01245 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01246 /* Blanking Filter for TIMER F */
01247 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
01248 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
01249 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
01250 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
01251 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
01252 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
01253 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
01254 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
01255
01256 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from counter reset/roll-over to Compare 2U */
01257 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)   /*!< Windowing from counter reset/roll-over to Compare 3U */
01258 #define LL_HRTIM_EEFLTR_WINDOWINGTIM                    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
01259                                                                                                        | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from another timing unit: TIMWIN source */
01260 /**
01261   * @}
01262   */
01263
01264 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
01265   * @{
01266   * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
01267   */
01268 #define LL_HRTIM_EELATCH_DISABLED    0x00000000U             /*!< Event is ignored if it happens during a blank, or passed through during a window */
01269 #define LL_HRTIM_EELATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
01270 /**
01271   * @}
01272   */
01273
01274 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
01275   * @{
01276   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
01277   */
01278 #define LL_HRTIM_DT_PRESCALER_MUL8    0x00000000U                                         /*!< fDTG = fHRTIM * 8 */
01279 #define LL_HRTIM_DT_PRESCALER_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4 */
01280 #define LL_HRTIM_DT_PRESCALER_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2 */
01281 #define LL_HRTIM_DT_PRESCALER_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
01282 #define LL_HRTIM_DT_PRESCALER_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2 */
01283 #define LL_HRTIM_DT_PRESCALER_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4 */
01284 #define LL_HRTIM_DT_PRESCALER_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8 */
01285 #define LL_HRTIM_DT_PRESCALER_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16 */
01286 /**
01287   * @}
01288   */
01289
01290 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
01291   * @{
01292   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
01293   */
01294 #define LL_HRTIM_DT_RISING_POSITIVE    0x00000000U             /*!< Positive deadtime on rising edge */
01295 #define LL_HRTIM_DT_RISING_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */
01296 /**
01297   * @}
01298   */
01299
01300 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
01301   * @{
01302   * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
01303   */
01304 #define LL_HRTIM_DT_FALLING_POSITIVE    0x00000000U             /*!< Positive deadtime on falling edge */
01305 #define LL_HRTIM_DT_FALLING_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */
01306 /**
01307   * @}
01308   */
01309
01310 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
01311   * @{
01312   * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
01313   */
01314 #define LL_HRTIM_CHP_PRESCALER_DIV16  0x00000000U                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
01315 #define LL_HRTIM_CHP_PRESCALER_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
01316 #define LL_HRTIM_CHP_PRESCALER_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
01317 #define LL_HRTIM_CHP_PRESCALER_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
01318 #define LL_HRTIM_CHP_PRESCALER_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
01319 #define LL_HRTIM_CHP_PRESCALER_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
01320 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
01321 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
01322 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
01323 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
01324 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
01325 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
01326 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
01327 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
01328 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
01329 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
01330 /**
01331   * @}
01332   */
01333
01334 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
01335   * @{
01336   * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
01337   */
01338 #define LL_HRTIM_CHP_DUTYCYCLE_0    0x00000000U                                              /*!< Only 1st pulse is present */
01339 #define LL_HRTIM_CHP_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 % */
01340 #define LL_HRTIM_CHP_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 % */
01341 #define LL_HRTIM_CHP_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 % */
01342 #define LL_HRTIM_CHP_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 % */
01343 #define LL_HRTIM_CHP_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 % */
01344 #define LL_HRTIM_CHP_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 % */
01345 #define LL_HRTIM_CHP_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
01346 /**
01347   * @}
01348   */
01349
01350 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
01351   * @{
01352   * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
01353   */
01354 #define LL_HRTIM_CHP_PULSEWIDTH_16   0x00000000U                                                                 /*!< tSTPW = tHRTIM x 16  */
01355 #define LL_HRTIM_CHP_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
01356 #define LL_HRTIM_CHP_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
01357 #define LL_HRTIM_CHP_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
01358 #define LL_HRTIM_CHP_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
01359 #define LL_HRTIM_CHP_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
01360 #define LL_HRTIM_CHP_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
01361 #define LL_HRTIM_CHP_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
01362 #define LL_HRTIM_CHP_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
01363 #define LL_HRTIM_CHP_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
01364 #define LL_HRTIM_CHP_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
01365 #define LL_HRTIM_CHP_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
01366 #define LL_HRTIM_CHP_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
01367 #define LL_HRTIM_CHP_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
01368 #define LL_HRTIM_CHP_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
01369 #define LL_HRTIM_CHP_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
01370 /**
01371   * @}
01372   */
01373
01374 /** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
01375   * @{
01376   * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
01377   */
01378 #define LL_HRTIM_OUTPUTSET_NONE                0x00000000U             /*!< Reset the output set crossbar */
01379 #define LL_HRTIM_OUTPUTSET_RESYNC              (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
01380 #define LL_HRTIM_OUTPUTSET_TIMPER              (HRTIM_SET1R_PER)       /*!< Timer period event forces an output level transition */
01381 #define LL_HRTIM_OUTPUTSET_TIMCMP1             (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces an output level transition */
01382 #define LL_HRTIM_OUTPUTSET_TIMCMP2             (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces an output level transition */
01383 #define LL_HRTIM_OUTPUTSET_TIMCMP3             (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces an output level transition */
01384 #define LL_HRTIM_OUTPUTSET_TIMCMP4             (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces an output level transition */
01385 #define LL_HRTIM_OUTPUTSET_MASTERPER           (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces an output level transition */
01386 #define LL_HRTIM_OUTPUTSET_MASTERCMP1          (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces an output level transition */
01387 #define LL_HRTIM_OUTPUTSET_MASTERCMP2          (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces an output level transition */
01388 #define LL_HRTIM_OUTPUTSET_MASTERCMP3          (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces an output level transition */
01389 #define LL_HRTIM_OUTPUTSET_MASTERCMP4          (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces an output level transition */
01390 /* Timer Events mapping for Timer A */
01391 #define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01392 #define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01393 #define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01394 #define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01395 #define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01396 #define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01397 #define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01398 #define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01399 #define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01400 /* Timer Events mapping for Timer B */
01401 #define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01402 #define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01403 #define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01404 #define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01405 #define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01406 #define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01407 #define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01408 #define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01409 #define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01410 /* Timer Events mapping for Timer C */
01411 #define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01412 #define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01413 #define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01414 #define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01415 #define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01416 #define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01417 #define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01418 #define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01419 #define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01420 /* Timer Events mapping for Timer D */
01421 #define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01422 #define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01423 #define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01424 #define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01425 #define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01426 #define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01427 #define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01428 #define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01429 #define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01430 /* Timer Events mapping for Timer E */
01431 #define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01432 #define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01433 #define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01434 #define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01435 #define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01436 #define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01437 #define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01438 #define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01439 #define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01440 /* Timer Events mapping for Timer F */
01441 #define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
01442 #define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
01443 #define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
01444 #define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
01445 #define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
01446 #define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
01447 #define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
01448 #define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
01449 #define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
01450 #define LL_HRTIM_OUTPUTSET_EEV_1               (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces an output level transition */
01451 #define LL_HRTIM_OUTPUTSET_EEV_2               (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces an output level transition */
01452 #define LL_HRTIM_OUTPUTSET_EEV_3               (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces an output level transition */
01453 #define LL_HRTIM_OUTPUTSET_EEV_4               (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces an output level transition */
01454 #define LL_HRTIM_OUTPUTSET_EEV_5               (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces an output level transition */
01455 #define LL_HRTIM_OUTPUTSET_EEV_6               (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces an output level transition */
01456 #define LL_HRTIM_OUTPUTSET_EEV_7               (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces an output level transition */
01457 #define LL_HRTIM_OUTPUTSET_EEV_8               (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces an output level transition */
01458 #define LL_HRTIM_OUTPUTSET_EEV_9               (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces an output level transition */
01459 #define LL_HRTIM_OUTPUTSET_EEV_10              (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces an output level transition */
01460 #define LL_HRTIM_OUTPUTSET_UPDATE              (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces an output level transition */
01461 /**
01462   * @}
01463   */
01464
01465 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
01466   * @{
01467   * @brief Constants defining the events that can be selected to configure the
01468   *        set crossbar of a timer output
01469   */
01470 #define LL_HRTIM_OUTPUTRESET_NONE                0x00000000U             /*!< Reset the output reset crossbar */
01471 #define LL_HRTIM_OUTPUTRESET_RESYNC              (HRTIM_RST1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
01472 #define LL_HRTIM_OUTPUTRESET_TIMPER              (HRTIM_RST1R_PER)       /*!< Timer period event forces the output to its inactive state */
01473 #define LL_HRTIM_OUTPUTRESET_TIMCMP1             (HRTIM_RST1R_CMP1)      /*!< Timer compare 1 event forces the output to its inactive state */
01474 #define LL_HRTIM_OUTPUTRESET_TIMCMP2             (HRTIM_RST1R_CMP2)      /*!< Timer compare 2 event forces the output to its inactive state */
01475 #define LL_HRTIM_OUTPUTRESET_TIMCMP3             (HRTIM_RST1R_CMP3)      /*!< Timer compare 3 event forces the output to its inactive state */
01476 #define LL_HRTIM_OUTPUTRESET_TIMCMP4             (HRTIM_RST1R_CMP4)      /*!< Timer compare 4 event forces the output to its inactive state */
01477 #define LL_HRTIM_OUTPUTRESET_MASTERPER           (HRTIM_RST1R_MSTPER)    /*!< The master timer period event forces the output to its inactive state */
01478 #define LL_HRTIM_OUTPUTRESET_MASTERCMP1          (HRTIM_RST1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its inactive state */
01479 #define LL_HRTIM_OUTPUTRESET_MASTERCMP2          (HRTIM_RST1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its inactive state */
01480 #define LL_HRTIM_OUTPUTRESET_MASTERCMP3          (HRTIM_RST1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its inactive state */
01481 #define LL_HRTIM_OUTPUTRESET_MASTERCMP4          (HRTIM_RST1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its inactive state */
01482 /* Timer Events mapping for Timer A */
01483 #define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01484 #define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01485 #define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01486 #define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01487 #define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01488 #define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01489 #define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01490 #define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01491 #define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01492 /* Timer Events mapping for Timer B */
01493 #define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01494 #define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01495 #define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01496 #define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01497 #define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01498 #define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01499 #define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01500 #define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01501 #define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01502 /* Timer Events mapping for Timer C */
01503 #define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01504 #define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01505 #define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01506 #define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01507 #define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01508 #define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01509 #define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01510 #define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01511 #define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01512 /* Timer Events mapping for Timer D */
01513 #define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01514 #define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01515 #define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01516 #define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01517 #define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01518 #define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01519 #define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01520 #define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01521 #define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01522 /* Timer Events mapping for Timer E */
01523 #define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01524 #define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01525 #define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01526 #define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01527 #define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01528 #define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01529 #define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01530 #define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01531 #define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01532 /* Timer Events mapping for Timer F */
01533 #define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
01534 #define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
01535 #define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
01536 #define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
01537 #define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
01538 #define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
01539 #define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
01540 #define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
01541 #define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
01542 #define LL_HRTIM_OUTPUTRESET_EEV_1               (HRTIM_RST1R_EXTVNT1)   /*!< External event 1 forces the output to its inactive state */
01543 #define LL_HRTIM_OUTPUTRESET_EEV_2               (HRTIM_RST1R_EXTVNT2)   /*!< External event 2 forces the output to its inactive state */
01544 #define LL_HRTIM_OUTPUTRESET_EEV_3               (HRTIM_RST1R_EXTVNT3)   /*!< External event 3 forces the output to its inactive state */
01545 #define LL_HRTIM_OUTPUTRESET_EEV_4               (HRTIM_RST1R_EXTVNT4)   /*!< External event 4 forces the output to its inactive state */
01546 #define LL_HRTIM_OUTPUTRESET_EEV_5               (HRTIM_RST1R_EXTVNT5)   /*!< External event 5 forces the output to its inactive state */
01547 #define LL_HRTIM_OUTPUTRESET_EEV_6               (HRTIM_RST1R_EXTVNT6)   /*!< External event 6 forces the output to its inactive state */
01548 #define LL_HRTIM_OUTPUTRESET_EEV_7               (HRTIM_RST1R_EXTVNT7)   /*!< External event 7 forces the output to its inactive state */
01549 #define LL_HRTIM_OUTPUTRESET_EEV_8               (HRTIM_RST1R_EXTVNT8)   /*!< External event 8 forces the output to its inactive state */
01550 #define LL_HRTIM_OUTPUTRESET_EEV_9               (HRTIM_RST1R_EXTVNT9)   /*!< External event 9 forces the output to its inactive state */
01551 #define LL_HRTIM_OUTPUTRESET_EEV_10              (HRTIM_RST1R_EXTVNT10)  /*!< External event 10 forces the output to its inactive state */
01552 #define LL_HRTIM_OUTPUTRESET_UPDATE              (HRTIM_RST1R_UPDATE)    /*!< Timer register update event forces the output to its inactive state */
01553 /**
01554   * @}
01555   */
01556
01557 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
01558   * @{
01559   * @brief Constants defining the polarity of a timer output.
01560   */
01561 #define LL_HRTIM_OUT_POSITIVE_POLARITY    0x00000000U             /*!< Output is active HIGH */
01562 #define LL_HRTIM_OUT_NEGATIVE_POLARITY    (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
01563 /**
01564   * @}
01565   */
01566
01567 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
01568   * @{
01569   * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
01570   */
01571 #define LL_HRTIM_OUT_NO_IDLE             0x00000000U            /*!< The output is not affected by the burst mode operation */
01572 #define LL_HRTIM_OUT_IDLE_WHEN_BURST     (HRTIM_OUTR_IDLM1)     /*!< The output is in idle state when requested by the burst mode controller */
01573 /**
01574   * @}
01575   */
01576
01577 /** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
01578   * @{
01579   * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
01580   */
01581 #define LL_HRTIM_INTERLEAVED_MODE_DISABLED   0x000U              /*!< HRTIM interleaved Mode is disabled */
01582 #define LL_HRTIM_INTERLEAVED_MODE_DUAL       HRTIM_MCR_HALF      /*!< HRTIM interleaved Mode is Dual */
01583 #define LL_HRTIM_INTERLEAVED_MODE_TRIPLE     HRTIM_MCR_INTLVD_0  /*!< HRTIM interleaved Mode is Triple */
01584 #define LL_HRTIM_INTERLEAVED_MODE_QUAD       HRTIM_MCR_INTLVD_1  /*!< HRTIM interleaved Mode is Quad */
01585 /**
01586   * @}
01587   */
01588 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
01589   * @{
01590   * @brief Constants defining the half mode of an HRTIM Timer instance.
01591   */
01592 #define LL_HRTIM_HALF_MODE_DISABLED          0x000U              /*!< HRTIM Half Mode is disabled */
01593 #define LL_HRTIM_HALF_MODE_ENABLE            HRTIM_MCR_HALF      /*!< HRTIM Half Mode is Half */
01594 /**
01595   * @}
01596   */
01597
01598 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
01599   * @{
01600   * @brief Constants defining the output level when output is in IDLE state
01601   */
01602 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
01603 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
01604 /**
01605   * @}
01606   */
01607
01608 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
01609   * @{
01610   * @brief Constants defining the output level when output is in FAULT state.
01611   */
01612 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U                      /*!< The output is not affected by the fault input */
01613 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
01614 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
01615 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
01616 /**
01617   * @}
01618   */
01619
01620 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
01621   * @{
01622   * @brief Constants defining whether or not chopper mode is enabled for a timer output.
01623   */
01624 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED   0x00000000U             /*!< Output signal is not altered  */
01625 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)       /*!< Output signal is chopped by a carrier signal  */
01626 /**
01627   * @}
01628   */
01629
01630 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
01631   * @{
01632   * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
01633 during a programmable period before the output takes its idle state.
01634   */
01635 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR   0x00000000U            /*!< The programmed Idle state is applied immediately to the Output */
01636 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED   (HRTIM_OUTR_DIDL1)     /*!< Deadtime is inserted on output before entering the idle mode */
01637 /**
01638   * @}
01639   */
01640 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
01641   * @{
01642   * @brief Constants defining the level of a timer output.
01643   */
01644 #define LL_HRTIM_OUT_LEVEL_INACTIVE   0x00000000U            /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
01645 #define LL_HRTIM_OUT_LEVEL_ACTIVE     ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
01646 /**
01647   * @}
01648   */
01649
01650 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
01651   * @{
01652   * @brief Constants defining available sources associated to external events.
01653   */
01654 #define LL_HRTIM_EEV1SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 1 */
01655 #define LL_HRTIM_EEV2SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 2 */
01656 #define LL_HRTIM_EEV3SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 3 */
01657 #define LL_HRTIM_EEV4SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 4 */
01658 #define LL_HRTIM_EEV5SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 5 */
01659 #define LL_HRTIM_EEV6SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 6 */
01660 #define LL_HRTIM_EEV7SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 7 */
01661 #define LL_HRTIM_EEV8SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 8 */
01662 #define LL_HRTIM_EEV9SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 9 */
01663 #define LL_HRTIM_EEV10SRC_GPIO       0x00000000U                                   /*!< External event source 1 for External Event 10 */
01664 #define LL_HRTIM_EEV1SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 1 */
01665 #define LL_HRTIM_EEV2SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 2 */
01666 #define LL_HRTIM_EEV3SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 3 */
01667 #define LL_HRTIM_EEV4SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 4 */
01668 #define LL_HRTIM_EEV5SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 5 */
01669 #define LL_HRTIM_EEV6SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 6 */
01670 #define LL_HRTIM_EEV7SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 7 */
01671 #define LL_HRTIM_EEV8SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 8 */
01672 #define LL_HRTIM_EEV9SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 9 */
01673 #define LL_HRTIM_EEV10SRC_COMP7_OUT  (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 10 */
01674 #define LL_HRTIM_EEV1SRC_TIM1_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 1 */
01675 #define LL_HRTIM_EEV2SRC_TIM2_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 2 */
01676 #define LL_HRTIM_EEV3SRC_TIM3_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 3 */
01677 #define LL_HRTIM_EEV4SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 4 */
01678 #define LL_HRTIM_EEV5SRC_COMP7_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 5 */
01679 #define LL_HRTIM_EEV6SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 6 */
01680 #define LL_HRTIM_EEV7SRC_TIM7_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 7 */
01681 #define LL_HRTIM_EEV8SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 8 */
01682 #define LL_HRTIM_EEV9SRC_TIM15_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 9 */
01683 #define LL_HRTIM_EEV10SRC_TIM6_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 10 */
01684 #define LL_HRTIM_EEV1SRC_ADC1_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
01685 #define LL_HRTIM_EEV2SRC_ADC1_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
01686 #define LL_HRTIM_EEV3SRC_ADC1_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
01687 #define LL_HRTIM_EEV4SRC_ADC2_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
01688 #define LL_HRTIM_EEV5SRC_ADC2_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
01689 #define LL_HRTIM_EEV6SRC_ADC2_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
01690 #define LL_HRTIM_EEV7SRC_ADC3_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
01691 #define LL_HRTIM_EEV8SRC_ADC4_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
01692 #define LL_HRTIM_EEV9SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
01693 #define LL_HRTIM_EEV10SRC_ADC5_AWD1  (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
01694 /**
01695   * @}
01696   */
01697 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
01698   * @{
01699   * @brief Constants defining the polarity of an external event.
01700   */
01701 #define LL_HRTIM_EE_POLARITY_HIGH    0x00000000U             /*!< External event is active high */
01702 #define LL_HRTIM_EE_POLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
01703 /**
01704   * @}
01705   */
01706
01707 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
01708   * @{
01709   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
01710   */
01711 #define LL_HRTIM_EE_SENSITIVITY_LEVEL          0x00000000U                        /*!< External event is active on level */
01712 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
01713 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
01714 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
01715 /**
01716   * @}
01717   */
01718
01719 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
01720   * @{
01721   * @brief Constants defining whether or not an external event is programmed in fast mode.
01722   */
01723 #define LL_HRTIM_EE_FASTMODE_DISABLE         0x00000000U              /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
01724 #define LL_HRTIM_EE_FASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is acting asynchronously on outputs (low latency mode) */
01725 /**
01726   * @}
01727   */
01728
01729 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
01730   * @{
01731   * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
01732   */
01733 #define LL_HRTIM_EE_FILTER_NONE      0x00000000U                                                               /*!< Filter disabled */
01734 #define LL_HRTIM_EE_FILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING = fHRTIM, N=2 */
01735 #define LL_HRTIM_EE_FILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING = fHRTIM, N=4 */
01736 #define LL_HRTIM_EE_FILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fHRTIM, N=8 */
01737 #define LL_HRTIM_EE_FILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING = fEEVS/2, N=6 */
01738 #define LL_HRTIM_EE_FILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/2, N=8 */
01739 #define LL_HRTIM_EE_FILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/4, N=6 */
01740 #define LL_HRTIM_EE_FILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/4, N=8 */
01741 #define LL_HRTIM_EE_FILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING = fEEVS/8, N=6 */
01742 #define LL_HRTIM_EE_FILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/8, N=8 */
01743 #define LL_HRTIM_EE_FILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/16, N=5 */
01744 #define LL_HRTIM_EE_FILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/16, N=6 */
01745 #define LL_HRTIM_EE_FILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING = fEEVS/16, N=8 */
01746 #define LL_HRTIM_EE_FILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING = fEEVS/32, N=5 */
01747 #define LL_HRTIM_EE_FILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING = fEEVS/32, N=6 */
01748 #define LL_HRTIM_EE_FILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING = fEEVS/32, N=8 */
01749 /**
01750   * @}
01751   */
01752
01753 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
01754   * @{
01755   * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
01756   */
01757 #define LL_HRTIM_EE_PRESCALER_DIV1    0x00000000U                     /*!< fEEVS = fHRTIM */
01758 #define LL_HRTIM_EE_PRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                       /*!< fEEVS = fHRTIM / 2 */
01759 #define LL_HRTIM_EE_PRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                       /*!< fEEVS = fHRTIM / 4 */
01760 #define LL_HRTIM_EE_PRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
01761 /**
01762   * @}
01763   */
01764
01765 /** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
01766   * @{
01767   * @brief Constants defining the external event counter.
01768   */
01769 #define LL_HRTIM_EE_COUNTER_A    ((uint32_t)0U)                     /*!< External Event A Counter */
01770 #define LL_HRTIM_EE_COUNTER_B    ((uint32_t)16U)                    /*!< External Event B Counter */
01771 /**
01772   * @}
01773   */
01774
01775 /** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
01776   * @{
01777   * @brief Constants defining the external event reset mode.
01778   */
01779 #define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL   ((uint32_t)0U)                     /*!< External Event counter is reset on each reset / roll-over event */
01780 #define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL     ((uint32_t)HRTIM_EEFR3_EEVARSTM)   /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
01781 /**
01782   * @}
01783   */
01784
01785 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
01786   * @{
01787   * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
01788   */
01789 #define LL_HRTIM_FLT_SRC_DIGITALINPUT         0x00000000U                /*!< Fault input is FLT input pin */
01790 #define LL_HRTIM_FLT_SRC_INTERNAL             HRTIM_FLTINR1_FLT1SRC_0    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
01791 #define LL_HRTIM_FLT_SRC_EEVINPUT             HRTIM_FLTINR2_FLT1SRC_1    /*!< Fault input is external event  pin */
01792 /**
01793   * @}
01794   */
01795
01796 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
01797   * @{
01798   * @brief Constants defining the polarity of a fault event.
01799   */
01800 #define LL_HRTIM_FLT_POLARITY_LOW     0x00000000U                /*!< Fault input is active low */
01801 #define LL_HRTIM_FLT_POLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)      /*!< Fault input is active high */
01802 /**
01803   * @}
01804   */
01805
01806 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
01807   * @{
01808   * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
01809   */
01810 #define LL_HRTIM_FLT_FILTER_NONE      0x00000000U                                                                          /*!< Filter disabled */
01811 #define LL_HRTIM_FLT_FILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2 */
01812 #define LL_HRTIM_FLT_FILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4 */
01813 #define LL_HRTIM_FLT_FILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8 */
01814 #define LL_HRTIM_FLT_FILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6 */
01815 #define LL_HRTIM_FLT_FILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8 */
01816 #define LL_HRTIM_FLT_FILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6 */
01817 #define LL_HRTIM_FLT_FILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8 */
01818 #define LL_HRTIM_FLT_FILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6 */
01819 #define LL_HRTIM_FLT_FILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8 */
01820 #define LL_HRTIM_FLT_FILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5 */
01821 #define LL_HRTIM_FLT_FILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6 */
01822 #define LL_HRTIM_FLT_FILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8 */
01823 #define LL_HRTIM_FLT_FILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5 */
01824 #define LL_HRTIM_FLT_FILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6 */
01825 #define LL_HRTIM_FLT_FILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8 */
01826 /**
01827   * @}
01828   */
01829
01830 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
01831   * @{
01832   * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used  by the digital filters.
01833   */
01834 #define LL_HRTIM_FLT_PRESCALER_DIV1    0x00000000U                                     /*!< fFLTS = fHRTIM */
01835 #define LL_HRTIM_FLT_PRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                         /*!< fFLTS = fHRTIM / 2 */
01836 #define LL_HRTIM_FLT_PRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                         /*!< fFLTS = fHRTIM / 4 */
01837 #define LL_HRTIM_FLT_PRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
01838 /**
01839   * @}
01840   */
01841
01842 /** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
01843   * @{
01844   * @brief Constants defining the Blanking Source of a fault event.
01845   */
01846 #define LL_HRTIM_FLT_BLANKING_RSTALIGNED            0x00000000U                /*!< Fault blanking source is Reset-aligned  */
01847 #define LL_HRTIM_FLT_BLANKING_MOVING                (HRTIM_FLTINR3_FLT1BLKS)   /*!< Fault blanking source is Moving window */
01848 /**
01849   * @}
01850   */
01851
01852 /** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
01853   * @{
01854   * @brief Constants defining the Counter RESet Mode of a fault event.
01855   */
01856 #define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL    0x00000000U                    /*!< Fault counter is reset on each reset / roll-over event */
01857 #define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL      (HRTIM_FLTINR3_FLT1RSTM)       /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
01858 period. */
01859 /**
01860   * @}
01861   */
01862
01863 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
01864   * @{
01865   * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
01866   */
01867 #define LL_HRTIM_BM_MODE_SINGLESHOT  0x00000000U            /*!< Burst mode operates in single shot mode */
01868 #define LL_HRTIM_BM_MODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
01869 /**
01870   * @}
01871   */
01872
01873 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
01874   * @{
01875   * @brief Constants defining the clock source for the burst mode counter.
01876   */
01877 #define LL_HRTIM_BM_CLKSRC_MASTER     0x00000000U                                         /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
01878 #define LL_HRTIM_BM_CLKSRC_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
01879 #define LL_HRTIM_BM_CLKSRC_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
01880 #define LL_HRTIM_BM_CLKSRC_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
01881 #define LL_HRTIM_BM_CLKSRC_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
01882 #define LL_HRTIM_BM_CLKSRC_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
01883 #define LL_HRTIM_BM_CLKSRC_TIMER_F    (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
01884 #define LL_HRTIM_BM_CLKSRC_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
01885 #define LL_HRTIM_BM_CLKSRC_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
01886 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
01887 #define LL_HRTIM_BM_CLKSRC_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
01888 /**
01889   * @}
01890   */
01891
01892 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
01893   * @{
01894   * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
01895   */
01896 #define LL_HRTIM_BM_PRESCALER_DIV1     0x00000000U                                                                 /*!< fBRST = fHRTIM */
01897 #define LL_HRTIM_BM_PRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2 */
01898 #define LL_HRTIM_BM_PRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4 */
01899 #define LL_HRTIM_BM_PRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8 */
01900 #define LL_HRTIM_BM_PRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16 */
01901 #define LL_HRTIM_BM_PRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32 */
01902 #define LL_HRTIM_BM_PRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64 */
01903 #define LL_HRTIM_BM_PRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128 */
01904 #define LL_HRTIM_BM_PRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256 */
01905 #define LL_HRTIM_BM_PRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512 */
01906 #define LL_HRTIM_BM_PRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024 */
01907 #define LL_HRTIM_BM_PRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048*/
01908 #define LL_HRTIM_BM_PRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096 */
01909 #define LL_HRTIM_BM_PRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192 */
01910 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384 */
01911 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
01912 /**
01913   * @}
01914   */
01915
01916 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
01917   * @{
01918   * @brief Constants defining the events that can be used to trig the burst mode operation.
01919   */
01920 #define LL_HRTIM_BM_TRIG_NONE               0x00000000U             /*!<  No trigger */
01921 #define LL_HRTIM_BM_TRIG_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master timer reset event is starting the burst mode operation */
01922 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master timer repetition event is starting the burst mode operation */
01923 #define LL_HRTIM_BM_TRIG_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master timer compare 1 event is starting the burst mode operation */
01924 #define LL_HRTIM_BM_TRIG_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master timer compare 2 event is starting the burst mode operation */
01925 #define LL_HRTIM_BM_TRIG_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master timer compare 3 event is starting the burst mode operation */
01926 #define LL_HRTIM_BM_TRIG_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master timer compare 4 event is starting the burst mode operation */
01927 #define LL_HRTIM_BM_TRIG_TIMA_RESET         (HRTIM_BMTRGR_TARST)    /*!< Timer A reset event is starting the burst mode operation */
01928 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION    (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition event is starting the burst mode operation */
01929 #define LL_HRTIM_BM_TRIG_TIMA_CMP1          (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1 event is starting the burst mode operation */
01930 #define LL_HRTIM_BM_TRIG_TIMA_CMP2          (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2 event is starting the burst mode operation */
01931 #define LL_HRTIM_BM_TRIG_TIMB_RESET         (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset event is starting the burst mode operation */
01932 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION    (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition event is starting the burst mode operation */
01933 #define LL_HRTIM_BM_TRIG_TIMB_CMP1          (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1 event is starting the burst mode operation */
01934 #define LL_HRTIM_BM_TRIG_TIMB_CMP2          (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2 event is starting the burst mode operation */
01935 #define LL_HRTIM_BM_TRIG_TIMC_RESET         (HRTIM_BMTRGR_TCRST)    /*!< Timer C resetevent is starting the burst mode operation  */
01936 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION    (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition event is starting the burst mode operation */
01937 #define LL_HRTIM_BM_TRIG_TIMC_CMP1          (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1 event is starting the burst mode operation */
01938 #define LL_HRTIM_BM_TRIG_TIMD_RESET         (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset event is starting the burst mode operation */
01939 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION    (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition event is starting the burst mode operation */
01940 #define LL_HRTIM_BM_TRIG_TIMD_CMP2          (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2 event is starting the burst mode operation */
01941 #define LL_HRTIM_BM_TRIG_TIME_REPETITION    (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition event is starting the burst mode operation */
01942 #define LL_HRTIM_BM_TRIG_TIME_CMP1          (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1 event is starting the burst mode operation */
01943 #define LL_HRTIM_BM_TRIG_TIME_CMP2          (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2 event is starting the burst mode operation */
01944 #define LL_HRTIM_BM_TRIG_TIMF_RESET         (HRTIM_BMTRGR_TFRST)    /*!< Timer F reset event is starting the burst mode operation */
01945 #define LL_HRTIM_BM_TRIG_TIMF_REPETITION    (HRTIM_BMTRGR_TFREP)    /*!< Timer F repetition event is starting the burst mode operation */
01946 #define LL_HRTIM_BM_TRIG_TIMF_CMP1          (HRTIM_BMTRGR_TFCMP1)   /*!< Timer F compare 1 event is starting the burst mode operation */
01947 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7        (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation  */
01948 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8        (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation  */
01949 #define LL_HRTIM_BM_TRIG_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
01950 #define LL_HRTIM_BM_TRIG_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
01951 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
01952 /**
01953   * @}
01954   */
01955
01956 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
01957   * @{
01958   * @brief Constants defining the operating state of the burst mode controller.
01959   */
01960 #define LL_HRTIM_BM_STATUS_NORMAL             0x00000000U           /*!< Normal operation */
01961 #define LL_HRTIM_BM_STATUS_BURST_ONGOING      HRTIM_BMCR_BMSTAT     /*!< Burst operation on-going */
01962 /**
01963   * @}
01964   */
01965
01966 /** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
01967   * @{
01968   * @brief Constants defining the Counter Up Down Mode.
01969   */
01970 #define LL_HRTIM_COUNTING_MODE_UP                    0x00000000U           /*!< counter is operating in up-counting mode */
01971 #define LL_HRTIM_COUNTING_MODE_UP_DOWN               HRTIM_TIMCR2_UDM      /*!< counter is operating in up-down counting mode  */
01972 /**
01973   * @}
01974   */
01975
01976 /** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
01977   * @{
01978   * @brief Constants defining the Roll-Over counter Mode.
01979   */
01980 #define LL_HRTIM_ROLLOVER_MODE_PER            2U                        /*!< Event generated when counter reaches period value  ('crest' mode) */
01981 #define LL_HRTIM_ROLLOVER_MODE_RST            1U                        /*!< Event generated when counter equals 0 ('valley' mode) */
01982 #define LL_HRTIM_ROLLOVER_MODE_BOTH           0U                        /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
01983 /**
01984   * @}
01985   */
01986
01987 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
01988   * @{
01989   * @brief Constants defining how the timer counter operates.
01990   */
01991 #define LL_HRTIM_TRIGHALF_DISABLED        0x00000000U            /*!< Timer Compare 2 register is behaving in standard mode */
01992 #define LL_HRTIM_TRIGHALF_ENABLED         HRTIM_TIMCR2_TRGHLF    /*!< Timer Compare 2 register is behaving in triggered-half mode  */
01993 /**
01994   * @}
01995   */
01996
01997 /** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
01998   * @{
01999   * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
02000   */
02001 #define LL_HRTIM_GTCMP1_EQUAL             0x00000000U            /*!< event is generated when counter is equal to compare value */
02002 #define LL_HRTIM_GTCMP1_GREATER           HRTIM_TIMCR2_GTCMP1    /*!< event is generated when counter is greater than compare value */
02003 #define LL_HRTIM_GTCMP3_EQUAL             0x00000000U            /*!< event is generated when counter is equal to compare value */
02004 #define LL_HRTIM_GTCMP3_GREATER           HRTIM_TIMCR2_GTCMP3    /*!< event is generated when counter is greater than compare value */
02005 /**
02006   * @}
02007   */
02008
02009 /** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
02010   * @{
02011   * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
02012   */
02013 #define LL_HRTIM_DCDE_DISABLED      0x00000000U              /*!<  Dual Channel DAC trigger is generated on counter reset or roll-over event */
02014 #define LL_HRTIM_DCDE_ENABLED       HRTIM_TIMCR2_DCDE        /*!<  Dual Channel DAC trigger is generated on output 1 set  event */
02015 /**
02016   * @}
02017   */
02018
02019 /** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
02020   * @{
02021   * @brief Constants defining the Dual Channel DAC Reset trigger.
02022   */
02023 #define LL_HRTIM_DCDR_COUNTER       0x00000000U              /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
02024 #define LL_HRTIM_DCDR_OUT1SET       HRTIM_TIMCR2_DCDR        /*!< Dual Channel DAC trigger is generated on output 1 set  event */
02025 /**
02026   * @}
02027   */
02028
02029 /** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
02030   * @{
02031   * @brief Constants defining the Dual Channel DAC Step trigger.
02032   */
02033 #define LL_HRTIM_DCDS_CMP2          0x00000000U              /*!< trigger is generated on compare 2 event */
02034 #define LL_HRTIM_DCDS_OUT1RST       HRTIM_TIMCR2_DCDS        /*!< trigger is generated on output 1 reset event */
02035 /**
02036   * @}
02037   */
02038
02039 /**
02040   * @}
02041   */
02042
02043 /* Exported macro ------------------------------------------------------------*/
02044 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
02045   * @{
02046   */
02047
02048 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
02049   * @{
02050   */
02051
02052 /**
02053   * @brief  Write a value in HRTIM register
02054   * @param  __INSTANCE__ HRTIM Instance
02055   * @param  __REG__ Register to be written
02056   * @param  __VALUE__ Value to be written in the register
02057   * @retval None
02058   */
02059 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
02060
02061 /**
02062   * @brief  Read a value in HRTIM register
02063   * @param  __INSTANCE__ HRTIM Instance
02064   * @param  __REG__ Register to be read
02065   * @retval Register value
02066   */
02067 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
02068 /**
02069   * @}
02070   */
02071
02072 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
02073   * @{
02074   */
02075 /**
02076   * @brief  HELPER macro returning the output state from output enable/disable status
02077   * @param  __OUTPUT_STATUS_EN__ output enable status
02078   * @param  __OUTPUT_STATUS_DIS__ output Disable status
02079   * @retval Returned value can be one of the following values:
02080   *         @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
02081   *         @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
02082   *         @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
02083   */
02084 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
02085   (((__OUTPUT_STATUS_EN__) == 1) ?  LL_HRTIM_OUTPUTSTATE_RUN :\
02086    ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
02087 /**
02088   * @}
02089   */
02090
02091 /**
02092   * @}
02093   */
02094
02095 /* Exported functions --------------------------------------------------------*/
02096 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
02097   * @{
02098   */
02099 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
02100   * @{
02101   */
02102
02103 /**
02104   * @brief  Select the HRTIM synchronization input source.
02105   * @note This function must not be called when  the concerned timer(s) is (are) enabled .
02106   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
02107   * @param  HRTIMx High Resolution Timer instance
02108   * @param  SyncInSrc This parameter can be one of the following values:
02109   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
02110   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
02111   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
02112   * @retval None
02113   */
02114 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
02115 {
02116   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
02117 }
02118
02119 /**
02120   * @brief  Get actual HRTIM synchronization input source.
02121   * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
02122   * @param  HRTIMx High Resolution Timer instance
02123   * @retval SyncInSrc Returned value can be one of the following values:
02124   *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
02125   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
02126   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
02127   */
02128 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
02129 {
02130   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
02131 }
02132
02133 /**
02134   * @brief  Configure the HRTIM synchronization output.
02135   * @rmtoll MCR          SYNCSRC      LL_HRTIM_ConfigSyncOut\n
02136   *         MCR          SYNCOUT      LL_HRTIM_ConfigSyncOut
02137   * @param  HRTIMx High Resolution Timer instance
02138   * @param  Config This parameter can be one of the following values:
02139   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
02140   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
02141   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
02142   * @param  Src This parameter can be one of the following values:
02143   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
02144   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
02145   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
02146   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
02147   * @retval None
02148   */
02149 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
02150 {
02151   MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
02152 }
02153
02154 /**
02155   * @brief  Set the routing and conditioning of the synchronization output event.
02156   * @rmtoll MCR          SYNCOUT      LL_HRTIM_SetSyncOutConfig
02157   * @note This function can be called only when the master timer is enabled.
02158   * @param  HRTIMx High Resolution Timer instance
02159   * @param  SyncOutConfig This parameter can be one of the following values:
02160   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
02161   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
02162   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
02166 {
02167   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
02168 }
02169
02170 /**
02171   * @brief  Get actual routing and conditioning of the synchronization output event.
02172   * @rmtoll MCR          SYNCOUT      LL_HRTIM_GetSyncOutConfig
02173   * @param  HRTIMx High Resolution Timer instance
02174   * @retval SyncOutConfig Returned value can be one of the following values:
02175   *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
02176   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
02177   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
02178   */
02179 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
02180 {
02181   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
02182 }
02183
02184 /**
02185   * @brief  Set the source and event to be sent on the HRTIM synchronization output.
02186   * @rmtoll MCR          SYNCSRC      LL_HRTIM_SetSyncOutSrc
02187   * @param  HRTIMx High Resolution Timer instance
02188   * @param  SyncOutSrc This parameter can be one of the following values:
02189   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
02190   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
02191   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
02192   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
02193   * @retval None
02194   */
02195 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
02196 {
02197   MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
02198 }
02199
02200 /**
02201   * @brief  Get actual  source and event sent on the HRTIM synchronization output.
02202   * @rmtoll MCR          SYNCSRC      LL_HRTIM_GetSyncOutSrc
02203   * @param  HRTIMx High Resolution Timer instance
02204   * @retval SyncOutSrc Returned value can be one of the following values:
02205   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
02206   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
02207   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
02208   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
02209   */
02210 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
02211 {
02212   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
02213 }
02214
02215 /**
02216   * @brief  Disable (temporarily) update event generation.
02217   * @rmtoll CR1          MUDIS         LL_HRTIM_SuspendUpdate\n
02218   *         CR1          TAUDIS        LL_HRTIM_SuspendUpdate\n
02219   *         CR1          TBUDIS        LL_HRTIM_SuspendUpdate\n
02220   *         CR1          TCUDIS        LL_HRTIM_SuspendUpdate\n
02221   *         CR1          TDUDIS        LL_HRTIM_SuspendUpdate\n
02222   *         CR1          TEUDIS        LL_HRTIM_SuspendUpdate\n
02223   *         CR1          TFUDIS        LL_HRTIM_SuspendUpdate
02224   * @note Allow to temporarily disable the transfer from preload to active
02225   *      registers, whatever the selected update event. This allows to modify
02226   *      several registers in multiple timers.
02227   * @param  HRTIMx High Resolution Timer instance
02228   * @param  Timers This parameter can be a combination of the following values:
02229   *         @arg @ref LL_HRTIM_TIMER_MASTER
02230   *         @arg @ref LL_HRTIM_TIMER_A
02231   *         @arg @ref LL_HRTIM_TIMER_B
02232   *         @arg @ref LL_HRTIM_TIMER_C
02233   *         @arg @ref LL_HRTIM_TIMER_D
02234   *         @arg @ref LL_HRTIM_TIMER_E
02235   *         @arg @ref LL_HRTIM_TIMER_F
02236   * @retval None
02237   */
02238 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02239 {
02240   /* clear register before applying the new value */
02241   CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
02242   SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
02243 }
02244
02245 /**
02246   * @brief  Enable update event generation.
02247   * @rmtoll CR1          MUDIS         LL_HRTIM_ResumeUpdate\n
02248   *         CR1          TAUDIS        LL_HRTIM_ResumeUpdate\n
02249   *         CR1          TBUDIS        LL_HRTIM_ResumeUpdate\n
02250   *         CR1          TCUDIS        LL_HRTIM_ResumeUpdate\n
02251   *         CR1          TDUDIS        LL_HRTIM_ResumeUpdate\n
02252   *         CR1          TEUDIS        LL_HRTIM_ResumeUpdate\n
02253   *         CR1          TFUDIS        LL_HRTIM_ResumeUpdate
02254   * @note The regular update event takes place.
02255   * @param  HRTIMx High Resolution Timer instance
02256   * @param  Timers This parameter can be a combination of the following values:
02257   *         @arg @ref LL_HRTIM_TIMER_MASTER
02258   *         @arg @ref LL_HRTIM_TIMER_A
02259   *         @arg @ref LL_HRTIM_TIMER_B
02260   *         @arg @ref LL_HRTIM_TIMER_C
02261   *         @arg @ref LL_HRTIM_TIMER_D
02262   *         @arg @ref LL_HRTIM_TIMER_E
02263   *         @arg @ref LL_HRTIM_TIMER_F
02264   * @retval None
02265   */
02266 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02267 {
02268   CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
02269 }
02270
02271 /**
02272   * @brief  Force an immediate transfer from the preload to the active register .
02273   * @rmtoll CR2          MSWU          LL_HRTIM_ForceUpdate\n
02274   *         CR2          TASWU         LL_HRTIM_ForceUpdate\n
02275   *         CR2          TBSWU         LL_HRTIM_ForceUpdate\n
02276   *         CR2          TCSWU         LL_HRTIM_ForceUpdate\n
02277   *         CR2          TDSWU         LL_HRTIM_ForceUpdate\n
02278   *         CR2          TESWU         LL_HRTIM_ForceUpdate\n
02279   *         CR2          TFSWU         LL_HRTIM_ForceUpdate
02280   * @note Any pending update request is cancelled.
02281   * @param  HRTIMx High Resolution Timer instance
02282   * @param  Timers This parameter can be a combination of the following values:
02283   *         @arg @ref LL_HRTIM_TIMER_MASTER
02284   *         @arg @ref LL_HRTIM_TIMER_A
02285   *         @arg @ref LL_HRTIM_TIMER_B
02286   *         @arg @ref LL_HRTIM_TIMER_C
02287   *         @arg @ref LL_HRTIM_TIMER_D
02288   *         @arg @ref LL_HRTIM_TIMER_E
02289   *         @arg @ref LL_HRTIM_TIMER_F
02290   * @retval None
02291   */
02292 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02293 {
02294   SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
02295 }
02296
02297 /**
02298   * @brief  Reset the HRTIM timer(s) counter.
02299   * @rmtoll CR2          MRST          LL_HRTIM_CounterReset\n
02300   *         CR2          TARST         LL_HRTIM_CounterReset\n
02301   *         CR2          TBRST         LL_HRTIM_CounterReset\n
02302   *         CR2          TCRST         LL_HRTIM_CounterReset\n
02303   *         CR2          TDRST         LL_HRTIM_CounterReset\n
02304   *         CR2          TERST         LL_HRTIM_CounterReset\n
02305   *         CR2          TFRST         LL_HRTIM_CounterReset
02306   * @param  HRTIMx High Resolution Timer instance
02307   * @param  Timers This parameter can be a combination of the following values:
02308   *         @arg @ref LL_HRTIM_TIMER_MASTER
02309   *         @arg @ref LL_HRTIM_TIMER_A
02310   *         @arg @ref LL_HRTIM_TIMER_B
02311   *         @arg @ref LL_HRTIM_TIMER_C
02312   *         @arg @ref LL_HRTIM_TIMER_D
02313   *         @arg @ref LL_HRTIM_TIMER_E
02314   *         @arg @ref LL_HRTIM_TIMER_F
02315   * @retval None
02316   */
02317 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
02318 {
02319   SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
02320 }
02321
02322 /**
02323   * @brief  enable the swap of the Timer Output.
02324   * @note   the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
02325   *         and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
02326   * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
02327   * @rmtoll CR2          SWPA         LL_HRTIM_EnableSwapOutputs\n
02328   *         CR2          SWPB         LL_HRTIM_EnableSwapOutputs\n
02329   *         CR2          SWPC         LL_HRTIM_EnableSwapOutputs\n
02330   *         CR2          SWPD         LL_HRTIM_EnableSwapOutputs\n
02331   *         CR2          SWPE         LL_HRTIM_EnableSwapOutputs\n
02332   *         CR2          SWPF         LL_HRTIM_EnableSwapOutputs
02333   * @param  HRTIMx High Resolution Timer instance
02334   * @param  Timer This parameter can be one of the following values:
02335   *         @arg @ref LL_HRTIM_TIMER_A
02336   *         @arg @ref LL_HRTIM_TIMER_B
02337   *         @arg @ref LL_HRTIM_TIMER_C
02338   *         @arg @ref LL_HRTIM_TIMER_D
02339   *         @arg @ref LL_HRTIM_TIMER_E
02340   *         @arg @ref LL_HRTIM_TIMER_F
02341   * @retval None
02342   */
02343 __STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02344 {
02345   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
02346
02347   SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
02348 }
02349
02350 /**
02351   * @brief  disable the swap of the Timer Output.
02352   * @note   the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
02353   *         and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
02354   * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
02355   * @rmtoll CR2          SWPA         LL_HRTIM_DisableSwapOutputs\n
02356   *         CR2          SWPB         LL_HRTIM_DisableSwapOutputs\n
02357   *         CR2          SWPC         LL_HRTIM_DisableSwapOutputs\n
02358   *         CR2          SWPD         LL_HRTIM_DisableSwapOutputs\n
02359   *         CR2          SWPE         LL_HRTIM_DisableSwapOutputs\n
02360   *         CR2          SWPF         LL_HRTIM_DisableSwapOutputs
02361   * @param  HRTIMx High Resolution Timer instance
02362   * @param  Timer This parameter can be one of the following values:
02363   *         @arg @ref LL_HRTIM_TIMER_A
02364   *         @arg @ref LL_HRTIM_TIMER_B
02365   *         @arg @ref LL_HRTIM_TIMER_C
02366   *         @arg @ref LL_HRTIM_TIMER_D
02367   *         @arg @ref LL_HRTIM_TIMER_E
02368   *         @arg @ref LL_HRTIM_TIMER_F
02369   * @retval None
02370   */
02371 __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02372 {
02373   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
02374
02375   CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
02376 }
02377
02378 /**
02379   * @brief  reports the Timer Outputs swap position.
02380   * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
02381   * @rmtoll CR2          SWPA         LL_HRTIM_IsEnabledSwapOutputs\n
02382   *         CR2          SWPB         LL_HRTIM_IsEnabledSwapOutputs\n
02383   *         CR2          SWPC         LL_HRTIM_IsEnabledSwapOutputs\n
02384   *         CR2          SWPD         LL_HRTIM_IsEnabledSwapOutputs\n
02385   *         CR2          SWPE         LL_HRTIM_IsEnabledSwapOutputs\n
02386   *         CR2          SWPF         LL_HRTIM_IsEnabledSwapOutputs
02387   * @param  HRTIMx High Resolution Timer instance
02388   * @param  Timer This parameter can be one of the following values:
02389   *         @arg @ref LL_HRTIM_TIMER_A
02390   *         @arg @ref LL_HRTIM_TIMER_B
02391   *         @arg @ref LL_HRTIM_TIMER_C
02392   *         @arg @ref LL_HRTIM_TIMER_D
02393   *         @arg @ref LL_HRTIM_TIMER_E
02394   *         @arg @ref LL_HRTIM_TIMER_F
02395   * @retval
02396   *         1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
02397   *            HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
02398   *         0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
02399   *            HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
02400   */
02401 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
02402 {
02403   uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
02404
02405   return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
02406 }
02407
02408 /**
02409   * @brief  Enable the HRTIM timer(s) output(s) .
02410   * @rmtoll OENR         TA1OEN        LL_HRTIM_EnableOutput\n
02411   *         OENR         TA2OEN        LL_HRTIM_EnableOutput\n
02412   *         OENR         TB1OEN        LL_HRTIM_EnableOutput\n
02413   *         OENR         TB2OEN        LL_HRTIM_EnableOutput\n
02414   *         OENR         TC1OEN        LL_HRTIM_EnableOutput\n
02415   *         OENR         TC2OEN        LL_HRTIM_EnableOutput\n
02416   *         OENR         TD1OEN        LL_HRTIM_EnableOutput\n
02417   *         OENR         TD2OEN        LL_HRTIM_EnableOutput\n
02418   *         OENR         TE1OEN        LL_HRTIM_EnableOutput\n
02419   *         OENR         TE2OEN        LL_HRTIM_EnableOutput\n
02420   *         OENR         TF1OEN        LL_HRTIM_EnableOutput\n
02421   *         OENR         TF2OEN        LL_HRTIM_EnableOutput
02422   * @param  HRTIMx High Resolution Timer instance
02423   * @param  Outputs This parameter can be a combination of the following values:
02424   *         @arg @ref LL_HRTIM_OUTPUT_TA1
02425   *         @arg @ref LL_HRTIM_OUTPUT_TA2
02426   *         @arg @ref LL_HRTIM_OUTPUT_TB1
02427   *         @arg @ref LL_HRTIM_OUTPUT_TB2
02428   *         @arg @ref LL_HRTIM_OUTPUT_TC1
02429   *         @arg @ref LL_HRTIM_OUTPUT_TC2
02430   *         @arg @ref LL_HRTIM_OUTPUT_TD1
02431   *         @arg @ref LL_HRTIM_OUTPUT_TD2
02432   *         @arg @ref LL_HRTIM_OUTPUT_TE1
02433   *         @arg @ref LL_HRTIM_OUTPUT_TE2
02434   *         @arg @ref LL_HRTIM_OUTPUT_TF1
02435   *         @arg @ref LL_HRTIM_OUTPUT_TF2
02436   * @retval None
02437   */
02438 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
02439 {
02440   SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
02441 }
02442
02443 /**
02444   * @brief  Disable the HRTIM timer(s) output(s) .
02445   * @rmtoll OENR         TA1OEN        LL_HRTIM_DisableOutput\n
02446   *         OENR         TA2OEN        LL_HRTIM_DisableOutput\n
02447   *         OENR         TB1OEN        LL_HRTIM_DisableOutput\n
02448   *         OENR         TB2OEN        LL_HRTIM_DisableOutput\n
02449   *         OENR         TC1OEN        LL_HRTIM_DisableOutput\n
02450   *         OENR         TC2OEN        LL_HRTIM_DisableOutput\n
02451   *         OENR         TD1OEN        LL_HRTIM_DisableOutput\n
02452   *         OENR         TD2OEN        LL_HRTIM_DisableOutput\n
02453   *         OENR         TE1OEN        LL_HRTIM_DisableOutput\n
02454   *         OENR         TE2OEN        LL_HRTIM_DisableOutput\n
02455   *         OENR         TF1OEN        LL_HRTIM_DisableOutput\n
02456   *         OENR         TF2OEN        LL_HRTIM_DisableOutput
02457   * @param  HRTIMx High Resolution Timer instance
02458   * @param  Outputs This parameter can be a combination of the following values:
02459   *         @arg @ref LL_HRTIM_OUTPUT_TA1
02460   *         @arg @ref LL_HRTIM_OUTPUT_TA2
02461   *         @arg @ref LL_HRTIM_OUTPUT_TB1
02462   *         @arg @ref LL_HRTIM_OUTPUT_TB2
02463   *         @arg @ref LL_HRTIM_OUTPUT_TC1
02464   *         @arg @ref LL_HRTIM_OUTPUT_TC2
02465   *         @arg @ref LL_HRTIM_OUTPUT_TD1
02466   *         @arg @ref LL_HRTIM_OUTPUT_TD2
02467   *         @arg @ref LL_HRTIM_OUTPUT_TE1
02468   *         @arg @ref LL_HRTIM_OUTPUT_TE2
02469   *         @arg @ref LL_HRTIM_OUTPUT_TF1
02470   *         @arg @ref LL_HRTIM_OUTPUT_TF2
02471   * @retval None
02472   */
02473 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
02474 {
02475   SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
02476 }
02477
02478 /**
02479   * @brief  Indicates whether the HRTIM timer output is enabled.
02480   * @rmtoll OENR         TA1OEN        LL_HRTIM_IsEnabledOutput\n
02481   *         OENR         TA2OEN        LL_HRTIM_IsEnabledOutput\n
02482   *         OENR         TB1OEN        LL_HRTIM_IsEnabledOutput\n
02483   *         OENR         TB2OEN        LL_HRTIM_IsEnabledOutput\n
02484   *         OENR         TC1OEN        LL_HRTIM_IsEnabledOutput\n
02485   *         OENR         TC2OEN        LL_HRTIM_IsEnabledOutput\n
02486   *         OENR         TD1OEN        LL_HRTIM_IsEnabledOutput\n
02487   *         OENR         TD2OEN        LL_HRTIM_IsEnabledOutput\n
02488   *         OENR         TE1OEN        LL_HRTIM_IsEnabledOutput\n
02489   *         OENR         TE2OEN        LL_HRTIM_IsEnabledOutput\n
02490   *         OENR         TF1OEN        LL_HRTIM_IsEnabledOutput\n
02491   *         OENR         TF2OEN        LL_HRTIM_IsEnabledOutput
02492   * @param  HRTIMx High Resolution Timer instance
02493   * @param  Output This parameter can be one of the following values:
02494   *         @arg @ref LL_HRTIM_OUTPUT_TA1
02495   *         @arg @ref LL_HRTIM_OUTPUT_TA2
02496   *         @arg @ref LL_HRTIM_OUTPUT_TB1
02497   *         @arg @ref LL_HRTIM_OUTPUT_TB2
02498   *         @arg @ref LL_HRTIM_OUTPUT_TC1
02499   *         @arg @ref LL_HRTIM_OUTPUT_TC2
02500   *         @arg @ref LL_HRTIM_OUTPUT_TD1
02501   *         @arg @ref LL_HRTIM_OUTPUT_TD2
02502   *         @arg @ref LL_HRTIM_OUTPUT_TE1
02503   *         @arg @ref LL_HRTIM_OUTPUT_TE2
02504   *         @arg @ref LL_HRTIM_OUTPUT_TF1
02505   *         @arg @ref LL_HRTIM_OUTPUT_TF2
02506   * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
02507   */
02508 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
02509 {
02510   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
02511 }
02512
02513 /**
02514   * @brief  Indicates whether the HRTIM timer output is disabled.
02515   * @rmtoll ODISR        TA1ODIS        LL_HRTIM_IsDisabledOutput\n
02516   *         ODISR        TA2ODIS        LL_HRTIM_IsDisabledOutput\n
02517   *         ODISR        TB1ODIS        LL_HRTIM_IsDisabledOutput\n
02518   *         ODISR        TB2ODIS        LL_HRTIM_IsDisabledOutput\n
02519   *         ODISR        TC1ODIS        LL_HRTIM_IsDisabledOutput\n
02520   *         ODISR        TC2ODIS        LL_HRTIM_IsDisabledOutput\n
02521   *         ODISR        TD1ODIS        LL_HRTIM_IsDisabledOutput\n
02522   *         ODISR        TD2ODIS        LL_HRTIM_IsDisabledOutput\n
02523   *         ODISR        TE1ODIS        LL_HRTIM_IsDisabledOutput\n
02524   *         ODISR        TE2ODIS        LL_HRTIM_IsDisabledOutput\n
02525   *         ODISR        TF1ODIS        LL_HRTIM_IsDisabledOutput\n
02526   *         ODISR        TF2ODIS        LL_HRTIM_IsDisabledOutput
02527   * @param  HRTIMx High Resolution Timer instance
02528   * @param  Output This parameter can be one of the following values:
02529   *         @arg @ref LL_HRTIM_OUTPUT_TA1
02530   *         @arg @ref LL_HRTIM_OUTPUT_TA2
02531   *         @arg @ref LL_HRTIM_OUTPUT_TB1
02532   *         @arg @ref LL_HRTIM_OUTPUT_TB2
02533   *         @arg @ref LL_HRTIM_OUTPUT_TC1
02534   *         @arg @ref LL_HRTIM_OUTPUT_TC2
02535   *         @arg @ref LL_HRTIM_OUTPUT_TD1
02536   *         @arg @ref LL_HRTIM_OUTPUT_TD2
02537   *         @arg @ref LL_HRTIM_OUTPUT_TE1
02538   *         @arg @ref LL_HRTIM_OUTPUT_TE2
02539   *         @arg @ref LL_HRTIM_OUTPUT_TF1
02540   *         @arg @ref LL_HRTIM_OUTPUT_TF2
02541   * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
02542   */
02543 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
02544 {
02545   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
02546 }
02547
02548 /**
02549   * @brief  Configure an ADC trigger.
02550   * @rmtoll CR1          ADC1USRC        LL_HRTIM_ConfigADCTrig\n
02551   *         CR1          ADC2USRC        LL_HRTIM_ConfigADCTrig\n
02552   *         CR1          ADC3USRC        LL_HRTIM_ConfigADCTrig\n
02553   *         CR1          ADC4USRC        LL_HRTIM_ConfigADCTrig\n
02554   *         ADC1R        ADC1MC1         LL_HRTIM_ConfigADCTrig\n
02555   *         ADC1R        ADC1MC2         LL_HRTIM_ConfigADCTrig\n
02556   *         ADC1R        ADC1MC3         LL_HRTIM_ConfigADCTrig\n
02557   *         ADC1R        ADC1MC4         LL_HRTIM_ConfigADCTrig\n
02558   *         ADC1R        ADC1MPER        LL_HRTIM_ConfigADCTrig\n
02559   *         ADC1R        ADC1EEV1        LL_HRTIM_ConfigADCTrig\n
02560   *         ADC1R        ADC1EEV2        LL_HRTIM_ConfigADCTrig\n
02561   *         ADC1R        ADC1EEV3        LL_HRTIM_ConfigADCTrig\n
02562   *         ADC1R        ADC1EEV4        LL_HRTIM_ConfigADCTrig\n
02563   *         ADC1R        ADC1EEV5        LL_HRTIM_ConfigADCTrig\n
02564   *         ADC1R        ADC1TFC2        LL_HRTIM_ConfigADCTrig\n
02565   *         ADC1R        ADC1TAC3        LL_HRTIM_ConfigADCTrig\n
02566   *         ADC1R        ADC1TAC4        LL_HRTIM_ConfigADCTrig\n
02567   *         ADC1R        ADC1TAPER       LL_HRTIM_ConfigADCTrig\n
02568   *         ADC1R        ADC1TARST       LL_HRTIM_ConfigADCTrig\n
02569   *         ADC1R        ADC1TFC3        LL_HRTIM_ConfigADCTrig\n
02570   *         ADC1R        ADC1TBC3        LL_HRTIM_ConfigADCTrig\n
02571   *         ADC1R        ADC1TBC4        LL_HRTIM_ConfigADCTrig\n
02572   *         ADC1R        ADC1TBPER       LL_HRTIM_ConfigADCTrig\n
02573   *         ADC1R        ADC1TBRST       LL_HRTIM_ConfigADCTrig\n
02574   *         ADC1R        ADC1TFC4        LL_HRTIM_ConfigADCTrig\n
02575   *         ADC1R        ADC1TCC3        LL_HRTIM_ConfigADCTrig\n
02576   *         ADC1R        ADC1TCC4        LL_HRTIM_ConfigADCTrig\n
02577   *         ADC1R        ADC1TCPER       LL_HRTIM_ConfigADCTrig\n
02578   *         ADC1R        ADC1TFPER       LL_HRTIM_ConfigADCTrig\n
02579   *         ADC1R        ADC1TDC3        LL_HRTIM_ConfigADCTrig\n
02580   *         ADC1R        ADC1TDC4        LL_HRTIM_ConfigADCTrig\n
02581   *         ADC1R        ADC1TDPER       LL_HRTIM_ConfigADCTrig\n
02582   *         ADC1R        ADC1TFRST       LL_HRTIM_ConfigADCTrig\n
02583   *         ADC1R        ADC1TEC3        LL_HRTIM_ConfigADCTrig\n
02584   *         ADC1R        ADC1TEC4        LL_HRTIM_ConfigADCTrig\n
02585   *         ADC1R        ADC1TEPER       LL_HRTIM_ConfigADCTrig\n
02586   *         ADC2R        ADC2MC1         LL_HRTIM_ConfigADCTrig\n
02587   *         ADC2R        ADC2MC2         LL_HRTIM_ConfigADCTrig\n
02588   *         ADC2R        ADC2MC3         LL_HRTIM_ConfigADCTrig\n
02589   *         ADC2R        ADC2MC4         LL_HRTIM_ConfigADCTrig\n
02590   *         ADC2R        ADC2MPER        LL_HRTIM_ConfigADCTrig\n
02591   *         ADC2R        ADC2EEV6        LL_HRTIM_ConfigADCTrig\n
02592   *         ADC2R        ADC2EEV7        LL_HRTIM_ConfigADCTrig\n
02593   *         ADC2R        ADC2EEV8        LL_HRTIM_ConfigADCTrig\n
02594   *         ADC2R        ADC2EEV9        LL_HRTIM_ConfigADCTrig\n
02595   *         ADC2R        ADC2EEV10       LL_HRTIM_ConfigADCTrig\n
02596   *         ADC2R        ADC2TAC2        LL_HRTIM_ConfigADCTrig\n
02597   *         ADC2R        ADC2TFC2        LL_HRTIM_ConfigADCTrig\n
02598   *         ADC2R        ADC2TAC4        LL_HRTIM_ConfigADCTrig\n
02599   *         ADC2R        ADC2TAPER       LL_HRTIM_ConfigADCTrig\n
02600   *         ADC2R        ADC2TBC2        LL_HRTIM_ConfigADCTrig\n
02601   *         ADC2R        ADC2TFC3        LL_HRTIM_ConfigADCTrig\n
02602   *         ADC2R        ADC2TBC4        LL_HRTIM_ConfigADCTrig\n
02603   *         ADC2R        ADC2TBPER       LL_HRTIM_ConfigADCTrig\n
02604   *         ADC2R        ADC2TCC2        LL_HRTIM_ConfigADCTrig\n
02605   *         ADC2R        ADC2TFC4        LL_HRTIM_ConfigADCTrig\n
02606   *         ADC2R        ADC2TCC4        LL_HRTIM_ConfigADCTrig\n
02607   *         ADC2R        ADC2TCPER       LL_HRTIM_ConfigADCTrig\n
02608   *         ADC2R        ADC2TCRST       LL_HRTIM_ConfigADCTrig\n
02609   *         ADC2R        ADC2TDC2        LL_HRTIM_ConfigADCTrig\n
02610   *         ADC2R        ADC2TFPER       LL_HRTIM_ConfigADCTrig\n
02611   *         ADC2R        ADC2TDC4        LL_HRTIM_ConfigADCTrig\n
02612   *         ADC2R        ADC2TDPER       LL_HRTIM_ConfigADCTrig\n
02613   *         ADC2R        ADC2TDRST       LL_HRTIM_ConfigADCTrig\n
02614   *         ADC2R        ADC2TEC2        LL_HRTIM_ConfigADCTrig\n
02615   *         ADC2R        ADC2TEC3        LL_HRTIM_ConfigADCTrig\n
02616   *         ADC2R        ADC2TEC4        LL_HRTIM_ConfigADCTrig\n
02617   *         ADC2R        ADC2TERST       LL_HRTIM_ConfigADCTrig\n
02618   *         ADC3R        ADC3MC1         LL_HRTIM_ConfigADCTrig\n
02619   *         ADC3R        ADC3MC2         LL_HRTIM_ConfigADCTrig\n
02620   *         ADC3R        ADC3MC3         LL_HRTIM_ConfigADCTrig\n
02621   *         ADC3R        ADC3MC4         LL_HRTIM_ConfigADCTrig\n
02622   *         ADC3R        ADC3MPER        LL_HRTIM_ConfigADCTrig\n
02623   *         ADC3R        ADC3EEV1        LL_HRTIM_ConfigADCTrig\n
02624   *         ADC3R        ADC3EEV2        LL_HRTIM_ConfigADCTrig\n
02625   *         ADC3R        ADC3EEV3        LL_HRTIM_ConfigADCTrig\n
02626   *         ADC3R        ADC3EEV4        LL_HRTIM_ConfigADCTrig\n
02627   *         ADC3R        ADC3EEV5        LL_HRTIM_ConfigADCTrig\n
02628   *         ADC3R        ADC3TFC2        LL_HRTIM_ConfigADCTrig\n
02629   *         ADC3R        ADC3TAC3        LL_HRTIM_ConfigADCTrig\n
02630   *         ADC3R        ADC3TAC4        LL_HRTIM_ConfigADCTrig\n
02631   *         ADC3R        ADC3TAPER       LL_HRTIM_ConfigADCTrig\n
02632   *         ADC3R        ADC3TARST       LL_HRTIM_ConfigADCTrig\n
02633   *         ADC3R        ADC3TFC3        LL_HRTIM_ConfigADCTrig\n
02634   *         ADC3R        ADC3TBC3        LL_HRTIM_ConfigADCTrig\n
02635   *         ADC3R        ADC3TBC4        LL_HRTIM_ConfigADCTrig\n
02636   *         ADC3R        ADC3TBPER       LL_HRTIM_ConfigADCTrig\n
02637   *         ADC3R        ADC3TBRST       LL_HRTIM_ConfigADCTrig\n
02638   *         ADC3R        ADC3TFC4        LL_HRTIM_ConfigADCTrig\n
02639   *         ADC3R        ADC3TCC3        LL_HRTIM_ConfigADCTrig\n
02640   *         ADC3R        ADC3TCC4        LL_HRTIM_ConfigADCTrig\n
02641   *         ADC3R        ADC3TCPER       LL_HRTIM_ConfigADCTrig\n
02642   *         ADC3R        ADC3TFPER       LL_HRTIM_ConfigADCTrig\n
02643   *         ADC3R        ADC3TDC3        LL_HRTIM_ConfigADCTrig\n
02644   *         ADC3R        ADC3TDC4        LL_HRTIM_ConfigADCTrig\n
02645   *         ADC3R        ADC3TDPER       LL_HRTIM_ConfigADCTrig\n
02646   *         ADC3R        ADC3TFRST       LL_HRTIM_ConfigADCTrig\n
02647   *         ADC3R        ADC3TEC3        LL_HRTIM_ConfigADCTrig\n
02648   *         ADC3R        ADC3TEC4        LL_HRTIM_ConfigADCTrig\n
02649   *         ADC3R        ADC3TEPER       LL_HRTIM_ConfigADCTrig\n
02650   *         ADC4R        ADC4MC1         LL_HRTIM_ConfigADCTrig\n
02651   *         ADC4R        ADC4MC2         LL_HRTIM_ConfigADCTrig\n
02652   *         ADC4R        ADC4MC3         LL_HRTIM_ConfigADCTrig\n
02653   *         ADC4R        ADC4MC4         LL_HRTIM_ConfigADCTrig\n
02654   *         ADC4R        ADC4MPER        LL_HRTIM_ConfigADCTrig\n
02655   *         ADC4R        ADC4EEV6        LL_HRTIM_ConfigADCTrig\n
02656   *         ADC4R        ADC4EEV7        LL_HRTIM_ConfigADCTrig\n
02657   *         ADC4R        ADC4EEV8        LL_HRTIM_ConfigADCTrig\n
02658   *         ADC4R        ADC4EEV9        LL_HRTIM_ConfigADCTrig\n
02659   *         ADC4R        ADC4EEV10       LL_HRTIM_ConfigADCTrig\n
02660   *         ADC4R        ADC4TAC2        LL_HRTIM_ConfigADCTrig\n
02661   *         ADC4R        ADC4TFC2        LL_HRTIM_ConfigADCTrig\n
02662   *         ADC4R        ADC4TAC4        LL_HRTIM_ConfigADCTrig\n
02663   *         ADC4R        ADC4TAPER       LL_HRTIM_ConfigADCTrig\n
02664   *         ADC4R        ADC4TBC2        LL_HRTIM_ConfigADCTrig\n
02665   *         ADC4R        ADC4TFC3        LL_HRTIM_ConfigADCTrig\n
02666   *         ADC4R        ADC4TBC4        LL_HRTIM_ConfigADCTrig\n
02667   *         ADC4R        ADC4TBPER       LL_HRTIM_ConfigADCTrig\n
02668   *         ADC4R        ADC4TCC2        LL_HRTIM_ConfigADCTrig\n
02669   *         ADC4R        ADC4TFC4        LL_HRTIM_ConfigADCTrig\n
02670   *         ADC4R        ADC4TCC4        LL_HRTIM_ConfigADCTrig\n
02671   *         ADC4R        ADC4TCPER       LL_HRTIM_ConfigADCTrig\n
02672   *         ADC4R        ADC4TCRST       LL_HRTIM_ConfigADCTrig\n
02673   *         ADC4R        ADC4TDC2        LL_HRTIM_ConfigADCTrig\n
02674   *         ADC4R        ADC4TFPER       LL_HRTIM_ConfigADCTrig\n
02675   *         ADC4R        ADC4TDC4        LL_HRTIM_ConfigADCTrig\n
02676   *         ADC4R        ADC4TDPER       LL_HRTIM_ConfigADCTrig\n
02677   *         ADC4R        ADC4TDRST       LL_HRTIM_ConfigADCTrig\n
02678   *         ADC4R        ADC4TEC2        LL_HRTIM_ConfigADCTrig\n
02679   *         ADC4R        ADC4TEC3        LL_HRTIM_ConfigADCTrig\n
02680   *         ADC4R        ADC4TEC4        LL_HRTIM_ConfigADCTrig\n
02681   *         ADC4R        ADC4TERST       LL_HRTIM_ConfigADCTrig
02682   * @param  HRTIMx High Resolution Timer instance
02683   * @param  ADCTrig This parameter can be one of the following values:
02684   *         @arg @ref LL_HRTIM_ADCTRIG_1
02685   *         @arg @ref LL_HRTIM_ADCTRIG_2
02686   *         @arg @ref LL_HRTIM_ADCTRIG_3
02687   *         @arg @ref LL_HRTIM_ADCTRIG_4
02688   * @param  Update This parameter can be one of the following values:
02689   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02690   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02691   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02692   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02693   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02694   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02695   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
02696   * @param  Src This parameter can be a combination of the following values:
02697   *
02698   *         For ADC trigger 1 and ADC trigger 3:
02699   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
02700   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
02701   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
02702   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
02703   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
02704   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
02705   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
02706   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
02707   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
02708   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
02709   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
02710   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
02711   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
02712   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
02713   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
02714   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
02715   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
02716   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
02717   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
02718   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
02719   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
02720   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
02721   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
02722   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
02723   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
02724   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
02725   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
02726   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
02727   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
02728   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
02729   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
02730   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
02731   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
02732   *
02733   *         For ADC trigger 2 and ADC trigger 4:
02734   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
02735   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
02736   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
02737   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
02738   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
02739   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
02740   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
02741   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
02742   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
02743   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
02744   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
02745   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
02746   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
02747   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
02748   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
02749   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
02750   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
02751   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
02752   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
02753   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
02754   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
02755   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
02756   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
02757   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
02758   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
02759   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
02760   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
02761   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
02762   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
02763   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
02764   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
02765   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
02766   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
02767   *
02768   *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
02769   *         can be one of the following values:
02770   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
02771   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
02772   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
02773   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
02774   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
02775   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
02776   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
02777   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
02778   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
02779   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
02780   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
02781   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
02782   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
02783   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
02784   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
02785   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
02786   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
02787   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
02788   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
02789   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
02790   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
02791   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
02792   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
02793   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
02794   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
02795   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
02796   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
02797   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
02798   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
02799   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
02800   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
02801   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
02802   *
02803   *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
02804   *         can be one of the following values:
02805   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
02806   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
02807   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
02808   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
02809   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
02810   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
02811   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
02812   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
02813   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
02814   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
02815   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
02816   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
02817   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
02818   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
02819   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
02820   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
02821   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
02822   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
02823   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
02824   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
02825   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
02826   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
02827   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
02828   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
02829   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
02830   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
02831   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
02832   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
02833   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
02834   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
02835   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
02836   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
02837   * @retval None
02838   */
02839 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
02840 {
02841   __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
02842                                                                 REG_OFFSET_TAB_ADCUR[ADCTrig]));
02843   __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
02844                                                                 REG_OFFSET_TAB_ADCER[ADCTrig]));
02845   MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
02846   MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
02847 }
02848
02849 /**
02850   * @brief  Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
02851   * @rmtoll CR1          ADC1USRC         LL_HRTIM_SetADCTrigUpdate\n
02852   *         CR1          ADC2USRC         LL_HRTIM_SetADCTrigUpdate\n
02853   *         CR1          ADC3USRC         LL_HRTIM_SetADCTrigUpdate\n
02854   *         CR1          ADC4USRC         LL_HRTIM_SetADCTrigUpdate\n
02855   *         ADCUR        ADC5USRC         LL_HRTIM_SetADCTrigUpdate\n
02856   *         ADCUR        ADC6USRC         LL_HRTIM_SetADCTrigUpdate\n
02857   *         ADCUR        ADC7USRC         LL_HRTIM_SetADCTrigUpdate\n
02858   *         ADCUR        ADC8USRC         LL_HRTIM_SetADCTrigUpdate\n
02859   *         ADCUR        ADC9USRC         LL_HRTIM_SetADCTrigUpdate\n
02860   *         ADCUR        ADC10USRC        LL_HRTIM_SetADCTrigUpdate
02861   * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
02862   *       registers are not preloaded either: a write access will result in an
02863   *       immediate update of the trigger source.
02864   * @param  HRTIMx High Resolution Timer instance
02865   * @param  ADCTrig This parameter can be one of the following values:
02866   *         @arg @ref LL_HRTIM_ADCTRIG_1
02867   *         @arg @ref LL_HRTIM_ADCTRIG_2
02868   *         @arg @ref LL_HRTIM_ADCTRIG_3
02869   *         @arg @ref LL_HRTIM_ADCTRIG_4
02870   *         @arg @ref LL_HRTIM_ADCTRIG_5
02871   *         @arg @ref LL_HRTIM_ADCTRIG_6
02872   *         @arg @ref LL_HRTIM_ADCTRIG_7
02873   *         @arg @ref LL_HRTIM_ADCTRIG_8
02874   *         @arg @ref LL_HRTIM_ADCTRIG_9
02875   *         @arg @ref LL_HRTIM_ADCTRIG_10
02876   * @param  Update This parameter can be one of the following values:
02877   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02878   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02879   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02880   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02881   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02882   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02883   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
02884   * @retval None
02885   */
02886 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
02887 {
02888   __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
02889                                                               REG_OFFSET_TAB_ADCUR[ADCTrig]));
02890   MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
02891 }
02892
02893 /**
02894   * @brief  Get the source timer triggering the update of the HRTIM_ADCxR register.
02895   * @rmtoll CR1          ADC1USRC        LL_HRTIM_GetADCTrigUpdate\n
02896   *         CR1          ADC2USRC        LL_HRTIM_GetADCTrigUpdate\n
02897   *         CR1          ADC3USRC        LL_HRTIM_GetADCTrigUpdate\n
02898   *         CR1          ADC4USRC        LL_HRTIM_GetADCTrigUpdate\n
02899   *         ADCUR        ADC5USRC        LL_HRTIM_GetADCTrigUpdate\n
02900   *         ADCUR        ADC6USRC        LL_HRTIM_GetADCTrigUpdate\n
02901   *         ADCUR        ADC7USRC        LL_HRTIM_GetADCTrigUpdate\n
02902   *         ADCUR        ADC8USRC        LL_HRTIM_GetADCTrigUpdate\n
02903   *         ADCUR        ADC9USRC        LL_HRTIM_GetADCTrigUpdate\n
02904   *         ADCUR        ADC10USRC       LL_HRTIM_GetADCTrigUpdate
02905   * @param  HRTIMx High Resolution Timer instance
02906   * @param  ADCTrig This parameter can be one of the following values:
02907   *         @arg @ref LL_HRTIM_ADCTRIG_1
02908   *         @arg @ref LL_HRTIM_ADCTRIG_2
02909   *         @arg @ref LL_HRTIM_ADCTRIG_3
02910   *         @arg @ref LL_HRTIM_ADCTRIG_4
02911   *         @arg @ref LL_HRTIM_ADCTRIG_5
02912   *         @arg @ref LL_HRTIM_ADCTRIG_6
02913   *         @arg @ref LL_HRTIM_ADCTRIG_7
02914   *         @arg @ref LL_HRTIM_ADCTRIG_8
02915   *         @arg @ref LL_HRTIM_ADCTRIG_9
02916   *         @arg @ref LL_HRTIM_ADCTRIG_10
02917   * @retval Update Returned value can be one of the following values:
02918   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
02919   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
02920   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
02921   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
02922   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
02923   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
02924   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
02925   */
02926 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
02927 {
02928   const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
02929                                                                     REG_OFFSET_TAB_ADCUR[ADCTrig]));
02930   return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
02931 }
02932
02933 /**
02934   * @brief  Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
02935   * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_SetADCTrigSrc\n
02936   *         ADC1R        ADC1MC2         LL_HRTIM_SetADCTrigSrc\n
02937   *         ADC1R        ADC1MC3         LL_HRTIM_SetADCTrigSrc\n
02938   *         ADC1R        ADC1MC4         LL_HRTIM_SetADCTrigSrc\n
02939   *         ADC1R        ADC1MPER        LL_HRTIM_SetADCTrigSrc\n
02940   *         ADC1R        ADC1EEV1        LL_HRTIM_SetADCTrigSrc\n
02941   *         ADC1R        ADC1EEV2        LL_HRTIM_SetADCTrigSrc\n
02942   *         ADC1R        ADC1EEV3        LL_HRTIM_SetADCTrigSrc\n
02943   *         ADC1R        ADC1EEV4        LL_HRTIM_SetADCTrigSrc\n
02944   *         ADC1R        ADC1EEV5        LL_HRTIM_SetADCTrigSrc\n
02945   *         ADC1R        ADC1TFC2        LL_HRTIM_SetADCTrigSrc\n
02946   *         ADC1R        ADC1TAC3        LL_HRTIM_SetADCTrigSrc\n
02947   *         ADC1R        ADC1TAC4        LL_HRTIM_SetADCTrigSrc\n
02948   *         ADC1R        ADC1TAPER       LL_HRTIM_SetADCTrigSrc\n
02949   *         ADC1R        ADC1TARST       LL_HRTIM_SetADCTrigSrc\n
02950   *         ADC1R        ADC1TFC3        LL_HRTIM_SetADCTrigSrc\n
02951   *         ADC1R        ADC1TBC3        LL_HRTIM_SetADCTrigSrc\n
02952   *         ADC1R        ADC1TBC4        LL_HRTIM_SetADCTrigSrc\n
02953   *         ADC1R        ADC1TBPER       LL_HRTIM_SetADCTrigSrc\n
02954   *         ADC1R        ADC1TBRST       LL_HRTIM_SetADCTrigSrc\n
02955   *         ADC1R        ADC1TFC4        LL_HRTIM_SetADCTrigSrc\n
02956   *         ADC1R        ADC1TCC3        LL_HRTIM_SetADCTrigSrc\n
02957   *         ADC1R        ADC1TCC4        LL_HRTIM_SetADCTrigSrc\n
02958   *         ADC1R        ADC1TCPER       LL_HRTIM_SetADCTrigSrc\n
02959   *         ADC1R        ADC1TFPER       LL_HRTIM_SetADCTrigSrc\n
02960   *         ADC1R        ADC1TDC3        LL_HRTIM_SetADCTrigSrc\n
02961   *         ADC1R        ADC1TDC4        LL_HRTIM_SetADCTrigSrc\n
02962   *         ADC1R        ADC1TDPER       LL_HRTIM_SetADCTrigSrc\n
02963   *         ADC1R        ADC1TFRST       LL_HRTIM_SetADCTrigSrc\n
02964   *         ADC1R        ADC1TEC3        LL_HRTIM_SetADCTrigSrc\n
02965   *         ADC1R        ADC1TEC4        LL_HRTIM_SetADCTrigSrc\n
02966   *         ADC1R        ADC1TEPER       LL_HRTIM_SetADCTrigSrc\n
02967   *         ADC2R        ADC2MC1         LL_HRTIM_SetADCTrigSrc\n
02968   *         ADC2R        ADC2MC2         LL_HRTIM_SetADCTrigSrc\n
02969   *         ADC2R        ADC2MC3         LL_HRTIM_SetADCTrigSrc\n
02970   *         ADC2R        ADC2MC4         LL_HRTIM_SetADCTrigSrc\n
02971   *         ADC2R        ADC2MPER        LL_HRTIM_SetADCTrigSrc\n
02972   *         ADC2R        ADC2EEV6        LL_HRTIM_SetADCTrigSrc\n
02973   *         ADC2R        ADC2EEV7        LL_HRTIM_SetADCTrigSrc\n
02974   *         ADC2R        ADC2EEV8        LL_HRTIM_SetADCTrigSrc\n
02975   *         ADC2R        ADC2EEV9        LL_HRTIM_SetADCTrigSrc\n
02976   *         ADC2R        ADC2EEV10       LL_HRTIM_SetADCTrigSrc\n
02977   *         ADC2R        ADC2TAC2        LL_HRTIM_SetADCTrigSrc\n
02978   *         ADC2R        ADC2TFC2        LL_HRTIM_SetADCTrigSrc\n
02979   *         ADC2R        ADC2TAC4        LL_HRTIM_SetADCTrigSrc\n
02980   *         ADC2R        ADC2TAPER       LL_HRTIM_SetADCTrigSrc\n
02981   *         ADC2R        ADC2TBC2        LL_HRTIM_SetADCTrigSrc\n
02982   *         ADC2R        ADC2TFC3        LL_HRTIM_SetADCTrigSrc\n
02983   *         ADC2R        ADC2TBC4        LL_HRTIM_SetADCTrigSrc\n
02984   *         ADC2R        ADC2TBPER       LL_HRTIM_SetADCTrigSrc\n
02985   *         ADC2R        ADC2TCC2        LL_HRTIM_SetADCTrigSrc\n
02986   *         ADC2R        ADC2TFC4        LL_HRTIM_SetADCTrigSrc\n
02987   *         ADC2R        ADC2TCC4        LL_HRTIM_SetADCTrigSrc\n
02988   *         ADC2R        ADC2TCPER       LL_HRTIM_SetADCTrigSrc\n
02989   *         ADC2R        ADC2TCRST       LL_HRTIM_SetADCTrigSrc\n
02990   *         ADC2R        ADC2TDC2        LL_HRTIM_SetADCTrigSrc\n
02991   *         ADC2R        ADC2TFPER       LL_HRTIM_SetADCTrigSrc\n
02992   *         ADC2R        ADC2TDC4        LL_HRTIM_SetADCTrigSrc\n
02993   *         ADC2R        ADC2TDPER       LL_HRTIM_SetADCTrigSrc\n
02994   *         ADC2R        ADC2TDRST       LL_HRTIM_SetADCTrigSrc\n
02995   *         ADC2R        ADC2TEC2        LL_HRTIM_SetADCTrigSrc\n
02996   *         ADC2R        ADC2TEC3        LL_HRTIM_SetADCTrigSrc\n
02997   *         ADC2R        ADC2TEC4        LL_HRTIM_SetADCTrigSrc\n
02998   *         ADC2R        ADC2TERST       LL_HRTIM_SetADCTrigSrc\n
02999   *         ADC3R        ADC3MC1         LL_HRTIM_SetADCTrigSrc\n
03000   *         ADC3R        ADC3MC2         LL_HRTIM_SetADCTrigSrc\n
03001   *         ADC3R        ADC3MC3         LL_HRTIM_SetADCTrigSrc\n
03002   *         ADC3R        ADC3MC4         LL_HRTIM_SetADCTrigSrc\n
03003   *         ADC3R        ADC3MPER        LL_HRTIM_SetADCTrigSrc\n
03004   *         ADC3R        ADC3EEV1        LL_HRTIM_SetADCTrigSrc\n
03005   *         ADC3R        ADC3EEV2        LL_HRTIM_SetADCTrigSrc\n
03006   *         ADC3R        ADC3EEV3        LL_HRTIM_SetADCTrigSrc\n
03007   *         ADC3R        ADC3EEV4        LL_HRTIM_SetADCTrigSrc\n
03008   *         ADC3R        ADC3EEV5        LL_HRTIM_SetADCTrigSrc\n
03009   *         ADC3R        ADC3TFC2        LL_HRTIM_SetADCTrigSrc\n
03010   *         ADC3R        ADC3TAC3        LL_HRTIM_SetADCTrigSrc\n
03011   *         ADC3R        ADC3TAC4        LL_HRTIM_SetADCTrigSrc\n
03012   *         ADC3R        ADC3TAPER       LL_HRTIM_SetADCTrigSrc\n
03013   *         ADC3R        ADC3TARST       LL_HRTIM_SetADCTrigSrc\n
03014   *         ADC3R        ADC3TFC3        LL_HRTIM_SetADCTrigSrc\n
03015   *         ADC3R        ADC3TBC3        LL_HRTIM_SetADCTrigSrc\n
03016   *         ADC3R        ADC3TBC4        LL_HRTIM_SetADCTrigSrc\n
03017   *         ADC3R        ADC3TBPER       LL_HRTIM_SetADCTrigSrc\n
03018   *         ADC3R        ADC3TBRST       LL_HRTIM_SetADCTrigSrc\n
03019   *         ADC3R        ADC3TFC4        LL_HRTIM_SetADCTrigSrc\n
03020   *         ADC3R        ADC3TCC3        LL_HRTIM_SetADCTrigSrc\n
03021   *         ADC3R        ADC3TCC4        LL_HRTIM_SetADCTrigSrc\n
03022   *         ADC3R        ADC3TCPER       LL_HRTIM_SetADCTrigSrc\n
03023   *         ADC3R        ADC3TFPER       LL_HRTIM_SetADCTrigSrc\n
03024   *         ADC3R        ADC3TDC3        LL_HRTIM_SetADCTrigSrc\n
03025   *         ADC3R        ADC3TDC4        LL_HRTIM_SetADCTrigSrc\n
03026   *         ADC3R        ADC3TDPER       LL_HRTIM_SetADCTrigSrc\n
03027   *         ADC3R        ADC3TFRST       LL_HRTIM_SetADCTrigSrc\n
03028   *         ADC3R        ADC3TEC3        LL_HRTIM_SetADCTrigSrc\n
03029   *         ADC3R        ADC3TEC4        LL_HRTIM_SetADCTrigSrc\n
03030   *         ADC3R        ADC3TEPER       LL_HRTIM_SetADCTrigSrc\n
03031   *         ADC4R        ADC4MC1         LL_HRTIM_SetADCTrigSrc\n
03032   *         ADC4R        ADC4MC2         LL_HRTIM_SetADCTrigSrc\n
03033   *         ADC4R        ADC4MC3         LL_HRTIM_SetADCTrigSrc\n
03034   *         ADC4R        ADC4MC4         LL_HRTIM_SetADCTrigSrc\n
03035   *         ADC4R        ADC4MPER        LL_HRTIM_SetADCTrigSrc\n
03036   *         ADC4R        ADC4EEV6        LL_HRTIM_SetADCTrigSrc\n
03037   *         ADC4R        ADC4EEV7        LL_HRTIM_SetADCTrigSrc\n
03038   *         ADC4R        ADC4EEV8        LL_HRTIM_SetADCTrigSrc\n
03039   *         ADC4R        ADC4EEV9        LL_HRTIM_SetADCTrigSrc\n
03040   *         ADC4R        ADC4EEV10       LL_HRTIM_SetADCTrigSrc\n
03041   *         ADC4R        ADC4TAC2        LL_HRTIM_SetADCTrigSrc\n
03042   *         ADC4R        ADC4TFC2        LL_HRTIM_SetADCTrigSrc\n
03043   *         ADC4R        ADC4TAC4        LL_HRTIM_SetADCTrigSrc\n
03044   *         ADC4R        ADC4TAPER       LL_HRTIM_SetADCTrigSrc\n
03045   *         ADC4R        ADC4TBC2        LL_HRTIM_SetADCTrigSrc\n
03046   *         ADC4R        ADC4TFC3        LL_HRTIM_SetADCTrigSrc\n
03047   *         ADC4R        ADC4TBC4        LL_HRTIM_SetADCTrigSrc\n
03048   *         ADC4R        ADC4TBPER       LL_HRTIM_SetADCTrigSrc\n
03049   *         ADC4R        ADC4TCC2        LL_HRTIM_SetADCTrigSrc\n
03050   *         ADC4R        ADC4TFC4        LL_HRTIM_SetADCTrigSrc\n
03051   *         ADC4R        ADC4TCC4        LL_HRTIM_SetADCTrigSrc\n
03052   *         ADC4R        ADC4TCPER       LL_HRTIM_SetADCTrigSrc\n
03053   *         ADC4R        ADC4TCRST       LL_HRTIM_SetADCTrigSrc\n
03054   *         ADC4R        ADC4TDC2        LL_HRTIM_SetADCTrigSrc\n
03055   *         ADC4R        ADC4TFPER       LL_HRTIM_SetADCTrigSrc\n
03056   *         ADC4R        ADC4TDC4        LL_HRTIM_SetADCTrigSrc\n
03057   *         ADC4R        ADC4TDPER       LL_HRTIM_SetADCTrigSrc\n
03058   *         ADC4R        ADC4TDRST       LL_HRTIM_SetADCTrigSrc\n
03059   *         ADC4R        ADC4TEC2        LL_HRTIM_SetADCTrigSrc\n
03060   *         ADC4R        ADC4TEC3        LL_HRTIM_SetADCTrigSrc\n
03061   *         ADC4R        ADC4TEC4        LL_HRTIM_SetADCTrigSrc\n
03062   *         ADC4R        ADC4TERST       LL_HRTIM_SetADCTrigSrc\n
03063   *         ADCER        ADC5TRG         LL_HRTIM_SetADCTrigSrc\n
03064   *         ADCER        ADC6TRG         LL_HRTIM_SetADCTrigSrc\n
03065   *         ADCER        ADC7TRG         LL_HRTIM_SetADCTrigSrc\n
03066   *         ADCER        ADC8TRG         LL_HRTIM_SetADCTrigSrc\n
03067   *         ADCER        ADC9TRG         LL_HRTIM_SetADCTrigSrc\n
03068   *         ADCER        ADC10TRG        LL_HRTIM_SetADCTrigSrc
03069   * @param  HRTIMx High Resolution Timer instance
03070   * @param  ADCTrig This parameter can be one of the following values:
03071   *         @arg @ref LL_HRTIM_ADCTRIG_1
03072   *         @arg @ref LL_HRTIM_ADCTRIG_2
03073   *         @arg @ref LL_HRTIM_ADCTRIG_3
03074   *         @arg @ref LL_HRTIM_ADCTRIG_4
03075   *         @arg @ref LL_HRTIM_ADCTRIG_5
03076   *         @arg @ref LL_HRTIM_ADCTRIG_6
03077   *         @arg @ref LL_HRTIM_ADCTRIG_7
03078   *         @arg @ref LL_HRTIM_ADCTRIG_8
03079   *         @arg @ref LL_HRTIM_ADCTRIG_9
03080   *         @arg @ref LL_HRTIM_ADCTRIG_10
03081   * @param  Src
03082   *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
03083   *         combination of the following values:
03084   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
03085   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
03086   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
03087   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
03088   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
03089   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
03090   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
03091   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
03092   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
03093   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
03094   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
03095   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
03096   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
03097   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
03098   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
03099   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
03100   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
03101   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
03102   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
03103   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
03104   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
03105   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
03106   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
03107   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
03108   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
03109   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
03110   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
03111   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
03112   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
03113   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
03114   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
03115   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
03116   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
03117   *
03118   *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
03119   *         combination of the following values:
03120   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
03121   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
03122   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
03123   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
03124   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
03125   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
03126   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
03127   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
03128   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
03129   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
03130   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
03131   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
03132   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
03133   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
03134   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
03135   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
03136   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
03137   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
03138   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
03139   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
03140   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
03141   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
03142   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
03143   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
03144   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
03145   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
03146   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
03147   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
03148   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
03149   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
03150   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
03151   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
03152   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
03153   *
03154   *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
03155   *         can be one of the following values:
03156   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
03157   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
03158   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
03159   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
03160   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
03161   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
03162   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
03163   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
03164   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
03165   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
03166   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
03167   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
03168   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
03169   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
03170   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
03171   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
03172   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
03173   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
03174   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
03175   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
03176   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
03177   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
03178   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
03179   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
03180   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
03181   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
03182   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
03183   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
03184   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
03185   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
03186   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
03187   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
03188   *
03189   *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
03190   *         can be one of the following values:
03191   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
03192   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
03193   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
03194   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
03195   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
03196   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
03197   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
03198   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
03199   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
03200   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
03201   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
03202   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
03203   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
03204   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
03205   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
03206   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
03207   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
03208   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
03209   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
03210   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
03211   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
03212   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
03213   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
03214   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
03215   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
03216   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
03217   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
03218   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
03219   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
03220   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
03221   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
03222   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
03223   * @retval None
03224   */
03225 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
03226 {
03227   __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
03228                                                               REG_OFFSET_TAB_ADCER[ADCTrig]));
03229   MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
03230 }
03231
03232 /**
03233   * @brief  Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
03234   * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_GetADCTrigSrc\n
03235   *         ADC1R        ADC1MC2         LL_HRTIM_GetADCTrigSrc\n
03236   *         ADC1R        ADC1MC3         LL_HRTIM_GetADCTrigSrc\n
03237   *         ADC1R        ADC1MC4         LL_HRTIM_GetADCTrigSrc\n
03238   *         ADC1R        ADC1MPER        LL_HRTIM_GetADCTrigSrc\n
03239   *         ADC1R        ADC1EEV1        LL_HRTIM_GetADCTrigSrc\n
03240   *         ADC1R        ADC1EEV2        LL_HRTIM_GetADCTrigSrc\n
03241   *         ADC1R        ADC1EEV3        LL_HRTIM_GetADCTrigSrc\n
03242   *         ADC1R        ADC1EEV4        LL_HRTIM_GetADCTrigSrc\n
03243   *         ADC1R        ADC1EEV5        LL_HRTIM_GetADCTrigSrc\n
03244   *         ADC1R        ADC1TFC2        LL_HRTIM_GetADCTrigSrc\n
03245   *         ADC1R        ADC1TAC3        LL_HRTIM_GetADCTrigSrc\n
03246   *         ADC1R        ADC1TAC4        LL_HRTIM_GetADCTrigSrc\n
03247   *         ADC1R        ADC1TAPER       LL_HRTIM_GetADCTrigSrc\n
03248   *         ADC1R        ADC1TARST       LL_HRTIM_GetADCTrigSrc\n
03249   *         ADC1R        ADC1TFC3        LL_HRTIM_GetADCTrigSrc\n
03250   *         ADC1R        ADC1TBC3        LL_HRTIM_GetADCTrigSrc\n
03251   *         ADC1R        ADC1TBC4        LL_HRTIM_GetADCTrigSrc\n
03252   *         ADC1R        ADC1TBPER       LL_HRTIM_GetADCTrigSrc\n
03253   *         ADC1R        ADC1TBRST       LL_HRTIM_GetADCTrigSrc\n
03254   *         ADC1R        ADC1TFC4        LL_HRTIM_GetADCTrigSrc\n
03255   *         ADC1R        ADC1TCC3        LL_HRTIM_GetADCTrigSrc\n
03256   *         ADC1R        ADC1TCC4        LL_HRTIM_GetADCTrigSrc\n
03257   *         ADC1R        ADC1TCPER       LL_HRTIM_GetADCTrigSrc\n
03258   *         ADC1R        ADC1TFPER       LL_HRTIM_GetADCTrigSrc\n
03259   *         ADC1R        ADC1TDC3        LL_HRTIM_GetADCTrigSrc\n
03260   *         ADC1R        ADC1TDC4        LL_HRTIM_GetADCTrigSrc\n
03261   *         ADC1R        ADC1TDPER       LL_HRTIM_GetADCTrigSrc\n
03262   *         ADC1R        ADC1TFRST       LL_HRTIM_GetADCTrigSrc\n
03263   *         ADC1R        ADC1TEC3        LL_HRTIM_GetADCTrigSrc\n
03264   *         ADC1R        ADC1TEC4        LL_HRTIM_GetADCTrigSrc\n
03265   *         ADC1R        ADC1TEPER       LL_HRTIM_GetADCTrigSrc\n
03266   *         ADC2R        ADC2MC1         LL_HRTIM_GetADCTrigSrc\n
03267   *         ADC2R        ADC2MC2         LL_HRTIM_GetADCTrigSrc\n
03268   *         ADC2R        ADC2MC3         LL_HRTIM_GetADCTrigSrc\n
03269   *         ADC2R        ADC2MC4         LL_HRTIM_GetADCTrigSrc\n
03270   *         ADC2R        ADC2MPER        LL_HRTIM_GetADCTrigSrc\n
03271   *         ADC2R        ADC2EEV6        LL_HRTIM_GetADCTrigSrc\n
03272   *         ADC2R        ADC2EEV7        LL_HRTIM_GetADCTrigSrc\n
03273   *         ADC2R        ADC2EEV8        LL_HRTIM_GetADCTrigSrc\n
03274   *         ADC2R        ADC2EEV9        LL_HRTIM_GetADCTrigSrc\n
03275   *         ADC2R        ADC2EEV10       LL_HRTIM_GetADCTrigSrc\n
03276   *         ADC2R        ADC2TAC2        LL_HRTIM_GetADCTrigSrc\n
03277   *         ADC2R        ADC2TFC2        LL_HRTIM_GetADCTrigSrc\n
03278   *         ADC2R        ADC2TAC4        LL_HRTIM_GetADCTrigSrc\n
03279   *         ADC2R        ADC2TAPER       LL_HRTIM_GetADCTrigSrc\n
03280   *         ADC2R        ADC2TBC2        LL_HRTIM_GetADCTrigSrc\n
03281   *         ADC2R        ADC2TFC3        LL_HRTIM_GetADCTrigSrc\n
03282   *         ADC2R        ADC2TBC4        LL_HRTIM_GetADCTrigSrc\n
03283   *         ADC2R        ADC2TBPER       LL_HRTIM_GetADCTrigSrc\n
03284   *         ADC2R        ADC2TCC2        LL_HRTIM_GetADCTrigSrc\n
03285   *         ADC2R        ADC2TFC4        LL_HRTIM_GetADCTrigSrc\n
03286   *         ADC2R        ADC2TCC4        LL_HRTIM_GetADCTrigSrc\n
03287   *         ADC2R        ADC2TCPER       LL_HRTIM_GetADCTrigSrc\n
03288   *         ADC2R        ADC2TCRST       LL_HRTIM_GetADCTrigSrc\n
03289   *         ADC2R        ADC2TDC2        LL_HRTIM_GetADCTrigSrc\n
03290   *         ADC2R        ADC2TFPER       LL_HRTIM_GetADCTrigSrc\n
03291   *         ADC2R        ADC2TDC4        LL_HRTIM_GetADCTrigSrc\n
03292   *         ADC2R        ADC2TDPER       LL_HRTIM_GetADCTrigSrc\n
03293   *         ADC2R        ADC2TDRST       LL_HRTIM_GetADCTrigSrc\n
03294   *         ADC2R        ADC2TEC2        LL_HRTIM_GetADCTrigSrc\n
03295   *         ADC2R        ADC2TEC3        LL_HRTIM_GetADCTrigSrc\n
03296   *         ADC2R        ADC2TEC4        LL_HRTIM_GetADCTrigSrc\n
03297   *         ADC2R        ADC2TERST       LL_HRTIM_GetADCTrigSrc\n
03298   *         ADC3R        ADC3MC1         LL_HRTIM_GetADCTrigSrc\n
03299   *         ADC3R        ADC3MC2         LL_HRTIM_GetADCTrigSrc\n
03300   *         ADC3R        ADC3MC3         LL_HRTIM_GetADCTrigSrc\n
03301   *         ADC3R        ADC3MC4         LL_HRTIM_GetADCTrigSrc\n
03302   *         ADC3R        ADC3MPER        LL_HRTIM_GetADCTrigSrc\n
03303   *         ADC3R        ADC3EEV1        LL_HRTIM_GetADCTrigSrc\n
03304   *         ADC3R        ADC3EEV2        LL_HRTIM_GetADCTrigSrc\n
03305   *         ADC3R        ADC3EEV3        LL_HRTIM_GetADCTrigSrc\n
03306   *         ADC3R        ADC3EEV4        LL_HRTIM_GetADCTrigSrc\n
03307   *         ADC3R        ADC3EEV5        LL_HRTIM_GetADCTrigSrc\n
03308   *         ADC3R        ADC3TFC2        LL_HRTIM_GetADCTrigSrc\n
03309   *         ADC3R        ADC3TAC3        LL_HRTIM_GetADCTrigSrc\n
03310   *         ADC3R        ADC3TAC4        LL_HRTIM_GetADCTrigSrc\n
03311   *         ADC3R        ADC3TAPER       LL_HRTIM_GetADCTrigSrc\n
03312   *         ADC3R        ADC3TARST       LL_HRTIM_GetADCTrigSrc\n
03313   *         ADC3R        ADC3TFC3        LL_HRTIM_GetADCTrigSrc\n
03314   *         ADC3R        ADC3TBC3        LL_HRTIM_GetADCTrigSrc\n
03315   *         ADC3R        ADC3TBC4        LL_HRTIM_GetADCTrigSrc\n
03316   *         ADC3R        ADC3TBPER       LL_HRTIM_GetADCTrigSrc\n
03317   *         ADC3R        ADC3TBRST       LL_HRTIM_GetADCTrigSrc\n
03318   *         ADC3R        ADC3TFC4        LL_HRTIM_GetADCTrigSrc\n
03319   *         ADC3R        ADC3TCC3        LL_HRTIM_GetADCTrigSrc\n
03320   *         ADC3R        ADC3TCC4        LL_HRTIM_GetADCTrigSrc\n
03321   *         ADC3R        ADC3TCPER       LL_HRTIM_GetADCTrigSrc\n
03322   *         ADC3R        ADC3TFPER       LL_HRTIM_GetADCTrigSrc\n
03323   *         ADC3R        ADC3TDC3        LL_HRTIM_GetADCTrigSrc\n
03324   *         ADC3R        ADC3TDC4        LL_HRTIM_GetADCTrigSrc\n
03325   *         ADC3R        ADC3TDPER       LL_HRTIM_GetADCTrigSrc\n
03326   *         ADC3R        ADC3TFRST       LL_HRTIM_GetADCTrigSrc\n
03327   *         ADC3R        ADC3TEC3        LL_HRTIM_GetADCTrigSrc\n
03328   *         ADC3R        ADC3TEC4        LL_HRTIM_GetADCTrigSrc\n
03329   *         ADC3R        ADC3TEPER       LL_HRTIM_GetADCTrigSrc\n
03330   *         ADC4R        ADC4MC1         LL_HRTIM_GetADCTrigSrc\n
03331   *         ADC4R        ADC4MC2         LL_HRTIM_GetADCTrigSrc\n
03332   *         ADC4R        ADC4MC3         LL_HRTIM_GetADCTrigSrc\n
03333   *         ADC4R        ADC4MC4         LL_HRTIM_GetADCTrigSrc\n
03334   *         ADC4R        ADC4MPER        LL_HRTIM_GetADCTrigSrc\n
03335   *         ADC4R        ADC4EEV6        LL_HRTIM_GetADCTrigSrc\n
03336   *         ADC4R        ADC4EEV7        LL_HRTIM_GetADCTrigSrc\n
03337   *         ADC4R        ADC4EEV8        LL_HRTIM_GetADCTrigSrc\n
03338   *         ADC4R        ADC4EEV9        LL_HRTIM_GetADCTrigSrc\n
03339   *         ADC4R        ADC4EEV10       LL_HRTIM_GetADCTrigSrc\n
03340   *         ADC4R        ADC4TAC2        LL_HRTIM_GetADCTrigSrc\n
03341   *         ADC4R        ADC4TFC2        LL_HRTIM_GetADCTrigSrc\n
03342   *         ADC4R        ADC4TAC4        LL_HRTIM_GetADCTrigSrc\n
03343   *         ADC4R        ADC4TAPER       LL_HRTIM_GetADCTrigSrc\n
03344   *         ADC4R        ADC4TBC2        LL_HRTIM_GetADCTrigSrc\n
03345   *         ADC4R        ADC4TFC3        LL_HRTIM_GetADCTrigSrc\n
03346   *         ADC4R        ADC4TBC4        LL_HRTIM_GetADCTrigSrc\n
03347   *         ADC4R        ADC4TBPER       LL_HRTIM_GetADCTrigSrc\n
03348   *         ADC4R        ADC4TCC2        LL_HRTIM_GetADCTrigSrc\n
03349   *         ADC4R        ADC4TFC4        LL_HRTIM_GetADCTrigSrc\n
03350   *         ADC4R        ADC4TCC4        LL_HRTIM_GetADCTrigSrc\n
03351   *         ADC4R        ADC4TCPER       LL_HRTIM_GetADCTrigSrc\n
03352   *         ADC4R        ADC4TCRST       LL_HRTIM_GetADCTrigSrc\n
03353   *         ADC4R        ADC4TDC2        LL_HRTIM_GetADCTrigSrc\n
03354   *         ADC4R        ADC4TFPER       LL_HRTIM_GetADCTrigSrc\n
03355   *         ADC4R        ADC4TDC4        LL_HRTIM_GetADCTrigSrc\n
03356   *         ADC4R        ADC4TDPER       LL_HRTIM_GetADCTrigSrc\n
03357   *         ADC4R        ADC4TDRST       LL_HRTIM_GetADCTrigSrc\n
03358   *         ADC4R        ADC4TEC2        LL_HRTIM_GetADCTrigSrc\n
03359   *         ADC4R        ADC4TEC3        LL_HRTIM_GetADCTrigSrc\n
03360   *         ADC4R        ADC4TEC4        LL_HRTIM_GetADCTrigSrc\n
03361   *         ADC4R        ADC4TERST       LL_HRTIM_GetADCTrigSrc
03362   *         ADCER        ADC5TRG         LL_HRTIM_SetADCTrigSrc\n
03363   *         ADCER        ADC6TRG         LL_HRTIM_SetADCTrigSrc\n
03364   *         ADCER        ADC7TRG         LL_HRTIM_SetADCTrigSrc\n
03365   *         ADCER        ADC8TRG         LL_HRTIM_SetADCTrigSrc\n
03366   *         ADCER        ADC9TRG         LL_HRTIM_SetADCTrigSrc\n
03367   *         ADCER        ADC10TRG        LL_HRTIM_SetADCTrigSrc
03368   * @param  HRTIMx High Resolution Timer instance
03369   * @param  HRTIMx High Resolution Timer instance
03370   * @param  ADCTrig This parameter can be one of the following values:
03371   *         @arg @ref LL_HRTIM_ADCTRIG_1
03372   *         @arg @ref LL_HRTIM_ADCTRIG_2
03373   *         @arg @ref LL_HRTIM_ADCTRIG_3
03374   *         @arg @ref LL_HRTIM_ADCTRIG_4
03375   *         @arg @ref LL_HRTIM_ADCTRIG_5
03376   *         @arg @ref LL_HRTIM_ADCTRIG_6
03377   *         @arg @ref LL_HRTIM_ADCTRIG_7
03378   *         @arg @ref LL_HRTIM_ADCTRIG_8
03379   *         @arg @ref LL_HRTIM_ADCTRIG_9
03380   *         @arg @ref LL_HRTIM_ADCTRIG_10
03381   * @retval Src This parameter can be a combination of the following values:
03382   *
03383   *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
03384   *         combination of the following values:
03385   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
03386   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
03387   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
03388   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
03389   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
03390   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
03391   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
03392   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
03393   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
03394   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
03395   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
03396   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
03397   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
03398   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
03399   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
03400   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
03401   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
03402   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
03403   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
03404   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
03405   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
03406   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
03407   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
03408   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
03409   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
03410   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
03411   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
03412   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
03413   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
03414   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
03415   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
03416   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
03417   *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
03418   *
03419   *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
03420   *         combination of the following values:
03421   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
03422   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
03423   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
03424   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
03425   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
03426   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
03427   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
03428   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
03429   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
03430   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
03431   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
03432   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
03433   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
03434   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
03435   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
03436   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
03437   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
03438   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
03439   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
03440   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
03441   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
03442   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
03443   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
03444   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
03445   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
03446   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
03447   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
03448   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
03449   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
03450   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
03451   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
03452   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
03453   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
03454   *
03455   *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
03456   *         can be one of the following values:
03457   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
03458   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
03459   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
03460   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
03461   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
03462   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
03463   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
03464   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
03465   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
03466   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
03467   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
03468   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
03469   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
03470   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
03471   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
03472   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
03473   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
03474   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
03475   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
03476   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
03477   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
03478   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
03479   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
03480   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
03481   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
03482   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
03483   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
03484   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
03485   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
03486   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
03487   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
03488   *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
03489   *
03490   *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
03491   *         can be one of the following values:
03492   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
03493   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
03494   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
03495   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
03496   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
03497   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
03498   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
03499   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
03500   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
03501   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
03502   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
03503   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
03504   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
03505   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
03506   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
03507   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
03508   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
03509   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
03510   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
03511   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
03512   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
03513   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
03514   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
03515   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
03516   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
03517   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
03518   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
03519   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
03520   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
03521   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
03522   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
03523   *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
03524   */
03525 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
03526 {
03527   const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
03528                                                                     REG_OFFSET_TAB_ADCER[ADCTrig]));
03529   return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
03530
03531 }
03532
03533
03534 /**
03535   * @brief  Select the ADC post scaler.
03536   * @note This function allows to adjust each ADC trigger rate individually.
03537   * @note In center-aligned mode, the ADC trigger rate is also dependent on
03538   *       ADROM[1:0] bitfield, programmed in the source timer
03539   *       (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
03540   * @rmtoll ADCPS2       ADC10PSC        LL_HRTIM_SetADCPostScaler\n
03541   *         ADCPS2       ADC9PSC         LL_HRTIM_SetADCPostScaler\n
03542   *         ADCPS2       ADC8PSC         LL_HRTIM_SetADCPostScaler\n
03543   *         ADCPS2       ADC7PSC         LL_HRTIM_SetADCPostScaler\n
03544   *         ADCPS2       ADC6PSC         LL_HRTIM_SetADCPostScaler\n
03545   *         ADCPS1       ADC5PSC         LL_HRTIM_SetADCPostScaler\n
03546   *         ADCPS1       ADC4PSC         LL_HRTIM_SetADCPostScaler\n
03547   *         ADCPS1       ADC3PSC         LL_HRTIM_SetADCPostScaler\n
03548   *         ADCPS1       ADC2PSC         LL_HRTIM_SetADCPostScaler\n
03549   *         ADCPS1       ADC1PSC         LL_HRTIM_SetADCPostScaler
03550   * @param  HRTIMx High Resolution Timer instance
03551   * @param  ADCTrig This parameter can be one of the following values:
03552   *         @arg @ref LL_HRTIM_ADCTRIG_1
03553   *         @arg @ref LL_HRTIM_ADCTRIG_2
03554   *         @arg @ref LL_HRTIM_ADCTRIG_3
03555   *         @arg @ref LL_HRTIM_ADCTRIG_4
03556   *         @arg @ref LL_HRTIM_ADCTRIG_5
03557   *         @arg @ref LL_HRTIM_ADCTRIG_6
03558   *         @arg @ref LL_HRTIM_ADCTRIG_7
03559   *         @arg @ref LL_HRTIM_ADCTRIG_8
03560   *         @arg @ref LL_HRTIM_ADCTRIG_9
03561   *         @arg @ref LL_HRTIM_ADCTRIG_10
03562   * @param  PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
03563   * @retval None
03564   */
03565 __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
03566 {
03567
03568   uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
03569   uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
03570
03571   MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
03572   MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
03573
03574 }
03575
03576 /**
03577   * @brief  Get the selected ADC post scaler.
03578   * @rmtoll ADCPS2       ADC10PSC        LL_HRTIM_GetADCPostScaler\n
03579   *         ADCPS2       ADC9PSC         LL_HRTIM_GetADCPostScaler\n
03580   *         ADCPS2       ADC8PSC         LL_HRTIM_GetADCPostScaler\n
03581   *         ADCPS2       ADC7PSC         LL_HRTIM_GetADCPostScaler\n
03582   *         ADCPS2       ADC6PSC         LL_HRTIM_GetADCPostScaler\n
03583   *         ADCPS1       ADC5PSC         LL_HRTIM_GetADCPostScaler\n
03584   *         ADCPS1       ADC4PSC         LL_HRTIM_GetADCPostScaler\n
03585   *         ADCPS1       ADC3PSC         LL_HRTIM_GetADCPostScaler\n
03586   *         ADCPS1       ADC2PSC         LL_HRTIM_GetADCPostScaler\n
03587   *         ADCPS1       ADC1PSC         LL_HRTIM_GetADCPostScaler
03588   * @param  HRTIMx High Resolution Timer instance
03589   * @param  ADCTrig This parameter can be one of the following values:
03590   *         @arg @ref LL_HRTIM_ADCTRIG_1
03591   *         @arg @ref LL_HRTIM_ADCTRIG_2
03592   *         @arg @ref LL_HRTIM_ADCTRIG_3
03593   *         @arg @ref LL_HRTIM_ADCTRIG_4
03594   *         @arg @ref LL_HRTIM_ADCTRIG_5
03595   *         @arg @ref LL_HRTIM_ADCTRIG_6
03596   *         @arg @ref LL_HRTIM_ADCTRIG_7
03597   *         @arg @ref LL_HRTIM_ADCTRIG_8
03598   *         @arg @ref LL_HRTIM_ADCTRIG_9
03599   *         @arg @ref LL_HRTIM_ADCTRIG_10
03600   * @retval  PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
03601   */
03602 __STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
03603 {
03604
03605   uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
03606   uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
03607
03608   uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
03609   uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
03610
03611   return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
03612
03613 }
03614
03615 /**
03616   * @brief  Configure the DLL calibration mode.
03617   * @rmtoll DLLCR        CALEN         LL_HRTIM_ConfigDLLCalibration\n
03618   *         DLLCR        CALRTE        LL_HRTIM_ConfigDLLCalibration
03619   * @param  HRTIMx High Resolution Timer instance
03620   * @param  Mode This parameter can be one of the following values:
03621   *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
03622   *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
03623   * @param  Period This parameter can be one of the following values:
03624   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
03625   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
03626   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
03627   *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
03628   * @retval None
03629   */
03630 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
03631 {
03632   MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
03633 }
03634
03635 /**
03636   * @brief  Launch DLL calibration
03637   * @rmtoll DLLCR        CAL           LL_HRTIM_StartDLLCalibration
03638   * @param  HRTIMx High Resolution Timer instance
03639   * @retval None
03640   */
03641 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
03642 {
03643   SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
03644 }
03645
03646 /**
03647   * @}
03648   */
03649
03650 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
03651   * @{
03652   */
03653
03654 /**
03655   * @brief  Enable timer(s) counter.
03656   * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_CounterEnable\n
03657   *         MDIER        TECEN         LL_HRTIM_TIM_CounterEnable\n
03658   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterEnable\n
03659   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterEnable\n
03660   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterEnable\n
03661   *         MDIER        TACEN         LL_HRTIM_TIM_CounterEnable\n
03662   *         MDIER        MCEN          LL_HRTIM_TIM_CounterEnable
03663   * @param  HRTIMx High Resolution Timer instance
03664   * @param  Timers This parameter can be a combination of the following values:
03665   *         @arg @ref LL_HRTIM_TIMER_MASTER
03666   *         @arg @ref LL_HRTIM_TIMER_A
03667   *         @arg @ref LL_HRTIM_TIMER_B
03668   *         @arg @ref LL_HRTIM_TIMER_C
03669   *         @arg @ref LL_HRTIM_TIMER_D
03670   *         @arg @ref LL_HRTIM_TIMER_E
03671   *         @arg @ref LL_HRTIM_TIMER_F
03672   * @retval None
03673   */
03674 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
03675 {
03676   SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
03677 }
03678
03679 /**
03680   * @brief  Disable timer(s) counter.
03681   * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_CounterDisable\n
03682   *         MDIER        TECEN         LL_HRTIM_TIM_CounterDisable\n
03683   *         MDIER        TDCEN         LL_HRTIM_TIM_CounterDisable\n
03684   *         MDIER        TCCEN         LL_HRTIM_TIM_CounterDisable\n
03685   *         MDIER        TBCEN         LL_HRTIM_TIM_CounterDisable\n
03686   *         MDIER        TACEN         LL_HRTIM_TIM_CounterDisable\n
03687   *         MDIER        MCEN          LL_HRTIM_TIM_CounterDisable
03688   * @param  HRTIMx High Resolution Timer instance
03689   * @param  Timers This parameter can be a combination of the following values:
03690   *         @arg @ref LL_HRTIM_TIMER_MASTER
03691   *         @arg @ref LL_HRTIM_TIMER_A
03692   *         @arg @ref LL_HRTIM_TIMER_B
03693   *         @arg @ref LL_HRTIM_TIMER_C
03694   *         @arg @ref LL_HRTIM_TIMER_D
03695   *         @arg @ref LL_HRTIM_TIMER_E
03696   *         @arg @ref LL_HRTIM_TIMER_F
03697   * @retval None
03698   */
03699 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
03700 {
03701   CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
03702 }
03703
03704 /**
03705   * @brief  Indicate whether the timer counter is enabled.
03706   * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_IsCounterEnabled\n
03707   *         MDIER        TECEN         LL_HRTIM_TIM_IsCounterEnabled\n
03708   *         MDIER        TDCEN         LL_HRTIM_TIM_IsCounterEnabled\n
03709   *         MDIER        TCCEN         LL_HRTIM_TIM_IsCounterEnabled\n
03710   *         MDIER        TBCEN         LL_HRTIM_TIM_IsCounterEnabled\n
03711   *         MDIER        TACEN         LL_HRTIM_TIM_IsCounterEnabled\n
03712   *         MDIER        MCEN          LL_HRTIM_TIM_IsCounterEnabled
03713   * @param  HRTIMx High Resolution Timer instance
03714   * @param  Timer This parameter can be one of the following values:
03715   *         @arg @ref LL_HRTIM_TIMER_MASTER
03716   *         @arg @ref LL_HRTIM_TIMER_A
03717   *         @arg @ref LL_HRTIM_TIMER_B
03718   *         @arg @ref LL_HRTIM_TIMER_C
03719   *         @arg @ref LL_HRTIM_TIMER_D
03720   *         @arg @ref LL_HRTIM_TIMER_E
03721   *         @arg @ref LL_HRTIM_TIMER_F
03722   * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
03723   */
03724 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03725 {
03726   return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
03727 }
03728
03729 /**
03730   * @brief  Set the timer clock prescaler ratio.
03731   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_SetPrescaler\n
03732   *         TIMxCR     CKPSC         LL_HRTIM_TIM_SetPrescaler
03733   * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
03734   * @note The prescaling ratio cannot be modified once the timer counter is enabled.
03735   * @param  HRTIMx High Resolution Timer instance
03736   * @param  Timer This parameter can be one of the following values:
03737   *         @arg @ref LL_HRTIM_TIMER_MASTER
03738   *         @arg @ref LL_HRTIM_TIMER_A
03739   *         @arg @ref LL_HRTIM_TIMER_B
03740   *         @arg @ref LL_HRTIM_TIMER_C
03741   *         @arg @ref LL_HRTIM_TIMER_D
03742   *         @arg @ref LL_HRTIM_TIMER_E
03743   *         @arg @ref LL_HRTIM_TIMER_F
03744   * @param  Prescaler This parameter can be one of the following values:
03745   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
03746   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
03747   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
03748   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
03749   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
03750   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
03751   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
03752   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
03753   * @retval None
03754   */
03755 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
03756 {
03757   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03758   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03759   MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
03760 }
03761
03762 /**
03763   * @brief  Get the timer clock prescaler ratio
03764   * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_GetPrescaler\n
03765   *         TIMxCR     CKPSC         LL_HRTIM_TIM_GetPrescaler
03766   * @param  HRTIMx High Resolution Timer instance
03767   * @param  Timer This parameter can be one of the following values:
03768   *         @arg @ref LL_HRTIM_TIMER_MASTER
03769   *         @arg @ref LL_HRTIM_TIMER_A
03770   *         @arg @ref LL_HRTIM_TIMER_B
03771   *         @arg @ref LL_HRTIM_TIMER_C
03772   *         @arg @ref LL_HRTIM_TIMER_D
03773   *         @arg @ref LL_HRTIM_TIMER_E
03774   *         @arg @ref LL_HRTIM_TIMER_F
03775   * @retval Prescaler Returned value can be one of the following values:
03776   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
03777   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
03778   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
03779   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
03780   *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
03781   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
03782   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
03783   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
03784   */
03785 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03786 {
03787   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03788   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03789   return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
03790 }
03791
03792 /**
03793   * @brief  Set the counter operating mode mode (single-shot, continuous or re-triggerable).
03794   * @rmtoll MCR        CONT         LL_HRTIM_TIM_SetCounterMode\n
03795   *         MCR        RETRIG       LL_HRTIM_TIM_SetCounterMode\n
03796   *         TIMxCR     CONT         LL_HRTIM_TIM_SetCounterMode\n
03797   *         TIMxCR     RETRIG       LL_HRTIM_TIM_SetCounterMode
03798   * @param  HRTIMx High Resolution Timer instance
03799   * @param  Timer This parameter can be one of the following values:
03800   *         @arg @ref LL_HRTIM_TIMER_MASTER
03801   *         @arg @ref LL_HRTIM_TIMER_A
03802   *         @arg @ref LL_HRTIM_TIMER_B
03803   *         @arg @ref LL_HRTIM_TIMER_C
03804   *         @arg @ref LL_HRTIM_TIMER_D
03805   *         @arg @ref LL_HRTIM_TIMER_E
03806   *         @arg @ref LL_HRTIM_TIMER_F
03807   * @param  Mode This parameter can be one of the following values:
03808   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
03809   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
03810   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
03811   * @retval None
03812   */
03813 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
03814 {
03815   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03816   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03817   MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
03818 }
03819
03820 /**
03821   * @brief  Get the counter operating mode mode
03822   * @rmtoll MCR        CONT         LL_HRTIM_TIM_GetCounterMode\n
03823   *         MCR        RETRIG       LL_HRTIM_TIM_GetCounterMode\n
03824   *         TIMxCR     CONT         LL_HRTIM_TIM_GetCounterMode\n
03825   *         TIMxCR     RETRIG       LL_HRTIM_TIM_GetCounterMode
03826   * @param  HRTIMx High Resolution Timer instance
03827   * @param  Timer This parameter can be one of the following values:
03828   *         @arg @ref LL_HRTIM_TIMER_MASTER
03829   *         @arg @ref LL_HRTIM_TIMER_A
03830   *         @arg @ref LL_HRTIM_TIMER_B
03831   *         @arg @ref LL_HRTIM_TIMER_C
03832   *         @arg @ref LL_HRTIM_TIMER_D
03833   *         @arg @ref LL_HRTIM_TIMER_E
03834   *         @arg @ref LL_HRTIM_TIMER_F
03835   * @retval Mode Returned value can be one of the following values:
03836   *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
03837   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
03838   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
03839   */
03840 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03841 {
03842   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03843   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03844   return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
03845 }
03846
03847 /**
03848   * @brief  Enable the half duty-cycle mode.
03849   * @rmtoll MCR        HALF         LL_HRTIM_TIM_EnableHalfMode\n
03850   *         TIMxCR     HALF         LL_HRTIM_TIM_EnableHalfMode
03851   * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
03852   *       active register is automatically updated with HRTIM_MPER/2
03853   *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
03854   * @param  HRTIMx High Resolution Timer instance
03855   * @param  Timer This parameter can be one of the following values:
03856   *         @arg @ref LL_HRTIM_TIMER_MASTER
03857   *         @arg @ref LL_HRTIM_TIMER_A
03858   *         @arg @ref LL_HRTIM_TIMER_B
03859   *         @arg @ref LL_HRTIM_TIMER_C
03860   *         @arg @ref LL_HRTIM_TIMER_D
03861   *         @arg @ref LL_HRTIM_TIMER_E
03862   *         @arg @ref LL_HRTIM_TIMER_F
03863   * @retval None
03864   */
03865 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03866 {
03867   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03868   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03869   SET_BIT(*pReg, HRTIM_MCR_HALF);
03870 }
03871
03872 /**
03873   * @brief  Disable the half duty-cycle mode.
03874   * @rmtoll MCR        HALF         LL_HRTIM_TIM_DisableHalfMode\n
03875   *         TIMxCR     HALF         LL_HRTIM_TIM_DisableHalfMode
03876   * @param  HRTIMx High Resolution Timer instance
03877   * @param  Timer This parameter can be one of the following values:
03878   *         @arg @ref LL_HRTIM_TIMER_MASTER
03879   *         @arg @ref LL_HRTIM_TIMER_A
03880   *         @arg @ref LL_HRTIM_TIMER_B
03881   *         @arg @ref LL_HRTIM_TIMER_C
03882   *         @arg @ref LL_HRTIM_TIMER_D
03883   *         @arg @ref LL_HRTIM_TIMER_E
03884   *         @arg @ref LL_HRTIM_TIMER_F
03885   * @retval None
03886   */
03887 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03888 {
03889   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03890   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03891   CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
03892   CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
03893 }
03894
03895 /**
03896   * @brief  Indicate whether half duty-cycle mode is enabled for a given timer.
03897   * @rmtoll MCR        HALF         LL_HRTIM_TIM_IsEnabledHalfMode\n
03898   *         TIMxCR     HALF         LL_HRTIM_TIM_IsEnabledHalfMode
03899   * @param  HRTIMx High Resolution Timer instance
03900   * @param  Timer This parameter can be one of the following values:
03901   *         @arg @ref LL_HRTIM_TIMER_MASTER
03902   *         @arg @ref LL_HRTIM_TIMER_A
03903   *         @arg @ref LL_HRTIM_TIMER_B
03904   *         @arg @ref LL_HRTIM_TIMER_C
03905   *         @arg @ref LL_HRTIM_TIMER_D
03906   *         @arg @ref LL_HRTIM_TIMER_E
03907   *         @arg @ref LL_HRTIM_TIMER_F
03908   * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
03909   */
03910 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03911 {
03912   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
03913   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
03914
03915   return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
03916 }
03917
03918 /**
03919   * @brief  Enable the Re-Syncronisation Update.
03920   * @note   The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
03921   *         or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
03922   * @note   LL_HRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force
03923   *         immediate update of the slave timer registers.
03924   * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_EnableResyncUpdate
03925   * @param  HRTIMx High Resolution Timer instance
03926   * @param  Timer This parameter can be one of the following values:
03927   *         @arg @ref LL_HRTIM_TIMER_A
03928   *         @arg @ref LL_HRTIM_TIMER_B
03929   *         @arg @ref LL_HRTIM_TIMER_C
03930   *         @arg @ref LL_HRTIM_TIMER_D
03931   *         @arg @ref LL_HRTIM_TIMER_E
03932   *         @arg @ref LL_HRTIM_TIMER_F
03933   * @retval None
03934   */
03935 __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03936 {
03937   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03938   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03939                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03940   SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
03941   /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
03942 }
03943
03944 /**
03945   * @brief  Disable the Re-Syncronisation Update.
03946   * @note   The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
03947   *         or from a software update (TxSWU bit) is taken into account immediately.
03948   * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_DisableResyncUpdate
03949   * @param  HRTIMx High Resolution Timer instance
03950   * @param  Timer This parameter can be one of the following values:
03951   *         @arg @ref LL_HRTIM_TIMER_A
03952   *         @arg @ref LL_HRTIM_TIMER_B
03953   *         @arg @ref LL_HRTIM_TIMER_C
03954   *         @arg @ref LL_HRTIM_TIMER_D
03955   *         @arg @ref LL_HRTIM_TIMER_E
03956   *         @arg @ref LL_HRTIM_TIMER_F
03957   * @retval None
03958   */
03959 __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03960 {
03961   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03962   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03963                                                               REG_OFFSET_TAB_TIMER[iTimer]));
03964
03965   CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
03966   /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
03967 }
03968
03969 /**
03970   * @brief  Indicate whether the Re-Syncronisation Update is enabled.
03971   * @note   This bit specifies whether update source coming outside
03972   *         from the timing unit must be synchronized
03973   * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_IsEnabledResyncUpdate
03974   * @param  HRTIMx High Resolution Timer instance
03975   * @param  Timer This parameter can be one of the following values:
03976   *         @arg @ref LL_HRTIM_TIMER_A
03977   *         @arg @ref LL_HRTIM_TIMER_B
03978   *         @arg @ref LL_HRTIM_TIMER_C
03979   *         @arg @ref LL_HRTIM_TIMER_D
03980   *         @arg @ref LL_HRTIM_TIMER_E
03981   *         @arg @ref LL_HRTIM_TIMER_F
03982   * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
03983   */
03984 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
03985 {
03986   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
03987   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
03988                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
03989
03990   return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
03991   /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
03992 }
03993
03994 /**
03995   * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
03996   * @note When interleaved mode is enabled, the content of the compare registers is overridden.
03997   * @rmtoll MCR        HALF      LL_HRTIM_TIM_SetInterleavedMode\n
03998   *         MCR        INTLVD    LL_HRTIM_TIM_SetInterleavedMode\n
03999   *         TIMxCR     HALF      LL_HRTIM_TIM_SetInterleavedMode\n
04000   *         TIMxCR     INTLVD    LL_HRTIM_TIM_SetInterleavedMode
04001   * @param  HRTIMx High Resolution Timer instance
04002   * @param  Timer This parameter can be one of the following values:
04003   *         @arg @ref LL_HRTIM_TIMER_MASTER
04004   *         @arg @ref LL_HRTIM_TIMER_A
04005   *         @arg @ref LL_HRTIM_TIMER_B
04006   *         @arg @ref LL_HRTIM_TIMER_C
04007   *         @arg @ref LL_HRTIM_TIMER_D
04008   *         @arg @ref LL_HRTIM_TIMER_E
04009   *         @arg @ref LL_HRTIM_TIMER_F
04010   * @param  Mode This parameter can be one of the following values:
04011   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
04012   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
04013   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
04014   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
04015   * @retval None
04016   */
04017 __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
04018 {
04019   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04020   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04021
04022   MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
04023              ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
04024 }
04025
04026 /**
04027   * @brief  get the Interleaved configuration.
04028   * @rmtoll MCR        INTLVD         LL_HRTIM_TIM_GetInterleavedMode\n
04029   *         TIMxCR     INTLVD         LL_HRTIM_TIM_GetInterleavedMode
04030   * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
04031   *              the interleaved Mode is dual if HALF bit is set,
04032
04033   *              HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
04034   *              with HRTIM_MPER/2 or HRTIM_MPER/4
04035   *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
04036
04037   * @param  HRTIMx High Resolution Timer instance
04038   * @param  Timer This parameter can be one of the following values:
04039   *         @arg @ref LL_HRTIM_TIMER_MASTER
04040   *         @arg @ref LL_HRTIM_TIMER_A
04041   *         @arg @ref LL_HRTIM_TIMER_B
04042   *         @arg @ref LL_HRTIM_TIMER_C
04043   *         @arg @ref LL_HRTIM_TIMER_D
04044   *         @arg @ref LL_HRTIM_TIMER_E
04045   *         @arg @ref LL_HRTIM_TIMER_F
04046   * @retval This parameter can be one of the following values:
04047   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
04048   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
04049   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
04050   *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
04051   */
04052 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04053 {
04054   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04055   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04056
04057   uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
04058   return ((Mode & HRTIM_MCR_HALF) | ((Mode  >> REG_SHIFT_TAB_INTLVD[iTimer]) &  HRTIM_MCR_INTLVD));
04059 }
04060
04061 /**
04062   * @brief  Enable the timer start when receiving a synchronization input event.
04063   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_EnableStartOnSync\n
04064   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_EnableStartOnSync
04065   * @param  HRTIMx High Resolution Timer instance
04066   * @param  Timer This parameter can be one of the following values:
04067   *         @arg @ref LL_HRTIM_TIMER_MASTER
04068   *         @arg @ref LL_HRTIM_TIMER_A
04069   *         @arg @ref LL_HRTIM_TIMER_B
04070   *         @arg @ref LL_HRTIM_TIMER_C
04071   *         @arg @ref LL_HRTIM_TIMER_D
04072   *         @arg @ref LL_HRTIM_TIMER_E
04073   *         @arg @ref LL_HRTIM_TIMER_F
04074   * @retval None
04075   */
04076 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04077 {
04078   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04079   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04080   SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
04081 }
04082
04083 /**
04084   * @brief  Disable the timer start when receiving a synchronization input event.
04085   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_DisableStartOnSync\n
04086   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_DisableStartOnSync
04087   * @param  HRTIMx High Resolution Timer instance
04088   * @param  Timer This parameter can be one of the following values:
04089   *         @arg @ref LL_HRTIM_TIMER_MASTER
04090   *         @arg @ref LL_HRTIM_TIMER_A
04091   *         @arg @ref LL_HRTIM_TIMER_B
04092   *         @arg @ref LL_HRTIM_TIMER_C
04093   *         @arg @ref LL_HRTIM_TIMER_D
04094   *         @arg @ref LL_HRTIM_TIMER_E
04095   *         @arg @ref LL_HRTIM_TIMER_F
04096   * @retval None
04097   */
04098 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04099 {
04100   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04101   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04102   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
04103 }
04104
04105 /**
04106   * @brief  Indicate whether the timer start when receiving a synchronization input event.
04107   * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_IsEnabledStartOnSync\n
04108   *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_IsEnabledStartOnSync
04109   * @param  HRTIMx High Resolution Timer instance
04110   * @param  Timer This parameter can be one of the following values:
04111   *         @arg @ref LL_HRTIM_TIMER_MASTER
04112   *         @arg @ref LL_HRTIM_TIMER_A
04113   *         @arg @ref LL_HRTIM_TIMER_B
04114   *         @arg @ref LL_HRTIM_TIMER_C
04115   *         @arg @ref LL_HRTIM_TIMER_D
04116   *         @arg @ref LL_HRTIM_TIMER_E
04117   *         @arg @ref LL_HRTIM_TIMER_F
04118   * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
04119   */
04120 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04121 {
04122   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04123   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04124
04125   return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
04126 }
04127
04128 /**
04129   * @brief  Enable the timer reset when receiving a synchronization input event.
04130   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_EnableResetOnSync\n
04131   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_EnableResetOnSync
04132   * @param  HRTIMx High Resolution Timer instance
04133   * @param  Timer This parameter can be one of the following values:
04134   *         @arg @ref LL_HRTIM_TIMER_MASTER
04135   *         @arg @ref LL_HRTIM_TIMER_A
04136   *         @arg @ref LL_HRTIM_TIMER_B
04137   *         @arg @ref LL_HRTIM_TIMER_C
04138   *         @arg @ref LL_HRTIM_TIMER_D
04139   *         @arg @ref LL_HRTIM_TIMER_E
04140   *         @arg @ref LL_HRTIM_TIMER_F
04141   * @retval None
04142   */
04143 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04144 {
04145   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04146   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04147   SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
04148 }
04149
04150 /**
04151   * @brief  Disable the timer reset when receiving a synchronization input event.
04152   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_DisableResetOnSync\n
04153   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_DisableResetOnSync
04154   * @param  HRTIMx High Resolution Timer instance
04155   * @param  Timer This parameter can be one of the following values:
04156   *         @arg @ref LL_HRTIM_TIMER_MASTER
04157   *         @arg @ref LL_HRTIM_TIMER_A
04158   *         @arg @ref LL_HRTIM_TIMER_B
04159   *         @arg @ref LL_HRTIM_TIMER_C
04160   *         @arg @ref LL_HRTIM_TIMER_D
04161   *         @arg @ref LL_HRTIM_TIMER_E
04162   *         @arg @ref LL_HRTIM_TIMER_F
04163   * @retval None
04164   */
04165 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04166 {
04167   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04168   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04169   CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
04170 }
04171
04172 /**
04173   * @brief  Indicate whether the timer reset when receiving a synchronization input event.
04174   * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_IsEnabledResetOnSync\n
04175   *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_IsEnabledResetOnSync
04176   * @param  HRTIMx High Resolution Timer instance
04177   * @param  Timer This parameter can be one of the following values:
04178   *         @arg @ref LL_HRTIM_TIMER_MASTER
04179   *         @arg @ref LL_HRTIM_TIMER_A
04180   *         @arg @ref LL_HRTIM_TIMER_B
04181   *         @arg @ref LL_HRTIM_TIMER_C
04182   *         @arg @ref LL_HRTIM_TIMER_D
04183   *         @arg @ref LL_HRTIM_TIMER_E
04184   *         @arg @ref LL_HRTIM_TIMER_F
04185   * @retval None
04186   */
04187 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04188 {
04189   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04190   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04191
04192   return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
04193 }
04194
04195 /**
04196   * @brief  Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
04197   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_SetDACTrig\n
04198   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_SetDACTrig
04199   * @param  HRTIMx High Resolution Timer instance
04200   * @param  Timer This parameter can be one of the following values:
04201   *         @arg @ref LL_HRTIM_TIMER_MASTER
04202   *         @arg @ref LL_HRTIM_TIMER_A
04203   *         @arg @ref LL_HRTIM_TIMER_B
04204   *         @arg @ref LL_HRTIM_TIMER_C
04205   *         @arg @ref LL_HRTIM_TIMER_D
04206   *         @arg @ref LL_HRTIM_TIMER_E
04207   *         @arg @ref LL_HRTIM_TIMER_F
04208   * @param  DACTrig This parameter can be one of the following values:
04209   *         @arg @ref LL_HRTIM_DACTRIG_NONE
04210   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
04211   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
04212   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
04213   * @retval None
04214   */
04215 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
04216 {
04217   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04218   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04219   MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
04220 }
04221
04222 /**
04223   * @brief  Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
04224   * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_GetDACTrig\n
04225   *         TIMxCR     DACSYNC        LL_HRTIM_TIM_GetDACTrig
04226   * @param  HRTIMx High Resolution Timer instance
04227   * @param  Timer This parameter can be one of the following values:
04228   *         @arg @ref LL_HRTIM_TIMER_MASTER
04229   *         @arg @ref LL_HRTIM_TIMER_A
04230   *         @arg @ref LL_HRTIM_TIMER_B
04231   *         @arg @ref LL_HRTIM_TIMER_C
04232   *         @arg @ref LL_HRTIM_TIMER_D
04233   *         @arg @ref LL_HRTIM_TIMER_E
04234   *         @arg @ref LL_HRTIM_TIMER_F
04235   * @retval DACTrig Returned value can be one of the following values:
04236   *         @arg @ref LL_HRTIM_DACTRIG_NONE
04237   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
04238   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
04239   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
04240   */
04241 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04242 {
04243   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04244   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04245   return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
04246 }
04247
04248 /**
04249   * @brief  Enable the timer registers preload mechanism.
04250   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_EnablePreload\n
04251   *         TIMxCR     PREEN        LL_HRTIM_TIM_EnablePreload
04252   * @note When the preload mode is enabled, accessed registers are shadow registers.
04253   *       Their content is transferred into the active register after an update request,
04254   *       either software or synchronized with an event.
04255   * @param  HRTIMx High Resolution Timer instance
04256   * @param  Timer This parameter can be one of the following values:
04257   *         @arg @ref LL_HRTIM_TIMER_MASTER
04258   *         @arg @ref LL_HRTIM_TIMER_A
04259   *         @arg @ref LL_HRTIM_TIMER_B
04260   *         @arg @ref LL_HRTIM_TIMER_C
04261   *         @arg @ref LL_HRTIM_TIMER_D
04262   *         @arg @ref LL_HRTIM_TIMER_E
04263   *         @arg @ref LL_HRTIM_TIMER_F
04264   * @retval None
04265   */
04266 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04267 {
04268   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04269   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04270   SET_BIT(*pReg, HRTIM_MCR_PREEN);
04271 }
04272
04273 /**
04274   * @brief  Disable the timer registers preload mechanism.
04275   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_DisablePreload\n
04276   *         TIMxCR     PREEN        LL_HRTIM_TIM_DisablePreload
04277   * @param  HRTIMx High Resolution Timer instance
04278   * @param  Timer This parameter can be one of the following values:
04279   *         @arg @ref LL_HRTIM_TIMER_MASTER
04280   *         @arg @ref LL_HRTIM_TIMER_A
04281   *         @arg @ref LL_HRTIM_TIMER_B
04282   *         @arg @ref LL_HRTIM_TIMER_C
04283   *         @arg @ref LL_HRTIM_TIMER_D
04284   *         @arg @ref LL_HRTIM_TIMER_E
04285   *         @arg @ref LL_HRTIM_TIMER_F
04286   * @retval None
04287   */
04288 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04289 {
04290   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04291   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04292   CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
04293 }
04294
04295 /**
04296   * @brief  Indicate whether the timer registers preload mechanism is enabled.
04297   * @rmtoll MCR        PREEN        LL_HRTIM_TIM_IsEnabledPreload\n
04298   *         TIMxCR     PREEN        LL_HRTIM_TIM_IsEnabledPreload
04299   * @param  HRTIMx High Resolution Timer instance
04300   * @param  Timer This parameter can be one of the following values:
04301   *         @arg @ref LL_HRTIM_TIMER_MASTER
04302   *         @arg @ref LL_HRTIM_TIMER_A
04303   *         @arg @ref LL_HRTIM_TIMER_B
04304   *         @arg @ref LL_HRTIM_TIMER_C
04305   *         @arg @ref LL_HRTIM_TIMER_D
04306   *         @arg @ref LL_HRTIM_TIMER_E
04307   *         @arg @ref LL_HRTIM_TIMER_F
04308   * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
04309   */
04310 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04311 {
04312   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04313   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04314
04315   return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
04316 }
04317
04318 /**
04319   * @brief  Set the timer register update trigger.
04320   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_SetUpdateTrig\n
04321   *         TIMxCR        TAU        LL_HRTIM_TIM_SetUpdateTrig\n
04322   *         TIMxCR        TBU        LL_HRTIM_TIM_SetUpdateTrig\n
04323   *         TIMxCR        TCU        LL_HRTIM_TIM_SetUpdateTrig\n
04324   *         TIMxCR        TDU        LL_HRTIM_TIM_SetUpdateTrig\n
04325   *         TIMxCR        TEU        LL_HRTIM_TIM_SetUpdateTrig\n
04326   *         TIMxCR        TFU        LL_HRTIM_TIM_SetUpdateTrig\n
04327   *         TIMxCR        MSTU       LL_HRTIM_TIM_SetUpdateTrig
04328   * @param  HRTIMx High Resolution Timer instance
04329   * @param  Timer This parameter can be one of the following values:
04330   *         @arg @ref LL_HRTIM_TIMER_MASTER
04331   *         @arg @ref LL_HRTIM_TIMER_A
04332   *         @arg @ref LL_HRTIM_TIMER_B
04333   *         @arg @ref LL_HRTIM_TIMER_C
04334   *         @arg @ref LL_HRTIM_TIMER_D
04335   *         @arg @ref LL_HRTIM_TIMER_E
04336   *         @arg @ref LL_HRTIM_TIMER_F
04337   * @param  UpdateTrig This parameter can be one of the following values:
04338   *
04339   *         For the master timer this parameter can be one of the following values:
04340   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
04341   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
04342   *
04343   *         For timer A..F this parameter can be:
04344   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
04345   *         or a combination of the following values:
04346   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
04347   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
04348   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
04349   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
04350   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
04351   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
04352   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
04353   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
04354   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
04355   * @retval None
04356   */
04357 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
04358 {
04359   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04360   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04361   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
04362 }
04363
04364 /**
04365   * @brief  Get the timer register update trigger.
04366   * @rmtoll MCR           MREPU      LL_HRTIM_TIM_GetUpdateTrig\n
04367   *         TIMxCR        TBU        LL_HRTIM_TIM_GetUpdateTrig\n
04368   *         TIMxCR        TCU        LL_HRTIM_TIM_GetUpdateTrig\n
04369   *         TIMxCR        TDU        LL_HRTIM_TIM_GetUpdateTrig\n
04370   *         TIMxCR        TEU        LL_HRTIM_TIM_GetUpdateTrig\n
04371   *         TIMxCR        TFU        LL_HRTIM_TIM_GetUpdateTrig\n
04372   *         TIMxCR        MSTU       LL_HRTIM_TIM_GetUpdateTrig
04373   * @param  HRTIMx High Resolution Timer instance
04374   * @param  Timer This parameter can be one of the following values:
04375   *         @arg @ref LL_HRTIM_TIMER_MASTER
04376   *         @arg @ref LL_HRTIM_TIMER_A
04377   *         @arg @ref LL_HRTIM_TIMER_B
04378   *         @arg @ref LL_HRTIM_TIMER_C
04379   *         @arg @ref LL_HRTIM_TIMER_D
04380   *         @arg @ref LL_HRTIM_TIMER_E
04381   *         @arg @ref LL_HRTIM_TIMER_F
04382   * @retval UpdateTrig Returned value can be one of the following values:
04383   *
04384   *         For the master timer this parameter can be one of the following values:
04385   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
04386   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
04387   *
04388   *         For timer A..F this parameter can be:
04389   *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
04390   *         or a combination of the following values:
04391   *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
04392   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
04393   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
04394   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
04395   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
04396   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
04397   *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
04398   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
04399   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
04400   */
04401 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04402 {
04403   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04404   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04405   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >>  REG_SHIFT_TAB_UPDATETRIG[iTimer]);
04406 }
04407
04408 /**
04409   * @brief  Set  the timer registers update condition (how the registers update occurs relatively to the burst DMA  transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
04410   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_SetUpdateGating\n
04411   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_SetUpdateGating
04412   * @param  HRTIMx High Resolution Timer instance
04413   * @param  Timer This parameter can be one of the following values:
04414   *         @arg @ref LL_HRTIM_TIMER_MASTER
04415   *         @arg @ref LL_HRTIM_TIMER_A
04416   *         @arg @ref LL_HRTIM_TIMER_B
04417   *         @arg @ref LL_HRTIM_TIMER_C
04418   *         @arg @ref LL_HRTIM_TIMER_D
04419   *         @arg @ref LL_HRTIM_TIMER_E
04420   *         @arg @ref LL_HRTIM_TIMER_F
04421   * @param  UpdateGating This parameter can be one of the following values:
04422   *
04423   *         For the master timer this parameter can be one of the following values:
04424   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
04425   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
04426   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
04427   *
04428   *         For the timer A..F this parameter can be one of the following values:
04429   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
04430   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
04431   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
04432   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
04433   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
04434   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
04435   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
04436   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
04437   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
04438   * @retval None
04439   */
04440 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
04441 {
04442   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04443   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04444   MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
04445 }
04446
04447 /**
04448   * @brief  Get  the timer registers update condition.
04449   * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_GetUpdateGating\n
04450   *         TIMxCR        UPDGAT       LL_HRTIM_TIM_GetUpdateGating
04451   * @param  HRTIMx High Resolution Timer instance
04452   * @param  Timer This parameter can be one of the following values:
04453   *         @arg @ref LL_HRTIM_TIMER_MASTER
04454   *         @arg @ref LL_HRTIM_TIMER_A
04455   *         @arg @ref LL_HRTIM_TIMER_B
04456   *         @arg @ref LL_HRTIM_TIMER_C
04457   *         @arg @ref LL_HRTIM_TIMER_D
04458   *         @arg @ref LL_HRTIM_TIMER_E
04459   *         @arg @ref LL_HRTIM_TIMER_F
04460   * @retval UpdateGating Returned value can be one of the following values:
04461   *
04462   *         For the master timer this parameter can be one of the following values:
04463   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
04464   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
04465   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
04466   *
04467   *         For the timer A..F this parameter can be one of the following values:
04468   *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
04469   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
04470   *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
04471   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
04472   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
04473   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
04474   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
04475   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
04476   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
04477   */
04478 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04479 {
04480   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04481   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
04482   return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >>  REG_SHIFT_TAB_UPDATEGATING[iTimer]);
04483 }
04484
04485 /**
04486   * @brief  Enable the push-pull mode.
04487   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_EnablePushPullMode
04488   * @param  HRTIMx High Resolution Timer instance
04489   * @param  Timer This parameter can be one of the following values:
04490   *         @arg @ref LL_HRTIM_TIMER_A
04491   *         @arg @ref LL_HRTIM_TIMER_B
04492   *         @arg @ref LL_HRTIM_TIMER_C
04493   *         @arg @ref LL_HRTIM_TIMER_D
04494   *         @arg @ref LL_HRTIM_TIMER_E
04495   *         @arg @ref LL_HRTIM_TIMER_F
04496   * @retval None
04497   */
04498 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04499 {
04500   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04501   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
04502                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04503   SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
04504 }
04505
04506 /**
04507   * @brief  Disable the push-pull mode.
04508   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_DisablePushPullMode
04509   * @param  HRTIMx High Resolution Timer instance
04510   * @param  Timer This parameter can be one of the following values:
04511   *         @arg @ref LL_HRTIM_TIMER_A
04512   *         @arg @ref LL_HRTIM_TIMER_B
04513   *         @arg @ref LL_HRTIM_TIMER_C
04514   *         @arg @ref LL_HRTIM_TIMER_D
04515   *         @arg @ref LL_HRTIM_TIMER_E
04516   *         @arg @ref LL_HRTIM_TIMER_F
04517   * @retval None
04518   */
04519 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04520 {
04521   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04522   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
04523                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04524   CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
04525 }
04526
04527 /**
04528   * @brief  Indicate whether the push-pull mode is enabled.
04529   * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_IsEnabledPushPullMode\n
04530   * @param  HRTIMx High Resolution Timer instance
04531   * @param  Timer This parameter can be one of the following values:
04532   *         @arg @ref LL_HRTIM_TIMER_A
04533   *         @arg @ref LL_HRTIM_TIMER_B
04534   *         @arg @ref LL_HRTIM_TIMER_C
04535   *         @arg @ref LL_HRTIM_TIMER_D
04536   *         @arg @ref LL_HRTIM_TIMER_E
04537   *         @arg @ref LL_HRTIM_TIMER_F
04538   * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
04539   */
04540 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04541 {
04542   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04543   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
04544                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04545   return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
04546 }
04547
04548 /**
04549   * @brief  Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
04550   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_SetCompareMode\n
04551   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_SetCompareMode
04552   * @note In auto-delayed mode  the compare match occurs independently from the timer counter value.
04553   * @param  HRTIMx High Resolution Timer instance
04554   * @param  Timer This parameter can be one of the following values:
04555   *         @arg @ref LL_HRTIM_TIMER_A
04556   *         @arg @ref LL_HRTIM_TIMER_B
04557   *         @arg @ref LL_HRTIM_TIMER_C
04558   *         @arg @ref LL_HRTIM_TIMER_D
04559   *         @arg @ref LL_HRTIM_TIMER_E
04560   *         @arg @ref LL_HRTIM_TIMER_F
04561   * @param  CompareUnit This parameter can be one of the following values:
04562   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
04563   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
04564   * @param  Mode This parameter can be one of the following values:
04565   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
04566   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
04567   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
04568   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
04569   * @retval None
04570   */
04571 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
04572                                                  uint32_t Mode)
04573 {
04574   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04575   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
04576                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04577   uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
04578   MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
04579 }
04580
04581 /**
04582   * @brief  Get the functioning mode of the compare unit.
04583   * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_GetCompareMode\n
04584   *         TIMxCR        DELCMP4       LL_HRTIM_TIM_GetCompareMode
04585   * @param  HRTIMx High Resolution Timer instance
04586   * @param  Timer This parameter can be one of the following values:
04587   *         @arg @ref LL_HRTIM_TIMER_A
04588   *         @arg @ref LL_HRTIM_TIMER_B
04589   *         @arg @ref LL_HRTIM_TIMER_C
04590   *         @arg @ref LL_HRTIM_TIMER_D
04591   *         @arg @ref LL_HRTIM_TIMER_E
04592   *         @arg @ref LL_HRTIM_TIMER_F
04593   * @param  CompareUnit This parameter can be one of the following values:
04594   *         @arg @ref LL_HRTIM_COMPAREUNIT_2
04595   *         @arg @ref LL_HRTIM_COMPAREUNIT_4
04596   * @retval Mode Returned value can be one of the following values:
04597   *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
04598   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
04599   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
04600   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
04601   */
04602 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
04603 {
04604   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
04605   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
04606                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04607   uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
04608   return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >>  shift);
04609 }
04610
04611 /**
04612   * @brief  Set the timer counter value.
04613   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_SetCounter\n
04614   *         CNTxR        CNTx       LL_HRTIM_TIM_SetCounter
04615   * @note  This function can only be called when the timer is stopped.
04616   * @note  For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
04617   *        significant bits of the counter are not significant. They cannot be
04618   *        written and return 0 when read.
04619   * @note The timer behavior is not guaranteed if the counter value is set above
04620   *       the period.
04621   * @param  HRTIMx High Resolution Timer instance
04622   * @param  Timer This parameter can be one of the following values:
04623   *         @arg @ref LL_HRTIM_TIMER_MASTER
04624   *         @arg @ref LL_HRTIM_TIMER_A
04625   *         @arg @ref LL_HRTIM_TIMER_B
04626   *         @arg @ref LL_HRTIM_TIMER_C
04627   *         @arg @ref LL_HRTIM_TIMER_D
04628   *         @arg @ref LL_HRTIM_TIMER_E
04629   *         @arg @ref LL_HRTIM_TIMER_F
04630   * @param  Counter Value between 0 and 0xFFFF
04631   * @retval None
04632   */
04633 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
04634 {
04635   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04636   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
04637                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04638   MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
04639 }
04640
04641 /**
04642   * @brief  Get actual timer counter value.
04643   * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_GetCounter\n
04644   *         CNTxR        CNTx       LL_HRTIM_TIM_GetCounter
04645   * @param  HRTIMx High Resolution Timer instance
04646   * @param  Timer This parameter can be one of the following values:
04647   *         @arg @ref LL_HRTIM_TIMER_MASTER
04648   *         @arg @ref LL_HRTIM_TIMER_A
04649   *         @arg @ref LL_HRTIM_TIMER_B
04650   *         @arg @ref LL_HRTIM_TIMER_C
04651   *         @arg @ref LL_HRTIM_TIMER_D
04652   *         @arg @ref LL_HRTIM_TIMER_E
04653   *         @arg @ref LL_HRTIM_TIMER_F
04654   * @retval Counter Value between 0 and 0xFFFF
04655   */
04656 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04657 {
04658   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04659   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
04660                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04661   return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
04662 }
04663
04664 /**
04665   * @brief  Set the timer period value.
04666   * @rmtoll MPER        MPER       LL_HRTIM_TIM_SetPeriod\n
04667   *         PERxR       PERx       LL_HRTIM_TIM_SetPeriod
04668   * @param  HRTIMx High Resolution Timer instance
04669   * @param  Timer This parameter can be one of the following values:
04670   *         @arg @ref LL_HRTIM_TIMER_MASTER
04671   *         @arg @ref LL_HRTIM_TIMER_A
04672   *         @arg @ref LL_HRTIM_TIMER_B
04673   *         @arg @ref LL_HRTIM_TIMER_C
04674   *         @arg @ref LL_HRTIM_TIMER_D
04675   *         @arg @ref LL_HRTIM_TIMER_E
04676   *         @arg @ref LL_HRTIM_TIMER_F
04677   * @param  Period Value between 0 and 0xFFFF
04678   * @retval None
04679   */
04680 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
04681 {
04682   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04683   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
04684                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04685   MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
04686 }
04687
04688 /**
04689   * @brief  Get actual timer period value.
04690   * @rmtoll MPER        MPER       LL_HRTIM_TIM_GetPeriod\n
04691   *         PERxR       PERx       LL_HRTIM_TIM_GetPeriod
04692   * @param  HRTIMx High Resolution Timer instance
04693   * @param  Timer This parameter can be one of the following values:
04694   *         @arg @ref LL_HRTIM_TIMER_MASTER
04695   *         @arg @ref LL_HRTIM_TIMER_A
04696   *         @arg @ref LL_HRTIM_TIMER_B
04697   *         @arg @ref LL_HRTIM_TIMER_C
04698   *         @arg @ref LL_HRTIM_TIMER_D
04699   *         @arg @ref LL_HRTIM_TIMER_E
04700   *         @arg @ref LL_HRTIM_TIMER_F
04701   * @retval Period Value between 0 and 0xFFFF
04702   */
04703 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04704 {
04705   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04706   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
04707                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04708   return (READ_BIT(*pReg, HRTIM_MPER_MPER));
04709 }
04710
04711 /**
04712   * @brief  Set the timer repetition period value.
04713   * @rmtoll MREP        MREP       LL_HRTIM_TIM_SetRepetition\n
04714   *         REPxR       REPx       LL_HRTIM_TIM_SetRepetition
04715   * @param  HRTIMx High Resolution Timer instance
04716   * @param  Timer This parameter can be one of the following values:
04717   *         @arg @ref LL_HRTIM_TIMER_MASTER
04718   *         @arg @ref LL_HRTIM_TIMER_A
04719   *         @arg @ref LL_HRTIM_TIMER_B
04720   *         @arg @ref LL_HRTIM_TIMER_C
04721   *         @arg @ref LL_HRTIM_TIMER_D
04722   *         @arg @ref LL_HRTIM_TIMER_E
04723   *         @arg @ref LL_HRTIM_TIMER_F
04724   * @param  Repetition Value between 0 and 0xFF
04725   * @retval None
04726   */
04727 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
04728 {
04729   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04730   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
04731                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04732   MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
04733 }
04734
04735 /**
04736   * @brief  Get actual timer repetition period value.
04737   * @rmtoll MREP        MREP       LL_HRTIM_TIM_GetRepetition\n
04738   *         REPxR       REPx       LL_HRTIM_TIM_GetRepetition
04739   * @param  HRTIMx High Resolution Timer instance
04740   * @param  Timer This parameter can be one of the following values:
04741   *         @arg @ref LL_HRTIM_TIMER_MASTER
04742   *         @arg @ref LL_HRTIM_TIMER_A
04743   *         @arg @ref LL_HRTIM_TIMER_B
04744   *         @arg @ref LL_HRTIM_TIMER_C
04745   *         @arg @ref LL_HRTIM_TIMER_D
04746   *         @arg @ref LL_HRTIM_TIMER_E
04747   *         @arg @ref LL_HRTIM_TIMER_F
04748   * @retval Repetition Value between 0 and 0xFF
04749   */
04750 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04751 {
04752   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04753   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
04754                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04755   return (READ_BIT(*pReg, HRTIM_MREP_MREP));
04756 }
04757
04758 /**
04759   * @brief  Set the compare value of the compare unit 1.
04760   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_SetCompare1\n
04761   *         CMP1xR      CMP1x       LL_HRTIM_TIM_SetCompare1
04762   * @param  HRTIMx High Resolution Timer instance
04763   * @param  Timer This parameter can be one of the following values:
04764   *         @arg @ref LL_HRTIM_TIMER_MASTER
04765   *         @arg @ref LL_HRTIM_TIMER_A
04766   *         @arg @ref LL_HRTIM_TIMER_B
04767   *         @arg @ref LL_HRTIM_TIMER_C
04768   *         @arg @ref LL_HRTIM_TIMER_D
04769   *         @arg @ref LL_HRTIM_TIMER_E
04770   *         @arg @ref LL_HRTIM_TIMER_F
04771   * @param  CompareValue Compare value must be above or equal to 3
04772   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04773   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04774   * @retval None
04775   */
04776 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
04777 {
04778   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04779   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
04780                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04781   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
04782 }
04783
04784 /**
04785   * @brief  Get actual compare value of the compare unit 1.
04786   * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_GetCompare1\n
04787   *         CMP1xR      CMP1x       LL_HRTIM_TIM_GetCompare1
04788   * @param  HRTIMx High Resolution Timer instance
04789   * @param  Timer This parameter can be one of the following values:
04790   *         @arg @ref LL_HRTIM_TIMER_MASTER
04791   *         @arg @ref LL_HRTIM_TIMER_A
04792   *         @arg @ref LL_HRTIM_TIMER_B
04793   *         @arg @ref LL_HRTIM_TIMER_C
04794   *         @arg @ref LL_HRTIM_TIMER_D
04795   *         @arg @ref LL_HRTIM_TIMER_E
04796   *         @arg @ref LL_HRTIM_TIMER_F
04797   * @retval CompareValue Compare value must be above or equal to 3
04798   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04799   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04800   */
04801 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04802 {
04803   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04804   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
04805                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04806   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
04807 }
04808
04809 /**
04810   * @brief  Set the compare value of the compare unit 2.
04811   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_SetCompare2\n
04812   *         CMP2xR      CMP2x       LL_HRTIM_TIM_SetCompare2
04813   * @param  HRTIMx High Resolution Timer instance
04814   * @param  Timer This parameter can be one of the following values:
04815   *         @arg @ref LL_HRTIM_TIMER_MASTER
04816   *         @arg @ref LL_HRTIM_TIMER_A
04817   *         @arg @ref LL_HRTIM_TIMER_B
04818   *         @arg @ref LL_HRTIM_TIMER_C
04819   *         @arg @ref LL_HRTIM_TIMER_D
04820   *         @arg @ref LL_HRTIM_TIMER_E
04821   *         @arg @ref LL_HRTIM_TIMER_F
04822   * @param  CompareValue Compare value must be above or equal to 3
04823   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04824   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04825   * @retval None
04826   */
04827 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
04828 {
04829   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04830   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
04831                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04832   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
04833 }
04834
04835 /**
04836   * @brief  Get actual compare value of the compare unit 2.
04837   * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_GetCompare2\n
04838   *         CMP2xR      CMP2x       LL_HRTIM_TIM_GetCompare2\n
04839   * @param  HRTIMx High Resolution Timer instance
04840   * @param  Timer This parameter can be one of the following values:
04841   *         @arg @ref LL_HRTIM_TIMER_MASTER
04842   *         @arg @ref LL_HRTIM_TIMER_A
04843   *         @arg @ref LL_HRTIM_TIMER_B
04844   *         @arg @ref LL_HRTIM_TIMER_C
04845   *         @arg @ref LL_HRTIM_TIMER_D
04846   *         @arg @ref LL_HRTIM_TIMER_E
04847   *         @arg @ref LL_HRTIM_TIMER_F
04848   * @retval CompareValue Compare value must be above or equal to 3
04849   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04850   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04851   */
04852 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04853 {
04854   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04855   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
04856                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04857   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
04858 }
04859
04860 /**
04861   * @brief  Set the compare value of the compare unit 3.
04862   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_SetCompare3\n
04863   *         CMP3xR      CMP3x       LL_HRTIM_TIM_SetCompare3
04864   * @param  HRTIMx High Resolution Timer instance
04865   * @param  Timer This parameter can be one of the following values:
04866   *         @arg @ref LL_HRTIM_TIMER_MASTER
04867   *         @arg @ref LL_HRTIM_TIMER_A
04868   *         @arg @ref LL_HRTIM_TIMER_B
04869   *         @arg @ref LL_HRTIM_TIMER_C
04870   *         @arg @ref LL_HRTIM_TIMER_D
04871   *         @arg @ref LL_HRTIM_TIMER_E
04872   *         @arg @ref LL_HRTIM_TIMER_F
04873   * @param  CompareValue Compare value must be above or equal to 3
04874   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04875   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04876   * @retval None
04877   */
04878 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
04879 {
04880   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04881   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
04882                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04883   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
04884 }
04885
04886 /**
04887   * @brief  Get actual compare value of the compare unit 3.
04888   * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_GetCompare3\n
04889   *         CMP3xR      CMP3x       LL_HRTIM_TIM_GetCompare3
04890   * @param  HRTIMx High Resolution Timer instance
04891   * @param  Timer This parameter can be one of the following values:
04892   *         @arg @ref LL_HRTIM_TIMER_MASTER
04893   *         @arg @ref LL_HRTIM_TIMER_A
04894   *         @arg @ref LL_HRTIM_TIMER_B
04895   *         @arg @ref LL_HRTIM_TIMER_C
04896   *         @arg @ref LL_HRTIM_TIMER_D
04897   *         @arg @ref LL_HRTIM_TIMER_E
04898   *         @arg @ref LL_HRTIM_TIMER_F
04899   * @retval CompareValue Compare value must be above or equal to 3
04900   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04901   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04902   */
04903 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04904 {
04905   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04906   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
04907                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04908   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
04909 }
04910
04911 /**
04912   * @brief  Set the compare value of the compare unit 4.
04913   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_SetCompare4\n
04914   *         CMP4xR      CMP4x       LL_HRTIM_TIM_SetCompare4
04915   * @param  HRTIMx High Resolution Timer instance
04916   * @param  Timer This parameter can be one of the following values:
04917   *         @arg @ref LL_HRTIM_TIMER_MASTER
04918   *         @arg @ref LL_HRTIM_TIMER_A
04919   *         @arg @ref LL_HRTIM_TIMER_B
04920   *         @arg @ref LL_HRTIM_TIMER_C
04921   *         @arg @ref LL_HRTIM_TIMER_D
04922   *         @arg @ref LL_HRTIM_TIMER_E
04923   *         @arg @ref LL_HRTIM_TIMER_F
04924   * @param  CompareValue Compare value must be above or equal to 3
04925   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04926   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04927   * @retval None
04928   */
04929 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
04930 {
04931   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04932   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
04933                                                               REG_OFFSET_TAB_TIMER[iTimer]));
04934   MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
04935 }
04936
04937 /**
04938   * @brief  Get actual compare value of the compare unit 4.
04939   * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_GetCompare4\n
04940   *         CMP4xR      CMP4x       LL_HRTIM_TIM_GetCompare4
04941   * @param  HRTIMx High Resolution Timer instance
04942   * @param  Timer This parameter can be one of the following values:
04943   *         @arg @ref LL_HRTIM_TIMER_MASTER
04944   *         @arg @ref LL_HRTIM_TIMER_A
04945   *         @arg @ref LL_HRTIM_TIMER_B
04946   *         @arg @ref LL_HRTIM_TIMER_C
04947   *         @arg @ref LL_HRTIM_TIMER_D
04948   *         @arg @ref LL_HRTIM_TIMER_E
04949   *         @arg @ref LL_HRTIM_TIMER_F
04950   * @retval CompareValue Compare value must be above or equal to 3
04951   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
04952   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
04953   */
04954 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
04955 {
04956   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
04957   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
04958                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
04959   return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
04960 }
04961
04962 /**
04963   * @brief  Set the reset trigger of a timer counter.
04964   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_SetResetTrig\n
04965   *         RSTxR      CMP2           LL_HRTIM_TIM_SetResetTrig\n
04966   *         RSTxR      CMP4           LL_HRTIM_TIM_SetResetTrig\n
04967   *         RSTxR      MSTPER         LL_HRTIM_TIM_SetResetTrig\n
04968   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_SetResetTrig\n
04969   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_SetResetTrig\n
04970   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_SetResetTrig\n
04971   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_SetResetTrig\n
04972   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_SetResetTrig\n
04973   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_SetResetTrig\n
04974   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_SetResetTrig\n
04975   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_SetResetTrig\n
04976   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_SetResetTrig\n
04977   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_SetResetTrig\n
04978   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_SetResetTrig\n
04979   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_SetResetTrig\n
04980   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_SetResetTrig\n
04981   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_SetResetTrig\n
04982   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_SetResetTrig\n
04983   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_SetResetTrig\n
04984   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_SetResetTrig\n
04985   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_SetResetTrig\n
04986   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_SetResetTrig\n
04987   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_SetResetTrig\n
04988   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_SetResetTrig\n
04989   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_SetResetTrig\n
04990   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_SetResetTrig\n
04991   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_SetResetTrig\n
04992   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_SetResetTrig\n
04993   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_SetResetTrig\n
04994   *         RSTxR      TIMFCMP1       LL_HRTIM_TIM_SetResetTrig\n
04995   *         RSTxR      TIMFCMP2       LL_HRTIM_TIM_SetResetTrig
04996   * @note The reset of the timer counter can be triggered by up to 30 events
04997   *       that can be selected among the following sources:
04998   *         @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
04999   *         @arg The master timer: Reset and Compare 1..4 (5 events).
05000   *         @arg The external events EXTEVNT1..10 (10 events).
05001   *         @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
05002   * @param  HRTIMx High Resolution Timer instance
05003   * @param  Timer This parameter can be one of the following values:
05004   *         @arg @ref LL_HRTIM_TIMER_A
05005   *         @arg @ref LL_HRTIM_TIMER_B
05006   *         @arg @ref LL_HRTIM_TIMER_C
05007   *         @arg @ref LL_HRTIM_TIMER_D
05008   *         @arg @ref LL_HRTIM_TIMER_E
05009   *         @arg @ref LL_HRTIM_TIMER_F
05010   * @param  ResetTrig This parameter can be a combination of the following values:
05011   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
05012   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
05013   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
05014   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
05015   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
05016   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
05017   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
05018   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
05019   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
05020   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
05021   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
05022   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
05023   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
05024   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
05025   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
05026   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
05027   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
05028   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
05029   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
05030   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
05031   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
05032   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
05033   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
05034   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
05035   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
05036   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
05037   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
05038   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
05039   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
05040   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
05041   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
05042   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
05043   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
05044   * @retval None
05045   */
05046 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
05047 {
05048   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05049   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
05050                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05051   WRITE_REG(*pReg, ResetTrig);
05052 }
05053
05054 /**
05055   * @brief  Get actual reset trigger of a timer counter.
05056   * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_GetResetTrig\n
05057   *         RSTxR      CMP2           LL_HRTIM_TIM_GetResetTrig\n
05058   *         RSTxR      CMP4           LL_HRTIM_TIM_GetResetTrig\n
05059   *         RSTxR      MSTPER         LL_HRTIM_TIM_GetResetTrig\n
05060   *         RSTxR      MSTCMP1        LL_HRTIM_TIM_GetResetTrig\n
05061   *         RSTxR      MSTCMP2        LL_HRTIM_TIM_GetResetTrig\n
05062   *         RSTxR      MSTCMP3        LL_HRTIM_TIM_GetResetTrig\n
05063   *         RSTxR      MSTCMP4        LL_HRTIM_TIM_GetResetTrig\n
05064   *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_GetResetTrig\n
05065   *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_GetResetTrig\n
05066   *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_GetResetTrig\n
05067   *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_GetResetTrig\n
05068   *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_GetResetTrig\n
05069   *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_GetResetTrig\n
05070   *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_GetResetTrig\n
05071   *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_GetResetTrig\n
05072   *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_GetResetTrig\n
05073   *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_GetResetTrig\n
05074   *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_GetResetTrig\n
05075   *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_GetResetTrig\n
05076   *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_GetResetTrig\n
05077   *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_GetResetTrig\n
05078   *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_GetResetTrig\n
05079   *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_GetResetTrig\n
05080   *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_GetResetTrig\n
05081   *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_GetResetTrig\n
05082   *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_GetResetTrig\n
05083   *         RSTxR      TIMECMP1       LL_HRTIM_TIM_GetResetTrig\n
05084   *         RSTxR      TIMECMP2       LL_HRTIM_TIM_GetResetTrig\n
05085   *         RSTxR      TIMECMP4       LL_HRTIM_TIM_GetResetTrig\n
05086   *         RSTxR      TIMFCMP1       LL_HRTIM_TIM_GetResetTrig\n
05087   *         RSTxR      TIMFCMP2       LL_HRTIM_TIM_GetResetTrig
05088   * @param  HRTIMx High Resolution Timer instance
05089   * @param  Timer This parameter can be one of the following values:
05090   *         @arg @ref LL_HRTIM_TIMER_A
05091   *         @arg @ref LL_HRTIM_TIMER_B
05092   *         @arg @ref LL_HRTIM_TIMER_C
05093   *         @arg @ref LL_HRTIM_TIMER_D
05094   *         @arg @ref LL_HRTIM_TIMER_E
05095   *         @arg @ref LL_HRTIM_TIMER_F
05096   * @retval ResetTrig Returned value can be one of the following values:
05097   *         @arg @ref LL_HRTIM_RESETTRIG_NONE
05098   *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
05099   *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
05100   *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
05101   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
05102   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
05103   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
05104   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
05105   *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
05106   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
05107   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
05108   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
05109   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
05110   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
05111   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
05112   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
05113   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
05114   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
05115   *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
05116   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
05117   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
05118   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
05119   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
05120   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
05121   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
05122   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
05123   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
05124   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
05125   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
05126   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
05127   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
05128   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
05129   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
05130   */
05131 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05132 {
05133   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05134   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
05135                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05136   return (READ_REG(*pReg));
05137 }
05138
05139 /**
05140   * @brief  Get captured value for capture unit 1.
05141   * @rmtoll CPT1xR      CPT1x           LL_HRTIM_TIM_GetCapture1
05142   * @param  HRTIMx High Resolution Timer instance
05143   * @param  Timer This parameter can be one of the following values:
05144   *         @arg @ref LL_HRTIM_TIMER_A
05145   *         @arg @ref LL_HRTIM_TIMER_B
05146   *         @arg @ref LL_HRTIM_TIMER_C
05147   *         @arg @ref LL_HRTIM_TIMER_D
05148   *         @arg @ref LL_HRTIM_TIMER_E
05149   *         @arg @ref LL_HRTIM_TIMER_F
05150   * @retval Captured value
05151   */
05152 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05153 {
05154   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05155   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
05156                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05157   return (READ_REG(*pReg));
05158 }
05159
05160 /**
05161   * @brief  Get the counting direction when capture 1 event occurred.
05162   * @rmtoll CPT1xR      DIR           LL_HRTIM_TIM_GetCapture1Direction
05163   * @param  HRTIMx High Resolution Timer instance
05164   * @param  Timer This parameter can be one of the following values:
05165   *         @arg @ref LL_HRTIM_TIMER_A
05166   *         @arg @ref LL_HRTIM_TIMER_B
05167   *         @arg @ref LL_HRTIM_TIMER_C
05168   *         @arg @ref LL_HRTIM_TIMER_D
05169   *         @arg @ref LL_HRTIM_TIMER_E
05170   *         @arg @ref LL_HRTIM_TIMER_F
05171   * @retval Filter This parameter can be one of the following values:
05172   *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP
05173   *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP_DOWN
05174   */
05175 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05176 {
05177   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05178   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
05179                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05180   return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
05181 }
05182
05183 /**
05184   * @brief  Get captured value for capture unit 2.
05185   * @rmtoll CPT2xR      CPT2x           LL_HRTIM_TIM_GetCapture2
05186   * @param  HRTIMx High Resolution Timer instance
05187   * @param  Timer This parameter can be one of the following values:
05188   *         @arg @ref LL_HRTIM_TIMER_A
05189   *         @arg @ref LL_HRTIM_TIMER_B
05190   *         @arg @ref LL_HRTIM_TIMER_C
05191   *         @arg @ref LL_HRTIM_TIMER_D
05192   *         @arg @ref LL_HRTIM_TIMER_E
05193   *         @arg @ref LL_HRTIM_TIMER_F
05194   * @retval Captured value
05195   */
05196 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05197 {
05198   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05199   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
05200                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05201   return (READ_REG(*pReg));
05202 }
05203
05204 /**
05205   * @brief  Get the counting direction when capture 2 event occurred.
05206   * @rmtoll CPT2xR      DIR           LL_HRTIM_TIM_GetCapture2Direction
05207   * @param  HRTIMx High Resolution Timer instance
05208   * @param  Timer This parameter can be one of the following values:
05209   *         @arg @ref LL_HRTIM_TIMER_A
05210   *         @arg @ref LL_HRTIM_TIMER_B
05211   *         @arg @ref LL_HRTIM_TIMER_C
05212   *         @arg @ref LL_HRTIM_TIMER_D
05213   *         @arg @ref LL_HRTIM_TIMER_E
05214   *         @arg @ref LL_HRTIM_TIMER_F
05215   * @retval Filter This parameter can be one of the following values:
05216   *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP
05217   *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP_DOWN
05218   */
05219 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05220 {
05221   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05222   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
05223                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05224   return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
05225 }
05226
05227 /**
05228   * @brief  Set the trigger of a capture unit for a given timer.
05229   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_SetCaptureTrig\n
05230   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_SetCaptureTrig\n
05231   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05232   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05233   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05234   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05235   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05236   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05237   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05238   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05239   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_SetCaptureTrig\n
05240   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_SetCaptureTrig\n
05241   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05242   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05243   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05244   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_SetCaptureTrig\n
05245   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05246   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05247   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05248   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
05249   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05250   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05251   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05252   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
05253   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05254   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05255   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05256   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
05257   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05258   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05259   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05260   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_SetCaptureTrig\n
05261   *         CPT1xCR      TF1SET           LL_HRTIM_TIM_SetCaptureTrig\n
05262   *         CPT1xCR      TF1RST           LL_HRTIM_TIM_SetCaptureTrig\n
05263   *         CPT1xCR      TFCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
05264   *         CPT1xCR      TFCMP2           LL_HRTIM_TIM_SetCaptureTrig
05265   * @param  HRTIMx High Resolution Timer instance
05266   * @param  Timer This parameter can be one of the following values:
05267   *         @arg @ref LL_HRTIM_TIMER_A
05268   *         @arg @ref LL_HRTIM_TIMER_B
05269   *         @arg @ref LL_HRTIM_TIMER_C
05270   *         @arg @ref LL_HRTIM_TIMER_D
05271   *         @arg @ref LL_HRTIM_TIMER_E
05272   *         @arg @ref LL_HRTIM_TIMER_F
05273   * @param  CaptureUnit This parameter can be one of the following values:
05274   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
05275   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
05276   * @param  CaptureTrig This parameter can be a combination of the following values:
05277   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
05278   *         @arg @ref LL_HRTIM_CAPTURETRIG_SW
05279   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
05280   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
05281   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
05282   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
05283   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
05284   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
05285   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
05286   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
05287   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
05288   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
05289   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
05290   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
05291   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
05292   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
05293   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
05294   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
05295   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
05296   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
05297   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
05298   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
05299   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
05300   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
05301   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
05302   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
05303   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
05304   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
05305   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
05306   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
05307   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
05308   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
05309   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
05310   *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
05311   *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
05312   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
05313   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
05314   * @retval None
05315   */
05316 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
05317                                                  uint64_t CaptureTrig)
05318 {
05319   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05320   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
05321                                                               REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
05322
05323   uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
05324   uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
05325
05326   cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
05327
05328   WRITE_REG(*pReg, (cfg1 | cfg2));
05329
05330 }
05331
05332 /**
05333   * @brief  Get actual trigger of a capture unit for a given timer.
05334   * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_GetCaptureTrig\n
05335   *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_GetCaptureTrig\n
05336   *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05337   *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05338   *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05339   *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05340   *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05341   *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05342   *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05343   *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05344   *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_GetCaptureTrig\n
05345   *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_GetCaptureTrig\n
05346   *         CPT1xCR      TA1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05347   *         CPT1xCR      TA1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05348   *         CPT1xCR      TACMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05349   *         CPT1xCR      TACMP2           LL_HRTIM_TIM_GetCaptureTrig\n
05350   *         CPT1xCR      TB1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05351   *         CPT1xCR      TB1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05352   *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05353   *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
05354   *         CPT1xCR      TC1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05355   *         CPT1xCR      TC1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05356   *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05357   *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
05358   *         CPT1xCR      TD1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05359   *         CPT1xCR      TD1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05360   *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05361   *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
05362   *         CPT1xCR      TE1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05363   *         CPT1xCR      TE1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05364   *         CPT1xCR      TECMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05365   *         CPT1xCR      TECMP2           LL_HRTIM_TIM_GetCaptureTrig\n
05366   *         CPT1xCR      TF1SET           LL_HRTIM_TIM_GetCaptureTrig\n
05367   *         CPT1xCR      TF1RST           LL_HRTIM_TIM_GetCaptureTrig\n
05368   *         CPT1xCR      TFCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
05369   *         CPT1xCR      TFCMP2           LL_HRTIM_TIM_GetCaptureTrig
05370   * @param  HRTIMx High Resolution Timer instance
05371   * @param  Timer This parameter can be one of the following values:
05372   *         @arg @ref LL_HRTIM_TIMER_A
05373   *         @arg @ref LL_HRTIM_TIMER_B
05374   *         @arg @ref LL_HRTIM_TIMER_C
05375   *         @arg @ref LL_HRTIM_TIMER_D
05376   *         @arg @ref LL_HRTIM_TIMER_E
05377   *         @arg @ref LL_HRTIM_TIMER_F
05378   * @param  CaptureUnit This parameter can be one of the following values:
05379   *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
05380   *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
05381   * @retval CaptureTrig This parameter can be a combination of the following values:
05382   *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
05383   *         @arg @ref LL_HRTIM_CAPTURETRIG_SW
05384   *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
05385   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
05386   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
05387   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
05388   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
05389   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
05390   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
05391   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
05392   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
05393   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
05394   *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
05395   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
05396   *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
05397   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
05398   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
05399   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
05400   *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
05401   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
05402   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
05403   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
05404   *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
05405   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
05406   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
05407   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
05408   *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
05409   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
05410   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
05411   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
05412   *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
05413   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
05414   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
05415   *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
05416   *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
05417   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
05418   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
05419   */
05420 __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
05421 {
05422   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05423   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
05424                                                                     (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
05425
05426   uint64_t cfg;
05427   uint32_t CaptureTrig = READ_REG(*pReg);
05428
05429   cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
05430
05431   return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
05432 }
05433
05434 /**
05435   * @brief  Enable deadtime insertion for a given timer.
05436   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_EnableDeadTime
05437   * @param  HRTIMx High Resolution Timer instance
05438   * @param  Timer This parameter can be one of the following values:
05439   *         @arg @ref LL_HRTIM_TIMER_A
05440   *         @arg @ref LL_HRTIM_TIMER_B
05441   *         @arg @ref LL_HRTIM_TIMER_C
05442   *         @arg @ref LL_HRTIM_TIMER_D
05443   *         @arg @ref LL_HRTIM_TIMER_E
05444   *         @arg @ref LL_HRTIM_TIMER_F
05445   * @retval None
05446   */
05447 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05448 {
05449   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05450   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05451                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05452   SET_BIT(*pReg, HRTIM_OUTR_DTEN);
05453 }
05454
05455 /**
05456   * @brief  Disable deadtime insertion for a given timer.
05457   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_DisableDeadTime
05458   * @param  HRTIMx High Resolution Timer instance
05459   * @param  Timer This parameter can be one of the following values:
05460   *         @arg @ref LL_HRTIM_TIMER_A
05461   *         @arg @ref LL_HRTIM_TIMER_B
05462   *         @arg @ref LL_HRTIM_TIMER_C
05463   *         @arg @ref LL_HRTIM_TIMER_D
05464   *         @arg @ref LL_HRTIM_TIMER_E
05465   *         @arg @ref LL_HRTIM_TIMER_F
05466   * @retval None
05467   */
05468 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05469 {
05470   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05471   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05472                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05473   CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
05474 }
05475
05476 /**
05477   * @brief  Indicate whether deadtime insertion is enabled for a given timer.
05478   * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_IsEnabledDeadTime
05479   * @param  HRTIMx High Resolution Timer instance
05480   * @param  Timer This parameter can be one of the following values:
05481   *         @arg @ref LL_HRTIM_TIMER_A
05482   *         @arg @ref LL_HRTIM_TIMER_B
05483   *         @arg @ref LL_HRTIM_TIMER_C
05484   *         @arg @ref LL_HRTIM_TIMER_D
05485   *         @arg @ref LL_HRTIM_TIMER_E
05486   *         @arg @ref LL_HRTIM_TIMER_F
05487   * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
05488   */
05489 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05490 {
05491   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05492   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05493                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05494
05495   return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
05496 }
05497
05498 /**
05499   * @brief  Set the delayed protection (DLYPRT) mode.
05500   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_SetDLYPRTMode\n
05501   *         OUTxR      DLYPRT         LL_HRTIM_TIM_SetDLYPRTMode
05502   * @note   This function must be called prior enabling the delayed protection
05503   * @note   Balanced Idle mode is only available in push-pull mode
05504   * @param  HRTIMx High Resolution Timer instance
05505   * @param  Timer This parameter can be one of the following values:
05506   *         @arg @ref LL_HRTIM_TIMER_A
05507   *         @arg @ref LL_HRTIM_TIMER_B
05508   *         @arg @ref LL_HRTIM_TIMER_C
05509   *         @arg @ref LL_HRTIM_TIMER_D
05510   *         @arg @ref LL_HRTIM_TIMER_E
05511   *         @arg @ref LL_HRTIM_TIMER_F
05512   * @param  DLYPRTMode Delayed protection (DLYPRT) mode
05513   *
05514   *         For timers A, B and C this parameter can be one of the following values:
05515   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
05516   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
05517   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
05518   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
05519   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
05520   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
05521   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
05522   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
05523   *
05524   *         For timers D, E and F this parameter can be one of the following values:
05525   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
05526   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
05527   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
05528   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
05529   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
05530   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
05531   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
05532   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
05533   * @retval None
05534   */
05535 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
05536 {
05537   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05538   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05539                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05540   MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
05541 }
05542
05543 /**
05544   * @brief  Get the delayed protection (DLYPRT) mode.
05545   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_GetDLYPRTMode\n
05546   *         OUTxR      DLYPRT         LL_HRTIM_TIM_GetDLYPRTMode
05547   * @param  HRTIMx High Resolution Timer instance
05548   * @param  Timer This parameter can be one of the following values:
05549   *         @arg @ref LL_HRTIM_TIMER_A
05550   *         @arg @ref LL_HRTIM_TIMER_B
05551   *         @arg @ref LL_HRTIM_TIMER_C
05552   *         @arg @ref LL_HRTIM_TIMER_D
05553   *         @arg @ref LL_HRTIM_TIMER_E
05554   *         @arg @ref LL_HRTIM_TIMER_F
05555   * @retval DLYPRTMode Delayed protection (DLYPRT) mode
05556   *
05557   *         For timers A, B and C this parameter can be one of the following values:
05558   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
05559   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
05560   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
05561   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
05562   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
05563   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
05564   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
05565   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
05566   *
05567   *         For timers D, E and F this parameter can be one of the following values:
05568   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
05569   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
05570   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
05571   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
05572   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
05573   *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
05574   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
05575   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
05576   */
05577 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05578 {
05579   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05580   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05581                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05582   return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
05583 }
05584
05585 /**
05586   * @brief  Enable delayed protection (DLYPRT) for a given timer.
05587   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_EnableDLYPRT
05588   * @note   This function must not be called once the concerned timer is enabled
05589   * @param  HRTIMx High Resolution Timer instance
05590   * @param  Timer This parameter can be one of the following values:
05591   *         @arg @ref LL_HRTIM_TIMER_A
05592   *         @arg @ref LL_HRTIM_TIMER_B
05593   *         @arg @ref LL_HRTIM_TIMER_C
05594   *         @arg @ref LL_HRTIM_TIMER_D
05595   *         @arg @ref LL_HRTIM_TIMER_E
05596   *         @arg @ref LL_HRTIM_TIMER_F
05597   * @retval None
05598   */
05599 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05600 {
05601   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05602   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05603                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05604   SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
05605 }
05606
05607 /**
05608   * @brief  Disable delayed protection (DLYPRT) for a given timer.
05609   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_DisableDLYPRT
05610   * @note   This function must not be called once the concerned timer is enabled
05611   * @param  HRTIMx High Resolution Timer instance
05612   * @param  Timer This parameter can be one of the following values:
05613   *         @arg @ref LL_HRTIM_TIMER_A
05614   *         @arg @ref LL_HRTIM_TIMER_B
05615   *         @arg @ref LL_HRTIM_TIMER_C
05616   *         @arg @ref LL_HRTIM_TIMER_D
05617   *         @arg @ref LL_HRTIM_TIMER_E
05618   *         @arg @ref LL_HRTIM_TIMER_F
05619   * @retval None
05620   */
05621 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05622 {
05623   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05624   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05625                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05626   CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
05627 }
05628
05629 /**
05630   * @brief  Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
05631   * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_IsEnabledDLYPRT
05632   * @param  HRTIMx High Resolution Timer instance
05633   * @param  Timer This parameter can be one of the following values:
05634   *         @arg @ref LL_HRTIM_TIMER_A
05635   *         @arg @ref LL_HRTIM_TIMER_B
05636   *         @arg @ref LL_HRTIM_TIMER_C
05637   *         @arg @ref LL_HRTIM_TIMER_D
05638   *         @arg @ref LL_HRTIM_TIMER_E
05639   *         @arg @ref LL_HRTIM_TIMER_F
05640   * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
05641   */
05642 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05643 {
05644   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05645   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05646                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05647   return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
05648 }
05649
05650 /**
05651   * @brief  Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
05652   * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_EnableBIAR
05653   * @note   This function must not be called once the concerned timer is enabled
05654   * @param  HRTIMx High Resolution Timer instance
05655   * @param  Timer This parameter can be one of the following values:
05656   *         @arg @ref LL_HRTIM_TIMER_A
05657   *         @arg @ref LL_HRTIM_TIMER_B
05658   *         @arg @ref LL_HRTIM_TIMER_C
05659   *         @arg @ref LL_HRTIM_TIMER_D
05660   *         @arg @ref LL_HRTIM_TIMER_E
05661   *         @arg @ref LL_HRTIM_TIMER_F
05662   * @retval None
05663   */
05664 __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05665 {
05666   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05667   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05668                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05669   SET_BIT(*pReg, HRTIM_OUTR_BIAR);
05670 }
05671
05672 /**
05673   * @brief  Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
05674   * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_DisableBIAR
05675   * @note   This function must not be called once the concerned timer is enabled
05676   * @param  HRTIMx High Resolution Timer instance
05677   * @param  Timer This parameter can be one of the following values:
05678   *         @arg @ref LL_HRTIM_TIMER_A
05679   *         @arg @ref LL_HRTIM_TIMER_B
05680   *         @arg @ref LL_HRTIM_TIMER_C
05681   *         @arg @ref LL_HRTIM_TIMER_D
05682   *         @arg @ref LL_HRTIM_TIMER_E
05683   *         @arg @ref LL_HRTIM_TIMER_F
05684   * @retval None
05685   */
05686 __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05687 {
05688   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05689   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
05690                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05691   CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
05692 }
05693
05694 /**
05695   * @brief  Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
05696   * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_IsEnabledBIAR
05697   * @param  HRTIMx High Resolution Timer instance
05698   * @param  Timer This parameter can be one of the following values:
05699   *         @arg @ref LL_HRTIM_TIMER_A
05700   *         @arg @ref LL_HRTIM_TIMER_B
05701   *         @arg @ref LL_HRTIM_TIMER_C
05702   *         @arg @ref LL_HRTIM_TIMER_D
05703   *         @arg @ref LL_HRTIM_TIMER_E
05704   *         @arg @ref LL_HRTIM_TIMER_F
05705   * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
05706   */
05707 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05708 {
05709   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05710   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
05711                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05712
05713   return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
05714 }
05715
05716 /**
05717   * @brief  Enable the fault channel(s) for a given timer.
05718   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_EnableFault\n
05719   *         FLTxR      FLT2EN       LL_HRTIM_TIM_EnableFault\n
05720   *         FLTxR      FLT3EN       LL_HRTIM_TIM_EnableFault\n
05721   *         FLTxR      FLT4EN       LL_HRTIM_TIM_EnableFault\n
05722   *         FLTxR      FLT5EN       LL_HRTIM_TIM_EnableFault\n
05723   *         FLTxR      FLT6EN       LL_HRTIM_TIM_EnableFault
05724   * @param  HRTIMx High Resolution Timer instance
05725   * @param  Timer This parameter can be one of the following values:
05726   *         @arg @ref LL_HRTIM_TIMER_A
05727   *         @arg @ref LL_HRTIM_TIMER_B
05728   *         @arg @ref LL_HRTIM_TIMER_C
05729   *         @arg @ref LL_HRTIM_TIMER_D
05730   *         @arg @ref LL_HRTIM_TIMER_E
05731   *         @arg @ref LL_HRTIM_TIMER_F
05732   * @param  Faults This parameter can be a combination of the following values:
05733   *         @arg @ref LL_HRTIM_FAULT_1
05734   *         @arg @ref LL_HRTIM_FAULT_2
05735   *         @arg @ref LL_HRTIM_FAULT_3
05736   *         @arg @ref LL_HRTIM_FAULT_4
05737   *         @arg @ref LL_HRTIM_FAULT_5
05738   *         @arg @ref LL_HRTIM_FAULT_6
05739   * @retval None
05740   */
05741 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
05742 {
05743   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05744   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
05745                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05746   SET_BIT(*pReg, Faults);
05747 }
05748
05749 /**
05750   * @brief  Disable the fault channel(s) for a given timer.
05751   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_DisableFault\n
05752   *         FLTxR      FLT2EN       LL_HRTIM_TIM_DisableFault\n
05753   *         FLTxR      FLT3EN       LL_HRTIM_TIM_DisableFault\n
05754   *         FLTxR      FLT4EN       LL_HRTIM_TIM_DisableFault\n
05755   *         FLTxR      FLT5EN       LL_HRTIM_TIM_DisableFault\n
05756   *         FLTxR      FLT6EN       LL_HRTIM_TIM_DisableFault
05757   * @param  HRTIMx High Resolution Timer instance
05758   * @param  Timer This parameter can be one of the following values:
05759   *         @arg @ref LL_HRTIM_TIMER_A
05760   *         @arg @ref LL_HRTIM_TIMER_B
05761   *         @arg @ref LL_HRTIM_TIMER_C
05762   *         @arg @ref LL_HRTIM_TIMER_D
05763   *         @arg @ref LL_HRTIM_TIMER_E
05764   *         @arg @ref LL_HRTIM_TIMER_F
05765   * @param  Faults This parameter can be a combination of the following values:
05766   *         @arg @ref LL_HRTIM_FAULT_1
05767   *         @arg @ref LL_HRTIM_FAULT_2
05768   *         @arg @ref LL_HRTIM_FAULT_3
05769   *         @arg @ref LL_HRTIM_FAULT_4
05770   *         @arg @ref LL_HRTIM_FAULT_5
05771   *         @arg @ref LL_HRTIM_FAULT_6
05772   * @retval None
05773   */
05774 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
05775 {
05776   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05777   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
05778                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05779   CLEAR_BIT(*pReg, Faults);
05780 }
05781
05782 /**
05783   * @brief  Indicate whether the fault channel is enabled for a given timer.
05784   * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_IsEnabledFault\n
05785   *         FLTxR      FLT2EN       LL_HRTIM_TIM_IsEnabledFault\n
05786   *         FLTxR      FLT3EN       LL_HRTIM_TIM_IsEnabledFault\n
05787   *         FLTxR      FLT4EN       LL_HRTIM_TIM_IsEnabledFault\n
05788   *         FLTxR      FLT5EN       LL_HRTIM_TIM_IsEnabledFault\n
05789   *         FLTxR      FLT6EN       LL_HRTIM_TIM_IsEnabledFault
05790   * @param  HRTIMx High Resolution Timer instance
05791   * @param  Timer This parameter can be one of the following values:
05792   *         @arg @ref LL_HRTIM_TIMER_A
05793   *         @arg @ref LL_HRTIM_TIMER_B
05794   *         @arg @ref LL_HRTIM_TIMER_C
05795   *         @arg @ref LL_HRTIM_TIMER_D
05796   *         @arg @ref LL_HRTIM_TIMER_E
05797   *         @arg @ref LL_HRTIM_TIMER_F
05798   * @param  Fault This parameter can be one of the following values:
05799   *         @arg @ref LL_HRTIM_FAULT_1
05800   *         @arg @ref LL_HRTIM_FAULT_2
05801   *         @arg @ref LL_HRTIM_FAULT_3
05802   *         @arg @ref LL_HRTIM_FAULT_4
05803   *         @arg @ref LL_HRTIM_FAULT_5
05804   *         @arg @ref LL_HRTIM_FAULT_6
05805   * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
05806   */
05807 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
05808 {
05809   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05810   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
05811                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
05812
05813   return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
05814 }
05815
05816 /**
05817   * @brief  Lock the fault conditioning set-up for a given timer.
05818   * @rmtoll FLTxR      FLTLCK       LL_HRTIM_TIM_LockFault
05819   * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
05820   * @param  HRTIMx High Resolution Timer instance
05821   * @param  Timer This parameter can be one of the following values:
05822   *         @arg @ref LL_HRTIM_TIMER_A
05823   *         @arg @ref LL_HRTIM_TIMER_B
05824   *         @arg @ref LL_HRTIM_TIMER_C
05825   *         @arg @ref LL_HRTIM_TIMER_D
05826   *         @arg @ref LL_HRTIM_TIMER_E
05827   *         @arg @ref LL_HRTIM_TIMER_F
05828   * @retval None
05829   */
05830 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05831 {
05832   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
05833   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
05834                                                               REG_OFFSET_TAB_TIMER[iTimer]));
05835   SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
05836 }
05837
05838 /**
05839   * @brief  Define how the timer behaves during a burst mode operation.
05840   * @rmtoll BMCR      MTBM       LL_HRTIM_TIM_SetBurstModeOption\n
05841   *         BMCR      TABM       LL_HRTIM_TIM_SetBurstModeOption\n
05842   *         BMCR      TBBM       LL_HRTIM_TIM_SetBurstModeOption\n
05843   *         BMCR      TCBM       LL_HRTIM_TIM_SetBurstModeOption\n
05844   *         BMCR      TDBM       LL_HRTIM_TIM_SetBurstModeOption\n
05845   *         BMCR      TEBM       LL_HRTIM_TIM_SetBurstModeOption\n
05846   *         BMCR      TFBM       LL_HRTIM_TIM_SetBurstModeOption
05847   * @note This function must not be called when the burst mode is enabled
05848   * @param  HRTIMx High Resolution Timer instance
05849   * @param  Timer This parameter can be one of the following values:
05850   *         @arg @ref LL_HRTIM_TIMER_MASTER
05851   *         @arg @ref LL_HRTIM_TIMER_A
05852   *         @arg @ref LL_HRTIM_TIMER_B
05853   *         @arg @ref LL_HRTIM_TIMER_C
05854   *         @arg @ref LL_HRTIM_TIMER_D
05855   *         @arg @ref LL_HRTIM_TIMER_E
05856   *         @arg @ref LL_HRTIM_TIMER_F
05857   * @param  BurtsModeOption This parameter can be one of the following values:
05858   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
05859   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
05860   * @retval None
05861   */
05862 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
05863 {
05864   uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
05865   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
05866 }
05867
05868 /**
05869   * @brief  Retrieve how the timer behaves during a burst mode operation.
05870   * @rmtoll BMCR      MCR        LL_HRTIM_TIM_GetBurstModeOption\n
05871   *         BMCR      TABM       LL_HRTIM_TIM_GetBurstModeOption\n
05872   *         BMCR      TBBM       LL_HRTIM_TIM_GetBurstModeOption\n
05873   *         BMCR      TCBM       LL_HRTIM_TIM_GetBurstModeOption\n
05874   *         BMCR      TDBM       LL_HRTIM_TIM_GetBurstModeOption\n
05875   *         BMCR      TEBM       LL_HRTIM_TIM_GetBurstModeOption\n
05876   *         BMCR      TFBM       LL_HRTIM_TIM_GetBurstModeOption
05877   * @param  HRTIMx High Resolution Timer instance
05878   * @param  Timer This parameter can be one of the following values:
05879   *         @arg @ref LL_HRTIM_TIMER_MASTER
05880   *         @arg @ref LL_HRTIM_TIMER_A
05881   *         @arg @ref LL_HRTIM_TIMER_B
05882   *         @arg @ref LL_HRTIM_TIMER_C
05883   *         @arg @ref LL_HRTIM_TIMER_D
05884   *         @arg @ref LL_HRTIM_TIMER_E
05885   *         @arg @ref LL_HRTIM_TIMER_F
05886   * @retval BurtsMode This parameter can be one of the following values:
05887   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
05888   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
05889   */
05890 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
05891 {
05892   uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
05893   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
05894 }
05895
05896 /**
05897   * @brief  Program which registers are to be written by Burst DMA transfers.
05898   * @rmtoll BDMUPDR      MTBM        LL_HRTIM_TIM_ConfigBurstDMA\n
05899   *         BDMUPDR      MICR        LL_HRTIM_TIM_ConfigBurstDMA\n
05900   *         BDMUPDR      MDIER       LL_HRTIM_TIM_ConfigBurstDMA\n
05901   *         BDMUPDR      MCNT        LL_HRTIM_TIM_ConfigBurstDMA\n
05902   *         BDMUPDR      MPER        LL_HRTIM_TIM_ConfigBurstDMA\n
05903   *         BDMUPDR      MREP        LL_HRTIM_TIM_ConfigBurstDMA\n
05904   *         BDMUPDR      MCMP1       LL_HRTIM_TIM_ConfigBurstDMA\n
05905   *         BDMUPDR      MCMP2       LL_HRTIM_TIM_ConfigBurstDMA\n
05906   *         BDMUPDR      MCMP3       LL_HRTIM_TIM_ConfigBurstDMA\n
05907   *         BDMUPDR      MCMP4       LL_HRTIM_TIM_ConfigBurstDMA\n
05908   *         BDTxUPDR     TIMxCR      LL_HRTIM_TIM_ConfigBurstDMA\n
05909   *         BDTxUPDR     TIMxICR     LL_HRTIM_TIM_ConfigBurstDMA\n
05910   *         BDTxUPDR     TIMxDIER    LL_HRTIM_TIM_ConfigBurstDMA\n
05911   *         BDTxUPDR     TIMxCNT     LL_HRTIM_TIM_ConfigBurstDMA\n
05912   *         BDTxUPDR     TIMxPER     LL_HRTIM_TIM_ConfigBurstDMA\n
05913   *         BDTxUPDR     TIMxREP     LL_HRTIM_TIM_ConfigBurstDMA\n
05914   *         BDTxUPDR     TIMxCMP1    LL_HRTIM_TIM_ConfigBurstDMA\n
05915   *         BDTxUPDR     TIMxCMP2    LL_HRTIM_TIM_ConfigBurstDMA\n
05916   *         BDTxUPDR     TIMxCMP3    LL_HRTIM_TIM_ConfigBurstDMA\n
05917   *         BDTxUPDR     TIMxCMP4    LL_HRTIM_TIM_ConfigBurstDMA\n
05918   *         BDTxUPDR     TIMxDTR     LL_HRTIM_TIM_ConfigBurstDMA\n
05919   *         BDTxUPDR     TIMxSET1R   LL_HRTIM_TIM_ConfigBurstDMA\n
05920   *         BDTxUPDR     TIMxRST1R   LL_HRTIM_TIM_ConfigBurstDMA\n
05921   *         BDTxUPDR     TIMxSET2R   LL_HRTIM_TIM_ConfigBurstDMA\n
05922   *         BDTxUPDR     TIMxRST2R   LL_HRTIM_TIM_ConfigBurstDMA\n
05923   *         BDTxUPDR     TIMxEEFR1   LL_HRTIM_TIM_ConfigBurstDMA\n
05924   *         BDTxUPDR     TIMxEEFR2   LL_HRTIM_TIM_ConfigBurstDMA\n
05925   *         BDTxUPDR     TIMxRSTR    LL_HRTIM_TIM_ConfigBurstDMA\n
05926   *         BDTxUPDR     TIMxOUTR    LL_HRTIM_TIM_ConfigBurstDMA\n
05927   *         BDTxUPDR     TIMxLTCH    LL_HRTIM_TIM_ConfigBurstDMA
05928   * @param  HRTIMx High Resolution Timer instance
05929   * @param  Timer This parameter can be one of the following values:
05930   *         @arg @ref LL_HRTIM_TIMER_MASTER
05931   *         @arg @ref LL_HRTIM_TIMER_A
05932   *         @arg @ref LL_HRTIM_TIMER_B
05933   *         @arg @ref LL_HRTIM_TIMER_C
05934   *         @arg @ref LL_HRTIM_TIMER_D
05935   *         @arg @ref LL_HRTIM_TIMER_E
05936   *         @arg @ref LL_HRTIM_TIMER_F
05937   * @param  Registers Registers to be updated by the DMA request
05938   *
05939   *         For Master timer this parameter can be can be a combination of the following values:
05940   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
05941   *         @arg @ref LL_HRTIM_BURSTDMA_MCR
05942   *         @arg @ref LL_HRTIM_BURSTDMA_MICR
05943   *         @arg @ref LL_HRTIM_BURSTDMA_MDIER
05944   *         @arg @ref LL_HRTIM_BURSTDMA_MCNT
05945   *         @arg @ref LL_HRTIM_BURSTDMA_MPER
05946   *         @arg @ref LL_HRTIM_BURSTDMA_MREP
05947   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP1
05948   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP2
05949   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP3
05950   *         @arg @ref LL_HRTIM_BURSTDMA_MCMP4
05951   *
05952   *         For Timers A..F this parameter can be can be a combination of the following values:
05953   *         @arg @ref LL_HRTIM_BURSTDMA_NONE
05954   *         @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
05955   *         @arg @ref LL_HRTIM_BURSTDMA_TIMICR
05956   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
05957   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
05958   *         @arg @ref LL_HRTIM_BURSTDMA_TIMPER
05959   *         @arg @ref LL_HRTIM_BURSTDMA_TIMREP
05960   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
05961   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
05962   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
05963   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
05964   *         @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
05965   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
05966   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
05967   *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
05968   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
05969   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
05970   *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
05971   *         @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
05972   *         @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
05973   *         @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
05974   *         @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
05975   *         @arg @ref LL_HRTIM_BURSTDMA_CR2
05976   *         @arg @ref LL_HRTIM_BURSTDMA_EEFR3
05977   * @retval None
05978   */
05979 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
05980 {
05981   const uint8_t REG_OFFSET_TAB_BDTUPR[] =
05982   {
05983     0x00U,   /* BDMUPR ; offset = 0x000 */
05984     0x04U,   /* BDAUPR ; offset = 0x05C */
05985     0x08U,   /* BDBUPR ; offset = 0x060 */
05986     0x0CU,   /* BDCUPR ; offset = 0x064 */
05987     0x10U,   /* BDDUPR ; offset = 0x068 */
05988     0x14U,   /* BDEUPR ; offset = 0x06C */
05989     0x1CU    /* BDFUPR ; offset = 0x074 */
05990   };
05991
05992   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
05993   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
05994   WRITE_REG(*pReg, Registers);
05995 }
05996
05997 /**
05998   * @brief  Indicate on which output the signal is currently applied.
05999   * @rmtoll TIMxISR      CPPSTAT        LL_HRTIM_TIM_GetCurrentPushPullStatus
06000   * @note Only significant when the timer operates in push-pull mode.
06001   * @param  HRTIMx High Resolution Timer instance
06002   * @param  Timer This parameter can be one of the following values:
06003   *         @arg @ref LL_HRTIM_TIMER_A
06004   *         @arg @ref LL_HRTIM_TIMER_B
06005   *         @arg @ref LL_HRTIM_TIMER_C
06006   *         @arg @ref LL_HRTIM_TIMER_D
06007   *         @arg @ref LL_HRTIM_TIMER_E
06008   *         @arg @ref LL_HRTIM_TIMER_F
06009   * @retval CPPSTAT This parameter can be one of the following values:
06010   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
06011   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
06012   */
06013 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06014 {
06015   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
06016   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
06017                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06018   return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
06019 }
06020
06021 /**
06022   * @brief  Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
06023   * @rmtoll TIMxISR      IPPSTAT        LL_HRTIM_TIM_GetIdlePushPullStatus
06024   * @param  HRTIMx High Resolution Timer instance
06025   * @param  Timer This parameter can be one of the following values:
06026   *         @arg @ref LL_HRTIM_TIMER_A
06027   *         @arg @ref LL_HRTIM_TIMER_B
06028   *         @arg @ref LL_HRTIM_TIMER_C
06029   *         @arg @ref LL_HRTIM_TIMER_D
06030   *         @arg @ref LL_HRTIM_TIMER_E
06031   *         @arg @ref LL_HRTIM_TIMER_F
06032   * @retval IPPSTAT This parameter can be one of the following values:
06033   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
06034   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
06035   */
06036 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06037 {
06038   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
06039   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
06040                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06041   return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
06042 }
06043
06044 /**
06045   * @brief  Set the event filter for a given timer.
06046   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventFilter\n
06047   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventFilter\n
06048   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventFilter\n
06049   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventFilter\n
06050   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventFilter\n
06051   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventFilter\n
06052   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventFilter\n
06053   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventFilter\n
06054   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventFilter\n
06055   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventFilter
06056   * @note This function must not be called when the timer counter is enabled.
06057   * @param  HRTIMx High Resolution Timer instance
06058   * @param  Timer This parameter can be one of the following values:
06059   *         @arg @ref LL_HRTIM_TIMER_A
06060   *         @arg @ref LL_HRTIM_TIMER_B
06061   *         @arg @ref LL_HRTIM_TIMER_C
06062   *         @arg @ref LL_HRTIM_TIMER_D
06063   *         @arg @ref LL_HRTIM_TIMER_E
06064   *         @arg @ref LL_HRTIM_TIMER_F
06065   * @param  Event This parameter can be one of the following values:
06066   *         @arg @ref LL_HRTIM_EVENT_1
06067   *         @arg @ref LL_HRTIM_EVENT_2
06068   *         @arg @ref LL_HRTIM_EVENT_3
06069   *         @arg @ref LL_HRTIM_EVENT_4
06070   *         @arg @ref LL_HRTIM_EVENT_5
06071   *         @arg @ref LL_HRTIM_EVENT_6
06072   *         @arg @ref LL_HRTIM_EVENT_7
06073   *         @arg @ref LL_HRTIM_EVENT_8
06074   *         @arg @ref LL_HRTIM_EVENT_9
06075   *         @arg @ref LL_HRTIM_EVENT_10
06076   * @param  Filter This parameter can be one of the following values:
06077   *         @arg @ref LL_HRTIM_EEFLTR_NONE
06078   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
06079   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
06080   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
06081   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
06082   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
06083   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
06084   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
06085   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
06086   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
06087   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
06088   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
06089   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
06090   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
06091   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
06092   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
06093   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
06094   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
06095   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
06096   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
06097   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
06098   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
06099   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
06100   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
06101   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
06102   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
06103   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
06104   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
06105   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
06106   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
06107   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
06108   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
06109   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
06110   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
06111   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
06112   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
06113   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
06114   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
06115   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
06116   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
06117   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
06118   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
06119   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
06120   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
06121   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
06122   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
06123   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
06124   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
06125   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
06126   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
06127   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
06128   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
06129   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
06130   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
06131   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
06132   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
06133
06134   * @retval None
06135   */
06136 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
06137 {
06138   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06139   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06140   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
06141                                                               REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
06142   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
06143 }
06144
06145 /**
06146   * @brief  Get actual event filter settings for a given timer.
06147   * @rmtoll EEFxR1      EE1FLTR        LL_HRTIM_TIM_GetEventFilter\n
06148   *         EEFxR1      EE2FLTR        LL_HRTIM_TIM_GetEventFilter\n
06149   *         EEFxR1      EE3FLTR        LL_HRTIM_TIM_GetEventFilter\n
06150   *         EEFxR1      EE4FLTR        LL_HRTIM_TIM_GetEventFilter\n
06151   *         EEFxR1      EE5FLTR        LL_HRTIM_TIM_GetEventFilter\n
06152   *         EEFxR2      EE6FLTR        LL_HRTIM_TIM_GetEventFilter\n
06153   *         EEFxR2      EE7FLTR        LL_HRTIM_TIM_GetEventFilter\n
06154   *         EEFxR2      EE8FLTR        LL_HRTIM_TIM_GetEventFilter\n
06155   *         EEFxR2      EE9FLTR        LL_HRTIM_TIM_GetEventFilter\n
06156   *         EEFxR2      EE10FLTR       LL_HRTIM_TIM_GetEventFilter
06157   * @param  HRTIMx High Resolution Timer instance
06158   * @param  Timer This parameter can be one of the following values:
06159   *         @arg @ref LL_HRTIM_TIMER_A
06160   *         @arg @ref LL_HRTIM_TIMER_B
06161   *         @arg @ref LL_HRTIM_TIMER_C
06162   *         @arg @ref LL_HRTIM_TIMER_D
06163   *         @arg @ref LL_HRTIM_TIMER_E
06164   *         @arg @ref LL_HRTIM_TIMER_F
06165   * @param  Event This parameter can be one of the following values:
06166   *         @arg @ref LL_HRTIM_EVENT_1
06167   *         @arg @ref LL_HRTIM_EVENT_2
06168   *         @arg @ref LL_HRTIM_EVENT_3
06169   *         @arg @ref LL_HRTIM_EVENT_4
06170   *         @arg @ref LL_HRTIM_EVENT_5
06171   *         @arg @ref LL_HRTIM_EVENT_6
06172   *         @arg @ref LL_HRTIM_EVENT_7
06173   *         @arg @ref LL_HRTIM_EVENT_8
06174   *         @arg @ref LL_HRTIM_EVENT_9
06175   *         @arg @ref LL_HRTIM_EVENT_10
06176   * @retval Filter This parameter can be one of the following values:
06177   *         @arg @ref LL_HRTIM_EEFLTR_NONE
06178   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
06179   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
06180   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
06181   *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
06182   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
06183   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
06184   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
06185   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
06186   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
06187   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
06188   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
06189   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
06190   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
06191   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
06192   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
06193   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
06194   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
06195   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
06196   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
06197   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
06198   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
06199   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
06200   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
06201   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
06202   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
06203   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
06204   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
06205   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
06206   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
06207   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
06208   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
06209   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
06210   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
06211   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
06212   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
06213   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
06214   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
06215   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
06216   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
06217   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
06218   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
06219   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
06220   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
06221   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
06222   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
06223   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
06224   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
06225   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
06226   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
06227   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
06228   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
06229   *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
06230   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
06231   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
06232   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
06233   */
06234 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
06235 {
06236   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06237   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06238   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
06239                                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
06240   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
06241 }
06242
06243 /**
06244   * @brief  Enable or disable event latch mechanism for a given timer.
06245   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06246   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06247   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06248   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06249   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06250   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06251   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06252   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06253   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
06254   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventLatchStatus
06255   * @note This function must not be called when the timer counter is enabled.
06256   * @param  HRTIMx High Resolution Timer instance
06257   * @param  Timer This parameter can be one of the following values:
06258   *         @arg @ref LL_HRTIM_TIMER_A
06259   *         @arg @ref LL_HRTIM_TIMER_B
06260   *         @arg @ref LL_HRTIM_TIMER_C
06261   *         @arg @ref LL_HRTIM_TIMER_D
06262   *         @arg @ref LL_HRTIM_TIMER_E
06263   *         @arg @ref LL_HRTIM_TIMER_F
06264   * @param  Event This parameter can be one of the following values:
06265   *         @arg @ref LL_HRTIM_EVENT_1
06266   *         @arg @ref LL_HRTIM_EVENT_2
06267   *         @arg @ref LL_HRTIM_EVENT_3
06268   *         @arg @ref LL_HRTIM_EVENT_4
06269   *         @arg @ref LL_HRTIM_EVENT_5
06270   *         @arg @ref LL_HRTIM_EVENT_6
06271   *         @arg @ref LL_HRTIM_EVENT_7
06272   *         @arg @ref LL_HRTIM_EVENT_8
06273   *         @arg @ref LL_HRTIM_EVENT_9
06274   *         @arg @ref LL_HRTIM_EVENT_10
06275   * @param  LatchStatus This parameter can be one of the following values:
06276   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
06277   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
06278   * @retval None
06279   */
06280 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
06281                                                       uint32_t LatchStatus)
06282 {
06283   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06284   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06285   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
06286                                                               REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
06287   MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
06288 }
06289
06290 /**
06291   * @brief  Get actual event latch status for a given timer.
06292   * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06293   *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06294   *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06295   *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06296   *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06297   *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06298   *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06299   *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06300   *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
06301   *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_GetEventLatchStatus
06302   * @param  HRTIMx High Resolution Timer instance
06303   * @param  Timer This parameter can be one of the following values:
06304   *         @arg @ref LL_HRTIM_TIMER_A
06305   *         @arg @ref LL_HRTIM_TIMER_B
06306   *         @arg @ref LL_HRTIM_TIMER_C
06307   *         @arg @ref LL_HRTIM_TIMER_D
06308   *         @arg @ref LL_HRTIM_TIMER_E
06309   *         @arg @ref LL_HRTIM_TIMER_F
06310   * @param  Event This parameter can be one of the following values:
06311   *         @arg @ref LL_HRTIM_EVENT_1
06312   *         @arg @ref LL_HRTIM_EVENT_2
06313   *         @arg @ref LL_HRTIM_EVENT_3
06314   *         @arg @ref LL_HRTIM_EVENT_4
06315   *         @arg @ref LL_HRTIM_EVENT_5
06316   *         @arg @ref LL_HRTIM_EVENT_6
06317   *         @arg @ref LL_HRTIM_EVENT_7
06318   *         @arg @ref LL_HRTIM_EVENT_8
06319   *         @arg @ref LL_HRTIM_EVENT_9
06320   *         @arg @ref LL_HRTIM_EVENT_10
06321   * @retval LatchStatus This parameter can be one of the following values:
06322   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
06323   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
06324   */
06325 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
06326 {
06327   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06328   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
06329   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
06330                                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
06331   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
06332 }
06333
06334 /**
06335   * @brief  Select the Trigger-Half operating mode for a given timer.
06336   * @note   This bitfield defines whether the compare 2 register
06337   * @note   is behaving in standard mode (compare match issued as soon as counter equal compare)
06338   * @note   or in triggered-half mode
06339   * @rmtoll TIMxCR2    TRGHLF      LL_HRTIM_TIM_SetTriggeredHalfMode
06340   * @param  HRTIMx High Resolution Timer instance
06341   * @param  Timer This parameter can be one of the following values:
06342   *         @arg @ref LL_HRTIM_TIMER_A
06343   *         @arg @ref LL_HRTIM_TIMER_B
06344   *         @arg @ref LL_HRTIM_TIMER_C
06345   *         @arg @ref LL_HRTIM_TIMER_D
06346   *         @arg @ref LL_HRTIM_TIMER_E
06347   *         @arg @ref LL_HRTIM_TIMER_F
06348   * @param  Mode This parameter can be one of the following values:
06349   *         @arg @ref LL_HRTIM_TRIGHALF_ENABLED
06350   *         @arg @ref LL_HRTIM_TRIGHALF_DISABLED
06351   * @retval None
06352   */
06353 __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06354 {
06355   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06356   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06357                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06358   MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
06359 }
06360
06361 /**
06362   * @brief  Get the Trigger-Half operating mode for a given timer.
06363   * @note   This bitfield reports whether the compare 2 register
06364   * @note   is behaving in standard mode (compare match issued as soon as counter equal compare)
06365   * @note   or in triggered-half mode
06366   * @rmtoll TIMxCR2    TRGHLF      LL_HRTIM_TIM_GetTriggeredHalfMode
06367   * @param  HRTIMx High Resolution Timer instance
06368   * @param  Timer This parameter can be one of the following values:
06369   *         @arg @ref LL_HRTIM_TIMER_A
06370   *         @arg @ref LL_HRTIM_TIMER_B
06371   *         @arg @ref LL_HRTIM_TIMER_C
06372   *         @arg @ref LL_HRTIM_TIMER_D
06373   *         @arg @ref LL_HRTIM_TIMER_E
06374   *         @arg @ref LL_HRTIM_TIMER_F
06375   * @retval Mode This parameter can be one of the following values:
06376   *         @arg @ref LL_HRTIM_TRIGHALF_ENABLED
06377   *         @arg @ref LL_HRTIM_TRIGHALF_DISABLED
06378   */
06379 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06380 {
06381   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06382   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06383                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06384   return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
06385 }
06386
06387 /**
06388   * @brief  Select the compare 1 operating mode.
06389   * @note   This bit defines the compare 1 operating mode:
06390   * @note   0: the compare 1 event is generated when the counter is equal to the compare value
06391   * @note   1: the compare 1 event is generated when the counter is greater than the compare value
06392   * @rmtoll TIMxCR2    GTCMP1      LL_HRTIM_TIM_SetComp1Mode
06393   * @param  HRTIMx High Resolution Timer instance
06394   * @param  Timer This parameter can be one of the following values:
06395   *         @arg @ref LL_HRTIM_TIMER_A
06396   *         @arg @ref LL_HRTIM_TIMER_B
06397   *         @arg @ref LL_HRTIM_TIMER_C
06398   *         @arg @ref LL_HRTIM_TIMER_D
06399   *         @arg @ref LL_HRTIM_TIMER_E
06400   *         @arg @ref LL_HRTIM_TIMER_F
06401   * @param  Mode This parameter can be one of the following values:
06402   *         @arg @ref LL_HRTIM_GTCMP1_EQUAL
06403   *         @arg @ref LL_HRTIM_GTCMP1_GREATER
06404   * @retval None
06405   */
06406 __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06407 {
06408   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06409   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06410                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06411   MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
06412 }
06413
06414 /**
06415   * @brief  Get the selected compare 1 operating mode.
06416   * @note   This bit reports the compare 1 operating mode:
06417   * @note   0: the compare 1 event is generated when the counter is equal to the compare value
06418   * @note   1: the compare 1 event is generated when the counter is greater than the compare value
06419   * @rmtoll TIMxCR2    GTCMP1      LL_HRTIM_TIM_GetComp1Mode
06420   * @param  HRTIMx High Resolution Timer instance
06421   * @param  Timer This parameter can be one of the following values:
06422   *         @arg @ref LL_HRTIM_TIMER_A
06423   *         @arg @ref LL_HRTIM_TIMER_B
06424   *         @arg @ref LL_HRTIM_TIMER_C
06425   *         @arg @ref LL_HRTIM_TIMER_D
06426   *         @arg @ref LL_HRTIM_TIMER_E
06427   *         @arg @ref LL_HRTIM_TIMER_F
06428   * @retval  Mode This parameter can be one of the following values:
06429   *         @arg @ref LL_HRTIM_GTCMP1_EQUAL
06430   *         @arg @ref LL_HRTIM_GTCMP1_GREATER
06431   */
06432 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06433 {
06434   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06435   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06436                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06437   return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
06438 }
06439
06440 /**
06441   * @brief  Select the compare 3 operating mode.
06442   * @note   This bit defines the compare 3 operating mode:
06443   * @note   0: the compare 3 event is generated when the counter is equal to the compare value
06444   * @note   1: the compare 3 event is generated when the counter is greater than the compare value
06445   * @rmtoll TIMxCR2    GTCMP3      LL_HRTIM_TIM_SetComp3Mode
06446   * @param  HRTIMx High Resolution Timer instance
06447   * @param  Timer This parameter can be one of the following values:
06448   *         @arg @ref LL_HRTIM_TIMER_A
06449   *         @arg @ref LL_HRTIM_TIMER_B
06450   *         @arg @ref LL_HRTIM_TIMER_C
06451   *         @arg @ref LL_HRTIM_TIMER_D
06452   *         @arg @ref LL_HRTIM_TIMER_E
06453   *         @arg @ref LL_HRTIM_TIMER_F
06454   * @param  Mode This parameter can be one of the following values:
06455   *         @arg @ref LL_HRTIM_GTCMP3_EQUAL
06456   *         @arg @ref LL_HRTIM_GTCMP3_GREATER
06457   * @retval None
06458   */
06459 __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06460 {
06461   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06462   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06463                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06464   MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
06465 }
06466
06467 /**
06468   * @brief  Get the selected compare 3 operating mode.
06469   * @note   This bit reports the compare 3 operating mode:
06470   * @note   0: the compare 3 event is generated when the counter is equal to the compare value
06471   * @note   1: the compare 3 event is generated when the counter is greater than the compare value
06472   * @rmtoll TIMxCR2    GTCMP3      LL_HRTIM_TIM_GetComp1Mode
06473   * @param  HRTIMx High Resolution Timer instance
06474   * @param  Timer This parameter can be one of the following values:
06475   *         @arg @ref LL_HRTIM_TIMER_A
06476   *         @arg @ref LL_HRTIM_TIMER_B
06477   *         @arg @ref LL_HRTIM_TIMER_C
06478   *         @arg @ref LL_HRTIM_TIMER_D
06479   *         @arg @ref LL_HRTIM_TIMER_E
06480   *         @arg @ref LL_HRTIM_TIMER_F
06481   * @retval Mode This parameter can be one of the following values:
06482   *         @arg @ref LL_HRTIM_GTCMP3_EQUAL
06483   *         @arg @ref LL_HRTIM_GTCMP3_GREATER
06484   */
06485 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06486 {
06487   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06488   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
06489                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06490   return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
06491 }
06492
06493 /**
06494   * @brief  Select the roll-over mode.
06495   * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
06496   * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
06497   *      and DMA requests, repetition counter decrement and External Event filtering.
06498   * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_SetRollOverMode
06499   * @param  HRTIMx High Resolution Timer instance
06500   * @param  Timer This parameter can be one of the following values:
06501   *         @arg @ref LL_HRTIM_TIMER_A
06502   *         @arg @ref LL_HRTIM_TIMER_B
06503   *         @arg @ref LL_HRTIM_TIMER_C
06504   *         @arg @ref LL_HRTIM_TIMER_D
06505   *         @arg @ref LL_HRTIM_TIMER_E
06506   *         @arg @ref LL_HRTIM_TIMER_F
06507   * @param  Mode This parameter can be one of the following values:
06508   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06509   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06510   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06511   * @retval None
06512   */
06513 __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06514 {
06515   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06516   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06517                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06518   MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
06519 }
06520
06521 /**
06522   * @brief  Get selected the roll-over mode.
06523   * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_GetRollOverMode
06524   * @param  HRTIMx High Resolution Timer instance
06525   * @param  Timer This parameter can be one of the following values:
06526   *         @arg @ref LL_HRTIM_TIMER_A
06527   *         @arg @ref LL_HRTIM_TIMER_B
06528   *         @arg @ref LL_HRTIM_TIMER_C
06529   *         @arg @ref LL_HRTIM_TIMER_D
06530   *         @arg @ref LL_HRTIM_TIMER_E
06531   *         @arg @ref LL_HRTIM_TIMER_F
06532   * @retval Mode returned value can be one of the following values:
06533   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06534   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06535   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06536   */
06537 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06538 {
06539   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06540   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06541                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06542   return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
06543 }
06544
06545 /**
06546   * @brief  Select Fault and Event roll-over mode.
06547   * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
06548   * @note only concerns the Roll-over event used by the Fault and Event counters.
06549   * @rmtoll TIMxCR2    FEROM      LL_HRTIM_TIM_SetFaultEventRollOverMode
06550   * @param  HRTIMx High Resolution Timer instance
06551   * @param  Timer This parameter can be one of the following values:
06552   *         @arg @ref LL_HRTIM_TIMER_A
06553   *         @arg @ref LL_HRTIM_TIMER_B
06554   *         @arg @ref LL_HRTIM_TIMER_C
06555   *         @arg @ref LL_HRTIM_TIMER_D
06556   *         @arg @ref LL_HRTIM_TIMER_E
06557   *         @arg @ref LL_HRTIM_TIMER_F
06558   * @param  Mode This parameter can be one of the following values:
06559   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06560   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06561   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06562   * @retval None
06563   */
06564 __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06565 {
06566   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06567   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06568                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06569   MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
06570 }
06571
06572 /**
06573   * @brief  Get selected Fault and Event role-over mode.
06574   * @rmtoll TIMxCR2    FEROM      LL_HRTIM_TIM_GetFaultEventRollOverMode
06575   * @param  HRTIMx High Resolution Timer instance
06576   * @param  Timer This parameter can be one of the following values:
06577   *         @arg @ref LL_HRTIM_TIMER_A
06578   *         @arg @ref LL_HRTIM_TIMER_B
06579   *         @arg @ref LL_HRTIM_TIMER_C
06580   *         @arg @ref LL_HRTIM_TIMER_D
06581   *         @arg @ref LL_HRTIM_TIMER_E
06582   *         @arg @ref LL_HRTIM_TIMER_F
06583   * @retval  Mode returned value can be one of the following values:
06584   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06585   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06586   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06587   */
06588 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06589 {
06590   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06591   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06592                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06593   return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
06594 }
06595
06596 /**
06597   * @brief  Select the Burst mode roll-over mode.
06598   * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
06599   * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
06600   * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_SetBMRollOverMode
06601   * @param  HRTIMx High Resolution Timer instance
06602   * @param  Timer This parameter can be one of the following values:
06603   *         @arg @ref LL_HRTIM_TIMER_A
06604   *         @arg @ref LL_HRTIM_TIMER_B
06605   *         @arg @ref LL_HRTIM_TIMER_C
06606   *         @arg @ref LL_HRTIM_TIMER_D
06607   *         @arg @ref LL_HRTIM_TIMER_E
06608   *         @arg @ref LL_HRTIM_TIMER_F
06609   * @param  Mode This parameter can be one of the following values:
06610   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06611   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06612   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06613   * @retval None
06614   */
06615 __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06616 {
06617   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06618   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06619                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06620   MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
06621 }
06622
06623 /**
06624   * @brief  Get selected Burst mode roll-over mode.
06625   * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_GetBMRollOverMode
06626   * @param  HRTIMx High Resolution Timer instance
06627   * @param  Timer This parameter can be one of the following values:
06628   *         @arg @ref LL_HRTIM_TIMER_A
06629   *         @arg @ref LL_HRTIM_TIMER_B
06630   *         @arg @ref LL_HRTIM_TIMER_C
06631   *         @arg @ref LL_HRTIM_TIMER_D
06632   *         @arg @ref LL_HRTIM_TIMER_E
06633   *         @arg @ref LL_HRTIM_TIMER_F
06634   * @retval  Mode returned value can be one of the following values:
06635   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06636   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06637   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06638   */
06639 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06640 {
06641   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06642   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06643                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06644   return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
06645 }
06646
06647 /**
06648   * @brief  Select the ADC roll-over mode.
06649   * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
06650   * @note Only concerns the Roll-over event used to trigger the ADC.
06651   * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_SetADCRollOverMode
06652   * @param  HRTIMx High Resolution Timer instance
06653   * @param  Timer This parameter can be one of the following values:
06654   *         @arg @ref LL_HRTIM_TIMER_A
06655   *         @arg @ref LL_HRTIM_TIMER_B
06656   *         @arg @ref LL_HRTIM_TIMER_C
06657   *         @arg @ref LL_HRTIM_TIMER_D
06658   *         @arg @ref LL_HRTIM_TIMER_E
06659   *         @arg @ref LL_HRTIM_TIMER_F
06660   * @param  Mode This parameter can be one of the following values:
06661   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06662   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06663   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06664   * @retval None
06665   */
06666 __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06667 {
06668   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06669   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06670                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06671   MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
06672 }
06673
06674 /**
06675   * @brief  Get selected ADC roll-over mode.
06676   * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_GetADCRollOverMode
06677   * @param  HRTIMx High Resolution Timer instance
06678   * @param  Timer This parameter can be one of the following values:
06679   *         @arg @ref LL_HRTIM_TIMER_A
06680   *         @arg @ref LL_HRTIM_TIMER_B
06681   *         @arg @ref LL_HRTIM_TIMER_C
06682   *         @arg @ref LL_HRTIM_TIMER_D
06683   *         @arg @ref LL_HRTIM_TIMER_E
06684   *         @arg @ref LL_HRTIM_TIMER_F
06685   * @retval  Mode returned value can be one of the following values:
06686   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06687   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06688   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06689   */
06690 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06691 {
06692   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06693   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06694                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06695   return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
06696 }
06697
06698 /**
06699   * @brief  Select the ADC roll-over mode.
06700   * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
06701   * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
06702   *       as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
06703   *       and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
06704   * @rmtoll TIMxCR2    OUTROM      LL_HRTIM_TIM_SetOutputRollOverMode
06705   * @param  HRTIMx High Resolution Timer instance
06706   * @param  Timer This parameter can be one of the following values:
06707   *         @arg @ref LL_HRTIM_TIMER_A
06708   *         @arg @ref LL_HRTIM_TIMER_B
06709   *         @arg @ref LL_HRTIM_TIMER_C
06710   *         @arg @ref LL_HRTIM_TIMER_D
06711   *         @arg @ref LL_HRTIM_TIMER_E
06712   *         @arg @ref LL_HRTIM_TIMER_F
06713   * @param  Mode This parameter can be one of the following values:
06714   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06715   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06716   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06717   * @retval None
06718   */
06719 __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06720 {
06721   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06722   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06723                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06724   MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
06725 }
06726
06727 /**
06728   * @brief  Get selected ADC roll-over mode.
06729   * @rmtoll TIMxCR2    OUTROM      LL_HRTIM_TIM_GetOutputRollOverMode
06730   * @param  HRTIMx High Resolution Timer instance
06731   * @param  Timer This parameter can be one of the following values:
06732   *         @arg @ref LL_HRTIM_TIMER_A
06733   *         @arg @ref LL_HRTIM_TIMER_B
06734   *         @arg @ref LL_HRTIM_TIMER_C
06735   *         @arg @ref LL_HRTIM_TIMER_D
06736   *         @arg @ref LL_HRTIM_TIMER_E
06737   *         @arg @ref LL_HRTIM_TIMER_F
06738   * @retval  Mode returned value can be one of the following values:
06739   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
06740   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
06741   *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
06742   */
06743 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06744 {
06745   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06746   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06747                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06748   return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
06749 }
06750
06751 /**
06752   * @brief  Select the counting mode.
06753   * @note The up-down counting mode is available for both continuous and single-shot
06754   *       (retriggerable and nonretriggerable) operating modes
06755   *       (see function @ref LL_HRTIM_TIM_SetCounterMode()).
06756   * @note The counter roll-over event is defined differently in-up-down counting mode to
06757   *       support various operating condition.
06758   *       See @ref LL_HRTIM_TIM_SetCounterMode()
06759   * @rmtoll TIMxCR2    UDM      LL_HRTIM_TIM_SetCountingMode
06760   * @param  HRTIMx High Resolution Timer instance
06761   * @param  Timer This parameter can be one of the following values:
06762   *         @arg @ref LL_HRTIM_TIMER_A
06763   *         @arg @ref LL_HRTIM_TIMER_B
06764   *         @arg @ref LL_HRTIM_TIMER_C
06765   *         @arg @ref LL_HRTIM_TIMER_D
06766   *         @arg @ref LL_HRTIM_TIMER_E
06767   *         @arg @ref LL_HRTIM_TIMER_F
06768   * @param  Mode This parameter can be one of the following values:
06769   *         @arg @ref LL_HRTIM_COUNTING_MODE_UP
06770   *         @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
06771   * @retval None
06772   */
06773 __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06774 {
06775   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06776   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06777                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06778   MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
06779 }
06780
06781 /**
06782   * @brief  Get selected counting mode.
06783   * @rmtoll TIMxCR2    UDM      LL_HRTIM_TIM_GetCountingMode
06784   * @param  HRTIMx High Resolution Timer instance
06785   * @param  Timer This parameter can be one of the following values:
06786   *         @arg @ref LL_HRTIM_TIMER_A
06787   *         @arg @ref LL_HRTIM_TIMER_B
06788   *         @arg @ref LL_HRTIM_TIMER_C
06789   *         @arg @ref LL_HRTIM_TIMER_D
06790   *         @arg @ref LL_HRTIM_TIMER_E
06791   *         @arg @ref LL_HRTIM_TIMER_F
06792   * @retval  Mode returned value can be one of the following values:
06793   *         @arg @ref LL_HRTIM_COUNTING_MODE_UP
06794   *         @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
06795   * @retval None
06796   */
06797 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06798 {
06799   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06800   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06801                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06802   return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
06803 }
06804
06805 /**
06806   * @brief  Select Dual Channel DAC Reset trigger.
06807   * @note Significant only when Dual channel DAC trigger is enabled
06808   *       (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
06809   * @rmtoll TIMxCR2    DCDR      LL_HRTIM_TIM_SetDualDacResetTrigger
06810   * @param  HRTIMx High Resolution Timer instance
06811   * @param  Timer This parameter can be one of the following values:
06812   *         @arg @ref LL_HRTIM_TIMER_A
06813   *         @arg @ref LL_HRTIM_TIMER_B
06814   *         @arg @ref LL_HRTIM_TIMER_C
06815   *         @arg @ref LL_HRTIM_TIMER_D
06816   *         @arg @ref LL_HRTIM_TIMER_E
06817   *         @arg @ref LL_HRTIM_TIMER_F
06818   * @param  Mode This parameter can be one of the following values:
06819   *         @arg @ref LL_HRTIM_DCDR_COUNTER
06820   *         @arg @ref LL_HRTIM_DCDR_OUT1SET
06821   * @retval None
06822   */
06823 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06824 {
06825   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06826   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06827                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06828   MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
06829 }
06830
06831 /**
06832   * @brief  Get selected Dual Channel DAC Reset trigger.
06833   * @rmtoll TIMxCR2    DCDR      LL_HRTIM_TIM_GetDualDacResetTrigger
06834   * @param  HRTIMx High Resolution Timer instance
06835   * @param  Timer This parameter can be one of the following values:
06836   *         @arg @ref LL_HRTIM_TIMER_A
06837   *         @arg @ref LL_HRTIM_TIMER_B
06838   *         @arg @ref LL_HRTIM_TIMER_C
06839   *         @arg @ref LL_HRTIM_TIMER_D
06840   *         @arg @ref LL_HRTIM_TIMER_E
06841   *         @arg @ref LL_HRTIM_TIMER_F
06842   * @retval  Trigger returned value can be one of the following values:
06843   *         @arg @ref LL_HRTIM_DCDR_COUNTER
06844   *         @arg @ref LL_HRTIM_DCDR_OUT1SET
06845   */
06846 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06847 {
06848   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06849   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06850                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06851   return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
06852 }
06853
06854 /**
06855   * @brief  Select Dual Channel DAC Reset trigger.
06856   * @rmtoll TIMxCR2    DCDS      LL_HRTIM_TIM_SetDualDacStepTrigger
06857   * @param  HRTIMx High Resolution Timer instance
06858   * @param  Timer This parameter can be one of the following values:
06859   *         @arg @ref LL_HRTIM_TIMER_A
06860   *         @arg @ref LL_HRTIM_TIMER_B
06861   *         @arg @ref LL_HRTIM_TIMER_C
06862   *         @arg @ref LL_HRTIM_TIMER_D
06863   *         @arg @ref LL_HRTIM_TIMER_E
06864   *         @arg @ref LL_HRTIM_TIMER_F
06865   * @param  Mode This parameter can be one of the following values:
06866   *         @arg @ref LL_HRTIM_DCDS_CMP2
06867   *         @arg @ref LL_HRTIM_DCDS_OUT1RST
06868   * @retval None
06869   */
06870 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
06871 {
06872   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06873   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06874                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06875   MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
06876 }
06877
06878 /**
06879   * @brief  Get selected Dual Channel DAC Reset trigger.
06880   * @rmtoll TIMxCR2    DCDS      LL_HRTIM_TIM_GetDualDacStepTrigger
06881   * @param  HRTIMx High Resolution Timer instance
06882   * @param  Timer This parameter can be one of the following values:
06883   *         @arg @ref LL_HRTIM_TIMER_A
06884   *         @arg @ref LL_HRTIM_TIMER_B
06885   *         @arg @ref LL_HRTIM_TIMER_C
06886   *         @arg @ref LL_HRTIM_TIMER_D
06887   *         @arg @ref LL_HRTIM_TIMER_E
06888   *         @arg @ref LL_HRTIM_TIMER_F
06889   * @retval  Trigger returned value can be one of the following values:
06890   *         @arg @ref LL_HRTIM_DCDS_CMP2
06891   *         @arg @ref LL_HRTIM_DCDS_OUT1RST
06892   */
06893 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06894 {
06895   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06896   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06897                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06898   return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
06899 }
06900
06901 /**
06902   * @brief  Enable Dual Channel DAC trigger.
06903   * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
06904   * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_EnableDualDacTrigger
06905   * @param  HRTIMx High Resolution Timer instance
06906   * @param  Timer This parameter can be one of the following values:
06907   *         @arg @ref LL_HRTIM_TIMER_A
06908   *         @arg @ref LL_HRTIM_TIMER_B
06909   *         @arg @ref LL_HRTIM_TIMER_C
06910   *         @arg @ref LL_HRTIM_TIMER_D
06911   *         @arg @ref LL_HRTIM_TIMER_E
06912   *         @arg @ref LL_HRTIM_TIMER_F
06913   * @retval None
06914   */
06915 __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06916 {
06917   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06918   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06919                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06920   SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
06921 }
06922
06923 /**
06924   * @brief  Disable Dual Channel DAC trigger.
06925   * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_DisableDualDacTrigger
06926   * @param  HRTIMx High Resolution Timer instance
06927   * @param  Timer This parameter can be one of the following values:
06928   *         @arg @ref LL_HRTIM_TIMER_A
06929   *         @arg @ref LL_HRTIM_TIMER_B
06930   *         @arg @ref LL_HRTIM_TIMER_C
06931   *         @arg @ref LL_HRTIM_TIMER_D
06932   *         @arg @ref LL_HRTIM_TIMER_E
06933   *         @arg @ref LL_HRTIM_TIMER_F
06934   * @retval None
06935   */
06936 __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06937 {
06938   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06939   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06940                                                               REG_OFFSET_TAB_TIMER[iTimer]));
06941   CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
06942 }
06943
06944 /**
06945   * @brief  Indicate whether Dual Channel DAC trigger is enabled for a given timer.
06946   * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_IsEnabledDualDacTrigger
06947   * @param  HRTIMx High Resolution Timer instance
06948   * @param  Timer This parameter can be one of the following values:
06949   *         @arg @ref LL_HRTIM_TIMER_A
06950   *         @arg @ref LL_HRTIM_TIMER_B
06951   *         @arg @ref LL_HRTIM_TIMER_C
06952   *         @arg @ref LL_HRTIM_TIMER_D
06953   *         @arg @ref LL_HRTIM_TIMER_E
06954   *         @arg @ref LL_HRTIM_TIMER_F
06955   * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
06956   */
06957 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
06958 {
06959   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06960   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
06961                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
06962
06963   return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
06964 }
06965
06966
06967 /**
06968   * @brief  Set the external event counter threshold.
06969   * @note The external event is propagated to the timer only if the number
06970   *       of active edges is greater than the external event counter threshold.
06971   * @rmtoll EEFxR3    EEVBCNT      LL_HRTIM_TIM_SetEventCounterThreshold\n
06972   *         EEFxR3    EEVACNT      LL_HRTIM_TIM_SetEventCounterThreshold
06973   * @param  HRTIMx High Resolution Timer instance
06974   * @param  Timer This parameter can be one of the following values:
06975   *         @arg @ref LL_HRTIM_TIMER_A
06976   *         @arg @ref LL_HRTIM_TIMER_B
06977   *         @arg @ref LL_HRTIM_TIMER_C
06978   *         @arg @ref LL_HRTIM_TIMER_D
06979   *         @arg @ref LL_HRTIM_TIMER_E
06980   *         @arg @ref LL_HRTIM_TIMER_F
06981   * @param  EventCounter This parameter can be one of the following values:
06982   *         @arg @ref LL_HRTIM_EE_COUNTER_A
06983   *         @arg @ref LL_HRTIM_EE_COUNTER_B
06984   * @param  Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
06985   * @retval None
06986   */
06987 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
06988                                                            uint32_t Threshold)
06989 {
06990   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
06991   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
06992
06993   MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
06994 }
06995
06996 /**
06997   * @brief  Get the programmed external event counter threshold.
06998   * @rmtoll EEFxR3    EEVBCNT      LL_HRTIM_TIM_GetEventCounterThreshold\n
06999   *         EEFxR3    EEVACNT      LL_HRTIM_TIM_GetEventCounterThreshold
07000   * @param  HRTIMx High Resolution Timer instance
07001   * @param  Timer This parameter can be one of the following values:
07002   *         @arg @ref LL_HRTIM_TIMER_A
07003   *         @arg @ref LL_HRTIM_TIMER_B
07004   *         @arg @ref LL_HRTIM_TIMER_C
07005   *         @arg @ref LL_HRTIM_TIMER_D
07006   *         @arg @ref LL_HRTIM_TIMER_E
07007   *         @arg @ref LL_HRTIM_TIMER_F
07008   * @param  EventCounter This parameter can be one of the following values:
07009   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07010   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07011   * @retval Threshold Value between Min_Data=0 and Max_Data=63
07012   */
07013 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
07014                                                                uint32_t EventCounter)
07015 {
07016   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07017   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07018
07019   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter)))  ;
07020 }
07021
07022 /**
07023   * @brief  Select the external event counter source.
07024   * @note External event counting is only valid for edge-sensitive
07025   *       external events (See function LL_HRTIM_EE_Config() and function
07026   *       LL_HRTIM_EE_SetSensitivity()).
07027   * @rmtoll EEFxR3    EEVBSEL      LL_HRTIM_TIM_SetEventCounterSource\n
07028   *         EEFxR3    EEVASEL      LL_HRTIM_TIM_SetEventCounterSource
07029   * @param  HRTIMx High Resolution Timer instance
07030   * @param  Timer This parameter can be one of the following values:
07031   *         @arg @ref LL_HRTIM_TIMER_A
07032   *         @arg @ref LL_HRTIM_TIMER_B
07033   *         @arg @ref LL_HRTIM_TIMER_C
07034   *         @arg @ref LL_HRTIM_TIMER_D
07035   *         @arg @ref LL_HRTIM_TIMER_E
07036   *         @arg @ref LL_HRTIM_TIMER_F
07037   * @param  EventCounter This parameter can be one of the following values:
07038   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07039   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07040   * @param  Event This parameter can be one of the following values:
07041   *         @arg @ref LL_HRTIM_EVENT_1
07042   *         @arg @ref LL_HRTIM_EVENT_2
07043   *         @arg @ref LL_HRTIM_EVENT_3
07044   *         @arg @ref LL_HRTIM_EVENT_4
07045   *         @arg @ref LL_HRTIM_EVENT_5
07046   *         @arg @ref LL_HRTIM_EVENT_6
07047   *         @arg @ref LL_HRTIM_EVENT_7
07048   *         @arg @ref LL_HRTIM_EVENT_8
07049   *         @arg @ref LL_HRTIM_EVENT_9
07050   *         @arg @ref LL_HRTIM_EVENT_10
07051   * @retval None
07052   */
07053 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
07054                                                         uint32_t Event)
07055 {
07056   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07057   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07058   uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
07059
07060   /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
07061      and 9 if LL_HRTIM_EVENT_10 */
07062   MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
07063 }
07064
07065 /**
07066   * @brief  get the selected external event counter source.
07067   *       LL_HRTIM_EE_SetSensitivity()).
07068   * @rmtoll EEFxR3    EEVBSEL      LL_HRTIM_TIM_GetEventCounterSource\n
07069   *         EEFxR3    EEVASEL      LL_HRTIM_TIM_GetEventCounterSource
07070   * @param  HRTIMx High Resolution Timer instance
07071   * @param  Timer This parameter can be one of the following values:
07072   *         @arg @ref LL_HRTIM_TIMER_A
07073   *         @arg @ref LL_HRTIM_TIMER_B
07074   *         @arg @ref LL_HRTIM_TIMER_C
07075   *         @arg @ref LL_HRTIM_TIMER_D
07076   *         @arg @ref LL_HRTIM_TIMER_E
07077   *         @arg @ref LL_HRTIM_TIMER_F
07078   * @param  EventCounter This parameter can be one of the following values:
07079   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07080   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07081   * @retval  Event This parameter can be one of the following values:
07082   *         @arg @ref LL_HRTIM_EVENT_1
07083   *         @arg @ref LL_HRTIM_EVENT_2
07084   *         @arg @ref LL_HRTIM_EVENT_3
07085   *         @arg @ref LL_HRTIM_EVENT_4
07086   *         @arg @ref LL_HRTIM_EVENT_5
07087   *         @arg @ref LL_HRTIM_EVENT_6
07088   *         @arg @ref LL_HRTIM_EVENT_7
07089   *         @arg @ref LL_HRTIM_EVENT_8
07090   *         @arg @ref LL_HRTIM_EVENT_9
07091   *         @arg @ref LL_HRTIM_EVENT_10
07092   */
07093 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
07094                                                             uint32_t EventCounter)
07095 {
07096   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07097   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07098
07099   uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
07100
07101   /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
07102      and 9 if SEL is LL_HRTIM_EVENT_10 */
07103   return ((uint32_t)0x1U << iEvent)  ;
07104 }
07105
07106 /**
07107   * @brief  Select the external event counter reset mode.
07108   * @rmtoll EEFxR3    EEVBRSTM      LL_HRTIM_TIM_SetEventCounterResetMode\n
07109   *         EEFxR3    EEVARSTM      LL_HRTIM_TIM_SetEventCounterResetMode
07110   * @param  HRTIMx High Resolution Timer instance
07111   * @param  Timer This parameter can be one of the following values:
07112   *         @arg @ref LL_HRTIM_TIMER_A
07113   *         @arg @ref LL_HRTIM_TIMER_B
07114   *         @arg @ref LL_HRTIM_TIMER_C
07115   *         @arg @ref LL_HRTIM_TIMER_D
07116   *         @arg @ref LL_HRTIM_TIMER_E
07117   *         @arg @ref LL_HRTIM_TIMER_F
07118   * @param  EventCounter This parameter can be one of the following values:
07119   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07120   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07121   * @param  Mode This parameter can be one of the following values:
07122   *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
07123   *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
07124   * @retval None
07125   */
07126 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
07127                                                            uint32_t Mode)
07128 {
07129   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07130   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07131
07132   MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
07133 }
07134
07135 /**
07136   * @brief  Get selected external event counter reset mode.
07137   * @rmtoll EEFxR3    EEVBRSTM      LL_HRTIM_TIM_GetEventCounterResetMode\n
07138   *         EEFxR3    EEVARSTM      LL_HRTIM_TIM_GetEventCounterResetMode
07139   * @param  HRTIMx High Resolution Timer instance
07140   * @param  Timer This parameter can be one of the following values:
07141   *         @arg @ref LL_HRTIM_TIMER_A
07142   *         @arg @ref LL_HRTIM_TIMER_B
07143   *         @arg @ref LL_HRTIM_TIMER_C
07144   *         @arg @ref LL_HRTIM_TIMER_D
07145   *         @arg @ref LL_HRTIM_TIMER_E
07146   *         @arg @ref LL_HRTIM_TIMER_F
07147   * @param  EventCounter This parameter can be one of the following values:
07148   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07149   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07150   * @retval  Mode This parameter can be one of the following values:
07151   *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
07152   *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
07153   */
07154 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
07155                                                                uint32_t EventCounter)
07156 {
07157   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07158   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07159
07160   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter))  ;
07161 }
07162
07163 /**
07164   * @brief  Reset the external event counter.
07165   * @rmtoll EEFxR3    EEVACRES      LL_HRTIM_TIM_ResetEventCounter\n
07166   *         EEFxR3    EEVBCRES      LL_HRTIM_TIM_ResetEventCounter
07167   * @param  HRTIMx High Resolution Timer instance
07168   * @param  Timer This parameter can be one of the following values:
07169   *         @arg @ref LL_HRTIM_TIMER_A
07170   *         @arg @ref LL_HRTIM_TIMER_B
07171   *         @arg @ref LL_HRTIM_TIMER_C
07172   *         @arg @ref LL_HRTIM_TIMER_D
07173   *         @arg @ref LL_HRTIM_TIMER_E
07174   *         @arg @ref LL_HRTIM_TIMER_F
07175   * @param  EventCounter This parameter can be one of the following values:
07176   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07177   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07178   * @retval None
07179   */
07180 __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
07181 {
07182   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07183   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07184
07185   SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
07186 }
07187
07188 /**
07189   * @brief  Enable the external event counter.
07190   * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_EnableEventCounter\n
07191   *         EEFxR3    EEVBCE      LL_HRTIM_TIM_EnableEventCounter
07192   * @param  HRTIMx High Resolution Timer instance
07193   * @param  Timer This parameter can be one of the following values:
07194   *         @arg @ref LL_HRTIM_TIMER_A
07195   *         @arg @ref LL_HRTIM_TIMER_B
07196   *         @arg @ref LL_HRTIM_TIMER_C
07197   *         @arg @ref LL_HRTIM_TIMER_D
07198   *         @arg @ref LL_HRTIM_TIMER_E
07199   *         @arg @ref LL_HRTIM_TIMER_F
07200   * @param  EventCounter This parameter can be one of the following values:
07201   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07202   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07203   * @retval None
07204   */
07205 __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
07206 {
07207   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07208   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07209
07210   SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
07211 }
07212
07213 /**
07214   * @brief  Disable the external event counter.
07215   * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_DisableEventCounter\n
07216   *         EEFxR3    EEVBCE      LL_HRTIM_TIM_DisableEventCounter
07217   * @param  HRTIMx High Resolution Timer instance
07218   * @param  Timer This parameter can be one of the following values:
07219   *         @arg @ref LL_HRTIM_TIMER_A
07220   *         @arg @ref LL_HRTIM_TIMER_B
07221   *         @arg @ref LL_HRTIM_TIMER_C
07222   *         @arg @ref LL_HRTIM_TIMER_D
07223   *         @arg @ref LL_HRTIM_TIMER_E
07224   *         @arg @ref LL_HRTIM_TIMER_F
07225   * @param  EventCounter This parameter can be one of the following values:
07226   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07227   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07228   * @retval None
07229   */
07230 __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
07231 {
07232   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07233   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07234
07235   CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
07236 }
07237
07238
07239 /**
07240   * @brief  Indicate whether the external event counter is enabled for a given timer.
07241   * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_IsEnabledEventCounter\n
07242   *         EEFxR3    EEVBCE      LL_HRTIM_TIM_IsEnabledEventCounter
07243   * @param  HRTIMx High Resolution Timer instance
07244   * @param  Timer This parameter can be one of the following values:
07245   *         @arg @ref LL_HRTIM_TIMER_A
07246   *         @arg @ref LL_HRTIM_TIMER_B
07247   *         @arg @ref LL_HRTIM_TIMER_C
07248   *         @arg @ref LL_HRTIM_TIMER_D
07249   *         @arg @ref LL_HRTIM_TIMER_E
07250   *         @arg @ref LL_HRTIM_TIMER_F
07251   * @param  EventCounter This parameter can be one of the following values:
07252   *         @arg @ref LL_HRTIM_EE_COUNTER_A
07253   *         @arg @ref LL_HRTIM_EE_COUNTER_B
07254   * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
07255   */
07256 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
07257                                                             uint32_t EventCounter)
07258 {
07259   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
07260   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
07261
07262   uint32_t temp; /* MISRAC-2012 compliance */
07263   temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
07264
07265   return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
07266 }
07267
07268 /**
07269   * @}
07270   */
07271
07272 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
07273   * @{
07274   */
07275
07276 /**
07277   * @brief  Configure the dead time insertion feature for a given timer.
07278   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_Config\n
07279   *         DTxR      SDTF       LL_HRTIM_DT_Config\n
07280   *         DTxR      SDRT       LL_HRTIM_DT_Config
07281   * @param  HRTIMx High Resolution Timer instance
07282   * @param  Timer This parameter can be one of the following values:
07283   *         @arg @ref LL_HRTIM_TIMER_A
07284   *         @arg @ref LL_HRTIM_TIMER_B
07285   *         @arg @ref LL_HRTIM_TIMER_C
07286   *         @arg @ref LL_HRTIM_TIMER_D
07287   *         @arg @ref LL_HRTIM_TIMER_E
07288   *         @arg @ref LL_HRTIM_TIMER_F
07289   * @param  Configuration This parameter must be a combination of all the following values:
07290   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
07291   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
07292   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
07293   * @retval None
07294   */
07295 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
07296 {
07297   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07298   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07299                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07300   MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
07301 }
07302
07303 /**
07304   * @brief  Set the deadtime prescaler value.
07305   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_SetPrescaler
07306   * @param  HRTIMx High Resolution Timer instance
07307   * @param  Timer This parameter can be one of the following values:
07308   *         @arg @ref LL_HRTIM_TIMER_A
07309   *         @arg @ref LL_HRTIM_TIMER_B
07310   *         @arg @ref LL_HRTIM_TIMER_C
07311   *         @arg @ref LL_HRTIM_TIMER_D
07312   *         @arg @ref LL_HRTIM_TIMER_E
07313   *         @arg @ref LL_HRTIM_TIMER_F
07314   * @param  Prescaler This parameter can be one of the following values:
07315   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
07316   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
07317   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
07318   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
07319   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
07320   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
07321   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
07322   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
07323   * @retval None
07324   */
07325 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
07326 {
07327   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07328   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07329                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07330   MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
07331 }
07332
07333 /**
07334   * @brief  Get actual deadtime prescaler value.
07335   * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_GetPrescaler
07336   * @param  HRTIMx High Resolution Timer instance
07337   * @param  Timer This parameter can be one of the following values:
07338   *         @arg @ref LL_HRTIM_TIMER_A
07339   *         @arg @ref LL_HRTIM_TIMER_B
07340   *         @arg @ref LL_HRTIM_TIMER_C
07341   *         @arg @ref LL_HRTIM_TIMER_D
07342   *         @arg @ref LL_HRTIM_TIMER_E
07343   *         @arg @ref LL_HRTIM_TIMER_F
07344   * @retval Prescaler This parameter can be one of the following values:
07345   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
07346   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
07347   *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
07348   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
07349   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
07350   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
07351   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
07352   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
07353   */
07354 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07355 {
07356   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07357   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07358                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07359   return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
07360 }
07361
07362 /**
07363   * @brief  Set the deadtime rising value.
07364   * @rmtoll DTxR      DTR       LL_HRTIM_DT_SetRisingValue
07365   * @param  HRTIMx High Resolution Timer instance
07366   * @param  Timer This parameter can be one of the following values:
07367   *         @arg @ref LL_HRTIM_TIMER_A
07368   *         @arg @ref LL_HRTIM_TIMER_B
07369   *         @arg @ref LL_HRTIM_TIMER_C
07370   *         @arg @ref LL_HRTIM_TIMER_D
07371   *         @arg @ref LL_HRTIM_TIMER_E
07372   *         @arg @ref LL_HRTIM_TIMER_F
07373   * @param  RisingValue Value between 0 and 0x1FF
07374   * @retval None
07375   */
07376 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
07377 {
07378   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07379   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07380                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07381   MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
07382 }
07383
07384 /**
07385   * @brief  Get actual deadtime rising value.
07386   * @rmtoll DTxR      DTR       LL_HRTIM_DT_GetRisingValue
07387   * @param  HRTIMx High Resolution Timer instance
07388   * @param  Timer This parameter can be one of the following values:
07389   *         @arg @ref LL_HRTIM_TIMER_A
07390   *         @arg @ref LL_HRTIM_TIMER_B
07391   *         @arg @ref LL_HRTIM_TIMER_C
07392   *         @arg @ref LL_HRTIM_TIMER_D
07393   *         @arg @ref LL_HRTIM_TIMER_E
07394   *         @arg @ref LL_HRTIM_TIMER_F
07395   * @retval RisingValue Value between 0 and 0x1FF
07396   */
07397 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07398 {
07399   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07400   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07401                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07402   return (READ_BIT(*pReg, HRTIM_DTR_DTR));
07403 }
07404
07405 /**
07406   * @brief  Set the deadtime sign on rising edge.
07407   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_SetRisingSign
07408   * @param  HRTIMx High Resolution Timer instance
07409   * @param  Timer This parameter can be one of the following values:
07410   *         @arg @ref LL_HRTIM_TIMER_A
07411   *         @arg @ref LL_HRTIM_TIMER_B
07412   *         @arg @ref LL_HRTIM_TIMER_C
07413   *         @arg @ref LL_HRTIM_TIMER_D
07414   *         @arg @ref LL_HRTIM_TIMER_E
07415   *         @arg @ref LL_HRTIM_TIMER_F
07416   * @param  RisingSign This parameter can be one of the following values:
07417   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
07418   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
07419   * @retval None
07420   */
07421 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
07422 {
07423   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07424   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07425                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07426   MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
07427 }
07428
07429 /**
07430   * @brief  Get actual deadtime sign on rising edge.
07431   * @rmtoll DTxR      SDTR       LL_HRTIM_DT_GetRisingSign
07432   * @param  HRTIMx High Resolution Timer instance
07433   * @param  Timer This parameter can be one of the following values:
07434   *         @arg @ref LL_HRTIM_TIMER_A
07435   *         @arg @ref LL_HRTIM_TIMER_B
07436   *         @arg @ref LL_HRTIM_TIMER_C
07437   *         @arg @ref LL_HRTIM_TIMER_D
07438   *         @arg @ref LL_HRTIM_TIMER_E
07439   *         @arg @ref LL_HRTIM_TIMER_F
07440   * @retval RisingSign This parameter can be one of the following values:
07441   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
07442   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
07443   */
07444 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07445 {
07446   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07447   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07448                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07449   return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
07450 }
07451
07452 /**
07453   * @brief  Set the deadime falling value.
07454   * @rmtoll DTxR      DTF       LL_HRTIM_DT_SetFallingValue
07455   * @param  HRTIMx High Resolution Timer instance
07456   * @param  Timer This parameter can be one of the following values:
07457   *         @arg @ref LL_HRTIM_TIMER_A
07458   *         @arg @ref LL_HRTIM_TIMER_B
07459   *         @arg @ref LL_HRTIM_TIMER_C
07460   *         @arg @ref LL_HRTIM_TIMER_D
07461   *         @arg @ref LL_HRTIM_TIMER_E
07462   *         @arg @ref LL_HRTIM_TIMER_F
07463   * @param  FallingValue Value between 0 and 0x1FF
07464   * @retval None
07465   */
07466 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
07467 {
07468   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07469   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07470                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07471   MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
07472 }
07473
07474 /**
07475   * @brief  Get actual deadtime falling value
07476   * @rmtoll DTxR      DTF       LL_HRTIM_DT_GetFallingValue
07477   * @param  HRTIMx High Resolution Timer instance
07478   * @param  Timer This parameter can be one of the following values:
07479   *         @arg @ref LL_HRTIM_TIMER_A
07480   *         @arg @ref LL_HRTIM_TIMER_B
07481   *         @arg @ref LL_HRTIM_TIMER_C
07482   *         @arg @ref LL_HRTIM_TIMER_D
07483   *         @arg @ref LL_HRTIM_TIMER_E
07484   *         @arg @ref LL_HRTIM_TIMER_F
07485   * @retval FallingValue Value between 0 and 0x1FF
07486   */
07487 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07488 {
07489   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07490   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07491                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07492   return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
07493 }
07494
07495 /**
07496   * @brief  Set the deadtime sign on falling edge.
07497   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_SetFallingSign
07498   * @param  HRTIMx High Resolution Timer instance
07499   * @param  Timer This parameter can be one of the following values:
07500   *         @arg @ref LL_HRTIM_TIMER_A
07501   *         @arg @ref LL_HRTIM_TIMER_B
07502   *         @arg @ref LL_HRTIM_TIMER_C
07503   *         @arg @ref LL_HRTIM_TIMER_D
07504   *         @arg @ref LL_HRTIM_TIMER_E
07505   *         @arg @ref LL_HRTIM_TIMER_F
07506   * @param  FallingSign This parameter can be one of the following values:
07507   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
07508   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
07509   * @retval None
07510   */
07511 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
07512 {
07513   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07514   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07515                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07516   MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
07517 }
07518
07519 /**
07520   * @brief  Get actual deadtime sign on falling edge.
07521   * @rmtoll DTxR      SDTF       LL_HRTIM_DT_GetFallingSign
07522   * @param  HRTIMx High Resolution Timer instance
07523   * @param  Timer This parameter can be one of the following values:
07524   *         @arg @ref LL_HRTIM_TIMER_A
07525   *         @arg @ref LL_HRTIM_TIMER_B
07526   *         @arg @ref LL_HRTIM_TIMER_C
07527   *         @arg @ref LL_HRTIM_TIMER_D
07528   *         @arg @ref LL_HRTIM_TIMER_E
07529   *         @arg @ref LL_HRTIM_TIMER_F
07530   * @retval FallingSign This parameter can be one of the following values:
07531   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
07532   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
07533   */
07534 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07535 {
07536   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07537   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07538                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07539   return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
07540 }
07541
07542 /**
07543   * @brief  Lock the deadtime value and sign on rising edge.
07544   * @rmtoll DTxR      DTRLK       LL_HRTIM_DT_LockRising
07545   * @param  HRTIMx High Resolution Timer instance
07546   * @param  Timer This parameter can be one of the following values:
07547   *         @arg @ref LL_HRTIM_TIMER_A
07548   *         @arg @ref LL_HRTIM_TIMER_B
07549   *         @arg @ref LL_HRTIM_TIMER_C
07550   *         @arg @ref LL_HRTIM_TIMER_D
07551   *         @arg @ref LL_HRTIM_TIMER_E
07552   *         @arg @ref LL_HRTIM_TIMER_F
07553   * @retval None
07554   */
07555 __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07556 {
07557   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07558   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07559                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07560   SET_BIT(*pReg, HRTIM_DTR_DTRLK);
07561 }
07562
07563 /**
07564   * @brief  Lock the deadtime sign on rising edge.
07565   * @rmtoll DTxR      DTRSLK       LL_HRTIM_DT_LockRisingSign
07566   * @param  HRTIMx High Resolution Timer instance
07567   * @param  Timer This parameter can be one of the following values:
07568   *         @arg @ref LL_HRTIM_TIMER_A
07569   *         @arg @ref LL_HRTIM_TIMER_B
07570   *         @arg @ref LL_HRTIM_TIMER_C
07571   *         @arg @ref LL_HRTIM_TIMER_D
07572   *         @arg @ref LL_HRTIM_TIMER_E
07573   *         @arg @ref LL_HRTIM_TIMER_F
07574   * @retval None
07575   */
07576 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07577 {
07578   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07579   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07580                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07581   SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
07582 }
07583
07584 /**
07585   * @brief  Lock the deadtime value and sign on falling edge.
07586   * @rmtoll DTxR      DTFLK       LL_HRTIM_DT_LockFalling
07587   * @param  HRTIMx High Resolution Timer instance
07588   * @param  Timer This parameter can be one of the following values:
07589   *         @arg @ref LL_HRTIM_TIMER_A
07590   *         @arg @ref LL_HRTIM_TIMER_B
07591   *         @arg @ref LL_HRTIM_TIMER_C
07592   *         @arg @ref LL_HRTIM_TIMER_D
07593   *         @arg @ref LL_HRTIM_TIMER_E
07594   *         @arg @ref LL_HRTIM_TIMER_F
07595   * @retval None
07596   */
07597 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07598 {
07599   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07600   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07601                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07602   SET_BIT(*pReg, HRTIM_DTR_DTFLK);
07603 }
07604
07605 /**
07606   * @brief  Lock the deadtime sign on falling edge.
07607   * @rmtoll DTxR      DTFSLK       LL_HRTIM_DT_LockFallingSign
07608   * @param  HRTIMx High Resolution Timer instance
07609   * @param  Timer This parameter can be one of the following values:
07610   *         @arg @ref LL_HRTIM_TIMER_A
07611   *         @arg @ref LL_HRTIM_TIMER_B
07612   *         @arg @ref LL_HRTIM_TIMER_C
07613   *         @arg @ref LL_HRTIM_TIMER_D
07614   *         @arg @ref LL_HRTIM_TIMER_E
07615   *         @arg @ref LL_HRTIM_TIMER_F
07616   * @retval None
07617   */
07618 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07619 {
07620   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07621   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
07622                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07623   SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
07624 }
07625
07626 /**
07627   * @}
07628   */
07629
07630 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
07631   * @{
07632   */
07633
07634 /**
07635   * @brief  Configure the chopper stage for a given timer.
07636   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_Config\n
07637   *         CHPxR      CARDTY       LL_HRTIM_CHP_Config\n
07638   *         CHPxR      STRTPW       LL_HRTIM_CHP_Config
07639   * @note This function must not be called if the chopper mode is already
07640   *       enabled for one of the timer outputs.
07641   * @param  HRTIMx High Resolution Timer instance
07642   * @param  Timer This parameter can be one of the following values:
07643   *         @arg @ref LL_HRTIM_TIMER_A
07644   *         @arg @ref LL_HRTIM_TIMER_B
07645   *         @arg @ref LL_HRTIM_TIMER_C
07646   *         @arg @ref LL_HRTIM_TIMER_D
07647   *         @arg @ref LL_HRTIM_TIMER_E
07648   *         @arg @ref LL_HRTIM_TIMER_F
07649   * @param  Configuration This parameter must be a combination of all the following values:
07650   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
07651   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
07652   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
07653   * @retval None
07654   */
07655 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
07656 {
07657   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07658   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07659                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07660   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
07661 }
07662
07663 /**
07664   * @brief  Set prescaler determining the carrier frequency to be added on top
07665   *         of the timer output signals when chopper mode is enabled.
07666   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_SetPrescaler
07667   * @note This function must not be called if the chopper mode is already
07668   *       enabled for one of the timer outputs.
07669   * @param  HRTIMx High Resolution Timer instance
07670   * @param  Timer This parameter can be one of the following values:
07671   *         @arg @ref LL_HRTIM_TIMER_A
07672   *         @arg @ref LL_HRTIM_TIMER_B
07673   *         @arg @ref LL_HRTIM_TIMER_C
07674   *         @arg @ref LL_HRTIM_TIMER_D
07675   *         @arg @ref LL_HRTIM_TIMER_E
07676   *         @arg @ref LL_HRTIM_TIMER_F
07677   * @param  Prescaler This parameter can be one of the following values:
07678   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
07679   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
07680   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
07681   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
07682   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
07683   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
07684   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
07685   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
07686   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
07687   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
07688   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
07689   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
07690   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
07691   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
07692   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
07693   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
07694   * @retval None
07695   */
07696 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
07697 {
07698   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07699   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07700                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07701   MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
07702 }
07703
07704 /**
07705   * @brief  Get actual chopper stage prescaler value.
07706   * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_GetPrescaler
07707   * @param  HRTIMx High Resolution Timer instance
07708   * @param  Timer This parameter can be one of the following values:
07709   *         @arg @ref LL_HRTIM_TIMER_A
07710   *         @arg @ref LL_HRTIM_TIMER_B
07711   *         @arg @ref LL_HRTIM_TIMER_C
07712   *         @arg @ref LL_HRTIM_TIMER_D
07713   *         @arg @ref LL_HRTIM_TIMER_E
07714   *         @arg @ref LL_HRTIM_TIMER_F
07715   * @retval Prescaler This parameter can be one of the following values:
07716   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
07717   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
07718   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
07719   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
07720   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
07721   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
07722   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
07723   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
07724   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
07725   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
07726   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
07727   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
07728   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
07729   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
07730   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
07731   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
07732   */
07733 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07734 {
07735   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07736   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07737                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07738   return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
07739 }
07740
07741 /**
07742   * @brief  Set the chopper duty cycle.
07743   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_SetDutyCycle
07744   * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
07745   * @note This function must not be called if the chopper mode is already
07746   *       enabled for one of the timer outputs.
07747   * @param  HRTIMx High Resolution Timer instance
07748   * @param  Timer This parameter can be one of the following values:
07749   *         @arg @ref LL_HRTIM_TIMER_A
07750   *         @arg @ref LL_HRTIM_TIMER_B
07751   *         @arg @ref LL_HRTIM_TIMER_C
07752   *         @arg @ref LL_HRTIM_TIMER_D
07753   *         @arg @ref LL_HRTIM_TIMER_E
07754   *         @arg @ref LL_HRTIM_TIMER_F
07755   * @param  DutyCycle This parameter can be one of the following values:
07756   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
07757   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
07758   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
07759   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
07760   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
07761   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
07762   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
07763   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
07764   * @retval None
07765   */
07766 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
07767 {
07768   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07769   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07770                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07771   MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
07772 }
07773
07774 /**
07775   * @brief  Get actual chopper duty cycle.
07776   * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_GetDutyCycle
07777   * @param  HRTIMx High Resolution Timer instance
07778   * @param  Timer This parameter can be one of the following values:
07779   *         @arg @ref LL_HRTIM_TIMER_A
07780   *         @arg @ref LL_HRTIM_TIMER_B
07781   *         @arg @ref LL_HRTIM_TIMER_C
07782   *         @arg @ref LL_HRTIM_TIMER_D
07783   *         @arg @ref LL_HRTIM_TIMER_E
07784   *         @arg @ref LL_HRTIM_TIMER_F
07785   * @retval DutyCycle This parameter can be one of the following values:
07786   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
07787   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
07788   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
07789   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
07790   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
07791   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
07792   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
07793   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
07794   */
07795 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07796 {
07797   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07798   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07799                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07800   return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
07801 }
07802
07803 /**
07804   * @brief  Set the start pulse width.
07805   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_SetPulseWidth
07806   * @note This function must not be called if the chopper mode is already
07807   *       enabled for one of the timer outputs.
07808   * @param  HRTIMx High Resolution Timer instance
07809   * @param  Timer This parameter can be one of the following values:
07810   *         @arg @ref LL_HRTIM_TIMER_A
07811   *         @arg @ref LL_HRTIM_TIMER_B
07812   *         @arg @ref LL_HRTIM_TIMER_C
07813   *         @arg @ref LL_HRTIM_TIMER_D
07814   *         @arg @ref LL_HRTIM_TIMER_E
07815   *         @arg @ref LL_HRTIM_TIMER_F
07816   * @param  PulseWidth This parameter can be one of the following values:
07817   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
07818   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
07819   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
07820   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
07821   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
07822   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
07823   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
07824   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
07825   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
07826   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
07827   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
07828   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
07829   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
07830   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
07831   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
07832   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
07833   * @retval None
07834   */
07835 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
07836 {
07837   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07838   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07839                                                               REG_OFFSET_TAB_TIMER[iTimer]));
07840   MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
07841 }
07842
07843 /**
07844   * @brief  Get actual start pulse width.
07845   * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_GetPulseWidth
07846   * @param  HRTIMx High Resolution Timer instance
07847   * @param  Timer This parameter can be one of the following values:
07848   *         @arg @ref LL_HRTIM_TIMER_A
07849   *         @arg @ref LL_HRTIM_TIMER_B
07850   *         @arg @ref LL_HRTIM_TIMER_C
07851   *         @arg @ref LL_HRTIM_TIMER_D
07852   *         @arg @ref LL_HRTIM_TIMER_E
07853   *         @arg @ref LL_HRTIM_TIMER_F
07854   * @retval PulseWidth This parameter can be one of the following values:
07855   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
07856   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
07857   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
07858   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
07859   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
07860   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
07861   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
07862   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
07863   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
07864   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
07865   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
07866   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
07867   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
07868   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
07869   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
07870   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
07871   */
07872 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
07873 {
07874   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
07875   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
07876                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
07877   return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
07878 }
07879
07880 /**
07881   * @}
07882   */
07883
07884 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
07885   * @{
07886   */
07887
07888 /**
07889   * @brief  Set the timer output set source.
07890   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
07891   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
07892   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
07893   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
07894   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
07895   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
07896   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
07897   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
07898   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
07899   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
07900   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
07901   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
07902   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
07903   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
07904   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
07905   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
07906   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
07907   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
07908   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
07909   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
07910   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
07911   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
07912   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
07913   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
07914   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
07915   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
07916   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
07917   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
07918   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
07919   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
07920   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
07921   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc\n
07922   *         SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
07923   *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
07924   *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
07925   *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
07926   *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
07927   *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
07928   *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
07929   *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
07930   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
07931   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
07932   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
07933   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
07934   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
07935   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
07936   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
07937   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
07938   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
07939   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
07940   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
07941   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
07942   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
07943   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
07944   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
07945   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
07946   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
07947   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
07948   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
07949   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
07950   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
07951   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
07952   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
07953   *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc
07954   * @param  HRTIMx High Resolution Timer instance
07955   * @param  Output This parameter can be one of the following values:
07956   *         @arg @ref LL_HRTIM_OUTPUT_TA1
07957   *         @arg @ref LL_HRTIM_OUTPUT_TA2
07958   *         @arg @ref LL_HRTIM_OUTPUT_TB1
07959   *         @arg @ref LL_HRTIM_OUTPUT_TB2
07960   *         @arg @ref LL_HRTIM_OUTPUT_TC1
07961   *         @arg @ref LL_HRTIM_OUTPUT_TC2
07962   *         @arg @ref LL_HRTIM_OUTPUT_TD1
07963   *         @arg @ref LL_HRTIM_OUTPUT_TD2
07964   *         @arg @ref LL_HRTIM_OUTPUT_TE1
07965   *         @arg @ref LL_HRTIM_OUTPUT_TE2
07966   *         @arg @ref LL_HRTIM_OUTPUT_TF1
07967   *         @arg @ref LL_HRTIM_OUTPUT_TF2
07968   * @param SetSrc This parameter can be a combination of the following values:
07969   *         @arg @ref LL_HRTIM_OUTPUTSET_NONE
07970   *         @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
07971   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
07972   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
07973   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
07974   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
07975   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
07976   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
07977   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
07978   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
07979   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
07980   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
07981   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
07982   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
07983   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
07984   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
07985   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
07986   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
07987   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
07988   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
07989   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
07990   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
07991   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
07992   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
07993   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
07994   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
07995   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
07996   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
07997   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
07998   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
07999   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
08000   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
08001   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
08002   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
08003   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
08004   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
08005   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
08006   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
08007   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
08008   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
08009   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
08010   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
08011   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
08012   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
08013   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
08014   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
08015   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
08016   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
08017   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
08018   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
08019   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
08020   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
08021   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
08022   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
08023   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
08024   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
08025   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
08026   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
08027   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
08028   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
08029   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
08030   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
08031   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
08032   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
08033   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
08034   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
08035   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
08036   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
08037   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
08038   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
08039   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
08040   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
08041   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
08042   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
08043   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
08044   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
08045   *         @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
08046   *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
08047   * @retval None
08048   */
08049 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
08050 {
08051   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08052   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
08053                                                               REG_OFFSET_TAB_SETxR[iOutput]));
08054   WRITE_REG(*pReg, SetSrc);
08055 }
08056
08057 /**
08058   * @brief  Get the timer output set source.
08059   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
08060   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
08061   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
08062   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
08063   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
08064   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
08065   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
08066   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
08067   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
08068   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
08069   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
08070   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
08071   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
08072   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
08073   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
08074   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
08075   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
08076   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
08077   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
08078   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
08079   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
08080   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
08081   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
08082   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
08083   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
08084   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
08085   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
08086   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
08087   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
08088   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
08089   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
08090   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc\n
08091   *         SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
08092   *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
08093   *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
08094   *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
08095   *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
08096   *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
08097   *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
08098   *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
08099   *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
08100   *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
08101   *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
08102   *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
08103   *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
08104   *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
08105   *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
08106   *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
08107   *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
08108   *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
08109   *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
08110   *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
08111   *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
08112   *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
08113   *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
08114   *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
08115   *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
08116   *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
08117   *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
08118   *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
08119   *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
08120   *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
08121   *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
08122   *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc
08123   * @param  HRTIMx High Resolution Timer instance
08124   * @param  Output This parameter can be one of the following values:
08125   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08126   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08127   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08128   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08129   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08130   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08131   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08132   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08133   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08134   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08135   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08136   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08137   * @retval SetSrc This parameter can be a combination of the following values:
08138   *         @arg @ref LL_HRTIM_OUTPUTSET_NONE
08139   *         @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
08140   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
08141   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
08142   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
08143   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
08144   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
08145   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
08146   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
08147   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
08148   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
08149   *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
08150   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
08151   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
08152   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
08153   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
08154   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
08155   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
08156   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
08157   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
08158   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
08159   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
08160   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
08161   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
08162   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
08163   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
08164   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
08165   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
08166   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
08167   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
08168   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
08169   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
08170   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
08171   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
08172   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
08173   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
08174   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
08175   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
08176   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
08177   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
08178   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
08179   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
08180   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
08181   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
08182   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
08183   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
08184   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
08185   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
08186   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
08187   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
08188   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
08189   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
08190   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
08191   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
08192   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
08193   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
08194   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
08195   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
08196   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
08197   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
08198   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
08199   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
08200   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
08201   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
08202   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
08203   *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
08204   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
08205   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
08206   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
08207   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
08208   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
08209   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
08210   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
08211   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
08212   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
08213   *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
08214   *         @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
08215   *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
08216   */
08217 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08218 {
08219   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08220   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
08221                                                                     REG_OFFSET_TAB_SETxR[iOutput]));
08222   return (uint32_t) READ_REG(*pReg);
08223 }
08224
08225 /**
08226   * @brief  Set the timer output reset source.
08227   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
08228   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
08229   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
08230   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
08231   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
08232   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
08233   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
08234   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
08235   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
08236   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
08237   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
08238   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
08239   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
08240   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
08241   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
08242   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
08243   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
08244   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
08245   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
08246   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
08247   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
08248   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
08249   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
08250   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
08251   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
08252   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
08253   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
08254   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
08255   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
08256   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
08257   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
08258   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc\n
08259   *         RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
08260   *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
08261   *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
08262   *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
08263   *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
08264   *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
08265   *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
08266   *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
08267   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
08268   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
08269   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
08270   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
08271   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
08272   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
08273   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
08274   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
08275   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
08276   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
08277   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
08278   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
08279   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
08280   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
08281   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
08282   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
08283   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
08284   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
08285   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
08286   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
08287   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
08288   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
08289   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
08290   *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc
08291   * @param  HRTIMx High Resolution Timer instance
08292   * @param  Output This parameter can be one of the following values:
08293   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08294   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08295   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08296   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08297   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08298   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08299   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08300   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08301   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08302   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08303   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08304   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08305   * @param ResetSrc This parameter can be a combination of the following values:
08306   *         @arg @ref LL_HRTIM_OUTPUTRESET_NONE
08307   *         @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
08308   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
08309   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
08310   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
08311   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
08312   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
08313   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
08314   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
08315   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
08316   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
08317   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
08318   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
08319   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
08320   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
08321   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
08322   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
08323   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
08324   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
08325   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
08326   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
08327   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
08328   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
08329   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
08330   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
08331   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
08332   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
08333   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
08334   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
08335   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
08336   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
08337   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
08338   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
08339   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
08340   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
08341   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
08342   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
08343   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
08344   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
08345   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
08346   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
08347   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
08348   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
08349   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
08350   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
08351   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
08352   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
08353   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
08354   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
08355   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
08356   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
08357   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
08358   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
08359   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
08360   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
08361   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
08362   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
08363   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
08364   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
08365   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
08366   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
08367   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
08368   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
08369   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
08370   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
08371   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
08372   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
08373   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
08374   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
08375   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
08376   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
08377   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
08378   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
08379   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
08380   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
08381   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
08382   *         @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
08383   *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
08384   * @retval None
08385   */
08386 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
08387 {
08388   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08389   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
08390                                                               REG_OFFSET_TAB_SETxR[iOutput]));
08391   WRITE_REG(*pReg, ResetSrc);
08392 }
08393
08394 /**
08395   * @brief  Get the timer output set source.
08396   * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
08397   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
08398   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
08399   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
08400   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
08401   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
08402   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
08403   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
08404   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
08405   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
08406   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
08407   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
08408   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
08409   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
08410   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
08411   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
08412   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
08413   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
08414   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
08415   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
08416   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
08417   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
08418   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
08419   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
08420   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
08421   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
08422   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
08423   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
08424   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
08425   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
08426   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
08427   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc\n
08428   *         RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
08429   *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
08430   *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
08431   *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
08432   *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
08433   *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
08434   *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
08435   *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
08436   *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
08437   *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
08438   *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
08439   *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
08440   *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
08441   *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
08442   *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
08443   *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
08444   *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
08445   *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
08446   *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
08447   *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
08448   *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
08449   *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
08450   *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
08451   *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
08452   *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
08453   *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
08454   *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
08455   *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
08456   *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
08457   *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
08458   *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
08459   *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc
08460   * @param  HRTIMx High Resolution Timer instance
08461   * @param  Output This parameter can be one of the following values:
08462   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08463   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08464   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08465   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08466   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08467   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08468   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08469   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08470   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08471   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08472   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08473   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08474   * @retval ResetSrc This parameter can be a combination of the following values:
08475   *         @arg @ref LL_HRTIM_OUTPUTRESET_NONE
08476   *         @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
08477   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
08478   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
08479   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
08480   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
08481   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
08482   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
08483   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
08484   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
08485   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
08486   *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
08487   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
08488   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
08489   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
08490   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
08491   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
08492   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
08493   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
08494   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
08495   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
08496   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
08497   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
08498   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
08499   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
08500   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
08501   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
08502   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
08503   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
08504   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
08505   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
08506   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
08507   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
08508   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
08509   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
08510   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
08511   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
08512   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
08513   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
08514   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
08515   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
08516   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
08517   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
08518   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
08519   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
08520   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
08521   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
08522   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
08523   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
08524   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
08525   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
08526   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
08527   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
08528   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
08529   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
08530   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
08531   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
08532   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
08533   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
08534   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
08535   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
08536   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
08537   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
08538   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
08539   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
08540   *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
08541   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
08542   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
08543   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
08544   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
08545   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
08546   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
08547   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
08548   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
08549   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
08550   *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
08551   *         @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
08552   *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
08553   */
08554 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08555 {
08556   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08557   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
08558                                                                     REG_OFFSET_TAB_SETxR[iOutput]));
08559   return (uint32_t) READ_REG(*pReg);
08560 }
08561
08562 /**
08563   * @brief  Configure a timer output.
08564   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_Config\n
08565   *         OUTxR      IDLEM1        LL_HRTIM_OUT_Config\n
08566   *         OUTxR      IDLES1        LL_HRTIM_OUT_Config\n
08567   *         OUTxR      FAULT1        LL_HRTIM_OUT_Config\n
08568   *         OUTxR      CHP1          LL_HRTIM_OUT_Config\n
08569   *         OUTxR      DIDL1         LL_HRTIM_OUT_Config\n
08570   *         OUTxR      POL2          LL_HRTIM_OUT_Config\n
08571   *         OUTxR      IDLEM2        LL_HRTIM_OUT_Config\n
08572   *         OUTxR      IDLES2        LL_HRTIM_OUT_Config\n
08573   *         OUTxR      FAULT2        LL_HRTIM_OUT_Config\n
08574   *         OUTxR      CHP2          LL_HRTIM_OUT_Config\n
08575   *         OUTxR      DIDL2         LL_HRTIM_OUT_Config
08576   * @param  HRTIMx High Resolution Timer instance
08577   * @param  Output This parameter can be one of the following values:
08578   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08579   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08580   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08581   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08582   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08583   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08584   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08585   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08586   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08587   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08588   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08589   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08590   * @param  Configuration This parameter must be a combination of all the following values:
08591   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
08592   *         @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
08593   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
08594   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
08595   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
08596   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
08597   * @retval None
08598   */
08599 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
08600 {
08601   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08602   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08603                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08604   MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
08605              (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
08606 }
08607
08608 /**
08609   * @brief  Set the polarity of a timer output.
08610   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_SetPolarity\n
08611   *         OUTxR      POL2          LL_HRTIM_OUT_SetPolarity
08612   * @param  HRTIMx High Resolution Timer instance
08613   * @param  Output This parameter can be one of the following values:
08614   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08615   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08616   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08617   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08618   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08619   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08620   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08621   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08622   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08623   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08624   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08625   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08626   * @param  Polarity This parameter can be one of the following values:
08627   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
08628   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
08629   * @retval None
08630   */
08631 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
08632 {
08633   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08634   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08635                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08636   MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
08637 }
08638
08639 /**
08640   * @brief  Get actual polarity of the timer output.
08641   * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_GetPolarity\n
08642   *         OUTxR      POL2          LL_HRTIM_OUT_GetPolarity
08643   * @param  HRTIMx High Resolution Timer instance
08644   * @param  Output This parameter can be one of the following values:
08645   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08646   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08647   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08648   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08649   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08650   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08651   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08652   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08653   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08654   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08655   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08656   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08657   * @retval Polarity This parameter can be one of the following values:
08658   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
08659   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
08660   */
08661 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08662 {
08663   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08664   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08665                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08666   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08667 }
08668
08669 /**
08670   * @brief  Set the output IDLE mode.
08671   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_SetIdleMode\n
08672   *         OUTxR      IDLEM2          LL_HRTIM_OUT_SetIdleMode
08673   * @note This function must not be called when the burst mode is active
08674   * @param  HRTIMx High Resolution Timer instance
08675   * @param  Output This parameter can be one of the following values:
08676   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08677   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08678   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08679   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08680   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08681   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08682   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08683   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08684   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08685   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08686   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08687   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08688   * @param  IdleMode This parameter can be one of the following values:
08689   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
08690   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
08691   * @retval None
08692   */
08693 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
08694 {
08695   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08696   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08697                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08698   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
08699 }
08700
08701 /**
08702   * @brief  Get actual output IDLE mode.
08703   * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_GetIdleMode\n
08704   *         OUTxR      IDLEM2          LL_HRTIM_OUT_GetIdleMode
08705   * @param  HRTIMx High Resolution Timer instance
08706   * @param  Output This parameter can be one of the following values:
08707   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08708   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08709   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08710   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08711   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08712   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08713   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08714   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08715   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08716   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08717   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08718   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08719   * @retval IdleMode This parameter can be one of the following values:
08720   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
08721   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
08722   */
08723 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08724 {
08725   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08726   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08727                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08728   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08729 }
08730
08731 /**
08732   * @brief  Set the output IDLE level.
08733   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_SetIdleLevel\n
08734   *         OUTxR      IDLES2          LL_HRTIM_OUT_SetIdleLevel
08735   * @note This function must be called prior enabling the timer.
08736   * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
08737   * @param  HRTIMx High Resolution Timer instance
08738   * @param  Output This parameter can be one of the following values:
08739   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08740   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08741   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08742   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08743   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08744   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08745   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08746   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08747   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08748   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08749   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08750   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08751   * @param  IdleLevel This parameter can be one of the following values:
08752   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
08753   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
08754   * @retval None
08755   */
08756 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
08757 {
08758   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08759   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08760                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08761   MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
08762 }
08763
08764 /**
08765   * @brief  Get actual output IDLE level.
08766   * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_GetIdleLevel\n
08767   *         OUTxR      IDLES2          LL_HRTIM_OUT_GetIdleLevel
08768   * @param  HRTIMx High Resolution Timer instance
08769   * @param  Output This parameter can be one of the following values:
08770   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08771   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08772   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08773   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08774   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08775   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08776   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08777   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08778   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08779   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08780   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08781   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08782   * @retval IdleLevel This parameter can be one of the following values:
08783   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
08784   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
08785   */
08786 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08787 {
08788   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08789   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08790                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08791   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08792 }
08793
08794 /**
08795   * @brief  Set the output FAULT state.
08796   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_SetFaultState\n
08797   *         OUTxR      FAULT2          LL_HRTIM_OUT_SetFaultState
08798   * @note This function must not called when the timer is enabled and a fault
08799   *       channel is enabled at timer level.
08800   * @param  HRTIMx High Resolution Timer instance
08801   * @param  Output This parameter can be one of the following values:
08802   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08803   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08804   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08805   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08806   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08807   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08808   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08809   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08810   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08811   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08812   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08813   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08814   * @param  FaultState This parameter can be one of the following values:
08815   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
08816   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
08817   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
08818   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
08819   * @retval None
08820   */
08821 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
08822 {
08823   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08824   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08825                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08826   MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
08827 }
08828
08829 /**
08830   * @brief  Get actual FAULT state.
08831   * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_GetFaultState\n
08832   *         OUTxR      FAULT2          LL_HRTIM_OUT_GetFaultState
08833   * @param  HRTIMx High Resolution Timer instance
08834   * @param  Output This parameter can be one of the following values:
08835   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08836   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08837   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08838   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08839   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08840   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08841   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08842   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08843   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08844   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08845   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08846   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08847   * @retval FaultState This parameter can be one of the following values:
08848   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
08849   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
08850   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
08851   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
08852   */
08853 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08854 {
08855   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08856   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08857                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08858   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08859 }
08860
08861 /**
08862   * @brief  Set the output chopper mode.
08863   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_SetChopperMode\n
08864   *         OUTxR      CHP2          LL_HRTIM_OUT_SetChopperMode
08865   * @note This function must not called when the timer is enabled.
08866   * @param  HRTIMx High Resolution Timer instance
08867   * @param  Output This parameter can be one of the following values:
08868   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08869   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08870   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08871   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08872   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08873   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08874   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08875   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08876   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08877   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08878   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08879   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08880   * @param  ChopperMode This parameter can be one of the following values:
08881   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
08882   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
08883   * @retval None
08884   */
08885 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
08886 {
08887   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08888   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08889                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08890   MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
08891 }
08892
08893 /**
08894   * @brief  Get actual output chopper mode
08895   * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_GetChopperMode\n
08896   *         OUTxR      CHP2          LL_HRTIM_OUT_GetChopperMode
08897   * @param  HRTIMx High Resolution Timer instance
08898   * @param  Output This parameter can be one of the following values:
08899   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08900   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08901   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08902   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08903   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08904   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08905   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08906   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08907   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08908   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08909   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08910   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08911   * @retval ChopperMode This parameter can be one of the following values:
08912   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
08913   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
08914   */
08915 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08916 {
08917   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08918   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08919                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08920   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08921 }
08922
08923 /**
08924   * @brief  Set the output burst mode entry mode.
08925   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_SetBMEntryMode\n
08926   *         OUTxR      DIDL2          LL_HRTIM_OUT_SetBMEntryMode
08927   * @note This function must not called when the timer is enabled.
08928   * @param  HRTIMx High Resolution Timer instance
08929   * @param  Output This parameter can be one of the following values:
08930   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08931   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08932   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08933   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08934   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08935   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08936   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08937   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08938   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08939   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08940   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08941   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08942   * @param  BMEntryMode This parameter can be one of the following values:
08943   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
08944   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
08945   * @retval None
08946   */
08947 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
08948 {
08949   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08950   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08951                                                               REG_OFFSET_TAB_OUTxR[iOutput]));
08952   MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
08953 }
08954
08955 /**
08956   * @brief  Get actual output burst mode entry mode.
08957   * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_GetBMEntryMode\n
08958   *         OUTxR      DIDL2          LL_HRTIM_OUT_GetBMEntryMode
08959   * @param  HRTIMx High Resolution Timer instance
08960   * @param  Output This parameter can be one of the following values:
08961   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08962   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08963   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08964   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08965   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08966   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08967   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08968   *         @arg @ref LL_HRTIM_OUTPUT_TD2
08969   *         @arg @ref LL_HRTIM_OUTPUT_TE1
08970   *         @arg @ref LL_HRTIM_OUTPUT_TE2
08971   *         @arg @ref LL_HRTIM_OUTPUT_TF1
08972   *         @arg @ref LL_HRTIM_OUTPUT_TF2
08973   * @retval BMEntryMode This parameter can be one of the following values:
08974   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
08975   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
08976   */
08977 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
08978 {
08979   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
08980   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
08981                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
08982   return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
08983 }
08984
08985 /**
08986   * @brief  Get the level (active or inactive) of the designated output when the
08987   *         delayed protection was triggered.
08988   * @rmtoll TIMxISR      O1SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus\n
08989   *         TIMxISR      O2SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus
08990   * @param  HRTIMx High Resolution Timer instance
08991   * @param  Output This parameter can be one of the following values:
08992   *         @arg @ref LL_HRTIM_OUTPUT_TA1
08993   *         @arg @ref LL_HRTIM_OUTPUT_TA2
08994   *         @arg @ref LL_HRTIM_OUTPUT_TB1
08995   *         @arg @ref LL_HRTIM_OUTPUT_TB2
08996   *         @arg @ref LL_HRTIM_OUTPUT_TC1
08997   *         @arg @ref LL_HRTIM_OUTPUT_TC2
08998   *         @arg @ref LL_HRTIM_OUTPUT_TD1
08999   *         @arg @ref LL_HRTIM_OUTPUT_TD2
09000   *         @arg @ref LL_HRTIM_OUTPUT_TE1
09001   *         @arg @ref LL_HRTIM_OUTPUT_TE2
09002   *         @arg @ref LL_HRTIM_OUTPUT_TF1
09003   *         @arg @ref LL_HRTIM_OUTPUT_TF2
09004   * @retval OutputLevel This parameter can be one of the following values:
09005   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
09006   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
09007   */
09008 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
09009 {
09010   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
09011   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
09012                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
09013   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
09014           HRTIM_TIMISR_O1STAT_Pos);
09015 }
09016
09017 /**
09018   * @brief  Force the timer output to its active or inactive level.
09019   * @rmtoll SETx1R      SST          LL_HRTIM_OUT_ForceLevel\n
09020   *         RSTx1R      SRT          LL_HRTIM_OUT_ForceLevel\n
09021   *         SETx2R      SST          LL_HRTIM_OUT_ForceLevel\n
09022   *         RSTx2R      SRT          LL_HRTIM_OUT_ForceLevel
09023   * @param  HRTIMx High Resolution Timer instance
09024   * @param  Output This parameter can be one of the following values:
09025   *         @arg @ref LL_HRTIM_OUTPUT_TA1
09026   *         @arg @ref LL_HRTIM_OUTPUT_TA2
09027   *         @arg @ref LL_HRTIM_OUTPUT_TB1
09028   *         @arg @ref LL_HRTIM_OUTPUT_TB2
09029   *         @arg @ref LL_HRTIM_OUTPUT_TC1
09030   *         @arg @ref LL_HRTIM_OUTPUT_TC2
09031   *         @arg @ref LL_HRTIM_OUTPUT_TD1
09032   *         @arg @ref LL_HRTIM_OUTPUT_TD2
09033   *         @arg @ref LL_HRTIM_OUTPUT_TE1
09034   *         @arg @ref LL_HRTIM_OUTPUT_TE2
09035   *         @arg @ref LL_HRTIM_OUTPUT_TF1
09036   *         @arg @ref LL_HRTIM_OUTPUT_TF2
09037   * @param  OutputLevel This parameter can be one of the following values:
09038   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
09039   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
09040   * @retval None
09041   */
09042 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
09043 {
09044   const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
09045   {
09046     0x04U,   /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE  */
09047     0x00U    /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE  */
09048   };
09049
09050   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
09051   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
09052                                                               REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
09053   SET_BIT(*pReg, HRTIM_SET1R_SST);
09054 }
09055
09056 /**
09057   * @brief  Get actual output level, before the output stage (chopper, polarity).
09058   * @rmtoll TIMxISR     O1CPY          LL_HRTIM_OUT_GetLevel\n
09059   *         TIMxISR     O2CPY          LL_HRTIM_OUT_GetLevel
09060   * @param  HRTIMx High Resolution Timer instance
09061   * @param  Output This parameter can be one of the following values:
09062   *         @arg @ref LL_HRTIM_OUTPUT_TA1
09063   *         @arg @ref LL_HRTIM_OUTPUT_TA2
09064   *         @arg @ref LL_HRTIM_OUTPUT_TB1
09065   *         @arg @ref LL_HRTIM_OUTPUT_TB2
09066   *         @arg @ref LL_HRTIM_OUTPUT_TC1
09067   *         @arg @ref LL_HRTIM_OUTPUT_TC2
09068   *         @arg @ref LL_HRTIM_OUTPUT_TD1
09069   *         @arg @ref LL_HRTIM_OUTPUT_TD2
09070   *         @arg @ref LL_HRTIM_OUTPUT_TE1
09071   *         @arg @ref LL_HRTIM_OUTPUT_TE2
09072   *         @arg @ref LL_HRTIM_OUTPUT_TF1
09073   *         @arg @ref LL_HRTIM_OUTPUT_TF2
09074   * @retval OutputLevel This parameter can be one of the following values:
09075   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
09076   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
09077   */
09078 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
09079 {
09080   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
09081   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
09082                                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
09083   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
09084           HRTIM_TIMISR_O1CPY_Pos);
09085 }
09086
09087 /**
09088   * @}
09089   */
09090
09091 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
09092   * @{
09093   */
09094
09095 /**
09096   * @brief  Configure external event conditioning.
09097   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_Config\n
09098   *         EECR1     EE1POL          LL_HRTIM_EE_Config\n
09099   *         EECR1     EE1SNS          LL_HRTIM_EE_Config\n
09100   *         EECR1     EE1FAST         LL_HRTIM_EE_Config\n
09101   *         EECR1     EE2SRC          LL_HRTIM_EE_Config\n
09102   *         EECR1     EE2POL          LL_HRTIM_EE_Config\n
09103   *         EECR1     EE2SNS          LL_HRTIM_EE_Config\n
09104   *         EECR1     EE2FAST         LL_HRTIM_EE_Config\n
09105   *         EECR1     EE3SRC          LL_HRTIM_EE_Config\n
09106   *         EECR1     EE3POL          LL_HRTIM_EE_Config\n
09107   *         EECR1     EE3SNS          LL_HRTIM_EE_Config\n
09108   *         EECR1     EE3FAST         LL_HRTIM_EE_Config\n
09109   *         EECR1     EE4SRC          LL_HRTIM_EE_Config\n
09110   *         EECR1     EE4POL          LL_HRTIM_EE_Config\n
09111   *         EECR1     EE4SNS          LL_HRTIM_EE_Config\n
09112   *         EECR1     EE4FAST         LL_HRTIM_EE_Config\n
09113   *         EECR1     EE5SRC          LL_HRTIM_EE_Config\n
09114   *         EECR1     EE5POL          LL_HRTIM_EE_Config\n
09115   *         EECR1     EE5SNS          LL_HRTIM_EE_Config\n
09116   *         EECR1     EE5FAST         LL_HRTIM_EE_Config\n
09117   *         EECR2     EE6SRC          LL_HRTIM_EE_Config\n
09118   *         EECR2     EE6POL          LL_HRTIM_EE_Config\n
09119   *         EECR2     EE6SNS          LL_HRTIM_EE_Config\n
09120   *         EECR2     EE6FAST         LL_HRTIM_EE_Config\n
09121   *         EECR2     EE7SRC          LL_HRTIM_EE_Config\n
09122   *         EECR2     EE7POL          LL_HRTIM_EE_Config\n
09123   *         EECR2     EE7SNS          LL_HRTIM_EE_Config\n
09124   *         EECR2     EE7FAST         LL_HRTIM_EE_Config\n
09125   *         EECR2     EE8SRC          LL_HRTIM_EE_Config\n
09126   *         EECR2     EE8POL          LL_HRTIM_EE_Config\n
09127   *         EECR2     EE8SNS          LL_HRTIM_EE_Config\n
09128   *         EECR2     EE8FAST         LL_HRTIM_EE_Config\n
09129   *         EECR2     EE9SRC          LL_HRTIM_EE_Config\n
09130   *         EECR2     EE9POL          LL_HRTIM_EE_Config\n
09131   *         EECR2     EE9SNS          LL_HRTIM_EE_Config\n
09132   *         EECR2     EE9FAST         LL_HRTIM_EE_Config\n
09133   *         EECR2     EE10SRC         LL_HRTIM_EE_Config\n
09134   *         EECR2     EE10POL         LL_HRTIM_EE_Config\n
09135   *         EECR2     EE10SNS         LL_HRTIM_EE_Config\n
09136   *         EECR2     EE10FAST        LL_HRTIM_EE_Config
09137   * @note This function must not be called when the timer counter is enabled.
09138   * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
09139   * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
09140   * @param  HRTIMx High Resolution Timer instance
09141   * @param  Event This parameter can be one of the following values:
09142   *         @arg @ref LL_HRTIM_EVENT_1
09143   *         @arg @ref LL_HRTIM_EVENT_2
09144   *         @arg @ref LL_HRTIM_EVENT_3
09145   *         @arg @ref LL_HRTIM_EVENT_4
09146   *         @arg @ref LL_HRTIM_EVENT_5
09147   *         @arg @ref LL_HRTIM_EVENT_6
09148   *         @arg @ref LL_HRTIM_EVENT_7
09149   *         @arg @ref LL_HRTIM_EVENT_8
09150   *         @arg @ref LL_HRTIM_EVENT_9
09151   *         @arg @ref LL_HRTIM_EVENT_10
09152   * @param  Configuration This parameter must be a combination of all the following values:
09153   *         @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
09154   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
09155   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
09156   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
09157   * @retval None
09158   */
09159 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
09160 {
09161   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09162   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09163                                                               REG_OFFSET_TAB_EECR[iEvent]));
09164   MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
09165              (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
09166 }
09167
09168 /**
09169   * @brief  Set the external event source.
09170   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_SetSrc\n
09171   *         EECR1     EE2SRC          LL_HRTIM_EE_SetSrc\n
09172   *         EECR1     EE3SRC          LL_HRTIM_EE_SetSrc\n
09173   *         EECR1     EE4SRC          LL_HRTIM_EE_SetSrc\n
09174   *         EECR1     EE5SRC          LL_HRTIM_EE_SetSrc\n
09175   *         EECR2     EE6SRC          LL_HRTIM_EE_SetSrc\n
09176   *         EECR2     EE7SRC          LL_HRTIM_EE_SetSrc\n
09177   *         EECR2     EE8SRC          LL_HRTIM_EE_SetSrc\n
09178   *         EECR2     EE9SRC          LL_HRTIM_EE_SetSrc\n
09179   *         EECR2     EE10SRC         LL_HRTIM_EE_SetSrc
09180   * @param  HRTIMx High Resolution Timer instance
09181   * @param  Event This parameter can be one of the following values:
09182   *         @arg @ref LL_HRTIM_EVENT_1
09183   *         @arg @ref LL_HRTIM_EVENT_2
09184   *         @arg @ref LL_HRTIM_EVENT_3
09185   *         @arg @ref LL_HRTIM_EVENT_4
09186   *         @arg @ref LL_HRTIM_EVENT_5
09187   *         @arg @ref LL_HRTIM_EVENT_6
09188   *         @arg @ref LL_HRTIM_EVENT_7
09189   *         @arg @ref LL_HRTIM_EVENT_8
09190   *         @arg @ref LL_HRTIM_EVENT_9
09191   *         @arg @ref LL_HRTIM_EVENT_10
09192   * @param  Src This parameter can be one of the following values:
09193   *         @arg External event source 1
09194   *         @arg External event source 2
09195   *         @arg External event source 3
09196   *         @arg External event source 4
09197   * @retval None
09198   */
09199 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
09200 {
09201   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09202   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09203                                                               REG_OFFSET_TAB_EECR[iEvent]));
09204   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
09205 }
09206
09207 /**
09208   * @brief  Get actual external event source.
09209   * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_GetSrc\n
09210   *         EECR1     EE2SRC          LL_HRTIM_EE_GetSrc\n
09211   *         EECR1     EE3SRC          LL_HRTIM_EE_GetSrc\n
09212   *         EECR1     EE4SRC          LL_HRTIM_EE_GetSrc\n
09213   *         EECR1     EE5SRC          LL_HRTIM_EE_GetSrc\n
09214   *         EECR2     EE6SRC          LL_HRTIM_EE_GetSrc\n
09215   *         EECR2     EE7SRC          LL_HRTIM_EE_GetSrc\n
09216   *         EECR2     EE8SRC          LL_HRTIM_EE_GetSrc\n
09217   *         EECR2     EE9SRC          LL_HRTIM_EE_GetSrc\n
09218   *         EECR2     EE10SRC         LL_HRTIM_EE_GetSrc
09219   * @param  HRTIMx High Resolution Timer instance
09220   * @param  Event This parameter can be one of the following values:
09221   *         @arg @ref LL_HRTIM_EVENT_1
09222   *         @arg @ref LL_HRTIM_EVENT_2
09223   *         @arg @ref LL_HRTIM_EVENT_3
09224   *         @arg @ref LL_HRTIM_EVENT_4
09225   *         @arg @ref LL_HRTIM_EVENT_5
09226   *         @arg @ref LL_HRTIM_EVENT_6
09227   *         @arg @ref LL_HRTIM_EVENT_7
09228   *         @arg @ref LL_HRTIM_EVENT_8
09229   *         @arg @ref LL_HRTIM_EVENT_9
09230   *         @arg @ref LL_HRTIM_EVENT_10
09231   * @retval EventSrc This parameter can be one of the following values:
09232   *         @arg External event source 1
09233   *         @arg External event source 2
09234   *         @arg External event source 3
09235   *         @arg External event source 4
09236   */
09237 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
09238 {
09239   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09240   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09241                                                                     REG_OFFSET_TAB_EECR[iEvent]));
09242   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
09243 }
09244
09245 /**
09246   * @brief  Set the polarity of an external event.
09247   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_SetPolarity\n
09248   *         EECR1     EE2POL          LL_HRTIM_EE_SetPolarity\n
09249   *         EECR1     EE3POL          LL_HRTIM_EE_SetPolarity\n
09250   *         EECR1     EE4POL          LL_HRTIM_EE_SetPolarity\n
09251   *         EECR1     EE5POL          LL_HRTIM_EE_SetPolarity\n
09252   *         EECR2     EE6POL          LL_HRTIM_EE_SetPolarity\n
09253   *         EECR2     EE7POL          LL_HRTIM_EE_SetPolarity\n
09254   *         EECR2     EE8POL          LL_HRTIM_EE_SetPolarity\n
09255   *         EECR2     EE9POL          LL_HRTIM_EE_SetPolarity\n
09256   *         EECR2     EE10POL         LL_HRTIM_EE_SetPolarity
09257   * @note This function must not be called when the timer counter is enabled.
09258   * @note Event polarity is only significant when event detection is level-sensitive.
09259   * @param  HRTIMx High Resolution Timer instance
09260   * @param  Event This parameter can be one of the following values:
09261   *         @arg @ref LL_HRTIM_EVENT_1
09262   *         @arg @ref LL_HRTIM_EVENT_2
09263   *         @arg @ref LL_HRTIM_EVENT_3
09264   *         @arg @ref LL_HRTIM_EVENT_4
09265   *         @arg @ref LL_HRTIM_EVENT_5
09266   *         @arg @ref LL_HRTIM_EVENT_6
09267   *         @arg @ref LL_HRTIM_EVENT_7
09268   *         @arg @ref LL_HRTIM_EVENT_8
09269   *         @arg @ref LL_HRTIM_EVENT_9
09270   *         @arg @ref LL_HRTIM_EVENT_10
09271   * @param  Polarity This parameter can be one of the following values:
09272   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
09273   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
09274   * @retval None
09275   */
09276 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
09277 {
09278   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09279   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09280                                                               REG_OFFSET_TAB_EECR[iEvent]));
09281   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
09282 }
09283
09284 /**
09285   * @brief  Get actual polarity setting of an external event.
09286   * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_GetPolarity\n
09287   *         EECR1     EE2POL          LL_HRTIM_EE_GetPolarity\n
09288   *         EECR1     EE3POL          LL_HRTIM_EE_GetPolarity\n
09289   *         EECR1     EE4POL          LL_HRTIM_EE_GetPolarity\n
09290   *         EECR1     EE5POL          LL_HRTIM_EE_GetPolarity\n
09291   *         EECR2     EE6POL          LL_HRTIM_EE_GetPolarity\n
09292   *         EECR2     EE7POL          LL_HRTIM_EE_GetPolarity\n
09293   *         EECR2     EE8POL          LL_HRTIM_EE_GetPolarity\n
09294   *         EECR2     EE9POL          LL_HRTIM_EE_GetPolarity\n
09295   *         EECR2     EE10POL         LL_HRTIM_EE_GetPolarity
09296   * @param  HRTIMx High Resolution Timer instance
09297   * @param  Event This parameter can be one of the following values:
09298   *         @arg @ref LL_HRTIM_EVENT_1
09299   *         @arg @ref LL_HRTIM_EVENT_2
09300   *         @arg @ref LL_HRTIM_EVENT_3
09301   *         @arg @ref LL_HRTIM_EVENT_4
09302   *         @arg @ref LL_HRTIM_EVENT_5
09303   *         @arg @ref LL_HRTIM_EVENT_6
09304   *         @arg @ref LL_HRTIM_EVENT_7
09305   *         @arg @ref LL_HRTIM_EVENT_8
09306   *         @arg @ref LL_HRTIM_EVENT_9
09307   *         @arg @ref LL_HRTIM_EVENT_10
09308   * @retval Polarity This parameter can be one of the following values:
09309   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
09310   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
09311   */
09312 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
09313 {
09314   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09315   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09316                                                                     REG_OFFSET_TAB_EECR[iEvent]));
09317   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
09318 }
09319
09320 /**
09321   * @brief  Set the sensitivity of an external event.
09322   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_SetSensitivity\n
09323   *         EECR1     EE2SNS          LL_HRTIM_EE_SetSensitivity\n
09324   *         EECR1     EE3SNS          LL_HRTIM_EE_SetSensitivity\n
09325   *         EECR1     EE4SNS          LL_HRTIM_EE_SetSensitivity\n
09326   *         EECR1     EE5SNS          LL_HRTIM_EE_SetSensitivity\n
09327   *         EECR2     EE6SNS          LL_HRTIM_EE_SetSensitivity\n
09328   *         EECR2     EE7SNS          LL_HRTIM_EE_SetSensitivity\n
09329   *         EECR2     EE8SNS          LL_HRTIM_EE_SetSensitivity\n
09330   *         EECR2     EE9SNS          LL_HRTIM_EE_SetSensitivity\n
09331   *         EECR2     EE10SNS         LL_HRTIM_EE_SetSensitivity
09332   * @param  HRTIMx High Resolution Timer instance
09333   * @param  Event This parameter can be one of the following values:
09334   *         @arg @ref LL_HRTIM_EVENT_1
09335   *         @arg @ref LL_HRTIM_EVENT_2
09336   *         @arg @ref LL_HRTIM_EVENT_3
09337   *         @arg @ref LL_HRTIM_EVENT_4
09338   *         @arg @ref LL_HRTIM_EVENT_5
09339   *         @arg @ref LL_HRTIM_EVENT_6
09340   *         @arg @ref LL_HRTIM_EVENT_7
09341   *         @arg @ref LL_HRTIM_EVENT_8
09342   *         @arg @ref LL_HRTIM_EVENT_9
09343   *         @arg @ref LL_HRTIM_EVENT_10
09344   * @param  Sensitivity This parameter can be one of the following values:
09345   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
09346   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
09347   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
09348   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
09349   * @retval None
09350   */
09351
09352 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
09353 {
09354   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09355   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09356                                                               REG_OFFSET_TAB_EECR[iEvent]));
09357   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
09358 }
09359
09360 /**
09361   * @brief  Get actual sensitivity setting of an external event.
09362   * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_GetSensitivity\n
09363   *         EECR1     EE2SNS          LL_HRTIM_EE_GetSensitivity\n
09364   *         EECR1     EE3SNS          LL_HRTIM_EE_GetSensitivity\n
09365   *         EECR1     EE4SNS          LL_HRTIM_EE_GetSensitivity\n
09366   *         EECR1     EE5SNS          LL_HRTIM_EE_GetSensitivity\n
09367   *         EECR2     EE6SNS          LL_HRTIM_EE_GetSensitivity\n
09368   *         EECR2     EE7SNS          LL_HRTIM_EE_GetSensitivity\n
09369   *         EECR2     EE8SNS          LL_HRTIM_EE_GetSensitivity\n
09370   *         EECR2     EE9SNS          LL_HRTIM_EE_GetSensitivity\n
09371   *         EECR2     EE10SNS         LL_HRTIM_EE_GetSensitivity
09372   * @param  HRTIMx High Resolution Timer instance
09373   * @param  Event This parameter can be one of the following values:
09374   *         @arg @ref LL_HRTIM_EVENT_1
09375   *         @arg @ref LL_HRTIM_EVENT_2
09376   *         @arg @ref LL_HRTIM_EVENT_3
09377   *         @arg @ref LL_HRTIM_EVENT_4
09378   *         @arg @ref LL_HRTIM_EVENT_5
09379   *         @arg @ref LL_HRTIM_EVENT_6
09380   *         @arg @ref LL_HRTIM_EVENT_7
09381   *         @arg @ref LL_HRTIM_EVENT_8
09382   *         @arg @ref LL_HRTIM_EVENT_9
09383   *         @arg @ref LL_HRTIM_EVENT_10
09384   * @retval Polarity This parameter can be one of the following values:
09385   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
09386   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
09387   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
09388   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
09389   */
09390 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
09391 {
09392   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09393   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09394                                                                     REG_OFFSET_TAB_EECR[iEvent]));
09395   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
09396 }
09397
09398 /**
09399   * @brief  Set the fast mode of an external event.
09400   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_SetFastMode\n
09401   *         EECR1     EE2FAST         LL_HRTIM_EE_SetFastMode\n
09402   *         EECR1     EE3FAST         LL_HRTIM_EE_SetFastMode\n
09403   *         EECR1     EE4FAST         LL_HRTIM_EE_SetFastMode\n
09404   *         EECR1     EE5FAST         LL_HRTIM_EE_SetFastMode\n
09405   *         EECR2     EE6FAST         LL_HRTIM_EE_SetFastMode\n
09406   *         EECR2     EE7FAST         LL_HRTIM_EE_SetFastMode\n
09407   *         EECR2     EE8FAST         LL_HRTIM_EE_SetFastMode\n
09408   *         EECR2     EE9FAST         LL_HRTIM_EE_SetFastMode\n
09409   *         EECR2     EE10FAST        LL_HRTIM_EE_SetFastMode
09410   * @note This function must not be called when the timer counter is enabled.
09411   * @param  HRTIMx High Resolution Timer instance
09412   * @param  Event This parameter can be one of the following values:
09413   *         @arg @ref LL_HRTIM_EVENT_1
09414   *         @arg @ref LL_HRTIM_EVENT_2
09415   *         @arg @ref LL_HRTIM_EVENT_3
09416   *         @arg @ref LL_HRTIM_EVENT_4
09417   *         @arg @ref LL_HRTIM_EVENT_5
09418   * @param  FastMode This parameter can be one of the following values:
09419   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
09420   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
09421   * @retval None
09422   */
09423 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
09424 {
09425   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09426   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09427                                                               REG_OFFSET_TAB_EECR[iEvent]));
09428   MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
09429 }
09430
09431 /**
09432   * @brief  Get actual fast mode setting of an external event.
09433   * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_GetFastMode\n
09434   *         EECR1     EE2FAST         LL_HRTIM_EE_GetFastMode\n
09435   *         EECR1     EE3FAST         LL_HRTIM_EE_GetFastMode\n
09436   *         EECR1     EE4FAST         LL_HRTIM_EE_GetFastMode\n
09437   *         EECR1     EE5FAST         LL_HRTIM_EE_GetFastMode\n
09438   *         EECR2     EE6FAST         LL_HRTIM_EE_GetFastMode\n
09439   *         EECR2     EE7FAST         LL_HRTIM_EE_GetFastMode\n
09440   *         EECR2     EE8FAST         LL_HRTIM_EE_GetFastMode\n
09441   *         EECR2     EE9FAST         LL_HRTIM_EE_GetFastMode\n
09442   *         EECR2     EE10FAST        LL_HRTIM_EE_GetFastMode
09443   * @param  HRTIMx High Resolution Timer instance
09444   * @param  Event This parameter can be one of the following values:
09445   *         @arg @ref LL_HRTIM_EVENT_1
09446   *         @arg @ref LL_HRTIM_EVENT_2
09447   *         @arg @ref LL_HRTIM_EVENT_3
09448   *         @arg @ref LL_HRTIM_EVENT_4
09449   *         @arg @ref LL_HRTIM_EVENT_5
09450   * @retval FastMode This parameter can be one of the following values:
09451   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
09452   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
09453   */
09454 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
09455 {
09456   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09457   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
09458                                                                     REG_OFFSET_TAB_EECR[iEvent]));
09459   return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
09460 }
09461
09462 /**
09463   * @brief  Set the digital noise filter of a external event.
09464   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_SetFilter\n
09465   *         EECR3     EE7F         LL_HRTIM_EE_SetFilter\n
09466   *         EECR3     EE8F         LL_HRTIM_EE_SetFilter\n
09467   *         EECR3     EE9F         LL_HRTIM_EE_SetFilter\n
09468   *         EECR3     EE10F        LL_HRTIM_EE_SetFilter
09469   * @param  HRTIMx High Resolution Timer instance
09470   * @param  Event This parameter can be one of the following values:
09471   *         @arg @ref LL_HRTIM_EVENT_6
09472   *         @arg @ref LL_HRTIM_EVENT_7
09473   *         @arg @ref LL_HRTIM_EVENT_8
09474   *         @arg @ref LL_HRTIM_EVENT_9
09475   *         @arg @ref LL_HRTIM_EVENT_10
09476   * @param  Filter This parameter can be one of the following values:
09477   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
09478   *         @arg @ref LL_HRTIM_EE_FILTER_1
09479   *         @arg @ref LL_HRTIM_EE_FILTER_2
09480   *         @arg @ref LL_HRTIM_EE_FILTER_3
09481   *         @arg @ref LL_HRTIM_EE_FILTER_4
09482   *         @arg @ref LL_HRTIM_EE_FILTER_5
09483   *         @arg @ref LL_HRTIM_EE_FILTER_6
09484   *         @arg @ref LL_HRTIM_EE_FILTER_7
09485   *         @arg @ref LL_HRTIM_EE_FILTER_8
09486   *         @arg @ref LL_HRTIM_EE_FILTER_9
09487   *         @arg @ref LL_HRTIM_EE_FILTER_10
09488   *         @arg @ref LL_HRTIM_EE_FILTER_11
09489   *         @arg @ref LL_HRTIM_EE_FILTER_12
09490   *         @arg @ref LL_HRTIM_EE_FILTER_13
09491   *         @arg @ref LL_HRTIM_EE_FILTER_14
09492   *         @arg @ref LL_HRTIM_EE_FILTER_15
09493   * @retval None
09494   */
09495 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
09496 {
09497   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
09498   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
09499              (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
09500 }
09501
09502 /**
09503   * @brief  Get actual digital noise filter setting of a external event.
09504   * @rmtoll EECR3     EE6F         LL_HRTIM_EE_GetFilter\n
09505   *         EECR3     EE7F         LL_HRTIM_EE_GetFilter\n
09506   *         EECR3     EE8F         LL_HRTIM_EE_GetFilter\n
09507   *         EECR3     EE9F         LL_HRTIM_EE_GetFilter\n
09508   *         EECR3     EE10F        LL_HRTIM_EE_GetFilter
09509   * @param  HRTIMx High Resolution Timer instance
09510   * @param  Event This parameter can be one of the following values:
09511   *         @arg @ref LL_HRTIM_EVENT_6
09512   *         @arg @ref LL_HRTIM_EVENT_7
09513   *         @arg @ref LL_HRTIM_EVENT_8
09514   *         @arg @ref LL_HRTIM_EVENT_9
09515   *         @arg @ref LL_HRTIM_EVENT_10
09516   * @retval Filter This parameter can be one of the following values:
09517   *         @arg @ref LL_HRTIM_EE_FILTER_NONE
09518   *         @arg @ref LL_HRTIM_EE_FILTER_1
09519   *         @arg @ref LL_HRTIM_EE_FILTER_2
09520   *         @arg @ref LL_HRTIM_EE_FILTER_3
09521   *         @arg @ref LL_HRTIM_EE_FILTER_4
09522   *         @arg @ref LL_HRTIM_EE_FILTER_5
09523   *         @arg @ref LL_HRTIM_EE_FILTER_6
09524   *         @arg @ref LL_HRTIM_EE_FILTER_7
09525   *         @arg @ref LL_HRTIM_EE_FILTER_8
09526   *         @arg @ref LL_HRTIM_EE_FILTER_9
09527   *         @arg @ref LL_HRTIM_EE_FILTER_10
09528   *         @arg @ref LL_HRTIM_EE_FILTER_11
09529   *         @arg @ref LL_HRTIM_EE_FILTER_12
09530   *         @arg @ref LL_HRTIM_EE_FILTER_13
09531   *         @arg @ref LL_HRTIM_EE_FILTER_14
09532   *         @arg @ref LL_HRTIM_EE_FILTER_15
09533   */
09534 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
09535 {
09536   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
09537   return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
09538                    (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
09539 }
09540
09541 /**
09542   * @brief  Set the external event prescaler.
09543   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_SetPrescaler
09544   * @param  HRTIMx High Resolution Timer instance
09545   * @param  Prescaler This parameter can be one of the following values:
09546   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
09547   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
09548   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
09549   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
09550   * @retval None
09551   */
09552
09553 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
09554 {
09555   MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
09556 }
09557
09558 /**
09559   * @brief  Get actual external event prescaler setting.
09560   * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_GetPrescaler
09561   * @param  HRTIMx High Resolution Timer instance
09562   * @retval Prescaler This parameter can be one of the following values:
09563   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
09564   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
09565   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
09566   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
09567   */
09568
09569 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
09570 {
09571   return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
09572 }
09573
09574 /**
09575   * @}
09576   */
09577
09578 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
09579   * @{
09580   */
09581 /**
09582   * @brief  Configure fault signal conditioning Polarity and Source.
09583   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_Config\n
09584   *         FLTINR1     FLT1SRC      LL_HRTIM_FLT_Config\n
09585   *         FLTINR1     FLT2P        LL_HRTIM_FLT_Config\n
09586   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_Config\n
09587   *         FLTINR1     FLT3P        LL_HRTIM_FLT_Config\n
09588   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_Config\n
09589   *         FLTINR1     FLT4P        LL_HRTIM_FLT_Config\n
09590   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_Config\n
09591   *         FLTINR2     FLT5P        LL_HRTIM_FLT_Config\n
09592   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_Config\n
09593   *         FLTINR2     FLT6P        LL_HRTIM_FLT_Config\n
09594   *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_Config
09595   * @note This function must not be called when the fault channel is enabled.
09596   * @param  HRTIMx High Resolution Timer instance
09597   * @param  Fault This parameter can be one of the following values:
09598   *         @arg @ref LL_HRTIM_FAULT_1
09599   *         @arg @ref LL_HRTIM_FAULT_2
09600   *         @arg @ref LL_HRTIM_FAULT_3
09601   *         @arg @ref LL_HRTIM_FAULT_4
09602   *         @arg @ref LL_HRTIM_FAULT_5
09603   *         @arg @ref LL_HRTIM_FAULT_6
09604   * @param  Configuration This parameter must be a combination of all the following values:
09605   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
09606   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
09607   * @retval None
09608   */
09609 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
09610 {
09611   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09612   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09613   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09614
09615   uint64_t cfg;
09616   uint64_t mask;
09617
09618   cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) |           /* this for SouRCe 0 and polarity bits */
09619         (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U);      /* this for SouRCe 1 bit  */
09620
09621   mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |       /* this for SouRCe 0 and polarity bits */
09622          ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U);                                                         /* this for SouRCe bit 1 */
09623
09624   MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
09625   MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
09626
09627 }
09628
09629 /**
09630   * @brief  Set the source of a fault signal.
09631   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_SetSrc\n
09632   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_SetSrc\n
09633   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_SetSrc\n
09634   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_SetSrc\n
09635   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_SetSrc\n
09636   *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_SetSrc
09637   * @note This function must not be called when the fault channel is enabled.
09638   * @param  HRTIMx High Resolution Timer instance
09639   * @param  Fault This parameter can be one of the following values:
09640   *         @arg @ref LL_HRTIM_FAULT_1
09641   *         @arg @ref LL_HRTIM_FAULT_2
09642   *         @arg @ref LL_HRTIM_FAULT_3
09643   *         @arg @ref LL_HRTIM_FAULT_4
09644   *         @arg @ref LL_HRTIM_FAULT_5
09645   *         @arg @ref LL_HRTIM_FAULT_6
09646   * @param  Src This parameter can be one of the following values:
09647   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
09648   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
09649   *         @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
09650   * @retval None
09651   */
09652 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
09653 {
09654   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09655   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09656   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09657
09658   uint64_t  cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |       /* this for SouRCe 0 bit */
09659                   (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK)    << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
09660   uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |       /* this for SouRCe bit 0 */
09661                   (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
09662
09663   MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
09664   MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
09665 }
09666
09667 /**
09668   * @brief  Get actual source of a fault signal.
09669   * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_GetSrc\n
09670   *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_GetSrc\n
09671   *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_GetSrc\n
09672   *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_GetSrc\n
09673   *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_GetSrc\n
09674   *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_GetSrc
09675   * @param  HRTIMx High Resolution Timer instance
09676   * @param  Fault This parameter can be one of the following values:
09677   *         @arg @ref LL_HRTIM_FAULT_1
09678   *         @arg @ref LL_HRTIM_FAULT_2
09679   *         @arg @ref LL_HRTIM_FAULT_3
09680   *         @arg @ref LL_HRTIM_FAULT_4
09681   *         @arg @ref LL_HRTIM_FAULT_5
09682   *         @arg @ref LL_HRTIM_FAULT_6
09683   * @retval Source This parameter can be one of the following values:
09684   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
09685   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
09686   *         @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
09687   */
09688 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09689 {
09690   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09691   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09692   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09693
09694   uint64_t Src0;
09695   uint32_t Src1;
09696   uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
09697
09698   /* this for SouRCe bit 1 */
09699   Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
09700   temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
09701   temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
09702
09703   /* this for SouRCe bit 0 */
09704   Src0 = (uint64_t)temp1 << 32U;
09705   Src0 |= (uint64_t)temp2;
09706   Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
09707
09708   return ((uint32_t)(Src0 | Src1));
09709 }
09710
09711 /**
09712   * @brief  Set the polarity of a fault signal.
09713   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_SetPolarity\n
09714   *         FLTINR1     FLT2P        LL_HRTIM_FLT_SetPolarity\n
09715   *         FLTINR1     FLT3P        LL_HRTIM_FLT_SetPolarity\n
09716   *         FLTINR1     FLT4P        LL_HRTIM_FLT_SetPolarity\n
09717   *         FLTINR2     FLT5P        LL_HRTIM_FLT_SetPolarity\n
09718   *         FLTINR2     FLT6P        LL_HRTIM_FLT_SetPolarity
09719   * @note This function must not be called when the fault channel is enabled.
09720   * @param  HRTIMx High Resolution Timer instance
09721   * @param  Fault This parameter can be one of the following values:
09722   *         @arg @ref LL_HRTIM_FAULT_1
09723   *         @arg @ref LL_HRTIM_FAULT_2
09724   *         @arg @ref LL_HRTIM_FAULT_3
09725   *         @arg @ref LL_HRTIM_FAULT_4
09726   *         @arg @ref LL_HRTIM_FAULT_5
09727   *         @arg @ref LL_HRTIM_FAULT_6
09728   * @param  Polarity This parameter can be one of the following values:
09729   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
09730   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
09731   * @retval None
09732   */
09733 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
09734 {
09735   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09736   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09737   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09738
09739   uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
09740   uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
09741
09742   /* for Polarity bit */
09743   MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
09744   MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
09745 }
09746
09747 /**
09748   * @brief  Get actual polarity of a fault signal.
09749   * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_GetPolarity\n
09750   *         FLTINR1     FLT2P        LL_HRTIM_FLT_GetPolarity\n
09751   *         FLTINR1     FLT3P        LL_HRTIM_FLT_GetPolarity\n
09752   *         FLTINR1     FLT4P        LL_HRTIM_FLT_GetPolarity\n
09753   *         FLTINR2     FLT5P        LL_HRTIM_FLT_GetPolarity\n
09754   *         FLTINR2     FLT6P        LL_HRTIM_FLT_GetPolarity
09755   * @param  HRTIMx High Resolution Timer instance
09756   * @param  Fault This parameter can be one of the following values:
09757   *         @arg @ref LL_HRTIM_FAULT_1
09758   *         @arg @ref LL_HRTIM_FAULT_2
09759   *         @arg @ref LL_HRTIM_FAULT_3
09760   *         @arg @ref LL_HRTIM_FAULT_4
09761   *         @arg @ref LL_HRTIM_FAULT_5
09762   *         @arg @ref LL_HRTIM_FAULT_6
09763   * @retval Polarity This parameter can be one of the following values:
09764   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
09765   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
09766   */
09767 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09768 {
09769   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09770   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09771   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09772   uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
09773   uint64_t cfg;
09774
09775   temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
09776   temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
09777
09778   cfg = (uint64_t)temp1 << 32 ;
09779   cfg |= (uint64_t)temp2;
09780   cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
09781
09782   return (uint32_t)(cfg);
09783
09784 }
09785
09786 /**
09787   * @brief  Set the digital noise filter of a fault signal.
09788   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_SetFilter\n
09789   *         FLTINR1     FLT2F      LL_HRTIM_FLT_SetFilter\n
09790   *         FLTINR1     FLT3F      LL_HRTIM_FLT_SetFilter\n
09791   *         FLTINR1     FLT4F      LL_HRTIM_FLT_SetFilter\n
09792   *         FLTINR2     FLT5F      LL_HRTIM_FLT_SetFilter\n
09793   *         FLTINR2     FLT6F      LL_HRTIM_FLT_SetFilter
09794   * @note This function must not be called when the fault channel is enabled.
09795   * @param  HRTIMx High Resolution Timer instance
09796   * @param  Fault This parameter can be one of the following values:
09797   *         @arg @ref LL_HRTIM_FAULT_1
09798   *         @arg @ref LL_HRTIM_FAULT_2
09799   *         @arg @ref LL_HRTIM_FAULT_3
09800   *         @arg @ref LL_HRTIM_FAULT_4
09801   *         @arg @ref LL_HRTIM_FAULT_5
09802   *         @arg @ref LL_HRTIM_FAULT_6
09803   * @param  Filter This parameter can be one of the following values:
09804   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
09805   *         @arg @ref LL_HRTIM_FLT_FILTER_1
09806   *         @arg @ref LL_HRTIM_FLT_FILTER_2
09807   *         @arg @ref LL_HRTIM_FLT_FILTER_3
09808   *         @arg @ref LL_HRTIM_FLT_FILTER_4
09809   *         @arg @ref LL_HRTIM_FLT_FILTER_5
09810   *         @arg @ref LL_HRTIM_FLT_FILTER_6
09811   *         @arg @ref LL_HRTIM_FLT_FILTER_7
09812   *         @arg @ref LL_HRTIM_FLT_FILTER_8
09813   *         @arg @ref LL_HRTIM_FLT_FILTER_9
09814   *         @arg @ref LL_HRTIM_FLT_FILTER_10
09815   *         @arg @ref LL_HRTIM_FLT_FILTER_11
09816   *         @arg @ref LL_HRTIM_FLT_FILTER_12
09817   *         @arg @ref LL_HRTIM_FLT_FILTER_13
09818   *         @arg @ref LL_HRTIM_FLT_FILTER_14
09819   *         @arg @ref LL_HRTIM_FLT_FILTER_15
09820   * @retval None
09821   */
09822 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
09823 {
09824   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09825   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09826   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09827
09828   uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for filter bits */
09829   uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
09830
09831   MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
09832   MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt  >> 32U));
09833 }
09834
09835 /**
09836   * @brief  Get actual digital noise filter setting of a fault signal.
09837   * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_GetFilter\n
09838   *         FLTINR1     FLT2F      LL_HRTIM_FLT_GetFilter\n
09839   *         FLTINR1     FLT3F      LL_HRTIM_FLT_GetFilter\n
09840   *         FLTINR1     FLT4F      LL_HRTIM_FLT_GetFilter\n
09841   *         FLTINR2     FLT5F      LL_HRTIM_FLT_GetFilter\n
09842   *         FLTINR2     FLT6F      LL_HRTIM_FLT_GetFilter
09843   * @param  HRTIMx High Resolution Timer instance
09844   * @param  Fault This parameter can be one of the following values:
09845   *         @arg @ref LL_HRTIM_FAULT_1
09846   *         @arg @ref LL_HRTIM_FAULT_2
09847   *         @arg @ref LL_HRTIM_FAULT_3
09848   *         @arg @ref LL_HRTIM_FAULT_4
09849   *         @arg @ref LL_HRTIM_FAULT_5
09850   *         @arg @ref LL_HRTIM_FAULT_6
09851   * @retval Filter This parameter can be one of the following values:
09852   *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
09853   *         @arg @ref LL_HRTIM_FLT_FILTER_1
09854   *         @arg @ref LL_HRTIM_FLT_FILTER_2
09855   *         @arg @ref LL_HRTIM_FLT_FILTER_3
09856   *         @arg @ref LL_HRTIM_FLT_FILTER_4
09857   *         @arg @ref LL_HRTIM_FLT_FILTER_5
09858   *         @arg @ref LL_HRTIM_FLT_FILTER_6
09859   *         @arg @ref LL_HRTIM_FLT_FILTER_7
09860   *         @arg @ref LL_HRTIM_FLT_FILTER_8
09861   *         @arg @ref LL_HRTIM_FLT_FILTER_9
09862   *         @arg @ref LL_HRTIM_FLT_FILTER_10
09863   *         @arg @ref LL_HRTIM_FLT_FILTER_11
09864   *         @arg @ref LL_HRTIM_FLT_FILTER_12
09865   *         @arg @ref LL_HRTIM_FLT_FILTER_13
09866   *         @arg @ref LL_HRTIM_FLT_FILTER_14
09867   *         @arg @ref LL_HRTIM_FLT_FILTER_15
09868   */
09869 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09870 {
09871   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09872   __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
09873   __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
09874   uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
09875   uint64_t flt;
09876   temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
09877   temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
09878
09879   flt = (uint64_t)temp1 << 32U;
09880   flt |= (uint64_t)temp2;
09881   flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
09882
09883   return (uint32_t)(flt);
09884
09885 }
09886
09887 /**
09888   * @brief  Set the fault circuitry prescaler.
09889   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_SetPrescaler
09890   * @param  HRTIMx High Resolution Timer instance
09891   * @param  Prescaler This parameter can be one of the following values:
09892   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
09893   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
09894   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
09895   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
09896   * @retval None
09897   */
09898 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
09899 {
09900   MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
09901 }
09902
09903 /**
09904   * @brief  Get actual fault circuitry prescaler setting.
09905   * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_GetPrescaler
09906   * @param  HRTIMx High Resolution Timer instance
09907   * @retval Prescaler This parameter can be one of the following values:
09908   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
09909   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
09910   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
09911   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
09912   */
09913 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
09914 {
09915   return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
09916 }
09917
09918 /**
09919   * @brief  Lock the fault signal conditioning settings.
09920   * @rmtoll FLTINR1     FLT1LCK      LL_HRTIM_FLT_Lock\n
09921   *         FLTINR1     FLT2LCK      LL_HRTIM_FLT_Lock\n
09922   *         FLTINR1     FLT3LCK      LL_HRTIM_FLT_Lock\n
09923   *         FLTINR1     FLT4LCK      LL_HRTIM_FLT_Lock\n
09924   *         FLTINR2     FLT5LCK      LL_HRTIM_FLT_Lock\n
09925   *         FLTINR2     FLT6LCK      LL_HRTIM_FLT_Lock
09926   * @param  HRTIMx High Resolution Timer instance
09927   * @param  Fault This parameter can be one of the following values:
09928   *         @arg @ref LL_HRTIM_FAULT_1
09929   *         @arg @ref LL_HRTIM_FAULT_2
09930   *         @arg @ref LL_HRTIM_FAULT_3
09931   *         @arg @ref LL_HRTIM_FAULT_4
09932   *         @arg @ref LL_HRTIM_FAULT_5
09933   *         @arg @ref LL_HRTIM_FAULT_6
09934   * @retval None
09935   */
09936 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09937 {
09938   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09939   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
09940                                                               REG_OFFSET_TAB_FLTINR[iFault]));
09941   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
09942 }
09943
09944 /**
09945   * @brief  Enable the fault circuitry for the designated fault input.
09946   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Enable\n
09947   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Enable\n
09948   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Enable\n
09949   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Enable\n
09950   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Enable\n
09951   *         FLTINR2     FLT6E      LL_HRTIM_FLT_Enable
09952   * @param  HRTIMx High Resolution Timer instance
09953   * @param  Fault This parameter can be one of the following values:
09954   *         @arg @ref LL_HRTIM_FAULT_1
09955   *         @arg @ref LL_HRTIM_FAULT_2
09956   *         @arg @ref LL_HRTIM_FAULT_3
09957   *         @arg @ref LL_HRTIM_FAULT_4
09958   *         @arg @ref LL_HRTIM_FAULT_5
09959   *         @arg @ref LL_HRTIM_FAULT_6
09960   * @retval None
09961   */
09962 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09963 {
09964   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09965   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
09966                                                               REG_OFFSET_TAB_FLTINR[iFault]));
09967   SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
09968 }
09969
09970 /**
09971   * @brief  Disable the fault circuitry for for the designated fault input.
09972   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Disable\n
09973   *         FLTINR1     FLT2E      LL_HRTIM_FLT_Disable\n
09974   *         FLTINR1     FLT3E      LL_HRTIM_FLT_Disable\n
09975   *         FLTINR1     FLT4E      LL_HRTIM_FLT_Disable\n
09976   *         FLTINR2     FLT5E      LL_HRTIM_FLT_Disable\n
09977   *         FLTINR2     FLT6E      LL_HRTIM_FLT_Disable
09978   * @param  HRTIMx High Resolution Timer instance
09979   * @param  Fault This parameter can be one of the following values:
09980   *         @arg @ref LL_HRTIM_FAULT_1
09981   *         @arg @ref LL_HRTIM_FAULT_2
09982   *         @arg @ref LL_HRTIM_FAULT_3
09983   *         @arg @ref LL_HRTIM_FAULT_4
09984   *         @arg @ref LL_HRTIM_FAULT_5
09985   *         @arg @ref LL_HRTIM_FAULT_6
09986   * @retval None
09987   */
09988 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
09989 {
09990   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
09991   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
09992                                                               REG_OFFSET_TAB_FLTINR[iFault]));
09993   CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
09994
09995 }
09996
09997 /**
09998   * @brief  Indicate whether the fault circuitry is enabled for a given fault input.
09999   * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_IsEnabled\n
10000   *         FLTINR1     FLT2E      LL_HRTIM_FLT_IsEnabled\n
10001   *         FLTINR1     FLT3E      LL_HRTIM_FLT_IsEnabled\n
10002   *         FLTINR1     FLT4E      LL_HRTIM_FLT_IsEnabled\n
10003   *         FLTINR2     FLT5E      LL_HRTIM_FLT_IsEnabled\n
10004   *         FLTINR2     FLT6E      LL_HRTIM_FLT_IsEnabled
10005   * @param  HRTIMx High Resolution Timer instance
10006   * @param  Fault This parameter can be one of the following values:
10007   *         @arg @ref LL_HRTIM_FAULT_1
10008   *         @arg @ref LL_HRTIM_FAULT_2
10009   *         @arg @ref LL_HRTIM_FAULT_3
10010   *         @arg @ref LL_HRTIM_FAULT_4
10011   *         @arg @ref LL_HRTIM_FAULT_5
10012   *         @arg @ref LL_HRTIM_FAULT_6
10013   * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
10014   */
10015 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10016 {
10017   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10018   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10019                                                                     REG_OFFSET_TAB_FLTINR[iFault]));
10020   return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
10021            (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
10022 }
10023
10024 /**
10025   * @brief  Enable the Blanking of the fault circuitry for the designated fault input.
10026   * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_EnableBlanking\n
10027   *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_EnableBlanking\n
10028   *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_EnableBlanking\n
10029   *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_EnableBlanking\n
10030   *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_EnableBlanking\n
10031   *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_EnableBlanking
10032   * @param  HRTIMx High Resolution Timer instance
10033   * @param  Fault This parameter can be one of the following values:
10034   *         @arg @ref LL_HRTIM_FAULT_1
10035   *         @arg @ref LL_HRTIM_FAULT_2
10036   *         @arg @ref LL_HRTIM_FAULT_3
10037   *         @arg @ref LL_HRTIM_FAULT_4
10038   *         @arg @ref LL_HRTIM_FAULT_5
10039   *         @arg @ref LL_HRTIM_FAULT_6
10040   * @retval None
10041   */
10042 __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10043 {
10044   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10045   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10046                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10047   SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
10048 }
10049
10050 /**
10051   * @brief  Disable the Blanking of the fault circuitry for the designated fault input.
10052   * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_DisableBlanking\n
10053   *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_DisableBlanking\n
10054   *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_DisableBlanking\n
10055   *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_DisableBlanking\n
10056   *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_DisableBlanking\n
10057   *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_DisableBlanking
10058   * @param  HRTIMx High Resolution Timer instance
10059   * @param  Fault This parameter can be one of the following values:
10060   *         @arg @ref LL_HRTIM_FAULT_1
10061   *         @arg @ref LL_HRTIM_FAULT_2
10062   *         @arg @ref LL_HRTIM_FAULT_3
10063   *         @arg @ref LL_HRTIM_FAULT_4
10064   *         @arg @ref LL_HRTIM_FAULT_5
10065   *         @arg @ref LL_HRTIM_FAULT_6
10066   * @retval None
10067   */
10068 __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10069 {
10070   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10071   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10072                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10073   CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
10074 }
10075
10076 /**
10077   * @brief  Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
10078   * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
10079   *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
10080   *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
10081   *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
10082   *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
10083   *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_IsEnabledBlanking
10084   * @param  HRTIMx High Resolution Timer instance
10085   * @param  Fault This parameter can be one of the following values:
10086   *         @arg @ref LL_HRTIM_FAULT_1
10087   *         @arg @ref LL_HRTIM_FAULT_2
10088   *         @arg @ref LL_HRTIM_FAULT_3
10089   *         @arg @ref LL_HRTIM_FAULT_4
10090   *         @arg @ref LL_HRTIM_FAULT_5
10091   *         @arg @ref LL_HRTIM_FAULT_6
10092   * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
10093   */
10094 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10095 {
10096   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10097   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10098                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10099   uint32_t temp; /* MISRAC-2012 compliance */
10100   temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
10101
10102   return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
10103 }
10104
10105 /**
10106   * @brief  Set the Blanking Source of the fault circuitry  for a given fault input.
10107   * @note Fault inputs can be temporary disabled to blank spurious fault events.
10108   * @note This function allows for selection amongst 2 possible blanking sources.
10109   * @note Events triggering blanking window start and blanking window end depend
10110   *       on both the selected blanking source and the fault input.
10111   * @rmtoll FLTINR3     FLT1BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
10112   *         FLTINR3     FLT2BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
10113   *         FLTINR3     FLT3BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
10114   *         FLTINR3     FLT4BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
10115   *         FLTINR4     FLT5BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
10116   *         FLTINR4     FLT6BLKS      LL_HRTIM_FLT_SetBlankingSrc
10117   * @param  HRTIMx High Resolution Timer instance
10118   * @param  Fault This parameter can be one of the following values:
10119   *         @arg @ref LL_HRTIM_FAULT_1
10120   *         @arg @ref LL_HRTIM_FAULT_2
10121   *         @arg @ref LL_HRTIM_FAULT_3
10122   *         @arg @ref LL_HRTIM_FAULT_4
10123   *         @arg @ref LL_HRTIM_FAULT_5
10124   *         @arg @ref LL_HRTIM_FAULT_6
10125   * @param  Source parameter can be one of the following values:
10126   *         @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
10127   *         @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
10128   * @retval None
10129   */
10130 __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
10131 {
10132   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10133   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10134                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10135   MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
10136
10137 }
10138
10139 /**
10140   * @brief  Get the Blanking Source of the fault circuitry is enabled for a given fault input.
10141   * @rmtoll FLTINR3     FLT1BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
10142   *         FLTINR3     FLT2BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
10143   *         FLTINR3     FLT3BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
10144   *         FLTINR3     FLT4BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
10145   *         FLTINR4     FLT5BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
10146   *         FLTINR4     FLT6BLKS      LL_HRTIM_FLT_GetBlankingSrc
10147   * @param  HRTIMx High Resolution Timer instance
10148   * @param  Fault This parameter can be one of the following values:
10149   *         @arg @ref LL_HRTIM_FAULT_1
10150   *         @arg @ref LL_HRTIM_FAULT_2
10151   *         @arg @ref LL_HRTIM_FAULT_3
10152   *         @arg @ref LL_HRTIM_FAULT_4
10153   *         @arg @ref LL_HRTIM_FAULT_5
10154   *         @arg @ref LL_HRTIM_FAULT_6
10155   */
10156 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10157 {
10158   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10159   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10160                                                                     REG_OFFSET_TAB_FLTINR[iFault]));
10161   return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
10162 }
10163
10164 /**
10165   * @brief  Set the Counter threshold value of a fault counter.
10166   * @rmtoll FLTINR3     FLT1CNT      LL_HRTIM_FLT_SetCounterThreshold\n
10167   *         FLTINR3     FLT2CNT      LL_HRTIM_FLT_SetCounterThreshold\n
10168   *         FLTINR3     FLT3CNT      LL_HRTIM_FLT_SetCounterThreshold\n
10169   *         FLTINR3     FLT4CNT      LL_HRTIM_FLT_SetCounterThreshold\n
10170   *         FLTINR4     FLT5CNT      LL_HRTIM_FLT_SetCounterThreshold\n
10171   *         FLTINR4     FLT6CNT      LL_HRTIM_FLT_SetCounterThreshold
10172   * @note This function must not be called when the fault channel is enabled.
10173   * @param  HRTIMx High Resolution Timer instance
10174   * @param  Fault This parameter can be one of the following values:
10175   *         @arg @ref LL_HRTIM_FAULT_1
10176   *         @arg @ref LL_HRTIM_FAULT_2
10177   *         @arg @ref LL_HRTIM_FAULT_3
10178   *         @arg @ref LL_HRTIM_FAULT_4
10179   *         @arg @ref LL_HRTIM_FAULT_5
10180   *         @arg @ref LL_HRTIM_FAULT_6
10181   * @param  Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10182   * @retval None
10183   */
10184 __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
10185 {
10186   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10187   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10188                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10189   MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxCNT[iFault]));
10190 }
10191
10192 /**
10193   * @brief  Get actual the Counter threshold value of a fault counter.
10194   * @rmtoll FLTINR3     FLT1CNT      LL_HRTIM_FLT_GetCounterThreshold\n
10195   *         FLTINR3     FLT2CNT      LL_HRTIM_FLT_GetCounterThreshold\n
10196   *         FLTINR3     FLT3CNT      LL_HRTIM_FLT_GetCounterThreshold\n
10197   *         FLTINR3     FLT4CNT      LL_HRTIM_FLT_GetCounterThreshold\n
10198   *         FLTINR4     FLT5CNT      LL_HRTIM_FLT_GetCounterThreshold\n
10199   *         FLTINR4     FLT6CNT      LL_HRTIM_FLT_GetCounterThreshold
10200   * @param  HRTIMx High Resolution Timer instance
10201   * @param  Fault This parameter can be one of the following values:
10202   *         @arg @ref LL_HRTIM_FAULT_1
10203   *         @arg @ref LL_HRTIM_FAULT_2
10204   *         @arg @ref LL_HRTIM_FAULT_3
10205   *         @arg @ref LL_HRTIM_FAULT_4
10206   *         @arg @ref LL_HRTIM_FAULT_5
10207   *         @arg @ref LL_HRTIM_FAULT_6
10208   * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10209   */
10210 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10211 {
10212   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10213   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10214                                                                     REG_OFFSET_TAB_FLTINR[iFault]));
10215   return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxCNT[iFault]);
10216 }
10217
10218 /**
10219   * @brief  Set the mode of reset of a fault counter to 'always reset'.
10220   * @rmtoll FLTINR3     FLT1RSTM      LL_HRTIM_FLT_SetResetMode\n
10221   *         FLTINR3     FLT2RSTM      LL_HRTIM_FLT_SetResetMode\n
10222   *         FLTINR3     FLT3RSTM      LL_HRTIM_FLT_SetResetMode\n
10223   *         FLTINR3     FLT4RSTM      LL_HRTIM_FLT_SetResetMode\n
10224   *         FLTINR4     FLT5RSTM      LL_HRTIM_FLT_SetResetMode\n
10225   *         FLTINR4     FLT6RSTM      LL_HRTIM_FLT_SetResetMode
10226   * @param  HRTIMx High Resolution Timer instance
10227   * @param  Fault This parameter can be one of the following values:
10228   *         @arg @ref LL_HRTIM_FAULT_1
10229   *         @arg @ref LL_HRTIM_FAULT_2
10230   *         @arg @ref LL_HRTIM_FAULT_3
10231   *         @arg @ref LL_HRTIM_FAULT_4
10232   *         @arg @ref LL_HRTIM_FAULT_5
10233   *         @arg @ref LL_HRTIM_FAULT_6
10234   * @param  Mode This parameter can be one of the following values:
10235   *         @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10236   *         @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10237   * @retval None
10238   */
10239 __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
10240 {
10241   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10242   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10243                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10244   MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
10245
10246 }
10247
10248 /**
10249   * @brief  Get the mode of reset of a fault counter to 'reset on event'.
10250   * @rmtoll FLTINR3     FLT1RSTM      LL_HRTIM_FLT_GetResetMode\n
10251   *         FLTINR3     FLT2RSTM      LL_HRTIM_FLT_GetResetMode\n
10252   *         FLTINR3     FLT3RSTM      LL_HRTIM_FLT_GetResetMode\n
10253   *         FLTINR3     FLT4RSTM      LL_HRTIM_FLT_GetResetMode\n
10254   *         FLTINR4     FLT5RSTM      LL_HRTIM_FLT_GetResetMode\n
10255   *         FLTINR4     FLT6RSTM      LL_HRTIM_FLT_GetResetMode
10256   * @param  HRTIMx High Resolution Timer instance
10257   * @param  Fault This parameter can be one of the following values:
10258   *         @arg @ref LL_HRTIM_FAULT_1
10259   *         @arg @ref LL_HRTIM_FAULT_2
10260   *         @arg @ref LL_HRTIM_FAULT_3
10261   *         @arg @ref LL_HRTIM_FAULT_4
10262   *         @arg @ref LL_HRTIM_FAULT_5
10263   *         @arg @ref LL_HRTIM_FAULT_6
10264   * @retval  Mode This parameter can be one of the following values:
10265   *         @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10266   *         @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10267   */
10268 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10269 {
10270   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10271   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10272                                                                     REG_OFFSET_TAB_FLTINR[iFault]));
10273   return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
10274 }
10275
10276 /**
10277   * @brief  Reset the fault counter for a fault circuitry
10278   * @rmtoll FLTINR3     FLT1CRES      LL_HRTIM_FLT_ResetCounter\n
10279   *         FLTINR3     FLT2CRES      LL_HRTIM_FLT_ResetCounter\n
10280   *         FLTINR3     FLT3CRES      LL_HRTIM_FLT_ResetCounter\n
10281   *         FLTINR3     FLT4CRES      LL_HRTIM_FLT_ResetCounter\n
10282   *         FLTINR4     FLT5CRES      LL_HRTIM_FLT_ResetCounter\n
10283   *         FLTINR4     FLT6CRES      LL_HRTIM_FLT_ResetCounter
10284   * @param  HRTIMx High Resolution Timer instance
10285   * @param  Fault This parameter can be one of the following values:
10286   *         @arg @ref LL_HRTIM_FAULT_1
10287   *         @arg @ref LL_HRTIM_FAULT_2
10288   *         @arg @ref LL_HRTIM_FAULT_3
10289   *         @arg @ref LL_HRTIM_FAULT_4
10290   *         @arg @ref LL_HRTIM_FAULT_5
10291   *         @arg @ref LL_HRTIM_FAULT_6
10292   * @retval None
10293   */
10294 __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10295 {
10296   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10297   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10298                                                               REG_OFFSET_TAB_FLTINR[iFault]));
10299   SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
10300
10301 }
10302
10303 /**
10304   * @}
10305   */
10306
10307 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
10308   * @{
10309   */
10310
10311 /**
10312   * @brief  Configure the burst mode controller.
10313   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_Config\n
10314   *         BMCR     BMCLK       LL_HRTIM_BM_Config\n
10315   *         BMCR     BMPRSC      LL_HRTIM_BM_Config
10316   * @param  HRTIMx High Resolution Timer instance
10317   * @param  Configuration This parameter must be a combination of all the following values:
10318   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
10319   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10320   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
10321   * @retval None
10322   */
10323 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
10324 {
10325   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
10326 }
10327
10328 /**
10329   * @brief  Set the burst mode controller operating mode.
10330   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_SetMode
10331   * @param  HRTIMx High Resolution Timer instance
10332   * @param  Mode This parameter can be one of the following values:
10333   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10334   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10335   * @retval None
10336   */
10337 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
10338 {
10339   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
10340 }
10341
10342 /**
10343   * @brief  Get actual burst mode controller operating mode.
10344   * @rmtoll BMCR     BMOM        LL_HRTIM_BM_GetMode
10345   * @param  HRTIMx High Resolution Timer instance
10346   * @retval Mode This parameter can be one of the following values:
10347   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10348   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10349   */
10350 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
10351 {
10352   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
10353 }
10354
10355 /**
10356   * @brief  Set the burst mode controller clock source.
10357   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_SetClockSrc
10358   * @param  HRTIMx High Resolution Timer instance
10359   * @param  ClockSrc This parameter can be one of the following values:
10360   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10361   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10362   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10363   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10364   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10365   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10366   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10367   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10368   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10369   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10370   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10371   * @retval None
10372   */
10373 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
10374 {
10375   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
10376 }
10377
10378 /**
10379   * @brief  Get actual burst mode controller clock source.
10380   * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_GetClockSrc
10381   * @param  HRTIMx High Resolution Timer instance
10382   * @retval ClockSrc This parameter can be one of the following values:
10383   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10384   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10385   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10386   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10387   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10388   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10389   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10390   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10391   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10392   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10393   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10394   * @retval ClockSrc This parameter can be one of the following values:
10395   *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10396   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10397   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10398   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10399   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10400   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10401   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10402   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10403   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10404   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10405   */
10406 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
10407 {
10408   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
10409 }
10410
10411 /**
10412   * @brief  Set the burst mode controller prescaler.
10413   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_SetPrescaler
10414   * @param  HRTIMx High Resolution Timer instance
10415   * @param  Prescaler This parameter can be one of the following values:
10416   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10417   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10418   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10419   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10420   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10421   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10422   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10423   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10424   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10425   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10426   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10427   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10428   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10429   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10430   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10431   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10432   * @retval None
10433   */
10434 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
10435 {
10436   MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
10437 }
10438
10439 /**
10440   * @brief  Get actual burst mode controller prescaler setting.
10441   * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_GetPrescaler
10442   * @param  HRTIMx High Resolution Timer instance
10443   * @retval Prescaler This parameter can be one of the following values:
10444   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10445   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10446   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10447   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10448   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10449   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10450   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10451   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10452   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10453   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10454   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10455   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10456   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10457   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10458   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10459   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10460   */
10461 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
10462 {
10463   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
10464 }
10465
10466 /**
10467   * @brief  Enable burst mode compare and period registers preload.
10468   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_EnablePreload
10469   * @param  HRTIMx High Resolution Timer instance
10470   * @retval None
10471   */
10472 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
10473 {
10474   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10475 }
10476
10477 /**
10478   * @brief  Disable burst mode compare and period registers preload.
10479   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_DisablePreload
10480   * @param  HRTIMx High Resolution Timer instance
10481   * @retval None
10482   */
10483 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
10484 {
10485   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10486 }
10487
10488 /**
10489   * @brief  Indicate whether burst mode compare and period registers are preloaded.
10490   * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_IsEnabledPreload
10491   * @param  HRTIMx High Resolution Timer instance
10492   * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
10493   */
10494 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
10495 {
10496   uint32_t temp; /* MISRAC-2012 compliance */
10497   temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10498
10499   return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
10500 }
10501
10502 /**
10503   * @brief  Set the burst mode controller trigger
10504   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_SetTrig\n
10505   *         BMTRGR     MSTRST       LL_HRTIM_BM_SetTrig\n
10506   *         BMTRGR     MSTREP       LL_HRTIM_BM_SetTrig\n
10507   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_SetTrig\n
10508   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_SetTrig\n
10509   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_SetTrig\n
10510   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_SetTrig\n
10511   *         BMTRGR     TARST        LL_HRTIM_BM_SetTrig\n
10512   *         BMTRGR     TAREP        LL_HRTIM_BM_SetTrig\n
10513   *         BMTRGR     TACMP1       LL_HRTIM_BM_SetTrig\n
10514   *         BMTRGR     TACMP2       LL_HRTIM_BM_SetTrig\n
10515   *         BMTRGR     TBRST        LL_HRTIM_BM_SetTrig\n
10516   *         BMTRGR     TBREP        LL_HRTIM_BM_SetTrig\n
10517   *         BMTRGR     TBCMP1       LL_HRTIM_BM_SetTrig\n
10518   *         BMTRGR     TBCMP2       LL_HRTIM_BM_SetTrig\n
10519   *         BMTRGR     TCRST        LL_HRTIM_BM_SetTrig\n
10520   *         BMTRGR     TCREP        LL_HRTIM_BM_SetTrig\n
10521   *         BMTRGR     TCCMP1       LL_HRTIM_BM_SetTrig\n
10522   *         BMTRGR     TDRST        LL_HRTIM_BM_SetTrig\n
10523   *         BMTRGR     TDREP        LL_HRTIM_BM_SetTrig\n
10524   *         BMTRGR     TDCMP2       LL_HRTIM_BM_SetTrig\n
10525   *         BMTRGR     TEREP        LL_HRTIM_BM_SetTrig\n
10526   *         BMTRGR     TECMP1       LL_HRTIM_BM_SetTrig\n
10527   *         BMTRGR     TECMP2       LL_HRTIM_BM_SetTrig\n
10528   *         BMTRGR     TFREP        LL_HRTIM_BM_SetTrig\n
10529   *         BMTRGR     TFRST        LL_HRTIM_BM_SetTrig\n
10530   *         BMTRGR     TFCMP1       LL_HRTIM_BM_SetTrig\n
10531   *         BMTRGR     TAEEV7       LL_HRTIM_BM_SetTrig\n
10532   *         BMTRGR     TAEEV8       LL_HRTIM_BM_SetTrig\n
10533   *         BMTRGR     EEV7         LL_HRTIM_BM_SetTrig\n
10534   *         BMTRGR     EEV8         LL_HRTIM_BM_SetTrig\n
10535   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_SetTrig
10536   * @param  HRTIMx High Resolution Timer instance
10537   * @param  Trig This parameter can be a combination of the following values:
10538   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
10539   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10540   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10541   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10542   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10543   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10544   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10545   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10546   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10547   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10548   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10549   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10550   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10551   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10552   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10553   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10554   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10555   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10556   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10557   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10558   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10559   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10560   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10561   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10562   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10563   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10564   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10565   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10566   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10567   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10568   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10569   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10570     * @retval None
10571   */
10572 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
10573 {
10574   WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
10575 }
10576
10577 /**
10578   * @brief  Get actual burst mode controller trigger.
10579   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_GetTrig\n
10580   *         BMTRGR     MSTRST       LL_HRTIM_BM_GetTrig\n
10581   *         BMTRGR     MSTREP       LL_HRTIM_BM_GetTrig\n
10582   *         BMTRGR     MSTCMP1      LL_HRTIM_BM_GetTrig\n
10583   *         BMTRGR     MSTCMP2      LL_HRTIM_BM_GetTrig\n
10584   *         BMTRGR     MSTCMP3      LL_HRTIM_BM_GetTrig\n
10585   *         BMTRGR     MSTCMP4      LL_HRTIM_BM_GetTrig\n
10586   *         BMTRGR     TARST        LL_HRTIM_BM_GetTrig\n
10587   *         BMTRGR     TAREP        LL_HRTIM_BM_GetTrig\n
10588   *         BMTRGR     TACMP1       LL_HRTIM_BM_GetTrig\n
10589   *         BMTRGR     TACMP2       LL_HRTIM_BM_GetTrig\n
10590   *         BMTRGR     TBRST        LL_HRTIM_BM_GetTrig\n
10591   *         BMTRGR     TBREP        LL_HRTIM_BM_GetTrig\n
10592   *         BMTRGR     TBCMP1       LL_HRTIM_BM_GetTrig\n
10593   *         BMTRGR     TBCMP2       LL_HRTIM_BM_GetTrig\n
10594   *         BMTRGR     TCRST        LL_HRTIM_BM_GetTrig\n
10595   *         BMTRGR     TCREP        LL_HRTIM_BM_GetTrig\n
10596   *         BMTRGR     TCCMP1       LL_HRTIM_BM_GetTrig\n
10597   *         BMTRGR     TDRST        LL_HRTIM_BM_GetTrig\n
10598   *         BMTRGR     TDREP        LL_HRTIM_BM_GetTrig\n
10599   *         BMTRGR     TDCMP2       LL_HRTIM_BM_GetTrig\n
10600   *         BMTRGR     TEREP        LL_HRTIM_BM_GetTrig\n
10601   *         BMTRGR     TECMP1       LL_HRTIM_BM_GetTrig\n
10602   *         BMTRGR     TECMP2       LL_HRTIM_BM_GetTrig\n
10603   *         BMTRGR     TFREP        LL_HRTIM_BM_GetTrig\n
10604   *         BMTRGR     TFRST        LL_HRTIM_BM_GetTrig\n
10605   *         BMTRGR     TFCMP1       LL_HRTIM_BM_GetTrig\n
10606   *         BMTRGR     TAEEV7       LL_HRTIM_BM_GetTrig\n
10607   *         BMTRGR     TAEEV8       LL_HRTIM_BM_GetTrig\n
10608   *         BMTRGR     EEV7         LL_HRTIM_BM_GetTrig\n
10609   *         BMTRGR     EEV8         LL_HRTIM_BM_GetTrig\n
10610   *         BMTRGR     OCHIPEV      LL_HRTIM_BM_GetTrig
10611   * @param  HRTIMx High Resolution Timer instance
10612   * @retval Trig This parameter can be a combination of the following values:
10613   *         @arg @ref LL_HRTIM_BM_TRIG_NONE
10614   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10615   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10616   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10617   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10618   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10619   *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10620   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10621   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10622   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10623   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10624   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10625   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10626   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10627   *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10628   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10629   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10630   *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10631   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10632   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10633   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10634   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10635   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10636   *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10637   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10638   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10639   *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10640   *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10641   *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10642   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10643   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10644   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10645   */
10646 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
10647 {
10648   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
10649 }
10650
10651 /**
10652   * @brief  Set the burst mode controller compare value.
10653   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_SetCompare
10654   * @param  HRTIMx High Resolution Timer instance
10655   * @param  CompareValue Compare value must be above or equal to 3
10656   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10657   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10658   * @retval None
10659   */
10660 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
10661 {
10662   WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
10663 }
10664
10665 /**
10666   * @brief  Get actual burst mode controller compare value.
10667   * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_GetCompare
10668   * @param  HRTIMx High Resolution Timer instance
10669   * @retval CompareValue Compare value must be above or equal to 3
10670   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10671   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10672   */
10673 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
10674 {
10675   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
10676 }
10677
10678 /**
10679   * @brief  Set the burst mode controller period.
10680   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_SetPeriod
10681   * @param  HRTIMx High Resolution Timer instance
10682   * @param  Period The period value must be above or equal to 3 periods of the fHRTIM clock,
10683   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10684   *         The maximum value is 0x0000 FFDF.
10685   * @retval None
10686   */
10687 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
10688 {
10689   WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
10690 }
10691
10692 /**
10693   * @brief  Get actual burst mode controller period.
10694   * @rmtoll BMPER     BMPER      LL_HRTIM_BM_GetPeriod
10695   * @param  HRTIMx High Resolution Timer instance
10696   * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
10697   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10698   *         The maximum value is 0x0000 FFDF.
10699   */
10700 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
10701 {
10702   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
10703 }
10704
10705 /**
10706   * @brief  Enable the burst mode controller
10707   * @rmtoll BMCR     BME      LL_HRTIM_BM_Enable
10708   * @param  HRTIMx High Resolution Timer instance
10709   * @retval None
10710   */
10711 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
10712 {
10713   SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10714 }
10715
10716 /**
10717   * @brief  Disable the burst mode controller
10718   * @rmtoll BMCR     BME      LL_HRTIM_BM_Disable
10719   * @param  HRTIMx High Resolution Timer instance
10720   * @retval None
10721   */
10722 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
10723 {
10724   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10725 }
10726
10727 /**
10728   * @brief  Indicate whether the burst mode controller is enabled.
10729   * @rmtoll BMCR     BME      LL_HRTIM_BM_IsEnabled
10730   * @param  HRTIMx High Resolution Timer instance
10731   * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
10732   */
10733 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
10734 {
10735   return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
10736 }
10737
10738 /**
10739   * @brief  Trigger the burst operation (software trigger)
10740   * @rmtoll BMTRGR     SW           LL_HRTIM_BM_Start
10741   * @param  HRTIMx High Resolution Timer instance
10742   * @retval None
10743   */
10744 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
10745 {
10746   SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
10747 }
10748
10749 /**
10750   * @brief  Stop the burst mode operation.
10751   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_Stop
10752   * @note Causes a burst mode early termination.
10753   * @param  HRTIMx High Resolution Timer instance
10754   * @retval None
10755   */
10756 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
10757 {
10758   CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
10759 }
10760
10761 /**
10762   * @brief  Get actual burst mode status
10763   * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_GetStatus
10764   * @param  HRTIMx High Resolution Timer instance
10765   * @retval Status This parameter can be one of the following values:
10766   *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL
10767   *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
10768   */
10769 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
10770 {
10771   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
10772 }
10773
10774 /**
10775   * @}
10776   */
10777
10778 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
10779   * @{
10780   */
10781
10782 /**
10783   * @brief  Clear the Fault 1 interrupt flag.
10784   * @rmtoll ICR     FLT1C           LL_HRTIM_ClearFlag_FLT1
10785   * @param  HRTIMx High Resolution Timer instance
10786   * @retval None
10787   */
10788 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10789 {
10790   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
10791 }
10792
10793 /**
10794   * @brief  Indicate whether Fault 1 interrupt occurred.
10795   * @rmtoll ICR     FLT1           LL_HRTIM_IsActiveFlag_FLT1
10796   * @param  HRTIMx High Resolution Timer instance
10797   * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
10798   */
10799 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
10800 {
10801   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
10802 }
10803
10804 /**
10805   * @brief  Clear the Fault 2 interrupt flag.
10806   * @rmtoll ICR     FLT2C           LL_HRTIM_ClearFlag_FLT2
10807   * @param  HRTIMx High Resolution Timer instance
10808   * @retval None
10809   */
10810 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10811 {
10812   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
10813 }
10814
10815 /**
10816   * @brief  Indicate whether Fault 2 interrupt occurred.
10817   * @rmtoll ICR     FLT2           LL_HRTIM_IsActiveFlag_FLT2
10818   * @param  HRTIMx High Resolution Timer instance
10819   * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
10820   */
10821 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
10822 {
10823   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
10824 }
10825
10826 /**
10827   * @brief  Clear the Fault 3 interrupt flag.
10828   * @rmtoll ICR     FLT3C           LL_HRTIM_ClearFlag_FLT3
10829   * @param  HRTIMx High Resolution Timer instance
10830   * @retval None
10831   */
10832 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10833 {
10834   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
10835 }
10836
10837 /**
10838   * @brief  Indicate whether Fault 3 interrupt occurred.
10839   * @rmtoll ICR     FLT3           LL_HRTIM_IsActiveFlag_FLT3
10840   * @param  HRTIMx High Resolution Timer instance
10841   * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
10842   */
10843 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
10844 {
10845   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
10846 }
10847
10848 /**
10849   * @brief  Clear the Fault 4 interrupt flag.
10850   * @rmtoll ICR     FLT4C           LL_HRTIM_ClearFlag_FLT4
10851   * @param  HRTIMx High Resolution Timer instance
10852   * @retval None
10853   */
10854 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10855 {
10856   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
10857 }
10858
10859 /**
10860   * @brief  Indicate whether Fault 4 interrupt occurred.
10861   * @rmtoll ICR     FLT4           LL_HRTIM_IsActiveFlag_FLT4
10862   * @param  HRTIMx High Resolution Timer instance
10863   * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
10864   */
10865 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
10866 {
10867   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
10868 }
10869
10870 /**
10871   * @brief  Clear the Fault 5 interrupt flag.
10872   * @rmtoll ICR     FLT5C           LL_HRTIM_ClearFlag_FLT5
10873   * @param  HRTIMx High Resolution Timer instance
10874   * @retval None
10875   */
10876 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10877 {
10878   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
10879 }
10880
10881 /**
10882   * @brief  Indicate whether Fault 5 interrupt occurred.
10883   * @rmtoll ICR     FLT5           LL_HRTIM_IsActiveFlag_FLT5
10884   * @param  HRTIMx High Resolution Timer instance
10885   * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
10886   */
10887 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
10888 {
10889   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
10890 }
10891
10892 /**
10893   * @brief  Clear the Fault 6 interrupt flag.
10894   * @rmtoll ICR     FLT6C           LL_HRTIM_ClearFlag_FLT6
10895   * @param  HRTIMx High Resolution Timer instance
10896   * @retval None
10897   */
10898 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10899 {
10900   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
10901 }
10902
10903 /**
10904   * @brief  Indicate whether Fault 6 interrupt occurred.
10905   * @rmtoll ICR     FLT6           LL_HRTIM_IsActiveFlag_FLT6
10906   * @param  HRTIMx High Resolution Timer instance
10907   * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
10908   */
10909 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(const HRTIM_TypeDef *HRTIMx)
10910 {
10911   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
10912 }
10913
10914 /**
10915   * @brief  Clear the System Fault interrupt flag.
10916   * @rmtoll ICR     SYSFLTC           LL_HRTIM_ClearFlag_SYSFLT
10917   * @param  HRTIMx High Resolution Timer instance
10918   * @retval None
10919   */
10920 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10921 {
10922   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
10923 }
10924
10925 /**
10926   * @brief  Indicate whether System Fault interrupt occurred.
10927   * @rmtoll ISR     SYSFLT           LL_HRTIM_IsActiveFlag_SYSFLT
10928   * @param  HRTIMx High Resolution Timer instance
10929   * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
10930   */
10931 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
10932 {
10933   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
10934 }
10935
10936 /**
10937   * @brief  Clear the DLL ready interrupt flag.
10938   * @rmtoll ICR     DLLRDYC           LL_HRTIM_ClearFlag_DLLRDY
10939   * @param  HRTIMx High Resolution Timer instance
10940   * @retval None
10941   */
10942 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10943 {
10944   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
10945 }
10946
10947 /**
10948   * @brief  Indicate whether DLL ready  interrupt occurred.
10949   * @rmtoll ISR     DLLRDY           LL_HRTIM_IsActiveFlag_DLLRDY
10950   * @param  HRTIMx High Resolution Timer instance
10951   * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
10952   */
10953 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef *HRTIMx)
10954 {
10955   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
10956 }
10957
10958 /**
10959   * @brief  Clear the Burst Mode period interrupt flag.
10960   * @rmtoll ICR     BMPERC           LL_HRTIM_ClearFlag_BMPER
10961   * @param  HRTIMx High Resolution Timer instance
10962   * @retval None
10963   */
10964 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10965 {
10966   SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
10967 }
10968
10969 /**
10970   * @brief  Indicate whether Burst Mode period interrupt occurred.
10971   * @rmtoll ISR     BMPER           LL_HRTIM_IsActiveFlag_BMPER
10972   * @param  HRTIMx High Resolution Timer instance
10973   * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
10974   */
10975 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
10976 {
10977   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
10978 }
10979
10980 /**
10981   * @brief  Clear the Synchronization Input interrupt flag.
10982   * @rmtoll MICR     SYNCC           LL_HRTIM_ClearFlag_SYNC
10983   * @param  HRTIMx High Resolution Timer instance
10984   * @retval None
10985   */
10986 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10987 {
10988   SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
10989 }
10990
10991 /**
10992   * @brief  Indicate whether the Synchronization Input interrupt occurred.
10993   * @rmtoll MISR     SYNC           LL_HRTIM_IsActiveFlag_SYNC
10994   * @param  HRTIMx High Resolution Timer instance
10995   * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).
10996   */
10997 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
10998 {
10999   return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
11000 }
11001
11002 /**
11003   * @brief  Clear the update interrupt flag for a given timer (including the master timer) .
11004   * @rmtoll MICR        MUPDC          LL_HRTIM_ClearFlag_UPDATE\n
11005   *         TIMxICR     UPDC           LL_HRTIM_ClearFlag_UPDATE
11006   * @param  HRTIMx High Resolution Timer instance
11007   * @param  Timer This parameter can be one of the following values:
11008   *         @arg @ref LL_HRTIM_TIMER_MASTER
11009   *         @arg @ref LL_HRTIM_TIMER_A
11010   *         @arg @ref LL_HRTIM_TIMER_B
11011   *         @arg @ref LL_HRTIM_TIMER_C
11012   *         @arg @ref LL_HRTIM_TIMER_D
11013   *         @arg @ref LL_HRTIM_TIMER_E
11014   *         @arg @ref LL_HRTIM_TIMER_F
11015   * @retval None
11016   */
11017 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11018 {
11019   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11020   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11021                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11022   SET_BIT(*pReg, HRTIM_MICR_MUPD);
11023 }
11024
11025 /**
11026   * @brief  Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
11027   * @rmtoll MISR        MUPD          LL_HRTIM_IsActiveFlag_UPDATE\n
11028   *         TIMxISR     UPD           LL_HRTIM_IsActiveFlag_UPDATE
11029   * @param  HRTIMx High Resolution Timer instance
11030   * @param  Timer This parameter can be one of the following values:
11031   *         @arg @ref LL_HRTIM_TIMER_MASTER
11032   *         @arg @ref LL_HRTIM_TIMER_A
11033   *         @arg @ref LL_HRTIM_TIMER_B
11034   *         @arg @ref LL_HRTIM_TIMER_C
11035   *         @arg @ref LL_HRTIM_TIMER_D
11036   *         @arg @ref LL_HRTIM_TIMER_E
11037   *         @arg @ref LL_HRTIM_TIMER_F
11038   * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11039   */
11040 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11041 {
11042   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11043   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11044                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11045
11046   return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
11047 }
11048
11049 /**
11050   * @brief  Clear the repetition interrupt flag for a given timer (including the master timer) .
11051   * @rmtoll MICR        MREPC          LL_HRTIM_ClearFlag_REP\n
11052   *         TIMxICR     REPC           LL_HRTIM_ClearFlag_REP
11053   * @param  HRTIMx High Resolution Timer instance
11054   * @param  Timer This parameter can be one of the following values:
11055   *         @arg @ref LL_HRTIM_TIMER_MASTER
11056   *         @arg @ref LL_HRTIM_TIMER_A
11057   *         @arg @ref LL_HRTIM_TIMER_B
11058   *         @arg @ref LL_HRTIM_TIMER_C
11059   *         @arg @ref LL_HRTIM_TIMER_D
11060   *         @arg @ref LL_HRTIM_TIMER_E
11061   *         @arg @ref LL_HRTIM_TIMER_F
11062   * @retval None
11063   */
11064 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11065 {
11066   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11067   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11068                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11069   SET_BIT(*pReg, HRTIM_MICR_MREP);
11070
11071 }
11072
11073 /**
11074   * @brief  Indicate whether the repetition  interrupt has occurred for a given timer (including the master timer) .
11075   * @rmtoll MISR        MREP          LL_HRTIM_IsActiveFlag_REP\n
11076   *         TIMxISR     REP           LL_HRTIM_IsActiveFlag_REP
11077   * @param  HRTIMx High Resolution Timer instance
11078   * @param  Timer This parameter can be one of the following values:
11079   *         @arg @ref LL_HRTIM_TIMER_MASTER
11080   *         @arg @ref LL_HRTIM_TIMER_A
11081   *         @arg @ref LL_HRTIM_TIMER_B
11082   *         @arg @ref LL_HRTIM_TIMER_C
11083   *         @arg @ref LL_HRTIM_TIMER_D
11084   *         @arg @ref LL_HRTIM_TIMER_E
11085   *         @arg @ref LL_HRTIM_TIMER_F
11086   * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11087   */
11088 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11089 {
11090   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11091   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11092                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11093
11094   return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
11095 }
11096
11097 /**
11098   * @brief  Clear the compare 1 match interrupt for a given timer (including the master timer).
11099   * @rmtoll MICR        MCMP1C          LL_HRTIM_ClearFlag_CMP1\n
11100   *         TIMxICR     CMP1C           LL_HRTIM_ClearFlag_CMP1
11101   * @param  HRTIMx High Resolution Timer instance
11102   * @param  Timer This parameter can be one of the following values:
11103   *         @arg @ref LL_HRTIM_TIMER_MASTER
11104   *         @arg @ref LL_HRTIM_TIMER_A
11105   *         @arg @ref LL_HRTIM_TIMER_B
11106   *         @arg @ref LL_HRTIM_TIMER_C
11107   *         @arg @ref LL_HRTIM_TIMER_D
11108   *         @arg @ref LL_HRTIM_TIMER_E
11109   *         @arg @ref LL_HRTIM_TIMER_F
11110   * @retval None
11111   */
11112 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11113 {
11114   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11115   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11116                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11117   SET_BIT(*pReg, HRTIM_MICR_MCMP1);
11118 }
11119
11120 /**
11121   * @brief  Indicate whether the compare match 1  interrupt has occurred for a given timer (including the master timer) .
11122   * @rmtoll MISR        MCMP1          LL_HRTIM_IsActiveFlag_CMP1\n
11123   *         TIMxISR     CMP1           LL_HRTIM_IsActiveFlag_CMP1
11124   * @param  HRTIMx High Resolution Timer instance
11125   * @param  Timer This parameter can be one of the following values:
11126   *         @arg @ref LL_HRTIM_TIMER_MASTER
11127   *         @arg @ref LL_HRTIM_TIMER_A
11128   *         @arg @ref LL_HRTIM_TIMER_B
11129   *         @arg @ref LL_HRTIM_TIMER_C
11130   *         @arg @ref LL_HRTIM_TIMER_D
11131   *         @arg @ref LL_HRTIM_TIMER_E
11132   *         @arg @ref LL_HRTIM_TIMER_F
11133   * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11134   */
11135 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11136 {
11137   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11138   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11139                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11140
11141   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
11142 }
11143
11144 /**
11145   * @brief  Clear the compare 2 match interrupt for a given timer (including the master timer).
11146   * @rmtoll MICR        MCMP2C          LL_HRTIM_ClearFlag_CMP2\n
11147   *         TIMxICR     CMP2C           LL_HRTIM_ClearFlag_CMP2
11148   * @param  HRTIMx High Resolution Timer instance
11149   * @param  Timer This parameter can be one of the following values:
11150   *         @arg @ref LL_HRTIM_TIMER_MASTER
11151   *         @arg @ref LL_HRTIM_TIMER_A
11152   *         @arg @ref LL_HRTIM_TIMER_B
11153   *         @arg @ref LL_HRTIM_TIMER_C
11154   *         @arg @ref LL_HRTIM_TIMER_D
11155   *         @arg @ref LL_HRTIM_TIMER_E
11156   *         @arg @ref LL_HRTIM_TIMER_F
11157   * @retval None
11158   */
11159 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11160 {
11161   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11162   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11163                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11164   SET_BIT(*pReg, HRTIM_MICR_MCMP2);
11165 }
11166
11167 /**
11168   * @brief  Indicate whether the compare match 2  interrupt has occurred for a given timer (including the master timer) .
11169   * @rmtoll MISR        MCMP2          LL_HRTIM_IsActiveFlag_CMP2\n
11170   *         TIMxISR     CMP2           LL_HRTIM_IsActiveFlag_CMP2
11171   * @param  HRTIMx High Resolution Timer instance
11172   * @param  Timer This parameter can be one of the following values:
11173   *         @arg @ref LL_HRTIM_TIMER_MASTER
11174   *         @arg @ref LL_HRTIM_TIMER_A
11175   *         @arg @ref LL_HRTIM_TIMER_B
11176   *         @arg @ref LL_HRTIM_TIMER_C
11177   *         @arg @ref LL_HRTIM_TIMER_D
11178   *         @arg @ref LL_HRTIM_TIMER_E
11179   *         @arg @ref LL_HRTIM_TIMER_F
11180   * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11181   */
11182 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11183 {
11184   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11185   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11186                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11187
11188   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
11189 }
11190
11191 /**
11192   * @brief  Clear the compare 3 match interrupt for a given timer (including the master timer).
11193   * @rmtoll MICR        MCMP3C          LL_HRTIM_ClearFlag_CMP3\n
11194   *         TIMxICR     CMP3C           LL_HRTIM_ClearFlag_CMP3
11195   * @param  HRTIMx High Resolution Timer instance
11196   * @param  Timer This parameter can be one of the following values:
11197   *         @arg @ref LL_HRTIM_TIMER_MASTER
11198   *         @arg @ref LL_HRTIM_TIMER_A
11199   *         @arg @ref LL_HRTIM_TIMER_B
11200   *         @arg @ref LL_HRTIM_TIMER_C
11201   *         @arg @ref LL_HRTIM_TIMER_D
11202   *         @arg @ref LL_HRTIM_TIMER_E
11203   *         @arg @ref LL_HRTIM_TIMER_F
11204   * @retval None
11205   */
11206 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11207 {
11208   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11209   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11210                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11211   SET_BIT(*pReg, HRTIM_MICR_MCMP3);
11212 }
11213
11214 /**
11215   * @brief  Indicate whether the compare match 3  interrupt has occurred for a given timer (including the master timer) .
11216   * @rmtoll MISR        MCMP3          LL_HRTIM_IsActiveFlag_CMP3\n
11217   *         TIMxISR     CMP3           LL_HRTIM_IsActiveFlag_CMP3
11218   * @param  HRTIMx High Resolution Timer instance
11219   * @param  Timer This parameter can be one of the following values:
11220   *         @arg @ref LL_HRTIM_TIMER_MASTER
11221   *         @arg @ref LL_HRTIM_TIMER_A
11222   *         @arg @ref LL_HRTIM_TIMER_B
11223   *         @arg @ref LL_HRTIM_TIMER_C
11224   *         @arg @ref LL_HRTIM_TIMER_D
11225   *         @arg @ref LL_HRTIM_TIMER_E
11226   *         @arg @ref LL_HRTIM_TIMER_F
11227   * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11228   */
11229 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11230 {
11231   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11232   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11233                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11234
11235   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
11236 }
11237
11238 /**
11239   * @brief  Clear the compare 4 match interrupt for a given timer (including the master timer).
11240   * @rmtoll MICR        MCMP4C          LL_HRTIM_ClearFlag_CMP4\n
11241   *         TIMxICR     CMP4C           LL_HRTIM_ClearFlag_CMP4
11242   * @param  HRTIMx High Resolution Timer instance
11243   * @param  Timer This parameter can be one of the following values:
11244   *         @arg @ref LL_HRTIM_TIMER_MASTER
11245   *         @arg @ref LL_HRTIM_TIMER_A
11246   *         @arg @ref LL_HRTIM_TIMER_B
11247   *         @arg @ref LL_HRTIM_TIMER_C
11248   *         @arg @ref LL_HRTIM_TIMER_D
11249   *         @arg @ref LL_HRTIM_TIMER_E
11250   *         @arg @ref LL_HRTIM_TIMER_F
11251   * @retval None
11252   */
11253 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11254 {
11255   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11256   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11257                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11258   SET_BIT(*pReg, HRTIM_MICR_MCMP4);
11259 }
11260
11261 /**
11262   * @brief  Indicate whether the compare match 4  interrupt has occurred for a given timer (including the master timer) .
11263   * @rmtoll MISR        MCMP4          LL_HRTIM_IsActiveFlag_CMP4\n
11264   *         TIMxISR     CMP4           LL_HRTIM_IsActiveFlag_CMP4
11265   * @param  HRTIMx High Resolution Timer instance
11266   * @param  Timer This parameter can be one of the following values:
11267   *         @arg @ref LL_HRTIM_TIMER_MASTER
11268   *         @arg @ref LL_HRTIM_TIMER_A
11269   *         @arg @ref LL_HRTIM_TIMER_B
11270   *         @arg @ref LL_HRTIM_TIMER_C
11271   *         @arg @ref LL_HRTIM_TIMER_D
11272   *         @arg @ref LL_HRTIM_TIMER_E
11273   *         @arg @ref LL_HRTIM_TIMER_F
11274   * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11275   */
11276 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11277 {
11278   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11279   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11280                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11281
11282   return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
11283 }
11284
11285 /**
11286   * @brief  Clear the capture 1 interrupt flag for a given timer.
11287   * @rmtoll TIMxICR     CPT1C           LL_HRTIM_ClearFlag_CPT1
11288   * @param  HRTIMx High Resolution Timer instance
11289   * @param  Timer This parameter can be one of the following values:
11290   *         @arg @ref LL_HRTIM_TIMER_A
11291   *         @arg @ref LL_HRTIM_TIMER_B
11292   *         @arg @ref LL_HRTIM_TIMER_C
11293   *         @arg @ref LL_HRTIM_TIMER_D
11294   *         @arg @ref LL_HRTIM_TIMER_E
11295   *         @arg @ref LL_HRTIM_TIMER_F
11296   * @retval None
11297   */
11298 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11299 {
11300   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11301   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11302                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11303   SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
11304 }
11305
11306 /**
11307   * @brief  Indicate whether the capture 1 interrupt occurred for a given timer.
11308   * @rmtoll TIMxISR     CPT1           LL_HRTIM_IsActiveFlag_CPT1
11309   * @param  HRTIMx High Resolution Timer instance
11310   * @param  Timer This parameter can be one of the following values:
11311   *         @arg @ref LL_HRTIM_TIMER_A
11312   *         @arg @ref LL_HRTIM_TIMER_B
11313   *         @arg @ref LL_HRTIM_TIMER_C
11314   *         @arg @ref LL_HRTIM_TIMER_D
11315   *         @arg @ref LL_HRTIM_TIMER_E
11316   *         @arg @ref LL_HRTIM_TIMER_F
11317   * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
11318   */
11319 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11320 {
11321   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11322   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11323                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11324
11325   return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
11326 }
11327
11328 /**
11329   * @brief  Clear the capture 2 interrupt flag for a given timer.
11330   * @rmtoll TIMxICR     CPT2C           LL_HRTIM_ClearFlag_CPT2
11331   * @param  HRTIMx High Resolution Timer instance
11332   * @param  Timer This parameter can be one of the following values:
11333   *         @arg @ref LL_HRTIM_TIMER_A
11334   *         @arg @ref LL_HRTIM_TIMER_B
11335   *         @arg @ref LL_HRTIM_TIMER_C
11336   *         @arg @ref LL_HRTIM_TIMER_D
11337   *         @arg @ref LL_HRTIM_TIMER_E
11338   *         @arg @ref LL_HRTIM_TIMER_F
11339   * @retval None
11340   */
11341 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11342 {
11343   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11344   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11345                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11346   SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
11347 }
11348
11349 /**
11350   * @brief  Indicate whether the capture 2 interrupt occurred for a given timer.
11351   * @rmtoll TIMxISR     CPT2           LL_HRTIM_IsActiveFlag_CPT2
11352   * @param  HRTIMx High Resolution Timer instance
11353   * @param  Timer This parameter can be one of the following values:
11354   *         @arg @ref LL_HRTIM_TIMER_A
11355   *         @arg @ref LL_HRTIM_TIMER_B
11356   *         @arg @ref LL_HRTIM_TIMER_C
11357   *         @arg @ref LL_HRTIM_TIMER_D
11358   *         @arg @ref LL_HRTIM_TIMER_E
11359   *         @arg @ref LL_HRTIM_TIMER_F
11360   * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
11361   */
11362 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11363 {
11364   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11365   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11366                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11367
11368   return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
11369 }
11370
11371 /**
11372   * @brief  Clear the output 1 set interrupt flag for a given timer.
11373   * @rmtoll TIMxICR     SET1C           LL_HRTIM_ClearFlag_SET1
11374   * @param  HRTIMx High Resolution Timer instance
11375   * @param  Timer This parameter can be one of the following values:
11376   *         @arg @ref LL_HRTIM_TIMER_A
11377   *         @arg @ref LL_HRTIM_TIMER_B
11378   *         @arg @ref LL_HRTIM_TIMER_C
11379   *         @arg @ref LL_HRTIM_TIMER_D
11380   *         @arg @ref LL_HRTIM_TIMER_E
11381   *         @arg @ref LL_HRTIM_TIMER_F
11382   * @retval None
11383   */
11384 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11385 {
11386   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11387   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11388                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11389   SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
11390 }
11391
11392 /**
11393   * @brief  Indicate whether the output 1 set interrupt occurred for a given timer.
11394   * @rmtoll TIMxISR     SET1           LL_HRTIM_IsActiveFlag_SET1
11395   * @param  HRTIMx High Resolution Timer instance
11396   * @param  Timer This parameter can be one of the following values:
11397   *         @arg @ref LL_HRTIM_TIMER_A
11398   *         @arg @ref LL_HRTIM_TIMER_B
11399   *         @arg @ref LL_HRTIM_TIMER_C
11400   *         @arg @ref LL_HRTIM_TIMER_D
11401   *         @arg @ref LL_HRTIM_TIMER_E
11402   *         @arg @ref LL_HRTIM_TIMER_F
11403   * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
11404   */
11405 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11406 {
11407   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11408   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11409                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11410
11411   return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
11412 }
11413
11414 /**
11415   * @brief  Clear the output 1 reset interrupt flag for a given timer.
11416   * @rmtoll TIMxICR     RST1C           LL_HRTIM_ClearFlag_RST1
11417   * @param  HRTIMx High Resolution Timer instance
11418   * @param  Timer This parameter can be one of the following values:
11419   *         @arg @ref LL_HRTIM_TIMER_A
11420   *         @arg @ref LL_HRTIM_TIMER_B
11421   *         @arg @ref LL_HRTIM_TIMER_C
11422   *         @arg @ref LL_HRTIM_TIMER_D
11423   *         @arg @ref LL_HRTIM_TIMER_E
11424   *         @arg @ref LL_HRTIM_TIMER_F
11425   * @retval None
11426   */
11427 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11428 {
11429   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11430   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11431                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11432   SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
11433 }
11434
11435 /**
11436   * @brief  Indicate whether the output 1 reset interrupt occurred for a given timer.
11437   * @rmtoll TIMxISR     RST1           LL_HRTIM_IsActiveFlag_RST1
11438   * @param  HRTIMx High Resolution Timer instance
11439   * @param  Timer This parameter can be one of the following values:
11440   *         @arg @ref LL_HRTIM_TIMER_A
11441   *         @arg @ref LL_HRTIM_TIMER_B
11442   *         @arg @ref LL_HRTIM_TIMER_C
11443   *         @arg @ref LL_HRTIM_TIMER_D
11444   *         @arg @ref LL_HRTIM_TIMER_E
11445   *         @arg @ref LL_HRTIM_TIMER_F
11446   * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
11447   */
11448 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11449 {
11450   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11451   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11452                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11453
11454   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
11455 }
11456
11457 /**
11458   * @brief  Clear the output 2 set interrupt flag for a given timer.
11459   * @rmtoll TIMxICR     SET2C           LL_HRTIM_ClearFlag_SET2
11460   * @param  HRTIMx High Resolution Timer instance
11461   * @param  Timer This parameter can be one of the following values:
11462   *         @arg @ref LL_HRTIM_TIMER_A
11463   *         @arg @ref LL_HRTIM_TIMER_B
11464   *         @arg @ref LL_HRTIM_TIMER_C
11465   *         @arg @ref LL_HRTIM_TIMER_D
11466   *         @arg @ref LL_HRTIM_TIMER_E
11467   *         @arg @ref LL_HRTIM_TIMER_F
11468   * @retval None
11469   */
11470 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11471 {
11472   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11473   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11474                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11475   SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
11476 }
11477
11478 /**
11479   * @brief  Indicate whether the output 2 set interrupt occurred for a given timer.
11480   * @rmtoll TIMxISR     SET2           LL_HRTIM_IsActiveFlag_SET2
11481   * @param  HRTIMx High Resolution Timer instance
11482   * @param  Timer This parameter can be one of the following values:
11483   *         @arg @ref LL_HRTIM_TIMER_A
11484   *         @arg @ref LL_HRTIM_TIMER_B
11485   *         @arg @ref LL_HRTIM_TIMER_C
11486   *         @arg @ref LL_HRTIM_TIMER_D
11487   *         @arg @ref LL_HRTIM_TIMER_E
11488   *         @arg @ref LL_HRTIM_TIMER_F
11489   * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
11490   */
11491 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11492 {
11493   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11494   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11495                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11496
11497   return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
11498 }
11499
11500 /**
11501   * @brief  Clear the output 2reset interrupt flag for a given timer.
11502   * @rmtoll TIMxICR     RST2C           LL_HRTIM_ClearFlag_RST2
11503   * @param  HRTIMx High Resolution Timer instance
11504   * @param  Timer This parameter can be one of the following values:
11505   *         @arg @ref LL_HRTIM_TIMER_A
11506   *         @arg @ref LL_HRTIM_TIMER_B
11507   *         @arg @ref LL_HRTIM_TIMER_C
11508   *         @arg @ref LL_HRTIM_TIMER_D
11509   *         @arg @ref LL_HRTIM_TIMER_E
11510   *         @arg @ref LL_HRTIM_TIMER_F
11511   * @retval None
11512   */
11513 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11514 {
11515   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11516   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11517                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11518   SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
11519 }
11520
11521 /**
11522   * @brief  Indicate whether the output 2 reset interrupt occurred for a given timer.
11523   * @rmtoll TIMxISR     RST2           LL_HRTIM_IsActiveFlag_RST2
11524   * @param  HRTIMx High Resolution Timer instance
11525   * @param  Timer This parameter can be one of the following values:
11526   *         @arg @ref LL_HRTIM_TIMER_A
11527   *         @arg @ref LL_HRTIM_TIMER_B
11528   *         @arg @ref LL_HRTIM_TIMER_C
11529   *         @arg @ref LL_HRTIM_TIMER_D
11530   *         @arg @ref LL_HRTIM_TIMER_E
11531   *         @arg @ref LL_HRTIM_TIMER_F
11532   * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
11533   */
11534 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11535 {
11536   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11537   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11538                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11539
11540   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
11541 }
11542
11543 /**
11544   * @brief  Clear the reset and/or roll-over interrupt flag for a given timer.
11545   * @rmtoll TIMxICR     RSTC           LL_HRTIM_ClearFlag_RST
11546   * @param  HRTIMx High Resolution Timer instance
11547   * @param  Timer This parameter can be one of the following values:
11548   *         @arg @ref LL_HRTIM_TIMER_A
11549   *         @arg @ref LL_HRTIM_TIMER_B
11550   *         @arg @ref LL_HRTIM_TIMER_C
11551   *         @arg @ref LL_HRTIM_TIMER_D
11552   *         @arg @ref LL_HRTIM_TIMER_E
11553   *         @arg @ref LL_HRTIM_TIMER_F
11554   * @retval None
11555   */
11556 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11557 {
11558   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11559   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11560                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11561   SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
11562 }
11563
11564 /**
11565   * @brief  Indicate whether the  reset and/or roll-over interrupt occurred for a given timer.
11566   * @rmtoll TIMxISR     RST           LL_HRTIM_IsActiveFlag_RST
11567   * @param  HRTIMx High Resolution Timer instance
11568   * @param  Timer This parameter can be one of the following values:
11569   *         @arg @ref LL_HRTIM_TIMER_A
11570   *         @arg @ref LL_HRTIM_TIMER_B
11571   *         @arg @ref LL_HRTIM_TIMER_C
11572   *         @arg @ref LL_HRTIM_TIMER_D
11573   *         @arg @ref LL_HRTIM_TIMER_E
11574   *         @arg @ref LL_HRTIM_TIMER_F
11575   * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
11576   */
11577 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11578 {
11579   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11580   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11581                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11582
11583   return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
11584 }
11585
11586 /**
11587   * @brief  Clear the delayed protection interrupt flag for a given timer.
11588   * @rmtoll TIMxICR     DLYPRTC           LL_HRTIM_ClearFlag_DLYPRT
11589   * @param  HRTIMx High Resolution Timer instance
11590   * @param  Timer This parameter can be one of the following values:
11591   *         @arg @ref LL_HRTIM_TIMER_A
11592   *         @arg @ref LL_HRTIM_TIMER_B
11593   *         @arg @ref LL_HRTIM_TIMER_C
11594   *         @arg @ref LL_HRTIM_TIMER_D
11595   *         @arg @ref LL_HRTIM_TIMER_E
11596   *         @arg @ref LL_HRTIM_TIMER_F
11597   * @retval None
11598   */
11599 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11600 {
11601   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11602   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11603                                                               REG_OFFSET_TAB_TIMER[iTimer]));
11604   SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
11605 }
11606
11607 /**
11608   * @brief  Indicate whether the  delayed protection interrupt occurred for a given timer.
11609   * @rmtoll TIMxISR     DLYPRT           LL_HRTIM_IsActiveFlag_DLYPRT
11610   * @param  HRTIMx High Resolution Timer instance
11611   * @param  Timer This parameter can be one of the following values:
11612   *         @arg @ref LL_HRTIM_TIMER_A
11613   *         @arg @ref LL_HRTIM_TIMER_B
11614   *         @arg @ref LL_HRTIM_TIMER_C
11615   *         @arg @ref LL_HRTIM_TIMER_D
11616   *         @arg @ref LL_HRTIM_TIMER_E
11617   *         @arg @ref LL_HRTIM_TIMER_F
11618   * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
11619   */
11620 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11621 {
11622   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11623   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11624                                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11625
11626   return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
11627 }
11628
11629 /**
11630   * @}
11631   */
11632
11633 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
11634   * @{
11635   */
11636
11637 /**
11638   * @brief  Enable the fault 1 interrupt.
11639   * @rmtoll IER     FLT1IE           LL_HRTIM_EnableIT_FLT1
11640   * @param  HRTIMx High Resolution Timer instance
11641   * @retval None
11642   */
11643 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11644 {
11645   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11646 }
11647
11648 /**
11649   * @brief  Disable the fault 1 interrupt.
11650   * @rmtoll IER     FLT1IE           LL_HRTIM_DisableIT_FLT1
11651   * @param  HRTIMx High Resolution Timer instance
11652   * @retval None
11653   */
11654 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11655 {
11656   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11657 }
11658
11659 /**
11660   * @brief  Indicate whether the fault 1 interrupt is enabled.
11661   * @rmtoll IER     FLT1IE           LL_HRTIM_IsEnabledIT_FLT1
11662   * @param  HRTIMx High Resolution Timer instance
11663   * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
11664   */
11665 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
11666 {
11667   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
11668 }
11669
11670 /**
11671   * @brief  Enable the fault 2 interrupt.
11672   * @rmtoll IER     FLT2IE           LL_HRTIM_EnableIT_FLT2
11673   * @param  HRTIMx High Resolution Timer instance
11674   * @retval None
11675   */
11676 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11677 {
11678   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11679 }
11680
11681 /**
11682   * @brief  Disable the fault 2 interrupt.
11683   * @rmtoll IER     FLT2IE           LL_HRTIM_DisableIT_FLT2
11684   * @param  HRTIMx High Resolution Timer instance
11685   * @retval None
11686   */
11687 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11688 {
11689   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11690 }
11691
11692 /**
11693   * @brief  Indicate whether the fault 2 interrupt is enabled.
11694   * @rmtoll IER     FLT2IE           LL_HRTIM_IsEnabledIT_FLT2
11695   * @param  HRTIMx High Resolution Timer instance
11696   * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
11697   */
11698 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
11699 {
11700   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
11701 }
11702
11703 /**
11704   * @brief  Enable the fault 3 interrupt.
11705   * @rmtoll IER     FLT3IE           LL_HRTIM_EnableIT_FLT3
11706   * @param  HRTIMx High Resolution Timer instance
11707   * @retval None
11708   */
11709 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11710 {
11711   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11712 }
11713
11714 /**
11715   * @brief  Disable the fault 3 interrupt.
11716   * @rmtoll IER     FLT3IE           LL_HRTIM_DisableIT_FLT3
11717   * @param  HRTIMx High Resolution Timer instance
11718   * @retval None
11719   */
11720 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11721 {
11722   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11723 }
11724
11725 /**
11726   * @brief  Indicate whether the fault 3 interrupt is enabled.
11727   * @rmtoll IER     FLT3IE           LL_HRTIM_IsEnabledIT_FLT3
11728   * @param  HRTIMx High Resolution Timer instance
11729   * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
11730   */
11731 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
11732 {
11733   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
11734 }
11735
11736 /**
11737   * @brief  Enable the fault 4 interrupt.
11738   * @rmtoll IER     FLT4IE           LL_HRTIM_EnableIT_FLT4
11739   * @param  HRTIMx High Resolution Timer instance
11740   * @retval None
11741   */
11742 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11743 {
11744   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11745 }
11746
11747 /**
11748   * @brief  Disable the fault 4 interrupt.
11749   * @rmtoll IER     FLT4IE           LL_HRTIM_DisableIT_FLT4
11750   * @param  HRTIMx High Resolution Timer instance
11751   * @retval None
11752   */
11753 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11754 {
11755   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11756 }
11757
11758 /**
11759   * @brief  Indicate whether the fault 4 interrupt is enabled.
11760   * @rmtoll IER     FLT4IE           LL_HRTIM_IsEnabledIT_FLT4
11761   * @param  HRTIMx High Resolution Timer instance
11762   * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
11763   */
11764 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
11765 {
11766   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
11767 }
11768
11769 /**
11770   * @brief  Enable the fault 5 interrupt.
11771   * @rmtoll IER     FLT5IE           LL_HRTIM_EnableIT_FLT5
11772   * @param  HRTIMx High Resolution Timer instance
11773   * @retval None
11774   */
11775 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11776 {
11777   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11778 }
11779
11780 /**
11781   * @brief  Disable the fault 5 interrupt.
11782   * @rmtoll IER     FLT5IE           LL_HRTIM_DisableIT_FLT5
11783   * @param  HRTIMx High Resolution Timer instance
11784   * @retval None
11785   */
11786 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11787 {
11788   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11789 }
11790
11791 /**
11792   * @brief  Indicate whether the fault 5 interrupt is enabled.
11793   * @rmtoll IER     FLT5IE           LL_HRTIM_IsEnabledIT_FLT5
11794   * @param  HRTIMx High Resolution Timer instance
11795   * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
11796   */
11797 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
11798 {
11799   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
11800 }
11801
11802 /**
11803   * @brief  Enable the fault 6 interrupt.
11804   * @rmtoll IER     FLT6IE           LL_HRTIM_EnableIT_FLT6
11805   * @param  HRTIMx High Resolution Timer instance
11806   * @retval None
11807   */
11808 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11809 {
11810   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11811 }
11812
11813 /**
11814   * @brief  Disable the fault 6 interrupt.
11815   * @rmtoll IER     FLT6IE           LL_HRTIM_DisableIT_FLT6
11816   * @param  HRTIMx High Resolution Timer instance
11817   * @retval None
11818   */
11819 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11820 {
11821   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11822 }
11823
11824 /**
11825   * @brief  Indicate whether the fault 6 interrupt is enabled.
11826   * @rmtoll IER     FLT6IE           LL_HRTIM_IsEnabledIT_FLT6
11827   * @param  HRTIMx High Resolution Timer instance
11828   * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
11829   */
11830 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(const HRTIM_TypeDef *HRTIMx)
11831 {
11832   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
11833 }
11834
11835 /**
11836   * @brief  Enable the system fault interrupt.
11837   * @rmtoll IER     SYSFLTIE           LL_HRTIM_EnableIT_SYSFLT
11838   * @param  HRTIMx High Resolution Timer instance
11839   * @retval None
11840   */
11841 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11842 {
11843   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11844 }
11845
11846 /**
11847   * @brief  Disable the system fault interrupt.
11848   * @rmtoll IER     SYSFLTIE           LL_HRTIM_DisableIT_SYSFLT
11849   * @param  HRTIMx High Resolution Timer instance
11850   * @retval None
11851   */
11852 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11853 {
11854   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11855 }
11856
11857 /**
11858   * @brief  Indicate whether the system fault interrupt is enabled.
11859   * @rmtoll IER     SYSFLTIE           LL_HRTIM_IsEnabledIT_SYSFLT
11860   * @param  HRTIMx High Resolution Timer instance
11861   * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
11862   */
11863 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
11864 {
11865   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
11866 }
11867
11868 /**
11869   * @brief  Enable the DLL ready interrupt.
11870   * @rmtoll IER     DLLRDYIE           LL_HRTIM_EnableIT_DLLRDY
11871   * @param  HRTIMx High Resolution Timer instance
11872   * @retval None
11873   */
11874 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11875 {
11876   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11877 }
11878
11879 /**
11880   * @brief  Disable the DLL ready interrupt.
11881   * @rmtoll IER     DLLRDYIE           LL_HRTIM_DisableIT_DLLRDY
11882   * @param  HRTIMx High Resolution Timer instance
11883   * @retval None
11884   */
11885 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11886 {
11887   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11888 }
11889
11890 /**
11891   * @brief  Indicate whether the DLL ready interrupt is enabled.
11892   * @rmtoll IER     DLLRDYIE           LL_HRTIM_IsEnabledIT_DLLRDY
11893   * @param  HRTIMx High Resolution Timer instance
11894   * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
11895   */
11896 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef *HRTIMx)
11897 {
11898   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
11899 }
11900
11901 /**
11902   * @brief  Enable the burst mode period interrupt.
11903   * @rmtoll IER     BMPERIE           LL_HRTIM_EnableIT_BMPER
11904   * @param  HRTIMx High Resolution Timer instance
11905   * @retval None
11906   */
11907 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11908 {
11909   SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11910 }
11911
11912 /**
11913   * @brief  Disable the burst mode period interrupt.
11914   * @rmtoll IER     BMPERIE           LL_HRTIM_DisableIT_BMPER
11915   * @param  HRTIMx High Resolution Timer instance
11916   * @retval None
11917   */
11918 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11919 {
11920   CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11921 }
11922
11923 /**
11924   * @brief  Indicate whether the burst mode period interrupt is enabled.
11925   * @rmtoll IER     BMPERIE           LL_HRTIM_IsEnabledIT_BMPER
11926   * @param  HRTIMx High Resolution Timer instance
11927   * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
11928   */
11929 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
11930 {
11931   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
11932 }
11933
11934 /**
11935   * @brief  Enable the synchronization input interrupt.
11936   * @rmtoll MDIER     SYNCIE           LL_HRTIM_EnableIT_SYNC
11937   * @param  HRTIMx High Resolution Timer instance
11938   * @retval None
11939   */
11940 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11941 {
11942   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11943 }
11944
11945 /**
11946   * @brief  Disable the synchronization input interrupt.
11947   * @rmtoll MDIER     SYNCIE           LL_HRTIM_DisableIT_SYNC
11948   * @param  HRTIMx High Resolution Timer instance
11949   * @retval None
11950   */
11951 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11952 {
11953   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11954 }
11955
11956 /**
11957   * @brief  Indicate whether the synchronization input interrupt is enabled.
11958   * @rmtoll MDIER     SYNCIE           LL_HRTIM_IsEnabledIT_SYNC
11959   * @param  HRTIMx High Resolution Timer instance
11960   * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
11961   */
11962 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
11963 {
11964   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
11965 }
11966
11967 /**
11968   * @brief  Enable the update interrupt for a given timer.
11969   * @rmtoll MDIER        MUPDIE           LL_HRTIM_EnableIT_UPDATE\n
11970   *         TIMxDIER     UPDIE            LL_HRTIM_EnableIT_UPDATE
11971   * @param  HRTIMx High Resolution Timer instance
11972   * @param  Timer This parameter can be one of the following values:
11973   *         @arg @ref LL_HRTIM_TIMER_MASTER
11974   *         @arg @ref LL_HRTIM_TIMER_A
11975   *         @arg @ref LL_HRTIM_TIMER_B
11976   *         @arg @ref LL_HRTIM_TIMER_C
11977   *         @arg @ref LL_HRTIM_TIMER_D
11978   *         @arg @ref LL_HRTIM_TIMER_E
11979   *         @arg @ref LL_HRTIM_TIMER_F
11980   * @retval None
11981   */
11982 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11983 {
11984   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11985   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11986                                                     REG_OFFSET_TAB_TIMER[iTimer]));
11987   SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
11988 }
11989
11990 /**
11991   * @brief  Disable the update interrupt for a given timer.
11992   * @rmtoll MDIER        MUPDIE           LL_HRTIM_DisableIT_UPDATE\n
11993   *         TIMxDIER     UPDIE            LL_HRTIM_DisableIT_UPDATE
11994   * @param  HRTIMx High Resolution Timer instance
11995   * @param  Timer This parameter can be one of the following values:
11996   *         @arg @ref LL_HRTIM_TIMER_MASTER
11997   *         @arg @ref LL_HRTIM_TIMER_A
11998   *         @arg @ref LL_HRTIM_TIMER_B
11999   *         @arg @ref LL_HRTIM_TIMER_C
12000   *         @arg @ref LL_HRTIM_TIMER_D
12001   *         @arg @ref LL_HRTIM_TIMER_E
12002   *         @arg @ref LL_HRTIM_TIMER_F
12003   * @retval None
12004   */
12005 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12006 {
12007   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12008   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12009                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12010   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
12011 }
12012
12013 /**
12014   * @brief  Indicate whether the update interrupt is enabled for a given timer.
12015   * @rmtoll MDIER        MUPDIE           LL_HRTIM_IsEnabledIT_UPDATE\n
12016   *         TIMxDIER     UPDIE            LL_HRTIM_IsEnabledIT_UPDATE
12017   * @param  HRTIMx High Resolution Timer instance
12018   * @param  Timer This parameter can be one of the following values:
12019   *         @arg @ref LL_HRTIM_TIMER_MASTER
12020   *         @arg @ref LL_HRTIM_TIMER_A
12021   *         @arg @ref LL_HRTIM_TIMER_B
12022   *         @arg @ref LL_HRTIM_TIMER_C
12023   *         @arg @ref LL_HRTIM_TIMER_D
12024   *         @arg @ref LL_HRTIM_TIMER_E
12025   *         @arg @ref LL_HRTIM_TIMER_F
12026   * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12027   */
12028 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12029 {
12030   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12031   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12032                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12033
12034   return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
12035 }
12036
12037 /**
12038   * @brief  Enable the repetition interrupt for a given timer.
12039   * @rmtoll MDIER        MREPIE           LL_HRTIM_EnableIT_REP\n
12040   *         TIMxDIER     REPIE            LL_HRTIM_EnableIT_REP
12041   * @param  HRTIMx High Resolution Timer instance
12042   * @param  Timer This parameter can be one of the following values:
12043   *         @arg @ref LL_HRTIM_TIMER_MASTER
12044   *         @arg @ref LL_HRTIM_TIMER_A
12045   *         @arg @ref LL_HRTIM_TIMER_B
12046   *         @arg @ref LL_HRTIM_TIMER_C
12047   *         @arg @ref LL_HRTIM_TIMER_D
12048   *         @arg @ref LL_HRTIM_TIMER_E
12049   *         @arg @ref LL_HRTIM_TIMER_F
12050   * @retval None
12051   */
12052 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12053 {
12054   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12055   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12056                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12057   SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
12058 }
12059
12060 /**
12061   * @brief  Disable the repetition interrupt for a given timer.
12062   * @rmtoll MDIER        MREPIE           LL_HRTIM_DisableIT_REP\n
12063   *         TIMxDIER     REPIE            LL_HRTIM_DisableIT_REP
12064   * @param  HRTIMx High Resolution Timer instance
12065   * @param  Timer This parameter can be one of the following values:
12066   *         @arg @ref LL_HRTIM_TIMER_MASTER
12067   *         @arg @ref LL_HRTIM_TIMER_A
12068   *         @arg @ref LL_HRTIM_TIMER_B
12069   *         @arg @ref LL_HRTIM_TIMER_C
12070   *         @arg @ref LL_HRTIM_TIMER_D
12071   *         @arg @ref LL_HRTIM_TIMER_E
12072   *         @arg @ref LL_HRTIM_TIMER_F
12073   * @retval None
12074   */
12075 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12076 {
12077   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12078   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12079                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12080   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
12081 }
12082
12083 /**
12084   * @brief  Indicate whether the repetition interrupt is enabled for a given timer.
12085   * @rmtoll MDIER        MREPIE           LL_HRTIM_IsEnabledIT_REP\n
12086   *         TIMxDIER     REPIE            LL_HRTIM_IsEnabledIT_REP
12087   * @param  HRTIMx High Resolution Timer instance
12088   * @param  Timer This parameter can be one of the following values:
12089   *         @arg @ref LL_HRTIM_TIMER_MASTER
12090   *         @arg @ref LL_HRTIM_TIMER_A
12091   *         @arg @ref LL_HRTIM_TIMER_B
12092   *         @arg @ref LL_HRTIM_TIMER_C
12093   *         @arg @ref LL_HRTIM_TIMER_D
12094   *         @arg @ref LL_HRTIM_TIMER_E
12095   *         @arg @ref LL_HRTIM_TIMER_F
12096   * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12097   */
12098 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12099 {
12100   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12101   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12102                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12103
12104   return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
12105 }
12106
12107 /**
12108   * @brief  Enable the compare 1 interrupt for a given timer.
12109   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_EnableIT_CMP1\n
12110   *         TIMxDIER     CMP1IE            LL_HRTIM_EnableIT_CMP1
12111   * @param  HRTIMx High Resolution Timer instance
12112   * @param  Timer This parameter can be one of the following values:
12113   *         @arg @ref LL_HRTIM_TIMER_MASTER
12114   *         @arg @ref LL_HRTIM_TIMER_A
12115   *         @arg @ref LL_HRTIM_TIMER_B
12116   *         @arg @ref LL_HRTIM_TIMER_C
12117   *         @arg @ref LL_HRTIM_TIMER_D
12118   *         @arg @ref LL_HRTIM_TIMER_E
12119   *         @arg @ref LL_HRTIM_TIMER_F
12120   * @retval None
12121   */
12122 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12123 {
12124   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12125   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12126                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12127   SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12128 }
12129
12130 /**
12131   * @brief  Disable the compare 1 interrupt for a given timer.
12132   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_DisableIT_CMP1\n
12133   *         TIMxDIER     CMP1IE            LL_HRTIM_DisableIT_CMP1
12134   * @param  HRTIMx High Resolution Timer instance
12135   * @param  Timer This parameter can be one of the following values:
12136   *         @arg @ref LL_HRTIM_TIMER_MASTER
12137   *         @arg @ref LL_HRTIM_TIMER_A
12138   *         @arg @ref LL_HRTIM_TIMER_B
12139   *         @arg @ref LL_HRTIM_TIMER_C
12140   *         @arg @ref LL_HRTIM_TIMER_D
12141   *         @arg @ref LL_HRTIM_TIMER_E
12142   *         @arg @ref LL_HRTIM_TIMER_F
12143   * @retval None
12144   */
12145 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12146 {
12147   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12148   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12149                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12150   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12151 }
12152
12153 /**
12154   * @brief  Indicate whether the compare 1 interrupt is enabled for a given timer.
12155   * @rmtoll MDIER        MCMP1IE           LL_HRTIM_IsEnabledIT_CMP1\n
12156   *         TIMxDIER     CMP1IE            LL_HRTIM_IsEnabledIT_CMP1
12157   * @param  HRTIMx High Resolution Timer instance
12158   * @param  Timer This parameter can be one of the following values:
12159   *         @arg @ref LL_HRTIM_TIMER_MASTER
12160   *         @arg @ref LL_HRTIM_TIMER_A
12161   *         @arg @ref LL_HRTIM_TIMER_B
12162   *         @arg @ref LL_HRTIM_TIMER_C
12163   *         @arg @ref LL_HRTIM_TIMER_D
12164   *         @arg @ref LL_HRTIM_TIMER_E
12165   *         @arg @ref LL_HRTIM_TIMER_F
12166   * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12167   */
12168 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12169 {
12170   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12171   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12172                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12173
12174   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
12175 }
12176
12177 /**
12178   * @brief  Enable the compare 2 interrupt for a given timer.
12179   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_EnableIT_CMP2\n
12180   *         TIMxDIER     CMP2IE            LL_HRTIM_EnableIT_CMP2
12181   * @param  HRTIMx High Resolution Timer instance
12182   * @param  Timer This parameter can be one of the following values:
12183   *         @arg @ref LL_HRTIM_TIMER_MASTER
12184   *         @arg @ref LL_HRTIM_TIMER_A
12185   *         @arg @ref LL_HRTIM_TIMER_B
12186   *         @arg @ref LL_HRTIM_TIMER_C
12187   *         @arg @ref LL_HRTIM_TIMER_D
12188   *         @arg @ref LL_HRTIM_TIMER_E
12189   *         @arg @ref LL_HRTIM_TIMER_F
12190   * @retval None
12191   */
12192 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12193 {
12194   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12195   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12196                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12197   SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12198 }
12199
12200 /**
12201   * @brief  Disable the compare 2 interrupt for a given timer.
12202   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_DisableIT_CMP2\n
12203   *         TIMxDIER     CMP2IE            LL_HRTIM_DisableIT_CMP2
12204   * @param  HRTIMx High Resolution Timer instance
12205   * @param  Timer This parameter can be one of the following values:
12206   *         @arg @ref LL_HRTIM_TIMER_MASTER
12207   *         @arg @ref LL_HRTIM_TIMER_A
12208   *         @arg @ref LL_HRTIM_TIMER_B
12209   *         @arg @ref LL_HRTIM_TIMER_C
12210   *         @arg @ref LL_HRTIM_TIMER_D
12211   *         @arg @ref LL_HRTIM_TIMER_E
12212   *         @arg @ref LL_HRTIM_TIMER_F
12213   * @retval None
12214   */
12215 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12216 {
12217   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12218   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12219                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12220   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12221 }
12222
12223 /**
12224   * @brief  Indicate whether the compare 2 interrupt is enabled for a given timer.
12225   * @rmtoll MDIER        MCMP2IE           LL_HRTIM_IsEnabledIT_CMP2\n
12226   *         TIMxDIER     CMP2IE            LL_HRTIM_IsEnabledIT_CMP2
12227   * @param  HRTIMx High Resolution Timer instance
12228   * @param  Timer This parameter can be one of the following values:
12229   *         @arg @ref LL_HRTIM_TIMER_MASTER
12230   *         @arg @ref LL_HRTIM_TIMER_A
12231   *         @arg @ref LL_HRTIM_TIMER_B
12232   *         @arg @ref LL_HRTIM_TIMER_C
12233   *         @arg @ref LL_HRTIM_TIMER_D
12234   *         @arg @ref LL_HRTIM_TIMER_E
12235   *         @arg @ref LL_HRTIM_TIMER_F
12236   * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12237   */
12238 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12239 {
12240   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12241   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12242                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12243
12244   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
12245 }
12246
12247 /**
12248   * @brief  Enable the compare 3 interrupt for a given timer.
12249   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_EnableIT_CMP3\n
12250   *         TIMxDIER     CMP3IE            LL_HRTIM_EnableIT_CMP3
12251   * @param  HRTIMx High Resolution Timer instance
12252   * @param  Timer This parameter can be one of the following values:
12253   *         @arg @ref LL_HRTIM_TIMER_MASTER
12254   *         @arg @ref LL_HRTIM_TIMER_A
12255   *         @arg @ref LL_HRTIM_TIMER_B
12256   *         @arg @ref LL_HRTIM_TIMER_C
12257   *         @arg @ref LL_HRTIM_TIMER_D
12258   *         @arg @ref LL_HRTIM_TIMER_E
12259   *         @arg @ref LL_HRTIM_TIMER_F
12260   * @retval None
12261   */
12262 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12263 {
12264   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12265   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12266                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12267   SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12268 }
12269
12270 /**
12271   * @brief  Disable the compare 3 interrupt for a given timer.
12272   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_DisableIT_CMP3\n
12273   *         TIMxDIER     CMP3IE            LL_HRTIM_DisableIT_CMP3
12274   * @param  HRTIMx High Resolution Timer instance
12275   * @param  Timer This parameter can be one of the following values:
12276   *         @arg @ref LL_HRTIM_TIMER_MASTER
12277   *         @arg @ref LL_HRTIM_TIMER_A
12278   *         @arg @ref LL_HRTIM_TIMER_B
12279   *         @arg @ref LL_HRTIM_TIMER_C
12280   *         @arg @ref LL_HRTIM_TIMER_D
12281   *         @arg @ref LL_HRTIM_TIMER_E
12282   *         @arg @ref LL_HRTIM_TIMER_F
12283   * @retval None
12284   */
12285 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12286 {
12287   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12288   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12289                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12290   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12291 }
12292
12293 /**
12294   * @brief  Indicate whether the compare 3 interrupt is enabled for a given timer.
12295   * @rmtoll MDIER        MCMP3IE           LL_HRTIM_IsEnabledIT_CMP3\n
12296   *         TIMxDIER     CMP3IE            LL_HRTIM_IsEnabledIT_CMP3
12297   * @param  HRTIMx High Resolution Timer instance
12298   * @param  Timer This parameter can be one of the following values:
12299   *         @arg @ref LL_HRTIM_TIMER_MASTER
12300   *         @arg @ref LL_HRTIM_TIMER_A
12301   *         @arg @ref LL_HRTIM_TIMER_B
12302   *         @arg @ref LL_HRTIM_TIMER_C
12303   *         @arg @ref LL_HRTIM_TIMER_D
12304   *         @arg @ref LL_HRTIM_TIMER_E
12305   *         @arg @ref LL_HRTIM_TIMER_F
12306   * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12307   */
12308 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12309 {
12310   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12311   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12312                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12313
12314   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
12315 }
12316
12317 /**
12318   * @brief  Enable the compare 4 interrupt for a given timer.
12319   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_EnableIT_CMP4\n
12320   *         TIMxDIER     CMP4IE            LL_HRTIM_EnableIT_CMP4
12321   * @param  HRTIMx High Resolution Timer instance
12322   * @param  Timer This parameter can be one of the following values:
12323   *         @arg @ref LL_HRTIM_TIMER_MASTER
12324   *         @arg @ref LL_HRTIM_TIMER_A
12325   *         @arg @ref LL_HRTIM_TIMER_B
12326   *         @arg @ref LL_HRTIM_TIMER_C
12327   *         @arg @ref LL_HRTIM_TIMER_D
12328   *         @arg @ref LL_HRTIM_TIMER_E
12329   *         @arg @ref LL_HRTIM_TIMER_F
12330   * @retval None
12331   */
12332 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12333 {
12334   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12335   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12336                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12337   SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12338 }
12339
12340 /**
12341   * @brief  Disable the compare 4 interrupt for a given timer.
12342   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_DisableIT_CMP4\n
12343   *         TIMxDIER     CMP4IE            LL_HRTIM_DisableIT_CMP4
12344   * @param  HRTIMx High Resolution Timer instance
12345   * @param  Timer This parameter can be one of the following values:
12346   *         @arg @ref LL_HRTIM_TIMER_MASTER
12347   *         @arg @ref LL_HRTIM_TIMER_A
12348   *         @arg @ref LL_HRTIM_TIMER_B
12349   *         @arg @ref LL_HRTIM_TIMER_C
12350   *         @arg @ref LL_HRTIM_TIMER_D
12351   *         @arg @ref LL_HRTIM_TIMER_E
12352   *         @arg @ref LL_HRTIM_TIMER_F
12353   * @retval None
12354   */
12355 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12356 {
12357   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12358   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12359                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12360   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12361 }
12362
12363 /**
12364   * @brief  Indicate whether the compare 4 interrupt is enabled for a given timer.
12365   * @rmtoll MDIER        MCMP4IE           LL_HRTIM_IsEnabledIT_CMP4\n
12366   *         TIMxDIER     CMP4IE            LL_HRTIM_IsEnabledIT_CMP4
12367   * @param  HRTIMx High Resolution Timer instance
12368   * @param  Timer This parameter can be one of the following values:
12369   *         @arg @ref LL_HRTIM_TIMER_MASTER
12370   *         @arg @ref LL_HRTIM_TIMER_A
12371   *         @arg @ref LL_HRTIM_TIMER_B
12372   *         @arg @ref LL_HRTIM_TIMER_C
12373   *         @arg @ref LL_HRTIM_TIMER_D
12374   *         @arg @ref LL_HRTIM_TIMER_E
12375   *         @arg @ref LL_HRTIM_TIMER_F
12376   * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12377   */
12378 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12379 {
12380   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12381   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12382                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12383
12384   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
12385 }
12386
12387 /**
12388   * @brief  Enable the capture 1 interrupt for a given timer.
12389   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_EnableIT_CPT1
12390   * @param  HRTIMx High Resolution Timer instance
12391   * @param  Timer This parameter can be one of the following values:
12392   *         @arg @ref LL_HRTIM_TIMER_A
12393   *         @arg @ref LL_HRTIM_TIMER_B
12394   *         @arg @ref LL_HRTIM_TIMER_C
12395   *         @arg @ref LL_HRTIM_TIMER_D
12396   *         @arg @ref LL_HRTIM_TIMER_E
12397   *         @arg @ref LL_HRTIM_TIMER_F
12398   * @retval None
12399   */
12400 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12401 {
12402   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12403   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12404                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12405   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12406 }
12407
12408 /**
12409   * @brief  Enable the capture 1 interrupt for a given timer.
12410   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_DisableIT_CPT1
12411   * @param  HRTIMx High Resolution Timer instance
12412   * @param  Timer This parameter can be one of the following values:
12413   *         @arg @ref LL_HRTIM_TIMER_A
12414   *         @arg @ref LL_HRTIM_TIMER_B
12415   *         @arg @ref LL_HRTIM_TIMER_C
12416   *         @arg @ref LL_HRTIM_TIMER_D
12417   *         @arg @ref LL_HRTIM_TIMER_E
12418   *         @arg @ref LL_HRTIM_TIMER_F
12419   * @retval None
12420   */
12421 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12422 {
12423   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12424   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12425                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12426   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12427 }
12428
12429 /**
12430   * @brief  Indicate whether the capture 1 interrupt is enabled for a given timer.
12431   * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_IsEnabledIT_CPT1
12432   * @param  HRTIMx High Resolution Timer instance
12433   * @param  Timer This parameter can be one of the following values:
12434   *         @arg @ref LL_HRTIM_TIMER_A
12435   *         @arg @ref LL_HRTIM_TIMER_B
12436   *         @arg @ref LL_HRTIM_TIMER_C
12437   *         @arg @ref LL_HRTIM_TIMER_D
12438   *         @arg @ref LL_HRTIM_TIMER_E
12439   *         @arg @ref LL_HRTIM_TIMER_F
12440   * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
12441   */
12442 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12443 {
12444   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12445   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12446                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12447
12448   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
12449 }
12450
12451 /**
12452   * @brief  Enable the capture 2 interrupt for a given timer.
12453   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_EnableIT_CPT2
12454   * @param  HRTIMx High Resolution Timer instance
12455   * @param  Timer This parameter can be one of the following values:
12456   *         @arg @ref LL_HRTIM_TIMER_A
12457   *         @arg @ref LL_HRTIM_TIMER_B
12458   *         @arg @ref LL_HRTIM_TIMER_C
12459   *         @arg @ref LL_HRTIM_TIMER_D
12460   *         @arg @ref LL_HRTIM_TIMER_E
12461   *         @arg @ref LL_HRTIM_TIMER_F
12462   * @retval None
12463   */
12464 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12465 {
12466   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12467   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12468                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12469   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12470 }
12471
12472 /**
12473   * @brief  Enable the capture 2 interrupt for a given timer.
12474   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_DisableIT_CPT2
12475   * @param  HRTIMx High Resolution Timer instance
12476   * @param  Timer This parameter can be one of the following values:
12477   *         @arg @ref LL_HRTIM_TIMER_A
12478   *         @arg @ref LL_HRTIM_TIMER_B
12479   *         @arg @ref LL_HRTIM_TIMER_C
12480   *         @arg @ref LL_HRTIM_TIMER_D
12481   *         @arg @ref LL_HRTIM_TIMER_E
12482   *         @arg @ref LL_HRTIM_TIMER_F
12483   * @retval None
12484   */
12485 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12486 {
12487   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12488   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12489                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12490   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12491 }
12492
12493 /**
12494   * @brief  Indicate whether the capture 2 interrupt is enabled for a given timer.
12495   * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_IsEnabledIT_CPT2
12496   * @param  HRTIMx High Resolution Timer instance
12497   * @param  Timer This parameter can be one of the following values:
12498   *         @arg @ref LL_HRTIM_TIMER_A
12499   *         @arg @ref LL_HRTIM_TIMER_B
12500   *         @arg @ref LL_HRTIM_TIMER_C
12501   *         @arg @ref LL_HRTIM_TIMER_D
12502   *         @arg @ref LL_HRTIM_TIMER_E
12503   *         @arg @ref LL_HRTIM_TIMER_F
12504   * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
12505   */
12506 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12507 {
12508   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12509   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12510                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12511
12512   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
12513 }
12514
12515 /**
12516   * @brief  Enable the output 1 set interrupt for a given timer.
12517   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_EnableIT_SET1
12518   * @param  HRTIMx High Resolution Timer instance
12519   * @param  Timer This parameter can be one of the following values:
12520   *         @arg @ref LL_HRTIM_TIMER_A
12521   *         @arg @ref LL_HRTIM_TIMER_B
12522   *         @arg @ref LL_HRTIM_TIMER_C
12523   *         @arg @ref LL_HRTIM_TIMER_D
12524   *         @arg @ref LL_HRTIM_TIMER_E
12525   *         @arg @ref LL_HRTIM_TIMER_F
12526   * @retval None
12527   */
12528 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12529 {
12530   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12531   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12532                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12533   SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12534 }
12535
12536 /**
12537   * @brief  Disable the output 1 set interrupt for a given timer.
12538   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_DisableIT_SET1
12539   * @param  HRTIMx High Resolution Timer instance
12540   * @param  Timer This parameter can be one of the following values:
12541   *         @arg @ref LL_HRTIM_TIMER_A
12542   *         @arg @ref LL_HRTIM_TIMER_B
12543   *         @arg @ref LL_HRTIM_TIMER_C
12544   *         @arg @ref LL_HRTIM_TIMER_D
12545   *         @arg @ref LL_HRTIM_TIMER_E
12546   *         @arg @ref LL_HRTIM_TIMER_F
12547   * @retval None
12548   */
12549 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12550 {
12551   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12552   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12553                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12554   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12555 }
12556
12557 /**
12558   * @brief  Indicate whether the output 1 set interrupt is enabled for a given timer.
12559   * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_IsEnabledIT_SET1
12560   * @param  HRTIMx High Resolution Timer instance
12561   * @param  Timer This parameter can be one of the following values:
12562   *         @arg @ref LL_HRTIM_TIMER_A
12563   *         @arg @ref LL_HRTIM_TIMER_B
12564   *         @arg @ref LL_HRTIM_TIMER_C
12565   *         @arg @ref LL_HRTIM_TIMER_D
12566   *         @arg @ref LL_HRTIM_TIMER_E
12567   *         @arg @ref LL_HRTIM_TIMER_F
12568   * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12569   */
12570 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12571 {
12572   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12573   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12574                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12575
12576   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
12577 }
12578
12579 /**
12580   * @brief  Enable the output 1 reset interrupt for a given timer.
12581   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_EnableIT_RST1
12582   * @param  HRTIMx High Resolution Timer instance
12583   * @param  Timer This parameter can be one of the following values:
12584   *         @arg @ref LL_HRTIM_TIMER_A
12585   *         @arg @ref LL_HRTIM_TIMER_B
12586   *         @arg @ref LL_HRTIM_TIMER_C
12587   *         @arg @ref LL_HRTIM_TIMER_D
12588   *         @arg @ref LL_HRTIM_TIMER_E
12589   *         @arg @ref LL_HRTIM_TIMER_F
12590   * @retval None
12591   */
12592 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12593 {
12594   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12595   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12596                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12597   SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12598 }
12599
12600 /**
12601   * @brief  Disable the output 1 reset interrupt for a given timer.
12602   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_DisableIT_RST1
12603   * @param  HRTIMx High Resolution Timer instance
12604   * @param  Timer This parameter can be one of the following values:
12605   *         @arg @ref LL_HRTIM_TIMER_A
12606   *         @arg @ref LL_HRTIM_TIMER_B
12607   *         @arg @ref LL_HRTIM_TIMER_C
12608   *         @arg @ref LL_HRTIM_TIMER_D
12609   *         @arg @ref LL_HRTIM_TIMER_E
12610   *         @arg @ref LL_HRTIM_TIMER_F
12611   * @retval None
12612   */
12613 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12614 {
12615   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12616   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12617                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12618   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12619 }
12620
12621 /**
12622   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
12623   * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_IsEnabledIT_RST1
12624   * @param  HRTIMx High Resolution Timer instance
12625   * @param  Timer This parameter can be one of the following values:
12626   *         @arg @ref LL_HRTIM_TIMER_A
12627   *         @arg @ref LL_HRTIM_TIMER_B
12628   *         @arg @ref LL_HRTIM_TIMER_C
12629   *         @arg @ref LL_HRTIM_TIMER_D
12630   *         @arg @ref LL_HRTIM_TIMER_E
12631   *         @arg @ref LL_HRTIM_TIMER_F
12632   * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12633   */
12634 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12635 {
12636   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12637   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12638                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12639
12640   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
12641 }
12642
12643 /**
12644   * @brief  Enable the output 2 set interrupt for a given timer.
12645   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_EnableIT_SET2
12646   * @param  HRTIMx High Resolution Timer instance
12647   * @param  Timer This parameter can be one of the following values:
12648   *         @arg @ref LL_HRTIM_TIMER_A
12649   *         @arg @ref LL_HRTIM_TIMER_B
12650   *         @arg @ref LL_HRTIM_TIMER_C
12651   *         @arg @ref LL_HRTIM_TIMER_D
12652   *         @arg @ref LL_HRTIM_TIMER_E
12653   *         @arg @ref LL_HRTIM_TIMER_F
12654   * @retval None
12655   */
12656 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12657 {
12658   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12659   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12660                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12661   SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12662 }
12663
12664 /**
12665   * @brief  Disable the output 2 set interrupt for a given timer.
12666   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_DisableIT_SET2
12667   * @param  HRTIMx High Resolution Timer instance
12668   * @param  Timer This parameter can be one of the following values:
12669   *         @arg @ref LL_HRTIM_TIMER_A
12670   *         @arg @ref LL_HRTIM_TIMER_B
12671   *         @arg @ref LL_HRTIM_TIMER_C
12672   *         @arg @ref LL_HRTIM_TIMER_D
12673   *         @arg @ref LL_HRTIM_TIMER_E
12674   *         @arg @ref LL_HRTIM_TIMER_F
12675   * @retval None
12676   */
12677 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12678 {
12679   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12680   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12681                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12682   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12683 }
12684
12685 /**
12686   * @brief  Indicate whether the output 2 set interrupt is enabled for a given timer.
12687   * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_IsEnabledIT_SET2
12688   * @param  HRTIMx High Resolution Timer instance
12689   * @param  Timer This parameter can be one of the following values:
12690   *         @arg @ref LL_HRTIM_TIMER_A
12691   *         @arg @ref LL_HRTIM_TIMER_B
12692   *         @arg @ref LL_HRTIM_TIMER_C
12693   *         @arg @ref LL_HRTIM_TIMER_D
12694   *         @arg @ref LL_HRTIM_TIMER_E
12695   *         @arg @ref LL_HRTIM_TIMER_F
12696   * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12697   */
12698 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12699 {
12700   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12701   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12702                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12703
12704   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
12705 }
12706
12707 /**
12708   * @brief  Enable the output 2 reset interrupt for a given timer.
12709   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_EnableIT_RST2
12710   * @param  HRTIMx High Resolution Timer instance
12711   * @param  Timer This parameter can be one of the following values:
12712   *         @arg @ref LL_HRTIM_TIMER_A
12713   *         @arg @ref LL_HRTIM_TIMER_B
12714   *         @arg @ref LL_HRTIM_TIMER_C
12715   *         @arg @ref LL_HRTIM_TIMER_D
12716   *         @arg @ref LL_HRTIM_TIMER_E
12717   *         @arg @ref LL_HRTIM_TIMER_F
12718   * @retval None
12719   */
12720 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12721 {
12722   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12723   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12724                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12725   SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12726 }
12727
12728 /**
12729   * @brief  Disable the output 2 reset interrupt for a given timer.
12730   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
12731   * @param  HRTIMx High Resolution Timer instance
12732   * @param  Timer This parameter can be one of the following values:
12733   *         @arg @ref LL_HRTIM_TIMER_A
12734   *         @arg @ref LL_HRTIM_TIMER_B
12735   *         @arg @ref LL_HRTIM_TIMER_C
12736   *         @arg @ref LL_HRTIM_TIMER_D
12737   *         @arg @ref LL_HRTIM_TIMER_E
12738   *         @arg @ref LL_HRTIM_TIMER_F
12739   * @retval None
12740   */
12741 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12742 {
12743   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12744   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12745                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12746   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12747 }
12748
12749 /**
12750   * @brief  Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
12751   * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
12752   * @param  HRTIMx High Resolution Timer instance
12753   * @param  Timer This parameter can be one of the following values:
12754   *         @arg @ref LL_HRTIM_TIMER_A
12755   *         @arg @ref LL_HRTIM_TIMER_B
12756   *         @arg @ref LL_HRTIM_TIMER_C
12757   *         @arg @ref LL_HRTIM_TIMER_D
12758   *         @arg @ref LL_HRTIM_TIMER_E
12759   *         @arg @ref LL_HRTIM_TIMER_F
12760   * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12761   */
12762 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12763 {
12764   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12765   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12766                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12767
12768   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
12769 }
12770
12771 /**
12772   * @brief  Enable the reset/roll-over interrupt for a given timer.
12773   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_EnableIT_RST
12774   * @param  HRTIMx High Resolution Timer instance
12775   * @param  Timer This parameter can be one of the following values:
12776   *         @arg @ref LL_HRTIM_TIMER_A
12777   *         @arg @ref LL_HRTIM_TIMER_B
12778   *         @arg @ref LL_HRTIM_TIMER_C
12779   *         @arg @ref LL_HRTIM_TIMER_D
12780   *         @arg @ref LL_HRTIM_TIMER_E
12781   *         @arg @ref LL_HRTIM_TIMER_F
12782   * @retval None
12783   */
12784 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12785 {
12786   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12787   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12788                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12789   SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12790 }
12791
12792 /**
12793   * @brief  Disable the reset/roll-over interrupt for a given timer.
12794   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_DisableIT_RST
12795   * @param  HRTIMx High Resolution Timer instance
12796   * @param  Timer This parameter can be one of the following values:
12797   *         @arg @ref LL_HRTIM_TIMER_A
12798   *         @arg @ref LL_HRTIM_TIMER_B
12799   *         @arg @ref LL_HRTIM_TIMER_C
12800   *         @arg @ref LL_HRTIM_TIMER_D
12801   *         @arg @ref LL_HRTIM_TIMER_E
12802   *         @arg @ref LL_HRTIM_TIMER_F
12803   * @retval None
12804   */
12805 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12806 {
12807   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12808   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12809                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12810   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12811 }
12812
12813 /**
12814   * @brief  Indicate whether the reset/roll-over interrupt is enabled for a given timer.
12815   * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_IsEnabledIT_RST
12816   * @param  HRTIMx High Resolution Timer instance
12817   * @param  Timer This parameter can be one of the following values:
12818   *         @arg @ref LL_HRTIM_TIMER_A
12819   *         @arg @ref LL_HRTIM_TIMER_B
12820   *         @arg @ref LL_HRTIM_TIMER_C
12821   *         @arg @ref LL_HRTIM_TIMER_D
12822   *         @arg @ref LL_HRTIM_TIMER_E
12823   *         @arg @ref LL_HRTIM_TIMER_F
12824   * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
12825   */
12826 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12827 {
12828   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12829   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12830                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12831
12832   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
12833 }
12834
12835 /**
12836   * @brief  Enable the delayed protection interrupt for a given timer.
12837   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_EnableIT_DLYPRT
12838   * @param  HRTIMx High Resolution Timer instance
12839   * @param  Timer This parameter can be one of the following values:
12840   *         @arg @ref LL_HRTIM_TIMER_A
12841   *         @arg @ref LL_HRTIM_TIMER_B
12842   *         @arg @ref LL_HRTIM_TIMER_C
12843   *         @arg @ref LL_HRTIM_TIMER_D
12844   *         @arg @ref LL_HRTIM_TIMER_E
12845   *         @arg @ref LL_HRTIM_TIMER_F
12846   * @retval None
12847   */
12848 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12849 {
12850   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12851   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12852                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12853   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12854 }
12855
12856 /**
12857   * @brief  Disable the delayed protection interrupt for a given timer.
12858   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_DisableIT_DLYPRT
12859   * @param  HRTIMx High Resolution Timer instance
12860   * @param  Timer This parameter can be one of the following values:
12861   *         @arg @ref LL_HRTIM_TIMER_A
12862   *         @arg @ref LL_HRTIM_TIMER_B
12863   *         @arg @ref LL_HRTIM_TIMER_C
12864   *         @arg @ref LL_HRTIM_TIMER_D
12865   *         @arg @ref LL_HRTIM_TIMER_E
12866   *         @arg @ref LL_HRTIM_TIMER_F
12867   * @retval None
12868   */
12869 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12870 {
12871   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12872   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12873                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12874   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12875 }
12876
12877 /**
12878   * @brief  Indicate whether the delayed protection interrupt is enabled for a given timer.
12879   * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_IsEnabledIT_DLYPRT
12880   * @param  HRTIMx High Resolution Timer instance
12881   * @param  Timer This parameter can be one of the following values:
12882   *         @arg @ref LL_HRTIM_TIMER_A
12883   *         @arg @ref LL_HRTIM_TIMER_B
12884   *         @arg @ref LL_HRTIM_TIMER_C
12885   *         @arg @ref LL_HRTIM_TIMER_D
12886   *         @arg @ref LL_HRTIM_TIMER_E
12887   *         @arg @ref LL_HRTIM_TIMER_F
12888   * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
12889   */
12890 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12891 {
12892   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12893   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12894                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12895
12896   return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
12897 }
12898
12899 /**
12900   * @}
12901   */
12902
12903 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
12904   * @{
12905   */
12906
12907 /**
12908   * @brief  Enable the synchronization input DMA request.
12909   * @rmtoll MDIER     SYNCDE            LL_HRTIM_EnableDMAReq_SYNC
12910   * @param  HRTIMx High Resolution Timer instance
12911   * @retval None
12912   */
12913 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12914 {
12915   SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12916 }
12917
12918 /**
12919   * @brief  Disable the synchronization input DMA request
12920   * @rmtoll MDIER     SYNCDE            LL_HRTIM_DisableDMAReq_SYNC
12921   * @param  HRTIMx High Resolution Timer instance
12922   * @retval None
12923   */
12924 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12925 {
12926   CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12927 }
12928
12929 /**
12930   * @brief  Indicate whether the synchronization input DMA request is enabled.
12931   * @rmtoll MDIER     SYNCDE            LL_HRTIM_IsEnabledDMAReq_SYNC
12932   * @param  HRTIMx High Resolution Timer instance
12933   * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
12934   */
12935 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
12936 {
12937   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
12938 }
12939
12940 /**
12941   * @brief  Enable the update DMA request for a given timer.
12942   * @rmtoll MDIER        MUPDDE            LL_HRTIM_EnableDMAReq_UPDATE\n
12943   *         TIMxDIER     UPDDE             LL_HRTIM_EnableDMAReq_UPDATE
12944   * @param  HRTIMx High Resolution Timer instance
12945   * @param  Timer This parameter can be one of the following values:
12946   *         @arg @ref LL_HRTIM_TIMER_MASTER
12947   *         @arg @ref LL_HRTIM_TIMER_A
12948   *         @arg @ref LL_HRTIM_TIMER_B
12949   *         @arg @ref LL_HRTIM_TIMER_C
12950   *         @arg @ref LL_HRTIM_TIMER_D
12951   *         @arg @ref LL_HRTIM_TIMER_E
12952   *         @arg @ref LL_HRTIM_TIMER_F
12953   * @retval None
12954   */
12955 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12956 {
12957   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12958   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12959                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12960   SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12961 }
12962
12963 /**
12964   * @brief  Disable the update DMA request for a given timer.
12965   * @rmtoll MDIER        MUPDDE            LL_HRTIM_DisableDMAReq_UPDATE\n
12966   *         TIMxDIER     UPDDE             LL_HRTIM_DisableDMAReq_UPDATE
12967   * @param  HRTIMx High Resolution Timer instance
12968   * @param  Timer This parameter can be one of the following values:
12969   *         @arg @ref LL_HRTIM_TIMER_MASTER
12970   *         @arg @ref LL_HRTIM_TIMER_A
12971   *         @arg @ref LL_HRTIM_TIMER_B
12972   *         @arg @ref LL_HRTIM_TIMER_C
12973   *         @arg @ref LL_HRTIM_TIMER_D
12974   *         @arg @ref LL_HRTIM_TIMER_E
12975   *         @arg @ref LL_HRTIM_TIMER_F
12976   * @retval None
12977   */
12978 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12979 {
12980   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12981   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12982                                                     REG_OFFSET_TAB_TIMER[iTimer]));
12983   CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12984 }
12985
12986 /**
12987   * @brief  Indicate whether the update DMA request is enabled for a given timer.
12988   * @rmtoll MDIER        MUPDDE            LL_HRTIM_IsEnabledDMAReq_UPDATE\n
12989   *         TIMxDIER     UPDDE             LL_HRTIM_IsEnabledDMAReq_UPDATE
12990   * @param  HRTIMx High Resolution Timer instance
12991   * @param  Timer This parameter can be one of the following values:
12992   *         @arg @ref LL_HRTIM_TIMER_MASTER
12993   *         @arg @ref LL_HRTIM_TIMER_A
12994   *         @arg @ref LL_HRTIM_TIMER_B
12995   *         @arg @ref LL_HRTIM_TIMER_C
12996   *         @arg @ref LL_HRTIM_TIMER_D
12997   *         @arg @ref LL_HRTIM_TIMER_E
12998   *         @arg @ref LL_HRTIM_TIMER_F
12999   * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13000   */
13001 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13002 {
13003   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13004   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13005                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13006
13007   return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
13008 }
13009
13010 /**
13011   * @brief  Enable the repetition DMA request for a given timer.
13012   * @rmtoll MDIER        MREPDE            LL_HRTIM_EnableDMAReq_REP\n
13013   *         TIMxDIER     REPDE             LL_HRTIM_EnableDMAReq_REP
13014   * @param  HRTIMx High Resolution Timer instance
13015   * @param  Timer This parameter can be one of the following values:
13016   *         @arg @ref LL_HRTIM_TIMER_MASTER
13017   *         @arg @ref LL_HRTIM_TIMER_A
13018   *         @arg @ref LL_HRTIM_TIMER_B
13019   *         @arg @ref LL_HRTIM_TIMER_C
13020   *         @arg @ref LL_HRTIM_TIMER_D
13021   *         @arg @ref LL_HRTIM_TIMER_E
13022   *         @arg @ref LL_HRTIM_TIMER_F
13023   * @retval None
13024   */
13025 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13026 {
13027   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13028   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13029                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13030   SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
13031 }
13032
13033 /**
13034   * @brief  Disable the repetition DMA request for a given timer.
13035   * @rmtoll MDIER        MREPDE            LL_HRTIM_DisableDMAReq_REP\n
13036   *         TIMxDIER     REPDE             LL_HRTIM_DisableDMAReq_REP
13037   * @param  HRTIMx High Resolution Timer instance
13038   * @param  Timer This parameter can be one of the following values:
13039   *         @arg @ref LL_HRTIM_TIMER_MASTER
13040   *         @arg @ref LL_HRTIM_TIMER_A
13041   *         @arg @ref LL_HRTIM_TIMER_B
13042   *         @arg @ref LL_HRTIM_TIMER_C
13043   *         @arg @ref LL_HRTIM_TIMER_D
13044   *         @arg @ref LL_HRTIM_TIMER_E
13045   *         @arg @ref LL_HRTIM_TIMER_F
13046   * @retval None
13047   */
13048 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13049 {
13050   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13051   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13052                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13053   CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
13054 }
13055
13056 /**
13057   * @brief  Indicate whether the repetition DMA request is enabled for a given timer.
13058   * @rmtoll MDIER        MREPDE            LL_HRTIM_IsEnabledDMAReq_REP\n
13059   *         TIMxDIER     REPDE             LL_HRTIM_IsEnabledDMAReq_REP
13060   * @param  HRTIMx High Resolution Timer instance
13061   * @param  Timer This parameter can be one of the following values:
13062   *         @arg @ref LL_HRTIM_TIMER_MASTER
13063   *         @arg @ref LL_HRTIM_TIMER_A
13064   *         @arg @ref LL_HRTIM_TIMER_B
13065   *         @arg @ref LL_HRTIM_TIMER_C
13066   *         @arg @ref LL_HRTIM_TIMER_D
13067   *         @arg @ref LL_HRTIM_TIMER_E
13068   *         @arg @ref LL_HRTIM_TIMER_F
13069   * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13070   */
13071 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13072 {
13073   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13074   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13075                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13076
13077   return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
13078 }
13079
13080 /**
13081   * @brief  Enable the compare 1 DMA request for a given timer.
13082   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_EnableDMAReq_CMP1\n
13083   *         TIMxDIER     CMP1DE             LL_HRTIM_EnableDMAReq_CMP1
13084   * @param  HRTIMx High Resolution Timer instance
13085   * @param  Timer This parameter can be one of the following values:
13086   *         @arg @ref LL_HRTIM_TIMER_MASTER
13087   *         @arg @ref LL_HRTIM_TIMER_A
13088   *         @arg @ref LL_HRTIM_TIMER_B
13089   *         @arg @ref LL_HRTIM_TIMER_C
13090   *         @arg @ref LL_HRTIM_TIMER_D
13091   *         @arg @ref LL_HRTIM_TIMER_E
13092   *         @arg @ref LL_HRTIM_TIMER_F
13093   * @retval None
13094   */
13095 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13096 {
13097   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13098   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13099                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13100   SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13101 }
13102
13103 /**
13104   * @brief  Disable the compare 1 DMA request for a given timer.
13105   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_DisableDMAReq_CMP1\n
13106   *         TIMxDIER     CMP1DE             LL_HRTIM_DisableDMAReq_CMP1
13107   * @param  HRTIMx High Resolution Timer instance
13108   * @param  Timer This parameter can be one of the following values:
13109   *         @arg @ref LL_HRTIM_TIMER_MASTER
13110   *         @arg @ref LL_HRTIM_TIMER_A
13111   *         @arg @ref LL_HRTIM_TIMER_B
13112   *         @arg @ref LL_HRTIM_TIMER_C
13113   *         @arg @ref LL_HRTIM_TIMER_D
13114   *         @arg @ref LL_HRTIM_TIMER_E
13115   *         @arg @ref LL_HRTIM_TIMER_F
13116   * @retval None
13117   */
13118 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13119 {
13120   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13121   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13122                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13123   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13124 }
13125
13126 /**
13127   * @brief  Indicate whether the compare 1 DMA request is enabled for a given timer.
13128   * @rmtoll MDIER        MCMP1DE            LL_HRTIM_IsEnabledDMAReq_CMP1\n
13129   *         TIMxDIER     CMP1DE             LL_HRTIM_IsEnabledDMAReq_CMP1
13130   * @param  HRTIMx High Resolution Timer instance
13131   * @param  Timer This parameter can be one of the following values:
13132   *         @arg @ref LL_HRTIM_TIMER_MASTER
13133   *         @arg @ref LL_HRTIM_TIMER_A
13134   *         @arg @ref LL_HRTIM_TIMER_B
13135   *         @arg @ref LL_HRTIM_TIMER_C
13136   *         @arg @ref LL_HRTIM_TIMER_D
13137   *         @arg @ref LL_HRTIM_TIMER_E
13138   *         @arg @ref LL_HRTIM_TIMER_F
13139   * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13140   */
13141 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13142 {
13143   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13144   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13145                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13146
13147   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
13148 }
13149
13150 /**
13151   * @brief  Enable the compare 2 DMA request for a given timer.
13152   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_EnableDMAReq_CMP2\n
13153   *         TIMxDIER     CMP2DE             LL_HRTIM_EnableDMAReq_CMP2
13154   * @param  HRTIMx High Resolution Timer instance
13155   * @param  Timer This parameter can be one of the following values:
13156   *         @arg @ref LL_HRTIM_TIMER_MASTER
13157   *         @arg @ref LL_HRTIM_TIMER_A
13158   *         @arg @ref LL_HRTIM_TIMER_B
13159   *         @arg @ref LL_HRTIM_TIMER_C
13160   *         @arg @ref LL_HRTIM_TIMER_D
13161   *         @arg @ref LL_HRTIM_TIMER_E
13162   *         @arg @ref LL_HRTIM_TIMER_F
13163   * @retval None
13164   */
13165 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13166 {
13167   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13168   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13169                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13170   SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13171 }
13172
13173 /**
13174   * @brief  Disable the compare 2 DMA request for a given timer.
13175   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_DisableDMAReq_CMP2\n
13176   *         TIMxDIER     CMP2DE             LL_HRTIM_DisableDMAReq_CMP2
13177   * @param  HRTIMx High Resolution Timer instance
13178   * @param  Timer This parameter can be one of the following values:
13179   *         @arg @ref LL_HRTIM_TIMER_MASTER
13180   *         @arg @ref LL_HRTIM_TIMER_A
13181   *         @arg @ref LL_HRTIM_TIMER_B
13182   *         @arg @ref LL_HRTIM_TIMER_C
13183   *         @arg @ref LL_HRTIM_TIMER_D
13184   *         @arg @ref LL_HRTIM_TIMER_E
13185   *         @arg @ref LL_HRTIM_TIMER_F
13186   * @retval None
13187   */
13188 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13189 {
13190   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13191   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13192                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13193   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13194 }
13195
13196 /**
13197   * @brief  Indicate whether the compare 2 DMA request is enabled for a given timer.
13198   * @rmtoll MDIER        MCMP2DE            LL_HRTIM_IsEnabledDMAReq_CMP2\n
13199   *         TIMxDIER     CMP2DE             LL_HRTIM_IsEnabledDMAReq_CMP2
13200   * @param  HRTIMx High Resolution Timer instance
13201   * @param  Timer This parameter can be one of the following values:
13202   *         @arg @ref LL_HRTIM_TIMER_MASTER
13203   *         @arg @ref LL_HRTIM_TIMER_A
13204   *         @arg @ref LL_HRTIM_TIMER_B
13205   *         @arg @ref LL_HRTIM_TIMER_C
13206   *         @arg @ref LL_HRTIM_TIMER_D
13207   *         @arg @ref LL_HRTIM_TIMER_E
13208   *         @arg @ref LL_HRTIM_TIMER_F
13209   * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13210   */
13211 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13212 {
13213   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13214   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13215                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13216
13217   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
13218 }
13219
13220 /**
13221   * @brief  Enable the compare 3 DMA request for a given timer.
13222   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_EnableDMAReq_CMP3\n
13223   *         TIMxDIER     CMP3DE             LL_HRTIM_EnableDMAReq_CMP3
13224   * @param  HRTIMx High Resolution Timer instance
13225   * @param  Timer This parameter can be one of the following values:
13226   *         @arg @ref LL_HRTIM_TIMER_MASTER
13227   *         @arg @ref LL_HRTIM_TIMER_A
13228   *         @arg @ref LL_HRTIM_TIMER_B
13229   *         @arg @ref LL_HRTIM_TIMER_C
13230   *         @arg @ref LL_HRTIM_TIMER_D
13231   *         @arg @ref LL_HRTIM_TIMER_E
13232   *         @arg @ref LL_HRTIM_TIMER_F
13233   * @retval None
13234   */
13235 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13236 {
13237   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13238   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13239                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13240   SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13241 }
13242
13243 /**
13244   * @brief  Disable the compare 3 DMA request for a given timer.
13245   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_DisableDMAReq_CMP3\n
13246   *         TIMxDIER     CMP3DE             LL_HRTIM_DisableDMAReq_CMP3
13247   * @param  HRTIMx High Resolution Timer instance
13248   * @param  Timer This parameter can be one of the following values:
13249   *         @arg @ref LL_HRTIM_TIMER_MASTER
13250   *         @arg @ref LL_HRTIM_TIMER_A
13251   *         @arg @ref LL_HRTIM_TIMER_B
13252   *         @arg @ref LL_HRTIM_TIMER_C
13253   *         @arg @ref LL_HRTIM_TIMER_D
13254   *         @arg @ref LL_HRTIM_TIMER_E
13255   *         @arg @ref LL_HRTIM_TIMER_F
13256   * @retval None
13257   */
13258 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13259 {
13260   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13261   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13262                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13263   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13264 }
13265
13266 /**
13267   * @brief  Indicate whether the compare 3 DMA request is enabled for a given timer.
13268   * @rmtoll MDIER        MCMP3DE            LL_HRTIM_IsEnabledDMAReq_CMP3\n
13269   *         TIMxDIER     CMP3DE             LL_HRTIM_IsEnabledDMAReq_CMP3
13270   * @param  HRTIMx High Resolution Timer instance
13271   * @param  Timer This parameter can be one of the following values:
13272   *         @arg @ref LL_HRTIM_TIMER_MASTER
13273   *         @arg @ref LL_HRTIM_TIMER_A
13274   *         @arg @ref LL_HRTIM_TIMER_B
13275   *         @arg @ref LL_HRTIM_TIMER_C
13276   *         @arg @ref LL_HRTIM_TIMER_D
13277   *         @arg @ref LL_HRTIM_TIMER_E
13278   *         @arg @ref LL_HRTIM_TIMER_F
13279   * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13280   */
13281 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13282 {
13283   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13284   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13285                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13286
13287   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
13288 }
13289
13290 /**
13291   * @brief  Enable the compare 4 DMA request for a given timer.
13292   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_EnableDMAReq_CMP4\n
13293   *         TIMxDIER     CMP4DE             LL_HRTIM_EnableDMAReq_CMP4
13294   * @param  HRTIMx High Resolution Timer instance
13295   * @param  Timer This parameter can be one of the following values:
13296   *         @arg @ref LL_HRTIM_TIMER_MASTER
13297   *         @arg @ref LL_HRTIM_TIMER_A
13298   *         @arg @ref LL_HRTIM_TIMER_B
13299   *         @arg @ref LL_HRTIM_TIMER_C
13300   *         @arg @ref LL_HRTIM_TIMER_D
13301   *         @arg @ref LL_HRTIM_TIMER_E
13302   *         @arg @ref LL_HRTIM_TIMER_F
13303   * @retval None
13304   */
13305 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13306 {
13307   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13308   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13309                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13310   SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13311 }
13312
13313 /**
13314   * @brief  Disable the compare 4 DMA request for a given timer.
13315   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_DisableDMAReq_CMP4\n
13316   *         TIMxDIER     CMP4DE             LL_HRTIM_DisableDMAReq_CMP4
13317   * @param  HRTIMx High Resolution Timer instance
13318   * @param  Timer This parameter can be one of the following values:
13319   *         @arg @ref LL_HRTIM_TIMER_MASTER
13320   *         @arg @ref LL_HRTIM_TIMER_A
13321   *         @arg @ref LL_HRTIM_TIMER_B
13322   *         @arg @ref LL_HRTIM_TIMER_C
13323   *         @arg @ref LL_HRTIM_TIMER_D
13324   *         @arg @ref LL_HRTIM_TIMER_E
13325   *         @arg @ref LL_HRTIM_TIMER_F
13326   * @retval None
13327   */
13328 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13329 {
13330   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13331   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13332                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13333   CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13334 }
13335
13336 /**
13337   * @brief  Indicate whether the compare 4 DMA request is enabled for a given timer.
13338   * @rmtoll MDIER        MCMP4DE            LL_HRTIM_IsEnabledDMAReq_CMP4\n
13339   *         TIMxDIER     CMP4DE             LL_HRTIM_IsEnabledDMAReq_CMP4
13340   * @param  HRTIMx High Resolution Timer instance
13341   * @param  Timer This parameter can be one of the following values:
13342   *         @arg @ref LL_HRTIM_TIMER_MASTER
13343   *         @arg @ref LL_HRTIM_TIMER_A
13344   *         @arg @ref LL_HRTIM_TIMER_B
13345   *         @arg @ref LL_HRTIM_TIMER_C
13346   *         @arg @ref LL_HRTIM_TIMER_D
13347   *         @arg @ref LL_HRTIM_TIMER_E
13348   *         @arg @ref LL_HRTIM_TIMER_F
13349   * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13350   */
13351 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13352 {
13353   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13354   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13355                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13356
13357   return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
13358 }
13359
13360 /**
13361   * @brief  Enable the capture 1 DMA request for a given timer.
13362   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_EnableDMAReq_CPT1
13363   * @param  HRTIMx High Resolution Timer instance
13364   * @param  Timer This parameter can be one of the following values:
13365   *         @arg @ref LL_HRTIM_TIMER_A
13366   *         @arg @ref LL_HRTIM_TIMER_B
13367   *         @arg @ref LL_HRTIM_TIMER_C
13368   *         @arg @ref LL_HRTIM_TIMER_D
13369   *         @arg @ref LL_HRTIM_TIMER_E
13370   *         @arg @ref LL_HRTIM_TIMER_F
13371   * @retval None
13372   */
13373 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13374 {
13375   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13376   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13377                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13378   SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13379 }
13380
13381 /**
13382   * @brief  Disable the capture 1 DMA request for a given timer.
13383   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_DisableDMAReq_CPT1
13384   * @param  HRTIMx High Resolution Timer instance
13385   * @param  Timer This parameter can be one of the following values:
13386   *         @arg @ref LL_HRTIM_TIMER_A
13387   *         @arg @ref LL_HRTIM_TIMER_B
13388   *         @arg @ref LL_HRTIM_TIMER_C
13389   *         @arg @ref LL_HRTIM_TIMER_D
13390   *         @arg @ref LL_HRTIM_TIMER_E
13391   *         @arg @ref LL_HRTIM_TIMER_F
13392   * @retval None
13393   */
13394 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13395 {
13396   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13397   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13398                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13399   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13400 }
13401
13402 /**
13403   * @brief  Indicate whether the capture 1 DMA request is enabled for a given timer.
13404   * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_IsEnabledDMAReq_CPT1
13405   * @param  HRTIMx High Resolution Timer instance
13406   * @param  Timer This parameter can be one of the following values:
13407   *         @arg @ref LL_HRTIM_TIMER_A
13408   *         @arg @ref LL_HRTIM_TIMER_B
13409   *         @arg @ref LL_HRTIM_TIMER_C
13410   *         @arg @ref LL_HRTIM_TIMER_D
13411   *         @arg @ref LL_HRTIM_TIMER_E
13412   *         @arg @ref LL_HRTIM_TIMER_F
13413   * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
13414   */
13415 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13416 {
13417   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13418   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13419                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13420
13421   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
13422 }
13423
13424 /**
13425   * @brief  Enable the capture 2 DMA request for a given timer.
13426   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_EnableDMAReq_CPT2
13427   * @param  HRTIMx High Resolution Timer instance
13428   * @param  Timer This parameter can be one of the following values:
13429   *         @arg @ref LL_HRTIM_TIMER_A
13430   *         @arg @ref LL_HRTIM_TIMER_B
13431   *         @arg @ref LL_HRTIM_TIMER_C
13432   *         @arg @ref LL_HRTIM_TIMER_D
13433   *         @arg @ref LL_HRTIM_TIMER_E
13434   *         @arg @ref LL_HRTIM_TIMER_F
13435   * @retval None
13436   */
13437 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13438 {
13439   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13440   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13441                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13442   SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13443 }
13444
13445 /**
13446   * @brief  Disable the capture 2 DMA request for a given timer.
13447   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_DisableDMAReq_CPT2
13448   * @param  HRTIMx High Resolution Timer instance
13449   * @param  Timer This parameter can be one of the following values:
13450   *         @arg @ref LL_HRTIM_TIMER_A
13451   *         @arg @ref LL_HRTIM_TIMER_B
13452   *         @arg @ref LL_HRTIM_TIMER_C
13453   *         @arg @ref LL_HRTIM_TIMER_D
13454   *         @arg @ref LL_HRTIM_TIMER_E
13455   *         @arg @ref LL_HRTIM_TIMER_F
13456   * @retval None
13457   */
13458 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13459 {
13460   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13461   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13462                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13463   CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13464 }
13465
13466 /**
13467   * @brief  Indicate whether the capture 2 DMA request is enabled for a given timer.
13468   * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_IsEnabledDMAReq_CPT2
13469   * @param  HRTIMx High Resolution Timer instance
13470   * @param  Timer This parameter can be one of the following values:
13471   *         @arg @ref LL_HRTIM_TIMER_A
13472   *         @arg @ref LL_HRTIM_TIMER_B
13473   *         @arg @ref LL_HRTIM_TIMER_C
13474   *         @arg @ref LL_HRTIM_TIMER_D
13475   *         @arg @ref LL_HRTIM_TIMER_E
13476   *         @arg @ref LL_HRTIM_TIMER_F
13477   * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
13478   */
13479 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13480 {
13481   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13482   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13483                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13484
13485   return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
13486 }
13487
13488 /**
13489   * @brief  Enable the output 1 set  DMA request for a given timer.
13490   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_EnableDMAReq_SET1
13491   * @param  HRTIMx High Resolution Timer instance
13492   * @param  Timer This parameter can be one of the following values:
13493   *         @arg @ref LL_HRTIM_TIMER_A
13494   *         @arg @ref LL_HRTIM_TIMER_B
13495   *         @arg @ref LL_HRTIM_TIMER_C
13496   *         @arg @ref LL_HRTIM_TIMER_D
13497   *         @arg @ref LL_HRTIM_TIMER_E
13498   *         @arg @ref LL_HRTIM_TIMER_F
13499   * @retval None
13500   */
13501 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13502 {
13503   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13504   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13505                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13506   SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13507 }
13508
13509 /**
13510   * @brief  Disable the output 1 set  DMA request for a given timer.
13511   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_DisableDMAReq_SET1
13512   * @param  HRTIMx High Resolution Timer instance
13513   * @param  Timer This parameter can be one of the following values:
13514   *         @arg @ref LL_HRTIM_TIMER_A
13515   *         @arg @ref LL_HRTIM_TIMER_B
13516   *         @arg @ref LL_HRTIM_TIMER_C
13517   *         @arg @ref LL_HRTIM_TIMER_D
13518   *         @arg @ref LL_HRTIM_TIMER_E
13519   *         @arg @ref LL_HRTIM_TIMER_F
13520   * @retval None
13521   */
13522 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13523 {
13524   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13525   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13526                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13527   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13528 }
13529
13530 /**
13531   * @brief  Indicate whether the output 1 set  DMA request is enabled for a given timer.
13532   * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_IsEnabledDMAReq_SET1
13533   * @param  HRTIMx High Resolution Timer instance
13534   * @param  Timer This parameter can be one of the following values:
13535   *         @arg @ref LL_HRTIM_TIMER_A
13536   *         @arg @ref LL_HRTIM_TIMER_B
13537   *         @arg @ref LL_HRTIM_TIMER_C
13538   *         @arg @ref LL_HRTIM_TIMER_D
13539   *         @arg @ref LL_HRTIM_TIMER_E
13540   *         @arg @ref LL_HRTIM_TIMER_F
13541   * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13542   */
13543 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13544 {
13545   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13546   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13547                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13548
13549   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
13550 }
13551
13552 /**
13553   * @brief  Enable the output 1 reset  DMA request for a given timer.
13554   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_EnableDMAReq_RST1
13555   * @param  HRTIMx High Resolution Timer instance
13556   * @param  Timer This parameter can be one of the following values:
13557   *         @arg @ref LL_HRTIM_TIMER_A
13558   *         @arg @ref LL_HRTIM_TIMER_B
13559   *         @arg @ref LL_HRTIM_TIMER_C
13560   *         @arg @ref LL_HRTIM_TIMER_D
13561   *         @arg @ref LL_HRTIM_TIMER_E
13562   *         @arg @ref LL_HRTIM_TIMER_F
13563   * @retval None
13564   */
13565 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13566 {
13567   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13568   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13569                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13570   SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13571 }
13572
13573 /**
13574   * @brief  Disable the output 1 reset  DMA request for a given timer.
13575   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_DisableDMAReq_RST1
13576   * @param  HRTIMx High Resolution Timer instance
13577   * @param  Timer This parameter can be one of the following values:
13578   *         @arg @ref LL_HRTIM_TIMER_A
13579   *         @arg @ref LL_HRTIM_TIMER_B
13580   *         @arg @ref LL_HRTIM_TIMER_C
13581   *         @arg @ref LL_HRTIM_TIMER_D
13582   *         @arg @ref LL_HRTIM_TIMER_E
13583   *         @arg @ref LL_HRTIM_TIMER_F
13584   * @retval None
13585   */
13586 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13587 {
13588   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13589   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13590                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13591   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13592 }
13593
13594 /**
13595   * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
13596   * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_IsEnabledDMAReq_RST1
13597   * @param  HRTIMx High Resolution Timer instance
13598   * @param  Timer This parameter can be one of the following values:
13599   *         @arg @ref LL_HRTIM_TIMER_A
13600   *         @arg @ref LL_HRTIM_TIMER_B
13601   *         @arg @ref LL_HRTIM_TIMER_C
13602   *         @arg @ref LL_HRTIM_TIMER_D
13603   *         @arg @ref LL_HRTIM_TIMER_E
13604   *         @arg @ref LL_HRTIM_TIMER_F
13605   * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13606   */
13607 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13608 {
13609   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13610   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13611                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13612
13613   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
13614 }
13615
13616 /**
13617   * @brief  Enable the output 2 set  DMA request for a given timer.
13618   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_EnableDMAReq_SET2
13619   * @param  HRTIMx High Resolution Timer instance
13620   * @param  Timer This parameter can be one of the following values:
13621   *         @arg @ref LL_HRTIM_TIMER_A
13622   *         @arg @ref LL_HRTIM_TIMER_B
13623   *         @arg @ref LL_HRTIM_TIMER_C
13624   *         @arg @ref LL_HRTIM_TIMER_D
13625   *         @arg @ref LL_HRTIM_TIMER_E
13626   *         @arg @ref LL_HRTIM_TIMER_F
13627   * @retval None
13628   */
13629 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13630 {
13631   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13632   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13633                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13634   SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13635 }
13636
13637 /**
13638   * @brief  Disable the output 2 set  DMA request for a given timer.
13639   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_DisableDMAReq_SET2
13640   * @param  HRTIMx High Resolution Timer instance
13641   * @param  Timer This parameter can be one of the following values:
13642   *         @arg @ref LL_HRTIM_TIMER_A
13643   *         @arg @ref LL_HRTIM_TIMER_B
13644   *         @arg @ref LL_HRTIM_TIMER_C
13645   *         @arg @ref LL_HRTIM_TIMER_D
13646   *         @arg @ref LL_HRTIM_TIMER_E
13647   *         @arg @ref LL_HRTIM_TIMER_F
13648   * @retval None
13649   */
13650 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13651 {
13652   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13653   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13654                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13655   CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13656 }
13657
13658 /**
13659   * @brief  Indicate whether the output 2 set  DMA request is enabled for a given timer.
13660   * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_IsEnabledDMAReq_SET2
13661   * @param  HRTIMx High Resolution Timer instance
13662   * @param  Timer This parameter can be one of the following values:
13663   *         @arg @ref LL_HRTIM_TIMER_A
13664   *         @arg @ref LL_HRTIM_TIMER_B
13665   *         @arg @ref LL_HRTIM_TIMER_C
13666   *         @arg @ref LL_HRTIM_TIMER_D
13667   *         @arg @ref LL_HRTIM_TIMER_E
13668   *         @arg @ref LL_HRTIM_TIMER_F
13669   * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13670   */
13671 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13672 {
13673   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13674   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13675                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13676
13677   return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
13678 }
13679
13680 /**
13681   * @brief  Enable the output 2 reset  DMA request for a given timer.
13682   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_EnableDMAReq_RST2
13683   * @param  HRTIMx High Resolution Timer instance
13684   * @param  Timer This parameter can be one of the following values:
13685   *         @arg @ref LL_HRTIM_TIMER_A
13686   *         @arg @ref LL_HRTIM_TIMER_B
13687   *         @arg @ref LL_HRTIM_TIMER_C
13688   *         @arg @ref LL_HRTIM_TIMER_D
13689   *         @arg @ref LL_HRTIM_TIMER_E
13690   *         @arg @ref LL_HRTIM_TIMER_F
13691   * @retval None
13692   */
13693 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13694 {
13695   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13696   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13697                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13698   SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13699 }
13700
13701 /**
13702   * @brief  Disable the output 2 reset  DMA request for a given timer.
13703   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_DisableDMAReq_RST2
13704   * @param  HRTIMx High Resolution Timer instance
13705   * @param  Timer This parameter can be one of the following values:
13706   *         @arg @ref LL_HRTIM_TIMER_A
13707   *         @arg @ref LL_HRTIM_TIMER_B
13708   *         @arg @ref LL_HRTIM_TIMER_C
13709   *         @arg @ref LL_HRTIM_TIMER_D
13710   *         @arg @ref LL_HRTIM_TIMER_E
13711   *         @arg @ref LL_HRTIM_TIMER_F
13712   * @retval None
13713   */
13714 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13715 {
13716   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13717   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13718                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13719   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13720 }
13721
13722 /**
13723   * @brief  Indicate whether the output 2 reset  DMA request is enabled for a given timer.
13724   * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_IsEnabledDMAReq_RST2
13725   * @param  HRTIMx High Resolution Timer instance
13726   * @param  Timer This parameter can be one of the following values:
13727   *         @arg @ref LL_HRTIM_TIMER_A
13728   *         @arg @ref LL_HRTIM_TIMER_B
13729   *         @arg @ref LL_HRTIM_TIMER_C
13730   *         @arg @ref LL_HRTIM_TIMER_D
13731   *         @arg @ref LL_HRTIM_TIMER_E
13732   *         @arg @ref LL_HRTIM_TIMER_F
13733   * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13734   */
13735 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13736 {
13737   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13738   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13739                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13740
13741   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
13742 }
13743
13744 /**
13745   * @brief  Enable the reset/roll-over DMA request for a given timer.
13746   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_EnableDMAReq_RST
13747   * @param  HRTIMx High Resolution Timer instance
13748   * @param  Timer This parameter can be one of the following values:
13749   *         @arg @ref LL_HRTIM_TIMER_A
13750   *         @arg @ref LL_HRTIM_TIMER_B
13751   *         @arg @ref LL_HRTIM_TIMER_C
13752   *         @arg @ref LL_HRTIM_TIMER_D
13753   *         @arg @ref LL_HRTIM_TIMER_E
13754   *         @arg @ref LL_HRTIM_TIMER_F
13755   * @retval None
13756   */
13757 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13758 {
13759   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13760   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13761                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13762   SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13763 }
13764
13765 /**
13766   * @brief  Disable the reset/roll-over DMA request for a given timer.
13767   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_DisableDMAReq_RST
13768   * @param  HRTIMx High Resolution Timer instance
13769   * @param  Timer This parameter can be one of the following values:
13770   *         @arg @ref LL_HRTIM_TIMER_A
13771   *         @arg @ref LL_HRTIM_TIMER_B
13772   *         @arg @ref LL_HRTIM_TIMER_C
13773   *         @arg @ref LL_HRTIM_TIMER_D
13774   *         @arg @ref LL_HRTIM_TIMER_E
13775   *         @arg @ref LL_HRTIM_TIMER_F
13776   * @retval None
13777   */
13778 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13779 {
13780   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13781   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13782                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13783   CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13784 }
13785
13786 /**
13787   * @brief  Indicate whether the reset/roll-over DMA request is enabled for a given timer.
13788   * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_IsEnabledDMAReq_RST
13789   * @param  HRTIMx High Resolution Timer instance
13790   * @param  Timer This parameter can be one of the following values:
13791   *         @arg @ref LL_HRTIM_TIMER_A
13792   *         @arg @ref LL_HRTIM_TIMER_B
13793   *         @arg @ref LL_HRTIM_TIMER_C
13794   *         @arg @ref LL_HRTIM_TIMER_D
13795   *         @arg @ref LL_HRTIM_TIMER_E
13796   *         @arg @ref LL_HRTIM_TIMER_F
13797   * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
13798   */
13799 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13800 {
13801   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13802   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13803                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13804
13805   return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
13806 }
13807
13808 /**
13809   * @brief  Enable the delayed protection DMA request for a given timer.
13810   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_EnableDMAReq_DLYPRT
13811   * @param  HRTIMx High Resolution Timer instance
13812   * @param  Timer This parameter can be one of the following values:
13813   *         @arg @ref LL_HRTIM_TIMER_A
13814   *         @arg @ref LL_HRTIM_TIMER_B
13815   *         @arg @ref LL_HRTIM_TIMER_C
13816   *         @arg @ref LL_HRTIM_TIMER_D
13817   *         @arg @ref LL_HRTIM_TIMER_E
13818   *         @arg @ref LL_HRTIM_TIMER_F
13819   * @retval None
13820   */
13821 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13822 {
13823   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13824   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13825                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13826   SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13827 }
13828
13829 /**
13830   * @brief  Disable the delayed protection DMA request for a given timer.
13831   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_DisableDMAReq_DLYPRT
13832   * @param  HRTIMx High Resolution Timer instance
13833   * @param  Timer This parameter can be one of the following values:
13834   *         @arg @ref LL_HRTIM_TIMER_A
13835   *         @arg @ref LL_HRTIM_TIMER_B
13836   *         @arg @ref LL_HRTIM_TIMER_C
13837   *         @arg @ref LL_HRTIM_TIMER_D
13838   *         @arg @ref LL_HRTIM_TIMER_E
13839   *         @arg @ref LL_HRTIM_TIMER_F
13840   * @retval None
13841   */
13842 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13843 {
13844   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13845   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13846                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13847   CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13848 }
13849
13850 /**
13851   * @brief  Indicate whether the delayed protection DMA request is enabled for a given timer.
13852   * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_IsEnabledDMAReq_DLYPRT
13853   * @param  HRTIMx High Resolution Timer instance
13854   * @param  Timer This parameter can be one of the following values:
13855   *         @arg @ref LL_HRTIM_TIMER_A
13856   *         @arg @ref LL_HRTIM_TIMER_B
13857   *         @arg @ref LL_HRTIM_TIMER_C
13858   *         @arg @ref LL_HRTIM_TIMER_D
13859   *         @arg @ref LL_HRTIM_TIMER_E
13860   *         @arg @ref LL_HRTIM_TIMER_F
13861   * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
13862   */
13863 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13864 {
13865   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13866   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13867                                                     REG_OFFSET_TAB_TIMER[iTimer]));
13868
13869   return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
13870 }
13871
13872 /**
13873   * @}
13874   */
13875
13876 #if defined(USE_FULL_LL_DRIVER)
13877 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
13878   * @{
13879   */
13880 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
13881 /**
13882   * @}
13883   */
13884 #endif /* USE_FULL_LL_DRIVER */
13885
13886 /**
13887   * @}
13888   */
13889
13890 /**
13891   * @}
13892   */
13893
13894 #endif /* HRTIM1 */
13895
13896 /**
13897   * @}
13898   */
13899
13900 #ifdef __cplusplus
13901 }
13902 #endif
13903
13904 #endif /* STM32G4xx_LL_HRTIM_H */
13905
13906
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_i2c.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_i2c.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_i2c.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
00034
00035 /** @defgroup I2C_LL I2C
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup I2C_LL_Private_Macros
00044   * @{
00045   */
00046
00047 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00048                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00049                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00050                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00051
00052 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00053                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00054
00055 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00056
00057 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00058
00059 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00060                                                  ((__VALUE__) == LL_I2C_NACK))
00061
00062 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00063                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00064 /**
00065   * @}
00066   */
00067
00068 /* Private function prototypes -----------------------------------------------*/
00069
00070 /* Exported functions --------------------------------------------------------*/
00071 /** @addtogroup I2C_LL_Exported_Functions
00072   * @{
00073   */
00074
00075 /** @addtogroup I2C_LL_EF_Init
00076   * @{
00077   */
00078
00079 /**
00080   * @brief  De-initialize the I2C registers to their default reset values.
00081   * @param  I2Cx I2C Instance.
00082   * @retval An ErrorStatus enumeration value:
00083   *          - SUCCESS: I2C registers are de-initialized
00084   *          - ERROR: I2C registers are not de-initialized
00085   */
00086 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
00087 {
00088   ErrorStatus status = SUCCESS;
00089
00090   /* Check the I2C Instance I2Cx */
00091   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00092
00093   if (I2Cx == I2C1)
00094   {
00095     /* Force reset of I2C clock */
00096     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00097
00098     /* Release reset of I2C clock */
00099     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00100   }
00101   else if (I2Cx == I2C2)
00102   {
00103     /* Force reset of I2C clock */
00104     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00105
00106     /* Release reset of I2C clock */
00107     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00108
00109   }
00110   else if (I2Cx == I2C3)
00111   {
00112     /* Force reset of I2C clock */
00113     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00114
00115     /* Release reset of I2C clock */
00116     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00117   }
00118 #if defined(I2C4)
00119   else if (I2Cx == I2C4)
00120   {
00121     /* Force reset of I2C clock */
00122     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C4);
00123
00124     /* Release reset of I2C clock */
00125     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
00126   }
00127 #endif /* I2C4 */
00128   else
00129   {
00130     status = ERROR;
00131   }
00132
00133   return status;
00134 }
00135
00136 /**
00137   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00138   * @param  I2Cx I2C Instance.
00139   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00140   * @retval An ErrorStatus enumeration value:
00141   *          - SUCCESS: I2C registers are initialized
00142   *          - ERROR: Not applicable
00143   */
00144 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
00145 {
00146   /* Check the I2C Instance I2Cx */
00147   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00148
00149   /* Check the I2C parameters from I2C_InitStruct */
00150   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00151   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00152   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00153   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00154   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00155   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00156
00157   /* Disable the selected I2Cx Peripheral */
00158   LL_I2C_Disable(I2Cx);
00159
00160   /*---------------------------- I2Cx CR1 Configuration ------------------------
00161    * Configure the analog and digital noise filters with parameters :
00162    * - AnalogFilter: I2C_CR1_ANFOFF bit
00163    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00164    */
00165   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00166
00167   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00168    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00169    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00170    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00171    */
00172   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00173
00174   /* Enable the selected I2Cx Peripheral */
00175   LL_I2C_Enable(I2Cx);
00176
00177   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00178    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00179    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00180    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00181    */
00182   LL_I2C_DisableOwnAddress1(I2Cx);
00183   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00184
00185   /* OwnAdress1 == 0 is reserved for General Call address */
00186   if (I2C_InitStruct->OwnAddress1 != 0U)
00187   {
00188     LL_I2C_EnableOwnAddress1(I2Cx);
00189   }
00190
00191   /*---------------------------- I2Cx MODE Configuration -----------------------
00192   * Configure I2Cx peripheral mode with parameter :
00193    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00194    */
00195   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00196
00197   /*---------------------------- I2Cx CR2 Configuration ------------------------
00198    * Configure the ACKnowledge or Non ACKnowledge condition
00199    * after the address receive match code or next received byte with parameter :
00200    * - TypeAcknowledge: I2C_CR2_NACK bit
00201    */
00202   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00203
00204   return SUCCESS;
00205 }
00206
00207 /**
00208   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00209   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00210   * @retval None
00211   */
00212 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00213 {
00214   /* Set I2C_InitStruct fields to default values */
00215   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00216   I2C_InitStruct->Timing          = 0U;
00217   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00218   I2C_InitStruct->DigitalFilter   = 0U;
00219   I2C_InitStruct->OwnAddress1     = 0U;
00220   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00221   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00222 }
00223
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /**
00233   * @}
00234   */
00235
00236 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
00237
00238 /**
00239   * @}
00240   */
00241
00242 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_i2c.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_i2c.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_I2C_H
00021 #define STM32G4xx_LL_I2C_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
00035
00036 /** @defgroup I2C_LL I2C
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051 /* Private macros ------------------------------------------------------------*/
00052 #if defined(USE_FULL_LL_DRIVER)
00053 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00054   * @{
00055   */
00056 /**
00057   * @}
00058   */
00059 #endif /*USE_FULL_LL_DRIVER*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 #if defined(USE_FULL_LL_DRIVER)
00063 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00069                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
00070
00071                                      This feature can be modified afterwards using unitary function
00072                                      @ref LL_I2C_SetMode(). */
00073
00074   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00075                                      This parameter must be set by referring to the STM32CubeMX Tool and
00076                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
00077
00078                                      This feature can be modified afterwards using unitary function
00079                                      @ref LL_I2C_SetTiming(). */
00080
00081   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00082                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
00083
00084                                      This feature can be modified afterwards using unitary functions
00085                                      @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00086
00087   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00088                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
00089
00090                                      This feature can be modified afterwards using unitary function
00091                                      @ref LL_I2C_SetDigitalFilter(). */
00092
00093   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00094                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
00095
00096                                      This feature can be modified afterwards using unitary function
00097                                      @ref LL_I2C_SetOwnAddress1(). */
00098
00099   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
00100                                      match code or next received byte.
00101                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
00102
00103                                      This feature can be modified afterwards using unitary function
00104                                      @ref LL_I2C_AcknowledgeNextData(). */
00105
00106   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00107                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
00108
00109                                      This feature can be modified afterwards using unitary function
00110                                      @ref LL_I2C_SetOwnAddress1(). */
00111 } LL_I2C_InitTypeDef;
00112 /**
00113   * @}
00114   */
00115 #endif /*USE_FULL_LL_DRIVER*/
00116
00117 /* Exported constants --------------------------------------------------------*/
00118 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00119   * @{
00120   */
00121
00122 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00123   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00124   * @{
00125   */
00126 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00127 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00128 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00129 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00130 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00131 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00132 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00133 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00134 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00140   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00141   * @{
00142   */
00143 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00144 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00145 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00146 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00147 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00148 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00149 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00150 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00151 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00152 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00153 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00154 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00155 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00156 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00157 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup I2C_LL_EC_IT IT Defines
00163   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00164   * @{
00165   */
00166 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00167 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00168 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00169 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00170 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00171 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00172 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00178   * @{
00179   */
00180 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
00181 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
00182 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
00183                                                                          (Default address not acknowledge)        */
00184 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00190   * @{
00191   */
00192 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
00193 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00199   * @{
00200   */
00201 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
00202 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00208   * @{
00209   */
00210 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
00211 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00217   * @{
00218   */
00219 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
00220 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
00221 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
00222 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
00223 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
00224 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
00225 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
00226 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
00227                                                                          All Address2 are acknowledged.        */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00233   * @{
00234   */
00235 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
00236 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00242   * @{
00243   */
00244 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
00245 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00251   * @{
00252   */
00253 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
00254 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00260   * @{
00261   */
00262 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
00263 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
00264                                                                           with no HW PEC comparison.  */
00265 #define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
00266                                                                           with no HW PEC comparison.  */
00267 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
00268                                                                           with HW PEC comparison.     */
00269 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
00270                                                                           with HW PEC comparison.     */
00271 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
00272                                                                           with HW PEC comparison.     */
00273 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
00274 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00275 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
00276 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00282   * @{
00283   */
00284 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
00285 /*!< Don't Generate Stop and Start condition. */
00286 #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
00287 /*!< Generate Stop condition (Size should be set to 0).      */
00288 #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00289 /*!< Generate Start for read request. */
00290 #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
00291 /*!< Generate Start for write request. */
00292 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00293 /*!< Generate Restart for read request, slave 7Bit address.  */
00294 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
00295 /*!< Generate Restart for write request, slave 7Bit address. */
00296 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
00297                                                        I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
00298 /*!< Generate Restart for read request, slave 10Bit address. */
00299 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
00300 /*!< Generate Restart for write request, slave 10Bit address.*/
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00306   * @{
00307   */
00308 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
00309                                                                           slave enters receiver mode.  */
00310 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
00311                                                                           slave enters transmitter mode.*/
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00317   * @{
00318   */
00319 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
00320                                                                           transmission */
00321 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
00322                                                                           reception */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00328   * @{
00329   */
00330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
00331                                                                           SCL low level timeout.              */
00332 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
00333                                                                           both SCL and SDA high level timeout.*/
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00339   * @{
00340   */
00341 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
00342 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
00343                                                                                        enable bit                   */
00344 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
00345                                                        I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
00346 (extended clock) enable bits */
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /* Exported macro ------------------------------------------------------------*/
00356 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00357   * @{
00358   */
00359
00360 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00361   * @{
00362   */
00363
00364 /**
00365   * @brief  Write a value in I2C register
00366   * @param  __INSTANCE__ I2C Instance
00367   * @param  __REG__ Register to be written
00368   * @param  __VALUE__ Value to be written in the register
00369   * @retval None
00370   */
00371 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00372
00373 /**
00374   * @brief  Read a value in I2C register
00375   * @param  __INSTANCE__ I2C Instance
00376   * @param  __REG__ Register to be read
00377   * @retval Register value
00378   */
00379 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00385   * @{
00386   */
00387 /**
00388   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00389   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
00390   * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
00391                            (tscldel = (SCLDEL+1)xtpresc)
00392   * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
00393                            (tsdadel = SDADELxtpresc)
00394   * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
00395                             (tsclh = (SCLH+1)xtpresc)
00396   * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
00397                             (tscll = (SCLL+1)xtpresc)
00398   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00399   */
00400 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
00401   ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
00402    (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
00403    (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
00404    (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
00405    (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /* Exported functions --------------------------------------------------------*/
00415 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00416   * @{
00417   */
00418
00419 /** @defgroup I2C_LL_EF_Configuration Configuration
00420   * @{
00421   */
00422
00423 /**
00424   * @brief  Enable I2C peripheral (PE = 1).
00425   * @rmtoll CR1          PE            LL_I2C_Enable
00426   * @param  I2Cx I2C Instance.
00427   * @retval None
00428   */
00429 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00430 {
00431   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00432 }
00433
00434 /**
00435   * @brief  Disable I2C peripheral (PE = 0).
00436   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00437   *         Internal state machines and status bits are put back to their reset value.
00438   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00439   * @rmtoll CR1          PE            LL_I2C_Disable
00440   * @param  I2Cx I2C Instance.
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00444 {
00445   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00446 }
00447
00448 /**
00449   * @brief  Check if the I2C peripheral is enabled or disabled.
00450   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00451   * @param  I2Cx I2C Instance.
00452   * @retval State of bit (1 or 0).
00453   */
00454 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
00455 {
00456   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
00457 }
00458
00459 /**
00460   * @brief  Configure Noise Filters (Analog and Digital).
00461   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00462   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00463   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00464   *         CR1          DNF           LL_I2C_ConfigFilters
00465   * @param  I2Cx I2C Instance.
00466   * @param  AnalogFilter This parameter can be one of the following values:
00467   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00468   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00469   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
00470                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00471   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00472   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00476 {
00477   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
00478 }
00479
00480 /**
00481   * @brief  Configure Digital Noise Filter.
00482   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00483   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00484   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00485   * @param  I2Cx I2C Instance.
00486   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
00487                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00488   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00489   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00490   * @retval None
00491   */
00492 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00493 {
00494   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
00495 }
00496
00497 /**
00498   * @brief  Get the current Digital Noise Filter configuration.
00499   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00500   * @param  I2Cx I2C Instance.
00501   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00502   */
00503 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
00504 {
00505   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
00506 }
00507
00508 /**
00509   * @brief  Enable Analog Noise Filter.
00510   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00511   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00512   * @param  I2Cx I2C Instance.
00513   * @retval None
00514   */
00515 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00516 {
00517   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00518 }
00519
00520 /**
00521   * @brief  Disable Analog Noise Filter.
00522   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00523   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00524   * @param  I2Cx I2C Instance.
00525   * @retval None
00526   */
00527 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00528 {
00529   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00530 }
00531
00532 /**
00533   * @brief  Check if Analog Noise Filter is enabled or disabled.
00534   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00535   * @param  I2Cx I2C Instance.
00536   * @retval State of bit (1 or 0).
00537   */
00538 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
00539 {
00540   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
00541 }
00542
00543 /**
00544   * @brief  Enable DMA transmission requests.
00545   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00546   * @param  I2Cx I2C Instance.
00547   * @retval None
00548   */
00549 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00550 {
00551   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00552 }
00553
00554 /**
00555   * @brief  Disable DMA transmission requests.
00556   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00557   * @param  I2Cx I2C Instance.
00558   * @retval None
00559   */
00560 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00561 {
00562   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00563 }
00564
00565 /**
00566   * @brief  Check if DMA transmission requests are enabled or disabled.
00567   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00568   * @param  I2Cx I2C Instance.
00569   * @retval State of bit (1 or 0).
00570   */
00571 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
00572 {
00573   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
00574 }
00575
00576 /**
00577   * @brief  Enable DMA reception requests.
00578   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00579   * @param  I2Cx I2C Instance.
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00583 {
00584   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00585 }
00586
00587 /**
00588   * @brief  Disable DMA reception requests.
00589   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00590   * @param  I2Cx I2C Instance.
00591   * @retval None
00592   */
00593 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00594 {
00595   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00596 }
00597
00598 /**
00599   * @brief  Check if DMA reception requests are enabled or disabled.
00600   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00601   * @param  I2Cx I2C Instance.
00602   * @retval State of bit (1 or 0).
00603   */
00604 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
00605 {
00606   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
00607 }
00608
00609 /**
00610   * @brief  Get the data register address used for DMA transfer
00611   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00612   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00613   * @param  I2Cx I2C Instance
00614   * @param  Direction This parameter can be one of the following values:
00615   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00616   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00617   * @retval Address of data register
00618   */
00619 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
00620 {
00621   uint32_t data_reg_addr;
00622
00623   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00624   {
00625     /* return address of TXDR register */
00626     data_reg_addr = (uint32_t) &(I2Cx->TXDR);
00627   }
00628   else
00629   {
00630     /* return address of RXDR register */
00631     data_reg_addr = (uint32_t) &(I2Cx->RXDR);
00632   }
00633
00634   return data_reg_addr;
00635 }
00636
00637 /**
00638   * @brief  Enable Clock stretching.
00639   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00640   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00641   * @param  I2Cx I2C Instance.
00642   * @retval None
00643   */
00644 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00645 {
00646   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00647 }
00648
00649 /**
00650   * @brief  Disable Clock stretching.
00651   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00652   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00653   * @param  I2Cx I2C Instance.
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00657 {
00658   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00659 }
00660
00661 /**
00662   * @brief  Check if Clock stretching is enabled or disabled.
00663   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00664   * @param  I2Cx I2C Instance.
00665   * @retval State of bit (1 or 0).
00666   */
00667 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
00668 {
00669   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
00670 }
00671
00672 /**
00673   * @brief  Enable hardware byte control in slave mode.
00674   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00675   * @param  I2Cx I2C Instance.
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00679 {
00680   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00681 }
00682
00683 /**
00684   * @brief  Disable hardware byte control in slave mode.
00685   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00686   * @param  I2Cx I2C Instance.
00687   * @retval None
00688   */
00689 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00690 {
00691   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00692 }
00693
00694 /**
00695   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00696   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00697   * @param  I2Cx I2C Instance.
00698   * @retval State of bit (1 or 0).
00699   */
00700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
00701 {
00702   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
00703 }
00704
00705 /**
00706   * @brief  Enable Wakeup from STOP.
00707   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00708   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00709   * @note   This bit can only be programmed when Digital Filter is disabled.
00710   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00711   * @param  I2Cx I2C Instance.
00712   * @retval None
00713   */
00714 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00715 {
00716   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00717 }
00718
00719 /**
00720   * @brief  Disable Wakeup from STOP.
00721   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00722   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00723   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00724   * @param  I2Cx I2C Instance.
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00728 {
00729   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00730 }
00731
00732 /**
00733   * @brief  Check if Wakeup from STOP is enabled or disabled.
00734   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00735   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00736   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00737   * @param  I2Cx I2C Instance.
00738   * @retval State of bit (1 or 0).
00739   */
00740 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
00741 {
00742   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
00743 }
00744
00745 /**
00746   * @brief  Enable General Call.
00747   * @note   When enabled the Address 0x00 is ACKed.
00748   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00749   * @param  I2Cx I2C Instance.
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00753 {
00754   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00755 }
00756
00757 /**
00758   * @brief  Disable General Call.
00759   * @note   When disabled the Address 0x00 is NACKed.
00760   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00761   * @param  I2Cx I2C Instance.
00762   * @retval None
00763   */
00764 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00765 {
00766   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00767 }
00768
00769 /**
00770   * @brief  Check if General Call is enabled or disabled.
00771   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00772   * @param  I2Cx I2C Instance.
00773   * @retval State of bit (1 or 0).
00774   */
00775 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
00776 {
00777   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
00778 }
00779
00780 /**
00781   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00782   * @note   Changing this bit is not allowed, when the START bit is set.
00783   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00784   * @param  I2Cx I2C Instance.
00785   * @param  AddressingMode This parameter can be one of the following values:
00786   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00787   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00791 {
00792   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00793 }
00794
00795 /**
00796   * @brief  Get the Master addressing mode.
00797   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00798   * @param  I2Cx I2C Instance.
00799   * @retval Returned value can be one of the following values:
00800   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00801   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00802   */
00803 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
00804 {
00805   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00806 }
00807
00808 /**
00809   * @brief  Set the Own Address1.
00810   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00811   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00812   * @param  I2Cx I2C Instance.
00813   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00814   * @param  OwnAddrSize This parameter can be one of the following values:
00815   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00816   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00817   * @retval None
00818   */
00819 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00820 {
00821   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00822 }
00823
00824 /**
00825   * @brief  Enable acknowledge on Own Address1 match address.
00826   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00827   * @param  I2Cx I2C Instance.
00828   * @retval None
00829   */
00830 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00831 {
00832   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00833 }
00834
00835 /**
00836   * @brief  Disable acknowledge on Own Address1 match address.
00837   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00838   * @param  I2Cx I2C Instance.
00839   * @retval None
00840   */
00841 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00842 {
00843   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00844 }
00845
00846 /**
00847   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00848   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00849   * @param  I2Cx I2C Instance.
00850   * @retval State of bit (1 or 0).
00851   */
00852 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
00853 {
00854   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
00855 }
00856
00857 /**
00858   * @brief  Set the 7bits Own Address2.
00859   * @note   This action has no effect if own address2 is enabled.
00860   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00861   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00862   * @param  I2Cx I2C Instance.
00863   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
00864   * @param  OwnAddrMask This parameter can be one of the following values:
00865   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00866   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00867   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00868   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00869   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00870   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00871   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00872   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00873   * @retval None
00874   */
00875 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00876 {
00877   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00878 }
00879
00880 /**
00881   * @brief  Enable acknowledge on Own Address2 match address.
00882   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00883   * @param  I2Cx I2C Instance.
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00887 {
00888   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00889 }
00890
00891 /**
00892   * @brief  Disable  acknowledge on Own Address2 match address.
00893   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00894   * @param  I2Cx I2C Instance.
00895   * @retval None
00896   */
00897 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00898 {
00899   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00900 }
00901
00902 /**
00903   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00904   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00905   * @param  I2Cx I2C Instance.
00906   * @retval State of bit (1 or 0).
00907   */
00908 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
00909 {
00910   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
00911 }
00912
00913 /**
00914   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00915   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00916   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00917   * @param  I2Cx I2C Instance.
00918   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
00919   * @note   This parameter is computed with the STM32CubeMX Tool.
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00923 {
00924   WRITE_REG(I2Cx->TIMINGR, Timing);
00925 }
00926
00927 /**
00928   * @brief  Get the Timing Prescaler setting.
00929   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00930   * @param  I2Cx I2C Instance.
00931   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00932   */
00933 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
00934 {
00935   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
00936 }
00937
00938 /**
00939   * @brief  Get the SCL low period setting.
00940   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00941   * @param  I2Cx I2C Instance.
00942   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00943   */
00944 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
00945 {
00946   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
00947 }
00948
00949 /**
00950   * @brief  Get the SCL high period setting.
00951   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00952   * @param  I2Cx I2C Instance.
00953   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00954   */
00955 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
00956 {
00957   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
00958 }
00959
00960 /**
00961   * @brief  Get the SDA hold time.
00962   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00963   * @param  I2Cx I2C Instance.
00964   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00965   */
00966 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
00967 {
00968   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
00969 }
00970
00971 /**
00972   * @brief  Get the SDA setup time.
00973   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00974   * @param  I2Cx I2C Instance.
00975   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00976   */
00977 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
00978 {
00979   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
00980 }
00981
00982 /**
00983   * @brief  Configure peripheral mode.
00984   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00985   *         SMBus feature is supported by the I2Cx Instance.
00986   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00987   *         CR1          SMBDEN        LL_I2C_SetMode
00988   * @param  I2Cx I2C Instance.
00989   * @param  PeripheralMode This parameter can be one of the following values:
00990   *         @arg @ref LL_I2C_MODE_I2C
00991   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00992   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00993   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00997 {
00998   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00999 }
01000
01001 /**
01002   * @brief  Get peripheral mode.
01003   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01004   *         SMBus feature is supported by the I2Cx Instance.
01005   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
01006   *         CR1          SMBDEN        LL_I2C_GetMode
01007   * @param  I2Cx I2C Instance.
01008   * @retval Returned value can be one of the following values:
01009   *         @arg @ref LL_I2C_MODE_I2C
01010   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
01011   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
01012   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
01013   */
01014 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
01015 {
01016   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
01017 }
01018
01019 /**
01020   * @brief  Enable SMBus alert (Host or Device mode)
01021   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01022   *         SMBus feature is supported by the I2Cx Instance.
01023   * @note   SMBus Device mode:
01024   *         - SMBus Alert pin is drived low and
01025   *           Alert Response Address Header acknowledge is enabled.
01026   *         SMBus Host mode:
01027   *         - SMBus Alert pin management is supported.
01028   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
01029   * @param  I2Cx I2C Instance.
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
01033 {
01034   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01035 }
01036
01037 /**
01038   * @brief  Disable SMBus alert (Host or Device mode)
01039   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01040   *         SMBus feature is supported by the I2Cx Instance.
01041   * @note   SMBus Device mode:
01042   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01043   *           Alert Response Address Header acknowledge is disabled.
01044   *         SMBus Host mode:
01045   *         - SMBus Alert pin management is not supported.
01046   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01047   * @param  I2Cx I2C Instance.
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01051 {
01052   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01053 }
01054
01055 /**
01056   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01057   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01058   *         SMBus feature is supported by the I2Cx Instance.
01059   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01060   * @param  I2Cx I2C Instance.
01061   * @retval State of bit (1 or 0).
01062   */
01063 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
01064 {
01065   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
01066 }
01067
01068 /**
01069   * @brief  Enable SMBus Packet Error Calculation (PEC).
01070   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01071   *         SMBus feature is supported by the I2Cx Instance.
01072   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01073   * @param  I2Cx I2C Instance.
01074   * @retval None
01075   */
01076 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01077 {
01078   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01079 }
01080
01081 /**
01082   * @brief  Disable SMBus Packet Error Calculation (PEC).
01083   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01084   *         SMBus feature is supported by the I2Cx Instance.
01085   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01086   * @param  I2Cx I2C Instance.
01087   * @retval None
01088   */
01089 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01090 {
01091   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01092 }
01093
01094 /**
01095   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01096   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01097   *         SMBus feature is supported by the I2Cx Instance.
01098   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01099   * @param  I2Cx I2C Instance.
01100   * @retval State of bit (1 or 0).
01101   */
01102 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
01103 {
01104   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
01105 }
01106
01107 /**
01108   * @brief  Configure the SMBus Clock Timeout.
01109   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01110   *         SMBus feature is supported by the I2Cx Instance.
01111   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01112   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01113   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01114   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01115   * @param  I2Cx I2C Instance.
01116   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01117   * @param  TimeoutAMode This parameter can be one of the following values:
01118   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01119   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01120   * @param  TimeoutB
01121   * @retval None
01122   */
01123 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01124                                                uint32_t TimeoutB)
01125 {
01126   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01127              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
01128 }
01129
01130 /**
01131   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01132   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01133   *         SMBus feature is supported by the I2Cx Instance.
01134   * @note   These bits can only be programmed when TimeoutA is disabled.
01135   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01136   * @param  I2Cx I2C Instance.
01137   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01141 {
01142   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01143 }
01144
01145 /**
01146   * @brief  Get the SMBus Clock TimeoutA setting.
01147   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01148   *         SMBus feature is supported by the I2Cx Instance.
01149   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01150   * @param  I2Cx I2C Instance.
01151   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01152   */
01153 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
01154 {
01155   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01156 }
01157
01158 /**
01159   * @brief  Set the SMBus Clock TimeoutA mode.
01160   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01161   *         SMBus feature is supported by the I2Cx Instance.
01162   * @note   This bit can only be programmed when TimeoutA is disabled.
01163   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01164   * @param  I2Cx I2C Instance.
01165   * @param  TimeoutAMode This parameter can be one of the following values:
01166   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01167   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01168   * @retval None
01169   */
01170 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01171 {
01172   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01173 }
01174
01175 /**
01176   * @brief  Get the SMBus Clock TimeoutA mode.
01177   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01178   *         SMBus feature is supported by the I2Cx Instance.
01179   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01180   * @param  I2Cx I2C Instance.
01181   * @retval Returned value can be one of the following values:
01182   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01183   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01184   */
01185 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
01186 {
01187   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01188 }
01189
01190 /**
01191   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01192   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01193   *         SMBus feature is supported by the I2Cx Instance.
01194   * @note   These bits can only be programmed when TimeoutB is disabled.
01195   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01196   * @param  I2Cx I2C Instance.
01197   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01198   * @retval None
01199   */
01200 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01201 {
01202   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
01203 }
01204
01205 /**
01206   * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
01207   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01208   *         SMBus feature is supported by the I2Cx Instance.
01209   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01210   * @param  I2Cx I2C Instance.
01211   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01212   */
01213 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
01214 {
01215   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
01216 }
01217
01218 /**
01219   * @brief  Enable the SMBus Clock Timeout.
01220   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01221   *         SMBus feature is supported by the I2Cx Instance.
01222   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01223   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01224   * @param  I2Cx I2C Instance.
01225   * @param  ClockTimeout This parameter can be one of the following values:
01226   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01227   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01228   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01229   * @retval None
01230   */
01231 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01232 {
01233   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01234 }
01235
01236 /**
01237   * @brief  Disable the SMBus Clock Timeout.
01238   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01239   *         SMBus feature is supported by the I2Cx Instance.
01240   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01241   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01242   * @param  I2Cx I2C Instance.
01243   * @param  ClockTimeout This parameter can be one of the following values:
01244   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01245   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01246   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01247   * @retval None
01248   */
01249 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01250 {
01251   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01252 }
01253
01254 /**
01255   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01256   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01257   *         SMBus feature is supported by the I2Cx Instance.
01258   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01259   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01260   * @param  I2Cx I2C Instance.
01261   * @param  ClockTimeout This parameter can be one of the following values:
01262   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01263   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01264   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01268 {
01269   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
01270            (ClockTimeout)) ? 1UL : 0UL);
01271 }
01272
01273 /**
01274   * @}
01275   */
01276
01277 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01278   * @{
01279   */
01280
01281 /**
01282   * @brief  Enable TXIS interrupt.
01283   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01284   * @param  I2Cx I2C Instance.
01285   * @retval None
01286   */
01287 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01288 {
01289   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01290 }
01291
01292 /**
01293   * @brief  Disable TXIS interrupt.
01294   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01295   * @param  I2Cx I2C Instance.
01296   * @retval None
01297   */
01298 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01299 {
01300   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01301 }
01302
01303 /**
01304   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01305   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01306   * @param  I2Cx I2C Instance.
01307   * @retval State of bit (1 or 0).
01308   */
01309 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
01310 {
01311   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
01312 }
01313
01314 /**
01315   * @brief  Enable RXNE interrupt.
01316   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01317   * @param  I2Cx I2C Instance.
01318   * @retval None
01319   */
01320 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01321 {
01322   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01323 }
01324
01325 /**
01326   * @brief  Disable RXNE interrupt.
01327   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01328   * @param  I2Cx I2C Instance.
01329   * @retval None
01330   */
01331 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01332 {
01333   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01334 }
01335
01336 /**
01337   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01338   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01339   * @param  I2Cx I2C Instance.
01340   * @retval State of bit (1 or 0).
01341   */
01342 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
01343 {
01344   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
01345 }
01346
01347 /**
01348   * @brief  Enable Address match interrupt (slave mode only).
01349   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01350   * @param  I2Cx I2C Instance.
01351   * @retval None
01352   */
01353 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01354 {
01355   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01356 }
01357
01358 /**
01359   * @brief  Disable Address match interrupt (slave mode only).
01360   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01361   * @param  I2Cx I2C Instance.
01362   * @retval None
01363   */
01364 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01365 {
01366   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01367 }
01368
01369 /**
01370   * @brief  Check if Address match interrupt is enabled or disabled.
01371   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01372   * @param  I2Cx I2C Instance.
01373   * @retval State of bit (1 or 0).
01374   */
01375 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
01376 {
01377   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
01378 }
01379
01380 /**
01381   * @brief  Enable Not acknowledge received interrupt.
01382   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01383   * @param  I2Cx I2C Instance.
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01387 {
01388   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01389 }
01390
01391 /**
01392   * @brief  Disable Not acknowledge received interrupt.
01393   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01394   * @param  I2Cx I2C Instance.
01395   * @retval None
01396   */
01397 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01398 {
01399   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01400 }
01401
01402 /**
01403   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01404   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01405   * @param  I2Cx I2C Instance.
01406   * @retval State of bit (1 or 0).
01407   */
01408 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
01409 {
01410   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
01411 }
01412
01413 /**
01414   * @brief  Enable STOP detection interrupt.
01415   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01416   * @param  I2Cx I2C Instance.
01417   * @retval None
01418   */
01419 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01420 {
01421   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01422 }
01423
01424 /**
01425   * @brief  Disable STOP detection interrupt.
01426   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01427   * @param  I2Cx I2C Instance.
01428   * @retval None
01429   */
01430 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01431 {
01432   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01433 }
01434
01435 /**
01436   * @brief  Check if STOP detection interrupt is enabled or disabled.
01437   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01438   * @param  I2Cx I2C Instance.
01439   * @retval State of bit (1 or 0).
01440   */
01441 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
01442 {
01443   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
01444 }
01445
01446 /**
01447   * @brief  Enable Transfer Complete interrupt.
01448   * @note   Any of these events will generate interrupt :
01449   *         Transfer Complete (TC)
01450   *         Transfer Complete Reload (TCR)
01451   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01452   * @param  I2Cx I2C Instance.
01453   * @retval None
01454   */
01455 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01456 {
01457   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01458 }
01459
01460 /**
01461   * @brief  Disable Transfer Complete interrupt.
01462   * @note   Any of these events will generate interrupt :
01463   *         Transfer Complete (TC)
01464   *         Transfer Complete Reload (TCR)
01465   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01466   * @param  I2Cx I2C Instance.
01467   * @retval None
01468   */
01469 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01470 {
01471   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01472 }
01473
01474 /**
01475   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01476   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01477   * @param  I2Cx I2C Instance.
01478   * @retval State of bit (1 or 0).
01479   */
01480 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
01481 {
01482   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
01483 }
01484
01485 /**
01486   * @brief  Enable Error interrupts.
01487   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01488   *         SMBus feature is supported by the I2Cx Instance.
01489   * @note   Any of these errors will generate interrupt :
01490   *         Arbitration Loss (ARLO)
01491   *         Bus Error detection (BERR)
01492   *         Overrun/Underrun (OVR)
01493   *         SMBus Timeout detection (TIMEOUT)
01494   *         SMBus PEC error detection (PECERR)
01495   *         SMBus Alert pin event detection (ALERT)
01496   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01497   * @param  I2Cx I2C Instance.
01498   * @retval None
01499   */
01500 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01501 {
01502   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01503 }
01504
01505 /**
01506   * @brief  Disable Error interrupts.
01507   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01508   *         SMBus feature is supported by the I2Cx Instance.
01509   * @note   Any of these errors will generate interrupt :
01510   *         Arbitration Loss (ARLO)
01511   *         Bus Error detection (BERR)
01512   *         Overrun/Underrun (OVR)
01513   *         SMBus Timeout detection (TIMEOUT)
01514   *         SMBus PEC error detection (PECERR)
01515   *         SMBus Alert pin event detection (ALERT)
01516   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01517   * @param  I2Cx I2C Instance.
01518   * @retval None
01519   */
01520 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01521 {
01522   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01523 }
01524
01525 /**
01526   * @brief  Check if Error interrupts are enabled or disabled.
01527   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01528   * @param  I2Cx I2C Instance.
01529   * @retval State of bit (1 or 0).
01530   */
01531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
01532 {
01533   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
01534 }
01535
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01541   * @{
01542   */
01543
01544 /**
01545   * @brief  Indicate the status of Transmit data register empty flag.
01546   * @note   RESET: When next data is written in Transmit data register.
01547   *         SET: When Transmit data register is empty.
01548   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01549   * @param  I2Cx I2C Instance.
01550   * @retval State of bit (1 or 0).
01551   */
01552 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
01553 {
01554   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
01555 }
01556
01557 /**
01558   * @brief  Indicate the status of Transmit interrupt flag.
01559   * @note   RESET: When next data is written in Transmit data register.
01560   *         SET: When Transmit data register is empty.
01561   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01562   * @param  I2Cx I2C Instance.
01563   * @retval State of bit (1 or 0).
01564   */
01565 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
01566 {
01567   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
01568 }
01569
01570 /**
01571   * @brief  Indicate the status of Receive data register not empty flag.
01572   * @note   RESET: When Receive data register is read.
01573   *         SET: When the received data is copied in Receive data register.
01574   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01575   * @param  I2Cx I2C Instance.
01576   * @retval State of bit (1 or 0).
01577   */
01578 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
01579 {
01580   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
01581 }
01582
01583 /**
01584   * @brief  Indicate the status of Address matched flag (slave mode).
01585   * @note   RESET: Clear default value.
01586   *         SET: When the received slave address matched with one of the enabled slave address.
01587   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01588   * @param  I2Cx I2C Instance.
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
01592 {
01593   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Indicate the status of Not Acknowledge received flag.
01598   * @note   RESET: Clear default value.
01599   *         SET: When a NACK is received after a byte transmission.
01600   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01601   * @param  I2Cx I2C Instance.
01602   * @retval State of bit (1 or 0).
01603   */
01604 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
01605 {
01606   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
01607 }
01608
01609 /**
01610   * @brief  Indicate the status of Stop detection flag.
01611   * @note   RESET: Clear default value.
01612   *         SET: When a Stop condition is detected.
01613   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01614   * @param  I2Cx I2C Instance.
01615   * @retval State of bit (1 or 0).
01616   */
01617 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
01618 {
01619   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
01620 }
01621
01622 /**
01623   * @brief  Indicate the status of Transfer complete flag (master mode).
01624   * @note   RESET: Clear default value.
01625   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01626   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01627   * @param  I2Cx I2C Instance.
01628   * @retval State of bit (1 or 0).
01629   */
01630 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
01631 {
01632   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
01633 }
01634
01635 /**
01636   * @brief  Indicate the status of Transfer complete flag (master mode).
01637   * @note   RESET: Clear default value.
01638   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01639   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01640   * @param  I2Cx I2C Instance.
01641   * @retval State of bit (1 or 0).
01642   */
01643 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
01644 {
01645   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
01646 }
01647
01648 /**
01649   * @brief  Indicate the status of Bus error flag.
01650   * @note   RESET: Clear default value.
01651   *         SET: When a misplaced Start or Stop condition is detected.
01652   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01653   * @param  I2Cx I2C Instance.
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
01657 {
01658   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Indicate the status of Arbitration lost flag.
01663   * @note   RESET: Clear default value.
01664   *         SET: When arbitration lost.
01665   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01666   * @param  I2Cx I2C Instance.
01667   * @retval State of bit (1 or 0).
01668   */
01669 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
01670 {
01671   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
01672 }
01673
01674 /**
01675   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01676   * @note   RESET: Clear default value.
01677   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01678   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01679   * @param  I2Cx I2C Instance.
01680   * @retval State of bit (1 or 0).
01681   */
01682 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
01683 {
01684   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
01685 }
01686
01687 /**
01688   * @brief  Indicate the status of SMBus PEC error flag in reception.
01689   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01690   *         SMBus feature is supported by the I2Cx Instance.
01691   * @note   RESET: Clear default value.
01692   *         SET: When the received PEC does not match with the PEC register content.
01693   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01694   * @param  I2Cx I2C Instance.
01695   * @retval State of bit (1 or 0).
01696   */
01697 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
01698 {
01699   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
01700 }
01701
01702 /**
01703   * @brief  Indicate the status of SMBus Timeout detection flag.
01704   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01705   *         SMBus feature is supported by the I2Cx Instance.
01706   * @note   RESET: Clear default value.
01707   *         SET: When a timeout or extended clock timeout occurs.
01708   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01709   * @param  I2Cx I2C Instance.
01710   * @retval State of bit (1 or 0).
01711   */
01712 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
01713 {
01714   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
01715 }
01716
01717 /**
01718   * @brief  Indicate the status of SMBus alert flag.
01719   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01720   *         SMBus feature is supported by the I2Cx Instance.
01721   * @note   RESET: Clear default value.
01722   *         SET: When SMBus host configuration, SMBus alert enabled and
01723   *              a falling edge event occurs on SMBA pin.
01724   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01725   * @param  I2Cx I2C Instance.
01726   * @retval State of bit (1 or 0).
01727   */
01728 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
01729 {
01730   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
01731 }
01732
01733 /**
01734   * @brief  Indicate the status of Bus Busy flag.
01735   * @note   RESET: Clear default value.
01736   *         SET: When a Start condition is detected.
01737   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01738   * @param  I2Cx I2C Instance.
01739   * @retval State of bit (1 or 0).
01740   */
01741 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
01742 {
01743   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
01744 }
01745
01746 /**
01747   * @brief  Clear Address Matched flag.
01748   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01749   * @param  I2Cx I2C Instance.
01750   * @retval None
01751   */
01752 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01753 {
01754   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01755 }
01756
01757 /**
01758   * @brief  Clear Not Acknowledge flag.
01759   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01760   * @param  I2Cx I2C Instance.
01761   * @retval None
01762   */
01763 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01764 {
01765   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01766 }
01767
01768 /**
01769   * @brief  Clear Stop detection flag.
01770   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01771   * @param  I2Cx I2C Instance.
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01775 {
01776   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01777 }
01778
01779 /**
01780   * @brief  Clear Transmit data register empty flag (TXE).
01781   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01782   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01783   * @param  I2Cx I2C Instance.
01784   * @retval None
01785   */
01786 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01787 {
01788   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01789 }
01790
01791 /**
01792   * @brief  Clear Bus error flag.
01793   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01794   * @param  I2Cx I2C Instance.
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01798 {
01799   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01800 }
01801
01802 /**
01803   * @brief  Clear Arbitration lost flag.
01804   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01805   * @param  I2Cx I2C Instance.
01806   * @retval None
01807   */
01808 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01809 {
01810   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01811 }
01812
01813 /**
01814   * @brief  Clear Overrun/Underrun flag.
01815   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01816   * @param  I2Cx I2C Instance.
01817   * @retval None
01818   */
01819 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01820 {
01821   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01822 }
01823
01824 /**
01825   * @brief  Clear SMBus PEC error flag.
01826   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01827   *         SMBus feature is supported by the I2Cx Instance.
01828   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01829   * @param  I2Cx I2C Instance.
01830   * @retval None
01831   */
01832 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01833 {
01834   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01835 }
01836
01837 /**
01838   * @brief  Clear SMBus Timeout detection flag.
01839   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01840   *         SMBus feature is supported by the I2Cx Instance.
01841   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01842   * @param  I2Cx I2C Instance.
01843   * @retval None
01844   */
01845 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01846 {
01847   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01848 }
01849
01850 /**
01851   * @brief  Clear SMBus Alert flag.
01852   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01853   *         SMBus feature is supported by the I2Cx Instance.
01854   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01855   * @param  I2Cx I2C Instance.
01856   * @retval None
01857   */
01858 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01859 {
01860   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01861 }
01862
01863 /**
01864   * @}
01865   */
01866
01867 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01868   * @{
01869   */
01870
01871 /**
01872   * @brief  Enable automatic STOP condition generation (master mode).
01873   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01874   *         This bit has no effect in slave mode or when RELOAD bit is set.
01875   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01876   * @param  I2Cx I2C Instance.
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01880 {
01881   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01882 }
01883
01884 /**
01885   * @brief  Disable automatic STOP condition generation (master mode).
01886   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01887   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01888   * @param  I2Cx I2C Instance.
01889   * @retval None
01890   */
01891 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01892 {
01893   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01894 }
01895
01896 /**
01897   * @brief  Check if automatic STOP condition is enabled or disabled.
01898   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01899   * @param  I2Cx I2C Instance.
01900   * @retval State of bit (1 or 0).
01901   */
01902 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
01903 {
01904   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
01905 }
01906
01907 /**
01908   * @brief  Enable reload mode (master mode).
01909   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01910   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01911   * @param  I2Cx I2C Instance.
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01915 {
01916   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01917 }
01918
01919 /**
01920   * @brief  Disable reload mode (master mode).
01921   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01922   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01923   * @param  I2Cx I2C Instance.
01924   * @retval None
01925   */
01926 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01927 {
01928   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01929 }
01930
01931 /**
01932   * @brief  Check if reload mode is enabled or disabled.
01933   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01934   * @param  I2Cx I2C Instance.
01935   * @retval State of bit (1 or 0).
01936   */
01937 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
01938 {
01939   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
01940 }
01941
01942 /**
01943   * @brief  Configure the number of bytes for transfer.
01944   * @note   Changing these bits when START bit is set is not allowed.
01945   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01946   * @param  I2Cx I2C Instance.
01947   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01948   * @retval None
01949   */
01950 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01951 {
01952   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
01953 }
01954
01955 /**
01956   * @brief  Get the number of bytes configured for transfer.
01957   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01958   * @param  I2Cx I2C Instance.
01959   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01960   */
01961 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
01962 {
01963   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
01964 }
01965
01966 /**
01967   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
01968             or next received byte.
01969   * @note   Usage in Slave mode only.
01970   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01971   * @param  I2Cx I2C Instance.
01972   * @param  TypeAcknowledge This parameter can be one of the following values:
01973   *         @arg @ref LL_I2C_ACK
01974   *         @arg @ref LL_I2C_NACK
01975   * @retval None
01976   */
01977 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01978 {
01979   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01980 }
01981
01982 /**
01983   * @brief  Generate a START or RESTART condition
01984   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01985   *         This action has no effect when RELOAD is set.
01986   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01987   * @param  I2Cx I2C Instance.
01988   * @retval None
01989   */
01990 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01991 {
01992   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01993 }
01994
01995 /**
01996   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01997   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01998   * @param  I2Cx I2C Instance.
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
02002 {
02003   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
02004 }
02005
02006 /**
02007   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
02008   * @note   The master sends the complete 10bit slave address read sequence :
02009   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
02010             in Read direction.
02011   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
02012   * @param  I2Cx I2C Instance.
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
02016 {
02017   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02018 }
02019
02020 /**
02021   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
02022   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
02023   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
02024   * @param  I2Cx I2C Instance.
02025   * @retval None
02026   */
02027 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
02028 {
02029   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02030 }
02031
02032 /**
02033   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
02034   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
02035   * @param  I2Cx I2C Instance.
02036   * @retval State of bit (1 or 0).
02037   */
02038 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
02039 {
02040   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
02041 }
02042
02043 /**
02044   * @brief  Configure the transfer direction (master mode).
02045   * @note   Changing these bits when START bit is set is not allowed.
02046   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02047   * @param  I2Cx I2C Instance.
02048   * @param  TransferRequest This parameter can be one of the following values:
02049   *         @arg @ref LL_I2C_REQUEST_WRITE
02050   *         @arg @ref LL_I2C_REQUEST_READ
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02054 {
02055   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02056 }
02057
02058 /**
02059   * @brief  Get the transfer direction requested (master mode).
02060   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02061   * @param  I2Cx I2C Instance.
02062   * @retval Returned value can be one of the following values:
02063   *         @arg @ref LL_I2C_REQUEST_WRITE
02064   *         @arg @ref LL_I2C_REQUEST_READ
02065   */
02066 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
02067 {
02068   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02069 }
02070
02071 /**
02072   * @brief  Configure the slave address for transfer (master mode).
02073   * @note   Changing these bits when START bit is set is not allowed.
02074   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02075   * @param  I2Cx I2C Instance.
02076   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02080 {
02081   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02082 }
02083
02084 /**
02085   * @brief  Get the slave address programmed for transfer.
02086   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02087   * @param  I2Cx I2C Instance.
02088   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02089   */
02090 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
02091 {
02092   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02093 }
02094
02095 /**
02096   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02097   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02098   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02099   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02100   *         CR2          START         LL_I2C_HandleTransfer\n
02101   *         CR2          STOP          LL_I2C_HandleTransfer\n
02102   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02103   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02104   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02105   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02106   * @param  I2Cx I2C Instance.
02107   * @param  SlaveAddr Specifies the slave address to be programmed.
02108   * @param  SlaveAddrSize This parameter can be one of the following values:
02109   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02110   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02111   * @param  TransferSize Specifies the number of bytes to be programmed.
02112   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
02113   * @param  EndMode This parameter can be one of the following values:
02114   *         @arg @ref LL_I2C_MODE_RELOAD
02115   *         @arg @ref LL_I2C_MODE_AUTOEND
02116   *         @arg @ref LL_I2C_MODE_SOFTEND
02117   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02118   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02119   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02120   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02121   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02122   * @param  Request This parameter can be one of the following values:
02123   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02124   *         @arg @ref LL_I2C_GENERATE_STOP
02125   *         @arg @ref LL_I2C_GENERATE_START_READ
02126   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02127   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02128   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02129   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02130   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02131   * @retval None
02132   */
02133 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02134                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02135 {
02136   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02137   uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
02138                              ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
02139                              (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
02140                              (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
02141
02142   /* update CR2 register */
02143   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
02144              (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
02145              I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02146              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02147              tmp);
02148 }
02149
02150 /**
02151   * @brief  Indicate the value of transfer direction (slave mode).
02152   * @note   RESET: Write transfer, Slave enters in receiver mode.
02153   *         SET: Read transfer, Slave enters in transmitter mode.
02154   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02155   * @param  I2Cx I2C Instance.
02156   * @retval Returned value can be one of the following values:
02157   *         @arg @ref LL_I2C_DIRECTION_WRITE
02158   *         @arg @ref LL_I2C_DIRECTION_READ
02159   */
02160 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
02161 {
02162   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02163 }
02164
02165 /**
02166   * @brief  Return the slave matched address.
02167   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02168   * @param  I2Cx I2C Instance.
02169   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02170   */
02171 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
02172 {
02173   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
02174 }
02175
02176 /**
02177   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
02178   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02179   *         SMBus feature is supported by the I2Cx Instance.
02180   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
02181             or an Address Matched is received.
02182   *         This bit has no effect when RELOAD bit is set.
02183   *         This bit has no effect in device mode when SBC bit is not set.
02184   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02185   * @param  I2Cx I2C Instance.
02186   * @retval None
02187   */
02188 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02189 {
02190   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02191 }
02192
02193 /**
02194   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
02195   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02196   *         SMBus feature is supported by the I2Cx Instance.
02197   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02198   * @param  I2Cx I2C Instance.
02199   * @retval State of bit (1 or 0).
02200   */
02201 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
02202 {
02203   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
02204 }
02205
02206 /**
02207   * @brief  Get the SMBus Packet Error byte calculated.
02208   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02209   *         SMBus feature is supported by the I2Cx Instance.
02210   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02211   * @param  I2Cx I2C Instance.
02212   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02213   */
02214 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
02215 {
02216   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02217 }
02218
02219 /**
02220   * @brief  Read Receive Data register.
02221   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02222   * @param  I2Cx I2C Instance.
02223   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02224   */
02225 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
02226 {
02227   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02228 }
02229
02230 /**
02231   * @brief  Write in Transmit Data Register .
02232   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02233   * @param  I2Cx I2C Instance.
02234   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02235   * @retval None
02236   */
02237 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02238 {
02239   WRITE_REG(I2Cx->TXDR, Data);
02240 }
02241
02242 /**
02243   * @}
02244   */
02245
02246 #if defined(USE_FULL_LL_DRIVER)
02247 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02248   * @{
02249   */
02250
02251 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
02252 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
02253 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02254
02255
02256 /**
02257   * @}
02258   */
02259 #endif /* USE_FULL_LL_DRIVER */
02260
02261 /**
02262   * @}
02263   */
02264
02265 /**
02266   * @}
02267   */
02268
02269 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
02270
02271 /**
02272   * @}
02273   */
02274
02275 #ifdef __cplusplus
02276 }
02277 #endif
02278
02279 #endif /* STM32G4xx_LL_I2C_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_iwdg.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_IWDG_H
00021 #define STM32G4xx_LL_IWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(IWDG)
00035
00036 /** @defgroup IWDG_LL IWDG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00045   * @{
00046   */
00047 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00048 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00049 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00050 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00064   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00065   * @{
00066   */
00067 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00068 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00069 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00075   * @{
00076   */
00077 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00078 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00079 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00080 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00081 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00082 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00083 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /* Exported macro ------------------------------------------------------------*/
00093 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00094   * @{
00095   */
00096
00097 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Write a value in IWDG register
00103   * @param  __INSTANCE__ IWDG Instance
00104   * @param  __REG__ Register to be written
00105   * @param  __VALUE__ Value to be written in the register
00106   * @retval None
00107   */
00108 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00109
00110 /**
00111   * @brief  Read a value in IWDG register
00112   * @param  __INSTANCE__ IWDG Instance
00113   * @param  __REG__ Register to be read
00114   * @retval Register value
00115   */
00116 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125
00126 /* Exported functions --------------------------------------------------------*/
00127 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00128   * @{
00129   */
00130 /** @defgroup IWDG_LL_EF_Configuration Configuration
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Start the Independent Watchdog
00136   * @note   Except if the hardware watchdog option is selected
00137   * @rmtoll KR           KEY           LL_IWDG_Enable
00138   * @param  IWDGx IWDG Instance
00139   * @retval None
00140   */
00141 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00142 {
00143   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
00144 }
00145
00146 /**
00147   * @brief  Reloads IWDG counter with value defined in the reload register
00148   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00149   * @param  IWDGx IWDG Instance
00150   * @retval None
00151   */
00152 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00153 {
00154   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
00155 }
00156
00157 /**
00158   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00159   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00160   * @param  IWDGx IWDG Instance
00161   * @retval None
00162   */
00163 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00164 {
00165   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00166 }
00167
00168 /**
00169   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00170   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00171   * @param  IWDGx IWDG Instance
00172   * @retval None
00173   */
00174 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00175 {
00176   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00177 }
00178
00179 /**
00180   * @brief  Select the prescaler of the IWDG
00181   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00182   * @param  IWDGx IWDG Instance
00183   * @param  Prescaler This parameter can be one of the following values:
00184   *         @arg @ref LL_IWDG_PRESCALER_4
00185   *         @arg @ref LL_IWDG_PRESCALER_8
00186   *         @arg @ref LL_IWDG_PRESCALER_16
00187   *         @arg @ref LL_IWDG_PRESCALER_32
00188   *         @arg @ref LL_IWDG_PRESCALER_64
00189   *         @arg @ref LL_IWDG_PRESCALER_128
00190   *         @arg @ref LL_IWDG_PRESCALER_256
00191   * @retval None
00192   */
00193 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00194 {
00195   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00196 }
00197
00198 /**
00199   * @brief  Get the selected prescaler of the IWDG
00200   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00201   * @param  IWDGx IWDG Instance
00202   * @retval Returned value can be one of the following values:
00203   *         @arg @ref LL_IWDG_PRESCALER_4
00204   *         @arg @ref LL_IWDG_PRESCALER_8
00205   *         @arg @ref LL_IWDG_PRESCALER_16
00206   *         @arg @ref LL_IWDG_PRESCALER_32
00207   *         @arg @ref LL_IWDG_PRESCALER_64
00208   *         @arg @ref LL_IWDG_PRESCALER_128
00209   *         @arg @ref LL_IWDG_PRESCALER_256
00210   */
00211 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
00212 {
00213   return (READ_REG(IWDGx->PR));
00214 }
00215
00216 /**
00217   * @brief  Specify the IWDG down-counter reload value
00218   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00219   * @param  IWDGx IWDG Instance
00220   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00221   * @retval None
00222   */
00223 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00224 {
00225   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00226 }
00227
00228 /**
00229   * @brief  Get the specified IWDG down-counter reload value
00230   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00231   * @param  IWDGx IWDG Instance
00232   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00233   */
00234 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
00235 {
00236   return (READ_REG(IWDGx->RLR));
00237 }
00238
00239 /**
00240   * @brief  Specify high limit of the window value to be compared to the down-counter.
00241   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00242   * @param  IWDGx IWDG Instance
00243   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00244   * @retval None
00245   */
00246 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00247 {
00248   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00249 }
00250
00251 /**
00252   * @brief  Get the high limit of the window value specified.
00253   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00254   * @param  IWDGx IWDG Instance
00255   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00256   */
00257 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
00258 {
00259   return (READ_REG(IWDGx->WINR));
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00267   * @{
00268   */
00269
00270 /**
00271   * @brief  Check if flag Prescaler Value Update is set or not
00272   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00273   * @param  IWDGx IWDG Instance
00274   * @retval State of bit (1 or 0).
00275   */
00276 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
00277 {
00278   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
00279 }
00280
00281 /**
00282   * @brief  Check if flag Reload Value Update is set or not
00283   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00284   * @param  IWDGx IWDG Instance
00285   * @retval State of bit (1 or 0).
00286   */
00287 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
00288 {
00289   return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
00290 }
00291
00292 /**
00293   * @brief  Check if flag Window Value Update is set or not
00294   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00295   * @param  IWDGx IWDG Instance
00296   * @retval State of bit (1 or 0).
00297   */
00298 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
00299 {
00300   return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
00301 }
00302
00303 /**
00304   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00305   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00306   *         SR           RVU           LL_IWDG_IsReady\n
00307   *         SR           WVU           LL_IWDG_IsReady
00308   * @param  IWDGx IWDG Instance
00309   * @retval State of bits (1 or 0).
00310   */
00311 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00312 {
00313   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 #endif /* IWDG */
00329
00330 /**
00331   * @}
00332   */
00333
00334 #ifdef __cplusplus
00335 }
00336 #endif
00337
00338 #endif /* STM32G4xx_LL_IWDG_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lptim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_lptim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_lptim.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #include "stm32g4xx_ll_rcc.h"
00024
00025
00026 #ifdef  USE_FULL_ASSERT
00027 #include "stm32_assert.h"
00028 #else
00029 #define assert_param(expr) ((void)0U)
00030 #endif /* USE_FULL_ASSERT */
00031
00032 /** @addtogroup STM32G4xx_LL_Driver
00033   * @{
00034   */
00035
00036
00037
00038 /** @addtogroup LPTIM_LL
00039   * @{
00040   */
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /* Private constants ---------------------------------------------------------*/
00045 /* Private macros ------------------------------------------------------------*/
00046 /** @addtogroup LPTIM_LL_Private_Macros
00047   * @{
00048   */
00049 #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
00050                                              || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
00051
00052 #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
00053                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
00054                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
00055                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
00056                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
00057                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
00058                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
00059                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
00060
00061 #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
00062                                          || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
00063
00064 #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
00065                                                 || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00074   * @{
00075   */
00076 /**
00077   * @}
00078   */
00079 /* Exported functions --------------------------------------------------------*/
00080 /** @addtogroup LPTIM_LL_Exported_Functions
00081   * @{
00082   */
00083
00084 /** @addtogroup LPTIM_LL_EF_Init
00085   * @{
00086   */
00087
00088 /**
00089   * @brief  Set LPTIMx registers to their reset values.
00090   * @param  LPTIMx LP Timer instance
00091   * @retval An ErrorStatus enumeration value:
00092   *          - SUCCESS: LPTIMx registers are de-initialized
00093   *          - ERROR: invalid LPTIMx instance
00094   */
00095 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx)
00096 {
00097   ErrorStatus result = SUCCESS;
00098
00099   /* Check the parameters */
00100   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00101
00102   if (LPTIMx == LPTIM1)
00103   {
00104     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00105     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00106   }
00107   else
00108   {
00109     result = ERROR;
00110   }
00111
00112   return result;
00113 }
00114
00115 /**
00116   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
00117   *         value.
00118   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00119   * @retval None
00120   */
00121 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00122 {
00123   /* Set the default configuration */
00124   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
00125   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
00126   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
00127   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
00128 }
00129
00130 /**
00131   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
00132   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
00133   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
00134   * @param  LPTIMx LP Timer Instance
00135   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00136   * @retval An ErrorStatus enumeration value:
00137   *          - SUCCESS: LPTIMx instance has been initialized
00138   *          - ERROR: LPTIMx instance hasn't been initialized
00139   */
00140 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00141 {
00142   ErrorStatus result = SUCCESS;
00143   /* Check the parameters */
00144   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00145   assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
00146   assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
00147   assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
00148   assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
00149
00150   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
00151      (ENABLE bit is reset to 0).
00152   */
00153   if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
00154   {
00155     result = ERROR;
00156   }
00157   else
00158   {
00159     /* Set CKSEL bitfield according to ClockSource value */
00160     /* Set PRESC bitfield according to Prescaler value */
00161     /* Set WAVE bitfield according to Waveform value */
00162     /* Set WAVEPOL bitfield according to Polarity value */
00163     MODIFY_REG(LPTIMx->CFGR,
00164                (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
00165                LPTIM_InitStruct->ClockSource | \
00166                LPTIM_InitStruct->Prescaler | \
00167                LPTIM_InitStruct->Waveform | \
00168                LPTIM_InitStruct->Polarity);
00169   }
00170
00171   return result;
00172 }
00173
00174 /**
00175   * @brief  Disable the LPTIM instance
00176   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
00177   * @param  LPTIMx Low-Power Timer instance
00178   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00179   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00180   *         stuck in LPTIM interrupt when entering Stop mode" section.
00181   * @retval None
00182   */
00183 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
00184 {
00185   LL_RCC_ClocksTypeDef rcc_clock;
00186   uint32_t tmpclksource = 0;
00187   uint32_t tmpIER;
00188   uint32_t tmpCFGR;
00189   uint32_t tmpCMP;
00190   uint32_t tmpARR;
00191   uint32_t primask_bit;
00192   uint32_t tmpOR;
00193
00194   /* Check the parameters */
00195   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00196
00197   /* Enter critical section */
00198   primask_bit = __get_PRIMASK();
00199   __set_PRIMASK(1) ;
00200
00201   /********** Save LPTIM Config *********/
00202   /* Save LPTIM source clock */
00203   switch ((uint32_t)LPTIMx)
00204   {
00205     case LPTIM1_BASE:
00206       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
00207       break;
00208     default:
00209       break;
00210   }
00211
00212   /* Save LPTIM configuration registers */
00213   tmpIER = LPTIMx->IER;
00214   tmpCFGR = LPTIMx->CFGR;
00215   tmpCMP = LPTIMx->CMP;
00216   tmpARR = LPTIMx->ARR;
00217   tmpOR = LPTIMx->OR;
00218
00219   /************* Reset LPTIM ************/
00220   (void)LL_LPTIM_DeInit(LPTIMx);
00221
00222   /********* Restore LPTIM Config *******/
00223   LL_RCC_GetSystemClocksFreq(&rcc_clock);
00224
00225   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
00226   {
00227     /* Force LPTIM source kernel clock from APB */
00228     switch ((uint32_t)LPTIMx)
00229     {
00230       case LPTIM1_BASE:
00231         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
00232         break;
00233       default:
00234         break;
00235     }
00236
00237     if (tmpCMP != 0UL)
00238     {
00239       /* Restore CMP and ARR registers (LPTIM should be enabled first) */
00240       LPTIMx->CR |= LPTIM_CR_ENABLE;
00241       LPTIMx->CMP = tmpCMP;
00242
00243       /* Polling on CMP write ok status after above restore operation */
00244       do
00245       {
00246         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00247       } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00248
00249       LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
00250     }
00251
00252     if (tmpARR != 0UL)
00253     {
00254       LPTIMx->CR |= LPTIM_CR_ENABLE;
00255       LPTIMx->ARR = tmpARR;
00256
00257       LL_RCC_GetSystemClocksFreq(&rcc_clock);
00258       /* Polling on ARR write ok status after above restore operation */
00259       do
00260       {
00261         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00262       } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00263
00264       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
00265     }
00266
00267
00268     /* Restore LPTIM source kernel clock */
00269     LL_RCC_SetLPTIMClockSource(tmpclksource);
00270   }
00271
00272   /* Restore configuration registers (LPTIM should be disabled first) */
00273   LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
00274   LPTIMx->IER = tmpIER;
00275   LPTIMx->CFGR = tmpCFGR;
00276   LPTIMx->OR = tmpOR;
00277
00278   /* Exit critical section: restore previous priority mask */
00279   __set_PRIMASK(primask_bit);
00280 }
00281
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294
00295
00296 /**
00297   * @}
00298   */
00299
00300 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lptim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_lptim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_LPTIM_H
00021 #define STM32G4xx_LL_LPTIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034
00035
00036 /** @defgroup LPTIM_LL LPTIM
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044
00045 /* Private macros ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053 #endif /*USE_FULL_LL_DRIVER*/
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 #if defined(USE_FULL_LL_DRIVER)
00057 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  LPTIM Init structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
00067                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
00068
00069                                 This feature can be modified afterwards using unitary
00070                                 function @ref LL_LPTIM_SetClockSource().*/
00071
00072   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
00073                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
00074
00075                                 This feature can be modified afterwards using using unitary
00076                                 function @ref LL_LPTIM_SetPrescaler().*/
00077
00078   uint32_t Waveform;       /*!< Specifies the waveform shape.
00079                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
00080
00081                                 This feature can be modified afterwards using unitary
00082                                 function @ref LL_LPTIM_ConfigOutput().*/
00083
00084   uint32_t Polarity;       /*!< Specifies waveform polarity.
00085                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
00086
00087                                 This feature can be modified afterwards using unitary
00088                                 function @ref LL_LPTIM_ConfigOutput().*/
00089 } LL_LPTIM_InitTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094 #endif /* USE_FULL_LL_DRIVER */
00095
00096 /* Exported constants --------------------------------------------------------*/
00097 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
00102   * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
00103   * @{
00104   */
00105 #define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
00106 #define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
00107 #define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
00108 #define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
00109 #define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
00110 #define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
00111 #define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup LPTIM_LL_EC_IT IT Defines
00117   * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
00118   * @{
00119   */
00120 #define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE     /*!< Compare match */
00121 #define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE    /*!< Compare register update OK */
00122 #define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE     /*!< Autoreload match */
00123 #define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE  /*!< External trigger edge event */
00124 #define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE    /*!< Autoreload register update OK */
00125 #define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE       /*!< Counter direction change down to up */
00126 #define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE     /*!< Counter direction change up to down */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
00132   * @{
00133   */
00134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
00135 #define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
00141   * @{
00142   */
00143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
00144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
00150   * @{
00151   */
00152 #define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
00153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
00159   * @{
00160   */
00161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
00162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
00168   * @{
00169   */
00170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
00177   * @{
00178   */
00179 #define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
00180 #define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
00181 #define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
00182 #define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
00183 #define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
00184 #define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
00185 #define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
00186 #define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
00192   * @{
00193   */
00194 #define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
00195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
00196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
00197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
00198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
00199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
00200 #define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/
00201 #define LL_LPTIM_TRIG_SOURCE_COMP2            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP2 output*/
00202 #define LL_LPTIM_TRIG_SOURCE_COMP3            LPTIM_CFGR_TRIGSEL_3                                                 /*!<External input trigger is connected to COMP3 output*/
00203 #define LL_LPTIM_TRIG_SOURCE_COMP4            (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to COMP4 output*/
00204 #if defined(COMP5)
00205 #define LL_LPTIM_TRIG_SOURCE_COMP5            (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP5 output*/
00206 #endif /* COMP5 */
00207 #if defined(COMP6)
00208 #define LL_LPTIM_TRIG_SOURCE_COMP6            (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP6 output*/
00209 #endif /* COMP6 */
00210 #if defined(COMP7)
00211 #define LL_LPTIM_TRIG_SOURCE_COMP7            (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_2)                        /*!<External input trigger is connected to COMP7 output*/
00212 #endif /* COMP7 */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
00218   * @{
00219   */
00220 #define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
00221 #define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
00222 #define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
00223 #define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
00229   * @{
00230   */
00231 #define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
00232 #define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
00233 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
00239   * @{
00240   */
00241 #define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
00242 #define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
00248   * @{
00249   */
00250 #define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
00251 #define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
00252 #define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
00253 #define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
00259   * @{
00260   */
00261 #define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00262 #define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00263 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
00269   * @{
00270   */
00271 #define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00272 #define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00273 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
00279   * @{
00280   */
00281 #define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U
00282 #define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_OR_IN1_0
00283 #define LL_LPTIM_INPUT1_SRC_COMP3        (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
00284 #if defined(COMP5)
00285 #define LL_LPTIM_INPUT1_SRC_COMP5        (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
00286 #endif /* COMP5 */
00287 #if defined(COMP7)
00288 #define LL_LPTIM_INPUT1_SRC_COMP7        (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
00289 #endif /* COMP7 */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
00295   * @{
00296   */
00297 #define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U
00298 #define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_OR_IN2_0
00299 #define LL_LPTIM_INPUT2_SRC_COMP4        (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
00300 #if defined(COMP6)
00301 #define LL_LPTIM_INPUT2_SRC_COMP6        (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
00302 #endif /* COMP6 */
00303 /**
00304   * @}
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Exported macro ------------------------------------------------------------*/
00312 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
00313   * @{
00314   */
00315
00316 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
00317   * @{
00318   */
00319
00320 /**
00321   * @brief  Write a value in LPTIM register
00322   * @param  __INSTANCE__ LPTIM Instance
00323   * @param  __REG__ Register to be written
00324   * @param  __VALUE__ Value to be written in the register
00325   * @retval None
00326   */
00327 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00328
00329 /**
00330   * @brief  Read a value in LPTIM register
00331   * @param  __INSTANCE__ LPTIM Instance
00332   * @param  __REG__ Register to be read
00333   * @retval Register value
00334   */
00335 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00336 /**
00337   * @}
00338   */
00339
00340 /**
00341   * @}
00342   */
00343
00344 /* Exported functions --------------------------------------------------------*/
00345 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
00346   * @{
00347   */
00348
00349 /** Legacy definitions for compatibility purpose
00350 @cond 0
00351   */
00352 #define LL_LPTIM_ClearFLAG_CMPM  LL_LPTIM_ClearFlag_CMPM
00353 #define LL_LPTIM_ClearFLAG_CC1   LL_LPTIM_ClearFlag_CC1
00354 #define LL_LPTIM_ClearFLAG_CC2   LL_LPTIM_ClearFlag_CC2
00355 #define LL_LPTIM_ClearFLAG_CC1O  LL_LPTIM_ClearFlag_CC1O
00356 #define LL_LPTIM_ClearFLAG_CC2O  LL_LPTIM_ClearFlag_CC2O
00357 #define LL_LPTIM_ClearFLAG_ARRM  LL_LPTIM_ClearFlag_ARRM
00358 /**
00359 @endcond
00360   */
00361
00362 #if defined(USE_FULL_LL_DRIVER)
00363 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
00364   * @{
00365   */
00366
00367 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
00368 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00369 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00370 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
00371 /**
00372   * @}
00373   */
00374 #endif /* USE_FULL_LL_DRIVER */
00375
00376 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
00377   * @{
00378   */
00379
00380 /**
00381   * @brief  Enable the LPTIM instance
00382   * @note After setting the ENABLE bit, a delay of two counter clock is needed
00383   *       before the LPTIM instance is actually enabled.
00384   * @rmtoll CR           ENABLE        LL_LPTIM_Enable
00385   * @param  LPTIMx Low-Power Timer instance
00386   * @retval None
00387   */
00388 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
00389 {
00390   SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00391 }
00392
00393 /**
00394   * @brief  Indicates whether the LPTIM instance is enabled.
00395   * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
00396   * @param  LPTIMx Low-Power Timer instance
00397   * @retval State of bit (1 or 0).
00398   */
00399 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
00400 {
00401   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
00402 }
00403
00404 /**
00405   * @brief  Starts the LPTIM counter in the desired mode.
00406   * @note LPTIM instance must be enabled before starting the counter.
00407   * @note It is possible to change on the fly from One Shot mode to
00408   *       Continuous mode.
00409   * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
00410   *         CR           SNGSTRT       LL_LPTIM_StartCounter
00411   * @param  LPTIMx Low-Power Timer instance
00412   * @param  OperatingMode This parameter can be one of the following values:
00413   *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
00414   *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
00415   * @retval None
00416   */
00417 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
00418 {
00419   MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
00420 }
00421
00422 /**
00423   * @brief  Enable reset after read.
00424   * @note After calling this function any read access to LPTIM_CNT
00425   *        register will asynchronously reset the LPTIM_CNT register content.
00426   * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead
00427   * @param  LPTIMx Low-Power Timer instance
00428   * @retval None
00429   */
00430 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00431 {
00432   SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00433 }
00434
00435 /**
00436   * @brief  Disable reset after read.
00437   * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead
00438   * @param  LPTIMx Low-Power Timer instance
00439   * @retval None
00440   */
00441 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00442 {
00443   CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00444 }
00445
00446 /**
00447   * @brief  Indicate whether the reset after read feature is enabled.
00448   * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead
00449   * @param  LPTIMx Low-Power Timer instance
00450   * @retval State of bit (1 or 0).
00451   */
00452 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
00453 {
00454   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
00455 }
00456
00457 /**
00458   * @brief  Reset of the LPTIM_CNT counter register (synchronous).
00459   * @note Due to the synchronous nature of this reset, it only takes
00460   *       place after a synchronization delay of 3 LPTIM core clock cycles
00461   *      (LPTIM core clock may be different from APB clock).
00462   * @note COUNTRST is automatically cleared by hardware
00463   * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n
00464   * @param  LPTIMx Low-Power Timer instance
00465   * @retval None
00466   */
00467 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
00468 {
00469   SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
00470 }
00471
00472 /**
00473   * @brief  Set the LPTIM registers update mode (enable/disable register preload)
00474   * @note This function must be called when the LPTIM instance is disabled.
00475   * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
00476   * @param  LPTIMx Low-Power Timer instance
00477   * @param  UpdateMode This parameter can be one of the following values:
00478   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00479   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00480   * @retval None
00481   */
00482 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
00483 {
00484   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
00485 }
00486
00487 /**
00488   * @brief  Get the LPTIM registers update mode
00489   * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
00490   * @param  LPTIMx Low-Power Timer instance
00491   * @retval Returned value can be one of the following values:
00492   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00493   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00494   */
00495 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
00496 {
00497   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
00498 }
00499
00500 /**
00501   * @brief  Set the auto reload value
00502   * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
00503   * @note After a write to the LPTIMx_ARR register a new write operation to the
00504   *       same register can only be performed when the previous write operation
00505   *       is completed. Any successive write before  the ARROK flag is set, will
00506   *       lead to unpredictable results.
00507   * @note autoreload value be strictly greater than the compare value.
00508   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
00509   * @param  LPTIMx Low-Power Timer instance
00510   * @param  AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
00511   * @retval None
00512   */
00513 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
00514 {
00515   MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
00516 }
00517
00518 /**
00519   * @brief  Get actual auto reload value
00520   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
00521   * @param  LPTIMx Low-Power Timer instance
00522   * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
00523   */
00524 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
00525 {
00526   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
00527 }
00528
00529 /**
00530   * @brief  Set the compare value
00531   * @note After a write to the LPTIMx_CMP register a new write operation to the
00532   *       same register can only be performed when the previous write operation
00533   *       is completed. Any successive write before the CMPOK flag is set, will
00534   *       lead to unpredictable results.
00535   * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
00536   * @param  LPTIMx Low-Power Timer instance
00537   * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00538   * @retval None
00539   */
00540 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
00541 {
00542   MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
00543 }
00544
00545 /**
00546   * @brief  Get actual compare value
00547   * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
00548   * @param  LPTIMx Low-Power Timer instance
00549   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00550   */
00551 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
00552 {
00553   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
00554 }
00555
00556 /**
00557   * @brief  Get actual counter value
00558   * @note When the LPTIM instance is running with an asynchronous clock, reading
00559   *       the LPTIMx_CNT register may return unreliable values. So in this case
00560   *       it is necessary to perform two consecutive read accesses and verify
00561   *       that the two returned values are identical.
00562   * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
00563   * @param  LPTIMx Low-Power Timer instance
00564   * @retval Counter value
00565   */
00566 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
00567 {
00568   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
00569 }
00570
00571 /**
00572   * @brief  Set the counter mode (selection of the LPTIM counter clock source).
00573   * @note The counter mode can be set only when the LPTIM instance is disabled.
00574   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
00575   * @param  LPTIMx Low-Power Timer instance
00576   * @param  CounterMode This parameter can be one of the following values:
00577   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00578   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00579   * @retval None
00580   */
00581 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
00582 {
00583   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
00584 }
00585
00586 /**
00587   * @brief  Get the counter mode
00588   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
00589   * @param  LPTIMx Low-Power Timer instance
00590   * @retval Returned value can be one of the following values:
00591   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00592   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00593   */
00594 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
00595 {
00596   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
00597 }
00598
00599 /**
00600   * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
00601   * @note This function must be called when the LPTIM instance is disabled.
00602   * @note Regarding the LPTIM output polarity the change takes effect
00603   *       immediately, so the output default value will change immediately after
00604   *       the polarity is re-configured, even before the timer is enabled.
00605   * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
00606   *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
00607   * @param  LPTIMx Low-Power Timer instance
00608   * @param  Waveform This parameter can be one of the following values:
00609   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00610   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00611   * @param  Polarity This parameter can be one of the following values:
00612   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00613   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
00617 {
00618   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
00619 }
00620
00621 /**
00622   * @brief  Set  waveform shape
00623   * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
00624   * @param  LPTIMx Low-Power Timer instance
00625   * @param  Waveform This parameter can be one of the following values:
00626   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00627   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
00631 {
00632   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
00633 }
00634
00635 /**
00636   * @brief  Get actual waveform shape
00637   * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
00638   * @param  LPTIMx Low-Power Timer instance
00639   * @retval Returned value can be one of the following values:
00640   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00641   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00642   */
00643 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
00644 {
00645   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
00646 }
00647
00648 /**
00649   * @brief  Set  output polarity
00650   * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
00651   * @param  LPTIMx Low-Power Timer instance
00652   * @param  Polarity This parameter can be one of the following values:
00653   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00654   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00655   * @retval None
00656   */
00657 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
00658 {
00659   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
00660 }
00661
00662 /**
00663   * @brief  Get actual output polarity
00664   * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
00665   * @param  LPTIMx Low-Power Timer instance
00666   * @retval Returned value can be one of the following values:
00667   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00668   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00669   */
00670 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
00671 {
00672   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
00673 }
00674
00675 /**
00676   * @brief  Set actual prescaler division ratio.
00677   * @note This function must be called when the LPTIM instance is disabled.
00678   * @note When the LPTIM is configured to be clocked by an internal clock source
00679   *       and the LPTIM counter is configured to be updated by active edges
00680   *       detected on the LPTIM external Input1, the internal clock provided to
00681   *       the LPTIM must be not be prescaled.
00682   * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
00683   * @param  LPTIMx Low-Power Timer instance
00684   * @param  Prescaler This parameter can be one of the following values:
00685   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00686   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00687   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00688   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00689   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00690   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00691   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00692   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
00696 {
00697   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
00698 }
00699
00700 /**
00701   * @brief  Get actual prescaler division ratio.
00702   * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
00703   * @param  LPTIMx Low-Power Timer instance
00704   * @retval Returned value can be one of the following values:
00705   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00706   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00707   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00708   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00709   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00710   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00711   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00712   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00713   */
00714 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
00715 {
00716   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
00717 }
00718
00719 /**
00720   * @brief  Set LPTIM input 1 source (default GPIO).
00721   * @rmtoll OR      IN1       LL_LPTIM_SetInput1Src
00722   * @param  LPTIMx Low-Power Timer instance
00723   * @param  Src This parameter can be one of the following values:
00724   *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
00725   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
00726   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP3
00727   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP5 (*)
00728   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP7 (*)
00729   *         (*) Value not defined for all devices
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00733 {
00734   MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
00735 }
00736
00737 /**
00738   * @brief  Set LPTIM input 2 source (default GPIO).
00739   * @rmtoll OR      IN2       LL_LPTIM_SetInput2Src
00740   * @param  LPTIMx Low-Power Timer instance
00741   * @param  Src This parameter can be one of the following values:
00742   *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
00743   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
00744   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP4
00745   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP6 (*)
00746   *         (*) Value not defined for all devices
00747   * @retval None
00748   */
00749 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00750 {
00751   MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
00752 }
00753
00754 /**
00755   * @}
00756   */
00757
00758 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Enable the timeout function
00764   * @note This function must be called when the LPTIM instance is disabled.
00765   * @note The first trigger event will start the timer, any successive trigger
00766   *       event will reset the counter and the timer will restart.
00767   * @note The timeout value corresponds to the compare value; if no trigger
00768   *       occurs within the expected time frame, the MCU is waked-up by the
00769   *       compare match event.
00770   * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
00771   * @param  LPTIMx Low-Power Timer instance
00772   * @retval None
00773   */
00774 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
00775 {
00776   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00777 }
00778
00779 /**
00780   * @brief  Disable the timeout function
00781   * @note This function must be called when the LPTIM instance is disabled.
00782   * @note A trigger event arriving when the timer is already started will be
00783   *       ignored.
00784   * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
00785   * @param  LPTIMx Low-Power Timer instance
00786   * @retval None
00787   */
00788 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
00789 {
00790   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00791 }
00792
00793 /**
00794   * @brief  Indicate whether the timeout function is enabled.
00795   * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
00796   * @param  LPTIMx Low-Power Timer instance
00797   * @retval State of bit (1 or 0).
00798   */
00799 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
00800 {
00801   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
00802 }
00803
00804 /**
00805   * @brief  Start the LPTIM counter
00806   * @note This function must be called when the LPTIM instance is disabled.
00807   * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
00808   * @param  LPTIMx Low-Power Timer instance
00809   * @retval None
00810   */
00811 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
00812 {
00813   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
00814 }
00815
00816 /**
00817   * @brief  Configure the external trigger used as a trigger event for the LPTIM.
00818   * @note This function must be called when the LPTIM instance is disabled.
00819   * @note An internal clock source must be present when a digital filter is
00820   *       required for the trigger.
00821   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
00822   *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
00823   *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
00824   * @param  LPTIMx Low-Power Timer instance
00825   * @param  Source This parameter can be one of the following values:
00826   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00827   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00828   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00829   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00830   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00831   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00832   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00833   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00834   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
00835   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
00836   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
00837   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
00838   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
00839   *
00840   *         (*)  Value not defined in all devices. \n
00841   *
00842   * @param  Filter This parameter can be one of the following values:
00843   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00844   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00845   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00846   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00847   * @param  Polarity This parameter can be one of the following values:
00848   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00849   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00850   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00851   * @retval None
00852   */
00853 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
00854 {
00855   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
00856 }
00857
00858 /**
00859   * @brief  Get actual external trigger source.
00860   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
00861   * @param  LPTIMx Low-Power Timer instance
00862   * @retval Returned value can be one of the following values:
00863   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00864   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00865   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00866   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00867   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00868   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00869   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00870   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00871   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
00872   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
00873   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
00874   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
00875   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
00876   *
00877   *         (*)  Value not defined in all devices. \n
00878   */
00879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
00880 {
00881   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
00882 }
00883
00884 /**
00885   * @brief  Get actual external trigger filter.
00886   * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
00887   * @param  LPTIMx Low-Power Timer instance
00888   * @retval Returned value can be one of the following values:
00889   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00890   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00891   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00892   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00893   */
00894 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
00895 {
00896   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
00897 }
00898
00899 /**
00900   * @brief  Get actual external trigger polarity.
00901   * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
00902   * @param  LPTIMx Low-Power Timer instance
00903   * @retval Returned value can be one of the following values:
00904   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00905   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00906   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00907   */
00908 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
00909 {
00910   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
00911 }
00912
00913 /**
00914   * @}
00915   */
00916
00917 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
00918   * @{
00919   */
00920
00921 /**
00922   * @brief  Set the source of the clock used by the LPTIM instance.
00923   * @note This function must be called when the LPTIM instance is disabled.
00924   * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
00925   * @param  LPTIMx Low-Power Timer instance
00926   * @param  ClockSource This parameter can be one of the following values:
00927   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00928   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00929   * @retval None
00930   */
00931 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
00932 {
00933   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
00934 }
00935
00936 /**
00937   * @brief  Get actual LPTIM instance clock source.
00938   * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
00939   * @param  LPTIMx Low-Power Timer instance
00940   * @retval Returned value can be one of the following values:
00941   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00942   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00943   */
00944 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
00945 {
00946   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
00947 }
00948
00949 /**
00950   * @brief  Configure the active edge or edges used by the counter when
00951             the LPTIM is clocked by an external clock source.
00952   * @note This function must be called when the LPTIM instance is disabled.
00953   * @note When both external clock signal edges are considered active ones,
00954   *       the LPTIM must also be clocked by an internal clock source with a
00955   *       frequency equal to at least four times the external clock frequency.
00956   * @note An internal clock source must be present when a digital filter is
00957   *       required for external clock.
00958   * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
00959   *         CFGR         CKPOL         LL_LPTIM_ConfigClock
00960   * @param  LPTIMx Low-Power Timer instance
00961   * @param  ClockFilter This parameter can be one of the following values:
00962   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00963   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00964   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00965   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00966   * @param  ClockPolarity This parameter can be one of the following values:
00967   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00968   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00969   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00970   * @retval None
00971   */
00972 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
00973 {
00974   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
00975 }
00976
00977 /**
00978   * @brief  Get actual clock polarity
00979   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
00980   * @param  LPTIMx Low-Power Timer instance
00981   * @retval Returned value can be one of the following values:
00982   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00983   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00984   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00985   */
00986 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
00987 {
00988   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00989 }
00990
00991 /**
00992   * @brief  Get actual clock digital filter
00993   * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
00994   * @param  LPTIMx Low-Power Timer instance
00995   * @retval Returned value can be one of the following values:
00996   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00997   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00998   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00999   *         @arg @ref LL_LPTIM_CLK_FILTER_8
01000   */
01001 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
01002 {
01003   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
01004 }
01005
01006 /**
01007   * @}
01008   */
01009
01010 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
01011   * @{
01012   */
01013
01014 /**
01015   * @brief  Configure the encoder mode.
01016   * @note This function must be called when the LPTIM instance is disabled.
01017   * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
01018   * @param  LPTIMx Low-Power Timer instance
01019   * @param  EncoderMode This parameter can be one of the following values:
01020   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
01021   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
01022   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
01026 {
01027   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
01028 }
01029
01030 /**
01031   * @brief  Get actual encoder mode.
01032   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
01033   * @param  LPTIMx Low-Power Timer instance
01034   * @retval Returned value can be one of the following values:
01035   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
01036   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
01037   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
01038   */
01039 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
01040 {
01041   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
01042 }
01043
01044 /**
01045   * @brief  Enable the encoder mode
01046   * @note This function must be called when the LPTIM instance is disabled.
01047   * @note In this mode the LPTIM instance must be clocked by an internal clock
01048   *       source. Also, the prescaler division ratio must be equal to 1.
01049   * @note LPTIM instance must be configured in continuous mode prior enabling
01050   *       the encoder mode.
01051   * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
01052   * @param  LPTIMx Low-Power Timer instance
01053   * @retval None
01054   */
01055 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
01056 {
01057   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01058 }
01059
01060 /**
01061   * @brief  Disable the encoder mode
01062   * @note This function must be called when the LPTIM instance is disabled.
01063   * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
01064   * @param  LPTIMx Low-Power Timer instance
01065   * @retval None
01066   */
01067 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
01068 {
01069   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01070 }
01071
01072 /**
01073   * @brief  Indicates whether the LPTIM operates in encoder mode.
01074   * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
01075   * @param  LPTIMx Low-Power Timer instance
01076   * @retval State of bit (1 or 0).
01077   */
01078 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
01079 {
01080   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
01081 }
01082
01083 /**
01084   * @}
01085   */
01086
01087 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
01088   * @{
01089   */
01090
01091
01092 /**
01093   * @brief  Clear the compare match flag (CMPMCF)
01094   * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFlag_CMPM
01095   * @param  LPTIMx Low-Power Timer instance
01096   * @retval None
01097   */
01098 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
01099 {
01100   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
01101 }
01102
01103 /**
01104   * @brief  Inform application whether a compare match interrupt has occurred.
01105   * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
01106   * @param  LPTIMx Low-Power Timer instance
01107   * @retval State of bit (1 or 0).
01108   */
01109 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
01110 {
01111   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
01112 }
01113
01114 /**
01115   * @brief  Clear the autoreload match flag (ARRMCF)
01116   * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFlag_ARRM
01117   * @param  LPTIMx Low-Power Timer instance
01118   * @retval None
01119   */
01120 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
01121 {
01122   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
01123 }
01124
01125 /**
01126   * @brief  Inform application whether a autoreload match interrupt has occurred.
01127   * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
01128   * @param  LPTIMx Low-Power Timer instance
01129   * @retval State of bit (1 or 0).
01130   */
01131 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
01132 {
01133   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
01134 }
01135
01136 /**
01137   * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
01138   * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
01139   * @param  LPTIMx Low-Power Timer instance
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01143 {
01144   SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
01145 }
01146
01147 /**
01148   * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
01149   * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
01150   * @param  LPTIMx Low-Power Timer instance
01151   * @retval State of bit (1 or 0).
01152   */
01153 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
01154 {
01155   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
01156 }
01157
01158 /**
01159   * @brief  Clear the compare register update interrupt flag (CMPOKCF).
01160   * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
01161   * @param  LPTIMx Low-Power Timer instance
01162   * @retval None
01163   */
01164 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01165 {
01166   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
01167 }
01168
01169 /**
01170   * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
01171             completed. If so, a new one can be initiated.
01172   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
01173   * @param  LPTIMx Low-Power Timer instance
01174   * @retval State of bit (1 or 0).
01175   */
01176 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
01177 {
01178   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
01179 }
01180
01181 /**
01182   * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
01183   * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
01184   * @param  LPTIMx Low-Power Timer instance
01185   * @retval None
01186   */
01187 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01188 {
01189   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
01190 }
01191
01192 /**
01193   * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
01194             completed. If so, a new one can be initiated.
01195   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
01196   * @param  LPTIMx Low-Power Timer instance
01197   * @retval State of bit (1 or 0).
01198   */
01199 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
01200 {
01201   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
01202 }
01203
01204 /**
01205   * @brief  Clear the counter direction change to up interrupt flag (UPCF).
01206   * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
01207   * @param  LPTIMx Low-Power Timer instance
01208   * @retval None
01209   */
01210 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
01211 {
01212   SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
01213 }
01214
01215 /**
01216   * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
01217             operates in encoder mode).
01218   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
01219   * @param  LPTIMx Low-Power Timer instance
01220   * @retval State of bit (1 or 0).
01221   */
01222 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
01223 {
01224   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
01225 }
01226
01227 /**
01228   * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
01229   * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
01230   * @param  LPTIMx Low-Power Timer instance
01231   * @retval None
01232   */
01233 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01234 {
01235   SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
01236 }
01237
01238 /**
01239   * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
01240             operates in encoder mode).
01241   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
01242   * @param  LPTIMx Low-Power Timer instance
01243   * @retval State of bit (1 or 0).
01244   */
01245 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
01246 {
01247   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
01248 }
01249
01250 /**
01251   * @}
01252   */
01253
01254 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
01255   * @{
01256   */
01257
01258 /**
01259   * @brief  Enable compare match interrupt (CMPMIE).
01260   * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
01261   * @param  LPTIMx Low-Power Timer instance
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01265 {
01266   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01267 }
01268
01269 /**
01270   * @brief  Disable compare match interrupt (CMPMIE).
01271   * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
01272   * @param  LPTIMx Low-Power Timer instance
01273   * @retval None
01274   */
01275 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01276 {
01277   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01278 }
01279
01280 /**
01281   * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
01282   * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
01283   * @param  LPTIMx Low-Power Timer instance
01284   * @retval State of bit (1 or 0).
01285   */
01286 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
01287 {
01288   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
01289 }
01290
01291 /**
01292   * @brief  Enable autoreload match interrupt (ARRMIE).
01293   * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
01294   * @param  LPTIMx Low-Power Timer instance
01295   * @retval None
01296   */
01297 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01298 {
01299   SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01300 }
01301
01302 /**
01303   * @brief  Disable autoreload match interrupt (ARRMIE).
01304   * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
01305   * @param  LPTIMx Low-Power Timer instance
01306   * @retval None
01307   */
01308 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01309 {
01310   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01311 }
01312
01313 /**
01314   * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
01315   * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
01316   * @param  LPTIMx Low-Power Timer instance
01317   * @retval State of bit (1 or 0).
01318   */
01319 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
01320 {
01321   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
01322 }
01323
01324 /**
01325   * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
01326   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
01327   * @param  LPTIMx Low-Power Timer instance
01328   * @retval None
01329   */
01330 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01331 {
01332   SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01333 }
01334
01335 /**
01336   * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
01337   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
01338   * @param  LPTIMx Low-Power Timer instance
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01342 {
01343   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01344 }
01345
01346 /**
01347   * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
01348   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
01349   * @param  LPTIMx Low-Power Timer instance
01350   * @retval State of bit (1 or 0).
01351   */
01352 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
01353 {
01354   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
01355 }
01356
01357 /**
01358   * @brief  Enable compare register write completed interrupt (CMPOKIE).
01359   * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
01360   * @param  LPTIMx Low-Power Timer instance
01361   * @retval None
01362   */
01363 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01364 {
01365   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01366 }
01367
01368 /**
01369   * @brief  Disable compare register write completed interrupt (CMPOKIE).
01370   * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
01371   * @param  LPTIMx Low-Power Timer instance
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01375 {
01376   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01377 }
01378
01379 /**
01380   * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
01381   * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
01382   * @param  LPTIMx Low-Power Timer instance
01383   * @retval State of bit (1 or 0).
01384   */
01385 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
01386 {
01387   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
01388 }
01389
01390 /**
01391   * @brief  Enable autoreload register write completed interrupt (ARROKIE).
01392   * @rmtoll IER         ARROKIE       LL_LPTIM_EnableIT_ARROK
01393   * @param  LPTIMx Low-Power Timer instance
01394   * @retval None
01395   */
01396 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01397 {
01398   SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01399 }
01400
01401 /**
01402   * @brief  Disable autoreload register write completed interrupt (ARROKIE).
01403   * @rmtoll IER         ARROKIE       LL_LPTIM_DisableIT_ARROK
01404   * @param  LPTIMx Low-Power Timer instance
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01408 {
01409   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01410 }
01411
01412 /**
01413   * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
01414   * @rmtoll IER         ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
01415   * @param  LPTIMx Low-Power Timer instance
01416   * @retval State of bit(1 or 0).
01417   */
01418 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
01419 {
01420   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
01421 }
01422
01423 /**
01424   * @brief  Enable direction change to up interrupt (UPIE).
01425   * @rmtoll IER         UPIE          LL_LPTIM_EnableIT_UP
01426   * @param  LPTIMx Low-Power Timer instance
01427   * @retval None
01428   */
01429 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
01430 {
01431   SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01432 }
01433
01434 /**
01435   * @brief  Disable direction change to up interrupt (UPIE).
01436   * @rmtoll IER         UPIE          LL_LPTIM_DisableIT_UP
01437   * @param  LPTIMx Low-Power Timer instance
01438   * @retval None
01439   */
01440 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
01441 {
01442   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01443 }
01444
01445 /**
01446   * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
01447   * @rmtoll IER         UPIE          LL_LPTIM_IsEnabledIT_UP
01448   * @param  LPTIMx Low-Power Timer instance
01449   * @retval State of bit(1 or 0).
01450   */
01451 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
01452 {
01453   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
01454 }
01455
01456 /**
01457   * @brief  Enable direction change to down interrupt (DOWNIE).
01458   * @rmtoll IER         DOWNIE        LL_LPTIM_EnableIT_DOWN
01459   * @param  LPTIMx Low-Power Timer instance
01460   * @retval None
01461   */
01462 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01463 {
01464   SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01465 }
01466
01467 /**
01468   * @brief  Disable direction change to down interrupt (DOWNIE).
01469   * @rmtoll IER         DOWNIE        LL_LPTIM_DisableIT_DOWN
01470   * @param  LPTIMx Low-Power Timer instance
01471   * @retval None
01472   */
01473 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01474 {
01475   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01476 }
01477
01478 /**
01479   * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
01480   * @rmtoll IER         DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
01481   * @param  LPTIMx Low-Power Timer instance
01482   * @retval State of bit(1 or 0).
01483   */
01484 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
01485 {
01486   return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
01487 }
01488
01489 /**
01490   * @}
01491   */
01492
01493 /**
01494   * @}
01495   */
01496
01497 /**
01498   * @}
01499   */
01500
01501
01502
01503 /**
01504   * @}
01505   */
01506
01507 #ifdef __cplusplus
01508 }
01509 #endif
01510
01511 #endif /* STM32G4xx_LL_LPTIM_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lpuart.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_lpuart.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_lpuart.c
00004   * @author  MCD Application Team
00005   * @brief   LPUART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_lpuart.h"
00022 #include "stm32g4xx_ll_rcc.h"
00023 #include "stm32g4xx_ll_bus.h"
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPUART1)
00035
00036 /** @addtogroup LPUART_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup LPUART_LL_Private_Constants
00044   * @{
00045   */
00046
00047 /* Definition of default baudrate value used for LPUART initialisation */
00048 #define LPUART_DEFAULT_BAUDRATE          (9600U)
00049
00050 /**
00051   * @}
00052   */
00053
00054
00055 /* Private macros ------------------------------------------------------------*/
00056 /** @addtogroup LPUART_LL_Private_Macros
00057   * @{
00058   */
00059
00060 /* Check of parameters for configuration of LPUART registers                  */
00061
00062 #define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
00063                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
00064                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
00065                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
00066                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
00067                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
00068                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
00069                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
00070                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
00071                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
00072                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
00073                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
00074
00075 /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
00076 /*              value :                                                       */
00077 /*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
00078 /*                - LPUART_BRR register value should be >= 0x300              */
00079 /*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
00080 /*              Baudrate specified by the user should belong to [8, 50000000].*/
00081 #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 50000000U) && ((__BAUDRATE__) >= 8U))
00082
00083 /* __VALUE__ BRR content must be greater than or equal to 0x300. */
00084 #define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
00085
00086 /* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
00087 #define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
00088
00089 #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
00090                                            || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
00091                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
00092                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
00093
00094 #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
00095                                         || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
00096                                         || ((__VALUE__) == LL_LPUART_PARITY_ODD))
00097
00098 #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
00099                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
00100                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
00101
00102 #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
00103                                           || ((__VALUE__) == LL_LPUART_STOPBITS_2))
00104
00105 #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
00106                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
00107                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
00108                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Private function prototypes -----------------------------------------------*/
00115
00116 /* Exported functions --------------------------------------------------------*/
00117 /** @addtogroup LPUART_LL_Exported_Functions
00118   * @{
00119   */
00120
00121 /** @addtogroup LPUART_LL_EF_Init
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  De-initialize LPUART registers (Registers restored to their default values).
00127   * @param  LPUARTx LPUART Instance
00128   * @retval An ErrorStatus enumeration value:
00129   *          - SUCCESS: LPUART registers are de-initialized
00130   *          - ERROR: not applicable
00131   */
00132 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
00133 {
00134   ErrorStatus status = SUCCESS;
00135
00136   /* Check the parameters */
00137   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00138
00139   if (LPUARTx == LPUART1)
00140   {
00141     /* Force reset of LPUART peripheral */
00142     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);
00143
00144     /* Release reset of LPUART peripheral */
00145     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);
00146   }
00147   else
00148   {
00149     status = ERROR;
00150   }
00151
00152   return (status);
00153 }
00154
00155 /**
00156   * @brief  Initialize LPUART registers according to the specified
00157   *         parameters in LPUART_InitStruct.
00158   * @note   As some bits in LPUART configuration registers can only be written when
00159   *         the LPUART is disabled (USART_CR1_UE bit =0),
00160   *         LPUART Peripheral should be in disabled state prior calling this function.
00161   *         Otherwise, ERROR result will be returned.
00162   * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
00163   * @param  LPUARTx LPUART Instance
00164   * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00165   *         that contains the configuration information for the specified LPUART peripheral.
00166   * @retval An ErrorStatus enumeration value:
00167   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
00168   *          - ERROR: Problem occurred during LPUART Registers initialization
00169   */
00170 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
00171 {
00172   ErrorStatus status = ERROR;
00173   uint32_t periphclk;
00174
00175   /* Check the parameters */
00176   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00177   assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
00178   assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
00179   assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
00180   assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
00181   assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
00182   assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
00183   assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
00184
00185   /* LPUART needs to be in disabled state, in order to be able to configure some bits in
00186      CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
00187   if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
00188   {
00189     /*---------------------------- LPUART CR1 Configuration -----------------------
00190      * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
00191      * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
00192      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
00193      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
00194      */
00195     MODIFY_REG(LPUARTx->CR1,
00196                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
00197                (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
00198
00199     /*---------------------------- LPUART CR2 Configuration -----------------------
00200      * Configure LPUARTx CR2 (Stop bits) with parameters:
00201      * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
00202      */
00203     LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
00204
00205     /*---------------------------- LPUART CR3 Configuration -----------------------
00206      * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
00207      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
00208      *   to LPUART_InitStruct->HardwareFlowControl value.
00209      */
00210     LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
00211
00212     /*---------------------------- LPUART BRR Configuration -----------------------
00213      * Retrieve Clock frequency used for LPUART Peripheral
00214      */
00215     periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00216
00217     /* Configure the LPUART Baud Rate :
00218        - prescaler value is required
00219        - valid baud rate value (different from 0) is required
00220        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00221     */
00222     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00223         && (LPUART_InitStruct->BaudRate != 0U))
00224     {
00225       status = SUCCESS;
00226       LL_LPUART_SetBaudRate(LPUARTx,
00227                             periphclk,
00228                             LPUART_InitStruct->PrescalerValue,
00229                             LPUART_InitStruct->BaudRate);
00230
00231       /* Check BRR is greater than or equal to 0x300 */
00232       assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
00233
00234       /* Check BRR is lower than or equal to 0xFFFFF */
00235       assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
00236     }
00237
00238     /*---------------------------- LPUART PRESC Configuration -----------------------
00239      * Configure LPUARTx PRESC (Prescaler) with parameters:
00240      * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
00241      */
00242     LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
00243   }
00244
00245   return (status);
00246 }
00247
00248 /**
00249   * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
00250   * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00251   *                          whose fields will be set to default values.
00252   * @retval None
00253   */
00254
00255 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
00256 {
00257   /* Set LPUART_InitStruct fields to default values */
00258   LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
00259   LPUART_InitStruct->BaudRate            = LPUART_DEFAULT_BAUDRATE;
00260   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
00261   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
00262   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
00263   LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
00264   LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
00265 }
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #endif /* LPUART1 */
00280
00281 /**
00282   * @}
00283   */
00284
00285 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_lpuart.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_lpuart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPUART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_LPUART_H
00021 #define STM32G4xx_LL_LPUART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPUART1)
00035
00036 /** @defgroup LPUART_LL LPUART
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
00043   * @{
00044   */
00045 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
00046 static const uint16_t LPUART_PRESCALER_TAB[] =
00047 {
00048   (uint16_t)1,
00049   (uint16_t)2,
00050   (uint16_t)4,
00051   (uint16_t)6,
00052   (uint16_t)8,
00053   (uint16_t)10,
00054   (uint16_t)12,
00055   (uint16_t)16,
00056   (uint16_t)32,
00057   (uint16_t)64,
00058   (uint16_t)128,
00059   (uint16_t)256
00060 };
00061 /**
00062   * @}
00063   */
00064
00065 /* Private constants ---------------------------------------------------------*/
00066 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00067   * @{
00068   */
00069 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00070 #define LPUART_LPUARTDIV_FREQ_MUL     256U
00071 #define LPUART_BRR_MASK               0x000FFFFFU
00072 #define LPUART_BRR_MIN_VALUE          0x00000300U
00073 /**
00074   * @}
00075   */
00076
00077
00078 /* Private macros ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086 #endif /*USE_FULL_LL_DRIVER*/
00087
00088 /* Exported types ------------------------------------------------------------*/
00089 #if defined(USE_FULL_LL_DRIVER)
00090 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00091   * @{
00092   */
00093
00094 /**
00095   * @brief LL LPUART Init Structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00100                                            This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
00101
00102                                            This feature can be modified afterwards using unitary
00103                                            function @ref LL_LPUART_SetPrescaler().*/
00104
00105   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00106
00107                                            This feature can be modified afterwards using unitary
00108                                            function @ref LL_LPUART_SetBaudRate().*/
00109
00110   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00111                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00112
00113                                            This feature can be modified afterwards using unitary
00114                                            function @ref LL_LPUART_SetDataWidth().*/
00115
00116   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00117                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00118
00119                                            This feature can be modified afterwards using unitary
00120                                            function @ref LL_LPUART_SetStopBitsLength().*/
00121
00122   uint32_t Parity;                    /*!< Specifies the parity mode.
00123                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00124
00125                                            This feature can be modified afterwards using unitary
00126                                            function @ref LL_LPUART_SetParity().*/
00127
00128   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00129                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00130
00131                                            This feature can be modified afterwards using unitary
00132                                            function @ref LL_LPUART_SetTransferDirection().*/
00133
00134   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00135                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00136
00137                                            This feature can be modified afterwards using unitary
00138                                            function @ref LL_LPUART_SetHWFlowCtrl().*/
00139
00140 } LL_LPUART_InitTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145 #endif /* USE_FULL_LL_DRIVER */
00146
00147 /* Exported constants --------------------------------------------------------*/
00148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00149   * @{
00150   */
00151
00152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00153   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00154   * @{
00155   */
00156 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
00157 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
00158 #define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
00159 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
00160 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
00161 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
00162 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
00163 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
00164 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00170   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00171   * @{
00172   */
00173 #define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
00174 #define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
00175 #define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
00176 #define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
00177 #define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
00178 #define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
00179 #define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
00180 #define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
00181 #define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
00182 #define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
00183 #define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
00184 #define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
00185 #define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
00186 #define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
00187 #define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
00188 #define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
00189 #define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
00190 #define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
00191 #define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
00192 #define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
00193 #define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup LPUART_LL_EC_IT IT Defines
00199   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00200   * @{
00201   */
00202 #define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
00203 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
00204                                                                    interrupt enable */
00205 #define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
00206 #define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
00207                                                                    not full interrupt enable */
00208 #define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
00209 #define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
00210 #define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
00211 #define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
00212 #define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
00213 #define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
00214 #define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
00215 #define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
00216 #define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00222   * @{
00223   */
00224 #define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
00225 #define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
00226 #define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
00227 #define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
00228 #define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
00229 #define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00235   * @{
00236   */
00237 #define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
00238 #define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
00239 #define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
00240 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00246   * @{
00247   */
00248 #define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
00249 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
00250 #define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00256   * @{
00257   */
00258 #define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
00259 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00265   * @{
00266   */
00267 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00268 #define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00269 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
00275   * @{
00276   */
00277 #define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
00278 #define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
00279 #define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
00280 #define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
00281                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
00282 #define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
00283 #define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
00284                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
00285 #define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
00286                                     USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
00287 #define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
00288                                     USART_PRESC_PRESCALER_1 |\
00289                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
00290 #define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
00291 #define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
00292                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
00293 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
00294                                     USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
00295 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
00296                                     USART_PRESC_PRESCALER_1 |\
00297                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00303   * @{
00304   */
00305 #define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
00306 #define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00312   * @{
00313   */
00314 #define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
00315 #define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00321   * @{
00322   */
00323 #define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
00324 #define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00330   * @{
00331   */
00332 #define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
00333 #define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00339   * @{
00340   */
00341 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
00342                                                                in positive/direct logic. (1=H, 0=L)                  */
00343 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
00344                                                                in negative/inverse logic. (1=L, 0=H).
00345                                                                The parity bit is also inverted.                      */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00351   * @{
00352   */
00353 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
00354                                                             following the start bit */
00355 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
00356                                                             following the start bit */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00362   * @{
00363   */
00364 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
00365 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00371   * @{
00372   */
00373 #define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
00374 #define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
00375                                                                            when there is space in the receive buffer  */
00376 #define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
00377                                                                            when the nCTS input is asserted (tied to 0)*/
00378 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00384   * @{
00385   */
00386 #define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
00387 #define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
00388 #define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00394   * @{
00395   */
00396 #define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
00397 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00403   * @{
00404   */
00405 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
00406 #define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /* Exported macro ------------------------------------------------------------*/
00416 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00417   * @{
00418   */
00419
00420 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Write a value in LPUART register
00426   * @param  __INSTANCE__ LPUART Instance
00427   * @param  __REG__ Register to be written
00428   * @param  __VALUE__ Value to be written in the register
00429   * @retval None
00430   */
00431 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00432
00433 /**
00434   * @brief  Read a value in LPUART register
00435   * @param  __INSTANCE__ LPUART Instance
00436   * @param  __REG__ Register to be read
00437   * @retval Register value
00438   */
00439 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00445   * @{
00446   */
00447
00448 /**
00449   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00450   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00451   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00452   * @param  __PRESCALER__ This parameter can be one of the following values:
00453   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00454   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00455   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00456   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00457   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00458   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00459   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00460   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00461   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00462   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00463   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00464   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00465   * @param  __BAUDRATE__ Baud Rate value to achieve
00466   * @retval LPUARTDIV value to be used for BRR register filling
00467   */
00468 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
00469   ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
00470       * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00471
00472 /**
00473   * @}
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /* Exported functions --------------------------------------------------------*/
00481 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00482   * @{
00483   */
00484
00485 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00486   * @{
00487   */
00488
00489 /**
00490   * @brief  LPUART Enable
00491   * @rmtoll CR1          UE            LL_LPUART_Enable
00492   * @param  LPUARTx LPUART Instance
00493   * @retval None
00494   */
00495 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00496 {
00497   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00498 }
00499
00500 /**
00501   * @brief  LPUART Disable
00502   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00503   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00504   *         flags, in the LPUARTx_ISR are set to their default values.
00505   * @note   In order to go into low-power mode without generating errors on the line,
00506   *         the TE bit must be reset before and the software must wait
00507   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00508   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00509   *         be disabled before resetting the UE bit.
00510   * @rmtoll CR1          UE            LL_LPUART_Disable
00511   * @param  LPUARTx LPUART Instance
00512   * @retval None
00513   */
00514 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00515 {
00516   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00517 }
00518
00519 /**
00520   * @brief  Indicate if LPUART is enabled
00521   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00522   * @param  LPUARTx LPUART Instance
00523   * @retval State of bit (1 or 0).
00524   */
00525 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
00526 {
00527   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00528 }
00529
00530 /**
00531   * @brief  FIFO Mode Enable
00532   * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
00533   * @param  LPUARTx LPUART Instance
00534   * @retval None
00535   */
00536 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
00537 {
00538   SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00539 }
00540
00541 /**
00542   * @brief  FIFO Mode Disable
00543   * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
00544   * @param  LPUARTx LPUART Instance
00545   * @retval None
00546   */
00547 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
00548 {
00549   CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00550 }
00551
00552 /**
00553   * @brief  Indicate if FIFO Mode is enabled
00554   * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
00555   * @param  LPUARTx LPUART Instance
00556   * @retval State of bit (1 or 0).
00557   */
00558 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
00559 {
00560   return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00561 }
00562
00563 /**
00564   * @brief  Configure TX FIFO Threshold
00565   * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
00566   * @param  LPUARTx LPUART Instance
00567   * @param  Threshold This parameter can be one of the following values:
00568   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00569   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00570   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00571   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00572   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00573   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00577 {
00578   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00579 }
00580
00581 /**
00582   * @brief  Return TX FIFO Threshold Configuration
00583   * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
00584   * @param  LPUARTx LPUART Instance
00585   * @retval Returned value can be one of the following values:
00586   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00587   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00588   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00589   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00590   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00591   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00592   */
00593 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
00594 {
00595   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00596 }
00597
00598 /**
00599   * @brief  Configure RX FIFO Threshold
00600   * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
00601   * @param  LPUARTx LPUART Instance
00602   * @param  Threshold This parameter can be one of the following values:
00603   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00604   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00605   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00606   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00607   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00608   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00609   * @retval None
00610   */
00611 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00612 {
00613   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00614 }
00615
00616 /**
00617   * @brief  Return RX FIFO Threshold Configuration
00618   * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
00619   * @param  LPUARTx LPUART Instance
00620   * @retval Returned value can be one of the following values:
00621   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00622   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00623   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00624   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00625   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00626   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00627   */
00628 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
00629 {
00630   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00631 }
00632
00633 /**
00634   * @brief  Configure TX and RX FIFOs Threshold
00635   * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
00636   *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
00637   * @param  LPUARTx LPUART Instance
00638   * @param  TXThreshold This parameter can be one of the following values:
00639   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00640   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00641   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00642   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00643   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00644   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00645   * @param  RXThreshold This parameter can be one of the following values:
00646   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00647   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00648   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00649   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00650   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00651   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00655 {
00656   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
00657                     (RXThreshold << USART_CR3_RXFTCFG_Pos));
00658 }
00659
00660 /**
00661   * @brief  LPUART enabled in STOP Mode
00662   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00663   *         LPUART clock selection is HSI or LSE in RCC.
00664   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00665   * @param  LPUARTx LPUART Instance
00666   * @retval None
00667   */
00668 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00669 {
00670   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00671 }
00672
00673 /**
00674   * @brief  LPUART disabled in STOP Mode
00675   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00676   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00677   * @param  LPUARTx LPUART Instance
00678   * @retval None
00679   */
00680 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00681 {
00682   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00683 }
00684
00685 /**
00686   * @brief  Indicate if LPUART is enabled in STOP Mode
00687   *         (able to wake up MCU from Stop mode or not)
00688   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00689   * @param  LPUARTx LPUART Instance
00690   * @retval State of bit (1 or 0).
00691   */
00692 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
00693 {
00694   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00695 }
00696
00697 /**
00698   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00699   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00700   * @param  LPUARTx LPUART Instance
00701   * @retval None
00702   */
00703 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00704 {
00705   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00706 }
00707
00708 /**
00709   * @brief  Receiver Disable
00710   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00711   * @param  LPUARTx LPUART Instance
00712   * @retval None
00713   */
00714 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00715 {
00716   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00717 }
00718
00719 /**
00720   * @brief  Transmitter Enable
00721   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00722   * @param  LPUARTx LPUART Instance
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00726 {
00727   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00728 }
00729
00730 /**
00731   * @brief  Transmitter Disable
00732   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00733   * @param  LPUARTx LPUART Instance
00734   * @retval None
00735   */
00736 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00737 {
00738   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00739 }
00740
00741 /**
00742   * @brief  Configure simultaneously enabled/disabled states
00743   *         of Transmitter and Receiver
00744   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00745   *         CR1          TE            LL_LPUART_SetTransferDirection
00746   * @param  LPUARTx LPUART Instance
00747   * @param  TransferDirection This parameter can be one of the following values:
00748   *         @arg @ref LL_LPUART_DIRECTION_NONE
00749   *         @arg @ref LL_LPUART_DIRECTION_RX
00750   *         @arg @ref LL_LPUART_DIRECTION_TX
00751   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00752   * @retval None
00753   */
00754 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00755 {
00756   ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00757 }
00758
00759 /**
00760   * @brief  Return enabled/disabled states of Transmitter and Receiver
00761   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00762   *         CR1          TE            LL_LPUART_GetTransferDirection
00763   * @param  LPUARTx LPUART Instance
00764   * @retval Returned value can be one of the following values:
00765   *         @arg @ref LL_LPUART_DIRECTION_NONE
00766   *         @arg @ref LL_LPUART_DIRECTION_RX
00767   *         @arg @ref LL_LPUART_DIRECTION_TX
00768   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00769   */
00770 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
00771 {
00772   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00773 }
00774
00775 /**
00776   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00777   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00778   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00779   *         (depending on data width) and parity is checked on the received data.
00780   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00781   *         CR1          PCE           LL_LPUART_SetParity
00782   * @param  LPUARTx LPUART Instance
00783   * @param  Parity This parameter can be one of the following values:
00784   *         @arg @ref LL_LPUART_PARITY_NONE
00785   *         @arg @ref LL_LPUART_PARITY_EVEN
00786   *         @arg @ref LL_LPUART_PARITY_ODD
00787   * @retval None
00788   */
00789 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00790 {
00791   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00792 }
00793
00794 /**
00795   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00796   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00797   *         CR1          PCE           LL_LPUART_GetParity
00798   * @param  LPUARTx LPUART Instance
00799   * @retval Returned value can be one of the following values:
00800   *         @arg @ref LL_LPUART_PARITY_NONE
00801   *         @arg @ref LL_LPUART_PARITY_EVEN
00802   *         @arg @ref LL_LPUART_PARITY_ODD
00803   */
00804 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
00805 {
00806   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00807 }
00808
00809 /**
00810   * @brief  Set Receiver Wake Up method from Mute mode.
00811   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00812   * @param  LPUARTx LPUART Instance
00813   * @param  Method This parameter can be one of the following values:
00814   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00815   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00819 {
00820   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00821 }
00822
00823 /**
00824   * @brief  Return Receiver Wake Up method from Mute mode
00825   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00826   * @param  LPUARTx LPUART Instance
00827   * @retval Returned value can be one of the following values:
00828   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00829   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00830   */
00831 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
00832 {
00833   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00834 }
00835
00836 /**
00837   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00838   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00839   * @param  LPUARTx LPUART Instance
00840   * @param  DataWidth This parameter can be one of the following values:
00841   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00842   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00843   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00847 {
00848   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00849 }
00850
00851 /**
00852   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00853   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00854   * @param  LPUARTx LPUART Instance
00855   * @retval Returned value can be one of the following values:
00856   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00857   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00858   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00859   */
00860 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
00861 {
00862   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00863 }
00864
00865 /**
00866   * @brief  Allow switch between Mute Mode and Active mode
00867   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00868   * @param  LPUARTx LPUART Instance
00869   * @retval None
00870   */
00871 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00872 {
00873   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00874 }
00875
00876 /**
00877   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00878   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00879   * @param  LPUARTx LPUART Instance
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00883 {
00884   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00885 }
00886
00887 /**
00888   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00889   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00890   * @param  LPUARTx LPUART Instance
00891   * @retval State of bit (1 or 0).
00892   */
00893 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
00894 {
00895   return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
00896 }
00897
00898 /**
00899   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
00900   * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
00901   * @param  LPUARTx LPUART Instance
00902   * @param  PrescalerValue This parameter can be one of the following values:
00903   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00904   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00905   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00906   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00907   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00908   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00909   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00910   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00911   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00912   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00913   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00914   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00915   * @retval None
00916   */
00917 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
00918 {
00919   MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
00920 }
00921
00922 /**
00923   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
00924   * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
00925   * @param  LPUARTx LPUART Instance
00926   * @retval Returned value can be one of the following values:
00927   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00928   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00929   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00930   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00931   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00932   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00933   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00934   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00935   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00936   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00937   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00938   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00939   */
00940 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
00941 {
00942   return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
00943 }
00944
00945 /**
00946   * @brief  Set the length of the stop bits
00947   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00948   * @param  LPUARTx LPUART Instance
00949   * @param  StopBits This parameter can be one of the following values:
00950   *         @arg @ref LL_LPUART_STOPBITS_1
00951   *         @arg @ref LL_LPUART_STOPBITS_2
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00955 {
00956   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00957 }
00958
00959 /**
00960   * @brief  Retrieve the length of the stop bits
00961   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00962   * @param  LPUARTx LPUART Instance
00963   * @retval Returned value can be one of the following values:
00964   *         @arg @ref LL_LPUART_STOPBITS_1
00965   *         @arg @ref LL_LPUART_STOPBITS_2
00966   */
00967 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
00968 {
00969   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00970 }
00971
00972 /**
00973   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00974   * @note   Call of this function is equivalent to following function call sequence :
00975   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00976   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00977   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00978   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00979   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00980   *         CR1          M             LL_LPUART_ConfigCharacter\n
00981   *         CR2          STOP          LL_LPUART_ConfigCharacter
00982   * @param  LPUARTx LPUART Instance
00983   * @param  DataWidth This parameter can be one of the following values:
00984   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00985   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00986   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00987   * @param  Parity This parameter can be one of the following values:
00988   *         @arg @ref LL_LPUART_PARITY_NONE
00989   *         @arg @ref LL_LPUART_PARITY_EVEN
00990   *         @arg @ref LL_LPUART_PARITY_ODD
00991   * @param  StopBits This parameter can be one of the following values:
00992   *         @arg @ref LL_LPUART_STOPBITS_1
00993   *         @arg @ref LL_LPUART_STOPBITS_2
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00997                                                uint32_t StopBits)
00998 {
00999   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01000   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
01001 }
01002
01003 /**
01004   * @brief  Configure TX/RX pins swapping setting.
01005   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
01006   * @param  LPUARTx LPUART Instance
01007   * @param  SwapConfig This parameter can be one of the following values:
01008   *         @arg @ref LL_LPUART_TXRX_STANDARD
01009   *         @arg @ref LL_LPUART_TXRX_SWAPPED
01010   * @retval None
01011   */
01012 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
01013 {
01014   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
01015 }
01016
01017 /**
01018   * @brief  Retrieve TX/RX pins swapping configuration.
01019   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
01020   * @param  LPUARTx LPUART Instance
01021   * @retval Returned value can be one of the following values:
01022   *         @arg @ref LL_LPUART_TXRX_STANDARD
01023   *         @arg @ref LL_LPUART_TXRX_SWAPPED
01024   */
01025 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
01026 {
01027   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
01028 }
01029
01030 /**
01031   * @brief  Configure RX pin active level logic
01032   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
01033   * @param  LPUARTx LPUART Instance
01034   * @param  PinInvMethod This parameter can be one of the following values:
01035   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01036   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01040 {
01041   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01042 }
01043
01044 /**
01045   * @brief  Retrieve RX pin active level logic configuration
01046   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
01047   * @param  LPUARTx LPUART Instance
01048   * @retval Returned value can be one of the following values:
01049   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01050   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01051   */
01052 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
01053 {
01054   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
01055 }
01056
01057 /**
01058   * @brief  Configure TX pin active level logic
01059   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
01060   * @param  LPUARTx LPUART Instance
01061   * @param  PinInvMethod This parameter can be one of the following values:
01062   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01063   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01064   * @retval None
01065   */
01066 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01067 {
01068   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01069 }
01070
01071 /**
01072   * @brief  Retrieve TX pin active level logic configuration
01073   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
01074   * @param  LPUARTx LPUART Instance
01075   * @retval Returned value can be one of the following values:
01076   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01077   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01078   */
01079 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
01080 {
01081   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
01082 }
01083
01084 /**
01085   * @brief  Configure Binary data logic.
01086   *
01087   * @note   Allow to define how Logical data from the data register are send/received :
01088   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01089   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
01090   * @param  LPUARTx LPUART Instance
01091   * @param  DataLogic This parameter can be one of the following values:
01092   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01093   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01094   * @retval None
01095   */
01096 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
01097 {
01098   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
01099 }
01100
01101 /**
01102   * @brief  Retrieve Binary data configuration
01103   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
01104   * @param  LPUARTx LPUART Instance
01105   * @retval Returned value can be one of the following values:
01106   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01107   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01108   */
01109 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
01110 {
01111   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
01112 }
01113
01114 /**
01115   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01116   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01117   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01118   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
01119   * @param  LPUARTx LPUART Instance
01120   * @param  BitOrder This parameter can be one of the following values:
01121   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01122   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
01126 {
01127   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01128 }
01129
01130 /**
01131   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01132   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01133   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01134   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
01135   * @param  LPUARTx LPUART Instance
01136   * @retval Returned value can be one of the following values:
01137   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01138   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01139   */
01140 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
01141 {
01142   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
01143 }
01144
01145 /**
01146   * @brief  Set Address of the LPUART node.
01147   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01148   *         for wake up with address mark detection.
01149   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01150   *         (b7-b4 should be set to 0)
01151   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01152   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01153   *         for wake up with 7-bit address mark detection.
01154   *         The MSB of the character sent by the transmitter should be equal to 1.
01155   *         It may also be used for character detection during normal reception,
01156   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01157   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01158   *         value and CMF flag is set on match)
01159   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
01160   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
01161   * @param  LPUARTx LPUART Instance
01162   * @param  AddressLen This parameter can be one of the following values:
01163   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01164   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01165   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
01166   * @retval None
01167   */
01168 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
01169 {
01170   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01171              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01172 }
01173
01174 /**
01175   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
01176   * @note   If 4-bit Address Detection is selected in ADDM7,
01177   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01178   *         If 7-bit Address Detection is selected in ADDM7,
01179   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01180   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
01181   * @param  LPUARTx LPUART Instance
01182   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
01183   */
01184 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
01185 {
01186   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01187 }
01188
01189 /**
01190   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01191   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
01192   * @param  LPUARTx LPUART Instance
01193   * @retval Returned value can be one of the following values:
01194   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01195   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01196   */
01197 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
01198 {
01199   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
01200 }
01201
01202 /**
01203   * @brief  Enable RTS HW Flow Control
01204   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
01205   * @param  LPUARTx LPUART Instance
01206   * @retval None
01207   */
01208 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01209 {
01210   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01211 }
01212
01213 /**
01214   * @brief  Disable RTS HW Flow Control
01215   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
01216   * @param  LPUARTx LPUART Instance
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01220 {
01221   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01222 }
01223
01224 /**
01225   * @brief  Enable CTS HW Flow Control
01226   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
01227   * @param  LPUARTx LPUART Instance
01228   * @retval None
01229   */
01230 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01231 {
01232   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01233 }
01234
01235 /**
01236   * @brief  Disable CTS HW Flow Control
01237   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
01238   * @param  LPUARTx LPUART Instance
01239   * @retval None
01240   */
01241 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01242 {
01243   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01244 }
01245
01246 /**
01247   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01248   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
01249   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
01250   * @param  LPUARTx LPUART Instance
01251   * @param  HardwareFlowControl This parameter can be one of the following values:
01252   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01253   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01254   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01255   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01256   * @retval None
01257   */
01258 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01259 {
01260   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01261 }
01262
01263 /**
01264   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01265   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01266   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01267   * @param  LPUARTx LPUART Instance
01268   * @retval Returned value can be one of the following values:
01269   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01270   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01271   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01272   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01273   */
01274 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
01275 {
01276   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01277 }
01278
01279 /**
01280   * @brief  Enable Overrun detection
01281   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01282   * @param  LPUARTx LPUART Instance
01283   * @retval None
01284   */
01285 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01286 {
01287   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01288 }
01289
01290 /**
01291   * @brief  Disable Overrun detection
01292   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01293   * @param  LPUARTx LPUART Instance
01294   * @retval None
01295   */
01296 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01297 {
01298   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01299 }
01300
01301 /**
01302   * @brief  Indicate if Overrun detection is enabled
01303   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01304   * @param  LPUARTx LPUART Instance
01305   * @retval State of bit (1 or 0).
01306   */
01307 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
01308 {
01309   return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01310 }
01311
01312 /**
01313   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01314   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01315   * @param  LPUARTx LPUART Instance
01316   * @param  Type This parameter can be one of the following values:
01317   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01318   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01319   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01320   * @retval None
01321   */
01322 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01323 {
01324   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01325 }
01326
01327 /**
01328   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01329   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01330   * @param  LPUARTx LPUART Instance
01331   * @retval Returned value can be one of the following values:
01332   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01333   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01334   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01335   */
01336 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
01337 {
01338   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01339 }
01340
01341 /**
01342   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01343   *
01344   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01345   *         according to used Peripheral Clock and expected Baud Rate values
01346   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01347   *         (Baud rate value != 0).
01348   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01349   *         a care should be taken when generating high baud rates using high PeriphClk
01350   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01351   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01352   * @param  LPUARTx LPUART Instance
01353   * @param  PeriphClk Peripheral Clock
01354   * @param  PrescalerValue This parameter can be one of the following values:
01355   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01356   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01357   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01358   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01359   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01360   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01361   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01362   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01363   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01364   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01365   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01366   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01367   * @param  BaudRate Baud Rate
01368   * @retval None
01369   */
01370 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01371                                            uint32_t BaudRate)
01372 {
01373   if (BaudRate != 0U)
01374   {
01375     LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
01376   }
01377 }
01378
01379 /**
01380   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01381   *         (full BRR content), and to used Peripheral Clock values
01382   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01383   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01384   * @param  LPUARTx LPUART Instance
01385   * @param  PeriphClk Peripheral Clock
01386   * @param  PrescalerValue This parameter can be one of the following values:
01387   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01388   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01389   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01390   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01391   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01392   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01393   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01394   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01395   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01396   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01397   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01398   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01399   * @retval Baud Rate
01400   */
01401 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
01402                                                uint32_t PrescalerValue)
01403 {
01404   uint32_t lpuartdiv;
01405   uint32_t brrresult;
01406   uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01407
01408   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01409
01410   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01411   {
01412     brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01413   }
01414   else
01415   {
01416     brrresult = 0x0UL;
01417   }
01418
01419   return (brrresult);
01420 }
01421
01422 /**
01423   * @}
01424   */
01425
01426 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01427   * @{
01428   */
01429
01430 /**
01431   * @brief  Enable Single Wire Half-Duplex mode
01432   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01433   * @param  LPUARTx LPUART Instance
01434   * @retval None
01435   */
01436 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01437 {
01438   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01439 }
01440
01441 /**
01442   * @brief  Disable Single Wire Half-Duplex mode
01443   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01444   * @param  LPUARTx LPUART Instance
01445   * @retval None
01446   */
01447 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01448 {
01449   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01450 }
01451
01452 /**
01453   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01454   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01455   * @param  LPUARTx LPUART Instance
01456   * @retval State of bit (1 or 0).
01457   */
01458 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
01459 {
01460   return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
01461 }
01462
01463 /**
01464   * @}
01465   */
01466
01467 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01468   * @{
01469   */
01470
01471 /**
01472   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01473   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01474   * @param  LPUARTx LPUART Instance
01475   * @param  Time Value between Min_Data=0 and Max_Data=31
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01479 {
01480   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
01481 }
01482
01483 /**
01484   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01485   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01486   * @param  LPUARTx LPUART Instance
01487   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01488   */
01489 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
01490 {
01491   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
01492 }
01493
01494 /**
01495   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01496   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01497   * @param  LPUARTx LPUART Instance
01498   * @param  Time Value between Min_Data=0 and Max_Data=31
01499   * @retval None
01500   */
01501 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01502 {
01503   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
01504 }
01505
01506 /**
01507   * @brief  Return DEAT (Driver Enable Assertion Time)
01508   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01509   * @param  LPUARTx LPUART Instance
01510   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01511   */
01512 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
01513 {
01514   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
01515 }
01516
01517 /**
01518   * @brief  Enable Driver Enable (DE) Mode
01519   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01520   * @param  LPUARTx LPUART Instance
01521   * @retval None
01522   */
01523 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01524 {
01525   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01526 }
01527
01528 /**
01529   * @brief  Disable Driver Enable (DE) Mode
01530   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01531   * @param  LPUARTx LPUART Instance
01532   * @retval None
01533   */
01534 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01535 {
01536   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01537 }
01538
01539 /**
01540   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01541   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01542   * @param  LPUARTx LPUART Instance
01543   * @retval State of bit (1 or 0).
01544   */
01545 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
01546 {
01547   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
01548 }
01549
01550 /**
01551   * @brief  Select Driver Enable Polarity
01552   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01553   * @param  LPUARTx LPUART Instance
01554   * @param  Polarity This parameter can be one of the following values:
01555   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01556   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01557   * @retval None
01558   */
01559 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01560 {
01561   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01562 }
01563
01564 /**
01565   * @brief  Return Driver Enable Polarity
01566   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01567   * @param  LPUARTx LPUART Instance
01568   * @retval Returned value can be one of the following values:
01569   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01570   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01571   */
01572 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
01573 {
01574   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01575 }
01576
01577 /**
01578   * @}
01579   */
01580
01581 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01582   * @{
01583   */
01584
01585 /**
01586   * @brief  Check if the LPUART Parity Error Flag is set or not
01587   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01588   * @param  LPUARTx LPUART Instance
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
01592 {
01593   return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Check if the LPUART Framing Error Flag is set or not
01598   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01599   * @param  LPUARTx LPUART Instance
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
01603 {
01604   return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Check if the LPUART Noise error detected Flag is set or not
01609   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01610   * @param  LPUARTx LPUART Instance
01611   * @retval State of bit (1 or 0).
01612   */
01613 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
01614 {
01615   return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
01616 }
01617
01618 /**
01619   * @brief  Check if the LPUART OverRun Error Flag is set or not
01620   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01621   * @param  LPUARTx LPUART Instance
01622   * @retval State of bit (1 or 0).
01623   */
01624 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
01625 {
01626   return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
01627 }
01628
01629 /**
01630   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01631   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01632   * @param  LPUARTx LPUART Instance
01633   * @retval State of bit (1 or 0).
01634   */
01635 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
01636 {
01637   return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
01638 }
01639
01640 #define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
01641
01642 /**
01643   * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
01644   * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
01645   * @param  LPUARTx LPUART Instance
01646   * @retval State of bit (1 or 0).
01647   */
01648 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
01649 {
01650   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
01651 }
01652
01653 /**
01654   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01655   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01656   * @param  LPUARTx LPUART Instance
01657   * @retval State of bit (1 or 0).
01658   */
01659 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
01660 {
01661   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
01662 }
01663
01664 #define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
01665
01666 /**
01667   * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
01668   * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
01669   * @param  LPUARTx LPUART Instance
01670   * @retval State of bit (1 or 0).
01671   */
01672 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
01673 {
01674   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
01675 }
01676
01677 /**
01678   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01679   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01680   * @param  LPUARTx LPUART Instance
01681   * @retval State of bit (1 or 0).
01682   */
01683 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
01684 {
01685   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
01686 }
01687
01688 /**
01689   * @brief  Check if the LPUART CTS Flag is set or not
01690   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01691   * @param  LPUARTx LPUART Instance
01692   * @retval State of bit (1 or 0).
01693   */
01694 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
01695 {
01696   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
01697 }
01698
01699 /**
01700   * @brief  Check if the LPUART Busy Flag is set or not
01701   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01702   * @param  LPUARTx LPUART Instance
01703   * @retval State of bit (1 or 0).
01704   */
01705 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
01706 {
01707   return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
01708 }
01709
01710 /**
01711   * @brief  Check if the LPUART Character Match Flag is set or not
01712   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01713   * @param  LPUARTx LPUART Instance
01714   * @retval State of bit (1 or 0).
01715   */
01716 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
01717 {
01718   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
01719 }
01720
01721 /**
01722   * @brief  Check if the LPUART Send Break Flag is set or not
01723   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01724   * @param  LPUARTx LPUART Instance
01725   * @retval State of bit (1 or 0).
01726   */
01727 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
01728 {
01729   return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
01730 }
01731
01732 /**
01733   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01734   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01735   * @param  LPUARTx LPUART Instance
01736   * @retval State of bit (1 or 0).
01737   */
01738 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
01739 {
01740   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
01741 }
01742
01743 /**
01744   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01745   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01746   * @param  LPUARTx LPUART Instance
01747   * @retval State of bit (1 or 0).
01748   */
01749 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
01750 {
01751   return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
01752 }
01753
01754 /**
01755   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01756   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01757   * @param  LPUARTx LPUART Instance
01758   * @retval State of bit (1 or 0).
01759   */
01760 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
01761 {
01762   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
01763 }
01764
01765 /**
01766   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01767   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01768   * @param  LPUARTx LPUART Instance
01769   * @retval State of bit (1 or 0).
01770   */
01771 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
01772 {
01773   return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
01774 }
01775
01776 /**
01777   * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
01778   * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
01779   * @param  LPUARTx LPUART Instance
01780   * @retval State of bit (1 or 0).
01781   */
01782 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
01783 {
01784   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
01785 }
01786
01787 /**
01788   * @brief  Check if the LPUART RX FIFO Full Flag is set or not
01789   * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
01790   * @param  LPUARTx LPUART Instance
01791   * @retval State of bit (1 or 0).
01792   */
01793 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
01794 {
01795   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
01796 }
01797
01798 /**
01799   * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
01800   * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
01801   * @param  LPUARTx LPUART Instance
01802   * @retval State of bit (1 or 0).
01803   */
01804 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
01805 {
01806   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
01807 }
01808
01809 /**
01810   * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
01811   * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
01812   * @param  LPUARTx LPUART Instance
01813   * @retval State of bit (1 or 0).
01814   */
01815 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
01816 {
01817   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
01818 }
01819
01820 /**
01821   * @brief  Clear Parity Error Flag
01822   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01823   * @param  LPUARTx LPUART Instance
01824   * @retval None
01825   */
01826 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01827 {
01828   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01829 }
01830
01831 /**
01832   * @brief  Clear Framing Error Flag
01833   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01834   * @param  LPUARTx LPUART Instance
01835   * @retval None
01836   */
01837 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01838 {
01839   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01840 }
01841
01842 /**
01843   * @brief  Clear Noise detected Flag
01844   * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
01845   * @param  LPUARTx LPUART Instance
01846   * @retval None
01847   */
01848 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01849 {
01850   WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
01851 }
01852
01853 /**
01854   * @brief  Clear OverRun Error Flag
01855   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01856   * @param  LPUARTx LPUART Instance
01857   * @retval None
01858   */
01859 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01860 {
01861   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01862 }
01863
01864 /**
01865   * @brief  Clear IDLE line detected Flag
01866   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01867   * @param  LPUARTx LPUART Instance
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01871 {
01872   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01873 }
01874
01875 /**
01876   * @brief  Clear Transmission Complete Flag
01877   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01878   * @param  LPUARTx LPUART Instance
01879   * @retval None
01880   */
01881 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01882 {
01883   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01884 }
01885
01886 /**
01887   * @brief  Clear CTS Interrupt Flag
01888   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01889   * @param  LPUARTx LPUART Instance
01890   * @retval None
01891   */
01892 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01893 {
01894   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01895 }
01896
01897 /**
01898   * @brief  Clear Character Match Flag
01899   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01900   * @param  LPUARTx LPUART Instance
01901   * @retval None
01902   */
01903 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01904 {
01905   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01906 }
01907
01908 /**
01909   * @brief  Clear Wake Up from stop mode Flag
01910   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01911   * @param  LPUARTx LPUART Instance
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01915 {
01916   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01917 }
01918
01919 /**
01920   * @}
01921   */
01922
01923 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01924   * @{
01925   */
01926
01927 /**
01928   * @brief  Enable IDLE Interrupt
01929   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01930   * @param  LPUARTx LPUART Instance
01931   * @retval None
01932   */
01933 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01934 {
01935   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01936 }
01937
01938 #define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
01939
01940 /**
01941   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
01942   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
01943   * @param  LPUARTx LPUART Instance
01944   * @retval None
01945   */
01946 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01947 {
01948   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
01949 }
01950
01951 /**
01952   * @brief  Enable Transmission Complete Interrupt
01953   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01954   * @param  LPUARTx LPUART Instance
01955   * @retval None
01956   */
01957 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01958 {
01959   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01960 }
01961
01962 #define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
01963
01964 /**
01965   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
01966   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
01967   * @param  LPUARTx LPUART Instance
01968   * @retval None
01969   */
01970 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
01971 {
01972   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
01973 }
01974
01975 /**
01976   * @brief  Enable Parity Error Interrupt
01977   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01978   * @param  LPUARTx LPUART Instance
01979   * @retval None
01980   */
01981 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01982 {
01983   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01984 }
01985
01986 /**
01987   * @brief  Enable Character Match Interrupt
01988   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01989   * @param  LPUARTx LPUART Instance
01990   * @retval None
01991   */
01992 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01993 {
01994   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01995 }
01996
01997 /**
01998   * @brief  Enable TX FIFO Empty Interrupt
01999   * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
02000   * @param  LPUARTx LPUART Instance
02001   * @retval None
02002   */
02003 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
02004 {
02005   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02006 }
02007
02008 /**
02009   * @brief  Enable RX FIFO Full Interrupt
02010   * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
02011   * @param  LPUARTx LPUART Instance
02012   * @retval None
02013   */
02014 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
02015 {
02016   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02017 }
02018
02019 /**
02020   * @brief  Enable Error Interrupt
02021   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02022   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02023   *         - 0: Interrupt is inhibited
02024   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02025   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
02026   * @param  LPUARTx LPUART Instance
02027   * @retval None
02028   */
02029 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
02030 {
02031   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
02032 }
02033
02034 /**
02035   * @brief  Enable CTS Interrupt
02036   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
02037   * @param  LPUARTx LPUART Instance
02038   * @retval None
02039   */
02040 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
02041 {
02042   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02043 }
02044
02045 /**
02046   * @brief  Enable Wake Up from Stop Mode Interrupt
02047   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
02048   * @param  LPUARTx LPUART Instance
02049   * @retval None
02050   */
02051 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
02052 {
02053   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02054 }
02055
02056 /**
02057   * @brief  Enable TX FIFO Threshold Interrupt
02058   * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
02059   * @param  LPUARTx LPUART Instance
02060   * @retval None
02061   */
02062 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
02063 {
02064   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02065 }
02066
02067 /**
02068   * @brief  Enable RX FIFO Threshold Interrupt
02069   * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
02070   * @param  LPUARTx LPUART Instance
02071   * @retval None
02072   */
02073 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
02074 {
02075   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02076 }
02077
02078 /**
02079   * @brief  Disable IDLE Interrupt
02080   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
02081   * @param  LPUARTx LPUART Instance
02082   * @retval None
02083   */
02084 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
02085 {
02086   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
02087 }
02088
02089 #define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
02090
02091 /**
02092   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
02093   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
02094   * @param  LPUARTx LPUART Instance
02095   * @retval None
02096   */
02097 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02098 {
02099   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
02100 }
02101
02102 /**
02103   * @brief  Disable Transmission Complete Interrupt
02104   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
02105   * @param  LPUARTx LPUART Instance
02106   * @retval None
02107   */
02108 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
02109 {
02110   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
02111 }
02112
02113 #define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
02114
02115 /**
02116   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
02117   * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
02118   * @param  LPUARTx LPUART Instance
02119   * @retval None
02120   */
02121 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02122 {
02123   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
02124 }
02125
02126 /**
02127   * @brief  Disable Parity Error Interrupt
02128   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
02129   * @param  LPUARTx LPUART Instance
02130   * @retval None
02131   */
02132 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
02133 {
02134   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
02135 }
02136
02137 /**
02138   * @brief  Disable Character Match Interrupt
02139   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
02140   * @param  LPUARTx LPUART Instance
02141   * @retval None
02142   */
02143 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
02144 {
02145   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
02146 }
02147
02148 /**
02149   * @brief  Disable TX FIFO Empty Interrupt
02150   * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
02151   * @param  LPUARTx LPUART Instance
02152   * @retval None
02153   */
02154 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
02155 {
02156   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02157 }
02158
02159 /**
02160   * @brief  Disable RX FIFO Full Interrupt
02161   * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
02162   * @param  LPUARTx LPUART Instance
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
02166 {
02167   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02168 }
02169
02170 /**
02171   * @brief  Disable Error Interrupt
02172   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02173   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02174   *         - 0: Interrupt is inhibited
02175   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02176   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
02177   * @param  LPUARTx LPUART Instance
02178   * @retval None
02179   */
02180 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
02181 {
02182   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
02183 }
02184
02185 /**
02186   * @brief  Disable CTS Interrupt
02187   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
02188   * @param  LPUARTx LPUART Instance
02189   * @retval None
02190   */
02191 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
02192 {
02193   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02194 }
02195
02196 /**
02197   * @brief  Disable Wake Up from Stop Mode Interrupt
02198   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
02199   * @param  LPUARTx LPUART Instance
02200   * @retval None
02201   */
02202 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
02203 {
02204   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02205 }
02206
02207 /**
02208   * @brief  Disable TX FIFO Threshold Interrupt
02209   * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
02210   * @param  LPUARTx LPUART Instance
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
02214 {
02215   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02216 }
02217
02218 /**
02219   * @brief  Disable RX FIFO Threshold Interrupt
02220   * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
02221   * @param  LPUARTx LPUART Instance
02222   * @retval None
02223   */
02224 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
02225 {
02226   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02227 }
02228
02229 /**
02230   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
02231   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
02232   * @param  LPUARTx LPUART Instance
02233   * @retval State of bit (1 or 0).
02234   */
02235 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
02236 {
02237   return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
02238 }
02239
02240 #define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
02241
02242 /**
02243   * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
02244   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02245   * @param  LPUARTx LPUART Instance
02246   * @retval State of bit (1 or 0).
02247   */
02248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
02249 {
02250   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
02251 }
02252
02253 /**
02254   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
02255   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
02256   * @param  LPUARTx LPUART Instance
02257   * @retval State of bit (1 or 0).
02258   */
02259 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
02260 {
02261   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
02262 }
02263
02264 #define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
02265
02266 /**
02267   * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
02268   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02269   * @param  LPUARTx LPUART Instance
02270   * @retval State of bit (1 or 0).
02271   */
02272 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
02273 {
02274   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
02275 }
02276
02277 /**
02278   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
02279   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
02280   * @param  LPUARTx LPUART Instance
02281   * @retval State of bit (1 or 0).
02282   */
02283 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
02284 {
02285   return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
02286 }
02287
02288 /**
02289   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
02290   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
02291   * @param  LPUARTx LPUART Instance
02292   * @retval State of bit (1 or 0).
02293   */
02294 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
02295 {
02296   return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
02297 }
02298
02299 /**
02300   * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
02301   * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
02302   * @param  LPUARTx LPUART Instance
02303   * @retval State of bit (1 or 0).
02304   */
02305 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
02306 {
02307   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
02308 }
02309
02310 /**
02311   * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
02312   * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
02313   * @param  LPUARTx LPUART Instance
02314   * @retval State of bit (1 or 0).
02315   */
02316 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
02317 {
02318   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
02319 }
02320
02321 /**
02322   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
02323   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
02324   * @param  LPUARTx LPUART Instance
02325   * @retval State of bit (1 or 0).
02326   */
02327 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
02328 {
02329   return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
02330 }
02331
02332 /**
02333   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
02334   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
02335   * @param  LPUARTx LPUART Instance
02336   * @retval State of bit (1 or 0).
02337   */
02338 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
02339 {
02340   return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
02341 }
02342
02343 /**
02344   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
02345   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
02346   * @param  LPUARTx LPUART Instance
02347   * @retval State of bit (1 or 0).
02348   */
02349 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
02350 {
02351   return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
02352 }
02353
02354 /**
02355   * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
02356   * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
02357   * @param  LPUARTx LPUART Instance
02358   * @retval State of bit (1 or 0).
02359   */
02360 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
02361 {
02362   return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
02363 }
02364
02365 /**
02366   * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
02367   * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
02368   * @param  LPUARTx LPUART Instance
02369   * @retval State of bit (1 or 0).
02370   */
02371 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
02372 {
02373   return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
02374 }
02375
02376 /**
02377   * @}
02378   */
02379
02380 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
02381   * @{
02382   */
02383
02384 /**
02385   * @brief  Enable DMA Mode for reception
02386   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
02387   * @param  LPUARTx LPUART Instance
02388   * @retval None
02389   */
02390 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
02391 {
02392   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02393 }
02394
02395 /**
02396   * @brief  Disable DMA Mode for reception
02397   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
02398   * @param  LPUARTx LPUART Instance
02399   * @retval None
02400   */
02401 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
02402 {
02403   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02404 }
02405
02406 /**
02407   * @brief  Check if DMA Mode is enabled for reception
02408   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
02409   * @param  LPUARTx LPUART Instance
02410   * @retval State of bit (1 or 0).
02411   */
02412 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
02413 {
02414   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
02415 }
02416
02417 /**
02418   * @brief  Enable DMA Mode for transmission
02419   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
02420   * @param  LPUARTx LPUART Instance
02421   * @retval None
02422   */
02423 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
02424 {
02425   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02426 }
02427
02428 /**
02429   * @brief  Disable DMA Mode for transmission
02430   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
02431   * @param  LPUARTx LPUART Instance
02432   * @retval None
02433   */
02434 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
02435 {
02436   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02437 }
02438
02439 /**
02440   * @brief  Check if DMA Mode is enabled for transmission
02441   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
02442   * @param  LPUARTx LPUART Instance
02443   * @retval State of bit (1 or 0).
02444   */
02445 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
02446 {
02447   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
02448 }
02449
02450 /**
02451   * @brief  Enable DMA Disabling on Reception Error
02452   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
02453   * @param  LPUARTx LPUART Instance
02454   * @retval None
02455   */
02456 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02457 {
02458   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02459 }
02460
02461 /**
02462   * @brief  Disable DMA Disabling on Reception Error
02463   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
02464   * @param  LPUARTx LPUART Instance
02465   * @retval None
02466   */
02467 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02468 {
02469   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02470 }
02471
02472 /**
02473   * @brief  Indicate if DMA Disabling on Reception Error is disabled
02474   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
02475   * @param  LPUARTx LPUART Instance
02476   * @retval State of bit (1 or 0).
02477   */
02478 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
02479 {
02480   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
02481 }
02482
02483 /**
02484   * @brief  Get the LPUART data register address used for DMA transfer
02485   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
02486   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02487   * @param  LPUARTx LPUART Instance
02488   * @param  Direction This parameter can be one of the following values:
02489   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02490   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02491   * @retval Address of data register
02492   */
02493 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
02494 {
02495   uint32_t data_reg_addr;
02496
02497   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02498   {
02499     /* return address of TDR register */
02500     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02501   }
02502   else
02503   {
02504     /* return address of RDR register */
02505     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02506   }
02507
02508   return data_reg_addr;
02509 }
02510
02511 /**
02512   * @}
02513   */
02514
02515 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02516   * @{
02517   */
02518
02519 /**
02520   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02521   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02522   * @param  LPUARTx LPUART Instance
02523   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02524   */
02525 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
02526 {
02527   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
02528 }
02529
02530 /**
02531   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02532   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02533   * @param  LPUARTx LPUART Instance
02534   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02535   */
02536 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
02537 {
02538   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02539 }
02540
02541 /**
02542   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02543   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02544   * @param  LPUARTx LPUART Instance
02545   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02546   * @retval None
02547   */
02548 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02549 {
02550   LPUARTx->TDR = Value;
02551 }
02552
02553 /**
02554   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02555   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02556   * @param  LPUARTx LPUART Instance
02557   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02558   * @retval None
02559   */
02560 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02561 {
02562   LPUARTx->TDR = Value & 0x1FFUL;
02563 }
02564
02565 /**
02566   * @}
02567   */
02568
02569 /** @defgroup LPUART_LL_EF_Execution Execution
02570   * @{
02571   */
02572
02573 /**
02574   * @brief  Request Break sending
02575   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02576   * @param  LPUARTx LPUART Instance
02577   * @retval None
02578   */
02579 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02580 {
02581   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
02582 }
02583
02584 /**
02585   * @brief  Put LPUART in mute mode and set the RWU flag
02586   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02587   * @param  LPUARTx LPUART Instance
02588   * @retval None
02589   */
02590 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02591 {
02592   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
02593 }
02594
02595 /**
02596   * @brief  Request a Receive Data and FIFO flush
02597   * @note   Allows to discard the received data without reading them, and avoid an overrun
02598   *         condition.
02599   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02600   * @param  LPUARTx LPUART Instance
02601   * @retval None
02602   */
02603 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02604 {
02605   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
02606 }
02607
02608 /**
02609   * @}
02610   */
02611
02612 #if defined(USE_FULL_LL_DRIVER)
02613 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02614   * @{
02615   */
02616 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
02617 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
02618 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02619 /**
02620   * @}
02621   */
02622 #endif /* USE_FULL_LL_DRIVER */
02623
02624 /**
02625   * @}
02626   */
02627
02628 /**
02629   * @}
02630   */
02631
02632 #endif /* LPUART1 */
02633
02634 /**
02635   * @}
02636   */
02637
02638 #ifdef __cplusplus
02639 }
02640 #endif
02641
02642 #endif /* STM32G4xx_LL_LPUART_H */
02643
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_opamp.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_opamp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_opamp.c
00004   * @author  MCD Application Team
00005   * @brief   OPAMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_opamp.h"
00022
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
00034
00035 /** @addtogroup OPAMP_LL OPAMP
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /** @addtogroup OPAMP_LL_Private_Macros
00045   * @{
00046   */
00047
00048 /* Check of parameters for configuration of OPAMP hierarchical scope:         */
00049 /* OPAMP instance.                                                            */
00050
00051 #define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)                                 \
00052   (   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMALSPEED)                     \
00053    || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_HIGHSPEED))
00054
00055 #define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
00056   (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
00057    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
00058    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
00059    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0)                         \
00060    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_BIAS)                    \
00061    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA_IO0_IO1_BIAS)                \
00062   )
00063
00064 #define IS_LL_OPAMP_INPUT_NONINVERTING(__INPUT_NONINVERTING__)                 \
00065   (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
00066    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1)               \
00067    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2)               \
00068    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3)               \
00069    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC)               \
00070   )
00071
00072 #define IS_LL_OPAMP_INPUT_INVERTING(__INPUT_INVERTING__)                       \
00073   (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
00074    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
00075    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
00076   )
00077
00078 /**
00079   * @}
00080   */
00081
00082
00083 /* Private function prototypes -----------------------------------------------*/
00084
00085 /* Exported functions --------------------------------------------------------*/
00086 /** @addtogroup OPAMP_LL_Exported_Functions
00087   * @{
00088   */
00089
00090 /** @addtogroup OPAMP_LL_EF_Init
00091   * @{
00092   */
00093
00094 /**
00095   * @brief  De-initialize registers of the selected OPAMP instance
00096   *         to their default reset values.
00097   * @note   If comparator is locked, de-initialization by software is
00098   *         not possible.
00099   *         The only way to unlock the comparator is a device hardware reset.
00100   * @param  OPAMPx OPAMP instance
00101   * @retval An ErrorStatus enumeration value:
00102   *          - SUCCESS: OPAMP registers are de-initialized
00103   *          - ERROR: OPAMP registers are not de-initialized
00104   */
00105 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx)
00106 {
00107   ErrorStatus status = SUCCESS;
00108
00109   /* Check the parameters */
00110   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00111
00112   /* Note: Hardware constraint (refer to description of this function):       */
00113   /*       OPAMP instance must not be locked.                                 */
00114   if (LL_OPAMP_IsLocked(OPAMPx) == 0UL)
00115   {
00116     LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000UL);
00117   }
00118   else
00119   {
00120     /* OPAMP instance is locked: de-initialization by software is              */
00121     /* not possible.                                                           */
00122     /* The only way to unlock the OPAMP is a device hardware reset.            */
00123     status = ERROR;
00124   }
00125
00126   /* Timer controlled mux mode register reset                                  */
00127   if (LL_OPAMP_IsTimerMuxLocked(OPAMPx) == 0UL)
00128   {
00129     LL_OPAMP_WriteReg(OPAMPx, TCMR, 0x00000000UL);
00130   }
00131   else if (LL_OPAMP_ReadReg(OPAMPx, TCMR) != 0x80000000UL)
00132   {
00133     /* OPAMP instance timer controlled mux is locked configured, deinit error  */
00134     /* The only way to unlock the OPAMP is a device hardware reset.            */
00135     status = ERROR;
00136   }
00137   else
00138   {
00139     /* OPAMP instance timer controlled mux is locked unconfigured, deinit OK */
00140   }
00141
00142   return status;
00143 }
00144
00145 /**
00146   * @brief  Initialize some features of OPAMP instance.
00147   * @note   This function reset bit of calibration mode to ensure
00148   *         to be in functional mode, in order to have OPAMP parameters
00149   *         (inputs selection, ...) set with the corresponding OPAMP mode
00150   *         to be effective.
00151   * @param  OPAMPx OPAMP instance
00152   * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
00153   * @retval An ErrorStatus enumeration value:
00154   *          - SUCCESS: OPAMP registers are initialized
00155   *          - ERROR: OPAMP registers are not initialized
00156   */
00157 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00158 {
00159   ErrorStatus status = SUCCESS;
00160
00161   /* Check the parameters */
00162   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00163   assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
00164   assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
00165   assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMP_InitStruct->InputNonInverting));
00166
00167   /* Note: OPAMP inverting input can be used with OPAMP in mode standalone    */
00168   /*       or PGA with external capacitors for filtering circuit.             */
00169   /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
00170   /*       not used (not connected to GPIO pin).                              */
00171   if (OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00172   {
00173     assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMP_InitStruct->InputInverting));
00174   }
00175
00176   /* Note: Hardware constraint (refer to description of this function):       */
00177   /*       OPAMP instance must not be locked.                                 */
00178   if (LL_OPAMP_IsLocked(OPAMPx) == 0U)
00179   {
00180     /* Configuration of OPAMP instance :                                      */
00181     /*  - PowerMode                                                             */
00182     /*  - Functional mode                                                     */
00183     /*  - Input non-inverting                                                 */
00184     /*  - Input inverting                                                     */
00185     /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode.    */
00186     if (OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00187     {
00188       MODIFY_REG(OPAMPx->CSR,
00189                  OPAMP_CSR_HIGHSPEEDEN
00190                  | OPAMP_CSR_CALON
00191                  | OPAMP_CSR_VMSEL
00192                  | OPAMP_CSR_VPSEL
00193                  | OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3
00194                  ,
00195                  OPAMP_InitStruct->PowerMode
00196                  | OPAMP_InitStruct->FunctionalMode
00197                  | OPAMP_InitStruct->InputNonInverting
00198                  | OPAMP_InitStruct->InputInverting
00199                 );
00200     }
00201     else
00202     {
00203       MODIFY_REG(OPAMPx->CSR,
00204                  OPAMP_CSR_HIGHSPEEDEN
00205                  | OPAMP_CSR_CALON
00206                  | OPAMP_CSR_VMSEL
00207                  | OPAMP_CSR_VPSEL
00208                  | OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3
00209                  ,
00210                  OPAMP_InitStruct->PowerMode
00211                  | LL_OPAMP_MODE_FOLLOWER
00212                  | OPAMP_InitStruct->InputNonInverting
00213                 );
00214     }
00215   }
00216   else
00217   {
00218     /* Initialization error: OPAMP instance is locked.                        */
00219     status = ERROR;
00220   }
00221
00222   return status;
00223 }
00224
00225 /**
00226   * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
00227   * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
00228   *                         whose fields will be set to default values.
00229   * @retval None
00230   */
00231 void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00232 {
00233   /* Set OPAMP_InitStruct fields to default values */
00234   OPAMP_InitStruct->PowerMode         = LL_OPAMP_POWERMODE_NORMALSPEED;
00235   OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
00236   OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
00237   /* Note: Parameter discarded if OPAMP in functional mode follower,          */
00238   /*       set anyway to its default value.                                   */
00239   OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
00240 }
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /**
00251   * @}
00252   */
00253
00254 #endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4  || OPAMP5 || OPAMP6 */
00255
00256 /**
00257   * @}
00258   */
00259
00260 #endif /* USE_FULL_LL_DRIVER */
00261
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_opamp.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_opamp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_opamp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of OPAMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_OPAMP_H
00021 #define STM32G4xx_LL_OPAMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
00035
00036 /** @defgroup OPAMP_LL OPAMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
00045   * @{
00046   */
00047
00048 /* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
00049 /* or PMOS.                                                                   */
00050 /* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
00051 /* - OPAMP trimming selection of transistors differential pair                */
00052 /* - OPAMP trimming values of transistors differential pair                   */
00053 #define OPAMP_TRIMMING_SELECT_MASK          (OPAMP_CSR_CALSEL)
00054 #define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
00055
00056 /**
00057   * @}
00058   */
00059
00060
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  Driver macro reserved for internal use: set a pointer to
00068   *         a register from a register basis from which an offset
00069   *         is applied.
00070   * @param  __REG__ Register basis from which the offset is applied.
00071   * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
00072   * @retval Register address
00073   */
00074 #define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
00075   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
00076
00077
00078
00079
00080 /**
00081   * @}
00082   */
00083
00084
00085 /* Exported types ------------------------------------------------------------*/
00086 #if defined(USE_FULL_LL_DRIVER)
00087 /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  Structure definition of some features of OPAMP instance.
00093   */
00094 typedef struct
00095 {
00096   uint32_t PowerMode;                   /*!< Set OPAMP power mode.
00097                                              This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
00098
00099                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
00100
00101
00102   uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
00103                                              This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
00104                                              @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
00105
00106                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
00107
00108   uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
00109                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
00110
00111                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
00112
00113   uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
00114                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
00115                                              @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
00116
00117                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
00118
00119 } LL_OPAMP_InitTypeDef;
00120
00121 /**
00122   * @}
00123   */
00124 #endif /* USE_FULL_LL_DRIVER */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
00132   * @{
00133   */
00134 #define LL_OPAMP_MODE_FUNCTIONAL        (0x00000000UL)                              /*!< OPAMP functional mode */
00135 #define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_CALON)                           /*!< OPAMP calibration mode */
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
00141   * @{
00142   */
00143 #define LL_OPAMP_MODE_STANDALONE        (0x00000000UL)                                                /*!< OPAMP functional mode, OPAMP operation in standalone */
00144 #define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)                       /*!< OPAMP functional mode, OPAMP operation in follower */
00145 #define LL_OPAMP_MODE_PGA               (OPAMP_CSR_VMSEL_1)                                           /*!< OPAMP functional mode, OPAMP operation in PGA */
00146 #define LL_OPAMP_MODE_PGA_IO0           (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
00147 #define LL_OPAMP_MODE_PGA_IO0_BIAS      (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0
00148                                                                                                           - Input signal on VINM0, bias on VINPx: negative gain
00149                                                                                                           - Bias on VINM0, input signal on VINPx: positive gain */
00150 #define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS  (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)     /*!< In PGA mode, the inverting input is connected to VINM0
00151                                                                                                           - Input signal on VINM0, bias on VINPx: negative gain
00152                                                                                                           - Bias on VINM0, input signal on VINPx: positive gain
00153                                                                                                           And VINM1 is connected too for filtering */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
00160   * @note Gain sign:
00161   *         - is positive if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
00162   *           @ref LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0
00163   *         - may be positive or negative if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
00164   *           @ref LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00165   *       see @ref OPAMP_LL_EC_FUNCTIONAL_MODE for more details
00166   * @{
00167   */
00168 #define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1             (0x00000000UL)                                                 /*!< OPAMP PGA gain 2  or -1  */
00169 #define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3             (                                          OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4  or -3  */
00170 #define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7             (                     OPAMP_CSR_PGGAIN_1                     ) /*!< OPAMP PGA gain 8  or -7  */
00171 #define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15           (                     OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 16 or -15 */
00172 #define LL_OPAMP_PGA_GAIN_32_OR_MINUS_31           (OPAMP_CSR_PGGAIN_2                                          ) /*!< OPAMP PGA gain 32 or -31 */
00173 #define LL_OPAMP_PGA_GAIN_64_OR_MINUS_63           (OPAMP_CSR_PGGAIN_2 |                      OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 64 or -63 */
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
00179   * @{
00180   */
00181 #define LL_OPAMP_INPUT_NONINVERT_IO0         (0x00000000UL)        /*!< OPAMP non inverting input connected to I/O VINP0
00182                                                                         (PA1  for OPAMP1, PA7  for OPAMP2, PB0  for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
00183                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00184 #define LL_OPAMP_INPUT_NONINVERT_IO1         OPAMP_CSR_VPSEL_0     /*!< OPAMP non inverting input connected to I/O VINP1
00185                                                                         (PA3  for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9  for OPAMP6)
00186                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00187 #define LL_OPAMP_INPUT_NONINVERT_IO2         OPAMP_CSR_VPSEL_1     /*!< OPAMP non inverting input connected to I/O VINP2
00188                                                                         (PA7  for OPAMP1, PB0  for OPAMP2, PA1  for OPAMP3, PB11 for OPAMP4, PC3  for OPAMP5, PB13 for OPAMP6)
00189                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00190 #define LL_OPAMP_INPUT_NONINVERT_IO3         OPAMP_CSR_VPSEL       /*!< OPAMP non inverting input connected to I/O VINP3
00191                                                                         (PD14 for OPAMP2) */
00192 #define LL_OPAMP_INPUT_NONINVERT_DAC         OPAMP_CSR_VPSEL       /*!< OPAMP non inverting input connected internally to DAC channel
00193                                                                         (DAC3_CH1 for OPAMP1, DAC3_CH2  for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
00194                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
00200   * @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.
00201   *       Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
00202   * @{
00203   */
00204 #define LL_OPAMP_INPUT_INVERT_IO0         (0x00000000UL)           /*!< OPAMP inverting input connected to I/O VINM0
00205                                                                         (PA3  for OPAMP1, PA5  for OPAMP2, PB2  for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1  for OPAMP6)
00206                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00207 #define LL_OPAMP_INPUT_INVERT_IO1         OPAMP_CSR_VMSEL_0        /*!< OPAMP inverting input connected to I/0 VINM1
00208                                                                         (PC5  for OPAMP1, PC5  for OPAMP2, PB10 for OPAMP3, PB8  for OPAMP4, PA3  for OPAMP5, PB1  for OPAMP6)
00209                                                                         Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00210 #define LL_OPAMP_INPUT_INVERT_CONNECT_NO  OPAMP_CSR_VMSEL_1        /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias).
00211                                                                         Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
00217   * @{
00218   */
00219 #define LL_OPAMP_INPUT_NONINVERT_IO0_SEC         (0x00000000UL)       /*!< OPAMP secondary non inverting input connected to I/O VINP0
00220                                                                            (PA1  for OPAMP1, PA7  for OPAMP2, PB0  for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
00221                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00222 #define LL_OPAMP_INPUT_NONINVERT_IO1_SEC         OPAMP_TCMR_VPSSEL_0  /*!< OPAMP secondary non inverting input connected to I/O VINP1
00223                                                                            (PA3  for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9  for OPAMP6)
00224                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00225 #define LL_OPAMP_INPUT_NONINVERT_IO2_SEC         OPAMP_TCMR_VPSSEL_1  /*!< OPAMP secondary non inverting input connected to I/O VINP2
00226                                                                            (PA7  for OPAMP1, PB0  for OPAMP2, PA1  for OPAMP3, PB11 for OPAMP4, PC3  for OPAMP5, PB13 for OPAMP6)
00227                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00228 #define LL_OPAMP_INPUT_NONINVERT_IO3_SEC         OPAMP_TCMR_VPSSEL    /*!< OPAMP secondary non inverting input connected to I/O VINP3
00229                                                                            (PD14 for OPAMP2) */
00230 #define LL_OPAMP_INPUT_NONINVERT_DAC_SEC         OPAMP_TCMR_VPSSEL    /*!< OPAMP secondary non inverting input connected internally to DAC channel
00231                                                                            (DAC3_CH1 for OPAMP1, DAC3_CH2  for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
00232                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
00238   * @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.
00239   *       Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
00240   * @{
00241   */
00242 #define LL_OPAMP_INPUT_INVERT_IO0_SEC         (0x00000000UL)          /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref LL_OPAMP_MODE_STANDALONE
00243                                                                            has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode().
00244                                                                            OPAMP secondary inverting input connected to I/O VINM0.
00245                                                                            (PA3  for OPAMP1, PA5  for OPAMP2, PB2  for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1  for OPAMP6)
00246                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details  */
00247 #define LL_OPAMP_INPUT_INVERT_IO1_SEC         OPAMP_TCMR_VMSSEL       /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref LL_OPAMP_MODE_STANDALONE
00248                                                                            has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode().
00249                                                                            OPAMP secondary inverting input connected to I/0 VINM1
00250                                                                            (PC5  for OPAMP1, PC5  for OPAMP2, PB10 for OPAMP3, PB8  for OPAMP4, PA3  for OPAMP5, PB1  for OPAMP6)
00251                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00252 #define LL_OPAMP_INPUT_INVERT_PGA_SEC         (0x00000000UL)          /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref LL_OPAMP_Init()
00253                                                                            or @ref LL_OPAMP_SetFunctionalMode() is NOT @ref LL_OPAMP_MODE_STANDALONE.
00254                                                                            OPAMP secondary inverting input is:
00255                                                                              - Not connected if configured mode is @ref LL_OPAMP_MODE_FOLLOWER or @ref LL_OPAMP_MODE_PGA
00256                                                                              - Connected to VINM0 and possibly VINM1 if any of the other modes as been configured
00257                                                                            (see @ref OPAMP_LL_EC_FUNCTIONAL_MODE description for more details on PGA connection modes) */
00258 #define LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC    OPAMP_TCMR_VMSSEL       /*!< OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to @ref LL_OPAMP_Init()
00259                                                                            or @ref LL_OPAMP_SetFunctionalMode() is NOT @ref LL_OPAMP_MODE_STANDALONE.
00260                                                                            OPAMP secondary inverting input is not connected. */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup OPAMP_LL_EC_INTERNAL_OUPUT_MODE OPAMP internal output mode
00266   * @{
00267   */
00268 #define LL_OPAMP_INTERNAL_OUPUT_DISABLED       (0x00000000UL)         /*!< OPAMP internal output to ADC disabled. */
00269 #define LL_OPAMP_INTERNAL_OUPUT_ENABLED        OPAMP_CSR_OPAMPINTEN   /*!< OPAMP internal output to ADC enabled.
00270                                                                              - OPAMP1 internal output is connected to ADC1/Channel13
00271                                                                              - OPAMP2 internal output is connected to ADC2/Channel16
00272                                                                              - OPAMP3 internal output is connected to ADC2/Channel18 & ADC3/Channel13
00273                                                                              - OPAMP4 internal output is connected to ADC5/Channel5
00274                                                                              - OPAMP5 internal output is connected to ADC5/Channel3
00275                                                                              - OPAMP6 internal output is connected to ADC4/Channel17
00276                                                                            Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
00282   * @note The switch can be controlled either by a single timer or a combination of them,
00283   *       in this case application has to 'ORed' the values below
00284   *       ex LL_OPAMP_INPUT_MUX_TIM1_CH6 | LL_OPAMP_INPUT_MUX_TIM20_CH6
00285   * @{
00286   */
00287 #define LL_OPAMP_INPUT_MUX_DISABLE       (0x00000000UL)         /*!< OPAMP inputs timer controlled multiplexer mode disabled. */
00288 #define LL_OPAMP_INPUT_MUX_TIM1_CH6      OPAMP_TCMR_T1CMEN      /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM1 OC6. */
00289 #define LL_OPAMP_INPUT_MUX_TIM8_CH6      OPAMP_TCMR_T8CMEN      /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM8 OC6. */
00290 #define LL_OPAMP_INPUT_MUX_TIM20_CH6     OPAMP_TCMR_T20CMEN     /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM20 OC6.
00291                                                                      Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode
00297   * @{
00298   */
00299 #define LL_OPAMP_POWERMODE_NORMALSPEED   (0x00000000UL)         /*!< OPAMP output in normal mode */
00300 #define LL_OPAMP_POWERMODE_HIGHSPEED     OPAMP_CSR_HIGHSPEEDEN  /*!< OPAMP output in highspeed mode */
00301
00302 #define LL_OPAMP_POWERMODE_NORMAL        LL_OPAMP_POWERMODE_NORMALSPEED /*!< OPAMP power mode normal - Old Naming for compatibility */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
00309   * @{
00310   */
00311 #define LL_OPAMP_TRIMMING_FACTORY       (0x00000000UL)           /*!< OPAMP trimming factors set to factory values */
00312 #define LL_OPAMP_TRIMMING_USER          OPAMP_CSR_USERTRIM      /*!< OPAMP trimming factors set to user values */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
00318   * @{
00319   */
00320 #define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA  (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00321 #define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA  (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1                     ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
00322 #define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA  (OPAMP_CSR_TRIMOFFSETP                      | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00323 #define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP                                          ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
00324 #define LL_OPAMP_TRIMMING_NMOS          (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00325 #define LL_OPAMP_TRIMMING_PMOS          (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
00331   * @note   Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
00332   *         not timeout values.
00333   *         For details on delays values, refer to descriptions in source code
00334   *         above each literal definition.
00335   * @{
00336   */
00337
00338 /* Delay for OPAMP startup time (transition from state disable to enable).    */
00339 /* Note: OPAMP startup time depends on board application environment:         */
00340 /*       impedance connected to OPAMP output.                                 */
00341 /*       The delay below is specified under conditions:                       */
00342 /*        - OPAMP in functional mode follower                                 */
00343 /*        - load impedance of 4kOhm (min), 50pF (max)                         */
00344 /* Literal set to maximum value (refer to device datasheet,                   */
00345 /* parameter "tWAKEUP").                                                      */
00346 /* Unit: us                                                                   */
00347 #define LL_OPAMP_DELAY_STARTUP_US         (6)  /*!< Delay for OPAMP startup time */
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported macro ------------------------------------------------------------*/
00357 /** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
00358   * @{
00359   */
00360 /** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
00361   * @{
00362   */
00363 /**
00364   * @brief  Write a value in OPAMP register
00365   * @param  __INSTANCE__ OPAMP Instance
00366   * @param  __REG__ Register to be written
00367   * @param  __VALUE__ Value to be written in the register
00368   * @retval None
00369   */
00370 #define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00371
00372 /**
00373   * @brief  Read a value in OPAMP register
00374   * @param  __INSTANCE__ OPAMP Instance
00375   * @param  __REG__ Register to be read
00376   * @retval Register value
00377   */
00378 #define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00379 /**
00380   * @}
00381   */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /* Exported functions --------------------------------------------------------*/
00388 /** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
00389   * @{
00390   */
00391
00392 /** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
00393   * @{
00394   */
00395
00396 /**
00397   * @brief  Set OPAMP mode calibration or functional.
00398   * @note   OPAMP mode corresponds to functional or calibration mode:
00399   *          - functional mode: OPAMP operation in standalone, follower, ...
00400   *            Set functional mode using function
00401   *            @ref LL_OPAMP_SetFunctionalMode().
00402   *          - calibration mode: offset calibration of the selected
00403   *            transistors differential pair NMOS or PMOS.
00404   * @rmtoll CSR      CALON          LL_OPAMP_SetMode
00405   * @param  OPAMPx OPAMP instance
00406   * @param  Mode This parameter can be one of the following values:
00407   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00408   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00409   * @retval None
00410   */
00411 __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
00412 {
00413   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
00414 }
00415
00416 /**
00417   * @brief  Get OPAMP mode calibration or functional.
00418   * @note   OPAMP mode corresponds to functional or calibration mode:
00419   *          - functional mode: OPAMP operation in standalone, follower, ...
00420   *            Set functional mode using function
00421   *            @ref LL_OPAMP_SetFunctionalMode().
00422   *          - calibration mode: offset calibration of the selected
00423   *            transistors differential pair NMOS or PMOS.
00424   * @rmtoll CSR      CALON          LL_OPAMP_GetMode
00425   * @param  OPAMPx OPAMP instance
00426   * @retval Returned value can be one of the following values:
00427   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00428   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00429   */
00430 __STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
00431 {
00432   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
00433 }
00434
00435 /**
00436   * @brief  Set OPAMP functional mode by setting internal connections.
00437   *         OPAMP operation in standalone, follower, ...
00438   * @note   This function reset bit of calibration mode to ensure
00439   *         to be in functional mode, in order to have OPAMP parameters
00440   *         (inputs selection, ...) set with the corresponding OPAMP mode
00441   *         to be effective.
00442   * @rmtoll CSR      VMSEL          LL_OPAMP_SetFunctionalMode
00443   * @param  OPAMPx OPAMP instance
00444   * @param  FunctionalMode This parameter can be one of the following values:
00445   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00446   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00447   *         @arg @ref LL_OPAMP_MODE_PGA
00448   *         @arg @ref LL_OPAMP_MODE_PGA_IO0
00449   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
00450   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00451   * @retval None
00452   */
00453 __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
00454 {
00455   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
00456   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
00457 }
00458
00459 /**
00460   * @brief  Get OPAMP functional mode from setting of internal connections.
00461   *         OPAMP operation in standalone, follower, ...
00462   * @rmtoll CSR      VMSEL          LL_OPAMP_GetFunctionalMode
00463   * @param  OPAMPx OPAMP instance
00464   * @retval Returned value can be one of the following values:
00465   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00466   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00467   *         @arg @ref LL_OPAMP_MODE_PGA
00468   *         @arg @ref LL_OPAMP_MODE_PGA_IO0
00469   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
00470   *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
00471   */
00472 __STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
00473 {
00474   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL));
00475 }
00476
00477 /**
00478   * @brief  Set OPAMP PGA gain.
00479   * @note   Preliminarily, OPAMP must be set in mode PGA
00480   *         using function @ref LL_OPAMP_SetFunctionalMode().
00481   * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain
00482   * @param  OPAMPx OPAMP instance
00483   * @param  PGAGain This parameter can be one of the following values:
00484   *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
00485   *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
00486   *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
00487   *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
00488   *         @arg @ref LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
00489   *         @arg @ref LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
00490   * @retval None
00491   */
00492 __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
00493 {
00494   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
00495 }
00496
00497 /**
00498   * @brief  Get OPAMP PGA gain.
00499   * @note   Preliminarily, OPAMP must be set in mode PGA
00500   *         using function @ref LL_OPAMP_SetFunctionalMode().
00501   * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain
00502   * @param  OPAMPx OPAMP instance
00503   * @retval Returned value can be one of the following values:
00504   *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
00505   *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
00506   *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
00507   *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
00508   *         @arg @ref LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
00509   *         @arg @ref LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
00510   */
00511 __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
00512 {
00513   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
00514 }
00515
00516 /**
00517   * @brief  Set OPAMP power mode normal or highspeed.
00518   * @note   OPAMP highspeed mode allows output stage to have a better slew rate.
00519   * @rmtoll CSR      HIGHSPEEDEN     LL_OPAMP_SetPowerMode
00520   * @param  OPAMPx OPAMP instance
00521   * @param  PowerMode This parameter can be one of the following values:
00522   *         @arg @ref LL_OPAMP_POWERMODE_NORMALSPEED
00523   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
00527 {
00528   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_HIGHSPEEDEN, PowerMode);
00529 }
00530
00531 /**
00532   * @brief  Get OPAMP power mode normal or highspeed.
00533   * @note   OPAMP highspeed mode allows output stage to have a better slew rate.
00534   * @rmtoll CSR      HIGHSPEEDEN     LL_OPAMP_GetPowerMode
00535   * @param  OPAMPx OPAMP instance
00536   * @retval Returned value can be one of the following values:
00537   *         @arg @ref LL_OPAMP_POWERMODE_NORMALSPEED
00538   *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
00539   */
00540 __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
00541 {
00542   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_HIGHSPEEDEN));
00543 }
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
00549   * @{
00550   */
00551
00552 /**
00553   * @brief  Set OPAMP non-inverting input connection.
00554   * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting
00555   * @param  OPAMPx OPAMP instance
00556   * @param  InputNonInverting This parameter can be one of the following values:
00557   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00558   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
00559   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
00560   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
00561   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
00562   * @retval None
00563   */
00564 __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00565 {
00566   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
00567 }
00568
00569 /**
00570   * @brief  Get OPAMP non-inverting input connection.
00571   * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting
00572   * @param  OPAMPx OPAMP instance
00573   * @retval Returned value can be one of the following values:
00574   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00575   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
00576   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
00577   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
00578   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
00579   */
00580 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
00581 {
00582   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
00583 }
00584
00585 /**
00586   * @brief  Set OPAMP inverting input connection.
00587   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00588   *         or PGA with external capacitors for filtering circuit.
00589   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00590   *         is not used (not connected to GPIO pin).
00591   * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting
00592   * @param  OPAMPx OPAMP instance
00593   * @param  InputInverting This parameter can be one of the following values:
00594   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00595   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00596   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00597   * @retval None
00598   */
00599 __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00600 {
00601   /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11)      */
00602   /* to not modify OPAMP mode follower or PGA.                                */
00603   /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
00604   MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
00605 }
00606
00607 /**
00608   * @brief  Get OPAMP inverting input connection.
00609   * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting
00610   * @param  OPAMPx OPAMP instance
00611   * @retval Returned value can be one of the following values:
00612   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00613   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00614   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00615   */
00616 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
00617 {
00618   uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
00619
00620   /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting     */
00621   /* input not connected.                                                     */
00622   return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
00623 }
00624
00625 /**
00626   * @brief  Set OPAMP non-inverting input secondary connection.
00627   * @rmtoll TCMR     VPSSEL         LL_OPAMP_SetInputNonInvertingSecondary
00628   * @param  OPAMPx OPAMP instance
00629   * @param  InputNonInverting This parameter can be one of the following values:
00630   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
00631   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
00632   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
00633   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
00634   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC_SEC
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00638 {
00639   MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_VPSSEL, InputNonInverting);
00640 }
00641
00642 /**
00643   * @brief  Get OPAMP non-inverting input secondary connection.
00644   * @rmtoll TCMR     VPSSEL         LL_OPAMP_GetInputNonInvertingSecondary
00645   * @param  OPAMPx OPAMP instance
00646   * @retval Returned value can be one of the following values:
00647   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
00648   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
00649   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
00650   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
00651   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC_SEC
00652   */
00653 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
00654 {
00655   return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_VPSSEL));
00656 }
00657
00658 /**
00659   * @brief  Set OPAMP inverting input secondary connection.
00660   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00661   *         or PGA with external capacitors for filtering circuit.
00662   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00663   *         is not used (not connected to GPIO pin).
00664   * @rmtoll TCMR     VMSSEL         LL_OPAMP_SetInputInvertingSecondary
00665   * @param  OPAMPx OPAMP instance
00666   * @param  InputInverting This parameter can be one of the following values:
00667   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
00668   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
00669   *         @arg @ref LL_OPAMP_INPUT_INVERT_PGA_SEC
00670   *         @arg @ref LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
00671   * @retval None
00672   */
00673 __STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00674 {
00675   MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_VMSSEL, InputInverting);
00676 }
00677
00678 /**
00679   * @brief  Get OPAMP inverting input secondary connection.
00680   * @rmtoll TCMR     VMSSEL         LL_OPAMP_GetInputInvertingSecondary
00681   * @param  OPAMPx OPAMP instance
00682   * @retval Returned value can be one of the following values:
00683   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
00684   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
00685   *         @arg @ref LL_OPAMP_INPUT_INVERT_PGA_SEC
00686   *         @arg @ref LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
00687   */
00688 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
00689 {
00690   return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_VMSSEL));
00691 }
00692
00693 /**
00694   * @brief  Set OPAMP inputs multiplexer mode.
00695   * @rmtoll TCMR     TCMEN          LL_OPAMP_SetInputsMuxMode
00696   * @param  OPAMPx OPAMP instance
00697   * @param  InputsMuxMode This parameter can be one of the following values:
00698   *         @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
00699   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
00700   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6
00701   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6  (1)
00702   *         On this STM32 series, this value is not available on all devices. Refer to datasheet for details.
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
00706 {
00707   MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_T1CMEN | OPAMP_TCMR_T8CMEN | OPAMP_TCMR_T20CMEN, InputsMuxMode);
00708 }
00709
00710 /**
00711   * @brief  Get OPAMP inputs multiplexer mode.
00712   * @rmtoll TCMR     TCMEN          LL_OPAMP_GetInputsMuxMode
00713   * @param  OPAMPx OPAMP instance
00714   * @retval Returned value can be one of the following values:
00715   *         @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
00716   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
00717   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6
00718   *         @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6  (1)
00719   *         On this STM32 series, this value is not available on all devices. Refer to datasheet for details.
00720   */
00721 __STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
00722 {
00723   return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_T1CMEN | OPAMP_TCMR_T8CMEN | OPAMP_TCMR_T20CMEN));
00724 }
00725
00726 /**
00727   * @brief  Set OPAMP internal output.
00728   * @note   OPAMP internal output is used to link OPAMP output to ADC input internally.
00729   * @rmtoll CSR      OPAMPINTEN     LL_OPAMP_SetInternalOutput
00730   * @param  OPAMPx OPAMP instance
00731   * @param  InternalOutput This parameter can be one of the following values:
00732   *         @arg @ref LL_OPAMP_INTERNAL_OUPUT_DISABLED
00733   *         @arg @ref LL_OPAMP_INTERNAL_OUPUT_ENABLED
00734   * @retval None
00735   */
00736 __STATIC_INLINE void LL_OPAMP_SetInternalOutput(OPAMP_TypeDef *OPAMPx, uint32_t InternalOutput)
00737 {
00738   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMPINTEN, InternalOutput);
00739 }
00740
00741 /**
00742   * @brief  Get OPAMP internal output state.
00743   * @rmtoll CSR      OPAMPINTEN     LL_OPAMP_GetInternalOutput
00744   * @param  OPAMPx OPAMP instance
00745   * @retval Returned value can be one of the following values:
00746   *         @arg @ref LL_OPAMP_INTERNAL_OUPUT_DISABLED
00747   *         @arg @ref LL_OPAMP_INTERNAL_OUPUT_ENABLED
00748   */
00749 __STATIC_INLINE uint32_t LL_OPAMP_GetInternalOutput(OPAMP_TypeDef *OPAMPx)
00750 {
00751   return READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPINTEN);
00752 }
00753
00754 /**
00755   * @}
00756   */
00757
00758 /** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Set OPAMP trimming mode.
00764   * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode
00765   * @param  OPAMPx OPAMP instance
00766   * @param  TrimmingMode This parameter can be one of the following values:
00767   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00768   *         @arg @ref LL_OPAMP_TRIMMING_USER
00769   * @retval None
00770   */
00771 __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
00772 {
00773   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
00774 }
00775
00776 /**
00777   * @brief  Get OPAMP trimming mode.
00778   * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode
00779   * @param  OPAMPx OPAMP instance
00780   * @retval Returned value can be one of the following values:
00781   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00782   *         @arg @ref LL_OPAMP_TRIMMING_USER
00783   */
00784 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
00785 {
00786   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
00787 }
00788
00789 /**
00790   * @brief  Set OPAMP offset to calibrate the selected transistors
00791   *         differential pair NMOS or PMOS.
00792   * @note   Preliminarily, OPAMP must be set in mode calibration
00793   *         using function @ref LL_OPAMP_SetMode().
00794   * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection
00795   * @param  OPAMPx OPAMP instance
00796   * @param  TransistorsDiffPair This parameter can be one of the following values:
00797   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00798   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00799   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00800   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00801   *
00802   *         (1) Default parameters to be used for calibration
00803   *             using two trimming steps (one with each transistors differential
00804   *             pair NMOS and PMOS)
00805   * @retval None
00806   */
00807 __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
00808 {
00809   /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
00810   /* containing other bits reserved for other purpose.                        */
00811   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
00812 }
00813
00814 /**
00815   * @brief  Get OPAMP offset to calibrate the selected transistors
00816   *         differential pair NMOS or PMOS.
00817   * @note   Preliminarily, OPAMP must be set in mode calibration
00818   *         using function @ref LL_OPAMP_SetMode().
00819   * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection
00820   * @param  OPAMPx OPAMP instance
00821   * @retval Returned value can be one of the following values:
00822   *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)
00823   *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)
00824   *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
00825   *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
00826   *
00827   *         (1) Default parameters to be used for calibration
00828   *             using two trimming steps (one with each transistors differential
00829   *             pair NMOS and PMOS)
00830   */
00831 __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
00832 {
00833   uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
00834
00835   return (CalibrationSelection |
00836           (((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_CSR_TRIMOFFSETP : OPAMP_CSR_TRIMOFFSETN));
00837 }
00838
00839 /**
00840   * @brief  Get OPAMP calibration result of toggling output.
00841   * @note   This functions returns:
00842   *         0 if OPAMP calibration output is reset
00843   *         1 if OPAMP calibration output is set
00844   * @rmtoll CSR      OUTCAL         LL_OPAMP_IsCalibrationOutputSet
00845   * @param  OPAMPx OPAMP instance
00846   * @retval State of bit (1 or 0).
00847   */
00848 __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
00849 {
00850   return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL) ? 1UL : 0UL);
00851 }
00852
00853 /**
00854   * @brief  Set OPAMP trimming factor for the selected transistors
00855   *         differential pair NMOS or PMOS, corresponding to the selected
00856   *         power mode.
00857   * @rmtoll CSR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
00858   *         CSR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue
00859   * @param  OPAMPx OPAMP instance
00860   * @param  TransistorsDiffPair This parameter can be one of the following values:
00861   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00862   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00863   * @param  TrimmingValue 0x00...0x1F
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair,
00867                                                uint32_t TrimmingValue)
00868 {
00869   MODIFY_REG(OPAMPx->CSR,
00870              (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
00871              TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
00872 }
00873
00874 /**
00875   * @brief  Get OPAMP trimming factor for the selected transistors
00876   *         differential pair NMOS or PMOS, corresponding to the selected
00877   *         power mode.
00878   * @rmtoll CSR      TRIMOFFSETN    LL_OPAMP_GetTrimmingValue\n
00879   *         CSR      TRIMOFFSETP    LL_OPAMP_GetTrimmingValue
00880   * @param  OPAMPx OPAMP instance
00881   * @param  TransistorsDiffPair This parameter can be one of the following values:
00882   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00883   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00884   * @retval 0x0...0x1F
00885   */
00886 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
00887 {
00888   return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00889                     >> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
00890 }
00891
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
00897   * @{
00898   */
00899 /**
00900   * @brief  Enable OPAMP instance.
00901   * @note   After enable from off state, OPAMP requires a delay
00902   *         to fulfill wake up time specification.
00903   *         Refer to device datasheet, parameter "tWAKEUP".
00904   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable
00905   * @param  OPAMPx OPAMP instance
00906   * @retval None
00907   */
00908 __STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
00909 {
00910   SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00911 }
00912
00913 /**
00914   * @brief  Disable OPAMP instance.
00915   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable
00916   * @param  OPAMPx OPAMP instance
00917   * @retval None
00918   */
00919 __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
00920 {
00921   CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00922 }
00923
00924 /**
00925   * @brief  Get OPAMP instance enable state
00926   *         (0: OPAMP is disabled, 1: OPAMP is enabled)
00927   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled
00928   * @param  OPAMPx OPAMP instance
00929   * @retval State of bit (1 or 0).
00930   */
00931 __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
00932 {
00933   return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL);
00934 }
00935
00936 /**
00937   * @brief  Lock OPAMP instance.
00938   * @note   Once locked, OPAMP configuration can be accessed in read-only.
00939   * @note   The only way to unlock the OPAMP is a device hardware reset.
00940   * @rmtoll CSR      LOCK           LL_OPAMP_Lock
00941   * @param  OPAMPx OPAMP instance
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
00945 {
00946   SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
00947 }
00948
00949 /**
00950   * @brief  Get OPAMP lock state
00951   *         (0: OPAMP is unlocked, 1: OPAMP is locked).
00952   * @note   Once locked, OPAMP configuration can be accessed in read-only.
00953   * @note   The only way to unlock the OPAMP is a device hardware reset.
00954   * @rmtoll CSR      LOCK           LL_OPAMP_IsLocked
00955   * @param  OPAMPx OPAMP instance
00956   * @retval State of bit (1 or 0).
00957   */
00958 __STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
00959 {
00960   return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK)) ? 1UL : 0UL);
00961 }
00962
00963 /**
00964   * @brief  Lock OPAMP instance timer controlled mux
00965   * @note   Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
00966   * @note   The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
00967   * @rmtoll TCMR     LOCK           LL_OPAMP_LockTimerMux
00968   * @param  OPAMPx OPAMP instance
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_OPAMP_LockTimerMux(OPAMP_TypeDef *OPAMPx)
00972 {
00973   SET_BIT(OPAMPx->TCMR, OPAMP_TCMR_LOCK);
00974 }
00975
00976 /**
00977   * @brief  Get OPAMP timer controlled mux lock state
00978   *         (0: OPAMP timer controlled mux is unlocked, 1: OPAMP timer controlled mux is locked).
00979   * @note   Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
00980   * @note   The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
00981   * @rmtoll TCMR     LOCK           LL_OPAMP_IsTimerMuxLocked
00982   * @param  OPAMPx OPAMP instance
00983   * @retval State of bit (1 or 0).
00984   */
00985 __STATIC_INLINE uint32_t LL_OPAMP_IsTimerMuxLocked(OPAMP_TypeDef *OPAMPx)
00986 {
00987   return ((READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_LOCK) == (OPAMP_TCMR_LOCK)) ? 1UL : 0UL);
00988 }
00989
00990 /**
00991   * @}
00992   */
00993
00994 #if defined(USE_FULL_LL_DRIVER)
00995 /** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
00996   * @{
00997   */
00998
00999 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
01000 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
01001 void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
01002
01003 /**
01004   * @}
01005   */
01006 #endif /* USE_FULL_LL_DRIVER */
01007
01008 /**
01009   * @}
01010   */
01011
01012 /**
01013   * @}
01014   */
01015
01016 #endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
01017
01018 /**
01019   * @}
01020   */
01021
01022 #ifdef __cplusplus
01023 }
01024 #endif
01025
01026 #endif /* STM32G4xx_LL_OPAMP_H */
01027
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_pwr.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_pwr.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_pwr.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 /** @addtogroup STM32G4xx_LL_Driver
00025   * @{
00026   */
00027
00028 #if defined(PWR)
00029
00030 /** @defgroup PWR_LL PWR
00031   * @{
00032   */
00033
00034 /* Private types -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 /* Private constants ---------------------------------------------------------*/
00037 /* Private macros ------------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039
00040 /* Exported functions --------------------------------------------------------*/
00041 /** @addtogroup PWR_LL_Exported_Functions
00042   * @{
00043   */
00044
00045 /** @addtogroup PWR_LL_EF_Init
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  De-initialize the PWR registers to their default reset values.
00051   * @retval An ErrorStatus enumeration value:
00052   *          - SUCCESS: PWR registers are de-initialized
00053   *          - ERROR: not applicable
00054   */
00055 ErrorStatus LL_PWR_DeInit(void)
00056 {
00057   /* Force reset of PWR clock */
00058   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
00059
00060   /* Release reset of PWR clock */
00061   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
00062
00063   return SUCCESS;
00064 }
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077 #endif /* defined(PWR) */
00078 /**
00079   * @}
00080   */
00081
00082 #endif /* USE_FULL_LL_DRIVER */
00083
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_pwr.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_PWR_H
00021 #define STM32G4xx_LL_PWR_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(PWR)
00035
00036 /** @defgroup PWR_LL PWR
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044
00045 /* Private macros ------------------------------------------------------------*/
00046
00047 /* Exported types ------------------------------------------------------------*/
00048 /* Exported constants --------------------------------------------------------*/
00049 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00054   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00055   * @{
00056   */
00057 #define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
00058 #define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
00059 #define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
00060 #define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
00061 #define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
00062 #define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
00063 #define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00069   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00070   * @{
00071   */
00072 #define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
00073 #define LL_PWR_SR1_SBF                     PWR_SR1_SBF
00074 #define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
00075 #define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
00076 #define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
00077 #define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
00078 #define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
00079 #if defined(PWR_SR2_PVMO4)
00080 #define LL_PWR_SR2_PVMO4                   PWR_SR2_PVMO4
00081 #endif /* PWR_SR2_PVMO4 */
00082 #if defined(PWR_SR2_PVMO3)
00083 #define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3
00084 #endif /* PWR_SR2_PVMO3 */
00085 #if defined(PWR_SR2_PVMO2)
00086 #define LL_PWR_SR2_PVMO2                   PWR_SR2_PVMO2
00087 #endif /* PWR_SR2_PVMO2 */
00088 #if defined(PWR_SR2_PVMO1)
00089 #define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1
00090 #endif /* PWR_SR2_PVMO1 */
00091 #define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
00092 #define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
00093 #define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
00094 #define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
00100   * @{
00101   */
00102 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0)
00103 #define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1)
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
00109   * @{
00110   */
00111 #define LL_PWR_MODE_STOP0                  (PWR_CR1_LPMS_STOP0)
00112 #define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_STOP1)
00113 #define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_STANDBY)
00114 #define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_SHUTDOWN)
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
00120   * @{
00121   */
00122 #if defined(PWR_CR2_PVME1)
00123 #define LL_PWR_PVM_VDDA_COMP               (PWR_CR2_PVME1)     /* Monitoring VDDA vs. x.xV */
00124 #endif
00125 #if defined(PWR_CR2_PVME2)
00126 #define LL_PWR_PVM_VDDA_FASTDAC            (PWR_CR2_PVME2)     /* Monitoring VDDA vs. x.xV */
00127 #endif
00128 #if defined(PWR_CR2_PVME3)
00129 #define LL_PWR_PVM_VDDA_ADC                (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */
00130 #endif
00131 #if defined(PWR_CR2_PVME4)
00132 #define LL_PWR_PVM_VDDA_OPAMP_DAC          (PWR_CR2_PVME4)     /* Monitoring VDDA vs. 1x.xV   */
00133 #endif
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
00139   * @{
00140   */
00141 #define LL_PWR_PVDLEVEL_0                  (PWR_CR2_PLS_LEV0)  /* VPVD0 around 2.0 V */
00142 #define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_LEV1)  /* VPVD1 around 2.2 V */
00143 #define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_LEV2)  /* VPVD2 around 2.4 V */
00144 #define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_LEV3)  /* VPVD3 around 2.5 V */
00145 #define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_LEV4)  /* VPVD4 around 2.6 V */
00146 #define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_LEV5)  /* VPVD5 around 2.8 V */
00147 #define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_LEV6)  /* VPVD6 around 2.9 V */
00148 #define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_LEV7)  /* External input analog voltage   (Compare internally to VREFINT) */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
00154   * @{
00155   */
00156 #define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
00157 #define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
00158 #define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
00159 #define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
00160 #define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
00166   * @{
00167   */
00168 #define LL_PWR_BATT_CHARG_RESISTOR_5K      ((uint32_t)0x00000000)
00169 #define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup PWR_LL_EC_GPIO GPIO
00175   * @{
00176   */
00177 #define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
00178 #define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
00179 #define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
00180 #define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
00181 #define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
00182 #define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
00183 #define LL_PWR_GPIO_G                      ((uint32_t)(&(PWR->PUCRG)))
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
00189   * @{
00190   */
00191 #define LL_PWR_GPIO_BIT_0                  ((uint32_t)0x00000001)
00192 #define LL_PWR_GPIO_BIT_1                  ((uint32_t)0x00000002)
00193 #define LL_PWR_GPIO_BIT_2                  ((uint32_t)0x00000004)
00194 #define LL_PWR_GPIO_BIT_3                  ((uint32_t)0x00000008)
00195 #define LL_PWR_GPIO_BIT_4                  ((uint32_t)0x00000010)
00196 #define LL_PWR_GPIO_BIT_5                  ((uint32_t)0x00000020)
00197 #define LL_PWR_GPIO_BIT_6                  ((uint32_t)0x00000040)
00198 #define LL_PWR_GPIO_BIT_7                  ((uint32_t)0x00000080)
00199 #define LL_PWR_GPIO_BIT_8                  ((uint32_t)0x00000100)
00200 #define LL_PWR_GPIO_BIT_9                  ((uint32_t)0x00000200)
00201 #define LL_PWR_GPIO_BIT_10                 ((uint32_t)0x00000400)
00202 #define LL_PWR_GPIO_BIT_11                 ((uint32_t)0x00000800)
00203 #define LL_PWR_GPIO_BIT_12                 ((uint32_t)0x00001000)
00204 #define LL_PWR_GPIO_BIT_13                 ((uint32_t)0x00002000)
00205 #define LL_PWR_GPIO_BIT_14                 ((uint32_t)0x00004000)
00206 #define LL_PWR_GPIO_BIT_15                 ((uint32_t)0x00008000)
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported macro ------------------------------------------------------------*/
00216 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00217   * @{
00218   */
00219
00220 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
00221   * @{
00222   */
00223
00224 /**
00225   * @brief  Write a value in PWR register
00226   * @param  __REG__ Register to be written
00227   * @param  __VALUE__ Value to be written in the register
00228   * @retval None
00229   */
00230 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00231
00232 /**
00233   * @brief  Read a value in PWR register
00234   * @param  __REG__ Register to be read
00235   * @retval Register value
00236   */
00237 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246
00247 /* Exported functions --------------------------------------------------------*/
00248 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00249   * @{
00250   */
00251
00252 /** @defgroup PWR_LL_EF_Configuration Configuration
00253   * @{
00254   */
00255
00256 /**
00257   * @brief  Switch the regulator from main mode to low-power mode
00258   * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
00259   * @retval None
00260   */
00261 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
00262 {
00263   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00264 }
00265
00266 /**
00267   * @brief  Switch the regulator from low-power mode to main mode
00268   * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
00272 {
00273   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00274 }
00275
00276 /**
00277   * @brief  Check if the regulator is in low-power mode
00278   * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
00279   * @retval State of bit (1 or 0).
00280   */
00281 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
00282 {
00283   uint32_t temp;
00284   temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
00285
00286   return ((temp == (PWR_CR1_LPR))?1U:0U);
00287
00288 }
00289
00290 /**
00291   * @brief  Switch from run main mode to run low-power mode.
00292   * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
00296 {
00297   LL_PWR_EnableLowPowerRunMode();
00298 }
00299
00300 /**
00301   * @brief  Switch from run main mode to low-power mode.
00302   * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
00303   * @retval None
00304   */
00305 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
00306 {
00307   LL_PWR_DisableLowPowerRunMode();
00308 }
00309
00310 /**
00311   * @brief  Set the main internal regulator output voltage
00312   * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
00313   * @param  VoltageScaling This parameter can be one of the following values:
00314   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00315   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00316   * @retval None
00317   */
00318 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
00319 {
00320   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
00321 }
00322
00323 /**
00324   * @brief  Get the main internal regulator output voltage
00325   * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
00326   * @retval Returned value can be one of the following values:
00327   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00328   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00329   */
00330 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
00331 {
00332   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
00333 }
00334
00335 #if defined(PWR_CR5_R1MODE)
00336 /**
00337   * @brief  Enable main regulator voltage range 1 boost mode
00338   * @rmtoll CR5          R1MODE        LL_PWR_EnableRange1BoostMode
00339   * @retval None
00340   */
00341 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
00342 {
00343   CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
00344 }
00345
00346 /**
00347   * @brief  Disable main regulator voltage range 1 boost mode
00348   * @rmtoll CR5          R1MODE        LL_PWR_DisableRange1BoostMode
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
00352 {
00353   SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
00354 }
00355
00356 /**
00357   * @brief  Check if the main regulator voltage range 1 boost mode is enabled
00358   * @rmtoll CR5          R1MODE        LL_PWR_IsEnabledRange1BoostMode
00359   * @retval Inverted state of bit (0 or 1).
00360   */
00361 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
00362 {
00363   uint32_t temp;
00364   temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
00365
00366   return ((temp == (0U))?1U:0U);
00367 }
00368 #endif /* PWR_CR5_R1MODE */
00369
00370 /**
00371   * @brief  Enable access to the backup domain
00372   * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
00373   * @retval None
00374   */
00375 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00376 {
00377   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00378 }
00379
00380 /**
00381   * @brief  Disable access to the backup domain
00382   * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
00383   * @retval None
00384   */
00385 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00386 {
00387   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00388 }
00389
00390 /**
00391   * @brief  Check if the backup domain is enabled
00392   * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
00393   * @retval State of bit (1 or 0).
00394   */
00395 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00396 {
00397   uint32_t temp;
00398   temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
00399
00400   return ((temp == (PWR_CR1_DBP))?1U:0U);
00401
00402 }
00403
00404 /**
00405   * @brief  Set Low-Power mode
00406   * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
00407   * @param  LowPowerMode This parameter can be one of the following values:
00408   *         @arg @ref LL_PWR_MODE_STOP0
00409   *         @arg @ref LL_PWR_MODE_STOP1
00410   *         @arg @ref LL_PWR_MODE_STANDBY
00411   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
00415 {
00416   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
00417 }
00418
00419 /**
00420   * @brief  Get Low-Power mode
00421   * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
00422   * @retval Returned value can be one of the following values:
00423   *         @arg @ref LL_PWR_MODE_STOP0
00424   *         @arg @ref LL_PWR_MODE_STOP1
00425   *         @arg @ref LL_PWR_MODE_STANDBY
00426   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00427   */
00428 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00429 {
00430   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
00431 }
00432
00433 #if defined(PWR_CR3_UCPD_STDBY)
00434 /**
00435   * @brief  Enable the USB Type-C and Power Delivery memorization in Standby mode.
00436   * @note   This function must be called just before entering Standby mode.
00437   * @rmtoll CR3          UCPD_STDBY    LL_PWR_EnableUCPDStandbyMode
00438   * @retval None
00439   */
00440 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
00441 {
00442   SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
00443 }
00444
00445 /**
00446   * @brief  Disable the USB Type-C and Power Delivery memorization in Standby mode.
00447   * @note   This function must be called after exiting Standby mode and before any
00448   *         UCPD configuration update.
00449   * @rmtoll CR3          UCPD_STDBY     LL_PWR_DisableUCPDStandbyMode
00450   * @retval None
00451   */
00452 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
00453 {
00454   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
00455 }
00456
00457 /**
00458   * @brief  Check the USB Type-C and Power Delivery Standby mode memorization state.
00459   * @rmtoll CR3          UCPD_STDBY           LL_PWR_IsEnabledUCPDStandbyMode
00460   * @retval State of bit (1 or 0).
00461   */
00462 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
00463 {
00464
00465   return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
00466
00467 }
00468 #endif /* PWR_CR3_UCPD_STDBY */
00469
00470 #if defined(PWR_CR3_UCPD_DBDIS)
00471 /**
00472   * @brief  Enable the USB Type-C and power delivery dead battery pull-down behavior
00473   *         on UCPD CC1 and CC2 pins.
00474   * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
00475   *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
00476   *         to disable it in all cases, either to stop this pull-down or to hand over
00477   *         control to the UCPD (which should therefore be initialized before doing the disable).
00478   * @rmtoll CR3          UCPD_DBDIS           LL_PWR_EnableUCPDDeadBattery
00479   * @retval None
00480   */
00481 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
00482 {
00483   CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
00484 }
00485
00486 /**
00487   * @brief  Disable the USB Type-C and power delivery dead battery pull-down behavior
00488   *         on UCPD CC1 and CC2 pins.
00489   * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
00490   *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
00491   *         to disable it in all cases, either to stop this pull-down or to hand over
00492   *         control to the UCPD (which should therefore be initialized before doing the disable).
00493   * @rmtoll CR3          UCPD_DBDIS           LL_PWR_DisableUCPDDeadBattery
00494   * @retval None
00495   */
00496 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
00497 {
00498   SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
00499 }
00500
00501 /**
00502   * @brief  Check the USB Type-C and power delivery dead battery pull-down behavior
00503   *         on UCPD CC1 and CC2 pins.
00504   * @note   After exiting reset, the USB Type-C dead battery behavior is enabled,
00505   *         which may have a pull-down effect on CC1 and CC2 pins. It is recommended
00506   *         to disable it in all cases, either to stop this pull-down or to hand over
00507   *         control to the UCPD (which should therefore be initialized before doing the disable).
00508   * @rmtoll CR3          UCPD_DBDIS           LL_PWR_IsEnabledUCPDDeadBattery
00509   * @retval State of feature (1 : enabled; 0 : disabled).
00510   */
00511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
00512 {
00513   return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
00514 }
00515 #endif /* PWR_CR3_UCPD_DBDIS */
00516
00517 #if defined(PWR_CR2_USV)
00518 /**
00519   * @brief  Enable VDDUSB supply
00520   * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
00521   * @retval None
00522   */
00523 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
00524 {
00525   SET_BIT(PWR->CR2, PWR_CR2_USV);
00526 }
00527
00528 /**
00529   * @brief  Disable VDDUSB supply
00530   * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
00531   * @retval None
00532   */
00533 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
00534 {
00535   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00536 }
00537
00538 /**
00539   * @brief  Check if VDDUSB supply is enabled
00540   * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
00541   * @retval State of bit (1 or 0).
00542   */
00543 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
00544 {
00545   uint32_t temp;
00546   temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
00547
00548   return ((temp == (PWR_CR2_USV))?1U:0U);
00549
00550 }
00551 #endif
00552
00553 #if defined(PWR_CR2_IOSV)
00554 /**
00555   * @brief  Enable VDDIO2 supply
00556   * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
00557   * @retval None
00558   */
00559 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
00560 {
00561   SET_BIT(PWR->CR2, PWR_CR2_IOSV);
00562 }
00563
00564 /**
00565   * @brief  Disable VDDIO2 supply
00566   * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
00567   * @retval None
00568   */
00569 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
00570 {
00571   CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
00572 }
00573
00574 /**
00575   * @brief  Check if VDDIO2 supply is enabled
00576   * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
00577   * @retval State of bit (1 or 0).
00578   */
00579 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
00580 {
00581   uint32_t temp;
00582   temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
00583
00584   return ((temp == (PWR_CR2_IOSV))?1U:0U);
00585
00586 }
00587 #endif
00588
00589 /**
00590   * @brief  Enable the Power Voltage Monitoring on a peripheral
00591   * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\n
00592   *         CR2          PVME2         LL_PWR_EnablePVM\n
00593   *         CR2          PVME3         LL_PWR_EnablePVM\n
00594   *         CR2          PVME4         LL_PWR_EnablePVM
00595   * @param  PeriphVoltage This parameter can be one of the following values:
00596   *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
00597   *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
00598   *         @arg @ref LL_PWR_PVM_VDDA_ADC
00599   *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
00600   *
00601   *         (*) value not defined in all devices
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
00605 {
00606   SET_BIT(PWR->CR2, PeriphVoltage);
00607 }
00608
00609 /**
00610   * @brief  Disable the Power Voltage Monitoring on a peripheral
00611   * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\n
00612   *         CR2          PVME2         LL_PWR_DisablePVM\n
00613   *         CR2          PVME3         LL_PWR_DisablePVM\n
00614   *         CR2          PVME4         LL_PWR_DisablePVM
00615   * @param  PeriphVoltage This parameter can be one of the following values:
00616   *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
00617   *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
00618   *         @arg @ref LL_PWR_PVM_VDDA_ADC
00619   *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
00620   *
00621   *         (*) value not defined in all devices
00622   * @retval None
00623   */
00624 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
00625 {
00626   CLEAR_BIT(PWR->CR2, PeriphVoltage);
00627 }
00628
00629 /**
00630   * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
00631   * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\n
00632   *         CR2          PVME2         LL_PWR_IsEnabledPVM\n
00633   *         CR2          PVME3         LL_PWR_IsEnabledPVM\n
00634   *         CR2          PVME4         LL_PWR_IsEnabledPVM
00635   * @param  PeriphVoltage This parameter can be one of the following values:
00636   *         @arg @ref LL_PWR_PVM_VDDA_COMP     (*)
00637   *         @arg @ref LL_PWR_PVM_VDDA_FASTDAC  (*)
00638   *         @arg @ref LL_PWR_PVM_VDDA_ADC
00639   *         @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
00640   *
00641   *         (*) value not defined in all devices
00642   * @retval State of bit (1 or 0).
00643   */
00644 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
00645 {
00646   uint32_t temp;
00647   temp = READ_BIT(PWR->CR2, PeriphVoltage);
00648
00649   return ((temp == (PeriphVoltage))?1U:0U);
00650
00651 }
00652
00653 /**
00654   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00655   * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel
00656   * @param  PVDLevel This parameter can be one of the following values:
00657   *         @arg @ref LL_PWR_PVDLEVEL_0
00658   *         @arg @ref LL_PWR_PVDLEVEL_1
00659   *         @arg @ref LL_PWR_PVDLEVEL_2
00660   *         @arg @ref LL_PWR_PVDLEVEL_3
00661   *         @arg @ref LL_PWR_PVDLEVEL_4
00662   *         @arg @ref LL_PWR_PVDLEVEL_5
00663   *         @arg @ref LL_PWR_PVDLEVEL_6
00664   *         @arg @ref LL_PWR_PVDLEVEL_7
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00668 {
00669   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
00670 }
00671
00672 /**
00673   * @brief  Get the voltage threshold detection
00674   * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel
00675   * @retval Returned value can be one of the following values:
00676   *         @arg @ref LL_PWR_PVDLEVEL_0
00677   *         @arg @ref LL_PWR_PVDLEVEL_1
00678   *         @arg @ref LL_PWR_PVDLEVEL_2
00679   *         @arg @ref LL_PWR_PVDLEVEL_3
00680   *         @arg @ref LL_PWR_PVDLEVEL_4
00681   *         @arg @ref LL_PWR_PVDLEVEL_5
00682   *         @arg @ref LL_PWR_PVDLEVEL_6
00683   *         @arg @ref LL_PWR_PVDLEVEL_7
00684   */
00685 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00686 {
00687   return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
00688 }
00689
00690 /**
00691   * @brief  Enable Power Voltage Detector
00692   * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00696 {
00697   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00698 }
00699
00700 /**
00701   * @brief  Disable Power Voltage Detector
00702   * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00706 {
00707   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00708 }
00709
00710 /**
00711   * @brief  Check if Power Voltage Detector is enabled
00712   * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
00713   * @retval State of bit (1 or 0).
00714   */
00715 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00716 {
00717   uint32_t temp;
00718   temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
00719
00720   return ((temp == (PWR_CR2_PVDE))?1U:0U);
00721 }
00722
00723 /**
00724   * @brief  Enable Internal Wake-up line
00725   * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
00726   * @retval None
00727   */
00728 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
00729 {
00730   SET_BIT(PWR->CR3, PWR_CR3_EIWF);
00731 }
00732
00733 /**
00734   * @brief  Disable Internal Wake-up line
00735   * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
00739 {
00740   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
00741 }
00742
00743 /**
00744   * @brief  Check if Internal Wake-up line is enabled
00745   * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
00746   * @retval State of bit (1 or 0).
00747   */
00748 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
00749 {
00750   return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
00751 }
00752
00753 /**
00754   * @brief  Enable pull-up and pull-down configuration
00755   * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
00756   * @retval None
00757   */
00758 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
00759 {
00760   SET_BIT(PWR->CR3, PWR_CR3_APC);
00761 }
00762
00763 /**
00764   * @brief  Disable pull-up and pull-down configuration
00765   * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
00766   * @retval None
00767   */
00768 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
00769 {
00770   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00771 }
00772
00773 /**
00774   * @brief  Check if pull-up and pull-down configuration  is enabled
00775   * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
00776   * @retval State of bit (1 or 0).
00777   */
00778 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
00779 {
00780   uint32_t temp;
00781   temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
00782
00783   return ((temp == (PWR_CR3_APC))?1U:0U);
00784 }
00785
00786 /**
00787   * @brief  Enable SRAM2 content retention in Standby mode
00788   * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
00792 {
00793   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00794 }
00795
00796 /**
00797   * @brief  Disable SRAM2 content retention in Standby mode
00798   * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
00802 {
00803   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00804 }
00805
00806 /**
00807   * @brief  Check if SRAM2 content retention in Standby mode  is enabled
00808   * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention
00809   * @retval State of bit (1 or 0).
00810   */
00811 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
00812 {
00813   uint32_t temp;
00814   temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
00815
00816   return ((temp == (PWR_CR3_RRS))?1U:0U);
00817 }
00818
00819 /**
00820   * @brief  Enable the WakeUp PINx functionality
00821   * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
00822   *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
00823   *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
00824   *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
00825   *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
00826   * @param  WakeUpPin This parameter can be one of the following values:
00827   *         @arg @ref LL_PWR_WAKEUP_PIN1
00828   *         @arg @ref LL_PWR_WAKEUP_PIN2
00829   *         @arg @ref LL_PWR_WAKEUP_PIN3
00830   *         @arg @ref LL_PWR_WAKEUP_PIN4
00831   *         @arg @ref LL_PWR_WAKEUP_PIN5
00832   * @retval None
00833   */
00834 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00835 {
00836   SET_BIT(PWR->CR3, WakeUpPin);
00837 }
00838
00839 /**
00840   * @brief  Disable the WakeUp PINx functionality
00841   * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
00842   *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
00843   *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
00844   *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
00845   *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
00846   * @param  WakeUpPin This parameter can be one of the following values:
00847   *         @arg @ref LL_PWR_WAKEUP_PIN1
00848   *         @arg @ref LL_PWR_WAKEUP_PIN2
00849   *         @arg @ref LL_PWR_WAKEUP_PIN3
00850   *         @arg @ref LL_PWR_WAKEUP_PIN4
00851   *         @arg @ref LL_PWR_WAKEUP_PIN5
00852   * @retval None
00853   */
00854 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00855 {
00856   CLEAR_BIT(PWR->CR3, WakeUpPin);
00857 }
00858
00859 /**
00860   * @brief  Check if the WakeUp PINx functionality is enabled
00861   * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
00862   *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
00863   *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
00864   *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
00865   *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
00866   * @param  WakeUpPin This parameter can be one of the following values:
00867   *         @arg @ref LL_PWR_WAKEUP_PIN1
00868   *         @arg @ref LL_PWR_WAKEUP_PIN2
00869   *         @arg @ref LL_PWR_WAKEUP_PIN3
00870   *         @arg @ref LL_PWR_WAKEUP_PIN4
00871   *         @arg @ref LL_PWR_WAKEUP_PIN5
00872   * @retval State of bit (1 or 0).
00873   */
00874 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00875 {
00876   uint32_t temp;
00877   temp = READ_BIT(PWR->CR3, WakeUpPin);
00878
00879   return ((temp == (WakeUpPin))?1U:0U);
00880 }
00881
00882 /**
00883   * @brief  Set the resistor impedance
00884   * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
00885   * @param  Resistor This parameter can be one of the following values:
00886   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00887   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
00891 {
00892   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
00893 }
00894
00895 /**
00896   * @brief  Get the resistor impedance
00897   * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
00898   * @retval Returned value can be one of the following values:
00899   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00900   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00901   */
00902 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
00903 {
00904   return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
00905 }
00906
00907 /**
00908   * @brief  Enable battery charging
00909   * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
00910   * @retval None
00911   */
00912 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
00913 {
00914   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00915 }
00916
00917 /**
00918   * @brief  Disable battery charging
00919   * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
00923 {
00924   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00925 }
00926
00927 /**
00928   * @brief  Check if battery charging is enabled
00929   * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
00930   * @retval State of bit (1 or 0).
00931   */
00932 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
00933 {
00934   uint32_t temp;
00935   temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
00936
00937   return ((temp == (PWR_CR4_VBE))?1U:0U);
00938 }
00939
00940 /**
00941   * @brief  Set the Wake-Up pin polarity low for the event detection
00942   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
00943   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
00944   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
00945   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
00946   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow
00947   * @param  WakeUpPin This parameter can be one of the following values:
00948   *         @arg @ref LL_PWR_WAKEUP_PIN1
00949   *         @arg @ref LL_PWR_WAKEUP_PIN2
00950   *         @arg @ref LL_PWR_WAKEUP_PIN3
00951   *         @arg @ref LL_PWR_WAKEUP_PIN4
00952   *         @arg @ref LL_PWR_WAKEUP_PIN5
00953   * @retval None
00954   */
00955 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
00956 {
00957   SET_BIT(PWR->CR4, WakeUpPin);
00958 }
00959
00960 /**
00961   * @brief  Set the Wake-Up pin polarity high for the event detection
00962   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
00963   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
00964   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
00965   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
00966   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh
00967   * @param  WakeUpPin This parameter can be one of the following values:
00968   *         @arg @ref LL_PWR_WAKEUP_PIN1
00969   *         @arg @ref LL_PWR_WAKEUP_PIN2
00970   *         @arg @ref LL_PWR_WAKEUP_PIN3
00971   *         @arg @ref LL_PWR_WAKEUP_PIN4
00972   *         @arg @ref LL_PWR_WAKEUP_PIN5
00973   * @retval None
00974   */
00975 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
00976 {
00977   CLEAR_BIT(PWR->CR4, WakeUpPin);
00978 }
00979
00980 /**
00981   * @brief  Get the Wake-Up pin polarity for the event detection
00982   * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
00983   *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
00984   *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
00985   *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
00986   *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow
00987   * @param  WakeUpPin This parameter can be one of the following values:
00988   *         @arg @ref LL_PWR_WAKEUP_PIN1
00989   *         @arg @ref LL_PWR_WAKEUP_PIN2
00990   *         @arg @ref LL_PWR_WAKEUP_PIN3
00991   *         @arg @ref LL_PWR_WAKEUP_PIN4
00992   *         @arg @ref LL_PWR_WAKEUP_PIN5
00993   * @retval State of bit (1 or 0).
00994   */
00995 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
00996 {
00997   uint32_t temp;
00998   temp = READ_BIT(PWR->CR4, WakeUpPin);
00999
01000   return ((temp == (WakeUpPin))?1U:0U);
01001 }
01002
01003 /**
01004   * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
01005   * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
01006   *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
01007   *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
01008   *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
01009   *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
01010   *         PUCRF        PU0-15        LL_PWR_EnableGPIOPullUp\n
01011   *         PUCRG        PU0-15        LL_PWR_EnableGPIOPullUp\n
01012   * @param  GPIO This parameter can be one of the following values:
01013   *         @arg @ref LL_PWR_GPIO_A
01014   *         @arg @ref LL_PWR_GPIO_B
01015   *         @arg @ref LL_PWR_GPIO_C
01016   *         @arg @ref LL_PWR_GPIO_D
01017   *         @arg @ref LL_PWR_GPIO_E
01018   *         @arg @ref LL_PWR_GPIO_F
01019   *         @arg @ref LL_PWR_GPIO_G
01020   *
01021   *         (*) value not defined in all devices
01022   * @param  GPIONumber This parameter can be one of the following values:
01023   *         @arg @ref LL_PWR_GPIO_BIT_0
01024   *         @arg @ref LL_PWR_GPIO_BIT_1
01025   *         @arg @ref LL_PWR_GPIO_BIT_2
01026   *         @arg @ref LL_PWR_GPIO_BIT_3
01027   *         @arg @ref LL_PWR_GPIO_BIT_4
01028   *         @arg @ref LL_PWR_GPIO_BIT_5
01029   *         @arg @ref LL_PWR_GPIO_BIT_6
01030   *         @arg @ref LL_PWR_GPIO_BIT_7
01031   *         @arg @ref LL_PWR_GPIO_BIT_8
01032   *         @arg @ref LL_PWR_GPIO_BIT_9
01033   *         @arg @ref LL_PWR_GPIO_BIT_10
01034   *         @arg @ref LL_PWR_GPIO_BIT_11
01035   *         @arg @ref LL_PWR_GPIO_BIT_12
01036   *         @arg @ref LL_PWR_GPIO_BIT_13
01037   *         @arg @ref LL_PWR_GPIO_BIT_14
01038   *         @arg @ref LL_PWR_GPIO_BIT_15
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01042 {
01043   SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01044 }
01045
01046 /**
01047   * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
01048   * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
01049   *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
01050   *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
01051   *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
01052   *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
01053   *         PUCRF        PU0-15        LL_PWR_DisableGPIOPullUp\n
01054   *         PUCRG        PU0-15        LL_PWR_DisableGPIOPullUp\n
01055   * @param  GPIO This parameter can be one of the following values:
01056   *         @arg @ref LL_PWR_GPIO_A
01057   *         @arg @ref LL_PWR_GPIO_B
01058   *         @arg @ref LL_PWR_GPIO_C
01059   *         @arg @ref LL_PWR_GPIO_D
01060   *         @arg @ref LL_PWR_GPIO_E
01061   *         @arg @ref LL_PWR_GPIO_F
01062   *         @arg @ref LL_PWR_GPIO_G
01063   *
01064   *         (*) value not defined in all devices
01065   * @param  GPIONumber This parameter can be one of the following values:
01066   *         @arg @ref LL_PWR_GPIO_BIT_0
01067   *         @arg @ref LL_PWR_GPIO_BIT_1
01068   *         @arg @ref LL_PWR_GPIO_BIT_2
01069   *         @arg @ref LL_PWR_GPIO_BIT_3
01070   *         @arg @ref LL_PWR_GPIO_BIT_4
01071   *         @arg @ref LL_PWR_GPIO_BIT_5
01072   *         @arg @ref LL_PWR_GPIO_BIT_6
01073   *         @arg @ref LL_PWR_GPIO_BIT_7
01074   *         @arg @ref LL_PWR_GPIO_BIT_8
01075   *         @arg @ref LL_PWR_GPIO_BIT_9
01076   *         @arg @ref LL_PWR_GPIO_BIT_10
01077   *         @arg @ref LL_PWR_GPIO_BIT_11
01078   *         @arg @ref LL_PWR_GPIO_BIT_12
01079   *         @arg @ref LL_PWR_GPIO_BIT_13
01080   *         @arg @ref LL_PWR_GPIO_BIT_14
01081   *         @arg @ref LL_PWR_GPIO_BIT_15
01082   * @retval None
01083   */
01084 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01085 {
01086   CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01087 }
01088
01089 /**
01090   * @brief  Check if GPIO pull-up state is enabled
01091   * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01092   *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01093   *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01094   *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01095   *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01096   *         PUCRF        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01097   *         PUCRG        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01098   * @param  GPIO This parameter can be one of the following values:
01099   *         @arg @ref LL_PWR_GPIO_A
01100   *         @arg @ref LL_PWR_GPIO_B
01101   *         @arg @ref LL_PWR_GPIO_C
01102   *         @arg @ref LL_PWR_GPIO_D
01103   *         @arg @ref LL_PWR_GPIO_E
01104   *         @arg @ref LL_PWR_GPIO_F
01105   *         @arg @ref LL_PWR_GPIO_G
01106   *
01107   *         (*) value not defined in all devices
01108   * @param  GPIONumber This parameter can be one of the following values:
01109   *         @arg @ref LL_PWR_GPIO_BIT_0
01110   *         @arg @ref LL_PWR_GPIO_BIT_1
01111   *         @arg @ref LL_PWR_GPIO_BIT_2
01112   *         @arg @ref LL_PWR_GPIO_BIT_3
01113   *         @arg @ref LL_PWR_GPIO_BIT_4
01114   *         @arg @ref LL_PWR_GPIO_BIT_5
01115   *         @arg @ref LL_PWR_GPIO_BIT_6
01116   *         @arg @ref LL_PWR_GPIO_BIT_7
01117   *         @arg @ref LL_PWR_GPIO_BIT_8
01118   *         @arg @ref LL_PWR_GPIO_BIT_9
01119   *         @arg @ref LL_PWR_GPIO_BIT_10
01120   *         @arg @ref LL_PWR_GPIO_BIT_11
01121   *         @arg @ref LL_PWR_GPIO_BIT_12
01122   *         @arg @ref LL_PWR_GPIO_BIT_13
01123   *         @arg @ref LL_PWR_GPIO_BIT_14
01124   *         @arg @ref LL_PWR_GPIO_BIT_15
01125   * @retval State of bit (1 or 0).
01126   */
01127 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01128 {
01129   return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01130 }
01131
01132 /**
01133   * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
01134   * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
01135   *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
01136   *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
01137   *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
01138   *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
01139   *         PDCRF        PD0-15        LL_PWR_EnableGPIOPullDown\n
01140   *         PDCRG        PD0-15        LL_PWR_EnableGPIOPullDown\n
01141   * @param  GPIO This parameter can be one of the following values:
01142   *         @arg @ref LL_PWR_GPIO_A
01143   *         @arg @ref LL_PWR_GPIO_B
01144   *         @arg @ref LL_PWR_GPIO_C
01145   *         @arg @ref LL_PWR_GPIO_D
01146   *         @arg @ref LL_PWR_GPIO_E
01147   *         @arg @ref LL_PWR_GPIO_F
01148   *         @arg @ref LL_PWR_GPIO_G
01149   *
01150   *         (*) value not defined in all devices
01151   * @param  GPIONumber This parameter can be one of the following values:
01152   *         @arg @ref LL_PWR_GPIO_BIT_0
01153   *         @arg @ref LL_PWR_GPIO_BIT_1
01154   *         @arg @ref LL_PWR_GPIO_BIT_2
01155   *         @arg @ref LL_PWR_GPIO_BIT_3
01156   *         @arg @ref LL_PWR_GPIO_BIT_4
01157   *         @arg @ref LL_PWR_GPIO_BIT_5
01158   *         @arg @ref LL_PWR_GPIO_BIT_6
01159   *         @arg @ref LL_PWR_GPIO_BIT_7
01160   *         @arg @ref LL_PWR_GPIO_BIT_8
01161   *         @arg @ref LL_PWR_GPIO_BIT_9
01162   *         @arg @ref LL_PWR_GPIO_BIT_10
01163   *         @arg @ref LL_PWR_GPIO_BIT_11
01164   *         @arg @ref LL_PWR_GPIO_BIT_12
01165   *         @arg @ref LL_PWR_GPIO_BIT_13
01166   *         @arg @ref LL_PWR_GPIO_BIT_14
01167   *         @arg @ref LL_PWR_GPIO_BIT_15
01168   * @retval None
01169   */
01170 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01171 {
01172   SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
01173 }
01174
01175 /**
01176   * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
01177   * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
01178   *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
01179   *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
01180   *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
01181   *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
01182   *         PDCRF        PD0-15        LL_PWR_DisableGPIOPullDown\n
01183   *         PDCRG        PD0-15        LL_PWR_DisableGPIOPullDown\n
01184   * @param  GPIO This parameter can be one of the following values:
01185   *         @arg @ref LL_PWR_GPIO_A
01186   *         @arg @ref LL_PWR_GPIO_B
01187   *         @arg @ref LL_PWR_GPIO_C
01188   *         @arg @ref LL_PWR_GPIO_D
01189   *         @arg @ref LL_PWR_GPIO_E
01190   *         @arg @ref LL_PWR_GPIO_F
01191   *         @arg @ref LL_PWR_GPIO_G
01192   *
01193   *         (*) value not defined in all devices
01194   * @param  GPIONumber This parameter can be one of the following values:
01195   *         @arg @ref LL_PWR_GPIO_BIT_0
01196   *         @arg @ref LL_PWR_GPIO_BIT_1
01197   *         @arg @ref LL_PWR_GPIO_BIT_2
01198   *         @arg @ref LL_PWR_GPIO_BIT_3
01199   *         @arg @ref LL_PWR_GPIO_BIT_4
01200   *         @arg @ref LL_PWR_GPIO_BIT_5
01201   *         @arg @ref LL_PWR_GPIO_BIT_6
01202   *         @arg @ref LL_PWR_GPIO_BIT_7
01203   *         @arg @ref LL_PWR_GPIO_BIT_8
01204   *         @arg @ref LL_PWR_GPIO_BIT_9
01205   *         @arg @ref LL_PWR_GPIO_BIT_10
01206   *         @arg @ref LL_PWR_GPIO_BIT_11
01207   *         @arg @ref LL_PWR_GPIO_BIT_12
01208   *         @arg @ref LL_PWR_GPIO_BIT_13
01209   *         @arg @ref LL_PWR_GPIO_BIT_14
01210   *         @arg @ref LL_PWR_GPIO_BIT_15
01211   * @retval None
01212   */
01213 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01214 {
01215   CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
01216 }
01217
01218 /**
01219   * @brief  Check if GPIO pull-down state is enabled
01220   * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01221   *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01222   *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01223   *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01224   *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01225   *         PDCRF        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01226   *         PDCRG        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01227   * @param  GPIO This parameter can be one of the following values:
01228   *         @arg @ref LL_PWR_GPIO_A
01229   *         @arg @ref LL_PWR_GPIO_B
01230   *         @arg @ref LL_PWR_GPIO_C
01231   *         @arg @ref LL_PWR_GPIO_D
01232   *         @arg @ref LL_PWR_GPIO_E
01233   *         @arg @ref LL_PWR_GPIO_F
01234   *         @arg @ref LL_PWR_GPIO_G
01235   *
01236   *         (*) value not defined in all devices
01237   * @param  GPIONumber This parameter can be one of the following values:
01238   *         @arg @ref LL_PWR_GPIO_BIT_0
01239   *         @arg @ref LL_PWR_GPIO_BIT_1
01240   *         @arg @ref LL_PWR_GPIO_BIT_2
01241   *         @arg @ref LL_PWR_GPIO_BIT_3
01242   *         @arg @ref LL_PWR_GPIO_BIT_4
01243   *         @arg @ref LL_PWR_GPIO_BIT_5
01244   *         @arg @ref LL_PWR_GPIO_BIT_6
01245   *         @arg @ref LL_PWR_GPIO_BIT_7
01246   *         @arg @ref LL_PWR_GPIO_BIT_8
01247   *         @arg @ref LL_PWR_GPIO_BIT_9
01248   *         @arg @ref LL_PWR_GPIO_BIT_10
01249   *         @arg @ref LL_PWR_GPIO_BIT_11
01250   *         @arg @ref LL_PWR_GPIO_BIT_12
01251   *         @arg @ref LL_PWR_GPIO_BIT_13
01252   *         @arg @ref LL_PWR_GPIO_BIT_14
01253   *         @arg @ref LL_PWR_GPIO_BIT_15
01254   * @retval State of bit (1 or 0).
01255   */
01256 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01257 {
01258   return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01259 }
01260
01261 /**
01262   * @}
01263   */
01264
01265 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
01266   * @{
01267   */
01268
01269 /**
01270   * @brief  Get Internal Wake-up line Flag
01271   * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
01272   * @retval State of bit (1 or 0).
01273   */
01274 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
01275 {
01276   uint32_t temp;
01277   temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
01278
01279   return ((temp == (PWR_SR1_WUFI))?1U:0U);
01280
01281 }
01282
01283 /**
01284   * @brief  Get Stand-By Flag
01285   * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
01286   * @retval State of bit (1 or 0).
01287   */
01288 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
01289 {
01290   uint32_t temp;
01291   temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
01292
01293   return ((temp == (PWR_SR1_SBF))?1U:0U);
01294
01295 }
01296
01297 /**
01298   * @brief  Get Wake-up Flag 5
01299   * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
01300   * @retval State of bit (1 or 0).
01301   */
01302 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
01303 {
01304   uint32_t temp;
01305   temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
01306
01307   return ((temp == (PWR_SR1_WUF5))?1U:0U);
01308 }
01309
01310 /**
01311   * @brief  Get Wake-up Flag 4
01312   * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
01313   * @retval State of bit (1 or 0).
01314   */
01315 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
01316 {
01317   uint32_t temp;
01318   temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
01319
01320   return ((temp == (PWR_SR1_WUF4))?1U:0U);
01321 }
01322
01323 /**
01324   * @brief  Get Wake-up Flag 3
01325   * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
01326   * @retval State of bit (1 or 0).
01327   */
01328 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
01329 {
01330   uint32_t temp;
01331   temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
01332
01333   return ((temp == (PWR_SR1_WUF3))?1U:0U);
01334 }
01335
01336 /**
01337   * @brief  Get Wake-up Flag 2
01338   * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
01339   * @retval State of bit (1 or 0).
01340   */
01341 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
01342 {
01343   uint32_t temp;
01344   temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
01345
01346   return ((temp == (PWR_SR1_WUF2))?1U:0U);
01347 }
01348
01349 /**
01350   * @brief  Get Wake-up Flag 1
01351   * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
01352   * @retval State of bit (1 or 0).
01353   */
01354 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
01355 {
01356   uint32_t temp;
01357   temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
01358
01359   return ((temp == (PWR_SR1_WUF1))?1U:0U);
01360 }
01361
01362 /**
01363   * @brief  Clear Stand-By Flag
01364   * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
01365   * @retval None
01366   */
01367 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
01368 {
01369   WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
01370 }
01371
01372 /**
01373   * @brief  Clear Wake-up Flags
01374   * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
01375   * @retval None
01376   */
01377 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
01378 {
01379   WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
01380 }
01381
01382 /**
01383   * @brief  Clear Wake-up Flag 5
01384   * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
01385   * @retval None
01386   */
01387 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
01388 {
01389   WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
01390 }
01391
01392 /**
01393   * @brief  Clear Wake-up Flag 4
01394   * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
01395   * @retval None
01396   */
01397 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
01398 {
01399   WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
01400 }
01401
01402 /**
01403   * @brief  Clear Wake-up Flag 3
01404   * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
01408 {
01409   WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
01410 }
01411
01412 /**
01413   * @brief  Clear Wake-up Flag 2
01414   * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
01415   * @retval None
01416   */
01417 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
01418 {
01419   WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
01420 }
01421
01422 /**
01423   * @brief  Clear Wake-up Flag 1
01424   * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
01425   * @retval None
01426   */
01427 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
01428 {
01429   WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
01430 }
01431
01432 /**
01433   * @brief  Indicate whether VDDA voltage is below or above PVM4 threshold
01434   * @rmtoll SR2          PVMO4         LL_PWR_IsActiveFlag_PVMO4
01435   * @retval State of bit (1 or 0).
01436   */
01437 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
01438 {
01439   uint32_t temp;
01440   temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
01441
01442   return ((temp == (PWR_SR2_PVMO4))?1U:0U);
01443
01444 }
01445
01446 /**
01447   * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold
01448   * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3
01449   * @retval State of bit (1 or 0).
01450   */
01451 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
01452 {
01453   uint32_t temp;
01454   temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
01455
01456   return ((temp == (PWR_SR2_PVMO3))?1U:0U);
01457
01458 }
01459
01460 #if defined(PWR_SR2_PVMO2)
01461 /**
01462   * @brief  Indicate whether VDDIO2 voltage is below or above PVM2 threshold
01463   * @rmtoll SR2          PVMO2         LL_PWR_IsActiveFlag_PVMO2
01464   * @retval State of bit (1 or 0).
01465   */
01466 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
01467 {
01468   uint32_t temp;
01469   temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
01470
01471   return ((temp == (PWR_SR2_PVMO2))?1U:0U);
01472
01473 }
01474 #endif /* PWR_SR2_PVMO2 */
01475
01476 #if defined(PWR_SR2_PVMO1)
01477 /**
01478   * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold
01479   * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1
01480   * @retval State of bit (1 or 0).
01481   */
01482 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
01483 {
01484   uint32_t temp;
01485   temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
01486
01487   return ((temp == (PWR_SR2_PVMO1))?1U:0U);
01488
01489 }
01490 #endif /* PWR_SR2_PVMO1 */
01491
01492 /**
01493   * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold
01494   * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
01495   * @retval State of bit (1 or 0).
01496   */
01497 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
01498 {
01499  uint32_t temp;
01500  temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
01501
01502  return ((temp == (PWR_SR2_PVDO))?1U:0U);
01503
01504 }
01505
01506 /**
01507   * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
01508   * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
01509   * @retval State of bit (1 or 0).
01510   */
01511 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
01512 {
01513   uint32_t temp;
01514   temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
01515
01516   return ((temp == (PWR_SR2_VOSF))?1U:0U);
01517
01518 }
01519
01520 /**
01521   * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode
01522   * @note: Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
01523   * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
01524   * @retval State of bit (1 or 0).
01525   */
01526 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
01527 {
01528   uint32_t temp;
01529   temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
01530
01531   return ((temp == (PWR_SR2_REGLPF))?1U:0U);
01532
01533 }
01534
01535 /**
01536   * @brief  Indicate whether or not the low-power regulator is ready
01537   * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
01541 {
01542   uint32_t temp;
01543   temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
01544
01545   return ((temp == (PWR_SR2_REGLPS))?1U:0U);
01546
01547 }
01548
01549 /**
01550   * @}
01551   */
01552
01553 #if defined(USE_FULL_LL_DRIVER)
01554 /** @defgroup PWR_LL_EF_Init De-initialization function
01555   * @{
01556   */
01557 ErrorStatus LL_PWR_DeInit(void);
01558 /**
01559   * @}
01560   */
01561 #endif /* USE_FULL_LL_DRIVER */
01562
01563 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
01564   * @{
01565   */
01566 /* Old functions name kept for legacy purpose, to be replaced by the          */
01567 /* current functions name.                                                    */
01568 #define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS
01569 #define LL_PWR_EnableUSBDeadBattery            LL_PWR_EnableUCPDDeadBattery
01570 #define LL_PWR_DisableUSBDeadBattery           LL_PWR_DisableUCPDDeadBattery
01571 #define LL_PWR_IsEnabledUSBDeadBattery         LL_PWR_IsEnabledUCPDDeadBattery
01572 #define LL_PWR_EnableDeadBatteryPD             LL_PWR_EnableUCPDDeadBattery
01573 #define LL_PWR_DisableDeadBatteryPD            LL_PWR_DisableUCPDDeadBattery
01574 #define LL_PWR_EnableUSBStandByModePD          LL_PWR_EnableUCPDStandbyMode
01575 #define LL_PWR_EnableStandByModePD             LL_PWR_EnableUCPDStandbyMode
01576 #define LL_PWR_DisableUSBStandByModePD         LL_PWR_DisableUCPDStandbyMode
01577 #define LL_PWR_DisableStandByModePD            LL_PWR_DisableUCPDStandbyMode
01578 #define LL_PWR_IsEnabledUSBStandByModePD       LL_PWR_IsEnabledUCPDStandbyMode
01579 /**
01580   * @}
01581   */
01582
01583 /**
01584   * @}
01585   */
01586
01587 /**
01588   * @}
01589   */
01590
01591 #endif /* defined(PWR) */
01592
01593 /**
01594   * @}
01595   */
01596
01597 #ifdef __cplusplus
01598 }
01599 #endif
01600
01601 #endif /* STM32G4xx_LL_PWR_H */
01602
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rcc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_rcc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017 #if defined(USE_FULL_LL_DRIVER)
00018
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32g4xx_ll_rcc.h"
00021 #ifdef  USE_FULL_ASSERT
00022   #include "stm32_assert.h"
00023 #else
00024   #define assert_param(expr) ((void)0U)
00025 #endif
00026 /** @addtogroup STM32G4xx_LL_Driver
00027   * @{
00028   */
00029
00030 /** @addtogroup RCC_LL
00031   * @{
00032   */
00033
00034 /* Private types -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 /* Private constants ---------------------------------------------------------*/
00037 /* Private macros ------------------------------------------------------------*/
00038 /** @addtogroup RCC_LL_Private_Macros
00039   * @{
00040   */
00041 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00042                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
00043                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
00044 #if defined(RCC_CCIPR_UART5SEL)
00045 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
00046                                              || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
00047 #elif defined(RCC_CCIPR_UART4SEL)
00048 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
00049 #endif /* RCC_CCIPR_UART5SEL*/
00050
00051 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
00052
00053 #if defined(RCC_CCIPR2_I2C4SEL)
00054 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00055                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
00056                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
00057                                             || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
00058
00059 #else
00060 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00061                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
00062                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00063 #endif /* RCC_CCIPR2_I2C4SEL */
00064 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
00065
00066 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
00067
00068 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
00069
00070 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
00071
00072 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00073
00074 #if defined(ADC345_COMMON)
00075 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
00076                                             || ((__VALUE__) == LL_RCC_ADC345_CLKSOURCE))
00077 #else
00078 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
00079 #endif /* ADC345_COMMON */
00080
00081 #if defined(QUADSPI)
00082 #define IS_LL_RCC_QUADSPI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_QUADSPI_CLKSOURCE))
00083 #endif /* QUADSPI */
00084
00085 #if defined(FDCAN1)
00086 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
00087 #endif /* FDCAN1 */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Private function prototypes -----------------------------------------------*/
00094 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00095   * @{
00096   */
00097 static uint32_t RCC_GetSystemClockFreq(void);
00098 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00099 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00100 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00101 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00102 static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
00103 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
00104 /**
00105   * @}
00106   */
00107
00108
00109 /* Exported functions --------------------------------------------------------*/
00110 /** @addtogroup RCC_LL_Exported_Functions
00111   * @{
00112   */
00113
00114 /** @addtogroup RCC_LL_EF_Init
00115   * @{
00116   */
00117
00118 /**
00119   * @brief  Reset the RCC clock configuration to the default reset state.
00120   * @note   The default reset state of the clock configuration is given below:
00121   *         - HSI  ON and used as system clock source
00122   *         - HSE and PLL OFF
00123   *         - AHB, APB1 and APB2 prescaler set to 1.
00124   *         - CSS, MCO OFF
00125   *         - All interrupts disabled
00126   * @note   This function doesn't modify the configuration of the
00127   *         - Peripheral clocks
00128   *         - LSI, LSE and RTC clocks
00129   * @retval An ErrorStatus enumeration value:
00130   *          - SUCCESS: RCC registers are de-initialized
00131   *          - ERROR: not applicable
00132   */
00133 ErrorStatus LL_RCC_DeInit(void)
00134 {
00135   uint32_t vl_mask;
00136
00137   /* Set HSION bit and wait for HSI READY bit */
00138   LL_RCC_HSI_Enable();
00139   while (LL_RCC_HSI_IsReady() == 0U)
00140   {}
00141
00142   /* Set HSITRIM bits to reset value*/
00143   LL_RCC_HSI_SetCalibTrimming(0x40U);
00144
00145   /* Reset whole CFGR register but keep HSI as system clock source */
00146   LL_RCC_WriteReg(CFGR, LL_RCC_SYS_CLKSOURCE_HSI);
00147   while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {};
00148
00149   /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
00150   LL_RCC_WriteReg(CR, RCC_CR_HSION);
00151   LL_RCC_WriteReg(CR, RCC_CR_HSION);
00152
00153   /* Wait for PLL READY bit to be reset */
00154   while (LL_RCC_PLL_IsReady() != 0U)
00155   {}
00156
00157   /* Reset PLLCFGR register */
00158   LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
00159
00160   /* Disable all interrupts */
00161   LL_RCC_WriteReg(CIER, 0x00000000U);
00162
00163   /* Clear all interrupt flags */
00164   vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
00165             RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC;
00166
00167   LL_RCC_WriteReg(CICR, vl_mask);
00168
00169   /* Clear reset flags */
00170   LL_RCC_ClearResetFlags();
00171
00172   return SUCCESS;
00173 }
00174
00175 /**
00176   * @}
00177   */
00178
00179 /** @addtogroup RCC_LL_EF_Get_Freq
00180   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00181   *         and different peripheral clocks available on the device.
00182   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
00183   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00184   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
00185   *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
00186   * @note   (**) HSI_VALUE is a constant defined in this file (default value
00187   *              16 MHz) but the real value may vary depending on the variations
00188   *              in voltage and temperature.
00189   * @note   (***) HSE_VALUE is a constant defined in this file (default value
00190   *               8 MHz), user has to ensure that HSE_VALUE is same as the real
00191   *               frequency of the crystal used. Otherwise, this function may
00192   *               have wrong result.
00193   * @note   The result of this function could be incorrect when using fractional
00194   *         value for HSE crystal.
00195   * @note   This function can be used by the user application to compute the
00196   *         baud-rate for the communication peripherals or configure other parameters.
00197   * @{
00198   */
00199
00200 /**
00201   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00202   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00203   *         must be called to update structure fields. Otherwise, any
00204   *         configuration based on this function will be incorrect.
00205   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00206   * @retval None
00207   */
00208 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00209 {
00210   /* Get SYSCLK frequency */
00211   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00212
00213   /* HCLK clock frequency */
00214   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00215
00216   /* PCLK1 clock frequency */
00217   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00218
00219   /* PCLK2 clock frequency */
00220   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
00221 }
00222
00223 /**
00224   * @brief  Return USARTx clock frequency
00225   * @param  USARTxSource This parameter can be one of the following values:
00226   *         @arg @ref LL_RCC_USART1_CLKSOURCE
00227   *         @arg @ref LL_RCC_USART2_CLKSOURCE
00228   *         @arg @ref LL_RCC_USART3_CLKSOURCE
00229   *
00230   * @retval USART clock frequency (in Hz)
00231   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00232   */
00233 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00234 {
00235   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00236
00237   /* Check parameter */
00238   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00239
00240   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
00241   {
00242     /* USART1CLK clock frequency */
00243     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00244     {
00245       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00246         usart_frequency = RCC_GetSystemClockFreq();
00247         break;
00248
00249       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00250         if (LL_RCC_HSI_IsReady() != 0U)
00251         {
00252           usart_frequency = HSI_VALUE;
00253         }
00254         break;
00255
00256       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00257         if (LL_RCC_LSE_IsReady() != 0U)
00258         {
00259           usart_frequency = LSE_VALUE;
00260         }
00261         break;
00262
00263       case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
00264       default:
00265         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00266         break;
00267     }
00268   }
00269   else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
00270   {
00271     /* USART2CLK clock frequency */
00272     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00273     {
00274       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
00275         usart_frequency = RCC_GetSystemClockFreq();
00276         break;
00277
00278       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
00279         if (LL_RCC_HSI_IsReady() != 0U)
00280         {
00281           usart_frequency = HSI_VALUE;
00282         }
00283         break;
00284
00285       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
00286         if (LL_RCC_LSE_IsReady() != 0U)
00287         {
00288           usart_frequency = LSE_VALUE;
00289         }
00290         break;
00291
00292       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
00293       default:
00294         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00295         break;
00296     }
00297   }
00298   else
00299   {
00300     if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
00301     {
00302       /* USART3CLK clock frequency */
00303       switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00304       {
00305         case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
00306           usart_frequency = RCC_GetSystemClockFreq();
00307           break;
00308
00309         case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
00310           if (LL_RCC_HSI_IsReady() != 0U)
00311           {
00312             usart_frequency = HSI_VALUE;
00313           }
00314           break;
00315
00316         case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
00317           if (LL_RCC_LSE_IsReady() != 0U)
00318           {
00319             usart_frequency = LSE_VALUE;
00320           }
00321           break;
00322
00323         case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
00324         default:
00325           usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00326           break;
00327       }
00328     }
00329   }
00330   return usart_frequency;
00331 }
00332
00333 #if defined(RCC_CCIPR_UART4SEL)
00334 /**
00335   * @brief  Return UARTx clock frequency
00336   * @param  UARTxSource This parameter can be one of the following values:
00337   *         @arg @ref LL_RCC_UART4_CLKSOURCE (*)
00338   *         @arg @ref LL_RCC_UART5_CLKSOURCE (*)
00339   *
00340   *         (*) value not defined in all devices.
00341   * @retval UART clock frequency (in Hz)
00342   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00343   */
00344 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
00345 {
00346   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00347
00348   /* Check parameter */
00349   assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
00350
00351   if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
00352   {
00353     /* UART4CLK clock frequency */
00354     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00355     {
00356       case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
00357         uart_frequency = RCC_GetSystemClockFreq();
00358         break;
00359
00360       case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
00361         if (LL_RCC_HSI_IsReady() != 0U)
00362         {
00363           uart_frequency = HSI_VALUE;
00364         }
00365         break;
00366
00367       case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
00368         if (LL_RCC_LSE_IsReady() != 0U)
00369         {
00370           uart_frequency = LSE_VALUE;
00371         }
00372         break;
00373
00374       case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
00375       default:
00376         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00377         break;
00378     }
00379   }
00380
00381 #if defined(RCC_CCIPR_UART5SEL)
00382   if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
00383   {
00384     /* UART5CLK clock frequency */
00385     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00386     {
00387       case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
00388         uart_frequency = RCC_GetSystemClockFreq();
00389         break;
00390
00391       case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
00392         if (LL_RCC_HSI_IsReady() != 0U)
00393         {
00394           uart_frequency = HSI_VALUE;
00395         }
00396         break;
00397
00398       case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
00399         if (LL_RCC_LSE_IsReady() != 0U)
00400         {
00401           uart_frequency = LSE_VALUE;
00402         }
00403         break;
00404
00405       case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
00406       default:
00407         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00408         break;
00409     }
00410   }
00411 #endif /* RCC_CCIPR_UART5SEL */
00412
00413   return uart_frequency;
00414 }
00415 #endif /* RCC_CCIPR_UART4SEL */
00416
00417 /**
00418   * @brief  Return I2Cx clock frequency
00419   * @param  I2CxSource This parameter can be one of the following values:
00420   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
00421   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
00422   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
00423   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
00424   *
00425   *         (*) value not defined in all devices.
00426   * @retval I2C clock frequency (in Hz)
00427   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
00428   */
00429 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00430 {
00431   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00432
00433   /* Check parameter */
00434   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00435
00436   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
00437   {
00438     /* I2C1 CLK clock frequency */
00439     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00440     {
00441       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00442         i2c_frequency = RCC_GetSystemClockFreq();
00443         break;
00444
00445       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00446         if (LL_RCC_HSI_IsReady() != 0U)
00447         {
00448           i2c_frequency = HSI_VALUE;
00449         }
00450         break;
00451
00452       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
00453       default:
00454         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00455         break;
00456     }
00457   }
00458   else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
00459   {
00460     /* I2C2 CLK clock frequency */
00461     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00462     {
00463       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
00464         i2c_frequency = RCC_GetSystemClockFreq();
00465         break;
00466
00467       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
00468         if (LL_RCC_HSI_IsReady() != 0U)
00469         {
00470           i2c_frequency = HSI_VALUE;
00471         }
00472         break;
00473
00474       case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
00475       default:
00476         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00477         break;
00478     }
00479   }
00480   else
00481   {
00482     if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
00483     {
00484       /* I2C3 CLK clock frequency */
00485       switch (LL_RCC_GetI2CClockSource(I2CxSource))
00486       {
00487         case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
00488           i2c_frequency = RCC_GetSystemClockFreq();
00489           break;
00490
00491         case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
00492           if (LL_RCC_HSI_IsReady() != 0U)
00493           {
00494             i2c_frequency = HSI_VALUE;
00495           }
00496           break;
00497
00498         case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
00499         default:
00500           i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00501           break;
00502       }
00503     }
00504 #if defined(RCC_CCIPR2_I2C4SEL)
00505     else
00506     {
00507       if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
00508       {
00509         /* I2C4 CLK clock frequency */
00510         switch (LL_RCC_GetI2CClockSource(I2CxSource))
00511         {
00512           case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
00513             i2c_frequency = RCC_GetSystemClockFreq();
00514             break;
00515
00516           case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */
00517             if (LL_RCC_HSI_IsReady() != 0U)
00518             {
00519               i2c_frequency = HSI_VALUE;
00520             }
00521             break;
00522
00523           case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */
00524           default:
00525             i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00526             break;
00527         }
00528       }
00529     }
00530 #endif /*RCC_CCIPR2_I2C4SEL*/
00531   }
00532
00533   return i2c_frequency;
00534 }
00535
00536
00537 /**
00538   * @brief  Return LPUARTx clock frequency
00539   * @param  LPUARTxSource This parameter can be one of the following values:
00540   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
00541   * @retval LPUART clock frequency (in Hz)
00542   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00543   */
00544 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
00545 {
00546   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00547
00548   /* Check parameter */
00549   assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
00550
00551   /* LPUART1CLK clock frequency */
00552   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00553   {
00554     case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
00555       lpuart_frequency = RCC_GetSystemClockFreq();
00556       break;
00557
00558     case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
00559       if (LL_RCC_HSI_IsReady() != 0U)
00560       {
00561         lpuart_frequency = HSI_VALUE;
00562       }
00563       break;
00564
00565     case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
00566       if (LL_RCC_LSE_IsReady() != 0U)
00567       {
00568         lpuart_frequency = LSE_VALUE;
00569       }
00570       break;
00571
00572     case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
00573     default:
00574       lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00575       break;
00576   }
00577
00578   return lpuart_frequency;
00579 }
00580
00581 /**
00582   * @brief  Return LPTIMx clock frequency
00583   * @param  LPTIMxSource This parameter can be one of the following values:
00584   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
00585   * @retval LPTIM clock frequency (in Hz)
00586   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
00587   */
00588 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
00589 {
00590   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00591
00592   /* Check parameter */
00593   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
00594
00595   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
00596   {
00597     /* LPTIM1CLK clock frequency */
00598     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00599     {
00600       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
00601         if (LL_RCC_LSI_IsReady() != 0U)
00602         {
00603           lptim_frequency = LSI_VALUE;
00604         }
00605         break;
00606
00607       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
00608         if (LL_RCC_HSI_IsReady() != 0U)
00609         {
00610           lptim_frequency = HSI_VALUE;
00611         }
00612         break;
00613
00614       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
00615         if (LL_RCC_LSE_IsReady() != 0U)
00616         {
00617           lptim_frequency = LSE_VALUE;
00618         }
00619         break;
00620
00621       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
00622       default:
00623         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00624         break;
00625     }
00626   }
00627
00628   return lptim_frequency;
00629 }
00630
00631 /**
00632   * @brief  Return SAIx clock frequency
00633   * @param  SAIxSource This parameter can be one of the following values:
00634   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
00635   *
00636   * @retval SAI clock frequency (in Hz)
00637   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
00638   */
00639 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
00640 {
00641   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00642
00643   /* Check parameter */
00644   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
00645
00646   if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
00647   {
00648     /* SAI1CLK clock frequency */
00649     switch (LL_RCC_GetSAIClockSource(SAIxSource))
00650     {
00651       case LL_RCC_SAI1_CLKSOURCE_SYSCLK:      /* System clock used as SAI1 clock source */
00652         sai_frequency = RCC_GetSystemClockFreq();
00653         break;
00654
00655       case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
00656         if (LL_RCC_PLL_IsReady() != 0U)
00657         {
00658           if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00659           {
00660             sai_frequency = RCC_PLL_GetFreqDomain_48M();
00661           }
00662         }
00663         break;
00664
00665       case LL_RCC_SAI1_CLKSOURCE_PIN:          /* SAI1 Clock is External clock */
00666         sai_frequency = EXTERNAL_CLOCK_VALUE;
00667         break;
00668
00669       case LL_RCC_SAI1_CLKSOURCE_HSI:        /* HSI clock used as SAI1 clock source */
00670       default:
00671         if (LL_RCC_HSI_IsReady() != 0U)
00672         {
00673           sai_frequency = HSI_VALUE;
00674         }
00675         break;
00676
00677     }
00678   }
00679
00680   return sai_frequency;
00681 }
00682
00683 /**
00684   * @brief  Return I2Sx clock frequency
00685   * @param  I2SxSource This parameter can be one of the following values:
00686   *         @arg @ref LL_RCC_I2S_CLKSOURCE
00687   * @retval I2S clock frequency (in Hz)
00688   *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00689   */
00690 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
00691 {
00692   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00693
00694   /* Check parameter */
00695   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
00696
00697   if (I2SxSource == LL_RCC_I2S_CLKSOURCE)
00698   {
00699     /* I2S CLK clock frequency */
00700     switch (LL_RCC_GetI2SClockSource(I2SxSource))
00701     {
00702       case LL_RCC_I2S_CLKSOURCE_SYSCLK:  /* I2S Clock is System Clock */
00703         i2s_frequency = RCC_GetSystemClockFreq();
00704       break;
00705
00706       case LL_RCC_I2S_CLKSOURCE_PLL:    /* I2S Clock is PLL"Q" */
00707       if (LL_RCC_PLL_IsReady() != 0U)
00708       {
00709         if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00710         {
00711           i2s_frequency = RCC_PLL_GetFreqDomain_48M();
00712         }
00713       }
00714       break;
00715
00716       case LL_RCC_I2S_CLKSOURCE_PIN:    /* I2S Clock is External clock */
00717         i2s_frequency = EXTERNAL_CLOCK_VALUE;
00718         break;
00719
00720       case LL_RCC_I2S_CLKSOURCE_HSI:    /* I2S Clock is HSI */
00721       default:
00722         if (LL_RCC_HSI_IsReady() != 0U)
00723         {
00724           i2s_frequency = HSI_VALUE;
00725         }
00726       break;
00727       }
00728   }
00729
00730   return i2s_frequency;
00731 }
00732
00733 #if defined(FDCAN1)
00734 /**
00735   * @brief  Return FDCAN kernel clock frequency
00736   * @param  FDCANxSource This parameter can be one of the following values:
00737   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
00738   * @retval FDCAN kernel clock frequency (in Hz)
00739   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00740   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00741   */
00742 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
00743 {
00744   uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00745
00746   /* Check parameter */
00747   assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
00748
00749   /* FDCAN kernel clock frequency */
00750   switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
00751   {
00752     case LL_RCC_FDCAN_CLKSOURCE_HSE:   /* HSE clock used as FDCAN kernel clock */
00753       if (LL_RCC_HSE_IsReady() != 0U)
00754       {
00755         fdcan_frequency = HSE_VALUE;
00756       }
00757       break;
00758
00759     case LL_RCC_FDCAN_CLKSOURCE_PLL:   /* PLL clock used as FDCAN kernel clock */
00760       if (LL_RCC_PLL_IsReady() != 0U)
00761       {
00762         if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00763         {
00764           fdcan_frequency = RCC_PLL_GetFreqDomain_48M();
00765         }
00766       }
00767       break;
00768
00769     case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* PCLK1 clock used as FDCAN kernel clock */
00770       fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00771       break;
00772
00773     default:
00774       fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00775       break;
00776   }
00777   return fdcan_frequency;
00778 }
00779 #endif /* FDCAN1 */
00780
00781 /**
00782   * @brief  Return RNGx clock frequency
00783   * @param  RNGxSource This parameter can be one of the following values:
00784   *         @arg @ref LL_RCC_RNG_CLKSOURCE
00785   * @retval RNG clock frequency (in Hz)
00786   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
00787   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00788   */
00789 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
00790 {
00791   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00792
00793   /* Check parameter */
00794   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
00795
00796   /* RNGCLK clock frequency */
00797   switch (LL_RCC_GetRNGClockSource(RNGxSource))
00798   {
00799     case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
00800       if (LL_RCC_PLL_IsReady() != 0U)
00801       {
00802         if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00803         {
00804           rng_frequency = RCC_PLL_GetFreqDomain_48M();
00805         }
00806       }
00807       break;
00808
00809     case LL_RCC_RNG_CLKSOURCE_HSI48:         /* HSI48 used as RNG clock source */
00810       if (LL_RCC_HSI48_IsReady() != 0U)
00811       {
00812         rng_frequency = HSI48_VALUE;
00813       }
00814       break;
00815
00816     default:
00817       rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00818       break;
00819
00820   }
00821
00822   return rng_frequency;
00823 }
00824
00825 /**
00826   * @brief  Return USBx clock frequency
00827   * @param  USBxSource This parameter can be one of the following values:
00828   *         @arg @ref LL_RCC_USB_CLKSOURCE
00829   * @retval USB clock frequency (in Hz)
00830   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
00831   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00832   */
00833 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00834 {
00835   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00836
00837   /* Check parameter */
00838   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
00839
00840   /* USBCLK clock frequency */
00841   switch (LL_RCC_GetUSBClockSource(USBxSource))
00842   {
00843     case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
00844       if (LL_RCC_PLL_IsReady() != 0U)
00845       {
00846         if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00847         {
00848           usb_frequency = RCC_PLL_GetFreqDomain_48M();
00849         }
00850       }
00851       break;
00852
00853     case LL_RCC_USB_CLKSOURCE_HSI48:         /* HSI48 used as USB clock source */
00854       if (LL_RCC_HSI48_IsReady() != 0U)
00855       {
00856         usb_frequency = HSI48_VALUE;
00857       }
00858       break;
00859
00860     default:
00861       usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00862       break;
00863   }
00864
00865   return usb_frequency;
00866 }
00867
00868 /**
00869   * @brief  Return ADCx clock frequency
00870   * @param  ADCxSource This parameter can be one of the following values:
00871   *         @arg @ref LL_RCC_ADC12_CLKSOURCE
00872   *         @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
00873   *
00874   *         (*) value not defined in all devices.
00875   * @retval ADC clock frequency (in Hz)
00876   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
00877   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00878   */
00879 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00880 {
00881   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00882
00883   /* Check parameter */
00884   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00885
00886   if (ADCxSource == LL_RCC_ADC12_CLKSOURCE)
00887   {
00888     /* ADC12CLK clock frequency */
00889     switch (LL_RCC_GetADCClockSource(ADCxSource))
00890     {
00891       case LL_RCC_ADC12_CLKSOURCE_PLL:       /* PLL clock used as ADC12 clock source */
00892         if (LL_RCC_PLL_IsReady() != 0U)
00893         {
00894           if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
00895           {
00896             adc_frequency = RCC_PLL_GetFreqDomain_ADC();
00897           }
00898         }
00899         break;
00900
00901       case LL_RCC_ADC12_CLKSOURCE_SYSCLK:    /* System clock used as ADC12 clock source */
00902         adc_frequency = RCC_GetSystemClockFreq();
00903         break;
00904
00905       case LL_RCC_ADC12_CLKSOURCE_NONE:        /* No clock used as ADC12 clock source */
00906       default:
00907         adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00908         break;
00909     }
00910   }
00911 #if defined(ADC345_COMMON)
00912   else
00913   {
00914     /* ADC345CLK clock frequency */
00915     switch (LL_RCC_GetADCClockSource(ADCxSource))
00916     {
00917       case LL_RCC_ADC345_CLKSOURCE_PLL:       /* PLL clock used as ADC345 clock source */
00918         if (LL_RCC_PLL_IsReady() != 0U)
00919         {
00920           if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
00921           {
00922             adc_frequency = RCC_PLL_GetFreqDomain_ADC();
00923           }
00924         }
00925         break;
00926
00927       case LL_RCC_ADC345_CLKSOURCE_SYSCLK:    /* System clock used as ADC345 clock source */
00928         adc_frequency = RCC_GetSystemClockFreq();
00929         break;
00930
00931       case LL_RCC_ADC345_CLKSOURCE_NONE:        /* No clock used as ADC345 clock source */
00932       default:
00933         adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00934         break;
00935     }
00936   }
00937 #endif /* ADC345_COMMON */
00938
00939   return adc_frequency;
00940 }
00941
00942 #if defined(QUADSPI)
00943 /**
00944   * @brief  Return QUADSPI clock frequency
00945   * @param  QUADSPIxSource This parameter can be one of the following values:
00946   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE
00947   * @retval QUADSPI clock frequency (in Hz)
00948   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that no clock is configured
00949   */
00950 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)
00951 {
00952   uint32_t quadspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00953
00954   /* Check parameter */
00955   assert_param(IS_LL_RCC_QUADSPI_CLKSOURCE(QUADSPIxSource));
00956
00957   /* QUADSPI clock frequency */
00958   switch (LL_RCC_GetQUADSPIClockSource(QUADSPIxSource))
00959   {
00960     case LL_RCC_QUADSPI_CLKSOURCE_SYSCLK:   /* SYSCLK used as QUADSPI source */
00961       quadspi_frequency = RCC_GetSystemClockFreq();
00962       break;
00963
00964     case LL_RCC_QUADSPI_CLKSOURCE_HSI:      /* HSI clock used as QUADSPI source */
00965       if (LL_RCC_HSI_IsReady() != 0U)
00966       {
00967         quadspi_frequency = HSI_VALUE;
00968       }
00969       break;
00970
00971     case LL_RCC_QUADSPI_CLKSOURCE_PLL:      /* PLL clock used as QUADSPI source */
00972       if (LL_RCC_PLL_IsReady() != 0U)
00973       {
00974         if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
00975         {
00976           quadspi_frequency = RCC_PLL_GetFreqDomain_48M();
00977         }
00978       }
00979       break;
00980
00981     default:
00982       /* Nothing to do: quadspi frequency already initilalized to LL_RCC_PERIPH_FREQUENCY_NO */
00983       break;
00984   }
00985
00986   return quadspi_frequency;
00987 }
00988 #endif /* QUADSPI */
00989
00990 /**
00991   * @}
00992   */
00993
00994 /**
00995   * @}
00996   */
00997
00998 /** @addtogroup RCC_LL_Private_Functions
00999   * @{
01000   */
01001
01002 /**
01003   * @brief  Return SYSTEM clock frequency
01004   * @retval SYSTEM clock frequency (in Hz)
01005   */
01006 static uint32_t RCC_GetSystemClockFreq(void)
01007 {
01008   uint32_t frequency;
01009
01010   /* Get SYSCLK source -------------------------------------------------------*/
01011   switch (LL_RCC_GetSysClkSource())
01012   {
01013     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
01014       frequency = HSI_VALUE;
01015       break;
01016
01017     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
01018       frequency = HSE_VALUE;
01019       break;
01020
01021     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
01022       frequency = RCC_PLL_GetFreqDomain_SYS();
01023       break;
01024
01025     default:
01026       frequency = HSI_VALUE;
01027       break;
01028   }
01029
01030   return frequency;
01031 }
01032
01033 /**
01034   * @brief  Return HCLK clock frequency
01035   * @param  SYSCLK_Frequency SYSCLK clock frequency
01036   * @retval HCLK clock frequency (in Hz)
01037   */
01038 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
01039 {
01040   /* HCLK clock frequency */
01041   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
01042 }
01043
01044 /**
01045   * @brief  Return PCLK1 clock frequency
01046   * @param  HCLK_Frequency HCLK clock frequency
01047   * @retval PCLK1 clock frequency (in Hz)
01048   */
01049 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01050 {
01051   /* PCLK1 clock frequency */
01052   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01053 }
01054
01055 /**
01056   * @brief  Return PCLK2 clock frequency
01057   * @param  HCLK_Frequency HCLK clock frequency
01058   * @retval PCLK2 clock frequency (in Hz)
01059   */
01060 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
01061 {
01062   /* PCLK2 clock frequency */
01063   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
01064 }
01065
01066 /**
01067   * @brief  Return PLL clock frequency used for system domain
01068   * @retval PLL clock frequency (in Hz)
01069   */
01070 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
01071 {
01072   uint32_t pllinputfreq, pllsource;
01073
01074   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01075      SYSCLK = PLL_VCO / PLLR
01076   */
01077   pllsource = LL_RCC_PLL_GetMainSource();
01078
01079   switch (pllsource)
01080   {
01081     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01082       pllinputfreq = HSI_VALUE;
01083       break;
01084
01085     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01086       pllinputfreq = HSE_VALUE;
01087       break;
01088
01089     default:
01090       pllinputfreq = HSI_VALUE;
01091       break;
01092   }
01093   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01094                                    LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
01095 }
01096
01097 /**
01098   * @brief  Return PLL clock frequency used for ADC domain
01099   * @retval PLL clock frequency (in Hz)
01100   */
01101 static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
01102 {
01103   uint32_t pllinputfreq, pllsource;
01104
01105   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01106      ADC Domain clock = PLL_VCO / PLLP
01107   */
01108   pllsource = LL_RCC_PLL_GetMainSource();
01109
01110   switch (pllsource)
01111   {
01112     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01113       pllinputfreq = HSI_VALUE;
01114       break;
01115
01116     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01117       pllinputfreq = HSE_VALUE;
01118       break;
01119
01120     default:
01121       pllinputfreq = HSI_VALUE;
01122       break;
01123   }
01124   return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01125                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01126 }
01127
01128 /**
01129   * @brief  Return PLL clock frequency used for 48 MHz domain
01130   * @retval PLL clock frequency (in Hz)
01131   */
01132 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
01133 {
01134   uint32_t pllinputfreq, pllsource;
01135
01136   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01137      48M Domain clock = PLL_VCO / PLLQ
01138   */
01139   pllsource = LL_RCC_PLL_GetMainSource();
01140
01141   switch (pllsource)
01142   {
01143     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01144       pllinputfreq = HSI_VALUE;
01145       break;
01146
01147     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01148       pllinputfreq = HSE_VALUE;
01149       break;
01150
01151     default:
01152       pllinputfreq = HSI_VALUE;
01153       break;
01154   }
01155   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01156                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01157 }
01158
01159 /**
01160   * @}
01161   */
01162
01163 /**
01164   * @}
01165   */
01166
01167 /**
01168   * @}
01169   */
01170
01171 #endif /* USE_FULL_LL_DRIVER */
01172
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rcc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_rcc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G4xx_LL_RCC_H
00020 #define STM32G4xx_LL_RCC_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g4xx.h"
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 /** @defgroup RCC_LL RCC
00034   * @{
00035   */
00036
00037 /* Private types -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00040   * @{
00041   */
00042
00043 /**
00044   * @}
00045   */
00046
00047 /* Private constants ---------------------------------------------------------*/
00048 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
00049   * @{
00050   */
00051 /* Defines used to perform offsets*/
00052 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
00053 #define RCC_OFFSET_CCIPR        0U
00054 #define RCC_OFFSET_CCIPR2       0x14U
00055
00056 /**
00057   * @}
00058   */
00059
00060 /* Private macros ------------------------------------------------------------*/
00061 #if defined(USE_FULL_LL_DRIVER)
00062 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00063   * @{
00064   */
00065 /**
00066   * @}
00067   */
00068 #endif /*USE_FULL_LL_DRIVER*/
00069
00070 /* Exported types ------------------------------------------------------------*/
00071 #if defined(USE_FULL_LL_DRIVER)
00072 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00073   * @{
00074   */
00075
00076 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  RCC Clocks Frequency Structure
00082   */
00083 typedef struct
00084 {
00085   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
00086   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
00087   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
00088   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
00089 } LL_RCC_ClocksTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098 #endif /* USE_FULL_LL_DRIVER */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00106   * @brief    Defines used to adapt values of different oscillators
00107   * @note     These values could be modified in the user environment according to
00108   *           HW set-up.
00109   * @{
00110   */
00111 #if !defined  (HSE_VALUE)
00112 #define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */
00113 #endif /* HSE_VALUE */
00114
00115 #if !defined  (HSI_VALUE)
00116 #define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
00117 #endif /* HSI_VALUE */
00118
00119 #if !defined  (LSE_VALUE)
00120 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
00121 #endif /* LSE_VALUE */
00122
00123 #if !defined  (LSI_VALUE)
00124 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
00125 #endif /* LSI_VALUE */
00126
00127 #if !defined  (HSI48_VALUE)
00128 #define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
00129 #endif /* HSI48_VALUE */
00130
00131 #if !defined  (EXTERNAL_CLOCK_VALUE)
00132 #define EXTERNAL_CLOCK_VALUE    48000U     /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
00133 #endif /* EXTERNAL_CLOCK_VALUE */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00140   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00141   * @{
00142   */
00143 #define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
00144 #define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00145 #define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00146 #define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00147 #define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00148 #define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
00149 #define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
00150 #define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00156   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00157   * @{
00158   */
00159 #define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
00160 #define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
00161 #define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00162 #define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
00163 #define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00164 #define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00165 #define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00166 #define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00167 #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
00168 #define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
00169 #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
00170 #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
00171 #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
00172 #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
00173 #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup RCC_LL_EC_IT IT Defines
00179   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00180   * @{
00181   */
00182 #define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
00183 #define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00184 #define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00185 #define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00186 #define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00187 #define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
00188 #define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00194   * @{
00195   */
00196 #define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
00197 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
00198 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
00199 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
00205   * @{
00206   */
00207 #define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */
00208 #define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL            /*!< LSE selection for low speed clock  */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00214   * @{
00215   */
00216 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00217 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00218 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00224   * @{
00225   */
00226 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00227 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00228 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00234   * @{
00235   */
00236 #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00237 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00238 #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00239 #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00240 #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00241 #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00242 #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00243 #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00244 #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00250   * @{
00251   */
00252 #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00253 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00254 #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00255 #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00256 #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00262   * @{
00263   */
00264 #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
00265 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
00266 #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
00267 #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
00268 #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00274   * @{
00275   */
00276 #define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */
00277 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00278 #define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
00279 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00280 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
00281 #define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00282 #define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00283 #define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00289   * @{
00290   */
00291 #define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1       /*!< MCO not divided */
00292 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2       /*!< MCO divided by 2 */
00293 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4       /*!< MCO divided by 4 */
00294 #define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8       /*!< MCO divided by 8 */
00295 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16      /*!< MCO divided by 16 */
00296 /**
00297   * @}
00298   */
00299
00300 #if defined(USE_FULL_LL_DRIVER)
00301 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00302   * @{
00303   */
00304 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
00305 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
00306 /**
00307   * @}
00308   */
00309 #endif /* USE_FULL_LL_DRIVER */
00310
00311 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
00312   * @{
00313   */
00314 #define LL_RCC_USART1_CLKSOURCE_PCLK2      (RCC_CCIPR_USART1SEL << 16U)                           /*!< PCLK2 clock used as USART1 clock source */
00315 #define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
00316 #define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
00317 #define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)   /*!< LSE clock used as USART1 clock source */
00318 #define LL_RCC_USART2_CLKSOURCE_PCLK1      (RCC_CCIPR_USART2SEL << 16U)                           /*!< PCLK1 clock used as USART2 clock source */
00319 #define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
00320 #define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
00321 #define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)   /*!< LSE clock used as USART2 clock source */
00322 #define LL_RCC_USART3_CLKSOURCE_PCLK1      (RCC_CCIPR_USART3SEL << 16U)                           /*!< PCLK1 clock used as USART3 clock source */
00323 #define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
00324 #define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
00325 #define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE  Peripheral UART clock source selection
00331   * @{
00332   */
00333 #if defined(RCC_CCIPR_UART4SEL)
00334 #define LL_RCC_UART4_CLKSOURCE_PCLK1       (RCC_CCIPR_UART4SEL << 16U)                           /*!< PCLK1 clock used as UART4 clock source */
00335 #define LL_RCC_UART4_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)  /*!< SYSCLK clock used as UART4 clock source */
00336 #define LL_RCC_UART4_CLKSOURCE_HSI         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)  /*!< HSI clock used as UART4 clock source */
00337 #define LL_RCC_UART4_CLKSOURCE_LSE         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)    /*!< LSE clock used as UART4 clock source */
00338 #endif /* RCC_CCIPR_UART4SEL */
00339 #if defined(RCC_CCIPR_UART5SEL)
00340 #define LL_RCC_UART5_CLKSOURCE_PCLK1       (RCC_CCIPR_UART5SEL << 16U)                           /*!< PCLK1 clock used as UART5 clock source */
00341 #define LL_RCC_UART5_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0)  /*!< SYSCLK clock used as UART5 clock source */
00342 #define LL_RCC_UART5_CLKSOURCE_HSI         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1)  /*!< HSI clock used as UART5 clock source */
00343 #define LL_RCC_UART5_CLKSOURCE_LSE         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL)    /*!< LSE clock used as UART5 clock source */
00344 #endif /* RCC_CCIPR_UART5SEL */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
00350   * @{
00351   */
00352 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U                     /*!< PCLK1 clock used as LPUART1 clock source */
00353 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0          /*!< SYSCLK clock used as LPUART1 clock source */
00354 #define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1          /*!< HSI clock used as LPUART1 clock source */
00355 #define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL            /*!< LSE clock used as LPUART1 clock source */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
00361   * @{
00362   */
00363 #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C1 clock source */
00364 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))     /*!< SYSCLK clock used as I2C1 clock source */
00365 #define LL_RCC_I2C1_CLKSOURCE_HSI          (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))     /*!< HSI clock used as I2C1 clock source */
00366 #define LL_RCC_I2C2_CLKSOURCE_PCLK1        (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C2 clock source */
00367 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))     /*!< SYSCLK clock used as I2C2 clock source */
00368 #define LL_RCC_I2C2_CLKSOURCE_HSI          (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))     /*!< HSI clock used as I2C2 clock source */
00369 #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U))                                                      /*!< PCLK1 clock used as I2C3 clock source */
00370 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))     /*!< SYSCLK clock used as I2C3 clock source */
00371 #define LL_RCC_I2C3_CLKSOURCE_HSI          (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))     /*!< HSI clock used as I2C3 clock source */
00372 #if defined(RCC_CCIPR2_I2C4SEL)
00373 #define LL_RCC_I2C4_CLKSOURCE_PCLK1        (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U))                                                    /*!< PCLK1 clock used as I2C4 clock source */
00374 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK       (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
00375 #define LL_RCC_I2C4_CLKSOURCE_HSI          (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
00376 #endif /* RCC_CCIPR2_I2C4SEL */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
00382   * @{
00383   */
00384 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      0x00000000U                                            /*!< PCLK1 clock used as LPTIM1 clock source */
00385 #define LL_RCC_LPTIM1_CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0                                  /*!< LSI clock used as LPTIM1 clock source */
00386 #define LL_RCC_LPTIM1_CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1                                  /*!< HSI clock used as LPTIM1 clock source */
00387 #define LL_RCC_LPTIM1_CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL                                    /*!< LSE clock used as LPTIM1 clock source */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection
00393   * @{
00394   */
00395 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK       0x00000000U                                           /*!< System clock used as SAI1 clock source */
00396 #define LL_RCC_SAI1_CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_0                                   /*!< PLL clock used as SAI1 clock source */
00397 #define LL_RCC_SAI1_CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL_1                                   /*!< EXT clock used as SAI1 clock source */
00398 #define LL_RCC_SAI1_CLKSOURCE_HSI          (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1)           /*!< HSI clock used as SAI1 clock source */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE  Peripheral I2S clock source selection
00404   * @{
00405   */
00406 #define LL_RCC_I2S_CLKSOURCE_SYSCLK       0x00000000U                                          /*!< System clock used as I2S clock source */
00407 #define LL_RCC_I2S_CLKSOURCE_PLL          RCC_CCIPR_I2S23SEL_0                                 /*!< PLL clock used as I2S clock source */
00408 #define LL_RCC_I2S_CLKSOURCE_PIN          RCC_CCIPR_I2S23SEL_1                                 /*!< EXT clock used as I2S clock source */
00409 #define LL_RCC_I2S_CLKSOURCE_HSI          (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1)        /*!< HSI clock used as I2S clock source */
00410 /**
00411   * @}
00412   */
00413
00414 #if defined(FDCAN1)
00415 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
00416   * @{
00417   */
00418 #define LL_RCC_FDCAN_CLKSOURCE_HSE        0x00000000U             /*!< HSE clock used as FDCAN clock source */
00419 #define LL_RCC_FDCAN_CLKSOURCE_PLL        RCC_CCIPR_FDCANSEL_0    /*!< PLL clock used as FDCAN clock source */
00420 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1      RCC_CCIPR_FDCANSEL_1    /*!< PCLK1 clock used as FDCAN clock source */
00421 /**
00422   * @}
00423   */
00424 #endif /* FDCAN1 */
00425
00426 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
00427   * @{
00428   */
00429 #define LL_RCC_RNG_CLKSOURCE_HSI48        0x00000000U             /*!< HSI48 clock used as RNG clock source */
00430 #define LL_RCC_RNG_CLKSOURCE_PLL          RCC_CCIPR_CLK48SEL_1    /*!< PLL clock used as RNG clock source */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
00436   * @{
00437   */
00438 #define LL_RCC_USB_CLKSOURCE_HSI48        0x00000000U             /*!< HSI48 clock used as USB clock source */
00439 #define LL_RCC_USB_CLKSOURCE_PLL          RCC_CCIPR_CLK48SEL_1    /*!< PLL clock used as USB clock source */
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
00445   * @{
00446   */
00447 #define LL_RCC_ADC12_CLKSOURCE_NONE        (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U))                                                       /*!< No clock used as ADC12 clock source */
00448 #define LL_RCC_ADC12_CLKSOURCE_PLL         (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos))    /*!< PLL clock used as ADC12 clock source */
00449 #define LL_RCC_ADC12_CLKSOURCE_SYSCLK      (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos))    /*!< SYSCLK clock used as ADC12 clock source */
00450 #if defined(RCC_CCIPR_ADC345SEL)
00451 #define LL_RCC_ADC345_CLKSOURCE_NONE       (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U))                                                      /*!< No clock used as ADC345 clock source */
00452 #define LL_RCC_ADC345_CLKSOURCE_PLL        (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
00453 #define LL_RCC_ADC345_CLKSOURCE_SYSCLK     (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
00454 #endif /* RCC_CCIPR_ADC345SEL */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup RCC_LL_EC_QUADSPI  Peripheral QUADSPI get clock source
00460   * @{
00461   */
00462 #define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK    0x00000000U              /*!< SYSCLK used as QuadSPI clock source */
00463 #define LL_RCC_QUADSPI_CLKSOURCE_HSI       RCC_CCIPR2_QSPISEL_0     /*!< HSI used as QuadSPI clock source */
00464 #define LL_RCC_QUADSPI_CLKSOURCE_PLL       RCC_CCIPR2_QSPISEL_1     /*!< PLL used as QuadSPI clock source */
00465 /**
00466   * @}
00467   */
00468
00469
00470 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
00471   * @{
00472   */
00473 #define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
00474 #define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
00475 #define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
00481   * @{
00482   */
00483 #if defined(RCC_CCIPR_UART4SEL)
00484 #define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
00485 #endif /* RCC_CCIPR_UART4SEL */
00486 #if defined(RCC_CCIPR_UART5SEL)
00487 #define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
00488 #endif /* RCC_CCIPR_UART5SEL */
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
00494   * @{
00495   */
00496 #define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
00502   * @{
00503   */
00504 #define LL_RCC_I2C1_CLKSOURCE              (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
00505 #define LL_RCC_I2C2_CLKSOURCE              (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
00506 #define LL_RCC_I2C3_CLKSOURCE              (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
00507 #if defined(RCC_CCIPR2_I2C4SEL)
00508 #define LL_RCC_I2C4_CLKSOURCE              (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
00509 #endif /* RCC_CCIPR2_I2C4SEL */
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
00515   * @{
00516   */
00517 #define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source
00523   * @{
00524   */
00525 #define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup RCC_LL_EC_I2S  Peripheral I2S get clock source
00531   * @{
00532   */
00533 #define LL_RCC_I2S_CLKSOURCE              RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
00534 /**
00535   * @}
00536   */
00537
00538 #if defined(FDCAN1)
00539 /** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
00540   * @{
00541   */
00542 #define LL_RCC_FDCAN_CLKSOURCE             RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
00543 #endif /* FDCAN1 */
00544
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
00550   * @{
00551   */
00552 #define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
00558   * @{
00559   */
00560 #define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
00566   * @{
00567   */
00568 #define LL_RCC_ADC12_CLKSOURCE             (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos))    /*!< ADC12 Clock source selection */
00569 #if defined(RCC_CCIPR_ADC345SEL_Pos)
00570 #define LL_RCC_ADC345_CLKSOURCE            (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
00571 #endif /* RCC_CCIPR_ADC345SEL_Pos */
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup RCC_LL_EC_QUADSPI  Peripheral QUADSPI get clock source
00577   * @{
00578   */
00579 #define LL_RCC_QUADSPI_CLKSOURCE           RCC_CCIPR2_QSPISEL    /*!< QuadSPI Clock source selection */
00580 /**
00581   * @}
00582   */
00583
00584 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00585   * @{
00586   */
00587 #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
00588 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00589 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00590 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00591 /**
00592   * @}
00593   */
00594
00595
00596 /** @defgroup RCC_LL_EC_PLLSOURCE  PLL entry clock source
00597   * @{
00598   */
00599 #define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
00600 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
00601 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup RCC_LL_EC_PLLM_DIV  PLL division factor
00607   * @{
00608   */
00609 #define LL_RCC_PLLM_DIV_1                  0x00000000U                                                                           /*!< PLL division factor by 1 */
00610 #define LL_RCC_PLLM_DIV_2                  RCC_PLLCFGR_PLLM_0                                                                    /*!< PLL division factor by 2 */
00611 #define LL_RCC_PLLM_DIV_3                  RCC_PLLCFGR_PLLM_1                                                                    /*!< PLL division factor by 3 */
00612 #define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 4 */
00613 #define LL_RCC_PLLM_DIV_5                  RCC_PLLCFGR_PLLM_2                                                                    /*!< PLL division factor by 5 */
00614 #define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 6 */
00615 #define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                                             /*!< PLL division factor by 7 */
00616 #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 8 */
00617 #define LL_RCC_PLLM_DIV_9                  RCC_PLLCFGR_PLLM_3                                                                    /*!< PLL division factor by 9 */
00618 #define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)                                             /*!< PLL division factor by 10 */
00619 #define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)                                             /*!< PLL division factor by 11 */
00620 #define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 12 */
00621 #define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)                                             /*!< PLL division factor by 13 */
00622 #define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 14 */
00623 #define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                        /*!< PLL division factor by 15 */
00624 #define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)   /*!< PLL division factor by 16 */
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
00630   * @{
00631   */
00632 #define LL_RCC_PLLR_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
00633 #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)   /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
00634 #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)   /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
00635 #define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)     /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
00641   * @{
00642   */
00643 #define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLPDIV_1)                                              /*!< Main PLL division factor for PLLP output by 2 */
00644 #define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 3 */
00645 #define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLPDIV_2)                                              /*!< Main PLL division factor for PLLP output by 4 */
00646 #define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 5 */
00647 #define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 6 */
00648 #define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 7 */
00649 #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLPDIV_3)                                              /*!< Main PLL division factor for PLLP output by 8 */
00650 #define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 9 */
00651 #define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 10 */
00652 #define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 11 */
00653 #define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 12 */
00654 #define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 13 */
00655 #define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 14 */
00656 #define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
00657 #define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLPDIV_4)                                              /*!< Main PLL division factor for PLLP output by 16 */
00658 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 17 */
00659 #define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 18 */
00660 #define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 19 */
00661 #define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 20 */
00662 #define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 21 */
00663 #define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 22 */
00664 #define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
00665 #define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 24 */
00666 #define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 25 */
00667 #define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 26 */
00668 #define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
00669 #define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)  /*!< Main PLL division factor for PLLP output by 28 */
00670 #define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
00671 #define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
00672 #define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
00678   * @{
00679   */
00680 #define LL_RCC_PLLQ_DIV_2                  0x00000000U             /*!< Main PLL division factor for PLLQ output by 2 */
00681 #define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)    /*!< Main PLL division factor for PLLQ output by 4 */
00682 #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)    /*!< Main PLL division factor for PLLQ output by 6 */
00683 #define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)      /*!< Main PLL division factor for PLLQ output by 8 */
00684 /**
00685   * @}
00686   */
00687
00688 /**
00689   * @}
00690   */
00691
00692 /* Exported macro ------------------------------------------------------------*/
00693 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00694   * @{
00695   */
00696
00697 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00698   * @{
00699   */
00700
00701 /**
00702   * @brief  Write a value in RCC register
00703   * @param  __REG__ Register to be written
00704   * @param  __VALUE__ Value to be written in the register
00705   * @retval None
00706   */
00707 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
00708
00709 /**
00710   * @brief  Read a value in RCC register
00711   * @param  __REG__ Register to be read
00712   * @retval Register value
00713   */
00714 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00715 /**
00716   * @}
00717   */
00718
00719 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00720   * @{
00721   */
00722
00723 /**
00724   * @brief  Helper macro to calculate the PLLCLK frequency on system domain
00725   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00726   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
00727   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00728   * @param  __PLLM__ This parameter can be one of the following values:
00729   *         @arg @ref LL_RCC_PLLM_DIV_1
00730   *         @arg @ref LL_RCC_PLLM_DIV_2
00731   *         @arg @ref LL_RCC_PLLM_DIV_3
00732   *         @arg @ref LL_RCC_PLLM_DIV_4
00733   *         @arg @ref LL_RCC_PLLM_DIV_5
00734   *         @arg @ref LL_RCC_PLLM_DIV_6
00735   *         @arg @ref LL_RCC_PLLM_DIV_7
00736   *         @arg @ref LL_RCC_PLLM_DIV_8
00737   *         @arg @ref LL_RCC_PLLM_DIV_9
00738   *         @arg @ref LL_RCC_PLLM_DIV_10
00739   *         @arg @ref LL_RCC_PLLM_DIV_11
00740   *         @arg @ref LL_RCC_PLLM_DIV_12
00741   *         @arg @ref LL_RCC_PLLM_DIV_13
00742   *         @arg @ref LL_RCC_PLLM_DIV_14
00743   *         @arg @ref LL_RCC_PLLM_DIV_15
00744   *         @arg @ref LL_RCC_PLLM_DIV_16
00745   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
00746   * @param  __PLLR__ This parameter can be one of the following values:
00747   *         @arg @ref LL_RCC_PLLR_DIV_2
00748   *         @arg @ref LL_RCC_PLLR_DIV_4
00749   *         @arg @ref LL_RCC_PLLR_DIV_6
00750   *         @arg @ref LL_RCC_PLLR_DIV_8
00751   * @retval PLL clock frequency (in Hz)
00752   */
00753 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00754                    ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
00755
00756 /**
00757   * @brief  Helper macro to calculate the PLLCLK frequency used on ADC domain
00758   * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00759   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00760   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00761   * @param  __PLLM__ This parameter can be one of the following values:
00762   *         @arg @ref LL_RCC_PLLM_DIV_1
00763   *         @arg @ref LL_RCC_PLLM_DIV_2
00764   *         @arg @ref LL_RCC_PLLM_DIV_3
00765   *         @arg @ref LL_RCC_PLLM_DIV_4
00766   *         @arg @ref LL_RCC_PLLM_DIV_5
00767   *         @arg @ref LL_RCC_PLLM_DIV_6
00768   *         @arg @ref LL_RCC_PLLM_DIV_7
00769   *         @arg @ref LL_RCC_PLLM_DIV_8
00770   *         @arg @ref LL_RCC_PLLM_DIV_9
00771   *         @arg @ref LL_RCC_PLLM_DIV_10
00772   *         @arg @ref LL_RCC_PLLM_DIV_11
00773   *         @arg @ref LL_RCC_PLLM_DIV_12
00774   *         @arg @ref LL_RCC_PLLM_DIV_13
00775   *         @arg @ref LL_RCC_PLLM_DIV_14
00776   *         @arg @ref LL_RCC_PLLM_DIV_15
00777   *         @arg @ref LL_RCC_PLLM_DIV_16
00778
00779   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
00780   * @param  __PLLP__ This parameter can be one of the following values:
00781   *         @arg @ref LL_RCC_PLLP_DIV_2
00782   *         @arg @ref LL_RCC_PLLP_DIV_3
00783   *         @arg @ref LL_RCC_PLLP_DIV_4
00784   *         @arg @ref LL_RCC_PLLP_DIV_5
00785   *         @arg @ref LL_RCC_PLLP_DIV_6
00786   *         @arg @ref LL_RCC_PLLP_DIV_7
00787   *         @arg @ref LL_RCC_PLLP_DIV_8
00788   *         @arg @ref LL_RCC_PLLP_DIV_9
00789   *         @arg @ref LL_RCC_PLLP_DIV_10
00790   *         @arg @ref LL_RCC_PLLP_DIV_11
00791   *         @arg @ref LL_RCC_PLLP_DIV_12
00792   *         @arg @ref LL_RCC_PLLP_DIV_13
00793   *         @arg @ref LL_RCC_PLLP_DIV_14
00794   *         @arg @ref LL_RCC_PLLP_DIV_15
00795   *         @arg @ref LL_RCC_PLLP_DIV_16
00796   *         @arg @ref LL_RCC_PLLP_DIV_17
00797   *         @arg @ref LL_RCC_PLLP_DIV_18
00798   *         @arg @ref LL_RCC_PLLP_DIV_19
00799   *         @arg @ref LL_RCC_PLLP_DIV_20
00800   *         @arg @ref LL_RCC_PLLP_DIV_21
00801   *         @arg @ref LL_RCC_PLLP_DIV_22
00802   *         @arg @ref LL_RCC_PLLP_DIV_23
00803   *         @arg @ref LL_RCC_PLLP_DIV_24
00804   *         @arg @ref LL_RCC_PLLP_DIV_25
00805   *         @arg @ref LL_RCC_PLLP_DIV_26
00806   *         @arg @ref LL_RCC_PLLP_DIV_27
00807   *         @arg @ref LL_RCC_PLLP_DIV_28
00808   *         @arg @ref LL_RCC_PLLP_DIV_29
00809   *         @arg @ref LL_RCC_PLLP_DIV_30
00810   *         @arg @ref LL_RCC_PLLP_DIV_31
00811   * @retval PLL clock frequency (in Hz)
00812   */
00813 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00814                    ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
00815
00816 /**
00817   * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
00818   * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00819   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
00820   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00821   * @param  __PLLM__ This parameter can be one of the following values:
00822   *         @arg @ref LL_RCC_PLLM_DIV_1
00823   *         @arg @ref LL_RCC_PLLM_DIV_2
00824   *         @arg @ref LL_RCC_PLLM_DIV_3
00825   *         @arg @ref LL_RCC_PLLM_DIV_4
00826   *         @arg @ref LL_RCC_PLLM_DIV_5
00827   *         @arg @ref LL_RCC_PLLM_DIV_6
00828   *         @arg @ref LL_RCC_PLLM_DIV_7
00829   *         @arg @ref LL_RCC_PLLM_DIV_8
00830   *         @arg @ref LL_RCC_PLLM_DIV_9
00831   *         @arg @ref LL_RCC_PLLM_DIV_10
00832   *         @arg @ref LL_RCC_PLLM_DIV_11
00833   *         @arg @ref LL_RCC_PLLM_DIV_12
00834   *         @arg @ref LL_RCC_PLLM_DIV_13
00835   *         @arg @ref LL_RCC_PLLM_DIV_14
00836   *         @arg @ref LL_RCC_PLLM_DIV_15
00837   *         @arg @ref LL_RCC_PLLM_DIV_16
00838   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 127
00839   * @param  __PLLQ__ This parameter can be one of the following values:
00840   *         @arg @ref LL_RCC_PLLQ_DIV_2
00841   *         @arg @ref LL_RCC_PLLQ_DIV_4
00842   *         @arg @ref LL_RCC_PLLQ_DIV_6
00843   *         @arg @ref LL_RCC_PLLQ_DIV_8
00844   * @retval PLL clock frequency (in Hz)
00845   */
00846 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00847                    ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
00848
00849 /**
00850   * @brief  Helper macro to calculate the HCLK frequency
00851   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
00852   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
00853   *         @arg @ref LL_RCC_SYSCLK_DIV_1
00854   *         @arg @ref LL_RCC_SYSCLK_DIV_2
00855   *         @arg @ref LL_RCC_SYSCLK_DIV_4
00856   *         @arg @ref LL_RCC_SYSCLK_DIV_8
00857   *         @arg @ref LL_RCC_SYSCLK_DIV_16
00858   *         @arg @ref LL_RCC_SYSCLK_DIV_64
00859   *         @arg @ref LL_RCC_SYSCLK_DIV_128
00860   *         @arg @ref LL_RCC_SYSCLK_DIV_256
00861   *         @arg @ref LL_RCC_SYSCLK_DIV_512
00862   * @retval HCLK clock frequency (in Hz)
00863   */
00864 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos] & 0x1FU))
00865
00866 /**
00867   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
00868   * @param  __HCLKFREQ__ HCLK frequency
00869   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
00870   *         @arg @ref LL_RCC_APB1_DIV_1
00871   *         @arg @ref LL_RCC_APB1_DIV_2
00872   *         @arg @ref LL_RCC_APB1_DIV_4
00873   *         @arg @ref LL_RCC_APB1_DIV_8
00874   *         @arg @ref LL_RCC_APB1_DIV_16
00875   * @retval PCLK1 clock frequency (in Hz)
00876   */
00877 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos] & 0x1FU))
00878
00879 /**
00880   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
00881   * @param  __HCLKFREQ__ HCLK frequency
00882   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
00883   *         @arg @ref LL_RCC_APB2_DIV_1
00884   *         @arg @ref LL_RCC_APB2_DIV_2
00885   *         @arg @ref LL_RCC_APB2_DIV_4
00886   *         @arg @ref LL_RCC_APB2_DIV_8
00887   *         @arg @ref LL_RCC_APB2_DIV_16
00888   * @retval PCLK2 clock frequency (in Hz)
00889   */
00890 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos] & 0x1FU))
00891
00892 /**
00893   * @}
00894   */
00895
00896 /**
00897   * @}
00898   */
00899
00900 /* Exported functions --------------------------------------------------------*/
00901 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
00902   * @{
00903   */
00904
00905 /** @defgroup RCC_LL_EF_HSE HSE
00906   * @{
00907   */
00908
00909 /**
00910   * @brief  Enable the Clock Security System.
00911   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
00912   * @retval None
00913   */
00914 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
00915 {
00916   SET_BIT(RCC->CR, RCC_CR_CSSON);
00917 }
00918
00919 /**
00920   * @brief  Enable HSE external oscillator (HSE Bypass)
00921   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
00922   * @retval None
00923   */
00924 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
00925 {
00926   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
00927 }
00928
00929 /**
00930   * @brief  Disable HSE external oscillator (HSE Bypass)
00931   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
00932   * @retval None
00933   */
00934 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
00935 {
00936   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00937 }
00938
00939 /**
00940   * @brief  Enable HSE crystal oscillator (HSE ON)
00941   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
00945 {
00946   SET_BIT(RCC->CR, RCC_CR_HSEON);
00947 }
00948
00949 /**
00950   * @brief  Disable HSE crystal oscillator (HSE ON)
00951   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
00955 {
00956   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
00957 }
00958
00959 /**
00960   * @brief  Check if HSE oscillator Ready
00961   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
00962   * @retval State of bit (1 or 0).
00963   */
00964 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
00965 {
00966   return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
00967 }
00968
00969 /**
00970   * @}
00971   */
00972
00973 /** @defgroup RCC_LL_EF_HSI HSI
00974   * @{
00975   */
00976
00977 /**
00978   * @brief  Enable HSI even in stop mode
00979   * @note HSI oscillator is forced ON even in Stop mode
00980   * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
00984 {
00985   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
00986 }
00987
00988 /**
00989   * @brief  Disable HSI in stop mode
00990   * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
00991   * @retval None
00992   */
00993 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
00994 {
00995   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
00996 }
00997
00998 /**
00999   * @brief  Enable HSI oscillator
01000   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01001   * @retval None
01002   */
01003 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01004 {
01005   SET_BIT(RCC->CR, RCC_CR_HSION);
01006 }
01007
01008 /**
01009   * @brief  Disable HSI oscillator
01010   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01014 {
01015   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01016 }
01017
01018 /**
01019   * @brief  Check if HSI clock is ready
01020   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01021   * @retval State of bit (1 or 0).
01022   */
01023 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01024 {
01025   return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
01026 }
01027
01028 /**
01029   * @brief  Get HSI Calibration value
01030   * @note When HSITRIM is written, HSICAL is updated with the sum of
01031   *       HSITRIM and the factory trim value
01032   * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
01033   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01034   */
01035 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01036 {
01037   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
01038 }
01039
01040 /**
01041   * @brief  Set HSI Calibration trimming
01042   * @note user-programmable trimming value that is added to the HSICAL
01043   * @note Default value is 16, which, when added to the HSICAL value,
01044   *       should trim the HSI to 16 MHz +/- 1 %
01045   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01046   * @param  Value Between Min_Data = 0 and Max_Data = 127
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01050 {
01051   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
01052 }
01053
01054 /**
01055   * @brief  Get HSI Calibration trimming
01056   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01057   * @retval Between Min_Data = 0 and Max_Data = 127
01058   */
01059 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01060 {
01061   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
01062 }
01063
01064 /**
01065   * @}
01066   */
01067
01068 /** @defgroup RCC_LL_EF_HSI48 HSI48
01069   * @{
01070   */
01071
01072 /**
01073   * @brief  Enable HSI48
01074   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
01075   * @retval None
01076   */
01077 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
01078 {
01079   SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01080 }
01081
01082 /**
01083   * @brief  Disable HSI48
01084   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
01088 {
01089   CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01090 }
01091
01092 /**
01093   * @brief  Check if HSI48 oscillator Ready
01094   * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
01095   * @retval State of bit (1 or 0).
01096   */
01097 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
01098 {
01099   return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
01100 }
01101
01102 /**
01103   * @brief  Get HSI48 Calibration value
01104   * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
01105   * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
01106   */
01107 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
01108 {
01109   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
01110 }
01111
01112 /**
01113   * @}
01114   */
01115
01116 /** @defgroup RCC_LL_EF_LSE LSE
01117   * @{
01118   */
01119
01120 /**
01121   * @brief  Enable  Low Speed External (LSE) crystal.
01122   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01126 {
01127   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01128 }
01129
01130 /**
01131   * @brief  Disable  Low Speed External (LSE) crystal.
01132   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01133   * @retval None
01134   */
01135 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01136 {
01137   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01138 }
01139
01140 /**
01141   * @brief  Enable external clock source (LSE bypass).
01142   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01143   * @retval None
01144   */
01145 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01146 {
01147   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01148 }
01149
01150 /**
01151   * @brief  Disable external clock source (LSE bypass).
01152   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01153   * @retval None
01154   */
01155 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01156 {
01157   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01158 }
01159
01160 /**
01161   * @brief  Set LSE oscillator drive capability
01162   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01163   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01164   * @param  LSEDrive This parameter can be one of the following values:
01165   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01166   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01167   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01168   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01169   * @retval None
01170   */
01171 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01172 {
01173   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01174 }
01175
01176 /**
01177   * @brief  Get LSE oscillator drive capability
01178   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01179   * @retval Returned value can be one of the following values:
01180   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01181   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01182   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01183   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01184   */
01185 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01186 {
01187   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01188 }
01189
01190 /**
01191   * @brief  Enable Clock security system on LSE.
01192   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
01193   * @retval None
01194   */
01195 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
01196 {
01197   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01198 }
01199
01200 /**
01201   * @brief  Disable Clock security system on LSE.
01202   * @note Clock security system can be disabled only after a LSE
01203   *       failure detection. In that case it MUST be disabled by software.
01204   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
01205   * @retval None
01206   */
01207 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
01208 {
01209   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01210 }
01211
01212 /**
01213   * @brief  Check if LSE oscillator Ready
01214   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01215   * @retval State of bit (1 or 0).
01216   */
01217 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01218 {
01219   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
01220 }
01221
01222 /**
01223   * @brief  Check if CSS on LSE failure Detection
01224   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
01225   * @retval State of bit (1 or 0).
01226   */
01227 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
01228 {
01229   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
01230 }
01231
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup RCC_LL_EF_LSI LSI
01237   * @{
01238   */
01239
01240 /**
01241   * @brief  Enable LSI Oscillator
01242   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
01243   * @retval None
01244   */
01245 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
01246 {
01247   SET_BIT(RCC->CSR, RCC_CSR_LSION);
01248 }
01249
01250 /**
01251   * @brief  Disable LSI Oscillator
01252   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
01253   * @retval None
01254   */
01255 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
01256 {
01257   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01258 }
01259
01260 /**
01261   * @brief  Check if LSI is Ready
01262   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01263   * @retval State of bit (1 or 0).
01264   */
01265 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01266 {
01267   return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
01268 }
01269
01270 /**
01271   * @}
01272   */
01273
01274 /** @defgroup RCC_LL_EF_LSCO LSCO
01275   * @{
01276   */
01277
01278 /**
01279   * @brief  Enable Low speed clock
01280   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
01281   * @retval None
01282   */
01283 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
01284 {
01285   SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01286 }
01287
01288 /**
01289   * @brief  Disable Low speed clock
01290   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
01291   * @retval None
01292   */
01293 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
01294 {
01295   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01296 }
01297
01298 /**
01299   * @brief  Configure Low speed clock selection
01300   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
01301   * @param  Source This parameter can be one of the following values:
01302   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01303   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01304   * @retval None
01305   */
01306 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
01307 {
01308   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
01309 }
01310
01311 /**
01312   * @brief  Get Low speed clock selection
01313   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
01314   * @retval Returned value can be one of the following values:
01315   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01316   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01317   */
01318 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
01319 {
01320   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
01321 }
01322
01323 /**
01324   * @}
01325   */
01326
01327 /** @defgroup RCC_LL_EF_System System
01328   * @{
01329   */
01330
01331 /**
01332   * @brief  Configure the system clock source
01333   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
01334   * @param  Source This parameter can be one of the following values:
01335   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
01336   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
01337   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
01338   * @retval None
01339   */
01340 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
01341 {
01342   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
01343 }
01344
01345 /**
01346   * @brief  Get the system clock source
01347   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
01348   * @retval Returned value can be one of the following values:
01349   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
01350   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
01351   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
01352   */
01353 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
01354 {
01355   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
01356 }
01357
01358 /**
01359   * @brief  Set AHB prescaler
01360   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
01361   * @param  Prescaler This parameter can be one of the following values:
01362   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01363   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01364   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01365   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01366   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01367   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01368   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01369   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01370   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01371   * @retval None
01372   */
01373 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
01374 {
01375   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
01376 }
01377
01378 /**
01379   * @brief  Set APB1 prescaler
01380   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
01381   * @param  Prescaler This parameter can be one of the following values:
01382   *         @arg @ref LL_RCC_APB1_DIV_1
01383   *         @arg @ref LL_RCC_APB1_DIV_2
01384   *         @arg @ref LL_RCC_APB1_DIV_4
01385   *         @arg @ref LL_RCC_APB1_DIV_8
01386   *         @arg @ref LL_RCC_APB1_DIV_16
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
01390 {
01391   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
01392 }
01393
01394 /**
01395   * @brief  Set APB2 prescaler
01396   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
01397   * @param  Prescaler This parameter can be one of the following values:
01398   *         @arg @ref LL_RCC_APB2_DIV_1
01399   *         @arg @ref LL_RCC_APB2_DIV_2
01400   *         @arg @ref LL_RCC_APB2_DIV_4
01401   *         @arg @ref LL_RCC_APB2_DIV_8
01402   *         @arg @ref LL_RCC_APB2_DIV_16
01403   * @retval None
01404   */
01405 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
01406 {
01407   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
01408 }
01409
01410 /**
01411   * @brief  Get AHB prescaler
01412   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
01413   * @retval Returned value can be one of the following values:
01414   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01415   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01416   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01417   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01418   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01419   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01420   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01421   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01422   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01423   */
01424 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
01425 {
01426   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
01427 }
01428
01429 /**
01430   * @brief  Get APB1 prescaler
01431   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
01432   * @retval Returned value can be one of the following values:
01433   *         @arg @ref LL_RCC_APB1_DIV_1
01434   *         @arg @ref LL_RCC_APB1_DIV_2
01435   *         @arg @ref LL_RCC_APB1_DIV_4
01436   *         @arg @ref LL_RCC_APB1_DIV_8
01437   *         @arg @ref LL_RCC_APB1_DIV_16
01438   */
01439 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
01440 {
01441   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
01442 }
01443
01444 /**
01445   * @brief  Get APB2 prescaler
01446   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
01447   * @retval Returned value can be one of the following values:
01448   *         @arg @ref LL_RCC_APB2_DIV_1
01449   *         @arg @ref LL_RCC_APB2_DIV_2
01450   *         @arg @ref LL_RCC_APB2_DIV_4
01451   *         @arg @ref LL_RCC_APB2_DIV_8
01452   *         @arg @ref LL_RCC_APB2_DIV_16
01453   */
01454 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
01455 {
01456   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
01457 }
01458
01459 /**
01460   * @}
01461   */
01462
01463 /** @defgroup RCC_LL_EF_MCO MCO
01464   * @{
01465   */
01466
01467 /**
01468   * @brief  Configure MCOx
01469   * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
01470   *         CFGR         MCOPRE        LL_RCC_ConfigMCO
01471   * @param  MCOxSource This parameter can be one of the following values:
01472   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
01473   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
01474   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
01475   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
01476   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
01477   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
01478   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
01479   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
01480   *
01481   *         (*) value not defined in all devices.
01482   * @param  MCOxPrescaler This parameter can be one of the following values:
01483   *         @arg @ref LL_RCC_MCO1_DIV_1
01484   *         @arg @ref LL_RCC_MCO1_DIV_2
01485   *         @arg @ref LL_RCC_MCO1_DIV_4
01486   *         @arg @ref LL_RCC_MCO1_DIV_8
01487   *         @arg @ref LL_RCC_MCO1_DIV_16
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
01491 {
01492   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
01493 }
01494
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
01500   * @{
01501   */
01502
01503 /**
01504   * @brief  Configure USARTx clock source
01505   * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
01506   * @param  USARTxSource This parameter can be one of the following values:
01507   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
01508   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01509   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01510   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01511   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
01512   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
01513   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
01514   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
01515   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
01516   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
01517   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
01518   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
01519   * @retval None
01520   */
01521 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
01522 {
01523   MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
01524 }
01525
01526 #if defined(UART4)
01527 /**
01528   * @brief  Configure UARTx clock source
01529   * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource
01530   * @param  UARTxSource This parameter can be one of the following values:
01531   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
01532   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
01533   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
01534   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
01535   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
01536   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
01537   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
01538   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
01539   *
01540   *         (*) value not defined in all devices.
01541   * @retval None
01542   */
01543 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
01544 {
01545   MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
01546 }
01547 #endif /* UART4 */
01548
01549 /**
01550   * @brief  Configure LPUART1x clock source
01551   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
01552   * @param  LPUARTxSource This parameter can be one of the following values:
01553   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
01554   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
01555   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
01556   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
01557   * @retval None
01558   */
01559 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
01560 {
01561   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
01562 }
01563
01564 /**
01565   * @brief  Configure I2Cx clock source
01566   * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
01567   * @param  I2CxSource This parameter can be one of the following values:
01568   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
01569   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01570   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01571   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
01572   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
01573   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
01574   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
01575   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
01576   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
01577   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
01578   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
01579   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
01580   *
01581   *         (*) value not defined in all devices.
01582   * @retval None
01583   */
01584 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
01585 {
01586   __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
01587   MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
01588 }
01589
01590 /**
01591   * @brief  Configure LPTIMx clock source
01592   * @rmtoll CCIPR        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
01593   * @param  LPTIMxSource This parameter can be one of the following values:
01594   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
01595   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
01596   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
01597   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
01598   * @retval None
01599   */
01600 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
01601 {
01602   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
01603 }
01604
01605 /**
01606   * @brief  Configure SAIx clock source
01607   * @rmtoll CCIPR        SAI1SEL       LL_RCC_SetSAIClockSource
01608   * @param  SAIxSource This parameter can be one of the following values:
01609   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
01610   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
01611   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
01612   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
01613   *
01614   *         (*) value not defined in all devices.
01615   * @retval None
01616   */
01617 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
01618 {
01619   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
01620 }
01621
01622 /**
01623   * @brief  Configure I2S clock source
01624   * @rmtoll CCIPR        I2S23SEL      LL_RCC_SetI2SClockSource
01625   * @param  I2SxSource This parameter can be one of the following values:
01626   *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
01627   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
01628   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
01629   *         @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
01630   * @retval None
01631   */
01632 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
01633 {
01634   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
01635 }
01636
01637 #if defined(FDCAN1)
01638 /**
01639   * @brief  Configure FDCAN clock source
01640   * @rmtoll CCIPR        FDCANSEL      LL_RCC_SetFDCANClockSource
01641   * @param  FDCANxSource This parameter can be one of the following values:
01642   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
01643   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
01644   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
01645   * @retval None
01646   */
01647 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
01648 {
01649   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
01650 }
01651 #endif /* FDCAN1 */
01652
01653 /**
01654   * @brief  Configure RNG clock source
01655   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource
01656   * @param  RNGxSource This parameter can be one of the following values:
01657   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
01658   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
01662 {
01663   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
01664 }
01665
01666 /**
01667   * @brief  Configure USB clock source
01668   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
01669   * @param  USBxSource This parameter can be one of the following values:
01670   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
01671   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01672   * @retval None
01673   */
01674 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
01675 {
01676   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
01677 }
01678
01679 /**
01680   * @brief  Configure ADC clock source
01681   * @rmtoll CCIPR        ADC12SEL         LL_RCC_SetADCClockSource\n
01682   *         CCIPR        ADC345SEL        LL_RCC_SetADCClockSource
01683   * @param  ADCxSource This parameter can be one of the following values:
01684   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
01685   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
01686   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
01687   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE   (*)
01688   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL    (*)
01689   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
01690   *
01691   *         (*) value not defined in all devices.
01692   * @retval None
01693   */
01694 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01695 {
01696   MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
01697 }
01698
01699 #if defined(QUADSPI)
01700 /**
01701   * @brief  Configure QUADSPI clock source
01702   * @rmtoll CCIPR2         QSPISEL     LL_RCC_SetQUADSPIClockSource
01703   * @param  Source This parameter can be one of the following values:
01704   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
01705   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
01706   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
01707   * @retval None
01708   */
01709 __STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
01710 {
01711   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
01712 }
01713 #endif /* QUADSPI */
01714
01715 /**
01716   * @brief  Get USARTx clock source
01717   * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
01718   * @param  USARTx This parameter can be one of the following values:
01719   *         @arg @ref LL_RCC_USART1_CLKSOURCE
01720   *         @arg @ref LL_RCC_USART2_CLKSOURCE
01721   *         @arg @ref LL_RCC_USART3_CLKSOURCE
01722   * @retval Returned value can be one of the following values:
01723   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
01724   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01725   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01726   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01727   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
01728   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
01729   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
01730   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
01731   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
01732   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
01733   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
01734   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
01735   */
01736 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
01737 {
01738   return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
01739 }
01740
01741 #if defined(UART4)
01742 /**
01743   * @brief  Get UARTx clock source
01744   * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource
01745   * @param  UARTx This parameter can be one of the following values:
01746   *         @arg @ref LL_RCC_UART4_CLKSOURCE (*)
01747   *         @arg @ref LL_RCC_UART5_CLKSOURCE (*)
01748   * @retval Returned value can be one of the following values:
01749   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
01750   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
01751   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
01752   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
01753   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
01754   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
01755   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
01756   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
01757   *
01758   *         (*) value not defined in all devices.
01759   */
01760 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
01761 {
01762   return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
01763 }
01764 #endif /* UART4 */
01765
01766 /**
01767   * @brief  Get LPUARTx clock source
01768   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
01769   * @param  LPUARTx This parameter can be one of the following values:
01770   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
01771   * @retval Returned value can be one of the following values:
01772   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
01773   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
01774   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
01775   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
01776   */
01777 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
01778 {
01779   return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
01780 }
01781
01782 /**
01783   * @brief  Get I2Cx clock source
01784   * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
01785   * @param  I2Cx This parameter can be one of the following values:
01786   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
01787   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
01788   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
01789   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
01790   *
01791   *         (*) value not defined in all devices.
01792   * @retval Returned value can be one of the following values:
01793   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
01794   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01795   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01796   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
01797   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
01798   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
01799   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
01800   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
01801   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
01802   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
01803   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
01804   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
01805   *
01806   *         (*) value not defined in all devices.
01807  */
01808 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
01809 {
01810   __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
01811   return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
01812 }
01813
01814 /**
01815   * @brief  Get LPTIMx clock source
01816   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
01817   * @param  LPTIMx This parameter can be one of the following values:
01818   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
01819   * @retval Returned value can be one of the following values:
01820   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
01821   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
01822   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
01823   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
01824   */
01825 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
01826 {
01827   return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
01828 }
01829
01830 /**
01831   * @brief  Get SAIx clock source
01832   * @rmtoll CCIPR        SAI1SEL       LL_RCC_GetSAIClockSource
01833   * @param  SAIx This parameter can be one of the following values:
01834   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
01835   *
01836   *         (*) value not defined in all devices.
01837   * @retval Returned value can be one of the following values:
01838   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
01839   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
01840   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
01841   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
01842   *
01843   *         (*) value not defined in all devices.
01844   */
01845 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
01846 {
01847   return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
01848 }
01849
01850 /**
01851   * @brief  Get I2Sx clock source
01852   * @rmtoll CCIPR        I2S23SEL      LL_RCC_GetI2SClockSource
01853   * @param  I2Sx This parameter can be one of the following values:
01854   *         @arg @ref LL_RCC_I2S_CLKSOURCE
01855   * @retval Returned value can be one of the following values:
01856   *         @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
01857   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
01858   *         @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
01859   *         @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
01860   */
01861 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
01862 {
01863   return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
01864 }
01865
01866 #if defined(FDCAN1)
01867 /**
01868   * @brief  Get FDCANx clock source
01869   * @rmtoll CCIPR        FDCANSEL      LL_RCC_GetFDCANClockSource
01870   * @param  FDCANx This parameter can be one of the following values:
01871   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
01872   * @retval Returned value can be one of the following values:
01873   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
01874   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
01875   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
01876   * @retval None
01877   */
01878 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
01879 {
01880   return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
01881 }
01882 #endif /* FDCAN1 */
01883
01884 /**
01885   * @brief  Get RNGx clock source
01886   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
01887   * @param  RNGx This parameter can be one of the following values:
01888   *         @arg @ref LL_RCC_RNG_CLKSOURCE
01889   * @retval Returned value can be one of the following values:
01890   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
01891   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
01892   */
01893 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
01894 {
01895   return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
01896 }
01897
01898 /**
01899   * @brief  Get USBx clock source
01900   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
01901   * @param  USBx This parameter can be one of the following values:
01902   *         @arg @ref LL_RCC_USB_CLKSOURCE
01903   * @retval Returned value can be one of the following values:
01904   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
01905   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01906   */
01907 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
01908 {
01909   return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
01910 }
01911
01912 /**
01913   * @brief  Get ADCx clock source
01914   * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
01915   * @param  ADCx This parameter can be one of the following values:
01916   *         @arg @ref LL_RCC_ADC12_CLKSOURCE
01917   *         @arg @ref LL_RCC_ADC345_CLKSOURCE        (*)
01918   * @retval Returned value can be one of the following values:
01919   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
01920   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
01921   *         @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
01922   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE   (*)
01923   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL    (*)
01924   *         @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
01925   *
01926   *         (*) value not defined in all devices.
01927   */
01928 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
01929 {
01930   return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
01931 }
01932
01933 #if defined(QUADSPI)
01934 /**
01935   * @brief  Get QUADSPI clock source
01936   * @rmtoll CCIPR2         QSPISEL     LL_RCC_GetQUADSPIClockSource
01937   * @param  QUADSPIx This parameter can be one of the following values:
01938   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE
01939   * @retval Returned value can be one of the following values:
01940   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
01941   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
01942   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
01943   */
01944 __STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
01945 {
01946   return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
01947 }
01948 #endif /* QUADSPI */
01949 /**
01950   * @}
01951   */
01952
01953 /** @defgroup RCC_LL_EF_RTC RTC
01954   * @{
01955   */
01956
01957 /**
01958   * @brief  Set RTC Clock Source
01959   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
01960   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
01961   *       set). The BDRST bit can be used to reset them.
01962   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
01963   * @param  Source This parameter can be one of the following values:
01964   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
01965   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
01966   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
01967   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
01968   * @retval None
01969   */
01970 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
01971 {
01972   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
01973 }
01974
01975 /**
01976   * @brief  Get RTC Clock Source
01977   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
01978   * @retval Returned value can be one of the following values:
01979   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
01980   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
01981   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
01982   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
01983   */
01984 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
01985 {
01986   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
01987 }
01988
01989 /**
01990   * @brief  Enable RTC
01991   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
01992   * @retval None
01993   */
01994 __STATIC_INLINE void LL_RCC_EnableRTC(void)
01995 {
01996   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
01997 }
01998
01999 /**
02000   * @brief  Disable RTC
02001   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02002   * @retval None
02003   */
02004 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02005 {
02006   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02007 }
02008
02009 /**
02010   * @brief  Check if RTC has been enabled or not
02011   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02012   * @retval State of bit (1 or 0).
02013   */
02014 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02015 {
02016   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
02017 }
02018
02019 /**
02020   * @brief  Force the Backup domain reset
02021   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02022   * @retval None
02023   */
02024 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02025 {
02026   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02027 }
02028
02029 /**
02030   * @brief  Release the Backup domain reset
02031   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02032   * @retval None
02033   */
02034 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02035 {
02036   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02037 }
02038
02039 /**
02040   * @}
02041   */
02042
02043
02044 /** @defgroup RCC_LL_EF_PLL PLL
02045   * @{
02046   */
02047
02048 /**
02049   * @brief  Enable PLL
02050   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02054 {
02055   SET_BIT(RCC->CR, RCC_CR_PLLON);
02056 }
02057
02058 /**
02059   * @brief  Disable PLL
02060   * @note Cannot be disabled if the PLL clock is used as the system clock
02061   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02065 {
02066   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02067 }
02068
02069 /**
02070   * @brief  Check if PLL Ready
02071   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02072   * @retval State of bit (1 or 0).
02073   */
02074 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02075 {
02076   return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
02077 }
02078
02079 /**
02080   * @brief  Configure PLL used for SYSCLK Domain
02081   * @note PLL Source and PLLM Divider can be written only when PLL
02082   *       is disabled.
02083   * @note PLLN/PLLR can be written only when PLL is disabled.
02084   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02085   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
02086   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
02087   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
02088   * @param  Source This parameter can be one of the following values:
02089   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02090   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02091   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02092   * @param  PLLM This parameter can be one of the following values:
02093   *         @arg @ref LL_RCC_PLLM_DIV_1
02094   *         @arg @ref LL_RCC_PLLM_DIV_2
02095   *         @arg @ref LL_RCC_PLLM_DIV_3
02096   *         @arg @ref LL_RCC_PLLM_DIV_4
02097   *         @arg @ref LL_RCC_PLLM_DIV_5
02098   *         @arg @ref LL_RCC_PLLM_DIV_6
02099   *         @arg @ref LL_RCC_PLLM_DIV_7
02100   *         @arg @ref LL_RCC_PLLM_DIV_8
02101   *         @arg @ref LL_RCC_PLLM_DIV_9
02102   *         @arg @ref LL_RCC_PLLM_DIV_10
02103   *         @arg @ref LL_RCC_PLLM_DIV_11
02104   *         @arg @ref LL_RCC_PLLM_DIV_12
02105   *         @arg @ref LL_RCC_PLLM_DIV_13
02106   *         @arg @ref LL_RCC_PLLM_DIV_14
02107   *         @arg @ref LL_RCC_PLLM_DIV_15
02108   *         @arg @ref LL_RCC_PLLM_DIV_16
02109   * @param  PLLN Between Min_Data = 8 and Max_Data = 127
02110   * @param  PLLR This parameter can be one of the following values:
02111   *         @arg @ref LL_RCC_PLLR_DIV_2
02112   *         @arg @ref LL_RCC_PLLR_DIV_4
02113   *         @arg @ref LL_RCC_PLLR_DIV_6
02114   *         @arg @ref LL_RCC_PLLR_DIV_8
02115   * @retval None
02116   */
02117 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02118 {
02119   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
02120              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
02121 }
02122
02123 /**
02124   * @brief  Configure PLL used for ADC domain clock
02125   * @note PLL Source and PLLM Divider can be written only when PLL
02126   *       is disabled.
02127   * @note PLLN/PLLP can be written only when PLL is disabled.
02128   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_ADC\n
02129   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_ADC\n
02130   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_ADC\n
02131   *         PLLCFGR      PLLPDIV       LL_RCC_PLL_ConfigDomain_ADC
02132   * @param  Source This parameter can be one of the following values:
02133   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02134   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02135   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02136   * @param  PLLM This parameter can be one of the following values:
02137   *         @arg @ref LL_RCC_PLLM_DIV_1
02138   *         @arg @ref LL_RCC_PLLM_DIV_2
02139   *         @arg @ref LL_RCC_PLLM_DIV_3
02140   *         @arg @ref LL_RCC_PLLM_DIV_4
02141   *         @arg @ref LL_RCC_PLLM_DIV_5
02142   *         @arg @ref LL_RCC_PLLM_DIV_6
02143   *         @arg @ref LL_RCC_PLLM_DIV_7
02144   *         @arg @ref LL_RCC_PLLM_DIV_8
02145   *         @arg @ref LL_RCC_PLLM_DIV_9
02146   *         @arg @ref LL_RCC_PLLM_DIV_10
02147   *         @arg @ref LL_RCC_PLLM_DIV_11
02148   *         @arg @ref LL_RCC_PLLM_DIV_12
02149   *         @arg @ref LL_RCC_PLLM_DIV_13
02150   *         @arg @ref LL_RCC_PLLM_DIV_14
02151   *         @arg @ref LL_RCC_PLLM_DIV_15
02152   *         @arg @ref LL_RCC_PLLM_DIV_16
02153   * @param  PLLN Between Min_Data = 8 and Max_Data = 127
02154   * @param  PLLP This parameter can be one of the following values:
02155   *         @arg @ref LL_RCC_PLLP_DIV_2
02156   *         @arg @ref LL_RCC_PLLP_DIV_3
02157   *         @arg @ref LL_RCC_PLLP_DIV_4
02158   *         @arg @ref LL_RCC_PLLP_DIV_5
02159   *         @arg @ref LL_RCC_PLLP_DIV_6
02160   *         @arg @ref LL_RCC_PLLP_DIV_7
02161   *         @arg @ref LL_RCC_PLLP_DIV_8
02162   *         @arg @ref LL_RCC_PLLP_DIV_9
02163   *         @arg @ref LL_RCC_PLLP_DIV_10
02164   *         @arg @ref LL_RCC_PLLP_DIV_11
02165   *         @arg @ref LL_RCC_PLLP_DIV_12
02166   *         @arg @ref LL_RCC_PLLP_DIV_13
02167   *         @arg @ref LL_RCC_PLLP_DIV_14
02168   *         @arg @ref LL_RCC_PLLP_DIV_15
02169   *         @arg @ref LL_RCC_PLLP_DIV_16
02170   *         @arg @ref LL_RCC_PLLP_DIV_17
02171   *         @arg @ref LL_RCC_PLLP_DIV_18
02172   *         @arg @ref LL_RCC_PLLP_DIV_19
02173   *         @arg @ref LL_RCC_PLLP_DIV_20
02174   *         @arg @ref LL_RCC_PLLP_DIV_21
02175   *         @arg @ref LL_RCC_PLLP_DIV_22
02176   *         @arg @ref LL_RCC_PLLP_DIV_23
02177   *         @arg @ref LL_RCC_PLLP_DIV_24
02178   *         @arg @ref LL_RCC_PLLP_DIV_25
02179   *         @arg @ref LL_RCC_PLLP_DIV_26
02180   *         @arg @ref LL_RCC_PLLP_DIV_27
02181   *         @arg @ref LL_RCC_PLLP_DIV_28
02182   *         @arg @ref LL_RCC_PLLP_DIV_29
02183   *         @arg @ref LL_RCC_PLLP_DIV_30
02184   *         @arg @ref LL_RCC_PLLP_DIV_31
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02188 {
02189   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
02190              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
02191 }
02192
02193 /**
02194   * @brief  Configure PLL used for 48Mhz domain clock
02195   * @note PLL Source and PLLM Divider can be written only when PLL,
02196   *       is disabled.
02197   * @note PLLN/PLLQ can be written only when PLL is disabled.
02198   * @note This  can be selected for USB, RNG
02199   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
02200   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
02201   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
02202   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
02203   * @param  Source This parameter can be one of the following values:
02204   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02205   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02206   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02207   * @param  PLLM This parameter can be one of the following values:
02208   *         @arg @ref LL_RCC_PLLM_DIV_1
02209   *         @arg @ref LL_RCC_PLLM_DIV_2
02210   *         @arg @ref LL_RCC_PLLM_DIV_3
02211   *         @arg @ref LL_RCC_PLLM_DIV_4
02212   *         @arg @ref LL_RCC_PLLM_DIV_5
02213   *         @arg @ref LL_RCC_PLLM_DIV_6
02214   *         @arg @ref LL_RCC_PLLM_DIV_7
02215   *         @arg @ref LL_RCC_PLLM_DIV_8
02216   *         @arg @ref LL_RCC_PLLM_DIV_9
02217   *         @arg @ref LL_RCC_PLLM_DIV_10
02218   *         @arg @ref LL_RCC_PLLM_DIV_11
02219   *         @arg @ref LL_RCC_PLLM_DIV_12
02220   *         @arg @ref LL_RCC_PLLM_DIV_13
02221   *         @arg @ref LL_RCC_PLLM_DIV_14
02222   *         @arg @ref LL_RCC_PLLM_DIV_15
02223   *         @arg @ref LL_RCC_PLLM_DIV_16
02224   * @param  PLLN Between Min_Data = 8 and Max_Data = 127
02225   * @param  PLLQ This parameter can be one of the following values:
02226   *         @arg @ref LL_RCC_PLLQ_DIV_2
02227   *         @arg @ref LL_RCC_PLLQ_DIV_4
02228   *         @arg @ref LL_RCC_PLLQ_DIV_6
02229   *         @arg @ref LL_RCC_PLLQ_DIV_8
02230   * @retval None
02231   */
02232 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02233 {
02234   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02235              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02236 }
02237
02238 /**
02239   * @brief  Configure PLL clock source
02240   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
02241   * @param PLLSource This parameter can be one of the following values:
02242   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02243   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02244   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02245   * @retval None
02246   */
02247 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
02248 {
02249   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
02250 }
02251
02252 /**
02253   * @brief  Get the oscillator used as PLL clock source.
02254   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
02255   * @retval Returned value can be one of the following values:
02256   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02257   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02258   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02259   */
02260 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
02261 {
02262   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
02263 }
02264
02265 /**
02266   * @brief  Get Main PLL multiplication factor for VCO
02267   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
02268   * @retval Between Min_Data = 8 and Max_Data = 127
02269   */
02270 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
02271 {
02272   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
02273 }
02274
02275 /**
02276   * @brief  Get Main PLL division factor for PLLP
02277   * @note Used for PLLADCCLK (ADC clock)
02278   * @rmtoll PLLCFGR      PLLPDIV       LL_RCC_PLL_GetP\n
02279   * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP
02280   * @retval Returned value can be one of the following values:
02281   *         @arg @ref LL_RCC_PLLP_DIV_2
02282   *         @arg @ref LL_RCC_PLLP_DIV_3
02283   *         @arg @ref LL_RCC_PLLP_DIV_4
02284   *         @arg @ref LL_RCC_PLLP_DIV_5
02285   *         @arg @ref LL_RCC_PLLP_DIV_6
02286   *         @arg @ref LL_RCC_PLLP_DIV_7
02287   *         @arg @ref LL_RCC_PLLP_DIV_8
02288   *         @arg @ref LL_RCC_PLLP_DIV_9
02289   *         @arg @ref LL_RCC_PLLP_DIV_10
02290   *         @arg @ref LL_RCC_PLLP_DIV_11
02291   *         @arg @ref LL_RCC_PLLP_DIV_12
02292   *         @arg @ref LL_RCC_PLLP_DIV_13
02293   *         @arg @ref LL_RCC_PLLP_DIV_14
02294   *         @arg @ref LL_RCC_PLLP_DIV_15
02295   *         @arg @ref LL_RCC_PLLP_DIV_16
02296   *         @arg @ref LL_RCC_PLLP_DIV_17
02297   *         @arg @ref LL_RCC_PLLP_DIV_18
02298   *         @arg @ref LL_RCC_PLLP_DIV_19
02299   *         @arg @ref LL_RCC_PLLP_DIV_20
02300   *         @arg @ref LL_RCC_PLLP_DIV_21
02301   *         @arg @ref LL_RCC_PLLP_DIV_22
02302   *         @arg @ref LL_RCC_PLLP_DIV_23
02303   *         @arg @ref LL_RCC_PLLP_DIV_24
02304   *         @arg @ref LL_RCC_PLLP_DIV_25
02305   *         @arg @ref LL_RCC_PLLP_DIV_26
02306   *         @arg @ref LL_RCC_PLLP_DIV_27
02307   *         @arg @ref LL_RCC_PLLP_DIV_28
02308   *         @arg @ref LL_RCC_PLLP_DIV_29
02309   *         @arg @ref LL_RCC_PLLP_DIV_30
02310   *         @arg @ref LL_RCC_PLLP_DIV_31
02311   */
02312 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
02313 {
02314   return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
02315 }
02316
02317 /**
02318   * @brief  Get Main PLL division factor for PLLQ
02319   * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
02320   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
02321   * @retval Returned value can be one of the following values:
02322   *         @arg @ref LL_RCC_PLLQ_DIV_2
02323   *         @arg @ref LL_RCC_PLLQ_DIV_4
02324   *         @arg @ref LL_RCC_PLLQ_DIV_6
02325   *         @arg @ref LL_RCC_PLLQ_DIV_8
02326   */
02327 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
02328 {
02329   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
02330 }
02331
02332 /**
02333   * @brief  Get Main PLL division factor for PLLR
02334   * @note Used for PLLCLK (system clock)
02335   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
02336   * @retval Returned value can be one of the following values:
02337   *         @arg @ref LL_RCC_PLLR_DIV_2
02338   *         @arg @ref LL_RCC_PLLR_DIV_4
02339   *         @arg @ref LL_RCC_PLLR_DIV_6
02340   *         @arg @ref LL_RCC_PLLR_DIV_8
02341   */
02342 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
02343 {
02344   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
02345 }
02346
02347 /**
02348   * @brief  Get Division factor for the main PLL and other PLL
02349   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
02350   * @retval Returned value can be one of the following values:
02351   *         @arg @ref LL_RCC_PLLM_DIV_1
02352   *         @arg @ref LL_RCC_PLLM_DIV_2
02353   *         @arg @ref LL_RCC_PLLM_DIV_3
02354   *         @arg @ref LL_RCC_PLLM_DIV_4
02355   *         @arg @ref LL_RCC_PLLM_DIV_5
02356   *         @arg @ref LL_RCC_PLLM_DIV_6
02357   *         @arg @ref LL_RCC_PLLM_DIV_7
02358   *         @arg @ref LL_RCC_PLLM_DIV_8
02359   *         @arg @ref LL_RCC_PLLM_DIV_9
02360   *         @arg @ref LL_RCC_PLLM_DIV_10
02361   *         @arg @ref LL_RCC_PLLM_DIV_11
02362   *         @arg @ref LL_RCC_PLLM_DIV_12
02363   *         @arg @ref LL_RCC_PLLM_DIV_13
02364   *         @arg @ref LL_RCC_PLLM_DIV_14
02365   *         @arg @ref LL_RCC_PLLM_DIV_15
02366   *         @arg @ref LL_RCC_PLLM_DIV_16
02367   */
02368 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
02369 {
02370   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
02371 }
02372
02373 /**
02374   * @brief  Enable PLL output mapped on ADC domain clock
02375   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_ADC
02376   * @retval None
02377   */
02378 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
02379 {
02380   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
02381 }
02382
02383 /**
02384   * @brief  Disable PLL output mapped on ADC domain clock
02385   * @note Cannot be disabled if the PLL clock is used as the system
02386   *       clock
02387   * @note In order to save power, when the PLLCLK  of the PLL is
02388   *       not used,  should be 0
02389   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_ADC
02390   * @retval None
02391   */
02392 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
02393 {
02394   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
02395 }
02396
02397 /**
02398   * @brief  Check if PLL output mapped on ADC domain clock is enabled
02399   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_IsEnabledDomain_ADC
02400   * @retval State of bit (1 or 0).
02401   */
02402 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
02403 {
02404   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
02405 }
02406
02407 /**
02408   * @brief  Enable PLL output mapped on 48MHz domain clock
02409   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
02410   * @retval None
02411   */
02412 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
02413 {
02414   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
02415 }
02416
02417 /**
02418   * @brief  Disable PLL output mapped on 48MHz domain clock
02419   * @note Cannot be disabled if the PLL clock is used as the system
02420   *       clock
02421   * @note In order to save power, when the PLLCLK  of the PLL is
02422   *       not used,  should be 0
02423   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
02424   * @retval None
02425   */
02426 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
02427 {
02428   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
02429 }
02430
02431 /**
02432   * @brief  Check if PLL output mapped on 48MHz domain clock is enabled
02433   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_48M
02434   * @retval State of bit (1 or 0).
02435   */
02436 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
02437 {
02438   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
02439 }
02440
02441 /**
02442   * @brief  Enable PLL output mapped on SYSCLK domain
02443   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
02444   * @retval None
02445   */
02446 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
02447 {
02448   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
02449 }
02450
02451 /**
02452   * @brief  Disable PLL output mapped on SYSCLK domain
02453   * @note Cannot be disabled if the PLL clock is used as the system
02454   *       clock
02455   * @note In order to save power, when the PLLCLK  of the PLL is
02456   *       not used, Main PLL  should be 0
02457   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
02458   * @retval None
02459   */
02460 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
02461 {
02462   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
02463 }
02464
02465 /**
02466   * @brief  Check if PLL output mapped on SYSCLK domain clock is enabled
02467   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_IsEnabledDomain_SYS
02468   * @retval State of bit (1 or 0).
02469   */
02470 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
02471 {
02472   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
02473 }
02474
02475 /**
02476   * @}
02477   */
02478
02479 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
02480   * @{
02481   */
02482
02483 /**
02484   * @brief  Clear LSI ready interrupt flag
02485   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
02486   * @retval None
02487   */
02488 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
02489 {
02490   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
02491 }
02492
02493 /**
02494   * @brief  Clear LSE ready interrupt flag
02495   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
02496   * @retval None
02497   */
02498 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
02499 {
02500   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
02501 }
02502
02503 /**
02504   * @brief  Clear HSI ready interrupt flag
02505   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
02506   * @retval None
02507   */
02508 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
02509 {
02510   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
02511 }
02512
02513 /**
02514   * @brief  Clear HSE ready interrupt flag
02515   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
02516   * @retval None
02517   */
02518 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
02519 {
02520   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
02521 }
02522
02523 /**
02524   * @brief  Clear PLL ready interrupt flag
02525   * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
02529 {
02530   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
02531 }
02532
02533 /**
02534   * @brief  Clear HSI48 ready interrupt flag
02535   * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
02536   * @retval None
02537   */
02538 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
02539 {
02540   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
02541 }
02542
02543 /**
02544   * @brief  Clear Clock security system interrupt flag
02545   * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
02546   * @retval None
02547   */
02548 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
02549 {
02550   SET_BIT(RCC->CICR, RCC_CICR_CSSC);
02551 }
02552
02553 /**
02554   * @brief  Clear LSE Clock security system interrupt flag
02555   * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
02556   * @retval None
02557   */
02558 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
02559 {
02560   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
02561 }
02562
02563 /**
02564   * @brief  Check if LSI ready interrupt occurred or not
02565   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
02566   * @retval State of bit (1 or 0).
02567   */
02568 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
02569 {
02570   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
02571 }
02572
02573 /**
02574   * @brief  Check if LSE ready interrupt occurred or not
02575   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
02576   * @retval State of bit (1 or 0).
02577   */
02578 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
02579 {
02580   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
02581 }
02582
02583 /**
02584   * @brief  Check if HSI ready interrupt occurred or not
02585   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
02586   * @retval State of bit (1 or 0).
02587   */
02588 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
02589 {
02590   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
02591 }
02592
02593 /**
02594   * @brief  Check if HSE ready interrupt occurred or not
02595   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
02596   * @retval State of bit (1 or 0).
02597   */
02598 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
02599 {
02600   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
02601 }
02602
02603 /**
02604   * @brief  Check if PLL ready interrupt occurred or not
02605   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
02606   * @retval State of bit (1 or 0).
02607   */
02608 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
02609 {
02610   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
02611 }
02612
02613 /**
02614   * @brief  Check if HSI48 ready interrupt occurred or not
02615   * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
02616   * @retval State of bit (1 or 0).
02617   */
02618 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
02619 {
02620   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
02621 }
02622
02623 /**
02624   * @brief  Check if Clock security system interrupt occurred or not
02625   * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
02626   * @retval State of bit (1 or 0).
02627   */
02628 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
02629 {
02630   return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
02631 }
02632
02633 /**
02634   * @brief  Check if LSE Clock security system interrupt occurred or not
02635   * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
02636   * @retval State of bit (1 or 0).
02637   */
02638 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
02639 {
02640   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
02641 }
02642
02643 /**
02644   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
02645   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
02646   * @retval State of bit (1 or 0).
02647   */
02648 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
02649 {
02650   return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
02651 }
02652
02653 /**
02654   * @brief  Check if RCC flag Low Power reset is set or not.
02655   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
02656   * @retval State of bit (1 or 0).
02657   */
02658 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
02659 {
02660   return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
02661 }
02662
02663 /**
02664   * @brief  Check if RCC flag Option byte reset is set or not.
02665   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
02666   * @retval State of bit (1 or 0).
02667   */
02668 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
02669 {
02670   return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
02671 }
02672
02673 /**
02674   * @brief  Check if RCC flag Pin reset is set or not.
02675   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
02676   * @retval State of bit (1 or 0).
02677   */
02678 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
02679 {
02680   return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
02681 }
02682
02683 /**
02684   * @brief  Check if RCC flag Software reset is set or not.
02685   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
02686   * @retval State of bit (1 or 0).
02687   */
02688 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
02689 {
02690   return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
02691 }
02692
02693 /**
02694   * @brief  Check if RCC flag Window Watchdog reset is set or not.
02695   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
02696   * @retval State of bit (1 or 0).
02697   */
02698 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
02699 {
02700   return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
02701 }
02702
02703 /**
02704   * @brief  Check if RCC flag BOR reset is set or not.
02705   * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
02706   * @retval State of bit (1 or 0).
02707   */
02708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
02709 {
02710   return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
02711 }
02712
02713 /**
02714   * @brief  Set RMVF bit to clear the reset flags.
02715   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
02716   * @retval None
02717   */
02718 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
02719 {
02720   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
02721 }
02722
02723 /**
02724   * @}
02725   */
02726
02727 /** @defgroup RCC_LL_EF_IT_Management IT Management
02728   * @{
02729   */
02730
02731 /**
02732   * @brief  Enable LSI ready interrupt
02733   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
02734   * @retval None
02735   */
02736 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
02737 {
02738   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
02739 }
02740
02741 /**
02742   * @brief  Enable LSE ready interrupt
02743   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
02744   * @retval None
02745   */
02746 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
02747 {
02748   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
02749 }
02750
02751 /**
02752   * @brief  Enable HSI ready interrupt
02753   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
02754   * @retval None
02755   */
02756 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
02757 {
02758   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
02759 }
02760
02761 /**
02762   * @brief  Enable HSE ready interrupt
02763   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
02764   * @retval None
02765   */
02766 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
02767 {
02768   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
02769 }
02770
02771 /**
02772   * @brief  Enable PLL ready interrupt
02773   * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
02774   * @retval None
02775   */
02776 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
02777 {
02778   SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
02779 }
02780
02781 /**
02782   * @brief  Enable HSI48 ready interrupt
02783   * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
02784   * @retval None
02785   */
02786 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
02787 {
02788   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
02789 }
02790
02791 /**
02792   * @brief  Enable LSE clock security system interrupt
02793   * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
02794   * @retval None
02795   */
02796 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
02797 {
02798   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
02799 }
02800
02801 /**
02802   * @brief  Disable LSI ready interrupt
02803   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
02804   * @retval None
02805   */
02806 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
02807 {
02808   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
02809 }
02810
02811 /**
02812   * @brief  Disable LSE ready interrupt
02813   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
02814   * @retval None
02815   */
02816 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
02817 {
02818   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
02819 }
02820
02821 /**
02822   * @brief  Disable HSI ready interrupt
02823   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
02824   * @retval None
02825   */
02826 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
02827 {
02828   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
02829 }
02830
02831 /**
02832   * @brief  Disable HSE ready interrupt
02833   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
02834   * @retval None
02835   */
02836 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
02837 {
02838   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
02839 }
02840
02841 /**
02842   * @brief  Disable PLL ready interrupt
02843   * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
02847 {
02848   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
02849 }
02850
02851 /**
02852   * @brief  Disable HSI48 ready interrupt
02853   * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
02854   * @retval None
02855   */
02856 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
02857 {
02858   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
02859 }
02860
02861 /**
02862   * @brief  Disable LSE clock security system interrupt
02863   * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
02864   * @retval None
02865   */
02866 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
02867 {
02868   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
02869 }
02870
02871 /**
02872   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
02873   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
02874   * @retval State of bit (1 or 0).
02875   */
02876 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
02877 {
02878   return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
02879 }
02880
02881 /**
02882   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
02883   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
02884   * @retval State of bit (1 or 0).
02885   */
02886 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
02887 {
02888   return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
02889 }
02890
02891 /**
02892   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
02893   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
02894   * @retval State of bit (1 or 0).
02895   */
02896 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
02897 {
02898   return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
02899 }
02900
02901 /**
02902   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
02903   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
02904   * @retval State of bit (1 or 0).
02905   */
02906 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
02907 {
02908   return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
02909 }
02910
02911 /**
02912   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
02913   * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
02914   * @retval State of bit (1 or 0).
02915   */
02916 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
02917 {
02918   return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
02919 }
02920
02921 /**
02922   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
02923   * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
02924   * @retval State of bit (1 or 0).
02925   */
02926 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
02927 {
02928   return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
02929 }
02930
02931 /**
02932   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
02933   * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
02934   * @retval State of bit (1 or 0).
02935   */
02936 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
02937 {
02938   return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
02939 }
02940
02941 /**
02942   * @}
02943   */
02944
02945 #if defined(USE_FULL_LL_DRIVER)
02946 /** @defgroup RCC_LL_EF_Init De-initialization function
02947   * @{
02948   */
02949 ErrorStatus LL_RCC_DeInit(void);
02950 /**
02951   * @}
02952   */
02953
02954 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
02955   * @{
02956   */
02957 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
02958 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
02959 #if defined(UART4)
02960 uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
02961 #endif /* UART4 */
02962 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
02963 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
02964 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
02965 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
02966 uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
02967 #if defined(FDCAN1)
02968 uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
02969 #endif /* FDCAN1 */
02970 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
02971 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
02972 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
02973 #if defined(QUADSPI)
02974 uint32_t    LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
02975 #endif /* QUADSPI */
02976 /**
02977   * @}
02978   */
02979 #endif /* USE_FULL_LL_DRIVER */
02980
02981 /**
02982   * @}
02983   */
02984
02985 /**
02986   * @}
02987   */
02988
02989 /**
02990   * @}
02991   */
02992
02993 #ifdef __cplusplus
02994 }
02995 #endif
02996
02997 #endif /* STM32G4xx_LL_RCC_H */
02998
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rng.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_rng.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_rng.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @addtogroup RNG_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @defgroup RNG_LL_Private_Macros RNG Private Macros
00045   * @{
00046   */
00047 #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
00048                                  ((__MODE__) == LL_RNG_CED_DISABLE))
00049
00050 /**
00051   * @}
00052   */
00053 /* Private function prototypes -----------------------------------------------*/
00054
00055 /* Exported functions --------------------------------------------------------*/
00056 /** @addtogroup RNG_LL_Exported_Functions
00057   * @{
00058   */
00059
00060 /** @addtogroup RNG_LL_EF_Init
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  De-initialize RNG registers (Registers restored to their default values).
00066   * @param  RNGx RNG Instance
00067   * @retval An ErrorStatus enumeration value:
00068   *          - SUCCESS: RNG registers are de-initialized
00069   *          - ERROR: not applicable
00070   */
00071 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
00072 {
00073   ErrorStatus status = SUCCESS;
00074
00075   /* Check the parameters */
00076   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00077   if (RNGx == RNG)
00078   {
00079     /* Enable RNG reset state */
00080     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
00081
00082     /* Release RNG from reset state */
00083     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
00084   }
00085   else
00086   {
00087     status = ERROR;
00088   }
00089
00090   return status;
00091 }
00092
00093 /**
00094   * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
00095   * @param  RNGx RNG Instance
00096   * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
00097   *         that contains the configuration information for the specified RNG peripheral.
00098   * @retval An ErrorStatus enumeration value:
00099   *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
00100   *          - ERROR: not applicable
00101   */
00102 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
00103 {
00104   /* Check the parameters */
00105   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00106   assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
00107
00108   /* Clock Error Detection configuration */
00109   MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
00110
00111   return (SUCCESS);
00112 }
00113
00114 /**
00115   * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
00116   * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
00117   *                       whose fields will be set to default values.
00118   * @retval None
00119   */
00120 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
00121 {
00122   /* Set RNG_InitStruct fields to default values */
00123   RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
00124
00125 }
00126 /**
00127   * @}
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 #endif /* RNG */
00139
00140 /**
00141   * @}
00142   */
00143
00144 #endif /* USE_FULL_LL_DRIVER */
00145
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rng.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_rng.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_RNG_H
00021 #define STM32G4xx_LL_RNG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @defgroup RNG_LL RNG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private defines -----------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 #if defined(USE_FULL_LL_DRIVER)
00048 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
00049   * @{
00050   */
00051
00052
00053 /**
00054   * @brief LL RNG Init Structure Definition
00055   */
00056 typedef struct
00057 {
00058   uint32_t         ClockErrorDetection; /*!< Clock error detection.
00059                                       This parameter can be one value of @ref RNG_LL_CED.
00060                                       This parameter can be modified using unitary
00061                                       functions @ref LL_RNG_EnableClkErrorDetect(). */
00062 } LL_RNG_InitTypeDef;
00063
00064 /**
00065   * @}
00066   */
00067 #endif /* USE_FULL_LL_DRIVER */
00068 /* Exported constants --------------------------------------------------------*/
00069 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
00070   * @{
00071   */
00072
00073 /** @defgroup RNG_LL_CED Clock Error Detection
00074   * @{
00075   */
00076 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
00077 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
00083   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
00084   * @{
00085   */
00086 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
00087 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
00088 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
00089 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
00090 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup RNG_LL_EC_IT IT Defines
00096   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
00097   * @{
00098   */
00099 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
00100 /**
00101   * @}
00102   */
00103
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported macro ------------------------------------------------------------*/
00109 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
00110   * @{
00111   */
00112
00113 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Write a value in RNG register
00119   * @param  __INSTANCE__ RNG Instance
00120   * @param  __REG__ Register to be written
00121   * @param  __VALUE__ Value to be written in the register
00122   * @retval None
00123   */
00124 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00125
00126 /**
00127   * @brief  Read a value in RNG register
00128   * @param  __INSTANCE__ RNG Instance
00129   * @param  __REG__ Register to be read
00130   * @retval Register value
00131   */
00132 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
00144   * @{
00145   */
00146 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
00147   * @{
00148   */
00149
00150 /**
00151   * @brief  Enable Random Number Generation
00152   * @rmtoll CR           RNGEN         LL_RNG_Enable
00153   * @param  RNGx RNG Instance
00154   * @retval None
00155   */
00156 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
00157 {
00158   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
00159 }
00160
00161 /**
00162   * @brief  Disable Random Number Generation
00163   * @rmtoll CR           RNGEN         LL_RNG_Disable
00164   * @param  RNGx RNG Instance
00165   * @retval None
00166   */
00167 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
00168 {
00169   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
00170 }
00171
00172 /**
00173   * @brief  Check if Random Number Generator is enabled
00174   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
00175   * @param  RNGx RNG Instance
00176   * @retval State of bit (1 or 0).
00177   */
00178 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
00179 {
00180   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
00181 }
00182
00183 /**
00184   * @brief  Enable Clock Error Detection
00185   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
00186   * @param  RNGx RNG Instance
00187   * @retval None
00188   */
00189 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
00190 {
00191   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
00192 }
00193
00194 /**
00195   * @brief  Disable RNG Clock Error Detection
00196   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
00197   * @param  RNGx RNG Instance
00198   * @retval None
00199   */
00200 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
00201 {
00202   SET_BIT(RNGx->CR, RNG_CR_CED);
00203 }
00204
00205 /**
00206   * @brief  Check if RNG Clock Error Detection is enabled
00207   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
00208   * @param  RNGx RNG Instance
00209   * @retval State of bit (1 or 0).
00210   */
00211 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
00212 {
00213   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
00214 }
00215
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
00221   * @{
00222   */
00223
00224 /**
00225   * @brief  Indicate if the RNG Data ready Flag is set or not
00226   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
00227   * @param  RNGx RNG Instance
00228   * @retval State of bit (1 or 0).
00229   */
00230 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
00231 {
00232   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
00233 }
00234
00235 /**
00236   * @brief  Indicate if the Clock Error Current Status Flag is set or not
00237   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
00238   * @param  RNGx RNG Instance
00239   * @retval State of bit (1 or 0).
00240   */
00241 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
00242 {
00243   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
00244 }
00245
00246 /**
00247   * @brief  Indicate if the Seed Error Current Status Flag is set or not
00248   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
00249   * @param  RNGx RNG Instance
00250   * @retval State of bit (1 or 0).
00251   */
00252 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
00253 {
00254   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
00255 }
00256
00257 /**
00258   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
00259   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
00260   * @param  RNGx RNG Instance
00261   * @retval State of bit (1 or 0).
00262   */
00263 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
00264 {
00265   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
00266 }
00267
00268 /**
00269   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
00270   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
00271   * @param  RNGx RNG Instance
00272   * @retval State of bit (1 or 0).
00273   */
00274 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
00275 {
00276   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
00277 }
00278
00279 /**
00280   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
00281   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
00282   * @param  RNGx RNG Instance
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
00286 {
00287   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
00288 }
00289
00290 /**
00291   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
00292   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
00293   * @param  RNGx RNG Instance
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
00297 {
00298   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
00299 }
00300
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup RNG_LL_EF_IT_Management IT Management
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Enable Random Number Generator Interrupt
00311   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00312   * @rmtoll CR           IE            LL_RNG_EnableIT
00313   * @param  RNGx RNG Instance
00314   * @retval None
00315   */
00316 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
00317 {
00318   SET_BIT(RNGx->CR, RNG_CR_IE);
00319 }
00320
00321 /**
00322   * @brief  Disable Random Number Generator Interrupt
00323   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00324   * @rmtoll CR           IE            LL_RNG_DisableIT
00325   * @param  RNGx RNG Instance
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
00329 {
00330   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
00331 }
00332
00333 /**
00334   * @brief  Check if Random Number Generator Interrupt is enabled
00335   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00336   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
00337   * @param  RNGx RNG Instance
00338   * @retval State of bit (1 or 0).
00339   */
00340 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
00341 {
00342   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
00343 }
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RNG_LL_EF_Data_Management Data Management
00350   * @{
00351   */
00352
00353 /**
00354   * @brief  Return32-bit Random Number value
00355   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
00356   * @param  RNGx RNG Instance
00357   * @retval Generated 32-bit random value
00358   */
00359 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
00360 {
00361   return (uint32_t)(READ_REG(RNGx->DR));
00362 }
00363
00364 /**
00365   * @}
00366   */
00367
00368 #if defined(USE_FULL_LL_DRIVER)
00369 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
00370   * @{
00371   */
00372 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
00373 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
00374 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
00375
00376 /**
00377   * @}
00378   */
00379 #endif /* USE_FULL_LL_DRIVER */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 #endif /* RNG */
00390
00391 /**
00392   * @}
00393   */
00394
00395 #ifdef __cplusplus
00396 }
00397 #endif
00398
00399 #endif /* __STM32G4xx_LL_RNG_H */
00400
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rtc.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_rtc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_rtc.h"
00022 #include "stm32g4xx_ll_cortex.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else  /* USE_FULL_ASSERT */
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G4xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined(RTC)
00034
00035 /** @addtogroup RTC_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /** @addtogroup RTC_LL_Private_Constants
00043   * @{
00044   */
00045 /* Default values used for prescaler */
00046 #define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
00047 #define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
00048
00049 /* Values used for timeout */
00050 #define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
00051 #define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057 /** @addtogroup RTC_LL_Private_Macros
00058   * @{
00059   */
00060 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00061                                          || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00062
00063 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
00064
00065 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
00066
00067 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00068                                      || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00069
00070 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00071                                           || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00072
00073 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00074 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00075 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00076 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00077
00078 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00079                                       || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00080                                       || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00081                                       || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00082                                       || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00083                                       || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00084                                       || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00085
00086 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
00087
00088 #define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
00089
00090 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00091
00092 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00093                                         || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00094                                         || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00095                                         || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00096                                         || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00097                                         || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00098
00099 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00100                                         || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00101                                         || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00102                                         || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00103                                         || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00104                                         || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00105
00106
00107 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00108                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00109
00110 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00111                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00112 /**
00113   * @}
00114   */
00115 /* Private function prototypes -----------------------------------------------*/
00116 /* Exported functions --------------------------------------------------------*/
00117 /** @addtogroup RTC_LL_Exported_Functions
00118   * @{
00119   */
00120
00121 /** @addtogroup RTC_LL_EF_Init
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  De-Initializes the RTC registers to their default reset values.
00127   * @note   This function does not reset the RTC Clock source and RTC Backup Data
00128   *         registers.
00129   * @param  RTCx RTC Instance
00130   * @retval An ErrorStatus enumeration value:
00131   *          - SUCCESS: RTC registers are de-initialized
00132   *          - ERROR: RTC registers are not de-initialized
00133   */
00134 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00135 {
00136   ErrorStatus status = ERROR;
00137
00138   /* Check the parameter */
00139   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00140   assert_param(IS_TAMP_ALL_INSTANCE(TAMP));
00141
00142   /* Disable the write protection for RTC registers */
00143   LL_RTC_DisableWriteProtection(RTCx);
00144
00145   /* Set Initialization mode */
00146   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00147   {
00148     /* Reset TR, DR and CR registers */
00149     WRITE_REG(RTCx->TR,       0x00000000U);
00150 #if defined(RTC_WAKEUP_SUPPORT)
00151     WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
00152 #endif /* RTC_WAKEUP_SUPPORT */
00153     WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00154     /* Reset All CR bits except CR[2:0] */
00155 #if defined(RTC_WAKEUP_SUPPORT)
00156     WRITE_REG(RTCx->CR, (READ_REG(RTCx->CR) & RTC_CR_WUCKSEL));
00157 #else
00158     WRITE_REG(RTCx->CR, 0x00000000U);
00159 #endif /* RTC_WAKEUP_SUPPORT */
00160     WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00161     WRITE_REG(RTCx->ALRMAR,   0x00000000U);
00162     WRITE_REG(RTCx->ALRMBR,   0x00000000U);
00163     WRITE_REG(RTCx->SHIFTR,   0x00000000U);
00164     WRITE_REG(RTCx->CALR,     0x00000000U);
00165     WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
00166     WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
00167
00168     /* Exit Initialization mode */
00169     LL_RTC_DisableInitMode(RTCx);
00170
00171     /* Wait till the RTC RSF flag is set */
00172     status = LL_RTC_WaitForSynchro(RTCx);
00173   }
00174
00175   /* Enable the write protection for RTC registers */
00176   LL_RTC_EnableWriteProtection(RTCx);
00177
00178   /* DeInitialization of the TAMP */
00179   /* Reset TAMP CR1 and CR2 registers */
00180   WRITE_REG(TAMP->CR1,      0xFFFF0000U);
00181   WRITE_REG(TAMP->CR2,     0x00000000U);
00182 #if defined (RTC_OTHER_SUPPORT)
00183   WRITE_REG(TAMP->CR3,     0x00000000U);
00184   WRITE_REG(TAMP->SMCR,     0x00000000U);
00185   WRITE_REG(TAMP->PRIVCR,   0x00000000U);
00186 #endif /* RTC_OTHER_SUPPORT */
00187   WRITE_REG(TAMP->FLTCR,    0x00000000U);
00188 #if defined (RTC_ACTIVE_TAMPER_SUPPORT)
00189   WRITE_REG(TAMP->ATCR1,    0x00000000U);
00190   WRITE_REG(TAMP->ATCR2,    0x00000000U);
00191 #endif /* RTC_ACTIVE_TAMPER_SUPPORT */
00192   WRITE_REG(TAMP->IER,      0x00000000U);
00193   WRITE_REG(TAMP->SCR,      0xFFFFFFFFU);
00194 #if defined (RTC_OPTION_REG_SUPPORT)
00195   WRITE_REG(TAMP->OR,       0x00000000U);
00196 #endif /* RTC_OPTION_REG_SUPPORT */
00197
00198   return status;
00199 }
00200
00201 /**
00202   * @brief  Initializes the RTC registers according to the specified parameters
00203   *         in RTC_InitStruct.
00204   * @param  RTCx RTC Instance
00205   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00206   *         the configuration information for the RTC peripheral.
00207   * @note   The RTC Prescaler register is write protected and can be written in
00208   *         initialization mode only.
00209   * @retval An ErrorStatus enumeration value:
00210   *          - SUCCESS: RTC registers are initialized
00211   *          - ERROR: RTC registers are not initialized
00212   */
00213 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00214 {
00215   ErrorStatus status = ERROR;
00216
00217   /* Check the parameters */
00218   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00219   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00220   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00221   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00222
00223   /* Disable the write protection for RTC registers */
00224   LL_RTC_DisableWriteProtection(RTCx);
00225
00226   /* Set Initialization mode */
00227   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00228   {
00229     /* Set Hour Format */
00230     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00231
00232     /* Configure Synchronous prescaler factor */
00233     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00234     /* Configure Asynchronous prescaler factor */
00235     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00236
00237     /* Exit Initialization mode */
00238     LL_RTC_DisableInitMode(RTCx);
00239
00240     status = SUCCESS;
00241   }
00242   /* Enable the write protection for RTC registers */
00243   LL_RTC_EnableWriteProtection(RTCx);
00244
00245   return status;
00246 }
00247
00248 /**
00249   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00250   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00251   * @retval None
00252   */
00253 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00254 {
00255   /* Set RTC_InitStruct fields to default values */
00256   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00257   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00258   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00259 }
00260
00261 /**
00262   * @brief  Set the RTC current time.
00263   * @param  RTCx RTC Instance
00264   * @param  RTC_Format This parameter can be one of the following values:
00265   *         @arg @ref LL_RTC_FORMAT_BIN
00266   *         @arg @ref LL_RTC_FORMAT_BCD
00267   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00268   *                        the time configuration information for the RTC.
00269   * @retval An ErrorStatus enumeration value:
00270   *          - SUCCESS: RTC Time register is configured
00271   *          - ERROR: RTC Time register is not configured
00272   */
00273 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00274 {
00275   ErrorStatus status = ERROR;
00276
00277   /* Check the parameters */
00278   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00279   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00280
00281   if (RTC_Format == LL_RTC_FORMAT_BIN)
00282   {
00283     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00284     {
00285       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00286       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00287     }
00288     else
00289     {
00290       RTC_TimeStruct->TimeFormat = 0x00U;
00291       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00292     }
00293     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00294     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00295   }
00296   else
00297   {
00298     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00299     {
00300       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00301       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00302     }
00303     else
00304     {
00305       RTC_TimeStruct->TimeFormat = 0x00U;
00306       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00307     }
00308     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00309     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00310   }
00311
00312   /* Disable the write protection for RTC registers */
00313   LL_RTC_DisableWriteProtection(RTCx);
00314
00315   /* Set Initialization mode */
00316   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00317   {
00318     /* Check the input parameters format */
00319     if (RTC_Format != LL_RTC_FORMAT_BIN)
00320     {
00321       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00322                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00323     }
00324     else
00325     {
00326       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00327                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00328                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00329     }
00330
00331     /* Exit Initialization mode */
00332     LL_RTC_DisableInitMode(RTCx);
00333
00334     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00335     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00336     {
00337       status = LL_RTC_WaitForSynchro(RTCx);
00338     }
00339     else
00340     {
00341       status = SUCCESS;
00342     }
00343   }
00344   /* Enable the write protection for RTC registers */
00345   LL_RTC_EnableWriteProtection(RTCx);
00346
00347   return status;
00348 }
00349
00350 /**
00351   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00352   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00353   * @retval None
00354   */
00355 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00356 {
00357   /* Time = 00h:00min:00sec */
00358   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00359   RTC_TimeStruct->Hours      = 0U;
00360   RTC_TimeStruct->Minutes    = 0U;
00361   RTC_TimeStruct->Seconds    = 0U;
00362 }
00363
00364 /**
00365   * @brief  Set the RTC current date.
00366   * @param  RTCx RTC Instance
00367   * @param  RTC_Format This parameter can be one of the following values:
00368   *         @arg @ref LL_RTC_FORMAT_BIN
00369   *         @arg @ref LL_RTC_FORMAT_BCD
00370   * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
00371   *                         the date configuration information for the RTC.
00372   * @retval An ErrorStatus enumeration value:
00373   *          - SUCCESS: RTC Day register is configured
00374   *          - ERROR: RTC Day register is not configured
00375   */
00376 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00377 {
00378   ErrorStatus status = ERROR;
00379
00380   /* Check the parameters */
00381   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00382   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00383
00384   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00385   {
00386     RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
00387   }
00388   if (RTC_Format == LL_RTC_FORMAT_BIN)
00389   {
00390     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00391     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00392     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00393   }
00394   else
00395   {
00396     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00397     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00398     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00399   }
00400   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00401
00402   /* Disable the write protection for RTC registers */
00403   LL_RTC_DisableWriteProtection(RTCx);
00404
00405   /* Set Initialization mode */
00406   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00407   {
00408     /* Check the input parameters format */
00409     if (RTC_Format != LL_RTC_FORMAT_BIN)
00410     {
00411       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00412     }
00413     else
00414     {
00415       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00416                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00417     }
00418
00419     /* Exit Initialization mode */
00420     LL_RTC_DisableInitMode(RTCx);
00421
00422     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00423     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00424     {
00425       status = LL_RTC_WaitForSynchro(RTCx);
00426     }
00427     else
00428     {
00429       status = SUCCESS;
00430     }
00431   }
00432   /* Enable the write protection for RTC registers */
00433   LL_RTC_EnableWriteProtection(RTCx);
00434
00435   return status;
00436 }
00437
00438 /**
00439   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00440   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00441   * @retval None
00442   */
00443 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00444 {
00445   /* Monday, January 01 xx00 */
00446   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00447   RTC_DateStruct->Day     = 1U;
00448   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00449   RTC_DateStruct->Year    = 0U;
00450 }
00451
00452 /**
00453   * @brief  Set the RTC Alarm A.
00454   * @note   The Alarm register can only be written when the corresponding Alarm
00455   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00456   * @param  RTCx RTC Instance
00457   * @param  RTC_Format This parameter can be one of the following values:
00458   *         @arg @ref LL_RTC_FORMAT_BIN
00459   *         @arg @ref LL_RTC_FORMAT_BCD
00460   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00461   *                         contains the alarm configuration parameters.
00462   * @retval An ErrorStatus enumeration value:
00463   *          - SUCCESS: ALARMA registers are configured
00464   *          - ERROR: ALARMA registers are not configured
00465   */
00466 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00467 {
00468   /* Check the parameters */
00469   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00470   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00471   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00472   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00473
00474   if (RTC_Format == LL_RTC_FORMAT_BIN)
00475   {
00476     /* initialize the AlarmTime for Binary format */
00477     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00478     {
00479       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00480       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00481     }
00482     else
00483     {
00484       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00485       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00486     }
00487     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00488     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00489
00490     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00491     {
00492       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00493     }
00494     else
00495     {
00496       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00497     }
00498   }
00499   else
00500   {
00501     /* initialize the AlarmTime for BCD format */
00502     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00503     {
00504       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00505       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00506     }
00507     else
00508     {
00509       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00510       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00511     }
00512
00513     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00514     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00515
00516     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00517     {
00518       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00519     }
00520     else
00521     {
00522       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00523     }
00524   }
00525
00526   /* Disable the write protection for RTC registers */
00527   LL_RTC_DisableWriteProtection(RTCx);
00528
00529   /* Select weekday selection */
00530   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00531   {
00532     /* Set the date for ALARM */
00533     LL_RTC_ALMA_DisableWeekday(RTCx);
00534     if (RTC_Format != LL_RTC_FORMAT_BIN)
00535     {
00536       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00537     }
00538     else
00539     {
00540       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00541     }
00542   }
00543   else
00544   {
00545     /* Set the week day for ALARM */
00546     LL_RTC_ALMA_EnableWeekday(RTCx);
00547     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00548   }
00549
00550   /* Configure the Alarm register */
00551   if (RTC_Format != LL_RTC_FORMAT_BIN)
00552   {
00553     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00554                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00555   }
00556   else
00557   {
00558     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00559                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00560                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00561                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00562   }
00563   /* Set ALARM mask */
00564   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00565
00566   /* Enable the write protection for RTC registers */
00567   LL_RTC_EnableWriteProtection(RTCx);
00568
00569   return SUCCESS;
00570 }
00571
00572 /**
00573   * @brief  Set the RTC Alarm B.
00574   * @note   The Alarm register can only be written when the corresponding Alarm
00575   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00576   * @param  RTCx RTC Instance
00577   * @param  RTC_Format This parameter can be one of the following values:
00578   *         @arg @ref LL_RTC_FORMAT_BIN
00579   *         @arg @ref LL_RTC_FORMAT_BCD
00580   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00581   *                         contains the alarm configuration parameters.
00582   * @retval An ErrorStatus enumeration value:
00583   *          - SUCCESS: ALARMB registers are configured
00584   *          - ERROR: ALARMB registers are not configured
00585   */
00586 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00587 {
00588   /* Check the parameters */
00589   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00590   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00591   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00592   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00593
00594   if (RTC_Format == LL_RTC_FORMAT_BIN)
00595   {
00596     /* initialize the AlarmTime for Binary format */
00597     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00598     {
00599       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00600       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00601     }
00602     else
00603     {
00604       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00605       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00606     }
00607     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00608     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00609
00610     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00611     {
00612       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00613     }
00614     else
00615     {
00616       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00617     }
00618   }
00619   else
00620   {
00621     /* initialize the AlarmTime for BCD format */
00622     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00623     {
00624       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00625       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00626     }
00627     else
00628     {
00629       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00630       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00631     }
00632
00633     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00634     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00635
00636     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00637     {
00638       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00639     }
00640     else
00641     {
00642       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00643     }
00644   }
00645
00646   /* Disable the write protection for RTC registers */
00647   LL_RTC_DisableWriteProtection(RTCx);
00648
00649   /* Select weekday selection */
00650   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00651   {
00652     /* Set the date for ALARM */
00653     LL_RTC_ALMB_DisableWeekday(RTCx);
00654     if (RTC_Format != LL_RTC_FORMAT_BIN)
00655     {
00656       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00657     }
00658     else
00659     {
00660       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00661     }
00662   }
00663   else
00664   {
00665     /* Set the week day for ALARM */
00666     LL_RTC_ALMB_EnableWeekday(RTCx);
00667     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00668   }
00669
00670   /* Configure the Alarm register */
00671   if (RTC_Format != LL_RTC_FORMAT_BIN)
00672   {
00673     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00674                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00675   }
00676   else
00677   {
00678     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00679                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00680                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00681                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00682   }
00683   /* Set ALARM mask */
00684   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00685
00686   /* Enable the write protection for RTC registers */
00687   LL_RTC_EnableWriteProtection(RTCx);
00688
00689   return SUCCESS;
00690 }
00691
00692 /**
00693   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00694   *         Day = 1st day of the month/Mask = all fields are masked).
00695   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00696   * @retval None
00697   */
00698 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00699 {
00700   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00701   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00702   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00703   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00704   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00705
00706   /* Alarm Day Settings : Day = 1st day of the month */
00707   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00708   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00709
00710   /* Alarm Masks Settings : Mask =  all fields are not masked */
00711   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00712 }
00713
00714 /**
00715   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMB field to default value (Time = 00h:00mn:00sec /
00716   *         Day = 1st day of the month/Mask = all fields are masked).
00717   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00718   * @retval None
00719   */
00720 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00721 {
00722   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00723   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00724   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00725   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00726   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00727
00728   /* Alarm Day Settings : Day = 1st day of the month */
00729   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00730   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00731
00732   /* Alarm Masks Settings : Mask =  all fields are not masked */
00733   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00734 }
00735
00736 /**
00737   * @brief  Enters the RTC Initialization mode.
00738   * @note   The RTC Initialization mode is write protected, use the
00739   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00740   * @param  RTCx RTC Instance
00741   * @retval An ErrorStatus enumeration value:
00742   *          - SUCCESS: RTC is in Init mode
00743   *          - ERROR: RTC is not in Init mode
00744   */
00745 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00746 {
00747   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00748   ErrorStatus status = SUCCESS;
00749   uint32_t tmp;
00750
00751   /* Check the parameter */
00752   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00753
00754   /* Check if the Initialization mode is set */
00755   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00756   {
00757     /* Set the Initialization mode */
00758     LL_RTC_EnableInitMode(RTCx);
00759
00760     /* Wait till RTC is in INIT state and if Time out is reached exit */
00761     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00762     while ((timeout != 0U) && (tmp != 1U))
00763     {
00764       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00765       {
00766         timeout --;
00767       }
00768       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00769       if (timeout == 0U)
00770       {
00771         status = ERROR;
00772       }
00773     }
00774   }
00775   return status;
00776 }
00777
00778 /**
00779   * @brief  Exit the RTC Initialization mode.
00780   * @note   When the initialization sequence is complete, the calendar restarts
00781   *         counting after 4 RTCCLK cycles.
00782   * @note   The RTC Initialization mode is write protected, use the
00783   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00784   * @param  RTCx RTC Instance
00785   * @retval An ErrorStatus enumeration value:
00786   *          - SUCCESS: RTC exited from in Init mode
00787   *          - ERROR: Not applicable
00788   */
00789 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00790 {
00791   /* Check the parameter */
00792   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00793
00794   /* Disable initialization mode */
00795   LL_RTC_DisableInitMode(RTCx);
00796
00797   return SUCCESS;
00798 }
00799
00800 /**
00801   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00802   *         synchronized with RTC APB clock.
00803   * @note   The RTC Resynchronization mode is write protected, use the
00804   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00805   * @note   To read the calendar through the shadow registers after Calendar
00806   *         initialization, calendar update or after wakeup from low power modes
00807   *         the software must first clear the RSF flag.
00808   *         The software must then wait until it is set again before reading
00809   *         the calendar, which means that the calendar registers have been
00810   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00811   * @param  RTCx RTC Instance
00812   * @retval An ErrorStatus enumeration value:
00813   *          - SUCCESS: RTC registers are synchronised
00814   *          - ERROR: RTC registers are not synchronised
00815   */
00816 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00817 {
00818   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00819   ErrorStatus status = SUCCESS;
00820   uint32_t tmp;
00821
00822   /* Check the parameter */
00823   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00824
00825   /* Clear RSF flag */
00826   LL_RTC_ClearFlag_RS(RTCx);
00827
00828   /* Wait the registers to be synchronised */
00829   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00830   while ((timeout != 0U) && (tmp != 0U))
00831   {
00832     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00833     {
00834       timeout--;
00835     }
00836     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00837     if (timeout == 0U)
00838     {
00839       status = ERROR;
00840     }
00841   }
00842
00843   if (status != ERROR)
00844   {
00845     timeout = RTC_SYNCHRO_TIMEOUT;
00846     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00847     while ((timeout != 0U) && (tmp != 1U))
00848     {
00849       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00850       {
00851         timeout--;
00852       }
00853       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00854       if (timeout == 0U)
00855       {
00856         status = ERROR;
00857       }
00858     }
00859   }
00860
00861   return (status);
00862 }
00863
00864 /**
00865   * @}
00866   */
00867
00868 /**
00869   * @}
00870   */
00871
00872 /**
00873   * @}
00874   */
00875
00876 #endif /* defined(RTC) */
00877
00878 /**
00879   * @}
00880   */
00881
00882 #endif /* USE_FULL_LL_DRIVER */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_rtc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_rtc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_RTC_H
00021 #define STM32G4xx_LL_RTC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(RTC)
00035
00036 /** @defgroup RTC_LL RTC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00044   * @{
00045   */
00046 /* Masks Definition */
00047 #define RTC_LL_INIT_MASK              0xFFFFFFFFU
00048 #define RTC_LL_RSF_MASK               0xFFFFFF5FU
00049
00050 /* Write protection defines */
00051 #define RTC_WRITE_PROTECTION_DISABLE  (uint8_t)0xFF
00052 #define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
00053 #define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
00054
00055 /* Defines used to combine date & time */
00056 #define RTC_OFFSET_WEEKDAY            24U
00057 #define RTC_OFFSET_DAY                16U
00058 #define RTC_OFFSET_MONTH              8U
00059 #define RTC_OFFSET_HOUR               16U
00060 #define RTC_OFFSET_MINUTE             8U
00061
00062 /**
00063   * @}
00064   */
00065
00066 /* Private macros ------------------------------------------------------------*/
00067 #if defined(USE_FULL_LL_DRIVER)
00068 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00069   * @{
00070   */
00071 /**
00072   * @}
00073   */
00074 #endif /*USE_FULL_LL_DRIVER*/
00075
00076 #if !defined (UNUSED)
00077 #define UNUSED(x) ((void)(x))
00078 #endif
00079
00080 /* Exported types ------------------------------------------------------------*/
00081 #if defined(USE_FULL_LL_DRIVER)
00082 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00083   * @{
00084   */
00085
00086 /**
00087   * @brief  RTC Init structures definition
00088   */
00089 typedef struct
00090 {
00091   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00092                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00093
00094                               This feature can be modified afterwards using unitary function
00095                               @ref LL_RTC_SetHourFormat(). */
00096
00097   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00098                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00099
00100                               This feature can be modified afterwards using unitary function
00101                               @ref LL_RTC_SetAsynchPrescaler(). */
00102
00103   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00104                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00105
00106                               This feature can be modified afterwards using unitary function
00107                               @ref LL_RTC_SetSynchPrescaler(). */
00108 } LL_RTC_InitTypeDef;
00109
00110 /**
00111   * @brief  RTC Time structure definition
00112   */
00113 typedef struct
00114 {
00115   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00116                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00117
00118                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00119
00120   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00121                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00122                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00123
00124                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00125
00126   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00127                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00128
00129                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00130
00131   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00132                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00133
00134                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00135 } LL_RTC_TimeTypeDef;
00136
00137 /**
00138   * @brief  RTC Date structure definition
00139   */
00140 typedef struct
00141 {
00142   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00143                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00144
00145                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00146
00147   uint8_t Month;    /*!< Specifies the RTC Date Month.
00148                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00149
00150                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00151
00152   uint8_t Day;      /*!< Specifies the RTC Date Day.
00153                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00154
00155                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00156
00157   uint8_t Year;     /*!< Specifies the RTC Date Year.
00158                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00159
00160                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00161 } LL_RTC_DateTypeDef;
00162
00163 /**
00164   * @brief  RTC Alarm structure definition
00165   */
00166 typedef struct
00167 {
00168   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00169
00170   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00171                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00172
00173                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00174                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00175                                  */
00176
00177   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00178                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00179
00180                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00181                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00182                                  */
00183
00184   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00185                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00186
00187                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00188                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00189
00190                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00191
00192                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00193                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00194                                  */
00195 } LL_RTC_AlarmTypeDef;
00196
00197 /**
00198   * @}
00199   */
00200 #endif /* USE_FULL_LL_DRIVER */
00201
00202 /* Exported constants --------------------------------------------------------*/
00203 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00204   * @{
00205   */
00206
00207 #if defined(USE_FULL_LL_DRIVER)
00208 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00209   * @{
00210   */
00211 #define LL_RTC_FORMAT_BIN                  0x00000000U /*!< Binary data format */
00212 #define LL_RTC_FORMAT_BCD                  0x00000001U /*!< BCD data format */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00218   * @{
00219   */
00220 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
00221 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00227   * @{
00228   */
00229 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
00230 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00231 /**
00232   * @}
00233   */
00234
00235 #endif /* USE_FULL_LL_DRIVER */
00236
00237 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00238   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00239   * @{
00240   */
00241 #define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF
00242 #define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF
00243 #define LL_RTC_SCR_TSF                     RTC_SCR_CTSF
00244 #define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF
00245 #define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF
00246 #define LL_RTC_CSR_ALRAF                   RTC_SCR_CALRAF
00247
00248 #define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF
00249 #define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF
00250 #define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF
00251 #define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS
00252 #define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF
00253 #define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF
00254 #define LL_RTC_ICSR_ALRBWF                 RTC_ICSR_ALRBWF
00255 #define LL_RTC_ICSR_ALRAWF                 RTC_ICSR_ALRAWF
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RTC_LL_EC_IT IT Defines
00261   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00262   * @{
00263   */
00264 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00265 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00266 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00267 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00273   * @{
00274   */
00275 #define LL_RTC_WEEKDAY_MONDAY              (uint8_t)0x01 /*!< Monday    */
00276 #define LL_RTC_WEEKDAY_TUESDAY             (uint8_t)0x02 /*!< Tuesday   */
00277 #define LL_RTC_WEEKDAY_WEDNESDAY           (uint8_t)0x03 /*!< Wednesday */
00278 #define LL_RTC_WEEKDAY_THURSDAY            (uint8_t)0x04 /*!< Thrusday  */
00279 #define LL_RTC_WEEKDAY_FRIDAY              (uint8_t)0x05 /*!< Friday    */
00280 #define LL_RTC_WEEKDAY_SATURDAY            (uint8_t)0x06 /*!< Saturday  */
00281 #define LL_RTC_WEEKDAY_SUNDAY              (uint8_t)0x07 /*!< Sunday    */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup RTC_LL_EC_MONTH  MONTH
00287   * @{
00288   */
00289 #define LL_RTC_MONTH_JANUARY               (uint8_t)0x01  /*!< January   */
00290 #define LL_RTC_MONTH_FEBRUARY              (uint8_t)0x02  /*!< February  */
00291 #define LL_RTC_MONTH_MARCH                 (uint8_t)0x03  /*!< March     */
00292 #define LL_RTC_MONTH_APRIL                 (uint8_t)0x04  /*!< April     */
00293 #define LL_RTC_MONTH_MAY                   (uint8_t)0x05  /*!< May       */
00294 #define LL_RTC_MONTH_JUNE                  (uint8_t)0x06  /*!< June      */
00295 #define LL_RTC_MONTH_JULY                  (uint8_t)0x07  /*!< July      */
00296 #define LL_RTC_MONTH_AUGUST                (uint8_t)0x08  /*!< August    */
00297 #define LL_RTC_MONTH_SEPTEMBER             (uint8_t)0x09  /*!< September */
00298 #define LL_RTC_MONTH_OCTOBER               (uint8_t)0x10  /*!< October   */
00299 #define LL_RTC_MONTH_NOVEMBER              (uint8_t)0x11  /*!< November  */
00300 #define LL_RTC_MONTH_DECEMBER              (uint8_t)0x12  /*!< December  */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00306   * @{
00307   */
00308 #define LL_RTC_HOURFORMAT_24HOUR           0x00000000U             /*!< 24 hour/day format */
00309 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00315   * @{
00316   */
00317 #define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
00318 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00319 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00320 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00326   * @{
00327   */
00328 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE    /*!< RTC_ALARM is open-drain output */
00329 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0x00000000U             /*!< RTC_ALARM is push-pull output */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00335   * @{
00336   */
00337 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00338 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00344   * @{
00345   */
00346 #define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
00347 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00353   * @{
00354   */
00355 #define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00356 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00362   * @{
00363   */
00364 #define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
00365 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00366 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00367 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00368 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00369 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00375   * @{
00376   */
00377 #define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00378 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00384   * @{
00385   */
00386 #define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
00387 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00388 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00389 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00390 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00391 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00397   * @{
00398   */
00399 #define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00400 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00406   * @{
00407   */
00408 #define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
00409 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00415   * @{
00416   */
00417 #define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
00418 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00424   * @{
00425   */
00426 #define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
00427 #define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
00428 #if (RTC_TAMP_NB == 3)
00429 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3  input detection */
00430 #elif (RTC_TAMP_NB == 8)
00431 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3  input detection */
00432 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3  input detection */
00433 #define LL_RTC_TAMPER_4                    TAMP_CR1_TAMP4E /*!< Tamper 4  input detection */
00434 #define LL_RTC_TAMPER_5                    TAMP_CR1_TAMP5E /*!< Tamper 5  input detection */
00435 #define LL_RTC_TAMPER_6                    TAMP_CR1_TAMP6E /*!< Tamper 6  input detection */
00436 #define LL_RTC_TAMPER_7                    TAMP_CR1_TAMP7E /*!< Tamper 7  input detection */
00437 #define LL_RTC_TAMPER_8                    TAMP_CR1_TAMP8E /*!< Tamper 8  input detection */
00438 #else
00439 #warning "RTC_TAMP_NB is not correct"
00440 #endif /* (RTC_TAMP_NB) */
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00446   * @{
00447   */
00448 #define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00449 #define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00450 #if (RTC_TAMP_NB == 3)
00451 #define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00452 #elif (RTC_TAMP_NB == 8)
00453 #define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00454 #define LL_RTC_TAMPER_MASK_TAMPER4         TAMP_CR2_TAMP4MF /*!< Tamper 4 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00455 #define LL_RTC_TAMPER_MASK_TAMPER5         TAMP_CR2_TAMP5MF /*!< Tamper 5 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00456 #define LL_RTC_TAMPER_MASK_TAMPER6         TAMP_CR2_TAMP6MF /*!< Tamper 6 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00457 #define LL_RTC_TAMPER_MASK_TAMPER7         TAMP_CR2_TAMP7MF /*!< Tamper 7 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00458 #define LL_RTC_TAMPER_MASK_TAMPER8         TAMP_CR2_TAMP8MF /*!< Tamper 8 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00459 #else
00460 #warning "RTC_TAMP_NB is not correct"
00461 #endif /* (RTC_TAMP_NB) */
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00467   * @{
00468   */
00469 #define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00470 #define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00471 #if (RTC_TAMP_NB == 3)
00472 #define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00473 #elif (RTC_TAMP_NB == 8)
00474 #define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00475 #define LL_RTC_TAMPER_NOERASE_TAMPER4      TAMP_CR2_TAMP4NOERASE /*!< Tamper 4 event does not erase the backup registers. */
00476 #define LL_RTC_TAMPER_NOERASE_TAMPER5      TAMP_CR2_TAMP5NOERASE /*!< Tamper 5 event does not erase the backup registers. */
00477 #define LL_RTC_TAMPER_NOERASE_TAMPER6      TAMP_CR2_TAMP6NOERASE /*!< Tamper 6 event does not erase the backup registers. */
00478 #define LL_RTC_TAMPER_NOERASE_TAMPER7      TAMP_CR2_TAMP7NOERASE /*!< Tamper 7 event does not erase the backup registers. */
00479 #define LL_RTC_TAMPER_NOERASE_TAMPER8      TAMP_CR2_TAMP8NOERASE /*!< Tamper 8 event does not erase the backup registers. */
00480 #else
00481 #warning "RTC_TAMP_NB is not correct"
00482 #endif /* (RTC_TAMP_NB) */
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00488   * @{
00489   */
00490 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U            /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00491 #define LL_RTC_TAMPER_DURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00492 #define LL_RTC_TAMPER_DURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00493 #define LL_RTC_TAMPER_DURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00499   * @{
00500   */
00501 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U             /*!< Tamper filter is disabled */
00502 #define LL_RTC_TAMPER_FILTER_2SAMPLE       TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00503 #define LL_RTC_TAMPER_FILTER_4SAMPLE       TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00504 #define LL_RTC_TAMPER_FILTER_8SAMPLE       TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00510   * @{
00511   */
00512 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00513 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00514 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00515 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00516 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00517 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00518 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00519 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00525   * @{
00526   */
00527 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00528 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00529 #if (RTC_TAMP_NB == 3)
00530 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00531 #elif (RTC_TAMP_NB == 8)
00532 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00533 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4    TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00534 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5    TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00535 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6    TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00536 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7    TAMP_CR2_TAMP7TRG /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00537 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP8    TAMP_CR2_TAMP8TRG /*!< Tamper 8 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00538 #endif /* (RTC_TAMP_NB) */
00539 /**
00540   * @}
00541   */
00542
00543
00544 /** @defgroup RTC_LL_EC_INTERNAL  INTERNAL TAMPER
00545   * @{
00546   */
00547 #define LL_RTC_TAMPER_ITAMP1           TAMP_CR1_ITAMP1E /*!< Internal tamper 1: RTC supply voltage monitoring */
00548 #if defined (RTC_TAMP_INT_2_SUPPORT)
00549 #define LL_RTC_TAMPER_ITAMP2           TAMP_CR1_ITAMP2E /*!< Internal tamper 2: temperature monitoring */
00550 #endif /* RTC_TAMP_INT_2_SUPPORT */
00551 #define LL_RTC_TAMPER_ITAMP3           TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */
00552 #define LL_RTC_TAMPER_ITAMP4           TAMP_CR1_ITAMP4E /*!< Internal tamper 4: HSE monitoring */
00553 #define LL_RTC_TAMPER_ITAMP5           TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */
00554 #if defined (RTC_TAMP_INT_6_SUPPORT)
00555 #define LL_RTC_TAMPER_ITAMP6           TAMP_CR1_ITAMP6E /*!< Internal tamper 6: Test mode entry */
00556 #endif /* RTC_TAMP_INT_6_SUPPORT */
00557 #if defined (RTC_TAMP_INT_7_SUPPORT)
00558 #define LL_RTC_TAMPER_ITAMP7           TAMP_CR1_ITAMP7E /*!< Internal tamper 7: Readout protection level decrease */
00559 #endif /* RTC_TAMP_INT_7_SUPPORT */
00560 #if defined (RTC_TAMP_INT_8_SUPPORT)
00561 #define LL_RTC_TAMPER_ITAMP8           TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */
00562 #endif /* RTC_TAMP_INT_8_SUPPORT */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup RTC_LL_EC_BKP  BACKUP
00569   * @{
00570   */
00571 #define LL_RTC_BKP_NUMBER                    RTC_BACKUP_NB
00572 #if (LL_RTC_BKP_NUMBER == 5)
00573 #define LL_RTC_BKP_DR0                       0x00U
00574 #define LL_RTC_BKP_DR1                       0x01U
00575 #define LL_RTC_BKP_DR2                       0x02U
00576 #define LL_RTC_BKP_DR3                       0x03U
00577 #define LL_RTC_BKP_DR4                       0x04U
00578 #elif (LL_RTC_BKP_NUMBER == 16)
00579 #define LL_RTC_BKP_DR0                       0x00U
00580 #define LL_RTC_BKP_DR1                       0x01U
00581 #define LL_RTC_BKP_DR2                       0x02U
00582 #define LL_RTC_BKP_DR3                       0x03U
00583 #define LL_RTC_BKP_DR4                       0x04U
00584 #define LL_RTC_BKP_DR5                       0x05U
00585 #define LL_RTC_BKP_DR6                       0x06U
00586 #define LL_RTC_BKP_DR7                       0x07U
00587 #define LL_RTC_BKP_DR8                       0x08U
00588 #define LL_RTC_BKP_DR9                       0x09U
00589 #define LL_RTC_BKP_DR10                      0x0AU
00590 #define LL_RTC_BKP_DR11                      0x0BU
00591 #define LL_RTC_BKP_DR12                      0x0CU
00592 #define LL_RTC_BKP_DR13                      0x0DU
00593 #define LL_RTC_BKP_DR14                      0x0EU
00594 #define LL_RTC_BKP_DR15                      0x0FU
00595 #elif (LL_RTC_BKP_NUMBER == 32)
00596 #define LL_RTC_BKP_DR0                       0x00U
00597 #define LL_RTC_BKP_DR1                       0x01U
00598 #define LL_RTC_BKP_DR2                       0x02U
00599 #define LL_RTC_BKP_DR3                       0x03U
00600 #define LL_RTC_BKP_DR4                       0x04U
00601 #define LL_RTC_BKP_DR5                       0x05U
00602 #define LL_RTC_BKP_DR6                       0x06U
00603 #define LL_RTC_BKP_DR7                       0x07U
00604 #define LL_RTC_BKP_DR8                       0x08U
00605 #define LL_RTC_BKP_DR9                       0x09U
00606 #define LL_RTC_BKP_DR10                      0x0AU
00607 #define LL_RTC_BKP_DR11                      0x0BU
00608 #define LL_RTC_BKP_DR12                      0x0CU
00609 #define LL_RTC_BKP_DR13                      0x0DU
00610 #define LL_RTC_BKP_DR14                      0x0EU
00611 #define LL_RTC_BKP_DR15                      0x0FU
00612 #define LL_RTC_BKP_DR16                      0x10U
00613 #define LL_RTC_BKP_DR17                      0x11U
00614 #define LL_RTC_BKP_DR18                      0x12U
00615 #define LL_RTC_BKP_DR19                      0x13U
00616 #define LL_RTC_BKP_DR20                      0x14U
00617 #define LL_RTC_BKP_DR21                      0x15U
00618 #define LL_RTC_BKP_DR22                      0x16U
00619 #define LL_RTC_BKP_DR23                      0x17U
00620 #define LL_RTC_BKP_DR24                      0x18U
00621 #define LL_RTC_BKP_DR25                      0x19U
00622 #define LL_RTC_BKP_DR26                      0x1AU
00623 #define LL_RTC_BKP_DR27                      0x1BU
00624 #define LL_RTC_BKP_DR28                      0x1CU
00625 #define LL_RTC_BKP_DR29                      0x1DU
00626 #define LL_RTC_BKP_DR30                      0x1EU
00627 #define LL_RTC_BKP_DR31                      0x1FU
00628 #else
00629 #error "no LL Backup Registers Definition"
00630 #endif /* (LL_RTC_BKP_NUMBER) */
00631
00632 /**
00633   * @}
00634   */
00635
00636 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00637   * @{
00638   */
00639 #define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
00640 #define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                      /*!< RTC/8 clock is selected */
00641 #define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                      /*!< RTC/4 clock is selected */
00642 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00643 #define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                      /*!< ck_spre (usually 1 Hz) clock is selected */
00644 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00645 /**
00646   * @}
00647   */
00648
00649 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00650   * @{
00651   */
00652 #define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
00653 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
00654 #define LL_RTC_CALIB_OUTPUT_512HZ          RTC_CR_COE                  /*!< Calibration output is 512 Hz */
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00660   * @{
00661   */
00662 #define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
00663 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00664 /**
00665   * @}
00666   */
00667
00668 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00669   * @{
00670   */
00671 #define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
00672 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00673 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /* Exported macro ------------------------------------------------------------*/
00683 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00684   * @{
00685   */
00686
00687 /**
00688   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00689   * @param  __VALUE__ Byte to be converted
00690   * @retval Converted byte
00691   */
00692 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00693
00694 /**
00695   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00696   * @param  __VALUE__ BCD value to be converted
00697   * @retval Converted byte
00698   */
00699 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
00700
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup RTC_LL_EM_Date Date helper Macros
00706   * @{
00707   */
00708
00709 /**
00710   * @brief  Helper macro to retrieve weekday.
00711   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00712   * @retval Returned value can be one of the following values:
00713   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00714   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00715   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00716   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00717   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00718   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00719   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00720   */
00721 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00722
00723 /**
00724   * @brief  Helper macro to retrieve Year in BCD format
00725   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00726   * @retval Year in BCD format (0x00 . . . 0x99)
00727   */
00728 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00729
00730 /**
00731   * @brief  Helper macro to retrieve Month in BCD format
00732   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00733   * @retval Returned value can be one of the following values:
00734   *         @arg @ref LL_RTC_MONTH_JANUARY
00735   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00736   *         @arg @ref LL_RTC_MONTH_MARCH
00737   *         @arg @ref LL_RTC_MONTH_APRIL
00738   *         @arg @ref LL_RTC_MONTH_MAY
00739   *         @arg @ref LL_RTC_MONTH_JUNE
00740   *         @arg @ref LL_RTC_MONTH_JULY
00741   *         @arg @ref LL_RTC_MONTH_AUGUST
00742   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00743   *         @arg @ref LL_RTC_MONTH_OCTOBER
00744   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00745   *         @arg @ref LL_RTC_MONTH_DECEMBER
00746   */
00747 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00748
00749 /**
00750   * @brief  Helper macro to retrieve Day in BCD format
00751   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00752   * @retval Day in BCD format (0x01 . . . 0x31)
00753   */
00754 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00755
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup RTC_LL_EM_Time Time helper Macros
00761   * @{
00762   */
00763
00764 /**
00765   * @brief  Helper macro to retrieve hour in BCD format
00766   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00767   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00768   */
00769 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00770
00771 /**
00772   * @brief  Helper macro to retrieve minute in BCD format
00773   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00774   * @retval Minutes in BCD format (0x00. . .0x59)
00775   */
00776 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00777
00778 /**
00779   * @brief  Helper macro to retrieve second in BCD format
00780   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00781   * @retval Seconds in  format (0x00. . .0x59)
00782   */
00783 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00784
00785 /**
00786   * @}
00787   */
00788
00789 /**
00790   * @}
00791   */
00792
00793 /* Exported functions --------------------------------------------------------*/
00794 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00795   * @{
00796   */
00797
00798 /** @defgroup RTC_LL_EF_Configuration Configuration
00799   * @{
00800   */
00801
00802 /**
00803   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00804   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00805   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00806   * @rmtoll RTC_CR           FMT           LL_RTC_SetHourFormat
00807   * @param  RTCx RTC Instance
00808   * @param  HourFormat This parameter can be one of the following values:
00809   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00810   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00811   * @retval None
00812   */
00813 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00814 {
00815   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00816 }
00817
00818 /**
00819   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00820   * @rmtoll RTC_CR           FMT           LL_RTC_GetHourFormat
00821   * @param  RTCx RTC Instance
00822   * @retval Returned value can be one of the following values:
00823   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00824   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00825   */
00826 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00827 {
00828   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00829 }
00830
00831 /**
00832   * @brief  Select the flag to be routed to RTC_ALARM output
00833   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00834   * @rmtoll RTC_CR           OSEL          LL_RTC_SetAlarmOutEvent
00835   * @param  RTCx RTC Instance
00836   * @param  AlarmOutput This parameter can be one of the following values:
00837   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00838   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00839   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00840   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00841   * @retval None
00842   */
00843 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
00844 {
00845   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
00846 }
00847
00848 /**
00849   * @brief  Get the flag to be routed to RTC_ALARM output
00850   * @rmtoll RTC_CR           OSEL          LL_RTC_GetAlarmOutEvent
00851   * @param  RTCx RTC Instance
00852   * @retval Returned value can be one of the following values:
00853   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00854   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00855   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00856   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00857   */
00858 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
00859 {
00860   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
00861 }
00862
00863 /**
00864   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
00865   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
00866   * @param  RTCx RTC Instance
00867   * @param  Output This parameter can be one of the following values:
00868   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00869   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00870   * @retval None
00871   */
00872 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
00873 {
00874   MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
00875 }
00876
00877 /**
00878   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
00879   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
00880   * @param  RTCx RTC Instance
00881   * @retval Returned value can be one of the following values:
00882   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00883   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00884   */
00885 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
00886 {
00887   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
00888 }
00889
00890
00891 /**
00892   * @brief  Enable initialization mode
00893   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
00894   *         and prescaler register (RTC_PRER).
00895   *         Counters are stopped and start counting from the new value when INIT is reset.
00896   * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
00897   * @param  RTCx RTC Instance
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
00901 {
00902   /* Set the Initialization mode */
00903   WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
00904 }
00905
00906 /**
00907   * @brief  Disable initialization mode (Free running mode)
00908   * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
00909   * @param  RTCx RTC Instance
00910   * @retval None
00911   */
00912 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
00913 {
00914   /* Exit Initialization mode */
00915   WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
00916 }
00917
00918 /**
00919   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
00920   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00921   * @rmtoll RTC_CR           POL           LL_RTC_SetOutputPolarity
00922   * @param  RTCx RTC Instance
00923   * @param  Polarity This parameter can be one of the following values:
00924   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00925   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00926   * @retval None
00927   */
00928 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
00929 {
00930   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
00931 }
00932
00933 /**
00934   * @brief  Get Output polarity
00935   * @rmtoll RTC_CR           POL           LL_RTC_GetOutputPolarity
00936   * @param  RTCx RTC Instance
00937   * @retval Returned value can be one of the following values:
00938   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00939   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00940   */
00941 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
00942 {
00943   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
00944 }
00945
00946 /**
00947   * @brief  Enable Bypass the shadow registers
00948   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00949   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
00950   * @param  RTCx RTC Instance
00951   * @retval None
00952   */
00953 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
00954 {
00955   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00956 }
00957
00958 /**
00959   * @brief  Disable Bypass the shadow registers
00960   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
00961   * @param  RTCx RTC Instance
00962   * @retval None
00963   */
00964 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
00965 {
00966   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00967 }
00968
00969 /**
00970   * @brief  Check if Shadow registers bypass is enabled or not.
00971   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
00972   * @param  RTCx RTC Instance
00973   * @retval State of bit (1 or 0).
00974   */
00975 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
00976 {
00977   return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
00978 }
00979
00980 /**
00981   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
00982   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00983   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00984   * @rmtoll RTC_CR           REFCKON       LL_RTC_EnableRefClock
00985   * @param  RTCx RTC Instance
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
00989 {
00990   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
00991 }
00992
00993 /**
00994   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
00995   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00996   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00997   * @rmtoll RTC_CR           REFCKON       LL_RTC_DisableRefClock
00998   * @param  RTCx RTC Instance
00999   * @retval None
01000   */
01001 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
01002 {
01003   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
01004 }
01005
01006 /**
01007   * @brief  Set Asynchronous prescaler factor
01008   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
01009   * @param  RTCx RTC Instance
01010   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
01014 {
01015   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
01016 }
01017
01018 /**
01019   * @brief  Set Synchronous prescaler factor
01020   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
01021   * @param  RTCx RTC Instance
01022   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
01026 {
01027   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
01028 }
01029
01030 /**
01031   * @brief  Get Asynchronous prescaler factor
01032   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
01033   * @param  RTCx RTC Instance
01034   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
01035   */
01036 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
01037 {
01038   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
01039 }
01040
01041 /**
01042   * @brief  Get Synchronous prescaler factor
01043   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
01044   * @param  RTCx RTC Instance
01045   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
01046   */
01047 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
01048 {
01049   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
01050 }
01051
01052 /**
01053   * @brief  Enable the write protection for RTC registers.
01054   * @rmtoll RTC_WPR          KEY           LL_RTC_EnableWriteProtection
01055   * @param  RTCx RTC Instance
01056   * @retval None
01057   */
01058 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
01059 {
01060   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
01061 }
01062
01063 /**
01064   * @brief  Disable the write protection for RTC registers.
01065   * @rmtoll RTC_WPR          KEY           LL_RTC_DisableWriteProtection
01066   * @param  RTCx RTC Instance
01067   * @retval None
01068   */
01069 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
01070 {
01071   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
01072   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
01073 }
01074
01075 /**
01076   * @brief  Enable tamper output.
01077   * @note When the tamper output is enabled, all external and internal tamper flags
01078   *       are ORed and routed to the TAMPALRM output.
01079   * @rmtoll RTC_CR           TAMPOE       LL_RTC_EnableTamperOutput
01080   * @param  RTCx RTC Instance
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
01084 {
01085   SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
01086 }
01087
01088 /**
01089   * @brief  Disable tamper output.
01090   * @rmtoll RTC_CR           TAMPOE       LL_RTC_DisableTamperOutput
01091   * @param  RTCx RTC Instance
01092   * @retval None
01093   */
01094 __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
01095 {
01096   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
01097 }
01098
01099 /**
01100   * @brief  Check if tamper output is enabled or not.
01101   * @rmtoll RTC_CR           TAMPOE       LL_RTC_IsTamperOutputEnabled
01102   * @param  RTCx RTC Instance
01103   * @retval State of bit (1 or 0).
01104   */
01105 __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
01106 {
01107   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
01108 }
01109
01110 /**
01111   * @brief  Enable internal pull-up in output mode.
01112   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01113   * @param  RTCx RTC Instance
01114   * @retval None
01115   */
01116 __STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
01117 {
01118   SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01119 }
01120
01121 /**
01122   * @brief  Disable internal pull-up in output mode.
01123   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01124   * @param  RTCx RTC Instance
01125   * @retval None
01126   */
01127 __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
01128 {
01129   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01130 }
01131
01132 /**
01133   * @brief  Check if internal pull-up in output mode is enabled or not.
01134   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_IsAlarmPullUpEnabled
01135   * @param  RTCx RTC Instance
01136   * @retval State of bit (1 or 0).
01137   */
01138 __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
01139 {
01140   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
01141 }
01142
01143 /**
01144   * @brief  Enable RTC_OUT2 output
01145   * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
01146   *       and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
01147   * @note RTC_OUT2 is not available ins VBAT mode.
01148   * @rmtoll RTC_CR           OUT2EN       LL_RTC_EnableOutput2
01149   * @param  RTCx RTC Instance
01150   * @retval None
01151   */
01152 __STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
01153 {
01154   SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
01155 }
01156
01157 /**
01158   * @brief  Disable RTC_OUT2 output
01159   * @rmtoll RTC_CR           OUT2EN       LL_RTC_DisableOutput2
01160   * @param  RTCx RTC Instance
01161   * @retval None
01162   */
01163 __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
01164 {
01165   CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
01166 }
01167
01168 /**
01169   * @brief  Check if RTC_OUT2 output is enabled or not.
01170   * @rmtoll RTC_CR           OUT2EN       LL_RTC_IsOutput2Enabled
01171   * @param  RTCx RTC Instance
01172   * @retval State of bit (1 or 0).
01173   */
01174 __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
01175 {
01176   return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
01177 }
01178
01179 /**
01180   * @}
01181   */
01182
01183 /** @defgroup RTC_LL_EF_Time Time
01184   * @{
01185   */
01186
01187 /**
01188   * @brief  Set time format (AM/24-hour or PM notation)
01189   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01190   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01191   * @rmtoll RTC_TR           PM            LL_RTC_TIME_SetFormat
01192   * @param  RTCx RTC Instance
01193   * @param  TimeFormat This parameter can be one of the following values:
01194   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01195   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01196   * @retval None
01197   */
01198 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01199 {
01200   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01201 }
01202
01203 /**
01204   * @brief  Get time format (AM or PM notation)
01205   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01206   *       before reading this bit
01207   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01208   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01209   * @rmtoll RTC_TR           PM            LL_RTC_TIME_GetFormat
01210   * @param  RTCx RTC Instance
01211   * @retval Returned value can be one of the following values:
01212   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01213   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01214   */
01215 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01216 {
01217   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01218 }
01219
01220 /**
01221   * @brief  Set Hours in BCD format
01222   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01223   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01224   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01225   * @rmtoll RTC_TR           HT            LL_RTC_TIME_SetHour\n
01226   *         RTC_TR           HU            LL_RTC_TIME_SetHour
01227   * @param  RTCx RTC Instance
01228   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01229   * @retval None
01230   */
01231 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01232 {
01233   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01234              (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
01235 }
01236
01237 /**
01238   * @brief  Get Hours in BCD format
01239   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01240   *       before reading this bit
01241   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01242   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01243   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01244   *       Binary format
01245   * @rmtoll RTC_TR           HT            LL_RTC_TIME_GetHour\n
01246   *         RTC_TR           HU            LL_RTC_TIME_GetHour
01247   * @param  RTCx RTC Instance
01248   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01249   */
01250 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01251 {
01252   return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
01253 }
01254
01255 /**
01256   * @brief  Set Minutes in BCD format
01257   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01258   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01259   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01260   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_SetMinute\n
01261   *         RTC_TR           MNU           LL_RTC_TIME_SetMinute
01262   * @param  RTCx RTC Instance
01263   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01264   * @retval None
01265   */
01266 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01267 {
01268   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01269              (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
01270 }
01271
01272 /**
01273   * @brief  Get Minutes in BCD format
01274   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01275   *       before reading this bit
01276   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01277   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01278   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01279   *       to Binary format
01280   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_GetMinute\n
01281   *         RTC_TR           MNU           LL_RTC_TIME_GetMinute
01282   * @param  RTCx RTC Instance
01283   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01284   */
01285 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01286 {
01287   return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
01288 }
01289
01290 /**
01291   * @brief  Set Seconds in BCD format
01292   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01293   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01294   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01295   * @rmtoll RTC_TR           ST            LL_RTC_TIME_SetSecond\n
01296   *         RTC_TR           SU            LL_RTC_TIME_SetSecond
01297   * @param  RTCx RTC Instance
01298   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01299   * @retval None
01300   */
01301 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01302 {
01303   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01304              (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
01305 }
01306
01307 /**
01308   * @brief  Get Seconds in BCD format
01309   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01310   *       before reading this bit
01311   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01312   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01313   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01314   *       to Binary format
01315   * @rmtoll RTC_TR           ST            LL_RTC_TIME_GetSecond\n
01316   *         RTC_TR           SU            LL_RTC_TIME_GetSecond
01317   * @param  RTCx RTC Instance
01318   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01319   */
01320 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01321 {
01322   return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
01323 }
01324
01325 /**
01326   * @brief  Set time (hour, minute and second) in BCD format
01327   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01328   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01329   * @note TimeFormat and Hours should follow the same format
01330   * @rmtoll RTC_TR           PM            LL_RTC_TIME_Config\n
01331   *         RTC_TR           HT            LL_RTC_TIME_Config\n
01332   *         RTC_TR           HU            LL_RTC_TIME_Config\n
01333   *         RTC_TR           MNT           LL_RTC_TIME_Config\n
01334   *         RTC_TR           MNU           LL_RTC_TIME_Config\n
01335   *         RTC_TR           ST            LL_RTC_TIME_Config\n
01336   *         RTC_TR           SU            LL_RTC_TIME_Config
01337   * @param  RTCx RTC Instance
01338   * @param  Format12_24 This parameter can be one of the following values:
01339   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01340   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01341   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01342   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01343   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01344   * @retval None
01345   */
01346 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
01347                                         uint32_t Seconds)
01348 {
01349   uint32_t temp;
01350
01351   temp = Format12_24                                                                                    | \
01352          (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
01353          (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
01354          (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
01355   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01356 }
01357
01358 /**
01359   * @brief  Get time (hour, minute and second) in BCD format
01360   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01361   *       before reading this bit
01362   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01363   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01364   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01365   *       are available to get independently each parameter.
01366   * @rmtoll RTC_TR           HT            LL_RTC_TIME_Get\n
01367   *         RTC_TR           HU            LL_RTC_TIME_Get\n
01368   *         RTC_TR           MNT           LL_RTC_TIME_Get\n
01369   *         RTC_TR           MNU           LL_RTC_TIME_Get\n
01370   *         RTC_TR           ST            LL_RTC_TIME_Get\n
01371   *         RTC_TR           SU            LL_RTC_TIME_Get
01372   * @param  RTCx RTC Instance
01373   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01374   */
01375 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01376 {
01377   uint32_t temp;
01378
01379   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
01380   return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR)       |  \
01381                     (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
01382                     ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
01383 }
01384
01385 /**
01386   * @brief  Memorize whether the daylight saving time change has been performed
01387   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01388   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_EnableDayLightStore
01389   * @param  RTCx RTC Instance
01390   * @retval None
01391   */
01392 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01393 {
01394   SET_BIT(RTCx->CR, RTC_CR_BKP);
01395 }
01396
01397 /**
01398   * @brief  Disable memorization whether the daylight saving time change has been performed.
01399   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01400   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_DisableDayLightStore
01401   * @param  RTCx RTC Instance
01402   * @retval None
01403   */
01404 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01405 {
01406   CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
01407 }
01408
01409 /**
01410   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01411   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
01412   * @param  RTCx RTC Instance
01413   * @retval State of bit (1 or 0).
01414   */
01415 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01416 {
01417   return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
01418 }
01419
01420 /**
01421   * @brief  Subtract 1 hour (winter time change)
01422   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01423   * @rmtoll RTC_CR           SUB1H         LL_RTC_TIME_DecHour
01424   * @param  RTCx RTC Instance
01425   * @retval None
01426   */
01427 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01428 {
01429   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01430 }
01431
01432 /**
01433   * @brief  Add 1 hour (summer time change)
01434   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01435   * @rmtoll RTC_CR           ADD1H         LL_RTC_TIME_IncHour
01436   * @param  RTCx RTC Instance
01437   * @retval None
01438   */
01439 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01440 {
01441   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01442 }
01443
01444 /**
01445   * @brief  Get Sub second value in the synchronous prescaler counter.
01446   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01447   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01448   *        SubSeconds value in second fraction ratio with time unit following
01449   *        generic formula:
01450   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01451   *        This conversion can be performed only if no shift operation is pending
01452   *        (ie. SHFP=0) when PREDIV_S >= SS.
01453   * @rmtoll RTC_SSR          SS            LL_RTC_TIME_GetSubSecond
01454   * @param  RTCx RTC Instance
01455   * @retval Sub second value (number between 0 and 65535)
01456   */
01457 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01458 {
01459   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01460 }
01461
01462 /**
01463   * @brief  Synchronize to a remote clock with a high degree of precision.
01464   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01465   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01466   * @note   When REFCKON is set, firmware must not write to Shift control register.
01467   * @rmtoll RTC_SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
01468   *         RTC_SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01469   * @param  RTCx RTC Instance
01470   * @param  ShiftSecond This parameter can be one of the following values:
01471   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01472   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01473   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01474   * @retval None
01475   */
01476 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01477 {
01478   WRITE_REG(RTCx->SHIFTR, (ShiftSecond | Fraction));
01479 }
01480
01481 /**
01482   * @}
01483   */
01484
01485 /** @defgroup RTC_LL_EF_Date Date
01486   * @{
01487   */
01488
01489 /**
01490   * @brief  Set Year in BCD format
01491   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01492   * @rmtoll RTC_DR           YT            LL_RTC_DATE_SetYear\n
01493   *         RTC_DR           YU            LL_RTC_DATE_SetYear
01494   * @param  RTCx RTC Instance
01495   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01496   * @retval None
01497   */
01498 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01499 {
01500   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01501              (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
01502 }
01503
01504 /**
01505   * @brief  Get Year in BCD format
01506   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01507   *       before reading this bit
01508   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01509   * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear\n
01510   *         RTC_DR           YU            LL_RTC_DATE_GetYear
01511   * @param  RTCx RTC Instance
01512   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01513   */
01514 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01515 {
01516   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
01517 }
01518
01519 /**
01520   * @brief  Set Week day
01521   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_SetWeekDay
01522   * @param  RTCx RTC Instance
01523   * @param  WeekDay This parameter can be one of the following values:
01524   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01525   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01526   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01527   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01528   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01529   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01530   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01531   * @retval None
01532   */
01533 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01534 {
01535   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
01536 }
01537
01538 /**
01539   * @brief  Get Week day
01540   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01541   *       before reading this bit
01542   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay
01543   * @param  RTCx RTC Instance
01544   * @retval Returned value can be one of the following values:
01545   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01546   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01547   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01548   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01549   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01550   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01551   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01552   */
01553 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01554 {
01555   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
01556 }
01557
01558 /**
01559   * @brief  Set Month in BCD format
01560   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01561   * @rmtoll RTC_DR           MT            LL_RTC_DATE_SetMonth\n
01562   *         RTC_DR           MU            LL_RTC_DATE_SetMonth
01563   * @param  RTCx RTC Instance
01564   * @param  Month This parameter can be one of the following values:
01565   *         @arg @ref LL_RTC_MONTH_JANUARY
01566   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01567   *         @arg @ref LL_RTC_MONTH_MARCH
01568   *         @arg @ref LL_RTC_MONTH_APRIL
01569   *         @arg @ref LL_RTC_MONTH_MAY
01570   *         @arg @ref LL_RTC_MONTH_JUNE
01571   *         @arg @ref LL_RTC_MONTH_JULY
01572   *         @arg @ref LL_RTC_MONTH_AUGUST
01573   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01574   *         @arg @ref LL_RTC_MONTH_OCTOBER
01575   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01576   *         @arg @ref LL_RTC_MONTH_DECEMBER
01577   * @retval None
01578   */
01579 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01580 {
01581   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01582              (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
01583 }
01584
01585 /**
01586   * @brief  Get Month in BCD format
01587   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01588   *       before reading this bit
01589   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01590   * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth\n
01591   *         RTC_DR           MU            LL_RTC_DATE_GetMonth
01592   * @param  RTCx RTC Instance
01593   * @retval Returned value can be one of the following values:
01594   *         @arg @ref LL_RTC_MONTH_JANUARY
01595   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01596   *         @arg @ref LL_RTC_MONTH_MARCH
01597   *         @arg @ref LL_RTC_MONTH_APRIL
01598   *         @arg @ref LL_RTC_MONTH_MAY
01599   *         @arg @ref LL_RTC_MONTH_JUNE
01600   *         @arg @ref LL_RTC_MONTH_JULY
01601   *         @arg @ref LL_RTC_MONTH_AUGUST
01602   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01603   *         @arg @ref LL_RTC_MONTH_OCTOBER
01604   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01605   *         @arg @ref LL_RTC_MONTH_DECEMBER
01606   */
01607 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01608 {
01609   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
01610 }
01611
01612 /**
01613   * @brief  Set Day in BCD format
01614   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01615   * @rmtoll RTC_DR           DT            LL_RTC_DATE_SetDay\n
01616   *         RTC_DR           DU            LL_RTC_DATE_SetDay
01617   * @param  RTCx RTC Instance
01618   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01619   * @retval None
01620   */
01621 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01622 {
01623   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01624              (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
01625 }
01626
01627 /**
01628   * @brief  Get Day in BCD format
01629   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01630   *       before reading this bit
01631   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01632   * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay\n
01633   *         RTC_DR           DU            LL_RTC_DATE_GetDay
01634   * @param  RTCx RTC Instance
01635   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01636   */
01637 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01638 {
01639   return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
01640 }
01641
01642 /**
01643   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01644   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Config\n
01645   *         RTC_DR           MT            LL_RTC_DATE_Config\n
01646   *         RTC_DR           MU            LL_RTC_DATE_Config\n
01647   *         RTC_DR           DT            LL_RTC_DATE_Config\n
01648   *         RTC_DR           DU            LL_RTC_DATE_Config\n
01649   *         RTC_DR           YT            LL_RTC_DATE_Config\n
01650   *         RTC_DR           YU            LL_RTC_DATE_Config
01651   * @param  RTCx RTC Instance
01652   * @param  WeekDay This parameter can be one of the following values:
01653   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01654   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01655   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01656   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01657   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01658   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01659   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01660   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01661   * @param  Month This parameter can be one of the following values:
01662   *         @arg @ref LL_RTC_MONTH_JANUARY
01663   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01664   *         @arg @ref LL_RTC_MONTH_MARCH
01665   *         @arg @ref LL_RTC_MONTH_APRIL
01666   *         @arg @ref LL_RTC_MONTH_MAY
01667   *         @arg @ref LL_RTC_MONTH_JUNE
01668   *         @arg @ref LL_RTC_MONTH_JULY
01669   *         @arg @ref LL_RTC_MONTH_AUGUST
01670   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01671   *         @arg @ref LL_RTC_MONTH_OCTOBER
01672   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01673   *         @arg @ref LL_RTC_MONTH_DECEMBER
01674   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01675   * @retval None
01676   */
01677 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month,
01678                                         uint32_t Year)
01679 {
01680   uint32_t temp;
01681
01682   temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
01683          (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
01684          (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
01685          (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
01686
01687   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01688 }
01689
01690 /**
01691   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01692   * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
01693   *       before reading this bit
01694   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01695   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01696   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Get\n
01697   *         RTC_DR           MT            LL_RTC_DATE_Get\n
01698   *         RTC_DR           MU            LL_RTC_DATE_Get\n
01699   *         RTC_DR           DT            LL_RTC_DATE_Get\n
01700   *         RTC_DR           DU            LL_RTC_DATE_Get\n
01701   *         RTC_DR           YT            LL_RTC_DATE_Get\n
01702   *         RTC_DR           YU            LL_RTC_DATE_Get
01703   * @param  RTCx RTC Instance
01704   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01705   */
01706 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01707 {
01708   uint32_t temp;
01709
01710   temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
01711   return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
01712                     (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY)   | \
01713                     (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
01714                     ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
01715 }
01716
01717 /**
01718   * @}
01719   */
01720
01721 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01722   * @{
01723   */
01724
01725 /**
01726   * @brief  Enable Alarm A
01727   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01728   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Enable
01729   * @param  RTCx RTC Instance
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01733 {
01734   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01735 }
01736
01737 /**
01738   * @brief  Disable Alarm A
01739   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01740   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Disable
01741   * @param  RTCx RTC Instance
01742   * @retval None
01743   */
01744 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
01745 {
01746   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
01747 }
01748
01749 /**
01750   * @brief  Specify the Alarm A masks.
01751   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
01752   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
01753   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
01754   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_SetMask
01755   * @param  RTCx RTC Instance
01756   * @param  Mask This parameter can be a combination of the following values:
01757   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01758   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01759   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01760   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01761   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01762   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01763   * @retval None
01764   */
01765 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
01766 {
01767   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
01768 }
01769
01770 /**
01771   * @brief  Get the Alarm A masks.
01772   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
01773   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
01774   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
01775   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_GetMask
01776   * @param  RTCx RTC Instance
01777   * @retval Returned value can be can be a combination of the following values:
01778   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01779   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01780   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01781   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01782   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01783   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01784   */
01785 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
01786 {
01787   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
01788 }
01789
01790 /**
01791   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
01792   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
01793   * @param  RTCx RTC Instance
01794   * @retval None
01795   */
01796 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
01797 {
01798   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01799 }
01800
01801 /**
01802   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
01803   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
01804   * @param  RTCx RTC Instance
01805   * @retval None
01806   */
01807 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
01808 {
01809   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01810 }
01811
01812 /**
01813   * @brief  Set ALARM A Day in BCD format
01814   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01815   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_SetDay\n
01816   *         RTC_ALRMAR       DU            LL_RTC_ALMA_SetDay
01817   * @param  RTCx RTC Instance
01818   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01822 {
01823   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
01824              (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
01825 }
01826
01827 /**
01828   * @brief  Get ALARM A Day in BCD format
01829   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01830   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_GetDay\n
01831   *         RTC_ALRMAR       DU            LL_RTC_ALMA_GetDay
01832   * @param  RTCx RTC Instance
01833   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01834   */
01835 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
01836 {
01837   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
01838 }
01839
01840 /**
01841   * @brief  Set ALARM A Weekday
01842   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
01843   * @param  RTCx RTC Instance
01844   * @param  WeekDay This parameter can be one of the following values:
01845   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01846   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01847   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01848   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01849   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01850   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01851   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01852   * @retval None
01853   */
01854 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01855 {
01856   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
01857 }
01858
01859 /**
01860   * @brief  Get ALARM A Weekday
01861   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
01862   * @param  RTCx RTC Instance
01863   * @retval Returned value can be one of the following values:
01864   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01865   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01866   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01867   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01868   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01869   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01870   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01871   */
01872 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
01873 {
01874   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
01875 }
01876
01877 /**
01878   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
01879   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
01880   * @param  RTCx RTC Instance
01881   * @param  TimeFormat This parameter can be one of the following values:
01882   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01883   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01884   * @retval None
01885   */
01886 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01887 {
01888   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
01889 }
01890
01891 /**
01892   * @brief  Get Alarm A time format (AM or PM notation)
01893   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
01894   * @param  RTCx RTC Instance
01895   * @retval Returned value can be one of the following values:
01896   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01897   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01898   */
01899 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
01900 {
01901   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
01902 }
01903
01904 /**
01905   * @brief  Set ALARM A Hours in BCD format
01906   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
01907   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_SetHour\n
01908   *         RTC_ALRMAR       HU            LL_RTC_ALMA_SetHour
01909   * @param  RTCx RTC Instance
01910   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01911   * @retval None
01912   */
01913 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01914 {
01915   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
01916              (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
01917 }
01918
01919 /**
01920   * @brief  Get ALARM A Hours in BCD format
01921   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
01922   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetHour\n
01923   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetHour
01924   * @param  RTCx RTC Instance
01925   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01926   */
01927 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
01928 {
01929   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
01930 }
01931
01932 /**
01933   * @brief  Set ALARM A Minutes in BCD format
01934   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01935   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
01936   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_SetMinute
01937   * @param  RTCx RTC Instance
01938   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01939   * @retval None
01940   */
01941 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01942 {
01943   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
01944              (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
01945 }
01946
01947 /**
01948   * @brief  Get ALARM A Minutes in BCD format
01949   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
01950   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
01951   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetMinute
01952   * @param  RTCx RTC Instance
01953   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01954   */
01955 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
01956 {
01957   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
01958 }
01959
01960 /**
01961   * @brief  Set ALARM A Seconds in BCD format
01962   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01963   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
01964   *         RTC_ALRMAR       SU            LL_RTC_ALMA_SetSecond
01965   * @param  RTCx RTC Instance
01966   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01967   * @retval None
01968   */
01969 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01970 {
01971   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
01972              (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
01973 }
01974
01975 /**
01976   * @brief  Get ALARM A Seconds in BCD format
01977   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
01978   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
01979   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetSecond
01980   * @param  RTCx RTC Instance
01981   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01982   */
01983 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
01984 {
01985   return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
01986 }
01987
01988 /**
01989   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
01990   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
01991   *         RTC_ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
01992   *         RTC_ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
01993   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
01994   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
01995   *         RTC_ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
01996   *         RTC_ALRMAR       SU            LL_RTC_ALMA_ConfigTime
01997   * @param  RTCx RTC Instance
01998   * @param  Format12_24 This parameter can be one of the following values:
01999   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
02000   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
02001   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02002   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02003   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02004   * @retval None
02005   */
02006 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
02007                                             uint32_t Seconds)
02008 {
02009   uint32_t temp;
02010
02011   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
02012          (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
02013          (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
02014
02015   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST
02016              | RTC_ALRMAR_SU, temp);
02017 }
02018
02019 /**
02020   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02021   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02022   * are available to get independently each parameter.
02023   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetTime\n
02024   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetTime\n
02025   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
02026   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
02027   *         RTC_ALRMAR       ST            LL_RTC_ALMA_GetTime\n
02028   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetTime
02029   * @param  RTCx RTC Instance
02030   * @retval Combination of hours, minutes and seconds.
02031   */
02032 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
02033 {
02034   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
02035 }
02036
02037 /**
02038   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
02039   * @note This register can be written only when ALRAE is reset in RTC_CR register,
02040   *       or in initialization mode.
02041   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
02042   * @param  RTCx RTC Instance
02043   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02047 {
02048   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
02049 }
02050
02051 /**
02052   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
02053   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
02054   * @param  RTCx RTC Instance
02055   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02056   */
02057 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
02058 {
02059   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
02060 }
02061
02062 /**
02063   * @brief  Set Alarm A Sub seconds value
02064   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
02065   * @param  RTCx RTC Instance
02066   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02067   * @retval None
02068   */
02069 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02070 {
02071   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
02072 }
02073
02074 /**
02075   * @brief  Get Alarm A Sub seconds value
02076   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
02077   * @param  RTCx RTC Instance
02078   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02079   */
02080 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
02081 {
02082   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
02083 }
02084
02085 /**
02086   * @}
02087   */
02088
02089 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02090   * @{
02091   */
02092
02093 /**
02094   * @brief  Enable Alarm B
02095   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02096   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Enable
02097   * @param  RTCx RTC Instance
02098   * @retval None
02099   */
02100 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02101 {
02102   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02103 }
02104
02105 /**
02106   * @brief  Disable Alarm B
02107   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02108   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Disable
02109   * @param  RTCx RTC Instance
02110   * @retval None
02111   */
02112 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02113 {
02114   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02115 }
02116
02117 /**
02118   * @brief  Specify the Alarm B masks.
02119   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
02120   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
02121   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
02122   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02123   * @param  RTCx RTC Instance
02124   * @param  Mask This parameter can be a combination of the following values:
02125   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02126   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02127   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02128   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02129   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02130   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02131   * @retval None
02132   */
02133 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02134 {
02135   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02136 }
02137
02138 /**
02139   * @brief  Get the Alarm B masks.
02140   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
02141   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
02142   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
02143   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02144   * @param  RTCx RTC Instance
02145   * @retval Returned value can be can be a combination of the following values:
02146   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02147   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02148   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02149   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02150   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02151   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02152   */
02153 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02154 {
02155   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02156 }
02157
02158 /**
02159   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02160   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02161   * @param  RTCx RTC Instance
02162   * @retval None
02163   */
02164 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02165 {
02166   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02167 }
02168
02169 /**
02170   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02171   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02172   * @param  RTCx RTC Instance
02173   * @retval None
02174   */
02175 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02176 {
02177   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02178 }
02179
02180 /**
02181   * @brief  Set ALARM B Day in BCD format
02182   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02183   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_SetDay\n
02184   *         RTC_ALRMBR       DU            LL_RTC_ALMB_SetDay
02185   * @param  RTCx RTC Instance
02186   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02187   * @retval None
02188   */
02189 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02190 {
02191   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02192              (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
02193 }
02194
02195 /**
02196   * @brief  Get ALARM B Day in BCD format
02197   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02198   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_GetDay\n
02199   *         RTC_ALRMBR       DU            LL_RTC_ALMB_GetDay
02200   * @param  RTCx RTC Instance
02201   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02202   */
02203 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02204 {
02205   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
02206 }
02207
02208 /**
02209   * @brief  Set ALARM B Weekday
02210   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02211   * @param  RTCx RTC Instance
02212   * @param  WeekDay This parameter can be one of the following values:
02213   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02214   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02215   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02216   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02217   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02218   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02219   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02220   * @retval None
02221   */
02222 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02223 {
02224   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
02225 }
02226
02227 /**
02228   * @brief  Get ALARM B Weekday
02229   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02230   * @param  RTCx RTC Instance
02231   * @retval Returned value can be one of the following values:
02232   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02233   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02234   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02235   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02236   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02237   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02238   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02239   */
02240 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02241 {
02242   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
02243 }
02244
02245 /**
02246   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02247   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02248   * @param  RTCx RTC Instance
02249   * @param  TimeFormat This parameter can be one of the following values:
02250   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02251   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02252   * @retval None
02253   */
02254 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02255 {
02256   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02257 }
02258
02259 /**
02260   * @brief  Get ALARM B time format (AM or PM notation)
02261   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02262   * @param  RTCx RTC Instance
02263   * @retval Returned value can be one of the following values:
02264   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02265   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02266   */
02267 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02268 {
02269   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02270 }
02271
02272 /**
02273   * @brief  Set ALARM B Hours in BCD format
02274   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02275   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_SetHour\n
02276   *         RTC_ALRMBR       HU            LL_RTC_ALMB_SetHour
02277   * @param  RTCx RTC Instance
02278   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02279   * @retval None
02280   */
02281 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02282 {
02283   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02284              (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
02285 }
02286
02287 /**
02288   * @brief  Get ALARM B Hours in BCD format
02289   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02290   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetHour\n
02291   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetHour
02292   * @param  RTCx RTC Instance
02293   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02294   */
02295 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02296 {
02297   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
02298 }
02299
02300 /**
02301   * @brief  Set ALARM B Minutes in BCD format
02302   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02303   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
02304   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02305   * @param  RTCx RTC Instance
02306   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02307   * @retval None
02308   */
02309 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02310 {
02311   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02312              (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
02313 }
02314
02315 /**
02316   * @brief  Get ALARM B Minutes in BCD format
02317   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02318   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
02319   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02320   * @param  RTCx RTC Instance
02321   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02322   */
02323 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02324 {
02325   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
02326 }
02327
02328 /**
02329   * @brief  Set ALARM B Seconds in BCD format
02330   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02331   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
02332   *         RTC_ALRMBR       SU            LL_RTC_ALMB_SetSecond
02333   * @param  RTCx RTC Instance
02334   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02335   * @retval None
02336   */
02337 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02338 {
02339   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02340              (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
02341 }
02342
02343 /**
02344   * @brief  Get ALARM B Seconds in BCD format
02345   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02346   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
02347   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetSecond
02348   * @param  RTCx RTC Instance
02349   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02350   */
02351 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02352 {
02353   return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
02354 }
02355
02356 /**
02357   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02358   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
02359   *         RTC_ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
02360   *         RTC_ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
02361   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
02362   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
02363   *         RTC_ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
02364   *         RTC_ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02365   * @param  RTCx RTC Instance
02366   * @param  Format12_24 This parameter can be one of the following values:
02367   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02368   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02369   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02370   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02371   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02372   * @retval None
02373   */
02374 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
02375                                             uint32_t Seconds)
02376 {
02377   uint32_t temp;
02378
02379   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
02380          (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
02381          (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
02382
02383   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST
02384              | RTC_ALRMBR_SU, temp);
02385 }
02386
02387 /**
02388   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02389   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02390   * are available to get independently each parameter.
02391   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetTime\n
02392   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetTime\n
02393   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
02394   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
02395   *         RTC_ALRMBR       ST            LL_RTC_ALMB_GetTime\n
02396   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetTime
02397   * @param  RTCx RTC Instance
02398   * @retval Combination of hours, minutes and seconds.
02399   */
02400 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02401 {
02402   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02403 }
02404
02405 /**
02406   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02407   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02408   *       or in initialization mode.
02409   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02410   * @param  RTCx RTC Instance
02411   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02412   * @retval None
02413   */
02414 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02415 {
02416   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
02417 }
02418
02419 /**
02420   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02421   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02422   * @param  RTCx RTC Instance
02423   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02424   */
02425 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02426 {
02427   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
02428 }
02429
02430 /**
02431   * @brief  Set Alarm B Sub seconds value
02432   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02433   * @param  RTCx RTC Instance
02434   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02435   * @retval None
02436   */
02437 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02438 {
02439   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02440 }
02441
02442 /**
02443   * @brief  Get Alarm B Sub seconds value
02444   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02445   * @param  RTCx RTC Instance
02446   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02447   */
02448 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02449 {
02450   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02451 }
02452
02453 /**
02454   * @}
02455   */
02456
02457 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02458   * @{
02459   */
02460
02461 /**
02462   * @brief  Enable internal event timestamp
02463   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02464   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_EnableInternalEvent
02465   * @param  RTCx RTC Instance
02466   * @retval None
02467   */
02468 __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
02469 {
02470   SET_BIT(RTCx->CR, RTC_CR_ITSE);
02471 }
02472
02473 /**
02474   * @brief  Disable internal event timestamp
02475   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02476   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_DisableInternalEvent
02477   * @param  RTCx RTC Instance
02478   * @retval None
02479   */
02480 __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
02481 {
02482   CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
02483 }
02484
02485 /**
02486   * @brief  Enable Timestamp
02487   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02488   * @rmtoll RTC_CR           ITSE           LL_RTC_TS_Enable
02489   * @param  RTCx RTC Instance
02490   * @retval None
02491   */
02492 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02493 {
02494   SET_BIT(RTCx->CR, RTC_CR_TSE);
02495 }
02496
02497 /**
02498   * @brief  Disable Timestamp
02499   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02500   * @rmtoll RTC_CR           ITSE           LL_RTC_TS_Disable
02501   * @param  RTCx RTC Instance
02502   * @retval None
02503   */
02504 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02505 {
02506   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02507 }
02508
02509 /**
02510   * @brief  Set Time-stamp event active edge
02511   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02512   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02513   * @rmtoll RTC_CR           ITSEDGE        LL_RTC_TS_SetActiveEdge
02514   * @param  RTCx RTC Instance
02515   * @param  Edge This parameter can be one of the following values:
02516   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02517   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02518   * @retval None
02519   */
02520 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02521 {
02522   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02523 }
02524
02525 /**
02526   * @brief  Get Time-stamp event active edge
02527   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02528   * @rmtoll RTC_CR           ITSEDGE        LL_RTC_TS_GetActiveEdge
02529   * @param  RTCx RTC Instance
02530   * @retval Returned value can be one of the following values:
02531   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02532   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02533   */
02534 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02535 {
02536   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02537 }
02538
02539 /**
02540   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02541   * @rmtoll RTC_TSTR         PM            LL_RTC_TS_GetTimeFormat
02542   * @param  RTCx RTC Instance
02543   * @retval Returned value can be one of the following values:
02544   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02545   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02546   */
02547 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02548 {
02549   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02550 }
02551
02552 /**
02553   * @brief  Get Timestamp Hours in BCD format
02554   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02555   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetHour\n
02556   *         RTC_TSTR         HU            LL_RTC_TS_GetHour
02557   * @param  RTCx RTC Instance
02558   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02559   */
02560 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02561 {
02562   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
02563 }
02564
02565 /**
02566   * @brief  Get Timestamp Minutes in BCD format
02567   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02568   * @rmtoll RTC_TSTR         MNT           LL_RTC_TS_GetMinute\n
02569   *         RTC_TSTR         HU           LL_RTC_TS_GetMinute
02570   * @param  RTCx RTC Instance
02571   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02572   */
02573 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02574 {
02575   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
02576 }
02577
02578 /**
02579   * @brief  Get Timestamp Seconds in BCD format
02580   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02581   * @rmtoll RTC_TSTR         ST            LL_RTC_TS_GetSecond\n
02582   *         RTC_TSTR         HU            LL_RTC_TS_GetSecond
02583   * @param  RTCx RTC Instance
02584   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02585   */
02586 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02587 {
02588   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02589 }
02590
02591 /**
02592   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02593   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02594   * are available to get independently each parameter.
02595   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetTime\n
02596   *         RTC_TSTR         HU            LL_RTC_TS_GetTime\n
02597   *         RTC_TSTR         MNT           LL_RTC_TS_GetTime\n
02598   *         RTC_TSTR         MNU           LL_RTC_TS_GetTime\n
02599   *         RTC_TSTR         ST            LL_RTC_TS_GetTime\n
02600   *         RTC_TSTR         SU            LL_RTC_TS_GetTime
02601   * @param  RTCx RTC Instance
02602   * @retval Combination of hours, minutes and seconds.
02603   */
02604 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02605 {
02606   return (uint32_t)(READ_BIT(RTCx->TSTR,
02607                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02608 }
02609
02610 /**
02611   * @brief  Get Timestamp Week day
02612   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetWeekDay
02613   * @param  RTCx RTC Instance
02614   * @retval Returned value can be one of the following values:
02615   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02616   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02617   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02618   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02619   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02620   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02621   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02622   */
02623 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02624 {
02625   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
02626 }
02627
02628 /**
02629   * @brief  Get Timestamp Month in BCD format
02630   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02631   * @rmtoll RTC_TSDR         MT            LL_RTC_TS_GetMonth\n
02632   *         RTC_TSDR         MU            LL_RTC_TS_GetMonth
02633   * @param  RTCx RTC Instance
02634   * @retval Returned value can be one of the following values:
02635   *         @arg @ref LL_RTC_MONTH_JANUARY
02636   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02637   *         @arg @ref LL_RTC_MONTH_MARCH
02638   *         @arg @ref LL_RTC_MONTH_APRIL
02639   *         @arg @ref LL_RTC_MONTH_MAY
02640   *         @arg @ref LL_RTC_MONTH_JUNE
02641   *         @arg @ref LL_RTC_MONTH_JULY
02642   *         @arg @ref LL_RTC_MONTH_AUGUST
02643   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02644   *         @arg @ref LL_RTC_MONTH_OCTOBER
02645   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02646   *         @arg @ref LL_RTC_MONTH_DECEMBER
02647   */
02648 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02649 {
02650   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
02651 }
02652
02653 /**
02654   * @brief  Get Timestamp Day in BCD format
02655   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02656   * @rmtoll RTC_TSDR         DT            LL_RTC_TS_GetDay\n
02657   *         RTC_TSDR         DU            LL_RTC_TS_GetDay
02658   * @param  RTCx RTC Instance
02659   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02660   */
02661 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02662 {
02663   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02664 }
02665
02666 /**
02667   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02668   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02669   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02670   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetDate\n
02671   *         RTC_TSDR         MT            LL_RTC_TS_GetDate\n
02672   *         RTC_TSDR         MU            LL_RTC_TS_GetDate\n
02673   *         RTC_TSDR         DT            LL_RTC_TS_GetDate\n
02674   *         RTC_TSDR         DU            LL_RTC_TS_GetDate
02675   * @param  RTCx RTC Instance
02676   * @retval Combination of Weekday, Day and Month
02677   */
02678 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02679 {
02680   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02681 }
02682
02683 /**
02684   * @brief  Get time-stamp sub second value
02685   * @rmtoll RTC_TSDR         SS            LL_RTC_TS_GetSubSecond
02686   * @param  RTCx RTC Instance
02687   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02688   */
02689 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02690 {
02691   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02692 }
02693
02694 /**
02695   * @brief  Activate timestamp on tamper detection event
02696   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
02697   * @param  RTCx RTC Instance
02698   * @retval None
02699   */
02700 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02701 {
02702   SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
02703 }
02704
02705 /**
02706   * @brief  Disable timestamp on tamper detection event
02707   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper
02708   * @param  RTCx RTC Instance
02709   * @retval None
02710   */
02711 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02712 {
02713   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
02714 }
02715
02716
02717 /**
02718   * @}
02719   */
02720
02721 /** @defgroup RTC_LL_EF_Tamper Tamper
02722   * @{
02723   */
02724
02725 /**
02726   * @brief  Enable TAMPx input detection
02727   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable\n
02728   *         TAMP_CR1       TAMP2E...     LL_RTC_TAMPER_Enable
02729   * @param  RTCx RTC Instance
02730   * @param  Tamper This parameter can be a combination of the following values:
02731   *         @arg @ref LL_RTC_TAMPER_1
02732   *         @arg @ref LL_RTC_TAMPER_2
02733   *
02734   * @retval None
02735   */
02736 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
02737 {
02738   UNUSED(RTCx);
02739   SET_BIT(TAMP->CR1, Tamper);
02740 }
02741
02742 /**
02743   * @brief  Clear TAMPx input detection
02744   * @rmtoll TAMP_CR1       TAMP1E         LL_RTC_TAMPER_Disable\n
02745   *         TAMP_CR1       TAMP2E...      LL_RTC_TAMPER_Disable
02746   * @param  RTCx RTC Instance
02747   * @param  Tamper This parameter can be a combination of the following values:
02748   *         @arg @ref LL_RTC_TAMPER_1
02749   *         @arg @ref LL_RTC_TAMPER_2
02750   *
02751   * @retval None
02752   */
02753 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
02754 {
02755   UNUSED(RTCx);
02756   CLEAR_BIT(TAMP->CR1, Tamper);
02757 }
02758
02759 /**
02760   * @brief  Enable Tamper mask flag
02761   * @note Associated Tamper IT must not enabled when tamper mask is set.
02762   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
02763   *         TAMP_CR2       TAMP2MF...    LL_RTC_TAMPER_EnableMask
02764   * @param  RTCx RTC Instance
02765   * @param  Mask This parameter can be a combination of the following values:
02766   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02767   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02768   *
02769   * @retval None
02770   */
02771 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02772 {
02773   UNUSED(RTCx);
02774   SET_BIT(TAMP->CR2, Mask);
02775 }
02776
02777 /**
02778   * @brief  Disable Tamper mask flag
02779   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
02780   *         TAMP_CR2       TAMP2MF...    LL_RTC_TAMPER_DisableMask
02781   * @param  RTCx RTC Instance
02782   * @param  Mask This parameter can be a combination of the following values:
02783   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02784   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02785   *
02786   * @retval None
02787   */
02788 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02789 {
02790   UNUSED(RTCx);
02791   CLEAR_BIT(TAMP->CR2, Mask);
02792 }
02793
02794 /**
02795   * @brief  Enable backup register erase after Tamper event detection
02796   * @rmtoll TAMP_CR2       TAMP1NOERASE     LL_RTC_TAMPER_EnableEraseBKP\n
02797   *         TAMP_CR2       TAMP2NOERASE...  LL_RTC_TAMPER_EnableEraseBKP
02798   * @param  RTCx RTC Instance
02799   * @param  Tamper This parameter can be a combination of the following values:
02800   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02801   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02802   *
02803   * @retval None
02804   */
02805 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02806 {
02807   UNUSED(RTCx);
02808   CLEAR_BIT(TAMP->CR2, Tamper);
02809 }
02810
02811 /**
02812   * @brief  Disable backup register erase after Tamper event detection
02813   * @rmtoll TAMP_CR2       TAMP1NOERASE     LL_RTC_TAMPER_DisableEraseBKP\n
02814   *         TAMP_CR2       TAMP2NOERASE...  LL_RTC_TAMPER_DisableEraseBKP
02815   * @param  RTCx RTC Instance
02816   * @param  Tamper This parameter can be a combination of the following values:
02817   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02818   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02819   *
02820   * @retval None
02821   */
02822 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02823 {
02824   UNUSED(RTCx);
02825   SET_BIT(TAMP->CR2, Tamper);
02826 }
02827
02828 /**
02829   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
02830   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
02831   * @param  RTCx RTC Instance
02832   * @retval None
02833   */
02834 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
02835 {
02836   UNUSED(RTCx);
02837   SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
02838 }
02839
02840 /**
02841   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
02842   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
02843   * @param  RTCx RTC Instance
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
02847 {
02848   UNUSED(RTCx);
02849   CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
02850 }
02851
02852 /**
02853   * @brief  Set RTC_TAMPx precharge duration
02854   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
02855   * @param  RTCx RTC Instance
02856   * @param  Duration This parameter can be one of the following values:
02857   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02858   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02859   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02860   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02861   * @retval None
02862   */
02863 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
02864 {
02865   UNUSED(RTCx);
02866   MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
02867 }
02868
02869 /**
02870   * @brief  Get RTC_TAMPx precharge duration
02871   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
02872   * @param  RTCx RTC Instance
02873   * @retval Returned value can be one of the following values:
02874   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02875   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02876   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02877   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02878   */
02879 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
02880 {
02881   UNUSED(RTCx);
02882   return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH));
02883 }
02884
02885 /**
02886   * @brief  Set RTC_TAMPx filter count
02887   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
02888   * @param  RTCx RTC Instance
02889   * @param  FilterCount This parameter can be one of the following values:
02890   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02891   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02892   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02893   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02894   * @retval None
02895   */
02896 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
02897 {
02898   UNUSED(RTCx);
02899   MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
02900 }
02901
02902 /**
02903   * @brief  Get RTC_TAMPx filter count
02904   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
02905   * @param  RTCx RTC Instance
02906   * @retval Returned value can be one of the following values:
02907   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02908   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02909   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02910   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02911   */
02912 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
02913 {
02914   UNUSED(RTCx);
02915   return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT));
02916 }
02917
02918 /**
02919   * @brief  Set Tamper sampling frequency
02920   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
02921   * @param  RTCx RTC Instance
02922   * @param  SamplingFreq This parameter can be one of the following values:
02923   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02924   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02925   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02926   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02927   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02928   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02929   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02930   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02931   * @retval None
02932   */
02933 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
02934 {
02935   UNUSED(RTCx);
02936   MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
02937 }
02938
02939 /**
02940   * @brief  Get Tamper sampling frequency
02941   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
02942   * @param  RTCx RTC Instance
02943   * @retval Returned value can be one of the following values:
02944   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02945   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02946   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02947   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02948   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02949   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02950   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02951   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02952   */
02953 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
02954 {
02955   UNUSED(RTCx);
02956   return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ));
02957 }
02958
02959 /**
02960   * @brief  Enable Active level for Tamper input
02961   * @rmtoll TAMP_CR2       TAMP1TRG       LL_RTC_TAMPER_EnableActiveLevel\n
02962   *         TAMP_CR2       TAMP2TRG...    LL_RTC_TAMPER_EnableActiveLevel
02963   * @param  RTCx RTC Instance
02964   * @param  Tamper This parameter can be a combination of the following values:
02965   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02966   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02967   *
02968   * @retval None
02969   */
02970 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02971 {
02972   UNUSED(RTCx);
02973   SET_BIT(TAMP->CR2, Tamper);
02974 }
02975
02976 /**
02977   * @brief  Disable Active level for Tamper input
02978   * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02979   *         TAMP_CR2       TAMP2TRG...   LL_RTC_TAMPER_DisableActiveLevel
02980   * @param  RTCx RTC Instance
02981   * @param  Tamper This parameter can be a combination of the following values:
02982   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02983   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02984   *
02985   * @retval None
02986   */
02987 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02988 {
02989   UNUSED(RTCx);
02990   CLEAR_BIT(TAMP->CR2, Tamper);
02991 }
02992
02993 /**
02994   * @}
02995   */
02996
02997 /** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
02998   * @{
02999   */
03000
03001 /**
03002   * @brief  Enable internal tamper detection.
03003   * @rmtoll TAMP_CR1       ITAMP1E       LL_RTC_TAMPER_ITAMP_Enable\n
03004   *         TAMP_CR1       ITAMP3E       LL_RTC_TAMPER_ITAMP_Enable\n
03005   *         TAMP_CR1       ITAMP4E       LL_RTC_TAMPER_ITAMP_Enable\n
03006   *         TAMP_CR1       ITAMP5E       LL_RTC_TAMPER_ITAMP_Enable\n
03007   *         TAMP_CR1       ITAMP6E       LL_RTC_TAMPER_ITAMP_Enable\n
03008   *         TAMP_CR1       ITAMP7E...    LL_RTC_TAMPER_ITAMP_Enable
03009   * @param  RTCx RTC Instance
03010   * @param  InternalTamper This parameter can be a combination of the following values:
03011   *         @arg @ref LL_RTC_TAMPER_ITAMP1
03012   *         @arg @ref LL_RTC_TAMPER_ITAMP3
03013   *         @arg @ref LL_RTC_TAMPER_ITAMP4
03014   *         @arg @ref LL_RTC_TAMPER_ITAMP5
03015   *         @arg @ref LL_RTC_TAMPER_ITAMP6
03016   @if RTC_TAMP_INT_7_SUPPORT
03017   *         @arg @ref LL_RTC_TAMPER_ITAMP7
03018   @endif
03019   *
03020   * @retval None
03021   */
03022 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
03023 {
03024   UNUSED(RTCx);
03025   SET_BIT(TAMP->CR1, InternalTamper);
03026 }
03027
03028 /**
03029   * @brief  Disable internal tamper detection.
03030   * @rmtoll TAMP_CR1       ITAMP1E       LL_RTC_TAMPER_ITAMP_Disable\n
03031   *         TAMP_CR1       ITAMP3E       LL_RTC_TAMPER_ITAMP_Disable\n
03032   *         TAMP_CR1       ITAMP4E       LL_RTC_TAMPER_ITAMP_Disable\n
03033   *         TAMP_CR1       ITAMP5E       LL_RTC_TAMPER_ITAMP_Disable\n
03034   *         TAMP_CR1       ITAMP6E       LL_RTC_TAMPER_ITAMP_Disable\n
03035   *         TAMP_CR1       ITAMP7E...    LL_RTC_TAMPER_ITAMP_Disable
03036   * @param  RTCx RTC Instance
03037   * @param  InternalTamper This parameter can be a combination of the following values:
03038   *         @arg @ref LL_RTC_TAMPER_ITAMP1
03039   *         @arg @ref LL_RTC_TAMPER_ITAMP3
03040   *         @arg @ref LL_RTC_TAMPER_ITAMP4
03041   *         @arg @ref LL_RTC_TAMPER_ITAMP5
03042   *         @arg @ref LL_RTC_TAMPER_ITAMP6
03043   @if RTC_TAMP_INT_7_SUPPORT
03044   *         @arg @ref LL_RTC_TAMPER_ITAMP7
03045   @endif
03046   *
03047   * @retval None
03048   */
03049 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
03050 {
03051   UNUSED(RTCx);
03052   CLEAR_BIT(TAMP->CR1, InternalTamper);
03053 }
03054
03055 /**
03056   * @}
03057   */
03058
03059
03060 /** @defgroup RTC_LL_EF_Wakeup Wakeup
03061   * @{
03062   */
03063
03064 /**
03065   * @brief  Enable Wakeup timer
03066   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03067   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Enable
03068   * @param  RTCx RTC Instance
03069   * @retval None
03070   */
03071 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
03072 {
03073   SET_BIT(RTCx->CR, RTC_CR_WUTE);
03074 }
03075
03076 /**
03077   * @brief  Disable Wakeup timer
03078   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03079   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Disable
03080   * @param  RTCx RTC Instance
03081   * @retval None
03082   */
03083 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
03084 {
03085   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
03086 }
03087
03088 /**
03089   * @brief  Check if Wakeup timer is enabled or not
03090   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_IsEnabled
03091   * @param  RTCx RTC Instance
03092   * @retval State of bit (1 or 0).
03093   */
03094 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
03095 {
03096   return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
03097 }
03098
03099 /**
03100   * @brief  Select Wakeup clock
03101   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03102   * @note   Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
03103   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
03104   * @param  RTCx RTC Instance
03105   * @param  WakeupClock This parameter can be one of the following values:
03106   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03107   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03108   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03109   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03110   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03111   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03112   * @retval None
03113   */
03114 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
03115 {
03116   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
03117 }
03118
03119 /**
03120   * @brief  Get Wakeup clock
03121   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
03122   * @param  RTCx RTC Instance
03123   * @retval Returned value can be one of the following values:
03124   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03125   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03126   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03127   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03128   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03129   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03130   */
03131 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
03132 {
03133   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
03134 }
03135
03136 /**
03137   * @brief  Set Wakeup auto-reload value
03138   * @note   Bit can be written only when WUTWF is set to 1 in RTC_ICSR
03139   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
03140   * @param  RTCx RTC Instance
03141   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
03142   * @retval None
03143   */
03144 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03145 {
03146   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03147 }
03148
03149 /**
03150   * @brief  Get Wakeup auto-reload value
03151   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03152   * @param  RTCx RTC Instance
03153   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03154   */
03155 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03156 {
03157   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03158 }
03159
03160 /**
03161   * @}
03162   */
03163
03164 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03165   * @{
03166   */
03167
03168 /**
03169   * @brief  Writes a data in a specified Backup data register.
03170   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister
03171   * @param  RTCx RTC Instance
03172   * @param  BackupRegister This parameter can be one of the following values:
03173   *         @arg @ref LL_RTC_BKP_DR0
03174   *         @arg @ref LL_RTC_BKP_DR1
03175   *         @arg @ref LL_RTC_BKP_DR2
03176   *         @arg @ref LL_RTC_BKP_DR3
03177   *         ...
03178   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03179   * @retval None
03180   */
03181 __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
03182 {
03183   __IO uint32_t *tmp;
03184
03185   UNUSED(RTCx);
03186
03187   tmp = &(TAMP->BKP0R) + BackupRegister;
03188
03189   /* Write the specified register */
03190   *tmp = Data;
03191 }
03192
03193 /**
03194   * @brief  Reads data from the specified RTC Backup data Register.
03195   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_GetRegister
03196   * @param  RTCx RTC Instance
03197   * @param  BackupRegister This parameter can be one of the following values:
03198   *         @arg @ref LL_RTC_BKP_DR0
03199   *         @arg @ref LL_RTC_BKP_DR1
03200   *         @arg @ref LL_RTC_BKP_DR2
03201   *         @arg @ref LL_RTC_BKP_DR3
03202   *         ...
03203   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03204   */
03205 __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
03206 {
03207   const __IO uint32_t *tmp;
03208
03209   UNUSED(RTCx);
03210
03211   tmp = &(TAMP->BKP0R) + BackupRegister;
03212
03213   /* Read the specified register */
03214   return *tmp;
03215 }
03216
03217 /**
03218   * @}
03219   */
03220
03221 /** @defgroup RTC_LL_EF_Calibration Calibration
03222   * @{
03223   */
03224
03225 /**
03226   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03227   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03228   * @rmtoll RTC_CR           COE           LL_RTC_CAL_SetOutputFreq\n
03229   *         RTC_CR           COSEL         LL_RTC_CAL_SetOutputFreq
03230   * @param  RTCx RTC Instance
03231   * @param  Frequency This parameter can be one of the following values:
03232   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03233   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03234   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03235   * @retval None
03236   */
03237 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03238 {
03239   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03240 }
03241
03242 /**
03243   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03244   * @rmtoll RTC_CR           COE           LL_RTC_CAL_GetOutputFreq\n
03245   *         RTC_CR           COSEL         LL_RTC_CAL_GetOutputFreq
03246   * @param  RTCx RTC Instance
03247   * @retval Returned value can be one of the following values:
03248   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03249   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03250   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03251   */
03252 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03253 {
03254   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03255 }
03256
03257 /**
03258   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03259   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03260   * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
03261   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_SetPulse
03262   * @param  RTCx RTC Instance
03263   * @param  Pulse This parameter can be one of the following values:
03264   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03265   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03266   * @retval None
03267   */
03268 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03269 {
03270   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03271 }
03272
03273 /**
03274   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03275   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_IsPulseInserted
03276   * @param  RTCx RTC Instance
03277   * @retval State of bit (1 or 0).
03278   */
03279 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03280 {
03281   return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
03282 }
03283
03284 /**
03285   * @brief  Set the calibration cycle period
03286   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03287   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ICSR
03288   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_SetPeriod\n
03289   *         RTC_CALR         CALW16        LL_RTC_CAL_SetPeriod
03290   * @param  RTCx RTC Instance
03291   * @param  Period This parameter can be one of the following values:
03292   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03293   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03294   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03295   * @retval None
03296   */
03297 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03298 {
03299   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03300 }
03301
03302 /**
03303   * @brief  Get the calibration cycle period
03304   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_GetPeriod\n
03305   *         RTC_CALR         CALW16        LL_RTC_CAL_GetPeriod
03306   * @param  RTCx RTC Instance
03307   * @retval Returned value can be one of the following values:
03308   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03309   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03310   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03311   */
03312 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03313 {
03314   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03315 }
03316
03317 /**
03318   * @brief  Set Calibration minus
03319   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03320   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ICSR
03321   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_SetMinus
03322   * @param  RTCx RTC Instance
03323   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03324   * @retval None
03325   */
03326 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03327 {
03328   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03329 }
03330
03331 /**
03332   * @brief  Get Calibration minus
03333   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_GetMinus
03334   * @param  RTCx RTC Instance
03335   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
03336   */
03337 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
03338 {
03339   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
03340 }
03341
03342 /**
03343   * @}
03344   */
03345
03346 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
03347   * @{
03348   */
03349
03350 /**
03351   * @brief  Get Internal Time-stamp flag
03352   * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS
03353   * @param  RTCx RTC Instance
03354   * @retval State of bit (1 or 0).
03355   */
03356 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
03357 {
03358   return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
03359 }
03360
03361 /**
03362   * @brief  Get Recalibration pending Flag
03363   * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP
03364   * @param  RTCx RTC Instance
03365   * @retval State of bit (1 or 0).
03366   */
03367 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
03368 {
03369   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
03370 }
03371
03372 /**
03373   * @brief  Get Time-stamp overflow flag
03374   * @rmtoll RTC_SR          TSOVF         LL_RTC_IsActiveFlag_TSOV
03375   * @param  RTCx RTC Instance
03376   * @retval State of bit (1 or 0).
03377   */
03378 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
03379 {
03380   return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
03381 }
03382
03383 /**
03384   * @brief  Get Time-stamp flag
03385   * @rmtoll RTC_SR          TSF           LL_RTC_IsActiveFlag_TS
03386   * @param  RTCx RTC Instance
03387   * @retval State of bit (1 or 0).
03388   */
03389 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
03390 {
03391   return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
03392 }
03393
03394 /**
03395   * @brief  Get Wakeup timer flag
03396   * @rmtoll RTC_SR          WUTF          LL_RTC_IsActiveFlag_WUT
03397   * @param  RTCx RTC Instance
03398   * @retval State of bit (1 or 0).
03399   */
03400 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
03401 {
03402   return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
03403 }
03404
03405 /**
03406   * @brief  Get Alarm B flag
03407   * @rmtoll RTC_SR          ALRBF         LL_RTC_IsActiveFlag_ALRB
03408   * @param  RTCx RTC Instance
03409   * @retval State of bit (1 or 0).
03410   */
03411 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
03412 {
03413   return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
03414 }
03415
03416 /**
03417   * @brief  Get Alarm A flag
03418   * @rmtoll RTC_SR          ALRAF         LL_RTC_IsActiveFlag_ALRA
03419   * @param  RTCx RTC Instance
03420   * @retval State of bit (1 or 0).
03421   */
03422 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
03423 {
03424   return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
03425 }
03426
03427 /**
03428   * @brief  Clear Internal Time-stamp flag
03429   * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS
03430   * @param  RTCx RTC Instance
03431   * @retval None
03432   */
03433 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
03434 {
03435   SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
03436 }
03437
03438 /**
03439   * @brief  Clear Time-stamp overflow flag
03440   * @rmtoll RTC_SCR          CTSOVF         LL_RTC_ClearFlag_TSOV
03441   * @param  RTCx RTC Instance
03442   * @retval None
03443   */
03444 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
03445 {
03446   SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
03447 }
03448
03449 /**
03450   * @brief  Clear Time-stamp flag
03451   * @rmtoll RTC_SCR          CTSF           LL_RTC_ClearFlag_TS
03452   * @param  RTCx RTC Instance
03453   * @retval None
03454   */
03455 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
03456 {
03457   SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
03458 }
03459
03460 /**
03461   * @brief  Clear Wakeup timer flag
03462   * @rmtoll RTC_SCR          CWUTF          LL_RTC_ClearFlag_WUT
03463   * @param  RTCx RTC Instance
03464   * @retval None
03465   */
03466 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
03467 {
03468   SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
03469 }
03470
03471 /**
03472   * @brief  Clear Alarm B flag
03473   * @rmtoll RTC_SCR          CALRBF         LL_RTC_ClearFlag_ALRB
03474   * @param  RTCx RTC Instance
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
03478 {
03479   SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
03480 }
03481
03482 /**
03483   * @brief  Clear Alarm A flag
03484   * @rmtoll RTC_SCR          CALRAF         LL_RTC_ClearFlag_ALRA
03485   * @param  RTCx RTC Instance
03486   * @retval None
03487   */
03488 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
03489 {
03490   SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
03491 }
03492
03493 /**
03494   * @brief  Get Initialization flag
03495   * @rmtoll RTC_ICSR          INITF         LL_RTC_IsActiveFlag_INIT
03496   * @param  RTCx RTC Instance
03497   * @retval State of bit (1 or 0).
03498   */
03499 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
03500 {
03501   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
03502 }
03503
03504 /**
03505   * @brief  Get Registers synchronization flag
03506   * @rmtoll RTC_ICSR          RSF           LL_RTC_IsActiveFlag_RS
03507   * @param  RTCx RTC Instance
03508   * @retval State of bit (1 or 0).
03509   */
03510 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
03511 {
03512   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
03513 }
03514
03515 /**
03516   * @brief  Clear Registers synchronization flag
03517   * @rmtoll RTC_ICSR          RSF           LL_RTC_ClearFlag_RS
03518   * @param  RTCx RTC Instance
03519   * @retval None
03520   */
03521 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
03522 {
03523   WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
03524 }
03525
03526 /**
03527   * @brief  Get Initialization status flag
03528   * @rmtoll RTC_ICSR          INITS         LL_RTC_IsActiveFlag_INITS
03529   * @param  RTCx RTC Instance
03530   * @retval State of bit (1 or 0).
03531   */
03532 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
03533 {
03534   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
03535 }
03536
03537 /**
03538   * @brief  Get Shift operation pending flag
03539   * @rmtoll RTC_ICSR          SHPF          LL_RTC_IsActiveFlag_SHP
03540   * @param  RTCx RTC Instance
03541   * @retval State of bit (1 or 0).
03542   */
03543 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
03544 {
03545   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
03546 }
03547
03548 /**
03549   * @brief  Get Wakeup timer write flag
03550   * @rmtoll RTC_ICSR          WUTWF         LL_RTC_IsActiveFlag_WUTW
03551   * @param  RTCx RTC Instance
03552   * @retval State of bit (1 or 0).
03553   */
03554 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
03555 {
03556   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
03557 }
03558
03559 /**
03560   * @brief  Get Alarm B write flag
03561   * @rmtoll RTC_ICSR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
03562   * @param  RTCx RTC Instance
03563   * @retval State of bit (1 or 0).
03564   */
03565 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
03566 {
03567   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1U : 0U);
03568 }
03569
03570 /**
03571   * @brief  Get Alarm A write flag
03572   * @rmtoll RTC_ICSR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
03573   * @param  RTCx RTC Instance
03574   * @retval State of bit (1 or 0).
03575   */
03576 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
03577 {
03578   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1U : 0U);
03579 }
03580
03581 /**
03582   * @brief  Get Alarm A masked flag.
03583   * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM
03584   * @param  RTCx RTC Instance
03585   * @retval State of bit (1 or 0).
03586   */
03587 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
03588 {
03589   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
03590 }
03591
03592 /**
03593   * @brief  Get Alarm B masked flag.
03594   * @rmtoll RTC_MISR          ALRBMF        LL_RTC_IsActiveFlag_ALRBM
03595   * @param  RTCx RTC Instance
03596   * @retval State of bit (1 or 0).
03597   */
03598 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
03599 {
03600   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
03601 }
03602
03603 /**
03604   * @brief  Get Wakeup timer masked flag.
03605   * @rmtoll RTC_MISR          WUTMF        LL_RTC_IsActiveFlag_WUTM
03606   * @param  RTCx RTC Instance
03607   * @retval State of bit (1 or 0).
03608   */
03609 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
03610 {
03611   return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
03612 }
03613
03614 /**
03615   * @brief  Get Time-stamp masked flag.
03616   * @rmtoll RTC_MISR          TSMF        LL_RTC_IsActiveFlag_TSM
03617   * @param  RTCx RTC Instance
03618   * @retval State of bit (1 or 0).
03619   */
03620 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
03621 {
03622   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
03623 }
03624
03625 /**
03626   * @brief  Get Time-stamp overflow masked flag.
03627   * @rmtoll RTC_MISR          TSOVMF        LL_RTC_IsActiveFlag_TSOVM
03628   * @param  RTCx RTC Instance
03629   * @retval State of bit (1 or 0).
03630   */
03631 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
03632 {
03633   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
03634 }
03635
03636 /**
03637   * @brief  Get Internal Time-stamp masked flag.
03638   * @rmtoll RTC_MISR          ITSMF        LL_RTC_IsActiveFlag_ITSM
03639   * @param  RTCx RTC Instance
03640   * @retval State of bit (1 or 0).
03641   */
03642 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
03643 {
03644   return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
03645 }
03646
03647 /**
03648   * @brief  Get tamper 1 detection flag.
03649   * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
03650   * @param  RTCx RTC Instance
03651   * @retval State of bit (1 or 0).
03652   */
03653 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
03654 {
03655   UNUSED(RTCx);
03656   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U);
03657 }
03658
03659 /**
03660   * @brief  Get tamper 2 detection flag.
03661   * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
03662   * @param  RTCx RTC Instance
03663   * @retval State of bit (1 or 0).
03664   */
03665 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
03666 {
03667   UNUSED(RTCx);
03668   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U);
03669 }
03670
03671 #if (RTC_TAMP_NB==3)
03672 /**
03673   * @brief  Get tamper 3 detection flag.
03674   * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03675   * @param  RTCx RTC Instance
03676   * @retval State of bit (1 or 0).
03677   */
03678 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
03679 {
03680   UNUSED(RTCx);
03681   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
03682 }
03683 #elif (RTC_TAMP_NB==8)
03684
03685 /**
03686   * @brief  Get tamper 3 detection flag.
03687   * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03688   * @param  RTCx RTC Instance
03689   * @retval State of bit (1 or 0).
03690   */
03691 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
03692 {
03693   UNUSED(RTCx);
03694   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
03695 }
03696 /**
03697   * @brief  Get tamper 4 detection flag.
03698   * @rmtoll TAMP_SR          TAMP4F        LL_RTC_IsActiveFlag_TAMP4
03699   * @param  RTCx RTC Instance
03700   * @retval State of bit (1 or 0).
03701   */
03702 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx)
03703 {
03704   UNUSED(RTCx);
03705   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U);
03706 }
03707 /**
03708   * @brief  Get tamper 5 detection flag.
03709   * @rmtoll TAMP_SR          TAMP5F        LL_RTC_IsActiveFlag_TAMP5
03710   * @param  RTCx RTC Instance
03711   * @retval State of bit (1 or 0).
03712   */
03713 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx)
03714 {
03715   UNUSED(RTCx);
03716   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U);
03717 }
03718 /**
03719   * @brief  Get tamper 6 detection flag.
03720   * @rmtoll TAMP_SR          TAMP6F        LL_RTC_IsActiveFlag_TAMP6
03721   * @param  RTCx RTC Instance
03722   * @retval State of bit (1 or 0).
03723   */
03724 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx)
03725 {
03726   UNUSED(RTCx);
03727   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U);
03728 }
03729 /**
03730   * @brief  Get tamper 7 detection flag.
03731   * @rmtoll TAMP_SR          TAMP7F        LL_RTC_IsActiveFlag_TAMP7
03732   * @param  RTCx RTC Instance
03733   * @retval State of bit (1 or 0).
03734   */
03735 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx)
03736 {
03737   UNUSED(RTCx);
03738   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U);
03739 }
03740 /**
03741   * @brief  Get tamper 8 detection flag.
03742   * @rmtoll TAMP_SR          TAMP8F        LL_RTC_IsActiveFlag_TAMP8
03743   * @param  RTCx RTC Instance
03744   * @retval State of bit (1 or 0).
03745   */
03746 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx)
03747 {
03748   UNUSED(RTCx);
03749   return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U);
03750 }
03751 #endif /* RTC_TAMP_NB */
03752
03753 #if defined (RTC_TAMP_INT_1_SUPPORT)
03754 /**
03755   * @brief  Get internal tamper 1 detection flag.
03756   * @rmtoll TAMP_SR          ITAMP1F        LL_RTC_IsActiveFlag_ITAMP1
03757   * @param  RTCx RTC Instance
03758   * @retval State of bit (1 or 0).
03759   */
03760 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx)
03761 {
03762   UNUSED(RTCx);
03763   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U);
03764 }
03765
03766 #endif /* RTC_TAMP_INT_1_SUPPORT */
03767 #if defined (RTC_TAMP_INT_2_SUPPORT)
03768 /**
03769   * @brief  Get internal tamper 2 detection flag.
03770   * @rmtoll TAMP_SR          ITAMP2F        LL_RTC_IsActiveFlag_ITAMP2
03771   * @param  RTCx RTC Instance
03772   * @retval State of bit (1 or 0).
03773   */
03774 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx)
03775 {
03776   UNUSED(RTCx);
03777   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U);
03778 }
03779
03780 #endif /* RTC_TAMP_INT_2_SUPPORT */
03781 /**
03782   * @brief  Get internal tamper 3 detection flag.
03783   * @rmtoll TAMP_SR          ITAMP3F        LL_RTC_IsActiveFlag_ITAMP3
03784   * @param  RTCx RTC Instance
03785   * @retval State of bit (1 or 0).
03786   */
03787 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx)
03788 {
03789   UNUSED(RTCx);
03790   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U);
03791 }
03792
03793 /**
03794   * @brief  Get internal tamper 4 detection flag.
03795   * @rmtoll TAMP_SR          ITAMP4F        LL_RTC_IsActiveFlag_ITAMP4
03796   * @param  RTCx RTC Instance
03797   * @retval State of bit (1 or 0).
03798   */
03799 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(RTC_TypeDef *RTCx)
03800 {
03801   UNUSED(RTCx);
03802   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1U : 0U);
03803 }
03804 /**
03805   * @brief  Get internal tamper 5 detection flag.
03806   * @rmtoll TAMP_SR          ITAMP5F        LL_RTC_IsActiveFlag_ITAMP5
03807   * @param  RTCx RTC Instance
03808   * @retval State of bit (1 or 0).
03809   */
03810 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx)
03811 {
03812   UNUSED(RTCx);
03813   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U);
03814 }
03815
03816 #if defined (RTC_TAMP_INT_6_SUPPORT)
03817 /**
03818   * @brief  Get internal tamper 6 detection flag.
03819   * @rmtoll TAMP_SR          ITAMP6F        LL_RTC_IsActiveFlag_ITAMP6
03820   * @param  RTCx RTC Instance
03821   * @retval State of bit (1 or 0).
03822   */
03823 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx)
03824 {
03825   UNUSED(RTCx);
03826   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U);
03827 }
03828 #endif /* RTC_TAMP_INT_6_SUPPORT */
03829
03830 #if defined (RTC_TAMP_INT_7_SUPPORT)
03831 /**
03832   * @brief  Get internal tamper 7 detection flag.
03833   * @rmtoll TAMP_SR          ITAMP7F        LL_RTC_IsActiveFlag_ITAMP7
03834   * @param  RTCx RTC Instance
03835   * @retval State of bit (1 or 0).
03836   */
03837 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(RTC_TypeDef *RTCx)
03838 {
03839   UNUSED(RTCx);
03840   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U);
03841 }
03842 #endif /* RTC_TAMP_INT_7_SUPPORT */
03843
03844 #if defined (RTC_TAMP_INT_8_SUPPORT)
03845 /**
03846   * @brief  Get internal tamper 8 detection flag.
03847   * @rmtoll TAMP_SR          ITAMP8F        LL_RTC_IsActiveFlag_ITAMP8
03848   * @param  RTCx RTC Instance
03849   * @retval State of bit (1 or 0).
03850   */
03851 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx)
03852 {
03853   UNUSED(RTCx);
03854   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U);
03855 }
03856 #endif /* RTC_TAMP_INT_8_SUPPORT */
03857
03858 #if 0
03859 /**
03860   * @brief  Get internal tamper 9 detection flag.
03861   * @rmtoll TAMP_SR          ITAMP9F        LL_RTC_IsActiveFlag_ITAMP9
03862   * @param  RTCx RTC Instance
03863   * @retval State of bit (1 or 0).
03864   */
03865 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx)
03866 {
03867   UNUSED(RTCx);
03868   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U);
03869 }
03870
03871 /**
03872   * @brief  Get internal tamper 10 detection flag.
03873   * @rmtoll TAMP_SR          ITAMP10F        LL_RTC_IsActiveFlag_ITAMP10
03874   * @param  RTCx RTC Instance
03875   * @retval State of bit (1 or 0).
03876   */
03877 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP10(RTC_TypeDef *RTCx)
03878 {
03879   UNUSED(RTCx);
03880   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP10F) == (TAMP_SR_ITAMP10F)) ? 1U : 0U);
03881 }
03882
03883 /**
03884   * @brief  Get internal tamper 11 detection flag.
03885   * @rmtoll TAMP_SR          ITAMP11F        LL_RTC_IsActiveFlag_ITAMP11
03886   * @param  RTCx RTC Instance
03887   * @retval State of bit (1 or 0).
03888   */
03889 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx)
03890 {
03891   UNUSED(RTCx);
03892   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U);
03893 }
03894
03895 /**
03896   * @brief  Get internal tamper 12 detection flag.
03897   * @rmtoll TAMP_SR          ITAMP7F        LL_RTC_IsActiveFlag_ITAMP12
03898   * @param  RTCx RTC Instance
03899   * @retval State of bit (1 or 0).
03900   */
03901 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx)
03902 {
03903   UNUSED(RTCx);
03904   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U);
03905 }
03906
03907 /**
03908   * @brief  Get internal tamper 13 detection flag.
03909   * @rmtoll TAMP_SR          ITAMP13F        LL_RTC_IsActiveFlag_ITAMP13
03910   * @param  RTCx RTC Instance
03911   * @retval State of bit (1 or 0).
03912   */
03913 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx)
03914 {
03915   UNUSED(RTCx);
03916   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U);
03917 }
03918
03919 /**
03920   * @brief  Get internal tamper 14 detection flag.
03921   * @rmtoll TAMP_SR          ITAMP14F        LL_RTC_IsActiveFlag_ITAMP14
03922   * @param  RTCx RTC Instance
03923   * @retval State of bit (1 or 0).
03924   */
03925 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP14(RTC_TypeDef *RTCx)
03926 {
03927   UNUSED(RTCx);
03928   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP14F) == (TAMP_SR_ITAMP14F)) ? 1U : 0U);
03929 }
03930
03931 /**
03932   * @brief  Get internal tamper 15 detection flag.
03933   * @rmtoll TAMP_SR          ITAMP15F        LL_RTC_IsActiveFlag_ITAMP15
03934   * @param  RTCx RTC Instance
03935   * @retval State of bit (1 or 0).
03936   */
03937 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP15(RTC_TypeDef *RTCx)
03938 {
03939   UNUSED(RTCx);
03940   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP15F) == (TAMP_SR_ITAMP15F)) ? 1U : 0U);
03941 }
03942
03943 /**
03944   * @brief  Get internal tamper 16 detection flag.
03945   * @rmtoll TAMP_SR          ITAMP7F        LL_RTC_IsActiveFlag_ITAMP16
03946   * @param  RTCx RTC Instance
03947   * @retval State of bit (1 or 0).
03948   */
03949 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP16(RTC_TypeDef *RTCx)
03950 {
03951   UNUSED(RTCx);
03952   return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP16F) == (TAMP_SR_ITAMP16F)) ? 1U : 0U);
03953 }
03954 #endif /*  0 */
03955
03956 /**
03957   * @brief  Get tamper 1 interrupt masked flag.
03958   * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M
03959   * @param  RTCx RTC Instance
03960   * @retval State of bit (1 or 0).
03961   */
03962 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx)
03963 {
03964   UNUSED(RTCx);
03965   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U);
03966 }
03967
03968 /**
03969   * @brief  Get tamper 2 interrupt masked flag.
03970   * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M
03971   * @param  RTCx RTC Instance
03972   * @retval State of bit (1 or 0).
03973   */
03974 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx)
03975 {
03976   UNUSED(RTCx);
03977   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U);
03978 }
03979
03980 #if (RTC_TAMP_NB ==3)
03981 /**
03982   * @brief  Get tamper 3 interrupt masked flag.
03983   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
03984   * @param  RTCx RTC Instance
03985   * @retval State of bit (1 or 0).
03986   */
03987 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
03988 {
03989   UNUSED(RTCx);
03990   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
03991 }
03992 #elif (RTC_TAMP_NB==8)
03993 /**
03994   * @brief  Get tamper 3 interrupt masked flag.
03995   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
03996   * @param  RTCx RTC Instance
03997   * @retval State of bit (1 or 0).
03998   */
03999 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
04000 {
04001   UNUSED(RTCx);
04002   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
04003 }
04004 /**
04005   * @brief  Get tamper 4 interrupt masked flag.
04006   * @rmtoll TAMP_MISR          TAMP4MF        LL_RTC_IsActiveFlag_TAMP4M
04007   * @param  RTCx RTC Instance
04008   * @retval State of bit (1 or 0).
04009   */
04010 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx)
04011 {
04012   UNUSED(RTCx);
04013   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U);
04014 }
04015 /**
04016   * @brief  Get tamper 5 interrupt masked flag.
04017   * @rmtoll TAMP_MISR          TAMP5MF        LL_RTC_IsActiveFlag_TAMP5M
04018   * @param  RTCx RTC Instance
04019   * @retval State of bit (1 or 0).
04020   */
04021 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx)
04022 {
04023   UNUSED(RTCx);
04024   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U);
04025 }
04026 /**
04027   * @brief  Get tamper 6 interrupt masked flag.
04028   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP6M
04029   * @param  RTCx RTC Instance
04030   * @retval State of bit (1 or 0).
04031   */
04032 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx)
04033 {
04034   UNUSED(RTCx);
04035   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U);
04036 }
04037 /**
04038   * @brief  Get tamper 7 interrupt masked flag.
04039   * @rmtoll TAMP_MISR          TAMP7MF        LL_RTC_IsActiveFlag_TAMP7M
04040   * @param  RTCx RTC Instance
04041   * @retval State of bit (1 or 0).
04042   */
04043 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx)
04044 {
04045   UNUSED(RTCx);
04046   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U);
04047 }
04048 /**
04049   * @brief  Get tamper 8 interrupt masked flag.
04050   * @rmtoll TAMP_MISR          TAMP8MF        LL_RTC_IsActiveFlag_TAMP8M
04051   * @param  RTCx RTC Instance
04052   * @retval State of bit (1 or 0).
04053   */
04054 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx)
04055 {
04056   UNUSED(RTCx);
04057   return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U);
04058 }
04059 #endif /* RTC_TAMP_NB */
04060
04061 #if defined (RTC_TAMP_INT_1_SUPPORT)
04062 /**
04063   * @brief  Get internal tamper 1 interrupt masked flag.
04064   * @rmtoll TAMP_MISR          ITAMP1MF        LL_RTC_IsActiveFlag_ITAMP1M
04065   * @param  RTCx RTC Instance
04066   * @retval State of bit (1 or 0).
04067   */
04068 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx)
04069 {
04070   UNUSED(RTCx);
04071   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U);
04072 }
04073
04074 #endif /* RTC_TAMP_INT_1_SUPPORT */
04075 #if defined (RTC_TAMP_INT_2_SUPPORT)
04076 /**
04077   * @brief  Get internal tamper 2 interrupt masked flag.
04078   * @rmtoll TAMP_MISR          ITAMP2MF        LL_RTC_IsActiveFlag_ITAMP2M
04079   * @param  RTCx RTC Instance
04080   * @retval State of bit (1 or 0).
04081   */
04082 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx)
04083 {
04084   UNUSED(RTCx);
04085   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U);
04086 }
04087
04088 #endif /* RTC_TAMP_INT_2_SUPPORT */
04089 /**
04090   * @brief  Get internal tamper 3 interrupt masked flag.
04091   * @rmtoll TAMP_MISR          ITAMP3MF        LL_RTC_IsActiveFlag_ITAMP3M
04092   * @param  RTCx RTC Instance
04093   * @retval State of bit (1 or 0).
04094   */
04095 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx)
04096 {
04097   UNUSED(RTCx);
04098   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U);
04099 }
04100
04101 /**
04102   * @brief  Get internal tamper 4 interrupt masked flag.
04103   * @rmtoll TAMP_MISR          ITAMP4MF        LL_RTC_IsActiveFlag_ITAMP4M
04104   * @param  RTCx RTC Instance
04105   * @retval State of bit (1 or 0).
04106   */
04107 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(RTC_TypeDef *RTCx)
04108 {
04109   UNUSED(RTCx);
04110   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1U : 0U);
04111 }
04112
04113 /**
04114   * @brief  Get internal tamper 5 interrupt masked flag.
04115   * @rmtoll TAMP_MISR          ITAMP5MF        LL_RTC_IsActiveFlag_ITAMP5M
04116   * @param  RTCx RTC Instance
04117   * @retval State of bit (1 or 0).
04118   */
04119 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx)
04120 {
04121   UNUSED(RTCx);
04122   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U);
04123 }
04124
04125 #if defined (RTC_TAMP_INT_6_SUPPORT)
04126 /**
04127   * @brief  Get internal tamper 6 interrupt masked flag.
04128   * @rmtoll TAMP_MISR          ITAMP6MF        LL_RTC_IsActiveFlag_ITAMP6M
04129   * @param  RTCx RTC Instance
04130   * @retval State of bit (1 or 0).
04131   */
04132 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef *RTCx)
04133 {
04134   UNUSED(RTCx);
04135   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U);
04136 }
04137 #endif /* RTC_TAMP_INT_6_SUPPORT */
04138
04139 #if defined (RTC_TAMP_INT_7_SUPPORT)
04140 /**
04141   * @brief  Get internal tamper 7 interrupt masked flag.
04142   * @rmtoll TAMP_MISR          ITAMP7MF        LL_RTC_IsActiveFlag_ITAMP7M
04143   * @param  RTCx RTC Instance
04144   * @retval State of bit (1 or 0).
04145   */
04146 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7M(RTC_TypeDef *RTCx)
04147 {
04148   UNUSED(RTCx);
04149   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP7MF) == (TAMP_MISR_ITAMP7MF)) ? 1U : 0U);
04150 }
04151 #endif /* RTC_TAMP_INT_7_SUPPORT */
04152
04153 #if defined (RTC_TAMP_INT_8_SUPPORT)
04154 /**
04155   * @brief  Get internal tamper 8 interrupt masked flag.
04156   * @rmtoll TAMP_MISR          ITAMP8MF        LL_RTC_IsActiveFlag_ITAMP8M
04157   * @param  RTCx RTC Instance
04158   * @retval State of bit (1 or 0).
04159   */
04160 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx)
04161 {
04162   UNUSED(RTCx);
04163   return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U);
04164 }
04165 #endif /* RTC_TAMP_INT_8_SUPPORT */
04166
04167 /**
04168   * @brief  Clear tamper 1 detection flag.
04169   * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1
04170   * @param  RTCx RTC Instance
04171   * @retval None
04172   */
04173 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
04174 {
04175   UNUSED(RTCx);
04176   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP1F);
04177 }
04178
04179 /**
04180   * @brief  Clear tamper 2 detection flag.
04181   * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2
04182   * @param  RTCx RTC Instance
04183   * @retval None
04184   */
04185 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
04186 {
04187   UNUSED(RTCx);
04188   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP2F);
04189 }
04190
04191 #if (RTC_TAMP_NB == 3)
04192 /**
04193   * @brief  Clear tamper 3 detection flag.
04194   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
04195   * @param  RTCx RTC Instance
04196   * @retval None
04197   */
04198 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
04199 {
04200   UNUSED(RTCx);
04201   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
04202 }
04203 #elif (RTC_TAMP_NB == 8)
04204 /**
04205   * @brief  Clear tamper 3 detection flag.
04206   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
04207   * @param  RTCx RTC Instance
04208   * @retval None
04209   */
04210 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
04211 {
04212   UNUSED(RTCx);
04213   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
04214 }
04215 /**
04216   * @brief  Clear tamper 4 detection flag.
04217   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP4
04218   * @param  RTCx RTC Instance
04219   * @retval None
04220   */
04221 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx)
04222 {
04223   UNUSED(RTCx);
04224   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP4F);
04225 }
04226 /**
04227   * @brief  Clear tamper 5 detection flag.
04228   * @rmtoll TAMP_SCR          CTAMP5F         LL_RTC_ClearFlag_TAMP5
04229   * @param  RTCx RTC Instance
04230   * @retval None
04231   */
04232 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx)
04233 {
04234   UNUSED(RTCx);
04235   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP5F);
04236 }
04237 /**
04238   * @brief  Clear tamper 6 detection flag.
04239   * @rmtoll TAMP_SCR          CTAMP6F         LL_RTC_ClearFlag_TAMP6
04240   * @param  RTCx RTC Instance
04241   * @retval None
04242   */
04243 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx)
04244 {
04245   UNUSED(RTCx);
04246   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP6F);
04247 }
04248 /**
04249   * @brief  Clear tamper 7 detection flag.
04250   * @rmtoll TAMP_SCR          CTAMP7F         LL_RTC_ClearFlag_TAMP7
04251   * @param  RTCx RTC Instance
04252   * @retval None
04253   */
04254 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx)
04255 {
04256   UNUSED(RTCx);
04257   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP7F);
04258 }
04259 /**
04260   * @brief  Clear tamper 8 detection flag.
04261   * @rmtoll TAMP_SCR          CTAMP8F         LL_RTC_ClearFlag_TAMP8
04262   * @param  RTCx RTC Instance
04263   * @retval None
04264   */
04265 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx)
04266 {
04267   UNUSED(RTCx);
04268   SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP8F);
04269 }
04270
04271 #endif /* RTC_TAMP_NB */
04272
04273 #if defined (RTC_TAMP_INT_1_SUPPORT)
04274 /**
04275   * @brief  Clear internal tamper 1 detection flag.
04276   * @rmtoll TAMP_SCR          CITAMP1F         LL_RTC_ClearFlag_ITAMP1
04277   * @param  RTCx RTC Instance
04278   * @retval None
04279   */
04280 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx)
04281 {
04282   UNUSED(RTCx);
04283   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP1F);
04284 }
04285
04286 #endif /* RTC_TAMP_INT_1_SUPPORT */
04287 #if defined (RTC_TAMP_INT_2_SUPPORT)
04288 /**
04289   * @brief  Clear internal tamper 2 detection flag.
04290   * @rmtoll TAMP_SCR          CITAMP2F         LL_RTC_ClearFlag_ITAMP2
04291   * @param  RTCx RTC Instance
04292   * @retval None
04293   */
04294 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx)
04295 {
04296   UNUSED(RTCx);
04297   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP2F);
04298 }
04299
04300 #endif /* RTC_TAMP_INT_2_SUPPORT */
04301 /**
04302   * @brief  Clear internal tamper 3 detection flag.
04303   * @rmtoll TAMP_SCR          CITAMP3F         LL_RTC_ClearFlag_ITAMP3
04304   * @param  RTCx RTC Instance
04305   * @retval None
04306   */
04307 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx)
04308 {
04309   UNUSED(RTCx);
04310   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP3F);
04311 }
04312
04313 /**
04314   * @brief  Clear internal tamper 4 detection flag.
04315   * @rmtoll TAMP_SCR          CITAMP4F         LL_RTC_ClearFlag_ITAMP4
04316   * @param  RTCx RTC Instance
04317   * @retval None
04318   */
04319 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(RTC_TypeDef *RTCx)
04320 {
04321   UNUSED(RTCx);
04322   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP4F);
04323 }
04324
04325 /**
04326   * @brief  Clear internal tamper 5 detection flag.
04327   * @rmtoll TAMP_SCR          CITAMP5F         LL_RTC_ClearFlag_ITAMP5
04328   * @param  RTCx RTC Instance
04329   * @retval None
04330   */
04331 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx)
04332 {
04333   UNUSED(RTCx);
04334   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP5F);
04335 }
04336
04337 #if defined (RTC_TAMP_INT_6_SUPPORT)
04338 /**
04339   * @brief  Clear internal tamper 6 detection flag.
04340   * @rmtoll TAMP_SCR          CITAMP6F         LL_RTC_ClearFlag_ITAMP6
04341   * @param  RTCx RTC Instance
04342   * @retval None
04343   */
04344 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef *RTCx)
04345 {
04346   UNUSED(RTCx);
04347   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP6F);
04348 }
04349 #endif /* (RTC_TAMP_INT_2_SUPPORT)*/
04350
04351 #if defined (RTC_TAMP_INT_7_SUPPORT)
04352 /**
04353   * @brief  Clear internal tamper 7 detection flag.
04354   * @rmtoll TAMP_SCR          CITAMP7F         LL_RTC_ClearFlag_ITAMP7
04355   * @param  RTCx RTC Instance
04356   * @retval None
04357   */
04358 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP7(RTC_TypeDef *RTCx)
04359 {
04360   UNUSED(RTCx);
04361   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP7F);
04362 }
04363 #endif /* (RTC_TAMP_INT_7_SUPPORT) */
04364
04365 #if defined (RTC_TAMP_INT_8_SUPPORT)
04366 /**
04367   * @brief  Clear internal tamper 8 detection flag.
04368   * @rmtoll TAMP_SCR          CITAMP8F         LL_RTC_ClearFlag_ITAMP8
04369   * @param  RTCx RTC Instance
04370   * @retval None
04371   */
04372 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx)
04373 {
04374   UNUSED(RTCx);
04375   SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP8F);
04376 }
04377 #endif /* (RTC_TAMP_INT_8_SUPPORT) */
04378
04379 /**
04380   * @}
04381   */
04382
04383 /** @defgroup RTC_LL_EF_IT_Management IT_Management
04384   * @{
04385   */
04386
04387 /**
04388   * @brief  Enable Time-stamp interrupt
04389   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04390   * @rmtoll RTC_CR          LL_RTC_EnableIT_TS
04391   * @param  RTCx RTC Instance
04392   * @retval None
04393   */
04394 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
04395 {
04396   SET_BIT(RTCx->CR, RTC_CR_TSIE);
04397 }
04398
04399 /**
04400   * @brief  Disable Time-stamp interrupt
04401   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04402   * @rmtoll RTC_CR          LL_RTC_DisableIT_TS
04403   * @param  RTCx RTC Instance
04404   * @retval None
04405   */
04406 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
04407 {
04408   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
04409 }
04410
04411 /**
04412   * @brief  Enable Wakeup timer interrupt
04413   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04414   * @rmtoll RTC_CR         LL_RTC_EnableIT_WUT
04415   * @param  RTCx RTC Instance
04416   * @retval None
04417   */
04418 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
04419 {
04420   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
04421 }
04422
04423 /**
04424   * @brief  Disable Wakeup timer interrupt
04425   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04426   * @rmtoll RTC_CR         LL_RTC_DisableIT_WUT
04427   * @param  RTCx RTC Instance
04428   * @retval None
04429   */
04430 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
04431 {
04432   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
04433 }
04434
04435 /**
04436   * @brief  Enable Alarm B interrupt
04437   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04438   * @rmtoll RTC_CR           ALRBIE        LL_RTC_EnableIT_ALRB
04439   * @param  RTCx RTC Instance
04440   * @retval None
04441   */
04442 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
04443 {
04444   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
04445 }
04446
04447 /**
04448   * @brief  Disable Alarm B interrupt
04449   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04450   * @rmtoll RTC_CR           ALRBIE        LL_RTC_DisableIT_ALRB
04451   * @param  RTCx RTC Instance
04452   * @retval None
04453   */
04454 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
04455 {
04456   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
04457 }
04458
04459 /**
04460   * @brief  Enable Alarm A interrupt
04461   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04462   * @rmtoll RTC_CR           ALRAIE        LL_RTC_EnableIT_ALRA
04463   * @param  RTCx RTC Instance
04464   * @retval None
04465   */
04466 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
04467 {
04468   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
04469 }
04470
04471 /**
04472   * @brief  Disable Alarm A interrupt
04473   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
04474   * @rmtoll RTC_CR           ALRAIE        LL_RTC_DisableIT_ALRA
04475   * @param  RTCx RTC Instance
04476   * @retval None
04477   */
04478 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
04479 {
04480   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
04481 }
04482
04483 /**
04484   * @brief  Check if Time-stamp interrupt is enabled or not
04485   * @rmtoll RTC_CR           TSIE          LL_RTC_IsEnabledIT_TS
04486   * @param  RTCx RTC Instance
04487   * @retval State of bit (1 or 0).
04488   */
04489 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
04490 {
04491   return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
04492 }
04493
04494 /**
04495   * @brief  Check if Wakeup timer interrupt is enabled or not
04496   * @rmtoll RTC_CR           WUTIE         LL_RTC_IsEnabledIT_WUT
04497   * @param  RTCx RTC Instance
04498   * @retval State of bit (1 or 0).
04499   */
04500 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
04501 {
04502   return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
04503 }
04504
04505 /**
04506   * @brief  Check if Alarm B interrupt is enabled or not
04507   * @rmtoll RTC_CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
04508   * @param  RTCx RTC Instance
04509   * @retval State of bit (1 or 0).
04510   */
04511 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
04512 {
04513   return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
04514 }
04515
04516 /**
04517   * @brief  Check if Alarm A interrupt is enabled or not
04518   * @rmtoll RTC_CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
04519   * @param  RTCx RTC Instance
04520   * @retval State of bit (1 or 0).
04521   */
04522 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
04523 {
04524   return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
04525 }
04526
04527 /**
04528   * @brief  Enable tamper 1 interrupt.
04529   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1
04530   * @param  RTCx RTC Instance
04531   * @retval None
04532   */
04533 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
04534 {
04535   UNUSED(RTCx);
04536   SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
04537 }
04538
04539 /**
04540   * @brief  Disable tamper 1 interrupt.
04541   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_TAMP1
04542   * @param  RTCx RTC Instance
04543   * @retval None
04544   */
04545 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
04546 {
04547   UNUSED(RTCx);
04548   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
04549 }
04550
04551 /**
04552   * @brief  Enable tamper 2 interrupt.
04553   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2
04554   * @param  RTCx RTC Instance
04555   * @retval None
04556   */
04557 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
04558 {
04559   UNUSED(RTCx);
04560   SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
04561 }
04562
04563 /**
04564   * @brief  Disable tamper 2 interrupt.
04565   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_TAMP2
04566   * @param  RTCx RTC Instance
04567   * @retval None
04568   */
04569 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
04570 {
04571   UNUSED(RTCx);
04572   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
04573 }
04574
04575 #if (RTC_TAMP_NB == 3)
04576 /**
04577   * @brief  Enable tamper 3 interrupt.
04578   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
04579   * @param  RTCx RTC Instance
04580   * @retval None
04581   */
04582 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
04583 {
04584   UNUSED(RTCx);
04585   SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
04586 }
04587 /**
04588   * @brief  Disable tamper 3 interrupt.
04589   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3
04590   * @param  RTCx RTC Instance
04591   * @retval None
04592   */
04593 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
04594 {
04595   UNUSED(RTCx);
04596   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
04597 }
04598 #elif (RTC_TAMP_NB == 8)
04599 /**
04600   * @brief  Enable tamper 3 interrupt.
04601   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
04602   * @param  RTCx RTC Instance
04603   * @retval None
04604   */
04605 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
04606 {
04607   UNUSED(RTCx);
04608   SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
04609 }
04610 /**
04611   * @brief  Disable tamper 3 interrupt.
04612   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3
04613   * @param  RTCx RTC Instance
04614   * @retval None
04615   */
04616 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
04617 {
04618   UNUSED(RTCx);
04619   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
04620 }
04621 /**
04622   * @brief  Enable tamper 4 interrupt.
04623   * @rmtoll TAMP_IER           TAMP4IE          LL_RTC_EnableIT_TAMP4
04624   * @param  RTCx RTC Instance
04625   * @retval None
04626   */
04627 __STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx)
04628 {
04629   UNUSED(RTCx);
04630   SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
04631 }
04632 /**
04633   * @brief  Disable tamper 4 interrupt.
04634   * @rmtoll TAMP_IER           TAMP4IE          LL_RTC_DisableIT_TAMP4
04635   * @param  RTCx RTC Instance
04636   * @retval None
04637   */
04638 __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx)
04639 {
04640   UNUSED(RTCx);
04641   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
04642 }
04643
04644 /**
04645   * @brief  Enable tamper 5 interrupt.
04646   * @rmtoll TAMP_IER           TAMP5IE          LL_RTC_EnableIT_TAMP5
04647   * @param  RTCx RTC Instance
04648   * @retval None
04649   */
04650 __STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx)
04651 {
04652   UNUSED(RTCx);
04653   SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
04654 }
04655 /**
04656   * @brief  Disable tamper 5 interrupt.
04657   * @rmtoll TAMP_IER           TAMP5IE          LL_RTC_DisableIT_TAMP5
04658   * @param  RTCx RTC Instance
04659   * @retval None
04660   */
04661 __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx)
04662 {
04663   UNUSED(RTCx);
04664   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
04665 }
04666
04667 /**
04668   * @brief  Enable tamper 6 interrupt.
04669   * @rmtoll TAMP_IER           TAMP6IE          LL_RTC_EnableIT_TAMP6
04670   * @param  RTCx RTC Instance
04671   * @retval None
04672   */
04673 __STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx)
04674 {
04675   UNUSED(RTCx);
04676   SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
04677 }
04678 /**
04679   * @brief  Disable tamper 6 interrupt.
04680   * @rmtoll TAMP_IER           TAMP6IE          LL_RTC_DisableIT_TAMP6
04681   * @param  RTCx RTC Instance
04682   * @retval None
04683   */
04684 __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx)
04685 {
04686   UNUSED(RTCx);
04687   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
04688 }
04689
04690 /**
04691   * @brief  Enable tamper 7 interrupt.
04692   * @rmtoll TAMP_IER           TAMP7IE          LL_RTC_EnableIT_TAMP7
04693   * @param  RTCx RTC Instance
04694   * @retval None
04695   */
04696 __STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx)
04697 {
04698   UNUSED(RTCx);
04699   SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
04700 }
04701 /**
04702   * @brief  Disable tamper 7 interrupt.
04703   * @rmtoll TAMP_IER           TAMP7IE          LL_RTC_DisableIT_TAMP7
04704   * @param  RTCx RTC Instance
04705   * @retval None
04706   */
04707 __STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx)
04708 {
04709   UNUSED(RTCx);
04710   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
04711 }
04712
04713 /**
04714   * @brief  Enable tamper 8 interrupt.
04715   * @rmtoll TAMP_IER           TAMP8IE          LL_RTC_EnableIT_TAMP8
04716   * @param  RTCx RTC Instance
04717   * @retval None
04718   */
04719 __STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx)
04720 {
04721   UNUSED(RTCx);
04722   SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
04723 }
04724 /**
04725   * @brief  Disable tamper 8 interrupt.
04726   * @rmtoll TAMP_IER           TAMP8IE          LL_RTC_DisableIT_TAMP8
04727   * @param  RTCx RTC Instance
04728   * @retval None
04729   */
04730 __STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx)
04731 {
04732   UNUSED(RTCx);
04733   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
04734 }
04735 #endif /* RTC_TAMP_NB */
04736
04737 #if 0
04738 /**
04739   * @brief  Enable tamper 92 interrupt.
04740   * @rmtoll TAMP_IER           TAMP9IE          LL_RTC_EnableIT_TAMP9
04741   * @param  RTCx RTC Instance
04742   * @retval None
04743   */
04744 __STATIC_INLINE void LL_RTC_EnableIT_TAMP9(RTC_TypeDef *RTCx)
04745 {
04746   UNUSED(RTCx);
04747   SET_BIT(TAMP->IER, TAMP_IER_TAMP9IE);
04748 }
04749
04750 /**
04751   * @brief  Disable tamper 9 interrupt.
04752   * @rmtoll TAMP_IER           TAMP9IE          LL_RTC_DisableIT_TAMP9
04753   * @param  RTCx RTC Instance
04754   * @retval None
04755   */
04756 __STATIC_INLINE void LL_RTC_DisableIT_TAMP9(RTC_TypeDef *RTCx)
04757 {
04758   UNUSED(RTCx);
04759   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP9IE);
04760 }
04761 /**
04762   * @brief  Enable tamper 10 interrupt.
04763   * @rmtoll TAMP_IER           TAMP10IE          LL_RTC_EnableIT_TAMP10
04764   * @param  RTCx RTC Instance
04765   * @retval None
04766   */
04767 __STATIC_INLINE void LL_RTC_EnableIT_TAMP10(RTC_TypeDef *RTCx)
04768 {
04769   UNUSED(RTCx);
04770   SET_BIT(TAMP->IER, TAMP_IER_TAMP10IE);
04771 }
04772
04773 /**
04774   * @brief  Disable tamper 10 interrupt.
04775   * @rmtoll TAMP_IER           TAMP10IE          LL_RTC_DisableIT_TAMP10
04776   * @param  RTCx RTC Instance
04777   * @retval None
04778   */
04779 __STATIC_INLINE void LL_RTC_DisableIT_TAMP10(RTC_TypeDef *RTCx)
04780 {
04781   UNUSED(RTCx);
04782   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP10IE);
04783 }
04784 /**
04785   * @brief  Enable tamper 11 interrupt.
04786   * @rmtoll TAMP_IER           TAMP11IE          LL_RTC_EnableIT_TAMP11
04787   * @param  RTCx RTC Instance
04788   * @retval None
04789   */
04790 __STATIC_INLINE void LL_RTC_EnableIT_TAMP11(RTC_TypeDef *RTCx)
04791 {
04792   UNUSED(RTCx);
04793   SET_BIT(TAMP->IER, TAMP_IER_TAMP11IE);
04794 }
04795
04796 /**
04797   * @brief  Disable tamper 11 interrupt.
04798   * @rmtoll TAMP_IER           TAMP11IE          LL_RTC_DisableIT_TAMP11
04799   * @param  RTCx RTC Instance
04800   * @retval None
04801   */
04802 __STATIC_INLINE void LL_RTC_DisableIT_TAMP11(RTC_TypeDef *RTCx)
04803 {
04804   UNUSED(RTCx);
04805   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP11IE);
04806 }
04807 /**
04808   * @brief  Enable tamper 12 interrupt.
04809   * @rmtoll TAMP_IER           TAMP12IE          LL_RTC_EnableIT_TAMP12
04810   * @param  RTCx RTC Instance
04811   * @retval None
04812   */
04813 __STATIC_INLINE void LL_RTC_EnableIT_TAMP12(RTC_TypeDef *RTCx)
04814 {
04815   UNUSED(RTCx);
04816   SET_BIT(TAMP->IER, TAMP_IER_TAMP12IE);
04817 }
04818
04819 /**
04820   * @brief  Disable tamper 12 interrupt.
04821   * @rmtoll TAMP_IER           TAMP12IE          LL_RTC_DisableIT_TAMP12
04822   * @param  RTCx RTC Instance
04823   * @retval None
04824   */
04825 __STATIC_INLINE void LL_RTC_DisableIT_TAMP12(RTC_TypeDef *RTCx)
04826 {
04827   UNUSED(RTCx);
04828   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP12IE);
04829 }
04830 /**
04831   * @brief  Enable tamper 13 interrupt.
04832   * @rmtoll TAMP_IER           TAMP13IE          LL_RTC_EnableIT_TAMP13
04833   * @param  RTCx RTC Instance
04834   * @retval None
04835   */
04836 __STATIC_INLINE void LL_RTC_EnableIT_TAMP13(RTC_TypeDef *RTCx)
04837 {
04838   UNUSED(RTCx);
04839   SET_BIT(TAMP->IER, TAMP_IER_TAMP13IE);
04840 }
04841
04842 /**
04843   * @brief  Disable tamper 13 interrupt.
04844   * @rmtoll TAMP_IER           TAMP13IE          LL_RTC_DisableIT_TAMP13
04845   * @param  RTCx RTC Instance
04846   * @retval None
04847   */
04848 __STATIC_INLINE void LL_RTC_DisableIT_TAMP13(RTC_TypeDef *RTCx)
04849 {
04850   UNUSED(RTCx);
04851   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP13IE);
04852 }
04853 /**
04854   * @brief  Enable tamper 14 interrupt.
04855   * @rmtoll TAMP_IER           TAMP14IE          LL_RTC_EnableIT_TAMP14
04856   * @param  RTCx RTC Instance
04857   * @retval None
04858   */
04859 __STATIC_INLINE void LL_RTC_EnableIT_TAMP14(RTC_TypeDef *RTCx)
04860 {
04861   UNUSED(RTCx);
04862   SET_BIT(TAMP->IER, TAMP_IER_TAMP14IE);
04863 }
04864
04865 /**
04866   * @brief  Disable tamper 14 interrupt.
04867   * @rmtoll TAMP_IER           TAMP14IE          LL_RTC_DisableIT_TAMP14
04868   * @param  RTCx RTC Instance
04869   * @retval None
04870   */
04871 __STATIC_INLINE void LL_RTC_DisableIT_TAMP14(RTC_TypeDef *RTCx)
04872 {
04873   UNUSED(RTCx);
04874   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP14IE);
04875 }
04876 /**
04877   * @brief  Enable tamper 15 interrupt.
04878   * @rmtoll TAMP_IER           TAMP15IE          LL_RTC_EnableIT_TAMP15
04879   * @param  RTCx RTC Instance
04880   * @retval None
04881   */
04882 __STATIC_INLINE void LL_RTC_EnableIT_TAMP15(RTC_TypeDef *RTCx)
04883 {
04884   UNUSED(RTCx);
04885   SET_BIT(TAMP->IER, TAMP_IER_TAMP15IE);
04886 }
04887
04888 /**
04889   * @brief  Disable tamper 15 interrupt.
04890   * @rmtoll TAMP_IER           TAMP15IE          LL_RTC_DisableIT_TAMP15
04891   * @param  RTCx RTC Instance
04892   * @retval None
04893   */
04894 __STATIC_INLINE void LL_RTC_DisableIT_TAMP15(RTC_TypeDef *RTCx)
04895 {
04896   UNUSED(RTCx);
04897   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP15IE);
04898 }
04899 /**
04900   * @brief  Enable tamper 16 interrupt.
04901   * @rmtoll TAMP_IER           TAMP16IE          LL_RTC_EnableIT_TAMP16
04902   * @param  RTCx RTC Instance
04903   * @retval None
04904   */
04905 __STATIC_INLINE void LL_RTC_EnableIT_TAMP16(RTC_TypeDef *RTCx)
04906 {
04907   UNUSED(RTCx);
04908   SET_BIT(TAMP->IER, TAMP_IER_TAMP16IE);
04909 }
04910
04911 /**
04912   * @brief  Disable tamper 16 interrupt.
04913   * @rmtoll TAMP_IER           TAMP16IE          LL_RTC_DisableIT_TAMP16
04914   * @param  RTCx RTC Instance
04915   * @retval None
04916   */
04917 __STATIC_INLINE void LL_RTC_DisableIT_TAMP16(RTC_TypeDef *RTCx)
04918 {
04919   UNUSED(RTCx);
04920   CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP16IE);
04921 }
04922 #endif /* 0 */
04923
04924 #if defined (RTC_TAMP_INT_1_SUPPORT)
04925 /**
04926   * @brief  Enable internal tamper 1 interrupt.
04927   * @rmtoll TAMP_IER           ITAMP1IE          LL_RTC_EnableIT_ITAMP1
04928   * @param  RTCx RTC Instance
04929   * @retval None
04930   */
04931 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx)
04932 {
04933   UNUSED(RTCx);
04934   SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
04935 }
04936 /**
04937   * @brief  Disable internal tamper 1 interrupt.
04938   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_ITAMP1
04939   * @param  RTCx RTC Instance
04940   * @retval None
04941   */
04942 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx)
04943 {
04944   UNUSED(RTCx);
04945   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
04946 }
04947 #endif /* RTC_TAMP_INT_1_SUPPORT */
04948
04949 #if defined (RTC_TAMP_INT_2_SUPPORT)
04950 /**
04951   * @brief  Enable internal tamper 2 interrupt.
04952   * @rmtoll TAMP_IER           ITAMP2IE          LL_RTC_EnableIT_ITAMP2
04953   * @param  RTCx RTC Instance
04954   * @retval None
04955   */
04956 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx)
04957 {
04958   UNUSED(RTCx);
04959   SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
04960 }
04961 /**
04962   * @brief  Disable internal tamper 2 interrupt.
04963   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_ITAMP2
04964   * @param  RTCx RTC Instance
04965   * @retval None
04966   */
04967 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx)
04968 {
04969   UNUSED(RTCx);
04970   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
04971 }
04972 #endif /* RTC_TAMP_INT_2_SUPPORT */
04973
04974 /**
04975   * @brief  Enable internal tamper 3 interrupt.
04976   * @rmtoll TAMP_IER           ITAMP3IE          LL_RTC_EnableIT_ITAMP3
04977   * @param  RTCx RTC Instance
04978   * @retval None
04979   */
04980 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx)
04981 {
04982   UNUSED(RTCx);
04983   SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
04984 }
04985 /**
04986   * @brief  Disable internal tamper 3 interrupt.
04987   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_ITAMP3
04988   * @param  RTCx RTC Instance
04989   * @retval None
04990   */
04991 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx)
04992 {
04993   UNUSED(RTCx);
04994   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
04995 }
04996
04997 /**
04998   * @brief  Enable internal tamper 4 interrupt.
04999   * @rmtoll TAMP_IER           ITAMP4IE          LL_RTC_EnableIT_ITAMP4
05000   * @param  RTCx RTC Instance
05001   * @retval None
05002   */
05003 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(RTC_TypeDef *RTCx)
05004 {
05005   UNUSED(RTCx);
05006   SET_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
05007 }
05008 /**
05009   * @brief  Disable internal tamper 4 interrupt.
05010   * @rmtoll TAMP_IER           TAMP4IE          LL_RTC_DisableIT_ITAMP4
05011   * @param  RTCx RTC Instance
05012   * @retval None
05013   */
05014 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(RTC_TypeDef *RTCx)
05015 {
05016   UNUSED(RTCx);
05017   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
05018 }
05019
05020 /**
05021   * @brief  Enable internal tamper 5 interrupt.
05022   * @rmtoll TAMP_IER           ITAMP5IE          LL_RTC_EnableIT_ITAMP5
05023   * @param  RTCx RTC Instance
05024   * @retval None
05025   */
05026 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx)
05027 {
05028   UNUSED(RTCx);
05029   SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
05030 }
05031 /**
05032   * @brief  Disable internal tamper 5 interrupt.
05033   * @rmtoll TAMP_IER           TAMP5IE          LL_RTC_DisableIT_ITAMP5
05034   * @param  RTCx RTC Instance
05035   * @retval None
05036   */
05037 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx)
05038 {
05039   UNUSED(RTCx);
05040   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
05041 }
05042 #if defined (RTC_TAMP_INT_6_SUPPORT)
05043
05044 /**
05045   * @brief  Enable internal tamper 6 interrupt.
05046   * @rmtoll TAMP_IER           ITAMP6IE          LL_RTC_EnableIT_ITAMP6
05047   * @param  RTCx RTC Instance
05048   * @retval None
05049   */
05050 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx)
05051 {
05052   UNUSED(RTCx);
05053   SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
05054 }
05055 /**
05056   * @brief  Disable internal tamper 6 interrupt.
05057   * @rmtoll TAMP_IER           TAMP6IE          LL_RTC_DisableIT_ITAMP6
05058   * @param  RTCx RTC Instance
05059   * @retval None
05060   */
05061 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx)
05062 {
05063   UNUSED(RTCx);
05064   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
05065 }
05066 #endif /* (RTC_TAMP_INT_2_SUPPORT) */
05067
05068 #if defined (RTC_TAMP_INT_7_SUPPORT)
05069
05070 /**
05071   * @brief  Enable internal tamper 7 interrupt.
05072   * @rmtoll TAMP_IER           ITAMP7IE          LL_RTC_EnableIT_ITAMP7
05073   * @param  RTCx RTC Instance
05074   * @retval None
05075   */
05076 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx)
05077 {
05078   UNUSED(RTCx);
05079   SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
05080 }
05081 /**
05082   * @brief  Disable internal tamper 7 interrupt.
05083   * @rmtoll TAMP_IER           TAMP7IE          LL_RTC_DisableIT_ITAMP7
05084   * @param  RTCx RTC Instance
05085   * @retval None
05086   */
05087 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx)
05088 {
05089   UNUSED(RTCx);
05090   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
05091 }
05092 #endif /* (RTC_TAMP_INT_7_SUPPORT)*/
05093
05094 #if defined (RTC_TAMP_INT_8_SUPPORT)
05095
05096 /**
05097   * @brief  Enable internal tamper 8 interrupt.
05098   * @rmtoll TAMP_IER           ITAMP8IE          LL_RTC_EnableIT_ITAMP8
05099   * @param  RTCx RTC Instance
05100   * @retval None
05101   */
05102 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx)
05103 {
05104   UNUSED(RTCx);
05105   SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
05106 }
05107 /**
05108   * @brief  Disable internal tamper 8 interrupt.
05109   * @rmtoll TAMP_IER           TAMP8IE          LL_RTC_DisableIT_ITAMP8
05110   * @param  RTCx RTC Instance
05111   * @retval None
05112   */
05113 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx)
05114 {
05115   UNUSED(RTCx);
05116   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
05117 }
05118 #endif /* (RTC_TAMP_INT_8_SUPPORT)*/
05119
05120 #if 0
05121 /**
05122   * @brief  Enable internal tamper 9 interrupt.
05123   * @rmtoll TAMP_IER           ITAMP7IE          LL_RTC_EnableIT_ITAMP9
05124   * @param  RTCx RTC Instance
05125   * @retval None
05126   */
05127 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx)
05128 {
05129   UNUSED(RTCx);
05130   SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
05131 }
05132 /**
05133   * @brief  Disable internal tamper 9 interrupt.
05134   * @rmtoll TAMP_IER           TAMP9IE          LL_RTC_DisableIT_ITAMP9
05135   * @param  RTCx RTC Instance
05136   * @retval None
05137   */
05138 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx)
05139 {
05140   UNUSED(RTCx);
05141   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
05142 }
05143
05144 /**
05145   * @brief  Enable internal tamper 10 interrupt.
05146   * @rmtoll TAMP_IER           ITAMP10IE          LL_RTC_EnableIT_ITAMP10
05147   * @param  RTCx RTC Instance
05148   * @retval None
05149   */
05150 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP10(RTC_TypeDef *RTCx)
05151 {
05152   UNUSED(RTCx);
05153   SET_BIT(TAMP->IER, TAMP_IER_ITAMP10IE);
05154 }
05155 /**
05156   * @brief  Disable internal tamper 10 interrupt.
05157   * @rmtoll TAMP_IER           TAMP10IE          LL_RTC_DisableIT_ITAMP10
05158   * @param  RTCx RTC Instance
05159   * @retval None
05160   */
05161 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP10(RTC_TypeDef *RTCx)
05162 {
05163   UNUSED(RTCx);
05164   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP10IE);
05165 }
05166
05167 /**
05168   * @brief  Enable internal tamper 11 interrupt.
05169   * @rmtoll TAMP_IER           ITAMP11IE          LL_RTC_EnableIT_ITAMP11
05170   * @param  RTCx RTC Instance
05171   * @retval None
05172   */
05173 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx)
05174 {
05175   UNUSED(RTCx);
05176   SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
05177 }
05178 /**
05179   * @brief  Disable internal tamper 11 interrupt.
05180   * @rmtoll TAMP_IER           TAMP11IE          LL_RTC_DisableIT_ITAMP11
05181   * @param  RTCx RTC Instance
05182   * @retval None
05183   */
05184 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(RTC_TypeDef *RTCx)
05185 {
05186   UNUSED(RTCx);
05187   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
05188 }
05189
05190 /**
05191   * @brief  Enable internal tamper 12 interrupt.
05192   * @rmtoll TAMP_IER           ITAMP12IE          LL_RTC_EnableIT_ITAMP12
05193   * @param  RTCx RTC Instance
05194   * @retval None
05195   */
05196 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx)
05197 {
05198   UNUSED(RTCx);
05199   SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
05200 }
05201 /**
05202   * @brief  Disable internal tamper 12 interrupt.
05203   * @rmtoll TAMP_IER           TAMP12IE          LL_RTC_DisableIT_ITAMP12
05204   * @param  RTCx RTC Instance
05205   * @retval None
05206   */
05207 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx)
05208 {
05209   UNUSED(RTCx);
05210   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
05211 }
05212
05213 /**
05214   * @brief  Enable internal tamper 13 interrupt.
05215   * @rmtoll TAMP_IER           ITAMP13IE          LL_RTC_EnableIT_ITAMP13
05216   * @param  RTCx RTC Instance
05217   * @retval None
05218   */
05219 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx)
05220 {
05221   UNUSED(RTCx);
05222   SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
05223 }
05224 /**
05225   * @brief  Disable internal tamper 13 interrupt.
05226   * @rmtoll TAMP_IER           TAMP13IE          LL_RTC_DisableIT_ITAMP13
05227   * @param  RTCx RTC Instance
05228   * @retval None
05229   */
05230 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx)
05231 {
05232   UNUSED(RTCx);
05233   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
05234 }
05235
05236 /**
05237   * @brief  Enable internal tamper 14 interrupt.
05238   * @rmtoll TAMP_IER           ITAMP14IE          LL_RTC_EnableIT_ITAMP14
05239   * @param  RTCx RTC Instance
05240   * @retval None
05241   */
05242 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP14(RTC_TypeDef *RTCx)
05243 {
05244   UNUSED(RTCx);
05245   SET_BIT(TAMP->IER, TAMP_IER_ITAMP14IE);
05246 }
05247 /**
05248   * @brief  Disable internal tamper 14 interrupt.
05249   * @rmtoll TAMP_IER           TAMP14IE          LL_RTC_DisableIT_ITAMP14
05250   * @param  RTCx RTC Instance
05251   * @retval None
05252   */
05253 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP14(RTC_TypeDef *RTCx)
05254 {
05255   UNUSED(RTCx);
05256   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP14IE);
05257 }
05258
05259 /**
05260   * @brief  Enable internal tamper 15 interrupt.
05261   * @rmtoll TAMP_IER           ITAMP15IE          LL_RTC_EnableIT_ITAMP15
05262   * @param  RTCx RTC Instance
05263   * @retval None
05264   */
05265 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP15(RTC_TypeDef *RTCx)
05266 {
05267   UNUSED(RTCx);
05268   SET_BIT(TAMP->IER, TAMP_IER_ITAMP15IE);
05269 }
05270 /**
05271   * @brief  Disable internal tamper 15 interrupt.
05272   * @rmtoll TAMP_IER           TAMP15IE          LL_RTC_DisableIT_ITAMP15
05273   * @param  RTCx RTC Instance
05274   * @retval None
05275   */
05276 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP15(RTC_TypeDef *RTCx)
05277 {
05278   UNUSED(RTCx);
05279   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP15IE);
05280 }
05281
05282 /**
05283   * @brief  Enable internal tamper 16 interrupt.
05284   * @rmtoll TAMP_IER           ITAMP16IE          LL_RTC_EnableIT_ITAMP16
05285   * @param  RTCx RTC Instance
05286   * @retval None
05287   */
05288 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP16(RTC_TypeDef *RTCx)
05289 {
05290   UNUSED(RTCx);
05291   SET_BIT(TAMP->IER, TAMP_IER_ITAMP16IE);
05292 }
05293 /**
05294   * @brief  Disable internal tamper 16 interrupt.
05295   * @rmtoll TAMP_IER           TAMP16IE          LL_RTC_DisableIT_ITAMP16
05296   * @param  RTCx RTC Instance
05297   * @retval None
05298   */
05299 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP16(RTC_TypeDef *RTCx)
05300 {
05301   UNUSED(RTCx);
05302   CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP16IE);
05303 }
05304 #endif /* 0 */
05305
05306 /**
05307   * @brief  Check if tamper 1 interrupt is enabled or not.
05308   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1
05309   * @param  RTCx RTC Instance
05310   * @retval State of bit (1 or 0).
05311   */
05312 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
05313 {
05314   UNUSED(RTCx);
05315   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U);
05316 }
05317
05318 /**
05319   * @brief  Check if tamper 2 interrupt is enabled or not.
05320   * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2
05321   * @param  RTCx RTC Instance
05322   * @retval State of bit (1 or 0).
05323   */
05324 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
05325 {
05326   UNUSED(RTCx);
05327   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U);
05328 }
05329
05330 #if (RTC_TAMP_NB == 3)
05331
05332 /**
05333   * @brief  Check if tamper 3 interrupt is enabled or not.
05334   * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
05335   * @param  RTCx RTC Instance
05336   * @retval State of bit (1 or 0).
05337   */
05338 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
05339 {
05340   UNUSED(RTCx);
05341   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
05342 }
05343 #elif (RTC_TAMP_NB == 8)
05344
05345 /**
05346   * @brief  Check if tamper 3 interrupt is enabled or not.
05347   * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
05348   * @param  RTCx RTC Instance
05349   * @retval State of bit (1 or 0).
05350   */
05351 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
05352 {
05353   UNUSED(RTCx);
05354   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
05355 }
05356 /**
05357   * @brief  Check if tamper 4 interrupt is enabled or not.
05358   * @rmtoll TAMP_IER           TAMP4IE        LL_RTC_IsEnabledIT_TAMP4
05359   * @param  RTCx RTC Instance
05360   * @retval State of bit (1 or 0).
05361   */
05362 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx)
05363 {
05364   UNUSED(RTCx);
05365   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U);
05366 }
05367 /**
05368   * @brief  Check if tamper 5 interrupt is enabled or not.
05369   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP5
05370   * @param  RTCx RTC Instance
05371   * @retval State of bit (1 or 0).
05372   */
05373 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx)
05374 {
05375   UNUSED(RTCx);
05376   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U);
05377 }
05378 /**
05379   * @brief  Check if tamper 6 interrupt is enabled or not.
05380   * @rmtoll TAMP_IER           TAMP6IE        LL_RTC_IsEnabledIT_TAMP6
05381   * @param  RTCx RTC Instance
05382   * @retval State of bit (1 or 0).
05383   */
05384 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx)
05385 {
05386   UNUSED(RTCx);
05387   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U);
05388 }
05389 /**
05390   * @brief  Check if tamper 7 interrupt is enabled or not.
05391   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP7
05392   * @param  RTCx RTC Instance
05393   * @retval State of bit (1 or 0).
05394   */
05395 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx)
05396 {
05397   UNUSED(RTCx);
05398   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U);
05399 }
05400 /**
05401   * @brief  Check if tamper 8 interrupt is enabled or not.
05402   * @rmtoll TAMP_IER           TAMP8IE        LL_RTC_IsEnabledIT_TAMP8
05403   * @param  RTCx RTC Instance
05404   * @retval State of bit (1 or 0).
05405   */
05406 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx)
05407 {
05408   UNUSED(RTCx);
05409   return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U);
05410 }
05411
05412 #endif /* RTC_TAMP_NB */
05413
05414
05415 #if defined (RTC_TAMP_INT_1_SUPPORT)
05416 /**
05417   * @brief  Check if internal tamper 1 interrupt is enabled or not.
05418   * @rmtoll TAMP_IER           ITAMP1IE        LL_RTC_IsEnabledIT_ITAMP1
05419   * @param  RTCx RTC Instance
05420   * @retval State of bit (1 or 0).
05421   */
05422 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx)
05423 {
05424   UNUSED(RTCx);
05425   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U);
05426 }
05427 #endif /* RTC_TAMP_INT_1_SUPPORT */
05428 #if defined (RTC_TAMP_INT_2_SUPPORT)
05429
05430 /**
05431   * @brief  Check if internal tamper 2 interrupt is enabled or not.
05432   * @rmtoll TAMP_IER           ITAMP2IE        LL_RTC_IsEnabledIT_ITAMP2
05433   * @param  RTCx RTC Instance
05434   * @retval State of bit (1 or 0).
05435   */
05436 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx)
05437 {
05438   UNUSED(RTCx);
05439   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U);
05440 }
05441 #endif /* RTC_TAMP_INT_2_SUPPORT */
05442
05443 /**
05444   * @brief  Check if internal tamper 3 interrupt is enabled or not.
05445   * @rmtoll TAMP_IER           ITAMP3IE        LL_RTC_IsEnabledIT_ITAMP3
05446   * @param  RTCx RTC Instance
05447   * @retval State of bit (1 or 0).
05448   */
05449 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx)
05450 {
05451   UNUSED(RTCx);
05452   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U);
05453 }
05454 /**
05455   * @brief  Check if internal tamper 4 interrupt is enabled or not.
05456   * @rmtoll TAMP_IER           ITAMP4IE        LL_RTC_IsEnabledIT_ITAMP4
05457   * @param  RTCx RTC Instance
05458   * @retval State of bit (1 or 0).
05459   */
05460 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(RTC_TypeDef *RTCx)
05461 {
05462   UNUSED(RTCx);
05463   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1U : 0U);
05464 }
05465
05466 /**
05467   * @brief  Check if internal tamper 5 interrupt is enabled or not.
05468   * @rmtoll TAMP_IER           ITAMP5IE        LL_RTC_IsEnabledIT_ITAMP5
05469   * @param  RTCx RTC Instance
05470   * @retval State of bit (1 or 0).
05471   */
05472 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx)
05473 {
05474   UNUSED(RTCx);
05475   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U);
05476 }
05477
05478 #if defined (RTC_TAMP_INT_6_SUPPORT)
05479 /**
05480   * @brief  Check if internal tamper 6 interrupt is enabled or not.
05481   * @rmtoll TAMP_IER           ITAMP6IE        LL_RTC_IsEnabledIT_ITAMP6
05482   * @param  RTCx RTC Instance
05483   * @retval State of bit (1 or 0).
05484   */
05485 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx)
05486 {
05487   UNUSED(RTCx);
05488   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U);
05489 }
05490 #endif /* RTC_TAMP_INT_6_SUPPORT */
05491
05492
05493 #if defined (RTC_TAMP_INT_7_SUPPORT)
05494
05495 /**
05496   * @brief  Check if internal tamper 7 interrupt is enabled or not.
05497   * @rmtoll TAMP_IER           ITAMP7IE        LL_RTC_IsEnabledIT_ITAMP7
05498   * @param  RTCx RTC Instance
05499   * @retval State of bit (1 or 0).
05500   */
05501 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
05502 {
05503   UNUSED(RTCx);
05504   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
05505 }
05506 #endif /* RTC_TAMP_INT_7_SUPPORT */
05507
05508 #if defined (RTC_TAMP_INT_8_SUPPORT)
05509
05510 /**
05511   * @brief  Check if internal tamper 7 interrupt is enabled or not.
05512   * @rmtoll TAMP_IER           ITAMP7IE        LL_RTC_IsEnabledIT_ITAMP7
05513   * @param  RTCx RTC Instance
05514   * @retval State of bit (1 or 0).
05515   */
05516 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
05517 {
05518   UNUSED(RTCx);
05519   return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
05520 }
05521 #endif /* RTC_TAMP_INT_8_SUPPORT */
05522
05523 /**
05524   * @}
05525   */
05526
05527 #if defined(USE_FULL_LL_DRIVER)
05528 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
05529   * @{
05530   */
05531
05532 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
05533 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
05534 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
05535 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
05536 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
05537 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
05538 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
05539 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05540 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05541 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05542 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
05543 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
05544 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
05545 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
05546
05547 /**
05548   * @}
05549   */
05550 #endif /* USE_FULL_LL_DRIVER */
05551
05552 /**
05553   * @}
05554   */
05555
05556 /**
05557   * @}
05558   */
05559
05560 #endif /* defined(RTC) */
05561
05562 /**
05563   * @}
05564   */
05565
05566 #ifdef __cplusplus
05567 }
05568 #endif
05569
05570 #endif /* STM32G4xx_LL_RTC_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_spi.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_spi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_spi.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #include "stm32g4xx_ll_rcc.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32G4xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
00036
00037 /** @addtogroup SPI_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00046   * @{
00047   */
00048 /* SPI registers Masks */
00049 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00050                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00051                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
00052                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00053                                             SPI_CR1_BIDIMODE)
00054 /**
00055   * @}
00056   */
00057
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00060   * @{
00061   */
00062 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
00063                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00064                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00065                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00066
00067 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00068                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00069
00070 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
00071                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
00072                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
00073                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
00074                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00075                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
00076                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
00077                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
00078                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
00079                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
00080                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
00081                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
00082                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00083
00084 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00085                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00086
00087 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00088                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00089
00090 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
00091                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00092                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00093
00094 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
00095                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00096                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00097                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00098                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00099                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00100                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00101                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00102
00103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00104                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
00105
00106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00107                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00108
00109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Private function prototypes -----------------------------------------------*/
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @addtogroup SPI_LL_Exported_Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup SPI_LL_EF_Init
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  De-initialize the SPI registers to their default reset values.
00128   * @param  SPIx SPI Instance
00129   * @retval An ErrorStatus enumeration value:
00130   *          - SUCCESS: SPI registers are de-initialized
00131   *          - ERROR: SPI registers are not de-initialized
00132   */
00133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00134 {
00135   ErrorStatus status = ERROR;
00136
00137   /* Check the parameters */
00138   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00139
00140 #if defined(SPI1)
00141   if (SPIx == SPI1)
00142   {
00143     /* Force reset of SPI clock */
00144     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00145
00146     /* Release reset of SPI clock */
00147     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00148
00149     status = SUCCESS;
00150   }
00151 #endif /* SPI1 */
00152 #if defined(SPI2)
00153   if (SPIx == SPI2)
00154   {
00155     /* Force reset of SPI clock */
00156     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00157
00158     /* Release reset of SPI clock */
00159     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00160
00161     status = SUCCESS;
00162   }
00163 #endif /* SPI2 */
00164 #if defined(SPI3)
00165   if (SPIx == SPI3)
00166   {
00167     /* Force reset of SPI clock */
00168     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00169
00170     /* Release reset of SPI clock */
00171     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00172
00173     status = SUCCESS;
00174   }
00175 #endif /* SPI3 */
00176 #if defined(SPI4)
00177   if (SPIx == SPI4)
00178   {
00179     /* Force reset of SPI clock */
00180     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
00181
00182     /* Release reset of SPI clock */
00183     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
00184
00185     status = SUCCESS;
00186   }
00187 #endif /* SPI4 */
00188
00189   return status;
00190 }
00191
00192 /**
00193   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00194   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00195   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00196   * @param  SPIx SPI Instance
00197   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00198   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00199   */
00200 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00201 {
00202   ErrorStatus status = ERROR;
00203
00204   /* Check the SPI Instance SPIx*/
00205   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00206
00207   /* Check the SPI parameters from SPI_InitStruct*/
00208   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00209   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00210   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00211   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00212   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00213   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00214   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00215   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00216   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00217
00218   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00219   {
00220     /*---------------------------- SPIx CR1 Configuration ------------------------
00221      * Configure SPIx CR1 with parameters:
00222      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00223      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00224      * - ClockPolarity:      SPI_CR1_CPOL bit
00225      * - ClockPhase:         SPI_CR1_CPHA bit
00226      * - NSS management:     SPI_CR1_SSM bit
00227      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00228      * - BitOrder:           SPI_CR1_LSBFIRST bit
00229      * - CRCCalculation:     SPI_CR1_CRCEN bit
00230      */
00231     MODIFY_REG(SPIx->CR1,
00232                SPI_CR1_CLEAR_MASK,
00233                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
00234                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00235                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00236                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00237
00238     /*---------------------------- SPIx CR2 Configuration ------------------------
00239      * Configure SPIx CR2 with parameters:
00240      * - DataWidth:          DS[3:0] bits
00241      * - NSS management:     SSOE bit
00242      */
00243     MODIFY_REG(SPIx->CR2,
00244                SPI_CR2_DS | SPI_CR2_SSOE,
00245                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
00246
00247     /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
00248     if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
00249     {
00250       LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
00251     }
00252
00253     /*---------------------------- SPIx CRCPR Configuration ----------------------
00254      * Configure SPIx CRCPR with parameters:
00255      * - CRCPoly:            CRCPOLY[15:0] bits
00256      */
00257     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00258     {
00259       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00260       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00261     }
00262     status = SUCCESS;
00263   }
00264
00265 #if defined (SPI_I2S_SUPPORT)
00266   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00267   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00268 #endif /* SPI_I2S_SUPPORT */
00269   return status;
00270 }
00271
00272 /**
00273   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00274   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00275   * whose fields will be set to default values.
00276   * @retval None
00277   */
00278 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00279 {
00280   /* Set SPI_InitStruct fields to default values */
00281   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00282   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00283   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00284   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00285   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00286   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00287   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00288   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00289   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00290   SPI_InitStruct->CRCPoly           = 7U;
00291 }
00292
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 #if defined(SPI_I2S_SUPPORT)
00306 /** @addtogroup I2S_LL
00307   * @{
00308   */
00309
00310 /* Private types -------------------------------------------------------------*/
00311 /* Private variables ---------------------------------------------------------*/
00312 /* Private constants ---------------------------------------------------------*/
00313 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
00314   * @{
00315   */
00316 /* I2S registers Masks */
00317 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
00318                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
00319                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
00320
00321 #define I2S_I2SPR_CLEAR_MASK               0x0002U
00322 /**
00323   * @}
00324   */
00325 /* Private macros ------------------------------------------------------------*/
00326 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
00327   * @{
00328   */
00329
00330 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
00331                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
00332                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
00333                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
00334
00335 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
00336                                           || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
00337
00338 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
00339                                           || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
00340                                           || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
00341                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
00342                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
00343
00344 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
00345                                           || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
00346                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
00347                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
00348
00349 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
00350                                           || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
00351
00352 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
00353                                           && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
00354                                          || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
00355
00356 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
00357
00358 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
00359                                                || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
00360 /**
00361   * @}
00362   */
00363
00364 /* Private function prototypes -----------------------------------------------*/
00365
00366 /* Exported functions --------------------------------------------------------*/
00367 /** @addtogroup I2S_LL_Exported_Functions
00368   * @{
00369   */
00370
00371 /** @addtogroup I2S_LL_EF_Init
00372   * @{
00373   */
00374
00375 /**
00376   * @brief  De-initialize the SPI/I2S registers to their default reset values.
00377   * @param  SPIx SPI Instance
00378   * @retval An ErrorStatus enumeration value:
00379   *          - SUCCESS: SPI registers are de-initialized
00380   *          - ERROR: SPI registers are not de-initialized
00381   */
00382 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
00383 {
00384   return LL_SPI_DeInit(SPIx);
00385 }
00386
00387 /**
00388   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
00389   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00390   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00391   * @param  SPIx SPI Instance
00392   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00393   * @retval An ErrorStatus enumeration value:
00394   *          - SUCCESS: SPI registers are Initialized
00395   *          - ERROR: SPI registers are not Initialized
00396   */
00397 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
00398 {
00399   uint32_t i2sdiv = 2U;
00400   uint32_t i2sodd = 0U;
00401   uint32_t packetlength = 1U;
00402   uint32_t tmp;
00403   uint32_t sourceclock;
00404   ErrorStatus status = ERROR;
00405
00406   /* Check the I2S parameters */
00407   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00408   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00409   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00410   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00411   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
00412   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
00413   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
00414
00415   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
00416   {
00417     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00418      * Configure SPIx I2SCFGR with parameters:
00419      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
00420      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00421      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
00422      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
00423      */
00424
00425     /* Write to SPIx I2SCFGR */
00426     MODIFY_REG(SPIx->I2SCFGR,
00427                I2S_I2SCFGR_CLEAR_MASK,
00428                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
00429                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00430                SPI_I2SCFGR_I2SMOD);
00431
00432     /*---------------------------- SPIx I2SPR Configuration ----------------------
00433      * Configure SPIx I2SPR with parameters:
00434      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
00435      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
00436      */
00437
00438     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
00439      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
00440      */
00441     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
00442     {
00443       /* Check the frame length (For the Prescaler computing)
00444        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
00445        */
00446       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
00447       {
00448         /* Packet length is 32 bits */
00449         packetlength = 2U;
00450       }
00451
00452       /* If an external I2S clock has to be used, the specific define should be set
00453       in the project configuration or in the stm32g4xx_ll_rcc.h file */
00454       /* Get the I2S source clock value */
00455       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
00456
00457       /* Compute the Real divider depending on the MCLK output state with a floating point */
00458       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
00459       {
00460         /* MCLK output is enabled */
00461         tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00462       }
00463       else
00464       {
00465         /* MCLK output is disabled */
00466         tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00467       }
00468
00469       /* Remove the floating point */
00470       tmp = tmp / 10U;
00471
00472       /* Check the parity of the divider */
00473       i2sodd = (tmp & (uint16_t)0x0001U);
00474
00475       /* Compute the i2sdiv prescaler */
00476       i2sdiv = ((tmp - i2sodd) / 2U);
00477
00478       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00479       i2sodd = (i2sodd << 8U);
00480     }
00481
00482     /* Test if the divider is 1 or 0 or greater than 0xFF */
00483     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00484     {
00485       /* Set the default values */
00486       i2sdiv = 2U;
00487       i2sodd = 0U;
00488     }
00489
00490     /* Write to SPIx I2SPR register the computed value */
00491     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
00492
00493     status = SUCCESS;
00494   }
00495   return status;
00496 }
00497
00498 /**
00499   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
00500   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00501   *         whose fields will be set to default values.
00502   * @retval None
00503   */
00504 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
00505 {
00506   /*--------------- Reset I2S init structure parameters values -----------------*/
00507   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
00508   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
00509   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
00510   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
00511   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
00512   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
00513 }
00514
00515 /**
00516   * @brief  Set linear and parity prescaler.
00517   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
00518   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
00519   * @param  SPIx SPI Instance
00520   * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
00521   * @param  PrescalerParity This parameter can be one of the following values:
00522   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00523   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00524   * @retval None
00525   */
00526 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
00527 {
00528   /* Check the I2S parameters */
00529   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00530   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
00531   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
00532
00533   /* Write to SPIx I2SPR */
00534   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
00535 }
00536
00537 /**
00538   * @}
00539   */
00540
00541 /**
00542   * @}
00543   */
00544
00545 /**
00546   * @}
00547   */
00548 #endif /* SPI_I2S_SUPPORT */
00549
00550 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
00551
00552 /**
00553   * @}
00554   */
00555
00556 #endif /* USE_FULL_LL_DRIVER */
00557
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_spi.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_spi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_SPI_H
00021 #define STM32G4xx_LL_SPI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
00035
00036 /** @defgroup SPI_LL SPI
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  SPI Init structures definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00056                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00057
00058                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00059
00060   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00061                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00062
00063                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00064
00065   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00066                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00067
00068                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00069
00070   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00071                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00072
00073                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00074
00075   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00076                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00077
00078                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00079
00080   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00081                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00082
00083                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00084
00085   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00086                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00087                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00088
00089                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00090
00091   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00092                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00093
00094                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00095
00096   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00097                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00098
00099                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00100
00101   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00102                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00103
00104                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00105
00106 } LL_SPI_InitTypeDef;
00107
00108 /**
00109   * @}
00110   */
00111 #endif /* USE_FULL_LL_DRIVER */
00112
00113 /* Exported constants --------------------------------------------------------*/
00114 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00115   * @{
00116   */
00117
00118 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00119   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00120   * @{
00121   */
00122 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00123 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00124 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00125 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00126 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00127 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00128 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup SPI_LL_EC_IT IT Defines
00134   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00135   * @{
00136   */
00137 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00138 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00139 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup SPI_LL_EC_MODE Operation Mode
00145   * @{
00146   */
00147 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00148 #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
00154   * @{
00155   */
00156 #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
00157 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00163   * @{
00164   */
00165 #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
00166 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00172   * @{
00173   */
00174 #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
00175 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00181   * @{
00182   */
00183 #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
00184 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00185 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00186 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00187 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00188 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00189 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00190 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00196   * @{
00197   */
00198 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00199 #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00205   * @{
00206   */
00207 #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00208 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00209 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00210 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00216   * @{
00217   */
00218 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00219 #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
00220 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00226   * @{
00227   */
00228 #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
00229 #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
00230 #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
00231 #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
00232 #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
00233 #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
00234 #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
00235 #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
00236 #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
00237 #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
00238 #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
00239 #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
00240 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
00241 /**
00242   * @}
00243   */
00244 #if defined(USE_FULL_LL_DRIVER)
00245
00246 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00247   * @{
00248   */
00249 #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
00250 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
00251 /**
00252   * @}
00253   */
00254 #endif /* USE_FULL_LL_DRIVER */
00255
00256 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
00257   * @{
00258   */
00259 #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
00260 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
00266   * @{
00267   */
00268 #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
00269 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
00275   * @{
00276   */
00277 #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
00278 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
00279 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
00280 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
00286   * @{
00287   */
00288 #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
00289 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
00290 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
00291 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
00297   * @{
00298   */
00299 #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
00300 #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /* Exported macro ------------------------------------------------------------*/
00311 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00312   * @{
00313   */
00314
00315 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  Write a value in SPI register
00321   * @param  __INSTANCE__ SPI Instance
00322   * @param  __REG__ Register to be written
00323   * @param  __VALUE__ Value to be written in the register
00324   * @retval None
00325   */
00326 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00327
00328 /**
00329   * @brief  Read a value in SPI register
00330   * @param  __INSTANCE__ SPI Instance
00331   * @param  __REG__ Register to be read
00332   * @retval Register value
00333   */
00334 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Exported functions --------------------------------------------------------*/
00344 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00345   * @{
00346   */
00347
00348 /** @defgroup SPI_LL_EF_Configuration Configuration
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Enable SPI peripheral
00354   * @rmtoll CR1          SPE           LL_SPI_Enable
00355   * @param  SPIx SPI Instance
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00359 {
00360   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00361 }
00362
00363 /**
00364   * @brief  Disable SPI peripheral
00365   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00366   * @rmtoll CR1          SPE           LL_SPI_Disable
00367   * @param  SPIx SPI Instance
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00371 {
00372   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00373 }
00374
00375 /**
00376   * @brief  Check if SPI peripheral is enabled
00377   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00378   * @param  SPIx SPI Instance
00379   * @retval State of bit (1 or 0).
00380   */
00381 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00382 {
00383   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
00384 }
00385
00386 /**
00387   * @brief  Set SPI operation mode to Master or Slave
00388   * @note   This bit should not be changed when communication is ongoing.
00389   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00390   *         CR1          SSI           LL_SPI_SetMode
00391   * @param  SPIx SPI Instance
00392   * @param  Mode This parameter can be one of the following values:
00393   *         @arg @ref LL_SPI_MODE_MASTER
00394   *         @arg @ref LL_SPI_MODE_SLAVE
00395   * @retval None
00396   */
00397 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00398 {
00399   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00400 }
00401
00402 /**
00403   * @brief  Get SPI operation mode (Master or Slave)
00404   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00405   *         CR1          SSI           LL_SPI_GetMode
00406   * @param  SPIx SPI Instance
00407   * @retval Returned value can be one of the following values:
00408   *         @arg @ref LL_SPI_MODE_MASTER
00409   *         @arg @ref LL_SPI_MODE_SLAVE
00410   */
00411 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00412 {
00413   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00414 }
00415
00416 /**
00417   * @brief  Set serial protocol used
00418   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00419   * @rmtoll CR2          FRF           LL_SPI_SetStandard
00420   * @param  SPIx SPI Instance
00421   * @param  Standard This parameter can be one of the following values:
00422   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00423   *         @arg @ref LL_SPI_PROTOCOL_TI
00424   * @retval None
00425   */
00426 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00427 {
00428   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
00429 }
00430
00431 /**
00432   * @brief  Get serial protocol used
00433   * @rmtoll CR2          FRF           LL_SPI_GetStandard
00434   * @param  SPIx SPI Instance
00435   * @retval Returned value can be one of the following values:
00436   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00437   *         @arg @ref LL_SPI_PROTOCOL_TI
00438   */
00439 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
00440 {
00441   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
00442 }
00443
00444 /**
00445   * @brief  Set clock phase
00446   * @note   This bit should not be changed when communication is ongoing.
00447   *         This bit is not used in SPI TI mode.
00448   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00449   * @param  SPIx SPI Instance
00450   * @param  ClockPhase This parameter can be one of the following values:
00451   *         @arg @ref LL_SPI_PHASE_1EDGE
00452   *         @arg @ref LL_SPI_PHASE_2EDGE
00453   * @retval None
00454   */
00455 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00456 {
00457   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00458 }
00459
00460 /**
00461   * @brief  Get clock phase
00462   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00463   * @param  SPIx SPI Instance
00464   * @retval Returned value can be one of the following values:
00465   *         @arg @ref LL_SPI_PHASE_1EDGE
00466   *         @arg @ref LL_SPI_PHASE_2EDGE
00467   */
00468 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00469 {
00470   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00471 }
00472
00473 /**
00474   * @brief  Set clock polarity
00475   * @note   This bit should not be changed when communication is ongoing.
00476   *         This bit is not used in SPI TI mode.
00477   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00478   * @param  SPIx SPI Instance
00479   * @param  ClockPolarity This parameter can be one of the following values:
00480   *         @arg @ref LL_SPI_POLARITY_LOW
00481   *         @arg @ref LL_SPI_POLARITY_HIGH
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00485 {
00486   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00487 }
00488
00489 /**
00490   * @brief  Get clock polarity
00491   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00492   * @param  SPIx SPI Instance
00493   * @retval Returned value can be one of the following values:
00494   *         @arg @ref LL_SPI_POLARITY_LOW
00495   *         @arg @ref LL_SPI_POLARITY_HIGH
00496   */
00497 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00498 {
00499   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00500 }
00501
00502 /**
00503   * @brief  Set baud rate prescaler
00504   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00505   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00506   * @param  SPIx SPI Instance
00507   * @param  BaudRate This parameter can be one of the following values:
00508   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00509   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00510   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00511   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00512   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00513   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00514   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00515   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00516   * @retval None
00517   */
00518 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00519 {
00520   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00521 }
00522
00523 /**
00524   * @brief  Get baud rate prescaler
00525   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00526   * @param  SPIx SPI Instance
00527   * @retval Returned value can be one of the following values:
00528   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00529   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00530   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00531   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00532   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00533   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00534   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00535   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00536   */
00537 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00538 {
00539   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00540 }
00541
00542 /**
00543   * @brief  Set transfer bit order
00544   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00545   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00546   * @param  SPIx SPI Instance
00547   * @param  BitOrder This parameter can be one of the following values:
00548   *         @arg @ref LL_SPI_LSB_FIRST
00549   *         @arg @ref LL_SPI_MSB_FIRST
00550   * @retval None
00551   */
00552 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00553 {
00554   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00555 }
00556
00557 /**
00558   * @brief  Get transfer bit order
00559   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00560   * @param  SPIx SPI Instance
00561   * @retval Returned value can be one of the following values:
00562   *         @arg @ref LL_SPI_LSB_FIRST
00563   *         @arg @ref LL_SPI_MSB_FIRST
00564   */
00565 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00566 {
00567   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00568 }
00569
00570 /**
00571   * @brief  Set transfer direction mode
00572   * @note   For Half-Duplex mode, Rx Direction is set by default.
00573   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00574   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00575   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00576   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00577   * @param  SPIx SPI Instance
00578   * @param  TransferDirection This parameter can be one of the following values:
00579   *         @arg @ref LL_SPI_FULL_DUPLEX
00580   *         @arg @ref LL_SPI_SIMPLEX_RX
00581   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00582   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00583   * @retval None
00584   */
00585 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00586 {
00587   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00588 }
00589
00590 /**
00591   * @brief  Get transfer direction mode
00592   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00593   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00594   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00595   * @param  SPIx SPI Instance
00596   * @retval Returned value can be one of the following values:
00597   *         @arg @ref LL_SPI_FULL_DUPLEX
00598   *         @arg @ref LL_SPI_SIMPLEX_RX
00599   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00600   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00601   */
00602 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00603 {
00604   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00605 }
00606
00607 /**
00608   * @brief  Set frame data width
00609   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
00610   * @param  SPIx SPI Instance
00611   * @param  DataWidth This parameter can be one of the following values:
00612   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00613   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00614   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00615   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00616   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00617   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00618   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00619   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00620   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00621   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00622   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00623   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00624   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00628 {
00629   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
00630 }
00631
00632 /**
00633   * @brief  Get frame data width
00634   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
00635   * @param  SPIx SPI Instance
00636   * @retval Returned value can be one of the following values:
00637   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00638   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00639   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00640   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00641   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00642   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00643   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00644   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00645   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00646   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00647   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00648   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00649   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00650   */
00651 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00652 {
00653   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
00654 }
00655
00656 /**
00657   * @brief  Set threshold of RXFIFO that triggers an RXNE event
00658   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
00659   * @param  SPIx SPI Instance
00660   * @param  Threshold This parameter can be one of the following values:
00661   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00662   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
00666 {
00667   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
00668 }
00669
00670 /**
00671   * @brief  Get threshold of RXFIFO that triggers an RXNE event
00672   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
00673   * @param  SPIx SPI Instance
00674   * @retval Returned value can be one of the following values:
00675   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00676   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00677   */
00678 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
00679 {
00680   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
00681 }
00682
00683 /**
00684   * @}
00685   */
00686
00687 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00688   * @{
00689   */
00690
00691 /**
00692   * @brief  Enable CRC
00693   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00694   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00695   * @param  SPIx SPI Instance
00696   * @retval None
00697   */
00698 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00699 {
00700   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00701 }
00702
00703 /**
00704   * @brief  Disable CRC
00705   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00706   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00707   * @param  SPIx SPI Instance
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00711 {
00712   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00713 }
00714
00715 /**
00716   * @brief  Check if CRC is enabled
00717   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00718   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00719   * @param  SPIx SPI Instance
00720   * @retval State of bit (1 or 0).
00721   */
00722 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00723 {
00724   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
00725 }
00726
00727 /**
00728   * @brief  Set CRC Length
00729   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00730   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
00731   * @param  SPIx SPI Instance
00732   * @param  CRCLength This parameter can be one of the following values:
00733   *         @arg @ref LL_SPI_CRC_8BIT
00734   *         @arg @ref LL_SPI_CRC_16BIT
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
00738 {
00739   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
00740 }
00741
00742 /**
00743   * @brief  Get CRC Length
00744   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
00745   * @param  SPIx SPI Instance
00746   * @retval Returned value can be one of the following values:
00747   *         @arg @ref LL_SPI_CRC_8BIT
00748   *         @arg @ref LL_SPI_CRC_16BIT
00749   */
00750 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
00751 {
00752   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
00753 }
00754
00755 /**
00756   * @brief  Set CRCNext to transfer CRC on the line
00757   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00758   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00759   * @param  SPIx SPI Instance
00760   * @retval None
00761   */
00762 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00763 {
00764   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00765 }
00766
00767 /**
00768   * @brief  Set polynomial for CRC calculation
00769   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00770   * @param  SPIx SPI Instance
00771   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00772   * @retval None
00773   */
00774 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00775 {
00776   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00777 }
00778
00779 /**
00780   * @brief  Get polynomial for CRC calculation
00781   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00782   * @param  SPIx SPI Instance
00783   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00784   */
00785 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00786 {
00787   return (uint32_t)(READ_REG(SPIx->CRCPR));
00788 }
00789
00790 /**
00791   * @brief  Get Rx CRC
00792   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00793   * @param  SPIx SPI Instance
00794   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00795   */
00796 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00797 {
00798   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00799 }
00800
00801 /**
00802   * @brief  Get Tx CRC
00803   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00804   * @param  SPIx SPI Instance
00805   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00806   */
00807 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00808 {
00809   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00810 }
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00817   * @{
00818   */
00819
00820 /**
00821   * @brief  Set NSS mode
00822   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00823   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00824   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00825   * @param  SPIx SPI Instance
00826   * @param  NSS This parameter can be one of the following values:
00827   *         @arg @ref LL_SPI_NSS_SOFT
00828   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00829   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00830   * @retval None
00831   */
00832 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00833 {
00834   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00835   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00836 }
00837
00838 /**
00839   * @brief  Get NSS mode
00840   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00841   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00842   * @param  SPIx SPI Instance
00843   * @retval Returned value can be one of the following values:
00844   *         @arg @ref LL_SPI_NSS_SOFT
00845   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00846   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00847   */
00848 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00849 {
00850   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00851   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00852   return (Ssm | Ssoe);
00853 }
00854
00855 /**
00856   * @brief  Enable NSS pulse management
00857   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00858   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
00859   * @param  SPIx SPI Instance
00860   * @retval None
00861   */
00862 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
00863 {
00864   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
00865 }
00866
00867 /**
00868   * @brief  Disable NSS pulse management
00869   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00870   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
00871   * @param  SPIx SPI Instance
00872   * @retval None
00873   */
00874 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
00875 {
00876   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
00877 }
00878
00879 /**
00880   * @brief  Check if NSS pulse is enabled
00881   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00882   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
00883   * @param  SPIx SPI Instance
00884   * @retval State of bit (1 or 0).
00885   */
00886 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
00887 {
00888   return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
00889 }
00890
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00896   * @{
00897   */
00898
00899 /**
00900   * @brief  Check if Rx buffer is not empty
00901   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00902   * @param  SPIx SPI Instance
00903   * @retval State of bit (1 or 0).
00904   */
00905 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00906 {
00907   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
00908 }
00909
00910 /**
00911   * @brief  Check if Tx buffer is empty
00912   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00913   * @param  SPIx SPI Instance
00914   * @retval State of bit (1 or 0).
00915   */
00916 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00917 {
00918   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
00919 }
00920
00921 /**
00922   * @brief  Get CRC error flag
00923   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00924   * @param  SPIx SPI Instance
00925   * @retval State of bit (1 or 0).
00926   */
00927 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00928 {
00929   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
00930 }
00931
00932 /**
00933   * @brief  Get mode fault error flag
00934   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00935   * @param  SPIx SPI Instance
00936   * @retval State of bit (1 or 0).
00937   */
00938 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00939 {
00940   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
00941 }
00942
00943 /**
00944   * @brief  Get overrun error flag
00945   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00946   * @param  SPIx SPI Instance
00947   * @retval State of bit (1 or 0).
00948   */
00949 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00950 {
00951   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
00952 }
00953
00954 /**
00955   * @brief  Get busy flag
00956   * @note   The BSY flag is cleared under any one of the following conditions:
00957   * -When the SPI is correctly disabled
00958   * -When a fault is detected in Master mode (MODF bit set to 1)
00959   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00960   * sent
00961   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00962   * each data transfer.
00963   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00964   * @param  SPIx SPI Instance
00965   * @retval State of bit (1 or 0).
00966   */
00967 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00968 {
00969   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
00970 }
00971
00972 /**
00973   * @brief  Get frame format error flag
00974   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
00975   * @param  SPIx SPI Instance
00976   * @retval State of bit (1 or 0).
00977   */
00978 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00979 {
00980   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
00981 }
00982
00983 /**
00984   * @brief  Get FIFO reception Level
00985   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
00986   * @param  SPIx SPI Instance
00987   * @retval Returned value can be one of the following values:
00988   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
00989   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
00990   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
00991   *         @arg @ref LL_SPI_RX_FIFO_FULL
00992   */
00993 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
00994 {
00995   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
00996 }
00997
00998 /**
00999   * @brief  Get FIFO Transmission Level
01000   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
01001   * @param  SPIx SPI Instance
01002   * @retval Returned value can be one of the following values:
01003   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
01004   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
01005   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
01006   *         @arg @ref LL_SPI_TX_FIFO_FULL
01007   */
01008 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
01009 {
01010   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
01011 }
01012
01013 /**
01014   * @brief  Clear CRC error flag
01015   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
01016   * @param  SPIx SPI Instance
01017   * @retval None
01018   */
01019 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01020 {
01021   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
01022 }
01023
01024 /**
01025   * @brief  Clear mode fault error flag
01026   * @note   Clearing this flag is done by a read access to the SPIx_SR
01027   *         register followed by a write access to the SPIx_CR1 register
01028   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
01029   * @param  SPIx SPI Instance
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01033 {
01034   __IO uint32_t tmpreg_sr;
01035   tmpreg_sr = SPIx->SR;
01036   (void) tmpreg_sr;
01037   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
01038 }
01039
01040 /**
01041   * @brief  Clear overrun error flag
01042   * @note   Clearing this flag is done by a read access to the SPIx_DR
01043   *         register followed by a read access to the SPIx_SR register
01044   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
01045   * @param  SPIx SPI Instance
01046   * @retval None
01047   */
01048 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01049 {
01050   __IO uint32_t tmpreg;
01051   tmpreg = SPIx->DR;
01052   (void) tmpreg;
01053   tmpreg = SPIx->SR;
01054   (void) tmpreg;
01055 }
01056
01057 /**
01058   * @brief  Clear frame format error flag
01059   * @note   Clearing this flag is done by reading SPIx_SR register
01060   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
01061   * @param  SPIx SPI Instance
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01065 {
01066   __IO uint32_t tmpreg;
01067   tmpreg = SPIx->SR;
01068   (void) tmpreg;
01069 }
01070
01071 /**
01072   * @}
01073   */
01074
01075 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
01076   * @{
01077   */
01078
01079 /**
01080   * @brief  Enable error interrupt
01081   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01082   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
01083   * @param  SPIx SPI Instance
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
01087 {
01088   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01089 }
01090
01091 /**
01092   * @brief  Enable Rx buffer not empty interrupt
01093   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
01094   * @param  SPIx SPI Instance
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
01098 {
01099   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01100 }
01101
01102 /**
01103   * @brief  Enable Tx buffer empty interrupt
01104   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
01105   * @param  SPIx SPI Instance
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
01109 {
01110   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01111 }
01112
01113 /**
01114   * @brief  Disable error interrupt
01115   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01116   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
01117   * @param  SPIx SPI Instance
01118   * @retval None
01119   */
01120 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
01121 {
01122   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01123 }
01124
01125 /**
01126   * @brief  Disable Rx buffer not empty interrupt
01127   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
01128   * @param  SPIx SPI Instance
01129   * @retval None
01130   */
01131 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
01132 {
01133   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01134 }
01135
01136 /**
01137   * @brief  Disable Tx buffer empty interrupt
01138   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
01139   * @param  SPIx SPI Instance
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
01143 {
01144   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01145 }
01146
01147 /**
01148   * @brief  Check if error interrupt is enabled
01149   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
01150   * @param  SPIx SPI Instance
01151   * @retval State of bit (1 or 0).
01152   */
01153 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01154 {
01155   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
01156 }
01157
01158 /**
01159   * @brief  Check if Rx buffer not empty interrupt is enabled
01160   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
01161   * @param  SPIx SPI Instance
01162   * @retval State of bit (1 or 0).
01163   */
01164 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01165 {
01166   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
01167 }
01168
01169 /**
01170   * @brief  Check if Tx buffer empty interrupt
01171   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
01172   * @param  SPIx SPI Instance
01173   * @retval State of bit (1 or 0).
01174   */
01175 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01176 {
01177   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
01178 }
01179
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
01185   * @{
01186   */
01187
01188 /**
01189   * @brief  Enable DMA Rx
01190   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
01191   * @param  SPIx SPI Instance
01192   * @retval None
01193   */
01194 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01195 {
01196   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01197 }
01198
01199 /**
01200   * @brief  Disable DMA Rx
01201   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
01202   * @param  SPIx SPI Instance
01203   * @retval None
01204   */
01205 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01206 {
01207   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01208 }
01209
01210 /**
01211   * @brief  Check if DMA Rx is enabled
01212   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
01213   * @param  SPIx SPI Instance
01214   * @retval State of bit (1 or 0).
01215   */
01216 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01217 {
01218   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
01219 }
01220
01221 /**
01222   * @brief  Enable DMA Tx
01223   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
01224   * @param  SPIx SPI Instance
01225   * @retval None
01226   */
01227 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01228 {
01229   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01230 }
01231
01232 /**
01233   * @brief  Disable DMA Tx
01234   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
01235   * @param  SPIx SPI Instance
01236   * @retval None
01237   */
01238 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01239 {
01240   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01241 }
01242
01243 /**
01244   * @brief  Check if DMA Tx is enabled
01245   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01246   * @param  SPIx SPI Instance
01247   * @retval State of bit (1 or 0).
01248   */
01249 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01250 {
01251   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
01252 }
01253
01254 /**
01255   * @brief  Set parity of  Last DMA reception
01256   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
01257   * @param  SPIx SPI Instance
01258   * @param  Parity This parameter can be one of the following values:
01259   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01260   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01261   * @retval None
01262   */
01263 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
01264 {
01265   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
01266 }
01267
01268 /**
01269   * @brief  Get parity configuration for  Last DMA reception
01270   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
01271   * @param  SPIx SPI Instance
01272   * @retval Returned value can be one of the following values:
01273   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01274   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01275   */
01276 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
01277 {
01278   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
01279 }
01280
01281 /**
01282   * @brief  Set parity of  Last DMA transmission
01283   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
01284   * @param  SPIx SPI Instance
01285   * @param  Parity This parameter can be one of the following values:
01286   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01287   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
01291 {
01292   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
01293 }
01294
01295 /**
01296   * @brief  Get parity configuration for Last DMA transmission
01297   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
01298   * @param  SPIx SPI Instance
01299   * @retval Returned value can be one of the following values:
01300   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01301   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01302   */
01303 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
01304 {
01305   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
01306 }
01307
01308 /**
01309   * @brief  Get the data register address used for DMA transfer
01310   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01311   * @param  SPIx SPI Instance
01312   * @retval Address of data register
01313   */
01314 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01315 {
01316   return (uint32_t) &(SPIx->DR);
01317 }
01318
01319 /**
01320   * @}
01321   */
01322
01323 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01324   * @{
01325   */
01326
01327 /**
01328   * @brief  Read 8-Bits in the data register
01329   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01330   * @param  SPIx SPI Instance
01331   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01332   */
01333 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01334 {
01335   return (*((__IO uint8_t *)&SPIx->DR));
01336 }
01337
01338 /**
01339   * @brief  Read 16-Bits in the data register
01340   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01341   * @param  SPIx SPI Instance
01342   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01343   */
01344 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01345 {
01346   return (uint16_t)(READ_REG(SPIx->DR));
01347 }
01348
01349 /**
01350   * @brief  Write 8-Bits in the data register
01351   * @rmtoll DR           DR            LL_SPI_TransmitData8
01352   * @param  SPIx SPI Instance
01353   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01357 {
01358 #if defined (__GNUC__)
01359   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
01360   *spidr = TxData;
01361 #else
01362   *((__IO uint8_t *)&SPIx->DR) = TxData;
01363 #endif /* __GNUC__ */
01364 }
01365
01366 /**
01367   * @brief  Write 16-Bits in the data register
01368   * @rmtoll DR           DR            LL_SPI_TransmitData16
01369   * @param  SPIx SPI Instance
01370   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01371   * @retval None
01372   */
01373 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01374 {
01375 #if defined (__GNUC__)
01376   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
01377   *spidr = TxData;
01378 #else
01379   SPIx->DR = TxData;
01380 #endif /* __GNUC__ */
01381 }
01382
01383 /**
01384   * @}
01385   */
01386 #if defined(USE_FULL_LL_DRIVER)
01387 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01388   * @{
01389   */
01390
01391 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01392 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01393 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01394
01395 /**
01396   * @}
01397   */
01398 #endif /* USE_FULL_LL_DRIVER */
01399 /**
01400   * @}
01401   */
01402
01403 /**
01404   * @}
01405   */
01406
01407 #if defined(SPI_I2S_SUPPORT)
01408 /** @defgroup I2S_LL I2S
01409   * @{
01410   */
01411
01412 /* Private variables ---------------------------------------------------------*/
01413 /* Private constants ---------------------------------------------------------*/
01414 /* Private macros ------------------------------------------------------------*/
01415
01416 /* Exported types ------------------------------------------------------------*/
01417 #if defined(USE_FULL_LL_DRIVER)
01418 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
01419   * @{
01420   */
01421
01422 /**
01423   * @brief  I2S Init structure definition
01424   */
01425
01426 typedef struct
01427 {
01428   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
01429                                          This parameter can be a value of @ref I2S_LL_EC_MODE
01430
01431                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
01432
01433   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
01434                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
01435
01436                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
01437
01438
01439   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
01440                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
01441
01442                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
01443
01444
01445   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
01446                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
01447
01448                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
01449
01450
01451   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
01452                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
01453
01454                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
01455                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
01456
01457
01458   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
01459                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
01460
01461                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
01462
01463 } LL_I2S_InitTypeDef;
01464
01465 /**
01466   * @}
01467   */
01468 #endif /*USE_FULL_LL_DRIVER*/
01469
01470 /* Exported constants --------------------------------------------------------*/
01471 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
01472   * @{
01473   */
01474
01475 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
01476   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
01477   * @{
01478   */
01479 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
01480 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
01481 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
01482 #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
01483 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
01484 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
01485 /**
01486   * @}
01487   */
01488
01489 /** @defgroup SPI_LL_EC_IT IT Defines
01490   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
01491   * @{
01492   */
01493 #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
01494 #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
01495 #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
01496 /**
01497   * @}
01498   */
01499
01500 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
01501   * @{
01502   */
01503 #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
01504 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
01505 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
01506 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
01507 /**
01508   * @}
01509   */
01510
01511 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
01512   * @{
01513   */
01514 #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
01515 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
01516 /**
01517   * @}
01518   */
01519
01520 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
01521   * @{
01522   */
01523 #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
01524 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
01525 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
01526 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
01527 #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
01528 /**
01529   * @}
01530   */
01531
01532 /** @defgroup I2S_LL_EC_MODE Operation Mode
01533   * @{
01534   */
01535 #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
01536 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
01537 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
01538 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
01539 /**
01540   * @}
01541   */
01542
01543 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
01544   * @{
01545   */
01546 #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
01547 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
01548 /**
01549   * @}
01550   */
01551
01552 #if defined(USE_FULL_LL_DRIVER)
01553
01554 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
01555   * @{
01556   */
01557 #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
01558 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
01559 /**
01560   * @}
01561   */
01562
01563 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
01564   * @{
01565   */
01566
01567 #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
01568 #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
01569 #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
01570 #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
01571 #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
01572 #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
01573 #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
01574 #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
01575 #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
01576 #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
01577 /**
01578   * @}
01579   */
01580 #endif /* USE_FULL_LL_DRIVER */
01581
01582 /**
01583   * @}
01584   */
01585
01586 /* Exported macro ------------------------------------------------------------*/
01587 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
01588   * @{
01589   */
01590
01591 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
01592   * @{
01593   */
01594
01595 /**
01596   * @brief  Write a value in I2S register
01597   * @param  __INSTANCE__ I2S Instance
01598   * @param  __REG__ Register to be written
01599   * @param  __VALUE__ Value to be written in the register
01600   * @retval None
01601   */
01602 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01603
01604 /**
01605   * @brief  Read a value in I2S register
01606   * @param  __INSTANCE__ I2S Instance
01607   * @param  __REG__ Register to be read
01608   * @retval Register value
01609   */
01610 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01611 /**
01612   * @}
01613   */
01614
01615 /**
01616   * @}
01617   */
01618
01619
01620 /* Exported functions --------------------------------------------------------*/
01621
01622 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
01623   * @{
01624   */
01625
01626 /** @defgroup I2S_LL_EF_Configuration Configuration
01627   * @{
01628   */
01629
01630 /**
01631   * @brief  Select I2S mode and Enable I2S peripheral
01632   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
01633   *         I2SCFGR      I2SE          LL_I2S_Enable
01634   * @param  SPIx SPI Instance
01635   * @retval None
01636   */
01637 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
01638 {
01639   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01640 }
01641
01642 /**
01643   * @brief  Disable I2S peripheral
01644   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
01645   * @param  SPIx SPI Instance
01646   * @retval None
01647   */
01648 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
01649 {
01650   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01651 }
01652
01653 /**
01654   * @brief  Check if I2S peripheral is enabled
01655   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
01656   * @param  SPIx SPI Instance
01657   * @retval State of bit (1 or 0).
01658   */
01659 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
01660 {
01661   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
01662 }
01663
01664 /**
01665   * @brief  Set I2S data frame length
01666   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
01667   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
01668   * @param  SPIx SPI Instance
01669   * @param  DataFormat This parameter can be one of the following values:
01670   *         @arg @ref LL_I2S_DATAFORMAT_16B
01671   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01672   *         @arg @ref LL_I2S_DATAFORMAT_24B
01673   *         @arg @ref LL_I2S_DATAFORMAT_32B
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
01677 {
01678   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
01679 }
01680
01681 /**
01682   * @brief  Get I2S data frame length
01683   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
01684   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
01685   * @param  SPIx SPI Instance
01686   * @retval Returned value can be one of the following values:
01687   *         @arg @ref LL_I2S_DATAFORMAT_16B
01688   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01689   *         @arg @ref LL_I2S_DATAFORMAT_24B
01690   *         @arg @ref LL_I2S_DATAFORMAT_32B
01691   */
01692 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
01693 {
01694   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
01695 }
01696
01697 /**
01698   * @brief  Set I2S clock polarity
01699   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
01700   * @param  SPIx SPI Instance
01701   * @param  ClockPolarity This parameter can be one of the following values:
01702   *         @arg @ref LL_I2S_POLARITY_LOW
01703   *         @arg @ref LL_I2S_POLARITY_HIGH
01704   * @retval None
01705   */
01706 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
01707 {
01708   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
01709 }
01710
01711 /**
01712   * @brief  Get I2S clock polarity
01713   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
01714   * @param  SPIx SPI Instance
01715   * @retval Returned value can be one of the following values:
01716   *         @arg @ref LL_I2S_POLARITY_LOW
01717   *         @arg @ref LL_I2S_POLARITY_HIGH
01718   */
01719 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
01720 {
01721   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
01722 }
01723
01724 /**
01725   * @brief  Set I2S standard protocol
01726   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
01727   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
01728   * @param  SPIx SPI Instance
01729   * @param  Standard This parameter can be one of the following values:
01730   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01731   *         @arg @ref LL_I2S_STANDARD_MSB
01732   *         @arg @ref LL_I2S_STANDARD_LSB
01733   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01734   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
01738 {
01739   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
01740 }
01741
01742 /**
01743   * @brief  Get I2S standard protocol
01744   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
01745   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
01746   * @param  SPIx SPI Instance
01747   * @retval Returned value can be one of the following values:
01748   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01749   *         @arg @ref LL_I2S_STANDARD_MSB
01750   *         @arg @ref LL_I2S_STANDARD_LSB
01751   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01752   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01753   */
01754 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
01755 {
01756   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
01757 }
01758
01759 /**
01760   * @brief  Set I2S transfer mode
01761   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
01762   * @param  SPIx SPI Instance
01763   * @param  Mode This parameter can be one of the following values:
01764   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01765   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01766   *         @arg @ref LL_I2S_MODE_MASTER_TX
01767   *         @arg @ref LL_I2S_MODE_MASTER_RX
01768   * @retval None
01769   */
01770 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
01771 {
01772   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
01773 }
01774
01775 /**
01776   * @brief  Get I2S transfer mode
01777   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
01778   * @param  SPIx SPI Instance
01779   * @retval Returned value can be one of the following values:
01780   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01781   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01782   *         @arg @ref LL_I2S_MODE_MASTER_TX
01783   *         @arg @ref LL_I2S_MODE_MASTER_RX
01784   */
01785 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
01786 {
01787   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
01788 }
01789
01790 /**
01791   * @brief  Set I2S linear prescaler
01792   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
01793   * @param  SPIx SPI Instance
01794   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
01798 {
01799   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
01800 }
01801
01802 /**
01803   * @brief  Get I2S linear prescaler
01804   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
01805   * @param  SPIx SPI Instance
01806   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01807   */
01808 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
01809 {
01810   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
01811 }
01812
01813 /**
01814   * @brief  Set I2S parity prescaler
01815   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
01816   * @param  SPIx SPI Instance
01817   * @param  PrescalerParity This parameter can be one of the following values:
01818   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01819   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01820   * @retval None
01821   */
01822 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
01823 {
01824   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
01825 }
01826
01827 /**
01828   * @brief  Get I2S parity prescaler
01829   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
01830   * @param  SPIx SPI Instance
01831   * @retval Returned value can be one of the following values:
01832   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01833   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01834   */
01835 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
01836 {
01837   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
01838 }
01839
01840 /**
01841   * @brief  Enable the master clock output (Pin MCK)
01842   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
01843   * @param  SPIx SPI Instance
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
01847 {
01848   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01849 }
01850
01851 /**
01852   * @brief  Disable the master clock output (Pin MCK)
01853   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
01854   * @param  SPIx SPI Instance
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
01858 {
01859   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01860 }
01861
01862 /**
01863   * @brief  Check if the master clock output (Pin MCK) is enabled
01864   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
01865   * @param  SPIx SPI Instance
01866   * @retval State of bit (1 or 0).
01867   */
01868 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
01869 {
01870   return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
01871 }
01872
01873 #if defined(SPI_I2SCFGR_ASTRTEN)
01874 /**
01875   * @brief  Enable asynchronous start
01876   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
01877   * @param  SPIx SPI Instance
01878   * @retval None
01879   */
01880 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
01881 {
01882   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
01883 }
01884
01885 /**
01886   * @brief  Disable  asynchronous start
01887   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
01888   * @param  SPIx SPI Instance
01889   * @retval None
01890   */
01891 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
01892 {
01893   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
01894 }
01895
01896 /**
01897   * @brief  Check if asynchronous start is enabled
01898   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
01899   * @param  SPIx SPI Instance
01900   * @retval State of bit (1 or 0).
01901   */
01902 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
01903 {
01904   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
01905 }
01906 #endif /* SPI_I2SCFGR_ASTRTEN */
01907
01908 /**
01909   * @}
01910   */
01911
01912 /** @defgroup I2S_LL_EF_FLAG FLAG Management
01913   * @{
01914   */
01915
01916 /**
01917   * @brief  Check if Rx buffer is not empty
01918   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
01919   * @param  SPIx SPI Instance
01920   * @retval State of bit (1 or 0).
01921   */
01922 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
01923 {
01924   return LL_SPI_IsActiveFlag_RXNE(SPIx);
01925 }
01926
01927 /**
01928   * @brief  Check if Tx buffer is empty
01929   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
01930   * @param  SPIx SPI Instance
01931   * @retval State of bit (1 or 0).
01932   */
01933 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
01934 {
01935   return LL_SPI_IsActiveFlag_TXE(SPIx);
01936 }
01937
01938 /**
01939   * @brief  Get busy flag
01940   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
01941   * @param  SPIx SPI Instance
01942   * @retval State of bit (1 or 0).
01943   */
01944 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
01945 {
01946   return LL_SPI_IsActiveFlag_BSY(SPIx);
01947 }
01948
01949 /**
01950   * @brief  Get overrun error flag
01951   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
01952   * @param  SPIx SPI Instance
01953   * @retval State of bit (1 or 0).
01954   */
01955 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
01956 {
01957   return LL_SPI_IsActiveFlag_OVR(SPIx);
01958 }
01959
01960 /**
01961   * @brief  Get underrun error flag
01962   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
01963   * @param  SPIx SPI Instance
01964   * @retval State of bit (1 or 0).
01965   */
01966 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
01967 {
01968   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
01969 }
01970
01971 /**
01972   * @brief  Get frame format error flag
01973   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
01974   * @param  SPIx SPI Instance
01975   * @retval State of bit (1 or 0).
01976   */
01977 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
01978 {
01979   return LL_SPI_IsActiveFlag_FRE(SPIx);
01980 }
01981
01982 /**
01983   * @brief  Get channel side flag.
01984   * @note   0: Channel Left has to be transmitted or has been received\n
01985   *         1: Channel Right has to be transmitted or has been received\n
01986   *         It has no significance in PCM mode.
01987   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
01988   * @param  SPIx SPI Instance
01989   * @retval State of bit (1 or 0).
01990   */
01991 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
01992 {
01993   return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
01994 }
01995
01996 /**
01997   * @brief  Clear overrun error flag
01998   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
01999   * @param  SPIx SPI Instance
02000   * @retval None
02001   */
02002 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
02003 {
02004   LL_SPI_ClearFlag_OVR(SPIx);
02005 }
02006
02007 /**
02008   * @brief  Clear underrun error flag
02009   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
02010   * @param  SPIx SPI Instance
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
02014 {
02015   __IO uint32_t tmpreg;
02016   tmpreg = SPIx->SR;
02017   (void)tmpreg;
02018 }
02019
02020 /**
02021   * @brief  Clear frame format error flag
02022   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
02023   * @param  SPIx SPI Instance
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
02027 {
02028   LL_SPI_ClearFlag_FRE(SPIx);
02029 }
02030
02031 /**
02032   * @}
02033   */
02034
02035 /** @defgroup I2S_LL_EF_IT Interrupt Management
02036   * @{
02037   */
02038
02039 /**
02040   * @brief  Enable error IT
02041   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02042   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
02043   * @param  SPIx SPI Instance
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
02047 {
02048   LL_SPI_EnableIT_ERR(SPIx);
02049 }
02050
02051 /**
02052   * @brief  Enable Rx buffer not empty IT
02053   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
02054   * @param  SPIx SPI Instance
02055   * @retval None
02056   */
02057 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
02058 {
02059   LL_SPI_EnableIT_RXNE(SPIx);
02060 }
02061
02062 /**
02063   * @brief  Enable Tx buffer empty IT
02064   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
02065   * @param  SPIx SPI Instance
02066   * @retval None
02067   */
02068 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
02069 {
02070   LL_SPI_EnableIT_TXE(SPIx);
02071 }
02072
02073 /**
02074   * @brief  Disable error IT
02075   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02076   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
02077   * @param  SPIx SPI Instance
02078   * @retval None
02079   */
02080 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
02081 {
02082   LL_SPI_DisableIT_ERR(SPIx);
02083 }
02084
02085 /**
02086   * @brief  Disable Rx buffer not empty IT
02087   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
02088   * @param  SPIx SPI Instance
02089   * @retval None
02090   */
02091 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
02092 {
02093   LL_SPI_DisableIT_RXNE(SPIx);
02094 }
02095
02096 /**
02097   * @brief  Disable Tx buffer empty IT
02098   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
02099   * @param  SPIx SPI Instance
02100   * @retval None
02101   */
02102 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
02103 {
02104   LL_SPI_DisableIT_TXE(SPIx);
02105 }
02106
02107 /**
02108   * @brief  Check if ERR IT is enabled
02109   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
02110   * @param  SPIx SPI Instance
02111   * @retval State of bit (1 or 0).
02112   */
02113 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
02114 {
02115   return LL_SPI_IsEnabledIT_ERR(SPIx);
02116 }
02117
02118 /**
02119   * @brief  Check if RXNE IT is enabled
02120   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
02121   * @param  SPIx SPI Instance
02122   * @retval State of bit (1 or 0).
02123   */
02124 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
02125 {
02126   return LL_SPI_IsEnabledIT_RXNE(SPIx);
02127 }
02128
02129 /**
02130   * @brief  Check if TXE IT is enabled
02131   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
02132   * @param  SPIx SPI Instance
02133   * @retval State of bit (1 or 0).
02134   */
02135 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
02136 {
02137   return LL_SPI_IsEnabledIT_TXE(SPIx);
02138 }
02139
02140 /**
02141   * @}
02142   */
02143
02144 /** @defgroup I2S_LL_EF_DMA DMA Management
02145   * @{
02146   */
02147
02148 /**
02149   * @brief  Enable DMA Rx
02150   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
02151   * @param  SPIx SPI Instance
02152   * @retval None
02153   */
02154 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
02155 {
02156   LL_SPI_EnableDMAReq_RX(SPIx);
02157 }
02158
02159 /**
02160   * @brief  Disable DMA Rx
02161   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
02162   * @param  SPIx SPI Instance
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
02166 {
02167   LL_SPI_DisableDMAReq_RX(SPIx);
02168 }
02169
02170 /**
02171   * @brief  Check if DMA Rx is enabled
02172   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
02173   * @param  SPIx SPI Instance
02174   * @retval State of bit (1 or 0).
02175   */
02176 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
02177 {
02178   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
02179 }
02180
02181 /**
02182   * @brief  Enable DMA Tx
02183   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
02184   * @param  SPIx SPI Instance
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
02188 {
02189   LL_SPI_EnableDMAReq_TX(SPIx);
02190 }
02191
02192 /**
02193   * @brief  Disable DMA Tx
02194   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
02195   * @param  SPIx SPI Instance
02196   * @retval None
02197   */
02198 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
02199 {
02200   LL_SPI_DisableDMAReq_TX(SPIx);
02201 }
02202
02203 /**
02204   * @brief  Check if DMA Tx is enabled
02205   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
02206   * @param  SPIx SPI Instance
02207   * @retval State of bit (1 or 0).
02208   */
02209 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
02210 {
02211   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
02212 }
02213
02214 /**
02215   * @}
02216   */
02217
02218 /** @defgroup I2S_LL_EF_DATA DATA Management
02219   * @{
02220   */
02221
02222 /**
02223   * @brief  Read 16-Bits in data register
02224   * @rmtoll DR           DR            LL_I2S_ReceiveData16
02225   * @param  SPIx SPI Instance
02226   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02227   */
02228 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
02229 {
02230   return LL_SPI_ReceiveData16(SPIx);
02231 }
02232
02233 /**
02234   * @brief  Write 16-Bits in data register
02235   * @rmtoll DR           DR            LL_I2S_TransmitData16
02236   * @param  SPIx SPI Instance
02237   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02238   * @retval None
02239   */
02240 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
02241 {
02242   LL_SPI_TransmitData16(SPIx, TxData);
02243 }
02244
02245 /**
02246   * @}
02247   */
02248
02249 #if defined(USE_FULL_LL_DRIVER)
02250 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
02251   * @{
02252   */
02253
02254 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
02255 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
02256 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
02257 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
02258
02259 /**
02260   * @}
02261   */
02262 #endif /* USE_FULL_LL_DRIVER */
02263
02264 /**
02265   * @}
02266   */
02267
02268 /**
02269   * @}
02270   */
02271 #endif /* SPI_I2S_SUPPORT */
02272
02273 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
02274
02275 /**
02276   * @}
02277   */
02278
02279 #ifdef __cplusplus
02280 }
02281 #endif
02282
02283 #endif /* STM32G4xx_LL_SPI_H */
02284
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_system.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_system.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SYSTEM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021     [..]
00022     The LL SYSTEM driver contains a set of generic APIs that can be
00023     used by user:
00024       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00025       (+) Access to DBGCMU registers
00026       (+) Access to SYSCFG registers
00027       (+) Access to VREFBUF registers
00028
00029   @endverbatim
00030   ******************************************************************************
00031   */
00032
00033 /* Define to prevent recursive inclusion -------------------------------------*/
00034 #ifndef __STM32G4xx_LL_SYSTEM_H
00035 #define __STM32G4xx_LL_SYSTEM_H
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32g4xx.h"
00043
00044 /** @addtogroup STM32G4xx_LL_Driver
00045   * @{
00046   */
00047
00048 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
00049
00050 /** @defgroup SYSTEM_LL SYSTEM
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056
00057 /* Private constants ---------------------------------------------------------*/
00058 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00059   * @{
00060   */
00061
00062 /* Defines used for position in the register */
00063 #define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
00064
00065 /**
00066   * @brief Power-down in Run mode Flash key
00067   */
00068 #define FLASH_PDKEY1                  0x04152637U /*!< Flash power down key1 */
00069 #define FLASH_PDKEY2                  0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
00070                                                        to unlock the RUN_PD bit in FLASH_ACR */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /* Private macros ------------------------------------------------------------*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00085   * @{
00086   */
00087 #define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */
00088 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
00089 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
00090 #if defined(FMC_Bank1_R)
00091 #define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
00092 #endif /* FMC_Bank1_R */
00093 #define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
00094 /**
00095   * @}
00096   */
00097
00098 #if defined(SYSCFG_MEMRMP_FB_MODE)
00099 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
00100   * @{
00101   */
00102 #define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
00103                                                                       and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000) */
00104 #define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
00105                                                                       and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000) */
00106 /**
00107   * @}
00108   */
00109
00110 #endif /* SYSCFG_MEMRMP_FB_MODE */
00111 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00112   * @{
00113   */
00114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
00115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
00116 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
00118 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00119 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00120 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
00121 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00122 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
00123 #if defined(I2C2)
00124 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
00125 #endif /* I2C2 */
00126 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
00127 #if defined(I2C4)
00128 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4    SYSCFG_CFGR1_I2C4_FMP     /*!< Enable Fast Mode Plus on I2C4 pins */
00129 #endif /* I2C4 */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00135   * @{
00136   */
00137 #define LL_SYSCFG_EXTI_PORTA               0U                        /*!< EXTI PORT A                        */
00138 #define LL_SYSCFG_EXTI_PORTB               1U                        /*!< EXTI PORT B                        */
00139 #define LL_SYSCFG_EXTI_PORTC               2U                        /*!< EXTI PORT C                        */
00140 #define LL_SYSCFG_EXTI_PORTD               3U                        /*!< EXTI PORT D                        */
00141 #define LL_SYSCFG_EXTI_PORTE               4U                        /*!< EXTI PORT E                        */
00142 #define LL_SYSCFG_EXTI_PORTF               5U                        /*!< EXTI PORT F                        */
00143 #define LL_SYSCFG_EXTI_PORTG               6U                        /*!< EXTI PORT G                        */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00149   * @{
00150   */
00151 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)((0x000FU << 16U) | 0U)  /* !< EXTI_POSITION_0  | EXTICR[0] */
00152 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)((0x00F0U << 16U) | 0U)  /* !< EXTI_POSITION_4  | EXTICR[0] */
00153 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)((0x0F00U << 16U) | 0U)  /* !< EXTI_POSITION_8  | EXTICR[0] */
00154 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)((0xF000U << 16U) | 0U)  /* !< EXTI_POSITION_12 | EXTICR[0] */
00155 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)((0x000FU << 16U) | 1U)  /* !< EXTI_POSITION_0  | EXTICR[1] */
00156 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)((0x00F0U << 16U) | 1U)  /* !< EXTI_POSITION_4  | EXTICR[1] */
00157 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)((0x0F00U << 16U) | 1U)  /* !< EXTI_POSITION_8  | EXTICR[1] */
00158 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)((0xF000U << 16U) | 1U)  /* !< EXTI_POSITION_12 | EXTICR[1] */
00159 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)((0x000FU << 16U) | 2U)  /* !< EXTI_POSITION_0  | EXTICR[2] */
00160 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)((0x00F0U << 16U) | 2U)  /* !< EXTI_POSITION_4  | EXTICR[2] */
00161 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)((0x0F00U << 16U) | 2U)  /* !< EXTI_POSITION_8  | EXTICR[2] */
00162 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)((0xF000U << 16U) | 2U)  /* !< EXTI_POSITION_12 | EXTICR[2] */
00163 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)((0x000FU << 16U) | 3U)  /* !< EXTI_POSITION_0  | EXTICR[3] */
00164 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)((0x00F0U << 16U) | 3U)  /* !< EXTI_POSITION_4  | EXTICR[3] */
00165 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)((0x0F00U << 16U) | 3U)  /* !< EXTI_POSITION_8  | EXTICR[3] */
00166 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)((0xF000U << 16U) | 3U)  /* !< EXTI_POSITION_12 | EXTICR[3] */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00172   * @{
00173   */
00174 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal
00175                                                                    with Break Input of TIM1/8/15/16/17                           */
00176 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection
00177                                                                    with TIM1/8/15/16/17 Break Input
00178                                                                    and also the PVDE and PLS bits of the Power Control Interface */
00179 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY     SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM_PARITY error signal
00180                                                                    with Break Input of TIM1/8/15/16/17                           */
00181 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4
00182                                                                    with Break Input of TIM1/15/16/17                             */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
00188   * @{
00189   */
00190 #define LL_SYSCFG_CCMSRAMWRP_PAGE0         SYSCFG_SWPR_PAGE0  /*!< CCMSRAM Write protection page 0  */
00191 #define LL_SYSCFG_CCMSRAMWRP_PAGE1         SYSCFG_SWPR_PAGE1  /*!< CCMSRAM Write protection page 1  */
00192 #define LL_SYSCFG_CCMSRAMWRP_PAGE2         SYSCFG_SWPR_PAGE2  /*!< CCMSRAM Write protection page 2  */
00193 #define LL_SYSCFG_CCMSRAMWRP_PAGE3         SYSCFG_SWPR_PAGE3  /*!< CCMSRAM Write protection page 3  */
00194 #define LL_SYSCFG_CCMSRAMWRP_PAGE4         SYSCFG_SWPR_PAGE4  /*!< CCMSRAM Write protection page 4  */
00195 #define LL_SYSCFG_CCMSRAMWRP_PAGE5         SYSCFG_SWPR_PAGE5  /*!< CCMSRAM Write protection page 5  */
00196 #define LL_SYSCFG_CCMSRAMWRP_PAGE6         SYSCFG_SWPR_PAGE6  /*!< CCMSRAM Write protection page 6  */
00197 #define LL_SYSCFG_CCMSRAMWRP_PAGE7         SYSCFG_SWPR_PAGE7  /*!< CCMSRAM Write protection page 7  */
00198 #define LL_SYSCFG_CCMSRAMWRP_PAGE8         SYSCFG_SWPR_PAGE8  /*!< CCMSRAM Write protection page 8  */
00199 #define LL_SYSCFG_CCMSRAMWRP_PAGE9         SYSCFG_SWPR_PAGE9  /*!< CCMSRAM Write protection page 9  */
00200 #if defined(SYSCFG_SWPR_PAGE10)
00201 #define LL_SYSCFG_CCMSRAMWRP_PAGE10        SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
00202 #define LL_SYSCFG_CCMSRAMWRP_PAGE11        SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
00203 #define LL_SYSCFG_CCMSRAMWRP_PAGE12        SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
00204 #define LL_SYSCFG_CCMSRAMWRP_PAGE13        SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
00205 #define LL_SYSCFG_CCMSRAMWRP_PAGE14        SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
00206 #define LL_SYSCFG_CCMSRAMWRP_PAGE15        SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
00207 #define LL_SYSCFG_CCMSRAMWRP_PAGE16        SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
00208 #define LL_SYSCFG_CCMSRAMWRP_PAGE17        SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
00209 #define LL_SYSCFG_CCMSRAMWRP_PAGE18        SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
00210 #define LL_SYSCFG_CCMSRAMWRP_PAGE19        SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
00211 #define LL_SYSCFG_CCMSRAMWRP_PAGE20        SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
00212 #define LL_SYSCFG_CCMSRAMWRP_PAGE21        SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
00213 #define LL_SYSCFG_CCMSRAMWRP_PAGE22        SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
00214 #define LL_SYSCFG_CCMSRAMWRP_PAGE23        SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
00215 #define LL_SYSCFG_CCMSRAMWRP_PAGE24        SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
00216 #define LL_SYSCFG_CCMSRAMWRP_PAGE25        SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
00217 #define LL_SYSCFG_CCMSRAMWRP_PAGE26        SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
00218 #define LL_SYSCFG_CCMSRAMWRP_PAGE27        SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
00219 #define LL_SYSCFG_CCMSRAMWRP_PAGE28        SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
00220 #define LL_SYSCFG_CCMSRAMWRP_PAGE29        SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
00221 #define LL_SYSCFG_CCMSRAMWRP_PAGE30        SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
00222 #define LL_SYSCFG_CCMSRAMWRP_PAGE31        SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
00223 #endif /* SYSCFG_SWPR_PAGE10 */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00229   * @{
00230   */
00231 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
00232 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00233 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00234 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00235 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00241   * @{
00242   */
00243 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
00244 #if defined(TIM3)
00245 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
00246 #endif /* TIM3 */
00247 #if defined(TIM4)
00248 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
00249 #endif /* TIM4 */
00250 #if defined(TIM5)
00251 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
00252 #endif /* TIM5 */
00253 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
00254 #if defined(TIM7)
00255 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
00256 #endif /* TIM7 */
00257 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
00258 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
00259 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
00260 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
00261 #if defined(I2C2)
00262 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
00263 #endif /* I2C2 */
00264 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
00265 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
00271   * @{
00272   */
00273 #if defined(I2C4)
00274 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/
00275 #endif /* I2C4 */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00281   * @{
00282   */
00283 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
00284 #if defined(TIM8)
00285 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
00286 #endif /* TIM8 */
00287 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
00288 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
00289 #if defined(TIM17)
00290 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
00291 #endif /* TIM17 */
00292 #if defined(TIM20)
00293 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP     DBGMCU_APB2FZ_DBG_TIM20_STOP    /*!< The counter clock of TIM20 is stopped when the core is halted*/
00294 #endif /* TIM20 */
00295 #if defined(HRTIM1)
00296 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP     DBGMCU_APB2FZ_DBG_HRTIM1_STOP    /*!< The counter clock of HRTIM1 is stopped when the core is halted*/
00297 #endif /* HRTIM1 */
00298 /**
00299   * @}
00300   */
00301
00302 #if defined(VREFBUF)
00303 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
00304   * @{
00305   */
00306 #define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
00307 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS_0      /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V)   */
00308 #define LL_VREFBUF_VOLTAGE_SCALE2          VREFBUF_CSR_VRS_1      /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V)   */
00309 /**
00310   * @}
00311   */
00312 #endif /* VREFBUF */
00313
00314 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00315   * @{
00316   */
00317 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
00318 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
00319 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
00320 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
00321 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
00322 #if defined(FLASH_ACR_LATENCY_5WS)
00323 #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
00324 #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
00325 #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
00326 #define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
00327 #define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
00328 #define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS  /*!< FLASH ten wait states */
00329 #define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS  /*!< FLASH eleven wait states */
00330 #define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS  /*!< FLASH twelve wait states */
00331 #define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS  /*!< FLASH thirteen wait states */
00332 #define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS  /*!< FLASH fourteen wait states */
00333 #define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS  /*!< FLASH fifteen wait states */
00334 #endif /* FLASH_ACR_LATENCY_5WS */
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Exported macro ------------------------------------------------------------*/
00344
00345 /* Exported functions --------------------------------------------------------*/
00346 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00347   * @{
00348   */
00349
00350 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00351   * @{
00352   */
00353
00354 /**
00355   * @brief  Set memory mapping at address 0x00000000
00356   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
00357   * @param  Memory This parameter can be one of the following values:
00358   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00359   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00360   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00361   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00362   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
00363   *
00364   *         (*) value not defined in all devices
00365   * @retval None
00366   */
00367 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00368 {
00369   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
00370 }
00371
00372 /**
00373   * @brief  Get memory mapping at address 0x00000000
00374   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
00375   * @retval Returned value can be one of the following values:
00376   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00377   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00378   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00379   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00380   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
00381   *
00382   *         (*) value not defined in all devices
00383   */
00384 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00385 {
00386   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
00387 }
00388
00389 #if defined(SYSCFG_MEMRMP_FB_MODE)
00390 /**
00391   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
00392   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
00393   * @param  Bank This parameter can be one of the following values:
00394   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00395   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00396   * @retval None
00397   */
00398 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
00399 {
00400   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
00401 }
00402
00403 /**
00404   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
00405   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
00406   * @retval Returned value can be one of the following values:
00407   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00408   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00409   */
00410 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
00411 {
00412   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
00413 }
00414 #endif /* SYSCFG_MEMRMP_FB_MODE */
00415
00416 /**
00417   * @brief  Enable I/O analog switch voltage booster.
00418   * @note   When voltage booster is enabled, I/O analog switches are supplied
00419   *         by a dedicated voltage booster, from VDD power domain. This is
00420   *         the recommended configuration with low VDDA voltage operation.
00421   * @note   The I/O analog switch voltage booster is relevant for peripherals
00422   *         using I/O in analog input: ADC, COMP, OPAMP.
00423   *         However, COMP and OPAMP inputs have a high impedance and
00424   *         voltage booster do not impact performance significantly.
00425   *         Therefore, the voltage booster is mainly intended for
00426   *         usage with ADC.
00427   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
00428   * @retval None
00429   */
00430 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00431 {
00432   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00433 }
00434
00435 /**
00436   * @brief  Disable I/O analog switch voltage booster.
00437   * @note   When voltage booster is enabled, I/O analog switches are supplied
00438   *         by a dedicated voltage booster, from VDD power domain. This is
00439   *         the recommended configuration with low VDDA voltage operation.
00440   * @note   The I/O analog switch voltage booster is relevant for peripherals
00441   *         using I/O in analog input: ADC, COMP, OPAMP.
00442   *         However, COMP and OPAMP inputs have a high impedance and
00443   *         voltage booster do not impact performance significantly.
00444   *         Therefore, the voltage booster is mainly intended for
00445   *         usage with ADC.
00446   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00450 {
00451   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00452 }
00453
00454 /**
00455   * @brief  Enable the I2C fast mode plus driving capability.
00456   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
00457   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
00458   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00459   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00460   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00461   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00462   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00463   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00464   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00465   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00466   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
00467   *
00468   *         (*) value not defined in all devices
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00472 {
00473   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00474 }
00475
00476 /**
00477   * @brief  Disable the I2C fast mode plus driving capability.
00478   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
00479   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
00480   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00481   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00482   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00483   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00484   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00485   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00486   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00487   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00488   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
00489   *
00490   *         (*) value not defined in all devices
00491   * @retval None
00492   */
00493 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00494 {
00495   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00496 }
00497
00498 /**
00499   * @brief  Enable Floating Point Unit Invalid operation Interrupt
00500   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
00501   * @retval None
00502   */
00503 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
00504 {
00505   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00506 }
00507
00508 /**
00509   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
00510   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
00511   * @retval None
00512   */
00513 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
00514 {
00515   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00516 }
00517
00518 /**
00519   * @brief  Enable Floating Point Unit Underflow Interrupt
00520   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
00521   * @retval None
00522   */
00523 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
00524 {
00525   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00526 }
00527
00528 /**
00529   * @brief  Enable Floating Point Unit Overflow Interrupt
00530   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
00531   * @retval None
00532   */
00533 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
00534 {
00535   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00536 }
00537
00538 /**
00539   * @brief  Enable Floating Point Unit Input denormal Interrupt
00540   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
00541   * @retval None
00542   */
00543 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
00544 {
00545   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00546 }
00547
00548 /**
00549   * @brief  Enable Floating Point Unit Inexact Interrupt
00550   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
00554 {
00555   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00556 }
00557
00558 /**
00559   * @brief  Disable Floating Point Unit Invalid operation Interrupt
00560   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
00561   * @retval None
00562   */
00563 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
00564 {
00565   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00566 }
00567
00568 /**
00569   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
00570   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
00571   * @retval None
00572   */
00573 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
00574 {
00575   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00576 }
00577
00578 /**
00579   * @brief  Disable Floating Point Unit Underflow Interrupt
00580   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
00584 {
00585   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00586 }
00587
00588 /**
00589   * @brief  Disable Floating Point Unit Overflow Interrupt
00590   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
00591   * @retval None
00592   */
00593 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
00594 {
00595   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00596 }
00597
00598 /**
00599   * @brief  Disable Floating Point Unit Input denormal Interrupt
00600   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
00601   * @retval None
00602   */
00603 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
00604 {
00605   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00606 }
00607
00608 /**
00609   * @brief  Disable Floating Point Unit Inexact Interrupt
00610   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
00611   * @retval None
00612   */
00613 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
00614 {
00615   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00616 }
00617
00618 /**
00619   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
00620   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
00621   * @retval State of bit (1 or 0).
00622   */
00623 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
00624 {
00625   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
00626 }
00627
00628 /**
00629   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
00630   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
00631   * @retval State of bit (1 or 0).
00632   */
00633 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
00634 {
00635   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
00636 }
00637
00638 /**
00639   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
00640   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
00641   * @retval State of bit (1 or 0).
00642   */
00643 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
00644 {
00645   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
00646 }
00647
00648 /**
00649   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
00650   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
00651   * @retval State of bit (1 or 0).
00652   */
00653 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
00654 {
00655   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
00656 }
00657
00658 /**
00659   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
00660   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
00661   * @retval State of bit (1 or 0).
00662   */
00663 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
00664 {
00665   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
00666 }
00667
00668 /**
00669   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
00670   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
00671   * @retval State of bit (1 or 0).
00672   */
00673 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
00674 {
00675   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
00676 }
00677
00678 /**
00679   * @brief  Configure source input for the EXTI external interrupt.
00680   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
00681   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
00682   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
00683   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
00684   * @param  Port This parameter can be one of the following values:
00685   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00686   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00687   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00688   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00689   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00690   *         @arg @ref LL_SYSCFG_EXTI_PORTF
00691   *         @arg @ref LL_SYSCFG_EXTI_PORTG
00692   *
00693   *         (*) value not defined in all devices
00694   * @param  Line This parameter can be one of the following values:
00695   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00696   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00697   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00698   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00699   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00700   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00701   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00702   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00703   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00704   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00705   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00706   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00707   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00708   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00709   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00710   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00711   * @retval None
00712   */
00713 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
00714 {
00715   MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << (POSITION_VAL((Line >> 16U)) & 0x1FU) );
00716 }
00717
00718 /**
00719   * @brief  Get the configured defined for specific EXTI Line
00720   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
00721   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
00722   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
00723   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
00724   * @param  Line This parameter can be one of the following values:
00725   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00726   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00727   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00728   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00729   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00730   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00731   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00732   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00733   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00734   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00735   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00736   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00737   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00738   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00739   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00740   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00741   * @retval Returned value can be one of the following values:
00742   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00743   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00744   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00745   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00746   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00747   *         @arg @ref LL_SYSCFG_EXTI_PORTF
00748   *         @arg @ref LL_SYSCFG_EXTI_PORTG
00749   *
00750   *         (*) value not defined in all devices
00751   */
00752 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
00753 {
00754   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
00755 }
00756
00757 /**
00758   * @brief  Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
00759   * automatically cleared at the end of the CCMSRAM erase operation.)
00760   * @note This bit is write-protected: setting this bit is possible only after the
00761   *       correct key sequence is written in the SYSCFG_SKR register as described in
00762   *       the Reference Manual.
00763   * @rmtoll SYSCFG_SCSR  CCMER       LL_SYSCFG_EnableCCMSRAMErase
00764   * @retval None
00765   */
00766 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void)
00767 {
00768   /* Starts a hardware CCMSRAM erase operation*/
00769   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
00770 }
00771
00772 /**
00773   * @brief  Check if CCMSRAM erase operation is on going
00774   * @rmtoll SYSCFG_SCSR  CCMBSY      LL_SYSCFG_IsCCMSRAMEraseOngoing
00775   * @retval State of bit (1 or 0).
00776   */
00777 __STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
00778 {
00779   return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
00780 }
00781
00782 /**
00783   * @brief  Set connections to TIM1/8/15/16/17 Break inputs
00784   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
00785   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
00786   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
00787   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
00788   * @param  Break This parameter can be a combination of the following values:
00789   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00790   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00791   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
00792   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00793   * @retval None
00794   */
00795 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
00796 {
00797   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
00798 }
00799
00800 /**
00801   * @brief  Get connections to TIM1/8/15/16/17 Break inputs
00802   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
00803   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
00804   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
00805   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
00806   * @retval Returned value can be can be a combination of the following values:
00807   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00808   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00809   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
00810   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00811   */
00812 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
00813 {
00814   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
00815 }
00816
00817 /**
00818   * @brief  Check if SRAM parity error detected
00819   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
00820   * @retval State of bit (1 or 0).
00821   */
00822 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
00823 {
00824   return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
00825 }
00826
00827 /**
00828   * @brief  Clear SRAM parity error flag
00829   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
00830   * @retval None
00831   */
00832 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
00833 {
00834   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
00835 }
00836
00837 /**
00838   * @brief  Enable CCMSRAM page write protection
00839   * @note Write protection is cleared only by a system reset
00840   * @rmtoll SYSCFG_SWPR  PAGEx         LL_SYSCFG_EnableCCMSRAMPageWRP
00841   * @param  CCMSRAMWRP This parameter can be a combination of the following values:
00842   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
00843   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
00844   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
00845   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
00846   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
00847   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
00848   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
00849   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
00850   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
00851   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
00852   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
00853   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
00854   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
00855   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
00856   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
00857   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
00858   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
00859   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
00860   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
00861   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
00862   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
00863   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
00864   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
00865   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
00866   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
00867   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
00868   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
00869   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
00870   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
00871   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
00872   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
00873   *         @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
00874   *
00875   *         (*) value not defined in all devices
00876   * @retval None
00877   */
00878 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
00879 {
00880   SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
00881 }
00882
00883 /**
00884   * @brief  CCMSRAM page write protection lock prior to erase
00885   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockCCMSRAMWRP
00886   * @retval None
00887   */
00888 __STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void)
00889 {
00890   /* Writing a wrong key reactivates the write protection */
00891   WRITE_REG(SYSCFG->SKR, 0x00);
00892 }
00893
00894 /**
00895   * @brief  CCMSRAM page write protection unlock prior to erase
00896   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockCCMSRAMWRP
00897   * @retval None
00898   */
00899 __STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void)
00900 {
00901   /* unlock the write protection of the CCMER bit */
00902   WRITE_REG(SYSCFG->SKR, 0xCA);
00903   WRITE_REG(SYSCFG->SKR, 0x53);
00904 }
00905
00906 /**
00907   * @}
00908   */
00909
00910
00911 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
00912   * @{
00913   */
00914
00915 /**
00916   * @brief  Return the device identifier
00917   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
00918   * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)
00919   */
00920 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
00921 {
00922   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
00923 }
00924
00925 /**
00926   * @brief  Return the device revision identifier
00927   * @note This field indicates the revision of the device.
00928   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
00929   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
00930   */
00931 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
00932 {
00933   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> (DBGMCU_REVID_POSITION & 0x1FU));
00934 }
00935
00936 /**
00937   * @brief  Enable the Debug Module during SLEEP mode
00938   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
00939   * @retval None
00940   */
00941 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
00942 {
00943   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00944 }
00945
00946 /**
00947   * @brief  Disable the Debug Module during SLEEP mode
00948   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
00949   * @retval None
00950   */
00951 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
00952 {
00953   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00954 }
00955
00956 /**
00957   * @brief  Enable the Debug Module during STOP mode
00958   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
00959   * @retval None
00960   */
00961 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
00962 {
00963   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00964 }
00965
00966 /**
00967   * @brief  Disable the Debug Module during STOP mode
00968   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
00972 {
00973   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00974 }
00975
00976 /**
00977   * @brief  Enable the Debug Module during STANDBY mode
00978   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
00979   * @retval None
00980   */
00981 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
00982 {
00983   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00984 }
00985
00986 /**
00987   * @brief  Disable the Debug Module during STANDBY mode
00988   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
00989   * @retval None
00990   */
00991 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
00992 {
00993   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00994 }
00995
00996 /**
00997   * @brief  Set Trace pin assignment control
00998   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
00999   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
01000   * @param  PinAssignment This parameter can be one of the following values:
01001   *         @arg @ref LL_DBGMCU_TRACE_NONE
01002   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01003   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01004   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01005   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01006   * @retval None
01007   */
01008 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
01009 {
01010   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
01011 }
01012
01013 /**
01014   * @brief  Get Trace pin assignment control
01015   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
01016   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
01017   * @retval Returned value can be one of the following values:
01018   *         @arg @ref LL_DBGMCU_TRACE_NONE
01019   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01020   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01021   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01022   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01023   */
01024 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
01025 {
01026   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
01027 }
01028
01029 /**
01030   * @brief  Freeze APB1 peripherals (group1 peripherals)
01031   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
01032   * @param  Periphs This parameter can be a combination of the following values:
01033   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01034   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01035   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
01036   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01037   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01038   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
01039   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01040   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01041   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01042   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01043   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
01044   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01045   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01046   *
01047   *         (*) value not defined in all devices.
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01051 {
01052   SET_BIT(DBGMCU->APB1FZR1, Periphs);
01053 }
01054
01055 /**
01056   * @brief  Freeze APB1 peripherals (group2 peripherals)
01057   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
01058   * @param  Periphs This parameter can be a combination of the following values:
01059   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
01060   *
01061   *         (*) value not defined in all devices.
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
01065 {
01066   SET_BIT(DBGMCU->APB1FZR2, Periphs);
01067 }
01068
01069 /**
01070   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01071   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01072   * @param  Periphs This parameter can be a combination of the following values:
01073   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01074   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01075   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
01076   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01077   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01078   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
01079   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01080   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01081   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01082   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01083   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
01084   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01085   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01086   *
01087   *         (*) value not defined in all devices.
01088   * @retval None
01089   */
01090 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01091 {
01092   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
01093 }
01094
01095 /**
01096   * @brief  Unfreeze APB1 peripherals (group2 peripherals)
01097   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
01098   * @param  Periphs This parameter can be a combination of the following values:
01099   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
01100   *
01101   *         (*) value not defined in all devices.
01102   * @retval None
01103   */
01104 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
01105 {
01106   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
01107 }
01108
01109 /**
01110   * @brief  Freeze APB2 peripherals
01111   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01112   * @param  Periphs This parameter can be a combination of the following values:
01113   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01114   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
01115   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01116   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01117   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01118   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
01119   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
01120   *
01121   *         (*) value not defined in all devices.
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01125 {
01126   SET_BIT(DBGMCU->APB2FZ, Periphs);
01127 }
01128
01129 /**
01130   * @brief  Unfreeze APB2 peripherals
01131   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01132   * @param  Periphs This parameter can be a combination of the following values:
01133   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01134   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
01135   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01136   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01137   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01138   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
01139   *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
01140   *
01141   *         (*) value not defined in all devices.
01142   * @retval None
01143   */
01144 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01145 {
01146   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
01147 }
01148
01149 /**
01150   * @}
01151   */
01152
01153 #if defined(VREFBUF)
01154 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
01155   * @{
01156   */
01157
01158 /**
01159   * @brief  Enable Internal voltage reference
01160   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
01161   * @retval None
01162   */
01163 __STATIC_INLINE void LL_VREFBUF_Enable(void)
01164 {
01165   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01166 }
01167
01168 /**
01169   * @brief  Disable Internal voltage reference
01170   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
01171   * @retval None
01172   */
01173 __STATIC_INLINE void LL_VREFBUF_Disable(void)
01174 {
01175   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01176 }
01177
01178 /**
01179   * @brief  Enable high impedance (VREF+pin is high impedance)
01180   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
01184 {
01185   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01186 }
01187
01188 /**
01189   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
01190   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
01191   * @retval None
01192   */
01193 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
01194 {
01195   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01196 }
01197
01198 /**
01199   * @brief  Set the Voltage reference scale
01200   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
01201   * @param  Scale This parameter can be one of the following values:
01202   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01203   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01204   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
01205   * @retval None
01206   */
01207 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
01208 {
01209   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
01210 }
01211
01212 /**
01213   * @brief  Get the Voltage reference scale
01214   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
01215   * @retval Returned value can be one of the following values:
01216   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01217   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01218   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
01219   */
01220 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
01221 {
01222   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
01223 }
01224
01225 /**
01226   * @brief  Check if Voltage reference buffer is ready
01227   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
01228   * @retval State of bit (1 or 0).
01229   */
01230 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
01231 {
01232   return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
01233 }
01234
01235 /**
01236   * @brief  Get the trimming code for VREFBUF calibration
01237   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
01238   * @retval Between 0 and 0x3F
01239   */
01240 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
01241 {
01242   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
01243 }
01244
01245 /**
01246   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
01247   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
01248   * @param  Value Between 0 and 0x3F
01249   * @retval None
01250   */
01251 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
01252 {
01253   WRITE_REG(VREFBUF->CCR, Value);
01254 }
01255
01256 /**
01257   * @}
01258   */
01259 #endif /* VREFBUF */
01260
01261 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01262   * @{
01263   */
01264
01265 /**
01266   * @brief  Set FLASH Latency
01267   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
01268   * @param  Latency This parameter can be one of the following values:
01269   *         @arg @ref LL_FLASH_LATENCY_0
01270   *         @arg @ref LL_FLASH_LATENCY_1
01271   *         @arg @ref LL_FLASH_LATENCY_2
01272   *         @arg @ref LL_FLASH_LATENCY_3
01273   *         @arg @ref LL_FLASH_LATENCY_4
01274   *         @arg @ref LL_FLASH_LATENCY_5 (*)
01275   *         @arg @ref LL_FLASH_LATENCY_6 (*)
01276   *         @arg @ref LL_FLASH_LATENCY_7 (*)
01277   *         @arg @ref LL_FLASH_LATENCY_8 (*)
01278   *         @arg @ref LL_FLASH_LATENCY_9 (*)
01279   *         @arg @ref LL_FLASH_LATENCY_10 (*)
01280   *         @arg @ref LL_FLASH_LATENCY_11 (*)
01281   *         @arg @ref LL_FLASH_LATENCY_12 (*)
01282   *         @arg @ref LL_FLASH_LATENCY_13 (*)
01283   *         @arg @ref LL_FLASH_LATENCY_14 (*)
01284   *         @arg @ref LL_FLASH_LATENCY_15 (*)
01285   *
01286   *         (*) value not defined in all devices.
01287   * @retval None
01288   */
01289 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01290 {
01291   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01292 }
01293
01294 /**
01295   * @brief  Get FLASH Latency
01296   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
01297   * @retval Returned value can be one of the following values:
01298   *         @arg @ref LL_FLASH_LATENCY_0
01299   *         @arg @ref LL_FLASH_LATENCY_1
01300   *         @arg @ref LL_FLASH_LATENCY_2
01301   *         @arg @ref LL_FLASH_LATENCY_3
01302   *         @arg @ref LL_FLASH_LATENCY_4
01303   *         @arg @ref LL_FLASH_LATENCY_5 (*)
01304   *         @arg @ref LL_FLASH_LATENCY_6 (*)
01305   *         @arg @ref LL_FLASH_LATENCY_7 (*)
01306   *         @arg @ref LL_FLASH_LATENCY_8 (*)
01307   *         @arg @ref LL_FLASH_LATENCY_9 (*)
01308   *         @arg @ref LL_FLASH_LATENCY_10 (*)
01309   *         @arg @ref LL_FLASH_LATENCY_11 (*)
01310   *         @arg @ref LL_FLASH_LATENCY_12 (*)
01311   *         @arg @ref LL_FLASH_LATENCY_13 (*)
01312   *         @arg @ref LL_FLASH_LATENCY_14 (*)
01313   *         @arg @ref LL_FLASH_LATENCY_15 (*)
01314   *
01315   *         (*) value not defined in all devices.
01316   */
01317 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01318 {
01319   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01320 }
01321
01322 /**
01323   * @brief  Enable Prefetch
01324   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
01325   * @retval None
01326   */
01327 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01328 {
01329   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01330 }
01331
01332 /**
01333   * @brief  Disable Prefetch
01334   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
01335   * @retval None
01336   */
01337 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
01338 {
01339   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01340 }
01341
01342 /**
01343   * @brief  Check if Prefetch buffer is enabled
01344   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
01345   * @retval State of bit (1 or 0).
01346   */
01347 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
01348 {
01349   return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
01350 }
01351
01352 /**
01353   * @brief  Enable Instruction cache
01354   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
01355   * @retval None
01356   */
01357 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
01358 {
01359   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01360 }
01361
01362 /**
01363   * @brief  Disable Instruction cache
01364   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
01365   * @retval None
01366   */
01367 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
01368 {
01369   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01370 }
01371
01372 /**
01373   * @brief  Enable Data cache
01374   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
01375   * @retval None
01376   */
01377 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
01378 {
01379   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01380 }
01381
01382 /**
01383   * @brief  Disable Data cache
01384   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
01385   * @retval None
01386   */
01387 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
01388 {
01389   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01390 }
01391
01392 /**
01393   * @brief  Enable Instruction cache reset
01394   * @note  bit can be written only when the instruction cache is disabled
01395   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
01396   * @retval None
01397   */
01398 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
01399 {
01400   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01401 }
01402
01403 /**
01404   * @brief  Disable Instruction cache reset
01405   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
01406   * @retval None
01407   */
01408 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
01409 {
01410   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01411 }
01412
01413 /**
01414   * @brief  Enable Data cache reset
01415   * @note bit can be written only when the data cache is disabled
01416   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
01417   * @retval None
01418   */
01419 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
01420 {
01421   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01422 }
01423
01424 /**
01425   * @brief  Disable Data cache reset
01426   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
01427   * @retval None
01428   */
01429 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
01430 {
01431   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01432 }
01433
01434 /**
01435   * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
01436   * @note Flash memory can be put in power-down mode only when the code is executed
01437   *       from RAM
01438   * @note Flash must not be accessed when power down is enabled
01439   * @note Flash must not be put in power-down while a program or an erase operation
01440   *       is on-going
01441   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
01442   *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
01443   *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
01444   * @retval None
01445   */
01446 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
01447 {
01448   /* Following values must be written consecutively to unlock the RUN_PD bit in
01449      FLASH_ACR */
01450   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01451   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01452   SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01453 }
01454
01455 /**
01456   * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
01457   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
01458   *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
01459   *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
01460   * @retval None
01461   */
01462 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
01463 {
01464   /* Following values must be written consecutively to unlock the RUN_PD bit in
01465      FLASH_ACR */
01466   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01467   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01468   CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01469 }
01470
01471 /**
01472   * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
01473   * @note Flash must not be put in power-down while a program or an erase operation
01474   *       is on-going
01475   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
01479 {
01480   SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01481 }
01482
01483 /**
01484   * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
01485   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
01489 {
01490   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01491 }
01492
01493 /**
01494   * @}
01495   */
01496
01497 /**
01498   * @}
01499   */
01500
01501 /**
01502   * @}
01503   */
01504
01505 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
01506
01507 /**
01508   * @}
01509   */
01510
01511 #ifdef __cplusplus
01512 }
01513 #endif
01514
01515 #endif /* __STM32G4xx_LL_SYSTEM_H */
01516
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_tim.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_tim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_tim.h"
00022 #include "stm32g4xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
00035
00036 /** @addtogroup TIM_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup TIM_LL_Private_Macros
00045   * @{
00046   */
00047 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00048                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00049                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00050                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00051                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00052
00053 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00054                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00055                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00056
00057 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00058                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00059                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00060                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00061                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00062                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00063                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00064                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00065                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00066                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00067                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00068                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00069                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
00070                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
00071                                      || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
00072                                      || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
00073
00074 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00075                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00076
00077 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00078                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00079
00080 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00081                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00082
00083 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00084                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00085                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00086
00087 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00088                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00089                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00090                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00091
00092 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00093                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00094                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00095                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00096                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00097                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00098                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00099                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00106                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00107                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00108
00109 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00110                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00111                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00112
00113 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00114                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00115                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
00116                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
00117                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
00118                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
00119                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
00120                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
00121                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
00122
00123 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00124                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00125
00126 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00127                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00128
00129 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00130                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00131
00132 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00133                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00134                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00135                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00136
00137 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00138                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00139
00140 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00141                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00142
00143 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
00144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
00145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
00146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
00147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
00148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
00149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
00150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
00151                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
00152                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
00153                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
00154                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
00155                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
00156                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
00157                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
00158                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
00159
00160 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
00161                                            || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
00162
00163 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
00164                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
00165
00166 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
00167                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
00168
00169 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
00170                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
00171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
00172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
00173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
00174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
00175                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
00176                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
00177                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
00178                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
00179                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
00180                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
00181                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
00182                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
00183                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
00184                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
00185
00186 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
00187                                             || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
00188
00189 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00190                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00191 /**
00192   * @}
00193   */
00194
00195
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00198   * @{
00199   */
00200 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00201 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00202 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00203 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00204 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00205 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00206 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00207 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00208 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00209 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported functions --------------------------------------------------------*/
00215 /** @addtogroup TIM_LL_Exported_Functions
00216   * @{
00217   */
00218
00219 /** @addtogroup TIM_LL_EF_Init
00220   * @{
00221   */
00222
00223 /**
00224   * @brief  Set TIMx registers to their reset values.
00225   * @param  TIMx Timer instance
00226   * @retval An ErrorStatus enumeration value:
00227   *          - SUCCESS: TIMx registers are de-initialized
00228   *          - ERROR: invalid TIMx instance
00229   */
00230 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
00231 {
00232   ErrorStatus result = SUCCESS;
00233
00234   /* Check the parameters */
00235   assert_param(IS_TIM_INSTANCE(TIMx));
00236
00237   if (TIMx == TIM1)
00238   {
00239     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00240     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00241   }
00242   else if (TIMx == TIM2)
00243   {
00244     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00245     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00246   }
00247   else if (TIMx == TIM3)
00248   {
00249     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00250     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00251   }
00252   else if (TIMx == TIM4)
00253   {
00254     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00255     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00256   }
00257 #if defined(TIM5)
00258   else if (TIMx == TIM5)
00259   {
00260     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
00261     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
00262   }
00263 #endif /* TIM5 */
00264   else if (TIMx == TIM6)
00265   {
00266     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00267     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00268   }
00269   else if (TIMx == TIM7)
00270   {
00271     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00272     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00273   }
00274   else if (TIMx == TIM8)
00275   {
00276     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
00277     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
00278   }
00279   else if (TIMx == TIM15)
00280   {
00281     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00282     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00283   }
00284   else if (TIMx == TIM16)
00285   {
00286     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00287     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00288   }
00289   else if (TIMx == TIM17)
00290   {
00291     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00292     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00293   }
00294 #if defined(TIM20)
00295   else if (TIMx == TIM20)
00296   {
00297     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
00298     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
00299   }
00300 #endif /* TIM20 */
00301   else
00302   {
00303     result = ERROR;
00304   }
00305
00306   return result;
00307 }
00308
00309 /**
00310   * @brief  Set the fields of the time base unit configuration data structure
00311   *         to their default values.
00312   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00313   * @retval None
00314   */
00315 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00316 {
00317   /* Set the default configuration */
00318   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
00319   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00320   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00321   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00322   TIM_InitStruct->RepetitionCounter = 0x00000000U;
00323 }
00324
00325 /**
00326   * @brief  Configure the TIMx time base unit.
00327   * @param  TIMx Timer Instance
00328   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
00329   *         (TIMx time base unit configuration data structure)
00330   * @retval An ErrorStatus enumeration value:
00331   *          - SUCCESS: TIMx registers are de-initialized
00332   *          - ERROR: not applicable
00333   */
00334 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
00335 {
00336   uint32_t tmpcr1;
00337
00338   /* Check the parameters */
00339   assert_param(IS_TIM_INSTANCE(TIMx));
00340   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00341   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00342
00343   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00344
00345   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00346   {
00347     /* Select the Counter Mode */
00348     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00349   }
00350
00351   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00352   {
00353     /* Set the clock division */
00354     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00355   }
00356
00357   /* Write to TIMx CR1 */
00358   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00359
00360   /* Set the Autoreload value */
00361   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00362
00363   /* Set the Prescaler value */
00364   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00365
00366   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00367   {
00368     /* Set the Repetition Counter value */
00369     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00370   }
00371
00372   /* Generate an update event to reload the Prescaler
00373      and the repetition counter value (if applicable) immediately */
00374   LL_TIM_GenerateEvent_UPDATE(TIMx);
00375
00376   return SUCCESS;
00377 }
00378
00379 /**
00380   * @brief  Set the fields of the TIMx output channel configuration data
00381   *         structure to their default values.
00382   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
00383   *         (the output channel configuration data structure)
00384   * @retval None
00385   */
00386 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00387 {
00388   /* Set the default configuration */
00389   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00390   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00391   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00392   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00393   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00394   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00395   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00396   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00397 }
00398
00399 /**
00400   * @brief  Configure the TIMx output channel.
00401   * @param  TIMx Timer Instance
00402   * @param  Channel This parameter can be one of the following values:
00403   *         @arg @ref LL_TIM_CHANNEL_CH1
00404   *         @arg @ref LL_TIM_CHANNEL_CH2
00405   *         @arg @ref LL_TIM_CHANNEL_CH3
00406   *         @arg @ref LL_TIM_CHANNEL_CH4
00407   *         @arg @ref LL_TIM_CHANNEL_CH5
00408   *         @arg @ref LL_TIM_CHANNEL_CH6
00409   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
00410   *         data structure)
00411   * @retval An ErrorStatus enumeration value:
00412   *          - SUCCESS: TIMx output channel is initialized
00413   *          - ERROR: TIMx output channel is not initialized
00414   */
00415 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00416 {
00417   ErrorStatus result = ERROR;
00418
00419   switch (Channel)
00420   {
00421     case LL_TIM_CHANNEL_CH1:
00422       result = OC1Config(TIMx, TIM_OC_InitStruct);
00423       break;
00424     case LL_TIM_CHANNEL_CH2:
00425       result = OC2Config(TIMx, TIM_OC_InitStruct);
00426       break;
00427     case LL_TIM_CHANNEL_CH3:
00428       result = OC3Config(TIMx, TIM_OC_InitStruct);
00429       break;
00430     case LL_TIM_CHANNEL_CH4:
00431       result = OC4Config(TIMx, TIM_OC_InitStruct);
00432       break;
00433     case LL_TIM_CHANNEL_CH5:
00434       result = OC5Config(TIMx, TIM_OC_InitStruct);
00435       break;
00436     case LL_TIM_CHANNEL_CH6:
00437       result = OC6Config(TIMx, TIM_OC_InitStruct);
00438       break;
00439     default:
00440       break;
00441   }
00442
00443   return result;
00444 }
00445
00446 /**
00447   * @brief  Set the fields of the TIMx input channel configuration data
00448   *         structure to their default values.
00449   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
00450   *         data structure)
00451   * @retval None
00452   */
00453 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00454 {
00455   /* Set the default configuration */
00456   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00457   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00458   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00459   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00460 }
00461
00462 /**
00463   * @brief  Configure the TIMx input channel.
00464   * @param  TIMx Timer Instance
00465   * @param  Channel This parameter can be one of the following values:
00466   *         @arg @ref LL_TIM_CHANNEL_CH1
00467   *         @arg @ref LL_TIM_CHANNEL_CH2
00468   *         @arg @ref LL_TIM_CHANNEL_CH3
00469   *         @arg @ref LL_TIM_CHANNEL_CH4
00470   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
00471   *         structure)
00472   * @retval An ErrorStatus enumeration value:
00473   *          - SUCCESS: TIMx output channel is initialized
00474   *          - ERROR: TIMx output channel is not initialized
00475   */
00476 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00477 {
00478   ErrorStatus result = ERROR;
00479
00480   switch (Channel)
00481   {
00482     case LL_TIM_CHANNEL_CH1:
00483       result = IC1Config(TIMx, TIM_IC_InitStruct);
00484       break;
00485     case LL_TIM_CHANNEL_CH2:
00486       result = IC2Config(TIMx, TIM_IC_InitStruct);
00487       break;
00488     case LL_TIM_CHANNEL_CH3:
00489       result = IC3Config(TIMx, TIM_IC_InitStruct);
00490       break;
00491     case LL_TIM_CHANNEL_CH4:
00492       result = IC4Config(TIMx, TIM_IC_InitStruct);
00493       break;
00494     default:
00495       break;
00496   }
00497
00498   return result;
00499 }
00500
00501 /**
00502   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00503   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
00504   *         configuration data structure)
00505   * @retval None
00506   */
00507 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00508 {
00509   /* Set the default configuration */
00510   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00511   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00512   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00513   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00514   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00515   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00516   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00517   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00518   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00519 }
00520
00521 /**
00522   * @brief  Configure the encoder interface of the timer instance.
00523   * @param  TIMx Timer Instance
00524   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
00525   *         configuration data structure)
00526   * @retval An ErrorStatus enumeration value:
00527   *          - SUCCESS: TIMx registers are de-initialized
00528   *          - ERROR: not applicable
00529   */
00530 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00531 {
00532   uint32_t tmpccmr1;
00533   uint32_t tmpccer;
00534
00535   /* Check the parameters */
00536   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00537   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00538   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00539   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00540   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00541   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00542   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00543   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00544   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00545   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00546
00547   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00548   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00549
00550   /* Get the TIMx CCMR1 register value */
00551   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00552
00553   /* Get the TIMx CCER register value */
00554   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00555
00556   /* Configure TI1 */
00557   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00558   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00559   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00560   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00561
00562   /* Configure TI2 */
00563   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00564   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00565   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00566   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00567
00568   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00569   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00570   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00571   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00572   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00573
00574   /* Set encoder mode */
00575   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00576
00577   /* Write to TIMx CCMR1 */
00578   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00579
00580   /* Write to TIMx CCER */
00581   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00582
00583   return SUCCESS;
00584 }
00585
00586 /**
00587   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00588   *         structure to their default values.
00589   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
00590   *         configuration data structure)
00591   * @retval None
00592   */
00593 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00594 {
00595   /* Set the default configuration */
00596   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00597   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00598   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00599   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00600 }
00601
00602 /**
00603   * @brief  Configure the Hall sensor interface of the timer instance.
00604   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00605   *       to the TI1 input channel
00606   * @note TIMx slave mode controller is configured in reset mode.
00607           Selected internal trigger is TI1F_ED.
00608   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00609   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00610   *       between 2 changes on the inputs. It gives information about motor speed.
00611   * @note Channel 2 is configured in output PWM 2 mode.
00612   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00613   * @note OC2REF is selected as trigger output on TRGO.
00614   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00615   *       when TIMx operates in Hall sensor interface mode.
00616   * @param  TIMx Timer Instance
00617   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
00618   *         interface configuration data structure)
00619   * @retval An ErrorStatus enumeration value:
00620   *          - SUCCESS: TIMx registers are de-initialized
00621   *          - ERROR: not applicable
00622   */
00623 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00624 {
00625   uint32_t tmpcr2;
00626   uint32_t tmpccmr1;
00627   uint32_t tmpccer;
00628   uint32_t tmpsmcr;
00629
00630   /* Check the parameters */
00631   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00632   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00633   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00634   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00635
00636   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00637   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00638
00639   /* Get the TIMx CR2 register value */
00640   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00641
00642   /* Get the TIMx CCMR1 register value */
00643   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00644
00645   /* Get the TIMx CCER register value */
00646   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00647
00648   /* Get the TIMx SMCR register value */
00649   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00650
00651   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00652   tmpcr2 |= TIM_CR2_TI1S;
00653
00654   /* OC2REF signal is used as trigger output (TRGO) */
00655   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00656
00657   /* Configure the slave mode controller */
00658   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00659   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00660   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00661
00662   /* Configure input channel 1 */
00663   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00664   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00665   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00666   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00667
00668   /* Configure input channel 2 */
00669   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00670   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00671
00672   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00673   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00674   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00675   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00676
00677   /* Write to TIMx CR2 */
00678   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00679
00680   /* Write to TIMx SMCR */
00681   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00682
00683   /* Write to TIMx CCMR1 */
00684   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00685
00686   /* Write to TIMx CCER */
00687   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00688
00689   /* Write to TIMx CCR2 */
00690   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00691
00692   return SUCCESS;
00693 }
00694
00695 /**
00696   * @brief  Set the fields of the Break and Dead Time configuration data structure
00697   *         to their default values.
00698   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
00699   *         data structure)
00700   * @retval None
00701   */
00702 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00703 {
00704   /* Set the default configuration */
00705   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00706   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00707   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00708   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
00709   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00710   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00711   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
00712   TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
00713   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
00714   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
00715   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
00716   TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
00717   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00718 }
00719
00720 /**
00721   * @brief  Configure the Break and Dead Time feature of the timer instance.
00722   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
00723   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
00724   *  can be necessary to configure all of them during the first write access to
00725   *  the TIMx_BDTR register.
00726   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00727   *       a timer instance provides a break input.
00728   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
00729   *       a timer instance provides a second break input.
00730   * @param  TIMx Timer Instance
00731   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
00732   *         data structure)
00733   * @retval An ErrorStatus enumeration value:
00734   *          - SUCCESS: Break and Dead Time is initialized
00735   *          - ERROR: not applicable
00736   */
00737 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00738 {
00739   uint32_t tmpbdtr = 0;
00740
00741   /* Check the parameters */
00742   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00743   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00744   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00745   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00746   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00747   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00748   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00749   assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
00750   assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
00751
00752   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00753   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00754
00755   /* Set the BDTR bits */
00756   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00757   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00758   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00759   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00760   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00761   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00762   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00763   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
00764   MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
00765
00766   if (IS_TIM_BKIN2_INSTANCE(TIMx))
00767   {
00768     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
00769     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
00770     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
00771     assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
00772
00773     /* Set the BREAK2 input related BDTR bit-fields */
00774     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
00775     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
00776     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
00777     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
00778   }
00779
00780   /* Set TIMx_BDTR */
00781   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00782
00783   return SUCCESS;
00784 }
00785 /**
00786   * @}
00787   */
00788
00789 /**
00790   * @}
00791   */
00792
00793 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00794   *  @brief   Private functions
00795   * @{
00796   */
00797 /**
00798   * @brief  Configure the TIMx output channel 1.
00799   * @param  TIMx Timer Instance
00800   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00801   * @retval An ErrorStatus enumeration value:
00802   *          - SUCCESS: TIMx registers are de-initialized
00803   *          - ERROR: not applicable
00804   */
00805 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00806 {
00807   uint32_t tmpccmr1;
00808   uint32_t tmpccer;
00809   uint32_t tmpcr2;
00810
00811   /* Check the parameters */
00812   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00813   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00814   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00815   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00816
00817   /* Disable the Channel 1: Reset the CC1E Bit */
00818   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00819
00820   /* Get the TIMx CCER register value */
00821   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00822
00823   /* Get the TIMx CR2 register value */
00824   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00825
00826   /* Get the TIMx CCMR1 register value */
00827   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00828
00829   /* Reset Capture/Compare selection Bits */
00830   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00831
00832   /* Set the Output Compare Mode */
00833   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00834
00835   /* Set the Output Compare Polarity */
00836   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00837
00838   /* Set the Output State */
00839   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00840
00841   if (IS_TIM_BREAK_INSTANCE(TIMx))
00842   {
00843     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00844     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00845     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00846     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00847
00848     /* Set the complementary output Polarity */
00849     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00850
00851     /* Set the complementary output State */
00852     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00853
00854     /* Set the Output Idle state */
00855     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00856
00857     /* Set the complementary output Idle state */
00858     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00859   }
00860
00861   /* Write to TIMx CR2 */
00862   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00863
00864   /* Write to TIMx CCMR1 */
00865   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00866
00867   /* Set the Capture Compare Register value */
00868   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00869
00870   /* Write to TIMx CCER */
00871   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00872
00873   return SUCCESS;
00874 }
00875
00876 /**
00877   * @brief  Configure the TIMx output channel 2.
00878   * @param  TIMx Timer Instance
00879   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00880   * @retval An ErrorStatus enumeration value:
00881   *          - SUCCESS: TIMx registers are de-initialized
00882   *          - ERROR: not applicable
00883   */
00884 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00885 {
00886   uint32_t tmpccmr1;
00887   uint32_t tmpccer;
00888   uint32_t tmpcr2;
00889
00890   /* Check the parameters */
00891   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00892   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00893   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00894   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00895
00896   /* Disable the Channel 2: Reset the CC2E Bit */
00897   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00898
00899   /* Get the TIMx CCER register value */
00900   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00901
00902   /* Get the TIMx CR2 register value */
00903   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00904
00905   /* Get the TIMx CCMR1 register value */
00906   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00907
00908   /* Reset Capture/Compare selection Bits */
00909   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00910
00911   /* Select the Output Compare Mode */
00912   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00913
00914   /* Set the Output Compare Polarity */
00915   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00916
00917   /* Set the Output State */
00918   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00919
00920   if (IS_TIM_BREAK_INSTANCE(TIMx))
00921   {
00922     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00923     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00924     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00925     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00926
00927     /* Set the complementary output Polarity */
00928     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00929
00930     /* Set the complementary output State */
00931     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00932
00933     /* Set the Output Idle state */
00934     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00935
00936     /* Set the complementary output Idle state */
00937     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00938   }
00939
00940   /* Write to TIMx CR2 */
00941   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00942
00943   /* Write to TIMx CCMR1 */
00944   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00945
00946   /* Set the Capture Compare Register value */
00947   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00948
00949   /* Write to TIMx CCER */
00950   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00951
00952   return SUCCESS;
00953 }
00954
00955 /**
00956   * @brief  Configure the TIMx output channel 3.
00957   * @param  TIMx Timer Instance
00958   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00959   * @retval An ErrorStatus enumeration value:
00960   *          - SUCCESS: TIMx registers are de-initialized
00961   *          - ERROR: not applicable
00962   */
00963 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00964 {
00965   uint32_t tmpccmr2;
00966   uint32_t tmpccer;
00967   uint32_t tmpcr2;
00968
00969   /* Check the parameters */
00970   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00971   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00972   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00973   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00974
00975   /* Disable the Channel 3: Reset the CC3E Bit */
00976   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00977
00978   /* Get the TIMx CCER register value */
00979   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00980
00981   /* Get the TIMx CR2 register value */
00982   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00983
00984   /* Get the TIMx CCMR2 register value */
00985   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00986
00987   /* Reset Capture/Compare selection Bits */
00988   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00989
00990   /* Select the Output Compare Mode */
00991   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
00992
00993   /* Set the Output Compare Polarity */
00994   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
00995
00996   /* Set the Output State */
00997   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
00998
00999   if (IS_TIM_BREAK_INSTANCE(TIMx))
01000   {
01001     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01002     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01003     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01004     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01005
01006     /* Set the complementary output Polarity */
01007     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
01008
01009     /* Set the complementary output State */
01010     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
01011
01012     /* Set the Output Idle state */
01013     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
01014
01015     /* Set the complementary output Idle state */
01016     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
01017   }
01018
01019   /* Write to TIMx CR2 */
01020   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01021
01022   /* Write to TIMx CCMR2 */
01023   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01024
01025   /* Set the Capture Compare Register value */
01026   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
01027
01028   /* Write to TIMx CCER */
01029   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01030
01031   return SUCCESS;
01032 }
01033
01034 /**
01035   * @brief  Configure the TIMx output channel 4.
01036   * @param  TIMx Timer Instance
01037   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
01038   * @retval An ErrorStatus enumeration value:
01039   *          - SUCCESS: TIMx registers are de-initialized
01040   *          - ERROR: not applicable
01041   */
01042 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01043 {
01044   uint32_t tmpccmr2;
01045   uint32_t tmpccer;
01046   uint32_t tmpcr2;
01047
01048   /* Check the parameters */
01049   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01050   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01051   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01052   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01053
01054   /* Disable the Channel 4: Reset the CC4E Bit */
01055   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
01056
01057   /* Get the TIMx CCER register value */
01058   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01059
01060   /* Get the TIMx CR2 register value */
01061   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
01062
01063   /* Get the TIMx CCMR2 register value */
01064   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01065
01066   /* Reset Capture/Compare selection Bits */
01067   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01068
01069   /* Select the Output Compare Mode */
01070   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01071
01072   /* Set the Output Compare Polarity */
01073   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01074
01075   /* Set the Output State */
01076   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01077
01078   if (IS_TIM_BREAK_INSTANCE(TIMx))
01079   {
01080     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01081     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01082     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01083     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01084
01085     /* Set the complementary output Polarity */
01086     MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
01087
01088     /* Set the complementary output State */
01089     MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
01090
01091     /* Set the Output Idle state */
01092     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01093
01094     /* Set the complementary output Idle state */
01095     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
01096   }
01097
01098   /* Write to TIMx CR2 */
01099   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01100
01101   /* Write to TIMx CCMR2 */
01102   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01103
01104   /* Set the Capture Compare Register value */
01105   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01106
01107   /* Write to TIMx CCER */
01108   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01109
01110   return SUCCESS;
01111 }
01112
01113 /**
01114   * @brief  Configure the TIMx output channel 5.
01115   * @param  TIMx Timer Instance
01116   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
01117   * @retval An ErrorStatus enumeration value:
01118   *          - SUCCESS: TIMx registers are de-initialized
01119   *          - ERROR: not applicable
01120   */
01121 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01122 {
01123   uint32_t tmpccmr3;
01124   uint32_t tmpccer;
01125
01126   /* Check the parameters */
01127   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
01128   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01129   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01130   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01131   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01132   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01133
01134   /* Disable the Channel 5: Reset the CC5E Bit */
01135   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
01136
01137   /* Get the TIMx CCER register value */
01138   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01139
01140   /* Get the TIMx CCMR3 register value */
01141   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01142
01143   /* Select the Output Compare Mode */
01144   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
01145
01146   /* Set the Output Compare Polarity */
01147   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
01148
01149   /* Set the Output State */
01150   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
01151
01152   if (IS_TIM_BREAK_INSTANCE(TIMx))
01153   {
01154     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01155     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01156
01157     /* Set the Output Idle state */
01158     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01159
01160   }
01161
01162   /* Write to TIMx CCMR3 */
01163   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01164
01165   /* Set the Capture Compare Register value */
01166   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01167
01168   /* Write to TIMx CCER */
01169   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01170
01171   return SUCCESS;
01172 }
01173
01174 /**
01175   * @brief  Configure the TIMx output channel 6.
01176   * @param  TIMx Timer Instance
01177   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01178   * @retval An ErrorStatus enumeration value:
01179   *          - SUCCESS: TIMx registers are de-initialized
01180   *          - ERROR: not applicable
01181   */
01182 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01183 {
01184   uint32_t tmpccmr3;
01185   uint32_t tmpccer;
01186
01187   /* Check the parameters */
01188   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01189   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01190   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01191   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01192   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01193   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01194
01195   /* Disable the Channel 5: Reset the CC6E Bit */
01196   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01197
01198   /* Get the TIMx CCER register value */
01199   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01200
01201   /* Get the TIMx CCMR3 register value */
01202   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01203
01204   /* Select the Output Compare Mode */
01205   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01206
01207   /* Set the Output Compare Polarity */
01208   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01209
01210   /* Set the Output State */
01211   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01212
01213   if (IS_TIM_BREAK_INSTANCE(TIMx))
01214   {
01215     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01216     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01217
01218     /* Set the Output Idle state */
01219     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01220   }
01221
01222   /* Write to TIMx CCMR3 */
01223   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01224
01225   /* Set the Capture Compare Register value */
01226   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01227
01228   /* Write to TIMx CCER */
01229   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01230
01231   return SUCCESS;
01232 }
01233
01234 /**
01235   * @brief  Configure the TIMx input channel 1.
01236   * @param  TIMx Timer Instance
01237   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01238   * @retval An ErrorStatus enumeration value:
01239   *          - SUCCESS: TIMx registers are de-initialized
01240   *          - ERROR: not applicable
01241   */
01242 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01243 {
01244   /* Check the parameters */
01245   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01246   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01247   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01248   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01249   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01250
01251   /* Disable the Channel 1: Reset the CC1E Bit */
01252   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01253
01254   /* Select the Input and set the filter and the prescaler value */
01255   MODIFY_REG(TIMx->CCMR1,
01256              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01257              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01258
01259   /* Select the Polarity and set the CC1E Bit */
01260   MODIFY_REG(TIMx->CCER,
01261              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01262              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01263
01264   return SUCCESS;
01265 }
01266
01267 /**
01268   * @brief  Configure the TIMx input channel 2.
01269   * @param  TIMx Timer Instance
01270   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01271   * @retval An ErrorStatus enumeration value:
01272   *          - SUCCESS: TIMx registers are de-initialized
01273   *          - ERROR: not applicable
01274   */
01275 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01276 {
01277   /* Check the parameters */
01278   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01279   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01280   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01281   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01282   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01283
01284   /* Disable the Channel 2: Reset the CC2E Bit */
01285   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01286
01287   /* Select the Input and set the filter and the prescaler value */
01288   MODIFY_REG(TIMx->CCMR1,
01289              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01290              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01291
01292   /* Select the Polarity and set the CC2E Bit */
01293   MODIFY_REG(TIMx->CCER,
01294              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01295              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01296
01297   return SUCCESS;
01298 }
01299
01300 /**
01301   * @brief  Configure the TIMx input channel 3.
01302   * @param  TIMx Timer Instance
01303   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01304   * @retval An ErrorStatus enumeration value:
01305   *          - SUCCESS: TIMx registers are de-initialized
01306   *          - ERROR: not applicable
01307   */
01308 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01309 {
01310   /* Check the parameters */
01311   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01312   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01313   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01314   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01315   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01316
01317   /* Disable the Channel 3: Reset the CC3E Bit */
01318   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01319
01320   /* Select the Input and set the filter and the prescaler value */
01321   MODIFY_REG(TIMx->CCMR2,
01322              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01323              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01324
01325   /* Select the Polarity and set the CC3E Bit */
01326   MODIFY_REG(TIMx->CCER,
01327              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01328              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01329
01330   return SUCCESS;
01331 }
01332
01333 /**
01334   * @brief  Configure the TIMx input channel 4.
01335   * @param  TIMx Timer Instance
01336   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01337   * @retval An ErrorStatus enumeration value:
01338   *          - SUCCESS: TIMx registers are de-initialized
01339   *          - ERROR: not applicable
01340   */
01341 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01342 {
01343   /* Check the parameters */
01344   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01345   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01346   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01347   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01348   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01349
01350   /* Disable the Channel 4: Reset the CC4E Bit */
01351   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01352
01353   /* Select the Input and set the filter and the prescaler value */
01354   MODIFY_REG(TIMx->CCMR2,
01355              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01356              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01357
01358   /* Select the Polarity and set the CC4E Bit */
01359   MODIFY_REG(TIMx->CCER,
01360              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01361              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01362
01363   return SUCCESS;
01364 }
01365
01366
01367 /**
01368   * @}
01369   */
01370
01371 /**
01372   * @}
01373   */
01374
01375 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
01376
01377 /**
01378   * @}
01379   */
01380
01381 #endif /* USE_FULL_LL_DRIVER */
01382
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_tim.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_tim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G4xx_LL_TIM_H
00021 #define __STM32G4xx_LL_TIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
00035
00036 /** @defgroup TIM_LL TIM
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00043   * @{
00044   */
00045 static const uint8_t OFFSET_TAB_CCMRx[] =
00046 {
00047   0x00U,   /* 0: TIMx_CH1  */
00048   0x00U,   /* 1: TIMx_CH1N */
00049   0x00U,   /* 2: TIMx_CH2  */
00050   0x00U,   /* 3: TIMx_CH2N */
00051   0x04U,   /* 4: TIMx_CH3  */
00052   0x04U,   /* 5: TIMx_CH3N */
00053   0x04U,   /* 6: TIMx_CH4  */
00054   0x04U,   /* 7: TIMx_CH4N */
00055   0x38U,   /* 8: TIMx_CH5  */
00056   0x38U    /* 9: TIMx_CH6  */
00057
00058 };
00059
00060 static const uint8_t SHIFT_TAB_OCxx[] =
00061 {
00062   0U,            /* 0: OC1M, OC1FE, OC1PE */
00063   0U,            /* 1: - NA */
00064   8U,            /* 2: OC2M, OC2FE, OC2PE */
00065   0U,            /* 3: - NA */
00066   0U,            /* 4: OC3M, OC3FE, OC3PE */
00067   0U,            /* 5: - NA */
00068   8U,            /* 6: OC4M, OC4FE, OC4PE */
00069   0U,            /* 7: - NA */
00070   0U,            /* 8: OC5M, OC5FE, OC5PE */
00071   8U             /* 9: OC6M, OC6FE, OC6PE */
00072 };
00073
00074 static const uint8_t SHIFT_TAB_ICxx[] =
00075 {
00076   0U,            /* 0: CC1S, IC1PSC, IC1F */
00077   0U,            /* 1: - NA */
00078   8U,            /* 2: CC2S, IC2PSC, IC2F */
00079   0U,            /* 3: - NA */
00080   0U,            /* 4: CC3S, IC3PSC, IC3F */
00081   0U,            /* 5: - NA */
00082   8U,            /* 6: CC4S, IC4PSC, IC4F */
00083   0U,            /* 7: - NA */
00084   0U,            /* 8: - NA */
00085   0U             /* 9: - NA */
00086 };
00087
00088 static const uint8_t SHIFT_TAB_CCxP[] =
00089 {
00090   0U,            /* 0: CC1P */
00091   2U,            /* 1: CC1NP */
00092   4U,            /* 2: CC2P */
00093   6U,            /* 3: CC2NP */
00094   8U,            /* 4: CC3P */
00095   10U,           /* 5: CC3NP */
00096   12U,           /* 6: CC4P */
00097   14U,           /* 7: CC4NP */
00098   16U,           /* 8: CC5P */
00099   20U            /* 9: CC6P */
00100 };
00101
00102 static const uint8_t SHIFT_TAB_OISx[] =
00103 {
00104   0U,            /* 0: OIS1 */
00105   1U,            /* 1: OIS1N */
00106   2U,            /* 2: OIS2 */
00107   3U,            /* 3: OIS2N */
00108   4U,            /* 4: OIS3 */
00109   5U,            /* 5: OIS3N */
00110   6U,            /* 6: OIS4 */
00111   7U,            /* 7: OIS4N */
00112   8U,            /* 8: OIS5 */
00113   10U            /* 9: OIS6 */
00114 };
00115 /**
00116   * @}
00117   */
00118
00119 /* Private constants ---------------------------------------------------------*/
00120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00121   * @{
00122   */
00123
00124 /* Defines used for the bit position in the register and perform offsets */
00125 #define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
00126
00127 /* Generic bit definitions for TIMx_AF1 register */
00128 #define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
00129 #define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
00130
00131
00132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00133 #define DT_DELAY_1 ((uint8_t)0x7F)
00134 #define DT_DELAY_2 ((uint8_t)0x3F)
00135 #define DT_DELAY_3 ((uint8_t)0x1F)
00136 #define DT_DELAY_4 ((uint8_t)0x1F)
00137
00138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00139 #define DT_RANGE_1 ((uint8_t)0x00)
00140 #define DT_RANGE_2 ((uint8_t)0x80)
00141 #define DT_RANGE_3 ((uint8_t)0xC0)
00142 #define DT_RANGE_4 ((uint8_t)0xE0)
00143
00144 /** Legacy definitions for compatibility purpose
00145 @cond 0
00146   */
00147 /**
00148 @endcond
00149   */
00150
00151 #define OCREF_CLEAR_SELECT_Pos (28U)
00152 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)                /*!< 0x10000000 */
00153 /**
00154   * @}
00155   */
00156
00157 /* Private macros ------------------------------------------------------------*/
00158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00159   * @{
00160   */
00161 /** @brief  Convert channel id into channel index.
00162   * @param  __CHANNEL__ This parameter can be one of the following values:
00163   *         @arg @ref LL_TIM_CHANNEL_CH1
00164   *         @arg @ref LL_TIM_CHANNEL_CH1N
00165   *         @arg @ref LL_TIM_CHANNEL_CH2
00166   *         @arg @ref LL_TIM_CHANNEL_CH2N
00167   *         @arg @ref LL_TIM_CHANNEL_CH3
00168   *         @arg @ref LL_TIM_CHANNEL_CH3N
00169   *         @arg @ref LL_TIM_CHANNEL_CH4
00170   *         @arg @ref LL_TIM_CHANNEL_CH4N
00171   *         @arg @ref LL_TIM_CHANNEL_CH5
00172   *         @arg @ref LL_TIM_CHANNEL_CH6
00173   * @retval none
00174   */
00175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00176   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00177    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00178    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00179    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00180    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00181    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00182    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00183    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
00184    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
00185
00186 /** @brief  Calculate the deadtime sampling period(in ps).
00187   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00188   * @param  __CKD__ This parameter can be one of the following values:
00189   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00190   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00191   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00192   * @retval none
00193   */
00194 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00195   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00196    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00197    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00198 /**
00199   * @}
00200   */
00201
00202
00203 /* Exported types ------------------------------------------------------------*/
00204 #if defined(USE_FULL_LL_DRIVER)
00205 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00206   * @{
00207   */
00208
00209 /**
00210   * @brief  TIM Time Base configuration structure definition.
00211   */
00212 typedef struct
00213 {
00214   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00215                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00216
00217                                    This feature can be modified afterwards using unitary function
00218                                    @ref LL_TIM_SetPrescaler().*/
00219
00220   uint32_t CounterMode;       /*!< Specifies the counter mode.
00221                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00222
00223                                    This feature can be modified afterwards using unitary function
00224                                    @ref LL_TIM_SetCounterMode().*/
00225
00226   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00227                                    Auto-Reload Register at the next update event.
00228                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00229                                    Some timer instances may support 32 bits counters. In that case this parameter must
00230                                    be a number between 0x0000 and 0xFFFFFFFF.
00231
00232                                    This feature can be modified afterwards using unitary function
00233                                    @ref LL_TIM_SetAutoReload().*/
00234
00235   uint32_t ClockDivision;     /*!< Specifies the clock division.
00236                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00237
00238                                    This feature can be modified afterwards using unitary function
00239                                    @ref LL_TIM_SetClockDivision().*/
00240
00241   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00242                                    reaches zero, an update event is generated and counting restarts
00243                                    from the RCR value (N).
00244                                    This means in PWM mode that (N+1) corresponds to:
00245                                       - the number of PWM periods in edge-aligned mode
00246                                       - the number of half PWM period in center-aligned mode
00247                                    GP timers: this parameter must be a number between Min_Data = 0x00 and
00248                                    Max_Data = 0xFF.
00249                                    Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
00250                                    Max_Data = 0xFFFF.
00251
00252                                    This feature can be modified afterwards using unitary function
00253                                    @ref LL_TIM_SetRepetitionCounter().*/
00254 } LL_TIM_InitTypeDef;
00255
00256 /**
00257   * @brief  TIM Output Compare configuration structure definition.
00258   */
00259 typedef struct
00260 {
00261   uint32_t OCMode;        /*!< Specifies the output mode.
00262                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00263
00264                                This feature can be modified afterwards using unitary function
00265                                @ref LL_TIM_OC_SetMode().*/
00266
00267   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00268                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00269
00270                                This feature can be modified afterwards using unitary functions
00271                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00272
00273   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00274                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00275
00276                                This feature can be modified afterwards using unitary functions
00277                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00278
00279   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00280                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00281
00282                                This feature can be modified afterwards using unitary function
00283                                LL_TIM_OC_SetCompareCHx (x=1..6).*/
00284
00285   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00286                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00287
00288                                This feature can be modified afterwards using unitary function
00289                                @ref LL_TIM_OC_SetPolarity().*/
00290
00291   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00292                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00293
00294                                This feature can be modified afterwards using unitary function
00295                                @ref LL_TIM_OC_SetPolarity().*/
00296
00297
00298   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00299                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00300
00301                                This feature can be modified afterwards using unitary function
00302                                @ref LL_TIM_OC_SetIdleState().*/
00303
00304   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00305                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00306
00307                                This feature can be modified afterwards using unitary function
00308                                @ref LL_TIM_OC_SetIdleState().*/
00309 } LL_TIM_OC_InitTypeDef;
00310
00311 /**
00312   * @brief  TIM Input Capture configuration structure definition.
00313   */
00314
00315 typedef struct
00316 {
00317
00318   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00319                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00320
00321                                This feature can be modified afterwards using unitary function
00322                                @ref LL_TIM_IC_SetPolarity().*/
00323
00324   uint32_t ICActiveInput; /*!< Specifies the input.
00325                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00326
00327                                This feature can be modified afterwards using unitary function
00328                                @ref LL_TIM_IC_SetActiveInput().*/
00329
00330   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00331                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00332
00333                                This feature can be modified afterwards using unitary function
00334                                @ref LL_TIM_IC_SetPrescaler().*/
00335
00336   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00337                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00338
00339                                This feature can be modified afterwards using unitary function
00340                                @ref LL_TIM_IC_SetFilter().*/
00341 } LL_TIM_IC_InitTypeDef;
00342
00343
00344 /**
00345   * @brief  TIM Encoder interface configuration structure definition.
00346   */
00347 typedef struct
00348 {
00349   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00350                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00351
00352                                  This feature can be modified afterwards using unitary function
00353                                  @ref LL_TIM_SetEncoderMode().*/
00354
00355   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00356                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00357
00358                                  This feature can be modified afterwards using unitary function
00359                                  @ref LL_TIM_IC_SetPolarity().*/
00360
00361   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00362                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00363
00364                                  This feature can be modified afterwards using unitary function
00365                                  @ref LL_TIM_IC_SetActiveInput().*/
00366
00367   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00368                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00369
00370                                  This feature can be modified afterwards using unitary function
00371                                  @ref LL_TIM_IC_SetPrescaler().*/
00372
00373   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00374                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00375
00376                                  This feature can be modified afterwards using unitary function
00377                                  @ref LL_TIM_IC_SetFilter().*/
00378
00379   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00380                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00381
00382                                  This feature can be modified afterwards using unitary function
00383                                  @ref LL_TIM_IC_SetPolarity().*/
00384
00385   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00386                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00387
00388                                  This feature can be modified afterwards using unitary function
00389                                  @ref LL_TIM_IC_SetActiveInput().*/
00390
00391   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00392                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00393
00394                                  This feature can be modified afterwards using unitary function
00395                                  @ref LL_TIM_IC_SetPrescaler().*/
00396
00397   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00398                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00399
00400                                  This feature can be modified afterwards using unitary function
00401                                  @ref LL_TIM_IC_SetFilter().*/
00402
00403 } LL_TIM_ENCODER_InitTypeDef;
00404
00405 /**
00406   * @brief  TIM Hall sensor interface configuration structure definition.
00407   */
00408 typedef struct
00409 {
00410
00411   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00412                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00413
00414                                     This feature can be modified afterwards using unitary function
00415                                     @ref LL_TIM_IC_SetPolarity().*/
00416
00417   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00418                                     Prescaler must be set to get a maximum counter period longer than the
00419                                     time interval between 2 consecutive changes on the Hall inputs.
00420                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00421
00422                                     This feature can be modified afterwards using unitary function
00423                                     @ref LL_TIM_IC_SetPrescaler().*/
00424
00425   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00426                                     This parameter can be a value of
00427                                     @ref TIM_LL_EC_IC_FILTER.
00428
00429                                     This feature can be modified afterwards using unitary function
00430                                     @ref LL_TIM_IC_SetFilter().*/
00431
00432   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00433                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00434                                     a change occurs on the Hall inputs.
00435                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00436
00437                                     This feature can be modified afterwards using unitary function
00438                                     @ref LL_TIM_OC_SetCompareCH2().*/
00439 } LL_TIM_HALLSENSOR_InitTypeDef;
00440
00441 /**
00442   * @brief  BDTR (Break and Dead Time) structure definition
00443   */
00444 typedef struct
00445 {
00446   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00447                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00448
00449                                       This feature can be modified afterwards using unitary function
00450                                       @ref LL_TIM_SetOffStates()
00451
00452                                       @note This bit-field cannot be modified as long as LOCK level 2 has been
00453                                        programmed. */
00454
00455   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00456                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00457
00458                                       This feature can be modified afterwards using unitary function
00459                                       @ref LL_TIM_SetOffStates()
00460
00461                                       @note This bit-field cannot be modified as long as LOCK level 2 has been
00462                                       programmed. */
00463
00464   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00465                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00466
00467                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
00468                                       register has been written, their content is frozen until the next reset.*/
00469
00470   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00471                                       switching-on of the outputs.
00472                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00473
00474                                       This feature can be modified afterwards using unitary function
00475                                       @ref LL_TIM_OC_SetDeadTime()
00476
00477                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
00478                                        programmed. */
00479
00480   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00481                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00482
00483                                       This feature can be modified afterwards using unitary functions
00484                                       @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00485
00486                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00487                                       programmed. */
00488
00489   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00490                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00491
00492                                       This feature can be modified afterwards using unitary function
00493                                       @ref LL_TIM_ConfigBRK()
00494
00495                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00496                                       programmed. */
00497
00498   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00499                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00500
00501                                       This feature can be modified afterwards using unitary function
00502                                       @ref LL_TIM_ConfigBRK()
00503
00504                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00505                                       programmed. */
00506
00507   uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
00508                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
00509
00510                                       This feature can be modified afterwards using unitary functions
00511                                       @ref LL_TIM_ConfigBRK()
00512
00513                                       @note Bidirectional break input is only supported by advanced timers instances.
00514
00515                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00516                                       programmed. */
00517
00518   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00519                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00520
00521                                       This feature can be modified afterwards using unitary functions
00522                                       @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00523
00524                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00525                                       programmed. */
00526
00527   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00528                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00529
00530                                       This feature can be modified afterwards using unitary function
00531                                       @ref LL_TIM_ConfigBRK2()
00532
00533                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00534                                       programmed. */
00535
00536   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00537                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00538
00539                                       This feature can be modified afterwards using unitary function
00540                                       @ref LL_TIM_ConfigBRK2()
00541
00542                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00543                                       programmed. */
00544
00545   uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
00546                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
00547
00548                                       This feature can be modified afterwards using unitary functions
00549                                       @ref LL_TIM_ConfigBRK2()
00550
00551                                       @note Bidirectional break input is only supported by advanced timers instances.
00552
00553                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00554                                       programmed. */
00555
00556   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00557                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00558
00559                                       This feature can be modified afterwards using unitary functions
00560                                       @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00561
00562                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00563                                       programmed. */
00564 } LL_TIM_BDTR_InitTypeDef;
00565
00566 /**
00567   * @}
00568   */
00569 #endif /* USE_FULL_LL_DRIVER */
00570
00571 /* Exported constants --------------------------------------------------------*/
00572 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00573   * @{
00574   */
00575
00576 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00577   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00578   * @{
00579   */
00580 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00581 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00582 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00583 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00584 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00585 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00586 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00587 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00588 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00589 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00590 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00591 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00592 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00593 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00594 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00595 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00596 #define LL_TIM_SR_IDXF                         TIM_SR_IDXF          /*!< Index interrupt flag  */
00597 #define LL_TIM_SR_DIRF                         TIM_SR_DIRF          /*!< Direction Change interrupt flag  */
00598 #define LL_TIM_SR_IERRF                        TIM_SR_IERRF         /*!< Index Error flag  */
00599 #define LL_TIM_SR_TERRF                        TIM_SR_TERRF         /*!< Transition Error flag  */
00600 /**
00601   * @}
00602   */
00603
00604 #if defined(USE_FULL_LL_DRIVER)
00605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00606   * @{
00607   */
00608 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00609 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00610 /**
00611   * @}
00612   */
00613
00614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00615   * @{
00616   */
00617 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00618 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00624   * @{
00625   */
00626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00628 /**
00629   * @}
00630   */
00631 #endif /* USE_FULL_LL_DRIVER */
00632
00633 /** @defgroup TIM_LL_EC_IT IT Defines
00634   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00635   * @{
00636   */
00637 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00638 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00639 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00640 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00641 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00642 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00643 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00644 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00645 #define LL_TIM_DIER_IDXIE                      TIM_DIER_IDXIE       /*!< Index interrupt enable */
00646 #define LL_TIM_DIER_DIRIE                      TIM_DIER_DIRIE       /*!< Direction Change interrupt enable */
00647 #define LL_TIM_DIER_IERRIE                     TIM_DIER_IERRIE      /*!< Index Error interrupt enable */
00648 #define LL_TIM_DIER_TERRIE                     TIM_DIER_TERRIE      /*!< Transition Error interrupt enable */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00654   * @{
00655   */
00656 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00657 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00663   * @{
00664   */
00665 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
00666 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
00667 /**
00668   * @}
00669   */
00670
00671 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00672   * @{
00673   */
00674 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
00675 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00676 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00677 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00678 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00684   * @{
00685   */
00686 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00687 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00688 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00694   * @{
00695   */
00696 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00697 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00703   * @{
00704   */
00705 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00706 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00712   * @{
00713   */
00714 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00715 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00716 /**
00717   * @}
00718   */
00719
00720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00721   * @{
00722   */
00723 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00724 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00725 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00726 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup TIM_LL_EC_CHANNEL Channel
00732   * @{
00733   */
00734 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00735 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00736 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00737 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00738 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00739 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00740 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00741 #define LL_TIM_CHANNEL_CH4N                    TIM_CCER_CC4NE     /*!< Timer complementary output channel 4 */
00742 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00743 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00744 /**
00745   * @}
00746   */
00747
00748 #if defined(USE_FULL_LL_DRIVER)
00749 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00750   * @{
00751   */
00752 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00753 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00754 /**
00755   * @}
00756   */
00757 #endif /* USE_FULL_LL_DRIVER */
00758
00759 /** Legacy definitions for compatibility purpose
00760 @cond 0
00761   */
00762 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
00763 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
00764 /**
00765 @endcond
00766   */
00767
00768 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00769   * @{
00770   */
00771 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00772 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00773 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00774 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00775 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
00776 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00777 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00778 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00779 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00780 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00781 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00782 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00783 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00784 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00785 #define LL_TIM_OCMODE_PULSE_ON_COMPARE         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                    /*!<Pulse on Compare mode */
00786 #define LL_TIM_OCMODE_DIRECTION_OUTPUT         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
00787 /**
00788   * @}
00789   */
00790
00791 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00792   * @{
00793   */
00794 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00795 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00801   * @{
00802   */
00803 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00804 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00805 /**
00806   * @}
00807   */
00808
00809 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00810   * @{
00811   */
00812 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00813 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00814 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00815 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00821   * @{
00822   */
00823 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00824 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00825 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00826 /**
00827   * @}
00828   */
00829
00830 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00831   * @{
00832   */
00833 #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00834 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00835 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00836 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00837 /**
00838   * @}
00839   */
00840
00841 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00842   * @{
00843   */
00844 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00845 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00846 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00847 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00848 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00849 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00850 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00851 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00852 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00853 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00854 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00855 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00856 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00857 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00858 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00859 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00865   * @{
00866   */
00867 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00868 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00869 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00875   * @{
00876   */
00877 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00878 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
00879 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00880 /**
00881   * @}
00882   */
00883
00884 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00885   * @{
00886   */
00887 #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00888 #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00889 #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
00890 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction - x2 mode */
00891 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
00892 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2       (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
00893 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12  (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
00894 #define LL_TIM_ENCODERMODE_X1_TI1                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
00895 #define LL_TIM_ENCODERMODE_X1_TI2                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
00896 /**
00897   * @}
00898   */
00899
00900 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00901   * @{
00902   */
00903 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00904 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00905 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00906 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00907 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00908 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00909 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00910 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00911 #define LL_TIM_TRGO_ENCODERCLK                 TIM_CR2_MMS_3                                   /*!< Encoder clock signal is used as trigger output */
00912 /**
00913   * @}
00914   */
00915
00916 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00917   * @{
00918   */
00919 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00920 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00921 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00922 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00923 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00924 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00925 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00926 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00927 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00928 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00929 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00930 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00931 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00932 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00933 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00934 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00940   * @{
00941   */
00942 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00943 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00944 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00945 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00946 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00947 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)   /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
00948                                                                                         the counter are controlled. */
00949 /**
00950   * @}
00951   */
00952
00953 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
00954   * @{
00955   */
00956 #define LL_TIM_SMSPS_TIMUPDATE                 0x00000000U                         /*!< The SMS preload transfer is triggered by the Timer's Update event */
00957 #define LL_TIM_SMSPS_INDEX                     TIM_SMCR_SMSPS                      /*!< The SMS preload transfer is triggered by the Index event */
00958 /**
00959   * @}
00960   */
00961
00962 /** @defgroup TIM_LL_EC_TS Trigger Selection
00963   * @{
00964   */
00965 #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00966 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00967 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00968 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00969 #define LL_TIM_TS_ITR4                         TIM_SMCR_TS_3                                                   /*!< Internal Trigger 4 (ITR4) is used as trigger input */
00970 #define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
00971 #define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
00972 #define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
00973 #define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
00974 #define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
00975 #define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
00976 #define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
00977 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00978 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00979 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00980 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
00981 /**
00982   * @}
00983   */
00984
00985 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00986   * @{
00987   */
00988 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00989 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00990 /**
00991   * @}
00992   */
00993
00994 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00995   * @{
00996   */
00997 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00998 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00999 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
01000 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
01006   * @{
01007   */
01008 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
01009 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
01010 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
01011 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
01012 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
01013 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
01014 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
01015 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
01016 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
01017 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
01018 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
01019 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
01020 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
01021 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
01022 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
01023 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
01024 /**
01025   * @}
01026   */
01027
01028 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
01029   * @{
01030   */
01031 #define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                  /*!< ETR input is connected to GPIO */
01032 #define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
01033 #define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
01034 #define LL_TIM_TIM1_ETRSOURCE_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
01035 #define LL_TIM_TIM1_ETRSOURCE_COMP4       TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
01036 #if defined(COMP5)
01037 #define LL_TIM_TIM1_ETRSOURCE_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
01038 #endif /* COMP5 */
01039 #if defined(COMP6)
01040 #define LL_TIM_TIM1_ETRSOURCE_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
01041 #endif /* COMP6 */
01042 #if defined(COMP7)
01043 #define LL_TIM_TIM1_ETRSOURCE_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
01044 #endif /* COMP7 */
01045 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   TIM1_AF1_ETRSEL_3                                            /*!< ADC1 analog watchdog 1 */
01046 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC1 analog watchdog 2 */
01047 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC1 analog watchdog 3 */
01048 #if defined(ADC4)
01049 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC4 analog watchdog 1 */
01050 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC4 analog watchdog 2 */
01051 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC4 analog watchdog 3 */
01052 #endif /* ADC4 */
01053 /**
01054   * @}
01055   */
01056
01057 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
01058   * @{
01059   */
01060 #define LL_TIM_TIM2_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
01061 #define LL_TIM_TIM2_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
01062 #define LL_TIM_TIM2_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
01063 #define LL_TIM_TIM2_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
01064 #define LL_TIM_TIM2_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
01065 #if defined(COMP5)
01066 #define LL_TIM_TIM2_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
01067 #endif /* COMP5 */
01068 #if defined(COMP6)
01069 #define LL_TIM_TIM2_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
01070 #endif /* COMP6 */
01071 #if defined(COMP7)
01072 #define LL_TIM_TIM2_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
01073 #endif /* COMP7 */
01074 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
01075 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
01076 #if defined(TIM5)
01077 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to TIM5 ETR */
01078 #endif /* TIM5 */
01079 #define LL_TIM_TIM2_ETRSOURCE_LSE          (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
01080 /**
01081   * @}
01082   */
01083
01084 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
01085   * @{
01086   */
01087 #define LL_TIM_TIM3_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
01088 #define LL_TIM_TIM3_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
01089 #define LL_TIM_TIM3_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
01090 #define LL_TIM_TIM3_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
01091 #define LL_TIM_TIM3_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
01092 #if defined(COMP5)
01093 #define LL_TIM_TIM3_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
01094 #endif /* COMP5 */
01095 #if defined(COMP6)
01096 #define LL_TIM_TIM3_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
01097 #endif /* COMP6 */
01098 #if defined(COMP7)
01099 #define LL_TIM_TIM3_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
01100 #endif /* COMP7 */
01101 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
01102 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
01103 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
01104 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ADC2 analog watchdog 2 */
01105 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
01106 /**
01107   * @}
01108   */
01109
01110 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
01111   * @{
01112   */
01113 #define LL_TIM_TIM4_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
01114 #define LL_TIM_TIM4_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
01115 #define LL_TIM_TIM4_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
01116 #define LL_TIM_TIM4_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
01117 #define LL_TIM_TIM4_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
01118 #if defined(COMP5)
01119 #define LL_TIM_TIM4_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
01120 #endif /* COMP5 */
01121 #if defined(COMP6)
01122 #define LL_TIM_TIM4_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
01123 #endif /* COMP6 */
01124 #if defined(COMP7)
01125 #define LL_TIM_TIM4_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
01126 #endif /* COMP7 */
01127 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
01128 #if defined(TIM5)
01129 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM5 ETR */
01130 #endif /* TIM5 */
01131 /**
01132   * @}
01133   */
01134
01135 #if defined(TIM5)
01136 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
01137   * @{
01138   */
01139 #define LL_TIM_TIM5_ETRSOURCE_GPIO         0x00000000U                                                 /*!< ETR input is connected to GPIO */
01140 #define LL_TIM_TIM5_ETRSOURCE_COMP1        TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
01141 #define LL_TIM_TIM5_ETRSOURCE_COMP2        TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
01142 #define LL_TIM_TIM5_ETRSOURCE_COMP3        (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP3_OUT */
01143 #define LL_TIM_TIM5_ETRSOURCE_COMP4        TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to COMP4_OUT */
01144 #if defined(COMP5)
01145 #define LL_TIM_TIM5_ETRSOURCE_COMP5        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP5_OUT */
01146 #endif /* COMP5 */
01147 #if defined(COMP6)
01148 #define LL_TIM_TIM5_ETRSOURCE_COMP6        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to COMP6_OUT */
01149 #endif /* COMP6 */
01150 #if defined(COMP7)
01151 #define LL_TIM_TIM5_ETRSOURCE_COMP7        (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
01152 #endif /* COMP7 */
01153 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR     TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
01154 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM3 ETR */
01155 /**
01156   * @}
01157   */
01158 #endif /* TIM5 */
01159
01160 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
01161   * @{
01162   */
01163 #define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                  /*!< ETR input is connected to GPIO */
01164 #define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
01165 #define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
01166 #define LL_TIM_TIM8_ETRSOURCE_COMP3       (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
01167 #define LL_TIM_TIM8_ETRSOURCE_COMP4       TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
01168 #if defined(COMP5)
01169 #define LL_TIM_TIM8_ETRSOURCE_COMP5       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
01170 #endif /* COMP5 */
01171 #if defined(COMP6)
01172 #define LL_TIM_TIM8_ETRSOURCE_COMP6       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
01173 #endif /* COMP6 */
01174 #if defined(COMP7)
01175 #define LL_TIM_TIM8_ETRSOURCE_COMP7       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
01176 #endif /* COMP7 */
01177 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   TIM1_AF1_ETRSEL_3                                            /*!< ADC2 analog watchdog 1 */
01178 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC2 analog watchdog 2 */
01179 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC2 analog watchdog 3 */
01180 #if defined(ADC3)
01181 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 1 */
01182 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC3 analog watchdog 2 */
01183 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC3 analog watchdog 3 */
01184 #endif /* ADC3 */
01185 /**
01186   * @}
01187   */
01188
01189 #if defined(TIM20)
01190 /** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
01191   * @{
01192   */
01193 #define LL_TIM_TIM20_ETRSOURCE_GPIO       0x00000000U                                                  /*!< ETR input is connected to GPIO */
01194 #define LL_TIM_TIM20_ETRSOURCE_COMP1      TIM1_AF1_ETRSEL_0                                            /*!< ETR input is connected to COMP1_OUT */
01195 #define LL_TIM_TIM20_ETRSOURCE_COMP2      TIM1_AF1_ETRSEL_1                                            /*!< ETR input is connected to COMP2_OUT */
01196 #define LL_TIM_TIM20_ETRSOURCE_COMP3      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP3_OUT */
01197 #define LL_TIM_TIM20_ETRSOURCE_COMP4      TIM1_AF1_ETRSEL_2                                            /*!< ETR input is connected to COMP4_OUT */
01198 #if defined(COMP5)
01199 #define LL_TIM_TIM20_ETRSOURCE_COMP5      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                      /*!< ETR input is connected to COMP5_OUT */
01200 #endif /* COMP5 */
01201 #if defined(COMP6)
01202 #define LL_TIM_TIM20_ETRSOURCE_COMP6      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                      /*!< ETR input is connected to COMP6_OUT */
01203 #endif /* COMP6 */
01204 #if defined(COMP7)
01205 #define LL_TIM_TIM20_ETRSOURCE_COMP7      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to COMP7_OUT */
01206 #endif /* COMP7 */
01207 #if defined(ADC3)
01208 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1  TIM1_AF1_ETRSEL_3                                            /*!< ADC3 analog watchdog 1 */
01209 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                      /*!< ADC3 analog watchdog 2 */
01210 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                      /*!< ADC3 analog watchdog 3 */
01211 #endif /* ADC3 */
01212 #if defined(ADC5)
01213 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)  /*!< ADC5 analog watchdog 1 */
01214 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                      /*!< ADC5 analog watchdog 2 */
01215 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3  (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)  /*!< ADC5 analog watchdog 3 */
01216 #endif /* ADC5 */
01217 /**
01218   * @}
01219   */
01220 #endif /* TIM20 */
01221
01222 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
01223   * @{
01224   */
01225 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
01226 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
01227 /**
01228   * @}
01229   */
01230
01231 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
01232   * @{
01233   */
01234 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
01235 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
01236 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
01237 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
01238 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
01239 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
01240 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
01241 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
01242 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
01243 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
01244 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
01245 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
01246 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
01247 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
01248 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
01249 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
01250 /**
01251   * @}
01252   */
01253
01254 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
01255   * @{
01256   */
01257 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
01258 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
01259 /**
01260   * @}
01261   */
01262
01263 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
01264   * @{
01265   */
01266 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
01267 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
01268 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
01269 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
01270 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
01271 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
01272 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
01273 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
01274 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
01275 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
01276 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
01277 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
01278 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
01279 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
01280 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
01281 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
01282 /**
01283   * @}
01284   */
01285
01286 /** @defgroup TIM_LL_EC_OSSI OSSI
01287   * @{
01288   */
01289 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01290 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
01291 /**
01292   * @}
01293   */
01294
01295 /** @defgroup TIM_LL_EC_OSSR OSSR
01296   * @{
01297   */
01298 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01299 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
01300 /**
01301   * @}
01302   */
01303
01304 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
01305   * @{
01306   */
01307 #define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
01308 #define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
01309 /**
01310   * @}
01311   */
01312
01313 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
01314   * @{
01315   */
01316 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
01317 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
01318 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
01319 #define LL_TIM_BKIN_SOURCE_BKCOMP3             TIM1_AF1_BKCMP3E    /*!< internal signal: COMP3 output */
01320 #define LL_TIM_BKIN_SOURCE_BKCOMP4             TIM1_AF1_BKCMP4E    /*!< internal signal: COMP4 output */
01321 #if defined(COMP5)
01322 #define LL_TIM_BKIN_SOURCE_BKCOMP5             TIM1_AF1_BKCMP5E    /*!< internal signal: COMP5 output */
01323 #endif /* COMP5 */
01324 #if defined(COMP6)
01325 #define LL_TIM_BKIN_SOURCE_BKCOMP6             TIM1_AF1_BKCMP6E    /*!< internal signal: COMP6 output */
01326 #endif /* COMP6 */
01327 #if defined(COMP7)
01328 #define LL_TIM_BKIN_SOURCE_BKCOMP7             TIM1_AF1_BKCMP7E    /*!< internal signal: COMP7 output */
01329 #endif /* COMP7 */
01330 /**
01331   * @}
01332   */
01333
01334 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
01335   * @{
01336   */
01337 #define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
01338 #define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
01339 /**
01340   * @}
01341   */
01342
01343 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
01344   * @{
01345   */
01346 #define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
01347 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
01348 /**
01349   * @}
01350   */
01351
01352 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
01353   * @{
01354   */
01355 #define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
01356 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
01357 /**
01358   * @}
01359   */
01360
01361 /** Legacy definitions for compatibility purpose
01362 @cond 0
01363   */
01364 #define LL_TIM_ReArmBRK(_PARAM_)
01365 #define LL_TIM_ReArmBRK2(_PARAM_)
01366 /**
01367 @endcond
01368   */
01369
01370 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01371   * @{
01372   */
01373 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01374 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01375 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01376 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01377 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01378 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01379 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01380 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01381 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01382 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01383 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01384 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01385 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01386 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01387 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01388 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01389 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01390 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01391 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01392 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01393 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01394 #define LL_TIM_DMABURST_BASEADDR_DTR2          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
01395 #define LL_TIM_DMABURST_BASEADDR_ECR           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_ECR register is the DMA base address for DMA burst */
01396 #define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
01397 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
01398 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
01399 #define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_OR register is the DMA base address for DMA burst */
01400 /**
01401   * @}
01402   */
01403
01404 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01405   * @{
01406   */
01407 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01408 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01409 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01410 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01411 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01412 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01413 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01414 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01415 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01416 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01417 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01418 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01419 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01420 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01421 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01422 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01423 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01424 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01425 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 19 registers starting from the DMA burst base address */
01426 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 20 registers starting from the DMA burst base address */
01427 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 21 registers starting from the DMA burst base address */
01428 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 22 registers starting from the DMA burst base address */
01429 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 23 registers starting from the DMA burst base address */
01430 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
01431 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)                                 /*!< Transfer is done to 25 registers starting from the DMA burst base address */
01432 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 26 registers starting from the DMA burst base address */
01433 /**
01434   * @}
01435   */
01436
01437 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
01438   * @{
01439   */
01440 #define LL_TIM_TIM1_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
01441 #define LL_TIM_TIM1_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
01442 #define LL_TIM_TIM1_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM1 input 1 is connected to COMP2_OUT */
01443 #define LL_TIM_TIM1_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM1 input 1 is connected to COMP3_OUT */
01444 #define LL_TIM_TIM1_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM1 input 1 is connected to COMP4_OUT */
01445 /**
01446   * @}
01447   */
01448
01449 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 Timer Input Ch1 Remap
01450   * @{
01451   */
01452 #define LL_TIM_TIM2_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
01453 #define LL_TIM_TIM2_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
01454 #define LL_TIM_TIM2_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM2 input 1 is connected to COMP2_OUT */
01455 #define LL_TIM_TIM2_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP3_OUT */
01456 #define LL_TIM_TIM2_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM2 input 1 is connected to COMP4_OUT */
01457 #if defined(COMP5)
01458 #define LL_TIM_TIM2_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM2 input 1 is connected to COMP5_OUT */
01459 #endif /* COMP5 */
01460 /**
01461   * @}
01462   */
01463
01464 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP  TIM2 Timer Input Ch2 Remap
01465   * @{
01466   */
01467 #define LL_TIM_TIM2_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
01468 #define LL_TIM_TIM2_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP1_OUT */
01469 #define LL_TIM_TIM2_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM2 input 2 is connected to COMP2_OUT */
01470 #define LL_TIM_TIM2_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP3_OUT */
01471 #define LL_TIM_TIM2_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM2 input 2 is connected to COMP4_OUT */
01472 #if defined(COMP6)
01473 #define LL_TIM_TIM2_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM2 input 2 is connected to COMP6_OUT */
01474 #endif /* COMP6 */
01475 /**
01476   * @}
01477   */
01478
01479 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP  TIM2 Timer Input Ch3 Remap
01480   * @{
01481   */
01482 #define LL_TIM_TIM2_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
01483 #define LL_TIM_TIM2_TI3_RMP_COMP4  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP4_OUT */
01484 /**
01485   * @}
01486   */
01487
01488 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
01489   * @{
01490   */
01491 #define LL_TIM_TIM2_TI4_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 4 is connected to GPIO */
01492 #define LL_TIM_TIM2_TI4_RMP_COMP1  TIM_TISEL_TI4SEL_0                                /*!< TIM2 input 4 is connected to COMP1_OUT */
01493 #define LL_TIM_TIM2_TI4_RMP_COMP2  TIM_TISEL_TI4SEL_1                                /*!< TIM2 input 4 is connected to COMP2_OUT */
01494 /**
01495   * @}
01496   */
01497
01498 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
01499   * @{
01500   */
01501 #define LL_TIM_TIM3_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
01502 #define LL_TIM_TIM3_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
01503 #define LL_TIM_TIM3_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM3 input 1 is connected to COMP2_OUT */
01504 #define LL_TIM_TIM3_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP3_OUT */
01505 #define LL_TIM_TIM3_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM3 input 1 is connected to COMP4_OUT */
01506 #if defined(COMP5)
01507 #define LL_TIM_TIM3_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM3 input 1 is connected to COMP5_OUT */
01508 #endif /* COMP5 */
01509 #if defined(COMP6)
01510 #define LL_TIM_TIM3_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM3 input 1 is connected to COMP6_OUT */
01511 #endif /* COMP6 */
01512 #if defined(COMP7)
01513 #define LL_TIM_TIM3_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM3 input 1 is connected to COMP7_OUT */
01514 #endif /* COMP7 */
01515 /**
01516   * @}
01517   */
01518
01519 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP  TIM3 Timer Input Ch2 Remap
01520   * @{
01521   */
01522 #define LL_TIM_TIM3_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
01523 #define LL_TIM_TIM3_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP1_OUT */
01524 #define LL_TIM_TIM3_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM3 input 2 is connected to COMP2_OUT */
01525 #define LL_TIM_TIM3_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP3_OUT */
01526 #define LL_TIM_TIM3_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM3 input 2 is connected to COMP4_OUT */
01527 #if defined(COMP5)
01528 #define LL_TIM_TIM3_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM3 input 2 is connected to COMP5_OUT */
01529 #endif /* COMP5 */
01530 #if defined(COMP6)
01531 #define LL_TIM_TIM3_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM3 input 2 is connected to COMP6_OUT */
01532 #endif /* COMP6 */
01533 #if defined(COMP7)
01534 #define LL_TIM_TIM3_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM3 input 2 is connected to COMP7_OUT */
01535 #endif /* COMP7 */
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP  TIM3 Timer Input Ch3 Remap
01541   * @{
01542   */
01543 #define LL_TIM_TIM3_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
01544 #define LL_TIM_TIM3_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
01545 /**
01546   * @}
01547   */
01548
01549 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP  TIM4 Timer Input Ch1 Remap
01550   * @{
01551   */
01552 #define LL_TIM_TIM4_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
01553 #define LL_TIM_TIM4_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
01554 #define LL_TIM_TIM4_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM4 input 1 is connected to COMP2_OUT */
01555 #define LL_TIM_TIM4_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP3_OUT */
01556 #define LL_TIM_TIM4_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM4 input 1 is connected to COMP4_OUT */
01557 #if defined(COMP5)
01558 #define LL_TIM_TIM4_TI1_RMP_COMP5  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM4 input 1 is connected to COMP5_OUT */
01559 #endif /* COMP5 */
01560 #if defined(COMP6)
01561 #define LL_TIM_TIM4_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM4 input 1 is connected to COMP6_OUT */
01562 #endif /* COMP6 */
01563 #if defined(COMP7)
01564 #define LL_TIM_TIM4_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM4 input 1 is connected to COMP7_OUT */
01565 #endif /* COMP7 */
01566 /**
01567   * @}
01568   */
01569
01570 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP  TIM4 Timer Input Ch2 Remap
01571   * @{
01572   */
01573 #define LL_TIM_TIM4_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
01574 #define LL_TIM_TIM4_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP1_OUT */
01575 #define LL_TIM_TIM4_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM4 input 2 is connected to COMP2_OUT */
01576 #define LL_TIM_TIM4_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP3_OUT */
01577 #define LL_TIM_TIM4_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM4 input 2 is connected to COMP4_OUT */
01578 #if defined(COMP5)
01579 #define LL_TIM_TIM4_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM4 input 2 is connected to COMP5_OUT */
01580 #endif /* COMP5 */
01581 #if defined(COMP6)
01582 #define LL_TIM_TIM4_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM4 input 2 is connected to COMP6_OUT */
01583 #endif /* COMP6 */
01584 #if defined(COMP7)
01585 #define LL_TIM_TIM4_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM4 input 2 is connected to COMP7_OUT */
01586 #endif /* COMP7 */
01587 /**
01588   * @}
01589   */
01590
01591 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP  TIM4 Timer Input Ch3 Remap
01592   * @{
01593   */
01594 #define LL_TIM_TIM4_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
01595 #if defined(COMP5)
01596 #define LL_TIM_TIM4_TI3_RMP_COMP5  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP5_OUT */
01597 #endif /* COMP5 */
01598 /**
01599   * @}
01600   */
01601
01602 /** @defgroup TIM_LL_EC_TIM4_TI4_RMP  TIM4 Timer Input Ch4 Remap
01603   * @{
01604   */
01605 #define LL_TIM_TIM4_TI4_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 4 is connected to GPIO */
01606 #if defined(COMP6)
01607 #define LL_TIM_TIM4_TI4_RMP_COMP6  TIM_TISEL_TI4SEL_0                                /*!< TIM4 input 4 is connected to COMP6_OUT */
01608 #endif /* COMP6 */
01609 /**
01610   * @}
01611   */
01612
01613 #if defined(TIM5)
01614 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
01615   * @{
01616   */
01617 #define LL_TIM_TIM5_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM5 input 1 is connected to GPIO */
01618 #define LL_TIM_TIM5_TI1_RMP_LSI    TIM_TISEL_TI1SEL_0                                /*!< TIM5 input 1 is connected to LSI */
01619 #define LL_TIM_TIM5_TI1_RMP_LSE    TIM_TISEL_TI1SEL_1                                /*!< TIM5 input 1 is connected to LSE */
01620 #define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to RTC_WAKEUP */
01621 #define LL_TIM_TIM5_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_2                                /*!< TIM5 input 1 is connected to COMP1_OUT */
01622 #define LL_TIM_TIM5_TI1_RMP_COMP2  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP2_OUT */
01623 #define LL_TIM_TIM5_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP3_OUT */
01624 #define LL_TIM_TIM5_TI1_RMP_COMP4  (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)   /*!< TIM5 input 1 is connected to COMP4_OUT */
01625 #if defined(COMP5)
01626 #define LL_TIM_TIM5_TI1_RMP_COMP5  TIM_TISEL_TI1SEL_3                                /*!< TIM5 input 1 is connected to COMP5_OUT */
01627 #endif /* COMP5 */
01628 #if defined(COMP6)
01629 #define LL_TIM_TIM5_TI1_RMP_COMP6  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)         /*!< TIM5 input 1 is connected to COMP6_OUT */
01630 #endif /* COMP6 */
01631 #if defined(COMP7)
01632 #define LL_TIM_TIM5_TI1_RMP_COMP7  (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1)         /*!< TIM5 input 1 is connected to COMP7_OUT */
01633 #endif /* COMP7 */
01634 /**
01635   * @}
01636   */
01637
01638 /** @defgroup TIM_LL_EC_TIM5_TI2_RMP  TIM5 Timer Input Ch2 Remap
01639   * @{
01640   */
01641 #define LL_TIM_TIM5_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM5 input 2 is connected to GPIO */
01642 #define LL_TIM_TIM5_TI2_RMP_COMP1  TIM_TISEL_TI2SEL_0                                /*!< TIM5 input 2 is connected to COMP1_OUT */
01643 #define LL_TIM_TIM5_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_1                                /*!< TIM5 input 2 is connected to COMP2_OUT */
01644 #define LL_TIM_TIM5_TI2_RMP_COMP3  (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP3_OUT */
01645 #define LL_TIM_TIM5_TI2_RMP_COMP4  TIM_TISEL_TI2SEL_2                                /*!< TIM5 input 2 is connected to COMP4_OUT */
01646 #if defined(COMP5)
01647 #define LL_TIM_TIM5_TI2_RMP_COMP5  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)         /*!< TIM5 input 2 is connected to COMP5_OUT */
01648 #endif /* COMP5 */
01649 #if defined(COMP6)
01650 #define LL_TIM_TIM5_TI2_RMP_COMP6  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1)         /*!< TIM5 input 2 is connected to COMP6_OUT */
01651 #endif /* COMP6 */
01652 #if defined(COMP7)
01653 #define LL_TIM_TIM5_TI2_RMP_COMP7  (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)   /*!< TIM5 input 2 is connected to COMP7_OUT */
01654 #endif /* COMP7 */
01655 /**
01656   * @}
01657   */
01658 #endif /* TIM5 */
01659
01660 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
01661   * @{
01662   */
01663 #define LL_TIM_TIM8_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM8 input 1 is connected to GPIO */
01664 #define LL_TIM_TIM8_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM8 input 1 is connected to COMP1_OUT */
01665 #define LL_TIM_TIM8_TI1_RMP_COMP2  TIM_TISEL_TI1SEL_1                                /*!< TIM8 input 1 is connected to COMP2_OUT */
01666 #define LL_TIM_TIM8_TI1_RMP_COMP3  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM8 input 1 is connected to COMP3_OUT */
01667 #define LL_TIM_TIM8_TI1_RMP_COMP4  TIM_TISEL_TI1SEL_2                                /*!< TIM8 input 1 is connected to COMP4_OUT */
01668 /**
01669   * @}
01670   */
01671
01672 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
01673   * @{
01674   */
01675 #define LL_TIM_TIM15_TI1_RMP_GPIO  0x00000000U                                       /*!< TIM15 input 1 is connected to GPIO */
01676 #define LL_TIM_TIM15_TI1_RMP_LSE   TIM_TISEL_TI1SEL_0                                /*!< TIM15 input 1 is connected to LSE */
01677 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1                                /*!< TIM15 input 1 is connected to COMP1_OUT */
01678 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP2_OUT */
01679 #if defined(COMP5)
01680 #define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2                                /*!< TIM15 input 1 is connected to COMP5_OUT */
01681 #endif /* COMP5 */
01682 #if defined(COMP7)
01683 #define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)         /*!< TIM15 input 1 is connected to COMP7_OUT */
01684 #endif /* COMP7 */
01685 /**
01686   * @}
01687   */
01688
01689 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
01690   * @{
01691   */
01692 #define LL_TIM_TIM15_TI2_RMP_GPIO  0x00000000U                                       /*!< TIM15 input 2 is connected to GPIO */
01693 #define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0                                /*!< TIM15 input 2 is connected to COMP2_OUT */
01694 #define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1                                /*!< TIM15 input 2 is connected to COMP3_OUT */
01695 #if defined(COMP6)
01696 #define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)         /*!< TIM15 input 2 is connected to COMP6_OUT */
01697 #endif /* COMP6 */
01698 #if defined(COMP7)
01699 #define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2                                /*!< TIM15 input 2 is connected to COMP7_OUT */
01700 #endif /* COMP7 */
01701 /**
01702   * @}
01703   */
01704
01705 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
01706   * @{
01707   */
01708 #define LL_TIM_TIM16_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
01709 #if defined(COMP6)
01710 #define LL_TIM_TIM16_TI1_RMP_COMP6   TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to COMP6_OUT */
01711 #endif /* COMP6 */
01712 #define LL_TIM_TIM16_TI1_RMP_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to MCO */
01713 #define LL_TIM_TIM16_TI1_RMP_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to HSE/32 */
01714 #define LL_TIM_TIM16_TI1_RMP_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to RTC_WAKEUP */
01715 #define LL_TIM_TIM16_TI1_RMP_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM16 input 1 is connected to LSE */
01716 #define LL_TIM_TIM16_TI1_RMP_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to LSI */
01717 /**
01718   * @}
01719   */
01720
01721 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
01722   * @{
01723   */
01724 #define LL_TIM_TIM17_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
01725 #if defined(COMP5)
01726 #define LL_TIM_TIM17_TI1_RMP_COMP5   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to COMP5_OUT */
01727 #endif /* COMP5 */
01728 #define LL_TIM_TIM17_TI1_RMP_MCO     TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to MCO */
01729 #define LL_TIM_TIM17_TI1_RMP_HSE_32  (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to HSE/32 */
01730 #define LL_TIM_TIM17_TI1_RMP_RTC_WK  TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to RTC_WAKEUP */
01731 #define LL_TIM_TIM17_TI1_RMP_LSE     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)       /*!< TIM17 input 1 is connected to LSE */
01732 #define LL_TIM_TIM17_TI1_RMP_LSI     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)       /*!< TIM17 input 1 is connected to LSI */
01733 /**
01734   * @}
01735   */
01736
01737 #if defined(TIM20)
01738 /** @defgroup TIM_LL_EC_TIM20_TI1_RMP  TIM20 Timer Input Ch1 Remap
01739   * @{
01740   */
01741 #define LL_TIM_TIM20_TI1_RMP_GPIO  0x00000000U                                      /*!< TIM20 input 1 is connected to GPIO */
01742 #define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0                               /*!< TIM20 input 1 is connected to COMP1_OUT */
01743 #define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1                               /*!< TIM20 input 1 is connected to COMP2_OUT */
01744 #define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)        /*!< TIM20 input 1 is connected to COMP3_OUT */
01745 #define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2                               /*!< TIM20 input 1 is connected to COMP4_OUT */
01746 /**
01747   * @}
01748   */
01749 #endif /* TIM20 */
01750
01751 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
01752   * @{
01753   */
01754 #define LL_TIM_OCREF_CLR_INT_ETR         OCREF_CLEAR_SELECT_Msk                   /*!< OCREF_CLR_INT is connected to ETRF */
01755 #define LL_TIM_OCREF_CLR_INT_COMP1       0x00000000U                              /*!< OCREF clear input is connected to COMP1_OUT */
01756 #define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_AF2_OCRSEL_0                        /*!< OCREF clear input is connected to COMP2_OUT */
01757 #define LL_TIM_OCREF_CLR_INT_COMP3       TIM1_AF2_OCRSEL_1                        /*!< OCREF clear input is connected to COMP3_OUT */
01758 #define LL_TIM_OCREF_CLR_INT_COMP4       (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0)  /*!< OCREF clear input is connected to COMP4_OUT */
01759 #if defined(COMP5)
01760 #define LL_TIM_OCREF_CLR_INT_COMP5       TIM1_AF2_OCRSEL_2                        /*!< OCREF clear input is connected to COMP5_OUT */
01761 #endif /* COMP5 */
01762 #if defined(COMP6)
01763 #define LL_TIM_OCREF_CLR_INT_COMP6       (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0)  /*!< OCREF clear input is connected to COMP6_OUT */
01764 #endif /* COMP6 */
01765 #if defined(COMP7)
01766 #define LL_TIM_OCREF_CLR_INT_COMP7       (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1)  /*!< OCREF clear input is connected to COMP7_OUT */
01767 #endif /* COMP7 */
01768 /**
01769   * @}
01770   */
01771
01772 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
01773   * @{
01774   */
01775 #define LL_TIM_INDEX_UP_DOWN     0x00000000U         /*!< Index resets the counter whatever the direction */
01776 #define LL_TIM_INDEX_UP          TIM_ECR_IDIR_0      /*!< Index resets the counter when up-counting only */
01777 #define LL_TIM_INDEX_DOWN        TIM_ECR_IDIR_1      /*!< Index resets the counter when down-counting only */
01778 /**
01779   * @}
01780   */
01781
01782 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
01783   * @{
01784   */
01785 #define LL_TIM_INDEX_POSITION_DOWN_DOWN    0x00000000U                           /*!< Index resets the counter when AB = 00 */
01786 #define LL_TIM_INDEX_POSITION_DOWN_UP      TIM_ECR_IPOS_0                        /*!< Index resets the counter when AB = 01 */
01787 #define LL_TIM_INDEX_POSITION_UP_DOWN      TIM_ECR_IPOS_1                        /*!< Index resets the counter when AB = 10 */
01788 #define LL_TIM_INDEX_POSITION_UP_UP        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Index resets the counter when AB = 11 */
01789 #define LL_TIM_INDEX_POSITION_DOWN         0x00000000U                           /*!< Index resets the counter when clock is 0 */
01790 #define LL_TIM_INDEX_POSITION_UP           TIM_ECR_IPOS_0                        /*!< Index resets the counter when clock is 1 */
01791 /**
01792   * @}
01793   */
01794
01795 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
01796   * @{
01797   */
01798 #define LL_TIM_INDEX_ALL           0x00000000U                           /*!< Index is always active */
01799 #define LL_TIM_INDEX_FIRST_ONLY    TIM_ECR_FIDX                          /*!< The first Index only resets the counter */
01800 /**
01801   * @}
01802   */
01803 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
01804   * @{
01805   */
01806 #define LL_TIM_PWPRSC_X1     0x00000000U                                              /*!< Pulse on compare pulse width prescaler 1 */
01807 #define LL_TIM_PWPRSC_X2     TIM_ECR_PWPRSC_0                                         /*!< Pulse on compare pulse width prescaler 2 */
01808 #define LL_TIM_PWPRSC_X4     TIM_ECR_PWPRSC_1                                         /*!< Pulse on compare pulse width prescaler 4 */
01809 #define LL_TIM_PWPRSC_X8     (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 8 */
01810 #define LL_TIM_PWPRSC_X16    TIM_ECR_PWPRSC_2                                         /*!< Pulse on compare pulse width prescaler 16 */
01811 #define LL_TIM_PWPRSC_X32    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 32 */
01812 #define LL_TIM_PWPRSC_X64    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)                    /*!< Pulse on compare pulse width prescaler 64 */
01813 #define LL_TIM_PWPRSC_X128   (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
01814 /**
01815   * @}
01816   */
01817
01818 /** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
01819   * @{
01820   */
01821 #define LL_TIM_HSE_32_NOT_REQUEST     0x00000000U            /*!< Clock HSE/32 not requested */
01822 #define LL_TIM_HSE_32_REQUEST         TIM_OR_HSE32EN         /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
01823 /**
01824   * @}
01825   */
01826
01827 /** Legacy definitions for compatibility purpose
01828 @cond 0
01829   */
01830 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01831 /**
01832 @endcond
01833   */
01834
01835 /**
01836   * @}
01837   */
01838
01839 /* Exported macro ------------------------------------------------------------*/
01840 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01841   * @{
01842   */
01843
01844 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01845   * @{
01846   */
01847 /**
01848   * @brief  Write a value in TIM register.
01849   * @param  __INSTANCE__ TIM Instance
01850   * @param  __REG__ Register to be written
01851   * @param  __VALUE__ Value to be written in the register
01852   * @retval None
01853   */
01854 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
01855
01856 /**
01857   * @brief  Read a value in TIM register.
01858   * @param  __INSTANCE__ TIM Instance
01859   * @param  __REG__ Register to be read
01860   * @retval Register value
01861   */
01862 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
01863 /**
01864   * @}
01865   */
01866
01867 /**
01868   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01869   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01870   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01871   *        to TIMx_CNT register bit 31)
01872   * @param  __CNT__ Counter value
01873   * @retval UIF status bit
01874   */
01875 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01876   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01877
01878 /**
01879   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01880   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01881   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01882   * @param  __CKD__ This parameter can be one of the following values:
01883   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01884   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01885   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01886   * @param  __DT__ deadtime duration (in ns)
01887   * @retval DTG[0:7]
01888   */
01889 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01890   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
01891     (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
01892     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
01893     (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
01894                                                  (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
01895     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
01896     (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
01897                                                  (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
01898     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
01899     (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
01900                                                  (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
01901     0U)
01902
01903 /**
01904   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01905   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01906   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01907   * @param  __CNTCLK__ counter clock frequency (in Hz)
01908   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01909   */
01910 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01911   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
01912
01913 /**
01914   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01915   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01916   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01917   * @param  __PSC__ prescaler
01918   * @param  __FREQ__ output signal frequency (in Hz)
01919   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01920   */
01921 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01922   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
01923
01924 /**
01925   * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
01926   *         output signal frequency.
01927   * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01928   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01929   * @param  __PSC__ prescaler
01930   * @param  __FREQ__ output signal frequency (in Hz)
01931   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01932   */
01933 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
01934   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
01935    (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
01936
01937 /**
01938   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
01939   *         active/inactive delay.
01940   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01941   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01942   * @param  __PSC__ prescaler
01943   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01944   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01945   */
01946 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01947   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01948               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01949
01950 /**
01951   * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
01952   *         output compare active/inactive delay.
01953   * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
01954   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01955   * @param  __PSC__ prescaler
01956   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01957   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01958   */
01959 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
01960   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
01961               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01962
01963 /**
01964   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
01965   *         (when the timer operates in one pulse mode).
01966   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01967   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01968   * @param  __PSC__ prescaler
01969   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01970   * @param  __PULSE__ pulse duration (in us)
01971   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01972   */
01973 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01974   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01975               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01976
01977 /**
01978   * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
01979   *         pulse duration (when the timer operates in one pulse mode).
01980   * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01981   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01982   * @param  __PSC__ prescaler
01983   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01984   * @param  __PULSE__ pulse duration (in us)
01985   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01986   */
01987 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01988   ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
01989               + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
01990
01991 /**
01992   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01993   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01994   * @param  __ICPSC__ This parameter can be one of the following values:
01995   *         @arg @ref LL_TIM_ICPSC_DIV1
01996   *         @arg @ref LL_TIM_ICPSC_DIV2
01997   *         @arg @ref LL_TIM_ICPSC_DIV4
01998   *         @arg @ref LL_TIM_ICPSC_DIV8
01999   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
02000   */
02001 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
02002   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
02003
02004
02005 /**
02006   * @}
02007   */
02008
02009 /* Exported functions --------------------------------------------------------*/
02010 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
02011   * @{
02012   */
02013
02014 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
02015   * @{
02016   */
02017 /**
02018   * @brief  Enable timer counter.
02019   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
02020   * @param  TIMx Timer instance
02021   * @retval None
02022   */
02023 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
02024 {
02025   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
02026 }
02027
02028 /**
02029   * @brief  Disable timer counter.
02030   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
02031   * @param  TIMx Timer instance
02032   * @retval None
02033   */
02034 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
02035 {
02036   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
02037 }
02038
02039 /**
02040   * @brief  Indicates whether the timer counter is enabled.
02041   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
02042   * @param  TIMx Timer instance
02043   * @retval State of bit (1 or 0).
02044   */
02045 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
02046 {
02047   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
02048 }
02049
02050 /**
02051   * @brief  Enable update event generation.
02052   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
02053   * @param  TIMx Timer instance
02054   * @retval None
02055   */
02056 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
02057 {
02058   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
02059 }
02060
02061 /**
02062   * @brief  Disable update event generation.
02063   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
02064   * @param  TIMx Timer instance
02065   * @retval None
02066   */
02067 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
02068 {
02069   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
02070 }
02071
02072 /**
02073   * @brief  Indicates whether update event generation is enabled.
02074   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
02075   * @param  TIMx Timer instance
02076   * @retval Inverted state of bit (0 or 1).
02077   */
02078 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
02079 {
02080   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
02081 }
02082
02083 /**
02084   * @brief  Set update event source
02085   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
02086   *       generate an update interrupt or DMA request if enabled:
02087   *        - Counter overflow/underflow
02088   *        - Setting the UG bit
02089   *        - Update generation through the slave mode controller
02090   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
02091   *       overflow/underflow generates an update interrupt or DMA request if enabled.
02092   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
02093   * @param  TIMx Timer instance
02094   * @param  UpdateSource This parameter can be one of the following values:
02095   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
02096   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
02097   * @retval None
02098   */
02099 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
02100 {
02101   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
02102 }
02103
02104 /**
02105   * @brief  Get actual event update source
02106   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
02107   * @param  TIMx Timer instance
02108   * @retval Returned value can be one of the following values:
02109   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
02110   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
02111   */
02112 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
02113 {
02114   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
02115 }
02116
02117 /**
02118   * @brief  Set one pulse mode (one shot v.s. repetitive).
02119   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
02120   * @param  TIMx Timer instance
02121   * @param  OnePulseMode This parameter can be one of the following values:
02122   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
02123   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
02124   * @retval None
02125   */
02126 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
02127 {
02128   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
02129 }
02130
02131 /**
02132   * @brief  Get actual one pulse mode.
02133   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
02134   * @param  TIMx Timer instance
02135   * @retval Returned value can be one of the following values:
02136   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
02137   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
02138   */
02139 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
02140 {
02141   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
02142 }
02143
02144 /**
02145   * @brief  Set the timer counter counting mode.
02146   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
02147   *       check whether or not the counter mode selection feature is supported
02148   *       by a timer instance.
02149   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02150   *       requires a timer reset to avoid unexpected direction
02151   *       due to DIR bit readonly in center aligned mode.
02152   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
02153   *         CR1          CMS           LL_TIM_SetCounterMode
02154   * @param  TIMx Timer instance
02155   * @param  CounterMode This parameter can be one of the following values:
02156   *         @arg @ref LL_TIM_COUNTERMODE_UP
02157   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
02158   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
02159   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
02160   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
02161   * @retval None
02162   */
02163 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
02164 {
02165   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
02166 }
02167
02168 /**
02169   * @brief  Get actual counter mode.
02170   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
02171   *       check whether or not the counter mode selection feature is supported
02172   *       by a timer instance.
02173   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
02174   *         CR1          CMS           LL_TIM_GetCounterMode
02175   * @param  TIMx Timer instance
02176   * @retval Returned value can be one of the following values:
02177   *         @arg @ref LL_TIM_COUNTERMODE_UP
02178   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
02179   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
02180   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
02181   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
02182   */
02183 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
02184 {
02185   uint32_t counter_mode;
02186
02187   counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
02188
02189   if (counter_mode == 0U)
02190   {
02191     counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
02192   }
02193
02194   return counter_mode;
02195 }
02196
02197 /**
02198   * @brief  Enable auto-reload (ARR) preload.
02199   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
02200   * @param  TIMx Timer instance
02201   * @retval None
02202   */
02203 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
02204 {
02205   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
02206 }
02207
02208 /**
02209   * @brief  Disable auto-reload (ARR) preload.
02210   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
02211   * @param  TIMx Timer instance
02212   * @retval None
02213   */
02214 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
02215 {
02216   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
02217 }
02218
02219 /**
02220   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
02221   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
02222   * @param  TIMx Timer instance
02223   * @retval State of bit (1 or 0).
02224   */
02225 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
02226 {
02227   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
02228 }
02229
02230 /**
02231   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
02232   *         (when supported) and the digital filters.
02233   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
02234   *       whether or not the clock division feature is supported by the timer
02235   *       instance.
02236   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
02237   * @param  TIMx Timer instance
02238   * @param  ClockDivision This parameter can be one of the following values:
02239   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
02240   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
02241   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
02242   * @retval None
02243   */
02244 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
02245 {
02246   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
02247 }
02248
02249 /**
02250   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
02251   *         generators (when supported) and the digital filters.
02252   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
02253   *       whether or not the clock division feature is supported by the timer
02254   *       instance.
02255   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
02256   * @param  TIMx Timer instance
02257   * @retval Returned value can be one of the following values:
02258   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
02259   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
02260   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
02261   */
02262 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
02263 {
02264   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
02265 }
02266
02267 /**
02268   * @brief  Set the counter value.
02269   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02270   *       whether or not a timer instance supports a 32 bits counter.
02271   * @note If dithering is activated, pay attention to the Counter value interpretation
02272   * @rmtoll CNT          CNT           LL_TIM_SetCounter
02273   * @param  TIMx Timer instance
02274   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
02275   * @retval None
02276   */
02277 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
02278 {
02279   WRITE_REG(TIMx->CNT, Counter);
02280 }
02281
02282 /**
02283   * @brief  Get the counter value.
02284   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02285   *       whether or not a timer instance supports a 32 bits counter.
02286   * @note If dithering is activated, pay attention to the Counter value interpretation
02287   * @rmtoll CNT          CNT           LL_TIM_GetCounter
02288   * @param  TIMx Timer instance
02289   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
02290   */
02291 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
02292 {
02293   return (uint32_t)(READ_REG(TIMx->CNT));
02294 }
02295
02296 /**
02297   * @brief  Get the current direction of the counter
02298   * @rmtoll CR1          DIR           LL_TIM_GetDirection
02299   * @param  TIMx Timer instance
02300   * @retval Returned value can be one of the following values:
02301   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
02302   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
02303   */
02304 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
02305 {
02306   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
02307 }
02308
02309 /**
02310   * @brief  Set the prescaler value.
02311   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
02312   * @note The prescaler can be changed on the fly as this control register is buffered. The new
02313   *       prescaler ratio is taken into account at the next update event.
02314   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
02315   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
02316   * @param  TIMx Timer instance
02317   * @param  Prescaler between Min_Data=0 and Max_Data=65535
02318   * @retval None
02319   */
02320 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
02321 {
02322   WRITE_REG(TIMx->PSC, Prescaler);
02323 }
02324
02325 /**
02326   * @brief  Get the prescaler value.
02327   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
02328   * @param  TIMx Timer instance
02329   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
02330   */
02331 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
02332 {
02333   return (uint32_t)(READ_REG(TIMx->PSC));
02334 }
02335
02336 /**
02337   * @brief  Set the auto-reload value.
02338   * @note The counter is blocked while the auto-reload value is null.
02339   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02340   *       whether or not a timer instance supports a 32 bits counter.
02341   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
02342   *       In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
02343   *       parameter.
02344   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
02345   * @param  TIMx Timer instance
02346   * @param  AutoReload between Min_Data=0 and Max_Data=65535
02347   * @retval None
02348   */
02349 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
02350 {
02351   WRITE_REG(TIMx->ARR, AutoReload);
02352 }
02353
02354 /**
02355   * @brief  Get the auto-reload value.
02356   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
02357   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02358   *       whether or not a timer instance supports a 32 bits counter.
02359   * @note If dithering is activated, pay attention to the returned value interpretation
02360   * @param  TIMx Timer instance
02361   * @retval Auto-reload value
02362   */
02363 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
02364 {
02365   return (uint32_t)(READ_REG(TIMx->ARR));
02366 }
02367
02368 /**
02369   * @brief  Set the repetition counter value.
02370   * @note For advanced timer instances RepetitionCounter can be up to 65535.
02371   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
02372   *       whether or not a timer instance supports a repetition counter.
02373   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
02374   * @param  TIMx Timer instance
02375   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
02376   * @retval None
02377   */
02378 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
02379 {
02380   WRITE_REG(TIMx->RCR, RepetitionCounter);
02381 }
02382
02383 /**
02384   * @brief  Get the repetition counter value.
02385   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
02386   *       whether or not a timer instance supports a repetition counter.
02387   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
02388   * @param  TIMx Timer instance
02389   * @retval Repetition counter value
02390   */
02391 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
02392 {
02393   return (uint32_t)(READ_REG(TIMx->RCR));
02394 }
02395
02396 /**
02397   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
02398   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
02399   *       in an atomic way.
02400   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
02401   * @param  TIMx Timer instance
02402   * @retval None
02403   */
02404 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
02405 {
02406   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
02407 }
02408
02409 /**
02410   * @brief  Disable update interrupt flag (UIF) remapping.
02411   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
02412   * @param  TIMx Timer instance
02413   * @retval None
02414   */
02415 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
02416 {
02417   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
02418 }
02419
02420 /**
02421   * @brief  Indicate whether update interrupt flag (UIF) copy is set.
02422   * @param  Counter Counter value
02423   * @retval State of bit (1 or 0).
02424   */
02425 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
02426 {
02427   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
02428 }
02429
02430 /**
02431   * @brief  Enable dithering.
02432   * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
02433   *       a timer instance provides dithering.
02434   * @rmtoll CR1          DITHEN          LL_TIM_EnableDithering
02435   * @param  TIMx Timer instance
02436   * @retval None
02437   */
02438 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
02439 {
02440   SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
02441 }
02442
02443 /**
02444   * @brief  Disable dithering.
02445   * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
02446   *       a timer instance provides dithering.
02447   * @rmtoll CR1          DITHEN          LL_TIM_DisableDithering
02448   * @param  TIMx Timer instance
02449   * @retval None
02450   */
02451 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
02452 {
02453   CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
02454 }
02455
02456 /**
02457   * @brief  Indicates whether dithering is activated.
02458   * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
02459   *       a timer instance provides dithering.
02460   * @rmtoll CR1          DITHEN          LL_TIM_IsEnabledDithering
02461   * @param  TIMx Timer instance
02462   * @retval State of bit (1 or 0).
02463   */
02464 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
02465 {
02466   return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
02467 }
02468
02469 /**
02470   * @}
02471   */
02472
02473 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
02474   * @{
02475   */
02476 /**
02477   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
02478   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
02479   *       they are updated only when a commutation event (COM) occurs.
02480   * @note Only on channels that have a complementary output.
02481   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
02482   *       whether or not a timer instance is able to generate a commutation event.
02483   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
02484   * @param  TIMx Timer instance
02485   * @retval None
02486   */
02487 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
02488 {
02489   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
02490 }
02491
02492 /**
02493   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
02494   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
02495   *       whether or not a timer instance is able to generate a commutation event.
02496   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
02497   * @param  TIMx Timer instance
02498   * @retval None
02499   */
02500 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
02501 {
02502   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
02503 }
02504
02505 /**
02506   * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
02507   * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
02508   * @param  TIMx Timer instance
02509   * @retval State of bit (1 or 0).
02510   */
02511 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
02512 {
02513   return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
02514 }
02515
02516 /**
02517   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
02518   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
02519   *       whether or not a timer instance is able to generate a commutation event.
02520   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
02521   * @param  TIMx Timer instance
02522   * @param  CCUpdateSource This parameter can be one of the following values:
02523   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
02524   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
02525   * @retval None
02526   */
02527 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
02528 {
02529   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
02530 }
02531
02532 /**
02533   * @brief  Set the trigger of the capture/compare DMA request.
02534   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
02535   * @param  TIMx Timer instance
02536   * @param  DMAReqTrigger This parameter can be one of the following values:
02537   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
02538   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
02539   * @retval None
02540   */
02541 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
02542 {
02543   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
02544 }
02545
02546 /**
02547   * @brief  Get actual trigger of the capture/compare DMA request.
02548   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
02549   * @param  TIMx Timer instance
02550   * @retval Returned value can be one of the following values:
02551   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
02552   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
02553   */
02554 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
02555 {
02556   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
02557 }
02558
02559 /**
02560   * @brief  Set the lock level to freeze the
02561   *         configuration of several capture/compare parameters.
02562   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02563   *       the lock mechanism is supported by a timer instance.
02564   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
02565   * @param  TIMx Timer instance
02566   * @param  LockLevel This parameter can be one of the following values:
02567   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
02568   *         @arg @ref LL_TIM_LOCKLEVEL_1
02569   *         @arg @ref LL_TIM_LOCKLEVEL_2
02570   *         @arg @ref LL_TIM_LOCKLEVEL_3
02571   * @retval None
02572   */
02573 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
02574 {
02575   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
02576 }
02577
02578 /**
02579   * @brief  Enable capture/compare channels.
02580   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
02581   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
02582   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
02583   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
02584   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
02585   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
02586   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
02587   *         CCER         CC4NE         LL_TIM_CC_EnableChannel\n
02588   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
02589   *         CCER         CC6E          LL_TIM_CC_EnableChannel
02590   * @param  TIMx Timer instance
02591   * @param  Channels This parameter can be a combination of the following values:
02592   *         @arg @ref LL_TIM_CHANNEL_CH1
02593   *         @arg @ref LL_TIM_CHANNEL_CH1N
02594   *         @arg @ref LL_TIM_CHANNEL_CH2
02595   *         @arg @ref LL_TIM_CHANNEL_CH2N
02596   *         @arg @ref LL_TIM_CHANNEL_CH3
02597   *         @arg @ref LL_TIM_CHANNEL_CH3N
02598   *         @arg @ref LL_TIM_CHANNEL_CH4
02599   *         @arg @ref LL_TIM_CHANNEL_CH4N
02600   *         @arg @ref LL_TIM_CHANNEL_CH5
02601   *         @arg @ref LL_TIM_CHANNEL_CH6
02602   * @retval None
02603   */
02604 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
02605 {
02606   SET_BIT(TIMx->CCER, Channels);
02607 }
02608
02609 /**
02610   * @brief  Disable capture/compare channels.
02611   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
02612   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
02613   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
02614   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
02615   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
02616   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
02617   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
02618   *         CCER         CC4NE         LL_TIM_CC_DisableChannel\n
02619   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
02620   *         CCER         CC6E          LL_TIM_CC_DisableChannel
02621   * @param  TIMx Timer instance
02622   * @param  Channels This parameter can be a combination of the following values:
02623   *         @arg @ref LL_TIM_CHANNEL_CH1
02624   *         @arg @ref LL_TIM_CHANNEL_CH1N
02625   *         @arg @ref LL_TIM_CHANNEL_CH2
02626   *         @arg @ref LL_TIM_CHANNEL_CH2N
02627   *         @arg @ref LL_TIM_CHANNEL_CH3
02628   *         @arg @ref LL_TIM_CHANNEL_CH3N
02629   *         @arg @ref LL_TIM_CHANNEL_CH4
02630   *         @arg @ref LL_TIM_CHANNEL_CH4N
02631   *         @arg @ref LL_TIM_CHANNEL_CH5
02632   *         @arg @ref LL_TIM_CHANNEL_CH6
02633   * @retval None
02634   */
02635 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
02636 {
02637   CLEAR_BIT(TIMx->CCER, Channels);
02638 }
02639
02640 /**
02641   * @brief  Indicate whether channel(s) is(are) enabled.
02642   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
02643   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
02644   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
02645   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
02646   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
02647   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
02648   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
02649   *         CCER         CC4NE         LL_TIM_CC_IsEnabledChannel\n
02650   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
02651   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
02652   * @param  TIMx Timer instance
02653   * @param  Channels This parameter can be a combination of the following values:
02654   *         @arg @ref LL_TIM_CHANNEL_CH1
02655   *         @arg @ref LL_TIM_CHANNEL_CH1N
02656   *         @arg @ref LL_TIM_CHANNEL_CH2
02657   *         @arg @ref LL_TIM_CHANNEL_CH2N
02658   *         @arg @ref LL_TIM_CHANNEL_CH3
02659   *         @arg @ref LL_TIM_CHANNEL_CH3N
02660   *         @arg @ref LL_TIM_CHANNEL_CH4
02661   *         @arg @ref LL_TIM_CHANNEL_CH4N
02662   *         @arg @ref LL_TIM_CHANNEL_CH5
02663   *         @arg @ref LL_TIM_CHANNEL_CH6
02664   * @retval State of bit (1 or 0).
02665   */
02666 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
02667 {
02668   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
02669 }
02670
02671 /**
02672   * @}
02673   */
02674
02675 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
02676   * @{
02677   */
02678 /**
02679   * @brief  Configure an output channel.
02680   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
02681   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
02682   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
02683   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
02684   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
02685   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
02686   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
02687   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
02688   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
02689   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
02690   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
02691   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
02692   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
02693   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
02694   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
02695   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
02696   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
02697   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
02698   * @param  TIMx Timer instance
02699   * @param  Channel This parameter can be one of the following values:
02700   *         @arg @ref LL_TIM_CHANNEL_CH1
02701   *         @arg @ref LL_TIM_CHANNEL_CH2
02702   *         @arg @ref LL_TIM_CHANNEL_CH3
02703   *         @arg @ref LL_TIM_CHANNEL_CH4
02704   *         @arg @ref LL_TIM_CHANNEL_CH5
02705   *         @arg @ref LL_TIM_CHANNEL_CH6
02706   * @param  Configuration This parameter must be a combination of all the following values:
02707   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
02708   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
02709   * @retval None
02710   */
02711 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02712 {
02713   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02714   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02715   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
02716   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
02717              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
02718   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
02719              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
02720 }
02721
02722 /**
02723   * @brief  Define the behavior of the output reference signal OCxREF from which
02724   *         OCx and OCxN (when relevant) are derived.
02725   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
02726   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
02727   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
02728   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
02729   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02730   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02731   * @param  TIMx Timer instance
02732   * @param  Channel This parameter can be one of the following values:
02733   *         @arg @ref LL_TIM_CHANNEL_CH1
02734   *         @arg @ref LL_TIM_CHANNEL_CH2
02735   *         @arg @ref LL_TIM_CHANNEL_CH3
02736   *         @arg @ref LL_TIM_CHANNEL_CH4
02737   *         @arg @ref LL_TIM_CHANNEL_CH5
02738   *         @arg @ref LL_TIM_CHANNEL_CH6
02739   * @param  Mode This parameter can be one of the following values:
02740   *         @arg @ref LL_TIM_OCMODE_FROZEN
02741   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02742   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02743   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02744   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02745   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02746   *         @arg @ref LL_TIM_OCMODE_PWM1
02747   *         @arg @ref LL_TIM_OCMODE_PWM2
02748   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02749   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02750   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02751   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02752   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
02753   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
02754   *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
02755   *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
02756   * @retval None
02757   */
02758 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
02759 {
02760   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02761   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02762   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
02763 }
02764
02765 /**
02766   * @brief  Get the output compare mode of an output channel.
02767   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
02768   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
02769   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
02770   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
02771   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02772   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02773   * @param  TIMx Timer instance
02774   * @param  Channel This parameter can be one of the following values:
02775   *         @arg @ref LL_TIM_CHANNEL_CH1
02776   *         @arg @ref LL_TIM_CHANNEL_CH2
02777   *         @arg @ref LL_TIM_CHANNEL_CH3
02778   *         @arg @ref LL_TIM_CHANNEL_CH4
02779   *         @arg @ref LL_TIM_CHANNEL_CH5
02780   *         @arg @ref LL_TIM_CHANNEL_CH6
02781   * @retval Returned value can be one of the following values:
02782   *         @arg @ref LL_TIM_OCMODE_FROZEN
02783   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02784   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02785   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02786   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02787   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02788   *         @arg @ref LL_TIM_OCMODE_PWM1
02789   *         @arg @ref LL_TIM_OCMODE_PWM2
02790   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02791   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02792   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02793   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02794   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
02795   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
02796   *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
02797   *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
02798   */
02799 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
02800 {
02801   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02802   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02803   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02804 }
02805
02806 /**
02807   * @brief  Set the polarity of an output channel.
02808   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02809   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02810   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02811   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02812   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02813   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02814   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02815   *         CCER         CC4NP         LL_TIM_OC_SetPolarity\n
02816   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02817   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02818   * @param  TIMx Timer instance
02819   * @param  Channel This parameter can be one of the following values:
02820   *         @arg @ref LL_TIM_CHANNEL_CH1
02821   *         @arg @ref LL_TIM_CHANNEL_CH1N
02822   *         @arg @ref LL_TIM_CHANNEL_CH2
02823   *         @arg @ref LL_TIM_CHANNEL_CH2N
02824   *         @arg @ref LL_TIM_CHANNEL_CH3
02825   *         @arg @ref LL_TIM_CHANNEL_CH3N
02826   *         @arg @ref LL_TIM_CHANNEL_CH4
02827   *         @arg @ref LL_TIM_CHANNEL_CH4N
02828   *         @arg @ref LL_TIM_CHANNEL_CH5
02829   *         @arg @ref LL_TIM_CHANNEL_CH6
02830   * @param  Polarity This parameter can be one of the following values:
02831   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02832   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02833   * @retval None
02834   */
02835 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
02836 {
02837   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02838   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02839 }
02840
02841 /**
02842   * @brief  Get the polarity of an output channel.
02843   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02844   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02845   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02846   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02847   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02848   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02849   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02850   *         CCER         CC4NP         LL_TIM_OC_GetPolarity\n
02851   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02852   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02853   * @param  TIMx Timer instance
02854   * @param  Channel This parameter can be one of the following values:
02855   *         @arg @ref LL_TIM_CHANNEL_CH1
02856   *         @arg @ref LL_TIM_CHANNEL_CH1N
02857   *         @arg @ref LL_TIM_CHANNEL_CH2
02858   *         @arg @ref LL_TIM_CHANNEL_CH2N
02859   *         @arg @ref LL_TIM_CHANNEL_CH3
02860   *         @arg @ref LL_TIM_CHANNEL_CH3N
02861   *         @arg @ref LL_TIM_CHANNEL_CH4
02862   *         @arg @ref LL_TIM_CHANNEL_CH4N
02863   *         @arg @ref LL_TIM_CHANNEL_CH5
02864   *         @arg @ref LL_TIM_CHANNEL_CH6
02865   * @retval Returned value can be one of the following values:
02866   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02867   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02868   */
02869 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
02870 {
02871   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02872   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02873 }
02874
02875 /**
02876   * @brief  Set the IDLE state of an output channel
02877   * @note This function is significant only for the timer instances
02878   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
02879   *       can be used to check whether or not a timer instance provides
02880   *       a break input.
02881   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02882   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02883   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02884   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02885   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02886   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02887   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02888   *         CR2         OIS4N         LL_TIM_OC_SetIdleState\n
02889   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02890   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02891   * @param  TIMx Timer instance
02892   * @param  Channel This parameter can be one of the following values:
02893   *         @arg @ref LL_TIM_CHANNEL_CH1
02894   *         @arg @ref LL_TIM_CHANNEL_CH1N
02895   *         @arg @ref LL_TIM_CHANNEL_CH2
02896   *         @arg @ref LL_TIM_CHANNEL_CH2N
02897   *         @arg @ref LL_TIM_CHANNEL_CH3
02898   *         @arg @ref LL_TIM_CHANNEL_CH3N
02899   *         @arg @ref LL_TIM_CHANNEL_CH4
02900   *         @arg @ref LL_TIM_CHANNEL_CH4N
02901   *         @arg @ref LL_TIM_CHANNEL_CH5
02902   *         @arg @ref LL_TIM_CHANNEL_CH6
02903   * @param  IdleState This parameter can be one of the following values:
02904   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02905   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02906   * @retval None
02907   */
02908 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02909 {
02910   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02911   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02912 }
02913
02914 /**
02915   * @brief  Get the IDLE state of an output channel
02916   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02917   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02918   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02919   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02920   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02921   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02922   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02923   *         CR2         OIS4N         LL_TIM_OC_GetIdleState\n
02924   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02925   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02926   * @param  TIMx Timer instance
02927   * @param  Channel This parameter can be one of the following values:
02928   *         @arg @ref LL_TIM_CHANNEL_CH1
02929   *         @arg @ref LL_TIM_CHANNEL_CH1N
02930   *         @arg @ref LL_TIM_CHANNEL_CH2
02931   *         @arg @ref LL_TIM_CHANNEL_CH2N
02932   *         @arg @ref LL_TIM_CHANNEL_CH3
02933   *         @arg @ref LL_TIM_CHANNEL_CH3N
02934   *         @arg @ref LL_TIM_CHANNEL_CH4
02935   *         @arg @ref LL_TIM_CHANNEL_CH4N
02936   *         @arg @ref LL_TIM_CHANNEL_CH5
02937   *         @arg @ref LL_TIM_CHANNEL_CH6
02938   * @retval Returned value can be one of the following values:
02939   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02940   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02941   */
02942 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
02943 {
02944   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02945   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02946 }
02947
02948 /**
02949   * @brief  Enable fast mode for the output channel.
02950   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02951   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02952   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02953   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02954   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02955   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02956   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02957   * @param  TIMx Timer instance
02958   * @param  Channel This parameter can be one of the following values:
02959   *         @arg @ref LL_TIM_CHANNEL_CH1
02960   *         @arg @ref LL_TIM_CHANNEL_CH2
02961   *         @arg @ref LL_TIM_CHANNEL_CH3
02962   *         @arg @ref LL_TIM_CHANNEL_CH4
02963   *         @arg @ref LL_TIM_CHANNEL_CH5
02964   *         @arg @ref LL_TIM_CHANNEL_CH6
02965   * @retval None
02966   */
02967 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02968 {
02969   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02970   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02971   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02972
02973 }
02974
02975 /**
02976   * @brief  Disable fast mode for the output channel.
02977   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02978   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02979   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02980   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02981   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02982   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02983   * @param  TIMx Timer instance
02984   * @param  Channel This parameter can be one of the following values:
02985   *         @arg @ref LL_TIM_CHANNEL_CH1
02986   *         @arg @ref LL_TIM_CHANNEL_CH2
02987   *         @arg @ref LL_TIM_CHANNEL_CH3
02988   *         @arg @ref LL_TIM_CHANNEL_CH4
02989   *         @arg @ref LL_TIM_CHANNEL_CH5
02990   *         @arg @ref LL_TIM_CHANNEL_CH6
02991   * @retval None
02992   */
02993 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02994 {
02995   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02996   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02997   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02998
02999 }
03000
03001 /**
03002   * @brief  Indicates whether fast mode is enabled for the output channel.
03003   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
03004   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
03005   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
03006   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
03007   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
03008   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
03009   * @param  TIMx Timer instance
03010   * @param  Channel This parameter can be one of the following values:
03011   *         @arg @ref LL_TIM_CHANNEL_CH1
03012   *         @arg @ref LL_TIM_CHANNEL_CH2
03013   *         @arg @ref LL_TIM_CHANNEL_CH3
03014   *         @arg @ref LL_TIM_CHANNEL_CH4
03015   *         @arg @ref LL_TIM_CHANNEL_CH5
03016   *         @arg @ref LL_TIM_CHANNEL_CH6
03017   * @retval State of bit (1 or 0).
03018   */
03019 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
03020 {
03021   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03022   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03023   uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
03024   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
03025 }
03026
03027 /**
03028   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
03029   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
03030   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
03031   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
03032   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
03033   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
03034   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
03035   * @param  TIMx Timer instance
03036   * @param  Channel This parameter can be one of the following values:
03037   *         @arg @ref LL_TIM_CHANNEL_CH1
03038   *         @arg @ref LL_TIM_CHANNEL_CH2
03039   *         @arg @ref LL_TIM_CHANNEL_CH3
03040   *         @arg @ref LL_TIM_CHANNEL_CH4
03041   *         @arg @ref LL_TIM_CHANNEL_CH5
03042   *         @arg @ref LL_TIM_CHANNEL_CH6
03043   * @retval None
03044   */
03045 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
03046 {
03047   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03048   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03049   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
03050 }
03051
03052 /**
03053   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
03054   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
03055   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
03056   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
03057   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
03058   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
03059   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
03060   * @param  TIMx Timer instance
03061   * @param  Channel This parameter can be one of the following values:
03062   *         @arg @ref LL_TIM_CHANNEL_CH1
03063   *         @arg @ref LL_TIM_CHANNEL_CH2
03064   *         @arg @ref LL_TIM_CHANNEL_CH3
03065   *         @arg @ref LL_TIM_CHANNEL_CH4
03066   *         @arg @ref LL_TIM_CHANNEL_CH5
03067   *         @arg @ref LL_TIM_CHANNEL_CH6
03068   * @retval None
03069   */
03070 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
03071 {
03072   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03073   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03074   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
03075 }
03076
03077 /**
03078   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
03079   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
03080   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
03081   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
03082   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
03083   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
03084   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
03085   * @param  TIMx Timer instance
03086   * @param  Channel This parameter can be one of the following values:
03087   *         @arg @ref LL_TIM_CHANNEL_CH1
03088   *         @arg @ref LL_TIM_CHANNEL_CH2
03089   *         @arg @ref LL_TIM_CHANNEL_CH3
03090   *         @arg @ref LL_TIM_CHANNEL_CH4
03091   *         @arg @ref LL_TIM_CHANNEL_CH5
03092   *         @arg @ref LL_TIM_CHANNEL_CH6
03093   * @retval State of bit (1 or 0).
03094   */
03095 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
03096 {
03097   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03098   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03099   uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
03100   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
03101 }
03102
03103 /**
03104   * @brief  Enable clearing the output channel on an external event.
03105   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
03106   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
03107   *       or not a timer instance can clear the OCxREF signal on an external event.
03108   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
03109   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
03110   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
03111   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
03112   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
03113   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
03114   * @param  TIMx Timer instance
03115   * @param  Channel This parameter can be one of the following values:
03116   *         @arg @ref LL_TIM_CHANNEL_CH1
03117   *         @arg @ref LL_TIM_CHANNEL_CH2
03118   *         @arg @ref LL_TIM_CHANNEL_CH3
03119   *         @arg @ref LL_TIM_CHANNEL_CH4
03120   *         @arg @ref LL_TIM_CHANNEL_CH5
03121   *         @arg @ref LL_TIM_CHANNEL_CH6
03122   * @retval None
03123   */
03124 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
03125 {
03126   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03127   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03128   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
03129 }
03130
03131 /**
03132   * @brief  Disable clearing the output channel on an external event.
03133   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
03134   *       or not a timer instance can clear the OCxREF signal on an external event.
03135   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
03136   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
03137   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
03138   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
03139   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
03140   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
03141   * @param  TIMx Timer instance
03142   * @param  Channel This parameter can be one of the following values:
03143   *         @arg @ref LL_TIM_CHANNEL_CH1
03144   *         @arg @ref LL_TIM_CHANNEL_CH2
03145   *         @arg @ref LL_TIM_CHANNEL_CH3
03146   *         @arg @ref LL_TIM_CHANNEL_CH4
03147   *         @arg @ref LL_TIM_CHANNEL_CH5
03148   *         @arg @ref LL_TIM_CHANNEL_CH6
03149   * @retval None
03150   */
03151 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
03152 {
03153   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03154   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03155   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
03156 }
03157
03158 /**
03159   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
03160   * @note This function enables clearing the output channel on an external event.
03161   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
03162   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
03163   *       or not a timer instance can clear the OCxREF signal on an external event.
03164   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
03165   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
03166   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
03167   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
03168   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
03169   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
03170   * @param  TIMx Timer instance
03171   * @param  Channel This parameter can be one of the following values:
03172   *         @arg @ref LL_TIM_CHANNEL_CH1
03173   *         @arg @ref LL_TIM_CHANNEL_CH2
03174   *         @arg @ref LL_TIM_CHANNEL_CH3
03175   *         @arg @ref LL_TIM_CHANNEL_CH4
03176   *         @arg @ref LL_TIM_CHANNEL_CH5
03177   *         @arg @ref LL_TIM_CHANNEL_CH6
03178   * @retval State of bit (1 or 0).
03179   */
03180 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
03181 {
03182   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03183   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03184   uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
03185   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
03186 }
03187
03188 /**
03189   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
03190   *         the Ocx and OCxN signals).
03191   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03192   *       dead-time insertion feature is supported by a timer instance.
03193   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
03194   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
03195   * @param  TIMx Timer instance
03196   * @param  DeadTime between Min_Data=0 and Max_Data=255
03197   * @retval None
03198   */
03199 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
03200 {
03201   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
03202 }
03203
03204 /**
03205   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
03206   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
03207   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03208   *       whether or not a timer instance supports a 32 bits counter.
03209   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03210   *       output channel 1 is supported by a timer instance.
03211   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03212   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
03213   * @param  TIMx Timer instance
03214   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03215   * @retval None
03216   */
03217 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
03218 {
03219   WRITE_REG(TIMx->CCR1, CompareValue);
03220 }
03221
03222 /**
03223   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
03224   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
03225   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03226   *       whether or not a timer instance supports a 32 bits counter.
03227   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03228   *       output channel 2 is supported by a timer instance.
03229   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03230   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
03231   * @param  TIMx Timer instance
03232   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03233   * @retval None
03234   */
03235 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
03236 {
03237   WRITE_REG(TIMx->CCR2, CompareValue);
03238 }
03239
03240 /**
03241   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
03242   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
03243   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03244   *       whether or not a timer instance supports a 32 bits counter.
03245   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03246   *       output channel is supported by a timer instance.
03247   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03248   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
03249   * @param  TIMx Timer instance
03250   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03251   * @retval None
03252   */
03253 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
03254 {
03255   WRITE_REG(TIMx->CCR3, CompareValue);
03256 }
03257
03258 /**
03259   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
03260   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
03261   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03262   *       whether or not a timer instance supports a 32 bits counter.
03263   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03264   *       output channel 4 is supported by a timer instance.
03265   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03266   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
03267   * @param  TIMx Timer instance
03268   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03269   * @retval None
03270   */
03271 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
03272 {
03273   WRITE_REG(TIMx->CCR4, CompareValue);
03274 }
03275
03276 /**
03277   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
03278   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
03279   *       output channel 5 is supported by a timer instance.
03280   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03281   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
03282   * @param  TIMx Timer instance
03283   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03284   * @retval None
03285   */
03286 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
03287 {
03288   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
03289 }
03290
03291 /**
03292   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
03293   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
03294   *       output channel 6 is supported by a timer instance.
03295   * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
03296   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
03297   * @param  TIMx Timer instance
03298   * @param  CompareValue between Min_Data=0 and Max_Data=65535
03299   * @retval None
03300   */
03301 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
03302 {
03303   WRITE_REG(TIMx->CCR6, CompareValue);
03304 }
03305
03306 /**
03307   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
03308   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
03309   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03310   *       whether or not a timer instance supports a 32 bits counter.
03311   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03312   *       output channel 1 is supported by a timer instance.
03313   * @note If dithering is activated, pay attention to the returned value interpretation.
03314   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
03315   * @param  TIMx Timer instance
03316   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03317   */
03318 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
03319 {
03320   return (uint32_t)(READ_REG(TIMx->CCR1));
03321 }
03322
03323 /**
03324   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
03325   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
03326   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03327   *       whether or not a timer instance supports a 32 bits counter.
03328   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03329   *       output channel 2 is supported by a timer instance.
03330   * @note If dithering is activated, pay attention to the returned value interpretation.
03331   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
03332   * @param  TIMx Timer instance
03333   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03334   */
03335 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
03336 {
03337   return (uint32_t)(READ_REG(TIMx->CCR2));
03338 }
03339
03340 /**
03341   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
03342   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
03343   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03344   *       whether or not a timer instance supports a 32 bits counter.
03345   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03346   *       output channel 3 is supported by a timer instance.
03347   * @note If dithering is activated, pay attention to the returned value interpretation.
03348   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
03349   * @param  TIMx Timer instance
03350   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03351   */
03352 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
03353 {
03354   return (uint32_t)(READ_REG(TIMx->CCR3));
03355 }
03356
03357 /**
03358   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
03359   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
03360   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03361   *       whether or not a timer instance supports a 32 bits counter.
03362   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03363   *       output channel 4 is supported by a timer instance.
03364   * @note If dithering is activated, pay attention to the returned value interpretation.
03365   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
03366   * @param  TIMx Timer instance
03367   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03368   */
03369 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
03370 {
03371   return (uint32_t)(READ_REG(TIMx->CCR4));
03372 }
03373
03374 /**
03375   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
03376   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
03377   *       output channel 5 is supported by a timer instance.
03378   * @note If dithering is activated, pay attention to the returned value interpretation.
03379   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
03380   * @param  TIMx Timer instance
03381   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03382   */
03383 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
03384 {
03385   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
03386 }
03387
03388 /**
03389   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
03390   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
03391   *       output channel 6 is supported by a timer instance.
03392   * @note If dithering is activated, pay attention to the returned value interpretation.
03393   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
03394   * @param  TIMx Timer instance
03395   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
03396   */
03397 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
03398 {
03399   return (uint32_t)(READ_REG(TIMx->CCR6));
03400 }
03401
03402 /**
03403   * @brief  Select on which reference signal the OC5REF is combined to.
03404   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
03405   *       whether or not a timer instance supports the combined 3-phase PWM mode.
03406   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
03407   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
03408   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
03409   * @param  TIMx Timer instance
03410   * @param  GroupCH5 This parameter can be a combination of the following values:
03411   *         @arg @ref LL_TIM_GROUPCH5_NONE
03412   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
03413   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
03414   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
03415   * @retval None
03416   */
03417 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
03418 {
03419   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
03420 }
03421
03422 /**
03423   * @brief  Set the pulse on compare pulse width prescaler.
03424   * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
03425   *       whether or not the pulse on compare feature is supported by the timer
03426   *       instance.
03427   * @rmtoll ECR          PWPRSC           LL_TIM_OC_SetPulseWidthPrescaler
03428   * @param  TIMx Timer instance
03429   * @param  PulseWidthPrescaler This parameter can be one of the following values:
03430   *         @arg @ref LL_TIM_PWPRSC_X1
03431   *         @arg @ref LL_TIM_PWPRSC_X2
03432   *         @arg @ref LL_TIM_PWPRSC_X4
03433   *         @arg @ref LL_TIM_PWPRSC_X8
03434   *         @arg @ref LL_TIM_PWPRSC_X16
03435   *         @arg @ref LL_TIM_PWPRSC_X32
03436   *         @arg @ref LL_TIM_PWPRSC_X64
03437   *         @arg @ref LL_TIM_PWPRSC_X128
03438   * @retval None
03439   */
03440 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
03441 {
03442   MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
03443 }
03444
03445 /**
03446   * @brief  Get the pulse on compare pulse width prescaler.
03447   * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
03448   *       whether or not the pulse on compare feature is supported by the timer
03449   *       instance.
03450   * @rmtoll ECR          PWPRSC           LL_TIM_OC_GetPulseWidthPrescaler
03451   * @param  TIMx Timer instance
03452   * @retval Returned value can be one of the following values:
03453   *         @arg @ref LL_TIM_PWPRSC_X1
03454   *         @arg @ref LL_TIM_PWPRSC_X2
03455   *         @arg @ref LL_TIM_PWPRSC_X4
03456   *         @arg @ref LL_TIM_PWPRSC_X8
03457   *         @arg @ref LL_TIM_PWPRSC_X16
03458   *         @arg @ref LL_TIM_PWPRSC_X32
03459   *         @arg @ref LL_TIM_PWPRSC_X64
03460   *         @arg @ref LL_TIM_PWPRSC_X128
03461   */
03462 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
03463 {
03464   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
03465 }
03466
03467 /**
03468   * @brief  Set the pulse on compare pulse width duration.
03469   * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
03470   *       whether or not the pulse on compare feature is supported by the timer
03471   *       instance.
03472   * @rmtoll ECR          PW           LL_TIM_OC_SetPulseWidth
03473   * @param  TIMx Timer instance
03474   * @param  PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
03478 {
03479   MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
03480 }
03481
03482 /**
03483   * @brief  Get the pulse on compare pulse width duration.
03484   * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
03485   *       whether or not the pulse on compare feature is supported by the timer
03486   *       instance.
03487   * @rmtoll ECR          PW           LL_TIM_OC_GetPulseWidth
03488   * @param  TIMx Timer instance
03489   * @retval Returned value can be between Min_Data=0 and Max_Data=255:
03490   */
03491 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
03492 {
03493   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
03494 }
03495
03496 /**
03497   * @}
03498   */
03499
03500 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
03501   * @{
03502   */
03503 /**
03504   * @brief  Configure input channel.
03505   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
03506   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
03507   *         CCMR1        IC1F          LL_TIM_IC_Config\n
03508   *         CCMR1        CC2S          LL_TIM_IC_Config\n
03509   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
03510   *         CCMR1        IC2F          LL_TIM_IC_Config\n
03511   *         CCMR2        CC3S          LL_TIM_IC_Config\n
03512   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
03513   *         CCMR2        IC3F          LL_TIM_IC_Config\n
03514   *         CCMR2        CC4S          LL_TIM_IC_Config\n
03515   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
03516   *         CCMR2        IC4F          LL_TIM_IC_Config\n
03517   *         CCER         CC1P          LL_TIM_IC_Config\n
03518   *         CCER         CC1NP         LL_TIM_IC_Config\n
03519   *         CCER         CC2P          LL_TIM_IC_Config\n
03520   *         CCER         CC2NP         LL_TIM_IC_Config\n
03521   *         CCER         CC3P          LL_TIM_IC_Config\n
03522   *         CCER         CC3NP         LL_TIM_IC_Config\n
03523   *         CCER         CC4P          LL_TIM_IC_Config\n
03524   *         CCER         CC4NP         LL_TIM_IC_Config
03525   * @param  TIMx Timer instance
03526   * @param  Channel This parameter can be one of the following values:
03527   *         @arg @ref LL_TIM_CHANNEL_CH1
03528   *         @arg @ref LL_TIM_CHANNEL_CH2
03529   *         @arg @ref LL_TIM_CHANNEL_CH3
03530   *         @arg @ref LL_TIM_CHANNEL_CH4
03531   * @param  Configuration This parameter must be a combination of all the following values:
03532   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
03533   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
03534   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
03535   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
03536   * @retval None
03537   */
03538 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
03539 {
03540   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03541   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03542   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
03543              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
03544              << SHIFT_TAB_ICxx[iChannel]);
03545   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
03546              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
03547 }
03548
03549 /**
03550   * @brief  Set the active input.
03551   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
03552   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
03553   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
03554   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
03555   * @param  TIMx Timer instance
03556   * @param  Channel This parameter can be one of the following values:
03557   *         @arg @ref LL_TIM_CHANNEL_CH1
03558   *         @arg @ref LL_TIM_CHANNEL_CH2
03559   *         @arg @ref LL_TIM_CHANNEL_CH3
03560   *         @arg @ref LL_TIM_CHANNEL_CH4
03561   * @param  ICActiveInput This parameter can be one of the following values:
03562   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
03563   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
03564   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
03565   * @retval None
03566   */
03567 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
03568 {
03569   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03570   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03571   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03572 }
03573
03574 /**
03575   * @brief  Get the current active input.
03576   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
03577   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
03578   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
03579   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
03580   * @param  TIMx Timer instance
03581   * @param  Channel This parameter can be one of the following values:
03582   *         @arg @ref LL_TIM_CHANNEL_CH1
03583   *         @arg @ref LL_TIM_CHANNEL_CH2
03584   *         @arg @ref LL_TIM_CHANNEL_CH3
03585   *         @arg @ref LL_TIM_CHANNEL_CH4
03586   * @retval Returned value can be one of the following values:
03587   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
03588   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
03589   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
03590   */
03591 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
03592 {
03593   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03594   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03595   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03596 }
03597
03598 /**
03599   * @brief  Set the prescaler of input channel.
03600   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
03601   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
03602   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
03603   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
03604   * @param  TIMx Timer instance
03605   * @param  Channel This parameter can be one of the following values:
03606   *         @arg @ref LL_TIM_CHANNEL_CH1
03607   *         @arg @ref LL_TIM_CHANNEL_CH2
03608   *         @arg @ref LL_TIM_CHANNEL_CH3
03609   *         @arg @ref LL_TIM_CHANNEL_CH4
03610   * @param  ICPrescaler This parameter can be one of the following values:
03611   *         @arg @ref LL_TIM_ICPSC_DIV1
03612   *         @arg @ref LL_TIM_ICPSC_DIV2
03613   *         @arg @ref LL_TIM_ICPSC_DIV4
03614   *         @arg @ref LL_TIM_ICPSC_DIV8
03615   * @retval None
03616   */
03617 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
03618 {
03619   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03620   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03621   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03622 }
03623
03624 /**
03625   * @brief  Get the current prescaler value acting on an  input channel.
03626   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
03627   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
03628   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
03629   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
03630   * @param  TIMx Timer instance
03631   * @param  Channel This parameter can be one of the following values:
03632   *         @arg @ref LL_TIM_CHANNEL_CH1
03633   *         @arg @ref LL_TIM_CHANNEL_CH2
03634   *         @arg @ref LL_TIM_CHANNEL_CH3
03635   *         @arg @ref LL_TIM_CHANNEL_CH4
03636   * @retval Returned value can be one of the following values:
03637   *         @arg @ref LL_TIM_ICPSC_DIV1
03638   *         @arg @ref LL_TIM_ICPSC_DIV2
03639   *         @arg @ref LL_TIM_ICPSC_DIV4
03640   *         @arg @ref LL_TIM_ICPSC_DIV8
03641   */
03642 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
03643 {
03644   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03645   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03646   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03647 }
03648
03649 /**
03650   * @brief  Set the input filter duration.
03651   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
03652   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
03653   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
03654   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
03655   * @param  TIMx Timer instance
03656   * @param  Channel This parameter can be one of the following values:
03657   *         @arg @ref LL_TIM_CHANNEL_CH1
03658   *         @arg @ref LL_TIM_CHANNEL_CH2
03659   *         @arg @ref LL_TIM_CHANNEL_CH3
03660   *         @arg @ref LL_TIM_CHANNEL_CH4
03661   * @param  ICFilter This parameter can be one of the following values:
03662   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03663   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03664   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03665   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03666   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03667   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03668   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03669   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03670   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03671   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03672   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03673   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03674   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03675   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03676   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03677   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03678   * @retval None
03679   */
03680 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
03681 {
03682   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03683   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03684   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03685 }
03686
03687 /**
03688   * @brief  Get the input filter duration.
03689   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
03690   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
03691   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
03692   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
03693   * @param  TIMx Timer instance
03694   * @param  Channel This parameter can be one of the following values:
03695   *         @arg @ref LL_TIM_CHANNEL_CH1
03696   *         @arg @ref LL_TIM_CHANNEL_CH2
03697   *         @arg @ref LL_TIM_CHANNEL_CH3
03698   *         @arg @ref LL_TIM_CHANNEL_CH4
03699   * @retval Returned value can be one of the following values:
03700   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03701   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03702   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03703   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03704   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03705   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03706   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03707   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03708   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03709   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03710   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03711   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03712   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03713   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03714   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03715   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03716   */
03717 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
03718 {
03719   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03720   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03721   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03722 }
03723
03724 /**
03725   * @brief  Set the input channel polarity.
03726   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
03727   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
03728   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
03729   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
03730   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
03731   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
03732   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
03733   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
03734   * @param  TIMx Timer instance
03735   * @param  Channel This parameter can be one of the following values:
03736   *         @arg @ref LL_TIM_CHANNEL_CH1
03737   *         @arg @ref LL_TIM_CHANNEL_CH2
03738   *         @arg @ref LL_TIM_CHANNEL_CH3
03739   *         @arg @ref LL_TIM_CHANNEL_CH4
03740   * @param  ICPolarity This parameter can be one of the following values:
03741   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03742   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03743   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03744   * @retval None
03745   */
03746 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
03747 {
03748   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03749   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
03750              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
03751 }
03752
03753 /**
03754   * @brief  Get the current input channel polarity.
03755   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
03756   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
03757   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
03758   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
03759   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
03760   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
03761   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
03762   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
03763   * @param  TIMx Timer instance
03764   * @param  Channel This parameter can be one of the following values:
03765   *         @arg @ref LL_TIM_CHANNEL_CH1
03766   *         @arg @ref LL_TIM_CHANNEL_CH2
03767   *         @arg @ref LL_TIM_CHANNEL_CH3
03768   *         @arg @ref LL_TIM_CHANNEL_CH4
03769   * @retval Returned value can be one of the following values:
03770   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03771   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03772   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03773   */
03774 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
03775 {
03776   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03777   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
03778           SHIFT_TAB_CCxP[iChannel]);
03779 }
03780
03781 /**
03782   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
03783   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03784   *       a timer instance provides an XOR input.
03785   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
03786   * @param  TIMx Timer instance
03787   * @retval None
03788   */
03789 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
03790 {
03791   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
03792 }
03793
03794 /**
03795   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
03796   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03797   *       a timer instance provides an XOR input.
03798   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
03799   * @param  TIMx Timer instance
03800   * @retval None
03801   */
03802 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
03803 {
03804   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
03805 }
03806
03807 /**
03808   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
03809   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03810   * a timer instance provides an XOR input.
03811   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
03812   * @param  TIMx Timer instance
03813   * @retval State of bit (1 or 0).
03814   */
03815 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
03816 {
03817   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
03818 }
03819
03820 /**
03821   * @brief  Get captured value for input channel 1.
03822   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03823   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03824   *       whether or not a timer instance supports a 32 bits counter.
03825   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03826   *       input channel 1 is supported by a timer instance.
03827   * @note If dithering is activated, pay attention to the returned value interpretation.
03828   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
03829   * @param  TIMx Timer instance
03830   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03831   */
03832 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
03833 {
03834   return (uint32_t)(READ_REG(TIMx->CCR1));
03835 }
03836
03837 /**
03838   * @brief  Get captured value for input channel 2.
03839   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03840   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03841   *       whether or not a timer instance supports a 32 bits counter.
03842   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03843   *       input channel 2 is supported by a timer instance.
03844   * @note If dithering is activated, pay attention to the returned value interpretation.
03845   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
03846   * @param  TIMx Timer instance
03847   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03848   */
03849 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
03850 {
03851   return (uint32_t)(READ_REG(TIMx->CCR2));
03852 }
03853
03854 /**
03855   * @brief  Get captured value for input channel 3.
03856   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03857   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03858   *       whether or not a timer instance supports a 32 bits counter.
03859   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03860   *       input channel 3 is supported by a timer instance.
03861   * @note If dithering is activated, pay attention to the returned value interpretation.
03862   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
03863   * @param  TIMx Timer instance
03864   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03865   */
03866 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
03867 {
03868   return (uint32_t)(READ_REG(TIMx->CCR3));
03869 }
03870
03871 /**
03872   * @brief  Get captured value for input channel 4.
03873   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03874   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03875   *       whether or not a timer instance supports a 32 bits counter.
03876   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03877   *       input channel 4 is supported by a timer instance.
03878   * @note If dithering is activated, pay attention to the returned value interpretation.
03879   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
03880   * @param  TIMx Timer instance
03881   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03882   */
03883 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
03884 {
03885   return (uint32_t)(READ_REG(TIMx->CCR4));
03886 }
03887
03888 /**
03889   * @}
03890   */
03891
03892 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03893   * @{
03894   */
03895 /**
03896   * @brief  Enable external clock mode 2.
03897   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03898   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03899   *       whether or not a timer instance supports external clock mode2.
03900   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03901   * @param  TIMx Timer instance
03902   * @retval None
03903   */
03904 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
03905 {
03906   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03907 }
03908
03909 /**
03910   * @brief  Disable external clock mode 2.
03911   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03912   *       whether or not a timer instance supports external clock mode2.
03913   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03914   * @param  TIMx Timer instance
03915   * @retval None
03916   */
03917 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
03918 {
03919   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03920 }
03921
03922 /**
03923   * @brief  Indicate whether external clock mode 2 is enabled.
03924   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03925   *       whether or not a timer instance supports external clock mode2.
03926   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03927   * @param  TIMx Timer instance
03928   * @retval State of bit (1 or 0).
03929   */
03930 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
03931 {
03932   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
03933 }
03934
03935 /**
03936   * @brief  Set the clock source of the counter clock.
03937   * @note when selected clock source is external clock mode 1, the timer input
03938   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03939   *       function. This timer input must be configured by calling
03940   *       the @ref LL_TIM_IC_Config() function.
03941   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03942   *       whether or not a timer instance supports external clock mode1.
03943   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03944   *       whether or not a timer instance supports external clock mode2.
03945   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03946   *         SMCR         ECE           LL_TIM_SetClockSource
03947   * @param  TIMx Timer instance
03948   * @param  ClockSource This parameter can be one of the following values:
03949   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03950   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03951   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03952   * @retval None
03953   */
03954 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
03955 {
03956   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03957 }
03958
03959 /**
03960   * @brief  Set the encoder interface mode.
03961   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03962   *       whether or not a timer instance supports the encoder mode.
03963   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03964   * @param  TIMx Timer instance
03965   * @param  EncoderMode This parameter can be one of the following values:
03966   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03967   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03968   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03969   *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
03970   *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
03971   *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
03972   *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
03973   *         @arg @ref LL_TIM_ENCODERMODE_X1_TI1
03974   *         @arg @ref LL_TIM_ENCODERMODE_X1_TI2
03975   * @retval None
03976   */
03977 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03978 {
03979   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03980 }
03981
03982 /**
03983   * @}
03984   */
03985
03986 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03987   * @{
03988   */
03989 /**
03990   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03991   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03992   *       whether or not a timer instance can operate as a master timer.
03993   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03994   * @param  TIMx Timer instance
03995   * @param  TimerSynchronization This parameter can be one of the following values:
03996   *         @arg @ref LL_TIM_TRGO_RESET
03997   *         @arg @ref LL_TIM_TRGO_ENABLE
03998   *         @arg @ref LL_TIM_TRGO_UPDATE
03999   *         @arg @ref LL_TIM_TRGO_CC1IF
04000   *         @arg @ref LL_TIM_TRGO_OC1REF
04001   *         @arg @ref LL_TIM_TRGO_OC2REF
04002   *         @arg @ref LL_TIM_TRGO_OC3REF
04003   *         @arg @ref LL_TIM_TRGO_OC4REF
04004   *         @arg @ref LL_TIM_TRGO_ENCODERCLK
04005   * @retval None
04006   */
04007 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
04008 {
04009   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
04010 }
04011
04012 /**
04013   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
04014   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
04015   *       whether or not a timer instance can be used for ADC synchronization.
04016   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
04017   * @param  TIMx Timer Instance
04018   * @param  ADCSynchronization This parameter can be one of the following values:
04019   *         @arg @ref LL_TIM_TRGO2_RESET
04020   *         @arg @ref LL_TIM_TRGO2_ENABLE
04021   *         @arg @ref LL_TIM_TRGO2_UPDATE
04022   *         @arg @ref LL_TIM_TRGO2_CC1F
04023   *         @arg @ref LL_TIM_TRGO2_OC1
04024   *         @arg @ref LL_TIM_TRGO2_OC2
04025   *         @arg @ref LL_TIM_TRGO2_OC3
04026   *         @arg @ref LL_TIM_TRGO2_OC4
04027   *         @arg @ref LL_TIM_TRGO2_OC5
04028   *         @arg @ref LL_TIM_TRGO2_OC6
04029   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
04030   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
04031   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
04032   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
04033   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
04034   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
04035   * @retval None
04036   */
04037 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
04038 {
04039   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
04040 }
04041
04042 /**
04043   * @brief  Set the synchronization mode of a slave timer.
04044   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
04045   *       a timer instance can operate as a slave timer.
04046   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
04047   * @param  TIMx Timer instance
04048   * @param  SlaveMode This parameter can be one of the following values:
04049   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
04050   *         @arg @ref LL_TIM_SLAVEMODE_RESET
04051   *         @arg @ref LL_TIM_SLAVEMODE_GATED
04052   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
04053   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
04054   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
04055   * @retval None
04056   */
04057 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
04058 {
04059   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
04060 }
04061
04062 /**
04063   * @brief  Set the selects the trigger input to be used to synchronize the counter.
04064   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
04065   *       a timer instance can operate as a slave timer.
04066   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
04067   * @param  TIMx Timer instance
04068   * @param  TriggerInput This parameter can be one of the following values:
04069   *         @arg @ref LL_TIM_TS_ITR0
04070   *         @arg @ref LL_TIM_TS_ITR1
04071   *         @arg @ref LL_TIM_TS_ITR2
04072   *         @arg @ref LL_TIM_TS_ITR3
04073   *         @arg @ref LL_TIM_TS_ITR4
04074   *         @arg @ref LL_TIM_TS_ITR5
04075   *         @arg @ref LL_TIM_TS_ITR6
04076   *         @arg @ref LL_TIM_TS_ITR7
04077   *         @arg @ref LL_TIM_TS_ITR8
04078   *         @arg @ref LL_TIM_TS_ITR9
04079   *         @arg @ref LL_TIM_TS_ITR10
04080   *         @arg @ref LL_TIM_TS_ITR11
04081   *         @arg @ref LL_TIM_TS_TI1F_ED
04082   *         @arg @ref LL_TIM_TS_TI1FP1
04083   *         @arg @ref LL_TIM_TS_TI2FP2
04084   *         @arg @ref LL_TIM_TS_ETRF
04085   * @retval None
04086   */
04087 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
04088 {
04089   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
04090 }
04091
04092 /**
04093   * @brief  Enable the Master/Slave mode.
04094   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
04095   *       a timer instance can operate as a slave timer.
04096   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
04097   * @param  TIMx Timer instance
04098   * @retval None
04099   */
04100 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
04101 {
04102   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
04103 }
04104
04105 /**
04106   * @brief  Disable the Master/Slave mode.
04107   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
04108   *       a timer instance can operate as a slave timer.
04109   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
04110   * @param  TIMx Timer instance
04111   * @retval None
04112   */
04113 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
04114 {
04115   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
04116 }
04117
04118 /**
04119   * @brief Indicates whether the Master/Slave mode is enabled.
04120   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
04121   * a timer instance can operate as a slave timer.
04122   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
04123   * @param  TIMx Timer instance
04124   * @retval State of bit (1 or 0).
04125   */
04126 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
04127 {
04128   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
04129 }
04130
04131 /**
04132   * @brief  Configure the external trigger (ETR) input.
04133   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
04134   *       a timer instance provides an external trigger input.
04135   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
04136   *         SMCR         ETPS          LL_TIM_ConfigETR\n
04137   *         SMCR         ETF           LL_TIM_ConfigETR
04138   * @param  TIMx Timer instance
04139   * @param  ETRPolarity This parameter can be one of the following values:
04140   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
04141   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
04142   * @param  ETRPrescaler This parameter can be one of the following values:
04143   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
04144   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
04145   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
04146   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
04147   * @param  ETRFilter This parameter can be one of the following values:
04148   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
04149   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
04150   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
04151   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
04152   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
04153   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
04154   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
04155   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
04156   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
04157   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
04158   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
04159   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
04160   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
04161   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
04162   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
04163   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
04164   * @retval None
04165   */
04166 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
04167                                       uint32_t ETRFilter)
04168 {
04169   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
04170 }
04171
04172 /**
04173   * @brief  Select the external trigger (ETR) input source.
04174   * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
04175   *       not a timer instance supports ETR source selection.
04176   * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
04177   * @param  TIMx Timer instance
04178   * @param  ETRSource This parameter can be one of the following values:
04179   *
04180   *         TIM1: any combination of ETR_RMP where
04181   *
04182   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
04183   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
04184   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
04185   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
04186   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
04187   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5       (*)
04188   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6       (*)
04189   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7       (*)
04190   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
04191   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
04192   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
04193   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1   (*)
04194   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2   (*)
04195   *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3   (*)
04196   *
04197   *         TIM2: any combination of ETR_RMP where
04198   *
04199   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
04200   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
04201   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
04202   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
04203   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
04204   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5       (*)
04205   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6       (*)
04206   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7       (*)
04207   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
04208   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
04209   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR    (*)
04210   *            @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
04211   *
04212   *         TIM3: any combination of ETR_RMP where
04213   *
04214   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
04215   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
04216   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
04217   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
04218   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
04219   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5       (*)
04220   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6       (*)
04221   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7       (*)
04222   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
04223   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
04224   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
04225   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
04226   *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
04227   *
04228   *         TIM4: any combination of ETR_RMP where
04229   *
04230   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
04231   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
04232   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
04233   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
04234   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
04235   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5       (*)
04236   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6       (*)
04237   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7       (*)
04238   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
04239   *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR    (*)
04240   *
04241   *         TIM5: any combination of ETR_RMP where       (**)
04242   *
04243   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO        (*)
04244   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1       (*)
04245   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2       (*)
04246   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3       (*)
04247   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4       (*)
04248   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5       (*)
04249   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6       (*)
04250   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7       (*)
04251   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR    (*)
04252   *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR    (*)
04253   *
04254   *         TIM8: any combination of ETR_RMP where
04255   *
04256   *            . . ETR_RMP can be one of the following values
04257   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
04258   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
04259   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
04260   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
04261   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
04262   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5       (*)
04263   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6       (*)
04264   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7       (*)
04265   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
04266   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
04267   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
04268   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (*)
04269   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (*)
04270   *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   (*)
04271   *
04272   *         TIM20: any combination of ETR_RMP where       (**)
04273   *
04274   *            . . ETR_RMP can be one of the following values
04275   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO       (*)
04276   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1      (*)
04277   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2      (*)
04278   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3      (*)
04279   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4      (*)
04280   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5      (*)
04281   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6      (*)
04282   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7      (*)
04283   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1  (*)
04284   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2  (*)
04285   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3  (*)
04286   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1  (*)
04287   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2  (*)
04288   *            @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3  (*)
04289   *
04290   *         (*)  Value not defined in all devices. \n
04291   *         (**) Register not available in all devices.
04292   * @retval None
04293   */
04294 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
04295 {
04296   MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
04297 }
04298
04299 /**
04300   * @brief  Enable SMS preload.
04301   * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
04302   *       whether or not a timer instance supports the preload of SMS field in SMCR register.
04303   * @rmtoll SMCR         SMSPE           LL_TIM_EnableSMSPreload
04304   * @param  TIMx Timer instance
04305   * @retval None
04306   */
04307 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
04308 {
04309   SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
04310 }
04311
04312 /**
04313   * @brief  Disable SMS preload.
04314   * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
04315   *       whether or not a timer instance supports the preload of SMS field in SMCR register.
04316   * @rmtoll SMCR         SMSPE           LL_TIM_DisableSMSPreload
04317   * @param  TIMx Timer instance
04318   * @retval None
04319   */
04320 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
04321 {
04322   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
04323 }
04324
04325 /**
04326   * @brief  Indicate whether  SMS preload is enabled.
04327   * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
04328   *       whether or not a timer instance supports the preload of SMS field in SMCR register.
04329   * @rmtoll SMCR         SMSPE           LL_TIM_IsEnabledSMSPreload
04330   * @param  TIMx Timer instance
04331   * @retval State of bit (1 or 0).
04332   */
04333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
04334 {
04335   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
04336 }
04337
04338 /**
04339   * @brief  Set the preload source of SMS.
04340   * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
04341   *       whether or not a timer instance supports the preload of SMS field in SMCR register.
04342   * @rmtoll SMCR         SMSPS        LL_TIM_SetSMSPreloadSource\n
04343   * @param  TIMx Timer instance
04344   * @param  PreloadSource This parameter can be one of the following values:
04345   *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
04346   *         @arg @ref LL_TIM_SMSPS_INDEX
04347   * @retval None
04348   */
04349 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
04350 {
04351   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
04352 }
04353
04354 /**
04355   * @brief  Get the preload source of SMS.
04356   * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
04357   *       whether or not a timer instance supports the preload of SMS field in SMCR register.
04358   * @rmtoll SMCR         SMSPS        LL_TIM_GetSMSPreloadSource\n
04359   * @param  TIMx Timer instance
04360   * @retval Returned value can be one of the following values:
04361   *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
04362   *         @arg @ref LL_TIM_SMSPS_INDEX
04363   */
04364 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
04365 {
04366   return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
04367 }
04368
04369 /**
04370   * @}
04371   */
04372
04373 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
04374   * @{
04375   */
04376 /**
04377   * @brief  Enable the break function.
04378   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04379   *       a timer instance provides a break input.
04380   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
04381   * @param  TIMx Timer instance
04382   * @retval None
04383   */
04384 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
04385 {
04386   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
04387 }
04388
04389 /**
04390   * @brief  Disable the break function.
04391   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
04392   * @param  TIMx Timer instance
04393   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04394   *       a timer instance provides a break input.
04395   * @retval None
04396   */
04397 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
04398 {
04399   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
04400 }
04401
04402 /**
04403   * @brief  Configure the break input.
04404   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04405   *       a timer instance provides a break input.
04406   * @note Bidirectional mode is only supported by advanced timer instances.
04407   *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
04408   *       a timer instance is an advanced-control timer.
04409   * @note In bidirectional mode (BKBID bit set), the Break input is configured both
04410   *        in input mode and in open drain output mode. Any active Break event will
04411   *        assert a low logic level on the Break input to indicate an internal break
04412   *        event to external devices.
04413   * @note When bidirectional mode isn't supported, BreakAFMode must be set to
04414   *       LL_TIM_BREAK_AFMODE_INPUT.
04415   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
04416   *         BDTR         BKF           LL_TIM_ConfigBRK\n
04417   *         BDTR         BKBID         LL_TIM_ConfigBRK
04418   * @param  TIMx Timer instance
04419   * @param  BreakPolarity This parameter can be one of the following values:
04420   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
04421   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
04422   * @param  BreakFilter This parameter can be one of the following values:
04423   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
04424   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
04425   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
04426   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
04427   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
04428   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
04429   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
04430   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
04431   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
04432   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
04433   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
04434   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
04435   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
04436   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
04437   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
04438   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
04439   * @param  BreakAFMode This parameter can be one of the following values:
04440   *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
04441   *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
04442   * @retval None
04443   */
04444 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
04445                                       uint32_t BreakAFMode)
04446 {
04447   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
04448 }
04449
04450 /**
04451   * @brief  Disarm the break input (when it operates in bidirectional mode).
04452   * @note  The break input can be disarmed only when it is configured in
04453   *        bidirectional mode and when when MOE is reset.
04454   * @note  Purpose is to be able to have the input voltage back to high-state,
04455   *        whatever the time constant on the output .
04456   * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
04457   * @param  TIMx Timer instance
04458   * @retval None
04459   */
04460 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
04461 {
04462   SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
04463 }
04464
04465 /**
04466   * @brief  Enable the break 2 function.
04467   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
04468   *       a timer instance provides a second break input.
04469   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
04470   * @param  TIMx Timer instance
04471   * @retval None
04472   */
04473 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
04474 {
04475   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
04476 }
04477
04478 /**
04479   * @brief  Disable the break  2 function.
04480   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
04481   *       a timer instance provides a second break input.
04482   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
04483   * @param  TIMx Timer instance
04484   * @retval None
04485   */
04486 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
04487 {
04488   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
04489 }
04490
04491 /**
04492   * @brief  Configure the break 2 input.
04493   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
04494   *       a timer instance provides a second break input.
04495   * @note Bidirectional mode is only supported by advanced timer instances.
04496   *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
04497   *       a timer instance is an advanced-control timer.
04498   * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
04499   *        in input mode and in open drain output mode. Any active Break event will
04500   *        assert a low logic level on the Break 2 input to indicate an internal break
04501   *        event to external devices.
04502   * @note When bidirectional mode isn't supported, Break2AFMode must be set to
04503   *       LL_TIM_BREAK2_AFMODE_INPUT.
04504   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
04505   *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
04506   *         BDTR         BK2BID        LL_TIM_ConfigBRK2
04507   * @param  TIMx Timer instance
04508   * @param  Break2Polarity This parameter can be one of the following values:
04509   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
04510   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
04511   * @param  Break2Filter This parameter can be one of the following values:
04512   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
04513   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
04514   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
04515   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
04516   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
04517   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
04518   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
04519   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
04520   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
04521   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
04522   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
04523   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
04524   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
04525   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
04526   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
04527   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
04528   * @param  Break2AFMode This parameter can be one of the following values:
04529   *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
04530   *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
04531   * @retval None
04532   */
04533 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
04534                                        uint32_t Break2AFMode)
04535 {
04536   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
04537 }
04538
04539 /**
04540   * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
04541   * @note  The break 2 input can be disarmed only when it is configured in
04542   *        bidirectional mode and when when MOE is reset.
04543   * @note  Purpose is to be able to have the input voltage back to high-state,
04544   *        whatever the time constant on the output.
04545   * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
04546   * @param  TIMx Timer instance
04547   * @retval None
04548   */
04549 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
04550 {
04551   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
04552 }
04553
04554 /**
04555   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
04556   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04557   *       a timer instance provides a break input.
04558   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
04559   *         BDTR         OSSR          LL_TIM_SetOffStates
04560   * @param  TIMx Timer instance
04561   * @param  OffStateIdle This parameter can be one of the following values:
04562   *         @arg @ref LL_TIM_OSSI_DISABLE
04563   *         @arg @ref LL_TIM_OSSI_ENABLE
04564   * @param  OffStateRun This parameter can be one of the following values:
04565   *         @arg @ref LL_TIM_OSSR_DISABLE
04566   *         @arg @ref LL_TIM_OSSR_ENABLE
04567   * @retval None
04568   */
04569 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
04570 {
04571   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
04572 }
04573
04574 /**
04575   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
04576   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04577   *       a timer instance provides a break input.
04578   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
04579   * @param  TIMx Timer instance
04580   * @retval None
04581   */
04582 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
04583 {
04584   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
04585 }
04586
04587 /**
04588   * @brief  Disable automatic output (MOE can be set only by software).
04589   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04590   *       a timer instance provides a break input.
04591   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
04592   * @param  TIMx Timer instance
04593   * @retval None
04594   */
04595 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
04596 {
04597   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
04598 }
04599
04600 /**
04601   * @brief  Indicate whether automatic output is enabled.
04602   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04603   *       a timer instance provides a break input.
04604   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
04605   * @param  TIMx Timer instance
04606   * @retval State of bit (1 or 0).
04607   */
04608 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
04609 {
04610   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
04611 }
04612
04613 /**
04614   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
04615   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
04616   *       software and is reset in case of break or break2 event
04617   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04618   *       a timer instance provides a break input.
04619   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
04620   * @param  TIMx Timer instance
04621   * @retval None
04622   */
04623 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
04624 {
04625   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
04626 }
04627
04628 /**
04629   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
04630   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
04631   *       software and is reset in case of break or break2 event.
04632   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04633   *       a timer instance provides a break input.
04634   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
04635   * @param  TIMx Timer instance
04636   * @retval None
04637   */
04638 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
04639 {
04640   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
04641 }
04642
04643 /**
04644   * @brief  Indicates whether outputs are enabled.
04645   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04646   *       a timer instance provides a break input.
04647   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
04648   * @param  TIMx Timer instance
04649   * @retval State of bit (1 or 0).
04650   */
04651 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
04652 {
04653   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
04654 }
04655
04656 /**
04657   * @brief  Enable the signals connected to the designated timer break input.
04658   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
04659   *       or not a timer instance allows for break input selection.
04660   * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
04661   *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
04662   *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
04663   *         AF1          BKCMP3E       LL_TIM_EnableBreakInputSource\n
04664   *         AF1          BKCMP4E       LL_TIM_EnableBreakInputSource\n
04665   *         AF1          BKCMP5E       LL_TIM_EnableBreakInputSource\n
04666   *         AF1          BKCMP6E       LL_TIM_EnableBreakInputSource\n
04667   *         AF1          BKCMP7E       LL_TIM_EnableBreakInputSource\n
04668   *         AF2          BK2NE         LL_TIM_EnableBreakInputSource\n
04669   *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
04670   *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
04671   *         AF2          BK2CMP3E      LL_TIM_EnableBreakInputSource\n
04672   *         AF2          BK2CMP4E      LL_TIM_EnableBreakInputSource\n
04673   *         AF2          BK2CMP5E      LL_TIM_EnableBreakInputSource\n
04674   *         AF2          BK2CMP6E      LL_TIM_EnableBreakInputSource\n
04675   *         AF2          BK2CMP7E      LL_TIM_EnableBreakInputSource
04676   * @param  TIMx Timer instance
04677   * @param  BreakInput This parameter can be one of the following values:
04678   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
04679   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
04680   * @param  Source This parameter can be one of the following values:
04681   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
04682   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
04683   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
04684   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
04685   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
04686   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
04687   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
04688   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
04689   *
04690   *         (*)  Value not defined in all devices.
04691   * @retval None
04692   */
04693 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
04694 {
04695   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
04696   SET_BIT(*pReg, Source);
04697 }
04698
04699 /**
04700   * @brief  Disable the signals connected to the designated timer break input.
04701   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
04702   *       or not a timer instance allows for break input selection.
04703   * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
04704   *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
04705   *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
04706   *         AF1          BKCMP3E       LL_TIM_DisableBreakInputSource\n
04707   *         AF1          BKCMP4E       LL_TIM_DisableBreakInputSource\n
04708   *         AF1          BKCMP5E       LL_TIM_DisableBreakInputSource\n
04709   *         AF1          BKCMP6E       LL_TIM_DisableBreakInputSource\n
04710   *         AF1          BKCMP7E       LL_TIM_DisableBreakInputSource\n
04711   *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
04712   *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
04713   *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
04714   *         AF2          BK2CMP3E      LL_TIM_DisableBreakInputSource\n
04715   *         AF2          BK2CMP4E      LL_TIM_DisableBreakInputSource\n
04716   *         AF2          BK2CMP5E      LL_TIM_DisableBreakInputSource\n
04717   *         AF2          BK2CMP6E      LL_TIM_DisableBreakInputSource\n
04718   *         AF2          BK2CMP7E      LL_TIM_DisableBreakInputSource
04719   * @param  TIMx Timer instance
04720   * @param  BreakInput This parameter can be one of the following values:
04721   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
04722   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
04723   * @param  Source This parameter can be one of the following values:
04724   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
04725   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
04726   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
04727   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
04728   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
04729   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
04730   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
04731   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
04732   *
04733   *         (*)  Value not defined in all devices.
04734   * @retval None
04735   */
04736 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
04737 {
04738   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
04739   CLEAR_BIT(*pReg, Source);
04740 }
04741
04742 /**
04743   * @brief  Set the polarity of the break signal for the timer break input.
04744   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
04745   *       or not a timer instance allows for break input selection.
04746   * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
04747   *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
04748   *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
04749   *         AF1          BKCMP3P       LL_TIM_SetBreakInputSourcePolarity\n
04750   *         AF1          BKCMP4P       LL_TIM_SetBreakInputSourcePolarity\n
04751   *         AF1          BKCMP5P       LL_TIM_SetBreakInputSourcePolarity\n
04752   *         AF1          BKCMP6P       LL_TIM_SetBreakInputSourcePolarity\n
04753   *         AF1          BKCMP7P       LL_TIM_SetBreakInputSourcePolarity\n
04754   *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
04755   *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
04756   *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity\n
04757   *         AF2          BK2CMP3P      LL_TIM_SetBreakInputSourcePolarity\n
04758   *         AF2          BK2CMP4P      LL_TIM_SetBreakInputSourcePolarity\n
04759   *         AF2          BK2CMP5P      LL_TIM_SetBreakInputSourcePolarity\n
04760   *         AF2          BK2CMP6P      LL_TIM_SetBreakInputSourcePolarity\n
04761   *         AF2          BK2CMP7P      LL_TIM_SetBreakInputSourcePolarity
04762   * @param  TIMx Timer instance
04763   * @param  BreakInput This parameter can be one of the following values:
04764   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
04765   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
04766   * @param  Source This parameter can be one of the following values:
04767   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
04768   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
04769   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
04770   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
04771   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
04772   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
04773   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
04774   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
04775   * @param  Polarity This parameter can be one of the following values:
04776   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
04777   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
04778   *
04779   *         (*)  Value not defined in all devices.
04780   * @retval None
04781   */
04782 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
04783                                                         uint32_t Polarity)
04784 {
04785   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
04786   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
04787 }
04788 /**
04789   * @brief  Enable asymmetrical deadtime.
04790   * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
04791   *       a timer instance provides asymmetrical deadtime.
04792   * @rmtoll DTR2          DTAE          LL_TIM_EnableAsymmetricalDeadTime
04793   * @param  TIMx Timer instance
04794   * @retval None
04795   */
04796 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
04797 {
04798   SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
04799 }
04800
04801 /**
04802   * @brief  Disable asymmetrical dead-time.
04803   * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
04804   *       a timer instance provides asymmetrical deadtime.
04805   * @rmtoll DTR2          DTAE          LL_TIM_DisableAsymmetricalDeadTime
04806   * @param  TIMx Timer instance
04807   * @retval None
04808   */
04809 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
04810 {
04811   CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
04812 }
04813
04814 /**
04815   * @brief  Indicates whether asymmetrical deadtime is activated.
04816   * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
04817   *       a timer instance provides asymmetrical deadtime.
04818   * @rmtoll DTR2          DTAE          LL_TIM_IsEnabledAsymmetricalDeadTime
04819   * @param  TIMx Timer instance
04820   * @retval State of bit (1 or 0).
04821   */
04822 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
04823 {
04824   return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
04825 }
04826
04827 /**
04828   * @brief  Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
04829   *         rising edge of OCxN signals).
04830   * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
04831   *       asymmetrical dead-time insertion feature is supported by a timer instance.
04832   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
04833   * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
04834   *       (LOCK bits in TIMx_BDTR register).
04835   * @rmtoll DTR2         DTGF           LL_TIM_SetFallingDeadTime
04836   * @param  TIMx Timer instance
04837   * @param  DeadTime between Min_Data=0 and Max_Data=255
04838   * @retval None
04839   */
04840 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
04841 {
04842   MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
04843 }
04844
04845 /**
04846   * @brief  Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
04847   *         the rising edge of OCxN signals).
04848   * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
04849   *       asymmetrical dead-time insertion feature is supported by a timer instance.
04850   * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
04851   *       (LOCK bits in TIMx_BDTR register).
04852   * @rmtoll DTR2          DTGF           LL_TIM_GetFallingDeadTime
04853   * @param  TIMx Timer instance
04854   * @retval Returned value can be between Min_Data=0 and Max_Data=255:
04855   */
04856 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
04857 {
04858   return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
04859 }
04860
04861 /**
04862   * @brief  Enable deadtime preload.
04863   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04864   *       a timer instance provides deadtime preload.
04865   * @rmtoll DTR2          DTPE          LL_TIM_EnableDeadTimePreload
04866   * @param  TIMx Timer instance
04867   * @retval None
04868   */
04869 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
04870 {
04871   SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
04872 }
04873
04874 /**
04875   * @brief  Disable dead-time preload.
04876   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04877   *       a timer instance provides deadtime preload.
04878   * @rmtoll DTR2          DTPE          LL_TIM_DisableDeadTimePreload
04879   * @param  TIMx Timer instance
04880   * @retval None
04881   */
04882 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
04883 {
04884   CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
04885 }
04886
04887 /**
04888   * @brief  Indicates whether deadtime preload is activated.
04889   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
04890   *       a timer instance provides deadtime preload.
04891   * @rmtoll DTR2          DTPE          LL_TIM_IsEnabledDeadTimePreload
04892   * @param  TIMx Timer instance
04893   * @retval State of bit (1 or 0).
04894   */
04895 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
04896 {
04897   return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
04898 }
04899
04900 /**
04901   * @}
04902   */
04903
04904 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
04905   * @{
04906   */
04907 /**
04908   * @brief  Configures the timer DMA burst feature.
04909   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
04910   *       not a timer instance supports the DMA burst mode.
04911   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
04912   *         DCR          DBA           LL_TIM_ConfigDMABurst
04913   * @param  TIMx Timer instance
04914   * @param  DMABurstBaseAddress This parameter can be one of the following values:
04915   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
04916   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
04917   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
04918   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
04919   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
04920   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
04921   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
04922   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
04923   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
04924   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
04925   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
04926   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
04927   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
04928   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
04929   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
04930   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
04931   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
04932   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
04933   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
04934   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
04935   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
04936   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
04937   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
04938   *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
04939   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
04940   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
04941   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
04942   * @param  DMABurstLength This parameter can be one of the following values:
04943   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
04944   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
04945   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
04946   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
04947   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
04948   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
04949   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
04950   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
04951   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
04952   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
04953   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
04954   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
04955   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
04956   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
04957   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
04958   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
04959   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
04960   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
04961   *         @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
04962   *         @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
04963   *         @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
04964   *         @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
04965   *         @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
04966   *         @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
04967   *         @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
04968   *         @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
04969   * @retval None
04970   */
04971 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
04972 {
04973   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
04974 }
04975
04976 /**
04977   * @}
04978   */
04979
04980 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
04981   * @{
04982   */
04983
04984 /**
04985   * @brief  Enable encoder index.
04986   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
04987   *       a timer instance provides an index input.
04988   * @rmtoll ECR         IE           LL_TIM_EnableEncoderIndex
04989   * @param  TIMx Timer instance
04990   * @retval None
04991   */
04992 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
04993 {
04994   SET_BIT(TIMx->ECR, TIM_ECR_IE);
04995 }
04996
04997 /**
04998   * @brief  Disable encoder index.
04999   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05000   *       a timer instance provides an index input.
05001   * @rmtoll ECR         IE           LL_TIM_DisableEncoderIndex
05002   * @param  TIMx Timer instance
05003   * @retval None
05004   */
05005 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
05006 {
05007   CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
05008 }
05009
05010 /**
05011   * @brief  Indicate whether encoder index is enabled.
05012   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05013   *       a timer instance provides an index input.
05014   * @rmtoll ECR         IE           LL_TIM_IsEnabledEncoderIndex
05015   * @param  TIMx Timer instance
05016   * @retval State of bit (1 or 0).
05017   */
05018 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
05019 {
05020   return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
05021 }
05022
05023 /**
05024   * @brief  Set index direction
05025   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05026   *       a timer instance provides an index input.
05027   * @rmtoll ECR          IDIR           LL_TIM_SetIndexDirection
05028   * @param  TIMx Timer instance
05029   * @param  IndexDirection This parameter can be one of the following values:
05030   *         @arg @ref LL_TIM_INDEX_UP_DOWN
05031   *         @arg @ref LL_TIM_INDEX_UP
05032   *         @arg @ref LL_TIM_INDEX_DOWN
05033   * @retval None
05034   */
05035 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
05036 {
05037   MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
05038 }
05039
05040 /**
05041   * @brief  Get actual index direction
05042   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05043   *       a timer instance provides an index input.
05044   * @rmtoll ECR          IDIR           LL_TIM_GetIndexDirection
05045   * @param  TIMx Timer instance
05046   * @retval Returned value can be one of the following values:
05047   *         @arg @ref LL_TIM_INDEX_UP_DOWN
05048   *         @arg @ref LL_TIM_INDEX_UP
05049   *         @arg @ref LL_TIM_INDEX_DOWN
05050   */
05051 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
05052 {
05053   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
05054 }
05055
05056 /**
05057   * @brief  Enable first index.
05058   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05059   *       a timer instance provides an index input.
05060   * @rmtoll ECR          FIDX          LL_TIM_EnableFirstIndex
05061   * @param  TIMx Timer instance
05062   * @retval None
05063   */
05064 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
05065 {
05066   SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
05067 }
05068
05069 /**
05070   * @brief  Disable first index.
05071   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05072   *       a timer instance provides an index input.
05073   * @rmtoll ECR          FIDX          LL_TIM_DisableFirstIndex
05074   * @param  TIMx Timer instance
05075   * @retval None
05076   */
05077 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
05078 {
05079   CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
05080 }
05081
05082 /**
05083   * @brief  Indicates whether first index is enabled.
05084   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05085   *       a timer instance provides an index input.
05086   * @rmtoll ECR          FIDX          LL_TIM_IsEnabledFirstIndex
05087   * @param  TIMx Timer instance
05088   * @retval State of bit (1 or 0).
05089   */
05090 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
05091 {
05092   return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
05093 }
05094
05095 /**
05096   * @brief  Set index positioning
05097   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05098   *       a timer instance provides an index input.
05099   * @rmtoll ECR          IPOS           LL_TIM_SetIndexPositionning
05100   * @param  TIMx Timer instance
05101   * @param  IndexPositionning This parameter can be one of the following values:
05102   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
05103   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
05104   *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
05105   *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
05106   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
05107   *         @arg @ref LL_TIM_INDEX_POSITION_UP
05108   * @retval None
05109   */
05110 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
05111 {
05112   MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
05113 }
05114
05115 /**
05116   * @brief  Get actual index positioning
05117   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05118   *       a timer instance provides an index input.
05119   * @rmtoll ECR          IPOS           LL_TIM_GetIndexPositionning
05120   * @param  TIMx Timer instance
05121   * @retval Returned value can be one of the following values:
05122   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
05123   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
05124   *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
05125   *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
05126   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
05127   *         @arg @ref LL_TIM_INDEX_POSITION_UP
05128   */
05129 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
05130 {
05131   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
05132 }
05133
05134 /**
05135   * @brief  Configure encoder index.
05136   * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
05137   *       a timer instance provides an index input.
05138   * @rmtoll ECR          IDIR          LL_TIM_ConfigIDX\n
05139   *         ECR          FIDX          LL_TIM_ConfigIDX\n
05140   *         ECR          IPOS          LL_TIM_ConfigIDX
05141   * @param  TIMx Timer instance
05142   * @param  Configuration This parameter must be a combination of all the following values:
05143   *         @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
05144   *         @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
05145   *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
05146   * @retval None
05147   */
05148 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
05149 {
05150   MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
05151 }
05152
05153 /**
05154   * @}
05155   */
05156
05157 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
05158   * @{
05159   */
05160 /**
05161   * @brief  Remap TIM inputs (input channel, internal/external triggers).
05162   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
05163   *       a some timer inputs can be remapped.
05164   * @rmtoll TIM1_TISEL    TI1SEL      LL_TIM_SetRemap\n
05165   *         TIM2_TISEL    TI1SEL      LL_TIM_SetRemap\n
05166   *         TIM2_TISEL    TI2SEL      LL_TIM_SetRemap\n
05167   *         TIM2_TISEL    TI3SEL      LL_TIM_SetRemap\n
05168   *         TIM2_TISEL    TI4SEL      LL_TIM_SetRemap\n
05169   *         TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
05170   *         TIM3_TISEL    TI2SEL      LL_TIM_SetRemap\n
05171   *         TIM3_TISEL    TI3SEL      LL_TIM_SetRemap\n
05172   *         TIM4_TISEL    TI1SEL      LL_TIM_SetRemap\n
05173   *         TIM4_TISEL    TI2SEL      LL_TIM_SetRemap\n
05174   *         TIM4_TISEL    TI3SEL      LL_TIM_SetRemap\n
05175   *         TIM4_TISEL    TI4SEL      LL_TIM_SetRemap\n
05176   *         TIM5_TISEL    TI1SEL      LL_TIM_SetRemap\n
05177   *         TIM5_TISEL    TI2SEL      LL_TIM_SetRemap\n
05178   *         TIM8_TISEL    TI1SEL      LL_TIM_SetRemap\n
05179   *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
05180   *         TIM15_TISEL   TI2SEL      LL_TIM_SetRemap\n
05181   *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
05182   *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap\n
05183   *         TIM20_TISEL   TI1SEL      LL_TIM_SetRemap
05184   * @param  TIMx Timer instance
05185   * @param  Remap Remap param depends on the TIMx. Description available only
05186   *         in CHM version of the User Manual (not in .pdf).
05187   *         Otherwise see Reference Manual description of TISEL registers.
05188   *
05189   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
05190   *
05191   *         TIM1: one of the following values
05192   *
05193   *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
05194   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
05195   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
05196   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
05197   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
05198   *
05199   *         TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
05200   *
05201   *            . . TI1_RMP can be one of the following values
05202   *            @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
05203   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
05204   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
05205   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
05206   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
05207   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
05208   *
05209   *            . . TI2_RMP can be one of the following values
05210   *            @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
05211   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
05212   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
05213   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
05214   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
05215   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
05216   *
05217   *            . . TI3_RMP can be one of the following values
05218   *            @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
05219   *            @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
05220   *
05221   *            . . TI4_RMP can be one of the following values
05222   *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
05223   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
05224   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
05225   *
05226   *         TIM3: any combination of TI1_RMP and TI2_RMP where
05227   *
05228   *            . . TI1_RMP can be one of the following values
05229   *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
05230   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
05231   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
05232   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
05233   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
05234   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
05235   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
05236   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
05237   *
05238   *            . . TI2_RMP can be one of the following values
05239   *            @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
05240   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
05241   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
05242   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
05243   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
05244   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
05245   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
05246   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
05247   *
05248   *            . . TI3_RMP can be one of the following values
05249   *            @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
05250   *            @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
05251   *
05252   *         TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
05253   *
05254   *            . . TI1_RMP can be one of the following values
05255   *            @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
05256   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
05257   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
05258   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
05259   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
05260   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
05261   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
05262   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
05263   *
05264   *            . . TI2_RMP can be one of the following values
05265   *            @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
05266   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
05267   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
05268   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
05269   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
05270   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
05271   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
05272   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
05273   *
05274   *            . . TI3_RMP can be one of the following values
05275   *            @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
05276   *            @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
05277   *
05278   *            . . TI4_RMP can be one of the following values
05279   *            @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
05280   *            @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
05281   *
05282   *         TIM5: any combination of TI1_RMP and TI2_RMP where (**)
05283   *
05284   *            . . TI1_RMP can be one of the following values
05285   *            @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO   (*)
05286   *            @arg @ref LL_TIM_TIM5_TI1_RMP_LSI    (*)
05287   *            @arg @ref LL_TIM_TIM5_TI1_RMP_LSE    (*)
05288   *            @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
05289   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1  (*)
05290   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2  (*)
05291   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3  (*)
05292   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4  (*)
05293   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5  (*)
05294   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6  (*)
05295   *            @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7  (*)
05296   *
05297   *            . . TI2_RMP can be one of the following values
05298   *            @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO  (*)
05299   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
05300   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
05301   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
05302   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
05303   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
05304   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
05305   *            @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
05306   *
05307   *         TIM8: one of the following values
05308   *
05309   *            @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
05310   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
05311   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
05312   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
05313   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
05314   *
05315   *         TIM15: any combination of TI1_RMP and TI2_RMP where
05316   *
05317   *            . . TI1_RMP can be one of the following values
05318   *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
05319   *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
05320   *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
05321   *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
05322   *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
05323   *            @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
05324   *
05325   *            . . TI2_RMP can be one of the following values
05326   *            @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
05327   *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
05328   *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
05329   *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
05330   *            @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
05331   *
05332   *         TIM16: one of the following values
05333   *
05334   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
05335   *            @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
05336   *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
05337   *            @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
05338   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
05339   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
05340   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
05341   *
05342   *         TIM17: one of the following values
05343   *
05344   *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
05345   *            @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
05346   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
05347   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
05348   *            @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
05349   *            @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
05350   *            @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
05351   *
05352   *         TIM20: one of the following values (**)
05353   *
05354   *            @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO  (*)
05355   *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
05356   *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
05357   *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
05358   *            @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
05359   *
05360   *         (*)  Value not defined in all devices. \n
05361   *         (**) Register not available in all devices.
05362   *
05363   *
05364   * @retval None
05365   */
05366 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
05367 {
05368   MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
05369 }
05370
05371 /**
05372   * @brief  Enable request for HSE/32 clock used for TISEL remap.
05373   * @note Only TIM16 and TIM17 support HSE/32 remap
05374   * @rmtoll OR         HSE32EN           LL_TIM_EnableHSE32
05375   * @param  TIMx Timer instance
05376   * @retval None
05377   */
05378 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
05379 {
05380   SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
05381 }
05382
05383 /**
05384   * @brief  Disable request for HSE/32 clock used for TISEL remap.
05385   * @note Only TIM16 and TIM17 support HSE/32 remap
05386   * @rmtoll OR         HSE32EN           LL_TIM_DisableHSE32
05387   * @param  TIMx Timer instance
05388   * @retval None
05389   */
05390 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
05391 {
05392   CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
05393 }
05394
05395 /**
05396   * @brief  Indicate whether request for HSE/32 clock is enabled.
05397   * @note Only TIM16 and TIM17 support HSE/32 remap
05398   * @rmtoll OR         HSE32EN           LL_TIM_IsEnabledHSE32
05399   * @param  TIMx Timer instance
05400   * @retval State of bit (1 or 0).
05401   */
05402 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx)
05403 {
05404   return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
05405 }
05406
05407 /**
05408   * @}
05409   */
05410
05411 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
05412   * @{
05413   */
05414 /**
05415   * @brief  Set the OCREF clear input source
05416   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
05417   * @note This function can only be used in Output compare and PWM modes.
05418   * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
05419   *       or not a timer instance can configure OCREF clear input source.
05420   * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
05421   * @rmtoll AF2           OCRSEL              LL_TIM_SetOCRefClearInputSource
05422   * @param  TIMx Timer instance
05423   * @param  OCRefClearInputSource This parameter can be one of the following values:
05424   *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
05425   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
05426   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
05427   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
05428   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
05429   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
05430   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
05431   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
05432   *
05433   *         (*)  Value not defined in all devices. \n
05434   * @retval None
05435   */
05436 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
05437 {
05438   MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
05439              ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
05440   MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
05441 }
05442 /**
05443   * @}
05444   */
05445
05446 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
05447   * @{
05448   */
05449 /**
05450   * @brief  Clear the update interrupt flag (UIF).
05451   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
05452   * @param  TIMx Timer instance
05453   * @retval None
05454   */
05455 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
05456 {
05457   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
05458 }
05459
05460 /**
05461   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
05462   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
05463   * @param  TIMx Timer instance
05464   * @retval State of bit (1 or 0).
05465   */
05466 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
05467 {
05468   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
05469 }
05470
05471 /**
05472   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
05473   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
05474   * @param  TIMx Timer instance
05475   * @retval None
05476   */
05477 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
05478 {
05479   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
05480 }
05481
05482 /**
05483   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
05484   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
05485   * @param  TIMx Timer instance
05486   * @retval State of bit (1 or 0).
05487   */
05488 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
05489 {
05490   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
05491 }
05492
05493 /**
05494   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
05495   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
05496   * @param  TIMx Timer instance
05497   * @retval None
05498   */
05499 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
05500 {
05501   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
05502 }
05503
05504 /**
05505   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
05506   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
05507   * @param  TIMx Timer instance
05508   * @retval State of bit (1 or 0).
05509   */
05510 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
05511 {
05512   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
05513 }
05514
05515 /**
05516   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
05517   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
05518   * @param  TIMx Timer instance
05519   * @retval None
05520   */
05521 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
05522 {
05523   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
05524 }
05525
05526 /**
05527   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
05528   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
05529   * @param  TIMx Timer instance
05530   * @retval State of bit (1 or 0).
05531   */
05532 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
05533 {
05534   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
05535 }
05536
05537 /**
05538   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
05539   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
05540   * @param  TIMx Timer instance
05541   * @retval None
05542   */
05543 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
05544 {
05545   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
05546 }
05547
05548 /**
05549   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
05550   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
05551   * @param  TIMx Timer instance
05552   * @retval State of bit (1 or 0).
05553   */
05554 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
05555 {
05556   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
05557 }
05558
05559 /**
05560   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
05561   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
05562   * @param  TIMx Timer instance
05563   * @retval None
05564   */
05565 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
05566 {
05567   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
05568 }
05569
05570 /**
05571   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
05572   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
05573   * @param  TIMx Timer instance
05574   * @retval State of bit (1 or 0).
05575   */
05576 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
05577 {
05578   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
05579 }
05580
05581 /**
05582   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
05583   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
05584   * @param  TIMx Timer instance
05585   * @retval None
05586   */
05587 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
05588 {
05589   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
05590 }
05591
05592 /**
05593   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
05594   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
05595   * @param  TIMx Timer instance
05596   * @retval State of bit (1 or 0).
05597   */
05598 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
05599 {
05600   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
05601 }
05602
05603 /**
05604   * @brief  Clear the commutation interrupt flag (COMIF).
05605   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
05606   * @param  TIMx Timer instance
05607   * @retval None
05608   */
05609 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
05610 {
05611   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
05612 }
05613
05614 /**
05615   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
05616   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
05617   * @param  TIMx Timer instance
05618   * @retval State of bit (1 or 0).
05619   */
05620 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
05621 {
05622   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
05623 }
05624
05625 /**
05626   * @brief  Clear the trigger interrupt flag (TIF).
05627   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
05628   * @param  TIMx Timer instance
05629   * @retval None
05630   */
05631 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
05632 {
05633   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
05634 }
05635
05636 /**
05637   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
05638   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
05639   * @param  TIMx Timer instance
05640   * @retval State of bit (1 or 0).
05641   */
05642 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
05643 {
05644   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
05645 }
05646
05647 /**
05648   * @brief  Clear the break interrupt flag (BIF).
05649   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
05650   * @param  TIMx Timer instance
05651   * @retval None
05652   */
05653 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
05654 {
05655   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
05656 }
05657
05658 /**
05659   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
05660   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
05661   * @param  TIMx Timer instance
05662   * @retval State of bit (1 or 0).
05663   */
05664 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
05665 {
05666   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
05667 }
05668
05669 /**
05670   * @brief  Clear the break 2 interrupt flag (B2IF).
05671   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
05672   * @param  TIMx Timer instance
05673   * @retval None
05674   */
05675 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
05676 {
05677   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
05678 }
05679
05680 /**
05681   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
05682   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
05683   * @param  TIMx Timer instance
05684   * @retval State of bit (1 or 0).
05685   */
05686 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
05687 {
05688   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
05689 }
05690
05691 /**
05692   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
05693   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
05694   * @param  TIMx Timer instance
05695   * @retval None
05696   */
05697 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
05698 {
05699   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
05700 }
05701
05702 /**
05703   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
05704   *         (Capture/Compare 1 interrupt is pending).
05705   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
05706   * @param  TIMx Timer instance
05707   * @retval State of bit (1 or 0).
05708   */
05709 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
05710 {
05711   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
05712 }
05713
05714 /**
05715   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
05716   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
05717   * @param  TIMx Timer instance
05718   * @retval None
05719   */
05720 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
05721 {
05722   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
05723 }
05724
05725 /**
05726   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
05727   *         (Capture/Compare 2 over-capture interrupt is pending).
05728   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
05729   * @param  TIMx Timer instance
05730   * @retval State of bit (1 or 0).
05731   */
05732 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
05733 {
05734   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
05735 }
05736
05737 /**
05738   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
05739   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
05740   * @param  TIMx Timer instance
05741   * @retval None
05742   */
05743 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
05744 {
05745   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
05746 }
05747
05748 /**
05749   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
05750   *         (Capture/Compare 3 over-capture interrupt is pending).
05751   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
05752   * @param  TIMx Timer instance
05753   * @retval State of bit (1 or 0).
05754   */
05755 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
05756 {
05757   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
05758 }
05759
05760 /**
05761   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
05762   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
05763   * @param  TIMx Timer instance
05764   * @retval None
05765   */
05766 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
05767 {
05768   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
05769 }
05770
05771 /**
05772   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
05773   *         (Capture/Compare 4 over-capture interrupt is pending).
05774   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
05775   * @param  TIMx Timer instance
05776   * @retval State of bit (1 or 0).
05777   */
05778 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
05779 {
05780   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
05781 }
05782
05783 /**
05784   * @brief  Clear the system break interrupt flag (SBIF).
05785   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
05786   * @param  TIMx Timer instance
05787   * @retval None
05788   */
05789 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
05790 {
05791   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
05792 }
05793
05794 /**
05795   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
05796   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
05797   * @param  TIMx Timer instance
05798   * @retval State of bit (1 or 0).
05799   */
05800 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
05801 {
05802   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
05803 }
05804
05805 /**
05806   * @brief  Clear the transition error interrupt flag (TERRF).
05807   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
05808   *       a timer instance provides encoder error management.
05809   * @rmtoll SR           TERRF           LL_TIM_ClearFlag_TERR
05810   * @param  TIMx Timer instance
05811   * @retval None
05812   */
05813 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
05814 {
05815   WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
05816 }
05817
05818 /**
05819   * @brief  Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
05820   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
05821   *       a timer instance provides encoder error management.
05822   * @rmtoll SR           TERRF           LL_TIM_IsActiveFlag_TERR
05823   * @param  TIMx Timer instance
05824   * @retval State of bit (1 or 0).
05825   */
05826 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
05827 {
05828   return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
05829 }
05830
05831 /**
05832   * @brief  Clear the index error interrupt flag (IERRF).
05833   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
05834   *       a timer instance provides encoder error management.
05835   * @rmtoll SR           IERRF           LL_TIM_ClearFlag_IERR
05836   * @param  TIMx Timer instance
05837   * @retval None
05838   */
05839 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
05840 {
05841   WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
05842 }
05843
05844 /**
05845   * @brief  Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
05846   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
05847   *       a timer instance provides encoder error management.
05848   * @rmtoll SR           IERRF           LL_TIM_IsActiveFlag_IERR
05849   * @param  TIMx Timer instance
05850   * @retval State of bit (1 or 0).
05851   */
05852 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
05853 {
05854   return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
05855 }
05856
05857 /**
05858   * @brief  Clear the direction change interrupt flag (DIRF).
05859   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
05860   *       a timer instance provides encoder interrupt management.
05861   * @rmtoll SR           DIRF           LL_TIM_ClearFlag_DIR
05862   * @param  TIMx Timer instance
05863   * @retval None
05864   */
05865 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
05866 {
05867   WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
05868 }
05869
05870 /**
05871   * @brief  Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
05872   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
05873   *       a timer instance provides encoder interrupt management.
05874   * @rmtoll SR           DIRF           LL_TIM_IsActiveFlag_DIR
05875   * @param  TIMx Timer instance
05876   * @retval State of bit (1 or 0).
05877   */
05878 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
05879 {
05880   return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
05881 }
05882
05883 /**
05884   * @brief  Clear the index interrupt flag (IDXF).
05885   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
05886   *       a timer instance provides encoder interrupt management.
05887   * @rmtoll SR           IDXF           LL_TIM_ClearFlag_IDX
05888   * @param  TIMx Timer instance
05889   * @retval None
05890   */
05891 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
05892 {
05893   WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
05894 }
05895
05896 /**
05897   * @brief  Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
05898   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
05899   *       a timer instance provides encoder interrupt management.
05900   * @rmtoll SR           IDXF           LL_TIM_IsActiveFlag_IDX
05901   * @param  TIMx Timer instance
05902   * @retval State of bit (1 or 0).
05903   */
05904 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
05905 {
05906   return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
05907 }
05908 /**
05909   * @}
05910   */
05911
05912 /** @defgroup TIM_LL_EF_IT_Management IT-Management
05913   * @{
05914   */
05915 /**
05916   * @brief  Enable update interrupt (UIE).
05917   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
05918   * @param  TIMx Timer instance
05919   * @retval None
05920   */
05921 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
05922 {
05923   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
05924 }
05925
05926 /**
05927   * @brief  Disable update interrupt (UIE).
05928   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
05929   * @param  TIMx Timer instance
05930   * @retval None
05931   */
05932 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
05933 {
05934   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
05935 }
05936
05937 /**
05938   * @brief  Indicates whether the update interrupt (UIE) is enabled.
05939   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
05940   * @param  TIMx Timer instance
05941   * @retval State of bit (1 or 0).
05942   */
05943 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
05944 {
05945   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
05946 }
05947
05948 /**
05949   * @brief  Enable capture/compare 1 interrupt (CC1IE).
05950   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
05951   * @param  TIMx Timer instance
05952   * @retval None
05953   */
05954 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
05955 {
05956   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
05957 }
05958
05959 /**
05960   * @brief  Disable capture/compare 1  interrupt (CC1IE).
05961   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
05962   * @param  TIMx Timer instance
05963   * @retval None
05964   */
05965 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
05966 {
05967   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
05968 }
05969
05970 /**
05971   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
05972   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
05973   * @param  TIMx Timer instance
05974   * @retval State of bit (1 or 0).
05975   */
05976 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
05977 {
05978   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
05979 }
05980
05981 /**
05982   * @brief  Enable capture/compare 2 interrupt (CC2IE).
05983   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
05984   * @param  TIMx Timer instance
05985   * @retval None
05986   */
05987 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
05988 {
05989   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
05990 }
05991
05992 /**
05993   * @brief  Disable capture/compare 2  interrupt (CC2IE).
05994   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
05995   * @param  TIMx Timer instance
05996   * @retval None
05997   */
05998 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
05999 {
06000   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
06001 }
06002
06003 /**
06004   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
06005   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
06006   * @param  TIMx Timer instance
06007   * @retval State of bit (1 or 0).
06008   */
06009 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
06010 {
06011   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
06012 }
06013
06014 /**
06015   * @brief  Enable capture/compare 3 interrupt (CC3IE).
06016   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
06017   * @param  TIMx Timer instance
06018   * @retval None
06019   */
06020 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
06021 {
06022   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
06023 }
06024
06025 /**
06026   * @brief  Disable capture/compare 3  interrupt (CC3IE).
06027   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
06028   * @param  TIMx Timer instance
06029   * @retval None
06030   */
06031 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
06032 {
06033   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
06034 }
06035
06036 /**
06037   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
06038   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
06039   * @param  TIMx Timer instance
06040   * @retval State of bit (1 or 0).
06041   */
06042 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
06043 {
06044   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
06045 }
06046
06047 /**
06048   * @brief  Enable capture/compare 4 interrupt (CC4IE).
06049   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
06050   * @param  TIMx Timer instance
06051   * @retval None
06052   */
06053 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
06054 {
06055   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
06056 }
06057
06058 /**
06059   * @brief  Disable capture/compare 4  interrupt (CC4IE).
06060   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
06061   * @param  TIMx Timer instance
06062   * @retval None
06063   */
06064 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
06065 {
06066   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
06067 }
06068
06069 /**
06070   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
06071   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
06072   * @param  TIMx Timer instance
06073   * @retval State of bit (1 or 0).
06074   */
06075 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
06076 {
06077   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
06078 }
06079
06080 /**
06081   * @brief  Enable commutation interrupt (COMIE).
06082   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
06083   * @param  TIMx Timer instance
06084   * @retval None
06085   */
06086 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
06087 {
06088   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
06089 }
06090
06091 /**
06092   * @brief  Disable commutation interrupt (COMIE).
06093   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
06094   * @param  TIMx Timer instance
06095   * @retval None
06096   */
06097 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
06098 {
06099   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
06100 }
06101
06102 /**
06103   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
06104   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
06105   * @param  TIMx Timer instance
06106   * @retval State of bit (1 or 0).
06107   */
06108 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
06109 {
06110   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
06111 }
06112
06113 /**
06114   * @brief  Enable trigger interrupt (TIE).
06115   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
06116   * @param  TIMx Timer instance
06117   * @retval None
06118   */
06119 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
06120 {
06121   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
06122 }
06123
06124 /**
06125   * @brief  Disable trigger interrupt (TIE).
06126   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
06127   * @param  TIMx Timer instance
06128   * @retval None
06129   */
06130 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
06131 {
06132   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
06133 }
06134
06135 /**
06136   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
06137   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
06138   * @param  TIMx Timer instance
06139   * @retval State of bit (1 or 0).
06140   */
06141 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
06142 {
06143   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
06144 }
06145
06146 /**
06147   * @brief  Enable break interrupt (BIE).
06148   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
06149   * @param  TIMx Timer instance
06150   * @retval None
06151   */
06152 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
06153 {
06154   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
06155 }
06156
06157 /**
06158   * @brief  Disable break interrupt (BIE).
06159   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
06160   * @param  TIMx Timer instance
06161   * @retval None
06162   */
06163 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
06164 {
06165   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
06166 }
06167
06168 /**
06169   * @brief  Indicates whether the break interrupt (BIE) is enabled.
06170   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
06171   * @param  TIMx Timer instance
06172   * @retval State of bit (1 or 0).
06173   */
06174 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
06175 {
06176   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
06177 }
06178
06179 /**
06180   * @brief  Enable transition error interrupt (TERRIE).
06181   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06182   *       a timer instance provides encoder error management.
06183   * @rmtoll DIER         TERRIE           LL_TIM_EnableIT_TERR
06184   * @param  TIMx Timer instance
06185   * @retval None
06186   */
06187 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
06188 {
06189   SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
06190 }
06191
06192 /**
06193   * @brief  Disable transition error interrupt (TERRIE).
06194   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06195   *       a timer instance provides encoder error management.
06196   * @rmtoll DIER         TERRIE           LL_TIM_DisableIT_TERR
06197   * @param  TIMx Timer instance
06198   * @retval None
06199   */
06200 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
06201 {
06202   CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
06203 }
06204
06205 /**
06206   * @brief  Indicates whether the transition error interrupt (TERRIE) is enabled.
06207   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06208   *       a timer instance provides encoder error management.
06209   * @rmtoll DIER         TERRIE           LL_TIM_IsEnabledIT_TERR
06210   * @param  TIMx Timer instance
06211   * @retval State of bit (1 or 0).
06212   */
06213 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
06214 {
06215   return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
06216 }
06217
06218 /**
06219   * @brief  Enable index error interrupt (IERRIE).
06220   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06221   *       a timer instance provides encoder error management.
06222   * @rmtoll DIER         IERRIE           LL_TIM_EnableIT_IERR
06223   * @param  TIMx Timer instance
06224   * @retval None
06225   */
06226 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
06227 {
06228   SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
06229 }
06230
06231 /**
06232   * @brief  Disable index error interrupt (IERRIE).
06233   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06234   *       a timer instance provides encoder error management.
06235   * @rmtoll DIER         IERRIE           LL_TIM_DisableIT_IERR
06236   * @param  TIMx Timer instance
06237   * @retval None
06238   */
06239 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
06240 {
06241   CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
06242 }
06243
06244 /**
06245   * @brief  Indicates whether the index error interrupt (IERRIE) is enabled.
06246   * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
06247   *       a timer instance provides encoder error management.
06248   * @rmtoll DIER         IERRIE           LL_TIM_IsEnabledIT_IERR
06249   * @param  TIMx Timer instance
06250   * @retval State of bit (1 or 0).
06251   */
06252 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
06253 {
06254   return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
06255 }
06256
06257 /**
06258   * @brief  Enable direction change interrupt (DIRIE).
06259   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06260   *       a timer instance provides encoder interrupt management.
06261   * @rmtoll DIER         DIRIE           LL_TIM_EnableIT_DIR
06262   * @param  TIMx Timer instance
06263   * @retval None
06264   */
06265 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
06266 {
06267   SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
06268 }
06269
06270 /**
06271   * @brief  Disable direction change interrupt (DIRIE).
06272   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06273   *       a timer instance provides encoder interrupt management.
06274   * @rmtoll DIER         DIRIE           LL_TIM_DisableIT_DIR
06275   * @param  TIMx Timer instance
06276   * @retval None
06277   */
06278 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
06279 {
06280   CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
06281 }
06282
06283 /**
06284   * @brief  Indicates whether the direction change interrupt (DIRIE) is enabled.
06285   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06286   *       a timer instance provides encoder interrupt management.
06287   * @rmtoll DIER         DIRIE           LL_TIM_IsEnabledIT_DIR
06288   * @param  TIMx Timer instance
06289   * @retval State of bit (1 or 0).
06290   */
06291 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
06292 {
06293   return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
06294 }
06295
06296 /**
06297   * @brief  Enable index interrupt (IDXIE).
06298   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06299   *       a timer instance provides encoder interrupt management.
06300   * @rmtoll DIER         IDXIE           LL_TIM_EnableIT_IDX
06301   * @param  TIMx Timer instance
06302   * @retval None
06303   */
06304 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
06305 {
06306   SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
06307 }
06308
06309 /**
06310   * @brief  Disable index interrupt (IDXIE).
06311   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06312   *       a timer instance provides encoder interrupt management.
06313   * @rmtoll DIER         IDXIE           LL_TIM_DisableIT_IDX
06314   * @param  TIMx Timer instance
06315   * @retval None
06316   */
06317 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
06318 {
06319   CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
06320 }
06321
06322 /**
06323   * @brief  Indicates whether the index interrupt (IDXIE) is enabled.
06324   * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
06325   *       a timer instance provides encoder interrupt management.
06326   * @rmtoll DIER         IDXIE           LL_TIM_IsEnabledIT_IDX
06327   * @param  TIMx Timer instance
06328   * @retval State of bit (1 or 0).
06329   */
06330 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
06331 {
06332   return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
06333 }
06334
06335 /**
06336   * @}
06337   */
06338
06339 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
06340   * @{
06341   */
06342 /**
06343   * @brief  Enable update DMA request (UDE).
06344   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
06345   * @param  TIMx Timer instance
06346   * @retval None
06347   */
06348 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
06349 {
06350   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
06351 }
06352
06353 /**
06354   * @brief  Disable update DMA request (UDE).
06355   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
06356   * @param  TIMx Timer instance
06357   * @retval None
06358   */
06359 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
06360 {
06361   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
06362 }
06363
06364 /**
06365   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
06366   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
06367   * @param  TIMx Timer instance
06368   * @retval State of bit (1 or 0).
06369   */
06370 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
06371 {
06372   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
06373 }
06374
06375 /**
06376   * @brief  Enable capture/compare 1 DMA request (CC1DE).
06377   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
06378   * @param  TIMx Timer instance
06379   * @retval None
06380   */
06381 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
06382 {
06383   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
06384 }
06385
06386 /**
06387   * @brief  Disable capture/compare 1  DMA request (CC1DE).
06388   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
06389   * @param  TIMx Timer instance
06390   * @retval None
06391   */
06392 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
06393 {
06394   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
06395 }
06396
06397 /**
06398   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
06399   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
06400   * @param  TIMx Timer instance
06401   * @retval State of bit (1 or 0).
06402   */
06403 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
06404 {
06405   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
06406 }
06407
06408 /**
06409   * @brief  Enable capture/compare 2 DMA request (CC2DE).
06410   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
06411   * @param  TIMx Timer instance
06412   * @retval None
06413   */
06414 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
06415 {
06416   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
06417 }
06418
06419 /**
06420   * @brief  Disable capture/compare 2  DMA request (CC2DE).
06421   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
06422   * @param  TIMx Timer instance
06423   * @retval None
06424   */
06425 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
06426 {
06427   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
06428 }
06429
06430 /**
06431   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
06432   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
06433   * @param  TIMx Timer instance
06434   * @retval State of bit (1 or 0).
06435   */
06436 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
06437 {
06438   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
06439 }
06440
06441 /**
06442   * @brief  Enable capture/compare 3 DMA request (CC3DE).
06443   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
06444   * @param  TIMx Timer instance
06445   * @retval None
06446   */
06447 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
06448 {
06449   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
06450 }
06451
06452 /**
06453   * @brief  Disable capture/compare 3  DMA request (CC3DE).
06454   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
06455   * @param  TIMx Timer instance
06456   * @retval None
06457   */
06458 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
06459 {
06460   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
06461 }
06462
06463 /**
06464   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
06465   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
06466   * @param  TIMx Timer instance
06467   * @retval State of bit (1 or 0).
06468   */
06469 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
06470 {
06471   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
06472 }
06473
06474 /**
06475   * @brief  Enable capture/compare 4 DMA request (CC4DE).
06476   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
06477   * @param  TIMx Timer instance
06478   * @retval None
06479   */
06480 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
06481 {
06482   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
06483 }
06484
06485 /**
06486   * @brief  Disable capture/compare 4  DMA request (CC4DE).
06487   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
06488   * @param  TIMx Timer instance
06489   * @retval None
06490   */
06491 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
06492 {
06493   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
06494 }
06495
06496 /**
06497   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
06498   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
06499   * @param  TIMx Timer instance
06500   * @retval State of bit (1 or 0).
06501   */
06502 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
06503 {
06504   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
06505 }
06506
06507 /**
06508   * @brief  Enable commutation DMA request (COMDE).
06509   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
06510   * @param  TIMx Timer instance
06511   * @retval None
06512   */
06513 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
06514 {
06515   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
06516 }
06517
06518 /**
06519   * @brief  Disable commutation DMA request (COMDE).
06520   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
06521   * @param  TIMx Timer instance
06522   * @retval None
06523   */
06524 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
06525 {
06526   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
06527 }
06528
06529 /**
06530   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
06531   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
06532   * @param  TIMx Timer instance
06533   * @retval State of bit (1 or 0).
06534   */
06535 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
06536 {
06537   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
06538 }
06539
06540 /**
06541   * @brief  Enable trigger interrupt (TDE).
06542   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
06543   * @param  TIMx Timer instance
06544   * @retval None
06545   */
06546 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
06547 {
06548   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
06549 }
06550
06551 /**
06552   * @brief  Disable trigger interrupt (TDE).
06553   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
06554   * @param  TIMx Timer instance
06555   * @retval None
06556   */
06557 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
06558 {
06559   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
06560 }
06561
06562 /**
06563   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
06564   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
06565   * @param  TIMx Timer instance
06566   * @retval State of bit (1 or 0).
06567   */
06568 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
06569 {
06570   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
06571 }
06572
06573 /**
06574   * @}
06575   */
06576
06577 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
06578   * @{
06579   */
06580 /**
06581   * @brief  Generate an update event.
06582   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
06583   * @param  TIMx Timer instance
06584   * @retval None
06585   */
06586 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
06587 {
06588   SET_BIT(TIMx->EGR, TIM_EGR_UG);
06589 }
06590
06591 /**
06592   * @brief  Generate Capture/Compare 1 event.
06593   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
06594   * @param  TIMx Timer instance
06595   * @retval None
06596   */
06597 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
06598 {
06599   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
06600 }
06601
06602 /**
06603   * @brief  Generate Capture/Compare 2 event.
06604   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
06605   * @param  TIMx Timer instance
06606   * @retval None
06607   */
06608 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
06609 {
06610   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
06611 }
06612
06613 /**
06614   * @brief  Generate Capture/Compare 3 event.
06615   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
06616   * @param  TIMx Timer instance
06617   * @retval None
06618   */
06619 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
06620 {
06621   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
06622 }
06623
06624 /**
06625   * @brief  Generate Capture/Compare 4 event.
06626   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
06627   * @param  TIMx Timer instance
06628   * @retval None
06629   */
06630 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
06631 {
06632   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
06633 }
06634
06635 /**
06636   * @brief  Generate commutation event.
06637   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
06638   * @param  TIMx Timer instance
06639   * @retval None
06640   */
06641 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
06642 {
06643   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
06644 }
06645
06646 /**
06647   * @brief  Generate trigger event.
06648   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
06649   * @param  TIMx Timer instance
06650   * @retval None
06651   */
06652 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
06653 {
06654   SET_BIT(TIMx->EGR, TIM_EGR_TG);
06655 }
06656
06657 /**
06658   * @brief  Generate break event.
06659   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
06660   * @param  TIMx Timer instance
06661   * @retval None
06662   */
06663 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
06664 {
06665   SET_BIT(TIMx->EGR, TIM_EGR_BG);
06666 }
06667
06668 /**
06669   * @brief  Generate break 2 event.
06670   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
06671   * @param  TIMx Timer instance
06672   * @retval None
06673   */
06674 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
06675 {
06676   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
06677 }
06678
06679 /**
06680   * @}
06681   */
06682
06683 #if defined(USE_FULL_LL_DRIVER)
06684 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
06685   * @{
06686   */
06687
06688 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
06689 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
06690 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
06691 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
06692 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
06693 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
06694 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
06695 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
06696 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
06697 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
06698 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
06699 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
06700 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
06701 /**
06702   * @}
06703   */
06704 #endif /* USE_FULL_LL_DRIVER */
06705
06706 /**
06707   * @}
06708   */
06709
06710 /**
06711   * @}
06712   */
06713
06714 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
06715
06716 /**
06717   * @}
06718   */
06719
06720 #ifdef __cplusplus
06721 }
06722 #endif
06723
06724 #endif /* __STM32G4xx_LL_TIM_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_ucpd.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_ucpd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_ucpd.c
00004   * @author  MCD Application Team
00005   * @brief   UCPD LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_ucpd.h"
00022 #include "stm32g4xx_ll_bus.h"
00023 #include "stm32g4xx_ll_rcc.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32G4xx_LL_Driver
00032   * @{
00033   */
00034 #if defined (UCPD1)
00035 /** @addtogroup UCPD_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /* Private macros ------------------------------------------------------------*/
00052 /** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
00053   * @{
00054   */
00055
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Private function prototypes -----------------------------------------------*/
00062
00063 /* Exported functions --------------------------------------------------------*/
00064 /** @addtogroup UCPD_LL_Exported_Functions
00065   * @{
00066   */
00067
00068 /** @addtogroup UCPD_LL_EF_Init
00069   * @{
00070   */
00071
00072 /**
00073   * @brief  De-initialize the UCPD registers to their default reset values.
00074   * @param  UCPDx ucpd Instance
00075   * @retval An ErrorStatus enumeration value:
00076   *          - SUCCESS: ucpd registers are de-initialized
00077   *          - ERROR: ucpd registers are not de-initialized
00078   */
00079 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
00080 {
00081   ErrorStatus status = ERROR;
00082
00083   /* Check the parameters */
00084   assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
00085
00086   LL_UCPD_Disable(UCPDx);
00087
00088   if (UCPD1 == UCPDx)
00089   {
00090     /* Force reset of ucpd clock */
00091     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1);
00092
00093     /* Release reset of ucpd clock */
00094     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1);
00095
00096     /* Disable ucpd clock */
00097     LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1);
00098
00099     status = SUCCESS;
00100   }
00101
00102   return status;
00103 }
00104
00105 /**
00106   * @brief  Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
00107   * @note   As some bits in ucpd configuration registers can only be written when the ucpd is disabled
00108   *         (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function.
00109   *         Otherwise, ERROR result will be returned.
00110   * @param  UCPDx UCPD Instance
00111   * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
00112   *         the configuration information for the UCPD peripheral.
00113   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00114   */
00115 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
00116 {
00117   /* Check the ucpd Instance UCPDx*/
00118   assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
00119
00120   if (UCPD1 == UCPDx)
00121   {
00122     LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1);
00123   }
00124
00125
00126   LL_UCPD_Disable(UCPDx);
00127
00128   /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
00129   MODIFY_REG(UCPDx->CFG1,
00130              UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
00131              UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin  << UCPD_CFG1_TRANSWIN_Pos) |
00132              (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
00133
00134   return SUCCESS;
00135 }
00136
00137 /**
00138   * @brief  Set each @ref LL_UCPD_InitTypeDef field to default value.
00139   * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
00140   *         whose fields will be set to default values.
00141   * @retval None
00142   */
00143 void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
00144 {
00145   /* Set UCPD_InitStruct fields to default values */
00146   UCPD_InitStruct->psc_ucpdclk  = LL_UCPD_PSC_DIV2;
00147   UCPD_InitStruct->transwin     = 0x7;   /* Divide by 8                     */
00148   UCPD_InitStruct->IfrGap       = 0x10;  /* Divide by 17                    */
00149   UCPD_InitStruct->HbitClockDiv = 0x0D;  /* Divide by 14 to produce HBITCLK */
00150 }
00151
00152 /**
00153   * @}
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /**
00161   * @}
00162   */
00163 #endif /* defined (UCPD1) */
00164 /**
00165   * @}
00166   */
00167
00168 #endif /* USE_FULL_LL_DRIVER */
00169
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_ucpd.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_ucpd.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_ucpd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UCPD LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_UCPD_H
00021 #define STM32G4xx_LL_UCPD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (UCPD1)
00035
00036 /** @defgroup UCPD_LL UCPD
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  UCPD Init structures definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t psc_ucpdclk;         /*!< Specify the prescaler for the UCPD clock.
00056                                      This parameter can be a value of @ref UCPD_LL_EC_PSC.
00057                                      This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
00058                                 */
00059
00060   uint32_t transwin;            /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
00061                                    to achieve a legal tTransitionWindow (set according to peripheral clock to define
00062                                     an interval of between 12 and 20 us).
00063                                     This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
00064                                     This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
00065                                 */
00066
00067   uint32_t IfrGap;              /*!< Specify the definition of the clock divider (minus 1) in order to generate
00068                                     tInterframeGap from the peripheral clock.
00069                                     This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
00070                                     This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
00071                                 */
00072
00073   uint32_t HbitClockDiv;        /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
00074                                      e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
00075                                      "UCPD1_CLK".
00076                                      This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
00077                                      This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
00078                                 */
00079
00080 } LL_UCPD_InitTypeDef;
00081
00082 /**
00083   * @}
00084   */
00085 #endif /* USE_FULL_LL_DRIVER */
00086
00087 /* Exported constants --------------------------------------------------------*/
00088 /** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
00089   * @{
00090   */
00091
00092 /** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
00093   * @brief    Flags defines which can be used with LL_ucpd_ReadReg function
00094   * @{
00095   */
00096 #define LL_UCPD_SR_TXIS             UCPD_SR_TXIS                  /*!< Transmit interrupt status                      */
00097 #define LL_UCPD_SR_TXMSGDISC        UCPD_SR_TXMSGDISC             /*!< Transmit message discarded interrupt           */
00098 #define LL_UCPD_SR_TXMSGSENT        UCPD_SR_TXMSGSENT             /*!< Transmit message sent interrupt                */
00099 #define LL_UCPD_SR_TXMSGABT         UCPD_SR_TXMSGABT              /*!< Transmit message abort interrupt               */
00100 #define LL_UCPD_SR_HRSTDISC         UCPD_SR_HRSTDISC              /*!< HRST discarded interrupt                       */
00101 #define LL_UCPD_SR_HRSTSENT         UCPD_SR_HRSTSENT              /*!< HRST sent interrupt                            */
00102 #define LL_UCPD_SR_TXUND            UCPD_SR_TXUND                 /*!< Tx data underrun condition interrupt           */
00103 #define LL_UCPD_SR_RXNE             UCPD_SR_RXNE                  /*!< Receive data register not empty interrupt      */
00104 #define LL_UCPD_SR_RXORDDET         UCPD_SR_RXORDDET              /*!< Rx ordered set (4 K-codes) detected interrupt  */
00105 #define LL_UCPD_SR_RXHRSTDET        UCPD_SR_RXHRSTDET             /*!< Rx Hard Reset detect interrupt                 */
00106 #define LL_UCPD_SR_RXOVR            UCPD_SR_RXOVR                 /*!< Rx data overflow interrupt                     */
00107 #define LL_UCPD_SR_RXMSGEND         UCPD_SR_RXMSGEND              /*!< Rx message received                            */
00108 #define LL_UCPD_SR_RXERR            UCPD_SR_RXERR                 /*!< Rx error                                       */
00109 #define LL_UCPD_SR_TYPECEVT1        UCPD_SR_TYPECEVT1             /*!< Type C voltage level event on CC1              */
00110 #define LL_UCPD_SR_TYPECEVT2        UCPD_SR_TYPECEVT2             /*!< Type C voltage level event on CC2              */
00111 #define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1      /*!<Status of DC level on CC1 pin                   */
00112 #define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2      /*!<Status of DC level on CC2 pin                   */
00113 #define LL_UCPD_SR_FRSEVT           UCPD_SR_FRSEVT                /*!<Fast Role Swap detection event                  */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup UCPD_LL_EC_IT IT Defines
00120   * @brief    IT defines which can be used with LL_UCPD_ReadReg and  LL_UCPD_WriteReg functions
00121   * @{
00122   */
00123 #define LL_UCPD_IMR_TXIS             UCPD_IMR_TXISIE              /*!< Enable transmit interrupt status                     */
00124 #define LL_UCPD_IMR_TXMSGDISC        UCPD_IMR_TXMSGDISCIE         /*!< Enable transmit message discarded interrupt          */
00125 #define LL_UCPD_IMR_TXMSGSENT        UCPD_IMR_TXMSGSENTIE         /*!< Enable transmit message sent interrupt               */
00126 #define LL_UCPD_IMR_TXMSGABT         UCPD_IMR_TXMSGABTIE          /*!< Enable transmit message abort interrupt              */
00127 #define LL_UCPD_IMR_HRSTDISC         UCPD_IMR_HRSTDISCIE          /*!< Enable HRST discarded interrupt                      */
00128 #define LL_UCPD_IMR_HRSTSENT         UCPD_IMR_HRSTSENTIE          /*!< Enable HRST sent interrupt                           */
00129 #define LL_UCPD_IMR_TXUND            UCPD_IMR_TXUNDIE             /*!< Enable tx data underrun condition interrupt          */
00130 #define LL_UCPD_IMR_RXNE             UCPD_IMR_RXNEIE              /*!< Enable Receive data register not empty interrupt     */
00131 #define LL_UCPD_IMR_RXORDDET         UCPD_IMR_RXORDDETIE          /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
00132 #define LL_UCPD_IMR_RXHRSTDET        UCPD_IMR_RXHRSTDETIE         /*!< Enable Rx Hard Reset detect interrupt                */
00133 #define LL_UCPD_IMR_RXOVR            UCPD_IMR_RXOVRIE             /*!< Enable Rx data overflow interrupt                    */
00134 #define LL_UCPD_IMR_RXMSGEND         UCPD_IMR_RXMSGENDIE          /*!< Enable Rx message received                           */
00135 #define LL_UCPD_IMR_TYPECEVT1        UCPD_IMR_TYPECEVT1IE         /*!< Enable Type C voltage level event on CC1             */
00136 #define LL_UCPD_IMR_TYPECEVT2        UCPD_IMR_TYPECEVT2IE         /*!< Enable Type C voltage level event on CC2             */
00137 #define LL_UCPD_IMR_FRSEVT           UCPD_IMR_FRSEVTIE            /*!< Enable fast Role Swap detection event                */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
00144   * @brief    definition of the usual Ordered sets
00145   * @{
00146   */
00147 #define LL_UCPD_SYNC1 0x18u                                       /*!< K-code for Startsynch #1                             */
00148 #define LL_UCPD_SYNC2 0x11u                                       /*!< K-code for Startsynch #2                             */
00149 #define LL_UCPD_SYNC3 0x06u                                       /*!< K-code for Startsynch #3                             */
00150 #define LL_UCPD_RST1  0x07u                                       /*!< K-code for Hard Reset #1                             */
00151 #define LL_UCPD_RST2  0x19u                                       /*!< K-code for Hard Reset #2                             */
00152 #define LL_UCPD_EOP   0x0Du                                       /*!< K-code for EOP End of Packet                         */
00153
00154 #define LL_UCPD_ORDERED_SET_SOP         (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding         */
00155 #define LL_UCPD_ORDERED_SET_SOP1        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding        */
00156 #define LL_UCPD_ORDERED_SET_SOP2        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding       */
00157 #define LL_UCPD_ORDERED_SET_HARD_RESET  (LL_UCPD_RST1  | (LL_UCPD_RST1<<5u)  | (LL_UCPD_RST1<<10u)  | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding  */
00158 #define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1  | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
00159 #define LL_UCPD_ORDERED_SET_SOP1_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_RST2<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding  */
00160 #define LL_UCPD_ORDERED_SET_SOP2_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup UCPD_LL_EC_MODE Role Mode
00166   * @{
00167   */
00168 #define LL_UCPD_ROLE_SNK             UCPD_CR_ANAMODE              /*!< Mode SNK Rd                                    */
00169 #define LL_UCPD_ROLE_SRC             0x0U                         /*!< Mode SRC Rp                                    */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup UCPD_LL_EC_RESISTOR Resistor value
00175   * @{
00176   */
00177 #define LL_UCPD_RESISTOR_DEFAULT    UCPD_CR_ANASUBMODE_0          /*!< Rp default                                     */
00178 #define LL_UCPD_RESISTOR_1_5A       UCPD_CR_ANASUBMODE_1          /*!< Rp 1.5 A                                       */
00179 #define LL_UCPD_RESISTOR_3_0A       UCPD_CR_ANASUBMODE            /*!< Rp 3.0 A                                       */
00180 #define LL_UCPD_RESISTOR_NONE       0x0U                          /*!< No resistor                                    */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
00186   * @{
00187   */
00188 #define LL_UCPD_ORDERSET_SOP         UCPD_CFG1_RXORDSETEN_0       /*!< SOP Ordered set detection enabled              */
00189 #define LL_UCPD_ORDERSET_SOP1        UCPD_CFG1_RXORDSETEN_1       /*!< SOP' Ordered set detection enabled             */
00190 #define LL_UCPD_ORDERSET_SOP2        UCPD_CFG1_RXORDSETEN_2       /*!< SOP'' Ordered set detection enabled            */
00191 #define LL_UCPD_ORDERSET_HARDRST     UCPD_CFG1_RXORDSETEN_3       /*!< Hard Reset Ordered set detection enabled       */
00192 #define LL_UCPD_ORDERSET_CABLERST    UCPD_CFG1_RXORDSETEN_4       /*!< Cable Reset Ordered set detection enabled      */
00193 #define LL_UCPD_ORDERSET_SOP1_DEBUG  UCPD_CFG1_RXORDSETEN_5       /*!< SOP' Debug Ordered set detection enabled       */
00194 #define LL_UCPD_ORDERSET_SOP2_DEBUG  UCPD_CFG1_RXORDSETEN_6       /*!< SOP'' Debug Ordered set detection enabled      */
00195 #define LL_UCPD_ORDERSET_SOP_EXT1    UCPD_CFG1_RXORDSETEN_7       /*!< SOP extension#1 Ordered set detection enabled  */
00196 #define LL_UCPD_ORDERSET_SOP_EXT2    UCPD_CFG1_RXORDSETEN_8       /*!< SOP extension#2 Ordered set detection enabled  */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup UCPD_LL_EC_CCxEVT  CCx event
00202   * @{
00203   */
00204 #define LL_UCPD_SNK_CC1_VOPEN      0x00u                                                      /*!< CC1 Sink Open state              */
00205 #define LL_UCPD_SNK_CC1_VRP        UCPD_SR_TYPEC_VSTATE_CC1_0                                 /*!< CC1 Sink vRP default state       */
00206 #define LL_UCPD_SNK_CC1_VRP15A     UCPD_SR_TYPEC_VSTATE_CC1_1                                 /*!< CC1 Sink vRP 1.5A state          */
00207 #define LL_UCPD_SNK_CC1_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)  /*!< CC1 Sink vRP 3.0A state          */
00208
00209 #define LL_UCPD_SNK_CC2_VOPEN      0x00u                                                      /*!< CC2 Sink Open state              */
00210 #define LL_UCPD_SNK_CC2_VRP        UCPD_SR_TYPEC_VSTATE_CC2_0                                 /*!< CC2 Sink vRP default state       */
00211 #define LL_UCPD_SNK_CC2_VRP15A     UCPD_SR_TYPEC_VSTATE_CC2_1                                 /*!< CC2 Sink vRP 1.5A state          */
00212 #define LL_UCPD_SNK_CC2_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)  /*!< CC2 Sink vRP 3.0A state          */
00213
00214 #define LL_UCPD_SRC_CC1_VRA        0x0U                                                      /*!< CC1 Source vRA state              */
00215 #define LL_UCPD_SRC_CC1_VRD        UCPD_SR_TYPEC_VSTATE_CC1_0                                /*!< CC1 Source vRD state              */
00216 #define LL_UCPD_SRC_CC1_OPEN       UCPD_SR_TYPEC_VSTATE_CC1_1                                /*!< CC1 Source Open state             */
00217
00218 #define LL_UCPD_SRC_CC2_VRA        0x0U                                                      /*!< CC2 Source vRA state              */
00219 #define LL_UCPD_SRC_CC2_VRD        UCPD_SR_TYPEC_VSTATE_CC2_0                                /*!< CC2 Source vRD state              */
00220 #define LL_UCPD_SRC_CC2_OPEN       UCPD_SR_TYPEC_VSTATE_CC2_1                                /*!< CC2 Source Open state             */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
00226   * @{
00227   */
00228 #define LL_UCPD_PSC_DIV1            0x0u                                                     /*!< Bypass pre-scaling / divide by 1  */
00229 #define LL_UCPD_PSC_DIV2            UCPD_CFG1_PSC_UCPDCLK_0                                  /*!< Pre-scale clock by dividing by 2  */
00230 #define LL_UCPD_PSC_DIV4            UCPD_CFG1_PSC_UCPDCLK_1                                  /*!< Pre-scale clock by dividing by 4  */
00231 #define LL_UCPD_PSC_DIV8            (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)      /*!< Pre-scale clock by dividing by 8  */
00232 #define LL_UCPD_PSC_DIV16           UCPD_CFG1_PSC_UCPDCLK_2                                  /*!< Pre-scale clock by dividing by 16 */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
00238   * @{
00239   */
00240 #define LL_UCPD_CCENABLE_NONE       0x0U                                                     /*!< Neither PHY is activated (e.g. disabled state of source)          */
00241 #define LL_UCPD_CCENABLE_CC1        UCPD_CR_CCENABLE_0                                       /*!< Controls apply to only CC1                                        */
00242 #define LL_UCPD_CCENABLE_CC2        UCPD_CR_CCENABLE_1                                       /*!< Controls apply to only CC1                                        */
00243 #define LL_UCPD_CCENABLE_CC1CC2     (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)                /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup UCPD_LL_EC_CCPIN CC pin selection
00249   * @{
00250   */
00251 #define LL_UCPD_CCPIN_CC1           0x0U                    /*!< Use CC1 IO for power delivery communication              */
00252 #define LL_UCPD_CCPIN_CC2           UCPD_CR_PHYCCSEL        /*!< Use CC2 IO for power delivery communication              */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup UCPD_LL_EC_RXMODE Receiver mode
00258   * @{
00259   */
00260 #define LL_UCPD_RXMODE_NORMAL           0x0U                /*!< Normal receive mode                                      */
00261 #define LL_UCPD_RXMODE_BIST_TEST_DATA   UCPD_CR_RXMODE      /*!< BIST receive mode (BIST Test Data Mode)                  */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
00267   * @{
00268   */
00269 #define LL_UCPD_TXMODE_NORMAL           0x0U                /*!< Initiate the transfer of a Tx message                    */
00270 #define LL_UCPD_TXMODE_CABLE_RESET      UCPD_CR_TXMODE_0    /*!< Trigger a the transfer of a Cable Reset sequence         */
00271 #define LL_UCPD_TXMODE_BIST_CARRIER2    UCPD_CR_TXMODE_1    /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2)  */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
00277   * @{
00278   */
00279 #define LL_UCPD_RXORDSET_SOP             0x0U                                                                                 /*!< SOP code detected in receiver              */
00280 #define LL_UCPD_RXORDSET_SOP1            UCPD_RX_ORDSET_RXORDSET_0                                                            /*!< SOP' code detected in receiver             */
00281 #define LL_UCPD_RXORDSET_SOP2            UCPD_RX_ORDSET_RXORDSET_1                                                            /*!< SOP'' code detected in receiver            */
00282 #define LL_UCPD_RXORDSET_SOP1_DEBUG      (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP' Debug code detected in receiver       */
00283 #define LL_UCPD_RXORDSET_SOP2_DEBUG      UCPD_RX_ORDSET_RXORDSET_2                                                            /*!< SOP'' Debug code detected in receiver      */
00284 #define LL_UCPD_RXORDSET_CABLE_RESET     (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)                              /*!< Cable Reset code detected in receiver      */
00285 #define LL_UCPD_RXORDSET_SOPEXT1         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP extension#1 code detected in receiver  */
00286 #define LL_UCPD_RXORDSET_SOPEXT2         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)  /*!< SOP extension#2 code detected in receiver  */
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /* Exported macro ------------------------------------------------------------*/
00296 /** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
00297   * @{
00298   */
00299
00300 /** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
00301   * @{
00302   */
00303
00304 /**
00305   * @brief  Write a value in UCPD register
00306   * @param  __INSTANCE__ UCPD Instance
00307   * @param  __REG__ Register to be written
00308   * @param  __VALUE__ Value to be written in the register
00309   * @retval None
00310   */
00311 #define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00312
00313 /**
00314   * @brief  Read a value in UCPD register
00315   * @param  __INSTANCE__ UCPD Instance
00316   * @param  __REG__ Register to be read
00317   * @retval Register value
00318   */
00319 #define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /* Exported functions --------------------------------------------------------*/
00329 /** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
00330   * @{
00331   */
00332
00333 /** @defgroup UCPD_LL_EF_Configuration Configuration
00334   * @{
00335   */
00336
00337 /** @defgroup UCPD_LL_EF_CFG1 CFG1 register
00338   * @{
00339   */
00340 /**
00341   * @brief  Enable UCPD peripheral
00342   * @rmtoll CFG1          UCPDEN           LL_UCPD_Enable
00343   * @param  UCPDx UCPD Instance
00344   * @retval None
00345   */
00346 __STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
00347 {
00348   SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
00349 }
00350
00351 /**
00352   * @brief  Disable UCPD peripheral
00353   * @note   When disabling the UCPD, follow the procedure described in the Reference Manual.
00354   * @rmtoll CFG1          UCPDEN           LL_UCPD_Disable
00355   * @param  UCPDx UCPD Instance
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
00359 {
00360   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
00361 }
00362
00363 /**
00364   * @brief  Check if UCPD peripheral is enabled
00365   * @rmtoll CFG1          UCPDEN           LL_UCPD_IsEnabled
00366   * @param  UCPDx UCPD Instance
00367   * @retval State of bit (1 or 0).
00368   */
00369 __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
00370 {
00371   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
00372 }
00373
00374 /**
00375   * @brief  Set the receiver ordered set detection enable
00376   * @rmtoll CFG1          RXORDSETEN          LL_UCPD_SetRxOrderSet
00377   * @param  UCPDx UCPD Instance
00378   * @param  OrderSet This parameter can be combination of the following values:
00379   *         @arg @ref LL_UCPD_ORDERSET_SOP
00380   *         @arg @ref LL_UCPD_ORDERSET_SOP1
00381   *         @arg @ref LL_UCPD_ORDERSET_SOP2
00382   *         @arg @ref LL_UCPD_ORDERSET_HARDRST
00383   *         @arg @ref LL_UCPD_ORDERSET_CABLERST
00384   *         @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
00385   *         @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
00386   *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
00387   *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
00391 {
00392   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
00393 }
00394
00395 /**
00396   * @brief  Set the prescaler for ucpd clock
00397   * @rmtoll CFG1          UCPDCLK          LL_UCPD_SetPSCClk
00398   * @param  UCPDx UCPD Instance
00399   * @param  Psc This parameter can be one of the following values:
00400   *         @arg @ref LL_UCPD_PSC_DIV1
00401   *         @arg @ref LL_UCPD_PSC_DIV2
00402   *         @arg @ref LL_UCPD_PSC_DIV4
00403   *         @arg @ref LL_UCPD_PSC_DIV8
00404   *         @arg @ref LL_UCPD_PSC_DIV16
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
00408 {
00409   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
00410 }
00411
00412 /**
00413   * @brief  Set the number of cycles (minus 1) of the half bit clock
00414   * @rmtoll CFG1          TRANSWIN          LL_UCPD_SetTransWin
00415   * @param  UCPDx UCPD Instance
00416   * @param  TransWin a value between Min_Data=0x1 and Max_Data=0x1F
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
00420 {
00421   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
00422 }
00423
00424 /**
00425   * @brief  Set the clock divider value to generate an interframe gap
00426   * @rmtoll CFG1          IFRGAP          LL_UCPD_SetIfrGap
00427   * @param  UCPDx UCPD Instance
00428   * @param  IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
00429   * @retval None
00430   */
00431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
00432 {
00433   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
00434 }
00435
00436 /**
00437   * @brief  Set the clock divider value to generate an interframe gap
00438   * @rmtoll CFG1          HBITCLKDIV          LL_UCPD_SetHbitClockDiv
00439   * @param  UCPDx UCPD Instance
00440   * @param  HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
00444 {
00445   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
00446 }
00447
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup UCPD_LL_EF_CFG2 CFG2 register
00453   * @{
00454   */
00455
00456 /**
00457   * @brief  Enable the wakeup mode
00458   * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpEnable
00459   * @param  UCPDx UCPD Instance
00460   * @retval None
00461   */
00462 __STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
00463 {
00464   SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
00465 }
00466
00467 /**
00468   * @brief  Disable the wakeup mode
00469   * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpDisable
00470   * @param  UCPDx UCPD Instance
00471   * @retval None
00472   */
00473 __STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
00474 {
00475   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
00476 }
00477
00478 /**
00479   * @brief  Force clock enable
00480   * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockEnable
00481   * @param  UCPDx UCPD Instance
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
00485 {
00486   SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
00487 }
00488
00489 /**
00490   * @brief  Force clock disable
00491   * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockDisable
00492   * @param  UCPDx UCPD Instance
00493   * @retval None
00494   */
00495 __STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
00496 {
00497   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
00498 }
00499
00500 /**
00501   * @brief  RxFilter enable
00502   * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterEnable
00503   * @param  UCPDx UCPD Instance
00504   * @retval None
00505   */
00506 __STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
00507 {
00508   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
00509 }
00510
00511 /**
00512   * @brief  RxFilter disable
00513   * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterDisable
00514   * @param  UCPDx UCPD Instance
00515   * @retval None
00516   */
00517 __STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
00518 {
00519   SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
00520 }
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup UCPD_LL_EF_CR CR register
00531   * @{
00532   */
00533 /**
00534   * @brief  Type C detector for CC2 enable
00535   * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Enable
00536   * @param  UCPDx UCPD Instance
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
00540 {
00541   CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
00542 }
00543
00544 /**
00545   * @brief  Type C detector for CC2 disable
00546   * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Disable
00547   * @param  UCPDx UCPD Instance
00548   * @retval None
00549   */
00550 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
00551 {
00552   SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
00553 }
00554
00555 /**
00556   * @brief  Type C detector for CC1 enable
00557   * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Enable
00558   * @param  UCPDx UCPD Instance
00559   * @retval None
00560   */
00561 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
00562 {
00563   CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
00564 }
00565
00566 /**
00567   * @brief  Type C detector for CC1 disable
00568   * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Disable
00569   * @param  UCPDx UCPD Instance
00570   * @retval None
00571   */
00572 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
00573 {
00574   SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
00575 }
00576
00577 /**
00578   * @brief  Source Vconn discharge enable
00579   * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeEnable
00580   * @param  UCPDx UCPD Instance
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
00584 {
00585   SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
00586 }
00587
00588 /**
00589   * @brief  Source Vconn discharge disable
00590   * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeDisable
00591   * @param  UCPDx UCPD Instance
00592   * @retval None
00593   */
00594 __STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
00595 {
00596   CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
00597 }
00598
00599 /**
00600   * @brief  Signal Fast Role Swap request
00601   * @rmtoll CR          FRSTX          LL_UCPD_VconnDischargeDisable
00602   * @param  UCPDx UCPD Instance
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
00606 {
00607   SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
00608 }
00609
00610 /**
00611   * @brief  Fast Role swap RX detection enable
00612   * @rmtoll CR          FRSRXEN          LL_UCPD_FRSDetectionEnable
00613   * @param  UCPDx UCPD Instance
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
00617 {
00618   SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
00619 }
00620
00621 /**
00622   * @brief  Fast Role swap RX detection disable
00623   * @rmtoll CR          FRSRXEN          LL_UCPD_FRSDetectionDisable
00624   * @param  UCPDx UCPD Instance
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
00628 {
00629   CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
00630 }
00631
00632 /**
00633   * @brief  Set cc enable
00634   * @rmtoll CR          CC1VCONNEN          LL_UCPD_SetccEnable
00635   * @param  UCPDx UCPD Instance
00636   * @param  CCEnable This parameter can be one of the following values:
00637   *         @arg @ref LL_UCPD_CCENABLE_NONE
00638   *         @arg @ref LL_UCPD_CCENABLE_CC1
00639   *         @arg @ref LL_UCPD_CCENABLE_CC2
00640   *         @arg @ref LL_UCPD_CCENABLE_CC1CC2
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
00644 {
00645   MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
00646 }
00647
00648 /**
00649   * @brief  Set UCPD SNK role
00650   * @rmtoll CR        ANAMODE          LL_UCPD_SetSNKRole
00651   * @param  UCPDx UCPD Instance
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
00655 {
00656   SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
00657 }
00658
00659 /**
00660   * @brief  Set UCPD SRC role
00661   * @rmtoll CR        ANAMODE          LL_UCPD_SetSRCRole
00662   * @param  UCPDx UCPD Instance
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
00666 {
00667   CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
00668 }
00669
00670 /**
00671   * @brief  Get UCPD Role
00672   * @rmtoll CR          ANAMODE          LL_UCPD_GetRole
00673   * @param  UCPDx UCPD Instance
00674   * @retval Returned value can be one of the following values:
00675   *         @arg @ref LL_UCPD_ROLE_SNK
00676   *         @arg @ref LL_UCPD_ROLE_SRC
00677   */
00678 __STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
00679 {
00680   return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
00681 }
00682
00683 /**
00684   * @brief  Set Rp resistor
00685   * @rmtoll CR        ANASUBMODE          LL_UCPD_SetRpResistor
00686   * @param  UCPDx UCPD Instance
00687   * @param  Resistor This parameter can be one of the following values:
00688   *         @arg @ref LL_UCPD_RESISTOR_DEFAULT
00689   *         @arg @ref LL_UCPD_RESISTOR_1_5A
00690   *         @arg @ref LL_UCPD_RESISTOR_3_0A
00691   *         @arg @ref LL_UCPD_RESISTOR_NONE
00692   * @retval None
00693   */
00694 __STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
00695 {
00696   MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE,  Resistor);
00697 }
00698
00699 /**
00700   * @brief  Set CC pin
00701   * @rmtoll CR        PHYCCSEL          LL_UCPD_SetCCPin
00702   * @param  UCPDx UCPD Instance
00703   * @param  CCPin This parameter can be one of the following values:
00704   *         @arg @ref LL_UCPD_CCPIN_CC1
00705   *         @arg @ref LL_UCPD_CCPIN_CC2
00706   * @retval None
00707   */
00708 __STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
00709 {
00710   MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL,  CCPin);
00711 }
00712
00713 /**
00714   * @brief  Rx enable
00715   * @rmtoll CR        PHYRXEN          LL_UCPD_RxEnable
00716   * @param  UCPDx UCPD Instance
00717   * @retval None
00718   */
00719 __STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
00720 {
00721   SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
00722 }
00723
00724 /**
00725   * @brief  Rx disable
00726   * @rmtoll CR        PHYRXEN          LL_UCPD_RxDisable
00727   * @param  UCPDx UCPD Instance
00728   * @retval None
00729   */
00730 __STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
00731 {
00732   CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
00733 }
00734
00735 /**
00736   * @brief  Set Rx mode
00737   * @rmtoll CR        RXMODE          LL_UCPD_SetRxMode
00738   * @param  UCPDx UCPD Instance
00739   * @param  RxMode This parameter can be one of the following values:
00740   *         @arg @ref LL_UCPD_RXMODE_NORMAL
00741   *         @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
00742   * @retval None
00743   */
00744 __STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
00745 {
00746   MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
00747 }
00748
00749 /**
00750   * @brief  Send Hard Reset
00751   * @rmtoll CR        TXHRST          LL_UCPD_SendHardReset
00752   * @param  UCPDx UCPD Instance
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
00756 {
00757   SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
00758 }
00759
00760 /**
00761   * @brief  Send message
00762   * @rmtoll CR        TXSEND          LL_UCPD_SendMessage
00763   * @param  UCPDx UCPD Instance
00764   * @retval None
00765   */
00766 __STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
00767 {
00768   SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
00769 }
00770
00771 /**
00772   * @brief  Set Tx mode
00773   * @rmtoll CR        TXMODE          LL_UCPD_SetTxMode
00774   * @param  UCPDx UCPD Instance
00775   * @param  TxMode This parameter can be one of the following values:
00776   *         @arg @ref LL_UCPD_TXMODE_NORMAL
00777   *         @arg @ref LL_UCPD_TXMODE_CABLE_RESET
00778   *         @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
00779   * @retval None
00780   */
00781 __STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
00782 {
00783   MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
00784 }
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
00791   * @{
00792   */
00793
00794 /**
00795   * @brief  Enable FRS interrupt
00796   * @rmtoll IMR          FRSEVTIE         LL_UCPD_EnableIT_FRS
00797   * @param  UCPDx UCPD Instance
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
00801 {
00802   SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
00803 }
00804
00805 /**
00806   * @brief  Enable type c event on CC2
00807   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_EnableIT_TypeCEventCC2
00808   * @param  UCPDx UCPD Instance
00809   * @retval None
00810   */
00811 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
00812 {
00813   SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
00814 }
00815
00816 /**
00817   * @brief  Enable type c event on CC1
00818   * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_EnableIT_TypeCEventCC1
00819   * @param  UCPDx UCPD Instance
00820   * @retval None
00821   */
00822 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
00823 {
00824   SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
00825 }
00826
00827 /**
00828   * @brief  Enable Rx message end interrupt
00829   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_EnableIT_RxMsgEnd
00830   * @param  UCPDx UCPD Instance
00831   * @retval None
00832   */
00833 __STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
00834 {
00835   SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
00836 }
00837
00838 /**
00839   * @brief  Enable Rx overrun interrupt
00840   * @rmtoll IMR          RXOVRIE         LL_UCPD_EnableIT_RxOvr
00841   * @param  UCPDx UCPD Instance
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
00845 {
00846   SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
00847 }
00848
00849 /**
00850   * @brief  Enable Rx hard resrt interrupt
00851   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_EnableIT_RxHRST
00852   * @param  UCPDx UCPD Instance
00853   * @retval None
00854   */
00855 __STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
00856 {
00857   SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
00858 }
00859
00860 /**
00861   * @brief  Enable Rx orderset interrupt
00862   * @rmtoll IMR          RXORDDETIE         LL_UCPD_EnableIT_RxOrderSet
00863   * @param  UCPDx UCPD Instance
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
00867 {
00868   SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
00869 }
00870
00871 /**
00872   * @brief  Enable Rx non empty interrupt
00873   * @rmtoll IMR          RXNEIE         LL_UCPD_EnableIT_RxNE
00874   * @param  UCPDx UCPD Instance
00875   * @retval None
00876   */
00877 __STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
00878 {
00879   SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
00880 }
00881
00882 /**
00883   * @brief  Enable TX underrun interrupt
00884   * @rmtoll IMR          TXUNDIE         LL_UCPD_EnableIT_TxUND
00885   * @param  UCPDx UCPD Instance
00886   * @retval None
00887   */
00888 __STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
00889 {
00890   SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
00891 }
00892
00893 /**
00894   * @brief  Enable hard reset sent interrupt
00895   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_EnableIT_TxHRSTSENT
00896   * @param  UCPDx UCPD Instance
00897   * @retval None
00898   */
00899 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
00900 {
00901   SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
00902 }
00903
00904 /**
00905   * @brief  Enable hard reset discard interrupt
00906   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_EnableIT_TxHRSTDISC
00907   * @param  UCPDx UCPD Instance
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
00911 {
00912   SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
00913 }
00914
00915 /**
00916   * @brief  Enable Tx message abort interrupt
00917   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_EnableIT_TxMSGABT
00918   * @param  UCPDx UCPD Instance
00919   * @retval None
00920   */
00921 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
00922 {
00923   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
00924 }
00925
00926 /**
00927   * @brief  Enable Tx message sent interrupt
00928   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_EnableIT_TxMSGSENT
00929   * @param  UCPDx UCPD Instance
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
00933 {
00934   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
00935 }
00936
00937 /**
00938   * @brief  Enable Tx message discarded interrupt
00939   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_EnableIT_TxMSGDISC
00940   * @param  UCPDx UCPD Instance
00941   * @retval None
00942   */
00943 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
00944 {
00945   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
00946 }
00947
00948 /**
00949   * @brief  Enable Tx data receive interrupt
00950   * @rmtoll IMR          TXISIE         LL_UCPD_EnableIT_TxIS
00951   * @param  UCPDx UCPD Instance
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
00955 {
00956   SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
00957 }
00958
00959 /**
00960   * @brief  Disable FRS interrupt
00961   * @rmtoll IMR          FRSEVTIE         LL_UCPD_DisableIT_FRS
00962   * @param  UCPDx UCPD Instance
00963   * @retval None
00964   */
00965 __STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
00966 {
00967   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
00968 }
00969
00970 /**
00971   * @brief  Disable type c event on CC2
00972   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
00973   * @param  UCPDx UCPD Instance
00974   * @retval None
00975   */
00976 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
00977 {
00978   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
00979 }
00980
00981 /**
00982   * @brief  Disable type c event on CC1
00983   * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_DisableIT_TypeCEventCC1
00984   * @param  UCPDx UCPD Instance
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
00988 {
00989   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
00990 }
00991
00992 /**
00993   * @brief  Disable Rx message end interrupt
00994   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_DisableIT_RxMsgEnd
00995   * @param  UCPDx UCPD Instance
00996   * @retval None
00997   */
00998 __STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
00999 {
01000   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
01001 }
01002
01003 /**
01004   * @brief  Disable Rx overrun interrupt
01005   * @rmtoll IMR          RXOVRIE         LL_UCPD_DisableIT_RxOvr
01006   * @param  UCPDx UCPD Instance
01007   * @retval None
01008   */
01009 __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
01010 {
01011   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
01012 }
01013
01014 /**
01015   * @brief  Disable Rx hard resrt interrupt
01016   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_DisableIT_RxHRST
01017   * @param  UCPDx UCPD Instance
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
01021 {
01022   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
01023 }
01024
01025 /**
01026   * @brief  Disable Rx orderset interrupt
01027   * @rmtoll IMR          RXORDDETIE         LL_UCPD_DisableIT_RxOrderSet
01028   * @param  UCPDx UCPD Instance
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
01032 {
01033   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
01034 }
01035
01036 /**
01037   * @brief  Disable Rx non empty interrupt
01038   * @rmtoll IMR          RXNEIE         LL_UCPD_DisableIT_RxNE
01039   * @param  UCPDx UCPD Instance
01040   * @retval None
01041   */
01042 __STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
01043 {
01044   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
01045 }
01046
01047 /**
01048   * @brief  Disable TX underrun interrupt
01049   * @rmtoll IMR          TXUNDIE         LL_UCPD_DisableIT_TxUND
01050   * @param  UCPDx UCPD Instance
01051   * @retval None
01052   */
01053 __STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
01054 {
01055   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
01056 }
01057
01058 /**
01059   * @brief  Disable hard reset sent interrupt
01060   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_DisableIT_TxHRSTSENT
01061   * @param  UCPDx UCPD Instance
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
01065 {
01066   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
01067 }
01068
01069 /**
01070   * @brief  Disable hard reset discard interrupt
01071   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_DisableIT_TxHRSTDISC
01072   * @param  UCPDx UCPD Instance
01073   * @retval None
01074   */
01075 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
01076 {
01077   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
01078 }
01079
01080 /**
01081   * @brief  Disable Tx message abort interrupt
01082   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_DisableIT_TxMSGABT
01083   * @param  UCPDx UCPD Instance
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
01087 {
01088   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
01089 }
01090
01091 /**
01092   * @brief  Disable Tx message sent interrupt
01093   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_DisableIT_TxMSGSENT
01094   * @param  UCPDx UCPD Instance
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
01098 {
01099   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
01100 }
01101
01102 /**
01103   * @brief  Disable Tx message discarded interrupt
01104   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_DisableIT_TxMSGDISC
01105   * @param  UCPDx UCPD Instance
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
01109 {
01110   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
01111 }
01112
01113 /**
01114   * @brief  Disable Tx data receive interrupt
01115   * @rmtoll IMR          TXISIE         LL_UCPD_DisableIT_TxIS
01116   * @param  UCPDx UCPD Instance
01117   * @retval None
01118   */
01119 __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
01120 {
01121   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
01122 }
01123
01124 /**
01125   * @brief  Check if FRS interrupt enabled
01126   * @rmtoll IMR          FRSEVTIE         LL_UCPD_DisableIT_FRS
01127   * @param  UCPDx UCPD Instance
01128   * @retval State of bit (1 or 0).
01129   */
01130 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
01131 {
01132   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
01133 }
01134
01135 /**
01136   * @brief  Check if type c event on CC2 enabled
01137   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
01138   * @param  UCPDx UCPD Instance
01139   * @retval State of bit (1 or 0).
01140   */
01141 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
01142 {
01143   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
01144 }
01145
01146 /**
01147   * @brief  Check if type c event on CC1 enabled
01148   * @rmtoll IMR2          TYPECEVT1IE        LL_UCPD_IsEnableIT_TypeCEventCC1
01149   * @param  UCPDx UCPD Instance
01150   * @retval State of bit (1 or 0).
01151   */
01152 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
01153 {
01154   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
01155 }
01156
01157 /**
01158   * @brief  Check if Rx message end interrupt enabled
01159   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_IsEnableIT_RxMsgEnd
01160   * @param  UCPDx UCPD Instance
01161   * @retval State of bit (1 or 0).
01162   */
01163 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
01164 {
01165   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
01166 }
01167
01168 /**
01169   * @brief  Check if Rx overrun interrupt enabled
01170   * @rmtoll IMR          RXOVRIE         LL_UCPD_IsEnableIT_RxOvr
01171   * @param  UCPDx UCPD Instance
01172   * @retval State of bit (1 or 0).
01173   */
01174 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
01175 {
01176   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
01177 }
01178
01179 /**
01180   * @brief  Check if Rx hard resrt interrupt enabled
01181   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_IsEnableIT_RxHRST
01182   * @param  UCPDx UCPD Instance
01183   * @retval State of bit (1 or 0).
01184   */
01185 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
01186 {
01187   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
01188 }
01189
01190 /**
01191   * @brief  Check if Rx orderset interrupt enabled
01192   * @rmtoll IMR          RXORDDETIE         LL_UCPD_IsEnableIT_RxOrderSet
01193   * @param  UCPDx UCPD Instance
01194   * @retval State of bit (1 or 0).
01195   */
01196 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
01197 {
01198   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
01199 }
01200
01201 /**
01202   * @brief  Check if Rx non empty interrupt enabled
01203   * @rmtoll IMR          RXNEIE         LL_UCPD_IsEnableIT_RxNE
01204   * @param  UCPDx UCPD Instance
01205   * @retval State of bit (1 or 0).
01206   */
01207 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
01208 {
01209   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
01210 }
01211
01212 /**
01213   * @brief  Check if TX underrun interrupt enabled
01214   * @rmtoll IMR          TXUNDIE         LL_UCPD_IsEnableIT_TxUND
01215   * @param  UCPDx UCPD Instance
01216   * @retval State of bit (1 or 0).
01217   */
01218 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
01219 {
01220   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
01221 }
01222
01223 /**
01224   * @brief  Check if hard reset sent interrupt enabled
01225   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_IsEnableIT_TxHRSTSENT
01226   * @param  UCPDx UCPD Instance
01227   * @retval State of bit (1 or 0).
01228   */
01229 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
01230 {
01231   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
01232 }
01233
01234 /**
01235   * @brief  Check if hard reset discard interrupt enabled
01236   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_IsEnableIT_TxHRSTDISC
01237   * @param  UCPDx UCPD Instance
01238   * @retval State of bit (1 or 0).
01239   */
01240 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
01241 {
01242   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
01243 }
01244
01245 /**
01246   * @brief  Check if Tx message abort interrupt enabled
01247   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_IsEnableIT_TxMSGABT
01248   * @param  UCPDx UCPD Instance
01249   * @retval State of bit (1 or 0).
01250   */
01251 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
01252 {
01253   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
01254 }
01255
01256 /**
01257   * @brief  Check if Tx message sent interrupt enabled
01258   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_IsEnableIT_TxMSGSENT
01259   * @param  UCPDx UCPD Instance
01260   * @retval State of bit (1 or 0).
01261   */
01262 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
01263 {
01264   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
01265 }
01266
01267 /**
01268   * @brief  Check if Tx message discarded interrupt enabled
01269   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_IsEnableIT_TxMSGDISC
01270   * @param  UCPDx UCPD Instance
01271   * @retval State of bit (1 or 0).
01272   */
01273 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
01274 {
01275   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
01276 }
01277
01278 /**
01279   * @brief  Check if Tx data receive interrupt enabled
01280   * @rmtoll IMR          TXISIE         LL_UCPD_IsEnableIT_TxIS
01281   * @param  UCPDx UCPD Instance
01282   * @retval State of bit (1 or 0).
01283   */
01284 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
01285 {
01286   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
01287 }
01288
01289 /**
01290   * @}
01291   */
01292
01293 /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
01294   * @{
01295   */
01296
01297 /**
01298   * @brief  Clear FRS interrupt
01299   * @rmtoll ICR          FRSEVTIE         LL_UCPD_ClearFlag_FRS
01300   * @param  UCPDx UCPD Instance
01301   * @retval None
01302   */
01303 __STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
01304 {
01305   SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
01306 }
01307
01308 /**
01309   * @brief  Clear type c event on CC2
01310   * @rmtoll IIMR          TYPECEVT2IE        LL_UCPD_ClearFlag_TypeCEventCC2
01311   * @param  UCPDx UCPD Instance
01312   * @retval None
01313   */
01314 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
01315 {
01316   SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
01317 }
01318
01319 /**
01320   * @brief  Clear type c event on CC1
01321   * @rmtoll IIMR          TYPECEVT1IE        LL_UCPD_ClearFlag_TypeCEventCC1
01322   * @param  UCPDx UCPD Instance
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
01326 {
01327   SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
01328 }
01329
01330 /**
01331   * @brief  Clear Rx message end interrupt
01332   * @rmtoll ICR          RXMSGENDIE         LL_UCPD_ClearFlag_RxMsgEnd
01333   * @param  UCPDx UCPD Instance
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
01337 {
01338   SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
01339 }
01340
01341 /**
01342   * @brief  Clear Rx overrun interrupt
01343   * @rmtoll ICR          RXOVRIE         LL_UCPD_ClearFlag_RxOvr
01344   * @param  UCPDx UCPD Instance
01345   * @retval None
01346   */
01347 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
01348 {
01349   SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
01350 }
01351
01352 /**
01353   * @brief  Clear Rx hard resrt interrupt
01354   * @rmtoll ICR          RXHRSTDETIE         LL_UCPD_ClearFlag_RxHRST
01355   * @param  UCPDx UCPD Instance
01356   * @retval None
01357   */
01358 __STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
01359 {
01360   SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
01361 }
01362
01363 /**
01364   * @brief  Clear Rx orderset interrupt
01365   * @rmtoll ICR          RXORDDETIE         LL_UCPD_ClearFlag_RxOrderSet
01366   * @param  UCPDx UCPD Instance
01367   * @retval None
01368   */
01369 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
01370 {
01371   SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
01372 }
01373
01374 /**
01375   * @brief  Clear TX underrun interrupt
01376   * @rmtoll ICR          TXUNDIE         LL_UCPD_ClearFlag_TxUND
01377   * @param  UCPDx UCPD Instance
01378   * @retval None
01379   */
01380 __STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
01381 {
01382   SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
01383 }
01384
01385 /**
01386   * @brief  Clear hard reset sent interrupt
01387   * @rmtoll ICR          HRSTSENTIE         LL_UCPD_ClearFlag_TxHRSTSENT
01388   * @param  UCPDx UCPD Instance
01389   * @retval None
01390   */
01391 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
01392 {
01393   SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
01394 }
01395
01396 /**
01397   * @brief  Clear hard reset discard interrupt
01398   * @rmtoll ICR          HRSTDISCIE         LL_UCPD_ClearFlag_TxHRSTDISC
01399   * @param  UCPDx UCPD Instance
01400   * @retval None
01401   */
01402 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
01403 {
01404   SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
01405 }
01406
01407 /**
01408   * @brief  Clear Tx message abort interrupt
01409   * @rmtoll ICR          TXMSGABTIE         LL_UCPD_ClearFlag_TxMSGABT
01410   * @param  UCPDx UCPD Instance
01411   * @retval None
01412   */
01413 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
01414 {
01415   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
01416 }
01417
01418 /**
01419   * @brief  Clear Tx message sent interrupt
01420   * @rmtoll ICR          TXMSGSENTIE         LL_UCPD_ClearFlag_TxMSGSENT
01421   * @param  UCPDx UCPD Instance
01422   * @retval None
01423   */
01424 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
01425 {
01426   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
01427 }
01428
01429 /**
01430   * @brief  Clear Tx message discarded interrupt
01431   * @rmtoll ICR          TXMSGDISCIE         LL_UCPD_ClearFlag_TxMSGDISC
01432   * @param  UCPDx UCPD Instance
01433   * @retval None
01434   */
01435 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
01436 {
01437   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
01438 }
01439
01440 /**
01441   * @}
01442   */
01443
01444 /** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
01445   * @{
01446   */
01447
01448 /**
01449   * @brief  Check if FRS interrupt
01450   * @rmtoll SR          FRSEVT         LL_UCPD_IsActiveFlag_FRS
01451   * @param  UCPDx UCPD Instance
01452   * @retval None
01453   */
01454 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
01455 {
01456   return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
01457 }
01458
01459 /**
01460   * @brief  Check if type c event on CC2
01461   * @rmtoll SR          TYPECEVT2        LL_UCPD_IsActiveFlag_TypeCEventCC2
01462   * @param  UCPDx UCPD Instance
01463   * @retval None
01464   */
01465 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
01466 {
01467   return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
01468 }
01469
01470 /**
01471   * @brief  Check if type c event on CC1
01472   * @rmtoll SR          TYPECEVT1        LL_UCPD_IsActiveFlag_TypeCEventCC1
01473   * @param  UCPDx UCPD Instance
01474   * @retval None
01475   */
01476 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
01477 {
01478   return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
01479 }
01480
01481 /**
01482   * @brief  Check if Rx message end interrupt
01483   * @rmtoll SR          RXMSGEND         LL_UCPD_IsActiveFlag_RxMsgEnd
01484   * @param  UCPDx UCPD Instance
01485   * @retval None
01486   */
01487 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
01488 {
01489   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
01490 }
01491
01492 /**
01493   * @brief  Check if Rx overrun interrupt
01494   * @rmtoll SR          RXOVR         LL_UCPD_IsActiveFlag_RxOvr
01495   * @param  UCPDx UCPD Instance
01496   * @retval None
01497   */
01498 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
01499 {
01500   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
01501 }
01502
01503 /**
01504   * @brief  Check if Rx hard resrt interrupt
01505   * @rmtoll SR          RXHRSTDET         LL_UCPD_IsActiveFlag_RxHRST
01506   * @param  UCPDx UCPD Instance
01507   * @retval None
01508   */
01509 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
01510 {
01511   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
01512 }
01513
01514 /**
01515   * @brief  Check if Rx orderset interrupt
01516   * @rmtoll SR          RXORDDET         LL_UCPD_IsActiveFlag_RxOrderSet
01517   * @param  UCPDx UCPD Instance
01518   * @retval State of bit (1 or 0).
01519   */
01520 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
01521 {
01522   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
01523 }
01524
01525 /**
01526   * @brief  Check if Rx non empty interrupt
01527   * @rmtoll SR          RXNE         LL_UCPD_IsActiveFlag_RxNE
01528   * @param  UCPDx UCPD Instance
01529   * @retval State of bit (1 or 0).
01530   */
01531 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
01532 {
01533   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
01534 }
01535
01536 /**
01537   * @brief  Check if TX underrun interrupt
01538   * @rmtoll SR          TXUND         LL_UCPD_IsActiveFlag_TxUND
01539   * @param  UCPDx UCPD Instance
01540   * @retval State of bit (1 or 0).
01541   */
01542 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
01543 {
01544   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
01545 }
01546
01547 /**
01548   * @brief  Check if hard reset sent interrupt
01549   * @rmtoll SR          HRSTSENT         LL_UCPD_IsActiveFlag_TxHRSTSENT
01550   * @param  UCPDx UCPD Instance
01551   * @retval State of bit (1 or 0).
01552   */
01553 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
01554 {
01555   return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
01556 }
01557
01558 /**
01559   * @brief  Check if hard reset discard interrupt
01560   * @rmtoll SR          HRSTDISC         LL_UCPD_IsActiveFlag_TxHRSTDISC
01561   * @param  UCPDx UCPD Instance
01562   * @retval State of bit (1 or 0).
01563   */
01564 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
01565 {
01566   return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
01567 }
01568
01569 /**
01570   * @brief  Check if Tx message abort interrupt
01571   * @rmtoll SR          TXMSGABT         LL_UCPD_IsActiveFlag_TxMSGABT
01572   * @param  UCPDx UCPD Instance
01573   * @retval State of bit (1 or 0).
01574   */
01575 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
01576 {
01577   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
01578 }
01579
01580 /**
01581   * @brief  Check if Tx message sent interrupt
01582   * @rmtoll SR          TXMSGSENT         LL_UCPD_IsActiveFlag_TxMSGSENT
01583   * @param  UCPDx UCPD Instance
01584   * @retval State of bit (1 or 0).
01585   */
01586 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
01587 {
01588   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
01589 }
01590
01591 /**
01592   * @brief  Check if Tx message discarded interrupt
01593   * @rmtoll SR         TXMSGDISC         LL_UCPD_IsActiveFlag_TxMSGDISC
01594   * @param  UCPDx UCPD Instance
01595   * @retval State of bit (1 or 0).
01596   */
01597 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
01598 {
01599   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
01600 }
01601
01602 /**
01603   * @brief  Check if Tx data receive interrupt
01604   * @rmtoll SR          TXIS         LL_UCPD_IsActiveFlag_TxIS
01605   * @param  UCPDx UCPD Instance
01606   * @retval State of bit (1 or 0).
01607   */
01608 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
01609 {
01610   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
01611 }
01612
01613 /**
01614   * @brief  return the vstate value for CC2
01615   * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC2
01616   * @param  UCPDx UCPD Instance
01617   * @retval val
01618   */
01619 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
01620 {
01621   return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
01622 }
01623
01624 /**
01625   * @brief  return the vstate value for CC1
01626   * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC1
01627   * @param  UCPDx UCPD Instance
01628   * @retval val
01629   */
01630 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
01631 {
01632   return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
01633 }
01634
01635 /**
01636   * @}
01637   */
01638
01639
01640 /** @defgroup UCPD_LL_EF_DMA_Management DMA Management
01641   * @{
01642   */
01643
01644 /**
01645   * @brief  Rx DMA Enable
01646   * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMAEnable
01647   * @param  UCPDx UCPD Instance
01648   * @retval None
01649   */
01650 __STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
01651 {
01652   SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
01653 }
01654
01655 /**
01656   * @brief  Rx DMA Disable
01657   * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMADisable
01658   * @param  UCPDx UCPD Instance
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
01662 {
01663   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
01664 }
01665
01666 /**
01667   * @brief  Tx DMA Enable
01668   * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMAEnable
01669   * @param  UCPDx UCPD Instance
01670   * @retval None
01671   */
01672 __STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
01673 {
01674   SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
01675 }
01676
01677 /**
01678   * @brief  Tx DMA Disable
01679   * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMADisable
01680   * @param  UCPDx UCPD Instance
01681   * @retval None
01682   */
01683 __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
01684 {
01685   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
01686 }
01687
01688 /**
01689   * @brief  Check if DMA Tx is enabled
01690   * @rmtoll CR2          TXDMAEN       LL_UCPD_IsEnabledTxDMA
01691   * @param  UCPDx UCPD Instance
01692   * @retval State of bit (1 or 0).
01693   */
01694 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
01695 {
01696   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
01697 }
01698
01699 /**
01700   * @brief  Check if DMA Rx is enabled
01701   * @rmtoll CR2          RXDMAEN       LL_UCPD_IsEnabledRxDMA
01702   * @param  UCPDx UCPD Instance
01703   * @retval State of bit (1 or 0).
01704   */
01705 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
01706 {
01707   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
01708 }
01709
01710 /**
01711   * @}
01712   */
01713
01714 /** @defgroup UCPD_LL_EF_DATA_Management DATA Management
01715   * @{
01716   */
01717
01718 /**
01719   * @brief  write the orderset for Tx message
01720   * @rmtoll TX_ORDSET           TXORDSET            LL_UCPD_WriteTxOrderSet
01721   * @param  UCPDx UCPD Instance
01722   * @param  TxOrderSet one of the following value
01723   *         @arg @ref LL_UCPD_ORDERED_SET_SOP
01724   *         @arg @ref LL_UCPD_ORDERED_SET_SOP1
01725   *         @arg @ref LL_UCPD_ORDERED_SET_SOP2
01726   *         @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
01727   *         @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
01728   *         @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
01729   *         @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
01733 {
01734   WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
01735 }
01736
01737 /**
01738   * @brief  write the Tx paysize
01739   * @rmtoll TX_PAYSZ          TXPAYSZ            LL_UCPD_WriteTxPaySize
01740   * @param  UCPDx UCPD Instance
01741   * @param  TxPaySize
01742   * @retval None.
01743   */
01744 __STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
01745 {
01746   WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
01747 }
01748
01749 /**
01750   * @brief  Write data
01751   * @rmtoll TXDR           DR            LL_UCPD_WriteData
01752   * @param  UCPDx UCPD Instance
01753   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01754   * @retval None.
01755   */
01756 __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
01757 {
01758   WRITE_REG(UCPDx->TXDR, Data);
01759 }
01760
01761 /**
01762   * @brief  read RX the orderset
01763   * @rmtoll RX_ORDSET           RXORDSET            LL_UCPD_ReadRxOrderSet
01764   * @param  UCPDx UCPD Instance
01765   * @retval RxOrderSet one of the following value
01766   *         @arg @ref LL_UCPD_RXORDSET_SOP
01767   *         @arg @ref LL_UCPD_RXORDSET_SOP1
01768   *         @arg @ref LL_UCPD_RXORDSET_SOP2
01769   *         @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
01770   *         @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
01771   *         @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
01772   *         @arg @ref LL_UCPD_RXORDSET_SOPEXT1
01773   *         @arg @ref LL_UCPD_RXORDSET_SOPEXT2
01774   */
01775 __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
01776 {
01777   return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
01778 }
01779
01780 /**
01781   * @brief  Read the Rx paysize
01782   * @rmtoll RX_PAYSZ          RXPAYSZ            LL_UCPD_ReadRxPaySize
01783   * @param  UCPDx UCPD Instance
01784   * @retval RXPaysize.
01785   */
01786 __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
01787 {
01788   return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
01789 }
01790
01791 /**
01792   * @brief  Read data
01793   * @rmtoll RXDR           RXDATA            LL_UCPD_ReadData
01794   * @param  UCPDx UCPD Instance
01795   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01796   */
01797 __STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
01798 {
01799   return READ_REG(UCPDx->RXDR);
01800 }
01801
01802 /**
01803   * @brief  Set Rx OrderSet Ext1
01804   * @rmtoll RX_ORDEXT1           RXSOPX1            LL_UCPD_SetRxOrdExt1
01805   * @param  UCPDx UCPD Instance
01806   * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
01807   * @retval None
01808   */
01809 __STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
01810 {
01811   WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
01812 }
01813
01814 /**
01815   * @brief  Set Rx OrderSet Ext2
01816   * @rmtoll RX_ORDEXT2           RXSOPX2            LL_UCPD_SetRxOrdExt2
01817   * @param  UCPDx UCPD Instance
01818   * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
01822 {
01823   WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
01824 }
01825
01826 /**
01827   * @}
01828   */
01829
01830 #if defined(USE_FULL_LL_DRIVER)
01831 /** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
01832   * @{
01833   */
01834
01835 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
01836 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
01837 void        LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
01838
01839 /**
01840   * @}
01841   */
01842 #endif /* USE_FULL_LL_DRIVER */
01843
01844 /**
01845   * @}
01846   */
01847
01848 #endif /* defined (UCPD1) */
01849
01850 /**
01851   * @}
01852   */
01853
01854 /**
01855   * @}
01856   */
01857
01858 #ifdef __cplusplus
01859 }
01860 #endif
01861
01862 #endif /* STM32G4xx_LL_UCPD_H */
01863
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_usart.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_usart.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g4xx_ll_usart.h"
00022 #include "stm32g4xx_ll_rcc.h"
00023 #include "stm32g4xx_ll_bus.h"
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
00035
00036 /** @addtogroup USART_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup USART_LL_Private_Constants
00044   * @{
00045   */
00046
00047 /* Definition of default baudrate value used for USART initialisation */
00048 #define USART_DEFAULT_BAUDRATE          (9600U)
00049
00050 /**
00051   * @}
00052   */
00053
00054 /* Private macros ------------------------------------------------------------*/
00055 /** @addtogroup USART_LL_Private_Macros
00056   * @{
00057   */
00058
00059 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
00060                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
00061                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
00062                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
00063                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
00064                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
00065                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
00066                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
00067                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
00068                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
00069                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
00070                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
00071
00072 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00073  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00074 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
00075
00076 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00077 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00078
00079 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00080                                           || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00081                                           || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00082                                           || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00083
00084 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00085                                        || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00086                                        || ((__VALUE__) == LL_USART_PARITY_ODD))
00087
00088 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00089                                           || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00090                                           || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00091
00092 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00093                                              || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00094
00095 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00096                                                  || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00097
00098 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00099                                            || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00100
00101 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00102                                               || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00103
00104 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00105                                             || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00106
00107 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00108                                          || ((__VALUE__) == LL_USART_STOPBITS_1) \
00109                                          || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00110                                          || ((__VALUE__) == LL_USART_STOPBITS_2))
00111
00112 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00113                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00114                                           || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00115                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Private function prototypes -----------------------------------------------*/
00122
00123 /* Exported functions --------------------------------------------------------*/
00124 /** @addtogroup USART_LL_Exported_Functions
00125   * @{
00126   */
00127
00128 /** @addtogroup USART_LL_EF_Init
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  De-initialize USART registers (Registers restored to their default values).
00134   * @param  USARTx USART Instance
00135   * @retval An ErrorStatus enumeration value:
00136   *          - SUCCESS: USART registers are de-initialized
00137   *          - ERROR: USART registers are not de-initialized
00138   */
00139 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
00140 {
00141   ErrorStatus status = SUCCESS;
00142
00143   /* Check the parameters */
00144   assert_param(IS_UART_INSTANCE(USARTx));
00145
00146   if (USARTx == USART1)
00147   {
00148     /* Force reset of USART clock */
00149     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00150
00151     /* Release reset of USART clock */
00152     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00153   }
00154   else if (USARTx == USART2)
00155   {
00156     /* Force reset of USART clock */
00157     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00158
00159     /* Release reset of USART clock */
00160     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00161   }
00162   else if (USARTx == USART3)
00163   {
00164     /* Force reset of USART clock */
00165     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00166
00167     /* Release reset of USART clock */
00168     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00169   }
00170 #if defined(UART4)
00171   else if (USARTx == UART4)
00172   {
00173     /* Force reset of UART clock */
00174     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00175
00176     /* Release reset of UART clock */
00177     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00178   }
00179 #endif /* UART4 */
00180 #if defined(UART5)
00181   else if (USARTx == UART5)
00182   {
00183     /* Force reset of UART clock */
00184     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00185
00186     /* Release reset of UART clock */
00187     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00188   }
00189 #endif /* UART5 */
00190   else
00191   {
00192     status = ERROR;
00193   }
00194
00195   return (status);
00196 }
00197
00198 /**
00199   * @brief  Initialize USART registers according to the specified
00200   *         parameters in USART_InitStruct.
00201   * @note   As some bits in USART configuration registers can only be written when
00202   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
00203   *         this function. Otherwise, ERROR result will be returned.
00204   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00205   * @param  USARTx USART Instance
00206   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00207   *         that contains the configuration information for the specified USART peripheral.
00208   * @retval An ErrorStatus enumeration value:
00209   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00210   *          - ERROR: Problem occurred during USART Registers initialization
00211   */
00212 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
00213 {
00214   ErrorStatus status = ERROR;
00215   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00216
00217   /* Check the parameters */
00218   assert_param(IS_UART_INSTANCE(USARTx));
00219   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
00220   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00221   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00222   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00223   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00224   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00225   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00226   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00227
00228   /* USART needs to be in disabled state, in order to be able to configure some bits in
00229      CRx registers */
00230   if (LL_USART_IsEnabled(USARTx) == 0U)
00231   {
00232     /*---------------------------- USART CR1 Configuration ---------------------
00233      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00234      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00235      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00236      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00237      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00238      */
00239     MODIFY_REG(USARTx->CR1,
00240                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00241                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00242                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00243                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00244
00245     /*---------------------------- USART CR2 Configuration ---------------------
00246      * Configure USARTx CR2 (Stop bits) with parameters:
00247      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00248      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00249      */
00250     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00251
00252     /*---------------------------- USART CR3 Configuration ---------------------
00253      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00254      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
00255      *   USART_InitStruct->HardwareFlowControl value.
00256      */
00257     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00258
00259     /*---------------------------- USART BRR Configuration ---------------------
00260      * Retrieve Clock frequency used for USART Peripheral
00261      */
00262     if (USARTx == USART1)
00263     {
00264       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
00265     }
00266     else if (USARTx == USART2)
00267     {
00268       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
00269     }
00270     else if (USARTx == USART3)
00271     {
00272       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
00273     }
00274 #if defined(UART4)
00275     else if (USARTx == UART4)
00276     {
00277       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
00278     }
00279 #endif /* UART4 */
00280 #if defined(UART5)
00281     else if (USARTx == UART5)
00282     {
00283       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
00284     }
00285 #endif /* UART5 */
00286     else
00287     {
00288       /* Nothing to do, as error code is already assigned to ERROR value */
00289     }
00290
00291     /* Configure the USART Baud Rate :
00292        - prescaler value is required
00293        - valid baud rate value (different from 0) is required
00294        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00295     */
00296     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00297         && (USART_InitStruct->BaudRate != 0U))
00298     {
00299       status = SUCCESS;
00300       LL_USART_SetBaudRate(USARTx,
00301                            periphclk,
00302                            USART_InitStruct->PrescalerValue,
00303                            USART_InitStruct->OverSampling,
00304                            USART_InitStruct->BaudRate);
00305
00306       /* Check BRR is greater than or equal to 16d */
00307       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00308     }
00309
00310     /*---------------------------- USART PRESC Configuration -----------------------
00311      * Configure USARTx PRESC (Prescaler) with parameters:
00312      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
00313      */
00314     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
00315   }
00316   /* Endif (=> USART not in Disabled state => return ERROR) */
00317
00318   return (status);
00319 }
00320
00321 /**
00322   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00323   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00324   *                         whose fields will be set to default values.
00325   * @retval None
00326   */
00327
00328 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00329 {
00330   /* Set USART_InitStruct fields to default values */
00331   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
00332   USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
00333   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00334   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00335   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00336   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00337   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00338   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00339 }
00340
00341 /**
00342   * @brief  Initialize USART Clock related settings according to the
00343   *         specified parameters in the USART_ClockInitStruct.
00344   * @note   As some bits in USART configuration registers can only be written when
00345   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
00346   *         this function. Otherwise, ERROR result will be returned.
00347   * @param  USARTx USART Instance
00348   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00349   *         that contains the Clock configuration information for the specified USART peripheral.
00350   * @retval An ErrorStatus enumeration value:
00351   *          - SUCCESS: USART registers related to Clock settings are initialized according
00352   *                     to USART_ClockInitStruct content
00353   *          - ERROR: Problem occurred during USART Registers initialization
00354   */
00355 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00356 {
00357   ErrorStatus status = SUCCESS;
00358
00359   /* Check USART Instance and Clock signal output parameters */
00360   assert_param(IS_UART_INSTANCE(USARTx));
00361   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00362
00363   /* USART needs to be in disabled state, in order to be able to configure some bits in
00364      CRx registers */
00365   if (LL_USART_IsEnabled(USARTx) == 0U)
00366   {
00367     /* Ensure USART instance is USART capable */
00368     assert_param(IS_USART_INSTANCE(USARTx));
00369
00370     /* Check clock related parameters */
00371     assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00372     assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00373     assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00374
00375     /*---------------------------- USART CR2 Configuration -----------------------
00376      * Configure USARTx CR2 (Clock signal related bits) with parameters:
00377      * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
00378      * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00379      * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00380      * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00381      */
00382     MODIFY_REG(USARTx->CR2,
00383                USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00384                USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
00385                USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00386   }
00387   /* Else (USART not in Disabled state => return ERROR */
00388   else
00389   {
00390     status = ERROR;
00391   }
00392
00393   return (status);
00394 }
00395
00396 /**
00397   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00398   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00399   *                              whose fields will be set to default values.
00400   * @retval None
00401   */
00402 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00403 {
00404   /* Set LL_USART_ClockInitStruct fields with default values */
00405   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00406   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
00407                                                                                   LL_USART_CLOCK_DISABLE */
00408   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
00409                                                                                   LL_USART_CLOCK_DISABLE */
00410   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
00411                                                                                   LL_USART_CLOCK_DISABLE */
00412 }
00413
00414 /**
00415   * @}
00416   */
00417
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
00427
00428 /**
00429   * @}
00430   */
00431
00432 #endif /* USE_FULL_LL_DRIVER */
00433
00434
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_usart.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_usart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_USART_H
00021 #define STM32G4xx_LL_USART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
00035
00036 /** @defgroup USART_LL USART
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup USART_LL_Private_Variables USART Private Variables
00043   * @{
00044   */
00045 /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
00046 static const uint32_t USART_PRESCALER_TAB[] =
00047 {
00048   1UL,
00049   2UL,
00050   4UL,
00051   6UL,
00052   8UL,
00053   10UL,
00054   12UL,
00055   16UL,
00056   32UL,
00057   64UL,
00058   128UL,
00059   256UL
00060 };
00061 /**
00062   * @}
00063   */
00064
00065 /* Private constants ---------------------------------------------------------*/
00066 /** @defgroup USART_LL_Private_Constants USART Private Constants
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072 /* Private macros ------------------------------------------------------------*/
00073 #if defined(USE_FULL_LL_DRIVER)
00074 /** @defgroup USART_LL_Private_Macros USART Private Macros
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080 #endif /*USE_FULL_LL_DRIVER*/
00081
00082 /* Exported types ------------------------------------------------------------*/
00083 #if defined(USE_FULL_LL_DRIVER)
00084 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00085   * @{
00086   */
00087
00088 /**
00089   * @brief LL USART Init Structure definition
00090   */
00091 typedef struct
00092 {
00093   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00094                                            This parameter can be a value of @ref USART_LL_EC_PRESCALER.
00095
00096                                            This feature can be modified afterwards using unitary
00097                                            function @ref LL_USART_SetPrescaler().*/
00098
00099   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00100
00101                                            This feature can be modified afterwards using unitary
00102                                            function @ref LL_USART_SetBaudRate().*/
00103
00104   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00105                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00106
00107                                            This feature can be modified afterwards using unitary
00108                                            function @ref LL_USART_SetDataWidth().*/
00109
00110   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00111                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00112
00113                                            This feature can be modified afterwards using unitary
00114                                            function @ref LL_USART_SetStopBitsLength().*/
00115
00116   uint32_t Parity;                    /*!< Specifies the parity mode.
00117                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00118
00119                                            This feature can be modified afterwards using unitary
00120                                            function @ref LL_USART_SetParity().*/
00121
00122   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00123                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00124
00125                                            This feature can be modified afterwards using unitary
00126                                            function @ref LL_USART_SetTransferDirection().*/
00127
00128   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00129                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00130
00131                                            This feature can be modified afterwards using unitary
00132                                            function @ref LL_USART_SetHWFlowCtrl().*/
00133
00134   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00135                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00136
00137                                            This feature can be modified afterwards using unitary
00138                                            function @ref LL_USART_SetOverSampling().*/
00139
00140 } LL_USART_InitTypeDef;
00141
00142 /**
00143   * @brief LL USART Clock Init Structure definition
00144   */
00145 typedef struct
00146 {
00147   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00148                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00149
00150                                            USART HW configuration can be modified afterwards using unitary functions
00151                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00152                                            For more details, refer to description of this function. */
00153
00154   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00155                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00156
00157                                            USART HW configuration can be modified afterwards using unitary
00158                                            functions @ref LL_USART_SetClockPolarity().
00159                                            For more details, refer to description of this function. */
00160
00161   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00162                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00163
00164                                            USART HW configuration can be modified afterwards using unitary
00165                                            functions @ref LL_USART_SetClockPhase().
00166                                            For more details, refer to description of this function. */
00167
00168   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00169                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00170                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00171
00172                                            USART HW configuration can be modified afterwards using unitary
00173                                            functions @ref LL_USART_SetLastClkPulseOutput().
00174                                            For more details, refer to description of this function. */
00175
00176 } LL_USART_ClockInitTypeDef;
00177
00178 /**
00179   * @}
00180   */
00181 #endif /* USE_FULL_LL_DRIVER */
00182
00183 /* Exported constants --------------------------------------------------------*/
00184 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00185   * @{
00186   */
00187
00188 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00189   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00190   * @{
00191   */
00192 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
00193 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
00194 #define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
00195 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
00196 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
00197 #define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
00198 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
00199 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
00200 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
00201 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
00202 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
00203 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
00204 #define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
00205 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
00206 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00212   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00213   * @{
00214   */
00215 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00216 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00217 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00218 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00219 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00220 #define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00221 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00222 #define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00223 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00224 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00225 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00226 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00227 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00228 #define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
00229 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00230 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00231 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00232 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00233 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00234 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00235 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00236 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00237 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00238 #define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
00239 #define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
00240 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00241 #define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00242 #define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup USART_LL_EC_IT IT Defines
00248   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00249   * @{
00250   */
00251 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00252 #define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00253 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00254 #define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00255 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00256 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00257 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00258 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00259 #define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00260 #define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00261 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00262 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00263 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00264 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00265 #define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00266 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00267 #define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00273   * @{
00274   */
00275 #define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
00276 #define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
00277 #define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
00278 #define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
00279 #define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
00280 #define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00286   * @{
00287   */
00288 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00289 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00290 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00291 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup USART_LL_EC_PARITY Parity Control
00297   * @{
00298   */
00299 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00300 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00301 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00307   * @{
00308   */
00309 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00310 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00316   * @{
00317   */
00318 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00319 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00320 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00326   * @{
00327   */
00328 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00329 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00330 /**
00331   * @}
00332   */
00333
00334 #if defined(USE_FULL_LL_DRIVER)
00335 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00336   * @{
00337   */
00338
00339 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00340 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00341 /**
00342   * @}
00343   */
00344 #endif /*USE_FULL_LL_DRIVER*/
00345
00346 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00347   * @{
00348   */
00349 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00350 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup USART_LL_EC_PHASE Clock Phase
00356   * @{
00357   */
00358 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00359 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00365   * @{
00366   */
00367 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00368 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
00374   * @{
00375   */
00376 #define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
00377 #define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
00378 #define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
00379 #define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
00380 #define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
00381 #define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
00382 #define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
00383 #define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
00384 #define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
00385 #define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
00386 #define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
00387 #define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00393   * @{
00394   */
00395 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00396 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00397 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00398 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00404   * @{
00405   */
00406 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00407 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00413   * @{
00414   */
00415 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00416 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00422   * @{
00423   */
00424 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00425 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00431   * @{
00432   */
00433 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00434 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup USART_LL_EC_BITORDER Bit Order
00440   * @{
00441   */
00442 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00443 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00449   * @{
00450   */
00451 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00452 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00453 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00454 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00460   * @{
00461   */
00462 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00463 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00469   * @{
00470   */
00471 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00472 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00473 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00474 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00480   * @{
00481   */
00482 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00483 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00484 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00490   * @{
00491   */
00492 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00493 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00499   * @{
00500   */
00501 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00502 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00508   * @{
00509   */
00510 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00511 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00517   * @{
00518   */
00519 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00520 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00521 /**
00522   * @}
00523   */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /* Exported macro ------------------------------------------------------------*/
00530 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00531   * @{
00532   */
00533
00534 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00535   * @{
00536   */
00537
00538 /**
00539   * @brief  Write a value in USART register
00540   * @param  __INSTANCE__ USART Instance
00541   * @param  __REG__ Register to be written
00542   * @param  __VALUE__ Value to be written in the register
00543   * @retval None
00544   */
00545 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00546
00547 /**
00548   * @brief  Read a value in USART register
00549   * @param  __INSTANCE__ USART Instance
00550   * @param  __REG__ Register to be read
00551   * @retval Register value
00552   */
00553 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00559   * @{
00560   */
00561
00562 /**
00563   * @brief  Compute USARTDIV value according to Peripheral Clock and
00564   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00565   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00566   * @param  __PRESCALER__ This parameter can be one of the following values:
00567   *         @arg @ref LL_USART_PRESCALER_DIV1
00568   *         @arg @ref LL_USART_PRESCALER_DIV2
00569   *         @arg @ref LL_USART_PRESCALER_DIV4
00570   *         @arg @ref LL_USART_PRESCALER_DIV6
00571   *         @arg @ref LL_USART_PRESCALER_DIV8
00572   *         @arg @ref LL_USART_PRESCALER_DIV10
00573   *         @arg @ref LL_USART_PRESCALER_DIV12
00574   *         @arg @ref LL_USART_PRESCALER_DIV16
00575   *         @arg @ref LL_USART_PRESCALER_DIV32
00576   *         @arg @ref LL_USART_PRESCALER_DIV64
00577   *         @arg @ref LL_USART_PRESCALER_DIV128
00578   *         @arg @ref LL_USART_PRESCALER_DIV256
00579   * @param  __BAUDRATE__ Baud rate value to achieve
00580   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00581   */
00582 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
00583   (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
00584     + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00585
00586 /**
00587   * @brief  Compute USARTDIV value according to Peripheral Clock and
00588   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00589   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00590   * @param  __PRESCALER__ This parameter can be one of the following values:
00591   *         @arg @ref LL_USART_PRESCALER_DIV1
00592   *         @arg @ref LL_USART_PRESCALER_DIV2
00593   *         @arg @ref LL_USART_PRESCALER_DIV4
00594   *         @arg @ref LL_USART_PRESCALER_DIV6
00595   *         @arg @ref LL_USART_PRESCALER_DIV8
00596   *         @arg @ref LL_USART_PRESCALER_DIV10
00597   *         @arg @ref LL_USART_PRESCALER_DIV12
00598   *         @arg @ref LL_USART_PRESCALER_DIV16
00599   *         @arg @ref LL_USART_PRESCALER_DIV32
00600   *         @arg @ref LL_USART_PRESCALER_DIV64
00601   *         @arg @ref LL_USART_PRESCALER_DIV128
00602   *         @arg @ref LL_USART_PRESCALER_DIV256
00603   * @param  __BAUDRATE__ Baud rate value to achieve
00604   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00605   */
00606 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
00607   ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
00608     + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00609
00610 /**
00611   * @}
00612   */
00613
00614 /**
00615   * @}
00616   */
00617
00618 /* Exported functions --------------------------------------------------------*/
00619
00620 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00621   * @{
00622   */
00623
00624 /** @defgroup USART_LL_EF_Configuration Configuration functions
00625   * @{
00626   */
00627
00628 /**
00629   * @brief  USART Enable
00630   * @rmtoll CR1          UE            LL_USART_Enable
00631   * @param  USARTx USART Instance
00632   * @retval None
00633   */
00634 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00635 {
00636   SET_BIT(USARTx->CR1, USART_CR1_UE);
00637 }
00638
00639 /**
00640   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00641   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00642   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00643   *         flags, in the USARTx_ISR are set to their default values.
00644   * @rmtoll CR1          UE            LL_USART_Disable
00645   * @param  USARTx USART Instance
00646   * @retval None
00647   */
00648 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00649 {
00650   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00651 }
00652
00653 /**
00654   * @brief  Indicate if USART is enabled
00655   * @rmtoll CR1          UE            LL_USART_IsEnabled
00656   * @param  USARTx USART Instance
00657   * @retval State of bit (1 or 0).
00658   */
00659 __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
00660 {
00661   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00662 }
00663
00664 /**
00665   * @brief  FIFO Mode Enable
00666   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00667   *         FIFO mode feature is supported by the USARTx instance.
00668   * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
00669   * @param  USARTx USART Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
00673 {
00674   SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00675 }
00676
00677 /**
00678   * @brief  FIFO Mode Disable
00679   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00680   *         FIFO mode feature is supported by the USARTx instance.
00681   * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
00682   * @param  USARTx USART Instance
00683   * @retval None
00684   */
00685 __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
00686 {
00687   CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00688 }
00689
00690 /**
00691   * @brief  Indicate if FIFO Mode is enabled
00692   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00693   *         FIFO mode feature is supported by the USARTx instance.
00694   * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
00695   * @param  USARTx USART Instance
00696   * @retval State of bit (1 or 0).
00697   */
00698 __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
00699 {
00700   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00701 }
00702
00703 /**
00704   * @brief  Configure TX FIFO Threshold
00705   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00706   *         FIFO mode feature is supported by the USARTx instance.
00707   * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
00708   * @param  USARTx USART Instance
00709   * @param  Threshold This parameter can be one of the following values:
00710   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00711   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00712   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00713   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00714   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00715   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00716   * @retval None
00717   */
00718 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00719 {
00720   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00721 }
00722
00723 /**
00724   * @brief  Return TX FIFO Threshold Configuration
00725   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00726   *         FIFO mode feature is supported by the USARTx instance.
00727   * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
00728   * @param  USARTx USART Instance
00729   * @retval Returned value can be one of the following values:
00730   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00731   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00732   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00733   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00734   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00735   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00736   */
00737 __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
00738 {
00739   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00740 }
00741
00742 /**
00743   * @brief  Configure RX FIFO Threshold
00744   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00745   *         FIFO mode feature is supported by the USARTx instance.
00746   * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
00747   * @param  USARTx USART Instance
00748   * @param  Threshold This parameter can be one of the following values:
00749   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00750   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00751   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00752   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00753   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00754   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00755   * @retval None
00756   */
00757 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00758 {
00759   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00760 }
00761
00762 /**
00763   * @brief  Return RX FIFO Threshold Configuration
00764   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00765   *         FIFO mode feature is supported by the USARTx instance.
00766   * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
00767   * @param  USARTx USART Instance
00768   * @retval Returned value can be one of the following values:
00769   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00770   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00771   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00772   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00773   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00774   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00775   */
00776 __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
00777 {
00778   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00779 }
00780
00781 /**
00782   * @brief  Configure TX and RX FIFOs Threshold
00783   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00784   *         FIFO mode feature is supported by the USARTx instance.
00785   * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
00786   *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
00787   * @param  USARTx USART Instance
00788   * @param  TXThreshold This parameter can be one of the following values:
00789   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00790   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00791   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00792   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00793   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00794   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00795   * @param  RXThreshold This parameter can be one of the following values:
00796   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00797   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00798   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00799   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00800   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00801   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00805 {
00806   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
00807                     (RXThreshold << USART_CR3_RXFTCFG_Pos));
00808 }
00809
00810 /**
00811   * @brief  USART enabled in STOP Mode.
00812   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00813   *         USART clock selection is HSI or LSE in RCC.
00814   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00815   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00816   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00817   * @param  USARTx USART Instance
00818   * @retval None
00819   */
00820 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00821 {
00822   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
00823 }
00824
00825 /**
00826   * @brief  USART disabled in STOP Mode.
00827   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00828   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00829   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00830   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00831   * @param  USARTx USART Instance
00832   * @retval None
00833   */
00834 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00835 {
00836   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00837 }
00838
00839 /**
00840   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00841   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00842   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00843   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00844   * @param  USARTx USART Instance
00845   * @retval State of bit (1 or 0).
00846   */
00847 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
00848 {
00849   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00850 }
00851
00852 /**
00853   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00854   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00855   * @param  USARTx USART Instance
00856   * @retval None
00857   */
00858 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00859 {
00860   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
00861 }
00862
00863 /**
00864   * @brief  Receiver Disable
00865   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00866   * @param  USARTx USART Instance
00867   * @retval None
00868   */
00869 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00870 {
00871   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00872 }
00873
00874 /**
00875   * @brief  Transmitter Enable
00876   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00877   * @param  USARTx USART Instance
00878   * @retval None
00879   */
00880 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00881 {
00882   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
00883 }
00884
00885 /**
00886   * @brief  Transmitter Disable
00887   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00888   * @param  USARTx USART Instance
00889   * @retval None
00890   */
00891 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00892 {
00893   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00894 }
00895
00896 /**
00897   * @brief  Configure simultaneously enabled/disabled states
00898   *         of Transmitter and Receiver
00899   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00900   *         CR1          TE            LL_USART_SetTransferDirection
00901   * @param  USARTx USART Instance
00902   * @param  TransferDirection This parameter can be one of the following values:
00903   *         @arg @ref LL_USART_DIRECTION_NONE
00904   *         @arg @ref LL_USART_DIRECTION_RX
00905   *         @arg @ref LL_USART_DIRECTION_TX
00906   *         @arg @ref LL_USART_DIRECTION_TX_RX
00907   * @retval None
00908   */
00909 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00910 {
00911   ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00912 }
00913
00914 /**
00915   * @brief  Return enabled/disabled states of Transmitter and Receiver
00916   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00917   *         CR1          TE            LL_USART_GetTransferDirection
00918   * @param  USARTx USART Instance
00919   * @retval Returned value can be one of the following values:
00920   *         @arg @ref LL_USART_DIRECTION_NONE
00921   *         @arg @ref LL_USART_DIRECTION_RX
00922   *         @arg @ref LL_USART_DIRECTION_TX
00923   *         @arg @ref LL_USART_DIRECTION_TX_RX
00924   */
00925 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
00926 {
00927   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00928 }
00929
00930 /**
00931   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00932   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00933   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00934   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00935   * @rmtoll CR1          PS            LL_USART_SetParity\n
00936   *         CR1          PCE           LL_USART_SetParity
00937   * @param  USARTx USART Instance
00938   * @param  Parity This parameter can be one of the following values:
00939   *         @arg @ref LL_USART_PARITY_NONE
00940   *         @arg @ref LL_USART_PARITY_EVEN
00941   *         @arg @ref LL_USART_PARITY_ODD
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00945 {
00946   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00947 }
00948
00949 /**
00950   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00951   * @rmtoll CR1          PS            LL_USART_GetParity\n
00952   *         CR1          PCE           LL_USART_GetParity
00953   * @param  USARTx USART Instance
00954   * @retval Returned value can be one of the following values:
00955   *         @arg @ref LL_USART_PARITY_NONE
00956   *         @arg @ref LL_USART_PARITY_EVEN
00957   *         @arg @ref LL_USART_PARITY_ODD
00958   */
00959 __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
00960 {
00961   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00962 }
00963
00964 /**
00965   * @brief  Set Receiver Wake Up method from Mute mode.
00966   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00967   * @param  USARTx USART Instance
00968   * @param  Method This parameter can be one of the following values:
00969   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00970   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00971   * @retval None
00972   */
00973 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00974 {
00975   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00976 }
00977
00978 /**
00979   * @brief  Return Receiver Wake Up method from Mute mode
00980   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00981   * @param  USARTx USART Instance
00982   * @retval Returned value can be one of the following values:
00983   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00984   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00985   */
00986 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
00987 {
00988   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00989 }
00990
00991 /**
00992   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00993   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00994   *         CR1          M1            LL_USART_SetDataWidth
00995   * @param  USARTx USART Instance
00996   * @param  DataWidth This parameter can be one of the following values:
00997   *         @arg @ref LL_USART_DATAWIDTH_7B
00998   *         @arg @ref LL_USART_DATAWIDTH_8B
00999   *         @arg @ref LL_USART_DATAWIDTH_9B
01000   * @retval None
01001   */
01002 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
01003 {
01004   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
01005 }
01006
01007 /**
01008   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
01009   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
01010   *         CR1          M1            LL_USART_GetDataWidth
01011   * @param  USARTx USART Instance
01012   * @retval Returned value can be one of the following values:
01013   *         @arg @ref LL_USART_DATAWIDTH_7B
01014   *         @arg @ref LL_USART_DATAWIDTH_8B
01015   *         @arg @ref LL_USART_DATAWIDTH_9B
01016   */
01017 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
01018 {
01019   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
01020 }
01021
01022 /**
01023   * @brief  Allow switch between Mute Mode and Active mode
01024   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
01025   * @param  USARTx USART Instance
01026   * @retval None
01027   */
01028 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
01029 {
01030   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
01031 }
01032
01033 /**
01034   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
01035   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
01036   * @param  USARTx USART Instance
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
01040 {
01041   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
01042 }
01043
01044 /**
01045   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
01046   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
01047   * @param  USARTx USART Instance
01048   * @retval State of bit (1 or 0).
01049   */
01050 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
01051 {
01052   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
01053 }
01054
01055 /**
01056   * @brief  Set Oversampling to 8-bit or 16-bit mode
01057   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
01058   * @param  USARTx USART Instance
01059   * @param  OverSampling This parameter can be one of the following values:
01060   *         @arg @ref LL_USART_OVERSAMPLING_16
01061   *         @arg @ref LL_USART_OVERSAMPLING_8
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
01065 {
01066   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
01067 }
01068
01069 /**
01070   * @brief  Return Oversampling mode
01071   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
01072   * @param  USARTx USART Instance
01073   * @retval Returned value can be one of the following values:
01074   *         @arg @ref LL_USART_OVERSAMPLING_16
01075   *         @arg @ref LL_USART_OVERSAMPLING_8
01076   */
01077 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
01078 {
01079   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
01080 }
01081
01082 /**
01083   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
01084   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01085   *         Synchronous mode is supported by the USARTx instance.
01086   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
01087   * @param  USARTx USART Instance
01088   * @param  LastBitClockPulse This parameter can be one of the following values:
01089   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01090   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01091   * @retval None
01092   */
01093 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
01094 {
01095   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
01096 }
01097
01098 /**
01099   * @brief  Retrieve Clock pulse of the last data bit output configuration
01100   *         (Last bit Clock pulse output to the SCLK pin or not)
01101   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01102   *         Synchronous mode is supported by the USARTx instance.
01103   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
01104   * @param  USARTx USART Instance
01105   * @retval Returned value can be one of the following values:
01106   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01107   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01108   */
01109 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
01110 {
01111   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
01112 }
01113
01114 /**
01115   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
01116   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01117   *         Synchronous mode is supported by the USARTx instance.
01118   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
01119   * @param  USARTx USART Instance
01120   * @param  ClockPhase This parameter can be one of the following values:
01121   *         @arg @ref LL_USART_PHASE_1EDGE
01122   *         @arg @ref LL_USART_PHASE_2EDGE
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
01126 {
01127   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
01128 }
01129
01130 /**
01131   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
01132   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01133   *         Synchronous mode is supported by the USARTx instance.
01134   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
01135   * @param  USARTx USART Instance
01136   * @retval Returned value can be one of the following values:
01137   *         @arg @ref LL_USART_PHASE_1EDGE
01138   *         @arg @ref LL_USART_PHASE_2EDGE
01139   */
01140 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
01141 {
01142   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
01143 }
01144
01145 /**
01146   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
01147   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01148   *         Synchronous mode is supported by the USARTx instance.
01149   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
01150   * @param  USARTx USART Instance
01151   * @param  ClockPolarity This parameter can be one of the following values:
01152   *         @arg @ref LL_USART_POLARITY_LOW
01153   *         @arg @ref LL_USART_POLARITY_HIGH
01154   * @retval None
01155   */
01156 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
01157 {
01158   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
01159 }
01160
01161 /**
01162   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
01163   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01164   *         Synchronous mode is supported by the USARTx instance.
01165   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
01166   * @param  USARTx USART Instance
01167   * @retval Returned value can be one of the following values:
01168   *         @arg @ref LL_USART_POLARITY_LOW
01169   *         @arg @ref LL_USART_POLARITY_HIGH
01170   */
01171 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
01172 {
01173   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
01174 }
01175
01176 /**
01177   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
01178   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01179   *         Synchronous mode is supported by the USARTx instance.
01180   * @note   Call of this function is equivalent to following function call sequence :
01181   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
01182   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
01183   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
01184   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
01185   *         CR2          CPOL          LL_USART_ConfigClock\n
01186   *         CR2          LBCL          LL_USART_ConfigClock
01187   * @param  USARTx USART Instance
01188   * @param  Phase This parameter can be one of the following values:
01189   *         @arg @ref LL_USART_PHASE_1EDGE
01190   *         @arg @ref LL_USART_PHASE_2EDGE
01191   * @param  Polarity This parameter can be one of the following values:
01192   *         @arg @ref LL_USART_POLARITY_LOW
01193   *         @arg @ref LL_USART_POLARITY_HIGH
01194   * @param  LBCPOutput This parameter can be one of the following values:
01195   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01196   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01197   * @retval None
01198   */
01199 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
01200 {
01201   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
01202 }
01203
01204 /**
01205   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
01206   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01207   *         FIFO mode feature is supported by the USARTx instance.
01208   * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
01209   * @param  USARTx USART Instance
01210   * @param  PrescalerValue This parameter can be one of the following values:
01211   *         @arg @ref LL_USART_PRESCALER_DIV1
01212   *         @arg @ref LL_USART_PRESCALER_DIV2
01213   *         @arg @ref LL_USART_PRESCALER_DIV4
01214   *         @arg @ref LL_USART_PRESCALER_DIV6
01215   *         @arg @ref LL_USART_PRESCALER_DIV8
01216   *         @arg @ref LL_USART_PRESCALER_DIV10
01217   *         @arg @ref LL_USART_PRESCALER_DIV12
01218   *         @arg @ref LL_USART_PRESCALER_DIV16
01219   *         @arg @ref LL_USART_PRESCALER_DIV32
01220   *         @arg @ref LL_USART_PRESCALER_DIV64
01221   *         @arg @ref LL_USART_PRESCALER_DIV128
01222   *         @arg @ref LL_USART_PRESCALER_DIV256
01223   * @retval None
01224   */
01225 __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01226 {
01227   MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
01228 }
01229
01230 /**
01231   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
01232   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01233   *         FIFO mode feature is supported by the USARTx instance.
01234   * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
01235   * @param  USARTx USART Instance
01236   * @retval Returned value can be one of the following values:
01237   *         @arg @ref LL_USART_PRESCALER_DIV1
01238   *         @arg @ref LL_USART_PRESCALER_DIV2
01239   *         @arg @ref LL_USART_PRESCALER_DIV4
01240   *         @arg @ref LL_USART_PRESCALER_DIV6
01241   *         @arg @ref LL_USART_PRESCALER_DIV8
01242   *         @arg @ref LL_USART_PRESCALER_DIV10
01243   *         @arg @ref LL_USART_PRESCALER_DIV12
01244   *         @arg @ref LL_USART_PRESCALER_DIV16
01245   *         @arg @ref LL_USART_PRESCALER_DIV32
01246   *         @arg @ref LL_USART_PRESCALER_DIV64
01247   *         @arg @ref LL_USART_PRESCALER_DIV128
01248   *         @arg @ref LL_USART_PRESCALER_DIV256
01249   */
01250 __STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
01251 {
01252   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
01253 }
01254
01255 /**
01256   * @brief  Enable Clock output on SCLK pin
01257   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01258   *         Synchronous mode is supported by the USARTx instance.
01259   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
01260   * @param  USARTx USART Instance
01261   * @retval None
01262   */
01263 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
01264 {
01265   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01266 }
01267
01268 /**
01269   * @brief  Disable Clock output on SCLK pin
01270   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01271   *         Synchronous mode is supported by the USARTx instance.
01272   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
01273   * @param  USARTx USART Instance
01274   * @retval None
01275   */
01276 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01277 {
01278   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01279 }
01280
01281 /**
01282   * @brief  Indicate if Clock output on SCLK pin is enabled
01283   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01284   *         Synchronous mode is supported by the USARTx instance.
01285   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01286   * @param  USARTx USART Instance
01287   * @retval State of bit (1 or 0).
01288   */
01289 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
01290 {
01291   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
01292 }
01293
01294 /**
01295   * @brief  Set the length of the stop bits
01296   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01297   * @param  USARTx USART Instance
01298   * @param  StopBits This parameter can be one of the following values:
01299   *         @arg @ref LL_USART_STOPBITS_0_5
01300   *         @arg @ref LL_USART_STOPBITS_1
01301   *         @arg @ref LL_USART_STOPBITS_1_5
01302   *         @arg @ref LL_USART_STOPBITS_2
01303   * @retval None
01304   */
01305 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01306 {
01307   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01308 }
01309
01310 /**
01311   * @brief  Retrieve the length of the stop bits
01312   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01313   * @param  USARTx USART Instance
01314   * @retval Returned value can be one of the following values:
01315   *         @arg @ref LL_USART_STOPBITS_0_5
01316   *         @arg @ref LL_USART_STOPBITS_1
01317   *         @arg @ref LL_USART_STOPBITS_1_5
01318   *         @arg @ref LL_USART_STOPBITS_2
01319   */
01320 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
01321 {
01322   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01323 }
01324
01325 /**
01326   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01327   * @note   Call of this function is equivalent to following function call sequence :
01328   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01329   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01330   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01331   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01332   *         CR1          PCE           LL_USART_ConfigCharacter\n
01333   *         CR1          M0            LL_USART_ConfigCharacter\n
01334   *         CR1          M1            LL_USART_ConfigCharacter\n
01335   *         CR2          STOP          LL_USART_ConfigCharacter
01336   * @param  USARTx USART Instance
01337   * @param  DataWidth This parameter can be one of the following values:
01338   *         @arg @ref LL_USART_DATAWIDTH_7B
01339   *         @arg @ref LL_USART_DATAWIDTH_8B
01340   *         @arg @ref LL_USART_DATAWIDTH_9B
01341   * @param  Parity This parameter can be one of the following values:
01342   *         @arg @ref LL_USART_PARITY_NONE
01343   *         @arg @ref LL_USART_PARITY_EVEN
01344   *         @arg @ref LL_USART_PARITY_ODD
01345   * @param  StopBits This parameter can be one of the following values:
01346   *         @arg @ref LL_USART_STOPBITS_0_5
01347   *         @arg @ref LL_USART_STOPBITS_1
01348   *         @arg @ref LL_USART_STOPBITS_1_5
01349   *         @arg @ref LL_USART_STOPBITS_2
01350   * @retval None
01351   */
01352 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01353                                               uint32_t StopBits)
01354 {
01355   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01356   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01357 }
01358
01359 /**
01360   * @brief  Configure TX/RX pins swapping setting.
01361   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01362   * @param  USARTx USART Instance
01363   * @param  SwapConfig This parameter can be one of the following values:
01364   *         @arg @ref LL_USART_TXRX_STANDARD
01365   *         @arg @ref LL_USART_TXRX_SWAPPED
01366   * @retval None
01367   */
01368 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01369 {
01370   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01371 }
01372
01373 /**
01374   * @brief  Retrieve TX/RX pins swapping configuration.
01375   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01376   * @param  USARTx USART Instance
01377   * @retval Returned value can be one of the following values:
01378   *         @arg @ref LL_USART_TXRX_STANDARD
01379   *         @arg @ref LL_USART_TXRX_SWAPPED
01380   */
01381 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
01382 {
01383   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01384 }
01385
01386 /**
01387   * @brief  Configure RX pin active level logic
01388   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01389   * @param  USARTx USART Instance
01390   * @param  PinInvMethod This parameter can be one of the following values:
01391   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01392   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01393   * @retval None
01394   */
01395 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01396 {
01397   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01398 }
01399
01400 /**
01401   * @brief  Retrieve RX pin active level logic configuration
01402   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01403   * @param  USARTx USART Instance
01404   * @retval Returned value can be one of the following values:
01405   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01406   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01407   */
01408 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
01409 {
01410   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01411 }
01412
01413 /**
01414   * @brief  Configure TX pin active level logic
01415   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01416   * @param  USARTx USART Instance
01417   * @param  PinInvMethod This parameter can be one of the following values:
01418   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01419   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01420   * @retval None
01421   */
01422 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01423 {
01424   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01425 }
01426
01427 /**
01428   * @brief  Retrieve TX pin active level logic configuration
01429   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01430   * @param  USARTx USART Instance
01431   * @retval Returned value can be one of the following values:
01432   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01433   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01434   */
01435 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
01436 {
01437   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01438 }
01439
01440 /**
01441   * @brief  Configure Binary data logic.
01442   * @note   Allow to define how Logical data from the data register are send/received :
01443   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01444   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01445   * @param  USARTx USART Instance
01446   * @param  DataLogic This parameter can be one of the following values:
01447   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01448   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01449   * @retval None
01450   */
01451 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01452 {
01453   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01454 }
01455
01456 /**
01457   * @brief  Retrieve Binary data configuration
01458   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01459   * @param  USARTx USART Instance
01460   * @retval Returned value can be one of the following values:
01461   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01462   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01463   */
01464 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
01465 {
01466   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01467 }
01468
01469 /**
01470   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01471   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01472   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01473   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01474   * @param  USARTx USART Instance
01475   * @param  BitOrder This parameter can be one of the following values:
01476   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01477   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01478   * @retval None
01479   */
01480 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01481 {
01482   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01483 }
01484
01485 /**
01486   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01487   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01488   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01489   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01490   * @param  USARTx USART Instance
01491   * @retval Returned value can be one of the following values:
01492   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01493   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01494   */
01495 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
01496 {
01497   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01498 }
01499
01500 /**
01501   * @brief  Enable Auto Baud-Rate Detection
01502   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01503   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01504   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01505   * @param  USARTx USART Instance
01506   * @retval None
01507   */
01508 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01509 {
01510   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01511 }
01512
01513 /**
01514   * @brief  Disable Auto Baud-Rate Detection
01515   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01516   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01517   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01518   * @param  USARTx USART Instance
01519   * @retval None
01520   */
01521 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01522 {
01523   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01524 }
01525
01526 /**
01527   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01528   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01529   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01530   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01531   * @param  USARTx USART Instance
01532   * @retval State of bit (1 or 0).
01533   */
01534 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
01535 {
01536   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
01537 }
01538
01539 /**
01540   * @brief  Set Auto Baud-Rate mode bits
01541   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01542   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01543   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01544   * @param  USARTx USART Instance
01545   * @param  AutoBaudRateMode This parameter can be one of the following values:
01546   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01547   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01548   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01549   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01550   * @retval None
01551   */
01552 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01553 {
01554   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01555 }
01556
01557 /**
01558   * @brief  Return Auto Baud-Rate mode
01559   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01560   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01561   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01562   * @param  USARTx USART Instance
01563   * @retval Returned value can be one of the following values:
01564   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01565   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01566   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01567   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01568   */
01569 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
01570 {
01571   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01572 }
01573
01574 /**
01575   * @brief  Enable Receiver Timeout
01576   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01577   * @param  USARTx USART Instance
01578   * @retval None
01579   */
01580 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01581 {
01582   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01583 }
01584
01585 /**
01586   * @brief  Disable Receiver Timeout
01587   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01588   * @param  USARTx USART Instance
01589   * @retval None
01590   */
01591 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01592 {
01593   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01594 }
01595
01596 /**
01597   * @brief  Indicate if Receiver Timeout feature is enabled
01598   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01599   * @param  USARTx USART Instance
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
01603 {
01604   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Set Address of the USART node.
01609   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01610   *         for wake up with address mark detection.
01611   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01612   *         (b7-b4 should be set to 0)
01613   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01614   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01615   *         for wake up with 7-bit address mark detection.
01616   *         The MSB of the character sent by the transmitter should be equal to 1.
01617   *         It may also be used for character detection during normal reception,
01618   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01619   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01620   *         value and CMF flag is set on match)
01621   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01622   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01623   * @param  USARTx USART Instance
01624   * @param  AddressLen This parameter can be one of the following values:
01625   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01626   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01627   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01628   * @retval None
01629   */
01630 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01631 {
01632   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01633              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01634 }
01635
01636 /**
01637   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01638   * @note   If 4-bit Address Detection is selected in ADDM7,
01639   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01640   *         If 7-bit Address Detection is selected in ADDM7,
01641   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01642   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01643   * @param  USARTx USART Instance
01644   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01645   */
01646 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
01647 {
01648   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01649 }
01650
01651 /**
01652   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01653   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01654   * @param  USARTx USART Instance
01655   * @retval Returned value can be one of the following values:
01656   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01657   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01658   */
01659 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
01660 {
01661   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01662 }
01663
01664 /**
01665   * @brief  Enable RTS HW Flow Control
01666   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01667   *         Hardware Flow control feature is supported by the USARTx instance.
01668   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01669   * @param  USARTx USART Instance
01670   * @retval None
01671   */
01672 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01673 {
01674   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01675 }
01676
01677 /**
01678   * @brief  Disable RTS HW Flow Control
01679   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01680   *         Hardware Flow control feature is supported by the USARTx instance.
01681   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01682   * @param  USARTx USART Instance
01683   * @retval None
01684   */
01685 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01686 {
01687   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01688 }
01689
01690 /**
01691   * @brief  Enable CTS HW Flow Control
01692   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01693   *         Hardware Flow control feature is supported by the USARTx instance.
01694   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01695   * @param  USARTx USART Instance
01696   * @retval None
01697   */
01698 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01699 {
01700   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01701 }
01702
01703 /**
01704   * @brief  Disable CTS HW Flow Control
01705   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01706   *         Hardware Flow control feature is supported by the USARTx instance.
01707   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01708   * @param  USARTx USART Instance
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01712 {
01713   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01714 }
01715
01716 /**
01717   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01718   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01719   *         Hardware Flow control feature is supported by the USARTx instance.
01720   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01721   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01722   * @param  USARTx USART Instance
01723   * @param  HardwareFlowControl This parameter can be one of the following values:
01724   *         @arg @ref LL_USART_HWCONTROL_NONE
01725   *         @arg @ref LL_USART_HWCONTROL_RTS
01726   *         @arg @ref LL_USART_HWCONTROL_CTS
01727   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01728   * @retval None
01729   */
01730 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01731 {
01732   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01733 }
01734
01735 /**
01736   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01737   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01738   *         Hardware Flow control feature is supported by the USARTx instance.
01739   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01740   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01741   * @param  USARTx USART Instance
01742   * @retval Returned value can be one of the following values:
01743   *         @arg @ref LL_USART_HWCONTROL_NONE
01744   *         @arg @ref LL_USART_HWCONTROL_RTS
01745   *         @arg @ref LL_USART_HWCONTROL_CTS
01746   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01747   */
01748 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
01749 {
01750   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01751 }
01752
01753 /**
01754   * @brief  Enable One bit sampling method
01755   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01756   * @param  USARTx USART Instance
01757   * @retval None
01758   */
01759 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01760 {
01761   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01762 }
01763
01764 /**
01765   * @brief  Disable One bit sampling method
01766   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01767   * @param  USARTx USART Instance
01768   * @retval None
01769   */
01770 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01771 {
01772   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01773 }
01774
01775 /**
01776   * @brief  Indicate if One bit sampling method is enabled
01777   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01778   * @param  USARTx USART Instance
01779   * @retval State of bit (1 or 0).
01780   */
01781 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
01782 {
01783   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
01784 }
01785
01786 /**
01787   * @brief  Enable Overrun detection
01788   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01789   * @param  USARTx USART Instance
01790   * @retval None
01791   */
01792 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01793 {
01794   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01795 }
01796
01797 /**
01798   * @brief  Disable Overrun detection
01799   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01800   * @param  USARTx USART Instance
01801   * @retval None
01802   */
01803 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01804 {
01805   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01806 }
01807
01808 /**
01809   * @brief  Indicate if Overrun detection is enabled
01810   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01811   * @param  USARTx USART Instance
01812   * @retval State of bit (1 or 0).
01813   */
01814 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
01815 {
01816   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01817 }
01818
01819 /**
01820   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01821   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01822   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01823   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01824   * @param  USARTx USART Instance
01825   * @param  Type This parameter can be one of the following values:
01826   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01827   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01828   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01832 {
01833   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01834 }
01835
01836 /**
01837   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01838   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01839   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01840   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01841   * @param  USARTx USART Instance
01842   * @retval Returned value can be one of the following values:
01843   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01844   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01845   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01846   */
01847 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
01848 {
01849   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01850 }
01851
01852 /**
01853   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01854   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01855   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01856   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01857   *         (Baud rate value != 0)
01858   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01859   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01860   * @param  USARTx USART Instance
01861   * @param  PeriphClk Peripheral Clock
01862   * @param  PrescalerValue This parameter can be one of the following values:
01863   *         @arg @ref LL_USART_PRESCALER_DIV1
01864   *         @arg @ref LL_USART_PRESCALER_DIV2
01865   *         @arg @ref LL_USART_PRESCALER_DIV4
01866   *         @arg @ref LL_USART_PRESCALER_DIV6
01867   *         @arg @ref LL_USART_PRESCALER_DIV8
01868   *         @arg @ref LL_USART_PRESCALER_DIV10
01869   *         @arg @ref LL_USART_PRESCALER_DIV12
01870   *         @arg @ref LL_USART_PRESCALER_DIV16
01871   *         @arg @ref LL_USART_PRESCALER_DIV32
01872   *         @arg @ref LL_USART_PRESCALER_DIV64
01873   *         @arg @ref LL_USART_PRESCALER_DIV128
01874   *         @arg @ref LL_USART_PRESCALER_DIV256
01875   * @param  OverSampling This parameter can be one of the following values:
01876   *         @arg @ref LL_USART_OVERSAMPLING_16
01877   *         @arg @ref LL_USART_OVERSAMPLING_8
01878   * @param  BaudRate Baud Rate
01879   * @retval None
01880   */
01881 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01882                                           uint32_t OverSampling,
01883                                           uint32_t BaudRate)
01884 {
01885   uint32_t usartdiv;
01886   uint32_t brrtemp;
01887
01888   if (PrescalerValue > LL_USART_PRESCALER_DIV256)
01889   {
01890     /* Do not overstep the size of USART_PRESCALER_TAB */
01891   }
01892   else if (BaudRate == 0U)
01893   {
01894     /* Can Not divide per 0 */
01895   }
01896   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01897   {
01898     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01899     brrtemp = usartdiv & 0xFFF0U;
01900     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01901     USARTx->BRR = brrtemp;
01902   }
01903   else
01904   {
01905     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01906   }
01907 }
01908
01909 /**
01910   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01911   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01912   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01913   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01914   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01915   * @param  USARTx USART Instance
01916   * @param  PeriphClk Peripheral Clock
01917   * @param  PrescalerValue This parameter can be one of the following values:
01918   *         @arg @ref LL_USART_PRESCALER_DIV1
01919   *         @arg @ref LL_USART_PRESCALER_DIV2
01920   *         @arg @ref LL_USART_PRESCALER_DIV4
01921   *         @arg @ref LL_USART_PRESCALER_DIV6
01922   *         @arg @ref LL_USART_PRESCALER_DIV8
01923   *         @arg @ref LL_USART_PRESCALER_DIV10
01924   *         @arg @ref LL_USART_PRESCALER_DIV12
01925   *         @arg @ref LL_USART_PRESCALER_DIV16
01926   *         @arg @ref LL_USART_PRESCALER_DIV32
01927   *         @arg @ref LL_USART_PRESCALER_DIV64
01928   *         @arg @ref LL_USART_PRESCALER_DIV128
01929   *         @arg @ref LL_USART_PRESCALER_DIV256
01930   * @param  OverSampling This parameter can be one of the following values:
01931   *         @arg @ref LL_USART_OVERSAMPLING_16
01932   *         @arg @ref LL_USART_OVERSAMPLING_8
01933   * @retval Baud Rate
01934   */
01935 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01936                                               uint32_t OverSampling)
01937 {
01938   uint32_t usartdiv;
01939   uint32_t brrresult = 0x0U;
01940   uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
01941
01942   usartdiv = USARTx->BRR;
01943
01944   if (usartdiv == 0U)
01945   {
01946     /* Do not perform a division by 0 */
01947   }
01948   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01949   {
01950     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01951     if (usartdiv != 0U)
01952     {
01953       brrresult = (periphclkpresc * 2U) / usartdiv;
01954     }
01955   }
01956   else
01957   {
01958     if ((usartdiv & 0xFFFFU) != 0U)
01959     {
01960       brrresult = periphclkpresc / usartdiv;
01961     }
01962   }
01963   return (brrresult);
01964 }
01965
01966 /**
01967   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01968   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01969   * @param  USARTx USART Instance
01970   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01974 {
01975   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01976 }
01977
01978 /**
01979   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01980   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01981   * @param  USARTx USART Instance
01982   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01983   */
01984 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
01985 {
01986   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01987 }
01988
01989 /**
01990   * @brief  Set Block Length value in reception
01991   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01992   * @param  USARTx USART Instance
01993   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01994   * @retval None
01995   */
01996 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01997 {
01998   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01999 }
02000
02001 /**
02002   * @brief  Get Block Length value in reception
02003   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
02004   * @param  USARTx USART Instance
02005   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02006   */
02007 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
02008 {
02009   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
02010 }
02011
02012 /**
02013   * @}
02014   */
02015
02016 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
02017   * @{
02018   */
02019
02020 /**
02021   * @brief  Enable IrDA mode
02022   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02023   *         IrDA feature is supported by the USARTx instance.
02024   * @rmtoll CR3          IREN          LL_USART_EnableIrda
02025   * @param  USARTx USART Instance
02026   * @retval None
02027   */
02028 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
02029 {
02030   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02031 }
02032
02033 /**
02034   * @brief  Disable IrDA mode
02035   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02036   *         IrDA feature is supported by the USARTx instance.
02037   * @rmtoll CR3          IREN          LL_USART_DisableIrda
02038   * @param  USARTx USART Instance
02039   * @retval None
02040   */
02041 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
02042 {
02043   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
02044 }
02045
02046 /**
02047   * @brief  Indicate if IrDA mode is enabled
02048   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02049   *         IrDA feature is supported by the USARTx instance.
02050   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
02051   * @param  USARTx USART Instance
02052   * @retval State of bit (1 or 0).
02053   */
02054 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
02055 {
02056   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
02057 }
02058
02059 /**
02060   * @brief  Configure IrDA Power Mode (Normal or Low Power)
02061   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02062   *         IrDA feature is supported by the USARTx instance.
02063   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
02064   * @param  USARTx USART Instance
02065   * @param  PowerMode This parameter can be one of the following values:
02066   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02067   *         @arg @ref LL_USART_IRDA_POWER_LOW
02068   * @retval None
02069   */
02070 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
02071 {
02072   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
02073 }
02074
02075 /**
02076   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
02077   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02078   *         IrDA feature is supported by the USARTx instance.
02079   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
02080   * @param  USARTx USART Instance
02081   * @retval Returned value can be one of the following values:
02082   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02083   *         @arg @ref LL_USART_PHASE_2EDGE
02084   */
02085 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
02086 {
02087   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
02088 }
02089
02090 /**
02091   * @brief  Set Irda prescaler value, used for dividing the USART clock source
02092   *         to achieve the Irda Low Power frequency (8 bits value)
02093   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02094   *         IrDA feature is supported by the USARTx instance.
02095   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
02096   * @param  USARTx USART Instance
02097   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
02098   * @retval None
02099   */
02100 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02101 {
02102   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02103 }
02104
02105 /**
02106   * @brief  Return Irda prescaler value, used for dividing the USART clock source
02107   *         to achieve the Irda Low Power frequency (8 bits value)
02108   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02109   *         IrDA feature is supported by the USARTx instance.
02110   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
02111   * @param  USARTx USART Instance
02112   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
02113   */
02114 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
02115 {
02116   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02117 }
02118
02119 /**
02120   * @}
02121   */
02122
02123 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
02124   * @{
02125   */
02126
02127 /**
02128   * @brief  Enable Smartcard NACK transmission
02129   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02130   *         Smartcard feature is supported by the USARTx instance.
02131   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
02132   * @param  USARTx USART Instance
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
02136 {
02137   SET_BIT(USARTx->CR3, USART_CR3_NACK);
02138 }
02139
02140 /**
02141   * @brief  Disable Smartcard NACK transmission
02142   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02143   *         Smartcard feature is supported by the USARTx instance.
02144   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
02145   * @param  USARTx USART Instance
02146   * @retval None
02147   */
02148 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
02149 {
02150   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
02151 }
02152
02153 /**
02154   * @brief  Indicate if Smartcard NACK transmission is enabled
02155   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02156   *         Smartcard feature is supported by the USARTx instance.
02157   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
02158   * @param  USARTx USART Instance
02159   * @retval State of bit (1 or 0).
02160   */
02161 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
02162 {
02163   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
02164 }
02165
02166 /**
02167   * @brief  Enable Smartcard mode
02168   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02169   *         Smartcard feature is supported by the USARTx instance.
02170   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
02171   * @param  USARTx USART Instance
02172   * @retval None
02173   */
02174 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
02175 {
02176   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02177 }
02178
02179 /**
02180   * @brief  Disable Smartcard mode
02181   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02182   *         Smartcard feature is supported by the USARTx instance.
02183   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
02184   * @param  USARTx USART Instance
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
02188 {
02189   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
02190 }
02191
02192 /**
02193   * @brief  Indicate if Smartcard mode is enabled
02194   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02195   *         Smartcard feature is supported by the USARTx instance.
02196   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
02197   * @param  USARTx USART Instance
02198   * @retval State of bit (1 or 0).
02199   */
02200 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
02201 {
02202   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
02203 }
02204
02205 /**
02206   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02207   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02208   *         Smartcard feature is supported by the USARTx instance.
02209   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
02210   *         In transmission mode, it specifies the number of automatic retransmission retries, before
02211   *         generating a transmission error (FE bit set).
02212   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
02213   *         reception error (RXNE and PE bits set)
02214   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
02215   * @param  USARTx USART Instance
02216   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
02217   * @retval None
02218   */
02219 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
02220 {
02221   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
02222 }
02223
02224 /**
02225   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02226   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02227   *         Smartcard feature is supported by the USARTx instance.
02228   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
02229   * @param  USARTx USART Instance
02230   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
02231   */
02232 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
02233 {
02234   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
02235 }
02236
02237 /**
02238   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
02239   *         source to provide the SMARTCARD Clock (5 bits value)
02240   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02241   *         Smartcard feature is supported by the USARTx instance.
02242   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
02243   * @param  USARTx USART Instance
02244   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
02245   * @retval None
02246   */
02247 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02248 {
02249   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02250 }
02251
02252 /**
02253   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
02254   *         source to provide the SMARTCARD Clock (5 bits value)
02255   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02256   *         Smartcard feature is supported by the USARTx instance.
02257   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
02258   * @param  USARTx USART Instance
02259   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
02260   */
02261 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
02262 {
02263   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02264 }
02265
02266 /**
02267   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
02268   *         (GT[7:0] bits : Guard time value)
02269   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02270   *         Smartcard feature is supported by the USARTx instance.
02271   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
02272   * @param  USARTx USART Instance
02273   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
02274   * @retval None
02275   */
02276 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
02277 {
02278   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
02279 }
02280
02281 /**
02282   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
02283   *         (GT[7:0] bits : Guard time value)
02284   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02285   *         Smartcard feature is supported by the USARTx instance.
02286   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
02287   * @param  USARTx USART Instance
02288   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
02289   */
02290 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
02291 {
02292   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
02293 }
02294
02295 /**
02296   * @}
02297   */
02298
02299 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
02300   * @{
02301   */
02302
02303 /**
02304   * @brief  Enable Single Wire Half-Duplex mode
02305   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02306   *         Half-Duplex mode is supported by the USARTx instance.
02307   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
02308   * @param  USARTx USART Instance
02309   * @retval None
02310   */
02311 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
02312 {
02313   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02314 }
02315
02316 /**
02317   * @brief  Disable Single Wire Half-Duplex mode
02318   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02319   *         Half-Duplex mode is supported by the USARTx instance.
02320   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02321   * @param  USARTx USART Instance
02322   * @retval None
02323   */
02324 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02325 {
02326   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02327 }
02328
02329 /**
02330   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02331   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02332   *         Half-Duplex mode is supported by the USARTx instance.
02333   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02334   * @param  USARTx USART Instance
02335   * @retval State of bit (1 or 0).
02336   */
02337 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
02338 {
02339   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
02340 }
02341
02342 /**
02343   * @}
02344   */
02345
02346 /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
02347   * @{
02348   */
02349 /**
02350   * @brief  Enable SPI Synchronous Slave mode
02351   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02352   *         SPI Slave mode feature is supported by the USARTx instance.
02353   * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
02354   * @param  USARTx USART Instance
02355   * @retval None
02356   */
02357 __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
02358 {
02359   SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
02360 }
02361
02362 /**
02363   * @brief  Disable SPI Synchronous Slave mode
02364   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02365   *         SPI Slave mode feature is supported by the USARTx instance.
02366   * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
02367   * @param  USARTx USART Instance
02368   * @retval None
02369   */
02370 __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
02371 {
02372   CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
02373 }
02374
02375 /**
02376   * @brief  Indicate if  SPI Synchronous Slave mode is enabled
02377   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02378   *         SPI Slave mode feature is supported by the USARTx instance.
02379   * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
02380   * @param  USARTx USART Instance
02381   * @retval State of bit (1 or 0).
02382   */
02383 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
02384 {
02385   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
02386 }
02387
02388 /**
02389   * @brief  Enable SPI Slave Selection using NSS input pin
02390   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02391   *         SPI Slave mode feature is supported by the USARTx instance.
02392   * @note   SPI Slave Selection depends on NSS input pin
02393   *         (The slave is selected when NSS is low and deselected when NSS is high).
02394   * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
02395   * @param  USARTx USART Instance
02396   * @retval None
02397   */
02398 __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
02399 {
02400   CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02401 }
02402
02403 /**
02404   * @brief  Disable SPI Slave Selection using NSS input pin
02405   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02406   *         SPI Slave mode feature is supported by the USARTx instance.
02407   * @note   SPI Slave will be always selected and NSS input pin will be ignored.
02408   * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
02409   * @param  USARTx USART Instance
02410   * @retval None
02411   */
02412 __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
02413 {
02414   SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02415 }
02416
02417 /**
02418   * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
02419   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02420   *         SPI Slave mode feature is supported by the USARTx instance.
02421   * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
02422   * @param  USARTx USART Instance
02423   * @retval State of bit (1 or 0).
02424   */
02425 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
02426 {
02427   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
02428 }
02429
02430 /**
02431   * @}
02432   */
02433
02434 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02435   * @{
02436   */
02437
02438 /**
02439   * @brief  Set LIN Break Detection Length
02440   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02441   *         LIN feature is supported by the USARTx instance.
02442   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02443   * @param  USARTx USART Instance
02444   * @param  LINBDLength This parameter can be one of the following values:
02445   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02446   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02447   * @retval None
02448   */
02449 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02450 {
02451   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02452 }
02453
02454 /**
02455   * @brief  Return LIN Break Detection Length
02456   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02457   *         LIN feature is supported by the USARTx instance.
02458   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02459   * @param  USARTx USART Instance
02460   * @retval Returned value can be one of the following values:
02461   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02462   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02463   */
02464 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
02465 {
02466   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02467 }
02468
02469 /**
02470   * @brief  Enable LIN mode
02471   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02472   *         LIN feature is supported by the USARTx instance.
02473   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02474   * @param  USARTx USART Instance
02475   * @retval None
02476   */
02477 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02478 {
02479   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02480 }
02481
02482 /**
02483   * @brief  Disable LIN mode
02484   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02485   *         LIN feature is supported by the USARTx instance.
02486   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02487   * @param  USARTx USART Instance
02488   * @retval None
02489   */
02490 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02491 {
02492   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02493 }
02494
02495 /**
02496   * @brief  Indicate if LIN mode is enabled
02497   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02498   *         LIN feature is supported by the USARTx instance.
02499   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02500   * @param  USARTx USART Instance
02501   * @retval State of bit (1 or 0).
02502   */
02503 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
02504 {
02505   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
02506 }
02507
02508 /**
02509   * @}
02510   */
02511
02512 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02513   * @{
02514   */
02515
02516 /**
02517   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02518   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02519   *         Driver Enable feature is supported by the USARTx instance.
02520   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02521   * @param  USARTx USART Instance
02522   * @param  Time Value between Min_Data=0 and Max_Data=31
02523   * @retval None
02524   */
02525 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02526 {
02527   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02528 }
02529
02530 /**
02531   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02532   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02533   *         Driver Enable feature is supported by the USARTx instance.
02534   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02535   * @param  USARTx USART Instance
02536   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02537   */
02538 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
02539 {
02540   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02541 }
02542
02543 /**
02544   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02545   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02546   *         Driver Enable feature is supported by the USARTx instance.
02547   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02548   * @param  USARTx USART Instance
02549   * @param  Time Value between Min_Data=0 and Max_Data=31
02550   * @retval None
02551   */
02552 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02553 {
02554   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02555 }
02556
02557 /**
02558   * @brief  Return DEAT (Driver Enable Assertion Time)
02559   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02560   *         Driver Enable feature is supported by the USARTx instance.
02561   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02562   * @param  USARTx USART Instance
02563   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02564   */
02565 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
02566 {
02567   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02568 }
02569
02570 /**
02571   * @brief  Enable Driver Enable (DE) Mode
02572   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02573   *         Driver Enable feature is supported by the USARTx instance.
02574   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02575   * @param  USARTx USART Instance
02576   * @retval None
02577   */
02578 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02579 {
02580   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02581 }
02582
02583 /**
02584   * @brief  Disable Driver Enable (DE) Mode
02585   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02586   *         Driver Enable feature is supported by the USARTx instance.
02587   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02588   * @param  USARTx USART Instance
02589   * @retval None
02590   */
02591 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02592 {
02593   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02594 }
02595
02596 /**
02597   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02598   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02599   *         Driver Enable feature is supported by the USARTx instance.
02600   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02601   * @param  USARTx USART Instance
02602   * @retval State of bit (1 or 0).
02603   */
02604 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
02605 {
02606   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
02607 }
02608
02609 /**
02610   * @brief  Select Driver Enable Polarity
02611   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02612   *         Driver Enable feature is supported by the USARTx instance.
02613   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02614   * @param  USARTx USART Instance
02615   * @param  Polarity This parameter can be one of the following values:
02616   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02617   *         @arg @ref LL_USART_DE_POLARITY_LOW
02618   * @retval None
02619   */
02620 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02621 {
02622   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02623 }
02624
02625 /**
02626   * @brief  Return Driver Enable Polarity
02627   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02628   *         Driver Enable feature is supported by the USARTx instance.
02629   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02630   * @param  USARTx USART Instance
02631   * @retval Returned value can be one of the following values:
02632   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02633   *         @arg @ref LL_USART_DE_POLARITY_LOW
02634   */
02635 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
02636 {
02637   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02638 }
02639
02640 /**
02641   * @}
02642   */
02643
02644 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02645   * @{
02646   */
02647
02648 /**
02649   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02650   * @note   In UART mode, the following bits must be kept cleared:
02651   *           - LINEN bit in the USART_CR2 register,
02652   *           - CLKEN bit in the USART_CR2 register,
02653   *           - SCEN bit in the USART_CR3 register,
02654   *           - IREN bit in the USART_CR3 register,
02655   *           - HDSEL bit in the USART_CR3 register.
02656   * @note   Call of this function is equivalent to following function call sequence :
02657   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02658   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02659   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02660   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02661   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02662   * @note   Other remaining configurations items related to Asynchronous Mode
02663   *         (as Baud Rate, Word length, Parity, ...) should be set using
02664   *         dedicated functions
02665   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02666   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02667   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02668   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02669   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02670   * @param  USARTx USART Instance
02671   * @retval None
02672   */
02673 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02674 {
02675   /* In Asynchronous mode, the following bits must be kept cleared:
02676   - LINEN, CLKEN bits in the USART_CR2 register,
02677   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
02678   */
02679   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02680   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02681 }
02682
02683 /**
02684   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02685   * @note   In Synchronous mode, the following bits must be kept cleared:
02686   *           - LINEN bit in the USART_CR2 register,
02687   *           - SCEN bit in the USART_CR3 register,
02688   *           - IREN bit in the USART_CR3 register,
02689   *           - HDSEL bit in the USART_CR3 register.
02690   *         This function also sets the USART in Synchronous mode.
02691   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
02692   *         Synchronous mode is supported by the USARTx instance.
02693   * @note   Call of this function is equivalent to following function call sequence :
02694   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02695   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02696   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02697   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02698   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02699   * @note   Other remaining configurations items related to Synchronous Mode
02700   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02701   *         dedicated functions
02702   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02703   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02704   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02705   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02706   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02707   * @param  USARTx USART Instance
02708   * @retval None
02709   */
02710 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02711 {
02712   /* In Synchronous mode, the following bits must be kept cleared:
02713   - LINEN bit in the USART_CR2 register,
02714   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
02715   */
02716   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02717   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02718   /* set the UART/USART in Synchronous mode */
02719   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02720 }
02721
02722 /**
02723   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02724   * @note   In LIN mode, the following bits must be kept cleared:
02725   *           - STOP and CLKEN bits in the USART_CR2 register,
02726   *           - SCEN bit in the USART_CR3 register,
02727   *           - IREN bit in the USART_CR3 register,
02728   *           - HDSEL bit in the USART_CR3 register.
02729   *         This function also set the UART/USART in LIN mode.
02730   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02731   *         LIN feature is supported by the USARTx instance.
02732   * @note   Call of this function is equivalent to following function call sequence :
02733   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02734   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02735   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02736   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02737   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02738   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02739   * @note   Other remaining configurations items related to LIN Mode
02740   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02741   *         dedicated functions
02742   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02743   *         CR2          STOP          LL_USART_ConfigLINMode\n
02744   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02745   *         CR3          IREN          LL_USART_ConfigLINMode\n
02746   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02747   *         CR3          HDSEL         LL_USART_ConfigLINMode
02748   * @param  USARTx USART Instance
02749   * @retval None
02750   */
02751 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02752 {
02753   /* In LIN mode, the following bits must be kept cleared:
02754   - STOP and CLKEN bits in the USART_CR2 register,
02755   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
02756   */
02757   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02758   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02759   /* Set the UART/USART in LIN mode */
02760   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02761 }
02762
02763 /**
02764   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02765   * @note   In Half Duplex mode, the following bits must be kept cleared:
02766   *           - LINEN bit in the USART_CR2 register,
02767   *           - CLKEN bit in the USART_CR2 register,
02768   *           - SCEN bit in the USART_CR3 register,
02769   *           - IREN bit in the USART_CR3 register,
02770   *         This function also sets the UART/USART in Half Duplex mode.
02771   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02772   *         Half-Duplex mode is supported by the USARTx instance.
02773   * @note   Call of this function is equivalent to following function call sequence :
02774   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02775   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02776   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02777   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02778   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02779   * @note   Other remaining configurations items related to Half Duplex Mode
02780   *         (as Baud Rate, Word length, Parity, ...) should be set using
02781   *         dedicated functions
02782   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02783   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02784   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02785   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02786   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02787   * @param  USARTx USART Instance
02788   * @retval None
02789   */
02790 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02791 {
02792   /* In Half Duplex mode, the following bits must be kept cleared:
02793   - LINEN and CLKEN bits in the USART_CR2 register,
02794   - SCEN and IREN bits in the USART_CR3 register.
02795   */
02796   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02797   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02798   /* set the UART/USART in Half Duplex mode */
02799   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02800 }
02801
02802 /**
02803   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02804   * @note   In Smartcard mode, the following bits must be kept cleared:
02805   *           - LINEN bit in the USART_CR2 register,
02806   *           - IREN bit in the USART_CR3 register,
02807   *           - HDSEL bit in the USART_CR3 register.
02808   *         This function also configures Stop bits to 1.5 bits and
02809   *         sets the USART in Smartcard mode (SCEN bit).
02810   *         Clock Output is also enabled (CLKEN).
02811   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02812   *         Smartcard feature is supported by the USARTx instance.
02813   * @note   Call of this function is equivalent to following function call sequence :
02814   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02815   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02816   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02817   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02818   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02819   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02820   * @note   Other remaining configurations items related to Smartcard Mode
02821   *         (as Baud Rate, Word length, Parity, ...) should be set using
02822   *         dedicated functions
02823   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02824   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02825   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02826   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02827   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02828   * @param  USARTx USART Instance
02829   * @retval None
02830   */
02831 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02832 {
02833   /* In Smartcard mode, the following bits must be kept cleared:
02834   - LINEN bit in the USART_CR2 register,
02835   - IREN and HDSEL bits in the USART_CR3 register.
02836   */
02837   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02838   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02839   /* Configure Stop bits to 1.5 bits */
02840   /* Synchronous mode is activated by default */
02841   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02842   /* set the UART/USART in Smartcard mode */
02843   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02844 }
02845
02846 /**
02847   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02848   * @note   In IRDA mode, the following bits must be kept cleared:
02849   *           - LINEN bit in the USART_CR2 register,
02850   *           - STOP and CLKEN bits in the USART_CR2 register,
02851   *           - SCEN bit in the USART_CR3 register,
02852   *           - HDSEL bit in the USART_CR3 register.
02853   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02854   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02855   *         IrDA feature is supported by the USARTx instance.
02856   * @note   Call of this function is equivalent to following function call sequence :
02857   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02858   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02859   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02860   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02861   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02862   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02863   * @note   Other remaining configurations items related to Irda Mode
02864   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02865   *         dedicated functions
02866   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02867   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02868   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02869   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02870   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02871   *         CR3          IREN          LL_USART_ConfigIrdaMode
02872   * @param  USARTx USART Instance
02873   * @retval None
02874   */
02875 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02876 {
02877   /* In IRDA mode, the following bits must be kept cleared:
02878   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02879   - SCEN and HDSEL bits in the USART_CR3 register.
02880   */
02881   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02882   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02883   /* set the UART/USART in IRDA mode */
02884   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02885 }
02886
02887 /**
02888   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02889   *         (several USARTs connected in a network, one of the USARTs can be the master,
02890   *         its TX output connected to the RX inputs of the other slaves USARTs).
02891   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02892   *           - LINEN bit in the USART_CR2 register,
02893   *           - CLKEN bit in the USART_CR2 register,
02894   *           - SCEN bit in the USART_CR3 register,
02895   *           - IREN bit in the USART_CR3 register,
02896   *           - HDSEL bit in the USART_CR3 register.
02897   * @note   Call of this function is equivalent to following function call sequence :
02898   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02899   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02900   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02901   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02902   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02903   * @note   Other remaining configurations items related to Multi processor Mode
02904   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02905   *         dedicated functions
02906   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02907   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02908   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02909   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02910   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02911   * @param  USARTx USART Instance
02912   * @retval None
02913   */
02914 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02915 {
02916   /* In Multi Processor mode, the following bits must be kept cleared:
02917   - LINEN and CLKEN bits in the USART_CR2 register,
02918   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
02919   */
02920   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02921   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02922 }
02923
02924 /**
02925   * @}
02926   */
02927
02928 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02929   * @{
02930   */
02931
02932 /**
02933   * @brief  Check if the USART Parity Error Flag is set or not
02934   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02935   * @param  USARTx USART Instance
02936   * @retval State of bit (1 or 0).
02937   */
02938 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
02939 {
02940   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
02941 }
02942
02943 /**
02944   * @brief  Check if the USART Framing Error Flag is set or not
02945   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02946   * @param  USARTx USART Instance
02947   * @retval State of bit (1 or 0).
02948   */
02949 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
02950 {
02951   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
02952 }
02953
02954 /**
02955   * @brief  Check if the USART Noise error detected Flag is set or not
02956   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
02957   * @param  USARTx USART Instance
02958   * @retval State of bit (1 or 0).
02959   */
02960 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
02961 {
02962   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
02963 }
02964
02965 /**
02966   * @brief  Check if the USART OverRun Error Flag is set or not
02967   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02968   * @param  USARTx USART Instance
02969   * @retval State of bit (1 or 0).
02970   */
02971 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
02972 {
02973   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
02974 }
02975
02976 /**
02977   * @brief  Check if the USART IDLE line detected Flag is set or not
02978   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02979   * @param  USARTx USART Instance
02980   * @retval State of bit (1 or 0).
02981   */
02982 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
02983 {
02984   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
02985 }
02986
02987 #define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
02988
02989 /**
02990   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
02991   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02992   *         FIFO mode feature is supported by the USARTx instance.
02993   * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
02994   * @param  USARTx USART Instance
02995   * @retval State of bit (1 or 0).
02996   */
02997 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
02998 {
02999   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
03000 }
03001
03002 /**
03003   * @brief  Check if the USART Transmission Complete Flag is set or not
03004   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
03005   * @param  USARTx USART Instance
03006   * @retval State of bit (1 or 0).
03007   */
03008 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
03009 {
03010   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
03011 }
03012
03013 #define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
03014
03015 /**
03016   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
03017   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03018   *         FIFO mode feature is supported by the USARTx instance.
03019   * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
03020   * @param  USARTx USART Instance
03021   * @retval State of bit (1 or 0).
03022   */
03023 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
03024 {
03025   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
03026 }
03027
03028 /**
03029   * @brief  Check if the USART LIN Break Detection Flag is set or not
03030   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03031   *         LIN feature is supported by the USARTx instance.
03032   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
03033   * @param  USARTx USART Instance
03034   * @retval State of bit (1 or 0).
03035   */
03036 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
03037 {
03038   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
03039 }
03040
03041 /**
03042   * @brief  Check if the USART CTS interrupt Flag is set or not
03043   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03044   *         Hardware Flow control feature is supported by the USARTx instance.
03045   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
03046   * @param  USARTx USART Instance
03047   * @retval State of bit (1 or 0).
03048   */
03049 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
03050 {
03051   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
03052 }
03053
03054 /**
03055   * @brief  Check if the USART CTS Flag is set or not
03056   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03057   *         Hardware Flow control feature is supported by the USARTx instance.
03058   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
03059   * @param  USARTx USART Instance
03060   * @retval State of bit (1 or 0).
03061   */
03062 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
03063 {
03064   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
03065 }
03066
03067 /**
03068   * @brief  Check if the USART Receiver Time Out Flag is set or not
03069   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
03070   * @param  USARTx USART Instance
03071   * @retval State of bit (1 or 0).
03072   */
03073 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
03074 {
03075   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
03076 }
03077
03078 /**
03079   * @brief  Check if the USART End Of Block Flag is set or not
03080   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03081   *         Smartcard feature is supported by the USARTx instance.
03082   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
03083   * @param  USARTx USART Instance
03084   * @retval State of bit (1 or 0).
03085   */
03086 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
03087 {
03088   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
03089 }
03090
03091 /**
03092   * @brief  Check if the SPI Slave Underrun error flag is set or not
03093   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03094   *         SPI Slave mode feature is supported by the USARTx instance.
03095   * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
03096   * @param  USARTx USART Instance
03097   * @retval State of bit (1 or 0).
03098   */
03099 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
03100 {
03101   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
03102 }
03103
03104 /**
03105   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
03106   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03107   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03108   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
03109   * @param  USARTx USART Instance
03110   * @retval State of bit (1 or 0).
03111   */
03112 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
03113 {
03114   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
03115 }
03116
03117 /**
03118   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
03119   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03120   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03121   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
03122   * @param  USARTx USART Instance
03123   * @retval State of bit (1 or 0).
03124   */
03125 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
03126 {
03127   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
03128 }
03129
03130 /**
03131   * @brief  Check if the USART Busy Flag is set or not
03132   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
03133   * @param  USARTx USART Instance
03134   * @retval State of bit (1 or 0).
03135   */
03136 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
03137 {
03138   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
03139 }
03140
03141 /**
03142   * @brief  Check if the USART Character Match Flag is set or not
03143   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
03144   * @param  USARTx USART Instance
03145   * @retval State of bit (1 or 0).
03146   */
03147 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
03148 {
03149   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
03150 }
03151
03152 /**
03153   * @brief  Check if the USART Send Break Flag is set or not
03154   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
03155   * @param  USARTx USART Instance
03156   * @retval State of bit (1 or 0).
03157   */
03158 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
03159 {
03160   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
03161 }
03162
03163 /**
03164   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
03165   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
03166   * @param  USARTx USART Instance
03167   * @retval State of bit (1 or 0).
03168   */
03169 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
03170 {
03171   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
03172 }
03173
03174 /**
03175   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
03176   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03177   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03178   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
03179   * @param  USARTx USART Instance
03180   * @retval State of bit (1 or 0).
03181   */
03182 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
03183 {
03184   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
03185 }
03186
03187 /**
03188   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
03189   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
03190   * @param  USARTx USART Instance
03191   * @retval State of bit (1 or 0).
03192   */
03193 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
03194 {
03195   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
03196 }
03197
03198 /**
03199   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
03200   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
03201   * @param  USARTx USART Instance
03202   * @retval State of bit (1 or 0).
03203   */
03204 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
03205 {
03206   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
03207 }
03208
03209 /**
03210   * @brief  Check if the USART TX FIFO Empty Flag is set or not
03211   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03212   *         FIFO mode feature is supported by the USARTx instance.
03213   * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
03214   * @param  USARTx USART Instance
03215   * @retval State of bit (1 or 0).
03216   */
03217 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
03218 {
03219   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
03220 }
03221
03222 /**
03223   * @brief  Check if the USART RX FIFO Full Flag is set or not
03224   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03225   *         FIFO mode feature is supported by the USARTx instance.
03226   * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
03227   * @param  USARTx USART Instance
03228   * @retval State of bit (1 or 0).
03229   */
03230 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
03231 {
03232   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
03233 }
03234
03235 /**
03236   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
03237   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
03238   * @param  USARTx USART Instance
03239   * @retval State of bit (1 or 0).
03240   */
03241 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
03242 {
03243   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
03244 }
03245
03246 /**
03247   * @brief  Check if the USART TX FIFO Threshold Flag is set or not
03248   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03249   *         FIFO mode feature is supported by the USARTx instance.
03250   * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
03251   * @param  USARTx USART Instance
03252   * @retval State of bit (1 or 0).
03253   */
03254 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
03255 {
03256   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
03257 }
03258
03259 /**
03260   * @brief  Check if the USART RX FIFO Threshold Flag is set or not
03261   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03262   *         FIFO mode feature is supported by the USARTx instance.
03263   * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
03264   * @param  USARTx USART Instance
03265   * @retval State of bit (1 or 0).
03266   */
03267 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
03268 {
03269   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
03270 }
03271
03272 /**
03273   * @brief  Clear Parity Error Flag
03274   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
03275   * @param  USARTx USART Instance
03276   * @retval None
03277   */
03278 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
03279 {
03280   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
03281 }
03282
03283 /**
03284   * @brief  Clear Framing Error Flag
03285   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
03286   * @param  USARTx USART Instance
03287   * @retval None
03288   */
03289 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
03290 {
03291   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
03292 }
03293
03294 /**
03295   * @brief  Clear Noise Error detected Flag
03296   * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
03297   * @param  USARTx USART Instance
03298   * @retval None
03299   */
03300 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
03301 {
03302   WRITE_REG(USARTx->ICR, USART_ICR_NECF);
03303 }
03304
03305 /**
03306   * @brief  Clear OverRun Error Flag
03307   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
03308   * @param  USARTx USART Instance
03309   * @retval None
03310   */
03311 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
03312 {
03313   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
03314 }
03315
03316 /**
03317   * @brief  Clear IDLE line detected Flag
03318   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
03319   * @param  USARTx USART Instance
03320   * @retval None
03321   */
03322 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
03323 {
03324   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
03325 }
03326
03327 /**
03328   * @brief  Clear TX FIFO Empty Flag
03329   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03330   *         FIFO mode feature is supported by the USARTx instance.
03331   * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
03332   * @param  USARTx USART Instance
03333   * @retval None
03334   */
03335 __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
03336 {
03337   WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
03338 }
03339
03340 /**
03341   * @brief  Clear Transmission Complete Flag
03342   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
03343   * @param  USARTx USART Instance
03344   * @retval None
03345   */
03346 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
03347 {
03348   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
03349 }
03350
03351 /**
03352   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
03353   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
03354   * @param  USARTx USART Instance
03355   * @retval None
03356   */
03357 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
03358 {
03359   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
03360 }
03361
03362 /**
03363   * @brief  Clear LIN Break Detection Flag
03364   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03365   *         LIN feature is supported by the USARTx instance.
03366   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
03367   * @param  USARTx USART Instance
03368   * @retval None
03369   */
03370 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
03371 {
03372   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
03373 }
03374
03375 /**
03376   * @brief  Clear CTS Interrupt Flag
03377   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03378   *         Hardware Flow control feature is supported by the USARTx instance.
03379   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
03380   * @param  USARTx USART Instance
03381   * @retval None
03382   */
03383 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
03384 {
03385   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
03386 }
03387
03388 /**
03389   * @brief  Clear Receiver Time Out Flag
03390   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
03391   * @param  USARTx USART Instance
03392   * @retval None
03393   */
03394 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
03395 {
03396   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
03397 }
03398
03399 /**
03400   * @brief  Clear End Of Block Flag
03401   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03402   *         Smartcard feature is supported by the USARTx instance.
03403   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
03404   * @param  USARTx USART Instance
03405   * @retval None
03406   */
03407 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
03408 {
03409   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
03410 }
03411
03412 /**
03413   * @brief  Clear SPI Slave Underrun Flag
03414   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03415   *         SPI Slave mode feature is supported by the USARTx instance.
03416   * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
03417   * @param  USARTx USART Instance
03418   * @retval None
03419   */
03420 __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
03421 {
03422   WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
03423 }
03424
03425 /**
03426   * @brief  Clear Character Match Flag
03427   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
03428   * @param  USARTx USART Instance
03429   * @retval None
03430   */
03431 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
03432 {
03433   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
03434 }
03435
03436 /**
03437   * @brief  Clear Wake Up from stop mode Flag
03438   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03439   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03440   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
03441   * @param  USARTx USART Instance
03442   * @retval None
03443   */
03444 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
03445 {
03446   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
03447 }
03448
03449 /**
03450   * @}
03451   */
03452
03453 /** @defgroup USART_LL_EF_IT_Management IT_Management
03454   * @{
03455   */
03456
03457 /**
03458   * @brief  Enable IDLE Interrupt
03459   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
03460   * @param  USARTx USART Instance
03461   * @retval None
03462   */
03463 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
03464 {
03465   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03466 }
03467
03468 #define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
03469
03470 /**
03471   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
03472   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03473   *         FIFO mode feature is supported by the USARTx instance.
03474   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
03475   * @param  USARTx USART Instance
03476   * @retval None
03477   */
03478 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03479 {
03480   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03481 }
03482
03483 /**
03484   * @brief  Enable Transmission Complete Interrupt
03485   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
03486   * @param  USARTx USART Instance
03487   * @retval None
03488   */
03489 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
03490 {
03491   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
03492 }
03493
03494 #define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
03495
03496 /**
03497   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
03498   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03499   *         FIFO mode feature is supported by the USARTx instance.
03500   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
03501   * @param  USARTx USART Instance
03502   * @retval None
03503   */
03504 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03505 {
03506   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03507 }
03508
03509 /**
03510   * @brief  Enable Parity Error Interrupt
03511   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
03512   * @param  USARTx USART Instance
03513   * @retval None
03514   */
03515 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03516 {
03517   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03518 }
03519
03520 /**
03521   * @brief  Enable Character Match Interrupt
03522   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03523   * @param  USARTx USART Instance
03524   * @retval None
03525   */
03526 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03527 {
03528   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03529 }
03530
03531 /**
03532   * @brief  Enable Receiver Timeout Interrupt
03533   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03534   * @param  USARTx USART Instance
03535   * @retval None
03536   */
03537 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03538 {
03539   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03540 }
03541
03542 /**
03543   * @brief  Enable End Of Block Interrupt
03544   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03545   *         Smartcard feature is supported by the USARTx instance.
03546   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03547   * @param  USARTx USART Instance
03548   * @retval None
03549   */
03550 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03551 {
03552   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03553 }
03554
03555 /**
03556   * @brief  Enable TX FIFO Empty Interrupt
03557   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03558   *         FIFO mode feature is supported by the USARTx instance.
03559   * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
03560   * @param  USARTx USART Instance
03561   * @retval None
03562   */
03563 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
03564 {
03565   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03566 }
03567
03568 /**
03569   * @brief  Enable RX FIFO Full Interrupt
03570   * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
03571   * @param  USARTx USART Instance
03572   * @retval None
03573   */
03574 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
03575 {
03576   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03577 }
03578
03579 /**
03580   * @brief  Enable LIN Break Detection Interrupt
03581   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03582   *         LIN feature is supported by the USARTx instance.
03583   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03584   * @param  USARTx USART Instance
03585   * @retval None
03586   */
03587 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03588 {
03589   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03590 }
03591
03592 /**
03593   * @brief  Enable Error Interrupt
03594   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03595   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03596   *           0: Interrupt is inhibited
03597   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03598   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03599   * @param  USARTx USART Instance
03600   * @retval None
03601   */
03602 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03603 {
03604   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
03605 }
03606
03607 /**
03608   * @brief  Enable CTS Interrupt
03609   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03610   *         Hardware Flow control feature is supported by the USARTx instance.
03611   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03612   * @param  USARTx USART Instance
03613   * @retval None
03614   */
03615 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03616 {
03617   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03618 }
03619
03620 /**
03621   * @brief  Enable Wake Up from Stop Mode Interrupt
03622   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03623   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03624   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03625   * @param  USARTx USART Instance
03626   * @retval None
03627   */
03628 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03629 {
03630   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03631 }
03632
03633 /**
03634   * @brief  Enable TX FIFO Threshold Interrupt
03635   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03636   *         FIFO mode feature is supported by the USARTx instance.
03637   * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
03638   * @param  USARTx USART Instance
03639   * @retval None
03640   */
03641 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
03642 {
03643   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03644 }
03645
03646 /**
03647   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03648   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03649   *         Smartcard feature is supported by the USARTx instance.
03650   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03651   * @param  USARTx USART Instance
03652   * @retval None
03653   */
03654 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03655 {
03656   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03657 }
03658
03659 /**
03660   * @brief  Enable RX FIFO Threshold Interrupt
03661   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03662   *         FIFO mode feature is supported by the USARTx instance.
03663   * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
03664   * @param  USARTx USART Instance
03665   * @retval None
03666   */
03667 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
03668 {
03669   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03670 }
03671
03672 /**
03673   * @brief  Disable IDLE Interrupt
03674   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03675   * @param  USARTx USART Instance
03676   * @retval None
03677   */
03678 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03679 {
03680   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03681 }
03682
03683 #define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
03684
03685 /**
03686   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
03687   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03688   *         FIFO mode feature is supported by the USARTx instance.
03689   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
03690   * @param  USARTx USART Instance
03691   * @retval None
03692   */
03693 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03694 {
03695   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03696 }
03697
03698 /**
03699   * @brief  Disable Transmission Complete Interrupt
03700   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03701   * @param  USARTx USART Instance
03702   * @retval None
03703   */
03704 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03705 {
03706   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03707 }
03708
03709 #define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
03710
03711 /**
03712   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
03713   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03714   *         FIFO mode feature is supported by the USARTx instance.
03715   * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
03716   * @param  USARTx USART Instance
03717   * @retval None
03718   */
03719 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03720 {
03721   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03722 }
03723
03724 /**
03725   * @brief  Disable Parity Error Interrupt
03726   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03727   * @param  USARTx USART Instance
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03731 {
03732   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03733 }
03734
03735 /**
03736   * @brief  Disable Character Match Interrupt
03737   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03738   * @param  USARTx USART Instance
03739   * @retval None
03740   */
03741 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03742 {
03743   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03744 }
03745
03746 /**
03747   * @brief  Disable Receiver Timeout Interrupt
03748   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03749   * @param  USARTx USART Instance
03750   * @retval None
03751   */
03752 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03753 {
03754   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03755 }
03756
03757 /**
03758   * @brief  Disable End Of Block Interrupt
03759   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03760   *         Smartcard feature is supported by the USARTx instance.
03761   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03762   * @param  USARTx USART Instance
03763   * @retval None
03764   */
03765 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03766 {
03767   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03768 }
03769
03770 /**
03771   * @brief  Disable TX FIFO Empty Interrupt
03772   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03773   *         FIFO mode feature is supported by the USARTx instance.
03774   * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
03775   * @param  USARTx USART Instance
03776   * @retval None
03777   */
03778 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
03779 {
03780   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03781 }
03782
03783 /**
03784   * @brief  Disable RX FIFO Full Interrupt
03785   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03786   *         FIFO mode feature is supported by the USARTx instance.
03787   * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
03788   * @param  USARTx USART Instance
03789   * @retval None
03790   */
03791 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
03792 {
03793   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03794 }
03795
03796 /**
03797   * @brief  Disable LIN Break Detection Interrupt
03798   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03799   *         LIN feature is supported by the USARTx instance.
03800   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03801   * @param  USARTx USART Instance
03802   * @retval None
03803   */
03804 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03805 {
03806   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03807 }
03808
03809 /**
03810   * @brief  Disable Error Interrupt
03811   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03812   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03813   *           0: Interrupt is inhibited
03814   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03815   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03816   * @param  USARTx USART Instance
03817   * @retval None
03818   */
03819 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03820 {
03821   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03822 }
03823
03824 /**
03825   * @brief  Disable CTS Interrupt
03826   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03827   *         Hardware Flow control feature is supported by the USARTx instance.
03828   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03829   * @param  USARTx USART Instance
03830   * @retval None
03831   */
03832 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03833 {
03834   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03835 }
03836
03837 /**
03838   * @brief  Disable Wake Up from Stop Mode Interrupt
03839   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03840   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03841   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03842   * @param  USARTx USART Instance
03843   * @retval None
03844   */
03845 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03846 {
03847   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03848 }
03849
03850 /**
03851   * @brief  Disable TX FIFO Threshold Interrupt
03852   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03853   *         FIFO mode feature is supported by the USARTx instance.
03854   * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
03855   * @param  USARTx USART Instance
03856   * @retval None
03857   */
03858 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
03859 {
03860   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03861 }
03862
03863 /**
03864   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03865   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03866   *         Smartcard feature is supported by the USARTx instance.
03867   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03868   * @param  USARTx USART Instance
03869   * @retval None
03870   */
03871 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03872 {
03873   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03874 }
03875
03876 /**
03877   * @brief  Disable RX FIFO Threshold Interrupt
03878   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03879   *         FIFO mode feature is supported by the USARTx instance.
03880   * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
03881   * @param  USARTx USART Instance
03882   * @retval None
03883   */
03884 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
03885 {
03886   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03887 }
03888
03889 /**
03890   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03891   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03892   * @param  USARTx USART Instance
03893   * @retval State of bit (1 or 0).
03894   */
03895 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
03896 {
03897   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
03898 }
03899
03900 #define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
03901
03902 /**
03903   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
03904   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03905   *         FIFO mode feature is supported by the USARTx instance.
03906   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
03907   * @param  USARTx USART Instance
03908   * @retval State of bit (1 or 0).
03909   */
03910 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
03911 {
03912   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
03913 }
03914
03915 /**
03916   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03917   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03918   * @param  USARTx USART Instance
03919   * @retval State of bit (1 or 0).
03920   */
03921 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
03922 {
03923   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
03924 }
03925
03926 #define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
03927
03928 /**
03929   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
03930   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03931   *         FIFO mode feature is supported by the USARTx instance.
03932   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
03933   * @param  USARTx USART Instance
03934   * @retval State of bit (1 or 0).
03935   */
03936 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
03937 {
03938   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
03939 }
03940
03941 /**
03942   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03943   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03944   * @param  USARTx USART Instance
03945   * @retval State of bit (1 or 0).
03946   */
03947 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
03948 {
03949   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
03950 }
03951
03952 /**
03953   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03954   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03955   * @param  USARTx USART Instance
03956   * @retval State of bit (1 or 0).
03957   */
03958 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
03959 {
03960   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
03961 }
03962
03963 /**
03964   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03965   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03966   * @param  USARTx USART Instance
03967   * @retval State of bit (1 or 0).
03968   */
03969 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
03970 {
03971   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
03972 }
03973
03974 /**
03975   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03976   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03977   *         Smartcard feature is supported by the USARTx instance.
03978   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03979   * @param  USARTx USART Instance
03980   * @retval State of bit (1 or 0).
03981   */
03982 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
03983 {
03984   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
03985 }
03986
03987 /**
03988   * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
03989   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03990   *         FIFO mode feature is supported by the USARTx instance.
03991   * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
03992   * @param  USARTx USART Instance
03993   * @retval State of bit (1 or 0).
03994   */
03995 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
03996 {
03997   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
03998 }
03999
04000 /**
04001   * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
04002   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04003   *         FIFO mode feature is supported by the USARTx instance.
04004   * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
04005   * @param  USARTx USART Instance
04006   * @retval State of bit (1 or 0).
04007   */
04008 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
04009 {
04010   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
04011 }
04012
04013 /**
04014   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
04015   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
04016   *         LIN feature is supported by the USARTx instance.
04017   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
04018   * @param  USARTx USART Instance
04019   * @retval State of bit (1 or 0).
04020   */
04021 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
04022 {
04023   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
04024 }
04025
04026 /**
04027   * @brief  Check if the USART Error Interrupt is enabled or disabled.
04028   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
04029   * @param  USARTx USART Instance
04030   * @retval State of bit (1 or 0).
04031   */
04032 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
04033 {
04034   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
04035 }
04036
04037 /**
04038   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
04039   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
04040   *         Hardware Flow control feature is supported by the USARTx instance.
04041   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
04042   * @param  USARTx USART Instance
04043   * @retval State of bit (1 or 0).
04044   */
04045 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
04046 {
04047   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
04048 }
04049
04050 /**
04051   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
04052   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
04053   *         Wake-up from Stop mode feature is supported by the USARTx instance.
04054   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
04055   * @param  USARTx USART Instance
04056   * @retval State of bit (1 or 0).
04057   */
04058 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
04059 {
04060   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
04061 }
04062
04063 /**
04064   * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
04065   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04066   *         FIFO mode feature is supported by the USARTx instance.
04067   * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
04068   * @param  USARTx USART Instance
04069   * @retval State of bit (1 or 0).
04070   */
04071 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
04072 {
04073   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
04074 }
04075
04076 /**
04077   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
04078   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
04079   *         Smartcard feature is supported by the USARTx instance.
04080   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
04081   * @param  USARTx USART Instance
04082   * @retval State of bit (1 or 0).
04083   */
04084 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
04085 {
04086   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
04087 }
04088
04089 /**
04090   * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
04091   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04092   *         FIFO mode feature is supported by the USARTx instance.
04093   * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
04094   * @param  USARTx USART Instance
04095   * @retval State of bit (1 or 0).
04096   */
04097 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
04098 {
04099   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
04100 }
04101
04102 /**
04103   * @}
04104   */
04105
04106 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
04107   * @{
04108   */
04109
04110 /**
04111   * @brief  Enable DMA Mode for reception
04112   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
04113   * @param  USARTx USART Instance
04114   * @retval None
04115   */
04116 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
04117 {
04118   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
04119 }
04120
04121 /**
04122   * @brief  Disable DMA Mode for reception
04123   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
04124   * @param  USARTx USART Instance
04125   * @retval None
04126   */
04127 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
04128 {
04129   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
04130 }
04131
04132 /**
04133   * @brief  Check if DMA Mode is enabled for reception
04134   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
04135   * @param  USARTx USART Instance
04136   * @retval State of bit (1 or 0).
04137   */
04138 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
04139 {
04140   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
04141 }
04142
04143 /**
04144   * @brief  Enable DMA Mode for transmission
04145   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
04146   * @param  USARTx USART Instance
04147   * @retval None
04148   */
04149 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
04150 {
04151   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
04152 }
04153
04154 /**
04155   * @brief  Disable DMA Mode for transmission
04156   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
04157   * @param  USARTx USART Instance
04158   * @retval None
04159   */
04160 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
04161 {
04162   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
04163 }
04164
04165 /**
04166   * @brief  Check if DMA Mode is enabled for transmission
04167   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
04168   * @param  USARTx USART Instance
04169   * @retval State of bit (1 or 0).
04170   */
04171 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
04172 {
04173   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
04174 }
04175
04176 /**
04177   * @brief  Enable DMA Disabling on Reception Error
04178   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
04179   * @param  USARTx USART Instance
04180   * @retval None
04181   */
04182 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
04183 {
04184   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
04185 }
04186
04187 /**
04188   * @brief  Disable DMA Disabling on Reception Error
04189   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
04190   * @param  USARTx USART Instance
04191   * @retval None
04192   */
04193 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
04194 {
04195   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
04196 }
04197
04198 /**
04199   * @brief  Indicate if DMA Disabling on Reception Error is disabled
04200   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
04201   * @param  USARTx USART Instance
04202   * @retval State of bit (1 or 0).
04203   */
04204 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
04205 {
04206   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
04207 }
04208
04209 /**
04210   * @brief  Get the data register address used for DMA transfer
04211   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
04212   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
04213   * @param  USARTx USART Instance
04214   * @param  Direction This parameter can be one of the following values:
04215   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
04216   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
04217   * @retval Address of data register
04218   */
04219 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
04220 {
04221   uint32_t data_reg_addr;
04222
04223   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
04224   {
04225     /* return address of TDR register */
04226     data_reg_addr = (uint32_t) &(USARTx->TDR);
04227   }
04228   else
04229   {
04230     /* return address of RDR register */
04231     data_reg_addr = (uint32_t) &(USARTx->RDR);
04232   }
04233
04234   return data_reg_addr;
04235 }
04236
04237 /**
04238   * @}
04239   */
04240
04241 /** @defgroup USART_LL_EF_Data_Management Data_Management
04242   * @{
04243   */
04244
04245 /**
04246   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
04247   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
04248   * @param  USARTx USART Instance
04249   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04250   */
04251 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
04252 {
04253   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
04254 }
04255
04256 /**
04257   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
04258   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
04259   * @param  USARTx USART Instance
04260   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
04261   */
04262 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
04263 {
04264   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04265 }
04266
04267 /**
04268   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
04269   * @rmtoll TDR          TDR           LL_USART_TransmitData8
04270   * @param  USARTx USART Instance
04271   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
04272   * @retval None
04273   */
04274 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
04275 {
04276   USARTx->TDR = Value;
04277 }
04278
04279 /**
04280   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
04281   * @rmtoll TDR          TDR           LL_USART_TransmitData9
04282   * @param  USARTx USART Instance
04283   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
04284   * @retval None
04285   */
04286 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
04287 {
04288   USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
04289 }
04290
04291 /**
04292   * @}
04293   */
04294
04295 /** @defgroup USART_LL_EF_Execution Execution
04296   * @{
04297   */
04298
04299 /**
04300   * @brief  Request an Automatic Baud Rate measurement on next received data frame
04301   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
04302   *         Auto Baud Rate detection feature is supported by the USARTx instance.
04303   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
04304   * @param  USARTx USART Instance
04305   * @retval None
04306   */
04307 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
04308 {
04309   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
04310 }
04311
04312 /**
04313   * @brief  Request Break sending
04314   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
04315   * @param  USARTx USART Instance
04316   * @retval None
04317   */
04318 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
04319 {
04320   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
04321 }
04322
04323 /**
04324   * @brief  Put USART in mute mode and set the RWU flag
04325   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
04326   * @param  USARTx USART Instance
04327   * @retval None
04328   */
04329 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
04330 {
04331   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
04332 }
04333
04334 /**
04335   * @brief  Request a Receive Data and FIFO flush
04336   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04337   *         FIFO mode feature is supported by the USARTx instance.
04338   * @note   Allows to discard the received data without reading them, and avoid an overrun
04339   *         condition.
04340   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
04341   * @param  USARTx USART Instance
04342   * @retval None
04343   */
04344 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
04345 {
04346   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
04347 }
04348
04349 /**
04350   * @brief  Request a Transmit data and FIFO flush
04351   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04352   *         FIFO mode feature is supported by the USARTx instance.
04353   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
04354   * @param  USARTx USART Instance
04355   * @retval None
04356   */
04357 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
04358 {
04359   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
04360 }
04361
04362 /**
04363   * @}
04364   */
04365
04366 #if defined(USE_FULL_LL_DRIVER)
04367 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
04368   * @{
04369   */
04370 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
04371 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
04372 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
04373 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04374 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04375 /**
04376   * @}
04377   */
04378 #endif /* USE_FULL_LL_DRIVER */
04379
04380 /**
04381   * @}
04382   */
04383
04384 /**
04385   * @}
04386   */
04387
04388 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
04389
04390 /**
04391   * @}
04392   */
04393
04394 #ifdef __cplusplus
04395 }
04396 #endif
04397
04398 #endif /* STM32G4xx_LL_USART_H */
04399
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_utils.c Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Src
stm32g4xx_ll_utils.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32g4xx_ll_utils.h"
00021 #include "stm32g4xx_ll_rcc.h"
00022 #include "stm32g4xx_ll_system.h"
00023 #include "stm32g4xx_ll_pwr.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UTILS_LL
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /** @addtogroup UTILS_LL_Private_Constants
00042   * @{
00043   */
00044 #define UTILS_MAX_FREQUENCY_SCALE1  170000000U       /*!< Maximum frequency for system clock at power scale1, in Hz */
00045 #define UTILS_MAX_FREQUENCY_SCALE2   26000000U       /*!< Maximum frequency for system clock at power scale2, in Hz */
00046
00047 /* Defines used for PLL range */
00048 #define UTILS_PLLVCO_INPUT_MIN        2660000U       /*!< Frequency min for PLLVCO input, in Hz   */
00049 #define UTILS_PLLVCO_INPUT_MAX       16000000U       /*!< Frequency max for PLLVCO input, in Hz   */
00050 #define UTILS_PLLVCO_OUTPUT_MIN      64000000U       /*!< Frequency min for PLLVCO output, in Hz  */
00051 #define UTILS_PLLVCO_OUTPUT_MAX     344000000U       /*!< Frequency max for PLLVCO output, in Hz  */
00052
00053 /* Defines used for HSE range */
00054 #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
00055 #define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
00056
00057 /* Defines used for FLASH latency according to HCLK Frequency */
00058 #define UTILS_SCALE1_LATENCY1_BOOST_FREQ   34000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
00059 #define UTILS_SCALE1_LATENCY2_BOOST_FREQ   68000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
00060 #define UTILS_SCALE1_LATENCY3_BOOST_FREQ  102000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
00061 #define UTILS_SCALE1_LATENCY4_BOOST_FREQ  136000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
00062 #define UTILS_SCALE1_LATENCY5_BOOST_FREQ  170000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
00063
00064 #define UTILS_SCALE1_LATENCY1_FREQ   30000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 normal mode */
00065 #define UTILS_SCALE1_LATENCY2_FREQ   60000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 normal mode */
00066 #define UTILS_SCALE1_LATENCY3_FREQ   90000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 normal mode */
00067 #define UTILS_SCALE1_LATENCY4_FREQ  120000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 normal mode */
00068 #define UTILS_SCALE1_LATENCY5_FREQ  150000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 1 normal mode */
00069
00070 #define UTILS_SCALE2_LATENCY1_FREQ   12000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
00071 #define UTILS_SCALE2_LATENCY2_FREQ   24000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
00072 #define UTILS_SCALE2_LATENCY3_FREQ   26000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
00073 /**
00074   * @}
00075   */
00076
00077 /* Private macros ------------------------------------------------------------*/
00078 /** @addtogroup UTILS_LL_Private_Macros
00079   * @{
00080   */
00081 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00082                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00083                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00084                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00085                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00086                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00087                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00088                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00089                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00090
00091 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00092                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00093                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00094                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00095                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00096
00097 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00098                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00099                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00100                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00101                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00102
00103 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
00104                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
00105                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
00106                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
00107                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
00108                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
00109                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
00110                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
00111                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
00112                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
00113                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
00114                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
00115                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
00116                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
00117                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
00118                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_16))
00119
00120 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
00121
00122 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
00123                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
00124                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
00125                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
00126
00127 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
00128
00129 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
00130
00131 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
00132                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
00133
00134 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00135                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00136
00137 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00138 /**
00139   * @}
00140   */
00141 /* Private function prototypes -----------------------------------------------*/
00142 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00143   * @{
00144   */
00145 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
00146                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00147 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00148 static ErrorStatus UTILS_PLL_IsBusy(void);
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions --------------------------------------------------------*/
00154 /** @addtogroup UTILS_LL_Exported_Functions
00155   * @{
00156   */
00157
00158 /** @addtogroup UTILS_LL_EF_DELAY
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00164   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00165   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00166   * @param  HCLKFrequency HCLK frequency in Hz
00167   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
00168   * @retval None
00169   */
00170 void LL_Init1msTick(uint32_t HCLKFrequency)
00171 {
00172   /* Use frequency provided in argument */
00173   LL_InitTick(HCLKFrequency, 1000U);
00174 }
00175
00176 /**
00177   * @brief  This function provides accurate delay (in milliseconds) based
00178   *         on SysTick counter flag
00179   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00180   *         and use rather osDelay service.
00181   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00182   *         will configure Systick to 1ms
00183   * @param  Delay specifies the delay time length, in milliseconds.
00184   * @retval None
00185   */
00186 void LL_mDelay(uint32_t Delay)
00187 {
00188   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00189   uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
00190   /* Add this code to indicate that local variable is not used */
00191   ((void)tmp);
00192   tmpDelay = Delay;
00193   /* Add a period to guaranty minimum wait */
00194   if(tmpDelay < LL_MAX_DELAY)
00195   {
00196     tmpDelay++;
00197   }
00198
00199   while (tmpDelay != 0U)
00200   {
00201     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00202     {
00203       tmpDelay--;
00204     }
00205   }
00206 }
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @addtogroup UTILS_EF_SYSTEM
00213   *  @brief    System Configuration functions
00214   *
00215   @verbatim
00216  ===============================================================================
00217            ##### System Configuration functions #####
00218  ===============================================================================
00219     [..]
00220          System, AHB and APB buses clocks configuration
00221
00222          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
00223              170000000 Hz for STM32G4xx.
00224   @endverbatim
00225   @internal
00226              Depending on the device voltage range, the maximum frequency should be
00227              adapted accordingly:
00228
00229            +----------------------------------------------------------------------------+
00230            | Latency         |            HCLK clock frequency (MHz)                    |
00231            |                 |----------------------------------------------------------|
00232            |                 |  voltage range 1  |  voltage range 1  | voltage range 2  |
00233            |                 | boost mode 1.28 V | normal mode 1.2 V |     1.0 V        |
00234            |-----------------|-------------------|-------------------|------------------|
00235            |0WS(1 CPU cycles)|    HCLK <= 34     |    HCLK <= 30     |    HCLK <= 12    |
00236            |-----------------|-------------------|-------------------|------------------|
00237            |1WS(2 CPU cycles)|    HCLK <= 68     |    HCLK <= 60     |    HCLK <= 24    |
00238            |-----------------|-------------------|-------------------|------------------|
00239            |2WS(3 CPU cycles)|    HCLK <= 102    |    HCLK <= 90     |    HCLK <= 26    |
00240            |-----------------|-------------------|-------------------|------------------|
00241            |3WS(4 CPU cycles)|    HCLK <= 136    |    HCLK <= 120    |        -         |
00242            |-----------------|-------------------|-------------------|------------------|
00243            |4WS(5 CPU cycles)|    HCLK <= 170    |    HCLK <= 150    |        -         |
00244            +----------------------------------------------------------------------------+
00245
00246
00247   @endinternal
00248   * @{
00249   */
00250
00251 /**
00252   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00253   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00254   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00255   * @retval None
00256   */
00257 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00258 {
00259   /* HCLK clock frequency */
00260   SystemCoreClock = HCLKFrequency;
00261 }
00262
00263 /**
00264   * @brief  Update number of Flash wait states in line with new frequency and current
00265             voltage range.
00266   * @param  HCLKFrequency  HCLK frequency
00267   * @retval An ErrorStatus enumeration value:
00268   *          - SUCCESS: Latency has been modified
00269   *          - ERROR: Latency cannot be modified
00270   */
00271 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
00272 {
00273   uint32_t timeout;
00274   uint32_t getlatency;
00275   ErrorStatus status = SUCCESS;
00276   uint32_t regulatorstatus = LL_PWR_GetRegulVoltageScaling();
00277   uint32_t regulatorbooststatus = LL_PWR_IsEnabledRange1BoostMode();
00278
00279   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
00280
00281   /* Frequency cannot be equal to 0 or greater than max clock */
00282   if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY5_BOOST_FREQ))
00283   {
00284     status = ERROR;
00285   }
00286   else
00287   {
00288     if((regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1) && (regulatorbooststatus == 1U))
00289     {
00290       if(HCLKFrequency > UTILS_SCALE1_LATENCY4_BOOST_FREQ)
00291       {
00292         /* 136 < HCLK <= 170 => 4WS (5 CPU cycles) */
00293         latency = LL_FLASH_LATENCY_4;
00294       }
00295       else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_BOOST_FREQ)
00296       {
00297         /* 102 < HCLK <= 136 => 3WS (4 CPU cycles) */
00298         latency = LL_FLASH_LATENCY_3;
00299       }
00300       else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_BOOST_FREQ)
00301       {
00302         /* 68 < HCLK <= 102 => 2WS (3 CPU cycles) */
00303         latency = LL_FLASH_LATENCY_2;
00304       }
00305       else
00306       {
00307         if(HCLKFrequency > UTILS_SCALE1_LATENCY1_BOOST_FREQ)
00308         {
00309           /* 34 < HCLK <= 68 => 1WS (2 CPU cycles) */
00310           latency = LL_FLASH_LATENCY_1;
00311         }
00312         /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
00313       }
00314     }
00315     /* SCALE1 normal mode*/
00316     else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1)
00317     {
00318       if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
00319       {
00320         /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
00321         latency = LL_FLASH_LATENCY_4;
00322       }
00323       else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
00324       {
00325         /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
00326         latency = LL_FLASH_LATENCY_3;
00327       }
00328       else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
00329       {
00330         /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
00331         latency = LL_FLASH_LATENCY_2;
00332       }
00333       else
00334       {
00335         if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
00336         {
00337           /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
00338           latency = LL_FLASH_LATENCY_1;
00339         }
00340         /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
00341       }
00342     }
00343     /* SCALE2 */
00344     else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE2)
00345     {
00346       if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
00347       {
00348         /* 24 < HCLK <= 26 => 2WS (3 CPU cycles) */
00349         latency = LL_FLASH_LATENCY_2;
00350       }
00351       else
00352       {
00353         if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
00354         {
00355           /* 12 < HCLK <= 24 => 1WS (2 CPU cycles) */
00356           latency = LL_FLASH_LATENCY_1;
00357         }
00358         /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
00359       }
00360     }
00361     else
00362     {
00363      /* Nothing to do */
00364     }
00365
00366     if (status != ERROR)
00367     {
00368       LL_FLASH_SetLatency(latency);
00369
00370       /* Check that the new number of wait states is taken into account to access the Flash
00371          memory by reading the FLASH_ACR register */
00372       timeout = 2U;
00373       do
00374       {
00375         /* Wait for Flash latency to be updated */
00376         getlatency = LL_FLASH_GetLatency();
00377         timeout--;
00378       } while ((getlatency != latency) && (timeout > 0U));
00379
00380       if(getlatency != latency)
00381       {
00382         status = ERROR;
00383       }
00384     }
00385   }
00386
00387   return status;
00388 }
00389
00390 /**
00391   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00392   * @note   The application need to ensure that PLL is disabled.
00393   * @note   Function is based on the following formula:
00394   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
00395   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSI frequency / PLLM)
00396   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00397   *         - PLLR: ensure that max frequency at 170000000 Hz is reach (PLLVCO_output / PLLR)
00398   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00399   *                             the configuration information for the PLL.
00400   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00401   *                             the configuration information for the BUS prescalers.
00402   * @retval An ErrorStatus enumeration value:
00403   *          - SUCCESS: Max frequency configuration done
00404   *          - ERROR: Max frequency configuration not done
00405   */
00406 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00407                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00408 {
00409   ErrorStatus status;
00410   uint32_t pllfreq;
00411   uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
00412
00413   /* Check if one of the PLL is enabled */
00414   if(UTILS_PLL_IsBusy() == SUCCESS)
00415   {
00416     /* Calculate the new PLL output frequency */
00417     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00418
00419     /* Enable HSI if not enabled */
00420     if(LL_RCC_HSI_IsReady() != 1U)
00421     {
00422       LL_RCC_HSI_Enable();
00423       while (LL_RCC_HSI_IsReady() != 1U)
00424       {
00425         /* Wait for HSI ready */
00426       }
00427     }
00428
00429     /* Configure PLL */
00430     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00431                                 UTILS_PLLInitStruct->PLLR);
00432
00433     /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
00434     if(pllfreq > 80000000U)
00435     {
00436       if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
00437       {
00438         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
00439         hpre = LL_RCC_SYSCLK_DIV_2;
00440       }
00441     }
00442
00443     /* Enable PLL and switch system clock to PLL */
00444     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00445
00446     /* Apply definitive AHB prescaler value if necessary */
00447     if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
00448     {
00449       /* Set FLASH latency to highest latency */
00450       status = LL_SetFlashLatency(pllfreq);
00451       if (status == SUCCESS)
00452       {
00453         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
00454         LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00455         LL_SetSystemCoreClock(pllfreq);
00456       }
00457     }
00458   }
00459   else
00460   {
00461     /* Current PLL configuration cannot be modified */
00462     status = ERROR;
00463   }
00464
00465   return status;
00466 }
00467
00468 /**
00469   * @brief  This function configures system clock with HSE as clock source of the PLL
00470   * @note   The application need to ensure that PLL is disabled.
00471   * @note   Function is based on the following formula:
00472   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
00473   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSE frequency / PLLM)
00474   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00475   *         - PLLR: ensure that max frequency at 170000000 Hz is reached (PLLVCO_output / PLLR)
00476   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
00477   * @param  HSEBypass This parameter can be one of the following values:
00478   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00479   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00480   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00481   *                             the configuration information for the PLL.
00482   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00483   *                             the configuration information for the BUS prescalers.
00484   * @retval An ErrorStatus enumeration value:
00485   *          - SUCCESS: Max frequency configuration done
00486   *          - ERROR: Max frequency configuration not done
00487   */
00488 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00489                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00490 {
00491   ErrorStatus status;
00492   uint32_t pllfreq;
00493   uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
00494
00495   /* Check the parameters */
00496   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00497   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00498
00499   /* Check if one of the PLL is enabled */
00500   if(UTILS_PLL_IsBusy() == SUCCESS)
00501   {
00502     /* Calculate the new PLL output frequency */
00503     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00504
00505     /* Enable HSE if not enabled */
00506     if(LL_RCC_HSE_IsReady() != 1U)
00507     {
00508       /* Check if need to enable HSE bypass feature or not */
00509       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
00510       {
00511         LL_RCC_HSE_EnableBypass();
00512       }
00513       else
00514       {
00515         LL_RCC_HSE_DisableBypass();
00516       }
00517
00518       /* Enable HSE */
00519       LL_RCC_HSE_Enable();
00520       while (LL_RCC_HSE_IsReady() != 1U)
00521       {
00522         /* Wait for HSE ready */
00523       }
00524     }
00525
00526     /* Configure PLL */
00527     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00528                                 UTILS_PLLInitStruct->PLLR);
00529
00530     /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
00531     if(pllfreq > 80000000U)
00532     {
00533       if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
00534       {
00535         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
00536         hpre = LL_RCC_SYSCLK_DIV_2;
00537       }
00538     }
00539
00540     /* Enable PLL and switch system clock to PLL */
00541     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00542
00543     /* Apply definitive AHB prescaler value if necessary */
00544     if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
00545     {
00546       /* Set FLASH latency to highest latency */
00547       status = LL_SetFlashLatency(pllfreq);
00548       if (status == SUCCESS)
00549       {
00550         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
00551         LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00552         LL_SetSystemCoreClock(pllfreq);
00553       }
00554     }
00555   }
00556   else
00557   {
00558     /* Current PLL configuration cannot be modified */
00559     status = ERROR;
00560   }
00561
00562   return status;
00563 }
00564
00565 /**
00566   * @}
00567   */
00568
00569 /**
00570   * @}
00571   */
00572
00573 /** @addtogroup UTILS_LL_Private_Functions
00574   * @{
00575   */
00576
00577 /**
00578   * @brief  Function to check that PLL can be modified
00579   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00580   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00581   *                             the configuration information for the PLL.
00582   * @retval PLL output frequency (in Hz)
00583   */
00584 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00585 {
00586   uint32_t pllfreq;
00587
00588   /* Check the parameters */
00589   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00590   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00591   assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
00592
00593   /* Check different PLL parameters according to RM                          */
00594   /*  - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz.   */
00595   pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
00596   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
00597
00598   /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
00599   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
00600   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
00601
00602   /*  - PLLR: ensure that max frequency at 170000000 Hz is reached                   */
00603   pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
00604   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00605
00606   return pllfreq;
00607 }
00608
00609 /**
00610   * @brief  Function to check that PLL can be modified
00611   * @retval An ErrorStatus enumeration value:
00612   *          - SUCCESS: PLL modification can be done
00613   *          - ERROR: PLL is busy
00614   */
00615 static ErrorStatus UTILS_PLL_IsBusy(void)
00616 {
00617   ErrorStatus status = SUCCESS;
00618
00619   /* Check if PLL is busy*/
00620   if(LL_RCC_PLL_IsReady() != 0U)
00621   {
00622     /* PLL configuration cannot be modified */
00623     status = ERROR;
00624   }
00625
00626   return status;
00627 }
00628
00629 /**
00630   * @brief  Function to enable PLL and switch system clock to PLL
00631   * @param  SYSCLK_Frequency SYSCLK frequency
00632   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00633   *                             the configuration information for the BUS prescalers.
00634   * @retval An ErrorStatus enumeration value:
00635   *          - SUCCESS: No problem to switch system to PLL
00636   *          - ERROR: Problem to switch system to PLL
00637   */
00638 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00639 {
00640   ErrorStatus status = SUCCESS;
00641   uint32_t hclk_frequency;
00642
00643   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00644   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00645   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00646
00647   /* Calculate HCLK frequency */
00648   hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
00649
00650   /* Increasing the number of wait states because of higher CPU frequency */
00651   if(SystemCoreClock < hclk_frequency)
00652   {
00653     /* Set FLASH latency to highest latency */
00654     status = LL_SetFlashLatency(hclk_frequency);
00655   }
00656
00657   /* Update system clock configuration */
00658   if(status == SUCCESS)
00659   {
00660     /* Enable PLL */
00661     LL_RCC_PLL_Enable();
00662     LL_RCC_PLL_EnableDomain_SYS();
00663     while (LL_RCC_PLL_IsReady() != 1U)
00664     {
00665       /* Wait for PLL ready */
00666     }
00667
00668     /* Sysclk activation on the main PLL */
00669     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00670     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00671     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00672     {
00673       /* Wait for system clock switch to PLL */
00674     }
00675
00676     /* Set APB1 & APB2 prescaler*/
00677     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00678     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00679   }
00680
00681   /* Decreasing the number of wait states because of lower CPU frequency */
00682   if(SystemCoreClock > hclk_frequency)
00683   {
00684     /* Set FLASH latency to lowest latency */
00685     status = LL_SetFlashLatency(hclk_frequency);
00686   }
00687
00688   /* Update SystemCoreClock variable */
00689   if(status == SUCCESS)
00690   {
00691     LL_SetSystemCoreClock(hclk_frequency);
00692   }
00693
00694   return status;
00695 }
00696
00697 /**
00698   * @}
00699   */
00700
00701 /**
00702   * @}
00703   */
00704
00705 /**
00706   * @}
00707   */
00708
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_utils.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_utils.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021     [..]
00022     The LL UTILS driver contains a set of generic APIs that can be
00023     used by user:
00024       (+) Device electronic signature
00025       (+) Timing functions
00026       (+) PLL configuration functions
00027
00028   @endverbatim
00029   */
00030
00031 /* Define to prevent recursive inclusion -------------------------------------*/
00032 #ifndef STM32G4xx_LL_UTILS_H
00033 #define STM32G4xx_LL_UTILS_H
00034
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32g4xx.h"
00041
00042 /** @addtogroup STM32G4xx_LL_Driver
00043   * @{
00044   */
00045
00046 /** @defgroup UTILS_LL UTILS
00047   * @{
00048   */
00049
00050 /* Private types -------------------------------------------------------------*/
00051 /* Private variables ---------------------------------------------------------*/
00052
00053 /* Private constants ---------------------------------------------------------*/
00054 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00055   * @{
00056   */
00057
00058 /* Max delay can be used in LL_mDelay */
00059 #define LL_MAX_DELAY                  0xFFFFFFFFU
00060
00061 /**
00062  * @brief Unique device ID register base address
00063  */
00064 #define UID_BASE_ADDRESS              UID_BASE
00065
00066 /**
00067  * @brief Flash size data register base address
00068  */
00069 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00070
00071 /**
00072  * @brief Package data register base address
00073  */
00074 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00075
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macros ------------------------------------------------------------*/
00081 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087 /* Exported types ------------------------------------------------------------*/
00088 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00089   * @{
00090   */
00091 /**
00092   * @brief  UTILS PLL structure definition
00093   */
00094 typedef struct
00095 {
00096   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00097                         This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
00098
00099                         This feature can be modified afterwards using unitary function
00100                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00101
00102   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00103                         This parameter must be a number between Min_Data = 8 and Max_Data = 86
00104
00105                         This feature can be modified afterwards using unitary function
00106                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00107
00108   uint32_t PLLR;   /*!< Division for the main system clock.
00109                         This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
00110
00111                         This feature can be modified afterwards using unitary function
00112                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00113 } LL_UTILS_PLLInitTypeDef;
00114
00115 /**
00116   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00121                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00122
00123                                        This feature can be modified afterwards using unitary function
00124                                        @ref LL_RCC_SetAHBPrescaler(). */
00125
00126   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00127                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00128
00129                                        This feature can be modified afterwards using unitary function
00130                                        @ref LL_RCC_SetAPB1Prescaler(). */
00131
00132   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00133                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00134
00135                                        This feature can be modified afterwards using unitary function
00136                                        @ref LL_RCC_SetAPB2Prescaler(). */
00137
00138 } LL_UTILS_ClkInitTypeDef;
00139
00140 /**
00141   * @}
00142   */
00143
00144 /* Exported constants --------------------------------------------------------*/
00145 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00146   * @{
00147   */
00148
00149 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00150   * @{
00151   */
00152 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00153 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00159   * @{
00160   */
00161 #define LL_UTILS_PACKAGETYPE_LQFP64             0x00000000U /*!< LQFP64 package type                      */
00162 #define LL_UTILS_PACKAGETYPE_WLCSP64            0x00000001U /*!< WLCSP64 package type                     */
00163 #if defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32G471xx) || \
00164     defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || \
00165     defined (STM32G484xx)
00166 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80     0x00000002U /*!< LQFP100 \ LQFP80 package type             */
00167 #define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80  /*!< For backward compatibility  */
00168 #else
00169 #define LL_UTILS_PACKAGETYPE_LQFP100            0x00000002U /*!< LQFP100 package type                      */
00170 #endif /* STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */
00171 #define LL_UTILS_PACKAGETYPE_WLCSP81            0x00000005U /*!< WLCSP81 package type                      */
00172 #define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121   0x00000007U /*!< LQFP128 \ UFBGA121 package type           */
00173 #define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */
00174 #define LL_UTILS_PACKAGETYPE_UFQFPN32           0x00000008U /*!< UFQFPN32 package type                     */
00175 #define LL_UTILS_PACKAGETYPE_LQFP32             0x00000009U /*!< LQFP32 package type                       */
00176 #define LL_UTILS_PACKAGETYPE_UFQFPN48           0x0000000AU /*!< UFQFPN48 package type                     */
00177 #define LL_UTILS_PACKAGETYPE_LQFP48             0x0000000BU /*!< LQFP48 package type                       */
00178 #define LL_UTILS_PACKAGETYPE_WLCSP49            0x0000000CU /*!< WLCSP49 package type                      */
00179 #define LL_UTILS_PACKAGETYPE_UFBGA64            0x0000000DU /*!< UFBGA64 package type                      */
00180 #define LL_UTILS_PACKAGETYPE_TFBGA100           0x0000000EU /*!< TFBGA100 package type                     */
00181 #define LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100  /*!< For backward compatibility       */
00182 #define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE       0x00000010U /*!< LQFP48 EBIKE package type                 */
00183 #if defined (STM32G491xx) || defined (STM32G4A1xx)
00184 #define LL_UTILS_PACKAGETYPE_LQFP80             0x00000011U /*!< LQFP80 package type                       */
00185 #endif /* STM32G491xx || STM32G4A1xx */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /* Exported macro ------------------------------------------------------------*/
00196
00197 /* Exported functions --------------------------------------------------------*/
00198 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00199   * @{
00200   */
00201
00202 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00203   * @{
00204   */
00205
00206 /**
00207   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00208   * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
00209   */
00210 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00211 {
00212   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00213 }
00214
00215 /**
00216   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00217   * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
00218   */
00219 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00220 {
00221   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00222 }
00223
00224 /**
00225   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00226   * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
00227   */
00228 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00229 {
00230   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00231 }
00232
00233 /**
00234   * @brief  Get Flash memory size
00235   * @note   This bitfield indicates the size of the device Flash memory expressed in
00236   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00237   * @retval FLASH_SIZE[15:0]: Flash memory size
00238   */
00239 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00240 {
00241   return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
00242 }
00243
00244 /**
00245   * @brief  Get Package type
00246   * @retval Returned value can be one of the following values:
00247   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
00248   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
00249   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
00250   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
00251   *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
00252   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
00253   *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
00254   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
00255   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
00256   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
00257   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
00258   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
00259   *
00260 */
00261 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00262 {
00263   return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
00264 }
00265
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup UTILS_LL_EF_DELAY DELAY
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  This function configures the Cortex-M SysTick source of the time base.
00276   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00277   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00278   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00279   * @param  Ticks Frequency of Ticks (Hz)
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00283 {
00284   /* Configure the SysTick to have interrupt in 1ms time base */
00285   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00286   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00287   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00288                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00289 }
00290
00291 void        LL_Init1msTick(uint32_t HCLKFrequency);
00292 void        LL_mDelay(uint32_t Delay);
00293
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00299   * @{
00300   */
00301
00302 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00303 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
00304 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00305                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00306 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00307                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324
00325 #ifdef __cplusplus
00326 }
00327 #endif
00328
00329 #endif /* STM32G4xx_LL_UTILS_H */
00330
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: stm32g4xx_ll_wwdg.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G4xx_HAL_Driver
  • Inc
stm32g4xx_ll_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g4xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G4xx_LL_WWDG_H
00021 #define STM32G4xx_LL_WWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g4xx.h"
00029
00030 /** @addtogroup STM32G4xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (WWDG)
00035
00036 /** @defgroup WWDG_LL WWDG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Exported types ------------------------------------------------------------*/
00045 /* Exported constants --------------------------------------------------------*/
00046 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00047   * @{
00048   */
00049
00050 /** @defgroup WWDG_LL_EC_IT IT Defines
00051   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00052   * @{
00053   */
00054 #define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00060   * @{
00061   */
00062 #define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
00063 #define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
00064 #define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
00065 #define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
00066 #define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
00067 #define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
00068 #define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
00069 #define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00080   * @{
00081   */
00082 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00083   * @{
00084   */
00085 /**
00086   * @brief  Write a value in WWDG register
00087   * @param  __INSTANCE__ WWDG Instance
00088   * @param  __REG__ Register to be written
00089   * @param  __VALUE__ Value to be written in the register
00090   * @retval None
00091   */
00092 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00093
00094 /**
00095   * @brief  Read a value in WWDG register
00096   * @param  __INSTANCE__ WWDG Instance
00097   * @param  __REG__ Register to be read
00098   * @retval Register value
00099   */
00100 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Exported functions --------------------------------------------------------*/
00110 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00111   * @{
00112   */
00113
00114 /** @defgroup WWDG_LL_EF_Configuration Configuration
00115   * @{
00116   */
00117 /**
00118   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00119   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00120   *         then it cannot be disabled again except by a reset.
00121   *         This bit is set by software and only cleared by hardware after a reset.
00122   *         When WDGA = 1, the watchdog can generate a reset.
00123   * @rmtoll CR           WDGA          LL_WWDG_Enable
00124   * @param  WWDGx WWDG Instance
00125   * @retval None
00126   */
00127 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00128 {
00129   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00130 }
00131
00132 /**
00133   * @brief  Checks if Window Watchdog is enabled
00134   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00135   * @param  WWDGx WWDG Instance
00136   * @retval State of bit (1 or 0).
00137   */
00138 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
00139 {
00140   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
00141 }
00142
00143 /**
00144   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00145   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00146   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00147   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00148   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00149   * @rmtoll CR           T             LL_WWDG_SetCounter
00150   * @param  WWDGx WWDG Instance
00151   * @param  Counter 0..0x7F (7 bit counter value)
00152   * @retval None
00153   */
00154 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00155 {
00156   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00157 }
00158
00159 /**
00160   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00161   * @rmtoll CR           T             LL_WWDG_GetCounter
00162   * @param  WWDGx WWDG Instance
00163   * @retval 7 bit Watchdog Counter value
00164   */
00165 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
00166 {
00167   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
00168 }
00169
00170 /**
00171   * @brief  Set the time base of the prescaler (WDGTB).
00172   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00173   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00174   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00175   * @param  WWDGx WWDG Instance
00176   * @param  Prescaler This parameter can be one of the following values:
00177   *         @arg @ref LL_WWDG_PRESCALER_1
00178   *         @arg @ref LL_WWDG_PRESCALER_2
00179   *         @arg @ref LL_WWDG_PRESCALER_4
00180   *         @arg @ref LL_WWDG_PRESCALER_8
00181   *         @arg @ref LL_WWDG_PRESCALER_16
00182   *         @arg @ref LL_WWDG_PRESCALER_32
00183   *         @arg @ref LL_WWDG_PRESCALER_64
00184   *         @arg @ref LL_WWDG_PRESCALER_128
00185   * @retval None
00186   */
00187 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00188 {
00189   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00190 }
00191
00192 /**
00193   * @brief  Return current Watchdog Prescaler Value
00194   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00195   * @param  WWDGx WWDG Instance
00196   * @retval Returned value can be one of the following values:
00197   *         @arg @ref LL_WWDG_PRESCALER_1
00198   *         @arg @ref LL_WWDG_PRESCALER_2
00199   *         @arg @ref LL_WWDG_PRESCALER_4
00200   *         @arg @ref LL_WWDG_PRESCALER_8
00201   *         @arg @ref LL_WWDG_PRESCALER_16
00202   *         @arg @ref LL_WWDG_PRESCALER_32
00203   *         @arg @ref LL_WWDG_PRESCALER_64
00204   *         @arg @ref LL_WWDG_PRESCALER_128
00205   */
00206 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
00207 {
00208   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00209 }
00210
00211 /**
00212   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00213   * @note   This window value defines when write in the WWDG_CR register
00214   *         to program Watchdog counter is allowed.
00215   *         Watchdog counter value update must occur only when the counter value
00216   *         is lower than the Watchdog window register value.
00217   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00218   *         (in the control register) is refreshed before the downcounter has reached
00219   *         the watchdog window register value.
00220   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00221   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00222   * @rmtoll CFR          W             LL_WWDG_SetWindow
00223   * @param  WWDGx WWDG Instance
00224   * @param  Window 0x00..0x7F (7 bit Window value)
00225   * @retval None
00226   */
00227 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00228 {
00229   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00230 }
00231
00232 /**
00233   * @brief  Return current Watchdog Window Value (7 bits value)
00234   * @rmtoll CFR          W             LL_WWDG_GetWindow
00235   * @param  WWDGx WWDG Instance
00236   * @retval 7 bit Watchdog Window value
00237   */
00238 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
00239 {
00240   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00241 }
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00248   * @{
00249   */
00250 /**
00251   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00252   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00253   *         It must be cleared by software by writing 0.
00254   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00255   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00256   * @param  WWDGx WWDG Instance
00257   * @retval State of bit (1 or 0).
00258   */
00259 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
00260 {
00261   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
00262 }
00263
00264 /**
00265   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00266   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00267   * @param  WWDGx WWDG Instance
00268   * @retval None
00269   */
00270 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00271 {
00272   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00280   * @{
00281   */
00282 /**
00283   * @brief  Enable the Early Wakeup Interrupt.
00284   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00285   *         This interrupt is only cleared by hardware after a reset
00286   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00287   * @param  WWDGx WWDG Instance
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00291 {
00292   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00293 }
00294
00295 /**
00296   * @brief  Check if Early Wakeup Interrupt is enabled
00297   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00298   * @param  WWDGx WWDG Instance
00299   * @retval State of bit (1 or 0).
00300   */
00301 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
00302 {
00303   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
00304 }
00305
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 #endif /* WWDG */
00319
00320 /**
00321   * @}
00322   */
00323
00324 #ifdef __cplusplus
00325 }
00326 #endif
00327
00328 #endif /* STM32G4xx_LL_WWDG_H */
Generated on Wed Dec 6 2023 15:11:29 for STM32G431xx HAL User Manual by doxygen 1.7.6.1


STM32G431xx HAL User Manual: userManualMainpage.txt File Reference

  • File List
  • Globals
userManualMainpage.txt File Reference
Generated on Wed Dec 6 2023 15:11:31 for STM32G431xx HAL User Manual by doxygen 1.7.6.1